4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Daniel Vetter <daniel@ffwll.ch>
26 * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c
29 #include <drm/i915_drm.h>
32 #include "intel_drv.h"
34 /* Limits for overlay size. According to intel doc, the real limits are:
35 * Y width: 4095, UV width (planar): 2047, Y height: 2047,
36 * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use
37 * the mininum of both. */
38 #define IMAGE_MAX_WIDTH 2048
39 #define IMAGE_MAX_HEIGHT 2046 /* 2 * 1023 */
40 /* on 830 and 845 these large limits result in the card hanging */
41 #define IMAGE_MAX_WIDTH_LEGACY 1024
42 #define IMAGE_MAX_HEIGHT_LEGACY 1088
44 /* overlay register definitions */
46 #define OCMD_TILED_SURFACE (0x1<<19)
47 #define OCMD_MIRROR_MASK (0x3<<17)
48 #define OCMD_MIRROR_MODE (0x3<<17)
49 #define OCMD_MIRROR_HORIZONTAL (0x1<<17)
50 #define OCMD_MIRROR_VERTICAL (0x2<<17)
51 #define OCMD_MIRROR_BOTH (0x3<<17)
52 #define OCMD_BYTEORDER_MASK (0x3<<14) /* zero for YUYV or FOURCC YUY2 */
53 #define OCMD_UV_SWAP (0x1<<14) /* YVYU */
54 #define OCMD_Y_SWAP (0x2<<14) /* UYVY or FOURCC UYVY */
55 #define OCMD_Y_AND_UV_SWAP (0x3<<14) /* VYUY */
56 #define OCMD_SOURCE_FORMAT_MASK (0xf<<10)
57 #define OCMD_RGB_888 (0x1<<10) /* not in i965 Intel docs */
58 #define OCMD_RGB_555 (0x2<<10) /* not in i965 Intel docs */
59 #define OCMD_RGB_565 (0x3<<10) /* not in i965 Intel docs */
60 #define OCMD_YUV_422_PACKED (0x8<<10)
61 #define OCMD_YUV_411_PACKED (0x9<<10) /* not in i965 Intel docs */
62 #define OCMD_YUV_420_PLANAR (0xc<<10)
63 #define OCMD_YUV_422_PLANAR (0xd<<10)
64 #define OCMD_YUV_410_PLANAR (0xe<<10) /* also 411 */
65 #define OCMD_TVSYNCFLIP_PARITY (0x1<<9)
66 #define OCMD_TVSYNCFLIP_ENABLE (0x1<<7)
67 #define OCMD_BUF_TYPE_MASK (0x1<<5)
68 #define OCMD_BUF_TYPE_FRAME (0x0<<5)
69 #define OCMD_BUF_TYPE_FIELD (0x1<<5)
70 #define OCMD_TEST_MODE (0x1<<4)
71 #define OCMD_BUFFER_SELECT (0x3<<2)
72 #define OCMD_BUFFER0 (0x0<<2)
73 #define OCMD_BUFFER1 (0x1<<2)
74 #define OCMD_FIELD_SELECT (0x1<<2)
75 #define OCMD_FIELD0 (0x0<<1)
76 #define OCMD_FIELD1 (0x1<<1)
77 #define OCMD_ENABLE (0x1<<0)
79 /* OCONFIG register */
80 #define OCONF_PIPE_MASK (0x1<<18)
81 #define OCONF_PIPE_A (0x0<<18)
82 #define OCONF_PIPE_B (0x1<<18)
83 #define OCONF_GAMMA2_ENABLE (0x1<<16)
84 #define OCONF_CSC_MODE_BT601 (0x0<<5)
85 #define OCONF_CSC_MODE_BT709 (0x1<<5)
86 #define OCONF_CSC_BYPASS (0x1<<4)
87 #define OCONF_CC_OUT_8BIT (0x1<<3)
88 #define OCONF_TEST_MODE (0x1<<2)
89 #define OCONF_THREE_LINE_BUFFER (0x1<<0)
90 #define OCONF_TWO_LINE_BUFFER (0x0<<0)
92 /* DCLRKM (dst-key) register */
93 #define DST_KEY_ENABLE (0x1<<31)
94 #define CLK_RGB24_MASK 0x0
95 #define CLK_RGB16_MASK 0x070307
96 #define CLK_RGB15_MASK 0x070707
97 #define CLK_RGB8I_MASK 0xffffff
99 #define RGB16_TO_COLORKEY(c) \
100 (((c & 0xF800) << 8) | ((c & 0x07E0) << 5) | ((c & 0x001F) << 3))
101 #define RGB15_TO_COLORKEY(c) \
102 (((c & 0x7c00) << 9) | ((c & 0x03E0) << 6) | ((c & 0x001F) << 3))
104 /* overlay flip addr flag */
105 #define OFC_UPDATE 0x1
107 /* polyphase filter coefficients */
108 #define N_HORIZ_Y_TAPS 5
109 #define N_VERT_Y_TAPS 3
110 #define N_HORIZ_UV_TAPS 3
111 #define N_VERT_UV_TAPS 3
115 /* memory bufferd overlay registers */
116 struct overlay_registers
{
144 u32 RESERVED1
; /* 0x6C */
157 u32 FASTHSCALE
; /* 0xA0 */
158 u32 UVSCALEV
; /* 0xA4 */
159 u32 RESERVEDC
[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */
160 u16 Y_VCOEFS
[N_VERT_Y_TAPS
* N_PHASES
]; /* 0x200 */
161 u16 RESERVEDD
[0x100 / 2 - N_VERT_Y_TAPS
* N_PHASES
];
162 u16 Y_HCOEFS
[N_HORIZ_Y_TAPS
* N_PHASES
]; /* 0x300 */
163 u16 RESERVEDE
[0x200 / 2 - N_HORIZ_Y_TAPS
* N_PHASES
];
164 u16 UV_VCOEFS
[N_VERT_UV_TAPS
* N_PHASES
]; /* 0x500 */
165 u16 RESERVEDF
[0x100 / 2 - N_VERT_UV_TAPS
* N_PHASES
];
166 u16 UV_HCOEFS
[N_HORIZ_UV_TAPS
* N_PHASES
]; /* 0x600 */
167 u16 RESERVEDG
[0x100 / 2 - N_HORIZ_UV_TAPS
* N_PHASES
];
170 struct intel_overlay
{
171 struct drm_device
*dev
;
172 struct intel_crtc
*crtc
;
173 struct drm_i915_gem_object
*vid_bo
;
174 struct drm_i915_gem_object
*old_vid_bo
;
177 u32 pfit_vscale_ratio
; /* shifted-point number, (1<<12) == 1.0 */
179 u32 color_key_enabled
:1;
180 u32 brightness
, contrast
, saturation
;
181 u32 old_xscale
, old_yscale
;
182 /* register access */
184 struct drm_i915_gem_object
*reg_bo
;
186 struct drm_i915_gem_request
*last_flip_req
;
187 void (*flip_tail
)(struct intel_overlay
*);
190 static struct overlay_registers __iomem
*
191 intel_overlay_map_regs(struct intel_overlay
*overlay
)
193 struct drm_i915_private
*dev_priv
= to_i915(overlay
->dev
);
194 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
195 struct overlay_registers __iomem
*regs
;
197 if (OVERLAY_NEEDS_PHYSICAL(overlay
->dev
))
198 regs
= (struct overlay_registers __iomem
*)overlay
->reg_bo
->phys_handle
->vaddr
;
200 regs
= io_mapping_map_wc(ggtt
->mappable
,
201 i915_gem_obj_ggtt_offset(overlay
->reg_bo
));
206 static void intel_overlay_unmap_regs(struct intel_overlay
*overlay
,
207 struct overlay_registers __iomem
*regs
)
209 if (!OVERLAY_NEEDS_PHYSICAL(overlay
->dev
))
210 io_mapping_unmap(regs
);
213 static int intel_overlay_do_wait_request(struct intel_overlay
*overlay
,
214 struct drm_i915_gem_request
*req
,
215 void (*tail
)(struct intel_overlay
*))
219 WARN_ON(overlay
->last_flip_req
);
220 i915_gem_request_assign(&overlay
->last_flip_req
, req
);
221 i915_add_request(req
);
223 overlay
->flip_tail
= tail
;
224 ret
= i915_wait_request(overlay
->last_flip_req
);
228 i915_gem_request_assign(&overlay
->last_flip_req
, NULL
);
232 /* overlay needs to be disable in OCMD reg */
233 static int intel_overlay_on(struct intel_overlay
*overlay
)
235 struct drm_device
*dev
= overlay
->dev
;
236 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
237 struct intel_engine_cs
*engine
= &dev_priv
->engine
[RCS
];
238 struct drm_i915_gem_request
*req
;
241 WARN_ON(overlay
->active
);
242 WARN_ON(IS_I830(dev
) && !(dev_priv
->quirks
& QUIRK_PIPEA_FORCE
));
244 req
= i915_gem_request_alloc(engine
, NULL
);
248 ret
= intel_ring_begin(req
, 4);
250 i915_gem_request_cancel(req
);
254 overlay
->active
= true;
256 intel_ring_emit(engine
, MI_OVERLAY_FLIP
| MI_OVERLAY_ON
);
257 intel_ring_emit(engine
, overlay
->flip_addr
| OFC_UPDATE
);
258 intel_ring_emit(engine
, MI_WAIT_FOR_EVENT
| MI_WAIT_FOR_OVERLAY_FLIP
);
259 intel_ring_emit(engine
, MI_NOOP
);
260 intel_ring_advance(engine
);
262 return intel_overlay_do_wait_request(overlay
, req
, NULL
);
265 /* overlay needs to be enabled in OCMD reg */
266 static int intel_overlay_continue(struct intel_overlay
*overlay
,
267 bool load_polyphase_filter
)
269 struct drm_device
*dev
= overlay
->dev
;
270 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
271 struct intel_engine_cs
*engine
= &dev_priv
->engine
[RCS
];
272 struct drm_i915_gem_request
*req
;
273 u32 flip_addr
= overlay
->flip_addr
;
277 WARN_ON(!overlay
->active
);
279 if (load_polyphase_filter
)
280 flip_addr
|= OFC_UPDATE
;
282 /* check for underruns */
283 tmp
= I915_READ(DOVSTA
);
285 DRM_DEBUG("overlay underrun, DOVSTA: %x\n", tmp
);
287 req
= i915_gem_request_alloc(engine
, NULL
);
291 ret
= intel_ring_begin(req
, 2);
293 i915_gem_request_cancel(req
);
297 intel_ring_emit(engine
, MI_OVERLAY_FLIP
| MI_OVERLAY_CONTINUE
);
298 intel_ring_emit(engine
, flip_addr
);
299 intel_ring_advance(engine
);
301 WARN_ON(overlay
->last_flip_req
);
302 i915_gem_request_assign(&overlay
->last_flip_req
, req
);
303 i915_add_request(req
);
308 static void intel_overlay_release_old_vid_tail(struct intel_overlay
*overlay
)
310 struct drm_i915_gem_object
*obj
= overlay
->old_vid_bo
;
312 i915_gem_object_ggtt_unpin(obj
);
313 drm_gem_object_unreference(&obj
->base
);
315 overlay
->old_vid_bo
= NULL
;
318 static void intel_overlay_off_tail(struct intel_overlay
*overlay
)
320 struct drm_i915_gem_object
*obj
= overlay
->vid_bo
;
322 /* never have the overlay hw on without showing a frame */
326 i915_gem_object_ggtt_unpin(obj
);
327 drm_gem_object_unreference(&obj
->base
);
328 overlay
->vid_bo
= NULL
;
330 overlay
->crtc
->overlay
= NULL
;
331 overlay
->crtc
= NULL
;
332 overlay
->active
= false;
335 /* overlay needs to be disabled in OCMD reg */
336 static int intel_overlay_off(struct intel_overlay
*overlay
)
338 struct drm_device
*dev
= overlay
->dev
;
339 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
340 struct intel_engine_cs
*engine
= &dev_priv
->engine
[RCS
];
341 struct drm_i915_gem_request
*req
;
342 u32 flip_addr
= overlay
->flip_addr
;
345 WARN_ON(!overlay
->active
);
347 /* According to intel docs the overlay hw may hang (when switching
348 * off) without loading the filter coeffs. It is however unclear whether
349 * this applies to the disabling of the overlay or to the switching off
350 * of the hw. Do it in both cases */
351 flip_addr
|= OFC_UPDATE
;
353 req
= i915_gem_request_alloc(engine
, NULL
);
357 ret
= intel_ring_begin(req
, 6);
359 i915_gem_request_cancel(req
);
363 /* wait for overlay to go idle */
364 intel_ring_emit(engine
, MI_OVERLAY_FLIP
| MI_OVERLAY_CONTINUE
);
365 intel_ring_emit(engine
, flip_addr
);
366 intel_ring_emit(engine
, MI_WAIT_FOR_EVENT
| MI_WAIT_FOR_OVERLAY_FLIP
);
367 /* turn overlay off */
369 /* Workaround: Don't disable the overlay fully, since otherwise
370 * it dies on the next OVERLAY_ON cmd. */
371 intel_ring_emit(engine
, MI_NOOP
);
372 intel_ring_emit(engine
, MI_NOOP
);
373 intel_ring_emit(engine
, MI_NOOP
);
375 intel_ring_emit(engine
, MI_OVERLAY_FLIP
| MI_OVERLAY_OFF
);
376 intel_ring_emit(engine
, flip_addr
);
377 intel_ring_emit(engine
,
378 MI_WAIT_FOR_EVENT
| MI_WAIT_FOR_OVERLAY_FLIP
);
380 intel_ring_advance(engine
);
382 return intel_overlay_do_wait_request(overlay
, req
, intel_overlay_off_tail
);
385 /* recover from an interruption due to a signal
386 * We have to be careful not to repeat work forever an make forward progess. */
387 static int intel_overlay_recover_from_interrupt(struct intel_overlay
*overlay
)
391 if (overlay
->last_flip_req
== NULL
)
394 ret
= i915_wait_request(overlay
->last_flip_req
);
398 if (overlay
->flip_tail
)
399 overlay
->flip_tail(overlay
);
401 i915_gem_request_assign(&overlay
->last_flip_req
, NULL
);
405 /* Wait for pending overlay flip and release old frame.
406 * Needs to be called before the overlay register are changed
407 * via intel_overlay_(un)map_regs
409 static int intel_overlay_release_old_vid(struct intel_overlay
*overlay
)
411 struct drm_device
*dev
= overlay
->dev
;
412 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
413 struct intel_engine_cs
*engine
= &dev_priv
->engine
[RCS
];
416 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
418 /* Only wait if there is actually an old frame to release to
419 * guarantee forward progress.
421 if (!overlay
->old_vid_bo
)
424 if (I915_READ(ISR
) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT
) {
425 /* synchronous slowpath */
426 struct drm_i915_gem_request
*req
;
428 req
= i915_gem_request_alloc(engine
, NULL
);
432 ret
= intel_ring_begin(req
, 2);
434 i915_gem_request_cancel(req
);
438 intel_ring_emit(engine
,
439 MI_WAIT_FOR_EVENT
| MI_WAIT_FOR_OVERLAY_FLIP
);
440 intel_ring_emit(engine
, MI_NOOP
);
441 intel_ring_advance(engine
);
443 ret
= intel_overlay_do_wait_request(overlay
, req
,
444 intel_overlay_release_old_vid_tail
);
449 intel_overlay_release_old_vid_tail(overlay
);
452 i915_gem_track_fb(overlay
->old_vid_bo
, NULL
,
453 INTEL_FRONTBUFFER_OVERLAY(overlay
->crtc
->pipe
));
457 void intel_overlay_reset(struct drm_i915_private
*dev_priv
)
459 struct intel_overlay
*overlay
= dev_priv
->overlay
;
464 intel_overlay_release_old_vid(overlay
);
466 overlay
->last_flip_req
= NULL
;
467 overlay
->old_xscale
= 0;
468 overlay
->old_yscale
= 0;
469 overlay
->crtc
= NULL
;
470 overlay
->active
= false;
473 struct put_image_params
{
490 static int packed_depth_bytes(u32 format
)
492 switch (format
& I915_OVERLAY_DEPTH_MASK
) {
493 case I915_OVERLAY_YUV422
:
495 case I915_OVERLAY_YUV411
:
496 /* return 6; not implemented */
502 static int packed_width_bytes(u32 format
, short width
)
504 switch (format
& I915_OVERLAY_DEPTH_MASK
) {
505 case I915_OVERLAY_YUV422
:
512 static int uv_hsubsampling(u32 format
)
514 switch (format
& I915_OVERLAY_DEPTH_MASK
) {
515 case I915_OVERLAY_YUV422
:
516 case I915_OVERLAY_YUV420
:
518 case I915_OVERLAY_YUV411
:
519 case I915_OVERLAY_YUV410
:
526 static int uv_vsubsampling(u32 format
)
528 switch (format
& I915_OVERLAY_DEPTH_MASK
) {
529 case I915_OVERLAY_YUV420
:
530 case I915_OVERLAY_YUV410
:
532 case I915_OVERLAY_YUV422
:
533 case I915_OVERLAY_YUV411
:
540 static u32
calc_swidthsw(struct drm_device
*dev
, u32 offset
, u32 width
)
542 u32 mask
, shift
, ret
;
550 ret
= ((offset
+ width
+ mask
) >> shift
) - (offset
>> shift
);
557 static const u16 y_static_hcoeffs
[N_HORIZ_Y_TAPS
* N_PHASES
] = {
558 0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0,
559 0x3000, 0xb500, 0x19d0, 0x1880, 0xb440,
560 0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0,
561 0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380,
562 0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320,
563 0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0,
564 0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260,
565 0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200,
566 0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0,
567 0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160,
568 0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120,
569 0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0,
570 0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0,
571 0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060,
572 0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040,
573 0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020,
574 0xb000, 0x3000, 0x0800, 0x3000, 0xb000
577 static const u16 uv_static_hcoeffs
[N_HORIZ_UV_TAPS
* N_PHASES
] = {
578 0x3000, 0x1800, 0x1800, 0xb000, 0x18d0, 0x2e60,
579 0xb000, 0x1990, 0x2ce0, 0xb020, 0x1a68, 0x2b40,
580 0xb040, 0x1b20, 0x29e0, 0xb060, 0x1bd8, 0x2880,
581 0xb080, 0x1c88, 0x3e60, 0xb0a0, 0x1d28, 0x3c00,
582 0xb0c0, 0x1db8, 0x39e0, 0xb0e0, 0x1e40, 0x37e0,
583 0xb100, 0x1eb8, 0x3620, 0xb100, 0x1f18, 0x34a0,
584 0xb100, 0x1f68, 0x3360, 0xb0e0, 0x1fa8, 0x3240,
585 0xb0c0, 0x1fe0, 0x3140, 0xb060, 0x1ff0, 0x30a0,
586 0x3000, 0x0800, 0x3000
589 static void update_polyphase_filter(struct overlay_registers __iomem
*regs
)
591 memcpy_toio(regs
->Y_HCOEFS
, y_static_hcoeffs
, sizeof(y_static_hcoeffs
));
592 memcpy_toio(regs
->UV_HCOEFS
, uv_static_hcoeffs
,
593 sizeof(uv_static_hcoeffs
));
596 static bool update_scaling_factors(struct intel_overlay
*overlay
,
597 struct overlay_registers __iomem
*regs
,
598 struct put_image_params
*params
)
600 /* fixed point with a 12 bit shift */
601 u32 xscale
, yscale
, xscale_UV
, yscale_UV
;
603 #define FRACT_MASK 0xfff
604 bool scale_changed
= false;
605 int uv_hscale
= uv_hsubsampling(params
->format
);
606 int uv_vscale
= uv_vsubsampling(params
->format
);
608 if (params
->dst_w
> 1)
609 xscale
= ((params
->src_scan_w
- 1) << FP_SHIFT
)
612 xscale
= 1 << FP_SHIFT
;
614 if (params
->dst_h
> 1)
615 yscale
= ((params
->src_scan_h
- 1) << FP_SHIFT
)
618 yscale
= 1 << FP_SHIFT
;
620 /*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/
621 xscale_UV
= xscale
/uv_hscale
;
622 yscale_UV
= yscale
/uv_vscale
;
623 /* make the Y scale to UV scale ratio an exact multiply */
624 xscale
= xscale_UV
* uv_hscale
;
625 yscale
= yscale_UV
* uv_vscale
;
631 if (xscale
!= overlay
->old_xscale
|| yscale
!= overlay
->old_yscale
)
632 scale_changed
= true;
633 overlay
->old_xscale
= xscale
;
634 overlay
->old_yscale
= yscale
;
636 iowrite32(((yscale
& FRACT_MASK
) << 20) |
637 ((xscale
>> FP_SHIFT
) << 16) |
638 ((xscale
& FRACT_MASK
) << 3),
641 iowrite32(((yscale_UV
& FRACT_MASK
) << 20) |
642 ((xscale_UV
>> FP_SHIFT
) << 16) |
643 ((xscale_UV
& FRACT_MASK
) << 3),
646 iowrite32((((yscale
>> FP_SHIFT
) << 16) |
647 ((yscale_UV
>> FP_SHIFT
) << 0)),
651 update_polyphase_filter(regs
);
653 return scale_changed
;
656 static void update_colorkey(struct intel_overlay
*overlay
,
657 struct overlay_registers __iomem
*regs
)
659 u32 key
= overlay
->color_key
;
663 if (overlay
->color_key_enabled
)
664 flags
|= DST_KEY_ENABLE
;
666 switch (overlay
->crtc
->base
.primary
->fb
->bits_per_pixel
) {
669 flags
|= CLK_RGB8I_MASK
;
673 if (overlay
->crtc
->base
.primary
->fb
->depth
== 15) {
674 key
= RGB15_TO_COLORKEY(key
);
675 flags
|= CLK_RGB15_MASK
;
677 key
= RGB16_TO_COLORKEY(key
);
678 flags
|= CLK_RGB16_MASK
;
684 flags
|= CLK_RGB24_MASK
;
688 iowrite32(key
, ®s
->DCLRKV
);
689 iowrite32(flags
, ®s
->DCLRKM
);
692 static u32
overlay_cmd_reg(struct put_image_params
*params
)
694 u32 cmd
= OCMD_ENABLE
| OCMD_BUF_TYPE_FRAME
| OCMD_BUFFER0
;
696 if (params
->format
& I915_OVERLAY_YUV_PLANAR
) {
697 switch (params
->format
& I915_OVERLAY_DEPTH_MASK
) {
698 case I915_OVERLAY_YUV422
:
699 cmd
|= OCMD_YUV_422_PLANAR
;
701 case I915_OVERLAY_YUV420
:
702 cmd
|= OCMD_YUV_420_PLANAR
;
704 case I915_OVERLAY_YUV411
:
705 case I915_OVERLAY_YUV410
:
706 cmd
|= OCMD_YUV_410_PLANAR
;
709 } else { /* YUV packed */
710 switch (params
->format
& I915_OVERLAY_DEPTH_MASK
) {
711 case I915_OVERLAY_YUV422
:
712 cmd
|= OCMD_YUV_422_PACKED
;
714 case I915_OVERLAY_YUV411
:
715 cmd
|= OCMD_YUV_411_PACKED
;
719 switch (params
->format
& I915_OVERLAY_SWAP_MASK
) {
720 case I915_OVERLAY_NO_SWAP
:
722 case I915_OVERLAY_UV_SWAP
:
725 case I915_OVERLAY_Y_SWAP
:
728 case I915_OVERLAY_Y_AND_UV_SWAP
:
729 cmd
|= OCMD_Y_AND_UV_SWAP
;
737 static int intel_overlay_do_put_image(struct intel_overlay
*overlay
,
738 struct drm_i915_gem_object
*new_bo
,
739 struct put_image_params
*params
)
742 struct overlay_registers __iomem
*regs
;
743 bool scale_changed
= false;
744 struct drm_device
*dev
= overlay
->dev
;
745 u32 swidth
, swidthsw
, sheight
, ostride
;
746 enum pipe pipe
= overlay
->crtc
->pipe
;
748 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
749 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
751 ret
= intel_overlay_release_old_vid(overlay
);
755 ret
= i915_gem_object_pin_to_display_plane(new_bo
, 0,
756 &i915_ggtt_view_normal
);
760 ret
= i915_gem_object_put_fence(new_bo
);
764 if (!overlay
->active
) {
766 regs
= intel_overlay_map_regs(overlay
);
771 oconfig
= OCONF_CC_OUT_8BIT
;
772 if (IS_GEN4(overlay
->dev
))
773 oconfig
|= OCONF_CSC_MODE_BT709
;
774 oconfig
|= pipe
== 0 ?
775 OCONF_PIPE_A
: OCONF_PIPE_B
;
776 iowrite32(oconfig
, ®s
->OCONFIG
);
777 intel_overlay_unmap_regs(overlay
, regs
);
779 ret
= intel_overlay_on(overlay
);
784 regs
= intel_overlay_map_regs(overlay
);
790 iowrite32((params
->dst_y
<< 16) | params
->dst_x
, ®s
->DWINPOS
);
791 iowrite32((params
->dst_h
<< 16) | params
->dst_w
, ®s
->DWINSZ
);
793 if (params
->format
& I915_OVERLAY_YUV_PACKED
)
794 tmp_width
= packed_width_bytes(params
->format
, params
->src_w
);
796 tmp_width
= params
->src_w
;
798 swidth
= params
->src_w
;
799 swidthsw
= calc_swidthsw(overlay
->dev
, params
->offset_Y
, tmp_width
);
800 sheight
= params
->src_h
;
801 iowrite32(i915_gem_obj_ggtt_offset(new_bo
) + params
->offset_Y
, ®s
->OBUF_0Y
);
802 ostride
= params
->stride_Y
;
804 if (params
->format
& I915_OVERLAY_YUV_PLANAR
) {
805 int uv_hscale
= uv_hsubsampling(params
->format
);
806 int uv_vscale
= uv_vsubsampling(params
->format
);
808 swidth
|= (params
->src_w
/uv_hscale
) << 16;
809 tmp_U
= calc_swidthsw(overlay
->dev
, params
->offset_U
,
810 params
->src_w
/uv_hscale
);
811 tmp_V
= calc_swidthsw(overlay
->dev
, params
->offset_V
,
812 params
->src_w
/uv_hscale
);
813 swidthsw
|= max_t(u32
, tmp_U
, tmp_V
) << 16;
814 sheight
|= (params
->src_h
/uv_vscale
) << 16;
815 iowrite32(i915_gem_obj_ggtt_offset(new_bo
) + params
->offset_U
, ®s
->OBUF_0U
);
816 iowrite32(i915_gem_obj_ggtt_offset(new_bo
) + params
->offset_V
, ®s
->OBUF_0V
);
817 ostride
|= params
->stride_UV
<< 16;
820 iowrite32(swidth
, ®s
->SWIDTH
);
821 iowrite32(swidthsw
, ®s
->SWIDTHSW
);
822 iowrite32(sheight
, ®s
->SHEIGHT
);
823 iowrite32(ostride
, ®s
->OSTRIDE
);
825 scale_changed
= update_scaling_factors(overlay
, regs
, params
);
827 update_colorkey(overlay
, regs
);
829 iowrite32(overlay_cmd_reg(params
), ®s
->OCMD
);
831 intel_overlay_unmap_regs(overlay
, regs
);
833 ret
= intel_overlay_continue(overlay
, scale_changed
);
837 i915_gem_track_fb(overlay
->vid_bo
, new_bo
,
838 INTEL_FRONTBUFFER_OVERLAY(pipe
));
840 overlay
->old_vid_bo
= overlay
->vid_bo
;
841 overlay
->vid_bo
= new_bo
;
843 intel_frontbuffer_flip(dev
,
844 INTEL_FRONTBUFFER_OVERLAY(pipe
));
849 i915_gem_object_ggtt_unpin(new_bo
);
853 int intel_overlay_switch_off(struct intel_overlay
*overlay
)
855 struct overlay_registers __iomem
*regs
;
856 struct drm_device
*dev
= overlay
->dev
;
859 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
860 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
862 ret
= intel_overlay_recover_from_interrupt(overlay
);
866 if (!overlay
->active
)
869 ret
= intel_overlay_release_old_vid(overlay
);
873 regs
= intel_overlay_map_regs(overlay
);
874 iowrite32(0, ®s
->OCMD
);
875 intel_overlay_unmap_regs(overlay
, regs
);
877 ret
= intel_overlay_off(overlay
);
881 intel_overlay_off_tail(overlay
);
885 static int check_overlay_possible_on_crtc(struct intel_overlay
*overlay
,
886 struct intel_crtc
*crtc
)
891 /* can't use the overlay with double wide pipe */
892 if (crtc
->config
->double_wide
)
898 static void update_pfit_vscale_ratio(struct intel_overlay
*overlay
)
900 struct drm_device
*dev
= overlay
->dev
;
901 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
902 u32 pfit_control
= I915_READ(PFIT_CONTROL
);
905 /* XXX: This is not the same logic as in the xorg driver, but more in
906 * line with the intel documentation for the i965
908 if (INTEL_INFO(dev
)->gen
>= 4) {
909 /* on i965 use the PGM reg to read out the autoscaler values */
910 ratio
= I915_READ(PFIT_PGM_RATIOS
) >> PFIT_VERT_SCALE_SHIFT_965
;
912 if (pfit_control
& VERT_AUTO_SCALE
)
913 ratio
= I915_READ(PFIT_AUTO_RATIOS
);
915 ratio
= I915_READ(PFIT_PGM_RATIOS
);
916 ratio
>>= PFIT_VERT_SCALE_SHIFT
;
919 overlay
->pfit_vscale_ratio
= ratio
;
922 static int check_overlay_dst(struct intel_overlay
*overlay
,
923 struct drm_intel_overlay_put_image
*rec
)
925 struct drm_display_mode
*mode
= &overlay
->crtc
->base
.mode
;
927 if (rec
->dst_x
< mode
->hdisplay
&&
928 rec
->dst_x
+ rec
->dst_width
<= mode
->hdisplay
&&
929 rec
->dst_y
< mode
->vdisplay
&&
930 rec
->dst_y
+ rec
->dst_height
<= mode
->vdisplay
)
936 static int check_overlay_scaling(struct put_image_params
*rec
)
940 /* downscaling limit is 8.0 */
941 tmp
= ((rec
->src_scan_h
<< 16) / rec
->dst_h
) >> 16;
944 tmp
= ((rec
->src_scan_w
<< 16) / rec
->dst_w
) >> 16;
951 static int check_overlay_src(struct drm_device
*dev
,
952 struct drm_intel_overlay_put_image
*rec
,
953 struct drm_i915_gem_object
*new_bo
)
955 int uv_hscale
= uv_hsubsampling(rec
->flags
);
956 int uv_vscale
= uv_vsubsampling(rec
->flags
);
961 /* check src dimensions */
962 if (IS_845G(dev
) || IS_I830(dev
)) {
963 if (rec
->src_height
> IMAGE_MAX_HEIGHT_LEGACY
||
964 rec
->src_width
> IMAGE_MAX_WIDTH_LEGACY
)
967 if (rec
->src_height
> IMAGE_MAX_HEIGHT
||
968 rec
->src_width
> IMAGE_MAX_WIDTH
)
972 /* better safe than sorry, use 4 as the maximal subsampling ratio */
973 if (rec
->src_height
< N_VERT_Y_TAPS
*4 ||
974 rec
->src_width
< N_HORIZ_Y_TAPS
*4)
977 /* check alignment constraints */
978 switch (rec
->flags
& I915_OVERLAY_TYPE_MASK
) {
979 case I915_OVERLAY_RGB
:
980 /* not implemented */
983 case I915_OVERLAY_YUV_PACKED
:
987 depth
= packed_depth_bytes(rec
->flags
);
991 /* ignore UV planes */
995 /* check pixel alignment */
996 if (rec
->offset_Y
% depth
)
1000 case I915_OVERLAY_YUV_PLANAR
:
1001 if (uv_vscale
< 0 || uv_hscale
< 0)
1003 /* no offset restrictions for planar formats */
1010 if (rec
->src_width
% uv_hscale
)
1013 /* stride checking */
1014 if (IS_I830(dev
) || IS_845G(dev
))
1019 if (rec
->stride_Y
& stride_mask
|| rec
->stride_UV
& stride_mask
)
1021 if (IS_GEN4(dev
) && rec
->stride_Y
< 512)
1024 tmp
= (rec
->flags
& I915_OVERLAY_TYPE_MASK
) == I915_OVERLAY_YUV_PLANAR
?
1026 if (rec
->stride_Y
> tmp
|| rec
->stride_UV
> 2*1024)
1029 /* check buffer dimensions */
1030 switch (rec
->flags
& I915_OVERLAY_TYPE_MASK
) {
1031 case I915_OVERLAY_RGB
:
1032 case I915_OVERLAY_YUV_PACKED
:
1033 /* always 4 Y values per depth pixels */
1034 if (packed_width_bytes(rec
->flags
, rec
->src_width
) > rec
->stride_Y
)
1037 tmp
= rec
->stride_Y
*rec
->src_height
;
1038 if (rec
->offset_Y
+ tmp
> new_bo
->base
.size
)
1042 case I915_OVERLAY_YUV_PLANAR
:
1043 if (rec
->src_width
> rec
->stride_Y
)
1045 if (rec
->src_width
/uv_hscale
> rec
->stride_UV
)
1048 tmp
= rec
->stride_Y
* rec
->src_height
;
1049 if (rec
->offset_Y
+ tmp
> new_bo
->base
.size
)
1052 tmp
= rec
->stride_UV
* (rec
->src_height
/ uv_vscale
);
1053 if (rec
->offset_U
+ tmp
> new_bo
->base
.size
||
1054 rec
->offset_V
+ tmp
> new_bo
->base
.size
)
1063 * Return the pipe currently connected to the panel fitter,
1064 * or -1 if the panel fitter is not present or not in use
1066 static int intel_panel_fitter_pipe(struct drm_device
*dev
)
1068 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1071 /* i830 doesn't have a panel fitter */
1072 if (INTEL_INFO(dev
)->gen
<= 3 && (IS_I830(dev
) || !IS_MOBILE(dev
)))
1075 pfit_control
= I915_READ(PFIT_CONTROL
);
1077 /* See if the panel fitter is in use */
1078 if ((pfit_control
& PFIT_ENABLE
) == 0)
1081 /* 965 can place panel fitter on either pipe */
1083 return (pfit_control
>> 29) & 0x3;
1085 /* older chips can only use pipe 1 */
1089 int intel_overlay_put_image(struct drm_device
*dev
, void *data
,
1090 struct drm_file
*file_priv
)
1092 struct drm_intel_overlay_put_image
*put_image_rec
= data
;
1093 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1094 struct intel_overlay
*overlay
;
1095 struct drm_crtc
*drmmode_crtc
;
1096 struct intel_crtc
*crtc
;
1097 struct drm_i915_gem_object
*new_bo
;
1098 struct put_image_params
*params
;
1101 overlay
= dev_priv
->overlay
;
1103 DRM_DEBUG("userspace bug: no overlay\n");
1107 if (!(put_image_rec
->flags
& I915_OVERLAY_ENABLE
)) {
1108 drm_modeset_lock_all(dev
);
1109 mutex_lock(&dev
->struct_mutex
);
1111 ret
= intel_overlay_switch_off(overlay
);
1113 mutex_unlock(&dev
->struct_mutex
);
1114 drm_modeset_unlock_all(dev
);
1119 params
= kmalloc(sizeof(*params
), GFP_KERNEL
);
1123 drmmode_crtc
= drm_crtc_find(dev
, put_image_rec
->crtc_id
);
1124 if (!drmmode_crtc
) {
1128 crtc
= to_intel_crtc(drmmode_crtc
);
1130 new_bo
= to_intel_bo(drm_gem_object_lookup(dev
, file_priv
,
1131 put_image_rec
->bo_handle
));
1132 if (&new_bo
->base
== NULL
) {
1137 drm_modeset_lock_all(dev
);
1138 mutex_lock(&dev
->struct_mutex
);
1140 if (new_bo
->tiling_mode
) {
1141 DRM_DEBUG_KMS("buffer used for overlay image can not be tiled\n");
1146 ret
= intel_overlay_recover_from_interrupt(overlay
);
1150 if (overlay
->crtc
!= crtc
) {
1151 struct drm_display_mode
*mode
= &crtc
->base
.mode
;
1152 ret
= intel_overlay_switch_off(overlay
);
1156 ret
= check_overlay_possible_on_crtc(overlay
, crtc
);
1160 overlay
->crtc
= crtc
;
1161 crtc
->overlay
= overlay
;
1163 /* line too wide, i.e. one-line-mode */
1164 if (mode
->hdisplay
> 1024 &&
1165 intel_panel_fitter_pipe(dev
) == crtc
->pipe
) {
1166 overlay
->pfit_active
= true;
1167 update_pfit_vscale_ratio(overlay
);
1169 overlay
->pfit_active
= false;
1172 ret
= check_overlay_dst(overlay
, put_image_rec
);
1176 if (overlay
->pfit_active
) {
1177 params
->dst_y
= ((((u32
)put_image_rec
->dst_y
) << 12) /
1178 overlay
->pfit_vscale_ratio
);
1179 /* shifting right rounds downwards, so add 1 */
1180 params
->dst_h
= ((((u32
)put_image_rec
->dst_height
) << 12) /
1181 overlay
->pfit_vscale_ratio
) + 1;
1183 params
->dst_y
= put_image_rec
->dst_y
;
1184 params
->dst_h
= put_image_rec
->dst_height
;
1186 params
->dst_x
= put_image_rec
->dst_x
;
1187 params
->dst_w
= put_image_rec
->dst_width
;
1189 params
->src_w
= put_image_rec
->src_width
;
1190 params
->src_h
= put_image_rec
->src_height
;
1191 params
->src_scan_w
= put_image_rec
->src_scan_width
;
1192 params
->src_scan_h
= put_image_rec
->src_scan_height
;
1193 if (params
->src_scan_h
> params
->src_h
||
1194 params
->src_scan_w
> params
->src_w
) {
1199 ret
= check_overlay_src(dev
, put_image_rec
, new_bo
);
1202 params
->format
= put_image_rec
->flags
& ~I915_OVERLAY_FLAGS_MASK
;
1203 params
->stride_Y
= put_image_rec
->stride_Y
;
1204 params
->stride_UV
= put_image_rec
->stride_UV
;
1205 params
->offset_Y
= put_image_rec
->offset_Y
;
1206 params
->offset_U
= put_image_rec
->offset_U
;
1207 params
->offset_V
= put_image_rec
->offset_V
;
1209 /* Check scaling after src size to prevent a divide-by-zero. */
1210 ret
= check_overlay_scaling(params
);
1214 ret
= intel_overlay_do_put_image(overlay
, new_bo
, params
);
1218 mutex_unlock(&dev
->struct_mutex
);
1219 drm_modeset_unlock_all(dev
);
1226 mutex_unlock(&dev
->struct_mutex
);
1227 drm_modeset_unlock_all(dev
);
1228 drm_gem_object_unreference_unlocked(&new_bo
->base
);
1235 static void update_reg_attrs(struct intel_overlay
*overlay
,
1236 struct overlay_registers __iomem
*regs
)
1238 iowrite32((overlay
->contrast
<< 18) | (overlay
->brightness
& 0xff),
1240 iowrite32(overlay
->saturation
, ®s
->OCLRC1
);
1243 static bool check_gamma_bounds(u32 gamma1
, u32 gamma2
)
1247 if (gamma1
& 0xff000000 || gamma2
& 0xff000000)
1250 for (i
= 0; i
< 3; i
++) {
1251 if (((gamma1
>> i
*8) & 0xff) >= ((gamma2
>> i
*8) & 0xff))
1258 static bool check_gamma5_errata(u32 gamma5
)
1262 for (i
= 0; i
< 3; i
++) {
1263 if (((gamma5
>> i
*8) & 0xff) == 0x80)
1270 static int check_gamma(struct drm_intel_overlay_attrs
*attrs
)
1272 if (!check_gamma_bounds(0, attrs
->gamma0
) ||
1273 !check_gamma_bounds(attrs
->gamma0
, attrs
->gamma1
) ||
1274 !check_gamma_bounds(attrs
->gamma1
, attrs
->gamma2
) ||
1275 !check_gamma_bounds(attrs
->gamma2
, attrs
->gamma3
) ||
1276 !check_gamma_bounds(attrs
->gamma3
, attrs
->gamma4
) ||
1277 !check_gamma_bounds(attrs
->gamma4
, attrs
->gamma5
) ||
1278 !check_gamma_bounds(attrs
->gamma5
, 0x00ffffff))
1281 if (!check_gamma5_errata(attrs
->gamma5
))
1287 int intel_overlay_attrs(struct drm_device
*dev
, void *data
,
1288 struct drm_file
*file_priv
)
1290 struct drm_intel_overlay_attrs
*attrs
= data
;
1291 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1292 struct intel_overlay
*overlay
;
1293 struct overlay_registers __iomem
*regs
;
1296 overlay
= dev_priv
->overlay
;
1298 DRM_DEBUG("userspace bug: no overlay\n");
1302 drm_modeset_lock_all(dev
);
1303 mutex_lock(&dev
->struct_mutex
);
1306 if (!(attrs
->flags
& I915_OVERLAY_UPDATE_ATTRS
)) {
1307 attrs
->color_key
= overlay
->color_key
;
1308 attrs
->brightness
= overlay
->brightness
;
1309 attrs
->contrast
= overlay
->contrast
;
1310 attrs
->saturation
= overlay
->saturation
;
1312 if (!IS_GEN2(dev
)) {
1313 attrs
->gamma0
= I915_READ(OGAMC0
);
1314 attrs
->gamma1
= I915_READ(OGAMC1
);
1315 attrs
->gamma2
= I915_READ(OGAMC2
);
1316 attrs
->gamma3
= I915_READ(OGAMC3
);
1317 attrs
->gamma4
= I915_READ(OGAMC4
);
1318 attrs
->gamma5
= I915_READ(OGAMC5
);
1321 if (attrs
->brightness
< -128 || attrs
->brightness
> 127)
1323 if (attrs
->contrast
> 255)
1325 if (attrs
->saturation
> 1023)
1328 overlay
->color_key
= attrs
->color_key
;
1329 overlay
->brightness
= attrs
->brightness
;
1330 overlay
->contrast
= attrs
->contrast
;
1331 overlay
->saturation
= attrs
->saturation
;
1333 regs
= intel_overlay_map_regs(overlay
);
1339 update_reg_attrs(overlay
, regs
);
1341 intel_overlay_unmap_regs(overlay
, regs
);
1343 if (attrs
->flags
& I915_OVERLAY_UPDATE_GAMMA
) {
1347 if (overlay
->active
) {
1352 ret
= check_gamma(attrs
);
1356 I915_WRITE(OGAMC0
, attrs
->gamma0
);
1357 I915_WRITE(OGAMC1
, attrs
->gamma1
);
1358 I915_WRITE(OGAMC2
, attrs
->gamma2
);
1359 I915_WRITE(OGAMC3
, attrs
->gamma3
);
1360 I915_WRITE(OGAMC4
, attrs
->gamma4
);
1361 I915_WRITE(OGAMC5
, attrs
->gamma5
);
1364 overlay
->color_key_enabled
= (attrs
->flags
& I915_OVERLAY_DISABLE_DEST_COLORKEY
) == 0;
1368 mutex_unlock(&dev
->struct_mutex
);
1369 drm_modeset_unlock_all(dev
);
1374 void intel_setup_overlay(struct drm_device
*dev
)
1376 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1377 struct intel_overlay
*overlay
;
1378 struct drm_i915_gem_object
*reg_bo
;
1379 struct overlay_registers __iomem
*regs
;
1382 if (!HAS_OVERLAY(dev
))
1385 overlay
= kzalloc(sizeof(*overlay
), GFP_KERNEL
);
1389 mutex_lock(&dev
->struct_mutex
);
1390 if (WARN_ON(dev_priv
->overlay
))
1396 if (!OVERLAY_NEEDS_PHYSICAL(dev
))
1397 reg_bo
= i915_gem_object_create_stolen(dev
, PAGE_SIZE
);
1399 reg_bo
= i915_gem_alloc_object(dev
, PAGE_SIZE
);
1402 overlay
->reg_bo
= reg_bo
;
1404 if (OVERLAY_NEEDS_PHYSICAL(dev
)) {
1405 ret
= i915_gem_object_attach_phys(reg_bo
, PAGE_SIZE
);
1407 DRM_ERROR("failed to attach phys overlay regs\n");
1410 overlay
->flip_addr
= reg_bo
->phys_handle
->busaddr
;
1412 ret
= i915_gem_obj_ggtt_pin(reg_bo
, PAGE_SIZE
, PIN_MAPPABLE
);
1414 DRM_ERROR("failed to pin overlay register bo\n");
1417 overlay
->flip_addr
= i915_gem_obj_ggtt_offset(reg_bo
);
1419 ret
= i915_gem_object_set_to_gtt_domain(reg_bo
, true);
1421 DRM_ERROR("failed to move overlay register bo into the GTT\n");
1426 /* init all values */
1427 overlay
->color_key
= 0x0101fe;
1428 overlay
->color_key_enabled
= true;
1429 overlay
->brightness
= -19;
1430 overlay
->contrast
= 75;
1431 overlay
->saturation
= 146;
1433 regs
= intel_overlay_map_regs(overlay
);
1437 memset_io(regs
, 0, sizeof(struct overlay_registers
));
1438 update_polyphase_filter(regs
);
1439 update_reg_attrs(overlay
, regs
);
1441 intel_overlay_unmap_regs(overlay
, regs
);
1443 dev_priv
->overlay
= overlay
;
1444 mutex_unlock(&dev
->struct_mutex
);
1445 DRM_INFO("initialized overlay support\n");
1449 if (!OVERLAY_NEEDS_PHYSICAL(dev
))
1450 i915_gem_object_ggtt_unpin(reg_bo
);
1452 drm_gem_object_unreference(®_bo
->base
);
1454 mutex_unlock(&dev
->struct_mutex
);
1459 void intel_cleanup_overlay(struct drm_device
*dev
)
1461 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1463 if (!dev_priv
->overlay
)
1466 /* The bo's should be free'd by the generic code already.
1467 * Furthermore modesetting teardown happens beforehand so the
1468 * hardware should be off already */
1469 WARN_ON(dev_priv
->overlay
->active
);
1471 drm_gem_object_unreference_unlocked(&dev_priv
->overlay
->reg_bo
->base
);
1472 kfree(dev_priv
->overlay
);
1475 struct intel_overlay_error_state
{
1476 struct overlay_registers regs
;
1482 static struct overlay_registers __iomem
*
1483 intel_overlay_map_regs_atomic(struct intel_overlay
*overlay
)
1485 struct drm_i915_private
*dev_priv
= to_i915(overlay
->dev
);
1486 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
1487 struct overlay_registers __iomem
*regs
;
1489 if (OVERLAY_NEEDS_PHYSICAL(overlay
->dev
))
1490 /* Cast to make sparse happy, but it's wc memory anyway, so
1491 * equivalent to the wc io mapping on X86. */
1492 regs
= (struct overlay_registers __iomem
*)
1493 overlay
->reg_bo
->phys_handle
->vaddr
;
1495 regs
= io_mapping_map_atomic_wc(ggtt
->mappable
,
1496 i915_gem_obj_ggtt_offset(overlay
->reg_bo
));
1501 static void intel_overlay_unmap_regs_atomic(struct intel_overlay
*overlay
,
1502 struct overlay_registers __iomem
*regs
)
1504 if (!OVERLAY_NEEDS_PHYSICAL(overlay
->dev
))
1505 io_mapping_unmap_atomic(regs
);
1509 struct intel_overlay_error_state
*
1510 intel_overlay_capture_error_state(struct drm_device
*dev
)
1512 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1513 struct intel_overlay
*overlay
= dev_priv
->overlay
;
1514 struct intel_overlay_error_state
*error
;
1515 struct overlay_registers __iomem
*regs
;
1517 if (!overlay
|| !overlay
->active
)
1520 error
= kmalloc(sizeof(*error
), GFP_ATOMIC
);
1524 error
->dovsta
= I915_READ(DOVSTA
);
1525 error
->isr
= I915_READ(ISR
);
1526 if (OVERLAY_NEEDS_PHYSICAL(overlay
->dev
))
1527 error
->base
= (__force
long)overlay
->reg_bo
->phys_handle
->vaddr
;
1529 error
->base
= i915_gem_obj_ggtt_offset(overlay
->reg_bo
);
1531 regs
= intel_overlay_map_regs_atomic(overlay
);
1535 memcpy_fromio(&error
->regs
, regs
, sizeof(struct overlay_registers
));
1536 intel_overlay_unmap_regs_atomic(overlay
, regs
);
1546 intel_overlay_print_error_state(struct drm_i915_error_state_buf
*m
,
1547 struct intel_overlay_error_state
*error
)
1549 i915_error_printf(m
, "Overlay, status: 0x%08x, interrupt: 0x%08x\n",
1550 error
->dovsta
, error
->isr
);
1551 i915_error_printf(m
, " Register file at 0x%08lx:\n",
1554 #define P(x) i915_error_printf(m, " " #x ": 0x%08x\n", error->regs.x)