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[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_overlay.c
1 /*
2 * Copyright © 2009
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Daniel Vetter <daniel@ffwll.ch>
25 *
26 * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c
27 */
28 #include "drmP.h"
29 #include "drm.h"
30 #include "i915_drm.h"
31 #include "i915_drv.h"
32 #include "i915_reg.h"
33 #include "intel_drv.h"
34
35 /* Limits for overlay size. According to intel doc, the real limits are:
36 * Y width: 4095, UV width (planar): 2047, Y height: 2047,
37 * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use
38 * the mininum of both. */
39 #define IMAGE_MAX_WIDTH 2048
40 #define IMAGE_MAX_HEIGHT 2046 /* 2 * 1023 */
41 /* on 830 and 845 these large limits result in the card hanging */
42 #define IMAGE_MAX_WIDTH_LEGACY 1024
43 #define IMAGE_MAX_HEIGHT_LEGACY 1088
44
45 /* overlay register definitions */
46 /* OCMD register */
47 #define OCMD_TILED_SURFACE (0x1<<19)
48 #define OCMD_MIRROR_MASK (0x3<<17)
49 #define OCMD_MIRROR_MODE (0x3<<17)
50 #define OCMD_MIRROR_HORIZONTAL (0x1<<17)
51 #define OCMD_MIRROR_VERTICAL (0x2<<17)
52 #define OCMD_MIRROR_BOTH (0x3<<17)
53 #define OCMD_BYTEORDER_MASK (0x3<<14) /* zero for YUYV or FOURCC YUY2 */
54 #define OCMD_UV_SWAP (0x1<<14) /* YVYU */
55 #define OCMD_Y_SWAP (0x2<<14) /* UYVY or FOURCC UYVY */
56 #define OCMD_Y_AND_UV_SWAP (0x3<<14) /* VYUY */
57 #define OCMD_SOURCE_FORMAT_MASK (0xf<<10)
58 #define OCMD_RGB_888 (0x1<<10) /* not in i965 Intel docs */
59 #define OCMD_RGB_555 (0x2<<10) /* not in i965 Intel docs */
60 #define OCMD_RGB_565 (0x3<<10) /* not in i965 Intel docs */
61 #define OCMD_YUV_422_PACKED (0x8<<10)
62 #define OCMD_YUV_411_PACKED (0x9<<10) /* not in i965 Intel docs */
63 #define OCMD_YUV_420_PLANAR (0xc<<10)
64 #define OCMD_YUV_422_PLANAR (0xd<<10)
65 #define OCMD_YUV_410_PLANAR (0xe<<10) /* also 411 */
66 #define OCMD_TVSYNCFLIP_PARITY (0x1<<9)
67 #define OCMD_TVSYNCFLIP_ENABLE (0x1<<7)
68 #define OCMD_BUF_TYPE_MASK (0x1<<5)
69 #define OCMD_BUF_TYPE_FRAME (0x0<<5)
70 #define OCMD_BUF_TYPE_FIELD (0x1<<5)
71 #define OCMD_TEST_MODE (0x1<<4)
72 #define OCMD_BUFFER_SELECT (0x3<<2)
73 #define OCMD_BUFFER0 (0x0<<2)
74 #define OCMD_BUFFER1 (0x1<<2)
75 #define OCMD_FIELD_SELECT (0x1<<2)
76 #define OCMD_FIELD0 (0x0<<1)
77 #define OCMD_FIELD1 (0x1<<1)
78 #define OCMD_ENABLE (0x1<<0)
79
80 /* OCONFIG register */
81 #define OCONF_PIPE_MASK (0x1<<18)
82 #define OCONF_PIPE_A (0x0<<18)
83 #define OCONF_PIPE_B (0x1<<18)
84 #define OCONF_GAMMA2_ENABLE (0x1<<16)
85 #define OCONF_CSC_MODE_BT601 (0x0<<5)
86 #define OCONF_CSC_MODE_BT709 (0x1<<5)
87 #define OCONF_CSC_BYPASS (0x1<<4)
88 #define OCONF_CC_OUT_8BIT (0x1<<3)
89 #define OCONF_TEST_MODE (0x1<<2)
90 #define OCONF_THREE_LINE_BUFFER (0x1<<0)
91 #define OCONF_TWO_LINE_BUFFER (0x0<<0)
92
93 /* DCLRKM (dst-key) register */
94 #define DST_KEY_ENABLE (0x1<<31)
95 #define CLK_RGB24_MASK 0x0
96 #define CLK_RGB16_MASK 0x070307
97 #define CLK_RGB15_MASK 0x070707
98 #define CLK_RGB8I_MASK 0xffffff
99
100 #define RGB16_TO_COLORKEY(c) \
101 (((c & 0xF800) << 8) | ((c & 0x07E0) << 5) | ((c & 0x001F) << 3))
102 #define RGB15_TO_COLORKEY(c) \
103 (((c & 0x7c00) << 9) | ((c & 0x03E0) << 6) | ((c & 0x001F) << 3))
104
105 /* overlay flip addr flag */
106 #define OFC_UPDATE 0x1
107
108 /* polyphase filter coefficients */
109 #define N_HORIZ_Y_TAPS 5
110 #define N_VERT_Y_TAPS 3
111 #define N_HORIZ_UV_TAPS 3
112 #define N_VERT_UV_TAPS 3
113 #define N_PHASES 17
114 #define MAX_TAPS 5
115
116 /* memory bufferd overlay registers */
117 struct overlay_registers {
118 u32 OBUF_0Y;
119 u32 OBUF_1Y;
120 u32 OBUF_0U;
121 u32 OBUF_0V;
122 u32 OBUF_1U;
123 u32 OBUF_1V;
124 u32 OSTRIDE;
125 u32 YRGB_VPH;
126 u32 UV_VPH;
127 u32 HORZ_PH;
128 u32 INIT_PHS;
129 u32 DWINPOS;
130 u32 DWINSZ;
131 u32 SWIDTH;
132 u32 SWIDTHSW;
133 u32 SHEIGHT;
134 u32 YRGBSCALE;
135 u32 UVSCALE;
136 u32 OCLRC0;
137 u32 OCLRC1;
138 u32 DCLRKV;
139 u32 DCLRKM;
140 u32 SCLRKVH;
141 u32 SCLRKVL;
142 u32 SCLRKEN;
143 u32 OCONFIG;
144 u32 OCMD;
145 u32 RESERVED1; /* 0x6C */
146 u32 OSTART_0Y;
147 u32 OSTART_1Y;
148 u32 OSTART_0U;
149 u32 OSTART_0V;
150 u32 OSTART_1U;
151 u32 OSTART_1V;
152 u32 OTILEOFF_0Y;
153 u32 OTILEOFF_1Y;
154 u32 OTILEOFF_0U;
155 u32 OTILEOFF_0V;
156 u32 OTILEOFF_1U;
157 u32 OTILEOFF_1V;
158 u32 FASTHSCALE; /* 0xA0 */
159 u32 UVSCALEV; /* 0xA4 */
160 u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */
161 u16 Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */
162 u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES];
163 u16 Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */
164 u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES];
165 u16 UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */
166 u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES];
167 u16 UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */
168 u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES];
169 };
170
171 struct intel_overlay {
172 struct drm_device *dev;
173 struct intel_crtc *crtc;
174 struct drm_i915_gem_object *vid_bo;
175 struct drm_i915_gem_object *old_vid_bo;
176 int active;
177 int pfit_active;
178 u32 pfit_vscale_ratio; /* shifted-point number, (1<<12) == 1.0 */
179 u32 color_key;
180 u32 brightness, contrast, saturation;
181 u32 old_xscale, old_yscale;
182 /* register access */
183 u32 flip_addr;
184 struct drm_i915_gem_object *reg_bo;
185 /* flip handling */
186 uint32_t last_flip_req;
187 void (*flip_tail)(struct intel_overlay *);
188 };
189
190 static struct overlay_registers __iomem *
191 intel_overlay_map_regs(struct intel_overlay *overlay)
192 {
193 drm_i915_private_t *dev_priv = overlay->dev->dev_private;
194 struct overlay_registers __iomem *regs;
195
196 if (OVERLAY_NEEDS_PHYSICAL(overlay->dev))
197 regs = (struct overlay_registers __iomem *)overlay->reg_bo->phys_obj->handle->vaddr;
198 else
199 regs = io_mapping_map_wc(dev_priv->mm.gtt_mapping,
200 overlay->reg_bo->gtt_offset);
201
202 return regs;
203 }
204
205 static void intel_overlay_unmap_regs(struct intel_overlay *overlay,
206 struct overlay_registers __iomem *regs)
207 {
208 if (!OVERLAY_NEEDS_PHYSICAL(overlay->dev))
209 io_mapping_unmap(regs);
210 }
211
212 static int intel_overlay_do_wait_request(struct intel_overlay *overlay,
213 struct drm_i915_gem_request *request,
214 void (*tail)(struct intel_overlay *))
215 {
216 struct drm_device *dev = overlay->dev;
217 drm_i915_private_t *dev_priv = dev->dev_private;
218 int ret;
219
220 BUG_ON(overlay->last_flip_req);
221 ret = i915_add_request(LP_RING(dev_priv), NULL, request);
222 if (ret) {
223 kfree(request);
224 return ret;
225 }
226 overlay->last_flip_req = request->seqno;
227 overlay->flip_tail = tail;
228 ret = i915_wait_request(LP_RING(dev_priv), overlay->last_flip_req,
229 true);
230 if (ret)
231 return ret;
232
233 overlay->last_flip_req = 0;
234 return 0;
235 }
236
237 /* Workaround for i830 bug where pipe a must be enable to change control regs */
238 static int
239 i830_activate_pipe_a(struct drm_device *dev)
240 {
241 drm_i915_private_t *dev_priv = dev->dev_private;
242 struct intel_crtc *crtc;
243 struct drm_crtc_helper_funcs *crtc_funcs;
244 struct drm_display_mode vesa_640x480 = {
245 DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
246 752, 800, 0, 480, 489, 492, 525, 0,
247 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC)
248 }, *mode;
249
250 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[0]);
251 if (crtc->dpms_mode == DRM_MODE_DPMS_ON)
252 return 0;
253
254 /* most i8xx have pipe a forced on, so don't trust dpms mode */
255 if (I915_READ(_PIPEACONF) & PIPECONF_ENABLE)
256 return 0;
257
258 crtc_funcs = crtc->base.helper_private;
259 if (crtc_funcs->dpms == NULL)
260 return 0;
261
262 DRM_DEBUG_DRIVER("Enabling pipe A in order to enable overlay\n");
263
264 mode = drm_mode_duplicate(dev, &vesa_640x480);
265 drm_mode_set_crtcinfo(mode, 0);
266 if (!drm_crtc_helper_set_mode(&crtc->base, mode,
267 crtc->base.x, crtc->base.y,
268 crtc->base.fb))
269 return 0;
270
271 crtc_funcs->dpms(&crtc->base, DRM_MODE_DPMS_ON);
272 return 1;
273 }
274
275 static void
276 i830_deactivate_pipe_a(struct drm_device *dev)
277 {
278 drm_i915_private_t *dev_priv = dev->dev_private;
279 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[0];
280 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
281
282 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
283 }
284
285 /* overlay needs to be disable in OCMD reg */
286 static int intel_overlay_on(struct intel_overlay *overlay)
287 {
288 struct drm_device *dev = overlay->dev;
289 struct drm_i915_private *dev_priv = dev->dev_private;
290 struct drm_i915_gem_request *request;
291 int pipe_a_quirk = 0;
292 int ret;
293
294 BUG_ON(overlay->active);
295 overlay->active = 1;
296
297 if (IS_I830(dev)) {
298 pipe_a_quirk = i830_activate_pipe_a(dev);
299 if (pipe_a_quirk < 0)
300 return pipe_a_quirk;
301 }
302
303 request = kzalloc(sizeof(*request), GFP_KERNEL);
304 if (request == NULL) {
305 ret = -ENOMEM;
306 goto out;
307 }
308
309 ret = BEGIN_LP_RING(4);
310 if (ret) {
311 kfree(request);
312 goto out;
313 }
314
315 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_ON);
316 OUT_RING(overlay->flip_addr | OFC_UPDATE);
317 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
318 OUT_RING(MI_NOOP);
319 ADVANCE_LP_RING();
320
321 ret = intel_overlay_do_wait_request(overlay, request, NULL);
322 out:
323 if (pipe_a_quirk)
324 i830_deactivate_pipe_a(dev);
325
326 return ret;
327 }
328
329 /* overlay needs to be enabled in OCMD reg */
330 static int intel_overlay_continue(struct intel_overlay *overlay,
331 bool load_polyphase_filter)
332 {
333 struct drm_device *dev = overlay->dev;
334 drm_i915_private_t *dev_priv = dev->dev_private;
335 struct drm_i915_gem_request *request;
336 u32 flip_addr = overlay->flip_addr;
337 u32 tmp;
338 int ret;
339
340 BUG_ON(!overlay->active);
341
342 request = kzalloc(sizeof(*request), GFP_KERNEL);
343 if (request == NULL)
344 return -ENOMEM;
345
346 if (load_polyphase_filter)
347 flip_addr |= OFC_UPDATE;
348
349 /* check for underruns */
350 tmp = I915_READ(DOVSTA);
351 if (tmp & (1 << 17))
352 DRM_DEBUG("overlay underrun, DOVSTA: %x\n", tmp);
353
354 ret = BEGIN_LP_RING(2);
355 if (ret) {
356 kfree(request);
357 return ret;
358 }
359 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
360 OUT_RING(flip_addr);
361 ADVANCE_LP_RING();
362
363 ret = i915_add_request(LP_RING(dev_priv), NULL, request);
364 if (ret) {
365 kfree(request);
366 return ret;
367 }
368
369 overlay->last_flip_req = request->seqno;
370 return 0;
371 }
372
373 static void intel_overlay_release_old_vid_tail(struct intel_overlay *overlay)
374 {
375 struct drm_i915_gem_object *obj = overlay->old_vid_bo;
376
377 i915_gem_object_unpin(obj);
378 drm_gem_object_unreference(&obj->base);
379
380 overlay->old_vid_bo = NULL;
381 }
382
383 static void intel_overlay_off_tail(struct intel_overlay *overlay)
384 {
385 struct drm_i915_gem_object *obj = overlay->vid_bo;
386
387 /* never have the overlay hw on without showing a frame */
388 BUG_ON(!overlay->vid_bo);
389
390 i915_gem_object_unpin(obj);
391 drm_gem_object_unreference(&obj->base);
392 overlay->vid_bo = NULL;
393
394 overlay->crtc->overlay = NULL;
395 overlay->crtc = NULL;
396 overlay->active = 0;
397 }
398
399 /* overlay needs to be disabled in OCMD reg */
400 static int intel_overlay_off(struct intel_overlay *overlay)
401 {
402 struct drm_device *dev = overlay->dev;
403 struct drm_i915_private *dev_priv = dev->dev_private;
404 u32 flip_addr = overlay->flip_addr;
405 struct drm_i915_gem_request *request;
406 int ret;
407
408 BUG_ON(!overlay->active);
409
410 request = kzalloc(sizeof(*request), GFP_KERNEL);
411 if (request == NULL)
412 return -ENOMEM;
413
414 /* According to intel docs the overlay hw may hang (when switching
415 * off) without loading the filter coeffs. It is however unclear whether
416 * this applies to the disabling of the overlay or to the switching off
417 * of the hw. Do it in both cases */
418 flip_addr |= OFC_UPDATE;
419
420 ret = BEGIN_LP_RING(6);
421 if (ret) {
422 kfree(request);
423 return ret;
424 }
425 /* wait for overlay to go idle */
426 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
427 OUT_RING(flip_addr);
428 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
429 /* turn overlay off */
430 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_OFF);
431 OUT_RING(flip_addr);
432 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
433 ADVANCE_LP_RING();
434
435 return intel_overlay_do_wait_request(overlay, request,
436 intel_overlay_off_tail);
437 }
438
439 /* recover from an interruption due to a signal
440 * We have to be careful not to repeat work forever an make forward progess. */
441 static int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay)
442 {
443 struct drm_device *dev = overlay->dev;
444 drm_i915_private_t *dev_priv = dev->dev_private;
445 int ret;
446
447 if (overlay->last_flip_req == 0)
448 return 0;
449
450 ret = i915_wait_request(LP_RING(dev_priv), overlay->last_flip_req,
451 true);
452 if (ret)
453 return ret;
454
455 if (overlay->flip_tail)
456 overlay->flip_tail(overlay);
457
458 overlay->last_flip_req = 0;
459 return 0;
460 }
461
462 /* Wait for pending overlay flip and release old frame.
463 * Needs to be called before the overlay register are changed
464 * via intel_overlay_(un)map_regs
465 */
466 static int intel_overlay_release_old_vid(struct intel_overlay *overlay)
467 {
468 struct drm_device *dev = overlay->dev;
469 drm_i915_private_t *dev_priv = dev->dev_private;
470 int ret;
471
472 /* Only wait if there is actually an old frame to release to
473 * guarantee forward progress.
474 */
475 if (!overlay->old_vid_bo)
476 return 0;
477
478 if (I915_READ(ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT) {
479 struct drm_i915_gem_request *request;
480
481 /* synchronous slowpath */
482 request = kzalloc(sizeof(*request), GFP_KERNEL);
483 if (request == NULL)
484 return -ENOMEM;
485
486 ret = BEGIN_LP_RING(2);
487 if (ret) {
488 kfree(request);
489 return ret;
490 }
491
492 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
493 OUT_RING(MI_NOOP);
494 ADVANCE_LP_RING();
495
496 ret = intel_overlay_do_wait_request(overlay, request,
497 intel_overlay_release_old_vid_tail);
498 if (ret)
499 return ret;
500 }
501
502 intel_overlay_release_old_vid_tail(overlay);
503 return 0;
504 }
505
506 struct put_image_params {
507 int format;
508 short dst_x;
509 short dst_y;
510 short dst_w;
511 short dst_h;
512 short src_w;
513 short src_scan_h;
514 short src_scan_w;
515 short src_h;
516 short stride_Y;
517 short stride_UV;
518 int offset_Y;
519 int offset_U;
520 int offset_V;
521 };
522
523 static int packed_depth_bytes(u32 format)
524 {
525 switch (format & I915_OVERLAY_DEPTH_MASK) {
526 case I915_OVERLAY_YUV422:
527 return 4;
528 case I915_OVERLAY_YUV411:
529 /* return 6; not implemented */
530 default:
531 return -EINVAL;
532 }
533 }
534
535 static int packed_width_bytes(u32 format, short width)
536 {
537 switch (format & I915_OVERLAY_DEPTH_MASK) {
538 case I915_OVERLAY_YUV422:
539 return width << 1;
540 default:
541 return -EINVAL;
542 }
543 }
544
545 static int uv_hsubsampling(u32 format)
546 {
547 switch (format & I915_OVERLAY_DEPTH_MASK) {
548 case I915_OVERLAY_YUV422:
549 case I915_OVERLAY_YUV420:
550 return 2;
551 case I915_OVERLAY_YUV411:
552 case I915_OVERLAY_YUV410:
553 return 4;
554 default:
555 return -EINVAL;
556 }
557 }
558
559 static int uv_vsubsampling(u32 format)
560 {
561 switch (format & I915_OVERLAY_DEPTH_MASK) {
562 case I915_OVERLAY_YUV420:
563 case I915_OVERLAY_YUV410:
564 return 2;
565 case I915_OVERLAY_YUV422:
566 case I915_OVERLAY_YUV411:
567 return 1;
568 default:
569 return -EINVAL;
570 }
571 }
572
573 static u32 calc_swidthsw(struct drm_device *dev, u32 offset, u32 width)
574 {
575 u32 mask, shift, ret;
576 if (IS_GEN2(dev)) {
577 mask = 0x1f;
578 shift = 5;
579 } else {
580 mask = 0x3f;
581 shift = 6;
582 }
583 ret = ((offset + width + mask) >> shift) - (offset >> shift);
584 if (!IS_GEN2(dev))
585 ret <<= 1;
586 ret -= 1;
587 return ret << 2;
588 }
589
590 static const u16 y_static_hcoeffs[N_HORIZ_Y_TAPS * N_PHASES] = {
591 0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0,
592 0x3000, 0xb500, 0x19d0, 0x1880, 0xb440,
593 0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0,
594 0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380,
595 0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320,
596 0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0,
597 0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260,
598 0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200,
599 0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0,
600 0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160,
601 0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120,
602 0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0,
603 0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0,
604 0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060,
605 0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040,
606 0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020,
607 0xb000, 0x3000, 0x0800, 0x3000, 0xb000
608 };
609
610 static const u16 uv_static_hcoeffs[N_HORIZ_UV_TAPS * N_PHASES] = {
611 0x3000, 0x1800, 0x1800, 0xb000, 0x18d0, 0x2e60,
612 0xb000, 0x1990, 0x2ce0, 0xb020, 0x1a68, 0x2b40,
613 0xb040, 0x1b20, 0x29e0, 0xb060, 0x1bd8, 0x2880,
614 0xb080, 0x1c88, 0x3e60, 0xb0a0, 0x1d28, 0x3c00,
615 0xb0c0, 0x1db8, 0x39e0, 0xb0e0, 0x1e40, 0x37e0,
616 0xb100, 0x1eb8, 0x3620, 0xb100, 0x1f18, 0x34a0,
617 0xb100, 0x1f68, 0x3360, 0xb0e0, 0x1fa8, 0x3240,
618 0xb0c0, 0x1fe0, 0x3140, 0xb060, 0x1ff0, 0x30a0,
619 0x3000, 0x0800, 0x3000
620 };
621
622 static void update_polyphase_filter(struct overlay_registers __iomem *regs)
623 {
624 memcpy_toio(regs->Y_HCOEFS, y_static_hcoeffs, sizeof(y_static_hcoeffs));
625 memcpy_toio(regs->UV_HCOEFS, uv_static_hcoeffs,
626 sizeof(uv_static_hcoeffs));
627 }
628
629 static bool update_scaling_factors(struct intel_overlay *overlay,
630 struct overlay_registers __iomem *regs,
631 struct put_image_params *params)
632 {
633 /* fixed point with a 12 bit shift */
634 u32 xscale, yscale, xscale_UV, yscale_UV;
635 #define FP_SHIFT 12
636 #define FRACT_MASK 0xfff
637 bool scale_changed = false;
638 int uv_hscale = uv_hsubsampling(params->format);
639 int uv_vscale = uv_vsubsampling(params->format);
640
641 if (params->dst_w > 1)
642 xscale = ((params->src_scan_w - 1) << FP_SHIFT)
643 /(params->dst_w);
644 else
645 xscale = 1 << FP_SHIFT;
646
647 if (params->dst_h > 1)
648 yscale = ((params->src_scan_h - 1) << FP_SHIFT)
649 /(params->dst_h);
650 else
651 yscale = 1 << FP_SHIFT;
652
653 /*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/
654 xscale_UV = xscale/uv_hscale;
655 yscale_UV = yscale/uv_vscale;
656 /* make the Y scale to UV scale ratio an exact multiply */
657 xscale = xscale_UV * uv_hscale;
658 yscale = yscale_UV * uv_vscale;
659 /*} else {
660 xscale_UV = 0;
661 yscale_UV = 0;
662 }*/
663
664 if (xscale != overlay->old_xscale || yscale != overlay->old_yscale)
665 scale_changed = true;
666 overlay->old_xscale = xscale;
667 overlay->old_yscale = yscale;
668
669 iowrite32(((yscale & FRACT_MASK) << 20) |
670 ((xscale >> FP_SHIFT) << 16) |
671 ((xscale & FRACT_MASK) << 3),
672 &regs->YRGBSCALE);
673
674 iowrite32(((yscale_UV & FRACT_MASK) << 20) |
675 ((xscale_UV >> FP_SHIFT) << 16) |
676 ((xscale_UV & FRACT_MASK) << 3),
677 &regs->UVSCALE);
678
679 iowrite32((((yscale >> FP_SHIFT) << 16) |
680 ((yscale_UV >> FP_SHIFT) << 0)),
681 &regs->UVSCALEV);
682
683 if (scale_changed)
684 update_polyphase_filter(regs);
685
686 return scale_changed;
687 }
688
689 static void update_colorkey(struct intel_overlay *overlay,
690 struct overlay_registers __iomem *regs)
691 {
692 u32 key = overlay->color_key;
693
694 switch (overlay->crtc->base.fb->bits_per_pixel) {
695 case 8:
696 iowrite32(0, &regs->DCLRKV);
697 iowrite32(CLK_RGB8I_MASK | DST_KEY_ENABLE, &regs->DCLRKM);
698 break;
699
700 case 16:
701 if (overlay->crtc->base.fb->depth == 15) {
702 iowrite32(RGB15_TO_COLORKEY(key), &regs->DCLRKV);
703 iowrite32(CLK_RGB15_MASK | DST_KEY_ENABLE,
704 &regs->DCLRKM);
705 } else {
706 iowrite32(RGB16_TO_COLORKEY(key), &regs->DCLRKV);
707 iowrite32(CLK_RGB16_MASK | DST_KEY_ENABLE,
708 &regs->DCLRKM);
709 }
710 break;
711
712 case 24:
713 case 32:
714 iowrite32(key, &regs->DCLRKV);
715 iowrite32(CLK_RGB24_MASK | DST_KEY_ENABLE, &regs->DCLRKM);
716 break;
717 }
718 }
719
720 static u32 overlay_cmd_reg(struct put_image_params *params)
721 {
722 u32 cmd = OCMD_ENABLE | OCMD_BUF_TYPE_FRAME | OCMD_BUFFER0;
723
724 if (params->format & I915_OVERLAY_YUV_PLANAR) {
725 switch (params->format & I915_OVERLAY_DEPTH_MASK) {
726 case I915_OVERLAY_YUV422:
727 cmd |= OCMD_YUV_422_PLANAR;
728 break;
729 case I915_OVERLAY_YUV420:
730 cmd |= OCMD_YUV_420_PLANAR;
731 break;
732 case I915_OVERLAY_YUV411:
733 case I915_OVERLAY_YUV410:
734 cmd |= OCMD_YUV_410_PLANAR;
735 break;
736 }
737 } else { /* YUV packed */
738 switch (params->format & I915_OVERLAY_DEPTH_MASK) {
739 case I915_OVERLAY_YUV422:
740 cmd |= OCMD_YUV_422_PACKED;
741 break;
742 case I915_OVERLAY_YUV411:
743 cmd |= OCMD_YUV_411_PACKED;
744 break;
745 }
746
747 switch (params->format & I915_OVERLAY_SWAP_MASK) {
748 case I915_OVERLAY_NO_SWAP:
749 break;
750 case I915_OVERLAY_UV_SWAP:
751 cmd |= OCMD_UV_SWAP;
752 break;
753 case I915_OVERLAY_Y_SWAP:
754 cmd |= OCMD_Y_SWAP;
755 break;
756 case I915_OVERLAY_Y_AND_UV_SWAP:
757 cmd |= OCMD_Y_AND_UV_SWAP;
758 break;
759 }
760 }
761
762 return cmd;
763 }
764
765 static int intel_overlay_do_put_image(struct intel_overlay *overlay,
766 struct drm_i915_gem_object *new_bo,
767 struct put_image_params *params)
768 {
769 int ret, tmp_width;
770 struct overlay_registers __iomem *regs;
771 bool scale_changed = false;
772 struct drm_device *dev = overlay->dev;
773 u32 swidth, swidthsw, sheight, ostride;
774
775 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
776 BUG_ON(!mutex_is_locked(&dev->mode_config.mutex));
777 BUG_ON(!overlay);
778
779 ret = intel_overlay_release_old_vid(overlay);
780 if (ret != 0)
781 return ret;
782
783 ret = i915_gem_object_pin_to_display_plane(new_bo, 0, NULL);
784 if (ret != 0)
785 return ret;
786
787 ret = i915_gem_object_put_fence(new_bo);
788 if (ret)
789 goto out_unpin;
790
791 if (!overlay->active) {
792 u32 oconfig;
793 regs = intel_overlay_map_regs(overlay);
794 if (!regs) {
795 ret = -ENOMEM;
796 goto out_unpin;
797 }
798 oconfig = OCONF_CC_OUT_8BIT;
799 if (IS_GEN4(overlay->dev))
800 oconfig |= OCONF_CSC_MODE_BT709;
801 oconfig |= overlay->crtc->pipe == 0 ?
802 OCONF_PIPE_A : OCONF_PIPE_B;
803 iowrite32(oconfig, &regs->OCONFIG);
804 intel_overlay_unmap_regs(overlay, regs);
805
806 ret = intel_overlay_on(overlay);
807 if (ret != 0)
808 goto out_unpin;
809 }
810
811 regs = intel_overlay_map_regs(overlay);
812 if (!regs) {
813 ret = -ENOMEM;
814 goto out_unpin;
815 }
816
817 iowrite32((params->dst_y << 16) | params->dst_x, &regs->DWINPOS);
818 iowrite32((params->dst_h << 16) | params->dst_w, &regs->DWINSZ);
819
820 if (params->format & I915_OVERLAY_YUV_PACKED)
821 tmp_width = packed_width_bytes(params->format, params->src_w);
822 else
823 tmp_width = params->src_w;
824
825 swidth = params->src_w;
826 swidthsw = calc_swidthsw(overlay->dev, params->offset_Y, tmp_width);
827 sheight = params->src_h;
828 iowrite32(new_bo->gtt_offset + params->offset_Y, &regs->OBUF_0Y);
829 ostride = params->stride_Y;
830
831 if (params->format & I915_OVERLAY_YUV_PLANAR) {
832 int uv_hscale = uv_hsubsampling(params->format);
833 int uv_vscale = uv_vsubsampling(params->format);
834 u32 tmp_U, tmp_V;
835 swidth |= (params->src_w/uv_hscale) << 16;
836 tmp_U = calc_swidthsw(overlay->dev, params->offset_U,
837 params->src_w/uv_hscale);
838 tmp_V = calc_swidthsw(overlay->dev, params->offset_V,
839 params->src_w/uv_hscale);
840 swidthsw |= max_t(u32, tmp_U, tmp_V) << 16;
841 sheight |= (params->src_h/uv_vscale) << 16;
842 iowrite32(new_bo->gtt_offset + params->offset_U, &regs->OBUF_0U);
843 iowrite32(new_bo->gtt_offset + params->offset_V, &regs->OBUF_0V);
844 ostride |= params->stride_UV << 16;
845 }
846
847 iowrite32(swidth, &regs->SWIDTH);
848 iowrite32(swidthsw, &regs->SWIDTHSW);
849 iowrite32(sheight, &regs->SHEIGHT);
850 iowrite32(ostride, &regs->OSTRIDE);
851
852 scale_changed = update_scaling_factors(overlay, regs, params);
853
854 update_colorkey(overlay, regs);
855
856 iowrite32(overlay_cmd_reg(params), &regs->OCMD);
857
858 intel_overlay_unmap_regs(overlay, regs);
859
860 ret = intel_overlay_continue(overlay, scale_changed);
861 if (ret)
862 goto out_unpin;
863
864 overlay->old_vid_bo = overlay->vid_bo;
865 overlay->vid_bo = new_bo;
866
867 return 0;
868
869 out_unpin:
870 i915_gem_object_unpin(new_bo);
871 return ret;
872 }
873
874 int intel_overlay_switch_off(struct intel_overlay *overlay)
875 {
876 struct overlay_registers __iomem *regs;
877 struct drm_device *dev = overlay->dev;
878 int ret;
879
880 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
881 BUG_ON(!mutex_is_locked(&dev->mode_config.mutex));
882
883 ret = intel_overlay_recover_from_interrupt(overlay);
884 if (ret != 0)
885 return ret;
886
887 if (!overlay->active)
888 return 0;
889
890 ret = intel_overlay_release_old_vid(overlay);
891 if (ret != 0)
892 return ret;
893
894 regs = intel_overlay_map_regs(overlay);
895 iowrite32(0, &regs->OCMD);
896 intel_overlay_unmap_regs(overlay, regs);
897
898 ret = intel_overlay_off(overlay);
899 if (ret != 0)
900 return ret;
901
902 intel_overlay_off_tail(overlay);
903 return 0;
904 }
905
906 static int check_overlay_possible_on_crtc(struct intel_overlay *overlay,
907 struct intel_crtc *crtc)
908 {
909 drm_i915_private_t *dev_priv = overlay->dev->dev_private;
910
911 if (!crtc->active)
912 return -EINVAL;
913
914 /* can't use the overlay with double wide pipe */
915 if (INTEL_INFO(overlay->dev)->gen < 4 &&
916 (I915_READ(PIPECONF(crtc->pipe)) & (PIPECONF_DOUBLE_WIDE | PIPECONF_ENABLE)) != PIPECONF_ENABLE)
917 return -EINVAL;
918
919 return 0;
920 }
921
922 static void update_pfit_vscale_ratio(struct intel_overlay *overlay)
923 {
924 struct drm_device *dev = overlay->dev;
925 drm_i915_private_t *dev_priv = dev->dev_private;
926 u32 pfit_control = I915_READ(PFIT_CONTROL);
927 u32 ratio;
928
929 /* XXX: This is not the same logic as in the xorg driver, but more in
930 * line with the intel documentation for the i965
931 */
932 if (INTEL_INFO(dev)->gen >= 4) {
933 /* on i965 use the PGM reg to read out the autoscaler values */
934 ratio = I915_READ(PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965;
935 } else {
936 if (pfit_control & VERT_AUTO_SCALE)
937 ratio = I915_READ(PFIT_AUTO_RATIOS);
938 else
939 ratio = I915_READ(PFIT_PGM_RATIOS);
940 ratio >>= PFIT_VERT_SCALE_SHIFT;
941 }
942
943 overlay->pfit_vscale_ratio = ratio;
944 }
945
946 static int check_overlay_dst(struct intel_overlay *overlay,
947 struct drm_intel_overlay_put_image *rec)
948 {
949 struct drm_display_mode *mode = &overlay->crtc->base.mode;
950
951 if (rec->dst_x < mode->hdisplay &&
952 rec->dst_x + rec->dst_width <= mode->hdisplay &&
953 rec->dst_y < mode->vdisplay &&
954 rec->dst_y + rec->dst_height <= mode->vdisplay)
955 return 0;
956 else
957 return -EINVAL;
958 }
959
960 static int check_overlay_scaling(struct put_image_params *rec)
961 {
962 u32 tmp;
963
964 /* downscaling limit is 8.0 */
965 tmp = ((rec->src_scan_h << 16) / rec->dst_h) >> 16;
966 if (tmp > 7)
967 return -EINVAL;
968 tmp = ((rec->src_scan_w << 16) / rec->dst_w) >> 16;
969 if (tmp > 7)
970 return -EINVAL;
971
972 return 0;
973 }
974
975 static int check_overlay_src(struct drm_device *dev,
976 struct drm_intel_overlay_put_image *rec,
977 struct drm_i915_gem_object *new_bo)
978 {
979 int uv_hscale = uv_hsubsampling(rec->flags);
980 int uv_vscale = uv_vsubsampling(rec->flags);
981 u32 stride_mask;
982 int depth;
983 u32 tmp;
984
985 /* check src dimensions */
986 if (IS_845G(dev) || IS_I830(dev)) {
987 if (rec->src_height > IMAGE_MAX_HEIGHT_LEGACY ||
988 rec->src_width > IMAGE_MAX_WIDTH_LEGACY)
989 return -EINVAL;
990 } else {
991 if (rec->src_height > IMAGE_MAX_HEIGHT ||
992 rec->src_width > IMAGE_MAX_WIDTH)
993 return -EINVAL;
994 }
995
996 /* better safe than sorry, use 4 as the maximal subsampling ratio */
997 if (rec->src_height < N_VERT_Y_TAPS*4 ||
998 rec->src_width < N_HORIZ_Y_TAPS*4)
999 return -EINVAL;
1000
1001 /* check alignment constraints */
1002 switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
1003 case I915_OVERLAY_RGB:
1004 /* not implemented */
1005 return -EINVAL;
1006
1007 case I915_OVERLAY_YUV_PACKED:
1008 if (uv_vscale != 1)
1009 return -EINVAL;
1010
1011 depth = packed_depth_bytes(rec->flags);
1012 if (depth < 0)
1013 return depth;
1014
1015 /* ignore UV planes */
1016 rec->stride_UV = 0;
1017 rec->offset_U = 0;
1018 rec->offset_V = 0;
1019 /* check pixel alignment */
1020 if (rec->offset_Y % depth)
1021 return -EINVAL;
1022 break;
1023
1024 case I915_OVERLAY_YUV_PLANAR:
1025 if (uv_vscale < 0 || uv_hscale < 0)
1026 return -EINVAL;
1027 /* no offset restrictions for planar formats */
1028 break;
1029
1030 default:
1031 return -EINVAL;
1032 }
1033
1034 if (rec->src_width % uv_hscale)
1035 return -EINVAL;
1036
1037 /* stride checking */
1038 if (IS_I830(dev) || IS_845G(dev))
1039 stride_mask = 255;
1040 else
1041 stride_mask = 63;
1042
1043 if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask)
1044 return -EINVAL;
1045 if (IS_GEN4(dev) && rec->stride_Y < 512)
1046 return -EINVAL;
1047
1048 tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ?
1049 4096 : 8192;
1050 if (rec->stride_Y > tmp || rec->stride_UV > 2*1024)
1051 return -EINVAL;
1052
1053 /* check buffer dimensions */
1054 switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
1055 case I915_OVERLAY_RGB:
1056 case I915_OVERLAY_YUV_PACKED:
1057 /* always 4 Y values per depth pixels */
1058 if (packed_width_bytes(rec->flags, rec->src_width) > rec->stride_Y)
1059 return -EINVAL;
1060
1061 tmp = rec->stride_Y*rec->src_height;
1062 if (rec->offset_Y + tmp > new_bo->base.size)
1063 return -EINVAL;
1064 break;
1065
1066 case I915_OVERLAY_YUV_PLANAR:
1067 if (rec->src_width > rec->stride_Y)
1068 return -EINVAL;
1069 if (rec->src_width/uv_hscale > rec->stride_UV)
1070 return -EINVAL;
1071
1072 tmp = rec->stride_Y * rec->src_height;
1073 if (rec->offset_Y + tmp > new_bo->base.size)
1074 return -EINVAL;
1075
1076 tmp = rec->stride_UV * (rec->src_height / uv_vscale);
1077 if (rec->offset_U + tmp > new_bo->base.size ||
1078 rec->offset_V + tmp > new_bo->base.size)
1079 return -EINVAL;
1080 break;
1081 }
1082
1083 return 0;
1084 }
1085
1086 /**
1087 * Return the pipe currently connected to the panel fitter,
1088 * or -1 if the panel fitter is not present or not in use
1089 */
1090 static int intel_panel_fitter_pipe(struct drm_device *dev)
1091 {
1092 struct drm_i915_private *dev_priv = dev->dev_private;
1093 u32 pfit_control;
1094
1095 /* i830 doesn't have a panel fitter */
1096 if (IS_I830(dev))
1097 return -1;
1098
1099 pfit_control = I915_READ(PFIT_CONTROL);
1100
1101 /* See if the panel fitter is in use */
1102 if ((pfit_control & PFIT_ENABLE) == 0)
1103 return -1;
1104
1105 /* 965 can place panel fitter on either pipe */
1106 if (IS_GEN4(dev))
1107 return (pfit_control >> 29) & 0x3;
1108
1109 /* older chips can only use pipe 1 */
1110 return 1;
1111 }
1112
1113 int intel_overlay_put_image(struct drm_device *dev, void *data,
1114 struct drm_file *file_priv)
1115 {
1116 struct drm_intel_overlay_put_image *put_image_rec = data;
1117 drm_i915_private_t *dev_priv = dev->dev_private;
1118 struct intel_overlay *overlay;
1119 struct drm_mode_object *drmmode_obj;
1120 struct intel_crtc *crtc;
1121 struct drm_i915_gem_object *new_bo;
1122 struct put_image_params *params;
1123 int ret;
1124
1125 /* No need to check for DRIVER_MODESET - we don't set it up then. */
1126 overlay = dev_priv->overlay;
1127 if (!overlay) {
1128 DRM_DEBUG("userspace bug: no overlay\n");
1129 return -ENODEV;
1130 }
1131
1132 if (!(put_image_rec->flags & I915_OVERLAY_ENABLE)) {
1133 mutex_lock(&dev->mode_config.mutex);
1134 mutex_lock(&dev->struct_mutex);
1135
1136 ret = intel_overlay_switch_off(overlay);
1137
1138 mutex_unlock(&dev->struct_mutex);
1139 mutex_unlock(&dev->mode_config.mutex);
1140
1141 return ret;
1142 }
1143
1144 params = kmalloc(sizeof(struct put_image_params), GFP_KERNEL);
1145 if (!params)
1146 return -ENOMEM;
1147
1148 drmmode_obj = drm_mode_object_find(dev, put_image_rec->crtc_id,
1149 DRM_MODE_OBJECT_CRTC);
1150 if (!drmmode_obj) {
1151 ret = -ENOENT;
1152 goto out_free;
1153 }
1154 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
1155
1156 new_bo = to_intel_bo(drm_gem_object_lookup(dev, file_priv,
1157 put_image_rec->bo_handle));
1158 if (&new_bo->base == NULL) {
1159 ret = -ENOENT;
1160 goto out_free;
1161 }
1162
1163 mutex_lock(&dev->mode_config.mutex);
1164 mutex_lock(&dev->struct_mutex);
1165
1166 if (new_bo->tiling_mode) {
1167 DRM_ERROR("buffer used for overlay image can not be tiled\n");
1168 ret = -EINVAL;
1169 goto out_unlock;
1170 }
1171
1172 ret = intel_overlay_recover_from_interrupt(overlay);
1173 if (ret != 0)
1174 goto out_unlock;
1175
1176 if (overlay->crtc != crtc) {
1177 struct drm_display_mode *mode = &crtc->base.mode;
1178 ret = intel_overlay_switch_off(overlay);
1179 if (ret != 0)
1180 goto out_unlock;
1181
1182 ret = check_overlay_possible_on_crtc(overlay, crtc);
1183 if (ret != 0)
1184 goto out_unlock;
1185
1186 overlay->crtc = crtc;
1187 crtc->overlay = overlay;
1188
1189 /* line too wide, i.e. one-line-mode */
1190 if (mode->hdisplay > 1024 &&
1191 intel_panel_fitter_pipe(dev) == crtc->pipe) {
1192 overlay->pfit_active = 1;
1193 update_pfit_vscale_ratio(overlay);
1194 } else
1195 overlay->pfit_active = 0;
1196 }
1197
1198 ret = check_overlay_dst(overlay, put_image_rec);
1199 if (ret != 0)
1200 goto out_unlock;
1201
1202 if (overlay->pfit_active) {
1203 params->dst_y = ((((u32)put_image_rec->dst_y) << 12) /
1204 overlay->pfit_vscale_ratio);
1205 /* shifting right rounds downwards, so add 1 */
1206 params->dst_h = ((((u32)put_image_rec->dst_height) << 12) /
1207 overlay->pfit_vscale_ratio) + 1;
1208 } else {
1209 params->dst_y = put_image_rec->dst_y;
1210 params->dst_h = put_image_rec->dst_height;
1211 }
1212 params->dst_x = put_image_rec->dst_x;
1213 params->dst_w = put_image_rec->dst_width;
1214
1215 params->src_w = put_image_rec->src_width;
1216 params->src_h = put_image_rec->src_height;
1217 params->src_scan_w = put_image_rec->src_scan_width;
1218 params->src_scan_h = put_image_rec->src_scan_height;
1219 if (params->src_scan_h > params->src_h ||
1220 params->src_scan_w > params->src_w) {
1221 ret = -EINVAL;
1222 goto out_unlock;
1223 }
1224
1225 ret = check_overlay_src(dev, put_image_rec, new_bo);
1226 if (ret != 0)
1227 goto out_unlock;
1228 params->format = put_image_rec->flags & ~I915_OVERLAY_FLAGS_MASK;
1229 params->stride_Y = put_image_rec->stride_Y;
1230 params->stride_UV = put_image_rec->stride_UV;
1231 params->offset_Y = put_image_rec->offset_Y;
1232 params->offset_U = put_image_rec->offset_U;
1233 params->offset_V = put_image_rec->offset_V;
1234
1235 /* Check scaling after src size to prevent a divide-by-zero. */
1236 ret = check_overlay_scaling(params);
1237 if (ret != 0)
1238 goto out_unlock;
1239
1240 ret = intel_overlay_do_put_image(overlay, new_bo, params);
1241 if (ret != 0)
1242 goto out_unlock;
1243
1244 mutex_unlock(&dev->struct_mutex);
1245 mutex_unlock(&dev->mode_config.mutex);
1246
1247 kfree(params);
1248
1249 return 0;
1250
1251 out_unlock:
1252 mutex_unlock(&dev->struct_mutex);
1253 mutex_unlock(&dev->mode_config.mutex);
1254 drm_gem_object_unreference_unlocked(&new_bo->base);
1255 out_free:
1256 kfree(params);
1257
1258 return ret;
1259 }
1260
1261 static void update_reg_attrs(struct intel_overlay *overlay,
1262 struct overlay_registers __iomem *regs)
1263 {
1264 iowrite32((overlay->contrast << 18) | (overlay->brightness & 0xff),
1265 &regs->OCLRC0);
1266 iowrite32(overlay->saturation, &regs->OCLRC1);
1267 }
1268
1269 static bool check_gamma_bounds(u32 gamma1, u32 gamma2)
1270 {
1271 int i;
1272
1273 if (gamma1 & 0xff000000 || gamma2 & 0xff000000)
1274 return false;
1275
1276 for (i = 0; i < 3; i++) {
1277 if (((gamma1 >> i*8) & 0xff) >= ((gamma2 >> i*8) & 0xff))
1278 return false;
1279 }
1280
1281 return true;
1282 }
1283
1284 static bool check_gamma5_errata(u32 gamma5)
1285 {
1286 int i;
1287
1288 for (i = 0; i < 3; i++) {
1289 if (((gamma5 >> i*8) & 0xff) == 0x80)
1290 return false;
1291 }
1292
1293 return true;
1294 }
1295
1296 static int check_gamma(struct drm_intel_overlay_attrs *attrs)
1297 {
1298 if (!check_gamma_bounds(0, attrs->gamma0) ||
1299 !check_gamma_bounds(attrs->gamma0, attrs->gamma1) ||
1300 !check_gamma_bounds(attrs->gamma1, attrs->gamma2) ||
1301 !check_gamma_bounds(attrs->gamma2, attrs->gamma3) ||
1302 !check_gamma_bounds(attrs->gamma3, attrs->gamma4) ||
1303 !check_gamma_bounds(attrs->gamma4, attrs->gamma5) ||
1304 !check_gamma_bounds(attrs->gamma5, 0x00ffffff))
1305 return -EINVAL;
1306
1307 if (!check_gamma5_errata(attrs->gamma5))
1308 return -EINVAL;
1309
1310 return 0;
1311 }
1312
1313 int intel_overlay_attrs(struct drm_device *dev, void *data,
1314 struct drm_file *file_priv)
1315 {
1316 struct drm_intel_overlay_attrs *attrs = data;
1317 drm_i915_private_t *dev_priv = dev->dev_private;
1318 struct intel_overlay *overlay;
1319 struct overlay_registers __iomem *regs;
1320 int ret;
1321
1322 /* No need to check for DRIVER_MODESET - we don't set it up then. */
1323 overlay = dev_priv->overlay;
1324 if (!overlay) {
1325 DRM_DEBUG("userspace bug: no overlay\n");
1326 return -ENODEV;
1327 }
1328
1329 mutex_lock(&dev->mode_config.mutex);
1330 mutex_lock(&dev->struct_mutex);
1331
1332 ret = -EINVAL;
1333 if (!(attrs->flags & I915_OVERLAY_UPDATE_ATTRS)) {
1334 attrs->color_key = overlay->color_key;
1335 attrs->brightness = overlay->brightness;
1336 attrs->contrast = overlay->contrast;
1337 attrs->saturation = overlay->saturation;
1338
1339 if (!IS_GEN2(dev)) {
1340 attrs->gamma0 = I915_READ(OGAMC0);
1341 attrs->gamma1 = I915_READ(OGAMC1);
1342 attrs->gamma2 = I915_READ(OGAMC2);
1343 attrs->gamma3 = I915_READ(OGAMC3);
1344 attrs->gamma4 = I915_READ(OGAMC4);
1345 attrs->gamma5 = I915_READ(OGAMC5);
1346 }
1347 } else {
1348 if (attrs->brightness < -128 || attrs->brightness > 127)
1349 goto out_unlock;
1350 if (attrs->contrast > 255)
1351 goto out_unlock;
1352 if (attrs->saturation > 1023)
1353 goto out_unlock;
1354
1355 overlay->color_key = attrs->color_key;
1356 overlay->brightness = attrs->brightness;
1357 overlay->contrast = attrs->contrast;
1358 overlay->saturation = attrs->saturation;
1359
1360 regs = intel_overlay_map_regs(overlay);
1361 if (!regs) {
1362 ret = -ENOMEM;
1363 goto out_unlock;
1364 }
1365
1366 update_reg_attrs(overlay, regs);
1367
1368 intel_overlay_unmap_regs(overlay, regs);
1369
1370 if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) {
1371 if (IS_GEN2(dev))
1372 goto out_unlock;
1373
1374 if (overlay->active) {
1375 ret = -EBUSY;
1376 goto out_unlock;
1377 }
1378
1379 ret = check_gamma(attrs);
1380 if (ret)
1381 goto out_unlock;
1382
1383 I915_WRITE(OGAMC0, attrs->gamma0);
1384 I915_WRITE(OGAMC1, attrs->gamma1);
1385 I915_WRITE(OGAMC2, attrs->gamma2);
1386 I915_WRITE(OGAMC3, attrs->gamma3);
1387 I915_WRITE(OGAMC4, attrs->gamma4);
1388 I915_WRITE(OGAMC5, attrs->gamma5);
1389 }
1390 }
1391
1392 ret = 0;
1393 out_unlock:
1394 mutex_unlock(&dev->struct_mutex);
1395 mutex_unlock(&dev->mode_config.mutex);
1396
1397 return ret;
1398 }
1399
1400 void intel_setup_overlay(struct drm_device *dev)
1401 {
1402 drm_i915_private_t *dev_priv = dev->dev_private;
1403 struct intel_overlay *overlay;
1404 struct drm_i915_gem_object *reg_bo;
1405 struct overlay_registers __iomem *regs;
1406 int ret;
1407
1408 if (!HAS_OVERLAY(dev))
1409 return;
1410
1411 overlay = kzalloc(sizeof(struct intel_overlay), GFP_KERNEL);
1412 if (!overlay)
1413 return;
1414
1415 mutex_lock(&dev->struct_mutex);
1416 if (WARN_ON(dev_priv->overlay))
1417 goto out_free;
1418
1419 overlay->dev = dev;
1420
1421 reg_bo = i915_gem_alloc_object(dev, PAGE_SIZE);
1422 if (!reg_bo)
1423 goto out_free;
1424 overlay->reg_bo = reg_bo;
1425
1426 if (OVERLAY_NEEDS_PHYSICAL(dev)) {
1427 ret = i915_gem_attach_phys_object(dev, reg_bo,
1428 I915_GEM_PHYS_OVERLAY_REGS,
1429 PAGE_SIZE);
1430 if (ret) {
1431 DRM_ERROR("failed to attach phys overlay regs\n");
1432 goto out_free_bo;
1433 }
1434 overlay->flip_addr = reg_bo->phys_obj->handle->busaddr;
1435 } else {
1436 ret = i915_gem_object_pin(reg_bo, PAGE_SIZE, true);
1437 if (ret) {
1438 DRM_ERROR("failed to pin overlay register bo\n");
1439 goto out_free_bo;
1440 }
1441 overlay->flip_addr = reg_bo->gtt_offset;
1442
1443 ret = i915_gem_object_set_to_gtt_domain(reg_bo, true);
1444 if (ret) {
1445 DRM_ERROR("failed to move overlay register bo into the GTT\n");
1446 goto out_unpin_bo;
1447 }
1448 }
1449
1450 /* init all values */
1451 overlay->color_key = 0x0101fe;
1452 overlay->brightness = -19;
1453 overlay->contrast = 75;
1454 overlay->saturation = 146;
1455
1456 regs = intel_overlay_map_regs(overlay);
1457 if (!regs)
1458 goto out_unpin_bo;
1459
1460 memset_io(regs, 0, sizeof(struct overlay_registers));
1461 update_polyphase_filter(regs);
1462 update_reg_attrs(overlay, regs);
1463
1464 intel_overlay_unmap_regs(overlay, regs);
1465
1466 dev_priv->overlay = overlay;
1467 mutex_unlock(&dev->struct_mutex);
1468 DRM_INFO("initialized overlay support\n");
1469 return;
1470
1471 out_unpin_bo:
1472 if (!OVERLAY_NEEDS_PHYSICAL(dev))
1473 i915_gem_object_unpin(reg_bo);
1474 out_free_bo:
1475 drm_gem_object_unreference(&reg_bo->base);
1476 out_free:
1477 mutex_unlock(&dev->struct_mutex);
1478 kfree(overlay);
1479 return;
1480 }
1481
1482 void intel_cleanup_overlay(struct drm_device *dev)
1483 {
1484 drm_i915_private_t *dev_priv = dev->dev_private;
1485
1486 if (!dev_priv->overlay)
1487 return;
1488
1489 /* The bo's should be free'd by the generic code already.
1490 * Furthermore modesetting teardown happens beforehand so the
1491 * hardware should be off already */
1492 BUG_ON(dev_priv->overlay->active);
1493
1494 drm_gem_object_unreference_unlocked(&dev_priv->overlay->reg_bo->base);
1495 kfree(dev_priv->overlay);
1496 }
1497
1498 #ifdef CONFIG_DEBUG_FS
1499 #include <linux/seq_file.h>
1500
1501 struct intel_overlay_error_state {
1502 struct overlay_registers regs;
1503 unsigned long base;
1504 u32 dovsta;
1505 u32 isr;
1506 };
1507
1508 static struct overlay_registers __iomem *
1509 intel_overlay_map_regs_atomic(struct intel_overlay *overlay)
1510 {
1511 drm_i915_private_t *dev_priv = overlay->dev->dev_private;
1512 struct overlay_registers __iomem *regs;
1513
1514 if (OVERLAY_NEEDS_PHYSICAL(overlay->dev))
1515 /* Cast to make sparse happy, but it's wc memory anyway, so
1516 * equivalent to the wc io mapping on X86. */
1517 regs = (struct overlay_registers __iomem *)
1518 overlay->reg_bo->phys_obj->handle->vaddr;
1519 else
1520 regs = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
1521 overlay->reg_bo->gtt_offset);
1522
1523 return regs;
1524 }
1525
1526 static void intel_overlay_unmap_regs_atomic(struct intel_overlay *overlay,
1527 struct overlay_registers __iomem *regs)
1528 {
1529 if (!OVERLAY_NEEDS_PHYSICAL(overlay->dev))
1530 io_mapping_unmap_atomic(regs);
1531 }
1532
1533
1534 struct intel_overlay_error_state *
1535 intel_overlay_capture_error_state(struct drm_device *dev)
1536 {
1537 drm_i915_private_t *dev_priv = dev->dev_private;
1538 struct intel_overlay *overlay = dev_priv->overlay;
1539 struct intel_overlay_error_state *error;
1540 struct overlay_registers __iomem *regs;
1541
1542 if (!overlay || !overlay->active)
1543 return NULL;
1544
1545 error = kmalloc(sizeof(*error), GFP_ATOMIC);
1546 if (error == NULL)
1547 return NULL;
1548
1549 error->dovsta = I915_READ(DOVSTA);
1550 error->isr = I915_READ(ISR);
1551 if (OVERLAY_NEEDS_PHYSICAL(overlay->dev))
1552 error->base = (__force long)overlay->reg_bo->phys_obj->handle->vaddr;
1553 else
1554 error->base = overlay->reg_bo->gtt_offset;
1555
1556 regs = intel_overlay_map_regs_atomic(overlay);
1557 if (!regs)
1558 goto err;
1559
1560 memcpy_fromio(&error->regs, regs, sizeof(struct overlay_registers));
1561 intel_overlay_unmap_regs_atomic(overlay, regs);
1562
1563 return error;
1564
1565 err:
1566 kfree(error);
1567 return NULL;
1568 }
1569
1570 void
1571 intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error)
1572 {
1573 seq_printf(m, "Overlay, status: 0x%08x, interrupt: 0x%08x\n",
1574 error->dovsta, error->isr);
1575 seq_printf(m, " Register file at 0x%08lx:\n",
1576 error->base);
1577
1578 #define P(x) seq_printf(m, " " #x ": 0x%08x\n", error->regs.x)
1579 P(OBUF_0Y);
1580 P(OBUF_1Y);
1581 P(OBUF_0U);
1582 P(OBUF_0V);
1583 P(OBUF_1U);
1584 P(OBUF_1V);
1585 P(OSTRIDE);
1586 P(YRGB_VPH);
1587 P(UV_VPH);
1588 P(HORZ_PH);
1589 P(INIT_PHS);
1590 P(DWINPOS);
1591 P(DWINSZ);
1592 P(SWIDTH);
1593 P(SWIDTHSW);
1594 P(SHEIGHT);
1595 P(YRGBSCALE);
1596 P(UVSCALE);
1597 P(OCLRC0);
1598 P(OCLRC1);
1599 P(DCLRKV);
1600 P(DCLRKM);
1601 P(SCLRKVH);
1602 P(SCLRKVL);
1603 P(SCLRKEN);
1604 P(OCONFIG);
1605 P(OCMD);
1606 P(OSTART_0Y);
1607 P(OSTART_1Y);
1608 P(OSTART_0U);
1609 P(OSTART_0V);
1610 P(OSTART_1U);
1611 P(OSTART_1V);
1612 P(OTILEOFF_0Y);
1613 P(OTILEOFF_1Y);
1614 P(OTILEOFF_0U);
1615 P(OTILEOFF_0V);
1616 P(OTILEOFF_1U);
1617 P(OTILEOFF_1V);
1618 P(FASTHSCALE);
1619 P(UVSCALEV);
1620 #undef P
1621 }
1622 #endif
Linux kernel - Deliverables
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