4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Daniel Vetter <daniel@ffwll.ch>
26 * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c
29 #include <linux/seq_file.h>
35 #include "intel_drv.h"
37 /* Limits for overlay size. According to intel doc, the real limits are:
38 * Y width: 4095, UV width (planar): 2047, Y height: 2047,
39 * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use
40 * the mininum of both. */
41 #define IMAGE_MAX_WIDTH 2048
42 #define IMAGE_MAX_HEIGHT 2046 /* 2 * 1023 */
43 /* on 830 and 845 these large limits result in the card hanging */
44 #define IMAGE_MAX_WIDTH_LEGACY 1024
45 #define IMAGE_MAX_HEIGHT_LEGACY 1088
47 /* overlay register definitions */
49 #define OCMD_TILED_SURFACE (0x1<<19)
50 #define OCMD_MIRROR_MASK (0x3<<17)
51 #define OCMD_MIRROR_MODE (0x3<<17)
52 #define OCMD_MIRROR_HORIZONTAL (0x1<<17)
53 #define OCMD_MIRROR_VERTICAL (0x2<<17)
54 #define OCMD_MIRROR_BOTH (0x3<<17)
55 #define OCMD_BYTEORDER_MASK (0x3<<14) /* zero for YUYV or FOURCC YUY2 */
56 #define OCMD_UV_SWAP (0x1<<14) /* YVYU */
57 #define OCMD_Y_SWAP (0x2<<14) /* UYVY or FOURCC UYVY */
58 #define OCMD_Y_AND_UV_SWAP (0x3<<14) /* VYUY */
59 #define OCMD_SOURCE_FORMAT_MASK (0xf<<10)
60 #define OCMD_RGB_888 (0x1<<10) /* not in i965 Intel docs */
61 #define OCMD_RGB_555 (0x2<<10) /* not in i965 Intel docs */
62 #define OCMD_RGB_565 (0x3<<10) /* not in i965 Intel docs */
63 #define OCMD_YUV_422_PACKED (0x8<<10)
64 #define OCMD_YUV_411_PACKED (0x9<<10) /* not in i965 Intel docs */
65 #define OCMD_YUV_420_PLANAR (0xc<<10)
66 #define OCMD_YUV_422_PLANAR (0xd<<10)
67 #define OCMD_YUV_410_PLANAR (0xe<<10) /* also 411 */
68 #define OCMD_TVSYNCFLIP_PARITY (0x1<<9)
69 #define OCMD_TVSYNCFLIP_ENABLE (0x1<<7)
70 #define OCMD_BUF_TYPE_MASK (0x1<<5)
71 #define OCMD_BUF_TYPE_FRAME (0x0<<5)
72 #define OCMD_BUF_TYPE_FIELD (0x1<<5)
73 #define OCMD_TEST_MODE (0x1<<4)
74 #define OCMD_BUFFER_SELECT (0x3<<2)
75 #define OCMD_BUFFER0 (0x0<<2)
76 #define OCMD_BUFFER1 (0x1<<2)
77 #define OCMD_FIELD_SELECT (0x1<<2)
78 #define OCMD_FIELD0 (0x0<<1)
79 #define OCMD_FIELD1 (0x1<<1)
80 #define OCMD_ENABLE (0x1<<0)
82 /* OCONFIG register */
83 #define OCONF_PIPE_MASK (0x1<<18)
84 #define OCONF_PIPE_A (0x0<<18)
85 #define OCONF_PIPE_B (0x1<<18)
86 #define OCONF_GAMMA2_ENABLE (0x1<<16)
87 #define OCONF_CSC_MODE_BT601 (0x0<<5)
88 #define OCONF_CSC_MODE_BT709 (0x1<<5)
89 #define OCONF_CSC_BYPASS (0x1<<4)
90 #define OCONF_CC_OUT_8BIT (0x1<<3)
91 #define OCONF_TEST_MODE (0x1<<2)
92 #define OCONF_THREE_LINE_BUFFER (0x1<<0)
93 #define OCONF_TWO_LINE_BUFFER (0x0<<0)
95 /* DCLRKM (dst-key) register */
96 #define DST_KEY_ENABLE (0x1<<31)
97 #define CLK_RGB24_MASK 0x0
98 #define CLK_RGB16_MASK 0x070307
99 #define CLK_RGB15_MASK 0x070707
100 #define CLK_RGB8I_MASK 0xffffff
102 #define RGB16_TO_COLORKEY(c) \
103 (((c & 0xF800) << 8) | ((c & 0x07E0) << 5) | ((c & 0x001F) << 3))
104 #define RGB15_TO_COLORKEY(c) \
105 (((c & 0x7c00) << 9) | ((c & 0x03E0) << 6) | ((c & 0x001F) << 3))
107 /* overlay flip addr flag */
108 #define OFC_UPDATE 0x1
110 /* polyphase filter coefficients */
111 #define N_HORIZ_Y_TAPS 5
112 #define N_VERT_Y_TAPS 3
113 #define N_HORIZ_UV_TAPS 3
114 #define N_VERT_UV_TAPS 3
118 /* memory bufferd overlay registers */
119 struct overlay_registers
{
147 u32 RESERVED1
; /* 0x6C */
160 u32 FASTHSCALE
; /* 0xA0 */
161 u32 UVSCALEV
; /* 0xA4 */
162 u32 RESERVEDC
[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */
163 u16 Y_VCOEFS
[N_VERT_Y_TAPS
* N_PHASES
]; /* 0x200 */
164 u16 RESERVEDD
[0x100 / 2 - N_VERT_Y_TAPS
* N_PHASES
];
165 u16 Y_HCOEFS
[N_HORIZ_Y_TAPS
* N_PHASES
]; /* 0x300 */
166 u16 RESERVEDE
[0x200 / 2 - N_HORIZ_Y_TAPS
* N_PHASES
];
167 u16 UV_VCOEFS
[N_VERT_UV_TAPS
* N_PHASES
]; /* 0x500 */
168 u16 RESERVEDF
[0x100 / 2 - N_VERT_UV_TAPS
* N_PHASES
];
169 u16 UV_HCOEFS
[N_HORIZ_UV_TAPS
* N_PHASES
]; /* 0x600 */
170 u16 RESERVEDG
[0x100 / 2 - N_HORIZ_UV_TAPS
* N_PHASES
];
173 struct intel_overlay
{
174 struct drm_device
*dev
;
175 struct intel_crtc
*crtc
;
176 struct drm_i915_gem_object
*vid_bo
;
177 struct drm_i915_gem_object
*old_vid_bo
;
180 u32 pfit_vscale_ratio
; /* shifted-point number, (1<<12) == 1.0 */
182 u32 brightness
, contrast
, saturation
;
183 u32 old_xscale
, old_yscale
;
184 /* register access */
186 struct drm_i915_gem_object
*reg_bo
;
188 uint32_t last_flip_req
;
189 void (*flip_tail
)(struct intel_overlay
*);
192 static struct overlay_registers
*
193 intel_overlay_map_regs(struct intel_overlay
*overlay
)
195 drm_i915_private_t
*dev_priv
= overlay
->dev
->dev_private
;
196 struct overlay_registers
*regs
;
198 if (OVERLAY_NEEDS_PHYSICAL(overlay
->dev
))
199 regs
= overlay
->reg_bo
->phys_obj
->handle
->vaddr
;
201 regs
= io_mapping_map_wc(dev_priv
->mm
.gtt_mapping
,
202 overlay
->reg_bo
->gtt_offset
);
207 static void intel_overlay_unmap_regs(struct intel_overlay
*overlay
,
208 struct overlay_registers
*regs
)
210 if (!OVERLAY_NEEDS_PHYSICAL(overlay
->dev
))
211 io_mapping_unmap(regs
);
214 static int intel_overlay_do_wait_request(struct intel_overlay
*overlay
,
215 struct drm_i915_gem_request
*request
,
216 void (*tail
)(struct intel_overlay
*))
218 struct drm_device
*dev
= overlay
->dev
;
219 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
222 BUG_ON(overlay
->last_flip_req
);
223 ret
= i915_add_request(LP_RING(dev_priv
), NULL
, request
);
228 overlay
->last_flip_req
= request
->seqno
;
229 overlay
->flip_tail
= tail
;
230 ret
= i915_wait_request(LP_RING(dev_priv
), overlay
->last_flip_req
);
234 overlay
->last_flip_req
= 0;
238 /* Workaround for i830 bug where pipe a must be enable to change control regs */
240 i830_activate_pipe_a(struct drm_device
*dev
)
242 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
243 struct intel_crtc
*crtc
;
244 struct drm_crtc_helper_funcs
*crtc_funcs
;
245 struct drm_display_mode vesa_640x480
= {
246 DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER
, 25175, 640, 656,
247 752, 800, 0, 480, 489, 492, 525, 0,
248 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
)
251 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[0]);
252 if (crtc
->dpms_mode
== DRM_MODE_DPMS_ON
)
255 /* most i8xx have pipe a forced on, so don't trust dpms mode */
256 if (I915_READ(_PIPEACONF
) & PIPECONF_ENABLE
)
259 crtc_funcs
= crtc
->base
.helper_private
;
260 if (crtc_funcs
->dpms
== NULL
)
263 DRM_DEBUG_DRIVER("Enabling pipe A in order to enable overlay\n");
265 mode
= drm_mode_duplicate(dev
, &vesa_640x480
);
266 drm_mode_set_crtcinfo(mode
, CRTC_INTERLACE_HALVE_V
);
267 if(!drm_crtc_helper_set_mode(&crtc
->base
, mode
,
268 crtc
->base
.x
, crtc
->base
.y
,
272 crtc_funcs
->dpms(&crtc
->base
, DRM_MODE_DPMS_ON
);
277 i830_deactivate_pipe_a(struct drm_device
*dev
)
279 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
280 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[0];
281 struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
283 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_OFF
);
286 /* overlay needs to be disable in OCMD reg */
287 static int intel_overlay_on(struct intel_overlay
*overlay
)
289 struct drm_device
*dev
= overlay
->dev
;
290 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
291 struct drm_i915_gem_request
*request
;
292 int pipe_a_quirk
= 0;
295 BUG_ON(overlay
->active
);
299 pipe_a_quirk
= i830_activate_pipe_a(dev
);
300 if (pipe_a_quirk
< 0)
304 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
305 if (request
== NULL
) {
310 ret
= BEGIN_LP_RING(4);
316 OUT_RING(MI_OVERLAY_FLIP
| MI_OVERLAY_ON
);
317 OUT_RING(overlay
->flip_addr
| OFC_UPDATE
);
318 OUT_RING(MI_WAIT_FOR_EVENT
| MI_WAIT_FOR_OVERLAY_FLIP
);
322 ret
= intel_overlay_do_wait_request(overlay
, request
, NULL
);
325 i830_deactivate_pipe_a(dev
);
330 /* overlay needs to be enabled in OCMD reg */
331 static int intel_overlay_continue(struct intel_overlay
*overlay
,
332 bool load_polyphase_filter
)
334 struct drm_device
*dev
= overlay
->dev
;
335 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
336 struct drm_i915_gem_request
*request
;
337 u32 flip_addr
= overlay
->flip_addr
;
341 BUG_ON(!overlay
->active
);
343 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
347 if (load_polyphase_filter
)
348 flip_addr
|= OFC_UPDATE
;
350 /* check for underruns */
351 tmp
= I915_READ(DOVSTA
);
353 DRM_DEBUG("overlay underrun, DOVSTA: %x\n", tmp
);
355 ret
= BEGIN_LP_RING(2);
360 OUT_RING(MI_OVERLAY_FLIP
| MI_OVERLAY_CONTINUE
);
364 ret
= i915_add_request(LP_RING(dev_priv
), NULL
, request
);
370 overlay
->last_flip_req
= request
->seqno
;
374 static void intel_overlay_release_old_vid_tail(struct intel_overlay
*overlay
)
376 struct drm_i915_gem_object
*obj
= overlay
->old_vid_bo
;
378 i915_gem_object_unpin(obj
);
379 drm_gem_object_unreference(&obj
->base
);
381 overlay
->old_vid_bo
= NULL
;
384 static void intel_overlay_off_tail(struct intel_overlay
*overlay
)
386 struct drm_i915_gem_object
*obj
= overlay
->vid_bo
;
388 /* never have the overlay hw on without showing a frame */
389 BUG_ON(!overlay
->vid_bo
);
391 i915_gem_object_unpin(obj
);
392 drm_gem_object_unreference(&obj
->base
);
393 overlay
->vid_bo
= NULL
;
395 overlay
->crtc
->overlay
= NULL
;
396 overlay
->crtc
= NULL
;
400 /* overlay needs to be disabled in OCMD reg */
401 static int intel_overlay_off(struct intel_overlay
*overlay
)
403 struct drm_device
*dev
= overlay
->dev
;
404 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
405 u32 flip_addr
= overlay
->flip_addr
;
406 struct drm_i915_gem_request
*request
;
409 BUG_ON(!overlay
->active
);
411 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
415 /* According to intel docs the overlay hw may hang (when switching
416 * off) without loading the filter coeffs. It is however unclear whether
417 * this applies to the disabling of the overlay or to the switching off
418 * of the hw. Do it in both cases */
419 flip_addr
|= OFC_UPDATE
;
421 ret
= BEGIN_LP_RING(6);
426 /* wait for overlay to go idle */
427 OUT_RING(MI_OVERLAY_FLIP
| MI_OVERLAY_CONTINUE
);
429 OUT_RING(MI_WAIT_FOR_EVENT
| MI_WAIT_FOR_OVERLAY_FLIP
);
430 /* turn overlay off */
431 OUT_RING(MI_OVERLAY_FLIP
| MI_OVERLAY_OFF
);
433 OUT_RING(MI_WAIT_FOR_EVENT
| MI_WAIT_FOR_OVERLAY_FLIP
);
436 return intel_overlay_do_wait_request(overlay
, request
,
437 intel_overlay_off_tail
);
440 /* recover from an interruption due to a signal
441 * We have to be careful not to repeat work forever an make forward progess. */
442 static int intel_overlay_recover_from_interrupt(struct intel_overlay
*overlay
)
444 struct drm_device
*dev
= overlay
->dev
;
445 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
448 if (overlay
->last_flip_req
== 0)
451 ret
= i915_wait_request(LP_RING(dev_priv
), overlay
->last_flip_req
);
455 if (overlay
->flip_tail
)
456 overlay
->flip_tail(overlay
);
458 overlay
->last_flip_req
= 0;
462 /* Wait for pending overlay flip and release old frame.
463 * Needs to be called before the overlay register are changed
464 * via intel_overlay_(un)map_regs
466 static int intel_overlay_release_old_vid(struct intel_overlay
*overlay
)
468 struct drm_device
*dev
= overlay
->dev
;
469 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
472 /* Only wait if there is actually an old frame to release to
473 * guarantee forward progress.
475 if (!overlay
->old_vid_bo
)
478 if (I915_READ(ISR
) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT
) {
479 struct drm_i915_gem_request
*request
;
481 /* synchronous slowpath */
482 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
486 ret
= BEGIN_LP_RING(2);
492 OUT_RING(MI_WAIT_FOR_EVENT
| MI_WAIT_FOR_OVERLAY_FLIP
);
496 ret
= intel_overlay_do_wait_request(overlay
, request
,
497 intel_overlay_release_old_vid_tail
);
502 intel_overlay_release_old_vid_tail(overlay
);
506 struct put_image_params
{
523 static int packed_depth_bytes(u32 format
)
525 switch (format
& I915_OVERLAY_DEPTH_MASK
) {
526 case I915_OVERLAY_YUV422
:
528 case I915_OVERLAY_YUV411
:
529 /* return 6; not implemented */
535 static int packed_width_bytes(u32 format
, short width
)
537 switch (format
& I915_OVERLAY_DEPTH_MASK
) {
538 case I915_OVERLAY_YUV422
:
545 static int uv_hsubsampling(u32 format
)
547 switch (format
& I915_OVERLAY_DEPTH_MASK
) {
548 case I915_OVERLAY_YUV422
:
549 case I915_OVERLAY_YUV420
:
551 case I915_OVERLAY_YUV411
:
552 case I915_OVERLAY_YUV410
:
559 static int uv_vsubsampling(u32 format
)
561 switch (format
& I915_OVERLAY_DEPTH_MASK
) {
562 case I915_OVERLAY_YUV420
:
563 case I915_OVERLAY_YUV410
:
565 case I915_OVERLAY_YUV422
:
566 case I915_OVERLAY_YUV411
:
573 static u32
calc_swidthsw(struct drm_device
*dev
, u32 offset
, u32 width
)
575 u32 mask
, shift
, ret
;
583 ret
= ((offset
+ width
+ mask
) >> shift
) - (offset
>> shift
);
590 static const u16 y_static_hcoeffs
[N_HORIZ_Y_TAPS
* N_PHASES
] = {
591 0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0,
592 0x3000, 0xb500, 0x19d0, 0x1880, 0xb440,
593 0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0,
594 0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380,
595 0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320,
596 0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0,
597 0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260,
598 0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200,
599 0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0,
600 0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160,
601 0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120,
602 0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0,
603 0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0,
604 0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060,
605 0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040,
606 0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020,
607 0xb000, 0x3000, 0x0800, 0x3000, 0xb000
610 static const u16 uv_static_hcoeffs
[N_HORIZ_UV_TAPS
* N_PHASES
] = {
611 0x3000, 0x1800, 0x1800, 0xb000, 0x18d0, 0x2e60,
612 0xb000, 0x1990, 0x2ce0, 0xb020, 0x1a68, 0x2b40,
613 0xb040, 0x1b20, 0x29e0, 0xb060, 0x1bd8, 0x2880,
614 0xb080, 0x1c88, 0x3e60, 0xb0a0, 0x1d28, 0x3c00,
615 0xb0c0, 0x1db8, 0x39e0, 0xb0e0, 0x1e40, 0x37e0,
616 0xb100, 0x1eb8, 0x3620, 0xb100, 0x1f18, 0x34a0,
617 0xb100, 0x1f68, 0x3360, 0xb0e0, 0x1fa8, 0x3240,
618 0xb0c0, 0x1fe0, 0x3140, 0xb060, 0x1ff0, 0x30a0,
619 0x3000, 0x0800, 0x3000
622 static void update_polyphase_filter(struct overlay_registers
*regs
)
624 memcpy(regs
->Y_HCOEFS
, y_static_hcoeffs
, sizeof(y_static_hcoeffs
));
625 memcpy(regs
->UV_HCOEFS
, uv_static_hcoeffs
, sizeof(uv_static_hcoeffs
));
628 static bool update_scaling_factors(struct intel_overlay
*overlay
,
629 struct overlay_registers
*regs
,
630 struct put_image_params
*params
)
632 /* fixed point with a 12 bit shift */
633 u32 xscale
, yscale
, xscale_UV
, yscale_UV
;
635 #define FRACT_MASK 0xfff
636 bool scale_changed
= false;
637 int uv_hscale
= uv_hsubsampling(params
->format
);
638 int uv_vscale
= uv_vsubsampling(params
->format
);
640 if (params
->dst_w
> 1)
641 xscale
= ((params
->src_scan_w
- 1) << FP_SHIFT
)
644 xscale
= 1 << FP_SHIFT
;
646 if (params
->dst_h
> 1)
647 yscale
= ((params
->src_scan_h
- 1) << FP_SHIFT
)
650 yscale
= 1 << FP_SHIFT
;
652 /*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/
653 xscale_UV
= xscale
/uv_hscale
;
654 yscale_UV
= yscale
/uv_vscale
;
655 /* make the Y scale to UV scale ratio an exact multiply */
656 xscale
= xscale_UV
* uv_hscale
;
657 yscale
= yscale_UV
* uv_vscale
;
663 if (xscale
!= overlay
->old_xscale
|| yscale
!= overlay
->old_yscale
)
664 scale_changed
= true;
665 overlay
->old_xscale
= xscale
;
666 overlay
->old_yscale
= yscale
;
668 regs
->YRGBSCALE
= (((yscale
& FRACT_MASK
) << 20) |
669 ((xscale
>> FP_SHIFT
) << 16) |
670 ((xscale
& FRACT_MASK
) << 3));
672 regs
->UVSCALE
= (((yscale_UV
& FRACT_MASK
) << 20) |
673 ((xscale_UV
>> FP_SHIFT
) << 16) |
674 ((xscale_UV
& FRACT_MASK
) << 3));
676 regs
->UVSCALEV
= ((((yscale
>> FP_SHIFT
) << 16) |
677 ((yscale_UV
>> FP_SHIFT
) << 0)));
680 update_polyphase_filter(regs
);
682 return scale_changed
;
685 static void update_colorkey(struct intel_overlay
*overlay
,
686 struct overlay_registers
*regs
)
688 u32 key
= overlay
->color_key
;
690 switch (overlay
->crtc
->base
.fb
->bits_per_pixel
) {
693 regs
->DCLRKM
= CLK_RGB8I_MASK
| DST_KEY_ENABLE
;
697 if (overlay
->crtc
->base
.fb
->depth
== 15) {
698 regs
->DCLRKV
= RGB15_TO_COLORKEY(key
);
699 regs
->DCLRKM
= CLK_RGB15_MASK
| DST_KEY_ENABLE
;
701 regs
->DCLRKV
= RGB16_TO_COLORKEY(key
);
702 regs
->DCLRKM
= CLK_RGB16_MASK
| DST_KEY_ENABLE
;
709 regs
->DCLRKM
= CLK_RGB24_MASK
| DST_KEY_ENABLE
;
714 static u32
overlay_cmd_reg(struct put_image_params
*params
)
716 u32 cmd
= OCMD_ENABLE
| OCMD_BUF_TYPE_FRAME
| OCMD_BUFFER0
;
718 if (params
->format
& I915_OVERLAY_YUV_PLANAR
) {
719 switch (params
->format
& I915_OVERLAY_DEPTH_MASK
) {
720 case I915_OVERLAY_YUV422
:
721 cmd
|= OCMD_YUV_422_PLANAR
;
723 case I915_OVERLAY_YUV420
:
724 cmd
|= OCMD_YUV_420_PLANAR
;
726 case I915_OVERLAY_YUV411
:
727 case I915_OVERLAY_YUV410
:
728 cmd
|= OCMD_YUV_410_PLANAR
;
731 } else { /* YUV packed */
732 switch (params
->format
& I915_OVERLAY_DEPTH_MASK
) {
733 case I915_OVERLAY_YUV422
:
734 cmd
|= OCMD_YUV_422_PACKED
;
736 case I915_OVERLAY_YUV411
:
737 cmd
|= OCMD_YUV_411_PACKED
;
741 switch (params
->format
& I915_OVERLAY_SWAP_MASK
) {
742 case I915_OVERLAY_NO_SWAP
:
744 case I915_OVERLAY_UV_SWAP
:
747 case I915_OVERLAY_Y_SWAP
:
750 case I915_OVERLAY_Y_AND_UV_SWAP
:
751 cmd
|= OCMD_Y_AND_UV_SWAP
;
759 static int intel_overlay_do_put_image(struct intel_overlay
*overlay
,
760 struct drm_i915_gem_object
*new_bo
,
761 struct put_image_params
*params
)
764 struct overlay_registers
*regs
;
765 bool scale_changed
= false;
766 struct drm_device
*dev
= overlay
->dev
;
768 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
769 BUG_ON(!mutex_is_locked(&dev
->mode_config
.mutex
));
772 ret
= intel_overlay_release_old_vid(overlay
);
776 ret
= i915_gem_object_pin(new_bo
, PAGE_SIZE
, true);
780 ret
= i915_gem_object_set_to_gtt_domain(new_bo
, 0);
784 ret
= i915_gem_object_put_fence(new_bo
);
788 if (!overlay
->active
) {
789 regs
= intel_overlay_map_regs(overlay
);
794 regs
->OCONFIG
= OCONF_CC_OUT_8BIT
;
795 if (IS_GEN4(overlay
->dev
))
796 regs
->OCONFIG
|= OCONF_CSC_MODE_BT709
;
797 regs
->OCONFIG
|= overlay
->crtc
->pipe
== 0 ?
798 OCONF_PIPE_A
: OCONF_PIPE_B
;
799 intel_overlay_unmap_regs(overlay
, regs
);
801 ret
= intel_overlay_on(overlay
);
806 regs
= intel_overlay_map_regs(overlay
);
812 regs
->DWINPOS
= (params
->dst_y
<< 16) | params
->dst_x
;
813 regs
->DWINSZ
= (params
->dst_h
<< 16) | params
->dst_w
;
815 if (params
->format
& I915_OVERLAY_YUV_PACKED
)
816 tmp_width
= packed_width_bytes(params
->format
, params
->src_w
);
818 tmp_width
= params
->src_w
;
820 regs
->SWIDTH
= params
->src_w
;
821 regs
->SWIDTHSW
= calc_swidthsw(overlay
->dev
,
822 params
->offset_Y
, tmp_width
);
823 regs
->SHEIGHT
= params
->src_h
;
824 regs
->OBUF_0Y
= new_bo
->gtt_offset
+ params
-> offset_Y
;
825 regs
->OSTRIDE
= params
->stride_Y
;
827 if (params
->format
& I915_OVERLAY_YUV_PLANAR
) {
828 int uv_hscale
= uv_hsubsampling(params
->format
);
829 int uv_vscale
= uv_vsubsampling(params
->format
);
831 regs
->SWIDTH
|= (params
->src_w
/uv_hscale
) << 16;
832 tmp_U
= calc_swidthsw(overlay
->dev
, params
->offset_U
,
833 params
->src_w
/uv_hscale
);
834 tmp_V
= calc_swidthsw(overlay
->dev
, params
->offset_V
,
835 params
->src_w
/uv_hscale
);
836 regs
->SWIDTHSW
|= max_t(u32
, tmp_U
, tmp_V
) << 16;
837 regs
->SHEIGHT
|= (params
->src_h
/uv_vscale
) << 16;
838 regs
->OBUF_0U
= new_bo
->gtt_offset
+ params
->offset_U
;
839 regs
->OBUF_0V
= new_bo
->gtt_offset
+ params
->offset_V
;
840 regs
->OSTRIDE
|= params
->stride_UV
<< 16;
843 scale_changed
= update_scaling_factors(overlay
, regs
, params
);
845 update_colorkey(overlay
, regs
);
847 regs
->OCMD
= overlay_cmd_reg(params
);
849 intel_overlay_unmap_regs(overlay
, regs
);
851 ret
= intel_overlay_continue(overlay
, scale_changed
);
855 overlay
->old_vid_bo
= overlay
->vid_bo
;
856 overlay
->vid_bo
= new_bo
;
861 i915_gem_object_unpin(new_bo
);
865 int intel_overlay_switch_off(struct intel_overlay
*overlay
)
867 struct overlay_registers
*regs
;
868 struct drm_device
*dev
= overlay
->dev
;
871 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
872 BUG_ON(!mutex_is_locked(&dev
->mode_config
.mutex
));
874 ret
= intel_overlay_recover_from_interrupt(overlay
);
878 if (!overlay
->active
)
881 ret
= intel_overlay_release_old_vid(overlay
);
885 regs
= intel_overlay_map_regs(overlay
);
887 intel_overlay_unmap_regs(overlay
, regs
);
889 ret
= intel_overlay_off(overlay
);
893 intel_overlay_off_tail(overlay
);
897 static int check_overlay_possible_on_crtc(struct intel_overlay
*overlay
,
898 struct intel_crtc
*crtc
)
900 drm_i915_private_t
*dev_priv
= overlay
->dev
->dev_private
;
905 /* can't use the overlay with double wide pipe */
906 if (INTEL_INFO(overlay
->dev
)->gen
< 4 &&
907 (I915_READ(PIPECONF(crtc
->pipe
)) & (PIPECONF_DOUBLE_WIDE
| PIPECONF_ENABLE
)) != PIPECONF_ENABLE
)
913 static void update_pfit_vscale_ratio(struct intel_overlay
*overlay
)
915 struct drm_device
*dev
= overlay
->dev
;
916 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
917 u32 pfit_control
= I915_READ(PFIT_CONTROL
);
920 /* XXX: This is not the same logic as in the xorg driver, but more in
921 * line with the intel documentation for the i965
923 if (INTEL_INFO(dev
)->gen
>= 4) {
924 /* on i965 use the PGM reg to read out the autoscaler values */
925 ratio
= I915_READ(PFIT_PGM_RATIOS
) >> PFIT_VERT_SCALE_SHIFT_965
;
927 if (pfit_control
& VERT_AUTO_SCALE
)
928 ratio
= I915_READ(PFIT_AUTO_RATIOS
);
930 ratio
= I915_READ(PFIT_PGM_RATIOS
);
931 ratio
>>= PFIT_VERT_SCALE_SHIFT
;
934 overlay
->pfit_vscale_ratio
= ratio
;
937 static int check_overlay_dst(struct intel_overlay
*overlay
,
938 struct drm_intel_overlay_put_image
*rec
)
940 struct drm_display_mode
*mode
= &overlay
->crtc
->base
.mode
;
942 if (rec
->dst_x
< mode
->crtc_hdisplay
&&
943 rec
->dst_x
+ rec
->dst_width
<= mode
->crtc_hdisplay
&&
944 rec
->dst_y
< mode
->crtc_vdisplay
&&
945 rec
->dst_y
+ rec
->dst_height
<= mode
->crtc_vdisplay
)
951 static int check_overlay_scaling(struct put_image_params
*rec
)
955 /* downscaling limit is 8.0 */
956 tmp
= ((rec
->src_scan_h
<< 16) / rec
->dst_h
) >> 16;
959 tmp
= ((rec
->src_scan_w
<< 16) / rec
->dst_w
) >> 16;
966 static int check_overlay_src(struct drm_device
*dev
,
967 struct drm_intel_overlay_put_image
*rec
,
968 struct drm_i915_gem_object
*new_bo
)
970 int uv_hscale
= uv_hsubsampling(rec
->flags
);
971 int uv_vscale
= uv_vsubsampling(rec
->flags
);
976 /* check src dimensions */
977 if (IS_845G(dev
) || IS_I830(dev
)) {
978 if (rec
->src_height
> IMAGE_MAX_HEIGHT_LEGACY
||
979 rec
->src_width
> IMAGE_MAX_WIDTH_LEGACY
)
982 if (rec
->src_height
> IMAGE_MAX_HEIGHT
||
983 rec
->src_width
> IMAGE_MAX_WIDTH
)
987 /* better safe than sorry, use 4 as the maximal subsampling ratio */
988 if (rec
->src_height
< N_VERT_Y_TAPS
*4 ||
989 rec
->src_width
< N_HORIZ_Y_TAPS
*4)
992 /* check alignment constraints */
993 switch (rec
->flags
& I915_OVERLAY_TYPE_MASK
) {
994 case I915_OVERLAY_RGB
:
995 /* not implemented */
998 case I915_OVERLAY_YUV_PACKED
:
1002 depth
= packed_depth_bytes(rec
->flags
);
1006 /* ignore UV planes */
1010 /* check pixel alignment */
1011 if (rec
->offset_Y
% depth
)
1015 case I915_OVERLAY_YUV_PLANAR
:
1016 if (uv_vscale
< 0 || uv_hscale
< 0)
1018 /* no offset restrictions for planar formats */
1025 if (rec
->src_width
% uv_hscale
)
1028 /* stride checking */
1029 if (IS_I830(dev
) || IS_845G(dev
))
1034 if (rec
->stride_Y
& stride_mask
|| rec
->stride_UV
& stride_mask
)
1036 if (IS_GEN4(dev
) && rec
->stride_Y
< 512)
1039 tmp
= (rec
->flags
& I915_OVERLAY_TYPE_MASK
) == I915_OVERLAY_YUV_PLANAR
?
1041 if (rec
->stride_Y
> tmp
|| rec
->stride_UV
> 2*1024)
1044 /* check buffer dimensions */
1045 switch (rec
->flags
& I915_OVERLAY_TYPE_MASK
) {
1046 case I915_OVERLAY_RGB
:
1047 case I915_OVERLAY_YUV_PACKED
:
1048 /* always 4 Y values per depth pixels */
1049 if (packed_width_bytes(rec
->flags
, rec
->src_width
) > rec
->stride_Y
)
1052 tmp
= rec
->stride_Y
*rec
->src_height
;
1053 if (rec
->offset_Y
+ tmp
> new_bo
->base
.size
)
1057 case I915_OVERLAY_YUV_PLANAR
:
1058 if (rec
->src_width
> rec
->stride_Y
)
1060 if (rec
->src_width
/uv_hscale
> rec
->stride_UV
)
1063 tmp
= rec
->stride_Y
* rec
->src_height
;
1064 if (rec
->offset_Y
+ tmp
> new_bo
->base
.size
)
1067 tmp
= rec
->stride_UV
* (rec
->src_height
/ uv_vscale
);
1068 if (rec
->offset_U
+ tmp
> new_bo
->base
.size
||
1069 rec
->offset_V
+ tmp
> new_bo
->base
.size
)
1078 * Return the pipe currently connected to the panel fitter,
1079 * or -1 if the panel fitter is not present or not in use
1081 static int intel_panel_fitter_pipe(struct drm_device
*dev
)
1083 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1086 /* i830 doesn't have a panel fitter */
1090 pfit_control
= I915_READ(PFIT_CONTROL
);
1092 /* See if the panel fitter is in use */
1093 if ((pfit_control
& PFIT_ENABLE
) == 0)
1096 /* 965 can place panel fitter on either pipe */
1098 return (pfit_control
>> 29) & 0x3;
1100 /* older chips can only use pipe 1 */
1104 int intel_overlay_put_image(struct drm_device
*dev
, void *data
,
1105 struct drm_file
*file_priv
)
1107 struct drm_intel_overlay_put_image
*put_image_rec
= data
;
1108 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1109 struct intel_overlay
*overlay
;
1110 struct drm_mode_object
*drmmode_obj
;
1111 struct intel_crtc
*crtc
;
1112 struct drm_i915_gem_object
*new_bo
;
1113 struct put_image_params
*params
;
1117 DRM_ERROR("called with no initialization\n");
1121 overlay
= dev_priv
->overlay
;
1123 DRM_DEBUG("userspace bug: no overlay\n");
1127 if (!(put_image_rec
->flags
& I915_OVERLAY_ENABLE
)) {
1128 mutex_lock(&dev
->mode_config
.mutex
);
1129 mutex_lock(&dev
->struct_mutex
);
1131 ret
= intel_overlay_switch_off(overlay
);
1133 mutex_unlock(&dev
->struct_mutex
);
1134 mutex_unlock(&dev
->mode_config
.mutex
);
1139 params
= kmalloc(sizeof(struct put_image_params
), GFP_KERNEL
);
1143 drmmode_obj
= drm_mode_object_find(dev
, put_image_rec
->crtc_id
,
1144 DRM_MODE_OBJECT_CRTC
);
1149 crtc
= to_intel_crtc(obj_to_crtc(drmmode_obj
));
1151 new_bo
= to_intel_bo(drm_gem_object_lookup(dev
, file_priv
,
1152 put_image_rec
->bo_handle
));
1153 if (&new_bo
->base
== NULL
) {
1158 mutex_lock(&dev
->mode_config
.mutex
);
1159 mutex_lock(&dev
->struct_mutex
);
1161 if (new_bo
->tiling_mode
) {
1162 DRM_ERROR("buffer used for overlay image can not be tiled\n");
1167 ret
= intel_overlay_recover_from_interrupt(overlay
);
1171 if (overlay
->crtc
!= crtc
) {
1172 struct drm_display_mode
*mode
= &crtc
->base
.mode
;
1173 ret
= intel_overlay_switch_off(overlay
);
1177 ret
= check_overlay_possible_on_crtc(overlay
, crtc
);
1181 overlay
->crtc
= crtc
;
1182 crtc
->overlay
= overlay
;
1184 /* line too wide, i.e. one-line-mode */
1185 if (mode
->hdisplay
> 1024 &&
1186 intel_panel_fitter_pipe(dev
) == crtc
->pipe
) {
1187 overlay
->pfit_active
= 1;
1188 update_pfit_vscale_ratio(overlay
);
1190 overlay
->pfit_active
= 0;
1193 ret
= check_overlay_dst(overlay
, put_image_rec
);
1197 if (overlay
->pfit_active
) {
1198 params
->dst_y
= ((((u32
)put_image_rec
->dst_y
) << 12) /
1199 overlay
->pfit_vscale_ratio
);
1200 /* shifting right rounds downwards, so add 1 */
1201 params
->dst_h
= ((((u32
)put_image_rec
->dst_height
) << 12) /
1202 overlay
->pfit_vscale_ratio
) + 1;
1204 params
->dst_y
= put_image_rec
->dst_y
;
1205 params
->dst_h
= put_image_rec
->dst_height
;
1207 params
->dst_x
= put_image_rec
->dst_x
;
1208 params
->dst_w
= put_image_rec
->dst_width
;
1210 params
->src_w
= put_image_rec
->src_width
;
1211 params
->src_h
= put_image_rec
->src_height
;
1212 params
->src_scan_w
= put_image_rec
->src_scan_width
;
1213 params
->src_scan_h
= put_image_rec
->src_scan_height
;
1214 if (params
->src_scan_h
> params
->src_h
||
1215 params
->src_scan_w
> params
->src_w
) {
1220 ret
= check_overlay_src(dev
, put_image_rec
, new_bo
);
1223 params
->format
= put_image_rec
->flags
& ~I915_OVERLAY_FLAGS_MASK
;
1224 params
->stride_Y
= put_image_rec
->stride_Y
;
1225 params
->stride_UV
= put_image_rec
->stride_UV
;
1226 params
->offset_Y
= put_image_rec
->offset_Y
;
1227 params
->offset_U
= put_image_rec
->offset_U
;
1228 params
->offset_V
= put_image_rec
->offset_V
;
1230 /* Check scaling after src size to prevent a divide-by-zero. */
1231 ret
= check_overlay_scaling(params
);
1235 ret
= intel_overlay_do_put_image(overlay
, new_bo
, params
);
1239 mutex_unlock(&dev
->struct_mutex
);
1240 mutex_unlock(&dev
->mode_config
.mutex
);
1247 mutex_unlock(&dev
->struct_mutex
);
1248 mutex_unlock(&dev
->mode_config
.mutex
);
1249 drm_gem_object_unreference_unlocked(&new_bo
->base
);
1256 static void update_reg_attrs(struct intel_overlay
*overlay
,
1257 struct overlay_registers
*regs
)
1259 regs
->OCLRC0
= (overlay
->contrast
<< 18) | (overlay
->brightness
& 0xff);
1260 regs
->OCLRC1
= overlay
->saturation
;
1263 static bool check_gamma_bounds(u32 gamma1
, u32 gamma2
)
1267 if (gamma1
& 0xff000000 || gamma2
& 0xff000000)
1270 for (i
= 0; i
< 3; i
++) {
1271 if (((gamma1
>> i
*8) & 0xff) >= ((gamma2
>> i
*8) & 0xff))
1278 static bool check_gamma5_errata(u32 gamma5
)
1282 for (i
= 0; i
< 3; i
++) {
1283 if (((gamma5
>> i
*8) & 0xff) == 0x80)
1290 static int check_gamma(struct drm_intel_overlay_attrs
*attrs
)
1292 if (!check_gamma_bounds(0, attrs
->gamma0
) ||
1293 !check_gamma_bounds(attrs
->gamma0
, attrs
->gamma1
) ||
1294 !check_gamma_bounds(attrs
->gamma1
, attrs
->gamma2
) ||
1295 !check_gamma_bounds(attrs
->gamma2
, attrs
->gamma3
) ||
1296 !check_gamma_bounds(attrs
->gamma3
, attrs
->gamma4
) ||
1297 !check_gamma_bounds(attrs
->gamma4
, attrs
->gamma5
) ||
1298 !check_gamma_bounds(attrs
->gamma5
, 0x00ffffff))
1301 if (!check_gamma5_errata(attrs
->gamma5
))
1307 int intel_overlay_attrs(struct drm_device
*dev
, void *data
,
1308 struct drm_file
*file_priv
)
1310 struct drm_intel_overlay_attrs
*attrs
= data
;
1311 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1312 struct intel_overlay
*overlay
;
1313 struct overlay_registers
*regs
;
1317 DRM_ERROR("called with no initialization\n");
1321 overlay
= dev_priv
->overlay
;
1323 DRM_DEBUG("userspace bug: no overlay\n");
1327 mutex_lock(&dev
->mode_config
.mutex
);
1328 mutex_lock(&dev
->struct_mutex
);
1331 if (!(attrs
->flags
& I915_OVERLAY_UPDATE_ATTRS
)) {
1332 attrs
->color_key
= overlay
->color_key
;
1333 attrs
->brightness
= overlay
->brightness
;
1334 attrs
->contrast
= overlay
->contrast
;
1335 attrs
->saturation
= overlay
->saturation
;
1337 if (!IS_GEN2(dev
)) {
1338 attrs
->gamma0
= I915_READ(OGAMC0
);
1339 attrs
->gamma1
= I915_READ(OGAMC1
);
1340 attrs
->gamma2
= I915_READ(OGAMC2
);
1341 attrs
->gamma3
= I915_READ(OGAMC3
);
1342 attrs
->gamma4
= I915_READ(OGAMC4
);
1343 attrs
->gamma5
= I915_READ(OGAMC5
);
1346 if (attrs
->brightness
< -128 || attrs
->brightness
> 127)
1348 if (attrs
->contrast
> 255)
1350 if (attrs
->saturation
> 1023)
1353 overlay
->color_key
= attrs
->color_key
;
1354 overlay
->brightness
= attrs
->brightness
;
1355 overlay
->contrast
= attrs
->contrast
;
1356 overlay
->saturation
= attrs
->saturation
;
1358 regs
= intel_overlay_map_regs(overlay
);
1364 update_reg_attrs(overlay
, regs
);
1366 intel_overlay_unmap_regs(overlay
, regs
);
1368 if (attrs
->flags
& I915_OVERLAY_UPDATE_GAMMA
) {
1372 if (overlay
->active
) {
1377 ret
= check_gamma(attrs
);
1381 I915_WRITE(OGAMC0
, attrs
->gamma0
);
1382 I915_WRITE(OGAMC1
, attrs
->gamma1
);
1383 I915_WRITE(OGAMC2
, attrs
->gamma2
);
1384 I915_WRITE(OGAMC3
, attrs
->gamma3
);
1385 I915_WRITE(OGAMC4
, attrs
->gamma4
);
1386 I915_WRITE(OGAMC5
, attrs
->gamma5
);
1392 mutex_unlock(&dev
->struct_mutex
);
1393 mutex_unlock(&dev
->mode_config
.mutex
);
1398 void intel_setup_overlay(struct drm_device
*dev
)
1400 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1401 struct intel_overlay
*overlay
;
1402 struct drm_i915_gem_object
*reg_bo
;
1403 struct overlay_registers
*regs
;
1406 if (!HAS_OVERLAY(dev
))
1409 overlay
= kzalloc(sizeof(struct intel_overlay
), GFP_KERNEL
);
1414 reg_bo
= i915_gem_alloc_object(dev
, PAGE_SIZE
);
1417 overlay
->reg_bo
= reg_bo
;
1419 if (OVERLAY_NEEDS_PHYSICAL(dev
)) {
1420 ret
= i915_gem_attach_phys_object(dev
, reg_bo
,
1421 I915_GEM_PHYS_OVERLAY_REGS
,
1424 DRM_ERROR("failed to attach phys overlay regs\n");
1427 overlay
->flip_addr
= reg_bo
->phys_obj
->handle
->busaddr
;
1429 ret
= i915_gem_object_pin(reg_bo
, PAGE_SIZE
, true);
1431 DRM_ERROR("failed to pin overlay register bo\n");
1434 overlay
->flip_addr
= reg_bo
->gtt_offset
;
1436 ret
= i915_gem_object_set_to_gtt_domain(reg_bo
, true);
1438 DRM_ERROR("failed to move overlay register bo into the GTT\n");
1443 /* init all values */
1444 overlay
->color_key
= 0x0101fe;
1445 overlay
->brightness
= -19;
1446 overlay
->contrast
= 75;
1447 overlay
->saturation
= 146;
1449 regs
= intel_overlay_map_regs(overlay
);
1453 memset(regs
, 0, sizeof(struct overlay_registers
));
1454 update_polyphase_filter(regs
);
1455 update_reg_attrs(overlay
, regs
);
1457 intel_overlay_unmap_regs(overlay
, regs
);
1459 dev_priv
->overlay
= overlay
;
1460 DRM_INFO("initialized overlay support\n");
1464 i915_gem_object_unpin(reg_bo
);
1466 drm_gem_object_unreference(®_bo
->base
);
1472 void intel_cleanup_overlay(struct drm_device
*dev
)
1474 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1476 if (!dev_priv
->overlay
)
1479 /* The bo's should be free'd by the generic code already.
1480 * Furthermore modesetting teardown happens beforehand so the
1481 * hardware should be off already */
1482 BUG_ON(dev_priv
->overlay
->active
);
1484 drm_gem_object_unreference_unlocked(&dev_priv
->overlay
->reg_bo
->base
);
1485 kfree(dev_priv
->overlay
);
1488 #ifdef CONFIG_DEBUG_FS
1489 #include <linux/seq_file.h>
1491 struct intel_overlay_error_state
{
1492 struct overlay_registers regs
;
1498 static struct overlay_registers
*
1499 intel_overlay_map_regs_atomic(struct intel_overlay
*overlay
)
1501 drm_i915_private_t
*dev_priv
= overlay
->dev
->dev_private
;
1502 struct overlay_registers
*regs
;
1504 if (OVERLAY_NEEDS_PHYSICAL(overlay
->dev
))
1505 regs
= overlay
->reg_bo
->phys_obj
->handle
->vaddr
;
1507 regs
= io_mapping_map_atomic_wc(dev_priv
->mm
.gtt_mapping
,
1508 overlay
->reg_bo
->gtt_offset
);
1513 static void intel_overlay_unmap_regs_atomic(struct intel_overlay
*overlay
,
1514 struct overlay_registers
*regs
)
1516 if (!OVERLAY_NEEDS_PHYSICAL(overlay
->dev
))
1517 io_mapping_unmap_atomic(regs
);
1521 struct intel_overlay_error_state
*
1522 intel_overlay_capture_error_state(struct drm_device
*dev
)
1524 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1525 struct intel_overlay
*overlay
= dev_priv
->overlay
;
1526 struct intel_overlay_error_state
*error
;
1527 struct overlay_registers __iomem
*regs
;
1529 if (!overlay
|| !overlay
->active
)
1532 error
= kmalloc(sizeof(*error
), GFP_ATOMIC
);
1536 error
->dovsta
= I915_READ(DOVSTA
);
1537 error
->isr
= I915_READ(ISR
);
1538 if (OVERLAY_NEEDS_PHYSICAL(overlay
->dev
))
1539 error
->base
= (long) overlay
->reg_bo
->phys_obj
->handle
->vaddr
;
1541 error
->base
= (long) overlay
->reg_bo
->gtt_offset
;
1543 regs
= intel_overlay_map_regs_atomic(overlay
);
1547 memcpy_fromio(&error
->regs
, regs
, sizeof(struct overlay_registers
));
1548 intel_overlay_unmap_regs_atomic(overlay
, regs
);
1558 intel_overlay_print_error_state(struct seq_file
*m
, struct intel_overlay_error_state
*error
)
1560 seq_printf(m
, "Overlay, status: 0x%08x, interrupt: 0x%08x\n",
1561 error
->dovsta
, error
->isr
);
1562 seq_printf(m
, " Register file at 0x%08lx:\n",
1565 #define P(x) seq_printf(m, " " #x ": 0x%08x\n", error->regs.x)