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drm/i915: Only pwrite through the GTT if there is space in the aperture
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_overlay.c
1 /*
2 * Copyright © 2009
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Daniel Vetter <daniel@ffwll.ch>
25 *
26 * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c
27 */
28 #include "drmP.h"
29 #include "drm.h"
30 #include "i915_drm.h"
31 #include "i915_drv.h"
32 #include "i915_reg.h"
33 #include "intel_drv.h"
34
35 /* Limits for overlay size. According to intel doc, the real limits are:
36 * Y width: 4095, UV width (planar): 2047, Y height: 2047,
37 * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use
38 * the mininum of both. */
39 #define IMAGE_MAX_WIDTH 2048
40 #define IMAGE_MAX_HEIGHT 2046 /* 2 * 1023 */
41 /* on 830 and 845 these large limits result in the card hanging */
42 #define IMAGE_MAX_WIDTH_LEGACY 1024
43 #define IMAGE_MAX_HEIGHT_LEGACY 1088
44
45 /* overlay register definitions */
46 /* OCMD register */
47 #define OCMD_TILED_SURFACE (0x1<<19)
48 #define OCMD_MIRROR_MASK (0x3<<17)
49 #define OCMD_MIRROR_MODE (0x3<<17)
50 #define OCMD_MIRROR_HORIZONTAL (0x1<<17)
51 #define OCMD_MIRROR_VERTICAL (0x2<<17)
52 #define OCMD_MIRROR_BOTH (0x3<<17)
53 #define OCMD_BYTEORDER_MASK (0x3<<14) /* zero for YUYV or FOURCC YUY2 */
54 #define OCMD_UV_SWAP (0x1<<14) /* YVYU */
55 #define OCMD_Y_SWAP (0x2<<14) /* UYVY or FOURCC UYVY */
56 #define OCMD_Y_AND_UV_SWAP (0x3<<14) /* VYUY */
57 #define OCMD_SOURCE_FORMAT_MASK (0xf<<10)
58 #define OCMD_RGB_888 (0x1<<10) /* not in i965 Intel docs */
59 #define OCMD_RGB_555 (0x2<<10) /* not in i965 Intel docs */
60 #define OCMD_RGB_565 (0x3<<10) /* not in i965 Intel docs */
61 #define OCMD_YUV_422_PACKED (0x8<<10)
62 #define OCMD_YUV_411_PACKED (0x9<<10) /* not in i965 Intel docs */
63 #define OCMD_YUV_420_PLANAR (0xc<<10)
64 #define OCMD_YUV_422_PLANAR (0xd<<10)
65 #define OCMD_YUV_410_PLANAR (0xe<<10) /* also 411 */
66 #define OCMD_TVSYNCFLIP_PARITY (0x1<<9)
67 #define OCMD_TVSYNCFLIP_ENABLE (0x1<<7)
68 #define OCMD_BUF_TYPE_MASK (0x1<<5)
69 #define OCMD_BUF_TYPE_FRAME (0x0<<5)
70 #define OCMD_BUF_TYPE_FIELD (0x1<<5)
71 #define OCMD_TEST_MODE (0x1<<4)
72 #define OCMD_BUFFER_SELECT (0x3<<2)
73 #define OCMD_BUFFER0 (0x0<<2)
74 #define OCMD_BUFFER1 (0x1<<2)
75 #define OCMD_FIELD_SELECT (0x1<<2)
76 #define OCMD_FIELD0 (0x0<<1)
77 #define OCMD_FIELD1 (0x1<<1)
78 #define OCMD_ENABLE (0x1<<0)
79
80 /* OCONFIG register */
81 #define OCONF_PIPE_MASK (0x1<<18)
82 #define OCONF_PIPE_A (0x0<<18)
83 #define OCONF_PIPE_B (0x1<<18)
84 #define OCONF_GAMMA2_ENABLE (0x1<<16)
85 #define OCONF_CSC_MODE_BT601 (0x0<<5)
86 #define OCONF_CSC_MODE_BT709 (0x1<<5)
87 #define OCONF_CSC_BYPASS (0x1<<4)
88 #define OCONF_CC_OUT_8BIT (0x1<<3)
89 #define OCONF_TEST_MODE (0x1<<2)
90 #define OCONF_THREE_LINE_BUFFER (0x1<<0)
91 #define OCONF_TWO_LINE_BUFFER (0x0<<0)
92
93 /* DCLRKM (dst-key) register */
94 #define DST_KEY_ENABLE (0x1<<31)
95 #define CLK_RGB24_MASK 0x0
96 #define CLK_RGB16_MASK 0x070307
97 #define CLK_RGB15_MASK 0x070707
98 #define CLK_RGB8I_MASK 0xffffff
99
100 #define RGB16_TO_COLORKEY(c) \
101 (((c & 0xF800) << 8) | ((c & 0x07E0) << 5) | ((c & 0x001F) << 3))
102 #define RGB15_TO_COLORKEY(c) \
103 (((c & 0x7c00) << 9) | ((c & 0x03E0) << 6) | ((c & 0x001F) << 3))
104
105 /* overlay flip addr flag */
106 #define OFC_UPDATE 0x1
107
108 /* polyphase filter coefficients */
109 #define N_HORIZ_Y_TAPS 5
110 #define N_VERT_Y_TAPS 3
111 #define N_HORIZ_UV_TAPS 3
112 #define N_VERT_UV_TAPS 3
113 #define N_PHASES 17
114 #define MAX_TAPS 5
115
116 /* memory bufferd overlay registers */
117 struct overlay_registers {
118 u32 OBUF_0Y;
119 u32 OBUF_1Y;
120 u32 OBUF_0U;
121 u32 OBUF_0V;
122 u32 OBUF_1U;
123 u32 OBUF_1V;
124 u32 OSTRIDE;
125 u32 YRGB_VPH;
126 u32 UV_VPH;
127 u32 HORZ_PH;
128 u32 INIT_PHS;
129 u32 DWINPOS;
130 u32 DWINSZ;
131 u32 SWIDTH;
132 u32 SWIDTHSW;
133 u32 SHEIGHT;
134 u32 YRGBSCALE;
135 u32 UVSCALE;
136 u32 OCLRC0;
137 u32 OCLRC1;
138 u32 DCLRKV;
139 u32 DCLRKM;
140 u32 SCLRKVH;
141 u32 SCLRKVL;
142 u32 SCLRKEN;
143 u32 OCONFIG;
144 u32 OCMD;
145 u32 RESERVED1; /* 0x6C */
146 u32 OSTART_0Y;
147 u32 OSTART_1Y;
148 u32 OSTART_0U;
149 u32 OSTART_0V;
150 u32 OSTART_1U;
151 u32 OSTART_1V;
152 u32 OTILEOFF_0Y;
153 u32 OTILEOFF_1Y;
154 u32 OTILEOFF_0U;
155 u32 OTILEOFF_0V;
156 u32 OTILEOFF_1U;
157 u32 OTILEOFF_1V;
158 u32 FASTHSCALE; /* 0xA0 */
159 u32 UVSCALEV; /* 0xA4 */
160 u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */
161 u16 Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */
162 u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES];
163 u16 Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */
164 u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES];
165 u16 UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */
166 u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES];
167 u16 UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */
168 u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES];
169 };
170
171 struct intel_overlay {
172 struct drm_device *dev;
173 struct intel_crtc *crtc;
174 struct drm_i915_gem_object *vid_bo;
175 struct drm_i915_gem_object *old_vid_bo;
176 int active;
177 int pfit_active;
178 u32 pfit_vscale_ratio; /* shifted-point number, (1<<12) == 1.0 */
179 u32 color_key;
180 u32 brightness, contrast, saturation;
181 u32 old_xscale, old_yscale;
182 /* register access */
183 u32 flip_addr;
184 struct drm_i915_gem_object *reg_bo;
185 /* flip handling */
186 uint32_t last_flip_req;
187 void (*flip_tail)(struct intel_overlay *);
188 };
189
190 static struct overlay_registers __iomem *
191 intel_overlay_map_regs(struct intel_overlay *overlay)
192 {
193 drm_i915_private_t *dev_priv = overlay->dev->dev_private;
194 struct overlay_registers __iomem *regs;
195
196 if (OVERLAY_NEEDS_PHYSICAL(overlay->dev))
197 regs = (struct overlay_registers __iomem *)overlay->reg_bo->phys_obj->handle->vaddr;
198 else
199 regs = io_mapping_map_wc(dev_priv->mm.gtt_mapping,
200 overlay->reg_bo->gtt_offset);
201
202 return regs;
203 }
204
205 static void intel_overlay_unmap_regs(struct intel_overlay *overlay,
206 struct overlay_registers __iomem *regs)
207 {
208 if (!OVERLAY_NEEDS_PHYSICAL(overlay->dev))
209 io_mapping_unmap(regs);
210 }
211
212 static int intel_overlay_do_wait_request(struct intel_overlay *overlay,
213 struct drm_i915_gem_request *request,
214 void (*tail)(struct intel_overlay *))
215 {
216 struct drm_device *dev = overlay->dev;
217 drm_i915_private_t *dev_priv = dev->dev_private;
218 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
219 int ret;
220
221 BUG_ON(overlay->last_flip_req);
222 ret = i915_add_request(ring, NULL, request);
223 if (ret) {
224 kfree(request);
225 return ret;
226 }
227 overlay->last_flip_req = request->seqno;
228 overlay->flip_tail = tail;
229 ret = i915_wait_seqno(ring, overlay->last_flip_req);
230 if (ret)
231 return ret;
232 i915_gem_retire_requests(dev);
233
234 overlay->last_flip_req = 0;
235 return 0;
236 }
237
238 /* overlay needs to be disable in OCMD reg */
239 static int intel_overlay_on(struct intel_overlay *overlay)
240 {
241 struct drm_device *dev = overlay->dev;
242 struct drm_i915_private *dev_priv = dev->dev_private;
243 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
244 struct drm_i915_gem_request *request;
245 int ret;
246
247 BUG_ON(overlay->active);
248 overlay->active = 1;
249
250 WARN_ON(IS_I830(dev) && !(dev_priv->quirks & QUIRK_PIPEA_FORCE));
251
252 request = kzalloc(sizeof(*request), GFP_KERNEL);
253 if (request == NULL) {
254 ret = -ENOMEM;
255 goto out;
256 }
257
258 ret = intel_ring_begin(ring, 4);
259 if (ret) {
260 kfree(request);
261 goto out;
262 }
263
264 intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_ON);
265 intel_ring_emit(ring, overlay->flip_addr | OFC_UPDATE);
266 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
267 intel_ring_emit(ring, MI_NOOP);
268 intel_ring_advance(ring);
269
270 ret = intel_overlay_do_wait_request(overlay, request, NULL);
271 out:
272 return ret;
273 }
274
275 /* overlay needs to be enabled in OCMD reg */
276 static int intel_overlay_continue(struct intel_overlay *overlay,
277 bool load_polyphase_filter)
278 {
279 struct drm_device *dev = overlay->dev;
280 drm_i915_private_t *dev_priv = dev->dev_private;
281 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
282 struct drm_i915_gem_request *request;
283 u32 flip_addr = overlay->flip_addr;
284 u32 tmp;
285 int ret;
286
287 BUG_ON(!overlay->active);
288
289 request = kzalloc(sizeof(*request), GFP_KERNEL);
290 if (request == NULL)
291 return -ENOMEM;
292
293 if (load_polyphase_filter)
294 flip_addr |= OFC_UPDATE;
295
296 /* check for underruns */
297 tmp = I915_READ(DOVSTA);
298 if (tmp & (1 << 17))
299 DRM_DEBUG("overlay underrun, DOVSTA: %x\n", tmp);
300
301 ret = intel_ring_begin(ring, 2);
302 if (ret) {
303 kfree(request);
304 return ret;
305 }
306 intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
307 intel_ring_emit(ring, flip_addr);
308 intel_ring_advance(ring);
309
310 ret = i915_add_request(ring, NULL, request);
311 if (ret) {
312 kfree(request);
313 return ret;
314 }
315
316 overlay->last_flip_req = request->seqno;
317 return 0;
318 }
319
320 static void intel_overlay_release_old_vid_tail(struct intel_overlay *overlay)
321 {
322 struct drm_i915_gem_object *obj = overlay->old_vid_bo;
323
324 i915_gem_object_unpin(obj);
325 drm_gem_object_unreference(&obj->base);
326
327 overlay->old_vid_bo = NULL;
328 }
329
330 static void intel_overlay_off_tail(struct intel_overlay *overlay)
331 {
332 struct drm_i915_gem_object *obj = overlay->vid_bo;
333
334 /* never have the overlay hw on without showing a frame */
335 BUG_ON(!overlay->vid_bo);
336
337 i915_gem_object_unpin(obj);
338 drm_gem_object_unreference(&obj->base);
339 overlay->vid_bo = NULL;
340
341 overlay->crtc->overlay = NULL;
342 overlay->crtc = NULL;
343 overlay->active = 0;
344 }
345
346 /* overlay needs to be disabled in OCMD reg */
347 static int intel_overlay_off(struct intel_overlay *overlay)
348 {
349 struct drm_device *dev = overlay->dev;
350 struct drm_i915_private *dev_priv = dev->dev_private;
351 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
352 u32 flip_addr = overlay->flip_addr;
353 struct drm_i915_gem_request *request;
354 int ret;
355
356 BUG_ON(!overlay->active);
357
358 request = kzalloc(sizeof(*request), GFP_KERNEL);
359 if (request == NULL)
360 return -ENOMEM;
361
362 /* According to intel docs the overlay hw may hang (when switching
363 * off) without loading the filter coeffs. It is however unclear whether
364 * this applies to the disabling of the overlay or to the switching off
365 * of the hw. Do it in both cases */
366 flip_addr |= OFC_UPDATE;
367
368 ret = intel_ring_begin(ring, 6);
369 if (ret) {
370 kfree(request);
371 return ret;
372 }
373 /* wait for overlay to go idle */
374 intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
375 intel_ring_emit(ring, flip_addr);
376 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
377 /* turn overlay off */
378 intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_OFF);
379 intel_ring_emit(ring, flip_addr);
380 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
381 intel_ring_advance(ring);
382
383 return intel_overlay_do_wait_request(overlay, request,
384 intel_overlay_off_tail);
385 }
386
387 /* recover from an interruption due to a signal
388 * We have to be careful not to repeat work forever an make forward progess. */
389 static int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay)
390 {
391 struct drm_device *dev = overlay->dev;
392 drm_i915_private_t *dev_priv = dev->dev_private;
393 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
394 int ret;
395
396 if (overlay->last_flip_req == 0)
397 return 0;
398
399 ret = i915_wait_seqno(ring, overlay->last_flip_req);
400 if (ret)
401 return ret;
402 i915_gem_retire_requests(dev);
403
404 if (overlay->flip_tail)
405 overlay->flip_tail(overlay);
406
407 overlay->last_flip_req = 0;
408 return 0;
409 }
410
411 /* Wait for pending overlay flip and release old frame.
412 * Needs to be called before the overlay register are changed
413 * via intel_overlay_(un)map_regs
414 */
415 static int intel_overlay_release_old_vid(struct intel_overlay *overlay)
416 {
417 struct drm_device *dev = overlay->dev;
418 drm_i915_private_t *dev_priv = dev->dev_private;
419 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
420 int ret;
421
422 /* Only wait if there is actually an old frame to release to
423 * guarantee forward progress.
424 */
425 if (!overlay->old_vid_bo)
426 return 0;
427
428 if (I915_READ(ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT) {
429 struct drm_i915_gem_request *request;
430
431 /* synchronous slowpath */
432 request = kzalloc(sizeof(*request), GFP_KERNEL);
433 if (request == NULL)
434 return -ENOMEM;
435
436 ret = intel_ring_begin(ring, 2);
437 if (ret) {
438 kfree(request);
439 return ret;
440 }
441
442 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
443 intel_ring_emit(ring, MI_NOOP);
444 intel_ring_advance(ring);
445
446 ret = intel_overlay_do_wait_request(overlay, request,
447 intel_overlay_release_old_vid_tail);
448 if (ret)
449 return ret;
450 }
451
452 intel_overlay_release_old_vid_tail(overlay);
453 return 0;
454 }
455
456 struct put_image_params {
457 int format;
458 short dst_x;
459 short dst_y;
460 short dst_w;
461 short dst_h;
462 short src_w;
463 short src_scan_h;
464 short src_scan_w;
465 short src_h;
466 short stride_Y;
467 short stride_UV;
468 int offset_Y;
469 int offset_U;
470 int offset_V;
471 };
472
473 static int packed_depth_bytes(u32 format)
474 {
475 switch (format & I915_OVERLAY_DEPTH_MASK) {
476 case I915_OVERLAY_YUV422:
477 return 4;
478 case I915_OVERLAY_YUV411:
479 /* return 6; not implemented */
480 default:
481 return -EINVAL;
482 }
483 }
484
485 static int packed_width_bytes(u32 format, short width)
486 {
487 switch (format & I915_OVERLAY_DEPTH_MASK) {
488 case I915_OVERLAY_YUV422:
489 return width << 1;
490 default:
491 return -EINVAL;
492 }
493 }
494
495 static int uv_hsubsampling(u32 format)
496 {
497 switch (format & I915_OVERLAY_DEPTH_MASK) {
498 case I915_OVERLAY_YUV422:
499 case I915_OVERLAY_YUV420:
500 return 2;
501 case I915_OVERLAY_YUV411:
502 case I915_OVERLAY_YUV410:
503 return 4;
504 default:
505 return -EINVAL;
506 }
507 }
508
509 static int uv_vsubsampling(u32 format)
510 {
511 switch (format & I915_OVERLAY_DEPTH_MASK) {
512 case I915_OVERLAY_YUV420:
513 case I915_OVERLAY_YUV410:
514 return 2;
515 case I915_OVERLAY_YUV422:
516 case I915_OVERLAY_YUV411:
517 return 1;
518 default:
519 return -EINVAL;
520 }
521 }
522
523 static u32 calc_swidthsw(struct drm_device *dev, u32 offset, u32 width)
524 {
525 u32 mask, shift, ret;
526 if (IS_GEN2(dev)) {
527 mask = 0x1f;
528 shift = 5;
529 } else {
530 mask = 0x3f;
531 shift = 6;
532 }
533 ret = ((offset + width + mask) >> shift) - (offset >> shift);
534 if (!IS_GEN2(dev))
535 ret <<= 1;
536 ret -= 1;
537 return ret << 2;
538 }
539
540 static const u16 y_static_hcoeffs[N_HORIZ_Y_TAPS * N_PHASES] = {
541 0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0,
542 0x3000, 0xb500, 0x19d0, 0x1880, 0xb440,
543 0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0,
544 0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380,
545 0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320,
546 0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0,
547 0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260,
548 0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200,
549 0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0,
550 0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160,
551 0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120,
552 0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0,
553 0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0,
554 0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060,
555 0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040,
556 0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020,
557 0xb000, 0x3000, 0x0800, 0x3000, 0xb000
558 };
559
560 static const u16 uv_static_hcoeffs[N_HORIZ_UV_TAPS * N_PHASES] = {
561 0x3000, 0x1800, 0x1800, 0xb000, 0x18d0, 0x2e60,
562 0xb000, 0x1990, 0x2ce0, 0xb020, 0x1a68, 0x2b40,
563 0xb040, 0x1b20, 0x29e0, 0xb060, 0x1bd8, 0x2880,
564 0xb080, 0x1c88, 0x3e60, 0xb0a0, 0x1d28, 0x3c00,
565 0xb0c0, 0x1db8, 0x39e0, 0xb0e0, 0x1e40, 0x37e0,
566 0xb100, 0x1eb8, 0x3620, 0xb100, 0x1f18, 0x34a0,
567 0xb100, 0x1f68, 0x3360, 0xb0e0, 0x1fa8, 0x3240,
568 0xb0c0, 0x1fe0, 0x3140, 0xb060, 0x1ff0, 0x30a0,
569 0x3000, 0x0800, 0x3000
570 };
571
572 static void update_polyphase_filter(struct overlay_registers __iomem *regs)
573 {
574 memcpy_toio(regs->Y_HCOEFS, y_static_hcoeffs, sizeof(y_static_hcoeffs));
575 memcpy_toio(regs->UV_HCOEFS, uv_static_hcoeffs,
576 sizeof(uv_static_hcoeffs));
577 }
578
579 static bool update_scaling_factors(struct intel_overlay *overlay,
580 struct overlay_registers __iomem *regs,
581 struct put_image_params *params)
582 {
583 /* fixed point with a 12 bit shift */
584 u32 xscale, yscale, xscale_UV, yscale_UV;
585 #define FP_SHIFT 12
586 #define FRACT_MASK 0xfff
587 bool scale_changed = false;
588 int uv_hscale = uv_hsubsampling(params->format);
589 int uv_vscale = uv_vsubsampling(params->format);
590
591 if (params->dst_w > 1)
592 xscale = ((params->src_scan_w - 1) << FP_SHIFT)
593 /(params->dst_w);
594 else
595 xscale = 1 << FP_SHIFT;
596
597 if (params->dst_h > 1)
598 yscale = ((params->src_scan_h - 1) << FP_SHIFT)
599 /(params->dst_h);
600 else
601 yscale = 1 << FP_SHIFT;
602
603 /*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/
604 xscale_UV = xscale/uv_hscale;
605 yscale_UV = yscale/uv_vscale;
606 /* make the Y scale to UV scale ratio an exact multiply */
607 xscale = xscale_UV * uv_hscale;
608 yscale = yscale_UV * uv_vscale;
609 /*} else {
610 xscale_UV = 0;
611 yscale_UV = 0;
612 }*/
613
614 if (xscale != overlay->old_xscale || yscale != overlay->old_yscale)
615 scale_changed = true;
616 overlay->old_xscale = xscale;
617 overlay->old_yscale = yscale;
618
619 iowrite32(((yscale & FRACT_MASK) << 20) |
620 ((xscale >> FP_SHIFT) << 16) |
621 ((xscale & FRACT_MASK) << 3),
622 &regs->YRGBSCALE);
623
624 iowrite32(((yscale_UV & FRACT_MASK) << 20) |
625 ((xscale_UV >> FP_SHIFT) << 16) |
626 ((xscale_UV & FRACT_MASK) << 3),
627 &regs->UVSCALE);
628
629 iowrite32((((yscale >> FP_SHIFT) << 16) |
630 ((yscale_UV >> FP_SHIFT) << 0)),
631 &regs->UVSCALEV);
632
633 if (scale_changed)
634 update_polyphase_filter(regs);
635
636 return scale_changed;
637 }
638
639 static void update_colorkey(struct intel_overlay *overlay,
640 struct overlay_registers __iomem *regs)
641 {
642 u32 key = overlay->color_key;
643
644 switch (overlay->crtc->base.fb->bits_per_pixel) {
645 case 8:
646 iowrite32(0, &regs->DCLRKV);
647 iowrite32(CLK_RGB8I_MASK | DST_KEY_ENABLE, &regs->DCLRKM);
648 break;
649
650 case 16:
651 if (overlay->crtc->base.fb->depth == 15) {
652 iowrite32(RGB15_TO_COLORKEY(key), &regs->DCLRKV);
653 iowrite32(CLK_RGB15_MASK | DST_KEY_ENABLE,
654 &regs->DCLRKM);
655 } else {
656 iowrite32(RGB16_TO_COLORKEY(key), &regs->DCLRKV);
657 iowrite32(CLK_RGB16_MASK | DST_KEY_ENABLE,
658 &regs->DCLRKM);
659 }
660 break;
661
662 case 24:
663 case 32:
664 iowrite32(key, &regs->DCLRKV);
665 iowrite32(CLK_RGB24_MASK | DST_KEY_ENABLE, &regs->DCLRKM);
666 break;
667 }
668 }
669
670 static u32 overlay_cmd_reg(struct put_image_params *params)
671 {
672 u32 cmd = OCMD_ENABLE | OCMD_BUF_TYPE_FRAME | OCMD_BUFFER0;
673
674 if (params->format & I915_OVERLAY_YUV_PLANAR) {
675 switch (params->format & I915_OVERLAY_DEPTH_MASK) {
676 case I915_OVERLAY_YUV422:
677 cmd |= OCMD_YUV_422_PLANAR;
678 break;
679 case I915_OVERLAY_YUV420:
680 cmd |= OCMD_YUV_420_PLANAR;
681 break;
682 case I915_OVERLAY_YUV411:
683 case I915_OVERLAY_YUV410:
684 cmd |= OCMD_YUV_410_PLANAR;
685 break;
686 }
687 } else { /* YUV packed */
688 switch (params->format & I915_OVERLAY_DEPTH_MASK) {
689 case I915_OVERLAY_YUV422:
690 cmd |= OCMD_YUV_422_PACKED;
691 break;
692 case I915_OVERLAY_YUV411:
693 cmd |= OCMD_YUV_411_PACKED;
694 break;
695 }
696
697 switch (params->format & I915_OVERLAY_SWAP_MASK) {
698 case I915_OVERLAY_NO_SWAP:
699 break;
700 case I915_OVERLAY_UV_SWAP:
701 cmd |= OCMD_UV_SWAP;
702 break;
703 case I915_OVERLAY_Y_SWAP:
704 cmd |= OCMD_Y_SWAP;
705 break;
706 case I915_OVERLAY_Y_AND_UV_SWAP:
707 cmd |= OCMD_Y_AND_UV_SWAP;
708 break;
709 }
710 }
711
712 return cmd;
713 }
714
715 static int intel_overlay_do_put_image(struct intel_overlay *overlay,
716 struct drm_i915_gem_object *new_bo,
717 struct put_image_params *params)
718 {
719 int ret, tmp_width;
720 struct overlay_registers __iomem *regs;
721 bool scale_changed = false;
722 struct drm_device *dev = overlay->dev;
723 u32 swidth, swidthsw, sheight, ostride;
724
725 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
726 BUG_ON(!mutex_is_locked(&dev->mode_config.mutex));
727 BUG_ON(!overlay);
728
729 ret = intel_overlay_release_old_vid(overlay);
730 if (ret != 0)
731 return ret;
732
733 ret = i915_gem_object_pin_to_display_plane(new_bo, 0, NULL);
734 if (ret != 0)
735 return ret;
736
737 ret = i915_gem_object_put_fence(new_bo);
738 if (ret)
739 goto out_unpin;
740
741 if (!overlay->active) {
742 u32 oconfig;
743 regs = intel_overlay_map_regs(overlay);
744 if (!regs) {
745 ret = -ENOMEM;
746 goto out_unpin;
747 }
748 oconfig = OCONF_CC_OUT_8BIT;
749 if (IS_GEN4(overlay->dev))
750 oconfig |= OCONF_CSC_MODE_BT709;
751 oconfig |= overlay->crtc->pipe == 0 ?
752 OCONF_PIPE_A : OCONF_PIPE_B;
753 iowrite32(oconfig, &regs->OCONFIG);
754 intel_overlay_unmap_regs(overlay, regs);
755
756 ret = intel_overlay_on(overlay);
757 if (ret != 0)
758 goto out_unpin;
759 }
760
761 regs = intel_overlay_map_regs(overlay);
762 if (!regs) {
763 ret = -ENOMEM;
764 goto out_unpin;
765 }
766
767 iowrite32((params->dst_y << 16) | params->dst_x, &regs->DWINPOS);
768 iowrite32((params->dst_h << 16) | params->dst_w, &regs->DWINSZ);
769
770 if (params->format & I915_OVERLAY_YUV_PACKED)
771 tmp_width = packed_width_bytes(params->format, params->src_w);
772 else
773 tmp_width = params->src_w;
774
775 swidth = params->src_w;
776 swidthsw = calc_swidthsw(overlay->dev, params->offset_Y, tmp_width);
777 sheight = params->src_h;
778 iowrite32(new_bo->gtt_offset + params->offset_Y, &regs->OBUF_0Y);
779 ostride = params->stride_Y;
780
781 if (params->format & I915_OVERLAY_YUV_PLANAR) {
782 int uv_hscale = uv_hsubsampling(params->format);
783 int uv_vscale = uv_vsubsampling(params->format);
784 u32 tmp_U, tmp_V;
785 swidth |= (params->src_w/uv_hscale) << 16;
786 tmp_U = calc_swidthsw(overlay->dev, params->offset_U,
787 params->src_w/uv_hscale);
788 tmp_V = calc_swidthsw(overlay->dev, params->offset_V,
789 params->src_w/uv_hscale);
790 swidthsw |= max_t(u32, tmp_U, tmp_V) << 16;
791 sheight |= (params->src_h/uv_vscale) << 16;
792 iowrite32(new_bo->gtt_offset + params->offset_U, &regs->OBUF_0U);
793 iowrite32(new_bo->gtt_offset + params->offset_V, &regs->OBUF_0V);
794 ostride |= params->stride_UV << 16;
795 }
796
797 iowrite32(swidth, &regs->SWIDTH);
798 iowrite32(swidthsw, &regs->SWIDTHSW);
799 iowrite32(sheight, &regs->SHEIGHT);
800 iowrite32(ostride, &regs->OSTRIDE);
801
802 scale_changed = update_scaling_factors(overlay, regs, params);
803
804 update_colorkey(overlay, regs);
805
806 iowrite32(overlay_cmd_reg(params), &regs->OCMD);
807
808 intel_overlay_unmap_regs(overlay, regs);
809
810 ret = intel_overlay_continue(overlay, scale_changed);
811 if (ret)
812 goto out_unpin;
813
814 overlay->old_vid_bo = overlay->vid_bo;
815 overlay->vid_bo = new_bo;
816
817 return 0;
818
819 out_unpin:
820 i915_gem_object_unpin(new_bo);
821 return ret;
822 }
823
824 int intel_overlay_switch_off(struct intel_overlay *overlay)
825 {
826 struct overlay_registers __iomem *regs;
827 struct drm_device *dev = overlay->dev;
828 int ret;
829
830 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
831 BUG_ON(!mutex_is_locked(&dev->mode_config.mutex));
832
833 ret = intel_overlay_recover_from_interrupt(overlay);
834 if (ret != 0)
835 return ret;
836
837 if (!overlay->active)
838 return 0;
839
840 ret = intel_overlay_release_old_vid(overlay);
841 if (ret != 0)
842 return ret;
843
844 regs = intel_overlay_map_regs(overlay);
845 iowrite32(0, &regs->OCMD);
846 intel_overlay_unmap_regs(overlay, regs);
847
848 ret = intel_overlay_off(overlay);
849 if (ret != 0)
850 return ret;
851
852 intel_overlay_off_tail(overlay);
853 return 0;
854 }
855
856 static int check_overlay_possible_on_crtc(struct intel_overlay *overlay,
857 struct intel_crtc *crtc)
858 {
859 drm_i915_private_t *dev_priv = overlay->dev->dev_private;
860
861 if (!crtc->active)
862 return -EINVAL;
863
864 /* can't use the overlay with double wide pipe */
865 if (INTEL_INFO(overlay->dev)->gen < 4 &&
866 (I915_READ(PIPECONF(crtc->pipe)) & (PIPECONF_DOUBLE_WIDE | PIPECONF_ENABLE)) != PIPECONF_ENABLE)
867 return -EINVAL;
868
869 return 0;
870 }
871
872 static void update_pfit_vscale_ratio(struct intel_overlay *overlay)
873 {
874 struct drm_device *dev = overlay->dev;
875 drm_i915_private_t *dev_priv = dev->dev_private;
876 u32 pfit_control = I915_READ(PFIT_CONTROL);
877 u32 ratio;
878
879 /* XXX: This is not the same logic as in the xorg driver, but more in
880 * line with the intel documentation for the i965
881 */
882 if (INTEL_INFO(dev)->gen >= 4) {
883 /* on i965 use the PGM reg to read out the autoscaler values */
884 ratio = I915_READ(PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965;
885 } else {
886 if (pfit_control & VERT_AUTO_SCALE)
887 ratio = I915_READ(PFIT_AUTO_RATIOS);
888 else
889 ratio = I915_READ(PFIT_PGM_RATIOS);
890 ratio >>= PFIT_VERT_SCALE_SHIFT;
891 }
892
893 overlay->pfit_vscale_ratio = ratio;
894 }
895
896 static int check_overlay_dst(struct intel_overlay *overlay,
897 struct drm_intel_overlay_put_image *rec)
898 {
899 struct drm_display_mode *mode = &overlay->crtc->base.mode;
900
901 if (rec->dst_x < mode->hdisplay &&
902 rec->dst_x + rec->dst_width <= mode->hdisplay &&
903 rec->dst_y < mode->vdisplay &&
904 rec->dst_y + rec->dst_height <= mode->vdisplay)
905 return 0;
906 else
907 return -EINVAL;
908 }
909
910 static int check_overlay_scaling(struct put_image_params *rec)
911 {
912 u32 tmp;
913
914 /* downscaling limit is 8.0 */
915 tmp = ((rec->src_scan_h << 16) / rec->dst_h) >> 16;
916 if (tmp > 7)
917 return -EINVAL;
918 tmp = ((rec->src_scan_w << 16) / rec->dst_w) >> 16;
919 if (tmp > 7)
920 return -EINVAL;
921
922 return 0;
923 }
924
925 static int check_overlay_src(struct drm_device *dev,
926 struct drm_intel_overlay_put_image *rec,
927 struct drm_i915_gem_object *new_bo)
928 {
929 int uv_hscale = uv_hsubsampling(rec->flags);
930 int uv_vscale = uv_vsubsampling(rec->flags);
931 u32 stride_mask;
932 int depth;
933 u32 tmp;
934
935 /* check src dimensions */
936 if (IS_845G(dev) || IS_I830(dev)) {
937 if (rec->src_height > IMAGE_MAX_HEIGHT_LEGACY ||
938 rec->src_width > IMAGE_MAX_WIDTH_LEGACY)
939 return -EINVAL;
940 } else {
941 if (rec->src_height > IMAGE_MAX_HEIGHT ||
942 rec->src_width > IMAGE_MAX_WIDTH)
943 return -EINVAL;
944 }
945
946 /* better safe than sorry, use 4 as the maximal subsampling ratio */
947 if (rec->src_height < N_VERT_Y_TAPS*4 ||
948 rec->src_width < N_HORIZ_Y_TAPS*4)
949 return -EINVAL;
950
951 /* check alignment constraints */
952 switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
953 case I915_OVERLAY_RGB:
954 /* not implemented */
955 return -EINVAL;
956
957 case I915_OVERLAY_YUV_PACKED:
958 if (uv_vscale != 1)
959 return -EINVAL;
960
961 depth = packed_depth_bytes(rec->flags);
962 if (depth < 0)
963 return depth;
964
965 /* ignore UV planes */
966 rec->stride_UV = 0;
967 rec->offset_U = 0;
968 rec->offset_V = 0;
969 /* check pixel alignment */
970 if (rec->offset_Y % depth)
971 return -EINVAL;
972 break;
973
974 case I915_OVERLAY_YUV_PLANAR:
975 if (uv_vscale < 0 || uv_hscale < 0)
976 return -EINVAL;
977 /* no offset restrictions for planar formats */
978 break;
979
980 default:
981 return -EINVAL;
982 }
983
984 if (rec->src_width % uv_hscale)
985 return -EINVAL;
986
987 /* stride checking */
988 if (IS_I830(dev) || IS_845G(dev))
989 stride_mask = 255;
990 else
991 stride_mask = 63;
992
993 if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask)
994 return -EINVAL;
995 if (IS_GEN4(dev) && rec->stride_Y < 512)
996 return -EINVAL;
997
998 tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ?
999 4096 : 8192;
1000 if (rec->stride_Y > tmp || rec->stride_UV > 2*1024)
1001 return -EINVAL;
1002
1003 /* check buffer dimensions */
1004 switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
1005 case I915_OVERLAY_RGB:
1006 case I915_OVERLAY_YUV_PACKED:
1007 /* always 4 Y values per depth pixels */
1008 if (packed_width_bytes(rec->flags, rec->src_width) > rec->stride_Y)
1009 return -EINVAL;
1010
1011 tmp = rec->stride_Y*rec->src_height;
1012 if (rec->offset_Y + tmp > new_bo->base.size)
1013 return -EINVAL;
1014 break;
1015
1016 case I915_OVERLAY_YUV_PLANAR:
1017 if (rec->src_width > rec->stride_Y)
1018 return -EINVAL;
1019 if (rec->src_width/uv_hscale > rec->stride_UV)
1020 return -EINVAL;
1021
1022 tmp = rec->stride_Y * rec->src_height;
1023 if (rec->offset_Y + tmp > new_bo->base.size)
1024 return -EINVAL;
1025
1026 tmp = rec->stride_UV * (rec->src_height / uv_vscale);
1027 if (rec->offset_U + tmp > new_bo->base.size ||
1028 rec->offset_V + tmp > new_bo->base.size)
1029 return -EINVAL;
1030 break;
1031 }
1032
1033 return 0;
1034 }
1035
1036 /**
1037 * Return the pipe currently connected to the panel fitter,
1038 * or -1 if the panel fitter is not present or not in use
1039 */
1040 static int intel_panel_fitter_pipe(struct drm_device *dev)
1041 {
1042 struct drm_i915_private *dev_priv = dev->dev_private;
1043 u32 pfit_control;
1044
1045 /* i830 doesn't have a panel fitter */
1046 if (IS_I830(dev))
1047 return -1;
1048
1049 pfit_control = I915_READ(PFIT_CONTROL);
1050
1051 /* See if the panel fitter is in use */
1052 if ((pfit_control & PFIT_ENABLE) == 0)
1053 return -1;
1054
1055 /* 965 can place panel fitter on either pipe */
1056 if (IS_GEN4(dev))
1057 return (pfit_control >> 29) & 0x3;
1058
1059 /* older chips can only use pipe 1 */
1060 return 1;
1061 }
1062
1063 int intel_overlay_put_image(struct drm_device *dev, void *data,
1064 struct drm_file *file_priv)
1065 {
1066 struct drm_intel_overlay_put_image *put_image_rec = data;
1067 drm_i915_private_t *dev_priv = dev->dev_private;
1068 struct intel_overlay *overlay;
1069 struct drm_mode_object *drmmode_obj;
1070 struct intel_crtc *crtc;
1071 struct drm_i915_gem_object *new_bo;
1072 struct put_image_params *params;
1073 int ret;
1074
1075 /* No need to check for DRIVER_MODESET - we don't set it up then. */
1076 overlay = dev_priv->overlay;
1077 if (!overlay) {
1078 DRM_DEBUG("userspace bug: no overlay\n");
1079 return -ENODEV;
1080 }
1081
1082 if (!(put_image_rec->flags & I915_OVERLAY_ENABLE)) {
1083 mutex_lock(&dev->mode_config.mutex);
1084 mutex_lock(&dev->struct_mutex);
1085
1086 ret = intel_overlay_switch_off(overlay);
1087
1088 mutex_unlock(&dev->struct_mutex);
1089 mutex_unlock(&dev->mode_config.mutex);
1090
1091 return ret;
1092 }
1093
1094 params = kmalloc(sizeof(struct put_image_params), GFP_KERNEL);
1095 if (!params)
1096 return -ENOMEM;
1097
1098 drmmode_obj = drm_mode_object_find(dev, put_image_rec->crtc_id,
1099 DRM_MODE_OBJECT_CRTC);
1100 if (!drmmode_obj) {
1101 ret = -ENOENT;
1102 goto out_free;
1103 }
1104 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
1105
1106 new_bo = to_intel_bo(drm_gem_object_lookup(dev, file_priv,
1107 put_image_rec->bo_handle));
1108 if (&new_bo->base == NULL) {
1109 ret = -ENOENT;
1110 goto out_free;
1111 }
1112
1113 mutex_lock(&dev->mode_config.mutex);
1114 mutex_lock(&dev->struct_mutex);
1115
1116 if (new_bo->tiling_mode) {
1117 DRM_ERROR("buffer used for overlay image can not be tiled\n");
1118 ret = -EINVAL;
1119 goto out_unlock;
1120 }
1121
1122 ret = intel_overlay_recover_from_interrupt(overlay);
1123 if (ret != 0)
1124 goto out_unlock;
1125
1126 if (overlay->crtc != crtc) {
1127 struct drm_display_mode *mode = &crtc->base.mode;
1128 ret = intel_overlay_switch_off(overlay);
1129 if (ret != 0)
1130 goto out_unlock;
1131
1132 ret = check_overlay_possible_on_crtc(overlay, crtc);
1133 if (ret != 0)
1134 goto out_unlock;
1135
1136 overlay->crtc = crtc;
1137 crtc->overlay = overlay;
1138
1139 /* line too wide, i.e. one-line-mode */
1140 if (mode->hdisplay > 1024 &&
1141 intel_panel_fitter_pipe(dev) == crtc->pipe) {
1142 overlay->pfit_active = 1;
1143 update_pfit_vscale_ratio(overlay);
1144 } else
1145 overlay->pfit_active = 0;
1146 }
1147
1148 ret = check_overlay_dst(overlay, put_image_rec);
1149 if (ret != 0)
1150 goto out_unlock;
1151
1152 if (overlay->pfit_active) {
1153 params->dst_y = ((((u32)put_image_rec->dst_y) << 12) /
1154 overlay->pfit_vscale_ratio);
1155 /* shifting right rounds downwards, so add 1 */
1156 params->dst_h = ((((u32)put_image_rec->dst_height) << 12) /
1157 overlay->pfit_vscale_ratio) + 1;
1158 } else {
1159 params->dst_y = put_image_rec->dst_y;
1160 params->dst_h = put_image_rec->dst_height;
1161 }
1162 params->dst_x = put_image_rec->dst_x;
1163 params->dst_w = put_image_rec->dst_width;
1164
1165 params->src_w = put_image_rec->src_width;
1166 params->src_h = put_image_rec->src_height;
1167 params->src_scan_w = put_image_rec->src_scan_width;
1168 params->src_scan_h = put_image_rec->src_scan_height;
1169 if (params->src_scan_h > params->src_h ||
1170 params->src_scan_w > params->src_w) {
1171 ret = -EINVAL;
1172 goto out_unlock;
1173 }
1174
1175 ret = check_overlay_src(dev, put_image_rec, new_bo);
1176 if (ret != 0)
1177 goto out_unlock;
1178 params->format = put_image_rec->flags & ~I915_OVERLAY_FLAGS_MASK;
1179 params->stride_Y = put_image_rec->stride_Y;
1180 params->stride_UV = put_image_rec->stride_UV;
1181 params->offset_Y = put_image_rec->offset_Y;
1182 params->offset_U = put_image_rec->offset_U;
1183 params->offset_V = put_image_rec->offset_V;
1184
1185 /* Check scaling after src size to prevent a divide-by-zero. */
1186 ret = check_overlay_scaling(params);
1187 if (ret != 0)
1188 goto out_unlock;
1189
1190 ret = intel_overlay_do_put_image(overlay, new_bo, params);
1191 if (ret != 0)
1192 goto out_unlock;
1193
1194 mutex_unlock(&dev->struct_mutex);
1195 mutex_unlock(&dev->mode_config.mutex);
1196
1197 kfree(params);
1198
1199 return 0;
1200
1201 out_unlock:
1202 mutex_unlock(&dev->struct_mutex);
1203 mutex_unlock(&dev->mode_config.mutex);
1204 drm_gem_object_unreference_unlocked(&new_bo->base);
1205 out_free:
1206 kfree(params);
1207
1208 return ret;
1209 }
1210
1211 static void update_reg_attrs(struct intel_overlay *overlay,
1212 struct overlay_registers __iomem *regs)
1213 {
1214 iowrite32((overlay->contrast << 18) | (overlay->brightness & 0xff),
1215 &regs->OCLRC0);
1216 iowrite32(overlay->saturation, &regs->OCLRC1);
1217 }
1218
1219 static bool check_gamma_bounds(u32 gamma1, u32 gamma2)
1220 {
1221 int i;
1222
1223 if (gamma1 & 0xff000000 || gamma2 & 0xff000000)
1224 return false;
1225
1226 for (i = 0; i < 3; i++) {
1227 if (((gamma1 >> i*8) & 0xff) >= ((gamma2 >> i*8) & 0xff))
1228 return false;
1229 }
1230
1231 return true;
1232 }
1233
1234 static bool check_gamma5_errata(u32 gamma5)
1235 {
1236 int i;
1237
1238 for (i = 0; i < 3; i++) {
1239 if (((gamma5 >> i*8) & 0xff) == 0x80)
1240 return false;
1241 }
1242
1243 return true;
1244 }
1245
1246 static int check_gamma(struct drm_intel_overlay_attrs *attrs)
1247 {
1248 if (!check_gamma_bounds(0, attrs->gamma0) ||
1249 !check_gamma_bounds(attrs->gamma0, attrs->gamma1) ||
1250 !check_gamma_bounds(attrs->gamma1, attrs->gamma2) ||
1251 !check_gamma_bounds(attrs->gamma2, attrs->gamma3) ||
1252 !check_gamma_bounds(attrs->gamma3, attrs->gamma4) ||
1253 !check_gamma_bounds(attrs->gamma4, attrs->gamma5) ||
1254 !check_gamma_bounds(attrs->gamma5, 0x00ffffff))
1255 return -EINVAL;
1256
1257 if (!check_gamma5_errata(attrs->gamma5))
1258 return -EINVAL;
1259
1260 return 0;
1261 }
1262
1263 int intel_overlay_attrs(struct drm_device *dev, void *data,
1264 struct drm_file *file_priv)
1265 {
1266 struct drm_intel_overlay_attrs *attrs = data;
1267 drm_i915_private_t *dev_priv = dev->dev_private;
1268 struct intel_overlay *overlay;
1269 struct overlay_registers __iomem *regs;
1270 int ret;
1271
1272 /* No need to check for DRIVER_MODESET - we don't set it up then. */
1273 overlay = dev_priv->overlay;
1274 if (!overlay) {
1275 DRM_DEBUG("userspace bug: no overlay\n");
1276 return -ENODEV;
1277 }
1278
1279 mutex_lock(&dev->mode_config.mutex);
1280 mutex_lock(&dev->struct_mutex);
1281
1282 ret = -EINVAL;
1283 if (!(attrs->flags & I915_OVERLAY_UPDATE_ATTRS)) {
1284 attrs->color_key = overlay->color_key;
1285 attrs->brightness = overlay->brightness;
1286 attrs->contrast = overlay->contrast;
1287 attrs->saturation = overlay->saturation;
1288
1289 if (!IS_GEN2(dev)) {
1290 attrs->gamma0 = I915_READ(OGAMC0);
1291 attrs->gamma1 = I915_READ(OGAMC1);
1292 attrs->gamma2 = I915_READ(OGAMC2);
1293 attrs->gamma3 = I915_READ(OGAMC3);
1294 attrs->gamma4 = I915_READ(OGAMC4);
1295 attrs->gamma5 = I915_READ(OGAMC5);
1296 }
1297 } else {
1298 if (attrs->brightness < -128 || attrs->brightness > 127)
1299 goto out_unlock;
1300 if (attrs->contrast > 255)
1301 goto out_unlock;
1302 if (attrs->saturation > 1023)
1303 goto out_unlock;
1304
1305 overlay->color_key = attrs->color_key;
1306 overlay->brightness = attrs->brightness;
1307 overlay->contrast = attrs->contrast;
1308 overlay->saturation = attrs->saturation;
1309
1310 regs = intel_overlay_map_regs(overlay);
1311 if (!regs) {
1312 ret = -ENOMEM;
1313 goto out_unlock;
1314 }
1315
1316 update_reg_attrs(overlay, regs);
1317
1318 intel_overlay_unmap_regs(overlay, regs);
1319
1320 if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) {
1321 if (IS_GEN2(dev))
1322 goto out_unlock;
1323
1324 if (overlay->active) {
1325 ret = -EBUSY;
1326 goto out_unlock;
1327 }
1328
1329 ret = check_gamma(attrs);
1330 if (ret)
1331 goto out_unlock;
1332
1333 I915_WRITE(OGAMC0, attrs->gamma0);
1334 I915_WRITE(OGAMC1, attrs->gamma1);
1335 I915_WRITE(OGAMC2, attrs->gamma2);
1336 I915_WRITE(OGAMC3, attrs->gamma3);
1337 I915_WRITE(OGAMC4, attrs->gamma4);
1338 I915_WRITE(OGAMC5, attrs->gamma5);
1339 }
1340 }
1341
1342 ret = 0;
1343 out_unlock:
1344 mutex_unlock(&dev->struct_mutex);
1345 mutex_unlock(&dev->mode_config.mutex);
1346
1347 return ret;
1348 }
1349
1350 void intel_setup_overlay(struct drm_device *dev)
1351 {
1352 drm_i915_private_t *dev_priv = dev->dev_private;
1353 struct intel_overlay *overlay;
1354 struct drm_i915_gem_object *reg_bo;
1355 struct overlay_registers __iomem *regs;
1356 int ret;
1357
1358 if (!HAS_OVERLAY(dev))
1359 return;
1360
1361 overlay = kzalloc(sizeof(struct intel_overlay), GFP_KERNEL);
1362 if (!overlay)
1363 return;
1364
1365 mutex_lock(&dev->struct_mutex);
1366 if (WARN_ON(dev_priv->overlay))
1367 goto out_free;
1368
1369 overlay->dev = dev;
1370
1371 reg_bo = i915_gem_alloc_object(dev, PAGE_SIZE);
1372 if (!reg_bo)
1373 goto out_free;
1374 overlay->reg_bo = reg_bo;
1375
1376 if (OVERLAY_NEEDS_PHYSICAL(dev)) {
1377 ret = i915_gem_attach_phys_object(dev, reg_bo,
1378 I915_GEM_PHYS_OVERLAY_REGS,
1379 PAGE_SIZE);
1380 if (ret) {
1381 DRM_ERROR("failed to attach phys overlay regs\n");
1382 goto out_free_bo;
1383 }
1384 overlay->flip_addr = reg_bo->phys_obj->handle->busaddr;
1385 } else {
1386 ret = i915_gem_object_pin(reg_bo, PAGE_SIZE, true, false);
1387 if (ret) {
1388 DRM_ERROR("failed to pin overlay register bo\n");
1389 goto out_free_bo;
1390 }
1391 overlay->flip_addr = reg_bo->gtt_offset;
1392
1393 ret = i915_gem_object_set_to_gtt_domain(reg_bo, true);
1394 if (ret) {
1395 DRM_ERROR("failed to move overlay register bo into the GTT\n");
1396 goto out_unpin_bo;
1397 }
1398 }
1399
1400 /* init all values */
1401 overlay->color_key = 0x0101fe;
1402 overlay->brightness = -19;
1403 overlay->contrast = 75;
1404 overlay->saturation = 146;
1405
1406 regs = intel_overlay_map_regs(overlay);
1407 if (!regs)
1408 goto out_unpin_bo;
1409
1410 memset_io(regs, 0, sizeof(struct overlay_registers));
1411 update_polyphase_filter(regs);
1412 update_reg_attrs(overlay, regs);
1413
1414 intel_overlay_unmap_regs(overlay, regs);
1415
1416 dev_priv->overlay = overlay;
1417 mutex_unlock(&dev->struct_mutex);
1418 DRM_INFO("initialized overlay support\n");
1419 return;
1420
1421 out_unpin_bo:
1422 if (!OVERLAY_NEEDS_PHYSICAL(dev))
1423 i915_gem_object_unpin(reg_bo);
1424 out_free_bo:
1425 drm_gem_object_unreference(&reg_bo->base);
1426 out_free:
1427 mutex_unlock(&dev->struct_mutex);
1428 kfree(overlay);
1429 return;
1430 }
1431
1432 void intel_cleanup_overlay(struct drm_device *dev)
1433 {
1434 drm_i915_private_t *dev_priv = dev->dev_private;
1435
1436 if (!dev_priv->overlay)
1437 return;
1438
1439 /* The bo's should be free'd by the generic code already.
1440 * Furthermore modesetting teardown happens beforehand so the
1441 * hardware should be off already */
1442 BUG_ON(dev_priv->overlay->active);
1443
1444 drm_gem_object_unreference_unlocked(&dev_priv->overlay->reg_bo->base);
1445 kfree(dev_priv->overlay);
1446 }
1447
1448 #ifdef CONFIG_DEBUG_FS
1449 #include <linux/seq_file.h>
1450
1451 struct intel_overlay_error_state {
1452 struct overlay_registers regs;
1453 unsigned long base;
1454 u32 dovsta;
1455 u32 isr;
1456 };
1457
1458 static struct overlay_registers __iomem *
1459 intel_overlay_map_regs_atomic(struct intel_overlay *overlay)
1460 {
1461 drm_i915_private_t *dev_priv = overlay->dev->dev_private;
1462 struct overlay_registers __iomem *regs;
1463
1464 if (OVERLAY_NEEDS_PHYSICAL(overlay->dev))
1465 /* Cast to make sparse happy, but it's wc memory anyway, so
1466 * equivalent to the wc io mapping on X86. */
1467 regs = (struct overlay_registers __iomem *)
1468 overlay->reg_bo->phys_obj->handle->vaddr;
1469 else
1470 regs = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
1471 overlay->reg_bo->gtt_offset);
1472
1473 return regs;
1474 }
1475
1476 static void intel_overlay_unmap_regs_atomic(struct intel_overlay *overlay,
1477 struct overlay_registers __iomem *regs)
1478 {
1479 if (!OVERLAY_NEEDS_PHYSICAL(overlay->dev))
1480 io_mapping_unmap_atomic(regs);
1481 }
1482
1483
1484 struct intel_overlay_error_state *
1485 intel_overlay_capture_error_state(struct drm_device *dev)
1486 {
1487 drm_i915_private_t *dev_priv = dev->dev_private;
1488 struct intel_overlay *overlay = dev_priv->overlay;
1489 struct intel_overlay_error_state *error;
1490 struct overlay_registers __iomem *regs;
1491
1492 if (!overlay || !overlay->active)
1493 return NULL;
1494
1495 error = kmalloc(sizeof(*error), GFP_ATOMIC);
1496 if (error == NULL)
1497 return NULL;
1498
1499 error->dovsta = I915_READ(DOVSTA);
1500 error->isr = I915_READ(ISR);
1501 if (OVERLAY_NEEDS_PHYSICAL(overlay->dev))
1502 error->base = (__force long)overlay->reg_bo->phys_obj->handle->vaddr;
1503 else
1504 error->base = overlay->reg_bo->gtt_offset;
1505
1506 regs = intel_overlay_map_regs_atomic(overlay);
1507 if (!regs)
1508 goto err;
1509
1510 memcpy_fromio(&error->regs, regs, sizeof(struct overlay_registers));
1511 intel_overlay_unmap_regs_atomic(overlay, regs);
1512
1513 return error;
1514
1515 err:
1516 kfree(error);
1517 return NULL;
1518 }
1519
1520 void
1521 intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error)
1522 {
1523 seq_printf(m, "Overlay, status: 0x%08x, interrupt: 0x%08x\n",
1524 error->dovsta, error->isr);
1525 seq_printf(m, " Register file at 0x%08lx:\n",
1526 error->base);
1527
1528 #define P(x) seq_printf(m, " " #x ": 0x%08x\n", error->regs.x)
1529 P(OBUF_0Y);
1530 P(OBUF_1Y);
1531 P(OBUF_0U);
1532 P(OBUF_0V);
1533 P(OBUF_1U);
1534 P(OBUF_1V);
1535 P(OSTRIDE);
1536 P(YRGB_VPH);
1537 P(UV_VPH);
1538 P(HORZ_PH);
1539 P(INIT_PHS);
1540 P(DWINPOS);
1541 P(DWINSZ);
1542 P(SWIDTH);
1543 P(SWIDTHSW);
1544 P(SHEIGHT);
1545 P(YRGBSCALE);
1546 P(UVSCALE);
1547 P(OCLRC0);
1548 P(OCLRC1);
1549 P(DCLRKV);
1550 P(DCLRKM);
1551 P(SCLRKVH);
1552 P(SCLRKVL);
1553 P(SCLRKEN);
1554 P(OCONFIG);
1555 P(OCMD);
1556 P(OSTART_0Y);
1557 P(OSTART_1Y);
1558 P(OSTART_0U);
1559 P(OSTART_0V);
1560 P(OSTART_1U);
1561 P(OSTART_1V);
1562 P(OTILEOFF_0Y);
1563 P(OTILEOFF_1Y);
1564 P(OTILEOFF_0U);
1565 P(OTILEOFF_0V);
1566 P(OTILEOFF_1U);
1567 P(OTILEOFF_1V);
1568 P(FASTHSCALE);
1569 P(UVSCALEV);
1570 #undef P
1571 }
1572 #endif
Linux kernel - Deliverables
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