4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Daniel Vetter <daniel@ffwll.ch>
26 * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c
29 #include <drm/i915_drm.h>
32 #include "intel_drv.h"
34 /* Limits for overlay size. According to intel doc, the real limits are:
35 * Y width: 4095, UV width (planar): 2047, Y height: 2047,
36 * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use
37 * the mininum of both. */
38 #define IMAGE_MAX_WIDTH 2048
39 #define IMAGE_MAX_HEIGHT 2046 /* 2 * 1023 */
40 /* on 830 and 845 these large limits result in the card hanging */
41 #define IMAGE_MAX_WIDTH_LEGACY 1024
42 #define IMAGE_MAX_HEIGHT_LEGACY 1088
44 /* overlay register definitions */
46 #define OCMD_TILED_SURFACE (0x1<<19)
47 #define OCMD_MIRROR_MASK (0x3<<17)
48 #define OCMD_MIRROR_MODE (0x3<<17)
49 #define OCMD_MIRROR_HORIZONTAL (0x1<<17)
50 #define OCMD_MIRROR_VERTICAL (0x2<<17)
51 #define OCMD_MIRROR_BOTH (0x3<<17)
52 #define OCMD_BYTEORDER_MASK (0x3<<14) /* zero for YUYV or FOURCC YUY2 */
53 #define OCMD_UV_SWAP (0x1<<14) /* YVYU */
54 #define OCMD_Y_SWAP (0x2<<14) /* UYVY or FOURCC UYVY */
55 #define OCMD_Y_AND_UV_SWAP (0x3<<14) /* VYUY */
56 #define OCMD_SOURCE_FORMAT_MASK (0xf<<10)
57 #define OCMD_RGB_888 (0x1<<10) /* not in i965 Intel docs */
58 #define OCMD_RGB_555 (0x2<<10) /* not in i965 Intel docs */
59 #define OCMD_RGB_565 (0x3<<10) /* not in i965 Intel docs */
60 #define OCMD_YUV_422_PACKED (0x8<<10)
61 #define OCMD_YUV_411_PACKED (0x9<<10) /* not in i965 Intel docs */
62 #define OCMD_YUV_420_PLANAR (0xc<<10)
63 #define OCMD_YUV_422_PLANAR (0xd<<10)
64 #define OCMD_YUV_410_PLANAR (0xe<<10) /* also 411 */
65 #define OCMD_TVSYNCFLIP_PARITY (0x1<<9)
66 #define OCMD_TVSYNCFLIP_ENABLE (0x1<<7)
67 #define OCMD_BUF_TYPE_MASK (0x1<<5)
68 #define OCMD_BUF_TYPE_FRAME (0x0<<5)
69 #define OCMD_BUF_TYPE_FIELD (0x1<<5)
70 #define OCMD_TEST_MODE (0x1<<4)
71 #define OCMD_BUFFER_SELECT (0x3<<2)
72 #define OCMD_BUFFER0 (0x0<<2)
73 #define OCMD_BUFFER1 (0x1<<2)
74 #define OCMD_FIELD_SELECT (0x1<<2)
75 #define OCMD_FIELD0 (0x0<<1)
76 #define OCMD_FIELD1 (0x1<<1)
77 #define OCMD_ENABLE (0x1<<0)
79 /* OCONFIG register */
80 #define OCONF_PIPE_MASK (0x1<<18)
81 #define OCONF_PIPE_A (0x0<<18)
82 #define OCONF_PIPE_B (0x1<<18)
83 #define OCONF_GAMMA2_ENABLE (0x1<<16)
84 #define OCONF_CSC_MODE_BT601 (0x0<<5)
85 #define OCONF_CSC_MODE_BT709 (0x1<<5)
86 #define OCONF_CSC_BYPASS (0x1<<4)
87 #define OCONF_CC_OUT_8BIT (0x1<<3)
88 #define OCONF_TEST_MODE (0x1<<2)
89 #define OCONF_THREE_LINE_BUFFER (0x1<<0)
90 #define OCONF_TWO_LINE_BUFFER (0x0<<0)
92 /* DCLRKM (dst-key) register */
93 #define DST_KEY_ENABLE (0x1<<31)
94 #define CLK_RGB24_MASK 0x0
95 #define CLK_RGB16_MASK 0x070307
96 #define CLK_RGB15_MASK 0x070707
97 #define CLK_RGB8I_MASK 0xffffff
99 #define RGB16_TO_COLORKEY(c) \
100 (((c & 0xF800) << 8) | ((c & 0x07E0) << 5) | ((c & 0x001F) << 3))
101 #define RGB15_TO_COLORKEY(c) \
102 (((c & 0x7c00) << 9) | ((c & 0x03E0) << 6) | ((c & 0x001F) << 3))
104 /* overlay flip addr flag */
105 #define OFC_UPDATE 0x1
107 /* polyphase filter coefficients */
108 #define N_HORIZ_Y_TAPS 5
109 #define N_VERT_Y_TAPS 3
110 #define N_HORIZ_UV_TAPS 3
111 #define N_VERT_UV_TAPS 3
115 /* memory bufferd overlay registers */
116 struct overlay_registers
{
144 u32 RESERVED1
; /* 0x6C */
157 u32 FASTHSCALE
; /* 0xA0 */
158 u32 UVSCALEV
; /* 0xA4 */
159 u32 RESERVEDC
[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */
160 u16 Y_VCOEFS
[N_VERT_Y_TAPS
* N_PHASES
]; /* 0x200 */
161 u16 RESERVEDD
[0x100 / 2 - N_VERT_Y_TAPS
* N_PHASES
];
162 u16 Y_HCOEFS
[N_HORIZ_Y_TAPS
* N_PHASES
]; /* 0x300 */
163 u16 RESERVEDE
[0x200 / 2 - N_HORIZ_Y_TAPS
* N_PHASES
];
164 u16 UV_VCOEFS
[N_VERT_UV_TAPS
* N_PHASES
]; /* 0x500 */
165 u16 RESERVEDF
[0x100 / 2 - N_VERT_UV_TAPS
* N_PHASES
];
166 u16 UV_HCOEFS
[N_HORIZ_UV_TAPS
* N_PHASES
]; /* 0x600 */
167 u16 RESERVEDG
[0x100 / 2 - N_HORIZ_UV_TAPS
* N_PHASES
];
170 struct intel_overlay
{
171 struct drm_i915_private
*i915
;
172 struct intel_crtc
*crtc
;
173 struct drm_i915_gem_object
*vid_bo
;
174 struct drm_i915_gem_object
*old_vid_bo
;
177 u32 pfit_vscale_ratio
; /* shifted-point number, (1<<12) == 1.0 */
179 u32 color_key_enabled
:1;
180 u32 brightness
, contrast
, saturation
;
181 u32 old_xscale
, old_yscale
;
182 /* register access */
184 struct drm_i915_gem_object
*reg_bo
;
186 struct drm_i915_gem_request
*last_flip_req
;
187 void (*flip_tail
)(struct intel_overlay
*);
190 static struct overlay_registers __iomem
*
191 intel_overlay_map_regs(struct intel_overlay
*overlay
)
193 struct drm_i915_private
*dev_priv
= overlay
->i915
;
194 struct overlay_registers __iomem
*regs
;
196 if (OVERLAY_NEEDS_PHYSICAL(dev_priv
))
197 regs
= (struct overlay_registers __iomem
*)overlay
->reg_bo
->phys_handle
->vaddr
;
199 regs
= io_mapping_map_wc(dev_priv
->ggtt
.mappable
,
206 static void intel_overlay_unmap_regs(struct intel_overlay
*overlay
,
207 struct overlay_registers __iomem
*regs
)
209 if (!OVERLAY_NEEDS_PHYSICAL(overlay
->i915
))
210 io_mapping_unmap(regs
);
213 static int intel_overlay_do_wait_request(struct intel_overlay
*overlay
,
214 struct drm_i915_gem_request
*req
,
215 void (*tail
)(struct intel_overlay
*))
219 WARN_ON(overlay
->last_flip_req
);
220 i915_gem_request_assign(&overlay
->last_flip_req
, req
);
221 i915_add_request(req
);
223 overlay
->flip_tail
= tail
;
224 ret
= i915_wait_request(overlay
->last_flip_req
);
228 i915_gem_request_assign(&overlay
->last_flip_req
, NULL
);
232 /* overlay needs to be disable in OCMD reg */
233 static int intel_overlay_on(struct intel_overlay
*overlay
)
235 struct drm_i915_private
*dev_priv
= overlay
->i915
;
236 struct intel_engine_cs
*engine
= &dev_priv
->engine
[RCS
];
237 struct drm_i915_gem_request
*req
;
238 struct intel_ringbuffer
*ring
;
241 WARN_ON(overlay
->active
);
242 WARN_ON(IS_I830(dev_priv
) && !(dev_priv
->quirks
& QUIRK_PIPEA_FORCE
));
244 req
= i915_gem_request_alloc(engine
, NULL
);
248 ret
= intel_ring_begin(req
, 4);
250 i915_add_request_no_flush(req
);
254 overlay
->active
= true;
257 intel_ring_emit(ring
, MI_OVERLAY_FLIP
| MI_OVERLAY_ON
);
258 intel_ring_emit(ring
, overlay
->flip_addr
| OFC_UPDATE
);
259 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| MI_WAIT_FOR_OVERLAY_FLIP
);
260 intel_ring_emit(ring
, MI_NOOP
);
261 intel_ring_advance(ring
);
263 return intel_overlay_do_wait_request(overlay
, req
, NULL
);
266 /* overlay needs to be enabled in OCMD reg */
267 static int intel_overlay_continue(struct intel_overlay
*overlay
,
268 bool load_polyphase_filter
)
270 struct drm_i915_private
*dev_priv
= overlay
->i915
;
271 struct intel_engine_cs
*engine
= &dev_priv
->engine
[RCS
];
272 struct drm_i915_gem_request
*req
;
273 struct intel_ringbuffer
*ring
;
274 u32 flip_addr
= overlay
->flip_addr
;
278 WARN_ON(!overlay
->active
);
280 if (load_polyphase_filter
)
281 flip_addr
|= OFC_UPDATE
;
283 /* check for underruns */
284 tmp
= I915_READ(DOVSTA
);
286 DRM_DEBUG("overlay underrun, DOVSTA: %x\n", tmp
);
288 req
= i915_gem_request_alloc(engine
, NULL
);
292 ret
= intel_ring_begin(req
, 2);
294 i915_add_request_no_flush(req
);
299 intel_ring_emit(ring
, MI_OVERLAY_FLIP
| MI_OVERLAY_CONTINUE
);
300 intel_ring_emit(ring
, flip_addr
);
301 intel_ring_advance(ring
);
303 WARN_ON(overlay
->last_flip_req
);
304 i915_gem_request_assign(&overlay
->last_flip_req
, req
);
305 i915_add_request(req
);
310 static void intel_overlay_release_old_vid_tail(struct intel_overlay
*overlay
)
312 struct drm_i915_gem_object
*obj
= overlay
->old_vid_bo
;
314 i915_gem_object_ggtt_unpin(obj
);
315 i915_gem_object_put(obj
);
317 overlay
->old_vid_bo
= NULL
;
320 static void intel_overlay_off_tail(struct intel_overlay
*overlay
)
322 struct drm_i915_gem_object
*obj
= overlay
->vid_bo
;
324 /* never have the overlay hw on without showing a frame */
328 i915_gem_object_ggtt_unpin(obj
);
329 i915_gem_object_put(obj
);
330 overlay
->vid_bo
= NULL
;
332 overlay
->crtc
->overlay
= NULL
;
333 overlay
->crtc
= NULL
;
334 overlay
->active
= false;
337 /* overlay needs to be disabled in OCMD reg */
338 static int intel_overlay_off(struct intel_overlay
*overlay
)
340 struct drm_i915_private
*dev_priv
= overlay
->i915
;
341 struct intel_engine_cs
*engine
= &dev_priv
->engine
[RCS
];
342 struct drm_i915_gem_request
*req
;
343 struct intel_ringbuffer
*ring
;
344 u32 flip_addr
= overlay
->flip_addr
;
347 WARN_ON(!overlay
->active
);
349 /* According to intel docs the overlay hw may hang (when switching
350 * off) without loading the filter coeffs. It is however unclear whether
351 * this applies to the disabling of the overlay or to the switching off
352 * of the hw. Do it in both cases */
353 flip_addr
|= OFC_UPDATE
;
355 req
= i915_gem_request_alloc(engine
, NULL
);
359 ret
= intel_ring_begin(req
, 6);
361 i915_add_request_no_flush(req
);
366 /* wait for overlay to go idle */
367 intel_ring_emit(ring
, MI_OVERLAY_FLIP
| MI_OVERLAY_CONTINUE
);
368 intel_ring_emit(ring
, flip_addr
);
369 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| MI_WAIT_FOR_OVERLAY_FLIP
);
370 /* turn overlay off */
371 if (IS_I830(dev_priv
)) {
372 /* Workaround: Don't disable the overlay fully, since otherwise
373 * it dies on the next OVERLAY_ON cmd. */
374 intel_ring_emit(ring
, MI_NOOP
);
375 intel_ring_emit(ring
, MI_NOOP
);
376 intel_ring_emit(ring
, MI_NOOP
);
378 intel_ring_emit(ring
, MI_OVERLAY_FLIP
| MI_OVERLAY_OFF
);
379 intel_ring_emit(ring
, flip_addr
);
380 intel_ring_emit(ring
,
381 MI_WAIT_FOR_EVENT
| MI_WAIT_FOR_OVERLAY_FLIP
);
383 intel_ring_advance(ring
);
385 return intel_overlay_do_wait_request(overlay
, req
, intel_overlay_off_tail
);
388 /* recover from an interruption due to a signal
389 * We have to be careful not to repeat work forever an make forward progess. */
390 static int intel_overlay_recover_from_interrupt(struct intel_overlay
*overlay
)
394 if (overlay
->last_flip_req
== NULL
)
397 ret
= i915_wait_request(overlay
->last_flip_req
);
401 if (overlay
->flip_tail
)
402 overlay
->flip_tail(overlay
);
404 i915_gem_request_assign(&overlay
->last_flip_req
, NULL
);
408 /* Wait for pending overlay flip and release old frame.
409 * Needs to be called before the overlay register are changed
410 * via intel_overlay_(un)map_regs
412 static int intel_overlay_release_old_vid(struct intel_overlay
*overlay
)
414 struct drm_i915_private
*dev_priv
= overlay
->i915
;
415 struct intel_engine_cs
*engine
= &dev_priv
->engine
[RCS
];
418 lockdep_assert_held(&dev_priv
->drm
.struct_mutex
);
420 /* Only wait if there is actually an old frame to release to
421 * guarantee forward progress.
423 if (!overlay
->old_vid_bo
)
426 if (I915_READ(ISR
) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT
) {
427 /* synchronous slowpath */
428 struct drm_i915_gem_request
*req
;
429 struct intel_ringbuffer
*ring
;
431 req
= i915_gem_request_alloc(engine
, NULL
);
435 ret
= intel_ring_begin(req
, 2);
437 i915_add_request_no_flush(req
);
442 intel_ring_emit(ring
,
443 MI_WAIT_FOR_EVENT
| MI_WAIT_FOR_OVERLAY_FLIP
);
444 intel_ring_emit(ring
, MI_NOOP
);
445 intel_ring_advance(ring
);
447 ret
= intel_overlay_do_wait_request(overlay
, req
,
448 intel_overlay_release_old_vid_tail
);
453 intel_overlay_release_old_vid_tail(overlay
);
456 i915_gem_track_fb(overlay
->old_vid_bo
, NULL
,
457 INTEL_FRONTBUFFER_OVERLAY(overlay
->crtc
->pipe
));
461 void intel_overlay_reset(struct drm_i915_private
*dev_priv
)
463 struct intel_overlay
*overlay
= dev_priv
->overlay
;
468 intel_overlay_release_old_vid(overlay
);
470 overlay
->last_flip_req
= NULL
;
471 overlay
->old_xscale
= 0;
472 overlay
->old_yscale
= 0;
473 overlay
->crtc
= NULL
;
474 overlay
->active
= false;
477 struct put_image_params
{
494 static int packed_depth_bytes(u32 format
)
496 switch (format
& I915_OVERLAY_DEPTH_MASK
) {
497 case I915_OVERLAY_YUV422
:
499 case I915_OVERLAY_YUV411
:
500 /* return 6; not implemented */
506 static int packed_width_bytes(u32 format
, short width
)
508 switch (format
& I915_OVERLAY_DEPTH_MASK
) {
509 case I915_OVERLAY_YUV422
:
516 static int uv_hsubsampling(u32 format
)
518 switch (format
& I915_OVERLAY_DEPTH_MASK
) {
519 case I915_OVERLAY_YUV422
:
520 case I915_OVERLAY_YUV420
:
522 case I915_OVERLAY_YUV411
:
523 case I915_OVERLAY_YUV410
:
530 static int uv_vsubsampling(u32 format
)
532 switch (format
& I915_OVERLAY_DEPTH_MASK
) {
533 case I915_OVERLAY_YUV420
:
534 case I915_OVERLAY_YUV410
:
536 case I915_OVERLAY_YUV422
:
537 case I915_OVERLAY_YUV411
:
544 static u32
calc_swidthsw(struct drm_i915_private
*dev_priv
, u32 offset
, u32 width
)
546 u32 mask
, shift
, ret
;
547 if (IS_GEN2(dev_priv
)) {
554 ret
= ((offset
+ width
+ mask
) >> shift
) - (offset
>> shift
);
555 if (!IS_GEN2(dev_priv
))
561 static const u16 y_static_hcoeffs
[N_HORIZ_Y_TAPS
* N_PHASES
] = {
562 0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0,
563 0x3000, 0xb500, 0x19d0, 0x1880, 0xb440,
564 0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0,
565 0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380,
566 0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320,
567 0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0,
568 0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260,
569 0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200,
570 0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0,
571 0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160,
572 0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120,
573 0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0,
574 0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0,
575 0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060,
576 0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040,
577 0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020,
578 0xb000, 0x3000, 0x0800, 0x3000, 0xb000
581 static const u16 uv_static_hcoeffs
[N_HORIZ_UV_TAPS
* N_PHASES
] = {
582 0x3000, 0x1800, 0x1800, 0xb000, 0x18d0, 0x2e60,
583 0xb000, 0x1990, 0x2ce0, 0xb020, 0x1a68, 0x2b40,
584 0xb040, 0x1b20, 0x29e0, 0xb060, 0x1bd8, 0x2880,
585 0xb080, 0x1c88, 0x3e60, 0xb0a0, 0x1d28, 0x3c00,
586 0xb0c0, 0x1db8, 0x39e0, 0xb0e0, 0x1e40, 0x37e0,
587 0xb100, 0x1eb8, 0x3620, 0xb100, 0x1f18, 0x34a0,
588 0xb100, 0x1f68, 0x3360, 0xb0e0, 0x1fa8, 0x3240,
589 0xb0c0, 0x1fe0, 0x3140, 0xb060, 0x1ff0, 0x30a0,
590 0x3000, 0x0800, 0x3000
593 static void update_polyphase_filter(struct overlay_registers __iomem
*regs
)
595 memcpy_toio(regs
->Y_HCOEFS
, y_static_hcoeffs
, sizeof(y_static_hcoeffs
));
596 memcpy_toio(regs
->UV_HCOEFS
, uv_static_hcoeffs
,
597 sizeof(uv_static_hcoeffs
));
600 static bool update_scaling_factors(struct intel_overlay
*overlay
,
601 struct overlay_registers __iomem
*regs
,
602 struct put_image_params
*params
)
604 /* fixed point with a 12 bit shift */
605 u32 xscale
, yscale
, xscale_UV
, yscale_UV
;
607 #define FRACT_MASK 0xfff
608 bool scale_changed
= false;
609 int uv_hscale
= uv_hsubsampling(params
->format
);
610 int uv_vscale
= uv_vsubsampling(params
->format
);
612 if (params
->dst_w
> 1)
613 xscale
= ((params
->src_scan_w
- 1) << FP_SHIFT
)
616 xscale
= 1 << FP_SHIFT
;
618 if (params
->dst_h
> 1)
619 yscale
= ((params
->src_scan_h
- 1) << FP_SHIFT
)
622 yscale
= 1 << FP_SHIFT
;
624 /*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/
625 xscale_UV
= xscale
/uv_hscale
;
626 yscale_UV
= yscale
/uv_vscale
;
627 /* make the Y scale to UV scale ratio an exact multiply */
628 xscale
= xscale_UV
* uv_hscale
;
629 yscale
= yscale_UV
* uv_vscale
;
635 if (xscale
!= overlay
->old_xscale
|| yscale
!= overlay
->old_yscale
)
636 scale_changed
= true;
637 overlay
->old_xscale
= xscale
;
638 overlay
->old_yscale
= yscale
;
640 iowrite32(((yscale
& FRACT_MASK
) << 20) |
641 ((xscale
>> FP_SHIFT
) << 16) |
642 ((xscale
& FRACT_MASK
) << 3),
645 iowrite32(((yscale_UV
& FRACT_MASK
) << 20) |
646 ((xscale_UV
>> FP_SHIFT
) << 16) |
647 ((xscale_UV
& FRACT_MASK
) << 3),
650 iowrite32((((yscale
>> FP_SHIFT
) << 16) |
651 ((yscale_UV
>> FP_SHIFT
) << 0)),
655 update_polyphase_filter(regs
);
657 return scale_changed
;
660 static void update_colorkey(struct intel_overlay
*overlay
,
661 struct overlay_registers __iomem
*regs
)
663 u32 key
= overlay
->color_key
;
667 if (overlay
->color_key_enabled
)
668 flags
|= DST_KEY_ENABLE
;
670 switch (overlay
->crtc
->base
.primary
->fb
->bits_per_pixel
) {
673 flags
|= CLK_RGB8I_MASK
;
677 if (overlay
->crtc
->base
.primary
->fb
->depth
== 15) {
678 key
= RGB15_TO_COLORKEY(key
);
679 flags
|= CLK_RGB15_MASK
;
681 key
= RGB16_TO_COLORKEY(key
);
682 flags
|= CLK_RGB16_MASK
;
688 flags
|= CLK_RGB24_MASK
;
692 iowrite32(key
, ®s
->DCLRKV
);
693 iowrite32(flags
, ®s
->DCLRKM
);
696 static u32
overlay_cmd_reg(struct put_image_params
*params
)
698 u32 cmd
= OCMD_ENABLE
| OCMD_BUF_TYPE_FRAME
| OCMD_BUFFER0
;
700 if (params
->format
& I915_OVERLAY_YUV_PLANAR
) {
701 switch (params
->format
& I915_OVERLAY_DEPTH_MASK
) {
702 case I915_OVERLAY_YUV422
:
703 cmd
|= OCMD_YUV_422_PLANAR
;
705 case I915_OVERLAY_YUV420
:
706 cmd
|= OCMD_YUV_420_PLANAR
;
708 case I915_OVERLAY_YUV411
:
709 case I915_OVERLAY_YUV410
:
710 cmd
|= OCMD_YUV_410_PLANAR
;
713 } else { /* YUV packed */
714 switch (params
->format
& I915_OVERLAY_DEPTH_MASK
) {
715 case I915_OVERLAY_YUV422
:
716 cmd
|= OCMD_YUV_422_PACKED
;
718 case I915_OVERLAY_YUV411
:
719 cmd
|= OCMD_YUV_411_PACKED
;
723 switch (params
->format
& I915_OVERLAY_SWAP_MASK
) {
724 case I915_OVERLAY_NO_SWAP
:
726 case I915_OVERLAY_UV_SWAP
:
729 case I915_OVERLAY_Y_SWAP
:
732 case I915_OVERLAY_Y_AND_UV_SWAP
:
733 cmd
|= OCMD_Y_AND_UV_SWAP
;
741 static int intel_overlay_do_put_image(struct intel_overlay
*overlay
,
742 struct drm_i915_gem_object
*new_bo
,
743 struct put_image_params
*params
)
746 struct overlay_registers __iomem
*regs
;
747 bool scale_changed
= false;
748 struct drm_i915_private
*dev_priv
= overlay
->i915
;
749 u32 swidth
, swidthsw
, sheight
, ostride
;
750 enum pipe pipe
= overlay
->crtc
->pipe
;
752 lockdep_assert_held(&dev_priv
->drm
.struct_mutex
);
753 WARN_ON(!drm_modeset_is_locked(&dev_priv
->drm
.mode_config
.connection_mutex
));
755 ret
= intel_overlay_release_old_vid(overlay
);
759 ret
= i915_gem_object_pin_to_display_plane(new_bo
, 0,
760 &i915_ggtt_view_normal
);
764 ret
= i915_gem_object_put_fence(new_bo
);
768 if (!overlay
->active
) {
770 regs
= intel_overlay_map_regs(overlay
);
775 oconfig
= OCONF_CC_OUT_8BIT
;
776 if (IS_GEN4(dev_priv
))
777 oconfig
|= OCONF_CSC_MODE_BT709
;
778 oconfig
|= pipe
== 0 ?
779 OCONF_PIPE_A
: OCONF_PIPE_B
;
780 iowrite32(oconfig
, ®s
->OCONFIG
);
781 intel_overlay_unmap_regs(overlay
, regs
);
783 ret
= intel_overlay_on(overlay
);
788 regs
= intel_overlay_map_regs(overlay
);
794 iowrite32((params
->dst_y
<< 16) | params
->dst_x
, ®s
->DWINPOS
);
795 iowrite32((params
->dst_h
<< 16) | params
->dst_w
, ®s
->DWINSZ
);
797 if (params
->format
& I915_OVERLAY_YUV_PACKED
)
798 tmp_width
= packed_width_bytes(params
->format
, params
->src_w
);
800 tmp_width
= params
->src_w
;
802 swidth
= params
->src_w
;
803 swidthsw
= calc_swidthsw(dev_priv
, params
->offset_Y
, tmp_width
);
804 sheight
= params
->src_h
;
805 iowrite32(i915_gem_obj_ggtt_offset(new_bo
) + params
->offset_Y
, ®s
->OBUF_0Y
);
806 ostride
= params
->stride_Y
;
808 if (params
->format
& I915_OVERLAY_YUV_PLANAR
) {
809 int uv_hscale
= uv_hsubsampling(params
->format
);
810 int uv_vscale
= uv_vsubsampling(params
->format
);
812 swidth
|= (params
->src_w
/uv_hscale
) << 16;
813 tmp_U
= calc_swidthsw(dev_priv
, params
->offset_U
,
814 params
->src_w
/uv_hscale
);
815 tmp_V
= calc_swidthsw(dev_priv
, params
->offset_V
,
816 params
->src_w
/uv_hscale
);
817 swidthsw
|= max_t(u32
, tmp_U
, tmp_V
) << 16;
818 sheight
|= (params
->src_h
/uv_vscale
) << 16;
819 iowrite32(i915_gem_obj_ggtt_offset(new_bo
) + params
->offset_U
, ®s
->OBUF_0U
);
820 iowrite32(i915_gem_obj_ggtt_offset(new_bo
) + params
->offset_V
, ®s
->OBUF_0V
);
821 ostride
|= params
->stride_UV
<< 16;
824 iowrite32(swidth
, ®s
->SWIDTH
);
825 iowrite32(swidthsw
, ®s
->SWIDTHSW
);
826 iowrite32(sheight
, ®s
->SHEIGHT
);
827 iowrite32(ostride
, ®s
->OSTRIDE
);
829 scale_changed
= update_scaling_factors(overlay
, regs
, params
);
831 update_colorkey(overlay
, regs
);
833 iowrite32(overlay_cmd_reg(params
), ®s
->OCMD
);
835 intel_overlay_unmap_regs(overlay
, regs
);
837 ret
= intel_overlay_continue(overlay
, scale_changed
);
841 i915_gem_track_fb(overlay
->vid_bo
, new_bo
,
842 INTEL_FRONTBUFFER_OVERLAY(pipe
));
844 overlay
->old_vid_bo
= overlay
->vid_bo
;
845 overlay
->vid_bo
= new_bo
;
847 intel_frontbuffer_flip(&dev_priv
->drm
,
848 INTEL_FRONTBUFFER_OVERLAY(pipe
));
853 i915_gem_object_ggtt_unpin(new_bo
);
857 int intel_overlay_switch_off(struct intel_overlay
*overlay
)
859 struct drm_i915_private
*dev_priv
= overlay
->i915
;
860 struct overlay_registers __iomem
*regs
;
863 lockdep_assert_held(&dev_priv
->drm
.struct_mutex
);
864 WARN_ON(!drm_modeset_is_locked(&dev_priv
->drm
.mode_config
.connection_mutex
));
866 ret
= intel_overlay_recover_from_interrupt(overlay
);
870 if (!overlay
->active
)
873 ret
= intel_overlay_release_old_vid(overlay
);
877 regs
= intel_overlay_map_regs(overlay
);
878 iowrite32(0, ®s
->OCMD
);
879 intel_overlay_unmap_regs(overlay
, regs
);
881 ret
= intel_overlay_off(overlay
);
885 intel_overlay_off_tail(overlay
);
889 static int check_overlay_possible_on_crtc(struct intel_overlay
*overlay
,
890 struct intel_crtc
*crtc
)
895 /* can't use the overlay with double wide pipe */
896 if (crtc
->config
->double_wide
)
902 static void update_pfit_vscale_ratio(struct intel_overlay
*overlay
)
904 struct drm_i915_private
*dev_priv
= overlay
->i915
;
905 u32 pfit_control
= I915_READ(PFIT_CONTROL
);
908 /* XXX: This is not the same logic as in the xorg driver, but more in
909 * line with the intel documentation for the i965
911 if (INTEL_GEN(dev_priv
) >= 4) {
912 /* on i965 use the PGM reg to read out the autoscaler values */
913 ratio
= I915_READ(PFIT_PGM_RATIOS
) >> PFIT_VERT_SCALE_SHIFT_965
;
915 if (pfit_control
& VERT_AUTO_SCALE
)
916 ratio
= I915_READ(PFIT_AUTO_RATIOS
);
918 ratio
= I915_READ(PFIT_PGM_RATIOS
);
919 ratio
>>= PFIT_VERT_SCALE_SHIFT
;
922 overlay
->pfit_vscale_ratio
= ratio
;
925 static int check_overlay_dst(struct intel_overlay
*overlay
,
926 struct drm_intel_overlay_put_image
*rec
)
928 struct drm_display_mode
*mode
= &overlay
->crtc
->base
.mode
;
930 if (rec
->dst_x
< mode
->hdisplay
&&
931 rec
->dst_x
+ rec
->dst_width
<= mode
->hdisplay
&&
932 rec
->dst_y
< mode
->vdisplay
&&
933 rec
->dst_y
+ rec
->dst_height
<= mode
->vdisplay
)
939 static int check_overlay_scaling(struct put_image_params
*rec
)
943 /* downscaling limit is 8.0 */
944 tmp
= ((rec
->src_scan_h
<< 16) / rec
->dst_h
) >> 16;
947 tmp
= ((rec
->src_scan_w
<< 16) / rec
->dst_w
) >> 16;
954 static int check_overlay_src(struct drm_i915_private
*dev_priv
,
955 struct drm_intel_overlay_put_image
*rec
,
956 struct drm_i915_gem_object
*new_bo
)
958 int uv_hscale
= uv_hsubsampling(rec
->flags
);
959 int uv_vscale
= uv_vsubsampling(rec
->flags
);
964 /* check src dimensions */
965 if (IS_845G(dev_priv
) || IS_I830(dev_priv
)) {
966 if (rec
->src_height
> IMAGE_MAX_HEIGHT_LEGACY
||
967 rec
->src_width
> IMAGE_MAX_WIDTH_LEGACY
)
970 if (rec
->src_height
> IMAGE_MAX_HEIGHT
||
971 rec
->src_width
> IMAGE_MAX_WIDTH
)
975 /* better safe than sorry, use 4 as the maximal subsampling ratio */
976 if (rec
->src_height
< N_VERT_Y_TAPS
*4 ||
977 rec
->src_width
< N_HORIZ_Y_TAPS
*4)
980 /* check alignment constraints */
981 switch (rec
->flags
& I915_OVERLAY_TYPE_MASK
) {
982 case I915_OVERLAY_RGB
:
983 /* not implemented */
986 case I915_OVERLAY_YUV_PACKED
:
990 depth
= packed_depth_bytes(rec
->flags
);
994 /* ignore UV planes */
998 /* check pixel alignment */
999 if (rec
->offset_Y
% depth
)
1003 case I915_OVERLAY_YUV_PLANAR
:
1004 if (uv_vscale
< 0 || uv_hscale
< 0)
1006 /* no offset restrictions for planar formats */
1013 if (rec
->src_width
% uv_hscale
)
1016 /* stride checking */
1017 if (IS_I830(dev_priv
) || IS_845G(dev_priv
))
1022 if (rec
->stride_Y
& stride_mask
|| rec
->stride_UV
& stride_mask
)
1024 if (IS_GEN4(dev_priv
) && rec
->stride_Y
< 512)
1027 tmp
= (rec
->flags
& I915_OVERLAY_TYPE_MASK
) == I915_OVERLAY_YUV_PLANAR
?
1029 if (rec
->stride_Y
> tmp
|| rec
->stride_UV
> 2*1024)
1032 /* check buffer dimensions */
1033 switch (rec
->flags
& I915_OVERLAY_TYPE_MASK
) {
1034 case I915_OVERLAY_RGB
:
1035 case I915_OVERLAY_YUV_PACKED
:
1036 /* always 4 Y values per depth pixels */
1037 if (packed_width_bytes(rec
->flags
, rec
->src_width
) > rec
->stride_Y
)
1040 tmp
= rec
->stride_Y
*rec
->src_height
;
1041 if (rec
->offset_Y
+ tmp
> new_bo
->base
.size
)
1045 case I915_OVERLAY_YUV_PLANAR
:
1046 if (rec
->src_width
> rec
->stride_Y
)
1048 if (rec
->src_width
/uv_hscale
> rec
->stride_UV
)
1051 tmp
= rec
->stride_Y
* rec
->src_height
;
1052 if (rec
->offset_Y
+ tmp
> new_bo
->base
.size
)
1055 tmp
= rec
->stride_UV
* (rec
->src_height
/ uv_vscale
);
1056 if (rec
->offset_U
+ tmp
> new_bo
->base
.size
||
1057 rec
->offset_V
+ tmp
> new_bo
->base
.size
)
1066 * Return the pipe currently connected to the panel fitter,
1067 * or -1 if the panel fitter is not present or not in use
1069 static int intel_panel_fitter_pipe(struct drm_i915_private
*dev_priv
)
1073 /* i830 doesn't have a panel fitter */
1074 if (INTEL_GEN(dev_priv
) <= 3 &&
1075 (IS_I830(dev_priv
) || !IS_MOBILE(dev_priv
)))
1078 pfit_control
= I915_READ(PFIT_CONTROL
);
1080 /* See if the panel fitter is in use */
1081 if ((pfit_control
& PFIT_ENABLE
) == 0)
1084 /* 965 can place panel fitter on either pipe */
1085 if (IS_GEN4(dev_priv
))
1086 return (pfit_control
>> 29) & 0x3;
1088 /* older chips can only use pipe 1 */
1092 int intel_overlay_put_image_ioctl(struct drm_device
*dev
, void *data
,
1093 struct drm_file
*file_priv
)
1095 struct drm_intel_overlay_put_image
*put_image_rec
= data
;
1096 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1097 struct intel_overlay
*overlay
;
1098 struct drm_crtc
*drmmode_crtc
;
1099 struct intel_crtc
*crtc
;
1100 struct drm_i915_gem_object
*new_bo
;
1101 struct put_image_params
*params
;
1104 overlay
= dev_priv
->overlay
;
1106 DRM_DEBUG("userspace bug: no overlay\n");
1110 if (!(put_image_rec
->flags
& I915_OVERLAY_ENABLE
)) {
1111 drm_modeset_lock_all(dev
);
1112 mutex_lock(&dev
->struct_mutex
);
1114 ret
= intel_overlay_switch_off(overlay
);
1116 mutex_unlock(&dev
->struct_mutex
);
1117 drm_modeset_unlock_all(dev
);
1122 params
= kmalloc(sizeof(*params
), GFP_KERNEL
);
1126 drmmode_crtc
= drm_crtc_find(dev
, put_image_rec
->crtc_id
);
1127 if (!drmmode_crtc
) {
1131 crtc
= to_intel_crtc(drmmode_crtc
);
1133 new_bo
= i915_gem_object_lookup(file_priv
, put_image_rec
->bo_handle
);
1139 drm_modeset_lock_all(dev
);
1140 mutex_lock(&dev
->struct_mutex
);
1142 if (new_bo
->tiling_mode
) {
1143 DRM_DEBUG_KMS("buffer used for overlay image can not be tiled\n");
1148 ret
= intel_overlay_recover_from_interrupt(overlay
);
1152 if (overlay
->crtc
!= crtc
) {
1153 struct drm_display_mode
*mode
= &crtc
->base
.mode
;
1154 ret
= intel_overlay_switch_off(overlay
);
1158 ret
= check_overlay_possible_on_crtc(overlay
, crtc
);
1162 overlay
->crtc
= crtc
;
1163 crtc
->overlay
= overlay
;
1165 /* line too wide, i.e. one-line-mode */
1166 if (mode
->hdisplay
> 1024 &&
1167 intel_panel_fitter_pipe(dev_priv
) == crtc
->pipe
) {
1168 overlay
->pfit_active
= true;
1169 update_pfit_vscale_ratio(overlay
);
1171 overlay
->pfit_active
= false;
1174 ret
= check_overlay_dst(overlay
, put_image_rec
);
1178 if (overlay
->pfit_active
) {
1179 params
->dst_y
= ((((u32
)put_image_rec
->dst_y
) << 12) /
1180 overlay
->pfit_vscale_ratio
);
1181 /* shifting right rounds downwards, so add 1 */
1182 params
->dst_h
= ((((u32
)put_image_rec
->dst_height
) << 12) /
1183 overlay
->pfit_vscale_ratio
) + 1;
1185 params
->dst_y
= put_image_rec
->dst_y
;
1186 params
->dst_h
= put_image_rec
->dst_height
;
1188 params
->dst_x
= put_image_rec
->dst_x
;
1189 params
->dst_w
= put_image_rec
->dst_width
;
1191 params
->src_w
= put_image_rec
->src_width
;
1192 params
->src_h
= put_image_rec
->src_height
;
1193 params
->src_scan_w
= put_image_rec
->src_scan_width
;
1194 params
->src_scan_h
= put_image_rec
->src_scan_height
;
1195 if (params
->src_scan_h
> params
->src_h
||
1196 params
->src_scan_w
> params
->src_w
) {
1201 ret
= check_overlay_src(dev_priv
, put_image_rec
, new_bo
);
1204 params
->format
= put_image_rec
->flags
& ~I915_OVERLAY_FLAGS_MASK
;
1205 params
->stride_Y
= put_image_rec
->stride_Y
;
1206 params
->stride_UV
= put_image_rec
->stride_UV
;
1207 params
->offset_Y
= put_image_rec
->offset_Y
;
1208 params
->offset_U
= put_image_rec
->offset_U
;
1209 params
->offset_V
= put_image_rec
->offset_V
;
1211 /* Check scaling after src size to prevent a divide-by-zero. */
1212 ret
= check_overlay_scaling(params
);
1216 ret
= intel_overlay_do_put_image(overlay
, new_bo
, params
);
1220 mutex_unlock(&dev
->struct_mutex
);
1221 drm_modeset_unlock_all(dev
);
1228 mutex_unlock(&dev
->struct_mutex
);
1229 drm_modeset_unlock_all(dev
);
1230 i915_gem_object_put_unlocked(new_bo
);
1237 static void update_reg_attrs(struct intel_overlay
*overlay
,
1238 struct overlay_registers __iomem
*regs
)
1240 iowrite32((overlay
->contrast
<< 18) | (overlay
->brightness
& 0xff),
1242 iowrite32(overlay
->saturation
, ®s
->OCLRC1
);
1245 static bool check_gamma_bounds(u32 gamma1
, u32 gamma2
)
1249 if (gamma1
& 0xff000000 || gamma2
& 0xff000000)
1252 for (i
= 0; i
< 3; i
++) {
1253 if (((gamma1
>> i
*8) & 0xff) >= ((gamma2
>> i
*8) & 0xff))
1260 static bool check_gamma5_errata(u32 gamma5
)
1264 for (i
= 0; i
< 3; i
++) {
1265 if (((gamma5
>> i
*8) & 0xff) == 0x80)
1272 static int check_gamma(struct drm_intel_overlay_attrs
*attrs
)
1274 if (!check_gamma_bounds(0, attrs
->gamma0
) ||
1275 !check_gamma_bounds(attrs
->gamma0
, attrs
->gamma1
) ||
1276 !check_gamma_bounds(attrs
->gamma1
, attrs
->gamma2
) ||
1277 !check_gamma_bounds(attrs
->gamma2
, attrs
->gamma3
) ||
1278 !check_gamma_bounds(attrs
->gamma3
, attrs
->gamma4
) ||
1279 !check_gamma_bounds(attrs
->gamma4
, attrs
->gamma5
) ||
1280 !check_gamma_bounds(attrs
->gamma5
, 0x00ffffff))
1283 if (!check_gamma5_errata(attrs
->gamma5
))
1289 int intel_overlay_attrs_ioctl(struct drm_device
*dev
, void *data
,
1290 struct drm_file
*file_priv
)
1292 struct drm_intel_overlay_attrs
*attrs
= data
;
1293 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1294 struct intel_overlay
*overlay
;
1295 struct overlay_registers __iomem
*regs
;
1298 overlay
= dev_priv
->overlay
;
1300 DRM_DEBUG("userspace bug: no overlay\n");
1304 drm_modeset_lock_all(dev
);
1305 mutex_lock(&dev
->struct_mutex
);
1308 if (!(attrs
->flags
& I915_OVERLAY_UPDATE_ATTRS
)) {
1309 attrs
->color_key
= overlay
->color_key
;
1310 attrs
->brightness
= overlay
->brightness
;
1311 attrs
->contrast
= overlay
->contrast
;
1312 attrs
->saturation
= overlay
->saturation
;
1314 if (!IS_GEN2(dev_priv
)) {
1315 attrs
->gamma0
= I915_READ(OGAMC0
);
1316 attrs
->gamma1
= I915_READ(OGAMC1
);
1317 attrs
->gamma2
= I915_READ(OGAMC2
);
1318 attrs
->gamma3
= I915_READ(OGAMC3
);
1319 attrs
->gamma4
= I915_READ(OGAMC4
);
1320 attrs
->gamma5
= I915_READ(OGAMC5
);
1323 if (attrs
->brightness
< -128 || attrs
->brightness
> 127)
1325 if (attrs
->contrast
> 255)
1327 if (attrs
->saturation
> 1023)
1330 overlay
->color_key
= attrs
->color_key
;
1331 overlay
->brightness
= attrs
->brightness
;
1332 overlay
->contrast
= attrs
->contrast
;
1333 overlay
->saturation
= attrs
->saturation
;
1335 regs
= intel_overlay_map_regs(overlay
);
1341 update_reg_attrs(overlay
, regs
);
1343 intel_overlay_unmap_regs(overlay
, regs
);
1345 if (attrs
->flags
& I915_OVERLAY_UPDATE_GAMMA
) {
1346 if (IS_GEN2(dev_priv
))
1349 if (overlay
->active
) {
1354 ret
= check_gamma(attrs
);
1358 I915_WRITE(OGAMC0
, attrs
->gamma0
);
1359 I915_WRITE(OGAMC1
, attrs
->gamma1
);
1360 I915_WRITE(OGAMC2
, attrs
->gamma2
);
1361 I915_WRITE(OGAMC3
, attrs
->gamma3
);
1362 I915_WRITE(OGAMC4
, attrs
->gamma4
);
1363 I915_WRITE(OGAMC5
, attrs
->gamma5
);
1366 overlay
->color_key_enabled
= (attrs
->flags
& I915_OVERLAY_DISABLE_DEST_COLORKEY
) == 0;
1370 mutex_unlock(&dev
->struct_mutex
);
1371 drm_modeset_unlock_all(dev
);
1376 void intel_setup_overlay(struct drm_i915_private
*dev_priv
)
1378 struct intel_overlay
*overlay
;
1379 struct drm_i915_gem_object
*reg_bo
;
1380 struct overlay_registers __iomem
*regs
;
1383 if (!HAS_OVERLAY(dev_priv
))
1386 overlay
= kzalloc(sizeof(*overlay
), GFP_KERNEL
);
1390 mutex_lock(&dev_priv
->drm
.struct_mutex
);
1391 if (WARN_ON(dev_priv
->overlay
))
1394 overlay
->i915
= dev_priv
;
1397 if (!OVERLAY_NEEDS_PHYSICAL(dev_priv
))
1398 reg_bo
= i915_gem_object_create_stolen(&dev_priv
->drm
,
1401 reg_bo
= i915_gem_object_create(&dev_priv
->drm
, PAGE_SIZE
);
1404 overlay
->reg_bo
= reg_bo
;
1406 if (OVERLAY_NEEDS_PHYSICAL(dev_priv
)) {
1407 ret
= i915_gem_object_attach_phys(reg_bo
, PAGE_SIZE
);
1409 DRM_ERROR("failed to attach phys overlay regs\n");
1412 overlay
->flip_addr
= reg_bo
->phys_handle
->busaddr
;
1414 ret
= i915_gem_obj_ggtt_pin(reg_bo
, PAGE_SIZE
, PIN_MAPPABLE
);
1416 DRM_ERROR("failed to pin overlay register bo\n");
1419 overlay
->flip_addr
= i915_gem_obj_ggtt_offset(reg_bo
);
1421 ret
= i915_gem_object_set_to_gtt_domain(reg_bo
, true);
1423 DRM_ERROR("failed to move overlay register bo into the GTT\n");
1428 /* init all values */
1429 overlay
->color_key
= 0x0101fe;
1430 overlay
->color_key_enabled
= true;
1431 overlay
->brightness
= -19;
1432 overlay
->contrast
= 75;
1433 overlay
->saturation
= 146;
1435 regs
= intel_overlay_map_regs(overlay
);
1439 memset_io(regs
, 0, sizeof(struct overlay_registers
));
1440 update_polyphase_filter(regs
);
1441 update_reg_attrs(overlay
, regs
);
1443 intel_overlay_unmap_regs(overlay
, regs
);
1445 dev_priv
->overlay
= overlay
;
1446 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
1447 DRM_INFO("initialized overlay support\n");
1451 if (!OVERLAY_NEEDS_PHYSICAL(dev_priv
))
1452 i915_gem_object_ggtt_unpin(reg_bo
);
1454 i915_gem_object_put(reg_bo
);
1456 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
1461 void intel_cleanup_overlay(struct drm_i915_private
*dev_priv
)
1463 if (!dev_priv
->overlay
)
1466 /* The bo's should be free'd by the generic code already.
1467 * Furthermore modesetting teardown happens beforehand so the
1468 * hardware should be off already */
1469 WARN_ON(dev_priv
->overlay
->active
);
1471 i915_gem_object_put_unlocked(dev_priv
->overlay
->reg_bo
);
1472 kfree(dev_priv
->overlay
);
1475 struct intel_overlay_error_state
{
1476 struct overlay_registers regs
;
1482 static struct overlay_registers __iomem
*
1483 intel_overlay_map_regs_atomic(struct intel_overlay
*overlay
)
1485 struct drm_i915_private
*dev_priv
= overlay
->i915
;
1486 struct overlay_registers __iomem
*regs
;
1488 if (OVERLAY_NEEDS_PHYSICAL(dev_priv
))
1489 /* Cast to make sparse happy, but it's wc memory anyway, so
1490 * equivalent to the wc io mapping on X86. */
1491 regs
= (struct overlay_registers __iomem
*)
1492 overlay
->reg_bo
->phys_handle
->vaddr
;
1494 regs
= io_mapping_map_atomic_wc(dev_priv
->ggtt
.mappable
,
1495 overlay
->flip_addr
);
1500 static void intel_overlay_unmap_regs_atomic(struct intel_overlay
*overlay
,
1501 struct overlay_registers __iomem
*regs
)
1503 if (!OVERLAY_NEEDS_PHYSICAL(overlay
->i915
))
1504 io_mapping_unmap_atomic(regs
);
1507 struct intel_overlay_error_state
*
1508 intel_overlay_capture_error_state(struct drm_i915_private
*dev_priv
)
1510 struct intel_overlay
*overlay
= dev_priv
->overlay
;
1511 struct intel_overlay_error_state
*error
;
1512 struct overlay_registers __iomem
*regs
;
1514 if (!overlay
|| !overlay
->active
)
1517 error
= kmalloc(sizeof(*error
), GFP_ATOMIC
);
1521 error
->dovsta
= I915_READ(DOVSTA
);
1522 error
->isr
= I915_READ(ISR
);
1523 error
->base
= overlay
->flip_addr
;
1525 regs
= intel_overlay_map_regs_atomic(overlay
);
1529 memcpy_fromio(&error
->regs
, regs
, sizeof(struct overlay_registers
));
1530 intel_overlay_unmap_regs_atomic(overlay
, regs
);
1540 intel_overlay_print_error_state(struct drm_i915_error_state_buf
*m
,
1541 struct intel_overlay_error_state
*error
)
1543 i915_error_printf(m
, "Overlay, status: 0x%08x, interrupt: 0x%08x\n",
1544 error
->dovsta
, error
->isr
);
1545 i915_error_printf(m
, " Register file at 0x%08lx:\n",
1548 #define P(x) i915_error_printf(m, " " #x ": 0x%08x\n", error->regs.x)