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043c5a8eae20f9c0513bd2aa1b045d29c0abd9f8
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_pm.c
1 /*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28 #include <linux/cpufreq.h>
29 #include "i915_drv.h"
30 #include "intel_drv.h"
31 #include "../../../platform/x86/intel_ips.h"
32 #include <linux/module.h>
33 #include <linux/vgaarb.h>
34 #include <drm/i915_powerwell.h>
35 #include <linux/pm_runtime.h>
36
37 /**
38 * RC6 is a special power stage which allows the GPU to enter an very
39 * low-voltage mode when idle, using down to 0V while at this stage. This
40 * stage is entered automatically when the GPU is idle when RC6 support is
41 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
42 *
43 * There are different RC6 modes available in Intel GPU, which differentiate
44 * among each other with the latency required to enter and leave RC6 and
45 * voltage consumed by the GPU in different states.
46 *
47 * The combination of the following flags define which states GPU is allowed
48 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
49 * RC6pp is deepest RC6. Their support by hardware varies according to the
50 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
51 * which brings the most power savings; deeper states save more power, but
52 * require higher latency to switch to and wake up.
53 */
54 #define INTEL_RC6_ENABLE (1<<0)
55 #define INTEL_RC6p_ENABLE (1<<1)
56 #define INTEL_RC6pp_ENABLE (1<<2)
57
58 /* FBC, or Frame Buffer Compression, is a technique employed to compress the
59 * framebuffer contents in-memory, aiming at reducing the required bandwidth
60 * during in-memory transfers and, therefore, reduce the power packet.
61 *
62 * The benefits of FBC are mostly visible with solid backgrounds and
63 * variation-less patterns.
64 *
65 * FBC-related functionality can be enabled by the means of the
66 * i915.i915_enable_fbc parameter
67 */
68
69 static void gen9_init_clock_gating(struct drm_device *dev)
70 {
71 struct drm_i915_private *dev_priv = dev->dev_private;
72
73 /*
74 * WaDisableSDEUnitClockGating:skl
75 * This seems to be a pre-production w/a.
76 */
77 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
78 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
79
80 /*
81 * WaDisableDgMirrorFixInHalfSliceChicken5:skl
82 * This is a pre-production w/a.
83 */
84 I915_WRITE(GEN9_HALF_SLICE_CHICKEN5,
85 I915_READ(GEN9_HALF_SLICE_CHICKEN5) &
86 ~GEN9_DG_MIRROR_FIX_ENABLE);
87
88 /* Wa4x4STCOptimizationDisable:skl */
89 I915_WRITE(CACHE_MODE_1,
90 _MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE));
91 }
92
93 static void i8xx_disable_fbc(struct drm_device *dev)
94 {
95 struct drm_i915_private *dev_priv = dev->dev_private;
96 u32 fbc_ctl;
97
98 dev_priv->fbc.enabled = false;
99
100 /* Disable compression */
101 fbc_ctl = I915_READ(FBC_CONTROL);
102 if ((fbc_ctl & FBC_CTL_EN) == 0)
103 return;
104
105 fbc_ctl &= ~FBC_CTL_EN;
106 I915_WRITE(FBC_CONTROL, fbc_ctl);
107
108 /* Wait for compressing bit to clear */
109 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
110 DRM_DEBUG_KMS("FBC idle timed out\n");
111 return;
112 }
113
114 DRM_DEBUG_KMS("disabled FBC\n");
115 }
116
117 static void i8xx_enable_fbc(struct drm_crtc *crtc)
118 {
119 struct drm_device *dev = crtc->dev;
120 struct drm_i915_private *dev_priv = dev->dev_private;
121 struct drm_framebuffer *fb = crtc->primary->fb;
122 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
123 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
124 int cfb_pitch;
125 int i;
126 u32 fbc_ctl;
127
128 dev_priv->fbc.enabled = true;
129
130 cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
131 if (fb->pitches[0] < cfb_pitch)
132 cfb_pitch = fb->pitches[0];
133
134 /* FBC_CTL wants 32B or 64B units */
135 if (IS_GEN2(dev))
136 cfb_pitch = (cfb_pitch / 32) - 1;
137 else
138 cfb_pitch = (cfb_pitch / 64) - 1;
139
140 /* Clear old tags */
141 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
142 I915_WRITE(FBC_TAG + (i * 4), 0);
143
144 if (IS_GEN4(dev)) {
145 u32 fbc_ctl2;
146
147 /* Set it up... */
148 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
149 fbc_ctl2 |= FBC_CTL_PLANE(intel_crtc->plane);
150 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
151 I915_WRITE(FBC_FENCE_OFF, crtc->y);
152 }
153
154 /* enable it... */
155 fbc_ctl = I915_READ(FBC_CONTROL);
156 fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT;
157 fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
158 if (IS_I945GM(dev))
159 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
160 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
161 fbc_ctl |= obj->fence_reg;
162 I915_WRITE(FBC_CONTROL, fbc_ctl);
163
164 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c\n",
165 cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
166 }
167
168 static bool i8xx_fbc_enabled(struct drm_device *dev)
169 {
170 struct drm_i915_private *dev_priv = dev->dev_private;
171
172 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
173 }
174
175 static void g4x_enable_fbc(struct drm_crtc *crtc)
176 {
177 struct drm_device *dev = crtc->dev;
178 struct drm_i915_private *dev_priv = dev->dev_private;
179 struct drm_framebuffer *fb = crtc->primary->fb;
180 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
181 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
182 u32 dpfc_ctl;
183
184 dev_priv->fbc.enabled = true;
185
186 dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane) | DPFC_SR_EN;
187 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
188 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
189 else
190 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
191 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
192
193 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
194
195 /* enable it... */
196 I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
197
198 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
199 }
200
201 static void g4x_disable_fbc(struct drm_device *dev)
202 {
203 struct drm_i915_private *dev_priv = dev->dev_private;
204 u32 dpfc_ctl;
205
206 dev_priv->fbc.enabled = false;
207
208 /* Disable compression */
209 dpfc_ctl = I915_READ(DPFC_CONTROL);
210 if (dpfc_ctl & DPFC_CTL_EN) {
211 dpfc_ctl &= ~DPFC_CTL_EN;
212 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
213
214 DRM_DEBUG_KMS("disabled FBC\n");
215 }
216 }
217
218 static bool g4x_fbc_enabled(struct drm_device *dev)
219 {
220 struct drm_i915_private *dev_priv = dev->dev_private;
221
222 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
223 }
224
225 static void sandybridge_blit_fbc_update(struct drm_device *dev)
226 {
227 struct drm_i915_private *dev_priv = dev->dev_private;
228 u32 blt_ecoskpd;
229
230 /* Make sure blitter notifies FBC of writes */
231
232 /* Blitter is part of Media powerwell on VLV. No impact of
233 * his param in other platforms for now */
234 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_MEDIA);
235
236 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
237 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
238 GEN6_BLITTER_LOCK_SHIFT;
239 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
240 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
241 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
242 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
243 GEN6_BLITTER_LOCK_SHIFT);
244 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
245 POSTING_READ(GEN6_BLITTER_ECOSKPD);
246
247 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_MEDIA);
248 }
249
250 static void ironlake_enable_fbc(struct drm_crtc *crtc)
251 {
252 struct drm_device *dev = crtc->dev;
253 struct drm_i915_private *dev_priv = dev->dev_private;
254 struct drm_framebuffer *fb = crtc->primary->fb;
255 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
256 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
257 u32 dpfc_ctl;
258
259 dev_priv->fbc.enabled = true;
260
261 dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane);
262 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
263 dev_priv->fbc.threshold++;
264
265 switch (dev_priv->fbc.threshold) {
266 case 4:
267 case 3:
268 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
269 break;
270 case 2:
271 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
272 break;
273 case 1:
274 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
275 break;
276 }
277 dpfc_ctl |= DPFC_CTL_FENCE_EN;
278 if (IS_GEN5(dev))
279 dpfc_ctl |= obj->fence_reg;
280
281 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
282 I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
283 /* enable it... */
284 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
285
286 if (IS_GEN6(dev)) {
287 I915_WRITE(SNB_DPFC_CTL_SA,
288 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
289 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
290 sandybridge_blit_fbc_update(dev);
291 }
292
293 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
294 }
295
296 static void ironlake_disable_fbc(struct drm_device *dev)
297 {
298 struct drm_i915_private *dev_priv = dev->dev_private;
299 u32 dpfc_ctl;
300
301 dev_priv->fbc.enabled = false;
302
303 /* Disable compression */
304 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
305 if (dpfc_ctl & DPFC_CTL_EN) {
306 dpfc_ctl &= ~DPFC_CTL_EN;
307 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
308
309 DRM_DEBUG_KMS("disabled FBC\n");
310 }
311 }
312
313 static bool ironlake_fbc_enabled(struct drm_device *dev)
314 {
315 struct drm_i915_private *dev_priv = dev->dev_private;
316
317 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
318 }
319
320 static void gen7_enable_fbc(struct drm_crtc *crtc)
321 {
322 struct drm_device *dev = crtc->dev;
323 struct drm_i915_private *dev_priv = dev->dev_private;
324 struct drm_framebuffer *fb = crtc->primary->fb;
325 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
326 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
327 u32 dpfc_ctl;
328
329 dev_priv->fbc.enabled = true;
330
331 dpfc_ctl = IVB_DPFC_CTL_PLANE(intel_crtc->plane);
332 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
333 dev_priv->fbc.threshold++;
334
335 switch (dev_priv->fbc.threshold) {
336 case 4:
337 case 3:
338 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
339 break;
340 case 2:
341 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
342 break;
343 case 1:
344 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
345 break;
346 }
347
348 dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
349
350 if (dev_priv->fbc.false_color)
351 dpfc_ctl |= FBC_CTL_FALSE_COLOR;
352
353 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
354
355 if (IS_IVYBRIDGE(dev)) {
356 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
357 I915_WRITE(ILK_DISPLAY_CHICKEN1,
358 I915_READ(ILK_DISPLAY_CHICKEN1) |
359 ILK_FBCQ_DIS);
360 } else {
361 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
362 I915_WRITE(CHICKEN_PIPESL_1(intel_crtc->pipe),
363 I915_READ(CHICKEN_PIPESL_1(intel_crtc->pipe)) |
364 HSW_FBCQ_DIS);
365 }
366
367 I915_WRITE(SNB_DPFC_CTL_SA,
368 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
369 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
370
371 sandybridge_blit_fbc_update(dev);
372
373 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
374 }
375
376 bool intel_fbc_enabled(struct drm_device *dev)
377 {
378 struct drm_i915_private *dev_priv = dev->dev_private;
379
380 return dev_priv->fbc.enabled;
381 }
382
383 void bdw_fbc_sw_flush(struct drm_device *dev, u32 value)
384 {
385 struct drm_i915_private *dev_priv = dev->dev_private;
386
387 if (!IS_GEN8(dev))
388 return;
389
390 if (!intel_fbc_enabled(dev))
391 return;
392
393 I915_WRITE(MSG_FBC_REND_STATE, value);
394 }
395
396 static void intel_fbc_work_fn(struct work_struct *__work)
397 {
398 struct intel_fbc_work *work =
399 container_of(to_delayed_work(__work),
400 struct intel_fbc_work, work);
401 struct drm_device *dev = work->crtc->dev;
402 struct drm_i915_private *dev_priv = dev->dev_private;
403
404 mutex_lock(&dev->struct_mutex);
405 if (work == dev_priv->fbc.fbc_work) {
406 /* Double check that we haven't switched fb without cancelling
407 * the prior work.
408 */
409 if (work->crtc->primary->fb == work->fb) {
410 dev_priv->display.enable_fbc(work->crtc);
411
412 dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;
413 dev_priv->fbc.fb_id = work->crtc->primary->fb->base.id;
414 dev_priv->fbc.y = work->crtc->y;
415 }
416
417 dev_priv->fbc.fbc_work = NULL;
418 }
419 mutex_unlock(&dev->struct_mutex);
420
421 kfree(work);
422 }
423
424 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
425 {
426 if (dev_priv->fbc.fbc_work == NULL)
427 return;
428
429 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
430
431 /* Synchronisation is provided by struct_mutex and checking of
432 * dev_priv->fbc.fbc_work, so we can perform the cancellation
433 * entirely asynchronously.
434 */
435 if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
436 /* tasklet was killed before being run, clean up */
437 kfree(dev_priv->fbc.fbc_work);
438
439 /* Mark the work as no longer wanted so that if it does
440 * wake-up (because the work was already running and waiting
441 * for our mutex), it will discover that is no longer
442 * necessary to run.
443 */
444 dev_priv->fbc.fbc_work = NULL;
445 }
446
447 static void intel_enable_fbc(struct drm_crtc *crtc)
448 {
449 struct intel_fbc_work *work;
450 struct drm_device *dev = crtc->dev;
451 struct drm_i915_private *dev_priv = dev->dev_private;
452
453 if (!dev_priv->display.enable_fbc)
454 return;
455
456 intel_cancel_fbc_work(dev_priv);
457
458 work = kzalloc(sizeof(*work), GFP_KERNEL);
459 if (work == NULL) {
460 DRM_ERROR("Failed to allocate FBC work structure\n");
461 dev_priv->display.enable_fbc(crtc);
462 return;
463 }
464
465 work->crtc = crtc;
466 work->fb = crtc->primary->fb;
467 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
468
469 dev_priv->fbc.fbc_work = work;
470
471 /* Delay the actual enabling to let pageflipping cease and the
472 * display to settle before starting the compression. Note that
473 * this delay also serves a second purpose: it allows for a
474 * vblank to pass after disabling the FBC before we attempt
475 * to modify the control registers.
476 *
477 * A more complicated solution would involve tracking vblanks
478 * following the termination of the page-flipping sequence
479 * and indeed performing the enable as a co-routine and not
480 * waiting synchronously upon the vblank.
481 *
482 * WaFbcWaitForVBlankBeforeEnable:ilk,snb
483 */
484 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
485 }
486
487 void intel_disable_fbc(struct drm_device *dev)
488 {
489 struct drm_i915_private *dev_priv = dev->dev_private;
490
491 intel_cancel_fbc_work(dev_priv);
492
493 if (!dev_priv->display.disable_fbc)
494 return;
495
496 dev_priv->display.disable_fbc(dev);
497 dev_priv->fbc.plane = -1;
498 }
499
500 static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
501 enum no_fbc_reason reason)
502 {
503 if (dev_priv->fbc.no_fbc_reason == reason)
504 return false;
505
506 dev_priv->fbc.no_fbc_reason = reason;
507 return true;
508 }
509
510 /**
511 * intel_update_fbc - enable/disable FBC as needed
512 * @dev: the drm_device
513 *
514 * Set up the framebuffer compression hardware at mode set time. We
515 * enable it if possible:
516 * - plane A only (on pre-965)
517 * - no pixel mulitply/line duplication
518 * - no alpha buffer discard
519 * - no dual wide
520 * - framebuffer <= max_hdisplay in width, max_vdisplay in height
521 *
522 * We can't assume that any compression will take place (worst case),
523 * so the compressed buffer has to be the same size as the uncompressed
524 * one. It also must reside (along with the line length buffer) in
525 * stolen memory.
526 *
527 * We need to enable/disable FBC on a global basis.
528 */
529 void intel_update_fbc(struct drm_device *dev)
530 {
531 struct drm_i915_private *dev_priv = dev->dev_private;
532 struct drm_crtc *crtc = NULL, *tmp_crtc;
533 struct intel_crtc *intel_crtc;
534 struct drm_framebuffer *fb;
535 struct drm_i915_gem_object *obj;
536 const struct drm_display_mode *adjusted_mode;
537 unsigned int max_width, max_height;
538
539 if (!HAS_FBC(dev)) {
540 set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED);
541 return;
542 }
543
544 if (!i915.powersave) {
545 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
546 DRM_DEBUG_KMS("fbc disabled per module param\n");
547 return;
548 }
549
550 /*
551 * If FBC is already on, we just have to verify that we can
552 * keep it that way...
553 * Need to disable if:
554 * - more than one pipe is active
555 * - changing FBC params (stride, fence, mode)
556 * - new fb is too large to fit in compressed buffer
557 * - going to an unsupported config (interlace, pixel multiply, etc.)
558 */
559 for_each_crtc(dev, tmp_crtc) {
560 if (intel_crtc_active(tmp_crtc) &&
561 to_intel_crtc(tmp_crtc)->primary_enabled) {
562 if (crtc) {
563 if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
564 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
565 goto out_disable;
566 }
567 crtc = tmp_crtc;
568 }
569 }
570
571 if (!crtc || crtc->primary->fb == NULL) {
572 if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
573 DRM_DEBUG_KMS("no output, disabling\n");
574 goto out_disable;
575 }
576
577 intel_crtc = to_intel_crtc(crtc);
578 fb = crtc->primary->fb;
579 obj = intel_fb_obj(fb);
580 adjusted_mode = &intel_crtc->config.adjusted_mode;
581
582 if (i915.enable_fbc < 0) {
583 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
584 DRM_DEBUG_KMS("disabled per chip default\n");
585 goto out_disable;
586 }
587 if (!i915.enable_fbc) {
588 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
589 DRM_DEBUG_KMS("fbc disabled per module param\n");
590 goto out_disable;
591 }
592 if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ||
593 (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
594 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
595 DRM_DEBUG_KMS("mode incompatible with compression, "
596 "disabling\n");
597 goto out_disable;
598 }
599
600 if (INTEL_INFO(dev)->gen >= 8 || IS_HASWELL(dev)) {
601 max_width = 4096;
602 max_height = 4096;
603 } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
604 max_width = 4096;
605 max_height = 2048;
606 } else {
607 max_width = 2048;
608 max_height = 1536;
609 }
610 if (intel_crtc->config.pipe_src_w > max_width ||
611 intel_crtc->config.pipe_src_h > max_height) {
612 if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
613 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
614 goto out_disable;
615 }
616 if ((INTEL_INFO(dev)->gen < 4 || HAS_DDI(dev)) &&
617 intel_crtc->plane != PLANE_A) {
618 if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
619 DRM_DEBUG_KMS("plane not A, disabling compression\n");
620 goto out_disable;
621 }
622
623 /* The use of a CPU fence is mandatory in order to detect writes
624 * by the CPU to the scanout and trigger updates to the FBC.
625 */
626 if (obj->tiling_mode != I915_TILING_X ||
627 obj->fence_reg == I915_FENCE_REG_NONE) {
628 if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED))
629 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
630 goto out_disable;
631 }
632 if (INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
633 to_intel_plane(crtc->primary)->rotation != BIT(DRM_ROTATE_0)) {
634 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
635 DRM_DEBUG_KMS("Rotation unsupported, disabling\n");
636 goto out_disable;
637 }
638
639 /* If the kernel debugger is active, always disable compression */
640 if (in_dbg_master())
641 goto out_disable;
642
643 if (i915_gem_stolen_setup_compression(dev, obj->base.size,
644 drm_format_plane_cpp(fb->pixel_format, 0))) {
645 if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL))
646 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
647 goto out_disable;
648 }
649
650 /* If the scanout has not changed, don't modify the FBC settings.
651 * Note that we make the fundamental assumption that the fb->obj
652 * cannot be unpinned (and have its GTT offset and fence revoked)
653 * without first being decoupled from the scanout and FBC disabled.
654 */
655 if (dev_priv->fbc.plane == intel_crtc->plane &&
656 dev_priv->fbc.fb_id == fb->base.id &&
657 dev_priv->fbc.y == crtc->y)
658 return;
659
660 if (intel_fbc_enabled(dev)) {
661 /* We update FBC along two paths, after changing fb/crtc
662 * configuration (modeswitching) and after page-flipping
663 * finishes. For the latter, we know that not only did
664 * we disable the FBC at the start of the page-flip
665 * sequence, but also more than one vblank has passed.
666 *
667 * For the former case of modeswitching, it is possible
668 * to switch between two FBC valid configurations
669 * instantaneously so we do need to disable the FBC
670 * before we can modify its control registers. We also
671 * have to wait for the next vblank for that to take
672 * effect. However, since we delay enabling FBC we can
673 * assume that a vblank has passed since disabling and
674 * that we can safely alter the registers in the deferred
675 * callback.
676 *
677 * In the scenario that we go from a valid to invalid
678 * and then back to valid FBC configuration we have
679 * no strict enforcement that a vblank occurred since
680 * disabling the FBC. However, along all current pipe
681 * disabling paths we do need to wait for a vblank at
682 * some point. And we wait before enabling FBC anyway.
683 */
684 DRM_DEBUG_KMS("disabling active FBC for update\n");
685 intel_disable_fbc(dev);
686 }
687
688 intel_enable_fbc(crtc);
689 dev_priv->fbc.no_fbc_reason = FBC_OK;
690 return;
691
692 out_disable:
693 /* Multiple disables should be harmless */
694 if (intel_fbc_enabled(dev)) {
695 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
696 intel_disable_fbc(dev);
697 }
698 i915_gem_stolen_cleanup_compression(dev);
699 }
700
701 static void i915_pineview_get_mem_freq(struct drm_device *dev)
702 {
703 struct drm_i915_private *dev_priv = dev->dev_private;
704 u32 tmp;
705
706 tmp = I915_READ(CLKCFG);
707
708 switch (tmp & CLKCFG_FSB_MASK) {
709 case CLKCFG_FSB_533:
710 dev_priv->fsb_freq = 533; /* 133*4 */
711 break;
712 case CLKCFG_FSB_800:
713 dev_priv->fsb_freq = 800; /* 200*4 */
714 break;
715 case CLKCFG_FSB_667:
716 dev_priv->fsb_freq = 667; /* 167*4 */
717 break;
718 case CLKCFG_FSB_400:
719 dev_priv->fsb_freq = 400; /* 100*4 */
720 break;
721 }
722
723 switch (tmp & CLKCFG_MEM_MASK) {
724 case CLKCFG_MEM_533:
725 dev_priv->mem_freq = 533;
726 break;
727 case CLKCFG_MEM_667:
728 dev_priv->mem_freq = 667;
729 break;
730 case CLKCFG_MEM_800:
731 dev_priv->mem_freq = 800;
732 break;
733 }
734
735 /* detect pineview DDR3 setting */
736 tmp = I915_READ(CSHRDDR3CTL);
737 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
738 }
739
740 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
741 {
742 struct drm_i915_private *dev_priv = dev->dev_private;
743 u16 ddrpll, csipll;
744
745 ddrpll = I915_READ16(DDRMPLL1);
746 csipll = I915_READ16(CSIPLL0);
747
748 switch (ddrpll & 0xff) {
749 case 0xc:
750 dev_priv->mem_freq = 800;
751 break;
752 case 0x10:
753 dev_priv->mem_freq = 1066;
754 break;
755 case 0x14:
756 dev_priv->mem_freq = 1333;
757 break;
758 case 0x18:
759 dev_priv->mem_freq = 1600;
760 break;
761 default:
762 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
763 ddrpll & 0xff);
764 dev_priv->mem_freq = 0;
765 break;
766 }
767
768 dev_priv->ips.r_t = dev_priv->mem_freq;
769
770 switch (csipll & 0x3ff) {
771 case 0x00c:
772 dev_priv->fsb_freq = 3200;
773 break;
774 case 0x00e:
775 dev_priv->fsb_freq = 3733;
776 break;
777 case 0x010:
778 dev_priv->fsb_freq = 4266;
779 break;
780 case 0x012:
781 dev_priv->fsb_freq = 4800;
782 break;
783 case 0x014:
784 dev_priv->fsb_freq = 5333;
785 break;
786 case 0x016:
787 dev_priv->fsb_freq = 5866;
788 break;
789 case 0x018:
790 dev_priv->fsb_freq = 6400;
791 break;
792 default:
793 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
794 csipll & 0x3ff);
795 dev_priv->fsb_freq = 0;
796 break;
797 }
798
799 if (dev_priv->fsb_freq == 3200) {
800 dev_priv->ips.c_m = 0;
801 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
802 dev_priv->ips.c_m = 1;
803 } else {
804 dev_priv->ips.c_m = 2;
805 }
806 }
807
808 static const struct cxsr_latency cxsr_latency_table[] = {
809 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
810 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
811 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
812 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
813 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
814
815 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
816 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
817 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
818 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
819 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
820
821 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
822 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
823 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
824 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
825 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
826
827 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
828 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
829 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
830 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
831 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
832
833 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
834 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
835 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
836 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
837 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
838
839 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
840 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
841 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
842 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
843 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
844 };
845
846 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
847 int is_ddr3,
848 int fsb,
849 int mem)
850 {
851 const struct cxsr_latency *latency;
852 int i;
853
854 if (fsb == 0 || mem == 0)
855 return NULL;
856
857 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
858 latency = &cxsr_latency_table[i];
859 if (is_desktop == latency->is_desktop &&
860 is_ddr3 == latency->is_ddr3 &&
861 fsb == latency->fsb_freq && mem == latency->mem_freq)
862 return latency;
863 }
864
865 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
866
867 return NULL;
868 }
869
870 void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
871 {
872 struct drm_device *dev = dev_priv->dev;
873 u32 val;
874
875 if (IS_VALLEYVIEW(dev)) {
876 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
877 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
878 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
879 } else if (IS_PINEVIEW(dev)) {
880 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
881 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
882 I915_WRITE(DSPFW3, val);
883 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
884 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
885 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
886 I915_WRITE(FW_BLC_SELF, val);
887 } else if (IS_I915GM(dev)) {
888 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
889 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
890 I915_WRITE(INSTPM, val);
891 } else {
892 return;
893 }
894
895 DRM_DEBUG_KMS("memory self-refresh is %s\n",
896 enable ? "enabled" : "disabled");
897 }
898
899 /*
900 * Latency for FIFO fetches is dependent on several factors:
901 * - memory configuration (speed, channels)
902 * - chipset
903 * - current MCH state
904 * It can be fairly high in some situations, so here we assume a fairly
905 * pessimal value. It's a tradeoff between extra memory fetches (if we
906 * set this value too high, the FIFO will fetch frequently to stay full)
907 * and power consumption (set it too low to save power and we might see
908 * FIFO underruns and display "flicker").
909 *
910 * A value of 5us seems to be a good balance; safe for very low end
911 * platforms but not overly aggressive on lower latency configs.
912 */
913 static const int pessimal_latency_ns = 5000;
914
915 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
916 {
917 struct drm_i915_private *dev_priv = dev->dev_private;
918 uint32_t dsparb = I915_READ(DSPARB);
919 int size;
920
921 size = dsparb & 0x7f;
922 if (plane)
923 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
924
925 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
926 plane ? "B" : "A", size);
927
928 return size;
929 }
930
931 static int i830_get_fifo_size(struct drm_device *dev, int plane)
932 {
933 struct drm_i915_private *dev_priv = dev->dev_private;
934 uint32_t dsparb = I915_READ(DSPARB);
935 int size;
936
937 size = dsparb & 0x1ff;
938 if (plane)
939 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
940 size >>= 1; /* Convert to cachelines */
941
942 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
943 plane ? "B" : "A", size);
944
945 return size;
946 }
947
948 static int i845_get_fifo_size(struct drm_device *dev, int plane)
949 {
950 struct drm_i915_private *dev_priv = dev->dev_private;
951 uint32_t dsparb = I915_READ(DSPARB);
952 int size;
953
954 size = dsparb & 0x7f;
955 size >>= 2; /* Convert to cachelines */
956
957 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
958 plane ? "B" : "A",
959 size);
960
961 return size;
962 }
963
964 /* Pineview has different values for various configs */
965 static const struct intel_watermark_params pineview_display_wm = {
966 .fifo_size = PINEVIEW_DISPLAY_FIFO,
967 .max_wm = PINEVIEW_MAX_WM,
968 .default_wm = PINEVIEW_DFT_WM,
969 .guard_size = PINEVIEW_GUARD_WM,
970 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
971 };
972 static const struct intel_watermark_params pineview_display_hplloff_wm = {
973 .fifo_size = PINEVIEW_DISPLAY_FIFO,
974 .max_wm = PINEVIEW_MAX_WM,
975 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
976 .guard_size = PINEVIEW_GUARD_WM,
977 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
978 };
979 static const struct intel_watermark_params pineview_cursor_wm = {
980 .fifo_size = PINEVIEW_CURSOR_FIFO,
981 .max_wm = PINEVIEW_CURSOR_MAX_WM,
982 .default_wm = PINEVIEW_CURSOR_DFT_WM,
983 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
984 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
985 };
986 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
987 .fifo_size = PINEVIEW_CURSOR_FIFO,
988 .max_wm = PINEVIEW_CURSOR_MAX_WM,
989 .default_wm = PINEVIEW_CURSOR_DFT_WM,
990 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
991 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
992 };
993 static const struct intel_watermark_params g4x_wm_info = {
994 .fifo_size = G4X_FIFO_SIZE,
995 .max_wm = G4X_MAX_WM,
996 .default_wm = G4X_MAX_WM,
997 .guard_size = 2,
998 .cacheline_size = G4X_FIFO_LINE_SIZE,
999 };
1000 static const struct intel_watermark_params g4x_cursor_wm_info = {
1001 .fifo_size = I965_CURSOR_FIFO,
1002 .max_wm = I965_CURSOR_MAX_WM,
1003 .default_wm = I965_CURSOR_DFT_WM,
1004 .guard_size = 2,
1005 .cacheline_size = G4X_FIFO_LINE_SIZE,
1006 };
1007 static const struct intel_watermark_params valleyview_wm_info = {
1008 .fifo_size = VALLEYVIEW_FIFO_SIZE,
1009 .max_wm = VALLEYVIEW_MAX_WM,
1010 .default_wm = VALLEYVIEW_MAX_WM,
1011 .guard_size = 2,
1012 .cacheline_size = G4X_FIFO_LINE_SIZE,
1013 };
1014 static const struct intel_watermark_params valleyview_cursor_wm_info = {
1015 .fifo_size = I965_CURSOR_FIFO,
1016 .max_wm = VALLEYVIEW_CURSOR_MAX_WM,
1017 .default_wm = I965_CURSOR_DFT_WM,
1018 .guard_size = 2,
1019 .cacheline_size = G4X_FIFO_LINE_SIZE,
1020 };
1021 static const struct intel_watermark_params i965_cursor_wm_info = {
1022 .fifo_size = I965_CURSOR_FIFO,
1023 .max_wm = I965_CURSOR_MAX_WM,
1024 .default_wm = I965_CURSOR_DFT_WM,
1025 .guard_size = 2,
1026 .cacheline_size = I915_FIFO_LINE_SIZE,
1027 };
1028 static const struct intel_watermark_params i945_wm_info = {
1029 .fifo_size = I945_FIFO_SIZE,
1030 .max_wm = I915_MAX_WM,
1031 .default_wm = 1,
1032 .guard_size = 2,
1033 .cacheline_size = I915_FIFO_LINE_SIZE,
1034 };
1035 static const struct intel_watermark_params i915_wm_info = {
1036 .fifo_size = I915_FIFO_SIZE,
1037 .max_wm = I915_MAX_WM,
1038 .default_wm = 1,
1039 .guard_size = 2,
1040 .cacheline_size = I915_FIFO_LINE_SIZE,
1041 };
1042 static const struct intel_watermark_params i830_a_wm_info = {
1043 .fifo_size = I855GM_FIFO_SIZE,
1044 .max_wm = I915_MAX_WM,
1045 .default_wm = 1,
1046 .guard_size = 2,
1047 .cacheline_size = I830_FIFO_LINE_SIZE,
1048 };
1049 static const struct intel_watermark_params i830_bc_wm_info = {
1050 .fifo_size = I855GM_FIFO_SIZE,
1051 .max_wm = I915_MAX_WM/2,
1052 .default_wm = 1,
1053 .guard_size = 2,
1054 .cacheline_size = I830_FIFO_LINE_SIZE,
1055 };
1056 static const struct intel_watermark_params i845_wm_info = {
1057 .fifo_size = I830_FIFO_SIZE,
1058 .max_wm = I915_MAX_WM,
1059 .default_wm = 1,
1060 .guard_size = 2,
1061 .cacheline_size = I830_FIFO_LINE_SIZE,
1062 };
1063
1064 /**
1065 * intel_calculate_wm - calculate watermark level
1066 * @clock_in_khz: pixel clock
1067 * @wm: chip FIFO params
1068 * @pixel_size: display pixel size
1069 * @latency_ns: memory latency for the platform
1070 *
1071 * Calculate the watermark level (the level at which the display plane will
1072 * start fetching from memory again). Each chip has a different display
1073 * FIFO size and allocation, so the caller needs to figure that out and pass
1074 * in the correct intel_watermark_params structure.
1075 *
1076 * As the pixel clock runs, the FIFO will be drained at a rate that depends
1077 * on the pixel size. When it reaches the watermark level, it'll start
1078 * fetching FIFO line sized based chunks from memory until the FIFO fills
1079 * past the watermark point. If the FIFO drains completely, a FIFO underrun
1080 * will occur, and a display engine hang could result.
1081 */
1082 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
1083 const struct intel_watermark_params *wm,
1084 int fifo_size,
1085 int pixel_size,
1086 unsigned long latency_ns)
1087 {
1088 long entries_required, wm_size;
1089
1090 /*
1091 * Note: we need to make sure we don't overflow for various clock &
1092 * latency values.
1093 * clocks go from a few thousand to several hundred thousand.
1094 * latency is usually a few thousand
1095 */
1096 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
1097 1000;
1098 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
1099
1100 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
1101
1102 wm_size = fifo_size - (entries_required + wm->guard_size);
1103
1104 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
1105
1106 /* Don't promote wm_size to unsigned... */
1107 if (wm_size > (long)wm->max_wm)
1108 wm_size = wm->max_wm;
1109 if (wm_size <= 0)
1110 wm_size = wm->default_wm;
1111
1112 /*
1113 * Bspec seems to indicate that the value shouldn't be lower than
1114 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
1115 * Lets go for 8 which is the burst size since certain platforms
1116 * already use a hardcoded 8 (which is what the spec says should be
1117 * done).
1118 */
1119 if (wm_size <= 8)
1120 wm_size = 8;
1121
1122 return wm_size;
1123 }
1124
1125 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1126 {
1127 struct drm_crtc *crtc, *enabled = NULL;
1128
1129 for_each_crtc(dev, crtc) {
1130 if (intel_crtc_active(crtc)) {
1131 if (enabled)
1132 return NULL;
1133 enabled = crtc;
1134 }
1135 }
1136
1137 return enabled;
1138 }
1139
1140 static void pineview_update_wm(struct drm_crtc *unused_crtc)
1141 {
1142 struct drm_device *dev = unused_crtc->dev;
1143 struct drm_i915_private *dev_priv = dev->dev_private;
1144 struct drm_crtc *crtc;
1145 const struct cxsr_latency *latency;
1146 u32 reg;
1147 unsigned long wm;
1148
1149 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1150 dev_priv->fsb_freq, dev_priv->mem_freq);
1151 if (!latency) {
1152 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1153 intel_set_memory_cxsr(dev_priv, false);
1154 return;
1155 }
1156
1157 crtc = single_enabled_crtc(dev);
1158 if (crtc) {
1159 const struct drm_display_mode *adjusted_mode;
1160 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1161 int clock;
1162
1163 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1164 clock = adjusted_mode->crtc_clock;
1165
1166 /* Display SR */
1167 wm = intel_calculate_wm(clock, &pineview_display_wm,
1168 pineview_display_wm.fifo_size,
1169 pixel_size, latency->display_sr);
1170 reg = I915_READ(DSPFW1);
1171 reg &= ~DSPFW_SR_MASK;
1172 reg |= wm << DSPFW_SR_SHIFT;
1173 I915_WRITE(DSPFW1, reg);
1174 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1175
1176 /* cursor SR */
1177 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1178 pineview_display_wm.fifo_size,
1179 pixel_size, latency->cursor_sr);
1180 reg = I915_READ(DSPFW3);
1181 reg &= ~DSPFW_CURSOR_SR_MASK;
1182 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1183 I915_WRITE(DSPFW3, reg);
1184
1185 /* Display HPLL off SR */
1186 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1187 pineview_display_hplloff_wm.fifo_size,
1188 pixel_size, latency->display_hpll_disable);
1189 reg = I915_READ(DSPFW3);
1190 reg &= ~DSPFW_HPLL_SR_MASK;
1191 reg |= wm & DSPFW_HPLL_SR_MASK;
1192 I915_WRITE(DSPFW3, reg);
1193
1194 /* cursor HPLL off SR */
1195 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1196 pineview_display_hplloff_wm.fifo_size,
1197 pixel_size, latency->cursor_hpll_disable);
1198 reg = I915_READ(DSPFW3);
1199 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1200 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1201 I915_WRITE(DSPFW3, reg);
1202 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1203
1204 intel_set_memory_cxsr(dev_priv, true);
1205 } else {
1206 intel_set_memory_cxsr(dev_priv, false);
1207 }
1208 }
1209
1210 static bool g4x_compute_wm0(struct drm_device *dev,
1211 int plane,
1212 const struct intel_watermark_params *display,
1213 int display_latency_ns,
1214 const struct intel_watermark_params *cursor,
1215 int cursor_latency_ns,
1216 int *plane_wm,
1217 int *cursor_wm)
1218 {
1219 struct drm_crtc *crtc;
1220 const struct drm_display_mode *adjusted_mode;
1221 int htotal, hdisplay, clock, pixel_size;
1222 int line_time_us, line_count;
1223 int entries, tlb_miss;
1224
1225 crtc = intel_get_crtc_for_plane(dev, plane);
1226 if (!intel_crtc_active(crtc)) {
1227 *cursor_wm = cursor->guard_size;
1228 *plane_wm = display->guard_size;
1229 return false;
1230 }
1231
1232 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1233 clock = adjusted_mode->crtc_clock;
1234 htotal = adjusted_mode->crtc_htotal;
1235 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1236 pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1237
1238 /* Use the small buffer method to calculate plane watermark */
1239 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1240 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1241 if (tlb_miss > 0)
1242 entries += tlb_miss;
1243 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1244 *plane_wm = entries + display->guard_size;
1245 if (*plane_wm > (int)display->max_wm)
1246 *plane_wm = display->max_wm;
1247
1248 /* Use the large buffer method to calculate cursor watermark */
1249 line_time_us = max(htotal * 1000 / clock, 1);
1250 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1251 entries = line_count * to_intel_crtc(crtc)->cursor_width * pixel_size;
1252 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1253 if (tlb_miss > 0)
1254 entries += tlb_miss;
1255 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1256 *cursor_wm = entries + cursor->guard_size;
1257 if (*cursor_wm > (int)cursor->max_wm)
1258 *cursor_wm = (int)cursor->max_wm;
1259
1260 return true;
1261 }
1262
1263 /*
1264 * Check the wm result.
1265 *
1266 * If any calculated watermark values is larger than the maximum value that
1267 * can be programmed into the associated watermark register, that watermark
1268 * must be disabled.
1269 */
1270 static bool g4x_check_srwm(struct drm_device *dev,
1271 int display_wm, int cursor_wm,
1272 const struct intel_watermark_params *display,
1273 const struct intel_watermark_params *cursor)
1274 {
1275 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1276 display_wm, cursor_wm);
1277
1278 if (display_wm > display->max_wm) {
1279 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1280 display_wm, display->max_wm);
1281 return false;
1282 }
1283
1284 if (cursor_wm > cursor->max_wm) {
1285 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1286 cursor_wm, cursor->max_wm);
1287 return false;
1288 }
1289
1290 if (!(display_wm || cursor_wm)) {
1291 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1292 return false;
1293 }
1294
1295 return true;
1296 }
1297
1298 static bool g4x_compute_srwm(struct drm_device *dev,
1299 int plane,
1300 int latency_ns,
1301 const struct intel_watermark_params *display,
1302 const struct intel_watermark_params *cursor,
1303 int *display_wm, int *cursor_wm)
1304 {
1305 struct drm_crtc *crtc;
1306 const struct drm_display_mode *adjusted_mode;
1307 int hdisplay, htotal, pixel_size, clock;
1308 unsigned long line_time_us;
1309 int line_count, line_size;
1310 int small, large;
1311 int entries;
1312
1313 if (!latency_ns) {
1314 *display_wm = *cursor_wm = 0;
1315 return false;
1316 }
1317
1318 crtc = intel_get_crtc_for_plane(dev, plane);
1319 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1320 clock = adjusted_mode->crtc_clock;
1321 htotal = adjusted_mode->crtc_htotal;
1322 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1323 pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1324
1325 line_time_us = max(htotal * 1000 / clock, 1);
1326 line_count = (latency_ns / line_time_us + 1000) / 1000;
1327 line_size = hdisplay * pixel_size;
1328
1329 /* Use the minimum of the small and large buffer method for primary */
1330 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1331 large = line_count * line_size;
1332
1333 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1334 *display_wm = entries + display->guard_size;
1335
1336 /* calculate the self-refresh watermark for display cursor */
1337 entries = line_count * pixel_size * to_intel_crtc(crtc)->cursor_width;
1338 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1339 *cursor_wm = entries + cursor->guard_size;
1340
1341 return g4x_check_srwm(dev,
1342 *display_wm, *cursor_wm,
1343 display, cursor);
1344 }
1345
1346 static bool vlv_compute_drain_latency(struct drm_crtc *crtc,
1347 int pixel_size,
1348 int *prec_mult,
1349 int *drain_latency)
1350 {
1351 int entries;
1352 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
1353
1354 if (WARN(clock == 0, "Pixel clock is zero!\n"))
1355 return false;
1356
1357 if (WARN(pixel_size == 0, "Pixel size is zero!\n"))
1358 return false;
1359
1360 entries = DIV_ROUND_UP(clock, 1000) * pixel_size;
1361 *prec_mult = (entries > 128) ? DRAIN_LATENCY_PRECISION_64 :
1362 DRAIN_LATENCY_PRECISION_32;
1363 *drain_latency = (64 * (*prec_mult) * 4) / entries;
1364
1365 if (*drain_latency > DRAIN_LATENCY_MASK)
1366 *drain_latency = DRAIN_LATENCY_MASK;
1367
1368 return true;
1369 }
1370
1371 /*
1372 * Update drain latency registers of memory arbiter
1373 *
1374 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1375 * to be programmed. Each plane has a drain latency multiplier and a drain
1376 * latency value.
1377 */
1378
1379 static void vlv_update_drain_latency(struct drm_crtc *crtc)
1380 {
1381 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1382 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1383 int pixel_size;
1384 int drain_latency;
1385 enum pipe pipe = intel_crtc->pipe;
1386 int plane_prec, prec_mult, plane_dl;
1387
1388 plane_dl = I915_READ(VLV_DDL(pipe)) & ~(DDL_PLANE_PRECISION_64 |
1389 DRAIN_LATENCY_MASK | DDL_CURSOR_PRECISION_64 |
1390 (DRAIN_LATENCY_MASK << DDL_CURSOR_SHIFT));
1391
1392 if (!intel_crtc_active(crtc)) {
1393 I915_WRITE(VLV_DDL(pipe), plane_dl);
1394 return;
1395 }
1396
1397 /* Primary plane Drain Latency */
1398 pixel_size = crtc->primary->fb->bits_per_pixel / 8; /* BPP */
1399 if (vlv_compute_drain_latency(crtc, pixel_size, &prec_mult, &drain_latency)) {
1400 plane_prec = (prec_mult == DRAIN_LATENCY_PRECISION_64) ?
1401 DDL_PLANE_PRECISION_64 :
1402 DDL_PLANE_PRECISION_32;
1403 plane_dl |= plane_prec | drain_latency;
1404 }
1405
1406 /* Cursor Drain Latency
1407 * BPP is always 4 for cursor
1408 */
1409 pixel_size = 4;
1410
1411 /* Program cursor DL only if it is enabled */
1412 if (intel_crtc->cursor_base &&
1413 vlv_compute_drain_latency(crtc, pixel_size, &prec_mult, &drain_latency)) {
1414 plane_prec = (prec_mult == DRAIN_LATENCY_PRECISION_64) ?
1415 DDL_CURSOR_PRECISION_64 :
1416 DDL_CURSOR_PRECISION_32;
1417 plane_dl |= plane_prec | (drain_latency << DDL_CURSOR_SHIFT);
1418 }
1419
1420 I915_WRITE(VLV_DDL(pipe), plane_dl);
1421 }
1422
1423 #define single_plane_enabled(mask) is_power_of_2(mask)
1424
1425 static void valleyview_update_wm(struct drm_crtc *crtc)
1426 {
1427 struct drm_device *dev = crtc->dev;
1428 static const int sr_latency_ns = 12000;
1429 struct drm_i915_private *dev_priv = dev->dev_private;
1430 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1431 int plane_sr, cursor_sr;
1432 int ignore_plane_sr, ignore_cursor_sr;
1433 unsigned int enabled = 0;
1434 bool cxsr_enabled;
1435
1436 vlv_update_drain_latency(crtc);
1437
1438 if (g4x_compute_wm0(dev, PIPE_A,
1439 &valleyview_wm_info, pessimal_latency_ns,
1440 &valleyview_cursor_wm_info, pessimal_latency_ns,
1441 &planea_wm, &cursora_wm))
1442 enabled |= 1 << PIPE_A;
1443
1444 if (g4x_compute_wm0(dev, PIPE_B,
1445 &valleyview_wm_info, pessimal_latency_ns,
1446 &valleyview_cursor_wm_info, pessimal_latency_ns,
1447 &planeb_wm, &cursorb_wm))
1448 enabled |= 1 << PIPE_B;
1449
1450 if (single_plane_enabled(enabled) &&
1451 g4x_compute_srwm(dev, ffs(enabled) - 1,
1452 sr_latency_ns,
1453 &valleyview_wm_info,
1454 &valleyview_cursor_wm_info,
1455 &plane_sr, &ignore_cursor_sr) &&
1456 g4x_compute_srwm(dev, ffs(enabled) - 1,
1457 2*sr_latency_ns,
1458 &valleyview_wm_info,
1459 &valleyview_cursor_wm_info,
1460 &ignore_plane_sr, &cursor_sr)) {
1461 cxsr_enabled = true;
1462 } else {
1463 cxsr_enabled = false;
1464 intel_set_memory_cxsr(dev_priv, false);
1465 plane_sr = cursor_sr = 0;
1466 }
1467
1468 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1469 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1470 planea_wm, cursora_wm,
1471 planeb_wm, cursorb_wm,
1472 plane_sr, cursor_sr);
1473
1474 I915_WRITE(DSPFW1,
1475 (plane_sr << DSPFW_SR_SHIFT) |
1476 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1477 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1478 (planea_wm << DSPFW_PLANEA_SHIFT));
1479 I915_WRITE(DSPFW2,
1480 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1481 (cursora_wm << DSPFW_CURSORA_SHIFT));
1482 I915_WRITE(DSPFW3,
1483 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1484 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1485
1486 if (cxsr_enabled)
1487 intel_set_memory_cxsr(dev_priv, true);
1488 }
1489
1490 static void cherryview_update_wm(struct drm_crtc *crtc)
1491 {
1492 struct drm_device *dev = crtc->dev;
1493 static const int sr_latency_ns = 12000;
1494 struct drm_i915_private *dev_priv = dev->dev_private;
1495 int planea_wm, planeb_wm, planec_wm;
1496 int cursora_wm, cursorb_wm, cursorc_wm;
1497 int plane_sr, cursor_sr;
1498 int ignore_plane_sr, ignore_cursor_sr;
1499 unsigned int enabled = 0;
1500 bool cxsr_enabled;
1501
1502 vlv_update_drain_latency(crtc);
1503
1504 if (g4x_compute_wm0(dev, PIPE_A,
1505 &valleyview_wm_info, pessimal_latency_ns,
1506 &valleyview_cursor_wm_info, pessimal_latency_ns,
1507 &planea_wm, &cursora_wm))
1508 enabled |= 1 << PIPE_A;
1509
1510 if (g4x_compute_wm0(dev, PIPE_B,
1511 &valleyview_wm_info, pessimal_latency_ns,
1512 &valleyview_cursor_wm_info, pessimal_latency_ns,
1513 &planeb_wm, &cursorb_wm))
1514 enabled |= 1 << PIPE_B;
1515
1516 if (g4x_compute_wm0(dev, PIPE_C,
1517 &valleyview_wm_info, pessimal_latency_ns,
1518 &valleyview_cursor_wm_info, pessimal_latency_ns,
1519 &planec_wm, &cursorc_wm))
1520 enabled |= 1 << PIPE_C;
1521
1522 if (single_plane_enabled(enabled) &&
1523 g4x_compute_srwm(dev, ffs(enabled) - 1,
1524 sr_latency_ns,
1525 &valleyview_wm_info,
1526 &valleyview_cursor_wm_info,
1527 &plane_sr, &ignore_cursor_sr) &&
1528 g4x_compute_srwm(dev, ffs(enabled) - 1,
1529 2*sr_latency_ns,
1530 &valleyview_wm_info,
1531 &valleyview_cursor_wm_info,
1532 &ignore_plane_sr, &cursor_sr)) {
1533 cxsr_enabled = true;
1534 } else {
1535 cxsr_enabled = false;
1536 intel_set_memory_cxsr(dev_priv, false);
1537 plane_sr = cursor_sr = 0;
1538 }
1539
1540 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1541 "B: plane=%d, cursor=%d, C: plane=%d, cursor=%d, "
1542 "SR: plane=%d, cursor=%d\n",
1543 planea_wm, cursora_wm,
1544 planeb_wm, cursorb_wm,
1545 planec_wm, cursorc_wm,
1546 plane_sr, cursor_sr);
1547
1548 I915_WRITE(DSPFW1,
1549 (plane_sr << DSPFW_SR_SHIFT) |
1550 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1551 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1552 (planea_wm << DSPFW_PLANEA_SHIFT));
1553 I915_WRITE(DSPFW2,
1554 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1555 (cursora_wm << DSPFW_CURSORA_SHIFT));
1556 I915_WRITE(DSPFW3,
1557 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1558 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1559 I915_WRITE(DSPFW9_CHV,
1560 (I915_READ(DSPFW9_CHV) & ~(DSPFW_PLANEC_MASK |
1561 DSPFW_CURSORC_MASK)) |
1562 (planec_wm << DSPFW_PLANEC_SHIFT) |
1563 (cursorc_wm << DSPFW_CURSORC_SHIFT));
1564
1565 if (cxsr_enabled)
1566 intel_set_memory_cxsr(dev_priv, true);
1567 }
1568
1569 static void valleyview_update_sprite_wm(struct drm_plane *plane,
1570 struct drm_crtc *crtc,
1571 uint32_t sprite_width,
1572 uint32_t sprite_height,
1573 int pixel_size,
1574 bool enabled, bool scaled)
1575 {
1576 struct drm_device *dev = crtc->dev;
1577 struct drm_i915_private *dev_priv = dev->dev_private;
1578 int pipe = to_intel_plane(plane)->pipe;
1579 int sprite = to_intel_plane(plane)->plane;
1580 int drain_latency;
1581 int plane_prec;
1582 int sprite_dl;
1583 int prec_mult;
1584
1585 sprite_dl = I915_READ(VLV_DDL(pipe)) & ~(DDL_SPRITE_PRECISION_64(sprite) |
1586 (DRAIN_LATENCY_MASK << DDL_SPRITE_SHIFT(sprite)));
1587
1588 if (enabled && vlv_compute_drain_latency(crtc, pixel_size, &prec_mult,
1589 &drain_latency)) {
1590 plane_prec = (prec_mult == DRAIN_LATENCY_PRECISION_64) ?
1591 DDL_SPRITE_PRECISION_64(sprite) :
1592 DDL_SPRITE_PRECISION_32(sprite);
1593 sprite_dl |= plane_prec |
1594 (drain_latency << DDL_SPRITE_SHIFT(sprite));
1595 }
1596
1597 I915_WRITE(VLV_DDL(pipe), sprite_dl);
1598 }
1599
1600 static void g4x_update_wm(struct drm_crtc *crtc)
1601 {
1602 struct drm_device *dev = crtc->dev;
1603 static const int sr_latency_ns = 12000;
1604 struct drm_i915_private *dev_priv = dev->dev_private;
1605 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1606 int plane_sr, cursor_sr;
1607 unsigned int enabled = 0;
1608 bool cxsr_enabled;
1609
1610 if (g4x_compute_wm0(dev, PIPE_A,
1611 &g4x_wm_info, pessimal_latency_ns,
1612 &g4x_cursor_wm_info, pessimal_latency_ns,
1613 &planea_wm, &cursora_wm))
1614 enabled |= 1 << PIPE_A;
1615
1616 if (g4x_compute_wm0(dev, PIPE_B,
1617 &g4x_wm_info, pessimal_latency_ns,
1618 &g4x_cursor_wm_info, pessimal_latency_ns,
1619 &planeb_wm, &cursorb_wm))
1620 enabled |= 1 << PIPE_B;
1621
1622 if (single_plane_enabled(enabled) &&
1623 g4x_compute_srwm(dev, ffs(enabled) - 1,
1624 sr_latency_ns,
1625 &g4x_wm_info,
1626 &g4x_cursor_wm_info,
1627 &plane_sr, &cursor_sr)) {
1628 cxsr_enabled = true;
1629 } else {
1630 cxsr_enabled = false;
1631 intel_set_memory_cxsr(dev_priv, false);
1632 plane_sr = cursor_sr = 0;
1633 }
1634
1635 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1636 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1637 planea_wm, cursora_wm,
1638 planeb_wm, cursorb_wm,
1639 plane_sr, cursor_sr);
1640
1641 I915_WRITE(DSPFW1,
1642 (plane_sr << DSPFW_SR_SHIFT) |
1643 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1644 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1645 (planea_wm << DSPFW_PLANEA_SHIFT));
1646 I915_WRITE(DSPFW2,
1647 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1648 (cursora_wm << DSPFW_CURSORA_SHIFT));
1649 /* HPLL off in SR has some issues on G4x... disable it */
1650 I915_WRITE(DSPFW3,
1651 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1652 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1653
1654 if (cxsr_enabled)
1655 intel_set_memory_cxsr(dev_priv, true);
1656 }
1657
1658 static void i965_update_wm(struct drm_crtc *unused_crtc)
1659 {
1660 struct drm_device *dev = unused_crtc->dev;
1661 struct drm_i915_private *dev_priv = dev->dev_private;
1662 struct drm_crtc *crtc;
1663 int srwm = 1;
1664 int cursor_sr = 16;
1665 bool cxsr_enabled;
1666
1667 /* Calc sr entries for one plane configs */
1668 crtc = single_enabled_crtc(dev);
1669 if (crtc) {
1670 /* self-refresh has much higher latency */
1671 static const int sr_latency_ns = 12000;
1672 const struct drm_display_mode *adjusted_mode =
1673 &to_intel_crtc(crtc)->config.adjusted_mode;
1674 int clock = adjusted_mode->crtc_clock;
1675 int htotal = adjusted_mode->crtc_htotal;
1676 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1677 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1678 unsigned long line_time_us;
1679 int entries;
1680
1681 line_time_us = max(htotal * 1000 / clock, 1);
1682
1683 /* Use ns/us then divide to preserve precision */
1684 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1685 pixel_size * hdisplay;
1686 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1687 srwm = I965_FIFO_SIZE - entries;
1688 if (srwm < 0)
1689 srwm = 1;
1690 srwm &= 0x1ff;
1691 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1692 entries, srwm);
1693
1694 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1695 pixel_size * to_intel_crtc(crtc)->cursor_width;
1696 entries = DIV_ROUND_UP(entries,
1697 i965_cursor_wm_info.cacheline_size);
1698 cursor_sr = i965_cursor_wm_info.fifo_size -
1699 (entries + i965_cursor_wm_info.guard_size);
1700
1701 if (cursor_sr > i965_cursor_wm_info.max_wm)
1702 cursor_sr = i965_cursor_wm_info.max_wm;
1703
1704 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1705 "cursor %d\n", srwm, cursor_sr);
1706
1707 cxsr_enabled = true;
1708 } else {
1709 cxsr_enabled = false;
1710 /* Turn off self refresh if both pipes are enabled */
1711 intel_set_memory_cxsr(dev_priv, false);
1712 }
1713
1714 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1715 srwm);
1716
1717 /* 965 has limitations... */
1718 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1719 (8 << DSPFW_CURSORB_SHIFT) |
1720 (8 << DSPFW_PLANEB_SHIFT) |
1721 (8 << DSPFW_PLANEA_SHIFT));
1722 I915_WRITE(DSPFW2, (8 << DSPFW_CURSORA_SHIFT) |
1723 (8 << DSPFW_PLANEC_SHIFT_OLD));
1724 /* update cursor SR watermark */
1725 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1726
1727 if (cxsr_enabled)
1728 intel_set_memory_cxsr(dev_priv, true);
1729 }
1730
1731 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1732 {
1733 struct drm_device *dev = unused_crtc->dev;
1734 struct drm_i915_private *dev_priv = dev->dev_private;
1735 const struct intel_watermark_params *wm_info;
1736 uint32_t fwater_lo;
1737 uint32_t fwater_hi;
1738 int cwm, srwm = 1;
1739 int fifo_size;
1740 int planea_wm, planeb_wm;
1741 struct drm_crtc *crtc, *enabled = NULL;
1742
1743 if (IS_I945GM(dev))
1744 wm_info = &i945_wm_info;
1745 else if (!IS_GEN2(dev))
1746 wm_info = &i915_wm_info;
1747 else
1748 wm_info = &i830_a_wm_info;
1749
1750 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1751 crtc = intel_get_crtc_for_plane(dev, 0);
1752 if (intel_crtc_active(crtc)) {
1753 const struct drm_display_mode *adjusted_mode;
1754 int cpp = crtc->primary->fb->bits_per_pixel / 8;
1755 if (IS_GEN2(dev))
1756 cpp = 4;
1757
1758 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1759 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1760 wm_info, fifo_size, cpp,
1761 pessimal_latency_ns);
1762 enabled = crtc;
1763 } else {
1764 planea_wm = fifo_size - wm_info->guard_size;
1765 if (planea_wm > (long)wm_info->max_wm)
1766 planea_wm = wm_info->max_wm;
1767 }
1768
1769 if (IS_GEN2(dev))
1770 wm_info = &i830_bc_wm_info;
1771
1772 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1773 crtc = intel_get_crtc_for_plane(dev, 1);
1774 if (intel_crtc_active(crtc)) {
1775 const struct drm_display_mode *adjusted_mode;
1776 int cpp = crtc->primary->fb->bits_per_pixel / 8;
1777 if (IS_GEN2(dev))
1778 cpp = 4;
1779
1780 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1781 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1782 wm_info, fifo_size, cpp,
1783 pessimal_latency_ns);
1784 if (enabled == NULL)
1785 enabled = crtc;
1786 else
1787 enabled = NULL;
1788 } else {
1789 planeb_wm = fifo_size - wm_info->guard_size;
1790 if (planeb_wm > (long)wm_info->max_wm)
1791 planeb_wm = wm_info->max_wm;
1792 }
1793
1794 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1795
1796 if (IS_I915GM(dev) && enabled) {
1797 struct drm_i915_gem_object *obj;
1798
1799 obj = intel_fb_obj(enabled->primary->fb);
1800
1801 /* self-refresh seems busted with untiled */
1802 if (obj->tiling_mode == I915_TILING_NONE)
1803 enabled = NULL;
1804 }
1805
1806 /*
1807 * Overlay gets an aggressive default since video jitter is bad.
1808 */
1809 cwm = 2;
1810
1811 /* Play safe and disable self-refresh before adjusting watermarks. */
1812 intel_set_memory_cxsr(dev_priv, false);
1813
1814 /* Calc sr entries for one plane configs */
1815 if (HAS_FW_BLC(dev) && enabled) {
1816 /* self-refresh has much higher latency */
1817 static const int sr_latency_ns = 6000;
1818 const struct drm_display_mode *adjusted_mode =
1819 &to_intel_crtc(enabled)->config.adjusted_mode;
1820 int clock = adjusted_mode->crtc_clock;
1821 int htotal = adjusted_mode->crtc_htotal;
1822 int hdisplay = to_intel_crtc(enabled)->config.pipe_src_w;
1823 int pixel_size = enabled->primary->fb->bits_per_pixel / 8;
1824 unsigned long line_time_us;
1825 int entries;
1826
1827 line_time_us = max(htotal * 1000 / clock, 1);
1828
1829 /* Use ns/us then divide to preserve precision */
1830 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1831 pixel_size * hdisplay;
1832 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1833 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1834 srwm = wm_info->fifo_size - entries;
1835 if (srwm < 0)
1836 srwm = 1;
1837
1838 if (IS_I945G(dev) || IS_I945GM(dev))
1839 I915_WRITE(FW_BLC_SELF,
1840 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1841 else if (IS_I915GM(dev))
1842 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1843 }
1844
1845 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1846 planea_wm, planeb_wm, cwm, srwm);
1847
1848 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1849 fwater_hi = (cwm & 0x1f);
1850
1851 /* Set request length to 8 cachelines per fetch */
1852 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1853 fwater_hi = fwater_hi | (1 << 8);
1854
1855 I915_WRITE(FW_BLC, fwater_lo);
1856 I915_WRITE(FW_BLC2, fwater_hi);
1857
1858 if (enabled)
1859 intel_set_memory_cxsr(dev_priv, true);
1860 }
1861
1862 static void i845_update_wm(struct drm_crtc *unused_crtc)
1863 {
1864 struct drm_device *dev = unused_crtc->dev;
1865 struct drm_i915_private *dev_priv = dev->dev_private;
1866 struct drm_crtc *crtc;
1867 const struct drm_display_mode *adjusted_mode;
1868 uint32_t fwater_lo;
1869 int planea_wm;
1870
1871 crtc = single_enabled_crtc(dev);
1872 if (crtc == NULL)
1873 return;
1874
1875 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1876 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1877 &i845_wm_info,
1878 dev_priv->display.get_fifo_size(dev, 0),
1879 4, pessimal_latency_ns);
1880 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1881 fwater_lo |= (3<<8) | planea_wm;
1882
1883 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1884
1885 I915_WRITE(FW_BLC, fwater_lo);
1886 }
1887
1888 static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
1889 struct drm_crtc *crtc)
1890 {
1891 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1892 uint32_t pixel_rate;
1893
1894 pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock;
1895
1896 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1897 * adjust the pixel_rate here. */
1898
1899 if (intel_crtc->config.pch_pfit.enabled) {
1900 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1901 uint32_t pfit_size = intel_crtc->config.pch_pfit.size;
1902
1903 pipe_w = intel_crtc->config.pipe_src_w;
1904 pipe_h = intel_crtc->config.pipe_src_h;
1905 pfit_w = (pfit_size >> 16) & 0xFFFF;
1906 pfit_h = pfit_size & 0xFFFF;
1907 if (pipe_w < pfit_w)
1908 pipe_w = pfit_w;
1909 if (pipe_h < pfit_h)
1910 pipe_h = pfit_h;
1911
1912 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1913 pfit_w * pfit_h);
1914 }
1915
1916 return pixel_rate;
1917 }
1918
1919 /* latency must be in 0.1us units. */
1920 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
1921 uint32_t latency)
1922 {
1923 uint64_t ret;
1924
1925 if (WARN(latency == 0, "Latency value missing\n"))
1926 return UINT_MAX;
1927
1928 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1929 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1930
1931 return ret;
1932 }
1933
1934 /* latency must be in 0.1us units. */
1935 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1936 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1937 uint32_t latency)
1938 {
1939 uint32_t ret;
1940
1941 if (WARN(latency == 0, "Latency value missing\n"))
1942 return UINT_MAX;
1943
1944 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1945 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1946 ret = DIV_ROUND_UP(ret, 64) + 2;
1947 return ret;
1948 }
1949
1950 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1951 uint8_t bytes_per_pixel)
1952 {
1953 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1954 }
1955
1956 struct ilk_pipe_wm_parameters {
1957 bool active;
1958 uint32_t pipe_htotal;
1959 uint32_t pixel_rate;
1960 struct intel_plane_wm_parameters pri;
1961 struct intel_plane_wm_parameters spr;
1962 struct intel_plane_wm_parameters cur;
1963 };
1964
1965 struct ilk_wm_maximums {
1966 uint16_t pri;
1967 uint16_t spr;
1968 uint16_t cur;
1969 uint16_t fbc;
1970 };
1971
1972 /* used in computing the new watermarks state */
1973 struct intel_wm_config {
1974 unsigned int num_pipes_active;
1975 bool sprites_enabled;
1976 bool sprites_scaled;
1977 };
1978
1979 /*
1980 * For both WM_PIPE and WM_LP.
1981 * mem_value must be in 0.1us units.
1982 */
1983 static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params,
1984 uint32_t mem_value,
1985 bool is_lp)
1986 {
1987 uint32_t method1, method2;
1988
1989 if (!params->active || !params->pri.enabled)
1990 return 0;
1991
1992 method1 = ilk_wm_method1(params->pixel_rate,
1993 params->pri.bytes_per_pixel,
1994 mem_value);
1995
1996 if (!is_lp)
1997 return method1;
1998
1999 method2 = ilk_wm_method2(params->pixel_rate,
2000 params->pipe_htotal,
2001 params->pri.horiz_pixels,
2002 params->pri.bytes_per_pixel,
2003 mem_value);
2004
2005 return min(method1, method2);
2006 }
2007
2008 /*
2009 * For both WM_PIPE and WM_LP.
2010 * mem_value must be in 0.1us units.
2011 */
2012 static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params,
2013 uint32_t mem_value)
2014 {
2015 uint32_t method1, method2;
2016
2017 if (!params->active || !params->spr.enabled)
2018 return 0;
2019
2020 method1 = ilk_wm_method1(params->pixel_rate,
2021 params->spr.bytes_per_pixel,
2022 mem_value);
2023 method2 = ilk_wm_method2(params->pixel_rate,
2024 params->pipe_htotal,
2025 params->spr.horiz_pixels,
2026 params->spr.bytes_per_pixel,
2027 mem_value);
2028 return min(method1, method2);
2029 }
2030
2031 /*
2032 * For both WM_PIPE and WM_LP.
2033 * mem_value must be in 0.1us units.
2034 */
2035 static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params,
2036 uint32_t mem_value)
2037 {
2038 if (!params->active || !params->cur.enabled)
2039 return 0;
2040
2041 return ilk_wm_method2(params->pixel_rate,
2042 params->pipe_htotal,
2043 params->cur.horiz_pixels,
2044 params->cur.bytes_per_pixel,
2045 mem_value);
2046 }
2047
2048 /* Only for WM_LP. */
2049 static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params,
2050 uint32_t pri_val)
2051 {
2052 if (!params->active || !params->pri.enabled)
2053 return 0;
2054
2055 return ilk_wm_fbc(pri_val,
2056 params->pri.horiz_pixels,
2057 params->pri.bytes_per_pixel);
2058 }
2059
2060 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
2061 {
2062 if (INTEL_INFO(dev)->gen >= 8)
2063 return 3072;
2064 else if (INTEL_INFO(dev)->gen >= 7)
2065 return 768;
2066 else
2067 return 512;
2068 }
2069
2070 static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
2071 int level, bool is_sprite)
2072 {
2073 if (INTEL_INFO(dev)->gen >= 8)
2074 /* BDW primary/sprite plane watermarks */
2075 return level == 0 ? 255 : 2047;
2076 else if (INTEL_INFO(dev)->gen >= 7)
2077 /* IVB/HSW primary/sprite plane watermarks */
2078 return level == 0 ? 127 : 1023;
2079 else if (!is_sprite)
2080 /* ILK/SNB primary plane watermarks */
2081 return level == 0 ? 127 : 511;
2082 else
2083 /* ILK/SNB sprite plane watermarks */
2084 return level == 0 ? 63 : 255;
2085 }
2086
2087 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
2088 int level)
2089 {
2090 if (INTEL_INFO(dev)->gen >= 7)
2091 return level == 0 ? 63 : 255;
2092 else
2093 return level == 0 ? 31 : 63;
2094 }
2095
2096 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
2097 {
2098 if (INTEL_INFO(dev)->gen >= 8)
2099 return 31;
2100 else
2101 return 15;
2102 }
2103
2104 /* Calculate the maximum primary/sprite plane watermark */
2105 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
2106 int level,
2107 const struct intel_wm_config *config,
2108 enum intel_ddb_partitioning ddb_partitioning,
2109 bool is_sprite)
2110 {
2111 unsigned int fifo_size = ilk_display_fifo_size(dev);
2112
2113 /* if sprites aren't enabled, sprites get nothing */
2114 if (is_sprite && !config->sprites_enabled)
2115 return 0;
2116
2117 /* HSW allows LP1+ watermarks even with multiple pipes */
2118 if (level == 0 || config->num_pipes_active > 1) {
2119 fifo_size /= INTEL_INFO(dev)->num_pipes;
2120
2121 /*
2122 * For some reason the non self refresh
2123 * FIFO size is only half of the self
2124 * refresh FIFO size on ILK/SNB.
2125 */
2126 if (INTEL_INFO(dev)->gen <= 6)
2127 fifo_size /= 2;
2128 }
2129
2130 if (config->sprites_enabled) {
2131 /* level 0 is always calculated with 1:1 split */
2132 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
2133 if (is_sprite)
2134 fifo_size *= 5;
2135 fifo_size /= 6;
2136 } else {
2137 fifo_size /= 2;
2138 }
2139 }
2140
2141 /* clamp to max that the registers can hold */
2142 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
2143 }
2144
2145 /* Calculate the maximum cursor plane watermark */
2146 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
2147 int level,
2148 const struct intel_wm_config *config)
2149 {
2150 /* HSW LP1+ watermarks w/ multiple pipes */
2151 if (level > 0 && config->num_pipes_active > 1)
2152 return 64;
2153
2154 /* otherwise just report max that registers can hold */
2155 return ilk_cursor_wm_reg_max(dev, level);
2156 }
2157
2158 static void ilk_compute_wm_maximums(const struct drm_device *dev,
2159 int level,
2160 const struct intel_wm_config *config,
2161 enum intel_ddb_partitioning ddb_partitioning,
2162 struct ilk_wm_maximums *max)
2163 {
2164 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
2165 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
2166 max->cur = ilk_cursor_wm_max(dev, level, config);
2167 max->fbc = ilk_fbc_wm_reg_max(dev);
2168 }
2169
2170 static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
2171 int level,
2172 struct ilk_wm_maximums *max)
2173 {
2174 max->pri = ilk_plane_wm_reg_max(dev, level, false);
2175 max->spr = ilk_plane_wm_reg_max(dev, level, true);
2176 max->cur = ilk_cursor_wm_reg_max(dev, level);
2177 max->fbc = ilk_fbc_wm_reg_max(dev);
2178 }
2179
2180 static bool ilk_validate_wm_level(int level,
2181 const struct ilk_wm_maximums *max,
2182 struct intel_wm_level *result)
2183 {
2184 bool ret;
2185
2186 /* already determined to be invalid? */
2187 if (!result->enable)
2188 return false;
2189
2190 result->enable = result->pri_val <= max->pri &&
2191 result->spr_val <= max->spr &&
2192 result->cur_val <= max->cur;
2193
2194 ret = result->enable;
2195
2196 /*
2197 * HACK until we can pre-compute everything,
2198 * and thus fail gracefully if LP0 watermarks
2199 * are exceeded...
2200 */
2201 if (level == 0 && !result->enable) {
2202 if (result->pri_val > max->pri)
2203 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2204 level, result->pri_val, max->pri);
2205 if (result->spr_val > max->spr)
2206 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2207 level, result->spr_val, max->spr);
2208 if (result->cur_val > max->cur)
2209 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2210 level, result->cur_val, max->cur);
2211
2212 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2213 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2214 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2215 result->enable = true;
2216 }
2217
2218 return ret;
2219 }
2220
2221 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
2222 int level,
2223 const struct ilk_pipe_wm_parameters *p,
2224 struct intel_wm_level *result)
2225 {
2226 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2227 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2228 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2229
2230 /* WM1+ latency values stored in 0.5us units */
2231 if (level > 0) {
2232 pri_latency *= 5;
2233 spr_latency *= 5;
2234 cur_latency *= 5;
2235 }
2236
2237 result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
2238 result->spr_val = ilk_compute_spr_wm(p, spr_latency);
2239 result->cur_val = ilk_compute_cur_wm(p, cur_latency);
2240 result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
2241 result->enable = true;
2242 }
2243
2244 static uint32_t
2245 hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
2246 {
2247 struct drm_i915_private *dev_priv = dev->dev_private;
2248 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2249 struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
2250 u32 linetime, ips_linetime;
2251
2252 if (!intel_crtc_active(crtc))
2253 return 0;
2254
2255 /* The WM are computed with base on how long it takes to fill a single
2256 * row at the given clock rate, multiplied by 8.
2257 * */
2258 linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
2259 mode->crtc_clock);
2260 ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
2261 intel_ddi_get_cdclk_freq(dev_priv));
2262
2263 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2264 PIPE_WM_LINETIME_TIME(linetime);
2265 }
2266
2267 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5])
2268 {
2269 struct drm_i915_private *dev_priv = dev->dev_private;
2270
2271 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2272 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2273
2274 wm[0] = (sskpd >> 56) & 0xFF;
2275 if (wm[0] == 0)
2276 wm[0] = sskpd & 0xF;
2277 wm[1] = (sskpd >> 4) & 0xFF;
2278 wm[2] = (sskpd >> 12) & 0xFF;
2279 wm[3] = (sskpd >> 20) & 0x1FF;
2280 wm[4] = (sskpd >> 32) & 0x1FF;
2281 } else if (INTEL_INFO(dev)->gen >= 6) {
2282 uint32_t sskpd = I915_READ(MCH_SSKPD);
2283
2284 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2285 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2286 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2287 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2288 } else if (INTEL_INFO(dev)->gen >= 5) {
2289 uint32_t mltr = I915_READ(MLTR_ILK);
2290
2291 /* ILK primary LP0 latency is 700 ns */
2292 wm[0] = 7;
2293 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2294 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2295 }
2296 }
2297
2298 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2299 {
2300 /* ILK sprite LP0 latency is 1300 ns */
2301 if (INTEL_INFO(dev)->gen == 5)
2302 wm[0] = 13;
2303 }
2304
2305 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2306 {
2307 /* ILK cursor LP0 latency is 1300 ns */
2308 if (INTEL_INFO(dev)->gen == 5)
2309 wm[0] = 13;
2310
2311 /* WaDoubleCursorLP3Latency:ivb */
2312 if (IS_IVYBRIDGE(dev))
2313 wm[3] *= 2;
2314 }
2315
2316 int ilk_wm_max_level(const struct drm_device *dev)
2317 {
2318 /* how many WM levels are we expecting */
2319 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2320 return 4;
2321 else if (INTEL_INFO(dev)->gen >= 6)
2322 return 3;
2323 else
2324 return 2;
2325 }
2326 static void intel_print_wm_latency(struct drm_device *dev,
2327 const char *name,
2328 const uint16_t wm[5])
2329 {
2330 int level, max_level = ilk_wm_max_level(dev);
2331
2332 for (level = 0; level <= max_level; level++) {
2333 unsigned int latency = wm[level];
2334
2335 if (latency == 0) {
2336 DRM_ERROR("%s WM%d latency not provided\n",
2337 name, level);
2338 continue;
2339 }
2340
2341 /* WM1+ latency values in 0.5us units */
2342 if (level > 0)
2343 latency *= 5;
2344
2345 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2346 name, level, wm[level],
2347 latency / 10, latency % 10);
2348 }
2349 }
2350
2351 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2352 uint16_t wm[5], uint16_t min)
2353 {
2354 int level, max_level = ilk_wm_max_level(dev_priv->dev);
2355
2356 if (wm[0] >= min)
2357 return false;
2358
2359 wm[0] = max(wm[0], min);
2360 for (level = 1; level <= max_level; level++)
2361 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2362
2363 return true;
2364 }
2365
2366 static void snb_wm_latency_quirk(struct drm_device *dev)
2367 {
2368 struct drm_i915_private *dev_priv = dev->dev_private;
2369 bool changed;
2370
2371 /*
2372 * The BIOS provided WM memory latency values are often
2373 * inadequate for high resolution displays. Adjust them.
2374 */
2375 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2376 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2377 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2378
2379 if (!changed)
2380 return;
2381
2382 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2383 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2384 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2385 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2386 }
2387
2388 static void ilk_setup_wm_latency(struct drm_device *dev)
2389 {
2390 struct drm_i915_private *dev_priv = dev->dev_private;
2391
2392 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2393
2394 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2395 sizeof(dev_priv->wm.pri_latency));
2396 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2397 sizeof(dev_priv->wm.pri_latency));
2398
2399 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2400 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2401
2402 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2403 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2404 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2405
2406 if (IS_GEN6(dev))
2407 snb_wm_latency_quirk(dev);
2408 }
2409
2410 static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
2411 struct ilk_pipe_wm_parameters *p)
2412 {
2413 struct drm_device *dev = crtc->dev;
2414 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2415 enum pipe pipe = intel_crtc->pipe;
2416 struct drm_plane *plane;
2417
2418 if (!intel_crtc_active(crtc))
2419 return;
2420
2421 p->active = true;
2422 p->pipe_htotal = intel_crtc->config.adjusted_mode.crtc_htotal;
2423 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
2424 p->pri.bytes_per_pixel = crtc->primary->fb->bits_per_pixel / 8;
2425 p->cur.bytes_per_pixel = 4;
2426 p->pri.horiz_pixels = intel_crtc->config.pipe_src_w;
2427 p->cur.horiz_pixels = intel_crtc->cursor_width;
2428 /* TODO: for now, assume primary and cursor planes are always enabled. */
2429 p->pri.enabled = true;
2430 p->cur.enabled = true;
2431
2432 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
2433 struct intel_plane *intel_plane = to_intel_plane(plane);
2434
2435 if (intel_plane->pipe == pipe) {
2436 p->spr = intel_plane->wm;
2437 break;
2438 }
2439 }
2440 }
2441
2442 static void ilk_compute_wm_config(struct drm_device *dev,
2443 struct intel_wm_config *config)
2444 {
2445 struct intel_crtc *intel_crtc;
2446
2447 /* Compute the currently _active_ config */
2448 for_each_intel_crtc(dev, intel_crtc) {
2449 const struct intel_pipe_wm *wm = &intel_crtc->wm.active;
2450
2451 if (!wm->pipe_enabled)
2452 continue;
2453
2454 config->sprites_enabled |= wm->sprites_enabled;
2455 config->sprites_scaled |= wm->sprites_scaled;
2456 config->num_pipes_active++;
2457 }
2458 }
2459
2460 /* Compute new watermarks for the pipe */
2461 static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
2462 const struct ilk_pipe_wm_parameters *params,
2463 struct intel_pipe_wm *pipe_wm)
2464 {
2465 struct drm_device *dev = crtc->dev;
2466 const struct drm_i915_private *dev_priv = dev->dev_private;
2467 int level, max_level = ilk_wm_max_level(dev);
2468 /* LP0 watermark maximums depend on this pipe alone */
2469 struct intel_wm_config config = {
2470 .num_pipes_active = 1,
2471 .sprites_enabled = params->spr.enabled,
2472 .sprites_scaled = params->spr.scaled,
2473 };
2474 struct ilk_wm_maximums max;
2475
2476 pipe_wm->pipe_enabled = params->active;
2477 pipe_wm->sprites_enabled = params->spr.enabled;
2478 pipe_wm->sprites_scaled = params->spr.scaled;
2479
2480 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2481 if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled)
2482 max_level = 1;
2483
2484 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2485 if (params->spr.scaled)
2486 max_level = 0;
2487
2488 ilk_compute_wm_level(dev_priv, 0, params, &pipe_wm->wm[0]);
2489
2490 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2491 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
2492
2493 /* LP0 watermarks always use 1/2 DDB partitioning */
2494 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2495
2496 /* At least LP0 must be valid */
2497 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
2498 return false;
2499
2500 ilk_compute_wm_reg_maximums(dev, 1, &max);
2501
2502 for (level = 1; level <= max_level; level++) {
2503 struct intel_wm_level wm = {};
2504
2505 ilk_compute_wm_level(dev_priv, level, params, &wm);
2506
2507 /*
2508 * Disable any watermark level that exceeds the
2509 * register maximums since such watermarks are
2510 * always invalid.
2511 */
2512 if (!ilk_validate_wm_level(level, &max, &wm))
2513 break;
2514
2515 pipe_wm->wm[level] = wm;
2516 }
2517
2518 return true;
2519 }
2520
2521 /*
2522 * Merge the watermarks from all active pipes for a specific level.
2523 */
2524 static void ilk_merge_wm_level(struct drm_device *dev,
2525 int level,
2526 struct intel_wm_level *ret_wm)
2527 {
2528 const struct intel_crtc *intel_crtc;
2529
2530 ret_wm->enable = true;
2531
2532 for_each_intel_crtc(dev, intel_crtc) {
2533 const struct intel_pipe_wm *active = &intel_crtc->wm.active;
2534 const struct intel_wm_level *wm = &active->wm[level];
2535
2536 if (!active->pipe_enabled)
2537 continue;
2538
2539 /*
2540 * The watermark values may have been used in the past,
2541 * so we must maintain them in the registers for some
2542 * time even if the level is now disabled.
2543 */
2544 if (!wm->enable)
2545 ret_wm->enable = false;
2546
2547 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2548 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2549 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2550 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2551 }
2552 }
2553
2554 /*
2555 * Merge all low power watermarks for all active pipes.
2556 */
2557 static void ilk_wm_merge(struct drm_device *dev,
2558 const struct intel_wm_config *config,
2559 const struct ilk_wm_maximums *max,
2560 struct intel_pipe_wm *merged)
2561 {
2562 int level, max_level = ilk_wm_max_level(dev);
2563 int last_enabled_level = max_level;
2564
2565 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2566 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2567 config->num_pipes_active > 1)
2568 return;
2569
2570 /* ILK: FBC WM must be disabled always */
2571 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
2572
2573 /* merge each WM1+ level */
2574 for (level = 1; level <= max_level; level++) {
2575 struct intel_wm_level *wm = &merged->wm[level];
2576
2577 ilk_merge_wm_level(dev, level, wm);
2578
2579 if (level > last_enabled_level)
2580 wm->enable = false;
2581 else if (!ilk_validate_wm_level(level, max, wm))
2582 /* make sure all following levels get disabled */
2583 last_enabled_level = level - 1;
2584
2585 /*
2586 * The spec says it is preferred to disable
2587 * FBC WMs instead of disabling a WM level.
2588 */
2589 if (wm->fbc_val > max->fbc) {
2590 if (wm->enable)
2591 merged->fbc_wm_enabled = false;
2592 wm->fbc_val = 0;
2593 }
2594 }
2595
2596 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2597 /*
2598 * FIXME this is racy. FBC might get enabled later.
2599 * What we should check here is whether FBC can be
2600 * enabled sometime later.
2601 */
2602 if (IS_GEN5(dev) && !merged->fbc_wm_enabled && intel_fbc_enabled(dev)) {
2603 for (level = 2; level <= max_level; level++) {
2604 struct intel_wm_level *wm = &merged->wm[level];
2605
2606 wm->enable = false;
2607 }
2608 }
2609 }
2610
2611 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2612 {
2613 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2614 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2615 }
2616
2617 /* The value we need to program into the WM_LPx latency field */
2618 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2619 {
2620 struct drm_i915_private *dev_priv = dev->dev_private;
2621
2622 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2623 return 2 * level;
2624 else
2625 return dev_priv->wm.pri_latency[level];
2626 }
2627
2628 static void ilk_compute_wm_results(struct drm_device *dev,
2629 const struct intel_pipe_wm *merged,
2630 enum intel_ddb_partitioning partitioning,
2631 struct ilk_wm_values *results)
2632 {
2633 struct intel_crtc *intel_crtc;
2634 int level, wm_lp;
2635
2636 results->enable_fbc_wm = merged->fbc_wm_enabled;
2637 results->partitioning = partitioning;
2638
2639 /* LP1+ register values */
2640 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2641 const struct intel_wm_level *r;
2642
2643 level = ilk_wm_lp_to_level(wm_lp, merged);
2644
2645 r = &merged->wm[level];
2646
2647 /*
2648 * Maintain the watermark values even if the level is
2649 * disabled. Doing otherwise could cause underruns.
2650 */
2651 results->wm_lp[wm_lp - 1] =
2652 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2653 (r->pri_val << WM1_LP_SR_SHIFT) |
2654 r->cur_val;
2655
2656 if (r->enable)
2657 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2658
2659 if (INTEL_INFO(dev)->gen >= 8)
2660 results->wm_lp[wm_lp - 1] |=
2661 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2662 else
2663 results->wm_lp[wm_lp - 1] |=
2664 r->fbc_val << WM1_LP_FBC_SHIFT;
2665
2666 /*
2667 * Always set WM1S_LP_EN when spr_val != 0, even if the
2668 * level is disabled. Doing otherwise could cause underruns.
2669 */
2670 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2671 WARN_ON(wm_lp != 1);
2672 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2673 } else
2674 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2675 }
2676
2677 /* LP0 register values */
2678 for_each_intel_crtc(dev, intel_crtc) {
2679 enum pipe pipe = intel_crtc->pipe;
2680 const struct intel_wm_level *r =
2681 &intel_crtc->wm.active.wm[0];
2682
2683 if (WARN_ON(!r->enable))
2684 continue;
2685
2686 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
2687
2688 results->wm_pipe[pipe] =
2689 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2690 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2691 r->cur_val;
2692 }
2693 }
2694
2695 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2696 * case both are at the same level. Prefer r1 in case they're the same. */
2697 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2698 struct intel_pipe_wm *r1,
2699 struct intel_pipe_wm *r2)
2700 {
2701 int level, max_level = ilk_wm_max_level(dev);
2702 int level1 = 0, level2 = 0;
2703
2704 for (level = 1; level <= max_level; level++) {
2705 if (r1->wm[level].enable)
2706 level1 = level;
2707 if (r2->wm[level].enable)
2708 level2 = level;
2709 }
2710
2711 if (level1 == level2) {
2712 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2713 return r2;
2714 else
2715 return r1;
2716 } else if (level1 > level2) {
2717 return r1;
2718 } else {
2719 return r2;
2720 }
2721 }
2722
2723 /* dirty bits used to track which watermarks need changes */
2724 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2725 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2726 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2727 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2728 #define WM_DIRTY_FBC (1 << 24)
2729 #define WM_DIRTY_DDB (1 << 25)
2730
2731 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
2732 const struct ilk_wm_values *old,
2733 const struct ilk_wm_values *new)
2734 {
2735 unsigned int dirty = 0;
2736 enum pipe pipe;
2737 int wm_lp;
2738
2739 for_each_pipe(dev_priv, pipe) {
2740 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2741 dirty |= WM_DIRTY_LINETIME(pipe);
2742 /* Must disable LP1+ watermarks too */
2743 dirty |= WM_DIRTY_LP_ALL;
2744 }
2745
2746 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2747 dirty |= WM_DIRTY_PIPE(pipe);
2748 /* Must disable LP1+ watermarks too */
2749 dirty |= WM_DIRTY_LP_ALL;
2750 }
2751 }
2752
2753 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2754 dirty |= WM_DIRTY_FBC;
2755 /* Must disable LP1+ watermarks too */
2756 dirty |= WM_DIRTY_LP_ALL;
2757 }
2758
2759 if (old->partitioning != new->partitioning) {
2760 dirty |= WM_DIRTY_DDB;
2761 /* Must disable LP1+ watermarks too */
2762 dirty |= WM_DIRTY_LP_ALL;
2763 }
2764
2765 /* LP1+ watermarks already deemed dirty, no need to continue */
2766 if (dirty & WM_DIRTY_LP_ALL)
2767 return dirty;
2768
2769 /* Find the lowest numbered LP1+ watermark in need of an update... */
2770 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2771 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2772 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2773 break;
2774 }
2775
2776 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2777 for (; wm_lp <= 3; wm_lp++)
2778 dirty |= WM_DIRTY_LP(wm_lp);
2779
2780 return dirty;
2781 }
2782
2783 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2784 unsigned int dirty)
2785 {
2786 struct ilk_wm_values *previous = &dev_priv->wm.hw;
2787 bool changed = false;
2788
2789 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2790 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2791 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2792 changed = true;
2793 }
2794 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2795 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2796 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2797 changed = true;
2798 }
2799 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2800 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2801 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2802 changed = true;
2803 }
2804
2805 /*
2806 * Don't touch WM1S_LP_EN here.
2807 * Doing so could cause underruns.
2808 */
2809
2810 return changed;
2811 }
2812
2813 /*
2814 * The spec says we shouldn't write when we don't need, because every write
2815 * causes WMs to be re-evaluated, expending some power.
2816 */
2817 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2818 struct ilk_wm_values *results)
2819 {
2820 struct drm_device *dev = dev_priv->dev;
2821 struct ilk_wm_values *previous = &dev_priv->wm.hw;
2822 unsigned int dirty;
2823 uint32_t val;
2824
2825 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
2826 if (!dirty)
2827 return;
2828
2829 _ilk_disable_lp_wm(dev_priv, dirty);
2830
2831 if (dirty & WM_DIRTY_PIPE(PIPE_A))
2832 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2833 if (dirty & WM_DIRTY_PIPE(PIPE_B))
2834 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2835 if (dirty & WM_DIRTY_PIPE(PIPE_C))
2836 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2837
2838 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2839 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2840 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2841 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2842 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2843 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2844
2845 if (dirty & WM_DIRTY_DDB) {
2846 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2847 val = I915_READ(WM_MISC);
2848 if (results->partitioning == INTEL_DDB_PART_1_2)
2849 val &= ~WM_MISC_DATA_PARTITION_5_6;
2850 else
2851 val |= WM_MISC_DATA_PARTITION_5_6;
2852 I915_WRITE(WM_MISC, val);
2853 } else {
2854 val = I915_READ(DISP_ARB_CTL2);
2855 if (results->partitioning == INTEL_DDB_PART_1_2)
2856 val &= ~DISP_DATA_PARTITION_5_6;
2857 else
2858 val |= DISP_DATA_PARTITION_5_6;
2859 I915_WRITE(DISP_ARB_CTL2, val);
2860 }
2861 }
2862
2863 if (dirty & WM_DIRTY_FBC) {
2864 val = I915_READ(DISP_ARB_CTL);
2865 if (results->enable_fbc_wm)
2866 val &= ~DISP_FBC_WM_DIS;
2867 else
2868 val |= DISP_FBC_WM_DIS;
2869 I915_WRITE(DISP_ARB_CTL, val);
2870 }
2871
2872 if (dirty & WM_DIRTY_LP(1) &&
2873 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2874 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2875
2876 if (INTEL_INFO(dev)->gen >= 7) {
2877 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2878 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2879 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2880 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2881 }
2882
2883 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2884 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2885 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2886 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2887 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2888 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2889
2890 dev_priv->wm.hw = *results;
2891 }
2892
2893 static bool ilk_disable_lp_wm(struct drm_device *dev)
2894 {
2895 struct drm_i915_private *dev_priv = dev->dev_private;
2896
2897 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2898 }
2899
2900 static void ilk_update_wm(struct drm_crtc *crtc)
2901 {
2902 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2903 struct drm_device *dev = crtc->dev;
2904 struct drm_i915_private *dev_priv = dev->dev_private;
2905 struct ilk_wm_maximums max;
2906 struct ilk_pipe_wm_parameters params = {};
2907 struct ilk_wm_values results = {};
2908 enum intel_ddb_partitioning partitioning;
2909 struct intel_pipe_wm pipe_wm = {};
2910 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
2911 struct intel_wm_config config = {};
2912
2913 ilk_compute_wm_parameters(crtc, &params);
2914
2915 intel_compute_pipe_wm(crtc, &params, &pipe_wm);
2916
2917 if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
2918 return;
2919
2920 intel_crtc->wm.active = pipe_wm;
2921
2922 ilk_compute_wm_config(dev, &config);
2923
2924 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
2925 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
2926
2927 /* 5/6 split only in single pipe config on IVB+ */
2928 if (INTEL_INFO(dev)->gen >= 7 &&
2929 config.num_pipes_active == 1 && config.sprites_enabled) {
2930 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
2931 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
2932
2933 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
2934 } else {
2935 best_lp_wm = &lp_wm_1_2;
2936 }
2937
2938 partitioning = (best_lp_wm == &lp_wm_1_2) ?
2939 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
2940
2941 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
2942
2943 ilk_write_wm_values(dev_priv, &results);
2944 }
2945
2946 static void
2947 ilk_update_sprite_wm(struct drm_plane *plane,
2948 struct drm_crtc *crtc,
2949 uint32_t sprite_width, uint32_t sprite_height,
2950 int pixel_size, bool enabled, bool scaled)
2951 {
2952 struct drm_device *dev = plane->dev;
2953 struct intel_plane *intel_plane = to_intel_plane(plane);
2954
2955 intel_plane->wm.enabled = enabled;
2956 intel_plane->wm.scaled = scaled;
2957 intel_plane->wm.horiz_pixels = sprite_width;
2958 intel_plane->wm.vert_pixels = sprite_width;
2959 intel_plane->wm.bytes_per_pixel = pixel_size;
2960
2961 /*
2962 * IVB workaround: must disable low power watermarks for at least
2963 * one frame before enabling scaling. LP watermarks can be re-enabled
2964 * when scaling is disabled.
2965 *
2966 * WaCxSRDisabledForSpriteScaling:ivb
2967 */
2968 if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev))
2969 intel_wait_for_vblank(dev, intel_plane->pipe);
2970
2971 ilk_update_wm(crtc);
2972 }
2973
2974 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
2975 {
2976 struct drm_device *dev = crtc->dev;
2977 struct drm_i915_private *dev_priv = dev->dev_private;
2978 struct ilk_wm_values *hw = &dev_priv->wm.hw;
2979 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2980 struct intel_pipe_wm *active = &intel_crtc->wm.active;
2981 enum pipe pipe = intel_crtc->pipe;
2982 static const unsigned int wm0_pipe_reg[] = {
2983 [PIPE_A] = WM0_PIPEA_ILK,
2984 [PIPE_B] = WM0_PIPEB_ILK,
2985 [PIPE_C] = WM0_PIPEC_IVB,
2986 };
2987
2988 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
2989 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2990 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
2991
2992 active->pipe_enabled = intel_crtc_active(crtc);
2993
2994 if (active->pipe_enabled) {
2995 u32 tmp = hw->wm_pipe[pipe];
2996
2997 /*
2998 * For active pipes LP0 watermark is marked as
2999 * enabled, and LP1+ watermaks as disabled since
3000 * we can't really reverse compute them in case
3001 * multiple pipes are active.
3002 */
3003 active->wm[0].enable = true;
3004 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3005 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3006 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3007 active->linetime = hw->wm_linetime[pipe];
3008 } else {
3009 int level, max_level = ilk_wm_max_level(dev);
3010
3011 /*
3012 * For inactive pipes, all watermark levels
3013 * should be marked as enabled but zeroed,
3014 * which is what we'd compute them to.
3015 */
3016 for (level = 0; level <= max_level; level++)
3017 active->wm[level].enable = true;
3018 }
3019 }
3020
3021 void ilk_wm_get_hw_state(struct drm_device *dev)
3022 {
3023 struct drm_i915_private *dev_priv = dev->dev_private;
3024 struct ilk_wm_values *hw = &dev_priv->wm.hw;
3025 struct drm_crtc *crtc;
3026
3027 for_each_crtc(dev, crtc)
3028 ilk_pipe_wm_get_hw_state(crtc);
3029
3030 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
3031 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
3032 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
3033
3034 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
3035 if (INTEL_INFO(dev)->gen >= 7) {
3036 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
3037 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
3038 }
3039
3040 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3041 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
3042 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
3043 else if (IS_IVYBRIDGE(dev))
3044 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
3045 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
3046
3047 hw->enable_fbc_wm =
3048 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
3049 }
3050
3051 /**
3052 * intel_update_watermarks - update FIFO watermark values based on current modes
3053 *
3054 * Calculate watermark values for the various WM regs based on current mode
3055 * and plane configuration.
3056 *
3057 * There are several cases to deal with here:
3058 * - normal (i.e. non-self-refresh)
3059 * - self-refresh (SR) mode
3060 * - lines are large relative to FIFO size (buffer can hold up to 2)
3061 * - lines are small relative to FIFO size (buffer can hold more than 2
3062 * lines), so need to account for TLB latency
3063 *
3064 * The normal calculation is:
3065 * watermark = dotclock * bytes per pixel * latency
3066 * where latency is platform & configuration dependent (we assume pessimal
3067 * values here).
3068 *
3069 * The SR calculation is:
3070 * watermark = (trunc(latency/line time)+1) * surface width *
3071 * bytes per pixel
3072 * where
3073 * line time = htotal / dotclock
3074 * surface width = hdisplay for normal plane and 64 for cursor
3075 * and latency is assumed to be high, as above.
3076 *
3077 * The final value programmed to the register should always be rounded up,
3078 * and include an extra 2 entries to account for clock crossings.
3079 *
3080 * We don't use the sprite, so we can ignore that. And on Crestline we have
3081 * to set the non-SR watermarks to 8.
3082 */
3083 void intel_update_watermarks(struct drm_crtc *crtc)
3084 {
3085 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
3086
3087 if (dev_priv->display.update_wm)
3088 dev_priv->display.update_wm(crtc);
3089 }
3090
3091 void intel_update_sprite_watermarks(struct drm_plane *plane,
3092 struct drm_crtc *crtc,
3093 uint32_t sprite_width,
3094 uint32_t sprite_height,
3095 int pixel_size,
3096 bool enabled, bool scaled)
3097 {
3098 struct drm_i915_private *dev_priv = plane->dev->dev_private;
3099
3100 if (dev_priv->display.update_sprite_wm)
3101 dev_priv->display.update_sprite_wm(plane, crtc,
3102 sprite_width, sprite_height,
3103 pixel_size, enabled, scaled);
3104 }
3105
3106 static struct drm_i915_gem_object *
3107 intel_alloc_context_page(struct drm_device *dev)
3108 {
3109 struct drm_i915_gem_object *ctx;
3110 int ret;
3111
3112 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3113
3114 ctx = i915_gem_alloc_object(dev, 4096);
3115 if (!ctx) {
3116 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
3117 return NULL;
3118 }
3119
3120 ret = i915_gem_obj_ggtt_pin(ctx, 4096, 0);
3121 if (ret) {
3122 DRM_ERROR("failed to pin power context: %d\n", ret);
3123 goto err_unref;
3124 }
3125
3126 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
3127 if (ret) {
3128 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
3129 goto err_unpin;
3130 }
3131
3132 return ctx;
3133
3134 err_unpin:
3135 i915_gem_object_ggtt_unpin(ctx);
3136 err_unref:
3137 drm_gem_object_unreference(&ctx->base);
3138 return NULL;
3139 }
3140
3141 /**
3142 * Lock protecting IPS related data structures
3143 */
3144 DEFINE_SPINLOCK(mchdev_lock);
3145
3146 /* Global for IPS driver to get at the current i915 device. Protected by
3147 * mchdev_lock. */
3148 static struct drm_i915_private *i915_mch_dev;
3149
3150 bool ironlake_set_drps(struct drm_device *dev, u8 val)
3151 {
3152 struct drm_i915_private *dev_priv = dev->dev_private;
3153 u16 rgvswctl;
3154
3155 assert_spin_locked(&mchdev_lock);
3156
3157 rgvswctl = I915_READ16(MEMSWCTL);
3158 if (rgvswctl & MEMCTL_CMD_STS) {
3159 DRM_DEBUG("gpu busy, RCS change rejected\n");
3160 return false; /* still busy with another command */
3161 }
3162
3163 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
3164 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
3165 I915_WRITE16(MEMSWCTL, rgvswctl);
3166 POSTING_READ16(MEMSWCTL);
3167
3168 rgvswctl |= MEMCTL_CMD_STS;
3169 I915_WRITE16(MEMSWCTL, rgvswctl);
3170
3171 return true;
3172 }
3173
3174 static void ironlake_enable_drps(struct drm_device *dev)
3175 {
3176 struct drm_i915_private *dev_priv = dev->dev_private;
3177 u32 rgvmodectl = I915_READ(MEMMODECTL);
3178 u8 fmax, fmin, fstart, vstart;
3179
3180 spin_lock_irq(&mchdev_lock);
3181
3182 /* Enable temp reporting */
3183 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
3184 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
3185
3186 /* 100ms RC evaluation intervals */
3187 I915_WRITE(RCUPEI, 100000);
3188 I915_WRITE(RCDNEI, 100000);
3189
3190 /* Set max/min thresholds to 90ms and 80ms respectively */
3191 I915_WRITE(RCBMAXAVG, 90000);
3192 I915_WRITE(RCBMINAVG, 80000);
3193
3194 I915_WRITE(MEMIHYST, 1);
3195
3196 /* Set up min, max, and cur for interrupt handling */
3197 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
3198 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
3199 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
3200 MEMMODE_FSTART_SHIFT;
3201
3202 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
3203 PXVFREQ_PX_SHIFT;
3204
3205 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
3206 dev_priv->ips.fstart = fstart;
3207
3208 dev_priv->ips.max_delay = fstart;
3209 dev_priv->ips.min_delay = fmin;
3210 dev_priv->ips.cur_delay = fstart;
3211
3212 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
3213 fmax, fmin, fstart);
3214
3215 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
3216
3217 /*
3218 * Interrupts will be enabled in ironlake_irq_postinstall
3219 */
3220
3221 I915_WRITE(VIDSTART, vstart);
3222 POSTING_READ(VIDSTART);
3223
3224 rgvmodectl |= MEMMODE_SWMODE_EN;
3225 I915_WRITE(MEMMODECTL, rgvmodectl);
3226
3227 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
3228 DRM_ERROR("stuck trying to change perf mode\n");
3229 mdelay(1);
3230
3231 ironlake_set_drps(dev, fstart);
3232
3233 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
3234 I915_READ(0x112e0);
3235 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
3236 dev_priv->ips.last_count2 = I915_READ(0x112f4);
3237 dev_priv->ips.last_time2 = ktime_get_raw_ns();
3238
3239 spin_unlock_irq(&mchdev_lock);
3240 }
3241
3242 static void ironlake_disable_drps(struct drm_device *dev)
3243 {
3244 struct drm_i915_private *dev_priv = dev->dev_private;
3245 u16 rgvswctl;
3246
3247 spin_lock_irq(&mchdev_lock);
3248
3249 rgvswctl = I915_READ16(MEMSWCTL);
3250
3251 /* Ack interrupts, disable EFC interrupt */
3252 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
3253 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
3254 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
3255 I915_WRITE(DEIIR, DE_PCU_EVENT);
3256 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
3257
3258 /* Go back to the starting frequency */
3259 ironlake_set_drps(dev, dev_priv->ips.fstart);
3260 mdelay(1);
3261 rgvswctl |= MEMCTL_CMD_STS;
3262 I915_WRITE(MEMSWCTL, rgvswctl);
3263 mdelay(1);
3264
3265 spin_unlock_irq(&mchdev_lock);
3266 }
3267
3268 /* There's a funny hw issue where the hw returns all 0 when reading from
3269 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3270 * ourselves, instead of doing a rmw cycle (which might result in us clearing
3271 * all limits and the gpu stuck at whatever frequency it is at atm).
3272 */
3273 static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)
3274 {
3275 u32 limits;
3276
3277 /* Only set the down limit when we've reached the lowest level to avoid
3278 * getting more interrupts, otherwise leave this clear. This prevents a
3279 * race in the hw when coming out of rc6: There's a tiny window where
3280 * the hw runs at the minimal clock before selecting the desired
3281 * frequency, if the down threshold expires in that window we will not
3282 * receive a down interrupt. */
3283 limits = dev_priv->rps.max_freq_softlimit << 24;
3284 if (val <= dev_priv->rps.min_freq_softlimit)
3285 limits |= dev_priv->rps.min_freq_softlimit << 16;
3286
3287 return limits;
3288 }
3289
3290 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
3291 {
3292 int new_power;
3293
3294 if (dev_priv->rps.is_bdw_sw_turbo)
3295 return;
3296
3297 new_power = dev_priv->rps.power;
3298 switch (dev_priv->rps.power) {
3299 case LOW_POWER:
3300 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
3301 new_power = BETWEEN;
3302 break;
3303
3304 case BETWEEN:
3305 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
3306 new_power = LOW_POWER;
3307 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
3308 new_power = HIGH_POWER;
3309 break;
3310
3311 case HIGH_POWER:
3312 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
3313 new_power = BETWEEN;
3314 break;
3315 }
3316 /* Max/min bins are special */
3317 if (val == dev_priv->rps.min_freq_softlimit)
3318 new_power = LOW_POWER;
3319 if (val == dev_priv->rps.max_freq_softlimit)
3320 new_power = HIGH_POWER;
3321 if (new_power == dev_priv->rps.power)
3322 return;
3323
3324 /* Note the units here are not exactly 1us, but 1280ns. */
3325 switch (new_power) {
3326 case LOW_POWER:
3327 /* Upclock if more than 95% busy over 16ms */
3328 I915_WRITE(GEN6_RP_UP_EI, 12500);
3329 I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800);
3330
3331 /* Downclock if less than 85% busy over 32ms */
3332 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3333 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250);
3334
3335 I915_WRITE(GEN6_RP_CONTROL,
3336 GEN6_RP_MEDIA_TURBO |
3337 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3338 GEN6_RP_MEDIA_IS_GFX |
3339 GEN6_RP_ENABLE |
3340 GEN6_RP_UP_BUSY_AVG |
3341 GEN6_RP_DOWN_IDLE_AVG);
3342 break;
3343
3344 case BETWEEN:
3345 /* Upclock if more than 90% busy over 13ms */
3346 I915_WRITE(GEN6_RP_UP_EI, 10250);
3347 I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225);
3348
3349 /* Downclock if less than 75% busy over 32ms */
3350 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3351 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750);
3352
3353 I915_WRITE(GEN6_RP_CONTROL,
3354 GEN6_RP_MEDIA_TURBO |
3355 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3356 GEN6_RP_MEDIA_IS_GFX |
3357 GEN6_RP_ENABLE |
3358 GEN6_RP_UP_BUSY_AVG |
3359 GEN6_RP_DOWN_IDLE_AVG);
3360 break;
3361
3362 case HIGH_POWER:
3363 /* Upclock if more than 85% busy over 10ms */
3364 I915_WRITE(GEN6_RP_UP_EI, 8000);
3365 I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800);
3366
3367 /* Downclock if less than 60% busy over 32ms */
3368 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3369 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000);
3370
3371 I915_WRITE(GEN6_RP_CONTROL,
3372 GEN6_RP_MEDIA_TURBO |
3373 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3374 GEN6_RP_MEDIA_IS_GFX |
3375 GEN6_RP_ENABLE |
3376 GEN6_RP_UP_BUSY_AVG |
3377 GEN6_RP_DOWN_IDLE_AVG);
3378 break;
3379 }
3380
3381 dev_priv->rps.power = new_power;
3382 dev_priv->rps.last_adj = 0;
3383 }
3384
3385 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
3386 {
3387 u32 mask = 0;
3388
3389 if (val > dev_priv->rps.min_freq_softlimit)
3390 mask |= GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
3391 if (val < dev_priv->rps.max_freq_softlimit)
3392 mask |= GEN6_PM_RP_UP_THRESHOLD;
3393
3394 mask |= dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED);
3395 mask &= dev_priv->pm_rps_events;
3396
3397 /* IVB and SNB hard hangs on looping batchbuffer
3398 * if GEN6_PM_UP_EI_EXPIRED is masked.
3399 */
3400 if (INTEL_INFO(dev_priv->dev)->gen <= 7 && !IS_HASWELL(dev_priv->dev))
3401 mask |= GEN6_PM_RP_UP_EI_EXPIRED;
3402
3403 if (IS_GEN8(dev_priv->dev))
3404 mask |= GEN8_PMINTR_REDIRECT_TO_NON_DISP;
3405
3406 return ~mask;
3407 }
3408
3409 /* gen6_set_rps is called to update the frequency request, but should also be
3410 * called when the range (min_delay and max_delay) is modified so that we can
3411 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
3412 void gen6_set_rps(struct drm_device *dev, u8 val)
3413 {
3414 struct drm_i915_private *dev_priv = dev->dev_private;
3415
3416 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3417 WARN_ON(val > dev_priv->rps.max_freq_softlimit);
3418 WARN_ON(val < dev_priv->rps.min_freq_softlimit);
3419
3420 /* min/max delay may still have been modified so be sure to
3421 * write the limits value.
3422 */
3423 if (val != dev_priv->rps.cur_freq) {
3424 gen6_set_rps_thresholds(dev_priv, val);
3425
3426 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3427 I915_WRITE(GEN6_RPNSWREQ,
3428 HSW_FREQUENCY(val));
3429 else
3430 I915_WRITE(GEN6_RPNSWREQ,
3431 GEN6_FREQUENCY(val) |
3432 GEN6_OFFSET(0) |
3433 GEN6_AGGRESSIVE_TURBO);
3434 }
3435
3436 /* Make sure we continue to get interrupts
3437 * until we hit the minimum or maximum frequencies.
3438 */
3439 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, gen6_rps_limits(dev_priv, val));
3440 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
3441
3442 POSTING_READ(GEN6_RPNSWREQ);
3443
3444 dev_priv->rps.cur_freq = val;
3445 trace_intel_gpu_freq_change(val * 50);
3446 }
3447
3448 /* vlv_set_rps_idle: Set the frequency to Rpn if Gfx clocks are down
3449 *
3450 * * If Gfx is Idle, then
3451 * 1. Mask Turbo interrupts
3452 * 2. Bring up Gfx clock
3453 * 3. Change the freq to Rpn and wait till P-Unit updates freq
3454 * 4. Clear the Force GFX CLK ON bit so that Gfx can down
3455 * 5. Unmask Turbo interrupts
3456 */
3457 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
3458 {
3459 struct drm_device *dev = dev_priv->dev;
3460
3461 /* Latest VLV doesn't need to force the gfx clock */
3462 if (dev->pdev->revision >= 0xd) {
3463 valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3464 return;
3465 }
3466
3467 /*
3468 * When we are idle. Drop to min voltage state.
3469 */
3470
3471 if (dev_priv->rps.cur_freq <= dev_priv->rps.min_freq_softlimit)
3472 return;
3473
3474 /* Mask turbo interrupt so that they will not come in between */
3475 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3476
3477 vlv_force_gfx_clock(dev_priv, true);
3478
3479 dev_priv->rps.cur_freq = dev_priv->rps.min_freq_softlimit;
3480
3481 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ,
3482 dev_priv->rps.min_freq_softlimit);
3483
3484 if (wait_for(((vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS))
3485 & GENFREQSTATUS) == 0, 5))
3486 DRM_ERROR("timed out waiting for Punit\n");
3487
3488 vlv_force_gfx_clock(dev_priv, false);
3489
3490 I915_WRITE(GEN6_PMINTRMSK,
3491 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
3492 }
3493
3494 void gen6_rps_idle(struct drm_i915_private *dev_priv)
3495 {
3496 struct drm_device *dev = dev_priv->dev;
3497
3498 mutex_lock(&dev_priv->rps.hw_lock);
3499 if (dev_priv->rps.enabled) {
3500 if (IS_CHERRYVIEW(dev))
3501 valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3502 else if (IS_VALLEYVIEW(dev))
3503 vlv_set_rps_idle(dev_priv);
3504 else if (!dev_priv->rps.is_bdw_sw_turbo
3505 || atomic_read(&dev_priv->rps.sw_turbo.flip_received)){
3506 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3507 }
3508
3509 dev_priv->rps.last_adj = 0;
3510 }
3511 mutex_unlock(&dev_priv->rps.hw_lock);
3512 }
3513
3514 void gen6_rps_boost(struct drm_i915_private *dev_priv)
3515 {
3516 struct drm_device *dev = dev_priv->dev;
3517
3518 mutex_lock(&dev_priv->rps.hw_lock);
3519 if (dev_priv->rps.enabled) {
3520 if (IS_VALLEYVIEW(dev))
3521 valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
3522 else if (!dev_priv->rps.is_bdw_sw_turbo
3523 || atomic_read(&dev_priv->rps.sw_turbo.flip_received)){
3524 gen6_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
3525 }
3526
3527 dev_priv->rps.last_adj = 0;
3528 }
3529 mutex_unlock(&dev_priv->rps.hw_lock);
3530 }
3531
3532 void valleyview_set_rps(struct drm_device *dev, u8 val)
3533 {
3534 struct drm_i915_private *dev_priv = dev->dev_private;
3535
3536 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3537 WARN_ON(val > dev_priv->rps.max_freq_softlimit);
3538 WARN_ON(val < dev_priv->rps.min_freq_softlimit);
3539
3540 DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
3541 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
3542 dev_priv->rps.cur_freq,
3543 vlv_gpu_freq(dev_priv, val), val);
3544
3545 if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1),
3546 "Odd GPU freq value\n"))
3547 val &= ~1;
3548
3549 if (val != dev_priv->rps.cur_freq)
3550 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
3551
3552 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
3553
3554 dev_priv->rps.cur_freq = val;
3555 trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val));
3556 }
3557
3558 static void gen8_disable_rps_interrupts(struct drm_device *dev)
3559 {
3560 struct drm_i915_private *dev_priv = dev->dev_private;
3561 if (IS_BROADWELL(dev) && dev_priv->rps.is_bdw_sw_turbo){
3562 if (atomic_read(&dev_priv->rps.sw_turbo.flip_received))
3563 del_timer(&dev_priv->rps.sw_turbo.flip_timer);
3564 dev_priv-> rps.is_bdw_sw_turbo = false;
3565 } else {
3566 I915_WRITE(GEN6_PMINTRMSK, ~GEN8_PMINTR_REDIRECT_TO_NON_DISP);
3567 I915_WRITE(GEN8_GT_IER(2), I915_READ(GEN8_GT_IER(2)) &
3568 ~dev_priv->pm_rps_events);
3569 /* Complete PM interrupt masking here doesn't race with the rps work
3570 * item again unmasking PM interrupts because that is using a different
3571 * register (GEN8_GT_IMR(2)) to mask PM interrupts. The only risk is in
3572 * leaving stale bits in GEN8_GT_IIR(2) and GEN8_GT_IMR(2) which
3573 * gen8_enable_rps will clean up. */
3574
3575 spin_lock_irq(&dev_priv->irq_lock);
3576 dev_priv->rps.pm_iir = 0;
3577 spin_unlock_irq(&dev_priv->irq_lock);
3578
3579 I915_WRITE(GEN8_GT_IIR(2), dev_priv->pm_rps_events);
3580 }
3581 }
3582
3583 static void gen6_disable_rps_interrupts(struct drm_device *dev)
3584 {
3585 struct drm_i915_private *dev_priv = dev->dev_private;
3586
3587 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3588 I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) &
3589 ~dev_priv->pm_rps_events);
3590 /* Complete PM interrupt masking here doesn't race with the rps work
3591 * item again unmasking PM interrupts because that is using a different
3592 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3593 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3594
3595 spin_lock_irq(&dev_priv->irq_lock);
3596 dev_priv->rps.pm_iir = 0;
3597 spin_unlock_irq(&dev_priv->irq_lock);
3598
3599 I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events);
3600 }
3601
3602 static void gen6_disable_rps(struct drm_device *dev)
3603 {
3604 struct drm_i915_private *dev_priv = dev->dev_private;
3605
3606 I915_WRITE(GEN6_RC_CONTROL, 0);
3607 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
3608
3609 if (IS_BROADWELL(dev))
3610 gen8_disable_rps_interrupts(dev);
3611 else
3612 gen6_disable_rps_interrupts(dev);
3613 }
3614
3615 static void cherryview_disable_rps(struct drm_device *dev)
3616 {
3617 struct drm_i915_private *dev_priv = dev->dev_private;
3618
3619 I915_WRITE(GEN6_RC_CONTROL, 0);
3620
3621 gen8_disable_rps_interrupts(dev);
3622 }
3623
3624 static void valleyview_disable_rps(struct drm_device *dev)
3625 {
3626 struct drm_i915_private *dev_priv = dev->dev_private;
3627
3628 /* we're doing forcewake before Disabling RC6,
3629 * This what the BIOS expects when going into suspend */
3630 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3631
3632 I915_WRITE(GEN6_RC_CONTROL, 0);
3633
3634 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3635
3636 gen6_disable_rps_interrupts(dev);
3637 }
3638
3639 static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
3640 {
3641 if (IS_VALLEYVIEW(dev)) {
3642 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
3643 mode = GEN6_RC_CTL_RC6_ENABLE;
3644 else
3645 mode = 0;
3646 }
3647 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
3648 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3649 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3650 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
3651 }
3652
3653 static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
3654 {
3655 /* No RC6 before Ironlake */
3656 if (INTEL_INFO(dev)->gen < 5)
3657 return 0;
3658
3659 /* RC6 is only on Ironlake mobile not on desktop */
3660 if (INTEL_INFO(dev)->gen == 5 && !IS_IRONLAKE_M(dev))
3661 return 0;
3662
3663 /* Respect the kernel parameter if it is set */
3664 if (enable_rc6 >= 0) {
3665 int mask;
3666
3667 if (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
3668 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
3669 INTEL_RC6pp_ENABLE;
3670 else
3671 mask = INTEL_RC6_ENABLE;
3672
3673 if ((enable_rc6 & mask) != enable_rc6)
3674 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
3675 enable_rc6 & mask, enable_rc6, mask);
3676
3677 return enable_rc6 & mask;
3678 }
3679
3680 /* Disable RC6 on Ironlake */
3681 if (INTEL_INFO(dev)->gen == 5)
3682 return 0;
3683
3684 if (IS_IVYBRIDGE(dev))
3685 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
3686
3687 return INTEL_RC6_ENABLE;
3688 }
3689
3690 int intel_enable_rc6(const struct drm_device *dev)
3691 {
3692 return i915.enable_rc6;
3693 }
3694
3695 static void gen8_enable_rps_interrupts(struct drm_device *dev)
3696 {
3697 struct drm_i915_private *dev_priv = dev->dev_private;
3698
3699 spin_lock_irq(&dev_priv->irq_lock);
3700 WARN_ON(dev_priv->rps.pm_iir);
3701 gen8_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
3702 I915_WRITE(GEN8_GT_IIR(2), dev_priv->pm_rps_events);
3703 spin_unlock_irq(&dev_priv->irq_lock);
3704 }
3705
3706 static void gen6_enable_rps_interrupts(struct drm_device *dev)
3707 {
3708 struct drm_i915_private *dev_priv = dev->dev_private;
3709
3710 spin_lock_irq(&dev_priv->irq_lock);
3711 WARN_ON(dev_priv->rps.pm_iir);
3712 gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
3713 I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events);
3714 spin_unlock_irq(&dev_priv->irq_lock);
3715 }
3716
3717 static void parse_rp_state_cap(struct drm_i915_private *dev_priv, u32 rp_state_cap)
3718 {
3719 /* All of these values are in units of 50MHz */
3720 dev_priv->rps.cur_freq = 0;
3721 /* static values from HW: RP0 < RPe < RP1 < RPn (min_freq) */
3722 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
3723 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
3724 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
3725 /* XXX: only BYT has a special efficient freq */
3726 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
3727 /* hw_max = RP0 until we check for overclocking */
3728 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
3729
3730 /* Preserve min/max settings in case of re-init */
3731 if (dev_priv->rps.max_freq_softlimit == 0)
3732 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
3733
3734 if (dev_priv->rps.min_freq_softlimit == 0)
3735 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
3736 }
3737
3738 static void bdw_sw_calculate_freq(struct drm_device *dev,
3739 struct intel_rps_bdw_cal *c, u32 *cur_time, u32 *c0)
3740 {
3741 struct drm_i915_private *dev_priv = dev->dev_private;
3742 u64 busy = 0;
3743 u32 busyness_pct = 0;
3744 u32 elapsed_time = 0;
3745 u16 new_freq = 0;
3746
3747 if (!c || !cur_time || !c0)
3748 return;
3749
3750 if (0 == c->last_c0)
3751 goto out;
3752
3753 /* Check Evaluation interval */
3754 elapsed_time = *cur_time - c->last_ts;
3755 if (elapsed_time < c->eval_interval)
3756 return;
3757
3758 mutex_lock(&dev_priv->rps.hw_lock);
3759
3760 /*
3761 * c0 unit in 32*1.28 usec, elapsed_time unit in 1 usec.
3762 * Whole busyness_pct calculation should be
3763 * busy = ((u64)(*c0 - c->last_c0) << 5 << 7) / 100;
3764 * busyness_pct = (u32)(busy * 100 / elapsed_time);
3765 * The final formula is to simplify CPU calculation
3766 */
3767 busy = (u64)(*c0 - c->last_c0) << 12;
3768 do_div(busy, elapsed_time);
3769 busyness_pct = (u32)busy;
3770
3771 if (c->is_up && busyness_pct >= c->it_threshold_pct)
3772 new_freq = (u16)dev_priv->rps.cur_freq + 3;
3773 if (!c->is_up && busyness_pct <= c->it_threshold_pct)
3774 new_freq = (u16)dev_priv->rps.cur_freq - 1;
3775
3776 /* Adjust to new frequency busyness and compare with threshold */
3777 if (0 != new_freq) {
3778 if (new_freq > dev_priv->rps.max_freq_softlimit)
3779 new_freq = dev_priv->rps.max_freq_softlimit;
3780 else if (new_freq < dev_priv->rps.min_freq_softlimit)
3781 new_freq = dev_priv->rps.min_freq_softlimit;
3782
3783 gen6_set_rps(dev, new_freq);
3784 }
3785
3786 mutex_unlock(&dev_priv->rps.hw_lock);
3787
3788 out:
3789 c->last_c0 = *c0;
3790 c->last_ts = *cur_time;
3791 }
3792
3793 static void gen8_set_frequency_RP0(struct work_struct *work)
3794 {
3795 struct intel_rps_bdw_turbo *p_bdw_turbo =
3796 container_of(work, struct intel_rps_bdw_turbo, work_max_freq);
3797 struct intel_gen6_power_mgmt *p_power_mgmt =
3798 container_of(p_bdw_turbo, struct intel_gen6_power_mgmt, sw_turbo);
3799 struct drm_i915_private *dev_priv =
3800 container_of(p_power_mgmt, struct drm_i915_private, rps);
3801
3802 mutex_lock(&dev_priv->rps.hw_lock);
3803 gen6_set_rps(dev_priv->dev, dev_priv->rps.rp0_freq);
3804 mutex_unlock(&dev_priv->rps.hw_lock);
3805 }
3806
3807 static void flip_active_timeout_handler(unsigned long var)
3808 {
3809 struct drm_i915_private *dev_priv = (struct drm_i915_private *) var;
3810
3811 del_timer(&dev_priv->rps.sw_turbo.flip_timer);
3812 atomic_set(&dev_priv->rps.sw_turbo.flip_received, false);
3813
3814 queue_work(dev_priv->wq, &dev_priv->rps.sw_turbo.work_max_freq);
3815 }
3816
3817 void bdw_software_turbo(struct drm_device *dev)
3818 {
3819 struct drm_i915_private *dev_priv = dev->dev_private;
3820
3821 u32 current_time = I915_READ(TIMESTAMP_CTR); /* unit in usec */
3822 u32 current_c0 = I915_READ(MCHBAR_PCU_C0); /* unit in 32*1.28 usec */
3823
3824 bdw_sw_calculate_freq(dev, &dev_priv->rps.sw_turbo.up,
3825 &current_time, &current_c0);
3826 bdw_sw_calculate_freq(dev, &dev_priv->rps.sw_turbo.down,
3827 &current_time, &current_c0);
3828 }
3829
3830 static void gen8_enable_rps(struct drm_device *dev)
3831 {
3832 struct drm_i915_private *dev_priv = dev->dev_private;
3833 struct intel_engine_cs *ring;
3834 uint32_t rc6_mask = 0, rp_state_cap;
3835 uint32_t threshold_up_pct, threshold_down_pct;
3836 uint32_t ei_up, ei_down; /* up and down evaluation interval */
3837 u32 rp_ctl_flag;
3838 int unused;
3839
3840 /* Use software Turbo for BDW */
3841 dev_priv->rps.is_bdw_sw_turbo = IS_BROADWELL(dev);
3842
3843 /* 1a: Software RC state - RC0 */
3844 I915_WRITE(GEN6_RC_STATE, 0);
3845
3846 /* 1c & 1d: Get forcewake during program sequence. Although the driver
3847 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
3848 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3849
3850 /* 2a: Disable RC states. */
3851 I915_WRITE(GEN6_RC_CONTROL, 0);
3852
3853 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3854 parse_rp_state_cap(dev_priv, rp_state_cap);
3855
3856 /* 2b: Program RC6 thresholds.*/
3857 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
3858 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
3859 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
3860 for_each_ring(ring, dev_priv, unused)
3861 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3862 I915_WRITE(GEN6_RC_SLEEP, 0);
3863 if (IS_BROADWELL(dev))
3864 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
3865 else
3866 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
3867
3868 /* 3: Enable RC6 */
3869 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
3870 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
3871 intel_print_rc6_info(dev, rc6_mask);
3872 if (IS_BROADWELL(dev))
3873 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
3874 GEN7_RC_CTL_TO_MODE |
3875 rc6_mask);
3876 else
3877 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
3878 GEN6_RC_CTL_EI_MODE(1) |
3879 rc6_mask);
3880
3881 /* 4 Program defaults and thresholds for RPS*/
3882 I915_WRITE(GEN6_RPNSWREQ,
3883 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
3884 I915_WRITE(GEN6_RC_VIDEO_FREQ,
3885 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
3886 ei_up = 84480; /* 84.48ms */
3887 ei_down = 448000;
3888 threshold_up_pct = 90; /* x percent busy */
3889 threshold_down_pct = 70;
3890
3891 if (dev_priv->rps.is_bdw_sw_turbo) {
3892 dev_priv->rps.sw_turbo.up.it_threshold_pct = threshold_up_pct;
3893 dev_priv->rps.sw_turbo.up.eval_interval = ei_up;
3894 dev_priv->rps.sw_turbo.up.is_up = true;
3895 dev_priv->rps.sw_turbo.up.last_ts = 0;
3896 dev_priv->rps.sw_turbo.up.last_c0 = 0;
3897
3898 dev_priv->rps.sw_turbo.down.it_threshold_pct = threshold_down_pct;
3899 dev_priv->rps.sw_turbo.down.eval_interval = ei_down;
3900 dev_priv->rps.sw_turbo.down.is_up = false;
3901 dev_priv->rps.sw_turbo.down.last_ts = 0;
3902 dev_priv->rps.sw_turbo.down.last_c0 = 0;
3903
3904 /* Start the timer to track if flip comes*/
3905 dev_priv->rps.sw_turbo.timeout = 200*1000; /* in us */
3906
3907 init_timer(&dev_priv->rps.sw_turbo.flip_timer);
3908 dev_priv->rps.sw_turbo.flip_timer.function = flip_active_timeout_handler;
3909 dev_priv->rps.sw_turbo.flip_timer.data = (unsigned long) dev_priv;
3910 dev_priv->rps.sw_turbo.flip_timer.expires =
3911 usecs_to_jiffies(dev_priv->rps.sw_turbo.timeout) + jiffies;
3912 add_timer(&dev_priv->rps.sw_turbo.flip_timer);
3913 INIT_WORK(&dev_priv->rps.sw_turbo.work_max_freq, gen8_set_frequency_RP0);
3914
3915 atomic_set(&dev_priv->rps.sw_turbo.flip_received, true);
3916 } else {
3917 /* NB: Docs say 1s, and 1000000 - which aren't equivalent
3918 * 1 second timeout*/
3919 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, FREQ_1_28_US(1000000));
3920
3921 /* Docs recommend 900MHz, and 300 MHz respectively */
3922 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
3923 dev_priv->rps.max_freq_softlimit << 24 |
3924 dev_priv->rps.min_freq_softlimit << 16);
3925
3926 I915_WRITE(GEN6_RP_UP_THRESHOLD,
3927 FREQ_1_28_US(ei_up * threshold_up_pct / 100));
3928 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
3929 FREQ_1_28_US(ei_down * threshold_down_pct / 100));
3930 I915_WRITE(GEN6_RP_UP_EI,
3931 FREQ_1_28_US(ei_up));
3932 I915_WRITE(GEN6_RP_DOWN_EI,
3933 FREQ_1_28_US(ei_down));
3934
3935 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3936 }
3937
3938 /* 5: Enable RPS */
3939 rp_ctl_flag = GEN6_RP_MEDIA_TURBO |
3940 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3941 GEN6_RP_MEDIA_IS_GFX |
3942 GEN6_RP_UP_BUSY_AVG |
3943 GEN6_RP_DOWN_IDLE_AVG;
3944 if (!dev_priv->rps.is_bdw_sw_turbo)
3945 rp_ctl_flag |= GEN6_RP_ENABLE;
3946
3947 I915_WRITE(GEN6_RP_CONTROL, rp_ctl_flag);
3948
3949 /* 6: Ring frequency + overclocking
3950 * (our driver does this later */
3951 gen6_set_rps(dev, (I915_READ(GEN6_GT_PERF_STATUS) & 0xff00) >> 8);
3952 if (!dev_priv->rps.is_bdw_sw_turbo)
3953 gen8_enable_rps_interrupts(dev);
3954
3955 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3956 }
3957
3958 static void gen6_enable_rps(struct drm_device *dev)
3959 {
3960 struct drm_i915_private *dev_priv = dev->dev_private;
3961 struct intel_engine_cs *ring;
3962 u32 rp_state_cap;
3963 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
3964 u32 gtfifodbg;
3965 int rc6_mode;
3966 int i, ret;
3967
3968 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3969
3970 /* Here begins a magic sequence of register writes to enable
3971 * auto-downclocking.
3972 *
3973 * Perhaps there might be some value in exposing these to
3974 * userspace...
3975 */
3976 I915_WRITE(GEN6_RC_STATE, 0);
3977
3978 /* Clear the DBG now so we don't confuse earlier errors */
3979 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3980 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3981 I915_WRITE(GTFIFODBG, gtfifodbg);
3982 }
3983
3984 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3985
3986 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3987
3988 parse_rp_state_cap(dev_priv, rp_state_cap);
3989
3990 /* disable the counters and set deterministic thresholds */
3991 I915_WRITE(GEN6_RC_CONTROL, 0);
3992
3993 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
3994 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
3995 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
3996 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3997 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3998
3999 for_each_ring(ring, dev_priv, i)
4000 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4001
4002 I915_WRITE(GEN6_RC_SLEEP, 0);
4003 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
4004 if (IS_IVYBRIDGE(dev))
4005 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
4006 else
4007 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
4008 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
4009 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
4010
4011 /* Check if we are enabling RC6 */
4012 rc6_mode = intel_enable_rc6(dev_priv->dev);
4013 if (rc6_mode & INTEL_RC6_ENABLE)
4014 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
4015
4016 /* We don't use those on Haswell */
4017 if (!IS_HASWELL(dev)) {
4018 if (rc6_mode & INTEL_RC6p_ENABLE)
4019 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
4020
4021 if (rc6_mode & INTEL_RC6pp_ENABLE)
4022 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
4023 }
4024
4025 intel_print_rc6_info(dev, rc6_mask);
4026
4027 I915_WRITE(GEN6_RC_CONTROL,
4028 rc6_mask |
4029 GEN6_RC_CTL_EI_MODE(1) |
4030 GEN6_RC_CTL_HW_ENABLE);
4031
4032 /* Power down if completely idle for over 50ms */
4033 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
4034 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4035
4036 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
4037 if (ret)
4038 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
4039
4040 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
4041 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
4042 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
4043 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
4044 (pcu_mbox & 0xff) * 50);
4045 dev_priv->rps.max_freq = pcu_mbox & 0xff;
4046 }
4047
4048 dev_priv->rps.power = HIGH_POWER; /* force a reset */
4049 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
4050
4051 gen6_enable_rps_interrupts(dev);
4052
4053 rc6vids = 0;
4054 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
4055 if (IS_GEN6(dev) && ret) {
4056 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
4057 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
4058 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
4059 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
4060 rc6vids &= 0xffff00;
4061 rc6vids |= GEN6_ENCODE_RC6_VID(450);
4062 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
4063 if (ret)
4064 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
4065 }
4066
4067 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
4068 }
4069
4070 static void __gen6_update_ring_freq(struct drm_device *dev)
4071 {
4072 struct drm_i915_private *dev_priv = dev->dev_private;
4073 int min_freq = 15;
4074 unsigned int gpu_freq;
4075 unsigned int max_ia_freq, min_ring_freq;
4076 int scaling_factor = 180;
4077 struct cpufreq_policy *policy;
4078
4079 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4080
4081 policy = cpufreq_cpu_get(0);
4082 if (policy) {
4083 max_ia_freq = policy->cpuinfo.max_freq;
4084 cpufreq_cpu_put(policy);
4085 } else {
4086 /*
4087 * Default to measured freq if none found, PCU will ensure we
4088 * don't go over
4089 */
4090 max_ia_freq = tsc_khz;
4091 }
4092
4093 /* Convert from kHz to MHz */
4094 max_ia_freq /= 1000;
4095
4096 min_ring_freq = I915_READ(DCLK) & 0xf;
4097 /* convert DDR frequency from units of 266.6MHz to bandwidth */
4098 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
4099
4100 /*
4101 * For each potential GPU frequency, load a ring frequency we'd like
4102 * to use for memory access. We do this by specifying the IA frequency
4103 * the PCU should use as a reference to determine the ring frequency.
4104 */
4105 for (gpu_freq = dev_priv->rps.max_freq_softlimit; gpu_freq >= dev_priv->rps.min_freq_softlimit;
4106 gpu_freq--) {
4107 int diff = dev_priv->rps.max_freq_softlimit - gpu_freq;
4108 unsigned int ia_freq = 0, ring_freq = 0;
4109
4110 if (INTEL_INFO(dev)->gen >= 8) {
4111 /* max(2 * GT, DDR). NB: GT is 50MHz units */
4112 ring_freq = max(min_ring_freq, gpu_freq);
4113 } else if (IS_HASWELL(dev)) {
4114 ring_freq = mult_frac(gpu_freq, 5, 4);
4115 ring_freq = max(min_ring_freq, ring_freq);
4116 /* leave ia_freq as the default, chosen by cpufreq */
4117 } else {
4118 /* On older processors, there is no separate ring
4119 * clock domain, so in order to boost the bandwidth
4120 * of the ring, we need to upclock the CPU (ia_freq).
4121 *
4122 * For GPU frequencies less than 750MHz,
4123 * just use the lowest ring freq.
4124 */
4125 if (gpu_freq < min_freq)
4126 ia_freq = 800;
4127 else
4128 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
4129 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
4130 }
4131
4132 sandybridge_pcode_write(dev_priv,
4133 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
4134 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
4135 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
4136 gpu_freq);
4137 }
4138 }
4139
4140 void gen6_update_ring_freq(struct drm_device *dev)
4141 {
4142 struct drm_i915_private *dev_priv = dev->dev_private;
4143
4144 if (INTEL_INFO(dev)->gen < 6 || IS_VALLEYVIEW(dev))
4145 return;
4146
4147 mutex_lock(&dev_priv->rps.hw_lock);
4148 __gen6_update_ring_freq(dev);
4149 mutex_unlock(&dev_priv->rps.hw_lock);
4150 }
4151
4152 static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
4153 {
4154 u32 val, rp0;
4155
4156 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
4157 rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & PUNIT_GPU_STATUS_MAX_FREQ_MASK;
4158
4159 return rp0;
4160 }
4161
4162 static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
4163 {
4164 u32 val, rpe;
4165
4166 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
4167 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
4168
4169 return rpe;
4170 }
4171
4172 static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
4173 {
4174 u32 val, rp1;
4175
4176 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4177 rp1 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & PUNIT_GPU_STATUS_MAX_FREQ_MASK;
4178
4179 return rp1;
4180 }
4181
4182 static int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
4183 {
4184 u32 val, rpn;
4185
4186 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
4187 rpn = (val >> PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT) & PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK;
4188 return rpn;
4189 }
4190
4191 static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
4192 {
4193 u32 val, rp1;
4194
4195 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
4196
4197 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
4198
4199 return rp1;
4200 }
4201
4202 static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
4203 {
4204 u32 val, rp0;
4205
4206 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
4207
4208 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
4209 /* Clamp to max */
4210 rp0 = min_t(u32, rp0, 0xea);
4211
4212 return rp0;
4213 }
4214
4215 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
4216 {
4217 u32 val, rpe;
4218
4219 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
4220 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
4221 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
4222 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
4223
4224 return rpe;
4225 }
4226
4227 static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
4228 {
4229 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
4230 }
4231
4232 /* Check that the pctx buffer wasn't move under us. */
4233 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
4234 {
4235 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
4236
4237 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
4238 dev_priv->vlv_pctx->stolen->start);
4239 }
4240
4241
4242 /* Check that the pcbr address is not empty. */
4243 static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
4244 {
4245 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
4246
4247 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
4248 }
4249
4250 static void cherryview_setup_pctx(struct drm_device *dev)
4251 {
4252 struct drm_i915_private *dev_priv = dev->dev_private;
4253 unsigned long pctx_paddr, paddr;
4254 struct i915_gtt *gtt = &dev_priv->gtt;
4255 u32 pcbr;
4256 int pctx_size = 32*1024;
4257
4258 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4259
4260 pcbr = I915_READ(VLV_PCBR);
4261 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
4262 paddr = (dev_priv->mm.stolen_base +
4263 (gtt->stolen_size - pctx_size));
4264
4265 pctx_paddr = (paddr & (~4095));
4266 I915_WRITE(VLV_PCBR, pctx_paddr);
4267 }
4268 }
4269
4270 static void valleyview_setup_pctx(struct drm_device *dev)
4271 {
4272 struct drm_i915_private *dev_priv = dev->dev_private;
4273 struct drm_i915_gem_object *pctx;
4274 unsigned long pctx_paddr;
4275 u32 pcbr;
4276 int pctx_size = 24*1024;
4277
4278 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4279
4280 pcbr = I915_READ(VLV_PCBR);
4281 if (pcbr) {
4282 /* BIOS set it up already, grab the pre-alloc'd space */
4283 int pcbr_offset;
4284
4285 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
4286 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
4287 pcbr_offset,
4288 I915_GTT_OFFSET_NONE,
4289 pctx_size);
4290 goto out;
4291 }
4292
4293 /*
4294 * From the Gunit register HAS:
4295 * The Gfx driver is expected to program this register and ensure
4296 * proper allocation within Gfx stolen memory. For example, this
4297 * register should be programmed such than the PCBR range does not
4298 * overlap with other ranges, such as the frame buffer, protected
4299 * memory, or any other relevant ranges.
4300 */
4301 pctx = i915_gem_object_create_stolen(dev, pctx_size);
4302 if (!pctx) {
4303 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
4304 return;
4305 }
4306
4307 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
4308 I915_WRITE(VLV_PCBR, pctx_paddr);
4309
4310 out:
4311 dev_priv->vlv_pctx = pctx;
4312 }
4313
4314 static void valleyview_cleanup_pctx(struct drm_device *dev)
4315 {
4316 struct drm_i915_private *dev_priv = dev->dev_private;
4317
4318 if (WARN_ON(!dev_priv->vlv_pctx))
4319 return;
4320
4321 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
4322 dev_priv->vlv_pctx = NULL;
4323 }
4324
4325 static void valleyview_init_gt_powersave(struct drm_device *dev)
4326 {
4327 struct drm_i915_private *dev_priv = dev->dev_private;
4328 u32 val;
4329
4330 valleyview_setup_pctx(dev);
4331
4332 mutex_lock(&dev_priv->rps.hw_lock);
4333
4334 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4335 switch ((val >> 6) & 3) {
4336 case 0:
4337 case 1:
4338 dev_priv->mem_freq = 800;
4339 break;
4340 case 2:
4341 dev_priv->mem_freq = 1066;
4342 break;
4343 case 3:
4344 dev_priv->mem_freq = 1333;
4345 break;
4346 }
4347 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
4348
4349 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
4350 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
4351 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
4352 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4353 dev_priv->rps.max_freq);
4354
4355 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
4356 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
4357 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4358 dev_priv->rps.efficient_freq);
4359
4360 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
4361 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
4362 vlv_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
4363 dev_priv->rps.rp1_freq);
4364
4365 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
4366 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
4367 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4368 dev_priv->rps.min_freq);
4369
4370 /* Preserve min/max settings in case of re-init */
4371 if (dev_priv->rps.max_freq_softlimit == 0)
4372 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4373
4374 if (dev_priv->rps.min_freq_softlimit == 0)
4375 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
4376
4377 mutex_unlock(&dev_priv->rps.hw_lock);
4378 }
4379
4380 static void cherryview_init_gt_powersave(struct drm_device *dev)
4381 {
4382 struct drm_i915_private *dev_priv = dev->dev_private;
4383 u32 val;
4384
4385 cherryview_setup_pctx(dev);
4386
4387 mutex_lock(&dev_priv->rps.hw_lock);
4388
4389 val = vlv_punit_read(dev_priv, CCK_FUSE_REG);
4390 switch ((val >> 2) & 0x7) {
4391 case 0:
4392 case 1:
4393 dev_priv->rps.cz_freq = 200;
4394 dev_priv->mem_freq = 1600;
4395 break;
4396 case 2:
4397 dev_priv->rps.cz_freq = 267;
4398 dev_priv->mem_freq = 1600;
4399 break;
4400 case 3:
4401 dev_priv->rps.cz_freq = 333;
4402 dev_priv->mem_freq = 2000;
4403 break;
4404 case 4:
4405 dev_priv->rps.cz_freq = 320;
4406 dev_priv->mem_freq = 1600;
4407 break;
4408 case 5:
4409 dev_priv->rps.cz_freq = 400;
4410 dev_priv->mem_freq = 1600;
4411 break;
4412 }
4413 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
4414
4415 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
4416 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
4417 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
4418 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4419 dev_priv->rps.max_freq);
4420
4421 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
4422 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
4423 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4424 dev_priv->rps.efficient_freq);
4425
4426 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
4427 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
4428 vlv_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
4429 dev_priv->rps.rp1_freq);
4430
4431 dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv);
4432 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
4433 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4434 dev_priv->rps.min_freq);
4435
4436 WARN_ONCE((dev_priv->rps.max_freq |
4437 dev_priv->rps.efficient_freq |
4438 dev_priv->rps.rp1_freq |
4439 dev_priv->rps.min_freq) & 1,
4440 "Odd GPU freq values\n");
4441
4442 /* Preserve min/max settings in case of re-init */
4443 if (dev_priv->rps.max_freq_softlimit == 0)
4444 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4445
4446 if (dev_priv->rps.min_freq_softlimit == 0)
4447 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
4448
4449 mutex_unlock(&dev_priv->rps.hw_lock);
4450 }
4451
4452 static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
4453 {
4454 valleyview_cleanup_pctx(dev);
4455 }
4456
4457 static void cherryview_enable_rps(struct drm_device *dev)
4458 {
4459 struct drm_i915_private *dev_priv = dev->dev_private;
4460 struct intel_engine_cs *ring;
4461 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
4462 int i;
4463
4464 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4465
4466 gtfifodbg = I915_READ(GTFIFODBG);
4467 if (gtfifodbg) {
4468 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4469 gtfifodbg);
4470 I915_WRITE(GTFIFODBG, gtfifodbg);
4471 }
4472
4473 cherryview_check_pctx(dev_priv);
4474
4475 /* 1a & 1b: Get forcewake during program sequence. Although the driver
4476 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4477 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
4478
4479 /* 2a: Program RC6 thresholds.*/
4480 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4481 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4482 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4483
4484 for_each_ring(ring, dev_priv, i)
4485 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4486 I915_WRITE(GEN6_RC_SLEEP, 0);
4487
4488 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
4489
4490 /* allows RC6 residency counter to work */
4491 I915_WRITE(VLV_COUNTER_CONTROL,
4492 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
4493 VLV_MEDIA_RC6_COUNT_EN |
4494 VLV_RENDER_RC6_COUNT_EN));
4495
4496 /* For now we assume BIOS is allocating and populating the PCBR */
4497 pcbr = I915_READ(VLV_PCBR);
4498
4499 DRM_DEBUG_DRIVER("PCBR offset : 0x%x\n", pcbr);
4500
4501 /* 3: Enable RC6 */
4502 if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
4503 (pcbr >> VLV_PCBR_ADDR_SHIFT))
4504 rc6_mode = GEN6_RC_CTL_EI_MODE(1);
4505
4506 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
4507
4508 /* 4 Program defaults and thresholds for RPS*/
4509 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
4510 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
4511 I915_WRITE(GEN6_RP_UP_EI, 66000);
4512 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
4513
4514 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4515
4516 /* WaDisablePwrmtrEvent:chv (pre-production hw) */
4517 I915_WRITE(0xA80C, I915_READ(0xA80C) & 0x00ffffff);
4518 I915_WRITE(0xA810, I915_READ(0xA810) & 0xffffff00);
4519
4520 /* 5: Enable RPS */
4521 I915_WRITE(GEN6_RP_CONTROL,
4522 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4523 GEN6_RP_MEDIA_IS_GFX | /* WaSetMaskForGfxBusyness:chv (pre-production hw ?) */
4524 GEN6_RP_ENABLE |
4525 GEN6_RP_UP_BUSY_AVG |
4526 GEN6_RP_DOWN_IDLE_AVG);
4527
4528 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4529
4530 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
4531 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
4532
4533 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
4534 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
4535 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
4536 dev_priv->rps.cur_freq);
4537
4538 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
4539 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4540 dev_priv->rps.efficient_freq);
4541
4542 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
4543
4544 gen8_enable_rps_interrupts(dev);
4545
4546 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
4547 }
4548
4549 static void valleyview_enable_rps(struct drm_device *dev)
4550 {
4551 struct drm_i915_private *dev_priv = dev->dev_private;
4552 struct intel_engine_cs *ring;
4553 u32 gtfifodbg, val, rc6_mode = 0;
4554 int i;
4555
4556 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4557
4558 valleyview_check_pctx(dev_priv);
4559
4560 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
4561 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4562 gtfifodbg);
4563 I915_WRITE(GTFIFODBG, gtfifodbg);
4564 }
4565
4566 /* If VLV, Forcewake all wells, else re-direct to regular path */
4567 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
4568
4569 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
4570 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
4571 I915_WRITE(GEN6_RP_UP_EI, 66000);
4572 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
4573
4574 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4575 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 0xf4240);
4576
4577 I915_WRITE(GEN6_RP_CONTROL,
4578 GEN6_RP_MEDIA_TURBO |
4579 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4580 GEN6_RP_MEDIA_IS_GFX |
4581 GEN6_RP_ENABLE |
4582 GEN6_RP_UP_BUSY_AVG |
4583 GEN6_RP_DOWN_IDLE_CONT);
4584
4585 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
4586 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4587 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4588
4589 for_each_ring(ring, dev_priv, i)
4590 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4591
4592 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
4593
4594 /* allows RC6 residency counter to work */
4595 I915_WRITE(VLV_COUNTER_CONTROL,
4596 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
4597 VLV_RENDER_RC0_COUNT_EN |
4598 VLV_MEDIA_RC6_COUNT_EN |
4599 VLV_RENDER_RC6_COUNT_EN));
4600
4601 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4602 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
4603
4604 intel_print_rc6_info(dev, rc6_mode);
4605
4606 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
4607
4608 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4609
4610 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
4611 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
4612
4613 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
4614 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
4615 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
4616 dev_priv->rps.cur_freq);
4617
4618 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
4619 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4620 dev_priv->rps.efficient_freq);
4621
4622 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
4623
4624 gen6_enable_rps_interrupts(dev);
4625
4626 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
4627 }
4628
4629 void ironlake_teardown_rc6(struct drm_device *dev)
4630 {
4631 struct drm_i915_private *dev_priv = dev->dev_private;
4632
4633 if (dev_priv->ips.renderctx) {
4634 i915_gem_object_ggtt_unpin(dev_priv->ips.renderctx);
4635 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
4636 dev_priv->ips.renderctx = NULL;
4637 }
4638
4639 if (dev_priv->ips.pwrctx) {
4640 i915_gem_object_ggtt_unpin(dev_priv->ips.pwrctx);
4641 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
4642 dev_priv->ips.pwrctx = NULL;
4643 }
4644 }
4645
4646 static void ironlake_disable_rc6(struct drm_device *dev)
4647 {
4648 struct drm_i915_private *dev_priv = dev->dev_private;
4649
4650 if (I915_READ(PWRCTXA)) {
4651 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
4652 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
4653 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
4654 50);
4655
4656 I915_WRITE(PWRCTXA, 0);
4657 POSTING_READ(PWRCTXA);
4658
4659 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
4660 POSTING_READ(RSTDBYCTL);
4661 }
4662 }
4663
4664 static int ironlake_setup_rc6(struct drm_device *dev)
4665 {
4666 struct drm_i915_private *dev_priv = dev->dev_private;
4667
4668 if (dev_priv->ips.renderctx == NULL)
4669 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
4670 if (!dev_priv->ips.renderctx)
4671 return -ENOMEM;
4672
4673 if (dev_priv->ips.pwrctx == NULL)
4674 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
4675 if (!dev_priv->ips.pwrctx) {
4676 ironlake_teardown_rc6(dev);
4677 return -ENOMEM;
4678 }
4679
4680 return 0;
4681 }
4682
4683 static void ironlake_enable_rc6(struct drm_device *dev)
4684 {
4685 struct drm_i915_private *dev_priv = dev->dev_private;
4686 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
4687 bool was_interruptible;
4688 int ret;
4689
4690 /* rc6 disabled by default due to repeated reports of hanging during
4691 * boot and resume.
4692 */
4693 if (!intel_enable_rc6(dev))
4694 return;
4695
4696 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4697
4698 ret = ironlake_setup_rc6(dev);
4699 if (ret)
4700 return;
4701
4702 was_interruptible = dev_priv->mm.interruptible;
4703 dev_priv->mm.interruptible = false;
4704
4705 /*
4706 * GPU can automatically power down the render unit if given a page
4707 * to save state.
4708 */
4709 ret = intel_ring_begin(ring, 6);
4710 if (ret) {
4711 ironlake_teardown_rc6(dev);
4712 dev_priv->mm.interruptible = was_interruptible;
4713 return;
4714 }
4715
4716 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
4717 intel_ring_emit(ring, MI_SET_CONTEXT);
4718 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) |
4719 MI_MM_SPACE_GTT |
4720 MI_SAVE_EXT_STATE_EN |
4721 MI_RESTORE_EXT_STATE_EN |
4722 MI_RESTORE_INHIBIT);
4723 intel_ring_emit(ring, MI_SUSPEND_FLUSH);
4724 intel_ring_emit(ring, MI_NOOP);
4725 intel_ring_emit(ring, MI_FLUSH);
4726 intel_ring_advance(ring);
4727
4728 /*
4729 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
4730 * does an implicit flush, combined with MI_FLUSH above, it should be
4731 * safe to assume that renderctx is valid
4732 */
4733 ret = intel_ring_idle(ring);
4734 dev_priv->mm.interruptible = was_interruptible;
4735 if (ret) {
4736 DRM_ERROR("failed to enable ironlake power savings\n");
4737 ironlake_teardown_rc6(dev);
4738 return;
4739 }
4740
4741 I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN);
4742 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
4743
4744 intel_print_rc6_info(dev, GEN6_RC_CTL_RC6_ENABLE);
4745 }
4746
4747 static unsigned long intel_pxfreq(u32 vidfreq)
4748 {
4749 unsigned long freq;
4750 int div = (vidfreq & 0x3f0000) >> 16;
4751 int post = (vidfreq & 0x3000) >> 12;
4752 int pre = (vidfreq & 0x7);
4753
4754 if (!pre)
4755 return 0;
4756
4757 freq = ((div * 133333) / ((1<<post) * pre));
4758
4759 return freq;
4760 }
4761
4762 static const struct cparams {
4763 u16 i;
4764 u16 t;
4765 u16 m;
4766 u16 c;
4767 } cparams[] = {
4768 { 1, 1333, 301, 28664 },
4769 { 1, 1066, 294, 24460 },
4770 { 1, 800, 294, 25192 },
4771 { 0, 1333, 276, 27605 },
4772 { 0, 1066, 276, 27605 },
4773 { 0, 800, 231, 23784 },
4774 };
4775
4776 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
4777 {
4778 u64 total_count, diff, ret;
4779 u32 count1, count2, count3, m = 0, c = 0;
4780 unsigned long now = jiffies_to_msecs(jiffies), diff1;
4781 int i;
4782
4783 assert_spin_locked(&mchdev_lock);
4784
4785 diff1 = now - dev_priv->ips.last_time1;
4786
4787 /* Prevent division-by-zero if we are asking too fast.
4788 * Also, we don't get interesting results if we are polling
4789 * faster than once in 10ms, so just return the saved value
4790 * in such cases.
4791 */
4792 if (diff1 <= 10)
4793 return dev_priv->ips.chipset_power;
4794
4795 count1 = I915_READ(DMIEC);
4796 count2 = I915_READ(DDREC);
4797 count3 = I915_READ(CSIEC);
4798
4799 total_count = count1 + count2 + count3;
4800
4801 /* FIXME: handle per-counter overflow */
4802 if (total_count < dev_priv->ips.last_count1) {
4803 diff = ~0UL - dev_priv->ips.last_count1;
4804 diff += total_count;
4805 } else {
4806 diff = total_count - dev_priv->ips.last_count1;
4807 }
4808
4809 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
4810 if (cparams[i].i == dev_priv->ips.c_m &&
4811 cparams[i].t == dev_priv->ips.r_t) {
4812 m = cparams[i].m;
4813 c = cparams[i].c;
4814 break;
4815 }
4816 }
4817
4818 diff = div_u64(diff, diff1);
4819 ret = ((m * diff) + c);
4820 ret = div_u64(ret, 10);
4821
4822 dev_priv->ips.last_count1 = total_count;
4823 dev_priv->ips.last_time1 = now;
4824
4825 dev_priv->ips.chipset_power = ret;
4826
4827 return ret;
4828 }
4829
4830 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
4831 {
4832 struct drm_device *dev = dev_priv->dev;
4833 unsigned long val;
4834
4835 if (INTEL_INFO(dev)->gen != 5)
4836 return 0;
4837
4838 spin_lock_irq(&mchdev_lock);
4839
4840 val = __i915_chipset_val(dev_priv);
4841
4842 spin_unlock_irq(&mchdev_lock);
4843
4844 return val;
4845 }
4846
4847 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
4848 {
4849 unsigned long m, x, b;
4850 u32 tsfs;
4851
4852 tsfs = I915_READ(TSFS);
4853
4854 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
4855 x = I915_READ8(TR1);
4856
4857 b = tsfs & TSFS_INTR_MASK;
4858
4859 return ((m * x) / 127) - b;
4860 }
4861
4862 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
4863 {
4864 struct drm_device *dev = dev_priv->dev;
4865 static const struct v_table {
4866 u16 vd; /* in .1 mil */
4867 u16 vm; /* in .1 mil */
4868 } v_table[] = {
4869 { 0, 0, },
4870 { 375, 0, },
4871 { 500, 0, },
4872 { 625, 0, },
4873 { 750, 0, },
4874 { 875, 0, },
4875 { 1000, 0, },
4876 { 1125, 0, },
4877 { 4125, 3000, },
4878 { 4125, 3000, },
4879 { 4125, 3000, },
4880 { 4125, 3000, },
4881 { 4125, 3000, },
4882 { 4125, 3000, },
4883 { 4125, 3000, },
4884 { 4125, 3000, },
4885 { 4125, 3000, },
4886 { 4125, 3000, },
4887 { 4125, 3000, },
4888 { 4125, 3000, },
4889 { 4125, 3000, },
4890 { 4125, 3000, },
4891 { 4125, 3000, },
4892 { 4125, 3000, },
4893 { 4125, 3000, },
4894 { 4125, 3000, },
4895 { 4125, 3000, },
4896 { 4125, 3000, },
4897 { 4125, 3000, },
4898 { 4125, 3000, },
4899 { 4125, 3000, },
4900 { 4125, 3000, },
4901 { 4250, 3125, },
4902 { 4375, 3250, },
4903 { 4500, 3375, },
4904 { 4625, 3500, },
4905 { 4750, 3625, },
4906 { 4875, 3750, },
4907 { 5000, 3875, },
4908 { 5125, 4000, },
4909 { 5250, 4125, },
4910 { 5375, 4250, },
4911 { 5500, 4375, },
4912 { 5625, 4500, },
4913 { 5750, 4625, },
4914 { 5875, 4750, },
4915 { 6000, 4875, },
4916 { 6125, 5000, },
4917 { 6250, 5125, },
4918 { 6375, 5250, },
4919 { 6500, 5375, },
4920 { 6625, 5500, },
4921 { 6750, 5625, },
4922 { 6875, 5750, },
4923 { 7000, 5875, },
4924 { 7125, 6000, },
4925 { 7250, 6125, },
4926 { 7375, 6250, },
4927 { 7500, 6375, },
4928 { 7625, 6500, },
4929 { 7750, 6625, },
4930 { 7875, 6750, },
4931 { 8000, 6875, },
4932 { 8125, 7000, },
4933 { 8250, 7125, },
4934 { 8375, 7250, },
4935 { 8500, 7375, },
4936 { 8625, 7500, },
4937 { 8750, 7625, },
4938 { 8875, 7750, },
4939 { 9000, 7875, },
4940 { 9125, 8000, },
4941 { 9250, 8125, },
4942 { 9375, 8250, },
4943 { 9500, 8375, },
4944 { 9625, 8500, },
4945 { 9750, 8625, },
4946 { 9875, 8750, },
4947 { 10000, 8875, },
4948 { 10125, 9000, },
4949 { 10250, 9125, },
4950 { 10375, 9250, },
4951 { 10500, 9375, },
4952 { 10625, 9500, },
4953 { 10750, 9625, },
4954 { 10875, 9750, },
4955 { 11000, 9875, },
4956 { 11125, 10000, },
4957 { 11250, 10125, },
4958 { 11375, 10250, },
4959 { 11500, 10375, },
4960 { 11625, 10500, },
4961 { 11750, 10625, },
4962 { 11875, 10750, },
4963 { 12000, 10875, },
4964 { 12125, 11000, },
4965 { 12250, 11125, },
4966 { 12375, 11250, },
4967 { 12500, 11375, },
4968 { 12625, 11500, },
4969 { 12750, 11625, },
4970 { 12875, 11750, },
4971 { 13000, 11875, },
4972 { 13125, 12000, },
4973 { 13250, 12125, },
4974 { 13375, 12250, },
4975 { 13500, 12375, },
4976 { 13625, 12500, },
4977 { 13750, 12625, },
4978 { 13875, 12750, },
4979 { 14000, 12875, },
4980 { 14125, 13000, },
4981 { 14250, 13125, },
4982 { 14375, 13250, },
4983 { 14500, 13375, },
4984 { 14625, 13500, },
4985 { 14750, 13625, },
4986 { 14875, 13750, },
4987 { 15000, 13875, },
4988 { 15125, 14000, },
4989 { 15250, 14125, },
4990 { 15375, 14250, },
4991 { 15500, 14375, },
4992 { 15625, 14500, },
4993 { 15750, 14625, },
4994 { 15875, 14750, },
4995 { 16000, 14875, },
4996 { 16125, 15000, },
4997 };
4998 if (INTEL_INFO(dev)->is_mobile)
4999 return v_table[pxvid].vm;
5000 else
5001 return v_table[pxvid].vd;
5002 }
5003
5004 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
5005 {
5006 u64 now, diff, diffms;
5007 u32 count;
5008
5009 assert_spin_locked(&mchdev_lock);
5010
5011 now = ktime_get_raw_ns();
5012 diffms = now - dev_priv->ips.last_time2;
5013 do_div(diffms, NSEC_PER_MSEC);
5014
5015 /* Don't divide by 0 */
5016 if (!diffms)
5017 return;
5018
5019 count = I915_READ(GFXEC);
5020
5021 if (count < dev_priv->ips.last_count2) {
5022 diff = ~0UL - dev_priv->ips.last_count2;
5023 diff += count;
5024 } else {
5025 diff = count - dev_priv->ips.last_count2;
5026 }
5027
5028 dev_priv->ips.last_count2 = count;
5029 dev_priv->ips.last_time2 = now;
5030
5031 /* More magic constants... */
5032 diff = diff * 1181;
5033 diff = div_u64(diff, diffms * 10);
5034 dev_priv->ips.gfx_power = diff;
5035 }
5036
5037 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
5038 {
5039 struct drm_device *dev = dev_priv->dev;
5040
5041 if (INTEL_INFO(dev)->gen != 5)
5042 return;
5043
5044 spin_lock_irq(&mchdev_lock);
5045
5046 __i915_update_gfx_val(dev_priv);
5047
5048 spin_unlock_irq(&mchdev_lock);
5049 }
5050
5051 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
5052 {
5053 unsigned long t, corr, state1, corr2, state2;
5054 u32 pxvid, ext_v;
5055
5056 assert_spin_locked(&mchdev_lock);
5057
5058 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_freq * 4));
5059 pxvid = (pxvid >> 24) & 0x7f;
5060 ext_v = pvid_to_extvid(dev_priv, pxvid);
5061
5062 state1 = ext_v;
5063
5064 t = i915_mch_val(dev_priv);
5065
5066 /* Revel in the empirically derived constants */
5067
5068 /* Correction factor in 1/100000 units */
5069 if (t > 80)
5070 corr = ((t * 2349) + 135940);
5071 else if (t >= 50)
5072 corr = ((t * 964) + 29317);
5073 else /* < 50 */
5074 corr = ((t * 301) + 1004);
5075
5076 corr = corr * ((150142 * state1) / 10000 - 78642);
5077 corr /= 100000;
5078 corr2 = (corr * dev_priv->ips.corr);
5079
5080 state2 = (corr2 * state1) / 10000;
5081 state2 /= 100; /* convert to mW */
5082
5083 __i915_update_gfx_val(dev_priv);
5084
5085 return dev_priv->ips.gfx_power + state2;
5086 }
5087
5088 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
5089 {
5090 struct drm_device *dev = dev_priv->dev;
5091 unsigned long val;
5092
5093 if (INTEL_INFO(dev)->gen != 5)
5094 return 0;
5095
5096 spin_lock_irq(&mchdev_lock);
5097
5098 val = __i915_gfx_val(dev_priv);
5099
5100 spin_unlock_irq(&mchdev_lock);
5101
5102 return val;
5103 }
5104
5105 /**
5106 * i915_read_mch_val - return value for IPS use
5107 *
5108 * Calculate and return a value for the IPS driver to use when deciding whether
5109 * we have thermal and power headroom to increase CPU or GPU power budget.
5110 */
5111 unsigned long i915_read_mch_val(void)
5112 {
5113 struct drm_i915_private *dev_priv;
5114 unsigned long chipset_val, graphics_val, ret = 0;
5115
5116 spin_lock_irq(&mchdev_lock);
5117 if (!i915_mch_dev)
5118 goto out_unlock;
5119 dev_priv = i915_mch_dev;
5120
5121 chipset_val = __i915_chipset_val(dev_priv);
5122 graphics_val = __i915_gfx_val(dev_priv);
5123
5124 ret = chipset_val + graphics_val;
5125
5126 out_unlock:
5127 spin_unlock_irq(&mchdev_lock);
5128
5129 return ret;
5130 }
5131 EXPORT_SYMBOL_GPL(i915_read_mch_val);
5132
5133 /**
5134 * i915_gpu_raise - raise GPU frequency limit
5135 *
5136 * Raise the limit; IPS indicates we have thermal headroom.
5137 */
5138 bool i915_gpu_raise(void)
5139 {
5140 struct drm_i915_private *dev_priv;
5141 bool ret = true;
5142
5143 spin_lock_irq(&mchdev_lock);
5144 if (!i915_mch_dev) {
5145 ret = false;
5146 goto out_unlock;
5147 }
5148 dev_priv = i915_mch_dev;
5149
5150 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
5151 dev_priv->ips.max_delay--;
5152
5153 out_unlock:
5154 spin_unlock_irq(&mchdev_lock);
5155
5156 return ret;
5157 }
5158 EXPORT_SYMBOL_GPL(i915_gpu_raise);
5159
5160 /**
5161 * i915_gpu_lower - lower GPU frequency limit
5162 *
5163 * IPS indicates we're close to a thermal limit, so throttle back the GPU
5164 * frequency maximum.
5165 */
5166 bool i915_gpu_lower(void)
5167 {
5168 struct drm_i915_private *dev_priv;
5169 bool ret = true;
5170
5171 spin_lock_irq(&mchdev_lock);
5172 if (!i915_mch_dev) {
5173 ret = false;
5174 goto out_unlock;
5175 }
5176 dev_priv = i915_mch_dev;
5177
5178 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
5179 dev_priv->ips.max_delay++;
5180
5181 out_unlock:
5182 spin_unlock_irq(&mchdev_lock);
5183
5184 return ret;
5185 }
5186 EXPORT_SYMBOL_GPL(i915_gpu_lower);
5187
5188 /**
5189 * i915_gpu_busy - indicate GPU business to IPS
5190 *
5191 * Tell the IPS driver whether or not the GPU is busy.
5192 */
5193 bool i915_gpu_busy(void)
5194 {
5195 struct drm_i915_private *dev_priv;
5196 struct intel_engine_cs *ring;
5197 bool ret = false;
5198 int i;
5199
5200 spin_lock_irq(&mchdev_lock);
5201 if (!i915_mch_dev)
5202 goto out_unlock;
5203 dev_priv = i915_mch_dev;
5204
5205 for_each_ring(ring, dev_priv, i)
5206 ret |= !list_empty(&ring->request_list);
5207
5208 out_unlock:
5209 spin_unlock_irq(&mchdev_lock);
5210
5211 return ret;
5212 }
5213 EXPORT_SYMBOL_GPL(i915_gpu_busy);
5214
5215 /**
5216 * i915_gpu_turbo_disable - disable graphics turbo
5217 *
5218 * Disable graphics turbo by resetting the max frequency and setting the
5219 * current frequency to the default.
5220 */
5221 bool i915_gpu_turbo_disable(void)
5222 {
5223 struct drm_i915_private *dev_priv;
5224 bool ret = true;
5225
5226 spin_lock_irq(&mchdev_lock);
5227 if (!i915_mch_dev) {
5228 ret = false;
5229 goto out_unlock;
5230 }
5231 dev_priv = i915_mch_dev;
5232
5233 dev_priv->ips.max_delay = dev_priv->ips.fstart;
5234
5235 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
5236 ret = false;
5237
5238 out_unlock:
5239 spin_unlock_irq(&mchdev_lock);
5240
5241 return ret;
5242 }
5243 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
5244
5245 /**
5246 * Tells the intel_ips driver that the i915 driver is now loaded, if
5247 * IPS got loaded first.
5248 *
5249 * This awkward dance is so that neither module has to depend on the
5250 * other in order for IPS to do the appropriate communication of
5251 * GPU turbo limits to i915.
5252 */
5253 static void
5254 ips_ping_for_i915_load(void)
5255 {
5256 void (*link)(void);
5257
5258 link = symbol_get(ips_link_to_i915_driver);
5259 if (link) {
5260 link();
5261 symbol_put(ips_link_to_i915_driver);
5262 }
5263 }
5264
5265 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
5266 {
5267 /* We only register the i915 ips part with intel-ips once everything is
5268 * set up, to avoid intel-ips sneaking in and reading bogus values. */
5269 spin_lock_irq(&mchdev_lock);
5270 i915_mch_dev = dev_priv;
5271 spin_unlock_irq(&mchdev_lock);
5272
5273 ips_ping_for_i915_load();
5274 }
5275
5276 void intel_gpu_ips_teardown(void)
5277 {
5278 spin_lock_irq(&mchdev_lock);
5279 i915_mch_dev = NULL;
5280 spin_unlock_irq(&mchdev_lock);
5281 }
5282
5283 static void intel_init_emon(struct drm_device *dev)
5284 {
5285 struct drm_i915_private *dev_priv = dev->dev_private;
5286 u32 lcfuse;
5287 u8 pxw[16];
5288 int i;
5289
5290 /* Disable to program */
5291 I915_WRITE(ECR, 0);
5292 POSTING_READ(ECR);
5293
5294 /* Program energy weights for various events */
5295 I915_WRITE(SDEW, 0x15040d00);
5296 I915_WRITE(CSIEW0, 0x007f0000);
5297 I915_WRITE(CSIEW1, 0x1e220004);
5298 I915_WRITE(CSIEW2, 0x04000004);
5299
5300 for (i = 0; i < 5; i++)
5301 I915_WRITE(PEW + (i * 4), 0);
5302 for (i = 0; i < 3; i++)
5303 I915_WRITE(DEW + (i * 4), 0);
5304
5305 /* Program P-state weights to account for frequency power adjustment */
5306 for (i = 0; i < 16; i++) {
5307 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
5308 unsigned long freq = intel_pxfreq(pxvidfreq);
5309 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5310 PXVFREQ_PX_SHIFT;
5311 unsigned long val;
5312
5313 val = vid * vid;
5314 val *= (freq / 1000);
5315 val *= 255;
5316 val /= (127*127*900);
5317 if (val > 0xff)
5318 DRM_ERROR("bad pxval: %ld\n", val);
5319 pxw[i] = val;
5320 }
5321 /* Render standby states get 0 weight */
5322 pxw[14] = 0;
5323 pxw[15] = 0;
5324
5325 for (i = 0; i < 4; i++) {
5326 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5327 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
5328 I915_WRITE(PXW + (i * 4), val);
5329 }
5330
5331 /* Adjust magic regs to magic values (more experimental results) */
5332 I915_WRITE(OGW0, 0);
5333 I915_WRITE(OGW1, 0);
5334 I915_WRITE(EG0, 0x00007f00);
5335 I915_WRITE(EG1, 0x0000000e);
5336 I915_WRITE(EG2, 0x000e0000);
5337 I915_WRITE(EG3, 0x68000300);
5338 I915_WRITE(EG4, 0x42000000);
5339 I915_WRITE(EG5, 0x00140031);
5340 I915_WRITE(EG6, 0);
5341 I915_WRITE(EG7, 0);
5342
5343 for (i = 0; i < 8; i++)
5344 I915_WRITE(PXWL + (i * 4), 0);
5345
5346 /* Enable PMON + select events */
5347 I915_WRITE(ECR, 0x80000019);
5348
5349 lcfuse = I915_READ(LCFUSE02);
5350
5351 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
5352 }
5353
5354 void intel_init_gt_powersave(struct drm_device *dev)
5355 {
5356 i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
5357
5358 if (IS_CHERRYVIEW(dev))
5359 cherryview_init_gt_powersave(dev);
5360 else if (IS_VALLEYVIEW(dev))
5361 valleyview_init_gt_powersave(dev);
5362 }
5363
5364 void intel_cleanup_gt_powersave(struct drm_device *dev)
5365 {
5366 if (IS_CHERRYVIEW(dev))
5367 return;
5368 else if (IS_VALLEYVIEW(dev))
5369 valleyview_cleanup_gt_powersave(dev);
5370 }
5371
5372 /**
5373 * intel_suspend_gt_powersave - suspend PM work and helper threads
5374 * @dev: drm device
5375 *
5376 * We don't want to disable RC6 or other features here, we just want
5377 * to make sure any work we've queued has finished and won't bother
5378 * us while we're suspended.
5379 */
5380 void intel_suspend_gt_powersave(struct drm_device *dev)
5381 {
5382 struct drm_i915_private *dev_priv = dev->dev_private;
5383
5384 /* Interrupts should be disabled already to avoid re-arming. */
5385 WARN_ON(intel_irqs_enabled(dev_priv));
5386
5387 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
5388
5389 cancel_work_sync(&dev_priv->rps.work);
5390
5391 /* Force GPU to min freq during suspend */
5392 gen6_rps_idle(dev_priv);
5393 }
5394
5395 void intel_disable_gt_powersave(struct drm_device *dev)
5396 {
5397 struct drm_i915_private *dev_priv = dev->dev_private;
5398
5399 /* Interrupts should be disabled already to avoid re-arming. */
5400 WARN_ON(intel_irqs_enabled(dev_priv));
5401
5402 if (IS_IRONLAKE_M(dev)) {
5403 ironlake_disable_drps(dev);
5404 ironlake_disable_rc6(dev);
5405 } else if (INTEL_INFO(dev)->gen >= 6) {
5406 intel_suspend_gt_powersave(dev);
5407
5408 mutex_lock(&dev_priv->rps.hw_lock);
5409 if (IS_CHERRYVIEW(dev))
5410 cherryview_disable_rps(dev);
5411 else if (IS_VALLEYVIEW(dev))
5412 valleyview_disable_rps(dev);
5413 else
5414 gen6_disable_rps(dev);
5415 dev_priv->rps.enabled = false;
5416 mutex_unlock(&dev_priv->rps.hw_lock);
5417 }
5418 }
5419
5420 static void intel_gen6_powersave_work(struct work_struct *work)
5421 {
5422 struct drm_i915_private *dev_priv =
5423 container_of(work, struct drm_i915_private,
5424 rps.delayed_resume_work.work);
5425 struct drm_device *dev = dev_priv->dev;
5426
5427 dev_priv->rps.is_bdw_sw_turbo = false;
5428
5429 mutex_lock(&dev_priv->rps.hw_lock);
5430
5431 if (IS_CHERRYVIEW(dev)) {
5432 cherryview_enable_rps(dev);
5433 } else if (IS_VALLEYVIEW(dev)) {
5434 valleyview_enable_rps(dev);
5435 } else if (IS_BROADWELL(dev)) {
5436 gen8_enable_rps(dev);
5437 __gen6_update_ring_freq(dev);
5438 } else {
5439 gen6_enable_rps(dev);
5440 __gen6_update_ring_freq(dev);
5441 }
5442 dev_priv->rps.enabled = true;
5443 mutex_unlock(&dev_priv->rps.hw_lock);
5444
5445 intel_runtime_pm_put(dev_priv);
5446 }
5447
5448 void intel_enable_gt_powersave(struct drm_device *dev)
5449 {
5450 struct drm_i915_private *dev_priv = dev->dev_private;
5451
5452 if (IS_IRONLAKE_M(dev)) {
5453 mutex_lock(&dev->struct_mutex);
5454 ironlake_enable_drps(dev);
5455 ironlake_enable_rc6(dev);
5456 intel_init_emon(dev);
5457 mutex_unlock(&dev->struct_mutex);
5458 } else if (INTEL_INFO(dev)->gen >= 6) {
5459 /*
5460 * PCU communication is slow and this doesn't need to be
5461 * done at any specific time, so do this out of our fast path
5462 * to make resume and init faster.
5463 *
5464 * We depend on the HW RC6 power context save/restore
5465 * mechanism when entering D3 through runtime PM suspend. So
5466 * disable RPM until RPS/RC6 is properly setup. We can only
5467 * get here via the driver load/system resume/runtime resume
5468 * paths, so the _noresume version is enough (and in case of
5469 * runtime resume it's necessary).
5470 */
5471 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
5472 round_jiffies_up_relative(HZ)))
5473 intel_runtime_pm_get_noresume(dev_priv);
5474 }
5475 }
5476
5477 void intel_reset_gt_powersave(struct drm_device *dev)
5478 {
5479 struct drm_i915_private *dev_priv = dev->dev_private;
5480
5481 dev_priv->rps.enabled = false;
5482 intel_enable_gt_powersave(dev);
5483 }
5484
5485 static void ibx_init_clock_gating(struct drm_device *dev)
5486 {
5487 struct drm_i915_private *dev_priv = dev->dev_private;
5488
5489 /*
5490 * On Ibex Peak and Cougar Point, we need to disable clock
5491 * gating for the panel power sequencer or it will fail to
5492 * start up when no ports are active.
5493 */
5494 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
5495 }
5496
5497 static void g4x_disable_trickle_feed(struct drm_device *dev)
5498 {
5499 struct drm_i915_private *dev_priv = dev->dev_private;
5500 int pipe;
5501
5502 for_each_pipe(dev_priv, pipe) {
5503 I915_WRITE(DSPCNTR(pipe),
5504 I915_READ(DSPCNTR(pipe)) |
5505 DISPPLANE_TRICKLE_FEED_DISABLE);
5506 intel_flush_primary_plane(dev_priv, pipe);
5507 }
5508 }
5509
5510 static void ilk_init_lp_watermarks(struct drm_device *dev)
5511 {
5512 struct drm_i915_private *dev_priv = dev->dev_private;
5513
5514 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
5515 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
5516 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
5517
5518 /*
5519 * Don't touch WM1S_LP_EN here.
5520 * Doing so could cause underruns.
5521 */
5522 }
5523
5524 static void ironlake_init_clock_gating(struct drm_device *dev)
5525 {
5526 struct drm_i915_private *dev_priv = dev->dev_private;
5527 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
5528
5529 /*
5530 * Required for FBC
5531 * WaFbcDisableDpfcClockGating:ilk
5532 */
5533 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
5534 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
5535 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
5536
5537 I915_WRITE(PCH_3DCGDIS0,
5538 MARIUNIT_CLOCK_GATE_DISABLE |
5539 SVSMUNIT_CLOCK_GATE_DISABLE);
5540 I915_WRITE(PCH_3DCGDIS1,
5541 VFMUNIT_CLOCK_GATE_DISABLE);
5542
5543 /*
5544 * According to the spec the following bits should be set in
5545 * order to enable memory self-refresh
5546 * The bit 22/21 of 0x42004
5547 * The bit 5 of 0x42020
5548 * The bit 15 of 0x45000
5549 */
5550 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5551 (I915_READ(ILK_DISPLAY_CHICKEN2) |
5552 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
5553 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
5554 I915_WRITE(DISP_ARB_CTL,
5555 (I915_READ(DISP_ARB_CTL) |
5556 DISP_FBC_WM_DIS));
5557
5558 ilk_init_lp_watermarks(dev);
5559
5560 /*
5561 * Based on the document from hardware guys the following bits
5562 * should be set unconditionally in order to enable FBC.
5563 * The bit 22 of 0x42000
5564 * The bit 22 of 0x42004
5565 * The bit 7,8,9 of 0x42020.
5566 */
5567 if (IS_IRONLAKE_M(dev)) {
5568 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
5569 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5570 I915_READ(ILK_DISPLAY_CHICKEN1) |
5571 ILK_FBCQ_DIS);
5572 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5573 I915_READ(ILK_DISPLAY_CHICKEN2) |
5574 ILK_DPARB_GATE);
5575 }
5576
5577 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
5578
5579 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5580 I915_READ(ILK_DISPLAY_CHICKEN2) |
5581 ILK_ELPIN_409_SELECT);
5582 I915_WRITE(_3D_CHICKEN2,
5583 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
5584 _3D_CHICKEN2_WM_READ_PIPELINED);
5585
5586 /* WaDisableRenderCachePipelinedFlush:ilk */
5587 I915_WRITE(CACHE_MODE_0,
5588 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
5589
5590 /* WaDisable_RenderCache_OperationalFlush:ilk */
5591 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5592
5593 g4x_disable_trickle_feed(dev);
5594
5595 ibx_init_clock_gating(dev);
5596 }
5597
5598 static void cpt_init_clock_gating(struct drm_device *dev)
5599 {
5600 struct drm_i915_private *dev_priv = dev->dev_private;
5601 int pipe;
5602 uint32_t val;
5603
5604 /*
5605 * On Ibex Peak and Cougar Point, we need to disable clock
5606 * gating for the panel power sequencer or it will fail to
5607 * start up when no ports are active.
5608 */
5609 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
5610 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
5611 PCH_CPUNIT_CLOCK_GATE_DISABLE);
5612 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
5613 DPLS_EDP_PPS_FIX_DIS);
5614 /* The below fixes the weird display corruption, a few pixels shifted
5615 * downward, on (only) LVDS of some HP laptops with IVY.
5616 */
5617 for_each_pipe(dev_priv, pipe) {
5618 val = I915_READ(TRANS_CHICKEN2(pipe));
5619 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
5620 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
5621 if (dev_priv->vbt.fdi_rx_polarity_inverted)
5622 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
5623 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
5624 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
5625 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
5626 I915_WRITE(TRANS_CHICKEN2(pipe), val);
5627 }
5628 /* WADP0ClockGatingDisable */
5629 for_each_pipe(dev_priv, pipe) {
5630 I915_WRITE(TRANS_CHICKEN1(pipe),
5631 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
5632 }
5633 }
5634
5635 static void gen6_check_mch_setup(struct drm_device *dev)
5636 {
5637 struct drm_i915_private *dev_priv = dev->dev_private;
5638 uint32_t tmp;
5639
5640 tmp = I915_READ(MCH_SSKPD);
5641 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
5642 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
5643 tmp);
5644 }
5645
5646 static void gen6_init_clock_gating(struct drm_device *dev)
5647 {
5648 struct drm_i915_private *dev_priv = dev->dev_private;
5649 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
5650
5651 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
5652
5653 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5654 I915_READ(ILK_DISPLAY_CHICKEN2) |
5655 ILK_ELPIN_409_SELECT);
5656
5657 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
5658 I915_WRITE(_3D_CHICKEN,
5659 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
5660
5661 /* WaSetupGtModeTdRowDispatch:snb */
5662 if (IS_SNB_GT1(dev))
5663 I915_WRITE(GEN6_GT_MODE,
5664 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
5665
5666 /* WaDisable_RenderCache_OperationalFlush:snb */
5667 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5668
5669 /*
5670 * BSpec recoomends 8x4 when MSAA is used,
5671 * however in practice 16x4 seems fastest.
5672 *
5673 * Note that PS/WM thread counts depend on the WIZ hashing
5674 * disable bit, which we don't touch here, but it's good
5675 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5676 */
5677 I915_WRITE(GEN6_GT_MODE,
5678 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5679
5680 ilk_init_lp_watermarks(dev);
5681
5682 I915_WRITE(CACHE_MODE_0,
5683 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
5684
5685 I915_WRITE(GEN6_UCGCTL1,
5686 I915_READ(GEN6_UCGCTL1) |
5687 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
5688 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
5689
5690 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5691 * gating disable must be set. Failure to set it results in
5692 * flickering pixels due to Z write ordering failures after
5693 * some amount of runtime in the Mesa "fire" demo, and Unigine
5694 * Sanctuary and Tropics, and apparently anything else with
5695 * alpha test or pixel discard.
5696 *
5697 * According to the spec, bit 11 (RCCUNIT) must also be set,
5698 * but we didn't debug actual testcases to find it out.
5699 *
5700 * WaDisableRCCUnitClockGating:snb
5701 * WaDisableRCPBUnitClockGating:snb
5702 */
5703 I915_WRITE(GEN6_UCGCTL2,
5704 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
5705 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5706
5707 /* WaStripsFansDisableFastClipPerformanceFix:snb */
5708 I915_WRITE(_3D_CHICKEN3,
5709 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
5710
5711 /*
5712 * Bspec says:
5713 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
5714 * 3DSTATE_SF number of SF output attributes is more than 16."
5715 */
5716 I915_WRITE(_3D_CHICKEN3,
5717 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
5718
5719 /*
5720 * According to the spec the following bits should be
5721 * set in order to enable memory self-refresh and fbc:
5722 * The bit21 and bit22 of 0x42000
5723 * The bit21 and bit22 of 0x42004
5724 * The bit5 and bit7 of 0x42020
5725 * The bit14 of 0x70180
5726 * The bit14 of 0x71180
5727 *
5728 * WaFbcAsynchFlipDisableFbcQueue:snb
5729 */
5730 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5731 I915_READ(ILK_DISPLAY_CHICKEN1) |
5732 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
5733 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5734 I915_READ(ILK_DISPLAY_CHICKEN2) |
5735 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
5736 I915_WRITE(ILK_DSPCLK_GATE_D,
5737 I915_READ(ILK_DSPCLK_GATE_D) |
5738 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
5739 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
5740
5741 g4x_disable_trickle_feed(dev);
5742
5743 cpt_init_clock_gating(dev);
5744
5745 gen6_check_mch_setup(dev);
5746 }
5747
5748 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
5749 {
5750 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
5751
5752 /*
5753 * WaVSThreadDispatchOverride:ivb,vlv
5754 *
5755 * This actually overrides the dispatch
5756 * mode for all thread types.
5757 */
5758 reg &= ~GEN7_FF_SCHED_MASK;
5759 reg |= GEN7_FF_TS_SCHED_HW;
5760 reg |= GEN7_FF_VS_SCHED_HW;
5761 reg |= GEN7_FF_DS_SCHED_HW;
5762
5763 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
5764 }
5765
5766 static void lpt_init_clock_gating(struct drm_device *dev)
5767 {
5768 struct drm_i915_private *dev_priv = dev->dev_private;
5769
5770 /*
5771 * TODO: this bit should only be enabled when really needed, then
5772 * disabled when not needed anymore in order to save power.
5773 */
5774 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
5775 I915_WRITE(SOUTH_DSPCLK_GATE_D,
5776 I915_READ(SOUTH_DSPCLK_GATE_D) |
5777 PCH_LP_PARTITION_LEVEL_DISABLE);
5778
5779 /* WADPOClockGatingDisable:hsw */
5780 I915_WRITE(_TRANSA_CHICKEN1,
5781 I915_READ(_TRANSA_CHICKEN1) |
5782 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
5783 }
5784
5785 static void lpt_suspend_hw(struct drm_device *dev)
5786 {
5787 struct drm_i915_private *dev_priv = dev->dev_private;
5788
5789 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
5790 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
5791
5792 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
5793 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
5794 }
5795 }
5796
5797 static void broadwell_init_clock_gating(struct drm_device *dev)
5798 {
5799 struct drm_i915_private *dev_priv = dev->dev_private;
5800 enum pipe pipe;
5801
5802 I915_WRITE(WM3_LP_ILK, 0);
5803 I915_WRITE(WM2_LP_ILK, 0);
5804 I915_WRITE(WM1_LP_ILK, 0);
5805
5806 /* FIXME(BDW): Check all the w/a, some might only apply to
5807 * pre-production hw. */
5808
5809
5810 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE));
5811
5812 I915_WRITE(_3D_CHICKEN3,
5813 _MASKED_BIT_ENABLE(_3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2)));
5814
5815
5816 /* WaSwitchSolVfFArbitrationPriority:bdw */
5817 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
5818
5819 /* WaPsrDPAMaskVBlankInSRD:bdw */
5820 I915_WRITE(CHICKEN_PAR1_1,
5821 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
5822
5823 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
5824 for_each_pipe(dev_priv, pipe) {
5825 I915_WRITE(CHICKEN_PIPESL_1(pipe),
5826 I915_READ(CHICKEN_PIPESL_1(pipe)) |
5827 BDW_DPRS_MASK_VBLANK_SRD);
5828 }
5829
5830 /* WaVSRefCountFullforceMissDisable:bdw */
5831 /* WaDSRefCountFullforceMissDisable:bdw */
5832 I915_WRITE(GEN7_FF_THREAD_MODE,
5833 I915_READ(GEN7_FF_THREAD_MODE) &
5834 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
5835
5836 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
5837 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
5838
5839 /* WaDisableSDEUnitClockGating:bdw */
5840 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
5841 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5842
5843 lpt_init_clock_gating(dev);
5844 }
5845
5846 static void haswell_init_clock_gating(struct drm_device *dev)
5847 {
5848 struct drm_i915_private *dev_priv = dev->dev_private;
5849
5850 ilk_init_lp_watermarks(dev);
5851
5852 /* L3 caching of data atomics doesn't work -- disable it. */
5853 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
5854 I915_WRITE(HSW_ROW_CHICKEN3,
5855 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
5856
5857 /* This is required by WaCatErrorRejectionIssue:hsw */
5858 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5859 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5860 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5861
5862 /* WaVSRefCountFullforceMissDisable:hsw */
5863 I915_WRITE(GEN7_FF_THREAD_MODE,
5864 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
5865
5866 /* WaDisable_RenderCache_OperationalFlush:hsw */
5867 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5868
5869 /* enable HiZ Raw Stall Optimization */
5870 I915_WRITE(CACHE_MODE_0_GEN7,
5871 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
5872
5873 /* WaDisable4x2SubspanOptimization:hsw */
5874 I915_WRITE(CACHE_MODE_1,
5875 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5876
5877 /*
5878 * BSpec recommends 8x4 when MSAA is used,
5879 * however in practice 16x4 seems fastest.
5880 *
5881 * Note that PS/WM thread counts depend on the WIZ hashing
5882 * disable bit, which we don't touch here, but it's good
5883 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5884 */
5885 I915_WRITE(GEN7_GT_MODE,
5886 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5887
5888 /* WaSwitchSolVfFArbitrationPriority:hsw */
5889 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
5890
5891 /* WaRsPkgCStateDisplayPMReq:hsw */
5892 I915_WRITE(CHICKEN_PAR1_1,
5893 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
5894
5895 lpt_init_clock_gating(dev);
5896 }
5897
5898 static void ivybridge_init_clock_gating(struct drm_device *dev)
5899 {
5900 struct drm_i915_private *dev_priv = dev->dev_private;
5901 uint32_t snpcr;
5902
5903 ilk_init_lp_watermarks(dev);
5904
5905 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
5906
5907 /* WaDisableEarlyCull:ivb */
5908 I915_WRITE(_3D_CHICKEN3,
5909 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5910
5911 /* WaDisableBackToBackFlipFix:ivb */
5912 I915_WRITE(IVB_CHICKEN3,
5913 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5914 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5915
5916 /* WaDisablePSDDualDispatchEnable:ivb */
5917 if (IS_IVB_GT1(dev))
5918 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5919 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5920
5921 /* WaDisable_RenderCache_OperationalFlush:ivb */
5922 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5923
5924 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
5925 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5926 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5927
5928 /* WaApplyL3ControlAndL3ChickenMode:ivb */
5929 I915_WRITE(GEN7_L3CNTLREG1,
5930 GEN7_WA_FOR_GEN7_L3_CONTROL);
5931 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
5932 GEN7_WA_L3_CHICKEN_MODE);
5933 if (IS_IVB_GT1(dev))
5934 I915_WRITE(GEN7_ROW_CHICKEN2,
5935 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5936 else {
5937 /* must write both registers */
5938 I915_WRITE(GEN7_ROW_CHICKEN2,
5939 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5940 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
5941 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5942 }
5943
5944 /* WaForceL3Serialization:ivb */
5945 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5946 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5947
5948 /*
5949 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5950 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
5951 */
5952 I915_WRITE(GEN6_UCGCTL2,
5953 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
5954
5955 /* This is required by WaCatErrorRejectionIssue:ivb */
5956 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5957 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5958 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5959
5960 g4x_disable_trickle_feed(dev);
5961
5962 gen7_setup_fixed_func_scheduler(dev_priv);
5963
5964 if (0) { /* causes HiZ corruption on ivb:gt1 */
5965 /* enable HiZ Raw Stall Optimization */
5966 I915_WRITE(CACHE_MODE_0_GEN7,
5967 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
5968 }
5969
5970 /* WaDisable4x2SubspanOptimization:ivb */
5971 I915_WRITE(CACHE_MODE_1,
5972 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5973
5974 /*
5975 * BSpec recommends 8x4 when MSAA is used,
5976 * however in practice 16x4 seems fastest.
5977 *
5978 * Note that PS/WM thread counts depend on the WIZ hashing
5979 * disable bit, which we don't touch here, but it's good
5980 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5981 */
5982 I915_WRITE(GEN7_GT_MODE,
5983 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5984
5985 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5986 snpcr &= ~GEN6_MBC_SNPCR_MASK;
5987 snpcr |= GEN6_MBC_SNPCR_MED;
5988 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5989
5990 if (!HAS_PCH_NOP(dev))
5991 cpt_init_clock_gating(dev);
5992
5993 gen6_check_mch_setup(dev);
5994 }
5995
5996 static void valleyview_init_clock_gating(struct drm_device *dev)
5997 {
5998 struct drm_i915_private *dev_priv = dev->dev_private;
5999
6000 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6001
6002 /* WaDisableEarlyCull:vlv */
6003 I915_WRITE(_3D_CHICKEN3,
6004 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6005
6006 /* WaDisableBackToBackFlipFix:vlv */
6007 I915_WRITE(IVB_CHICKEN3,
6008 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6009 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6010
6011 /* WaPsdDispatchEnable:vlv */
6012 /* WaDisablePSDDualDispatchEnable:vlv */
6013 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6014 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
6015 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
6016
6017 /* WaDisable_RenderCache_OperationalFlush:vlv */
6018 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6019
6020 /* WaForceL3Serialization:vlv */
6021 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6022 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6023
6024 /* WaDisableDopClockGating:vlv */
6025 I915_WRITE(GEN7_ROW_CHICKEN2,
6026 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6027
6028 /* This is required by WaCatErrorRejectionIssue:vlv */
6029 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6030 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6031 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6032
6033 gen7_setup_fixed_func_scheduler(dev_priv);
6034
6035 /*
6036 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6037 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
6038 */
6039 I915_WRITE(GEN6_UCGCTL2,
6040 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
6041
6042 /* WaDisableL3Bank2xClockGate:vlv
6043 * Disabling L3 clock gating- MMIO 940c[25] = 1
6044 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
6045 I915_WRITE(GEN7_UCGCTL4,
6046 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
6047
6048 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6049
6050 /*
6051 * BSpec says this must be set, even though
6052 * WaDisable4x2SubspanOptimization isn't listed for VLV.
6053 */
6054 I915_WRITE(CACHE_MODE_1,
6055 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6056
6057 /*
6058 * WaIncreaseL3CreditsForVLVB0:vlv
6059 * This is the hardware default actually.
6060 */
6061 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
6062
6063 /*
6064 * WaDisableVLVClockGating_VBIIssue:vlv
6065 * Disable clock gating on th GCFG unit to prevent a delay
6066 * in the reporting of vblank events.
6067 */
6068 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6069 }
6070
6071 static void cherryview_init_clock_gating(struct drm_device *dev)
6072 {
6073 struct drm_i915_private *dev_priv = dev->dev_private;
6074
6075 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6076
6077 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6078
6079 /* WaVSRefCountFullforceMissDisable:chv */
6080 /* WaDSRefCountFullforceMissDisable:chv */
6081 I915_WRITE(GEN7_FF_THREAD_MODE,
6082 I915_READ(GEN7_FF_THREAD_MODE) &
6083 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
6084
6085 /* WaDisableSemaphoreAndSyncFlipWait:chv */
6086 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6087 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
6088
6089 /* WaDisableCSUnitClockGating:chv */
6090 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
6091 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6092
6093 /* WaDisableSDEUnitClockGating:chv */
6094 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6095 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6096
6097 /* WaDisableGunitClockGating:chv (pre-production hw) */
6098 I915_WRITE(VLV_GUNIT_CLOCK_GATE, I915_READ(VLV_GUNIT_CLOCK_GATE) |
6099 GINT_DIS);
6100
6101 /* WaDisableFfDopClockGating:chv (pre-production hw) */
6102 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6103 _MASKED_BIT_ENABLE(GEN8_FF_DOP_CLOCK_GATE_DISABLE));
6104
6105 /* WaDisableDopClockGating:chv (pre-production hw) */
6106 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
6107 GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
6108 }
6109
6110 static void g4x_init_clock_gating(struct drm_device *dev)
6111 {
6112 struct drm_i915_private *dev_priv = dev->dev_private;
6113 uint32_t dspclk_gate;
6114
6115 I915_WRITE(RENCLK_GATE_D1, 0);
6116 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
6117 GS_UNIT_CLOCK_GATE_DISABLE |
6118 CL_UNIT_CLOCK_GATE_DISABLE);
6119 I915_WRITE(RAMCLK_GATE_D, 0);
6120 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
6121 OVRUNIT_CLOCK_GATE_DISABLE |
6122 OVCUNIT_CLOCK_GATE_DISABLE;
6123 if (IS_GM45(dev))
6124 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
6125 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
6126
6127 /* WaDisableRenderCachePipelinedFlush */
6128 I915_WRITE(CACHE_MODE_0,
6129 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6130
6131 /* WaDisable_RenderCache_OperationalFlush:g4x */
6132 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6133
6134 g4x_disable_trickle_feed(dev);
6135 }
6136
6137 static void crestline_init_clock_gating(struct drm_device *dev)
6138 {
6139 struct drm_i915_private *dev_priv = dev->dev_private;
6140
6141 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
6142 I915_WRITE(RENCLK_GATE_D2, 0);
6143 I915_WRITE(DSPCLK_GATE_D, 0);
6144 I915_WRITE(RAMCLK_GATE_D, 0);
6145 I915_WRITE16(DEUC, 0);
6146 I915_WRITE(MI_ARB_STATE,
6147 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6148
6149 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6150 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6151 }
6152
6153 static void broadwater_init_clock_gating(struct drm_device *dev)
6154 {
6155 struct drm_i915_private *dev_priv = dev->dev_private;
6156
6157 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
6158 I965_RCC_CLOCK_GATE_DISABLE |
6159 I965_RCPB_CLOCK_GATE_DISABLE |
6160 I965_ISC_CLOCK_GATE_DISABLE |
6161 I965_FBC_CLOCK_GATE_DISABLE);
6162 I915_WRITE(RENCLK_GATE_D2, 0);
6163 I915_WRITE(MI_ARB_STATE,
6164 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6165
6166 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6167 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6168 }
6169
6170 static void gen3_init_clock_gating(struct drm_device *dev)
6171 {
6172 struct drm_i915_private *dev_priv = dev->dev_private;
6173 u32 dstate = I915_READ(D_STATE);
6174
6175 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
6176 DSTATE_DOT_CLOCK_GATING;
6177 I915_WRITE(D_STATE, dstate);
6178
6179 if (IS_PINEVIEW(dev))
6180 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
6181
6182 /* IIR "flip pending" means done if this bit is set */
6183 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
6184
6185 /* interrupts should cause a wake up from C3 */
6186 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
6187
6188 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
6189 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
6190
6191 I915_WRITE(MI_ARB_STATE,
6192 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6193 }
6194
6195 static void i85x_init_clock_gating(struct drm_device *dev)
6196 {
6197 struct drm_i915_private *dev_priv = dev->dev_private;
6198
6199 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
6200
6201 /* interrupts should cause a wake up from C3 */
6202 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
6203 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
6204
6205 I915_WRITE(MEM_MODE,
6206 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
6207 }
6208
6209 static void i830_init_clock_gating(struct drm_device *dev)
6210 {
6211 struct drm_i915_private *dev_priv = dev->dev_private;
6212
6213 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
6214
6215 I915_WRITE(MEM_MODE,
6216 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
6217 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
6218 }
6219
6220 void intel_init_clock_gating(struct drm_device *dev)
6221 {
6222 struct drm_i915_private *dev_priv = dev->dev_private;
6223
6224 dev_priv->display.init_clock_gating(dev);
6225 }
6226
6227 void intel_suspend_hw(struct drm_device *dev)
6228 {
6229 if (HAS_PCH_LPT(dev))
6230 lpt_suspend_hw(dev);
6231 }
6232
6233 #define for_each_power_well(i, power_well, domain_mask, power_domains) \
6234 for (i = 0; \
6235 i < (power_domains)->power_well_count && \
6236 ((power_well) = &(power_domains)->power_wells[i]); \
6237 i++) \
6238 if ((power_well)->domains & (domain_mask))
6239
6240 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
6241 for (i = (power_domains)->power_well_count - 1; \
6242 i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
6243 i--) \
6244 if ((power_well)->domains & (domain_mask))
6245
6246 /**
6247 * We should only use the power well if we explicitly asked the hardware to
6248 * enable it, so check if it's enabled and also check if we've requested it to
6249 * be enabled.
6250 */
6251 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
6252 struct i915_power_well *power_well)
6253 {
6254 return I915_READ(HSW_PWR_WELL_DRIVER) ==
6255 (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
6256 }
6257
6258 bool intel_display_power_enabled_unlocked(struct drm_i915_private *dev_priv,
6259 enum intel_display_power_domain domain)
6260 {
6261 struct i915_power_domains *power_domains;
6262 struct i915_power_well *power_well;
6263 bool is_enabled;
6264 int i;
6265
6266 if (dev_priv->pm.suspended)
6267 return false;
6268
6269 power_domains = &dev_priv->power_domains;
6270
6271 is_enabled = true;
6272
6273 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
6274 if (power_well->always_on)
6275 continue;
6276
6277 if (!power_well->hw_enabled) {
6278 is_enabled = false;
6279 break;
6280 }
6281 }
6282
6283 return is_enabled;
6284 }
6285
6286 bool intel_display_power_enabled(struct drm_i915_private *dev_priv,
6287 enum intel_display_power_domain domain)
6288 {
6289 struct i915_power_domains *power_domains;
6290 bool ret;
6291
6292 power_domains = &dev_priv->power_domains;
6293
6294 mutex_lock(&power_domains->lock);
6295 ret = intel_display_power_enabled_unlocked(dev_priv, domain);
6296 mutex_unlock(&power_domains->lock);
6297
6298 return ret;
6299 }
6300
6301 /*
6302 * Starting with Haswell, we have a "Power Down Well" that can be turned off
6303 * when not needed anymore. We have 4 registers that can request the power well
6304 * to be enabled, and it will only be disabled if none of the registers is
6305 * requesting it to be enabled.
6306 */
6307 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
6308 {
6309 struct drm_device *dev = dev_priv->dev;
6310
6311 /*
6312 * After we re-enable the power well, if we touch VGA register 0x3d5
6313 * we'll get unclaimed register interrupts. This stops after we write
6314 * anything to the VGA MSR register. The vgacon module uses this
6315 * register all the time, so if we unbind our driver and, as a
6316 * consequence, bind vgacon, we'll get stuck in an infinite loop at
6317 * console_unlock(). So make here we touch the VGA MSR register, making
6318 * sure vgacon can keep working normally without triggering interrupts
6319 * and error messages.
6320 */
6321 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
6322 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
6323 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
6324
6325 if (IS_BROADWELL(dev) || (INTEL_INFO(dev)->gen >= 9))
6326 gen8_irq_power_well_post_enable(dev_priv);
6327 }
6328
6329 static void hsw_set_power_well(struct drm_i915_private *dev_priv,
6330 struct i915_power_well *power_well, bool enable)
6331 {
6332 bool is_enabled, enable_requested;
6333 uint32_t tmp;
6334
6335 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
6336 is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
6337 enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
6338
6339 if (enable) {
6340 if (!enable_requested)
6341 I915_WRITE(HSW_PWR_WELL_DRIVER,
6342 HSW_PWR_WELL_ENABLE_REQUEST);
6343
6344 if (!is_enabled) {
6345 DRM_DEBUG_KMS("Enabling power well\n");
6346 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
6347 HSW_PWR_WELL_STATE_ENABLED), 20))
6348 DRM_ERROR("Timeout enabling power well\n");
6349 }
6350
6351 hsw_power_well_post_enable(dev_priv);
6352 } else {
6353 if (enable_requested) {
6354 I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
6355 POSTING_READ(HSW_PWR_WELL_DRIVER);
6356 DRM_DEBUG_KMS("Requesting to disable the power well\n");
6357 }
6358 }
6359 }
6360
6361 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
6362 struct i915_power_well *power_well)
6363 {
6364 hsw_set_power_well(dev_priv, power_well, power_well->count > 0);
6365
6366 /*
6367 * We're taking over the BIOS, so clear any requests made by it since
6368 * the driver is in charge now.
6369 */
6370 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
6371 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
6372 }
6373
6374 static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
6375 struct i915_power_well *power_well)
6376 {
6377 hsw_set_power_well(dev_priv, power_well, true);
6378 }
6379
6380 static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
6381 struct i915_power_well *power_well)
6382 {
6383 hsw_set_power_well(dev_priv, power_well, false);
6384 }
6385
6386 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
6387 struct i915_power_well *power_well)
6388 {
6389 }
6390
6391 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
6392 struct i915_power_well *power_well)
6393 {
6394 return true;
6395 }
6396
6397 static void vlv_set_power_well(struct drm_i915_private *dev_priv,
6398 struct i915_power_well *power_well, bool enable)
6399 {
6400 enum punit_power_well power_well_id = power_well->data;
6401 u32 mask;
6402 u32 state;
6403 u32 ctrl;
6404
6405 mask = PUNIT_PWRGT_MASK(power_well_id);
6406 state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) :
6407 PUNIT_PWRGT_PWR_GATE(power_well_id);
6408
6409 mutex_lock(&dev_priv->rps.hw_lock);
6410
6411 #define COND \
6412 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
6413
6414 if (COND)
6415 goto out;
6416
6417 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
6418 ctrl &= ~mask;
6419 ctrl |= state;
6420 vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
6421
6422 if (wait_for(COND, 100))
6423 DRM_ERROR("timout setting power well state %08x (%08x)\n",
6424 state,
6425 vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
6426
6427 #undef COND
6428
6429 out:
6430 mutex_unlock(&dev_priv->rps.hw_lock);
6431 }
6432
6433 static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv,
6434 struct i915_power_well *power_well)
6435 {
6436 vlv_set_power_well(dev_priv, power_well, power_well->count > 0);
6437 }
6438
6439 static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
6440 struct i915_power_well *power_well)
6441 {
6442 vlv_set_power_well(dev_priv, power_well, true);
6443 }
6444
6445 static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
6446 struct i915_power_well *power_well)
6447 {
6448 vlv_set_power_well(dev_priv, power_well, false);
6449 }
6450
6451 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
6452 struct i915_power_well *power_well)
6453 {
6454 int power_well_id = power_well->data;
6455 bool enabled = false;
6456 u32 mask;
6457 u32 state;
6458 u32 ctrl;
6459
6460 mask = PUNIT_PWRGT_MASK(power_well_id);
6461 ctrl = PUNIT_PWRGT_PWR_ON(power_well_id);
6462
6463 mutex_lock(&dev_priv->rps.hw_lock);
6464
6465 state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
6466 /*
6467 * We only ever set the power-on and power-gate states, anything
6468 * else is unexpected.
6469 */
6470 WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) &&
6471 state != PUNIT_PWRGT_PWR_GATE(power_well_id));
6472 if (state == ctrl)
6473 enabled = true;
6474
6475 /*
6476 * A transient state at this point would mean some unexpected party
6477 * is poking at the power controls too.
6478 */
6479 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
6480 WARN_ON(ctrl != state);
6481
6482 mutex_unlock(&dev_priv->rps.hw_lock);
6483
6484 return enabled;
6485 }
6486
6487 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
6488 struct i915_power_well *power_well)
6489 {
6490 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
6491
6492 vlv_set_power_well(dev_priv, power_well, true);
6493
6494 spin_lock_irq(&dev_priv->irq_lock);
6495 valleyview_enable_display_irqs(dev_priv);
6496 spin_unlock_irq(&dev_priv->irq_lock);
6497
6498 /*
6499 * During driver initialization/resume we can avoid restoring the
6500 * part of the HW/SW state that will be inited anyway explicitly.
6501 */
6502 if (dev_priv->power_domains.initializing)
6503 return;
6504
6505 intel_hpd_init(dev_priv->dev);
6506
6507 i915_redisable_vga_power_on(dev_priv->dev);
6508 }
6509
6510 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
6511 struct i915_power_well *power_well)
6512 {
6513 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
6514
6515 spin_lock_irq(&dev_priv->irq_lock);
6516 valleyview_disable_display_irqs(dev_priv);
6517 spin_unlock_irq(&dev_priv->irq_lock);
6518
6519 vlv_set_power_well(dev_priv, power_well, false);
6520
6521 vlv_power_sequencer_reset(dev_priv);
6522 }
6523
6524 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
6525 struct i915_power_well *power_well)
6526 {
6527 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
6528
6529 /*
6530 * Enable the CRI clock source so we can get at the
6531 * display and the reference clock for VGA
6532 * hotplug / manual detection.
6533 */
6534 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
6535 DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
6536 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
6537
6538 vlv_set_power_well(dev_priv, power_well, true);
6539
6540 /*
6541 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
6542 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
6543 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
6544 * b. The other bits such as sfr settings / modesel may all
6545 * be set to 0.
6546 *
6547 * This should only be done on init and resume from S3 with
6548 * both PLLs disabled, or we risk losing DPIO and PLL
6549 * synchronization.
6550 */
6551 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
6552 }
6553
6554 static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
6555 struct i915_power_well *power_well)
6556 {
6557 enum pipe pipe;
6558
6559 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
6560
6561 for_each_pipe(dev_priv, pipe)
6562 assert_pll_disabled(dev_priv, pipe);
6563
6564 /* Assert common reset */
6565 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST);
6566
6567 vlv_set_power_well(dev_priv, power_well, false);
6568 }
6569
6570 static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
6571 struct i915_power_well *power_well)
6572 {
6573 enum dpio_phy phy;
6574
6575 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
6576 power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
6577
6578 /*
6579 * Enable the CRI clock source so we can get at the
6580 * display and the reference clock for VGA
6581 * hotplug / manual detection.
6582 */
6583 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
6584 phy = DPIO_PHY0;
6585 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
6586 DPLL_REFA_CLK_ENABLE_VLV);
6587 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
6588 DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
6589 } else {
6590 phy = DPIO_PHY1;
6591 I915_WRITE(DPLL(PIPE_C), I915_READ(DPLL(PIPE_C)) |
6592 DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
6593 }
6594 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
6595 vlv_set_power_well(dev_priv, power_well, true);
6596
6597 /* Poll for phypwrgood signal */
6598 if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1))
6599 DRM_ERROR("Display PHY %d is not power up\n", phy);
6600
6601 I915_WRITE(DISPLAY_PHY_CONTROL, I915_READ(DISPLAY_PHY_CONTROL) |
6602 PHY_COM_LANE_RESET_DEASSERT(phy));
6603 }
6604
6605 static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
6606 struct i915_power_well *power_well)
6607 {
6608 enum dpio_phy phy;
6609
6610 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
6611 power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
6612
6613 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
6614 phy = DPIO_PHY0;
6615 assert_pll_disabled(dev_priv, PIPE_A);
6616 assert_pll_disabled(dev_priv, PIPE_B);
6617 } else {
6618 phy = DPIO_PHY1;
6619 assert_pll_disabled(dev_priv, PIPE_C);
6620 }
6621
6622 I915_WRITE(DISPLAY_PHY_CONTROL, I915_READ(DISPLAY_PHY_CONTROL) &
6623 ~PHY_COM_LANE_RESET_DEASSERT(phy));
6624
6625 vlv_set_power_well(dev_priv, power_well, false);
6626 }
6627
6628 static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,
6629 struct i915_power_well *power_well)
6630 {
6631 enum pipe pipe = power_well->data;
6632 bool enabled;
6633 u32 state, ctrl;
6634
6635 mutex_lock(&dev_priv->rps.hw_lock);
6636
6637 state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe);
6638 /*
6639 * We only ever set the power-on and power-gate states, anything
6640 * else is unexpected.
6641 */
6642 WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe));
6643 enabled = state == DP_SSS_PWR_ON(pipe);
6644
6645 /*
6646 * A transient state at this point would mean some unexpected party
6647 * is poking at the power controls too.
6648 */
6649 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe);
6650 WARN_ON(ctrl << 16 != state);
6651
6652 mutex_unlock(&dev_priv->rps.hw_lock);
6653
6654 return enabled;
6655 }
6656
6657 static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
6658 struct i915_power_well *power_well,
6659 bool enable)
6660 {
6661 enum pipe pipe = power_well->data;
6662 u32 state;
6663 u32 ctrl;
6664
6665 state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe);
6666
6667 mutex_lock(&dev_priv->rps.hw_lock);
6668
6669 #define COND \
6670 ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state)
6671
6672 if (COND)
6673 goto out;
6674
6675 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
6676 ctrl &= ~DP_SSC_MASK(pipe);
6677 ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe);
6678 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl);
6679
6680 if (wait_for(COND, 100))
6681 DRM_ERROR("timout setting power well state %08x (%08x)\n",
6682 state,
6683 vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ));
6684
6685 #undef COND
6686
6687 out:
6688 mutex_unlock(&dev_priv->rps.hw_lock);
6689 }
6690
6691 static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv,
6692 struct i915_power_well *power_well)
6693 {
6694 chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0);
6695 }
6696
6697 static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
6698 struct i915_power_well *power_well)
6699 {
6700 WARN_ON_ONCE(power_well->data != PIPE_A &&
6701 power_well->data != PIPE_B &&
6702 power_well->data != PIPE_C);
6703
6704 chv_set_pipe_power_well(dev_priv, power_well, true);
6705 }
6706
6707 static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
6708 struct i915_power_well *power_well)
6709 {
6710 WARN_ON_ONCE(power_well->data != PIPE_A &&
6711 power_well->data != PIPE_B &&
6712 power_well->data != PIPE_C);
6713
6714 chv_set_pipe_power_well(dev_priv, power_well, false);
6715 }
6716
6717 static void check_power_well_state(struct drm_i915_private *dev_priv,
6718 struct i915_power_well *power_well)
6719 {
6720 bool enabled = power_well->ops->is_enabled(dev_priv, power_well);
6721
6722 if (power_well->always_on || !i915.disable_power_well) {
6723 if (!enabled)
6724 goto mismatch;
6725
6726 return;
6727 }
6728
6729 if (enabled != (power_well->count > 0))
6730 goto mismatch;
6731
6732 return;
6733
6734 mismatch:
6735 WARN(1, "state mismatch for '%s' (always_on %d hw state %d use-count %d disable_power_well %d\n",
6736 power_well->name, power_well->always_on, enabled,
6737 power_well->count, i915.disable_power_well);
6738 }
6739
6740 void intel_display_power_get(struct drm_i915_private *dev_priv,
6741 enum intel_display_power_domain domain)
6742 {
6743 struct i915_power_domains *power_domains;
6744 struct i915_power_well *power_well;
6745 int i;
6746
6747 intel_runtime_pm_get(dev_priv);
6748
6749 power_domains = &dev_priv->power_domains;
6750
6751 mutex_lock(&power_domains->lock);
6752
6753 for_each_power_well(i, power_well, BIT(domain), power_domains) {
6754 if (!power_well->count++) {
6755 DRM_DEBUG_KMS("enabling %s\n", power_well->name);
6756 power_well->ops->enable(dev_priv, power_well);
6757 power_well->hw_enabled = true;
6758 }
6759
6760 check_power_well_state(dev_priv, power_well);
6761 }
6762
6763 power_domains->domain_use_count[domain]++;
6764
6765 mutex_unlock(&power_domains->lock);
6766 }
6767
6768 void intel_display_power_put(struct drm_i915_private *dev_priv,
6769 enum intel_display_power_domain domain)
6770 {
6771 struct i915_power_domains *power_domains;
6772 struct i915_power_well *power_well;
6773 int i;
6774
6775 power_domains = &dev_priv->power_domains;
6776
6777 mutex_lock(&power_domains->lock);
6778
6779 WARN_ON(!power_domains->domain_use_count[domain]);
6780 power_domains->domain_use_count[domain]--;
6781
6782 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
6783 WARN_ON(!power_well->count);
6784
6785 if (!--power_well->count && i915.disable_power_well) {
6786 DRM_DEBUG_KMS("disabling %s\n", power_well->name);
6787 power_well->hw_enabled = false;
6788 power_well->ops->disable(dev_priv, power_well);
6789 }
6790
6791 check_power_well_state(dev_priv, power_well);
6792 }
6793
6794 mutex_unlock(&power_domains->lock);
6795
6796 intel_runtime_pm_put(dev_priv);
6797 }
6798
6799 static struct i915_power_domains *hsw_pwr;
6800
6801 /* Display audio driver power well request */
6802 int i915_request_power_well(void)
6803 {
6804 struct drm_i915_private *dev_priv;
6805
6806 if (!hsw_pwr)
6807 return -ENODEV;
6808
6809 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
6810 power_domains);
6811 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
6812 return 0;
6813 }
6814 EXPORT_SYMBOL_GPL(i915_request_power_well);
6815
6816 /* Display audio driver power well release */
6817 int i915_release_power_well(void)
6818 {
6819 struct drm_i915_private *dev_priv;
6820
6821 if (!hsw_pwr)
6822 return -ENODEV;
6823
6824 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
6825 power_domains);
6826 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
6827 return 0;
6828 }
6829 EXPORT_SYMBOL_GPL(i915_release_power_well);
6830
6831 /*
6832 * Private interface for the audio driver to get CDCLK in kHz.
6833 *
6834 * Caller must request power well using i915_request_power_well() prior to
6835 * making the call.
6836 */
6837 int i915_get_cdclk_freq(void)
6838 {
6839 struct drm_i915_private *dev_priv;
6840
6841 if (!hsw_pwr)
6842 return -ENODEV;
6843
6844 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
6845 power_domains);
6846
6847 return intel_ddi_get_cdclk_freq(dev_priv);
6848 }
6849 EXPORT_SYMBOL_GPL(i915_get_cdclk_freq);
6850
6851
6852 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
6853
6854 #define HSW_ALWAYS_ON_POWER_DOMAINS ( \
6855 BIT(POWER_DOMAIN_PIPE_A) | \
6856 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
6857 BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
6858 BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
6859 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6860 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6861 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6862 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6863 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
6864 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
6865 BIT(POWER_DOMAIN_PORT_CRT) | \
6866 BIT(POWER_DOMAIN_PLLS) | \
6867 BIT(POWER_DOMAIN_INIT))
6868 #define HSW_DISPLAY_POWER_DOMAINS ( \
6869 (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \
6870 BIT(POWER_DOMAIN_INIT))
6871
6872 #define BDW_ALWAYS_ON_POWER_DOMAINS ( \
6873 HSW_ALWAYS_ON_POWER_DOMAINS | \
6874 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
6875 #define BDW_DISPLAY_POWER_DOMAINS ( \
6876 (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) | \
6877 BIT(POWER_DOMAIN_INIT))
6878
6879 #define VLV_ALWAYS_ON_POWER_DOMAINS BIT(POWER_DOMAIN_INIT)
6880 #define VLV_DISPLAY_POWER_DOMAINS POWER_DOMAIN_MASK
6881
6882 #define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \
6883 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6884 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6885 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6886 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6887 BIT(POWER_DOMAIN_PORT_CRT) | \
6888 BIT(POWER_DOMAIN_INIT))
6889
6890 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \
6891 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6892 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6893 BIT(POWER_DOMAIN_INIT))
6894
6895 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \
6896 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6897 BIT(POWER_DOMAIN_INIT))
6898
6899 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \
6900 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6901 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6902 BIT(POWER_DOMAIN_INIT))
6903
6904 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \
6905 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6906 BIT(POWER_DOMAIN_INIT))
6907
6908 #define CHV_PIPE_A_POWER_DOMAINS ( \
6909 BIT(POWER_DOMAIN_PIPE_A) | \
6910 BIT(POWER_DOMAIN_INIT))
6911
6912 #define CHV_PIPE_B_POWER_DOMAINS ( \
6913 BIT(POWER_DOMAIN_PIPE_B) | \
6914 BIT(POWER_DOMAIN_INIT))
6915
6916 #define CHV_PIPE_C_POWER_DOMAINS ( \
6917 BIT(POWER_DOMAIN_PIPE_C) | \
6918 BIT(POWER_DOMAIN_INIT))
6919
6920 #define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \
6921 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6922 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6923 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6924 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6925 BIT(POWER_DOMAIN_INIT))
6926
6927 #define CHV_DPIO_CMN_D_POWER_DOMAINS ( \
6928 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
6929 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
6930 BIT(POWER_DOMAIN_INIT))
6931
6932 #define CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS ( \
6933 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
6934 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
6935 BIT(POWER_DOMAIN_INIT))
6936
6937 #define CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS ( \
6938 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
6939 BIT(POWER_DOMAIN_INIT))
6940
6941 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
6942 .sync_hw = i9xx_always_on_power_well_noop,
6943 .enable = i9xx_always_on_power_well_noop,
6944 .disable = i9xx_always_on_power_well_noop,
6945 .is_enabled = i9xx_always_on_power_well_enabled,
6946 };
6947
6948 static const struct i915_power_well_ops chv_pipe_power_well_ops = {
6949 .sync_hw = chv_pipe_power_well_sync_hw,
6950 .enable = chv_pipe_power_well_enable,
6951 .disable = chv_pipe_power_well_disable,
6952 .is_enabled = chv_pipe_power_well_enabled,
6953 };
6954
6955 static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = {
6956 .sync_hw = vlv_power_well_sync_hw,
6957 .enable = chv_dpio_cmn_power_well_enable,
6958 .disable = chv_dpio_cmn_power_well_disable,
6959 .is_enabled = vlv_power_well_enabled,
6960 };
6961
6962 static struct i915_power_well i9xx_always_on_power_well[] = {
6963 {
6964 .name = "always-on",
6965 .always_on = 1,
6966 .domains = POWER_DOMAIN_MASK,
6967 .ops = &i9xx_always_on_power_well_ops,
6968 },
6969 };
6970
6971 static const struct i915_power_well_ops hsw_power_well_ops = {
6972 .sync_hw = hsw_power_well_sync_hw,
6973 .enable = hsw_power_well_enable,
6974 .disable = hsw_power_well_disable,
6975 .is_enabled = hsw_power_well_enabled,
6976 };
6977
6978 static struct i915_power_well hsw_power_wells[] = {
6979 {
6980 .name = "always-on",
6981 .always_on = 1,
6982 .domains = HSW_ALWAYS_ON_POWER_DOMAINS,
6983 .ops = &i9xx_always_on_power_well_ops,
6984 },
6985 {
6986 .name = "display",
6987 .domains = HSW_DISPLAY_POWER_DOMAINS,
6988 .ops = &hsw_power_well_ops,
6989 },
6990 };
6991
6992 static struct i915_power_well bdw_power_wells[] = {
6993 {
6994 .name = "always-on",
6995 .always_on = 1,
6996 .domains = BDW_ALWAYS_ON_POWER_DOMAINS,
6997 .ops = &i9xx_always_on_power_well_ops,
6998 },
6999 {
7000 .name = "display",
7001 .domains = BDW_DISPLAY_POWER_DOMAINS,
7002 .ops = &hsw_power_well_ops,
7003 },
7004 };
7005
7006 static const struct i915_power_well_ops vlv_display_power_well_ops = {
7007 .sync_hw = vlv_power_well_sync_hw,
7008 .enable = vlv_display_power_well_enable,
7009 .disable = vlv_display_power_well_disable,
7010 .is_enabled = vlv_power_well_enabled,
7011 };
7012
7013 static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = {
7014 .sync_hw = vlv_power_well_sync_hw,
7015 .enable = vlv_dpio_cmn_power_well_enable,
7016 .disable = vlv_dpio_cmn_power_well_disable,
7017 .is_enabled = vlv_power_well_enabled,
7018 };
7019
7020 static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
7021 .sync_hw = vlv_power_well_sync_hw,
7022 .enable = vlv_power_well_enable,
7023 .disable = vlv_power_well_disable,
7024 .is_enabled = vlv_power_well_enabled,
7025 };
7026
7027 static struct i915_power_well vlv_power_wells[] = {
7028 {
7029 .name = "always-on",
7030 .always_on = 1,
7031 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
7032 .ops = &i9xx_always_on_power_well_ops,
7033 },
7034 {
7035 .name = "display",
7036 .domains = VLV_DISPLAY_POWER_DOMAINS,
7037 .data = PUNIT_POWER_WELL_DISP2D,
7038 .ops = &vlv_display_power_well_ops,
7039 },
7040 {
7041 .name = "dpio-tx-b-01",
7042 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
7043 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
7044 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
7045 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
7046 .ops = &vlv_dpio_power_well_ops,
7047 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
7048 },
7049 {
7050 .name = "dpio-tx-b-23",
7051 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
7052 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
7053 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
7054 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
7055 .ops = &vlv_dpio_power_well_ops,
7056 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
7057 },
7058 {
7059 .name = "dpio-tx-c-01",
7060 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
7061 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
7062 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
7063 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
7064 .ops = &vlv_dpio_power_well_ops,
7065 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
7066 },
7067 {
7068 .name = "dpio-tx-c-23",
7069 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
7070 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
7071 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
7072 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
7073 .ops = &vlv_dpio_power_well_ops,
7074 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
7075 },
7076 {
7077 .name = "dpio-common",
7078 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
7079 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
7080 .ops = &vlv_dpio_cmn_power_well_ops,
7081 },
7082 };
7083
7084 static struct i915_power_well chv_power_wells[] = {
7085 {
7086 .name = "always-on",
7087 .always_on = 1,
7088 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
7089 .ops = &i9xx_always_on_power_well_ops,
7090 },
7091 #if 0
7092 {
7093 .name = "display",
7094 .domains = VLV_DISPLAY_POWER_DOMAINS,
7095 .data = PUNIT_POWER_WELL_DISP2D,
7096 .ops = &vlv_display_power_well_ops,
7097 },
7098 {
7099 .name = "pipe-a",
7100 .domains = CHV_PIPE_A_POWER_DOMAINS,
7101 .data = PIPE_A,
7102 .ops = &chv_pipe_power_well_ops,
7103 },
7104 {
7105 .name = "pipe-b",
7106 .domains = CHV_PIPE_B_POWER_DOMAINS,
7107 .data = PIPE_B,
7108 .ops = &chv_pipe_power_well_ops,
7109 },
7110 {
7111 .name = "pipe-c",
7112 .domains = CHV_PIPE_C_POWER_DOMAINS,
7113 .data = PIPE_C,
7114 .ops = &chv_pipe_power_well_ops,
7115 },
7116 #endif
7117 {
7118 .name = "dpio-common-bc",
7119 /*
7120 * XXX: cmnreset for one PHY seems to disturb the other.
7121 * As a workaround keep both powered on at the same
7122 * time for now.
7123 */
7124 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS | CHV_DPIO_CMN_D_POWER_DOMAINS,
7125 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
7126 .ops = &chv_dpio_cmn_power_well_ops,
7127 },
7128 {
7129 .name = "dpio-common-d",
7130 /*
7131 * XXX: cmnreset for one PHY seems to disturb the other.
7132 * As a workaround keep both powered on at the same
7133 * time for now.
7134 */
7135 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS | CHV_DPIO_CMN_D_POWER_DOMAINS,
7136 .data = PUNIT_POWER_WELL_DPIO_CMN_D,
7137 .ops = &chv_dpio_cmn_power_well_ops,
7138 },
7139 #if 0
7140 {
7141 .name = "dpio-tx-b-01",
7142 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
7143 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS,
7144 .ops = &vlv_dpio_power_well_ops,
7145 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
7146 },
7147 {
7148 .name = "dpio-tx-b-23",
7149 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
7150 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS,
7151 .ops = &vlv_dpio_power_well_ops,
7152 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
7153 },
7154 {
7155 .name = "dpio-tx-c-01",
7156 .domains = VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
7157 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
7158 .ops = &vlv_dpio_power_well_ops,
7159 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
7160 },
7161 {
7162 .name = "dpio-tx-c-23",
7163 .domains = VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
7164 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
7165 .ops = &vlv_dpio_power_well_ops,
7166 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
7167 },
7168 {
7169 .name = "dpio-tx-d-01",
7170 .domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS |
7171 CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS,
7172 .ops = &vlv_dpio_power_well_ops,
7173 .data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_01,
7174 },
7175 {
7176 .name = "dpio-tx-d-23",
7177 .domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS |
7178 CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS,
7179 .ops = &vlv_dpio_power_well_ops,
7180 .data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_23,
7181 },
7182 #endif
7183 };
7184
7185 static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv,
7186 enum punit_power_well power_well_id)
7187 {
7188 struct i915_power_domains *power_domains = &dev_priv->power_domains;
7189 struct i915_power_well *power_well;
7190 int i;
7191
7192 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
7193 if (power_well->data == power_well_id)
7194 return power_well;
7195 }
7196
7197 return NULL;
7198 }
7199
7200 #define set_power_wells(power_domains, __power_wells) ({ \
7201 (power_domains)->power_wells = (__power_wells); \
7202 (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \
7203 })
7204
7205 int intel_power_domains_init(struct drm_i915_private *dev_priv)
7206 {
7207 struct i915_power_domains *power_domains = &dev_priv->power_domains;
7208
7209 mutex_init(&power_domains->lock);
7210
7211 /*
7212 * The enabling order will be from lower to higher indexed wells,
7213 * the disabling order is reversed.
7214 */
7215 if (IS_HASWELL(dev_priv->dev)) {
7216 set_power_wells(power_domains, hsw_power_wells);
7217 hsw_pwr = power_domains;
7218 } else if (IS_BROADWELL(dev_priv->dev)) {
7219 set_power_wells(power_domains, bdw_power_wells);
7220 hsw_pwr = power_domains;
7221 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
7222 set_power_wells(power_domains, chv_power_wells);
7223 } else if (IS_VALLEYVIEW(dev_priv->dev)) {
7224 set_power_wells(power_domains, vlv_power_wells);
7225 } else {
7226 set_power_wells(power_domains, i9xx_always_on_power_well);
7227 }
7228
7229 return 0;
7230 }
7231
7232 void intel_power_domains_remove(struct drm_i915_private *dev_priv)
7233 {
7234 hsw_pwr = NULL;
7235 }
7236
7237 static void intel_power_domains_resume(struct drm_i915_private *dev_priv)
7238 {
7239 struct i915_power_domains *power_domains = &dev_priv->power_domains;
7240 struct i915_power_well *power_well;
7241 int i;
7242
7243 mutex_lock(&power_domains->lock);
7244 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
7245 power_well->ops->sync_hw(dev_priv, power_well);
7246 power_well->hw_enabled = power_well->ops->is_enabled(dev_priv,
7247 power_well);
7248 }
7249 mutex_unlock(&power_domains->lock);
7250 }
7251
7252 static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
7253 {
7254 struct i915_power_well *cmn =
7255 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
7256 struct i915_power_well *disp2d =
7257 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D);
7258
7259 /* nothing to do if common lane is already off */
7260 if (!cmn->ops->is_enabled(dev_priv, cmn))
7261 return;
7262
7263 /* If the display might be already active skip this */
7264 if (disp2d->ops->is_enabled(dev_priv, disp2d) &&
7265 I915_READ(DPIO_CTL) & DPIO_CMNRST)
7266 return;
7267
7268 DRM_DEBUG_KMS("toggling display PHY side reset\n");
7269
7270 /* cmnlane needs DPLL registers */
7271 disp2d->ops->enable(dev_priv, disp2d);
7272
7273 /*
7274 * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
7275 * Need to assert and de-assert PHY SB reset by gating the
7276 * common lane power, then un-gating it.
7277 * Simply ungating isn't enough to reset the PHY enough to get
7278 * ports and lanes running.
7279 */
7280 cmn->ops->disable(dev_priv, cmn);
7281 }
7282
7283 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv)
7284 {
7285 struct drm_device *dev = dev_priv->dev;
7286 struct i915_power_domains *power_domains = &dev_priv->power_domains;
7287
7288 power_domains->initializing = true;
7289
7290 if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
7291 mutex_lock(&power_domains->lock);
7292 vlv_cmnlane_wa(dev_priv);
7293 mutex_unlock(&power_domains->lock);
7294 }
7295
7296 /* For now, we need the power well to be always enabled. */
7297 intel_display_set_init_power(dev_priv, true);
7298 intel_power_domains_resume(dev_priv);
7299 power_domains->initializing = false;
7300 }
7301
7302 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)
7303 {
7304 intel_runtime_pm_get(dev_priv);
7305 }
7306
7307 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)
7308 {
7309 intel_runtime_pm_put(dev_priv);
7310 }
7311
7312 void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
7313 {
7314 struct drm_device *dev = dev_priv->dev;
7315 struct device *device = &dev->pdev->dev;
7316
7317 if (!HAS_RUNTIME_PM(dev))
7318 return;
7319
7320 pm_runtime_get_sync(device);
7321 WARN(dev_priv->pm.suspended, "Device still suspended.\n");
7322 }
7323
7324 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv)
7325 {
7326 struct drm_device *dev = dev_priv->dev;
7327 struct device *device = &dev->pdev->dev;
7328
7329 if (!HAS_RUNTIME_PM(dev))
7330 return;
7331
7332 WARN(dev_priv->pm.suspended, "Getting nosync-ref while suspended.\n");
7333 pm_runtime_get_noresume(device);
7334 }
7335
7336 void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
7337 {
7338 struct drm_device *dev = dev_priv->dev;
7339 struct device *device = &dev->pdev->dev;
7340
7341 if (!HAS_RUNTIME_PM(dev))
7342 return;
7343
7344 pm_runtime_mark_last_busy(device);
7345 pm_runtime_put_autosuspend(device);
7346 }
7347
7348 void intel_init_runtime_pm(struct drm_i915_private *dev_priv)
7349 {
7350 struct drm_device *dev = dev_priv->dev;
7351 struct device *device = &dev->pdev->dev;
7352
7353 if (!HAS_RUNTIME_PM(dev))
7354 return;
7355
7356 pm_runtime_set_active(device);
7357
7358 /*
7359 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
7360 * requirement.
7361 */
7362 if (!intel_enable_rc6(dev)) {
7363 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
7364 return;
7365 }
7366
7367 pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
7368 pm_runtime_mark_last_busy(device);
7369 pm_runtime_use_autosuspend(device);
7370
7371 pm_runtime_put_autosuspend(device);
7372 }
7373
7374 void intel_fini_runtime_pm(struct drm_i915_private *dev_priv)
7375 {
7376 struct drm_device *dev = dev_priv->dev;
7377 struct device *device = &dev->pdev->dev;
7378
7379 if (!HAS_RUNTIME_PM(dev))
7380 return;
7381
7382 if (!intel_enable_rc6(dev))
7383 return;
7384
7385 /* Make sure we're not suspended first. */
7386 pm_runtime_get_sync(device);
7387 pm_runtime_disable(device);
7388 }
7389
7390 static void intel_init_fbc(struct drm_i915_private *dev_priv)
7391 {
7392 if (!HAS_FBC(dev_priv)) {
7393 dev_priv->fbc.enabled = false;
7394 return;
7395 }
7396
7397 if (INTEL_INFO(dev_priv)->gen >= 7) {
7398 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
7399 dev_priv->display.enable_fbc = gen7_enable_fbc;
7400 dev_priv->display.disable_fbc = ironlake_disable_fbc;
7401 } else if (INTEL_INFO(dev_priv)->gen >= 5) {
7402 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
7403 dev_priv->display.enable_fbc = ironlake_enable_fbc;
7404 dev_priv->display.disable_fbc = ironlake_disable_fbc;
7405 } else if (IS_GM45(dev_priv)) {
7406 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
7407 dev_priv->display.enable_fbc = g4x_enable_fbc;
7408 dev_priv->display.disable_fbc = g4x_disable_fbc;
7409 } else {
7410 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
7411 dev_priv->display.enable_fbc = i8xx_enable_fbc;
7412 dev_priv->display.disable_fbc = i8xx_disable_fbc;
7413
7414 /* This value was pulled out of someone's hat */
7415 I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);
7416 }
7417
7418 dev_priv->fbc.enabled = dev_priv->display.fbc_enabled(dev_priv->dev);
7419 }
7420
7421 /* Set up chip specific power management-related functions */
7422 void intel_init_pm(struct drm_device *dev)
7423 {
7424 struct drm_i915_private *dev_priv = dev->dev_private;
7425
7426 intel_init_fbc(dev_priv);
7427
7428 /* For cxsr */
7429 if (IS_PINEVIEW(dev))
7430 i915_pineview_get_mem_freq(dev);
7431 else if (IS_GEN5(dev))
7432 i915_ironlake_get_mem_freq(dev);
7433
7434 /* For FIFO watermark updates */
7435 if (IS_GEN9(dev)) {
7436 dev_priv->display.init_clock_gating = gen9_init_clock_gating;
7437 } else if (HAS_PCH_SPLIT(dev)) {
7438 ilk_setup_wm_latency(dev);
7439
7440 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
7441 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7442 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7443 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
7444 dev_priv->display.update_wm = ilk_update_wm;
7445 dev_priv->display.update_sprite_wm = ilk_update_sprite_wm;
7446 } else {
7447 DRM_DEBUG_KMS("Failed to read display plane latency. "
7448 "Disable CxSR\n");
7449 }
7450
7451 if (IS_GEN5(dev))
7452 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7453 else if (IS_GEN6(dev))
7454 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7455 else if (IS_IVYBRIDGE(dev))
7456 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7457 else if (IS_HASWELL(dev))
7458 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7459 else if (INTEL_INFO(dev)->gen == 8)
7460 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7461 } else if (IS_CHERRYVIEW(dev)) {
7462 dev_priv->display.update_wm = cherryview_update_wm;
7463 dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;
7464 dev_priv->display.init_clock_gating =
7465 cherryview_init_clock_gating;
7466 } else if (IS_VALLEYVIEW(dev)) {
7467 dev_priv->display.update_wm = valleyview_update_wm;
7468 dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;
7469 dev_priv->display.init_clock_gating =
7470 valleyview_init_clock_gating;
7471 } else if (IS_PINEVIEW(dev)) {
7472 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7473 dev_priv->is_ddr3,
7474 dev_priv->fsb_freq,
7475 dev_priv->mem_freq)) {
7476 DRM_INFO("failed to find known CxSR latency "
7477 "(found ddr%s fsb freq %d, mem freq %d), "
7478 "disabling CxSR\n",
7479 (dev_priv->is_ddr3 == 1) ? "3" : "2",
7480 dev_priv->fsb_freq, dev_priv->mem_freq);
7481 /* Disable CxSR and never update its watermark again */
7482 intel_set_memory_cxsr(dev_priv, false);
7483 dev_priv->display.update_wm = NULL;
7484 } else
7485 dev_priv->display.update_wm = pineview_update_wm;
7486 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7487 } else if (IS_G4X(dev)) {
7488 dev_priv->display.update_wm = g4x_update_wm;
7489 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7490 } else if (IS_GEN4(dev)) {
7491 dev_priv->display.update_wm = i965_update_wm;
7492 if (IS_CRESTLINE(dev))
7493 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7494 else if (IS_BROADWATER(dev))
7495 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7496 } else if (IS_GEN3(dev)) {
7497 dev_priv->display.update_wm = i9xx_update_wm;
7498 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7499 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7500 } else if (IS_GEN2(dev)) {
7501 if (INTEL_INFO(dev)->num_pipes == 1) {
7502 dev_priv->display.update_wm = i845_update_wm;
7503 dev_priv->display.get_fifo_size = i845_get_fifo_size;
7504 } else {
7505 dev_priv->display.update_wm = i9xx_update_wm;
7506 dev_priv->display.get_fifo_size = i830_get_fifo_size;
7507 }
7508
7509 if (IS_I85X(dev) || IS_I865G(dev))
7510 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7511 else
7512 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7513 } else {
7514 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
7515 }
7516 }
7517
7518 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
7519 {
7520 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7521
7522 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7523 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7524 return -EAGAIN;
7525 }
7526
7527 I915_WRITE(GEN6_PCODE_DATA, *val);
7528 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7529
7530 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7531 500)) {
7532 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7533 return -ETIMEDOUT;
7534 }
7535
7536 *val = I915_READ(GEN6_PCODE_DATA);
7537 I915_WRITE(GEN6_PCODE_DATA, 0);
7538
7539 return 0;
7540 }
7541
7542 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
7543 {
7544 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7545
7546 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7547 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7548 return -EAGAIN;
7549 }
7550
7551 I915_WRITE(GEN6_PCODE_DATA, val);
7552 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7553
7554 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7555 500)) {
7556 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7557 return -ETIMEDOUT;
7558 }
7559
7560 I915_WRITE(GEN6_PCODE_DATA, 0);
7561
7562 return 0;
7563 }
7564
7565 static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7566 {
7567 int div;
7568
7569 /* 4 x czclk */
7570 switch (dev_priv->mem_freq) {
7571 case 800:
7572 div = 10;
7573 break;
7574 case 1066:
7575 div = 12;
7576 break;
7577 case 1333:
7578 div = 16;
7579 break;
7580 default:
7581 return -1;
7582 }
7583
7584 return DIV_ROUND_CLOSEST(dev_priv->mem_freq * (val + 6 - 0xbd), 4 * div);
7585 }
7586
7587 static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
7588 {
7589 int mul;
7590
7591 /* 4 x czclk */
7592 switch (dev_priv->mem_freq) {
7593 case 800:
7594 mul = 10;
7595 break;
7596 case 1066:
7597 mul = 12;
7598 break;
7599 case 1333:
7600 mul = 16;
7601 break;
7602 default:
7603 return -1;
7604 }
7605
7606 return DIV_ROUND_CLOSEST(4 * mul * val, dev_priv->mem_freq) + 0xbd - 6;
7607 }
7608
7609 static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
7610 {
7611 int div, freq;
7612
7613 switch (dev_priv->rps.cz_freq) {
7614 case 200:
7615 div = 5;
7616 break;
7617 case 267:
7618 div = 6;
7619 break;
7620 case 320:
7621 case 333:
7622 case 400:
7623 div = 8;
7624 break;
7625 default:
7626 return -1;
7627 }
7628
7629 freq = (DIV_ROUND_CLOSEST((dev_priv->rps.cz_freq * val), 2 * div) / 2);
7630
7631 return freq;
7632 }
7633
7634 static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
7635 {
7636 int mul, opcode;
7637
7638 switch (dev_priv->rps.cz_freq) {
7639 case 200:
7640 mul = 5;
7641 break;
7642 case 267:
7643 mul = 6;
7644 break;
7645 case 320:
7646 case 333:
7647 case 400:
7648 mul = 8;
7649 break;
7650 default:
7651 return -1;
7652 }
7653
7654 /* CHV needs even values */
7655 opcode = (DIV_ROUND_CLOSEST((val * 2 * mul), dev_priv->rps.cz_freq) * 2);
7656
7657 return opcode;
7658 }
7659
7660 int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val)
7661 {
7662 int ret = -1;
7663
7664 if (IS_CHERRYVIEW(dev_priv->dev))
7665 ret = chv_gpu_freq(dev_priv, val);
7666 else if (IS_VALLEYVIEW(dev_priv->dev))
7667 ret = byt_gpu_freq(dev_priv, val);
7668
7669 return ret;
7670 }
7671
7672 int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val)
7673 {
7674 int ret = -1;
7675
7676 if (IS_CHERRYVIEW(dev_priv->dev))
7677 ret = chv_freq_opcode(dev_priv, val);
7678 else if (IS_VALLEYVIEW(dev_priv->dev))
7679 ret = byt_freq_opcode(dev_priv, val);
7680
7681 return ret;
7682 }
7683
7684 void intel_pm_setup(struct drm_device *dev)
7685 {
7686 struct drm_i915_private *dev_priv = dev->dev_private;
7687
7688 mutex_init(&dev_priv->rps.hw_lock);
7689
7690 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
7691 intel_gen6_powersave_work);
7692
7693 dev_priv->pm.suspended = false;
7694 dev_priv->pm._irqs_disabled = false;
7695 }
Linux kernel - Deliverables
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