projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge remote-tracking branch 'airlied/drm-next' into drm-intel-next-queued
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_pm.c
1 /*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28 #include <linux/cpufreq.h>
29 #include <drm/drm_plane_helper.h>
30 #include "i915_drv.h"
31 #include "intel_drv.h"
32 #include "../../../platform/x86/intel_ips.h"
33 #include <linux/module.h>
34
35 /**
36 * DOC: RC6
37 *
38 * RC6 is a special power stage which allows the GPU to enter an very
39 * low-voltage mode when idle, using down to 0V while at this stage. This
40 * stage is entered automatically when the GPU is idle when RC6 support is
41 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
42 *
43 * There are different RC6 modes available in Intel GPU, which differentiate
44 * among each other with the latency required to enter and leave RC6 and
45 * voltage consumed by the GPU in different states.
46 *
47 * The combination of the following flags define which states GPU is allowed
48 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
49 * RC6pp is deepest RC6. Their support by hardware varies according to the
50 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
51 * which brings the most power savings; deeper states save more power, but
52 * require higher latency to switch to and wake up.
53 */
54 #define INTEL_RC6_ENABLE (1<<0)
55 #define INTEL_RC6p_ENABLE (1<<1)
56 #define INTEL_RC6pp_ENABLE (1<<2)
57
58 static void bxt_init_clock_gating(struct drm_device *dev)
59 {
60 struct drm_i915_private *dev_priv = dev->dev_private;
61
62 /* See Bspec note for PSR2_CTL bit 31, Wa#828:bxt */
63 I915_WRITE(CHICKEN_PAR1_1,
64 I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
65
66 /* WaDisableSDEUnitClockGating:bxt */
67 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
68 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
69
70 /*
71 * FIXME:
72 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
73 */
74 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
75 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
76
77 /*
78 * Wa: Backlight PWM may stop in the asserted state, causing backlight
79 * to stay fully on.
80 */
81 if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
82 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
83 PWM1_GATING_DIS | PWM2_GATING_DIS);
84 }
85
86 static void i915_pineview_get_mem_freq(struct drm_device *dev)
87 {
88 struct drm_i915_private *dev_priv = dev->dev_private;
89 u32 tmp;
90
91 tmp = I915_READ(CLKCFG);
92
93 switch (tmp & CLKCFG_FSB_MASK) {
94 case CLKCFG_FSB_533:
95 dev_priv->fsb_freq = 533; /* 133*4 */
96 break;
97 case CLKCFG_FSB_800:
98 dev_priv->fsb_freq = 800; /* 200*4 */
99 break;
100 case CLKCFG_FSB_667:
101 dev_priv->fsb_freq = 667; /* 167*4 */
102 break;
103 case CLKCFG_FSB_400:
104 dev_priv->fsb_freq = 400; /* 100*4 */
105 break;
106 }
107
108 switch (tmp & CLKCFG_MEM_MASK) {
109 case CLKCFG_MEM_533:
110 dev_priv->mem_freq = 533;
111 break;
112 case CLKCFG_MEM_667:
113 dev_priv->mem_freq = 667;
114 break;
115 case CLKCFG_MEM_800:
116 dev_priv->mem_freq = 800;
117 break;
118 }
119
120 /* detect pineview DDR3 setting */
121 tmp = I915_READ(CSHRDDR3CTL);
122 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
123 }
124
125 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
126 {
127 struct drm_i915_private *dev_priv = dev->dev_private;
128 u16 ddrpll, csipll;
129
130 ddrpll = I915_READ16(DDRMPLL1);
131 csipll = I915_READ16(CSIPLL0);
132
133 switch (ddrpll & 0xff) {
134 case 0xc:
135 dev_priv->mem_freq = 800;
136 break;
137 case 0x10:
138 dev_priv->mem_freq = 1066;
139 break;
140 case 0x14:
141 dev_priv->mem_freq = 1333;
142 break;
143 case 0x18:
144 dev_priv->mem_freq = 1600;
145 break;
146 default:
147 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
148 ddrpll & 0xff);
149 dev_priv->mem_freq = 0;
150 break;
151 }
152
153 dev_priv->ips.r_t = dev_priv->mem_freq;
154
155 switch (csipll & 0x3ff) {
156 case 0x00c:
157 dev_priv->fsb_freq = 3200;
158 break;
159 case 0x00e:
160 dev_priv->fsb_freq = 3733;
161 break;
162 case 0x010:
163 dev_priv->fsb_freq = 4266;
164 break;
165 case 0x012:
166 dev_priv->fsb_freq = 4800;
167 break;
168 case 0x014:
169 dev_priv->fsb_freq = 5333;
170 break;
171 case 0x016:
172 dev_priv->fsb_freq = 5866;
173 break;
174 case 0x018:
175 dev_priv->fsb_freq = 6400;
176 break;
177 default:
178 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
179 csipll & 0x3ff);
180 dev_priv->fsb_freq = 0;
181 break;
182 }
183
184 if (dev_priv->fsb_freq == 3200) {
185 dev_priv->ips.c_m = 0;
186 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
187 dev_priv->ips.c_m = 1;
188 } else {
189 dev_priv->ips.c_m = 2;
190 }
191 }
192
193 static const struct cxsr_latency cxsr_latency_table[] = {
194 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
195 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
196 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
197 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
198 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
199
200 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
201 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
202 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
203 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
204 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
205
206 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
207 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
208 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
209 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
210 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
211
212 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
213 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
214 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
215 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
216 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
217
218 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
219 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
220 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
221 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
222 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
223
224 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
225 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
226 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
227 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
228 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
229 };
230
231 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
232 int is_ddr3,
233 int fsb,
234 int mem)
235 {
236 const struct cxsr_latency *latency;
237 int i;
238
239 if (fsb == 0 || mem == 0)
240 return NULL;
241
242 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
243 latency = &cxsr_latency_table[i];
244 if (is_desktop == latency->is_desktop &&
245 is_ddr3 == latency->is_ddr3 &&
246 fsb == latency->fsb_freq && mem == latency->mem_freq)
247 return latency;
248 }
249
250 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
251
252 return NULL;
253 }
254
255 static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
256 {
257 u32 val;
258
259 mutex_lock(&dev_priv->rps.hw_lock);
260
261 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
262 if (enable)
263 val &= ~FORCE_DDR_HIGH_FREQ;
264 else
265 val |= FORCE_DDR_HIGH_FREQ;
266 val &= ~FORCE_DDR_LOW_FREQ;
267 val |= FORCE_DDR_FREQ_REQ_ACK;
268 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
269
270 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
271 FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
272 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
273
274 mutex_unlock(&dev_priv->rps.hw_lock);
275 }
276
277 static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
278 {
279 u32 val;
280
281 mutex_lock(&dev_priv->rps.hw_lock);
282
283 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
284 if (enable)
285 val |= DSP_MAXFIFO_PM5_ENABLE;
286 else
287 val &= ~DSP_MAXFIFO_PM5_ENABLE;
288 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
289
290 mutex_unlock(&dev_priv->rps.hw_lock);
291 }
292
293 #define FW_WM(value, plane) \
294 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
295
296 void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
297 {
298 struct drm_device *dev = dev_priv->dev;
299 u32 val;
300
301 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
302 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
303 POSTING_READ(FW_BLC_SELF_VLV);
304 dev_priv->wm.vlv.cxsr = enable;
305 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
306 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
307 POSTING_READ(FW_BLC_SELF);
308 } else if (IS_PINEVIEW(dev)) {
309 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
310 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
311 I915_WRITE(DSPFW3, val);
312 POSTING_READ(DSPFW3);
313 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
314 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
315 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
316 I915_WRITE(FW_BLC_SELF, val);
317 POSTING_READ(FW_BLC_SELF);
318 } else if (IS_I915GM(dev)) {
319 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
320 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
321 I915_WRITE(INSTPM, val);
322 POSTING_READ(INSTPM);
323 } else {
324 return;
325 }
326
327 DRM_DEBUG_KMS("memory self-refresh is %s\n",
328 enable ? "enabled" : "disabled");
329 }
330
331
332 /*
333 * Latency for FIFO fetches is dependent on several factors:
334 * - memory configuration (speed, channels)
335 * - chipset
336 * - current MCH state
337 * It can be fairly high in some situations, so here we assume a fairly
338 * pessimal value. It's a tradeoff between extra memory fetches (if we
339 * set this value too high, the FIFO will fetch frequently to stay full)
340 * and power consumption (set it too low to save power and we might see
341 * FIFO underruns and display "flicker").
342 *
343 * A value of 5us seems to be a good balance; safe for very low end
344 * platforms but not overly aggressive on lower latency configs.
345 */
346 static const int pessimal_latency_ns = 5000;
347
348 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
349 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
350
351 static int vlv_get_fifo_size(struct drm_device *dev,
352 enum pipe pipe, int plane)
353 {
354 struct drm_i915_private *dev_priv = dev->dev_private;
355 int sprite0_start, sprite1_start, size;
356
357 switch (pipe) {
358 uint32_t dsparb, dsparb2, dsparb3;
359 case PIPE_A:
360 dsparb = I915_READ(DSPARB);
361 dsparb2 = I915_READ(DSPARB2);
362 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
363 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
364 break;
365 case PIPE_B:
366 dsparb = I915_READ(DSPARB);
367 dsparb2 = I915_READ(DSPARB2);
368 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
369 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
370 break;
371 case PIPE_C:
372 dsparb2 = I915_READ(DSPARB2);
373 dsparb3 = I915_READ(DSPARB3);
374 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
375 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
376 break;
377 default:
378 return 0;
379 }
380
381 switch (plane) {
382 case 0:
383 size = sprite0_start;
384 break;
385 case 1:
386 size = sprite1_start - sprite0_start;
387 break;
388 case 2:
389 size = 512 - 1 - sprite1_start;
390 break;
391 default:
392 return 0;
393 }
394
395 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
396 pipe_name(pipe), plane == 0 ? "primary" : "sprite",
397 plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
398 size);
399
400 return size;
401 }
402
403 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
404 {
405 struct drm_i915_private *dev_priv = dev->dev_private;
406 uint32_t dsparb = I915_READ(DSPARB);
407 int size;
408
409 size = dsparb & 0x7f;
410 if (plane)
411 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
412
413 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
414 plane ? "B" : "A", size);
415
416 return size;
417 }
418
419 static int i830_get_fifo_size(struct drm_device *dev, int plane)
420 {
421 struct drm_i915_private *dev_priv = dev->dev_private;
422 uint32_t dsparb = I915_READ(DSPARB);
423 int size;
424
425 size = dsparb & 0x1ff;
426 if (plane)
427 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
428 size >>= 1; /* Convert to cachelines */
429
430 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
431 plane ? "B" : "A", size);
432
433 return size;
434 }
435
436 static int i845_get_fifo_size(struct drm_device *dev, int plane)
437 {
438 struct drm_i915_private *dev_priv = dev->dev_private;
439 uint32_t dsparb = I915_READ(DSPARB);
440 int size;
441
442 size = dsparb & 0x7f;
443 size >>= 2; /* Convert to cachelines */
444
445 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
446 plane ? "B" : "A",
447 size);
448
449 return size;
450 }
451
452 /* Pineview has different values for various configs */
453 static const struct intel_watermark_params pineview_display_wm = {
454 .fifo_size = PINEVIEW_DISPLAY_FIFO,
455 .max_wm = PINEVIEW_MAX_WM,
456 .default_wm = PINEVIEW_DFT_WM,
457 .guard_size = PINEVIEW_GUARD_WM,
458 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
459 };
460 static const struct intel_watermark_params pineview_display_hplloff_wm = {
461 .fifo_size = PINEVIEW_DISPLAY_FIFO,
462 .max_wm = PINEVIEW_MAX_WM,
463 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
464 .guard_size = PINEVIEW_GUARD_WM,
465 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
466 };
467 static const struct intel_watermark_params pineview_cursor_wm = {
468 .fifo_size = PINEVIEW_CURSOR_FIFO,
469 .max_wm = PINEVIEW_CURSOR_MAX_WM,
470 .default_wm = PINEVIEW_CURSOR_DFT_WM,
471 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
472 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
473 };
474 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
475 .fifo_size = PINEVIEW_CURSOR_FIFO,
476 .max_wm = PINEVIEW_CURSOR_MAX_WM,
477 .default_wm = PINEVIEW_CURSOR_DFT_WM,
478 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
479 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
480 };
481 static const struct intel_watermark_params g4x_wm_info = {
482 .fifo_size = G4X_FIFO_SIZE,
483 .max_wm = G4X_MAX_WM,
484 .default_wm = G4X_MAX_WM,
485 .guard_size = 2,
486 .cacheline_size = G4X_FIFO_LINE_SIZE,
487 };
488 static const struct intel_watermark_params g4x_cursor_wm_info = {
489 .fifo_size = I965_CURSOR_FIFO,
490 .max_wm = I965_CURSOR_MAX_WM,
491 .default_wm = I965_CURSOR_DFT_WM,
492 .guard_size = 2,
493 .cacheline_size = G4X_FIFO_LINE_SIZE,
494 };
495 static const struct intel_watermark_params i965_cursor_wm_info = {
496 .fifo_size = I965_CURSOR_FIFO,
497 .max_wm = I965_CURSOR_MAX_WM,
498 .default_wm = I965_CURSOR_DFT_WM,
499 .guard_size = 2,
500 .cacheline_size = I915_FIFO_LINE_SIZE,
501 };
502 static const struct intel_watermark_params i945_wm_info = {
503 .fifo_size = I945_FIFO_SIZE,
504 .max_wm = I915_MAX_WM,
505 .default_wm = 1,
506 .guard_size = 2,
507 .cacheline_size = I915_FIFO_LINE_SIZE,
508 };
509 static const struct intel_watermark_params i915_wm_info = {
510 .fifo_size = I915_FIFO_SIZE,
511 .max_wm = I915_MAX_WM,
512 .default_wm = 1,
513 .guard_size = 2,
514 .cacheline_size = I915_FIFO_LINE_SIZE,
515 };
516 static const struct intel_watermark_params i830_a_wm_info = {
517 .fifo_size = I855GM_FIFO_SIZE,
518 .max_wm = I915_MAX_WM,
519 .default_wm = 1,
520 .guard_size = 2,
521 .cacheline_size = I830_FIFO_LINE_SIZE,
522 };
523 static const struct intel_watermark_params i830_bc_wm_info = {
524 .fifo_size = I855GM_FIFO_SIZE,
525 .max_wm = I915_MAX_WM/2,
526 .default_wm = 1,
527 .guard_size = 2,
528 .cacheline_size = I830_FIFO_LINE_SIZE,
529 };
530 static const struct intel_watermark_params i845_wm_info = {
531 .fifo_size = I830_FIFO_SIZE,
532 .max_wm = I915_MAX_WM,
533 .default_wm = 1,
534 .guard_size = 2,
535 .cacheline_size = I830_FIFO_LINE_SIZE,
536 };
537
538 /**
539 * intel_calculate_wm - calculate watermark level
540 * @clock_in_khz: pixel clock
541 * @wm: chip FIFO params
542 * @cpp: bytes per pixel
543 * @latency_ns: memory latency for the platform
544 *
545 * Calculate the watermark level (the level at which the display plane will
546 * start fetching from memory again). Each chip has a different display
547 * FIFO size and allocation, so the caller needs to figure that out and pass
548 * in the correct intel_watermark_params structure.
549 *
550 * As the pixel clock runs, the FIFO will be drained at a rate that depends
551 * on the pixel size. When it reaches the watermark level, it'll start
552 * fetching FIFO line sized based chunks from memory until the FIFO fills
553 * past the watermark point. If the FIFO drains completely, a FIFO underrun
554 * will occur, and a display engine hang could result.
555 */
556 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
557 const struct intel_watermark_params *wm,
558 int fifo_size, int cpp,
559 unsigned long latency_ns)
560 {
561 long entries_required, wm_size;
562
563 /*
564 * Note: we need to make sure we don't overflow for various clock &
565 * latency values.
566 * clocks go from a few thousand to several hundred thousand.
567 * latency is usually a few thousand
568 */
569 entries_required = ((clock_in_khz / 1000) * cpp * latency_ns) /
570 1000;
571 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
572
573 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
574
575 wm_size = fifo_size - (entries_required + wm->guard_size);
576
577 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
578
579 /* Don't promote wm_size to unsigned... */
580 if (wm_size > (long)wm->max_wm)
581 wm_size = wm->max_wm;
582 if (wm_size <= 0)
583 wm_size = wm->default_wm;
584
585 /*
586 * Bspec seems to indicate that the value shouldn't be lower than
587 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
588 * Lets go for 8 which is the burst size since certain platforms
589 * already use a hardcoded 8 (which is what the spec says should be
590 * done).
591 */
592 if (wm_size <= 8)
593 wm_size = 8;
594
595 return wm_size;
596 }
597
598 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
599 {
600 struct drm_crtc *crtc, *enabled = NULL;
601
602 for_each_crtc(dev, crtc) {
603 if (intel_crtc_active(crtc)) {
604 if (enabled)
605 return NULL;
606 enabled = crtc;
607 }
608 }
609
610 return enabled;
611 }
612
613 static void pineview_update_wm(struct drm_crtc *unused_crtc)
614 {
615 struct drm_device *dev = unused_crtc->dev;
616 struct drm_i915_private *dev_priv = dev->dev_private;
617 struct drm_crtc *crtc;
618 const struct cxsr_latency *latency;
619 u32 reg;
620 unsigned long wm;
621
622 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
623 dev_priv->fsb_freq, dev_priv->mem_freq);
624 if (!latency) {
625 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
626 intel_set_memory_cxsr(dev_priv, false);
627 return;
628 }
629
630 crtc = single_enabled_crtc(dev);
631 if (crtc) {
632 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
633 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
634 int clock = adjusted_mode->crtc_clock;
635
636 /* Display SR */
637 wm = intel_calculate_wm(clock, &pineview_display_wm,
638 pineview_display_wm.fifo_size,
639 cpp, latency->display_sr);
640 reg = I915_READ(DSPFW1);
641 reg &= ~DSPFW_SR_MASK;
642 reg |= FW_WM(wm, SR);
643 I915_WRITE(DSPFW1, reg);
644 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
645
646 /* cursor SR */
647 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
648 pineview_display_wm.fifo_size,
649 cpp, latency->cursor_sr);
650 reg = I915_READ(DSPFW3);
651 reg &= ~DSPFW_CURSOR_SR_MASK;
652 reg |= FW_WM(wm, CURSOR_SR);
653 I915_WRITE(DSPFW3, reg);
654
655 /* Display HPLL off SR */
656 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
657 pineview_display_hplloff_wm.fifo_size,
658 cpp, latency->display_hpll_disable);
659 reg = I915_READ(DSPFW3);
660 reg &= ~DSPFW_HPLL_SR_MASK;
661 reg |= FW_WM(wm, HPLL_SR);
662 I915_WRITE(DSPFW3, reg);
663
664 /* cursor HPLL off SR */
665 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
666 pineview_display_hplloff_wm.fifo_size,
667 cpp, latency->cursor_hpll_disable);
668 reg = I915_READ(DSPFW3);
669 reg &= ~DSPFW_HPLL_CURSOR_MASK;
670 reg |= FW_WM(wm, HPLL_CURSOR);
671 I915_WRITE(DSPFW3, reg);
672 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
673
674 intel_set_memory_cxsr(dev_priv, true);
675 } else {
676 intel_set_memory_cxsr(dev_priv, false);
677 }
678 }
679
680 static bool g4x_compute_wm0(struct drm_device *dev,
681 int plane,
682 const struct intel_watermark_params *display,
683 int display_latency_ns,
684 const struct intel_watermark_params *cursor,
685 int cursor_latency_ns,
686 int *plane_wm,
687 int *cursor_wm)
688 {
689 struct drm_crtc *crtc;
690 const struct drm_display_mode *adjusted_mode;
691 int htotal, hdisplay, clock, cpp;
692 int line_time_us, line_count;
693 int entries, tlb_miss;
694
695 crtc = intel_get_crtc_for_plane(dev, plane);
696 if (!intel_crtc_active(crtc)) {
697 *cursor_wm = cursor->guard_size;
698 *plane_wm = display->guard_size;
699 return false;
700 }
701
702 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
703 clock = adjusted_mode->crtc_clock;
704 htotal = adjusted_mode->crtc_htotal;
705 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
706 cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
707
708 /* Use the small buffer method to calculate plane watermark */
709 entries = ((clock * cpp / 1000) * display_latency_ns) / 1000;
710 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
711 if (tlb_miss > 0)
712 entries += tlb_miss;
713 entries = DIV_ROUND_UP(entries, display->cacheline_size);
714 *plane_wm = entries + display->guard_size;
715 if (*plane_wm > (int)display->max_wm)
716 *plane_wm = display->max_wm;
717
718 /* Use the large buffer method to calculate cursor watermark */
719 line_time_us = max(htotal * 1000 / clock, 1);
720 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
721 entries = line_count * crtc->cursor->state->crtc_w * cpp;
722 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
723 if (tlb_miss > 0)
724 entries += tlb_miss;
725 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
726 *cursor_wm = entries + cursor->guard_size;
727 if (*cursor_wm > (int)cursor->max_wm)
728 *cursor_wm = (int)cursor->max_wm;
729
730 return true;
731 }
732
733 /*
734 * Check the wm result.
735 *
736 * If any calculated watermark values is larger than the maximum value that
737 * can be programmed into the associated watermark register, that watermark
738 * must be disabled.
739 */
740 static bool g4x_check_srwm(struct drm_device *dev,
741 int display_wm, int cursor_wm,
742 const struct intel_watermark_params *display,
743 const struct intel_watermark_params *cursor)
744 {
745 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
746 display_wm, cursor_wm);
747
748 if (display_wm > display->max_wm) {
749 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
750 display_wm, display->max_wm);
751 return false;
752 }
753
754 if (cursor_wm > cursor->max_wm) {
755 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
756 cursor_wm, cursor->max_wm);
757 return false;
758 }
759
760 if (!(display_wm || cursor_wm)) {
761 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
762 return false;
763 }
764
765 return true;
766 }
767
768 static bool g4x_compute_srwm(struct drm_device *dev,
769 int plane,
770 int latency_ns,
771 const struct intel_watermark_params *display,
772 const struct intel_watermark_params *cursor,
773 int *display_wm, int *cursor_wm)
774 {
775 struct drm_crtc *crtc;
776 const struct drm_display_mode *adjusted_mode;
777 int hdisplay, htotal, cpp, clock;
778 unsigned long line_time_us;
779 int line_count, line_size;
780 int small, large;
781 int entries;
782
783 if (!latency_ns) {
784 *display_wm = *cursor_wm = 0;
785 return false;
786 }
787
788 crtc = intel_get_crtc_for_plane(dev, plane);
789 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
790 clock = adjusted_mode->crtc_clock;
791 htotal = adjusted_mode->crtc_htotal;
792 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
793 cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
794
795 line_time_us = max(htotal * 1000 / clock, 1);
796 line_count = (latency_ns / line_time_us + 1000) / 1000;
797 line_size = hdisplay * cpp;
798
799 /* Use the minimum of the small and large buffer method for primary */
800 small = ((clock * cpp / 1000) * latency_ns) / 1000;
801 large = line_count * line_size;
802
803 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
804 *display_wm = entries + display->guard_size;
805
806 /* calculate the self-refresh watermark for display cursor */
807 entries = line_count * cpp * crtc->cursor->state->crtc_w;
808 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
809 *cursor_wm = entries + cursor->guard_size;
810
811 return g4x_check_srwm(dev,
812 *display_wm, *cursor_wm,
813 display, cursor);
814 }
815
816 #define FW_WM_VLV(value, plane) \
817 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
818
819 static void vlv_write_wm_values(struct intel_crtc *crtc,
820 const struct vlv_wm_values *wm)
821 {
822 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
823 enum pipe pipe = crtc->pipe;
824
825 I915_WRITE(VLV_DDL(pipe),
826 (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
827 (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
828 (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
829 (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
830
831 I915_WRITE(DSPFW1,
832 FW_WM(wm->sr.plane, SR) |
833 FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
834 FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
835 FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
836 I915_WRITE(DSPFW2,
837 FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
838 FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
839 FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
840 I915_WRITE(DSPFW3,
841 FW_WM(wm->sr.cursor, CURSOR_SR));
842
843 if (IS_CHERRYVIEW(dev_priv)) {
844 I915_WRITE(DSPFW7_CHV,
845 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
846 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
847 I915_WRITE(DSPFW8_CHV,
848 FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
849 FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
850 I915_WRITE(DSPFW9_CHV,
851 FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
852 FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
853 I915_WRITE(DSPHOWM,
854 FW_WM(wm->sr.plane >> 9, SR_HI) |
855 FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
856 FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
857 FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
858 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
859 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
860 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
861 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
862 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
863 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
864 } else {
865 I915_WRITE(DSPFW7,
866 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
867 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
868 I915_WRITE(DSPHOWM,
869 FW_WM(wm->sr.plane >> 9, SR_HI) |
870 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
871 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
872 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
873 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
874 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
875 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
876 }
877
878 /* zero (unused) WM1 watermarks */
879 I915_WRITE(DSPFW4, 0);
880 I915_WRITE(DSPFW5, 0);
881 I915_WRITE(DSPFW6, 0);
882 I915_WRITE(DSPHOWM1, 0);
883
884 POSTING_READ(DSPFW1);
885 }
886
887 #undef FW_WM_VLV
888
889 enum vlv_wm_level {
890 VLV_WM_LEVEL_PM2,
891 VLV_WM_LEVEL_PM5,
892 VLV_WM_LEVEL_DDR_DVFS,
893 };
894
895 /* latency must be in 0.1us units. */
896 static unsigned int vlv_wm_method2(unsigned int pixel_rate,
897 unsigned int pipe_htotal,
898 unsigned int horiz_pixels,
899 unsigned int cpp,
900 unsigned int latency)
901 {
902 unsigned int ret;
903
904 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
905 ret = (ret + 1) * horiz_pixels * cpp;
906 ret = DIV_ROUND_UP(ret, 64);
907
908 return ret;
909 }
910
911 static void vlv_setup_wm_latency(struct drm_device *dev)
912 {
913 struct drm_i915_private *dev_priv = dev->dev_private;
914
915 /* all latencies in usec */
916 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
917
918 dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
919
920 if (IS_CHERRYVIEW(dev_priv)) {
921 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
922 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
923
924 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
925 }
926 }
927
928 static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
929 struct intel_crtc *crtc,
930 const struct intel_plane_state *state,
931 int level)
932 {
933 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
934 int clock, htotal, cpp, width, wm;
935
936 if (dev_priv->wm.pri_latency[level] == 0)
937 return USHRT_MAX;
938
939 if (!state->visible)
940 return 0;
941
942 cpp = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
943 clock = crtc->config->base.adjusted_mode.crtc_clock;
944 htotal = crtc->config->base.adjusted_mode.crtc_htotal;
945 width = crtc->config->pipe_src_w;
946 if (WARN_ON(htotal == 0))
947 htotal = 1;
948
949 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
950 /*
951 * FIXME the formula gives values that are
952 * too big for the cursor FIFO, and hence we
953 * would never be able to use cursors. For
954 * now just hardcode the watermark.
955 */
956 wm = 63;
957 } else {
958 wm = vlv_wm_method2(clock, htotal, width, cpp,
959 dev_priv->wm.pri_latency[level] * 10);
960 }
961
962 return min_t(int, wm, USHRT_MAX);
963 }
964
965 static void vlv_compute_fifo(struct intel_crtc *crtc)
966 {
967 struct drm_device *dev = crtc->base.dev;
968 struct vlv_wm_state *wm_state = &crtc->wm_state;
969 struct intel_plane *plane;
970 unsigned int total_rate = 0;
971 const int fifo_size = 512 - 1;
972 int fifo_extra, fifo_left = fifo_size;
973
974 for_each_intel_plane_on_crtc(dev, crtc, plane) {
975 struct intel_plane_state *state =
976 to_intel_plane_state(plane->base.state);
977
978 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
979 continue;
980
981 if (state->visible) {
982 wm_state->num_active_planes++;
983 total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
984 }
985 }
986
987 for_each_intel_plane_on_crtc(dev, crtc, plane) {
988 struct intel_plane_state *state =
989 to_intel_plane_state(plane->base.state);
990 unsigned int rate;
991
992 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
993 plane->wm.fifo_size = 63;
994 continue;
995 }
996
997 if (!state->visible) {
998 plane->wm.fifo_size = 0;
999 continue;
1000 }
1001
1002 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1003 plane->wm.fifo_size = fifo_size * rate / total_rate;
1004 fifo_left -= plane->wm.fifo_size;
1005 }
1006
1007 fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1008
1009 /* spread the remainder evenly */
1010 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1011 int plane_extra;
1012
1013 if (fifo_left == 0)
1014 break;
1015
1016 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1017 continue;
1018
1019 /* give it all to the first plane if none are active */
1020 if (plane->wm.fifo_size == 0 &&
1021 wm_state->num_active_planes)
1022 continue;
1023
1024 plane_extra = min(fifo_extra, fifo_left);
1025 plane->wm.fifo_size += plane_extra;
1026 fifo_left -= plane_extra;
1027 }
1028
1029 WARN_ON(fifo_left != 0);
1030 }
1031
1032 static void vlv_invert_wms(struct intel_crtc *crtc)
1033 {
1034 struct vlv_wm_state *wm_state = &crtc->wm_state;
1035 int level;
1036
1037 for (level = 0; level < wm_state->num_levels; level++) {
1038 struct drm_device *dev = crtc->base.dev;
1039 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1040 struct intel_plane *plane;
1041
1042 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1043 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1044
1045 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1046 switch (plane->base.type) {
1047 int sprite;
1048 case DRM_PLANE_TYPE_CURSOR:
1049 wm_state->wm[level].cursor = plane->wm.fifo_size -
1050 wm_state->wm[level].cursor;
1051 break;
1052 case DRM_PLANE_TYPE_PRIMARY:
1053 wm_state->wm[level].primary = plane->wm.fifo_size -
1054 wm_state->wm[level].primary;
1055 break;
1056 case DRM_PLANE_TYPE_OVERLAY:
1057 sprite = plane->plane;
1058 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1059 wm_state->wm[level].sprite[sprite];
1060 break;
1061 }
1062 }
1063 }
1064 }
1065
1066 static void vlv_compute_wm(struct intel_crtc *crtc)
1067 {
1068 struct drm_device *dev = crtc->base.dev;
1069 struct vlv_wm_state *wm_state = &crtc->wm_state;
1070 struct intel_plane *plane;
1071 int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1072 int level;
1073
1074 memset(wm_state, 0, sizeof(*wm_state));
1075
1076 wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
1077 wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
1078
1079 wm_state->num_active_planes = 0;
1080
1081 vlv_compute_fifo(crtc);
1082
1083 if (wm_state->num_active_planes != 1)
1084 wm_state->cxsr = false;
1085
1086 if (wm_state->cxsr) {
1087 for (level = 0; level < wm_state->num_levels; level++) {
1088 wm_state->sr[level].plane = sr_fifo_size;
1089 wm_state->sr[level].cursor = 63;
1090 }
1091 }
1092
1093 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1094 struct intel_plane_state *state =
1095 to_intel_plane_state(plane->base.state);
1096
1097 if (!state->visible)
1098 continue;
1099
1100 /* normal watermarks */
1101 for (level = 0; level < wm_state->num_levels; level++) {
1102 int wm = vlv_compute_wm_level(plane, crtc, state, level);
1103 int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1104
1105 /* hack */
1106 if (WARN_ON(level == 0 && wm > max_wm))
1107 wm = max_wm;
1108
1109 if (wm > plane->wm.fifo_size)
1110 break;
1111
1112 switch (plane->base.type) {
1113 int sprite;
1114 case DRM_PLANE_TYPE_CURSOR:
1115 wm_state->wm[level].cursor = wm;
1116 break;
1117 case DRM_PLANE_TYPE_PRIMARY:
1118 wm_state->wm[level].primary = wm;
1119 break;
1120 case DRM_PLANE_TYPE_OVERLAY:
1121 sprite = plane->plane;
1122 wm_state->wm[level].sprite[sprite] = wm;
1123 break;
1124 }
1125 }
1126
1127 wm_state->num_levels = level;
1128
1129 if (!wm_state->cxsr)
1130 continue;
1131
1132 /* maxfifo watermarks */
1133 switch (plane->base.type) {
1134 int sprite, level;
1135 case DRM_PLANE_TYPE_CURSOR:
1136 for (level = 0; level < wm_state->num_levels; level++)
1137 wm_state->sr[level].cursor =
1138 wm_state->wm[level].cursor;
1139 break;
1140 case DRM_PLANE_TYPE_PRIMARY:
1141 for (level = 0; level < wm_state->num_levels; level++)
1142 wm_state->sr[level].plane =
1143 min(wm_state->sr[level].plane,
1144 wm_state->wm[level].primary);
1145 break;
1146 case DRM_PLANE_TYPE_OVERLAY:
1147 sprite = plane->plane;
1148 for (level = 0; level < wm_state->num_levels; level++)
1149 wm_state->sr[level].plane =
1150 min(wm_state->sr[level].plane,
1151 wm_state->wm[level].sprite[sprite]);
1152 break;
1153 }
1154 }
1155
1156 /* clear any (partially) filled invalid levels */
1157 for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
1158 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1159 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1160 }
1161
1162 vlv_invert_wms(crtc);
1163 }
1164
1165 #define VLV_FIFO(plane, value) \
1166 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1167
1168 static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1169 {
1170 struct drm_device *dev = crtc->base.dev;
1171 struct drm_i915_private *dev_priv = to_i915(dev);
1172 struct intel_plane *plane;
1173 int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1174
1175 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1176 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1177 WARN_ON(plane->wm.fifo_size != 63);
1178 continue;
1179 }
1180
1181 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1182 sprite0_start = plane->wm.fifo_size;
1183 else if (plane->plane == 0)
1184 sprite1_start = sprite0_start + plane->wm.fifo_size;
1185 else
1186 fifo_size = sprite1_start + plane->wm.fifo_size;
1187 }
1188
1189 WARN_ON(fifo_size != 512 - 1);
1190
1191 DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1192 pipe_name(crtc->pipe), sprite0_start,
1193 sprite1_start, fifo_size);
1194
1195 switch (crtc->pipe) {
1196 uint32_t dsparb, dsparb2, dsparb3;
1197 case PIPE_A:
1198 dsparb = I915_READ(DSPARB);
1199 dsparb2 = I915_READ(DSPARB2);
1200
1201 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1202 VLV_FIFO(SPRITEB, 0xff));
1203 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1204 VLV_FIFO(SPRITEB, sprite1_start));
1205
1206 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1207 VLV_FIFO(SPRITEB_HI, 0x1));
1208 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1209 VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1210
1211 I915_WRITE(DSPARB, dsparb);
1212 I915_WRITE(DSPARB2, dsparb2);
1213 break;
1214 case PIPE_B:
1215 dsparb = I915_READ(DSPARB);
1216 dsparb2 = I915_READ(DSPARB2);
1217
1218 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1219 VLV_FIFO(SPRITED, 0xff));
1220 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1221 VLV_FIFO(SPRITED, sprite1_start));
1222
1223 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1224 VLV_FIFO(SPRITED_HI, 0xff));
1225 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1226 VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1227
1228 I915_WRITE(DSPARB, dsparb);
1229 I915_WRITE(DSPARB2, dsparb2);
1230 break;
1231 case PIPE_C:
1232 dsparb3 = I915_READ(DSPARB3);
1233 dsparb2 = I915_READ(DSPARB2);
1234
1235 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1236 VLV_FIFO(SPRITEF, 0xff));
1237 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1238 VLV_FIFO(SPRITEF, sprite1_start));
1239
1240 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1241 VLV_FIFO(SPRITEF_HI, 0xff));
1242 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1243 VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1244
1245 I915_WRITE(DSPARB3, dsparb3);
1246 I915_WRITE(DSPARB2, dsparb2);
1247 break;
1248 default:
1249 break;
1250 }
1251 }
1252
1253 #undef VLV_FIFO
1254
1255 static void vlv_merge_wm(struct drm_device *dev,
1256 struct vlv_wm_values *wm)
1257 {
1258 struct intel_crtc *crtc;
1259 int num_active_crtcs = 0;
1260
1261 wm->level = to_i915(dev)->wm.max_level;
1262 wm->cxsr = true;
1263
1264 for_each_intel_crtc(dev, crtc) {
1265 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1266
1267 if (!crtc->active)
1268 continue;
1269
1270 if (!wm_state->cxsr)
1271 wm->cxsr = false;
1272
1273 num_active_crtcs++;
1274 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1275 }
1276
1277 if (num_active_crtcs != 1)
1278 wm->cxsr = false;
1279
1280 if (num_active_crtcs > 1)
1281 wm->level = VLV_WM_LEVEL_PM2;
1282
1283 for_each_intel_crtc(dev, crtc) {
1284 struct vlv_wm_state *wm_state = &crtc->wm_state;
1285 enum pipe pipe = crtc->pipe;
1286
1287 if (!crtc->active)
1288 continue;
1289
1290 wm->pipe[pipe] = wm_state->wm[wm->level];
1291 if (wm->cxsr)
1292 wm->sr = wm_state->sr[wm->level];
1293
1294 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1295 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1296 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1297 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1298 }
1299 }
1300
1301 static void vlv_update_wm(struct drm_crtc *crtc)
1302 {
1303 struct drm_device *dev = crtc->dev;
1304 struct drm_i915_private *dev_priv = dev->dev_private;
1305 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1306 enum pipe pipe = intel_crtc->pipe;
1307 struct vlv_wm_values wm = {};
1308
1309 vlv_compute_wm(intel_crtc);
1310 vlv_merge_wm(dev, &wm);
1311
1312 if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1313 /* FIXME should be part of crtc atomic commit */
1314 vlv_pipe_set_fifo_size(intel_crtc);
1315 return;
1316 }
1317
1318 if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1319 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1320 chv_set_memory_dvfs(dev_priv, false);
1321
1322 if (wm.level < VLV_WM_LEVEL_PM5 &&
1323 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1324 chv_set_memory_pm5(dev_priv, false);
1325
1326 if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
1327 intel_set_memory_cxsr(dev_priv, false);
1328
1329 /* FIXME should be part of crtc atomic commit */
1330 vlv_pipe_set_fifo_size(intel_crtc);
1331
1332 vlv_write_wm_values(intel_crtc, &wm);
1333
1334 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1335 "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1336 pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1337 wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1338 wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1339
1340 if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
1341 intel_set_memory_cxsr(dev_priv, true);
1342
1343 if (wm.level >= VLV_WM_LEVEL_PM5 &&
1344 dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1345 chv_set_memory_pm5(dev_priv, true);
1346
1347 if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1348 dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1349 chv_set_memory_dvfs(dev_priv, true);
1350
1351 dev_priv->wm.vlv = wm;
1352 }
1353
1354 #define single_plane_enabled(mask) is_power_of_2(mask)
1355
1356 static void g4x_update_wm(struct drm_crtc *crtc)
1357 {
1358 struct drm_device *dev = crtc->dev;
1359 static const int sr_latency_ns = 12000;
1360 struct drm_i915_private *dev_priv = dev->dev_private;
1361 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1362 int plane_sr, cursor_sr;
1363 unsigned int enabled = 0;
1364 bool cxsr_enabled;
1365
1366 if (g4x_compute_wm0(dev, PIPE_A,
1367 &g4x_wm_info, pessimal_latency_ns,
1368 &g4x_cursor_wm_info, pessimal_latency_ns,
1369 &planea_wm, &cursora_wm))
1370 enabled |= 1 << PIPE_A;
1371
1372 if (g4x_compute_wm0(dev, PIPE_B,
1373 &g4x_wm_info, pessimal_latency_ns,
1374 &g4x_cursor_wm_info, pessimal_latency_ns,
1375 &planeb_wm, &cursorb_wm))
1376 enabled |= 1 << PIPE_B;
1377
1378 if (single_plane_enabled(enabled) &&
1379 g4x_compute_srwm(dev, ffs(enabled) - 1,
1380 sr_latency_ns,
1381 &g4x_wm_info,
1382 &g4x_cursor_wm_info,
1383 &plane_sr, &cursor_sr)) {
1384 cxsr_enabled = true;
1385 } else {
1386 cxsr_enabled = false;
1387 intel_set_memory_cxsr(dev_priv, false);
1388 plane_sr = cursor_sr = 0;
1389 }
1390
1391 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1392 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1393 planea_wm, cursora_wm,
1394 planeb_wm, cursorb_wm,
1395 plane_sr, cursor_sr);
1396
1397 I915_WRITE(DSPFW1,
1398 FW_WM(plane_sr, SR) |
1399 FW_WM(cursorb_wm, CURSORB) |
1400 FW_WM(planeb_wm, PLANEB) |
1401 FW_WM(planea_wm, PLANEA));
1402 I915_WRITE(DSPFW2,
1403 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1404 FW_WM(cursora_wm, CURSORA));
1405 /* HPLL off in SR has some issues on G4x... disable it */
1406 I915_WRITE(DSPFW3,
1407 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1408 FW_WM(cursor_sr, CURSOR_SR));
1409
1410 if (cxsr_enabled)
1411 intel_set_memory_cxsr(dev_priv, true);
1412 }
1413
1414 static void i965_update_wm(struct drm_crtc *unused_crtc)
1415 {
1416 struct drm_device *dev = unused_crtc->dev;
1417 struct drm_i915_private *dev_priv = dev->dev_private;
1418 struct drm_crtc *crtc;
1419 int srwm = 1;
1420 int cursor_sr = 16;
1421 bool cxsr_enabled;
1422
1423 /* Calc sr entries for one plane configs */
1424 crtc = single_enabled_crtc(dev);
1425 if (crtc) {
1426 /* self-refresh has much higher latency */
1427 static const int sr_latency_ns = 12000;
1428 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1429 int clock = adjusted_mode->crtc_clock;
1430 int htotal = adjusted_mode->crtc_htotal;
1431 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
1432 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
1433 unsigned long line_time_us;
1434 int entries;
1435
1436 line_time_us = max(htotal * 1000 / clock, 1);
1437
1438 /* Use ns/us then divide to preserve precision */
1439 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1440 cpp * hdisplay;
1441 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1442 srwm = I965_FIFO_SIZE - entries;
1443 if (srwm < 0)
1444 srwm = 1;
1445 srwm &= 0x1ff;
1446 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1447 entries, srwm);
1448
1449 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1450 cpp * crtc->cursor->state->crtc_w;
1451 entries = DIV_ROUND_UP(entries,
1452 i965_cursor_wm_info.cacheline_size);
1453 cursor_sr = i965_cursor_wm_info.fifo_size -
1454 (entries + i965_cursor_wm_info.guard_size);
1455
1456 if (cursor_sr > i965_cursor_wm_info.max_wm)
1457 cursor_sr = i965_cursor_wm_info.max_wm;
1458
1459 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1460 "cursor %d\n", srwm, cursor_sr);
1461
1462 cxsr_enabled = true;
1463 } else {
1464 cxsr_enabled = false;
1465 /* Turn off self refresh if both pipes are enabled */
1466 intel_set_memory_cxsr(dev_priv, false);
1467 }
1468
1469 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1470 srwm);
1471
1472 /* 965 has limitations... */
1473 I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1474 FW_WM(8, CURSORB) |
1475 FW_WM(8, PLANEB) |
1476 FW_WM(8, PLANEA));
1477 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1478 FW_WM(8, PLANEC_OLD));
1479 /* update cursor SR watermark */
1480 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
1481
1482 if (cxsr_enabled)
1483 intel_set_memory_cxsr(dev_priv, true);
1484 }
1485
1486 #undef FW_WM
1487
1488 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1489 {
1490 struct drm_device *dev = unused_crtc->dev;
1491 struct drm_i915_private *dev_priv = dev->dev_private;
1492 const struct intel_watermark_params *wm_info;
1493 uint32_t fwater_lo;
1494 uint32_t fwater_hi;
1495 int cwm, srwm = 1;
1496 int fifo_size;
1497 int planea_wm, planeb_wm;
1498 struct drm_crtc *crtc, *enabled = NULL;
1499
1500 if (IS_I945GM(dev))
1501 wm_info = &i945_wm_info;
1502 else if (!IS_GEN2(dev))
1503 wm_info = &i915_wm_info;
1504 else
1505 wm_info = &i830_a_wm_info;
1506
1507 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1508 crtc = intel_get_crtc_for_plane(dev, 0);
1509 if (intel_crtc_active(crtc)) {
1510 const struct drm_display_mode *adjusted_mode;
1511 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
1512 if (IS_GEN2(dev))
1513 cpp = 4;
1514
1515 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1516 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1517 wm_info, fifo_size, cpp,
1518 pessimal_latency_ns);
1519 enabled = crtc;
1520 } else {
1521 planea_wm = fifo_size - wm_info->guard_size;
1522 if (planea_wm > (long)wm_info->max_wm)
1523 planea_wm = wm_info->max_wm;
1524 }
1525
1526 if (IS_GEN2(dev))
1527 wm_info = &i830_bc_wm_info;
1528
1529 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1530 crtc = intel_get_crtc_for_plane(dev, 1);
1531 if (intel_crtc_active(crtc)) {
1532 const struct drm_display_mode *adjusted_mode;
1533 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
1534 if (IS_GEN2(dev))
1535 cpp = 4;
1536
1537 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1538 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1539 wm_info, fifo_size, cpp,
1540 pessimal_latency_ns);
1541 if (enabled == NULL)
1542 enabled = crtc;
1543 else
1544 enabled = NULL;
1545 } else {
1546 planeb_wm = fifo_size - wm_info->guard_size;
1547 if (planeb_wm > (long)wm_info->max_wm)
1548 planeb_wm = wm_info->max_wm;
1549 }
1550
1551 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1552
1553 if (IS_I915GM(dev) && enabled) {
1554 struct drm_i915_gem_object *obj;
1555
1556 obj = intel_fb_obj(enabled->primary->state->fb);
1557
1558 /* self-refresh seems busted with untiled */
1559 if (obj->tiling_mode == I915_TILING_NONE)
1560 enabled = NULL;
1561 }
1562
1563 /*
1564 * Overlay gets an aggressive default since video jitter is bad.
1565 */
1566 cwm = 2;
1567
1568 /* Play safe and disable self-refresh before adjusting watermarks. */
1569 intel_set_memory_cxsr(dev_priv, false);
1570
1571 /* Calc sr entries for one plane configs */
1572 if (HAS_FW_BLC(dev) && enabled) {
1573 /* self-refresh has much higher latency */
1574 static const int sr_latency_ns = 6000;
1575 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode;
1576 int clock = adjusted_mode->crtc_clock;
1577 int htotal = adjusted_mode->crtc_htotal;
1578 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
1579 int cpp = drm_format_plane_cpp(enabled->primary->state->fb->pixel_format, 0);
1580 unsigned long line_time_us;
1581 int entries;
1582
1583 line_time_us = max(htotal * 1000 / clock, 1);
1584
1585 /* Use ns/us then divide to preserve precision */
1586 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1587 cpp * hdisplay;
1588 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1589 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1590 srwm = wm_info->fifo_size - entries;
1591 if (srwm < 0)
1592 srwm = 1;
1593
1594 if (IS_I945G(dev) || IS_I945GM(dev))
1595 I915_WRITE(FW_BLC_SELF,
1596 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1597 else if (IS_I915GM(dev))
1598 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1599 }
1600
1601 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1602 planea_wm, planeb_wm, cwm, srwm);
1603
1604 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1605 fwater_hi = (cwm & 0x1f);
1606
1607 /* Set request length to 8 cachelines per fetch */
1608 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1609 fwater_hi = fwater_hi | (1 << 8);
1610
1611 I915_WRITE(FW_BLC, fwater_lo);
1612 I915_WRITE(FW_BLC2, fwater_hi);
1613
1614 if (enabled)
1615 intel_set_memory_cxsr(dev_priv, true);
1616 }
1617
1618 static void i845_update_wm(struct drm_crtc *unused_crtc)
1619 {
1620 struct drm_device *dev = unused_crtc->dev;
1621 struct drm_i915_private *dev_priv = dev->dev_private;
1622 struct drm_crtc *crtc;
1623 const struct drm_display_mode *adjusted_mode;
1624 uint32_t fwater_lo;
1625 int planea_wm;
1626
1627 crtc = single_enabled_crtc(dev);
1628 if (crtc == NULL)
1629 return;
1630
1631 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1632 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1633 &i845_wm_info,
1634 dev_priv->display.get_fifo_size(dev, 0),
1635 4, pessimal_latency_ns);
1636 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1637 fwater_lo |= (3<<8) | planea_wm;
1638
1639 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1640
1641 I915_WRITE(FW_BLC, fwater_lo);
1642 }
1643
1644 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
1645 {
1646 uint32_t pixel_rate;
1647
1648 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
1649
1650 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1651 * adjust the pixel_rate here. */
1652
1653 if (pipe_config->pch_pfit.enabled) {
1654 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1655 uint32_t pfit_size = pipe_config->pch_pfit.size;
1656
1657 pipe_w = pipe_config->pipe_src_w;
1658 pipe_h = pipe_config->pipe_src_h;
1659
1660 pfit_w = (pfit_size >> 16) & 0xFFFF;
1661 pfit_h = pfit_size & 0xFFFF;
1662 if (pipe_w < pfit_w)
1663 pipe_w = pfit_w;
1664 if (pipe_h < pfit_h)
1665 pipe_h = pfit_h;
1666
1667 if (WARN_ON(!pfit_w || !pfit_h))
1668 return pixel_rate;
1669
1670 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1671 pfit_w * pfit_h);
1672 }
1673
1674 return pixel_rate;
1675 }
1676
1677 /* latency must be in 0.1us units. */
1678 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
1679 {
1680 uint64_t ret;
1681
1682 if (WARN(latency == 0, "Latency value missing\n"))
1683 return UINT_MAX;
1684
1685 ret = (uint64_t) pixel_rate * cpp * latency;
1686 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1687
1688 return ret;
1689 }
1690
1691 /* latency must be in 0.1us units. */
1692 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1693 uint32_t horiz_pixels, uint8_t cpp,
1694 uint32_t latency)
1695 {
1696 uint32_t ret;
1697
1698 if (WARN(latency == 0, "Latency value missing\n"))
1699 return UINT_MAX;
1700 if (WARN_ON(!pipe_htotal))
1701 return UINT_MAX;
1702
1703 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1704 ret = (ret + 1) * horiz_pixels * cpp;
1705 ret = DIV_ROUND_UP(ret, 64) + 2;
1706 return ret;
1707 }
1708
1709 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1710 uint8_t cpp)
1711 {
1712 /*
1713 * Neither of these should be possible since this function shouldn't be
1714 * called if the CRTC is off or the plane is invisible. But let's be
1715 * extra paranoid to avoid a potential divide-by-zero if we screw up
1716 * elsewhere in the driver.
1717 */
1718 if (WARN_ON(!cpp))
1719 return 0;
1720 if (WARN_ON(!horiz_pixels))
1721 return 0;
1722
1723 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
1724 }
1725
1726 struct ilk_wm_maximums {
1727 uint16_t pri;
1728 uint16_t spr;
1729 uint16_t cur;
1730 uint16_t fbc;
1731 };
1732
1733 /*
1734 * For both WM_PIPE and WM_LP.
1735 * mem_value must be in 0.1us units.
1736 */
1737 static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
1738 const struct intel_plane_state *pstate,
1739 uint32_t mem_value,
1740 bool is_lp)
1741 {
1742 int cpp = pstate->base.fb ?
1743 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1744 uint32_t method1, method2;
1745
1746 if (!cstate->base.active || !pstate->visible)
1747 return 0;
1748
1749 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
1750
1751 if (!is_lp)
1752 return method1;
1753
1754 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1755 cstate->base.adjusted_mode.crtc_htotal,
1756 drm_rect_width(&pstate->dst),
1757 cpp, mem_value);
1758
1759 return min(method1, method2);
1760 }
1761
1762 /*
1763 * For both WM_PIPE and WM_LP.
1764 * mem_value must be in 0.1us units.
1765 */
1766 static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
1767 const struct intel_plane_state *pstate,
1768 uint32_t mem_value)
1769 {
1770 int cpp = pstate->base.fb ?
1771 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1772 uint32_t method1, method2;
1773
1774 if (!cstate->base.active || !pstate->visible)
1775 return 0;
1776
1777 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
1778 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1779 cstate->base.adjusted_mode.crtc_htotal,
1780 drm_rect_width(&pstate->dst),
1781 cpp, mem_value);
1782 return min(method1, method2);
1783 }
1784
1785 /*
1786 * For both WM_PIPE and WM_LP.
1787 * mem_value must be in 0.1us units.
1788 */
1789 static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
1790 const struct intel_plane_state *pstate,
1791 uint32_t mem_value)
1792 {
1793 /*
1794 * We treat the cursor plane as always-on for the purposes of watermark
1795 * calculation. Until we have two-stage watermark programming merged,
1796 * this is necessary to avoid flickering.
1797 */
1798 int cpp = 4;
1799 int width = pstate->visible ? pstate->base.crtc_w : 64;
1800
1801 if (!cstate->base.active)
1802 return 0;
1803
1804 return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1805 cstate->base.adjusted_mode.crtc_htotal,
1806 width, cpp, mem_value);
1807 }
1808
1809 /* Only for WM_LP. */
1810 static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
1811 const struct intel_plane_state *pstate,
1812 uint32_t pri_val)
1813 {
1814 int cpp = pstate->base.fb ?
1815 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1816
1817 if (!cstate->base.active || !pstate->visible)
1818 return 0;
1819
1820 return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->dst), cpp);
1821 }
1822
1823 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1824 {
1825 if (INTEL_INFO(dev)->gen >= 8)
1826 return 3072;
1827 else if (INTEL_INFO(dev)->gen >= 7)
1828 return 768;
1829 else
1830 return 512;
1831 }
1832
1833 static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1834 int level, bool is_sprite)
1835 {
1836 if (INTEL_INFO(dev)->gen >= 8)
1837 /* BDW primary/sprite plane watermarks */
1838 return level == 0 ? 255 : 2047;
1839 else if (INTEL_INFO(dev)->gen >= 7)
1840 /* IVB/HSW primary/sprite plane watermarks */
1841 return level == 0 ? 127 : 1023;
1842 else if (!is_sprite)
1843 /* ILK/SNB primary plane watermarks */
1844 return level == 0 ? 127 : 511;
1845 else
1846 /* ILK/SNB sprite plane watermarks */
1847 return level == 0 ? 63 : 255;
1848 }
1849
1850 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1851 int level)
1852 {
1853 if (INTEL_INFO(dev)->gen >= 7)
1854 return level == 0 ? 63 : 255;
1855 else
1856 return level == 0 ? 31 : 63;
1857 }
1858
1859 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1860 {
1861 if (INTEL_INFO(dev)->gen >= 8)
1862 return 31;
1863 else
1864 return 15;
1865 }
1866
1867 /* Calculate the maximum primary/sprite plane watermark */
1868 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1869 int level,
1870 const struct intel_wm_config *config,
1871 enum intel_ddb_partitioning ddb_partitioning,
1872 bool is_sprite)
1873 {
1874 unsigned int fifo_size = ilk_display_fifo_size(dev);
1875
1876 /* if sprites aren't enabled, sprites get nothing */
1877 if (is_sprite && !config->sprites_enabled)
1878 return 0;
1879
1880 /* HSW allows LP1+ watermarks even with multiple pipes */
1881 if (level == 0 || config->num_pipes_active > 1) {
1882 fifo_size /= INTEL_INFO(dev)->num_pipes;
1883
1884 /*
1885 * For some reason the non self refresh
1886 * FIFO size is only half of the self
1887 * refresh FIFO size on ILK/SNB.
1888 */
1889 if (INTEL_INFO(dev)->gen <= 6)
1890 fifo_size /= 2;
1891 }
1892
1893 if (config->sprites_enabled) {
1894 /* level 0 is always calculated with 1:1 split */
1895 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1896 if (is_sprite)
1897 fifo_size *= 5;
1898 fifo_size /= 6;
1899 } else {
1900 fifo_size /= 2;
1901 }
1902 }
1903
1904 /* clamp to max that the registers can hold */
1905 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
1906 }
1907
1908 /* Calculate the maximum cursor plane watermark */
1909 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
1910 int level,
1911 const struct intel_wm_config *config)
1912 {
1913 /* HSW LP1+ watermarks w/ multiple pipes */
1914 if (level > 0 && config->num_pipes_active > 1)
1915 return 64;
1916
1917 /* otherwise just report max that registers can hold */
1918 return ilk_cursor_wm_reg_max(dev, level);
1919 }
1920
1921 static void ilk_compute_wm_maximums(const struct drm_device *dev,
1922 int level,
1923 const struct intel_wm_config *config,
1924 enum intel_ddb_partitioning ddb_partitioning,
1925 struct ilk_wm_maximums *max)
1926 {
1927 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1928 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1929 max->cur = ilk_cursor_wm_max(dev, level, config);
1930 max->fbc = ilk_fbc_wm_reg_max(dev);
1931 }
1932
1933 static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1934 int level,
1935 struct ilk_wm_maximums *max)
1936 {
1937 max->pri = ilk_plane_wm_reg_max(dev, level, false);
1938 max->spr = ilk_plane_wm_reg_max(dev, level, true);
1939 max->cur = ilk_cursor_wm_reg_max(dev, level);
1940 max->fbc = ilk_fbc_wm_reg_max(dev);
1941 }
1942
1943 static bool ilk_validate_wm_level(int level,
1944 const struct ilk_wm_maximums *max,
1945 struct intel_wm_level *result)
1946 {
1947 bool ret;
1948
1949 /* already determined to be invalid? */
1950 if (!result->enable)
1951 return false;
1952
1953 result->enable = result->pri_val <= max->pri &&
1954 result->spr_val <= max->spr &&
1955 result->cur_val <= max->cur;
1956
1957 ret = result->enable;
1958
1959 /*
1960 * HACK until we can pre-compute everything,
1961 * and thus fail gracefully if LP0 watermarks
1962 * are exceeded...
1963 */
1964 if (level == 0 && !result->enable) {
1965 if (result->pri_val > max->pri)
1966 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1967 level, result->pri_val, max->pri);
1968 if (result->spr_val > max->spr)
1969 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1970 level, result->spr_val, max->spr);
1971 if (result->cur_val > max->cur)
1972 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1973 level, result->cur_val, max->cur);
1974
1975 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
1976 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
1977 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
1978 result->enable = true;
1979 }
1980
1981 return ret;
1982 }
1983
1984 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
1985 const struct intel_crtc *intel_crtc,
1986 int level,
1987 struct intel_crtc_state *cstate,
1988 struct intel_plane_state *pristate,
1989 struct intel_plane_state *sprstate,
1990 struct intel_plane_state *curstate,
1991 struct intel_wm_level *result)
1992 {
1993 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
1994 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
1995 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
1996
1997 /* WM1+ latency values stored in 0.5us units */
1998 if (level > 0) {
1999 pri_latency *= 5;
2000 spr_latency *= 5;
2001 cur_latency *= 5;
2002 }
2003
2004 if (pristate) {
2005 result->pri_val = ilk_compute_pri_wm(cstate, pristate,
2006 pri_latency, level);
2007 result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
2008 }
2009
2010 if (sprstate)
2011 result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
2012
2013 if (curstate)
2014 result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
2015
2016 result->enable = true;
2017 }
2018
2019 static uint32_t
2020 hsw_compute_linetime_wm(const struct intel_crtc_state *cstate)
2021 {
2022 const struct intel_atomic_state *intel_state =
2023 to_intel_atomic_state(cstate->base.state);
2024 const struct drm_display_mode *adjusted_mode =
2025 &cstate->base.adjusted_mode;
2026 u32 linetime, ips_linetime;
2027
2028 if (!cstate->base.active)
2029 return 0;
2030 if (WARN_ON(adjusted_mode->crtc_clock == 0))
2031 return 0;
2032 if (WARN_ON(intel_state->cdclk == 0))
2033 return 0;
2034
2035 /* The WM are computed with base on how long it takes to fill a single
2036 * row at the given clock rate, multiplied by 8.
2037 * */
2038 linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2039 adjusted_mode->crtc_clock);
2040 ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2041 intel_state->cdclk);
2042
2043 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2044 PIPE_WM_LINETIME_TIME(linetime);
2045 }
2046
2047 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
2048 {
2049 struct drm_i915_private *dev_priv = dev->dev_private;
2050
2051 if (IS_GEN9(dev)) {
2052 uint32_t val;
2053 int ret, i;
2054 int level, max_level = ilk_wm_max_level(dev);
2055
2056 /* read the first set of memory latencies[0:3] */
2057 val = 0; /* data0 to be programmed to 0 for first set */
2058 mutex_lock(&dev_priv->rps.hw_lock);
2059 ret = sandybridge_pcode_read(dev_priv,
2060 GEN9_PCODE_READ_MEM_LATENCY,
2061 &val);
2062 mutex_unlock(&dev_priv->rps.hw_lock);
2063
2064 if (ret) {
2065 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2066 return;
2067 }
2068
2069 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2070 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2071 GEN9_MEM_LATENCY_LEVEL_MASK;
2072 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2073 GEN9_MEM_LATENCY_LEVEL_MASK;
2074 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2075 GEN9_MEM_LATENCY_LEVEL_MASK;
2076
2077 /* read the second set of memory latencies[4:7] */
2078 val = 1; /* data0 to be programmed to 1 for second set */
2079 mutex_lock(&dev_priv->rps.hw_lock);
2080 ret = sandybridge_pcode_read(dev_priv,
2081 GEN9_PCODE_READ_MEM_LATENCY,
2082 &val);
2083 mutex_unlock(&dev_priv->rps.hw_lock);
2084 if (ret) {
2085 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2086 return;
2087 }
2088
2089 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2090 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2091 GEN9_MEM_LATENCY_LEVEL_MASK;
2092 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2093 GEN9_MEM_LATENCY_LEVEL_MASK;
2094 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2095 GEN9_MEM_LATENCY_LEVEL_MASK;
2096
2097 /*
2098 * WaWmMemoryReadLatency:skl
2099 *
2100 * punit doesn't take into account the read latency so we need
2101 * to add 2us to the various latency levels we retrieve from
2102 * the punit.
2103 * - W0 is a bit special in that it's the only level that
2104 * can't be disabled if we want to have display working, so
2105 * we always add 2us there.
2106 * - For levels >=1, punit returns 0us latency when they are
2107 * disabled, so we respect that and don't add 2us then
2108 *
2109 * Additionally, if a level n (n > 1) has a 0us latency, all
2110 * levels m (m >= n) need to be disabled. We make sure to
2111 * sanitize the values out of the punit to satisfy this
2112 * requirement.
2113 */
2114 wm[0] += 2;
2115 for (level = 1; level <= max_level; level++)
2116 if (wm[level] != 0)
2117 wm[level] += 2;
2118 else {
2119 for (i = level + 1; i <= max_level; i++)
2120 wm[i] = 0;
2121
2122 break;
2123 }
2124 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2125 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2126
2127 wm[0] = (sskpd >> 56) & 0xFF;
2128 if (wm[0] == 0)
2129 wm[0] = sskpd & 0xF;
2130 wm[1] = (sskpd >> 4) & 0xFF;
2131 wm[2] = (sskpd >> 12) & 0xFF;
2132 wm[3] = (sskpd >> 20) & 0x1FF;
2133 wm[4] = (sskpd >> 32) & 0x1FF;
2134 } else if (INTEL_INFO(dev)->gen >= 6) {
2135 uint32_t sskpd = I915_READ(MCH_SSKPD);
2136
2137 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2138 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2139 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2140 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2141 } else if (INTEL_INFO(dev)->gen >= 5) {
2142 uint32_t mltr = I915_READ(MLTR_ILK);
2143
2144 /* ILK primary LP0 latency is 700 ns */
2145 wm[0] = 7;
2146 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2147 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2148 }
2149 }
2150
2151 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2152 {
2153 /* ILK sprite LP0 latency is 1300 ns */
2154 if (IS_GEN5(dev))
2155 wm[0] = 13;
2156 }
2157
2158 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2159 {
2160 /* ILK cursor LP0 latency is 1300 ns */
2161 if (IS_GEN5(dev))
2162 wm[0] = 13;
2163
2164 /* WaDoubleCursorLP3Latency:ivb */
2165 if (IS_IVYBRIDGE(dev))
2166 wm[3] *= 2;
2167 }
2168
2169 int ilk_wm_max_level(const struct drm_device *dev)
2170 {
2171 /* how many WM levels are we expecting */
2172 if (INTEL_INFO(dev)->gen >= 9)
2173 return 7;
2174 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2175 return 4;
2176 else if (INTEL_INFO(dev)->gen >= 6)
2177 return 3;
2178 else
2179 return 2;
2180 }
2181
2182 static void intel_print_wm_latency(struct drm_device *dev,
2183 const char *name,
2184 const uint16_t wm[8])
2185 {
2186 int level, max_level = ilk_wm_max_level(dev);
2187
2188 for (level = 0; level <= max_level; level++) {
2189 unsigned int latency = wm[level];
2190
2191 if (latency == 0) {
2192 DRM_ERROR("%s WM%d latency not provided\n",
2193 name, level);
2194 continue;
2195 }
2196
2197 /*
2198 * - latencies are in us on gen9.
2199 * - before then, WM1+ latency values are in 0.5us units
2200 */
2201 if (IS_GEN9(dev))
2202 latency *= 10;
2203 else if (level > 0)
2204 latency *= 5;
2205
2206 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2207 name, level, wm[level],
2208 latency / 10, latency % 10);
2209 }
2210 }
2211
2212 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2213 uint16_t wm[5], uint16_t min)
2214 {
2215 int level, max_level = ilk_wm_max_level(dev_priv->dev);
2216
2217 if (wm[0] >= min)
2218 return false;
2219
2220 wm[0] = max(wm[0], min);
2221 for (level = 1; level <= max_level; level++)
2222 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2223
2224 return true;
2225 }
2226
2227 static void snb_wm_latency_quirk(struct drm_device *dev)
2228 {
2229 struct drm_i915_private *dev_priv = dev->dev_private;
2230 bool changed;
2231
2232 /*
2233 * The BIOS provided WM memory latency values are often
2234 * inadequate for high resolution displays. Adjust them.
2235 */
2236 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2237 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2238 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2239
2240 if (!changed)
2241 return;
2242
2243 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2244 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2245 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2246 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2247 }
2248
2249 static void ilk_setup_wm_latency(struct drm_device *dev)
2250 {
2251 struct drm_i915_private *dev_priv = dev->dev_private;
2252
2253 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2254
2255 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2256 sizeof(dev_priv->wm.pri_latency));
2257 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2258 sizeof(dev_priv->wm.pri_latency));
2259
2260 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2261 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2262
2263 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2264 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2265 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2266
2267 if (IS_GEN6(dev))
2268 snb_wm_latency_quirk(dev);
2269 }
2270
2271 static void skl_setup_wm_latency(struct drm_device *dev)
2272 {
2273 struct drm_i915_private *dev_priv = dev->dev_private;
2274
2275 intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2276 intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2277 }
2278
2279 static bool ilk_validate_pipe_wm(struct drm_device *dev,
2280 struct intel_pipe_wm *pipe_wm)
2281 {
2282 /* LP0 watermark maximums depend on this pipe alone */
2283 const struct intel_wm_config config = {
2284 .num_pipes_active = 1,
2285 .sprites_enabled = pipe_wm->sprites_enabled,
2286 .sprites_scaled = pipe_wm->sprites_scaled,
2287 };
2288 struct ilk_wm_maximums max;
2289
2290 /* LP0 watermarks always use 1/2 DDB partitioning */
2291 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2292
2293 /* At least LP0 must be valid */
2294 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
2295 DRM_DEBUG_KMS("LP0 watermark invalid\n");
2296 return false;
2297 }
2298
2299 return true;
2300 }
2301
2302 /* Compute new watermarks for the pipe */
2303 static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
2304 {
2305 struct drm_atomic_state *state = cstate->base.state;
2306 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
2307 struct intel_pipe_wm *pipe_wm;
2308 struct drm_device *dev = state->dev;
2309 const struct drm_i915_private *dev_priv = dev->dev_private;
2310 struct intel_plane *intel_plane;
2311 struct intel_plane_state *pristate = NULL;
2312 struct intel_plane_state *sprstate = NULL;
2313 struct intel_plane_state *curstate = NULL;
2314 int level, max_level = ilk_wm_max_level(dev), usable_level;
2315 struct ilk_wm_maximums max;
2316
2317 pipe_wm = &cstate->wm.ilk.optimal;
2318
2319 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2320 struct intel_plane_state *ps;
2321
2322 ps = intel_atomic_get_existing_plane_state(state,
2323 intel_plane);
2324 if (!ps)
2325 continue;
2326
2327 if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
2328 pristate = ps;
2329 else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
2330 sprstate = ps;
2331 else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
2332 curstate = ps;
2333 }
2334
2335 pipe_wm->pipe_enabled = cstate->base.active;
2336 if (sprstate) {
2337 pipe_wm->sprites_enabled = sprstate->visible;
2338 pipe_wm->sprites_scaled = sprstate->visible &&
2339 (drm_rect_width(&sprstate->dst) != drm_rect_width(&sprstate->src) >> 16 ||
2340 drm_rect_height(&sprstate->dst) != drm_rect_height(&sprstate->src) >> 16);
2341 }
2342
2343 usable_level = max_level;
2344
2345 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2346 if (INTEL_INFO(dev)->gen <= 6 && pipe_wm->sprites_enabled)
2347 usable_level = 1;
2348
2349 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2350 if (pipe_wm->sprites_scaled)
2351 usable_level = 0;
2352
2353 ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
2354 pristate, sprstate, curstate, &pipe_wm->raw_wm[0]);
2355
2356 memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
2357 pipe_wm->wm[0] = pipe_wm->raw_wm[0];
2358
2359 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2360 pipe_wm->linetime = hsw_compute_linetime_wm(cstate);
2361
2362 if (!ilk_validate_pipe_wm(dev, pipe_wm))
2363 return -EINVAL;
2364
2365 ilk_compute_wm_reg_maximums(dev, 1, &max);
2366
2367 for (level = 1; level <= max_level; level++) {
2368 struct intel_wm_level *wm = &pipe_wm->raw_wm[level];
2369
2370 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
2371 pristate, sprstate, curstate, wm);
2372
2373 /*
2374 * Disable any watermark level that exceeds the
2375 * register maximums since such watermarks are
2376 * always invalid.
2377 */
2378 if (level > usable_level)
2379 continue;
2380
2381 if (ilk_validate_wm_level(level, &max, wm))
2382 pipe_wm->wm[level] = *wm;
2383 else
2384 usable_level = level;
2385 }
2386
2387 return 0;
2388 }
2389
2390 /*
2391 * Build a set of 'intermediate' watermark values that satisfy both the old
2392 * state and the new state. These can be programmed to the hardware
2393 * immediately.
2394 */
2395 static int ilk_compute_intermediate_wm(struct drm_device *dev,
2396 struct intel_crtc *intel_crtc,
2397 struct intel_crtc_state *newstate)
2398 {
2399 struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate;
2400 struct intel_pipe_wm *b = &intel_crtc->wm.active.ilk;
2401 int level, max_level = ilk_wm_max_level(dev);
2402
2403 /*
2404 * Start with the final, target watermarks, then combine with the
2405 * currently active watermarks to get values that are safe both before
2406 * and after the vblank.
2407 */
2408 *a = newstate->wm.ilk.optimal;
2409 a->pipe_enabled |= b->pipe_enabled;
2410 a->sprites_enabled |= b->sprites_enabled;
2411 a->sprites_scaled |= b->sprites_scaled;
2412
2413 for (level = 0; level <= max_level; level++) {
2414 struct intel_wm_level *a_wm = &a->wm[level];
2415 const struct intel_wm_level *b_wm = &b->wm[level];
2416
2417 a_wm->enable &= b_wm->enable;
2418 a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val);
2419 a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val);
2420 a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val);
2421 a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val);
2422 }
2423
2424 /*
2425 * We need to make sure that these merged watermark values are
2426 * actually a valid configuration themselves. If they're not,
2427 * there's no safe way to transition from the old state to
2428 * the new state, so we need to fail the atomic transaction.
2429 */
2430 if (!ilk_validate_pipe_wm(dev, a))
2431 return -EINVAL;
2432
2433 /*
2434 * If our intermediate WM are identical to the final WM, then we can
2435 * omit the post-vblank programming; only update if it's different.
2436 */
2437 if (memcmp(a, &newstate->wm.ilk.optimal, sizeof(*a)) == 0)
2438 newstate->wm.need_postvbl_update = false;
2439
2440 return 0;
2441 }
2442
2443 /*
2444 * Merge the watermarks from all active pipes for a specific level.
2445 */
2446 static void ilk_merge_wm_level(struct drm_device *dev,
2447 int level,
2448 struct intel_wm_level *ret_wm)
2449 {
2450 const struct intel_crtc *intel_crtc;
2451
2452 ret_wm->enable = true;
2453
2454 for_each_intel_crtc(dev, intel_crtc) {
2455 const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk;
2456 const struct intel_wm_level *wm = &active->wm[level];
2457
2458 if (!active->pipe_enabled)
2459 continue;
2460
2461 /*
2462 * The watermark values may have been used in the past,
2463 * so we must maintain them in the registers for some
2464 * time even if the level is now disabled.
2465 */
2466 if (!wm->enable)
2467 ret_wm->enable = false;
2468
2469 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2470 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2471 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2472 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2473 }
2474 }
2475
2476 /*
2477 * Merge all low power watermarks for all active pipes.
2478 */
2479 static void ilk_wm_merge(struct drm_device *dev,
2480 const struct intel_wm_config *config,
2481 const struct ilk_wm_maximums *max,
2482 struct intel_pipe_wm *merged)
2483 {
2484 struct drm_i915_private *dev_priv = dev->dev_private;
2485 int level, max_level = ilk_wm_max_level(dev);
2486 int last_enabled_level = max_level;
2487
2488 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2489 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2490 config->num_pipes_active > 1)
2491 last_enabled_level = 0;
2492
2493 /* ILK: FBC WM must be disabled always */
2494 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
2495
2496 /* merge each WM1+ level */
2497 for (level = 1; level <= max_level; level++) {
2498 struct intel_wm_level *wm = &merged->wm[level];
2499
2500 ilk_merge_wm_level(dev, level, wm);
2501
2502 if (level > last_enabled_level)
2503 wm->enable = false;
2504 else if (!ilk_validate_wm_level(level, max, wm))
2505 /* make sure all following levels get disabled */
2506 last_enabled_level = level - 1;
2507
2508 /*
2509 * The spec says it is preferred to disable
2510 * FBC WMs instead of disabling a WM level.
2511 */
2512 if (wm->fbc_val > max->fbc) {
2513 if (wm->enable)
2514 merged->fbc_wm_enabled = false;
2515 wm->fbc_val = 0;
2516 }
2517 }
2518
2519 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2520 /*
2521 * FIXME this is racy. FBC might get enabled later.
2522 * What we should check here is whether FBC can be
2523 * enabled sometime later.
2524 */
2525 if (IS_GEN5(dev) && !merged->fbc_wm_enabled &&
2526 intel_fbc_is_active(dev_priv)) {
2527 for (level = 2; level <= max_level; level++) {
2528 struct intel_wm_level *wm = &merged->wm[level];
2529
2530 wm->enable = false;
2531 }
2532 }
2533 }
2534
2535 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2536 {
2537 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2538 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2539 }
2540
2541 /* The value we need to program into the WM_LPx latency field */
2542 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2543 {
2544 struct drm_i915_private *dev_priv = dev->dev_private;
2545
2546 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2547 return 2 * level;
2548 else
2549 return dev_priv->wm.pri_latency[level];
2550 }
2551
2552 static void ilk_compute_wm_results(struct drm_device *dev,
2553 const struct intel_pipe_wm *merged,
2554 enum intel_ddb_partitioning partitioning,
2555 struct ilk_wm_values *results)
2556 {
2557 struct intel_crtc *intel_crtc;
2558 int level, wm_lp;
2559
2560 results->enable_fbc_wm = merged->fbc_wm_enabled;
2561 results->partitioning = partitioning;
2562
2563 /* LP1+ register values */
2564 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2565 const struct intel_wm_level *r;
2566
2567 level = ilk_wm_lp_to_level(wm_lp, merged);
2568
2569 r = &merged->wm[level];
2570
2571 /*
2572 * Maintain the watermark values even if the level is
2573 * disabled. Doing otherwise could cause underruns.
2574 */
2575 results->wm_lp[wm_lp - 1] =
2576 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2577 (r->pri_val << WM1_LP_SR_SHIFT) |
2578 r->cur_val;
2579
2580 if (r->enable)
2581 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2582
2583 if (INTEL_INFO(dev)->gen >= 8)
2584 results->wm_lp[wm_lp - 1] |=
2585 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2586 else
2587 results->wm_lp[wm_lp - 1] |=
2588 r->fbc_val << WM1_LP_FBC_SHIFT;
2589
2590 /*
2591 * Always set WM1S_LP_EN when spr_val != 0, even if the
2592 * level is disabled. Doing otherwise could cause underruns.
2593 */
2594 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2595 WARN_ON(wm_lp != 1);
2596 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2597 } else
2598 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2599 }
2600
2601 /* LP0 register values */
2602 for_each_intel_crtc(dev, intel_crtc) {
2603 enum pipe pipe = intel_crtc->pipe;
2604 const struct intel_wm_level *r =
2605 &intel_crtc->wm.active.ilk.wm[0];
2606
2607 if (WARN_ON(!r->enable))
2608 continue;
2609
2610 results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime;
2611
2612 results->wm_pipe[pipe] =
2613 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2614 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2615 r->cur_val;
2616 }
2617 }
2618
2619 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2620 * case both are at the same level. Prefer r1 in case they're the same. */
2621 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2622 struct intel_pipe_wm *r1,
2623 struct intel_pipe_wm *r2)
2624 {
2625 int level, max_level = ilk_wm_max_level(dev);
2626 int level1 = 0, level2 = 0;
2627
2628 for (level = 1; level <= max_level; level++) {
2629 if (r1->wm[level].enable)
2630 level1 = level;
2631 if (r2->wm[level].enable)
2632 level2 = level;
2633 }
2634
2635 if (level1 == level2) {
2636 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2637 return r2;
2638 else
2639 return r1;
2640 } else if (level1 > level2) {
2641 return r1;
2642 } else {
2643 return r2;
2644 }
2645 }
2646
2647 /* dirty bits used to track which watermarks need changes */
2648 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2649 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2650 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2651 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2652 #define WM_DIRTY_FBC (1 << 24)
2653 #define WM_DIRTY_DDB (1 << 25)
2654
2655 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
2656 const struct ilk_wm_values *old,
2657 const struct ilk_wm_values *new)
2658 {
2659 unsigned int dirty = 0;
2660 enum pipe pipe;
2661 int wm_lp;
2662
2663 for_each_pipe(dev_priv, pipe) {
2664 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2665 dirty |= WM_DIRTY_LINETIME(pipe);
2666 /* Must disable LP1+ watermarks too */
2667 dirty |= WM_DIRTY_LP_ALL;
2668 }
2669
2670 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2671 dirty |= WM_DIRTY_PIPE(pipe);
2672 /* Must disable LP1+ watermarks too */
2673 dirty |= WM_DIRTY_LP_ALL;
2674 }
2675 }
2676
2677 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2678 dirty |= WM_DIRTY_FBC;
2679 /* Must disable LP1+ watermarks too */
2680 dirty |= WM_DIRTY_LP_ALL;
2681 }
2682
2683 if (old->partitioning != new->partitioning) {
2684 dirty |= WM_DIRTY_DDB;
2685 /* Must disable LP1+ watermarks too */
2686 dirty |= WM_DIRTY_LP_ALL;
2687 }
2688
2689 /* LP1+ watermarks already deemed dirty, no need to continue */
2690 if (dirty & WM_DIRTY_LP_ALL)
2691 return dirty;
2692
2693 /* Find the lowest numbered LP1+ watermark in need of an update... */
2694 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2695 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2696 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2697 break;
2698 }
2699
2700 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2701 for (; wm_lp <= 3; wm_lp++)
2702 dirty |= WM_DIRTY_LP(wm_lp);
2703
2704 return dirty;
2705 }
2706
2707 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2708 unsigned int dirty)
2709 {
2710 struct ilk_wm_values *previous = &dev_priv->wm.hw;
2711 bool changed = false;
2712
2713 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2714 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2715 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2716 changed = true;
2717 }
2718 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2719 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2720 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2721 changed = true;
2722 }
2723 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2724 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2725 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2726 changed = true;
2727 }
2728
2729 /*
2730 * Don't touch WM1S_LP_EN here.
2731 * Doing so could cause underruns.
2732 */
2733
2734 return changed;
2735 }
2736
2737 /*
2738 * The spec says we shouldn't write when we don't need, because every write
2739 * causes WMs to be re-evaluated, expending some power.
2740 */
2741 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2742 struct ilk_wm_values *results)
2743 {
2744 struct drm_device *dev = dev_priv->dev;
2745 struct ilk_wm_values *previous = &dev_priv->wm.hw;
2746 unsigned int dirty;
2747 uint32_t val;
2748
2749 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
2750 if (!dirty)
2751 return;
2752
2753 _ilk_disable_lp_wm(dev_priv, dirty);
2754
2755 if (dirty & WM_DIRTY_PIPE(PIPE_A))
2756 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2757 if (dirty & WM_DIRTY_PIPE(PIPE_B))
2758 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2759 if (dirty & WM_DIRTY_PIPE(PIPE_C))
2760 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2761
2762 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2763 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2764 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2765 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2766 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2767 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2768
2769 if (dirty & WM_DIRTY_DDB) {
2770 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2771 val = I915_READ(WM_MISC);
2772 if (results->partitioning == INTEL_DDB_PART_1_2)
2773 val &= ~WM_MISC_DATA_PARTITION_5_6;
2774 else
2775 val |= WM_MISC_DATA_PARTITION_5_6;
2776 I915_WRITE(WM_MISC, val);
2777 } else {
2778 val = I915_READ(DISP_ARB_CTL2);
2779 if (results->partitioning == INTEL_DDB_PART_1_2)
2780 val &= ~DISP_DATA_PARTITION_5_6;
2781 else
2782 val |= DISP_DATA_PARTITION_5_6;
2783 I915_WRITE(DISP_ARB_CTL2, val);
2784 }
2785 }
2786
2787 if (dirty & WM_DIRTY_FBC) {
2788 val = I915_READ(DISP_ARB_CTL);
2789 if (results->enable_fbc_wm)
2790 val &= ~DISP_FBC_WM_DIS;
2791 else
2792 val |= DISP_FBC_WM_DIS;
2793 I915_WRITE(DISP_ARB_CTL, val);
2794 }
2795
2796 if (dirty & WM_DIRTY_LP(1) &&
2797 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2798 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2799
2800 if (INTEL_INFO(dev)->gen >= 7) {
2801 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2802 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2803 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2804 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2805 }
2806
2807 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2808 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2809 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2810 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2811 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2812 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2813
2814 dev_priv->wm.hw = *results;
2815 }
2816
2817 bool ilk_disable_lp_wm(struct drm_device *dev)
2818 {
2819 struct drm_i915_private *dev_priv = dev->dev_private;
2820
2821 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2822 }
2823
2824 /*
2825 * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2826 * different active planes.
2827 */
2828
2829 #define SKL_DDB_SIZE 896 /* in blocks */
2830 #define BXT_DDB_SIZE 512
2831
2832 /*
2833 * Return the index of a plane in the SKL DDB and wm result arrays. Primary
2834 * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
2835 * other universal planes are in indices 1..n. Note that this may leave unused
2836 * indices between the top "sprite" plane and the cursor.
2837 */
2838 static int
2839 skl_wm_plane_id(const struct intel_plane *plane)
2840 {
2841 switch (plane->base.type) {
2842 case DRM_PLANE_TYPE_PRIMARY:
2843 return 0;
2844 case DRM_PLANE_TYPE_CURSOR:
2845 return PLANE_CURSOR;
2846 case DRM_PLANE_TYPE_OVERLAY:
2847 return plane->plane + 1;
2848 default:
2849 MISSING_CASE(plane->base.type);
2850 return plane->plane;
2851 }
2852 }
2853
2854 static void
2855 skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
2856 const struct intel_crtc_state *cstate,
2857 struct skl_ddb_entry *alloc, /* out */
2858 int *num_active /* out */)
2859 {
2860 struct drm_atomic_state *state = cstate->base.state;
2861 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
2862 struct drm_i915_private *dev_priv = to_i915(dev);
2863 struct drm_crtc *for_crtc = cstate->base.crtc;
2864 unsigned int pipe_size, ddb_size;
2865 int nth_active_pipe;
2866 int pipe = to_intel_crtc(for_crtc)->pipe;
2867
2868 if (WARN_ON(!state) || !cstate->base.active) {
2869 alloc->start = 0;
2870 alloc->end = 0;
2871 *num_active = hweight32(dev_priv->active_crtcs);
2872 return;
2873 }
2874
2875 if (intel_state->active_pipe_changes)
2876 *num_active = hweight32(intel_state->active_crtcs);
2877 else
2878 *num_active = hweight32(dev_priv->active_crtcs);
2879
2880 if (IS_BROXTON(dev))
2881 ddb_size = BXT_DDB_SIZE;
2882 else
2883 ddb_size = SKL_DDB_SIZE;
2884
2885 ddb_size -= 4; /* 4 blocks for bypass path allocation */
2886
2887 /*
2888 * If the state doesn't change the active CRTC's, then there's
2889 * no need to recalculate; the existing pipe allocation limits
2890 * should remain unchanged. Note that we're safe from racing
2891 * commits since any racing commit that changes the active CRTC
2892 * list would need to grab _all_ crtc locks, including the one
2893 * we currently hold.
2894 */
2895 if (!intel_state->active_pipe_changes) {
2896 *alloc = dev_priv->wm.skl_hw.ddb.pipe[pipe];
2897 return;
2898 }
2899
2900 nth_active_pipe = hweight32(intel_state->active_crtcs &
2901 (drm_crtc_mask(for_crtc) - 1));
2902 pipe_size = ddb_size / hweight32(intel_state->active_crtcs);
2903 alloc->start = nth_active_pipe * ddb_size / *num_active;
2904 alloc->end = alloc->start + pipe_size;
2905 }
2906
2907 static unsigned int skl_cursor_allocation(int num_active)
2908 {
2909 if (num_active == 1)
2910 return 32;
2911
2912 return 8;
2913 }
2914
2915 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
2916 {
2917 entry->start = reg & 0x3ff;
2918 entry->end = (reg >> 16) & 0x3ff;
2919 if (entry->end)
2920 entry->end += 1;
2921 }
2922
2923 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2924 struct skl_ddb_allocation *ddb /* out */)
2925 {
2926 enum pipe pipe;
2927 int plane;
2928 u32 val;
2929
2930 memset(ddb, 0, sizeof(*ddb));
2931
2932 for_each_pipe(dev_priv, pipe) {
2933 enum intel_display_power_domain power_domain;
2934
2935 power_domain = POWER_DOMAIN_PIPE(pipe);
2936 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
2937 continue;
2938
2939 for_each_plane(dev_priv, pipe, plane) {
2940 val = I915_READ(PLANE_BUF_CFG(pipe, plane));
2941 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
2942 val);
2943 }
2944
2945 val = I915_READ(CUR_BUF_CFG(pipe));
2946 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
2947 val);
2948
2949 intel_display_power_put(dev_priv, power_domain);
2950 }
2951 }
2952
2953 /*
2954 * Determines the downscale amount of a plane for the purposes of watermark calculations.
2955 * The bspec defines downscale amount as:
2956 *
2957 * """
2958 * Horizontal down scale amount = maximum[1, Horizontal source size /
2959 * Horizontal destination size]
2960 * Vertical down scale amount = maximum[1, Vertical source size /
2961 * Vertical destination size]
2962 * Total down scale amount = Horizontal down scale amount *
2963 * Vertical down scale amount
2964 * """
2965 *
2966 * Return value is provided in 16.16 fixed point form to retain fractional part.
2967 * Caller should take care of dividing & rounding off the value.
2968 */
2969 static uint32_t
2970 skl_plane_downscale_amount(const struct intel_plane_state *pstate)
2971 {
2972 uint32_t downscale_h, downscale_w;
2973 uint32_t src_w, src_h, dst_w, dst_h;
2974
2975 if (WARN_ON(!pstate->visible))
2976 return DRM_PLANE_HELPER_NO_SCALING;
2977
2978 /* n.b., src is 16.16 fixed point, dst is whole integer */
2979 src_w = drm_rect_width(&pstate->src);
2980 src_h = drm_rect_height(&pstate->src);
2981 dst_w = drm_rect_width(&pstate->dst);
2982 dst_h = drm_rect_height(&pstate->dst);
2983 if (intel_rotation_90_or_270(pstate->base.rotation))
2984 swap(dst_w, dst_h);
2985
2986 downscale_h = max(src_h / dst_h, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
2987 downscale_w = max(src_w / dst_w, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
2988
2989 /* Provide result in 16.16 fixed point */
2990 return (uint64_t)downscale_w * downscale_h >> 16;
2991 }
2992
2993 static unsigned int
2994 skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
2995 const struct drm_plane_state *pstate,
2996 int y)
2997 {
2998 struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
2999 struct drm_framebuffer *fb = pstate->fb;
3000 uint32_t down_scale_amount, data_rate;
3001 uint32_t width = 0, height = 0;
3002 unsigned format = fb ? fb->pixel_format : DRM_FORMAT_XRGB8888;
3003
3004 if (!intel_pstate->visible)
3005 return 0;
3006 if (pstate->plane->type == DRM_PLANE_TYPE_CURSOR)
3007 return 0;
3008 if (y && format != DRM_FORMAT_NV12)
3009 return 0;
3010
3011 width = drm_rect_width(&intel_pstate->src) >> 16;
3012 height = drm_rect_height(&intel_pstate->src) >> 16;
3013
3014 if (intel_rotation_90_or_270(pstate->rotation))
3015 swap(width, height);
3016
3017 /* for planar format */
3018 if (format == DRM_FORMAT_NV12) {
3019 if (y) /* y-plane data rate */
3020 data_rate = width * height *
3021 drm_format_plane_cpp(format, 0);
3022 else /* uv-plane data rate */
3023 data_rate = (width / 2) * (height / 2) *
3024 drm_format_plane_cpp(format, 1);
3025 } else {
3026 /* for packed formats */
3027 data_rate = width * height * drm_format_plane_cpp(format, 0);
3028 }
3029
3030 down_scale_amount = skl_plane_downscale_amount(intel_pstate);
3031
3032 return (uint64_t)data_rate * down_scale_amount >> 16;
3033 }
3034
3035 /*
3036 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
3037 * a 8192x4096@32bpp framebuffer:
3038 * 3 * 4096 * 8192 * 4 < 2^32
3039 */
3040 static unsigned int
3041 skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate)
3042 {
3043 struct drm_crtc_state *cstate = &intel_cstate->base;
3044 struct drm_atomic_state *state = cstate->state;
3045 struct drm_crtc *crtc = cstate->crtc;
3046 struct drm_device *dev = crtc->dev;
3047 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3048 const struct drm_plane *plane;
3049 const struct intel_plane *intel_plane;
3050 struct drm_plane_state *pstate;
3051 unsigned int rate, total_data_rate = 0;
3052 int id;
3053 int i;
3054
3055 if (WARN_ON(!state))
3056 return 0;
3057
3058 /* Calculate and cache data rate for each plane */
3059 for_each_plane_in_state(state, plane, pstate, i) {
3060 id = skl_wm_plane_id(to_intel_plane(plane));
3061 intel_plane = to_intel_plane(plane);
3062
3063 if (intel_plane->pipe != intel_crtc->pipe)
3064 continue;
3065
3066 /* packed/uv */
3067 rate = skl_plane_relative_data_rate(intel_cstate,
3068 pstate, 0);
3069 intel_cstate->wm.skl.plane_data_rate[id] = rate;
3070
3071 /* y-plane */
3072 rate = skl_plane_relative_data_rate(intel_cstate,
3073 pstate, 1);
3074 intel_cstate->wm.skl.plane_y_data_rate[id] = rate;
3075 }
3076
3077 /* Calculate CRTC's total data rate from cached values */
3078 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3079 int id = skl_wm_plane_id(intel_plane);
3080
3081 /* packed/uv */
3082 total_data_rate += intel_cstate->wm.skl.plane_data_rate[id];
3083 total_data_rate += intel_cstate->wm.skl.plane_y_data_rate[id];
3084 }
3085
3086 WARN_ON(cstate->plane_mask && total_data_rate == 0);
3087
3088 return total_data_rate;
3089 }
3090
3091 static uint16_t
3092 skl_ddb_min_alloc(const struct drm_plane_state *pstate,
3093 const int y)
3094 {
3095 struct drm_framebuffer *fb = pstate->fb;
3096 struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
3097 uint32_t src_w, src_h;
3098 uint32_t min_scanlines = 8;
3099 uint8_t plane_bpp;
3100
3101 if (WARN_ON(!fb))
3102 return 0;
3103
3104 /* For packed formats, no y-plane, return 0 */
3105 if (y && fb->pixel_format != DRM_FORMAT_NV12)
3106 return 0;
3107
3108 /* For Non Y-tile return 8-blocks */
3109 if (fb->modifier[0] != I915_FORMAT_MOD_Y_TILED &&
3110 fb->modifier[0] != I915_FORMAT_MOD_Yf_TILED)
3111 return 8;
3112
3113 src_w = drm_rect_width(&intel_pstate->src) >> 16;
3114 src_h = drm_rect_height(&intel_pstate->src) >> 16;
3115
3116 if (intel_rotation_90_or_270(pstate->rotation))
3117 swap(src_w, src_h);
3118
3119 /* Halve UV plane width and height for NV12 */
3120 if (fb->pixel_format == DRM_FORMAT_NV12 && !y) {
3121 src_w /= 2;
3122 src_h /= 2;
3123 }
3124
3125 if (fb->pixel_format == DRM_FORMAT_NV12 && !y)
3126 plane_bpp = drm_format_plane_cpp(fb->pixel_format, 1);
3127 else
3128 plane_bpp = drm_format_plane_cpp(fb->pixel_format, 0);
3129
3130 if (intel_rotation_90_or_270(pstate->rotation)) {
3131 switch (plane_bpp) {
3132 case 1:
3133 min_scanlines = 32;
3134 break;
3135 case 2:
3136 min_scanlines = 16;
3137 break;
3138 case 4:
3139 min_scanlines = 8;
3140 break;
3141 case 8:
3142 min_scanlines = 4;
3143 break;
3144 default:
3145 WARN(1, "Unsupported pixel depth %u for rotation",
3146 plane_bpp);
3147 min_scanlines = 32;
3148 }
3149 }
3150
3151 return DIV_ROUND_UP((4 * src_w * plane_bpp), 512) * min_scanlines/4 + 3;
3152 }
3153
3154 static int
3155 skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
3156 struct skl_ddb_allocation *ddb /* out */)
3157 {
3158 struct drm_atomic_state *state = cstate->base.state;
3159 struct drm_crtc *crtc = cstate->base.crtc;
3160 struct drm_device *dev = crtc->dev;
3161 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3162 struct intel_plane *intel_plane;
3163 struct drm_plane *plane;
3164 struct drm_plane_state *pstate;
3165 enum pipe pipe = intel_crtc->pipe;
3166 struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
3167 uint16_t alloc_size, start, cursor_blocks;
3168 uint16_t *minimum = cstate->wm.skl.minimum_blocks;
3169 uint16_t *y_minimum = cstate->wm.skl.minimum_y_blocks;
3170 unsigned int total_data_rate;
3171 int num_active;
3172 int id, i;
3173
3174 if (WARN_ON(!state))
3175 return 0;
3176
3177 if (!cstate->base.active) {
3178 ddb->pipe[pipe].start = ddb->pipe[pipe].end = 0;
3179 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3180 memset(ddb->y_plane[pipe], 0, sizeof(ddb->y_plane[pipe]));
3181 return 0;
3182 }
3183
3184 skl_ddb_get_pipe_allocation_limits(dev, cstate, alloc, &num_active);
3185 alloc_size = skl_ddb_entry_size(alloc);
3186 if (alloc_size == 0) {
3187 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3188 return 0;
3189 }
3190
3191 cursor_blocks = skl_cursor_allocation(num_active);
3192 ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks;
3193 ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
3194
3195 alloc_size -= cursor_blocks;
3196
3197 /* 1. Allocate the mininum required blocks for each active plane */
3198 for_each_plane_in_state(state, plane, pstate, i) {
3199 intel_plane = to_intel_plane(plane);
3200 id = skl_wm_plane_id(intel_plane);
3201
3202 if (intel_plane->pipe != pipe)
3203 continue;
3204
3205 if (!to_intel_plane_state(pstate)->visible) {
3206 minimum[id] = 0;
3207 y_minimum[id] = 0;
3208 continue;
3209 }
3210 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
3211 minimum[id] = 0;
3212 y_minimum[id] = 0;
3213 continue;
3214 }
3215
3216 minimum[id] = skl_ddb_min_alloc(pstate, 0);
3217 y_minimum[id] = skl_ddb_min_alloc(pstate, 1);
3218 }
3219
3220 for (i = 0; i < PLANE_CURSOR; i++) {
3221 alloc_size -= minimum[i];
3222 alloc_size -= y_minimum[i];
3223 }
3224
3225 /*
3226 * 2. Distribute the remaining space in proportion to the amount of
3227 * data each plane needs to fetch from memory.
3228 *
3229 * FIXME: we may not allocate every single block here.
3230 */
3231 total_data_rate = skl_get_total_relative_data_rate(cstate);
3232 if (total_data_rate == 0)
3233 return 0;
3234
3235 start = alloc->start;
3236 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3237 unsigned int data_rate, y_data_rate;
3238 uint16_t plane_blocks, y_plane_blocks = 0;
3239 int id = skl_wm_plane_id(intel_plane);
3240
3241 data_rate = cstate->wm.skl.plane_data_rate[id];
3242
3243 /*
3244 * allocation for (packed formats) or (uv-plane part of planar format):
3245 * promote the expression to 64 bits to avoid overflowing, the
3246 * result is < available as data_rate / total_data_rate < 1
3247 */
3248 plane_blocks = minimum[id];
3249 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3250 total_data_rate);
3251
3252 /* Leave disabled planes at (0,0) */
3253 if (data_rate) {
3254 ddb->plane[pipe][id].start = start;
3255 ddb->plane[pipe][id].end = start + plane_blocks;
3256 }
3257
3258 start += plane_blocks;
3259
3260 /*
3261 * allocation for y_plane part of planar format:
3262 */
3263 y_data_rate = cstate->wm.skl.plane_y_data_rate[id];
3264
3265 y_plane_blocks = y_minimum[id];
3266 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3267 total_data_rate);
3268
3269 if (y_data_rate) {
3270 ddb->y_plane[pipe][id].start = start;
3271 ddb->y_plane[pipe][id].end = start + y_plane_blocks;
3272 }
3273
3274 start += y_plane_blocks;
3275 }
3276
3277 return 0;
3278 }
3279
3280 static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
3281 {
3282 /* TODO: Take into account the scalers once we support them */
3283 return config->base.adjusted_mode.crtc_clock;
3284 }
3285
3286 /*
3287 * The max latency should be 257 (max the punit can code is 255 and we add 2us
3288 * for the read latency) and cpp should always be <= 8, so that
3289 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3290 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3291 */
3292 static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
3293 {
3294 uint32_t wm_intermediate_val, ret;
3295
3296 if (latency == 0)
3297 return UINT_MAX;
3298
3299 wm_intermediate_val = latency * pixel_rate * cpp / 512;
3300 ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3301
3302 return ret;
3303 }
3304
3305 static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
3306 uint32_t horiz_pixels, uint8_t cpp,
3307 uint64_t tiling, uint32_t latency)
3308 {
3309 uint32_t ret;
3310 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3311 uint32_t wm_intermediate_val;
3312
3313 if (latency == 0)
3314 return UINT_MAX;
3315
3316 plane_bytes_per_line = horiz_pixels * cpp;
3317
3318 if (tiling == I915_FORMAT_MOD_Y_TILED ||
3319 tiling == I915_FORMAT_MOD_Yf_TILED) {
3320 plane_bytes_per_line *= 4;
3321 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3322 plane_blocks_per_line /= 4;
3323 } else {
3324 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3325 }
3326
3327 wm_intermediate_val = latency * pixel_rate;
3328 ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
3329 plane_blocks_per_line;
3330
3331 return ret;
3332 }
3333
3334 static uint32_t skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cstate,
3335 struct intel_plane_state *pstate)
3336 {
3337 uint64_t adjusted_pixel_rate;
3338 uint64_t downscale_amount;
3339 uint64_t pixel_rate;
3340
3341 /* Shouldn't reach here on disabled planes... */
3342 if (WARN_ON(!pstate->visible))
3343 return 0;
3344
3345 /*
3346 * Adjusted plane pixel rate is just the pipe's adjusted pixel rate
3347 * with additional adjustments for plane-specific scaling.
3348 */
3349 adjusted_pixel_rate = skl_pipe_pixel_rate(cstate);
3350 downscale_amount = skl_plane_downscale_amount(pstate);
3351
3352 pixel_rate = adjusted_pixel_rate * downscale_amount >> 16;
3353 WARN_ON(pixel_rate != clamp_t(uint32_t, pixel_rate, 0, ~0));
3354
3355 return pixel_rate;
3356 }
3357
3358 static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3359 struct intel_crtc_state *cstate,
3360 struct intel_plane_state *intel_pstate,
3361 uint16_t ddb_allocation,
3362 int level,
3363 uint16_t *out_blocks, /* out */
3364 uint8_t *out_lines, /* out */
3365 bool *enabled /* out */)
3366 {
3367 struct drm_plane_state *pstate = &intel_pstate->base;
3368 struct drm_framebuffer *fb = pstate->fb;
3369 uint32_t latency = dev_priv->wm.skl_latency[level];
3370 uint32_t method1, method2;
3371 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3372 uint32_t res_blocks, res_lines;
3373 uint32_t selected_result;
3374 uint8_t cpp;
3375 uint32_t width = 0, height = 0;
3376 uint32_t plane_pixel_rate;
3377
3378 if (latency == 0 || !cstate->base.active || !intel_pstate->visible) {
3379 *enabled = false;
3380 return 0;
3381 }
3382
3383 width = drm_rect_width(&intel_pstate->src) >> 16;
3384 height = drm_rect_height(&intel_pstate->src) >> 16;
3385
3386 if (intel_rotation_90_or_270(pstate->rotation))
3387 swap(width, height);
3388
3389 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
3390 plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate, intel_pstate);
3391
3392 method1 = skl_wm_method1(plane_pixel_rate, cpp, latency);
3393 method2 = skl_wm_method2(plane_pixel_rate,
3394 cstate->base.adjusted_mode.crtc_htotal,
3395 width,
3396 cpp,
3397 fb->modifier[0],
3398 latency);
3399
3400 plane_bytes_per_line = width * cpp;
3401 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3402
3403 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3404 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
3405 uint32_t min_scanlines = 4;
3406 uint32_t y_tile_minimum;
3407 if (intel_rotation_90_or_270(pstate->rotation)) {
3408 int cpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
3409 drm_format_plane_cpp(fb->pixel_format, 1) :
3410 drm_format_plane_cpp(fb->pixel_format, 0);
3411
3412 switch (cpp) {
3413 case 1:
3414 min_scanlines = 16;
3415 break;
3416 case 2:
3417 min_scanlines = 8;
3418 break;
3419 case 8:
3420 WARN(1, "Unsupported pixel depth for rotation");
3421 }
3422 }
3423 y_tile_minimum = plane_blocks_per_line * min_scanlines;
3424 selected_result = max(method2, y_tile_minimum);
3425 } else {
3426 if ((ddb_allocation / plane_blocks_per_line) >= 1)
3427 selected_result = min(method1, method2);
3428 else
3429 selected_result = method1;
3430 }
3431
3432 res_blocks = selected_result + 1;
3433 res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
3434
3435 if (level >= 1 && level <= 7) {
3436 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3437 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED)
3438 res_lines += 4;
3439 else
3440 res_blocks++;
3441 }
3442
3443 if (res_blocks >= ddb_allocation || res_lines > 31) {
3444 *enabled = false;
3445
3446 /*
3447 * If there are no valid level 0 watermarks, then we can't
3448 * support this display configuration.
3449 */
3450 if (level) {
3451 return 0;
3452 } else {
3453 DRM_DEBUG_KMS("Requested display configuration exceeds system watermark limitations\n");
3454 DRM_DEBUG_KMS("Plane %d.%d: blocks required = %u/%u, lines required = %u/31\n",
3455 to_intel_crtc(cstate->base.crtc)->pipe,
3456 skl_wm_plane_id(to_intel_plane(pstate->plane)),
3457 res_blocks, ddb_allocation, res_lines);
3458
3459 return -EINVAL;
3460 }
3461 }
3462
3463 *out_blocks = res_blocks;
3464 *out_lines = res_lines;
3465 *enabled = true;
3466
3467 return 0;
3468 }
3469
3470 static int
3471 skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3472 struct skl_ddb_allocation *ddb,
3473 struct intel_crtc_state *cstate,
3474 int level,
3475 struct skl_wm_level *result)
3476 {
3477 struct drm_device *dev = dev_priv->dev;
3478 struct drm_atomic_state *state = cstate->base.state;
3479 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
3480 struct drm_plane *plane;
3481 struct intel_plane *intel_plane;
3482 struct intel_plane_state *intel_pstate;
3483 uint16_t ddb_blocks;
3484 enum pipe pipe = intel_crtc->pipe;
3485 int ret;
3486
3487 /*
3488 * We'll only calculate watermarks for planes that are actually
3489 * enabled, so make sure all other planes are set as disabled.
3490 */
3491 memset(result, 0, sizeof(*result));
3492
3493 for_each_intel_plane_mask(dev, intel_plane, cstate->base.plane_mask) {
3494 int i = skl_wm_plane_id(intel_plane);
3495
3496 plane = &intel_plane->base;
3497 intel_pstate = NULL;
3498 if (state)
3499 intel_pstate =
3500 intel_atomic_get_existing_plane_state(state,
3501 intel_plane);
3502
3503 /*
3504 * Note: If we start supporting multiple pending atomic commits
3505 * against the same planes/CRTC's in the future, plane->state
3506 * will no longer be the correct pre-state to use for the
3507 * calculations here and we'll need to change where we get the
3508 * 'unchanged' plane data from.
3509 *
3510 * For now this is fine because we only allow one queued commit
3511 * against a CRTC. Even if the plane isn't modified by this
3512 * transaction and we don't have a plane lock, we still have
3513 * the CRTC's lock, so we know that no other transactions are
3514 * racing with us to update it.
3515 */
3516 if (!intel_pstate)
3517 intel_pstate = to_intel_plane_state(plane->state);
3518
3519 WARN_ON(!intel_pstate->base.fb);
3520
3521 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3522
3523 ret = skl_compute_plane_wm(dev_priv,
3524 cstate,
3525 intel_pstate,
3526 ddb_blocks,
3527 level,
3528 &result->plane_res_b[i],
3529 &result->plane_res_l[i],
3530 &result->plane_en[i]);
3531 if (ret)
3532 return ret;
3533 }
3534
3535 return 0;
3536 }
3537
3538 static uint32_t
3539 skl_compute_linetime_wm(struct intel_crtc_state *cstate)
3540 {
3541 if (!cstate->base.active)
3542 return 0;
3543
3544 if (WARN_ON(skl_pipe_pixel_rate(cstate) == 0))
3545 return 0;
3546
3547 return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
3548 skl_pipe_pixel_rate(cstate));
3549 }
3550
3551 static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
3552 struct skl_wm_level *trans_wm /* out */)
3553 {
3554 struct drm_crtc *crtc = cstate->base.crtc;
3555 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3556 struct intel_plane *intel_plane;
3557
3558 if (!cstate->base.active)
3559 return;
3560
3561 /* Until we know more, just disable transition WMs */
3562 for_each_intel_plane_on_crtc(crtc->dev, intel_crtc, intel_plane) {
3563 int i = skl_wm_plane_id(intel_plane);
3564
3565 trans_wm->plane_en[i] = false;
3566 }
3567 }
3568
3569 static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
3570 struct skl_ddb_allocation *ddb,
3571 struct skl_pipe_wm *pipe_wm)
3572 {
3573 struct drm_device *dev = cstate->base.crtc->dev;
3574 const struct drm_i915_private *dev_priv = dev->dev_private;
3575 int level, max_level = ilk_wm_max_level(dev);
3576 int ret;
3577
3578 for (level = 0; level <= max_level; level++) {
3579 ret = skl_compute_wm_level(dev_priv, ddb, cstate,
3580 level, &pipe_wm->wm[level]);
3581 if (ret)
3582 return ret;
3583 }
3584 pipe_wm->linetime = skl_compute_linetime_wm(cstate);
3585
3586 skl_compute_transition_wm(cstate, &pipe_wm->trans_wm);
3587
3588 return 0;
3589 }
3590
3591 static void skl_compute_wm_results(struct drm_device *dev,
3592 struct skl_pipe_wm *p_wm,
3593 struct skl_wm_values *r,
3594 struct intel_crtc *intel_crtc)
3595 {
3596 int level, max_level = ilk_wm_max_level(dev);
3597 enum pipe pipe = intel_crtc->pipe;
3598 uint32_t temp;
3599 int i;
3600
3601 for (level = 0; level <= max_level; level++) {
3602 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3603 temp = 0;
3604
3605 temp |= p_wm->wm[level].plane_res_l[i] <<
3606 PLANE_WM_LINES_SHIFT;
3607 temp |= p_wm->wm[level].plane_res_b[i];
3608 if (p_wm->wm[level].plane_en[i])
3609 temp |= PLANE_WM_EN;
3610
3611 r->plane[pipe][i][level] = temp;
3612 }
3613
3614 temp = 0;
3615
3616 temp |= p_wm->wm[level].plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3617 temp |= p_wm->wm[level].plane_res_b[PLANE_CURSOR];
3618
3619 if (p_wm->wm[level].plane_en[PLANE_CURSOR])
3620 temp |= PLANE_WM_EN;
3621
3622 r->plane[pipe][PLANE_CURSOR][level] = temp;
3623
3624 }
3625
3626 /* transition WMs */
3627 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3628 temp = 0;
3629 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3630 temp |= p_wm->trans_wm.plane_res_b[i];
3631 if (p_wm->trans_wm.plane_en[i])
3632 temp |= PLANE_WM_EN;
3633
3634 r->plane_trans[pipe][i] = temp;
3635 }
3636
3637 temp = 0;
3638 temp |= p_wm->trans_wm.plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3639 temp |= p_wm->trans_wm.plane_res_b[PLANE_CURSOR];
3640 if (p_wm->trans_wm.plane_en[PLANE_CURSOR])
3641 temp |= PLANE_WM_EN;
3642
3643 r->plane_trans[pipe][PLANE_CURSOR] = temp;
3644
3645 r->wm_linetime[pipe] = p_wm->linetime;
3646 }
3647
3648 static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
3649 i915_reg_t reg,
3650 const struct skl_ddb_entry *entry)
3651 {
3652 if (entry->end)
3653 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3654 else
3655 I915_WRITE(reg, 0);
3656 }
3657
3658 static void skl_write_wm_values(struct drm_i915_private *dev_priv,
3659 const struct skl_wm_values *new)
3660 {
3661 struct drm_device *dev = dev_priv->dev;
3662 struct intel_crtc *crtc;
3663
3664 for_each_intel_crtc(dev, crtc) {
3665 int i, level, max_level = ilk_wm_max_level(dev);
3666 enum pipe pipe = crtc->pipe;
3667
3668 if ((new->dirty_pipes & drm_crtc_mask(&crtc->base)) == 0)
3669 continue;
3670 if (!crtc->active)
3671 continue;
3672
3673 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]);
3674
3675 for (level = 0; level <= max_level; level++) {
3676 for (i = 0; i < intel_num_planes(crtc); i++)
3677 I915_WRITE(PLANE_WM(pipe, i, level),
3678 new->plane[pipe][i][level]);
3679 I915_WRITE(CUR_WM(pipe, level),
3680 new->plane[pipe][PLANE_CURSOR][level]);
3681 }
3682 for (i = 0; i < intel_num_planes(crtc); i++)
3683 I915_WRITE(PLANE_WM_TRANS(pipe, i),
3684 new->plane_trans[pipe][i]);
3685 I915_WRITE(CUR_WM_TRANS(pipe),
3686 new->plane_trans[pipe][PLANE_CURSOR]);
3687
3688 for (i = 0; i < intel_num_planes(crtc); i++) {
3689 skl_ddb_entry_write(dev_priv,
3690 PLANE_BUF_CFG(pipe, i),
3691 &new->ddb.plane[pipe][i]);
3692 skl_ddb_entry_write(dev_priv,
3693 PLANE_NV12_BUF_CFG(pipe, i),
3694 &new->ddb.y_plane[pipe][i]);
3695 }
3696
3697 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3698 &new->ddb.plane[pipe][PLANE_CURSOR]);
3699 }
3700 }
3701
3702 /*
3703 * When setting up a new DDB allocation arrangement, we need to correctly
3704 * sequence the times at which the new allocations for the pipes are taken into
3705 * account or we'll have pipes fetching from space previously allocated to
3706 * another pipe.
3707 *
3708 * Roughly the sequence looks like:
3709 * 1. re-allocate the pipe(s) with the allocation being reduced and not
3710 * overlapping with a previous light-up pipe (another way to put it is:
3711 * pipes with their new allocation strickly included into their old ones).
3712 * 2. re-allocate the other pipes that get their allocation reduced
3713 * 3. allocate the pipes having their allocation increased
3714 *
3715 * Steps 1. and 2. are here to take care of the following case:
3716 * - Initially DDB looks like this:
3717 * | B | C |
3718 * - enable pipe A.
3719 * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
3720 * allocation
3721 * | A | B | C |
3722 *
3723 * We need to sequence the re-allocation: C, B, A (and not B, C, A).
3724 */
3725
3726 static void
3727 skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass)
3728 {
3729 int plane;
3730
3731 DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);
3732
3733 for_each_plane(dev_priv, pipe, plane) {
3734 I915_WRITE(PLANE_SURF(pipe, plane),
3735 I915_READ(PLANE_SURF(pipe, plane)));
3736 }
3737 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3738 }
3739
3740 static bool
3741 skl_ddb_allocation_included(const struct skl_ddb_allocation *old,
3742 const struct skl_ddb_allocation *new,
3743 enum pipe pipe)
3744 {
3745 uint16_t old_size, new_size;
3746
3747 old_size = skl_ddb_entry_size(&old->pipe[pipe]);
3748 new_size = skl_ddb_entry_size(&new->pipe[pipe]);
3749
3750 return old_size != new_size &&
3751 new->pipe[pipe].start >= old->pipe[pipe].start &&
3752 new->pipe[pipe].end <= old->pipe[pipe].end;
3753 }
3754
3755 static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
3756 struct skl_wm_values *new_values)
3757 {
3758 struct drm_device *dev = dev_priv->dev;
3759 struct skl_ddb_allocation *cur_ddb, *new_ddb;
3760 bool reallocated[I915_MAX_PIPES] = {};
3761 struct intel_crtc *crtc;
3762 enum pipe pipe;
3763
3764 new_ddb = &new_values->ddb;
3765 cur_ddb = &dev_priv->wm.skl_hw.ddb;
3766
3767 /*
3768 * First pass: flush the pipes with the new allocation contained into
3769 * the old space.
3770 *
3771 * We'll wait for the vblank on those pipes to ensure we can safely
3772 * re-allocate the freed space without this pipe fetching from it.
3773 */
3774 for_each_intel_crtc(dev, crtc) {
3775 if (!crtc->active)
3776 continue;
3777
3778 pipe = crtc->pipe;
3779
3780 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))
3781 continue;
3782
3783 skl_wm_flush_pipe(dev_priv, pipe, 1);
3784 intel_wait_for_vblank(dev, pipe);
3785
3786 reallocated[pipe] = true;
3787 }
3788
3789
3790 /*
3791 * Second pass: flush the pipes that are having their allocation
3792 * reduced, but overlapping with a previous allocation.
3793 *
3794 * Here as well we need to wait for the vblank to make sure the freed
3795 * space is not used anymore.
3796 */
3797 for_each_intel_crtc(dev, crtc) {
3798 if (!crtc->active)
3799 continue;
3800
3801 pipe = crtc->pipe;
3802
3803 if (reallocated[pipe])
3804 continue;
3805
3806 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <
3807 skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
3808 skl_wm_flush_pipe(dev_priv, pipe, 2);
3809 intel_wait_for_vblank(dev, pipe);
3810 reallocated[pipe] = true;
3811 }
3812 }
3813
3814 /*
3815 * Third pass: flush the pipes that got more space allocated.
3816 *
3817 * We don't need to actively wait for the update here, next vblank
3818 * will just get more DDB space with the correct WM values.
3819 */
3820 for_each_intel_crtc(dev, crtc) {
3821 if (!crtc->active)
3822 continue;
3823
3824 pipe = crtc->pipe;
3825
3826 /*
3827 * At this point, only the pipes more space than before are
3828 * left to re-allocate.
3829 */
3830 if (reallocated[pipe])
3831 continue;
3832
3833 skl_wm_flush_pipe(dev_priv, pipe, 3);
3834 }
3835 }
3836
3837 static int skl_update_pipe_wm(struct drm_crtc_state *cstate,
3838 struct skl_ddb_allocation *ddb, /* out */
3839 struct skl_pipe_wm *pipe_wm, /* out */
3840 bool *changed /* out */)
3841 {
3842 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->crtc);
3843 struct intel_crtc_state *intel_cstate = to_intel_crtc_state(cstate);
3844 int ret;
3845
3846 ret = skl_build_pipe_wm(intel_cstate, ddb, pipe_wm);
3847 if (ret)
3848 return ret;
3849
3850 if (!memcmp(&intel_crtc->wm.active.skl, pipe_wm, sizeof(*pipe_wm)))
3851 *changed = false;
3852 else
3853 *changed = true;
3854
3855 return 0;
3856 }
3857
3858 static int
3859 skl_compute_ddb(struct drm_atomic_state *state)
3860 {
3861 struct drm_device *dev = state->dev;
3862 struct drm_i915_private *dev_priv = to_i915(dev);
3863 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3864 struct intel_crtc *intel_crtc;
3865 struct skl_ddb_allocation *ddb = &intel_state->wm_results.ddb;
3866 unsigned realloc_pipes = dev_priv->active_crtcs;
3867 int ret;
3868
3869 /*
3870 * If this is our first atomic update following hardware readout,
3871 * we can't trust the DDB that the BIOS programmed for us. Let's
3872 * pretend that all pipes switched active status so that we'll
3873 * ensure a full DDB recompute.
3874 */
3875 if (dev_priv->wm.distrust_bios_wm)
3876 intel_state->active_pipe_changes = ~0;
3877
3878 /*
3879 * If the modeset changes which CRTC's are active, we need to
3880 * recompute the DDB allocation for *all* active pipes, even
3881 * those that weren't otherwise being modified in any way by this
3882 * atomic commit. Due to the shrinking of the per-pipe allocations
3883 * when new active CRTC's are added, it's possible for a pipe that
3884 * we were already using and aren't changing at all here to suddenly
3885 * become invalid if its DDB needs exceeds its new allocation.
3886 *
3887 * Note that if we wind up doing a full DDB recompute, we can't let
3888 * any other display updates race with this transaction, so we need
3889 * to grab the lock on *all* CRTC's.
3890 */
3891 if (intel_state->active_pipe_changes) {
3892 realloc_pipes = ~0;
3893 intel_state->wm_results.dirty_pipes = ~0;
3894 }
3895
3896 for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) {
3897 struct intel_crtc_state *cstate;
3898
3899 cstate = intel_atomic_get_crtc_state(state, intel_crtc);
3900 if (IS_ERR(cstate))
3901 return PTR_ERR(cstate);
3902
3903 ret = skl_allocate_pipe_ddb(cstate, ddb);
3904 if (ret)
3905 return ret;
3906 }
3907
3908 return 0;
3909 }
3910
3911 static int
3912 skl_compute_wm(struct drm_atomic_state *state)
3913 {
3914 struct drm_crtc *crtc;
3915 struct drm_crtc_state *cstate;
3916 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3917 struct skl_wm_values *results = &intel_state->wm_results;
3918 struct skl_pipe_wm *pipe_wm;
3919 bool changed = false;
3920 int ret, i;
3921
3922 /*
3923 * If this transaction isn't actually touching any CRTC's, don't
3924 * bother with watermark calculation. Note that if we pass this
3925 * test, we're guaranteed to hold at least one CRTC state mutex,
3926 * which means we can safely use values like dev_priv->active_crtcs
3927 * since any racing commits that want to update them would need to
3928 * hold _all_ CRTC state mutexes.
3929 */
3930 for_each_crtc_in_state(state, crtc, cstate, i)
3931 changed = true;
3932 if (!changed)
3933 return 0;
3934
3935 /* Clear all dirty flags */
3936 results->dirty_pipes = 0;
3937
3938 ret = skl_compute_ddb(state);
3939 if (ret)
3940 return ret;
3941
3942 /*
3943 * Calculate WM's for all pipes that are part of this transaction.
3944 * Note that the DDB allocation above may have added more CRTC's that
3945 * weren't otherwise being modified (and set bits in dirty_pipes) if
3946 * pipe allocations had to change.
3947 *
3948 * FIXME: Now that we're doing this in the atomic check phase, we
3949 * should allow skl_update_pipe_wm() to return failure in cases where
3950 * no suitable watermark values can be found.
3951 */
3952 for_each_crtc_in_state(state, crtc, cstate, i) {
3953 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3954 struct intel_crtc_state *intel_cstate =
3955 to_intel_crtc_state(cstate);
3956
3957 pipe_wm = &intel_cstate->wm.skl.optimal;
3958 ret = skl_update_pipe_wm(cstate, &results->ddb, pipe_wm,
3959 &changed);
3960 if (ret)
3961 return ret;
3962
3963 if (changed)
3964 results->dirty_pipes |= drm_crtc_mask(crtc);
3965
3966 if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
3967 /* This pipe's WM's did not change */
3968 continue;
3969
3970 intel_cstate->update_wm_pre = true;
3971 skl_compute_wm_results(crtc->dev, pipe_wm, results, intel_crtc);
3972 }
3973
3974 return 0;
3975 }
3976
3977 static void skl_update_wm(struct drm_crtc *crtc)
3978 {
3979 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3980 struct drm_device *dev = crtc->dev;
3981 struct drm_i915_private *dev_priv = dev->dev_private;
3982 struct skl_wm_values *results = &dev_priv->wm.skl_results;
3983 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3984 struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;
3985
3986 if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
3987 return;
3988
3989 intel_crtc->wm.active.skl = *pipe_wm;
3990
3991 mutex_lock(&dev_priv->wm.wm_mutex);
3992
3993 skl_write_wm_values(dev_priv, results);
3994 skl_flush_wm_values(dev_priv, results);
3995
3996 /* store the new configuration */
3997 dev_priv->wm.skl_hw = *results;
3998
3999 mutex_unlock(&dev_priv->wm.wm_mutex);
4000 }
4001
4002 static void ilk_compute_wm_config(struct drm_device *dev,
4003 struct intel_wm_config *config)
4004 {
4005 struct intel_crtc *crtc;
4006
4007 /* Compute the currently _active_ config */
4008 for_each_intel_crtc(dev, crtc) {
4009 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
4010
4011 if (!wm->pipe_enabled)
4012 continue;
4013
4014 config->sprites_enabled |= wm->sprites_enabled;
4015 config->sprites_scaled |= wm->sprites_scaled;
4016 config->num_pipes_active++;
4017 }
4018 }
4019
4020 static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
4021 {
4022 struct drm_device *dev = dev_priv->dev;
4023 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
4024 struct ilk_wm_maximums max;
4025 struct intel_wm_config config = {};
4026 struct ilk_wm_values results = {};
4027 enum intel_ddb_partitioning partitioning;
4028
4029 ilk_compute_wm_config(dev, &config);
4030
4031 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
4032 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
4033
4034 /* 5/6 split only in single pipe config on IVB+ */
4035 if (INTEL_INFO(dev)->gen >= 7 &&
4036 config.num_pipes_active == 1 && config.sprites_enabled) {
4037 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
4038 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
4039
4040 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
4041 } else {
4042 best_lp_wm = &lp_wm_1_2;
4043 }
4044
4045 partitioning = (best_lp_wm == &lp_wm_1_2) ?
4046 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
4047
4048 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
4049
4050 ilk_write_wm_values(dev_priv, &results);
4051 }
4052
4053 static void ilk_initial_watermarks(struct intel_crtc_state *cstate)
4054 {
4055 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4056 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
4057
4058 mutex_lock(&dev_priv->wm.wm_mutex);
4059 intel_crtc->wm.active.ilk = cstate->wm.ilk.intermediate;
4060 ilk_program_watermarks(dev_priv);
4061 mutex_unlock(&dev_priv->wm.wm_mutex);
4062 }
4063
4064 static void ilk_optimize_watermarks(struct intel_crtc_state *cstate)
4065 {
4066 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4067 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
4068
4069 mutex_lock(&dev_priv->wm.wm_mutex);
4070 if (cstate->wm.need_postvbl_update) {
4071 intel_crtc->wm.active.ilk = cstate->wm.ilk.optimal;
4072 ilk_program_watermarks(dev_priv);
4073 }
4074 mutex_unlock(&dev_priv->wm.wm_mutex);
4075 }
4076
4077 static void skl_pipe_wm_active_state(uint32_t val,
4078 struct skl_pipe_wm *active,
4079 bool is_transwm,
4080 bool is_cursor,
4081 int i,
4082 int level)
4083 {
4084 bool is_enabled = (val & PLANE_WM_EN) != 0;
4085
4086 if (!is_transwm) {
4087 if (!is_cursor) {
4088 active->wm[level].plane_en[i] = is_enabled;
4089 active->wm[level].plane_res_b[i] =
4090 val & PLANE_WM_BLOCKS_MASK;
4091 active->wm[level].plane_res_l[i] =
4092 (val >> PLANE_WM_LINES_SHIFT) &
4093 PLANE_WM_LINES_MASK;
4094 } else {
4095 active->wm[level].plane_en[PLANE_CURSOR] = is_enabled;
4096 active->wm[level].plane_res_b[PLANE_CURSOR] =
4097 val & PLANE_WM_BLOCKS_MASK;
4098 active->wm[level].plane_res_l[PLANE_CURSOR] =
4099 (val >> PLANE_WM_LINES_SHIFT) &
4100 PLANE_WM_LINES_MASK;
4101 }
4102 } else {
4103 if (!is_cursor) {
4104 active->trans_wm.plane_en[i] = is_enabled;
4105 active->trans_wm.plane_res_b[i] =
4106 val & PLANE_WM_BLOCKS_MASK;
4107 active->trans_wm.plane_res_l[i] =
4108 (val >> PLANE_WM_LINES_SHIFT) &
4109 PLANE_WM_LINES_MASK;
4110 } else {
4111 active->trans_wm.plane_en[PLANE_CURSOR] = is_enabled;
4112 active->trans_wm.plane_res_b[PLANE_CURSOR] =
4113 val & PLANE_WM_BLOCKS_MASK;
4114 active->trans_wm.plane_res_l[PLANE_CURSOR] =
4115 (val >> PLANE_WM_LINES_SHIFT) &
4116 PLANE_WM_LINES_MASK;
4117 }
4118 }
4119 }
4120
4121 static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
4122 {
4123 struct drm_device *dev = crtc->dev;
4124 struct drm_i915_private *dev_priv = dev->dev_private;
4125 struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
4126 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4127 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
4128 struct skl_pipe_wm *active = &cstate->wm.skl.optimal;
4129 enum pipe pipe = intel_crtc->pipe;
4130 int level, i, max_level;
4131 uint32_t temp;
4132
4133 max_level = ilk_wm_max_level(dev);
4134
4135 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
4136
4137 for (level = 0; level <= max_level; level++) {
4138 for (i = 0; i < intel_num_planes(intel_crtc); i++)
4139 hw->plane[pipe][i][level] =
4140 I915_READ(PLANE_WM(pipe, i, level));
4141 hw->plane[pipe][PLANE_CURSOR][level] = I915_READ(CUR_WM(pipe, level));
4142 }
4143
4144 for (i = 0; i < intel_num_planes(intel_crtc); i++)
4145 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
4146 hw->plane_trans[pipe][PLANE_CURSOR] = I915_READ(CUR_WM_TRANS(pipe));
4147
4148 if (!intel_crtc->active)
4149 return;
4150
4151 hw->dirty_pipes |= drm_crtc_mask(crtc);
4152
4153 active->linetime = hw->wm_linetime[pipe];
4154
4155 for (level = 0; level <= max_level; level++) {
4156 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
4157 temp = hw->plane[pipe][i][level];
4158 skl_pipe_wm_active_state(temp, active, false,
4159 false, i, level);
4160 }
4161 temp = hw->plane[pipe][PLANE_CURSOR][level];
4162 skl_pipe_wm_active_state(temp, active, false, true, i, level);
4163 }
4164
4165 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
4166 temp = hw->plane_trans[pipe][i];
4167 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
4168 }
4169
4170 temp = hw->plane_trans[pipe][PLANE_CURSOR];
4171 skl_pipe_wm_active_state(temp, active, true, true, i, 0);
4172
4173 intel_crtc->wm.active.skl = *active;
4174 }
4175
4176 void skl_wm_get_hw_state(struct drm_device *dev)
4177 {
4178 struct drm_i915_private *dev_priv = dev->dev_private;
4179 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
4180 struct drm_crtc *crtc;
4181
4182 skl_ddb_get_hw_state(dev_priv, ddb);
4183 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
4184 skl_pipe_wm_get_hw_state(crtc);
4185
4186 if (dev_priv->active_crtcs) {
4187 /* Fully recompute DDB on first atomic commit */
4188 dev_priv->wm.distrust_bios_wm = true;
4189 } else {
4190 /* Easy/common case; just sanitize DDB now if everything off */
4191 memset(ddb, 0, sizeof(*ddb));
4192 }
4193 }
4194
4195 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
4196 {
4197 struct drm_device *dev = crtc->dev;
4198 struct drm_i915_private *dev_priv = dev->dev_private;
4199 struct ilk_wm_values *hw = &dev_priv->wm.hw;
4200 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4201 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
4202 struct intel_pipe_wm *active = &cstate->wm.ilk.optimal;
4203 enum pipe pipe = intel_crtc->pipe;
4204 static const i915_reg_t wm0_pipe_reg[] = {
4205 [PIPE_A] = WM0_PIPEA_ILK,
4206 [PIPE_B] = WM0_PIPEB_ILK,
4207 [PIPE_C] = WM0_PIPEC_IVB,
4208 };
4209
4210 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
4211 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4212 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
4213
4214 memset(active, 0, sizeof(*active));
4215
4216 active->pipe_enabled = intel_crtc->active;
4217
4218 if (active->pipe_enabled) {
4219 u32 tmp = hw->wm_pipe[pipe];
4220
4221 /*
4222 * For active pipes LP0 watermark is marked as
4223 * enabled, and LP1+ watermaks as disabled since
4224 * we can't really reverse compute them in case
4225 * multiple pipes are active.
4226 */
4227 active->wm[0].enable = true;
4228 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
4229 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
4230 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
4231 active->linetime = hw->wm_linetime[pipe];
4232 } else {
4233 int level, max_level = ilk_wm_max_level(dev);
4234
4235 /*
4236 * For inactive pipes, all watermark levels
4237 * should be marked as enabled but zeroed,
4238 * which is what we'd compute them to.
4239 */
4240 for (level = 0; level <= max_level; level++)
4241 active->wm[level].enable = true;
4242 }
4243
4244 intel_crtc->wm.active.ilk = *active;
4245 }
4246
4247 #define _FW_WM(value, plane) \
4248 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
4249 #define _FW_WM_VLV(value, plane) \
4250 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
4251
4252 static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
4253 struct vlv_wm_values *wm)
4254 {
4255 enum pipe pipe;
4256 uint32_t tmp;
4257
4258 for_each_pipe(dev_priv, pipe) {
4259 tmp = I915_READ(VLV_DDL(pipe));
4260
4261 wm->ddl[pipe].primary =
4262 (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4263 wm->ddl[pipe].cursor =
4264 (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4265 wm->ddl[pipe].sprite[0] =
4266 (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4267 wm->ddl[pipe].sprite[1] =
4268 (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4269 }
4270
4271 tmp = I915_READ(DSPFW1);
4272 wm->sr.plane = _FW_WM(tmp, SR);
4273 wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
4274 wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
4275 wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
4276
4277 tmp = I915_READ(DSPFW2);
4278 wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
4279 wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
4280 wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
4281
4282 tmp = I915_READ(DSPFW3);
4283 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
4284
4285 if (IS_CHERRYVIEW(dev_priv)) {
4286 tmp = I915_READ(DSPFW7_CHV);
4287 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4288 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4289
4290 tmp = I915_READ(DSPFW8_CHV);
4291 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
4292 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
4293
4294 tmp = I915_READ(DSPFW9_CHV);
4295 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
4296 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
4297
4298 tmp = I915_READ(DSPHOWM);
4299 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4300 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
4301 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
4302 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
4303 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4304 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4305 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4306 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4307 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4308 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4309 } else {
4310 tmp = I915_READ(DSPFW7);
4311 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4312 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4313
4314 tmp = I915_READ(DSPHOWM);
4315 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4316 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4317 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4318 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4319 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4320 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4321 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4322 }
4323 }
4324
4325 #undef _FW_WM
4326 #undef _FW_WM_VLV
4327
4328 void vlv_wm_get_hw_state(struct drm_device *dev)
4329 {
4330 struct drm_i915_private *dev_priv = to_i915(dev);
4331 struct vlv_wm_values *wm = &dev_priv->wm.vlv;
4332 struct intel_plane *plane;
4333 enum pipe pipe;
4334 u32 val;
4335
4336 vlv_read_wm_values(dev_priv, wm);
4337
4338 for_each_intel_plane(dev, plane) {
4339 switch (plane->base.type) {
4340 int sprite;
4341 case DRM_PLANE_TYPE_CURSOR:
4342 plane->wm.fifo_size = 63;
4343 break;
4344 case DRM_PLANE_TYPE_PRIMARY:
4345 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
4346 break;
4347 case DRM_PLANE_TYPE_OVERLAY:
4348 sprite = plane->plane;
4349 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
4350 break;
4351 }
4352 }
4353
4354 wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4355 wm->level = VLV_WM_LEVEL_PM2;
4356
4357 if (IS_CHERRYVIEW(dev_priv)) {
4358 mutex_lock(&dev_priv->rps.hw_lock);
4359
4360 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4361 if (val & DSP_MAXFIFO_PM5_ENABLE)
4362 wm->level = VLV_WM_LEVEL_PM5;
4363
4364 /*
4365 * If DDR DVFS is disabled in the BIOS, Punit
4366 * will never ack the request. So if that happens
4367 * assume we don't have to enable/disable DDR DVFS
4368 * dynamically. To test that just set the REQ_ACK
4369 * bit to poke the Punit, but don't change the
4370 * HIGH/LOW bits so that we don't actually change
4371 * the current state.
4372 */
4373 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4374 val |= FORCE_DDR_FREQ_REQ_ACK;
4375 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
4376
4377 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
4378 FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
4379 DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4380 "assuming DDR DVFS is disabled\n");
4381 dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
4382 } else {
4383 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4384 if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4385 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4386 }
4387
4388 mutex_unlock(&dev_priv->rps.hw_lock);
4389 }
4390
4391 for_each_pipe(dev_priv, pipe)
4392 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4393 pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4394 wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4395
4396 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4397 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4398 }
4399
4400 void ilk_wm_get_hw_state(struct drm_device *dev)
4401 {
4402 struct drm_i915_private *dev_priv = dev->dev_private;
4403 struct ilk_wm_values *hw = &dev_priv->wm.hw;
4404 struct drm_crtc *crtc;
4405
4406 for_each_crtc(dev, crtc)
4407 ilk_pipe_wm_get_hw_state(crtc);
4408
4409 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4410 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4411 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4412
4413 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
4414 if (INTEL_INFO(dev)->gen >= 7) {
4415 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4416 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4417 }
4418
4419 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4420 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4421 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4422 else if (IS_IVYBRIDGE(dev))
4423 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4424 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4425
4426 hw->enable_fbc_wm =
4427 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4428 }
4429
4430 /**
4431 * intel_update_watermarks - update FIFO watermark values based on current modes
4432 *
4433 * Calculate watermark values for the various WM regs based on current mode
4434 * and plane configuration.
4435 *
4436 * There are several cases to deal with here:
4437 * - normal (i.e. non-self-refresh)
4438 * - self-refresh (SR) mode
4439 * - lines are large relative to FIFO size (buffer can hold up to 2)
4440 * - lines are small relative to FIFO size (buffer can hold more than 2
4441 * lines), so need to account for TLB latency
4442 *
4443 * The normal calculation is:
4444 * watermark = dotclock * bytes per pixel * latency
4445 * where latency is platform & configuration dependent (we assume pessimal
4446 * values here).
4447 *
4448 * The SR calculation is:
4449 * watermark = (trunc(latency/line time)+1) * surface width *
4450 * bytes per pixel
4451 * where
4452 * line time = htotal / dotclock
4453 * surface width = hdisplay for normal plane and 64 for cursor
4454 * and latency is assumed to be high, as above.
4455 *
4456 * The final value programmed to the register should always be rounded up,
4457 * and include an extra 2 entries to account for clock crossings.
4458 *
4459 * We don't use the sprite, so we can ignore that. And on Crestline we have
4460 * to set the non-SR watermarks to 8.
4461 */
4462 void intel_update_watermarks(struct drm_crtc *crtc)
4463 {
4464 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4465
4466 if (dev_priv->display.update_wm)
4467 dev_priv->display.update_wm(crtc);
4468 }
4469
4470 /*
4471 * Lock protecting IPS related data structures
4472 */
4473 DEFINE_SPINLOCK(mchdev_lock);
4474
4475 /* Global for IPS driver to get at the current i915 device. Protected by
4476 * mchdev_lock. */
4477 static struct drm_i915_private *i915_mch_dev;
4478
4479 bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val)
4480 {
4481 u16 rgvswctl;
4482
4483 assert_spin_locked(&mchdev_lock);
4484
4485 rgvswctl = I915_READ16(MEMSWCTL);
4486 if (rgvswctl & MEMCTL_CMD_STS) {
4487 DRM_DEBUG("gpu busy, RCS change rejected\n");
4488 return false; /* still busy with another command */
4489 }
4490
4491 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4492 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4493 I915_WRITE16(MEMSWCTL, rgvswctl);
4494 POSTING_READ16(MEMSWCTL);
4495
4496 rgvswctl |= MEMCTL_CMD_STS;
4497 I915_WRITE16(MEMSWCTL, rgvswctl);
4498
4499 return true;
4500 }
4501
4502 static void ironlake_enable_drps(struct drm_i915_private *dev_priv)
4503 {
4504 u32 rgvmodectl;
4505 u8 fmax, fmin, fstart, vstart;
4506
4507 spin_lock_irq(&mchdev_lock);
4508
4509 rgvmodectl = I915_READ(MEMMODECTL);
4510
4511 /* Enable temp reporting */
4512 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4513 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4514
4515 /* 100ms RC evaluation intervals */
4516 I915_WRITE(RCUPEI, 100000);
4517 I915_WRITE(RCDNEI, 100000);
4518
4519 /* Set max/min thresholds to 90ms and 80ms respectively */
4520 I915_WRITE(RCBMAXAVG, 90000);
4521 I915_WRITE(RCBMINAVG, 80000);
4522
4523 I915_WRITE(MEMIHYST, 1);
4524
4525 /* Set up min, max, and cur for interrupt handling */
4526 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4527 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4528 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4529 MEMMODE_FSTART_SHIFT;
4530
4531 vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
4532 PXVFREQ_PX_SHIFT;
4533
4534 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4535 dev_priv->ips.fstart = fstart;
4536
4537 dev_priv->ips.max_delay = fstart;
4538 dev_priv->ips.min_delay = fmin;
4539 dev_priv->ips.cur_delay = fstart;
4540
4541 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4542 fmax, fmin, fstart);
4543
4544 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4545
4546 /*
4547 * Interrupts will be enabled in ironlake_irq_postinstall
4548 */
4549
4550 I915_WRITE(VIDSTART, vstart);
4551 POSTING_READ(VIDSTART);
4552
4553 rgvmodectl |= MEMMODE_SWMODE_EN;
4554 I915_WRITE(MEMMODECTL, rgvmodectl);
4555
4556 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
4557 DRM_ERROR("stuck trying to change perf mode\n");
4558 mdelay(1);
4559
4560 ironlake_set_drps(dev_priv, fstart);
4561
4562 dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4563 I915_READ(DDREC) + I915_READ(CSIEC);
4564 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
4565 dev_priv->ips.last_count2 = I915_READ(GFXEC);
4566 dev_priv->ips.last_time2 = ktime_get_raw_ns();
4567
4568 spin_unlock_irq(&mchdev_lock);
4569 }
4570
4571 static void ironlake_disable_drps(struct drm_i915_private *dev_priv)
4572 {
4573 u16 rgvswctl;
4574
4575 spin_lock_irq(&mchdev_lock);
4576
4577 rgvswctl = I915_READ16(MEMSWCTL);
4578
4579 /* Ack interrupts, disable EFC interrupt */
4580 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4581 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4582 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4583 I915_WRITE(DEIIR, DE_PCU_EVENT);
4584 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4585
4586 /* Go back to the starting frequency */
4587 ironlake_set_drps(dev_priv, dev_priv->ips.fstart);
4588 mdelay(1);
4589 rgvswctl |= MEMCTL_CMD_STS;
4590 I915_WRITE(MEMSWCTL, rgvswctl);
4591 mdelay(1);
4592
4593 spin_unlock_irq(&mchdev_lock);
4594 }
4595
4596 /* There's a funny hw issue where the hw returns all 0 when reading from
4597 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4598 * ourselves, instead of doing a rmw cycle (which might result in us clearing
4599 * all limits and the gpu stuck at whatever frequency it is at atm).
4600 */
4601 static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
4602 {
4603 u32 limits;
4604
4605 /* Only set the down limit when we've reached the lowest level to avoid
4606 * getting more interrupts, otherwise leave this clear. This prevents a
4607 * race in the hw when coming out of rc6: There's a tiny window where
4608 * the hw runs at the minimal clock before selecting the desired
4609 * frequency, if the down threshold expires in that window we will not
4610 * receive a down interrupt. */
4611 if (IS_GEN9(dev_priv)) {
4612 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4613 if (val <= dev_priv->rps.min_freq_softlimit)
4614 limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4615 } else {
4616 limits = dev_priv->rps.max_freq_softlimit << 24;
4617 if (val <= dev_priv->rps.min_freq_softlimit)
4618 limits |= dev_priv->rps.min_freq_softlimit << 16;
4619 }
4620
4621 return limits;
4622 }
4623
4624 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4625 {
4626 int new_power;
4627 u32 threshold_up = 0, threshold_down = 0; /* in % */
4628 u32 ei_up = 0, ei_down = 0;
4629
4630 new_power = dev_priv->rps.power;
4631 switch (dev_priv->rps.power) {
4632 case LOW_POWER:
4633 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
4634 new_power = BETWEEN;
4635 break;
4636
4637 case BETWEEN:
4638 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
4639 new_power = LOW_POWER;
4640 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
4641 new_power = HIGH_POWER;
4642 break;
4643
4644 case HIGH_POWER:
4645 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
4646 new_power = BETWEEN;
4647 break;
4648 }
4649 /* Max/min bins are special */
4650 if (val <= dev_priv->rps.min_freq_softlimit)
4651 new_power = LOW_POWER;
4652 if (val >= dev_priv->rps.max_freq_softlimit)
4653 new_power = HIGH_POWER;
4654 if (new_power == dev_priv->rps.power)
4655 return;
4656
4657 /* Note the units here are not exactly 1us, but 1280ns. */
4658 switch (new_power) {
4659 case LOW_POWER:
4660 /* Upclock if more than 95% busy over 16ms */
4661 ei_up = 16000;
4662 threshold_up = 95;
4663
4664 /* Downclock if less than 85% busy over 32ms */
4665 ei_down = 32000;
4666 threshold_down = 85;
4667 break;
4668
4669 case BETWEEN:
4670 /* Upclock if more than 90% busy over 13ms */
4671 ei_up = 13000;
4672 threshold_up = 90;
4673
4674 /* Downclock if less than 75% busy over 32ms */
4675 ei_down = 32000;
4676 threshold_down = 75;
4677 break;
4678
4679 case HIGH_POWER:
4680 /* Upclock if more than 85% busy over 10ms */
4681 ei_up = 10000;
4682 threshold_up = 85;
4683
4684 /* Downclock if less than 60% busy over 32ms */
4685 ei_down = 32000;
4686 threshold_down = 60;
4687 break;
4688 }
4689
4690 I915_WRITE(GEN6_RP_UP_EI,
4691 GT_INTERVAL_FROM_US(dev_priv, ei_up));
4692 I915_WRITE(GEN6_RP_UP_THRESHOLD,
4693 GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100)));
4694
4695 I915_WRITE(GEN6_RP_DOWN_EI,
4696 GT_INTERVAL_FROM_US(dev_priv, ei_down));
4697 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4698 GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100)));
4699
4700 I915_WRITE(GEN6_RP_CONTROL,
4701 GEN6_RP_MEDIA_TURBO |
4702 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4703 GEN6_RP_MEDIA_IS_GFX |
4704 GEN6_RP_ENABLE |
4705 GEN6_RP_UP_BUSY_AVG |
4706 GEN6_RP_DOWN_IDLE_AVG);
4707
4708 dev_priv->rps.power = new_power;
4709 dev_priv->rps.up_threshold = threshold_up;
4710 dev_priv->rps.down_threshold = threshold_down;
4711 dev_priv->rps.last_adj = 0;
4712 }
4713
4714 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4715 {
4716 u32 mask = 0;
4717
4718 if (val > dev_priv->rps.min_freq_softlimit)
4719 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
4720 if (val < dev_priv->rps.max_freq_softlimit)
4721 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
4722
4723 mask &= dev_priv->pm_rps_events;
4724
4725 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
4726 }
4727
4728 /* gen6_set_rps is called to update the frequency request, but should also be
4729 * called when the range (min_delay and max_delay) is modified so that we can
4730 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
4731 static void gen6_set_rps(struct drm_i915_private *dev_priv, u8 val)
4732 {
4733 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4734 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
4735 return;
4736
4737 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4738 WARN_ON(val > dev_priv->rps.max_freq);
4739 WARN_ON(val < dev_priv->rps.min_freq);
4740
4741 /* min/max delay may still have been modified so be sure to
4742 * write the limits value.
4743 */
4744 if (val != dev_priv->rps.cur_freq) {
4745 gen6_set_rps_thresholds(dev_priv, val);
4746
4747 if (IS_GEN9(dev_priv))
4748 I915_WRITE(GEN6_RPNSWREQ,
4749 GEN9_FREQUENCY(val));
4750 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
4751 I915_WRITE(GEN6_RPNSWREQ,
4752 HSW_FREQUENCY(val));
4753 else
4754 I915_WRITE(GEN6_RPNSWREQ,
4755 GEN6_FREQUENCY(val) |
4756 GEN6_OFFSET(0) |
4757 GEN6_AGGRESSIVE_TURBO);
4758 }
4759
4760 /* Make sure we continue to get interrupts
4761 * until we hit the minimum or maximum frequencies.
4762 */
4763 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
4764 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4765
4766 POSTING_READ(GEN6_RPNSWREQ);
4767
4768 dev_priv->rps.cur_freq = val;
4769 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4770 }
4771
4772 static void valleyview_set_rps(struct drm_i915_private *dev_priv, u8 val)
4773 {
4774 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4775 WARN_ON(val > dev_priv->rps.max_freq);
4776 WARN_ON(val < dev_priv->rps.min_freq);
4777
4778 if (WARN_ONCE(IS_CHERRYVIEW(dev_priv) && (val & 1),
4779 "Odd GPU freq value\n"))
4780 val &= ~1;
4781
4782 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4783
4784 if (val != dev_priv->rps.cur_freq) {
4785 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
4786 if (!IS_CHERRYVIEW(dev_priv))
4787 gen6_set_rps_thresholds(dev_priv, val);
4788 }
4789
4790 dev_priv->rps.cur_freq = val;
4791 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4792 }
4793
4794 /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
4795 *
4796 * * If Gfx is Idle, then
4797 * 1. Forcewake Media well.
4798 * 2. Request idle freq.
4799 * 3. Release Forcewake of Media well.
4800 */
4801 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4802 {
4803 u32 val = dev_priv->rps.idle_freq;
4804
4805 if (dev_priv->rps.cur_freq <= val)
4806 return;
4807
4808 /* Wake up the media well, as that takes a lot less
4809 * power than the Render well. */
4810 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
4811 valleyview_set_rps(dev_priv, val);
4812 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
4813 }
4814
4815 void gen6_rps_busy(struct drm_i915_private *dev_priv)
4816 {
4817 mutex_lock(&dev_priv->rps.hw_lock);
4818 if (dev_priv->rps.enabled) {
4819 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
4820 gen6_rps_reset_ei(dev_priv);
4821 I915_WRITE(GEN6_PMINTRMSK,
4822 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
4823 }
4824 mutex_unlock(&dev_priv->rps.hw_lock);
4825 }
4826
4827 void gen6_rps_idle(struct drm_i915_private *dev_priv)
4828 {
4829 mutex_lock(&dev_priv->rps.hw_lock);
4830 if (dev_priv->rps.enabled) {
4831 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4832 vlv_set_rps_idle(dev_priv);
4833 else
4834 gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
4835 dev_priv->rps.last_adj = 0;
4836 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
4837 }
4838 mutex_unlock(&dev_priv->rps.hw_lock);
4839
4840 spin_lock(&dev_priv->rps.client_lock);
4841 while (!list_empty(&dev_priv->rps.clients))
4842 list_del_init(dev_priv->rps.clients.next);
4843 spin_unlock(&dev_priv->rps.client_lock);
4844 }
4845
4846 void gen6_rps_boost(struct drm_i915_private *dev_priv,
4847 struct intel_rps_client *rps,
4848 unsigned long submitted)
4849 {
4850 /* This is intentionally racy! We peek at the state here, then
4851 * validate inside the RPS worker.
4852 */
4853 if (!(dev_priv->mm.busy &&
4854 dev_priv->rps.enabled &&
4855 dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit))
4856 return;
4857
4858 /* Force a RPS boost (and don't count it against the client) if
4859 * the GPU is severely congested.
4860 */
4861 if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
4862 rps = NULL;
4863
4864 spin_lock(&dev_priv->rps.client_lock);
4865 if (rps == NULL || list_empty(&rps->link)) {
4866 spin_lock_irq(&dev_priv->irq_lock);
4867 if (dev_priv->rps.interrupts_enabled) {
4868 dev_priv->rps.client_boost = true;
4869 queue_work(dev_priv->wq, &dev_priv->rps.work);
4870 }
4871 spin_unlock_irq(&dev_priv->irq_lock);
4872
4873 if (rps != NULL) {
4874 list_add(&rps->link, &dev_priv->rps.clients);
4875 rps->boosts++;
4876 } else
4877 dev_priv->rps.boosts++;
4878 }
4879 spin_unlock(&dev_priv->rps.client_lock);
4880 }
4881
4882 void intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
4883 {
4884 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4885 valleyview_set_rps(dev_priv, val);
4886 else
4887 gen6_set_rps(dev_priv, val);
4888 }
4889
4890 static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
4891 {
4892 I915_WRITE(GEN6_RC_CONTROL, 0);
4893 I915_WRITE(GEN9_PG_ENABLE, 0);
4894 }
4895
4896 static void gen9_disable_rps(struct drm_i915_private *dev_priv)
4897 {
4898 I915_WRITE(GEN6_RP_CONTROL, 0);
4899 }
4900
4901 static void gen6_disable_rps(struct drm_i915_private *dev_priv)
4902 {
4903 I915_WRITE(GEN6_RC_CONTROL, 0);
4904 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
4905 I915_WRITE(GEN6_RP_CONTROL, 0);
4906 }
4907
4908 static void cherryview_disable_rps(struct drm_i915_private *dev_priv)
4909 {
4910 I915_WRITE(GEN6_RC_CONTROL, 0);
4911 }
4912
4913 static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
4914 {
4915 /* we're doing forcewake before Disabling RC6,
4916 * This what the BIOS expects when going into suspend */
4917 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4918
4919 I915_WRITE(GEN6_RC_CONTROL, 0);
4920
4921 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4922 }
4923
4924 static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode)
4925 {
4926 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
4927 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
4928 mode = GEN6_RC_CTL_RC6_ENABLE;
4929 else
4930 mode = 0;
4931 }
4932 if (HAS_RC6p(dev_priv))
4933 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
4934 onoff(mode & GEN6_RC_CTL_RC6_ENABLE),
4935 onoff(mode & GEN6_RC_CTL_RC6p_ENABLE),
4936 onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE));
4937
4938 else
4939 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
4940 onoff(mode & GEN6_RC_CTL_RC6_ENABLE));
4941 }
4942
4943 static bool bxt_check_bios_rc6_setup(struct drm_i915_private *dev_priv)
4944 {
4945 struct i915_ggtt *ggtt = &dev_priv->ggtt;
4946 bool enable_rc6 = true;
4947 unsigned long rc6_ctx_base;
4948
4949 if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
4950 DRM_DEBUG_KMS("RC6 Base location not set properly.\n");
4951 enable_rc6 = false;
4952 }
4953
4954 /*
4955 * The exact context size is not known for BXT, so assume a page size
4956 * for this check.
4957 */
4958 rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
4959 if (!((rc6_ctx_base >= ggtt->stolen_reserved_base) &&
4960 (rc6_ctx_base + PAGE_SIZE <= ggtt->stolen_reserved_base +
4961 ggtt->stolen_reserved_size))) {
4962 DRM_DEBUG_KMS("RC6 Base address not as expected.\n");
4963 enable_rc6 = false;
4964 }
4965
4966 if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) &&
4967 ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) &&
4968 ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) &&
4969 ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) {
4970 DRM_DEBUG_KMS("Engine Idle wait time not set properly.\n");
4971 enable_rc6 = false;
4972 }
4973
4974 if (!(I915_READ(GEN6_RC_CONTROL) & (GEN6_RC_CTL_RC6_ENABLE |
4975 GEN6_RC_CTL_HW_ENABLE)) &&
4976 ((I915_READ(GEN6_RC_CONTROL) & GEN6_RC_CTL_HW_ENABLE) ||
4977 !(I915_READ(GEN6_RC_STATE) & RC6_STATE))) {
4978 DRM_DEBUG_KMS("HW/SW RC6 is not enabled by BIOS.\n");
4979 enable_rc6 = false;
4980 }
4981
4982 return enable_rc6;
4983 }
4984
4985 int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6)
4986 {
4987 /* No RC6 before Ironlake and code is gone for ilk. */
4988 if (INTEL_INFO(dev_priv)->gen < 6)
4989 return 0;
4990
4991 if (!enable_rc6)
4992 return 0;
4993
4994 if (IS_BROXTON(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) {
4995 DRM_INFO("RC6 disabled by BIOS\n");
4996 return 0;
4997 }
4998
4999 /* Respect the kernel parameter if it is set */
5000 if (enable_rc6 >= 0) {
5001 int mask;
5002
5003 if (HAS_RC6p(dev_priv))
5004 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
5005 INTEL_RC6pp_ENABLE;
5006 else
5007 mask = INTEL_RC6_ENABLE;
5008
5009 if ((enable_rc6 & mask) != enable_rc6)
5010 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
5011 enable_rc6 & mask, enable_rc6, mask);
5012
5013 return enable_rc6 & mask;
5014 }
5015
5016 if (IS_IVYBRIDGE(dev_priv))
5017 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
5018
5019 return INTEL_RC6_ENABLE;
5020 }
5021
5022 static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
5023 {
5024 uint32_t rp_state_cap;
5025 u32 ddcc_status = 0;
5026 int ret;
5027
5028 /* All of these values are in units of 50MHz */
5029 dev_priv->rps.cur_freq = 0;
5030 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
5031 if (IS_BROXTON(dev_priv)) {
5032 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
5033 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
5034 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
5035 dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff;
5036 } else {
5037 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
5038 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
5039 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
5040 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
5041 }
5042
5043 /* hw_max = RP0 until we check for overclocking */
5044 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
5045
5046 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
5047 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
5048 IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5049 ret = sandybridge_pcode_read(dev_priv,
5050 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
5051 &ddcc_status);
5052 if (0 == ret)
5053 dev_priv->rps.efficient_freq =
5054 clamp_t(u8,
5055 ((ddcc_status >> 8) & 0xff),
5056 dev_priv->rps.min_freq,
5057 dev_priv->rps.max_freq);
5058 }
5059
5060 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5061 /* Store the frequency values in 16.66 MHZ units, which is
5062 the natural hardware unit for SKL */
5063 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
5064 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
5065 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
5066 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
5067 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
5068 }
5069
5070 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5071
5072 /* Preserve min/max settings in case of re-init */
5073 if (dev_priv->rps.max_freq_softlimit == 0)
5074 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5075
5076 if (dev_priv->rps.min_freq_softlimit == 0) {
5077 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5078 dev_priv->rps.min_freq_softlimit =
5079 max_t(int, dev_priv->rps.efficient_freq,
5080 intel_freq_opcode(dev_priv, 450));
5081 else
5082 dev_priv->rps.min_freq_softlimit =
5083 dev_priv->rps.min_freq;
5084 }
5085 }
5086
5087 /* See the Gen9_GT_PM_Programming_Guide doc for the below */
5088 static void gen9_enable_rps(struct drm_i915_private *dev_priv)
5089 {
5090 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5091
5092 gen6_init_rps_frequencies(dev_priv);
5093
5094 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
5095 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
5096 /*
5097 * BIOS could leave the Hw Turbo enabled, so need to explicitly
5098 * clear out the Control register just to avoid inconsitency
5099 * with debugfs interface, which will show Turbo as enabled
5100 * only and that is not expected by the User after adding the
5101 * WaGsvDisableTurbo. Apart from this there is no problem even
5102 * if the Turbo is left enabled in the Control register, as the
5103 * Up/Down interrupts would remain masked.
5104 */
5105 gen9_disable_rps(dev_priv);
5106 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5107 return;
5108 }
5109
5110 /* Program defaults and thresholds for RPS*/
5111 I915_WRITE(GEN6_RC_VIDEO_FREQ,
5112 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
5113
5114 /* 1 second timeout*/
5115 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
5116 GT_INTERVAL_FROM_US(dev_priv, 1000000));
5117
5118 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
5119
5120 /* Leaning on the below call to gen6_set_rps to program/setup the
5121 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
5122 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
5123 dev_priv->rps.power = HIGH_POWER; /* force a reset */
5124 gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
5125
5126 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5127 }
5128
5129 static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
5130 {
5131 struct intel_engine_cs *engine;
5132 uint32_t rc6_mask = 0;
5133
5134 /* 1a: Software RC state - RC0 */
5135 I915_WRITE(GEN6_RC_STATE, 0);
5136
5137 /* 1b: Get forcewake during program sequence. Although the driver
5138 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5139 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5140
5141 /* 2a: Disable RC states. */
5142 I915_WRITE(GEN6_RC_CONTROL, 0);
5143
5144 /* 2b: Program RC6 thresholds.*/
5145
5146 /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
5147 if (IS_SKYLAKE(dev_priv))
5148 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
5149 else
5150 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
5151 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5152 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5153 for_each_engine(engine, dev_priv)
5154 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5155
5156 if (HAS_GUC(dev_priv))
5157 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
5158
5159 I915_WRITE(GEN6_RC_SLEEP, 0);
5160
5161 /* 2c: Program Coarse Power Gating Policies. */
5162 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
5163 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
5164
5165 /* 3a: Enable RC6 */
5166 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
5167 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
5168 DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
5169 /* WaRsUseTimeoutMode */
5170 if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_D0) ||
5171 IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
5172 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
5173 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5174 GEN7_RC_CTL_TO_MODE |
5175 rc6_mask);
5176 } else {
5177 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
5178 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5179 GEN6_RC_CTL_EI_MODE(1) |
5180 rc6_mask);
5181 }
5182
5183 /*
5184 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
5185 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
5186 */
5187 if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
5188 I915_WRITE(GEN9_PG_ENABLE, 0);
5189 else
5190 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
5191 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
5192
5193 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5194 }
5195
5196 static void gen8_enable_rps(struct drm_i915_private *dev_priv)
5197 {
5198 struct intel_engine_cs *engine;
5199 uint32_t rc6_mask = 0;
5200
5201 /* 1a: Software RC state - RC0 */
5202 I915_WRITE(GEN6_RC_STATE, 0);
5203
5204 /* 1c & 1d: Get forcewake during program sequence. Although the driver
5205 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5206 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5207
5208 /* 2a: Disable RC states. */
5209 I915_WRITE(GEN6_RC_CONTROL, 0);
5210
5211 /* Initialize rps frequencies */
5212 gen6_init_rps_frequencies(dev_priv);
5213
5214 /* 2b: Program RC6 thresholds.*/
5215 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5216 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5217 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5218 for_each_engine(engine, dev_priv)
5219 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5220 I915_WRITE(GEN6_RC_SLEEP, 0);
5221 if (IS_BROADWELL(dev_priv))
5222 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
5223 else
5224 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
5225
5226 /* 3: Enable RC6 */
5227 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
5228 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
5229 intel_print_rc6_info(dev_priv, rc6_mask);
5230 if (IS_BROADWELL(dev_priv))
5231 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5232 GEN7_RC_CTL_TO_MODE |
5233 rc6_mask);
5234 else
5235 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5236 GEN6_RC_CTL_EI_MODE(1) |
5237 rc6_mask);
5238
5239 /* 4 Program defaults and thresholds for RPS*/
5240 I915_WRITE(GEN6_RPNSWREQ,
5241 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
5242 I915_WRITE(GEN6_RC_VIDEO_FREQ,
5243 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
5244 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
5245 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
5246
5247 /* Docs recommend 900MHz, and 300 MHz respectively */
5248 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
5249 dev_priv->rps.max_freq_softlimit << 24 |
5250 dev_priv->rps.min_freq_softlimit << 16);
5251
5252 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
5253 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
5254 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
5255 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
5256
5257 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5258
5259 /* 5: Enable RPS */
5260 I915_WRITE(GEN6_RP_CONTROL,
5261 GEN6_RP_MEDIA_TURBO |
5262 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5263 GEN6_RP_MEDIA_IS_GFX |
5264 GEN6_RP_ENABLE |
5265 GEN6_RP_UP_BUSY_AVG |
5266 GEN6_RP_DOWN_IDLE_AVG);
5267
5268 /* 6: Ring frequency + overclocking (our driver does this later */
5269
5270 dev_priv->rps.power = HIGH_POWER; /* force a reset */
5271 gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
5272
5273 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5274 }
5275
5276 static void gen6_enable_rps(struct drm_i915_private *dev_priv)
5277 {
5278 struct intel_engine_cs *engine;
5279 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
5280 u32 gtfifodbg;
5281 int rc6_mode;
5282 int ret;
5283
5284 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5285
5286 /* Here begins a magic sequence of register writes to enable
5287 * auto-downclocking.
5288 *
5289 * Perhaps there might be some value in exposing these to
5290 * userspace...
5291 */
5292 I915_WRITE(GEN6_RC_STATE, 0);
5293
5294 /* Clear the DBG now so we don't confuse earlier errors */
5295 gtfifodbg = I915_READ(GTFIFODBG);
5296 if (gtfifodbg) {
5297 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
5298 I915_WRITE(GTFIFODBG, gtfifodbg);
5299 }
5300
5301 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5302
5303 /* Initialize rps frequencies */
5304 gen6_init_rps_frequencies(dev_priv);
5305
5306 /* disable the counters and set deterministic thresholds */
5307 I915_WRITE(GEN6_RC_CONTROL, 0);
5308
5309 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
5310 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
5311 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
5312 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5313 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5314
5315 for_each_engine(engine, dev_priv)
5316 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5317
5318 I915_WRITE(GEN6_RC_SLEEP, 0);
5319 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
5320 if (IS_IVYBRIDGE(dev_priv))
5321 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
5322 else
5323 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
5324 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
5325 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
5326
5327 /* Check if we are enabling RC6 */
5328 rc6_mode = intel_enable_rc6();
5329 if (rc6_mode & INTEL_RC6_ENABLE)
5330 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
5331
5332 /* We don't use those on Haswell */
5333 if (!IS_HASWELL(dev_priv)) {
5334 if (rc6_mode & INTEL_RC6p_ENABLE)
5335 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
5336
5337 if (rc6_mode & INTEL_RC6pp_ENABLE)
5338 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
5339 }
5340
5341 intel_print_rc6_info(dev_priv, rc6_mask);
5342
5343 I915_WRITE(GEN6_RC_CONTROL,
5344 rc6_mask |
5345 GEN6_RC_CTL_EI_MODE(1) |
5346 GEN6_RC_CTL_HW_ENABLE);
5347
5348 /* Power down if completely idle for over 50ms */
5349 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
5350 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5351
5352 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
5353 if (ret)
5354 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
5355
5356 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
5357 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
5358 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
5359 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
5360 (pcu_mbox & 0xff) * 50);
5361 dev_priv->rps.max_freq = pcu_mbox & 0xff;
5362 }
5363
5364 dev_priv->rps.power = HIGH_POWER; /* force a reset */
5365 gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
5366
5367 rc6vids = 0;
5368 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
5369 if (IS_GEN6(dev_priv) && ret) {
5370 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
5371 } else if (IS_GEN6(dev_priv) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
5372 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5373 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5374 rc6vids &= 0xffff00;
5375 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5376 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5377 if (ret)
5378 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5379 }
5380
5381 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5382 }
5383
5384 static void __gen6_update_ring_freq(struct drm_i915_private *dev_priv)
5385 {
5386 int min_freq = 15;
5387 unsigned int gpu_freq;
5388 unsigned int max_ia_freq, min_ring_freq;
5389 unsigned int max_gpu_freq, min_gpu_freq;
5390 int scaling_factor = 180;
5391 struct cpufreq_policy *policy;
5392
5393 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5394
5395 policy = cpufreq_cpu_get(0);
5396 if (policy) {
5397 max_ia_freq = policy->cpuinfo.max_freq;
5398 cpufreq_cpu_put(policy);
5399 } else {
5400 /*
5401 * Default to measured freq if none found, PCU will ensure we
5402 * don't go over
5403 */
5404 max_ia_freq = tsc_khz;
5405 }
5406
5407 /* Convert from kHz to MHz */
5408 max_ia_freq /= 1000;
5409
5410 min_ring_freq = I915_READ(DCLK) & 0xf;
5411 /* convert DDR frequency from units of 266.6MHz to bandwidth */
5412 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
5413
5414 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5415 /* Convert GT frequency to 50 HZ units */
5416 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5417 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5418 } else {
5419 min_gpu_freq = dev_priv->rps.min_freq;
5420 max_gpu_freq = dev_priv->rps.max_freq;
5421 }
5422
5423 /*
5424 * For each potential GPU frequency, load a ring frequency we'd like
5425 * to use for memory access. We do this by specifying the IA frequency
5426 * the PCU should use as a reference to determine the ring frequency.
5427 */
5428 for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5429 int diff = max_gpu_freq - gpu_freq;
5430 unsigned int ia_freq = 0, ring_freq = 0;
5431
5432 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5433 /*
5434 * ring_freq = 2 * GT. ring_freq is in 100MHz units
5435 * No floor required for ring frequency on SKL.
5436 */
5437 ring_freq = gpu_freq;
5438 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
5439 /* max(2 * GT, DDR). NB: GT is 50MHz units */
5440 ring_freq = max(min_ring_freq, gpu_freq);
5441 } else if (IS_HASWELL(dev_priv)) {
5442 ring_freq = mult_frac(gpu_freq, 5, 4);
5443 ring_freq = max(min_ring_freq, ring_freq);
5444 /* leave ia_freq as the default, chosen by cpufreq */
5445 } else {
5446 /* On older processors, there is no separate ring
5447 * clock domain, so in order to boost the bandwidth
5448 * of the ring, we need to upclock the CPU (ia_freq).
5449 *
5450 * For GPU frequencies less than 750MHz,
5451 * just use the lowest ring freq.
5452 */
5453 if (gpu_freq < min_freq)
5454 ia_freq = 800;
5455 else
5456 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5457 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5458 }
5459
5460 sandybridge_pcode_write(dev_priv,
5461 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
5462 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5463 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5464 gpu_freq);
5465 }
5466 }
5467
5468 void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
5469 {
5470 if (!HAS_CORE_RING_FREQ(dev_priv))
5471 return;
5472
5473 mutex_lock(&dev_priv->rps.hw_lock);
5474 __gen6_update_ring_freq(dev_priv);
5475 mutex_unlock(&dev_priv->rps.hw_lock);
5476 }
5477
5478 static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
5479 {
5480 u32 val, rp0;
5481
5482 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5483
5484 switch (INTEL_INFO(dev_priv)->eu_total) {
5485 case 8:
5486 /* (2 * 4) config */
5487 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5488 break;
5489 case 12:
5490 /* (2 * 6) config */
5491 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5492 break;
5493 case 16:
5494 /* (2 * 8) config */
5495 default:
5496 /* Setting (2 * 8) Min RP0 for any other combination */
5497 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5498 break;
5499 }
5500
5501 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5502
5503 return rp0;
5504 }
5505
5506 static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5507 {
5508 u32 val, rpe;
5509
5510 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5511 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5512
5513 return rpe;
5514 }
5515
5516 static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5517 {
5518 u32 val, rp1;
5519
5520 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5521 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5522
5523 return rp1;
5524 }
5525
5526 static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5527 {
5528 u32 val, rp1;
5529
5530 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5531
5532 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5533
5534 return rp1;
5535 }
5536
5537 static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
5538 {
5539 u32 val, rp0;
5540
5541 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5542
5543 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5544 /* Clamp to max */
5545 rp0 = min_t(u32, rp0, 0xea);
5546
5547 return rp0;
5548 }
5549
5550 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5551 {
5552 u32 val, rpe;
5553
5554 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
5555 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
5556 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
5557 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5558
5559 return rpe;
5560 }
5561
5562 static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
5563 {
5564 u32 val;
5565
5566 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5567 /*
5568 * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
5569 * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
5570 * a BYT-M B0 the above register contains 0xbf. Moreover when setting
5571 * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
5572 * to make sure it matches what Punit accepts.
5573 */
5574 return max_t(u32, val, 0xc0);
5575 }
5576
5577 /* Check that the pctx buffer wasn't move under us. */
5578 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5579 {
5580 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5581
5582 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5583 dev_priv->vlv_pctx->stolen->start);
5584 }
5585
5586
5587 /* Check that the pcbr address is not empty. */
5588 static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5589 {
5590 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5591
5592 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5593 }
5594
5595 static void cherryview_setup_pctx(struct drm_i915_private *dev_priv)
5596 {
5597 struct i915_ggtt *ggtt = &dev_priv->ggtt;
5598 unsigned long pctx_paddr, paddr;
5599 u32 pcbr;
5600 int pctx_size = 32*1024;
5601
5602 pcbr = I915_READ(VLV_PCBR);
5603 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
5604 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5605 paddr = (dev_priv->mm.stolen_base +
5606 (ggtt->stolen_size - pctx_size));
5607
5608 pctx_paddr = (paddr & (~4095));
5609 I915_WRITE(VLV_PCBR, pctx_paddr);
5610 }
5611
5612 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5613 }
5614
5615 static void valleyview_setup_pctx(struct drm_i915_private *dev_priv)
5616 {
5617 struct drm_i915_gem_object *pctx;
5618 unsigned long pctx_paddr;
5619 u32 pcbr;
5620 int pctx_size = 24*1024;
5621
5622 mutex_lock(&dev_priv->dev->struct_mutex);
5623
5624 pcbr = I915_READ(VLV_PCBR);
5625 if (pcbr) {
5626 /* BIOS set it up already, grab the pre-alloc'd space */
5627 int pcbr_offset;
5628
5629 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
5630 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
5631 pcbr_offset,
5632 I915_GTT_OFFSET_NONE,
5633 pctx_size);
5634 goto out;
5635 }
5636
5637 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5638
5639 /*
5640 * From the Gunit register HAS:
5641 * The Gfx driver is expected to program this register and ensure
5642 * proper allocation within Gfx stolen memory. For example, this
5643 * register should be programmed such than the PCBR range does not
5644 * overlap with other ranges, such as the frame buffer, protected
5645 * memory, or any other relevant ranges.
5646 */
5647 pctx = i915_gem_object_create_stolen(dev_priv->dev, pctx_size);
5648 if (!pctx) {
5649 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
5650 goto out;
5651 }
5652
5653 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5654 I915_WRITE(VLV_PCBR, pctx_paddr);
5655
5656 out:
5657 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5658 dev_priv->vlv_pctx = pctx;
5659 mutex_unlock(&dev_priv->dev->struct_mutex);
5660 }
5661
5662 static void valleyview_cleanup_pctx(struct drm_i915_private *dev_priv)
5663 {
5664 if (WARN_ON(!dev_priv->vlv_pctx))
5665 return;
5666
5667 drm_gem_object_unreference_unlocked(&dev_priv->vlv_pctx->base);
5668 dev_priv->vlv_pctx = NULL;
5669 }
5670
5671 static void vlv_init_gpll_ref_freq(struct drm_i915_private *dev_priv)
5672 {
5673 dev_priv->rps.gpll_ref_freq =
5674 vlv_get_cck_clock(dev_priv, "GPLL ref",
5675 CCK_GPLL_CLOCK_CONTROL,
5676 dev_priv->czclk_freq);
5677
5678 DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n",
5679 dev_priv->rps.gpll_ref_freq);
5680 }
5681
5682 static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv)
5683 {
5684 u32 val;
5685
5686 valleyview_setup_pctx(dev_priv);
5687
5688 vlv_init_gpll_ref_freq(dev_priv);
5689
5690 mutex_lock(&dev_priv->rps.hw_lock);
5691
5692 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5693 switch ((val >> 6) & 3) {
5694 case 0:
5695 case 1:
5696 dev_priv->mem_freq = 800;
5697 break;
5698 case 2:
5699 dev_priv->mem_freq = 1066;
5700 break;
5701 case 3:
5702 dev_priv->mem_freq = 1333;
5703 break;
5704 }
5705 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5706
5707 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5708 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5709 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5710 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5711 dev_priv->rps.max_freq);
5712
5713 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5714 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5715 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5716 dev_priv->rps.efficient_freq);
5717
5718 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5719 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
5720 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5721 dev_priv->rps.rp1_freq);
5722
5723 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5724 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5725 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5726 dev_priv->rps.min_freq);
5727
5728 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5729
5730 /* Preserve min/max settings in case of re-init */
5731 if (dev_priv->rps.max_freq_softlimit == 0)
5732 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5733
5734 if (dev_priv->rps.min_freq_softlimit == 0)
5735 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5736
5737 mutex_unlock(&dev_priv->rps.hw_lock);
5738 }
5739
5740 static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv)
5741 {
5742 u32 val;
5743
5744 cherryview_setup_pctx(dev_priv);
5745
5746 vlv_init_gpll_ref_freq(dev_priv);
5747
5748 mutex_lock(&dev_priv->rps.hw_lock);
5749
5750 mutex_lock(&dev_priv->sb_lock);
5751 val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
5752 mutex_unlock(&dev_priv->sb_lock);
5753
5754 switch ((val >> 2) & 0x7) {
5755 case 3:
5756 dev_priv->mem_freq = 2000;
5757 break;
5758 default:
5759 dev_priv->mem_freq = 1600;
5760 break;
5761 }
5762 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5763
5764 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5765 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5766 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5767 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5768 dev_priv->rps.max_freq);
5769
5770 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5771 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5772 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5773 dev_priv->rps.efficient_freq);
5774
5775 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5776 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
5777 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5778 dev_priv->rps.rp1_freq);
5779
5780 /* PUnit validated range is only [RPe, RP0] */
5781 dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
5782 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5783 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5784 dev_priv->rps.min_freq);
5785
5786 WARN_ONCE((dev_priv->rps.max_freq |
5787 dev_priv->rps.efficient_freq |
5788 dev_priv->rps.rp1_freq |
5789 dev_priv->rps.min_freq) & 1,
5790 "Odd GPU freq values\n");
5791
5792 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5793
5794 /* Preserve min/max settings in case of re-init */
5795 if (dev_priv->rps.max_freq_softlimit == 0)
5796 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5797
5798 if (dev_priv->rps.min_freq_softlimit == 0)
5799 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5800
5801 mutex_unlock(&dev_priv->rps.hw_lock);
5802 }
5803
5804 static void valleyview_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
5805 {
5806 valleyview_cleanup_pctx(dev_priv);
5807 }
5808
5809 static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
5810 {
5811 struct intel_engine_cs *engine;
5812 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
5813
5814 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5815
5816 gtfifodbg = I915_READ(GTFIFODBG) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV |
5817 GT_FIFO_FREE_ENTRIES_CHV);
5818 if (gtfifodbg) {
5819 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5820 gtfifodbg);
5821 I915_WRITE(GTFIFODBG, gtfifodbg);
5822 }
5823
5824 cherryview_check_pctx(dev_priv);
5825
5826 /* 1a & 1b: Get forcewake during program sequence. Although the driver
5827 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5828 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5829
5830 /* Disable RC states. */
5831 I915_WRITE(GEN6_RC_CONTROL, 0);
5832
5833 /* 2a: Program RC6 thresholds.*/
5834 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5835 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5836 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5837
5838 for_each_engine(engine, dev_priv)
5839 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5840 I915_WRITE(GEN6_RC_SLEEP, 0);
5841
5842 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
5843 I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
5844
5845 /* allows RC6 residency counter to work */
5846 I915_WRITE(VLV_COUNTER_CONTROL,
5847 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
5848 VLV_MEDIA_RC6_COUNT_EN |
5849 VLV_RENDER_RC6_COUNT_EN));
5850
5851 /* For now we assume BIOS is allocating and populating the PCBR */
5852 pcbr = I915_READ(VLV_PCBR);
5853
5854 /* 3: Enable RC6 */
5855 if ((intel_enable_rc6() & INTEL_RC6_ENABLE) &&
5856 (pcbr >> VLV_PCBR_ADDR_SHIFT))
5857 rc6_mode = GEN7_RC_CTL_TO_MODE;
5858
5859 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5860
5861 /* 4 Program defaults and thresholds for RPS*/
5862 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
5863 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5864 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5865 I915_WRITE(GEN6_RP_UP_EI, 66000);
5866 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5867
5868 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5869
5870 /* 5: Enable RPS */
5871 I915_WRITE(GEN6_RP_CONTROL,
5872 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5873 GEN6_RP_MEDIA_IS_GFX |
5874 GEN6_RP_ENABLE |
5875 GEN6_RP_UP_BUSY_AVG |
5876 GEN6_RP_DOWN_IDLE_AVG);
5877
5878 /* Setting Fixed Bias */
5879 val = VLV_OVERRIDE_EN |
5880 VLV_SOC_TDP_EN |
5881 CHV_BIAS_CPU_50_SOC_50;
5882 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5883
5884 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5885
5886 /* RPS code assumes GPLL is used */
5887 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5888
5889 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
5890 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5891
5892 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5893 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5894 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
5895 dev_priv->rps.cur_freq);
5896
5897 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5898 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq),
5899 dev_priv->rps.idle_freq);
5900
5901 valleyview_set_rps(dev_priv, dev_priv->rps.idle_freq);
5902
5903 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5904 }
5905
5906 static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
5907 {
5908 struct intel_engine_cs *engine;
5909 u32 gtfifodbg, val, rc6_mode = 0;
5910
5911 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5912
5913 valleyview_check_pctx(dev_priv);
5914
5915 gtfifodbg = I915_READ(GTFIFODBG);
5916 if (gtfifodbg) {
5917 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5918 gtfifodbg);
5919 I915_WRITE(GTFIFODBG, gtfifodbg);
5920 }
5921
5922 /* If VLV, Forcewake all wells, else re-direct to regular path */
5923 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5924
5925 /* Disable RC states. */
5926 I915_WRITE(GEN6_RC_CONTROL, 0);
5927
5928 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
5929 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5930 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5931 I915_WRITE(GEN6_RP_UP_EI, 66000);
5932 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5933
5934 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5935
5936 I915_WRITE(GEN6_RP_CONTROL,
5937 GEN6_RP_MEDIA_TURBO |
5938 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5939 GEN6_RP_MEDIA_IS_GFX |
5940 GEN6_RP_ENABLE |
5941 GEN6_RP_UP_BUSY_AVG |
5942 GEN6_RP_DOWN_IDLE_CONT);
5943
5944 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
5945 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5946 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5947
5948 for_each_engine(engine, dev_priv)
5949 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5950
5951 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
5952
5953 /* allows RC6 residency counter to work */
5954 I915_WRITE(VLV_COUNTER_CONTROL,
5955 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
5956 VLV_RENDER_RC0_COUNT_EN |
5957 VLV_MEDIA_RC6_COUNT_EN |
5958 VLV_RENDER_RC6_COUNT_EN));
5959
5960 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
5961 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
5962
5963 intel_print_rc6_info(dev_priv, rc6_mode);
5964
5965 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5966
5967 /* Setting Fixed Bias */
5968 val = VLV_OVERRIDE_EN |
5969 VLV_SOC_TDP_EN |
5970 VLV_BIAS_CPU_125_SOC_875;
5971 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5972
5973 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5974
5975 /* RPS code assumes GPLL is used */
5976 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5977
5978 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
5979 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5980
5981 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5982 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5983 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
5984 dev_priv->rps.cur_freq);
5985
5986 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5987 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq),
5988 dev_priv->rps.idle_freq);
5989
5990 valleyview_set_rps(dev_priv, dev_priv->rps.idle_freq);
5991
5992 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5993 }
5994
5995 static unsigned long intel_pxfreq(u32 vidfreq)
5996 {
5997 unsigned long freq;
5998 int div = (vidfreq & 0x3f0000) >> 16;
5999 int post = (vidfreq & 0x3000) >> 12;
6000 int pre = (vidfreq & 0x7);
6001
6002 if (!pre)
6003 return 0;
6004
6005 freq = ((div * 133333) / ((1<<post) * pre));
6006
6007 return freq;
6008 }
6009
6010 static const struct cparams {
6011 u16 i;
6012 u16 t;
6013 u16 m;
6014 u16 c;
6015 } cparams[] = {
6016 { 1, 1333, 301, 28664 },
6017 { 1, 1066, 294, 24460 },
6018 { 1, 800, 294, 25192 },
6019 { 0, 1333, 276, 27605 },
6020 { 0, 1066, 276, 27605 },
6021 { 0, 800, 231, 23784 },
6022 };
6023
6024 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
6025 {
6026 u64 total_count, diff, ret;
6027 u32 count1, count2, count3, m = 0, c = 0;
6028 unsigned long now = jiffies_to_msecs(jiffies), diff1;
6029 int i;
6030
6031 assert_spin_locked(&mchdev_lock);
6032
6033 diff1 = now - dev_priv->ips.last_time1;
6034
6035 /* Prevent division-by-zero if we are asking too fast.
6036 * Also, we don't get interesting results if we are polling
6037 * faster than once in 10ms, so just return the saved value
6038 * in such cases.
6039 */
6040 if (diff1 <= 10)
6041 return dev_priv->ips.chipset_power;
6042
6043 count1 = I915_READ(DMIEC);
6044 count2 = I915_READ(DDREC);
6045 count3 = I915_READ(CSIEC);
6046
6047 total_count = count1 + count2 + count3;
6048
6049 /* FIXME: handle per-counter overflow */
6050 if (total_count < dev_priv->ips.last_count1) {
6051 diff = ~0UL - dev_priv->ips.last_count1;
6052 diff += total_count;
6053 } else {
6054 diff = total_count - dev_priv->ips.last_count1;
6055 }
6056
6057 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
6058 if (cparams[i].i == dev_priv->ips.c_m &&
6059 cparams[i].t == dev_priv->ips.r_t) {
6060 m = cparams[i].m;
6061 c = cparams[i].c;
6062 break;
6063 }
6064 }
6065
6066 diff = div_u64(diff, diff1);
6067 ret = ((m * diff) + c);
6068 ret = div_u64(ret, 10);
6069
6070 dev_priv->ips.last_count1 = total_count;
6071 dev_priv->ips.last_time1 = now;
6072
6073 dev_priv->ips.chipset_power = ret;
6074
6075 return ret;
6076 }
6077
6078 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
6079 {
6080 unsigned long val;
6081
6082 if (INTEL_INFO(dev_priv)->gen != 5)
6083 return 0;
6084
6085 spin_lock_irq(&mchdev_lock);
6086
6087 val = __i915_chipset_val(dev_priv);
6088
6089 spin_unlock_irq(&mchdev_lock);
6090
6091 return val;
6092 }
6093
6094 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
6095 {
6096 unsigned long m, x, b;
6097 u32 tsfs;
6098
6099 tsfs = I915_READ(TSFS);
6100
6101 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
6102 x = I915_READ8(TR1);
6103
6104 b = tsfs & TSFS_INTR_MASK;
6105
6106 return ((m * x) / 127) - b;
6107 }
6108
6109 static int _pxvid_to_vd(u8 pxvid)
6110 {
6111 if (pxvid == 0)
6112 return 0;
6113
6114 if (pxvid >= 8 && pxvid < 31)
6115 pxvid = 31;
6116
6117 return (pxvid + 2) * 125;
6118 }
6119
6120 static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
6121 {
6122 const int vd = _pxvid_to_vd(pxvid);
6123 const int vm = vd - 1125;
6124
6125 if (INTEL_INFO(dev_priv)->is_mobile)
6126 return vm > 0 ? vm : 0;
6127
6128 return vd;
6129 }
6130
6131 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
6132 {
6133 u64 now, diff, diffms;
6134 u32 count;
6135
6136 assert_spin_locked(&mchdev_lock);
6137
6138 now = ktime_get_raw_ns();
6139 diffms = now - dev_priv->ips.last_time2;
6140 do_div(diffms, NSEC_PER_MSEC);
6141
6142 /* Don't divide by 0 */
6143 if (!diffms)
6144 return;
6145
6146 count = I915_READ(GFXEC);
6147
6148 if (count < dev_priv->ips.last_count2) {
6149 diff = ~0UL - dev_priv->ips.last_count2;
6150 diff += count;
6151 } else {
6152 diff = count - dev_priv->ips.last_count2;
6153 }
6154
6155 dev_priv->ips.last_count2 = count;
6156 dev_priv->ips.last_time2 = now;
6157
6158 /* More magic constants... */
6159 diff = diff * 1181;
6160 diff = div_u64(diff, diffms * 10);
6161 dev_priv->ips.gfx_power = diff;
6162 }
6163
6164 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
6165 {
6166 if (INTEL_INFO(dev_priv)->gen != 5)
6167 return;
6168
6169 spin_lock_irq(&mchdev_lock);
6170
6171 __i915_update_gfx_val(dev_priv);
6172
6173 spin_unlock_irq(&mchdev_lock);
6174 }
6175
6176 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
6177 {
6178 unsigned long t, corr, state1, corr2, state2;
6179 u32 pxvid, ext_v;
6180
6181 assert_spin_locked(&mchdev_lock);
6182
6183 pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
6184 pxvid = (pxvid >> 24) & 0x7f;
6185 ext_v = pvid_to_extvid(dev_priv, pxvid);
6186
6187 state1 = ext_v;
6188
6189 t = i915_mch_val(dev_priv);
6190
6191 /* Revel in the empirically derived constants */
6192
6193 /* Correction factor in 1/100000 units */
6194 if (t > 80)
6195 corr = ((t * 2349) + 135940);
6196 else if (t >= 50)
6197 corr = ((t * 964) + 29317);
6198 else /* < 50 */
6199 corr = ((t * 301) + 1004);
6200
6201 corr = corr * ((150142 * state1) / 10000 - 78642);
6202 corr /= 100000;
6203 corr2 = (corr * dev_priv->ips.corr);
6204
6205 state2 = (corr2 * state1) / 10000;
6206 state2 /= 100; /* convert to mW */
6207
6208 __i915_update_gfx_val(dev_priv);
6209
6210 return dev_priv->ips.gfx_power + state2;
6211 }
6212
6213 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
6214 {
6215 unsigned long val;
6216
6217 if (INTEL_INFO(dev_priv)->gen != 5)
6218 return 0;
6219
6220 spin_lock_irq(&mchdev_lock);
6221
6222 val = __i915_gfx_val(dev_priv);
6223
6224 spin_unlock_irq(&mchdev_lock);
6225
6226 return val;
6227 }
6228
6229 /**
6230 * i915_read_mch_val - return value for IPS use
6231 *
6232 * Calculate and return a value for the IPS driver to use when deciding whether
6233 * we have thermal and power headroom to increase CPU or GPU power budget.
6234 */
6235 unsigned long i915_read_mch_val(void)
6236 {
6237 struct drm_i915_private *dev_priv;
6238 unsigned long chipset_val, graphics_val, ret = 0;
6239
6240 spin_lock_irq(&mchdev_lock);
6241 if (!i915_mch_dev)
6242 goto out_unlock;
6243 dev_priv = i915_mch_dev;
6244
6245 chipset_val = __i915_chipset_val(dev_priv);
6246 graphics_val = __i915_gfx_val(dev_priv);
6247
6248 ret = chipset_val + graphics_val;
6249
6250 out_unlock:
6251 spin_unlock_irq(&mchdev_lock);
6252
6253 return ret;
6254 }
6255 EXPORT_SYMBOL_GPL(i915_read_mch_val);
6256
6257 /**
6258 * i915_gpu_raise - raise GPU frequency limit
6259 *
6260 * Raise the limit; IPS indicates we have thermal headroom.
6261 */
6262 bool i915_gpu_raise(void)
6263 {
6264 struct drm_i915_private *dev_priv;
6265 bool ret = true;
6266
6267 spin_lock_irq(&mchdev_lock);
6268 if (!i915_mch_dev) {
6269 ret = false;
6270 goto out_unlock;
6271 }
6272 dev_priv = i915_mch_dev;
6273
6274 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
6275 dev_priv->ips.max_delay--;
6276
6277 out_unlock:
6278 spin_unlock_irq(&mchdev_lock);
6279
6280 return ret;
6281 }
6282 EXPORT_SYMBOL_GPL(i915_gpu_raise);
6283
6284 /**
6285 * i915_gpu_lower - lower GPU frequency limit
6286 *
6287 * IPS indicates we're close to a thermal limit, so throttle back the GPU
6288 * frequency maximum.
6289 */
6290 bool i915_gpu_lower(void)
6291 {
6292 struct drm_i915_private *dev_priv;
6293 bool ret = true;
6294
6295 spin_lock_irq(&mchdev_lock);
6296 if (!i915_mch_dev) {
6297 ret = false;
6298 goto out_unlock;
6299 }
6300 dev_priv = i915_mch_dev;
6301
6302 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
6303 dev_priv->ips.max_delay++;
6304
6305 out_unlock:
6306 spin_unlock_irq(&mchdev_lock);
6307
6308 return ret;
6309 }
6310 EXPORT_SYMBOL_GPL(i915_gpu_lower);
6311
6312 /**
6313 * i915_gpu_busy - indicate GPU business to IPS
6314 *
6315 * Tell the IPS driver whether or not the GPU is busy.
6316 */
6317 bool i915_gpu_busy(void)
6318 {
6319 struct drm_i915_private *dev_priv;
6320 struct intel_engine_cs *engine;
6321 bool ret = false;
6322
6323 spin_lock_irq(&mchdev_lock);
6324 if (!i915_mch_dev)
6325 goto out_unlock;
6326 dev_priv = i915_mch_dev;
6327
6328 for_each_engine(engine, dev_priv)
6329 ret |= !list_empty(&engine->request_list);
6330
6331 out_unlock:
6332 spin_unlock_irq(&mchdev_lock);
6333
6334 return ret;
6335 }
6336 EXPORT_SYMBOL_GPL(i915_gpu_busy);
6337
6338 /**
6339 * i915_gpu_turbo_disable - disable graphics turbo
6340 *
6341 * Disable graphics turbo by resetting the max frequency and setting the
6342 * current frequency to the default.
6343 */
6344 bool i915_gpu_turbo_disable(void)
6345 {
6346 struct drm_i915_private *dev_priv;
6347 bool ret = true;
6348
6349 spin_lock_irq(&mchdev_lock);
6350 if (!i915_mch_dev) {
6351 ret = false;
6352 goto out_unlock;
6353 }
6354 dev_priv = i915_mch_dev;
6355
6356 dev_priv->ips.max_delay = dev_priv->ips.fstart;
6357
6358 if (!ironlake_set_drps(dev_priv, dev_priv->ips.fstart))
6359 ret = false;
6360
6361 out_unlock:
6362 spin_unlock_irq(&mchdev_lock);
6363
6364 return ret;
6365 }
6366 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6367
6368 /**
6369 * Tells the intel_ips driver that the i915 driver is now loaded, if
6370 * IPS got loaded first.
6371 *
6372 * This awkward dance is so that neither module has to depend on the
6373 * other in order for IPS to do the appropriate communication of
6374 * GPU turbo limits to i915.
6375 */
6376 static void
6377 ips_ping_for_i915_load(void)
6378 {
6379 void (*link)(void);
6380
6381 link = symbol_get(ips_link_to_i915_driver);
6382 if (link) {
6383 link();
6384 symbol_put(ips_link_to_i915_driver);
6385 }
6386 }
6387
6388 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6389 {
6390 /* We only register the i915 ips part with intel-ips once everything is
6391 * set up, to avoid intel-ips sneaking in and reading bogus values. */
6392 spin_lock_irq(&mchdev_lock);
6393 i915_mch_dev = dev_priv;
6394 spin_unlock_irq(&mchdev_lock);
6395
6396 ips_ping_for_i915_load();
6397 }
6398
6399 void intel_gpu_ips_teardown(void)
6400 {
6401 spin_lock_irq(&mchdev_lock);
6402 i915_mch_dev = NULL;
6403 spin_unlock_irq(&mchdev_lock);
6404 }
6405
6406 static void intel_init_emon(struct drm_i915_private *dev_priv)
6407 {
6408 u32 lcfuse;
6409 u8 pxw[16];
6410 int i;
6411
6412 /* Disable to program */
6413 I915_WRITE(ECR, 0);
6414 POSTING_READ(ECR);
6415
6416 /* Program energy weights for various events */
6417 I915_WRITE(SDEW, 0x15040d00);
6418 I915_WRITE(CSIEW0, 0x007f0000);
6419 I915_WRITE(CSIEW1, 0x1e220004);
6420 I915_WRITE(CSIEW2, 0x04000004);
6421
6422 for (i = 0; i < 5; i++)
6423 I915_WRITE(PEW(i), 0);
6424 for (i = 0; i < 3; i++)
6425 I915_WRITE(DEW(i), 0);
6426
6427 /* Program P-state weights to account for frequency power adjustment */
6428 for (i = 0; i < 16; i++) {
6429 u32 pxvidfreq = I915_READ(PXVFREQ(i));
6430 unsigned long freq = intel_pxfreq(pxvidfreq);
6431 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6432 PXVFREQ_PX_SHIFT;
6433 unsigned long val;
6434
6435 val = vid * vid;
6436 val *= (freq / 1000);
6437 val *= 255;
6438 val /= (127*127*900);
6439 if (val > 0xff)
6440 DRM_ERROR("bad pxval: %ld\n", val);
6441 pxw[i] = val;
6442 }
6443 /* Render standby states get 0 weight */
6444 pxw[14] = 0;
6445 pxw[15] = 0;
6446
6447 for (i = 0; i < 4; i++) {
6448 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6449 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
6450 I915_WRITE(PXW(i), val);
6451 }
6452
6453 /* Adjust magic regs to magic values (more experimental results) */
6454 I915_WRITE(OGW0, 0);
6455 I915_WRITE(OGW1, 0);
6456 I915_WRITE(EG0, 0x00007f00);
6457 I915_WRITE(EG1, 0x0000000e);
6458 I915_WRITE(EG2, 0x000e0000);
6459 I915_WRITE(EG3, 0x68000300);
6460 I915_WRITE(EG4, 0x42000000);
6461 I915_WRITE(EG5, 0x00140031);
6462 I915_WRITE(EG6, 0);
6463 I915_WRITE(EG7, 0);
6464
6465 for (i = 0; i < 8; i++)
6466 I915_WRITE(PXWL(i), 0);
6467
6468 /* Enable PMON + select events */
6469 I915_WRITE(ECR, 0x80000019);
6470
6471 lcfuse = I915_READ(LCFUSE02);
6472
6473 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
6474 }
6475
6476 void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
6477 {
6478 /*
6479 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6480 * requirement.
6481 */
6482 if (!i915.enable_rc6) {
6483 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6484 intel_runtime_pm_get(dev_priv);
6485 }
6486
6487 if (IS_CHERRYVIEW(dev_priv))
6488 cherryview_init_gt_powersave(dev_priv);
6489 else if (IS_VALLEYVIEW(dev_priv))
6490 valleyview_init_gt_powersave(dev_priv);
6491 }
6492
6493 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
6494 {
6495 if (IS_CHERRYVIEW(dev_priv))
6496 return;
6497 else if (IS_VALLEYVIEW(dev_priv))
6498 valleyview_cleanup_gt_powersave(dev_priv);
6499
6500 if (!i915.enable_rc6)
6501 intel_runtime_pm_put(dev_priv);
6502 }
6503
6504 static void gen6_suspend_rps(struct drm_i915_private *dev_priv)
6505 {
6506 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
6507
6508 gen6_disable_rps_interrupts(dev_priv);
6509 }
6510
6511 /**
6512 * intel_suspend_gt_powersave - suspend PM work and helper threads
6513 * @dev_priv: i915 device
6514 *
6515 * We don't want to disable RC6 or other features here, we just want
6516 * to make sure any work we've queued has finished and won't bother
6517 * us while we're suspended.
6518 */
6519 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
6520 {
6521 if (INTEL_GEN(dev_priv) < 6)
6522 return;
6523
6524 gen6_suspend_rps(dev_priv);
6525
6526 /* Force GPU to min freq during suspend */
6527 gen6_rps_idle(dev_priv);
6528 }
6529
6530 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
6531 {
6532 if (IS_IRONLAKE_M(dev_priv)) {
6533 ironlake_disable_drps(dev_priv);
6534 } else if (INTEL_INFO(dev_priv)->gen >= 6) {
6535 intel_suspend_gt_powersave(dev_priv);
6536
6537 mutex_lock(&dev_priv->rps.hw_lock);
6538 if (INTEL_INFO(dev_priv)->gen >= 9) {
6539 gen9_disable_rc6(dev_priv);
6540 gen9_disable_rps(dev_priv);
6541 } else if (IS_CHERRYVIEW(dev_priv))
6542 cherryview_disable_rps(dev_priv);
6543 else if (IS_VALLEYVIEW(dev_priv))
6544 valleyview_disable_rps(dev_priv);
6545 else
6546 gen6_disable_rps(dev_priv);
6547
6548 dev_priv->rps.enabled = false;
6549 mutex_unlock(&dev_priv->rps.hw_lock);
6550 }
6551 }
6552
6553 static void intel_gen6_powersave_work(struct work_struct *work)
6554 {
6555 struct drm_i915_private *dev_priv =
6556 container_of(work, struct drm_i915_private,
6557 rps.delayed_resume_work.work);
6558
6559 mutex_lock(&dev_priv->rps.hw_lock);
6560
6561 gen6_reset_rps_interrupts(dev_priv);
6562
6563 if (IS_CHERRYVIEW(dev_priv)) {
6564 cherryview_enable_rps(dev_priv);
6565 } else if (IS_VALLEYVIEW(dev_priv)) {
6566 valleyview_enable_rps(dev_priv);
6567 } else if (INTEL_INFO(dev_priv)->gen >= 9) {
6568 gen9_enable_rc6(dev_priv);
6569 gen9_enable_rps(dev_priv);
6570 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
6571 __gen6_update_ring_freq(dev_priv);
6572 } else if (IS_BROADWELL(dev_priv)) {
6573 gen8_enable_rps(dev_priv);
6574 __gen6_update_ring_freq(dev_priv);
6575 } else {
6576 gen6_enable_rps(dev_priv);
6577 __gen6_update_ring_freq(dev_priv);
6578 }
6579
6580 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6581 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6582
6583 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6584 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6585
6586 dev_priv->rps.enabled = true;
6587
6588 gen6_enable_rps_interrupts(dev_priv);
6589
6590 mutex_unlock(&dev_priv->rps.hw_lock);
6591
6592 intel_runtime_pm_put(dev_priv);
6593 }
6594
6595 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
6596 {
6597 /* Powersaving is controlled by the host when inside a VM */
6598 if (intel_vgpu_active(dev_priv))
6599 return;
6600
6601 if (IS_IRONLAKE_M(dev_priv)) {
6602 ironlake_enable_drps(dev_priv);
6603 mutex_lock(&dev_priv->dev->struct_mutex);
6604 intel_init_emon(dev_priv);
6605 mutex_unlock(&dev_priv->dev->struct_mutex);
6606 } else if (INTEL_INFO(dev_priv)->gen >= 6) {
6607 /*
6608 * PCU communication is slow and this doesn't need to be
6609 * done at any specific time, so do this out of our fast path
6610 * to make resume and init faster.
6611 *
6612 * We depend on the HW RC6 power context save/restore
6613 * mechanism when entering D3 through runtime PM suspend. So
6614 * disable RPM until RPS/RC6 is properly setup. We can only
6615 * get here via the driver load/system resume/runtime resume
6616 * paths, so the _noresume version is enough (and in case of
6617 * runtime resume it's necessary).
6618 */
6619 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
6620 round_jiffies_up_relative(HZ)))
6621 intel_runtime_pm_get_noresume(dev_priv);
6622 }
6623 }
6624
6625 void intel_reset_gt_powersave(struct drm_i915_private *dev_priv)
6626 {
6627 if (INTEL_INFO(dev_priv)->gen < 6)
6628 return;
6629
6630 gen6_suspend_rps(dev_priv);
6631 dev_priv->rps.enabled = false;
6632 }
6633
6634 static void ibx_init_clock_gating(struct drm_device *dev)
6635 {
6636 struct drm_i915_private *dev_priv = dev->dev_private;
6637
6638 /*
6639 * On Ibex Peak and Cougar Point, we need to disable clock
6640 * gating for the panel power sequencer or it will fail to
6641 * start up when no ports are active.
6642 */
6643 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6644 }
6645
6646 static void g4x_disable_trickle_feed(struct drm_device *dev)
6647 {
6648 struct drm_i915_private *dev_priv = dev->dev_private;
6649 enum pipe pipe;
6650
6651 for_each_pipe(dev_priv, pipe) {
6652 I915_WRITE(DSPCNTR(pipe),
6653 I915_READ(DSPCNTR(pipe)) |
6654 DISPPLANE_TRICKLE_FEED_DISABLE);
6655
6656 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6657 POSTING_READ(DSPSURF(pipe));
6658 }
6659 }
6660
6661 static void ilk_init_lp_watermarks(struct drm_device *dev)
6662 {
6663 struct drm_i915_private *dev_priv = dev->dev_private;
6664
6665 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6666 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6667 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6668
6669 /*
6670 * Don't touch WM1S_LP_EN here.
6671 * Doing so could cause underruns.
6672 */
6673 }
6674
6675 static void ironlake_init_clock_gating(struct drm_device *dev)
6676 {
6677 struct drm_i915_private *dev_priv = dev->dev_private;
6678 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6679
6680 /*
6681 * Required for FBC
6682 * WaFbcDisableDpfcClockGating:ilk
6683 */
6684 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6685 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6686 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6687
6688 I915_WRITE(PCH_3DCGDIS0,
6689 MARIUNIT_CLOCK_GATE_DISABLE |
6690 SVSMUNIT_CLOCK_GATE_DISABLE);
6691 I915_WRITE(PCH_3DCGDIS1,
6692 VFMUNIT_CLOCK_GATE_DISABLE);
6693
6694 /*
6695 * According to the spec the following bits should be set in
6696 * order to enable memory self-refresh
6697 * The bit 22/21 of 0x42004
6698 * The bit 5 of 0x42020
6699 * The bit 15 of 0x45000
6700 */
6701 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6702 (I915_READ(ILK_DISPLAY_CHICKEN2) |
6703 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
6704 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6705 I915_WRITE(DISP_ARB_CTL,
6706 (I915_READ(DISP_ARB_CTL) |
6707 DISP_FBC_WM_DIS));
6708
6709 ilk_init_lp_watermarks(dev);
6710
6711 /*
6712 * Based on the document from hardware guys the following bits
6713 * should be set unconditionally in order to enable FBC.
6714 * The bit 22 of 0x42000
6715 * The bit 22 of 0x42004
6716 * The bit 7,8,9 of 0x42020.
6717 */
6718 if (IS_IRONLAKE_M(dev)) {
6719 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6720 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6721 I915_READ(ILK_DISPLAY_CHICKEN1) |
6722 ILK_FBCQ_DIS);
6723 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6724 I915_READ(ILK_DISPLAY_CHICKEN2) |
6725 ILK_DPARB_GATE);
6726 }
6727
6728 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6729
6730 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6731 I915_READ(ILK_DISPLAY_CHICKEN2) |
6732 ILK_ELPIN_409_SELECT);
6733 I915_WRITE(_3D_CHICKEN2,
6734 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6735 _3D_CHICKEN2_WM_READ_PIPELINED);
6736
6737 /* WaDisableRenderCachePipelinedFlush:ilk */
6738 I915_WRITE(CACHE_MODE_0,
6739 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6740
6741 /* WaDisable_RenderCache_OperationalFlush:ilk */
6742 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6743
6744 g4x_disable_trickle_feed(dev);
6745
6746 ibx_init_clock_gating(dev);
6747 }
6748
6749 static void cpt_init_clock_gating(struct drm_device *dev)
6750 {
6751 struct drm_i915_private *dev_priv = dev->dev_private;
6752 int pipe;
6753 uint32_t val;
6754
6755 /*
6756 * On Ibex Peak and Cougar Point, we need to disable clock
6757 * gating for the panel power sequencer or it will fail to
6758 * start up when no ports are active.
6759 */
6760 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6761 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6762 PCH_CPUNIT_CLOCK_GATE_DISABLE);
6763 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6764 DPLS_EDP_PPS_FIX_DIS);
6765 /* The below fixes the weird display corruption, a few pixels shifted
6766 * downward, on (only) LVDS of some HP laptops with IVY.
6767 */
6768 for_each_pipe(dev_priv, pipe) {
6769 val = I915_READ(TRANS_CHICKEN2(pipe));
6770 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6771 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6772 if (dev_priv->vbt.fdi_rx_polarity_inverted)
6773 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6774 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6775 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6776 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
6777 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6778 }
6779 /* WADP0ClockGatingDisable */
6780 for_each_pipe(dev_priv, pipe) {
6781 I915_WRITE(TRANS_CHICKEN1(pipe),
6782 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6783 }
6784 }
6785
6786 static void gen6_check_mch_setup(struct drm_device *dev)
6787 {
6788 struct drm_i915_private *dev_priv = dev->dev_private;
6789 uint32_t tmp;
6790
6791 tmp = I915_READ(MCH_SSKPD);
6792 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6793 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6794 tmp);
6795 }
6796
6797 static void gen6_init_clock_gating(struct drm_device *dev)
6798 {
6799 struct drm_i915_private *dev_priv = dev->dev_private;
6800 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6801
6802 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6803
6804 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6805 I915_READ(ILK_DISPLAY_CHICKEN2) |
6806 ILK_ELPIN_409_SELECT);
6807
6808 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
6809 I915_WRITE(_3D_CHICKEN,
6810 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
6811
6812 /* WaDisable_RenderCache_OperationalFlush:snb */
6813 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6814
6815 /*
6816 * BSpec recoomends 8x4 when MSAA is used,
6817 * however in practice 16x4 seems fastest.
6818 *
6819 * Note that PS/WM thread counts depend on the WIZ hashing
6820 * disable bit, which we don't touch here, but it's good
6821 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6822 */
6823 I915_WRITE(GEN6_GT_MODE,
6824 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6825
6826 ilk_init_lp_watermarks(dev);
6827
6828 I915_WRITE(CACHE_MODE_0,
6829 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6830
6831 I915_WRITE(GEN6_UCGCTL1,
6832 I915_READ(GEN6_UCGCTL1) |
6833 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
6834 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6835
6836 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
6837 * gating disable must be set. Failure to set it results in
6838 * flickering pixels due to Z write ordering failures after
6839 * some amount of runtime in the Mesa "fire" demo, and Unigine
6840 * Sanctuary and Tropics, and apparently anything else with
6841 * alpha test or pixel discard.
6842 *
6843 * According to the spec, bit 11 (RCCUNIT) must also be set,
6844 * but we didn't debug actual testcases to find it out.
6845 *
6846 * WaDisableRCCUnitClockGating:snb
6847 * WaDisableRCPBUnitClockGating:snb
6848 */
6849 I915_WRITE(GEN6_UCGCTL2,
6850 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
6851 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
6852
6853 /* WaStripsFansDisableFastClipPerformanceFix:snb */
6854 I915_WRITE(_3D_CHICKEN3,
6855 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6856
6857 /*
6858 * Bspec says:
6859 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
6860 * 3DSTATE_SF number of SF output attributes is more than 16."
6861 */
6862 I915_WRITE(_3D_CHICKEN3,
6863 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
6864
6865 /*
6866 * According to the spec the following bits should be
6867 * set in order to enable memory self-refresh and fbc:
6868 * The bit21 and bit22 of 0x42000
6869 * The bit21 and bit22 of 0x42004
6870 * The bit5 and bit7 of 0x42020
6871 * The bit14 of 0x70180
6872 * The bit14 of 0x71180
6873 *
6874 * WaFbcAsynchFlipDisableFbcQueue:snb
6875 */
6876 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6877 I915_READ(ILK_DISPLAY_CHICKEN1) |
6878 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6879 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6880 I915_READ(ILK_DISPLAY_CHICKEN2) |
6881 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
6882 I915_WRITE(ILK_DSPCLK_GATE_D,
6883 I915_READ(ILK_DSPCLK_GATE_D) |
6884 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
6885 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6886
6887 g4x_disable_trickle_feed(dev);
6888
6889 cpt_init_clock_gating(dev);
6890
6891 gen6_check_mch_setup(dev);
6892 }
6893
6894 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
6895 {
6896 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
6897
6898 /*
6899 * WaVSThreadDispatchOverride:ivb,vlv
6900 *
6901 * This actually overrides the dispatch
6902 * mode for all thread types.
6903 */
6904 reg &= ~GEN7_FF_SCHED_MASK;
6905 reg |= GEN7_FF_TS_SCHED_HW;
6906 reg |= GEN7_FF_VS_SCHED_HW;
6907 reg |= GEN7_FF_DS_SCHED_HW;
6908
6909 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
6910 }
6911
6912 static void lpt_init_clock_gating(struct drm_device *dev)
6913 {
6914 struct drm_i915_private *dev_priv = dev->dev_private;
6915
6916 /*
6917 * TODO: this bit should only be enabled when really needed, then
6918 * disabled when not needed anymore in order to save power.
6919 */
6920 if (HAS_PCH_LPT_LP(dev))
6921 I915_WRITE(SOUTH_DSPCLK_GATE_D,
6922 I915_READ(SOUTH_DSPCLK_GATE_D) |
6923 PCH_LP_PARTITION_LEVEL_DISABLE);
6924
6925 /* WADPOClockGatingDisable:hsw */
6926 I915_WRITE(TRANS_CHICKEN1(PIPE_A),
6927 I915_READ(TRANS_CHICKEN1(PIPE_A)) |
6928 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6929 }
6930
6931 static void lpt_suspend_hw(struct drm_device *dev)
6932 {
6933 struct drm_i915_private *dev_priv = dev->dev_private;
6934
6935 if (HAS_PCH_LPT_LP(dev)) {
6936 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
6937
6938 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6939 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6940 }
6941 }
6942
6943 static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
6944 int general_prio_credits,
6945 int high_prio_credits)
6946 {
6947 u32 misccpctl;
6948
6949 /* WaTempDisableDOPClkGating:bdw */
6950 misccpctl = I915_READ(GEN7_MISCCPCTL);
6951 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
6952
6953 I915_WRITE(GEN8_L3SQCREG1,
6954 L3_GENERAL_PRIO_CREDITS(general_prio_credits) |
6955 L3_HIGH_PRIO_CREDITS(high_prio_credits));
6956
6957 /*
6958 * Wait at least 100 clocks before re-enabling clock gating.
6959 * See the definition of L3SQCREG1 in BSpec.
6960 */
6961 POSTING_READ(GEN8_L3SQCREG1);
6962 udelay(1);
6963 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
6964 }
6965
6966 static void skylake_init_clock_gating(struct drm_device *dev)
6967 {
6968 struct drm_i915_private *dev_priv = dev->dev_private;
6969
6970 /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,kbl */
6971 I915_WRITE(CHICKEN_PAR1_1,
6972 I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
6973 }
6974
6975 static void broadwell_init_clock_gating(struct drm_device *dev)
6976 {
6977 struct drm_i915_private *dev_priv = dev->dev_private;
6978 enum pipe pipe;
6979
6980 ilk_init_lp_watermarks(dev);
6981
6982 /* WaSwitchSolVfFArbitrationPriority:bdw */
6983 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6984
6985 /* WaPsrDPAMaskVBlankInSRD:bdw */
6986 I915_WRITE(CHICKEN_PAR1_1,
6987 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
6988
6989 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
6990 for_each_pipe(dev_priv, pipe) {
6991 I915_WRITE(CHICKEN_PIPESL_1(pipe),
6992 I915_READ(CHICKEN_PIPESL_1(pipe)) |
6993 BDW_DPRS_MASK_VBLANK_SRD);
6994 }
6995
6996 /* WaVSRefCountFullforceMissDisable:bdw */
6997 /* WaDSRefCountFullforceMissDisable:bdw */
6998 I915_WRITE(GEN7_FF_THREAD_MODE,
6999 I915_READ(GEN7_FF_THREAD_MODE) &
7000 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
7001
7002 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7003 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
7004
7005 /* WaDisableSDEUnitClockGating:bdw */
7006 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7007 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7008
7009 /* WaProgramL3SqcReg1Default:bdw */
7010 gen8_set_l3sqc_credits(dev_priv, 30, 2);
7011
7012 /*
7013 * WaGttCachingOffByDefault:bdw
7014 * GTT cache may not work with big pages, so if those
7015 * are ever enabled GTT cache may need to be disabled.
7016 */
7017 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
7018
7019 lpt_init_clock_gating(dev);
7020 }
7021
7022 static void haswell_init_clock_gating(struct drm_device *dev)
7023 {
7024 struct drm_i915_private *dev_priv = dev->dev_private;
7025
7026 ilk_init_lp_watermarks(dev);
7027
7028 /* L3 caching of data atomics doesn't work -- disable it. */
7029 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
7030 I915_WRITE(HSW_ROW_CHICKEN3,
7031 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
7032
7033 /* This is required by WaCatErrorRejectionIssue:hsw */
7034 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7035 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7036 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7037
7038 /* WaVSRefCountFullforceMissDisable:hsw */
7039 I915_WRITE(GEN7_FF_THREAD_MODE,
7040 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
7041
7042 /* WaDisable_RenderCache_OperationalFlush:hsw */
7043 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7044
7045 /* enable HiZ Raw Stall Optimization */
7046 I915_WRITE(CACHE_MODE_0_GEN7,
7047 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7048
7049 /* WaDisable4x2SubspanOptimization:hsw */
7050 I915_WRITE(CACHE_MODE_1,
7051 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7052
7053 /*
7054 * BSpec recommends 8x4 when MSAA is used,
7055 * however in practice 16x4 seems fastest.
7056 *
7057 * Note that PS/WM thread counts depend on the WIZ hashing
7058 * disable bit, which we don't touch here, but it's good
7059 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7060 */
7061 I915_WRITE(GEN7_GT_MODE,
7062 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7063
7064 /* WaSampleCChickenBitEnable:hsw */
7065 I915_WRITE(HALF_SLICE_CHICKEN3,
7066 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
7067
7068 /* WaSwitchSolVfFArbitrationPriority:hsw */
7069 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
7070
7071 /* WaRsPkgCStateDisplayPMReq:hsw */
7072 I915_WRITE(CHICKEN_PAR1_1,
7073 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
7074
7075 lpt_init_clock_gating(dev);
7076 }
7077
7078 static void ivybridge_init_clock_gating(struct drm_device *dev)
7079 {
7080 struct drm_i915_private *dev_priv = dev->dev_private;
7081 uint32_t snpcr;
7082
7083 ilk_init_lp_watermarks(dev);
7084
7085 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
7086
7087 /* WaDisableEarlyCull:ivb */
7088 I915_WRITE(_3D_CHICKEN3,
7089 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7090
7091 /* WaDisableBackToBackFlipFix:ivb */
7092 I915_WRITE(IVB_CHICKEN3,
7093 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7094 CHICKEN3_DGMG_DONE_FIX_DISABLE);
7095
7096 /* WaDisablePSDDualDispatchEnable:ivb */
7097 if (IS_IVB_GT1(dev))
7098 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
7099 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
7100
7101 /* WaDisable_RenderCache_OperationalFlush:ivb */
7102 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7103
7104 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
7105 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
7106 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
7107
7108 /* WaApplyL3ControlAndL3ChickenMode:ivb */
7109 I915_WRITE(GEN7_L3CNTLREG1,
7110 GEN7_WA_FOR_GEN7_L3_CONTROL);
7111 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
7112 GEN7_WA_L3_CHICKEN_MODE);
7113 if (IS_IVB_GT1(dev))
7114 I915_WRITE(GEN7_ROW_CHICKEN2,
7115 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7116 else {
7117 /* must write both registers */
7118 I915_WRITE(GEN7_ROW_CHICKEN2,
7119 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7120 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
7121 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7122 }
7123
7124 /* WaForceL3Serialization:ivb */
7125 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7126 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7127
7128 /*
7129 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
7130 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
7131 */
7132 I915_WRITE(GEN6_UCGCTL2,
7133 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
7134
7135 /* This is required by WaCatErrorRejectionIssue:ivb */
7136 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7137 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7138 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7139
7140 g4x_disable_trickle_feed(dev);
7141
7142 gen7_setup_fixed_func_scheduler(dev_priv);
7143
7144 if (0) { /* causes HiZ corruption on ivb:gt1 */
7145 /* enable HiZ Raw Stall Optimization */
7146 I915_WRITE(CACHE_MODE_0_GEN7,
7147 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7148 }
7149
7150 /* WaDisable4x2SubspanOptimization:ivb */
7151 I915_WRITE(CACHE_MODE_1,
7152 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7153
7154 /*
7155 * BSpec recommends 8x4 when MSAA is used,
7156 * however in practice 16x4 seems fastest.
7157 *
7158 * Note that PS/WM thread counts depend on the WIZ hashing
7159 * disable bit, which we don't touch here, but it's good
7160 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7161 */
7162 I915_WRITE(GEN7_GT_MODE,
7163 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7164
7165 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
7166 snpcr &= ~GEN6_MBC_SNPCR_MASK;
7167 snpcr |= GEN6_MBC_SNPCR_MED;
7168 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
7169
7170 if (!HAS_PCH_NOP(dev))
7171 cpt_init_clock_gating(dev);
7172
7173 gen6_check_mch_setup(dev);
7174 }
7175
7176 static void valleyview_init_clock_gating(struct drm_device *dev)
7177 {
7178 struct drm_i915_private *dev_priv = dev->dev_private;
7179
7180 /* WaDisableEarlyCull:vlv */
7181 I915_WRITE(_3D_CHICKEN3,
7182 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7183
7184 /* WaDisableBackToBackFlipFix:vlv */
7185 I915_WRITE(IVB_CHICKEN3,
7186 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7187 CHICKEN3_DGMG_DONE_FIX_DISABLE);
7188
7189 /* WaPsdDispatchEnable:vlv */
7190 /* WaDisablePSDDualDispatchEnable:vlv */
7191 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
7192 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
7193 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
7194
7195 /* WaDisable_RenderCache_OperationalFlush:vlv */
7196 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7197
7198 /* WaForceL3Serialization:vlv */
7199 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7200 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7201
7202 /* WaDisableDopClockGating:vlv */
7203 I915_WRITE(GEN7_ROW_CHICKEN2,
7204 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7205
7206 /* This is required by WaCatErrorRejectionIssue:vlv */
7207 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7208 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7209 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7210
7211 gen7_setup_fixed_func_scheduler(dev_priv);
7212
7213 /*
7214 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
7215 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
7216 */
7217 I915_WRITE(GEN6_UCGCTL2,
7218 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
7219
7220 /* WaDisableL3Bank2xClockGate:vlv
7221 * Disabling L3 clock gating- MMIO 940c[25] = 1
7222 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
7223 I915_WRITE(GEN7_UCGCTL4,
7224 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
7225
7226 /*
7227 * BSpec says this must be set, even though
7228 * WaDisable4x2SubspanOptimization isn't listed for VLV.
7229 */
7230 I915_WRITE(CACHE_MODE_1,
7231 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7232
7233 /*
7234 * BSpec recommends 8x4 when MSAA is used,
7235 * however in practice 16x4 seems fastest.
7236 *
7237 * Note that PS/WM thread counts depend on the WIZ hashing
7238 * disable bit, which we don't touch here, but it's good
7239 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7240 */
7241 I915_WRITE(GEN7_GT_MODE,
7242 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7243
7244 /*
7245 * WaIncreaseL3CreditsForVLVB0:vlv
7246 * This is the hardware default actually.
7247 */
7248 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
7249
7250 /*
7251 * WaDisableVLVClockGating_VBIIssue:vlv
7252 * Disable clock gating on th GCFG unit to prevent a delay
7253 * in the reporting of vblank events.
7254 */
7255 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
7256 }
7257
7258 static void cherryview_init_clock_gating(struct drm_device *dev)
7259 {
7260 struct drm_i915_private *dev_priv = dev->dev_private;
7261
7262 /* WaVSRefCountFullforceMissDisable:chv */
7263 /* WaDSRefCountFullforceMissDisable:chv */
7264 I915_WRITE(GEN7_FF_THREAD_MODE,
7265 I915_READ(GEN7_FF_THREAD_MODE) &
7266 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
7267
7268 /* WaDisableSemaphoreAndSyncFlipWait:chv */
7269 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7270 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
7271
7272 /* WaDisableCSUnitClockGating:chv */
7273 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7274 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
7275
7276 /* WaDisableSDEUnitClockGating:chv */
7277 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7278 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7279
7280 /*
7281 * WaProgramL3SqcReg1Default:chv
7282 * See gfxspecs/Related Documents/Performance Guide/
7283 * LSQC Setting Recommendations.
7284 */
7285 gen8_set_l3sqc_credits(dev_priv, 38, 2);
7286
7287 /*
7288 * GTT cache may not work with big pages, so if those
7289 * are ever enabled GTT cache may need to be disabled.
7290 */
7291 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
7292 }
7293
7294 static void g4x_init_clock_gating(struct drm_device *dev)
7295 {
7296 struct drm_i915_private *dev_priv = dev->dev_private;
7297 uint32_t dspclk_gate;
7298
7299 I915_WRITE(RENCLK_GATE_D1, 0);
7300 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7301 GS_UNIT_CLOCK_GATE_DISABLE |
7302 CL_UNIT_CLOCK_GATE_DISABLE);
7303 I915_WRITE(RAMCLK_GATE_D, 0);
7304 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7305 OVRUNIT_CLOCK_GATE_DISABLE |
7306 OVCUNIT_CLOCK_GATE_DISABLE;
7307 if (IS_GM45(dev))
7308 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7309 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
7310
7311 /* WaDisableRenderCachePipelinedFlush */
7312 I915_WRITE(CACHE_MODE_0,
7313 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
7314
7315 /* WaDisable_RenderCache_OperationalFlush:g4x */
7316 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7317
7318 g4x_disable_trickle_feed(dev);
7319 }
7320
7321 static void crestline_init_clock_gating(struct drm_device *dev)
7322 {
7323 struct drm_i915_private *dev_priv = dev->dev_private;
7324
7325 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7326 I915_WRITE(RENCLK_GATE_D2, 0);
7327 I915_WRITE(DSPCLK_GATE_D, 0);
7328 I915_WRITE(RAMCLK_GATE_D, 0);
7329 I915_WRITE16(DEUC, 0);
7330 I915_WRITE(MI_ARB_STATE,
7331 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7332
7333 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7334 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7335 }
7336
7337 static void broadwater_init_clock_gating(struct drm_device *dev)
7338 {
7339 struct drm_i915_private *dev_priv = dev->dev_private;
7340
7341 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7342 I965_RCC_CLOCK_GATE_DISABLE |
7343 I965_RCPB_CLOCK_GATE_DISABLE |
7344 I965_ISC_CLOCK_GATE_DISABLE |
7345 I965_FBC_CLOCK_GATE_DISABLE);
7346 I915_WRITE(RENCLK_GATE_D2, 0);
7347 I915_WRITE(MI_ARB_STATE,
7348 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7349
7350 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7351 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7352 }
7353
7354 static void gen3_init_clock_gating(struct drm_device *dev)
7355 {
7356 struct drm_i915_private *dev_priv = dev->dev_private;
7357 u32 dstate = I915_READ(D_STATE);
7358
7359 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7360 DSTATE_DOT_CLOCK_GATING;
7361 I915_WRITE(D_STATE, dstate);
7362
7363 if (IS_PINEVIEW(dev))
7364 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
7365
7366 /* IIR "flip pending" means done if this bit is set */
7367 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
7368
7369 /* interrupts should cause a wake up from C3 */
7370 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
7371
7372 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7373 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
7374
7375 I915_WRITE(MI_ARB_STATE,
7376 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7377 }
7378
7379 static void i85x_init_clock_gating(struct drm_device *dev)
7380 {
7381 struct drm_i915_private *dev_priv = dev->dev_private;
7382
7383 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7384
7385 /* interrupts should cause a wake up from C3 */
7386 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7387 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
7388
7389 I915_WRITE(MEM_MODE,
7390 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
7391 }
7392
7393 static void i830_init_clock_gating(struct drm_device *dev)
7394 {
7395 struct drm_i915_private *dev_priv = dev->dev_private;
7396
7397 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
7398
7399 I915_WRITE(MEM_MODE,
7400 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7401 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
7402 }
7403
7404 void intel_init_clock_gating(struct drm_device *dev)
7405 {
7406 struct drm_i915_private *dev_priv = dev->dev_private;
7407
7408 dev_priv->display.init_clock_gating(dev);
7409 }
7410
7411 void intel_suspend_hw(struct drm_device *dev)
7412 {
7413 if (HAS_PCH_LPT(dev))
7414 lpt_suspend_hw(dev);
7415 }
7416
7417 static void nop_init_clock_gating(struct drm_device *dev)
7418 {
7419 DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n");
7420 }
7421
7422 /**
7423 * intel_init_clock_gating_hooks - setup the clock gating hooks
7424 * @dev_priv: device private
7425 *
7426 * Setup the hooks that configure which clocks of a given platform can be
7427 * gated and also apply various GT and display specific workarounds for these
7428 * platforms. Note that some GT specific workarounds are applied separately
7429 * when GPU contexts or batchbuffers start their execution.
7430 */
7431 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
7432 {
7433 if (IS_SKYLAKE(dev_priv))
7434 dev_priv->display.init_clock_gating = skylake_init_clock_gating;
7435 else if (IS_KABYLAKE(dev_priv))
7436 dev_priv->display.init_clock_gating = skylake_init_clock_gating;
7437 else if (IS_BROXTON(dev_priv))
7438 dev_priv->display.init_clock_gating = bxt_init_clock_gating;
7439 else if (IS_BROADWELL(dev_priv))
7440 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7441 else if (IS_CHERRYVIEW(dev_priv))
7442 dev_priv->display.init_clock_gating = cherryview_init_clock_gating;
7443 else if (IS_HASWELL(dev_priv))
7444 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7445 else if (IS_IVYBRIDGE(dev_priv))
7446 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7447 else if (IS_VALLEYVIEW(dev_priv))
7448 dev_priv->display.init_clock_gating = valleyview_init_clock_gating;
7449 else if (IS_GEN6(dev_priv))
7450 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7451 else if (IS_GEN5(dev_priv))
7452 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7453 else if (IS_G4X(dev_priv))
7454 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7455 else if (IS_CRESTLINE(dev_priv))
7456 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7457 else if (IS_BROADWATER(dev_priv))
7458 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7459 else if (IS_GEN3(dev_priv))
7460 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7461 else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
7462 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7463 else if (IS_GEN2(dev_priv))
7464 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7465 else {
7466 MISSING_CASE(INTEL_DEVID(dev_priv));
7467 dev_priv->display.init_clock_gating = nop_init_clock_gating;
7468 }
7469 }
7470
7471 /* Set up chip specific power management-related functions */
7472 void intel_init_pm(struct drm_device *dev)
7473 {
7474 struct drm_i915_private *dev_priv = dev->dev_private;
7475
7476 intel_fbc_init(dev_priv);
7477
7478 /* For cxsr */
7479 if (IS_PINEVIEW(dev))
7480 i915_pineview_get_mem_freq(dev);
7481 else if (IS_GEN5(dev))
7482 i915_ironlake_get_mem_freq(dev);
7483
7484 /* For FIFO watermark updates */
7485 if (INTEL_INFO(dev)->gen >= 9) {
7486 skl_setup_wm_latency(dev);
7487 dev_priv->display.update_wm = skl_update_wm;
7488 dev_priv->display.compute_global_watermarks = skl_compute_wm;
7489 } else if (HAS_PCH_SPLIT(dev)) {
7490 ilk_setup_wm_latency(dev);
7491
7492 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
7493 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7494 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7495 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
7496 dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
7497 dev_priv->display.compute_intermediate_wm =
7498 ilk_compute_intermediate_wm;
7499 dev_priv->display.initial_watermarks =
7500 ilk_initial_watermarks;
7501 dev_priv->display.optimize_watermarks =
7502 ilk_optimize_watermarks;
7503 } else {
7504 DRM_DEBUG_KMS("Failed to read display plane latency. "
7505 "Disable CxSR\n");
7506 }
7507 } else if (IS_CHERRYVIEW(dev)) {
7508 vlv_setup_wm_latency(dev);
7509 dev_priv->display.update_wm = vlv_update_wm;
7510 } else if (IS_VALLEYVIEW(dev)) {
7511 vlv_setup_wm_latency(dev);
7512 dev_priv->display.update_wm = vlv_update_wm;
7513 } else if (IS_PINEVIEW(dev)) {
7514 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7515 dev_priv->is_ddr3,
7516 dev_priv->fsb_freq,
7517 dev_priv->mem_freq)) {
7518 DRM_INFO("failed to find known CxSR latency "
7519 "(found ddr%s fsb freq %d, mem freq %d), "
7520 "disabling CxSR\n",
7521 (dev_priv->is_ddr3 == 1) ? "3" : "2",
7522 dev_priv->fsb_freq, dev_priv->mem_freq);
7523 /* Disable CxSR and never update its watermark again */
7524 intel_set_memory_cxsr(dev_priv, false);
7525 dev_priv->display.update_wm = NULL;
7526 } else
7527 dev_priv->display.update_wm = pineview_update_wm;
7528 } else if (IS_G4X(dev)) {
7529 dev_priv->display.update_wm = g4x_update_wm;
7530 } else if (IS_GEN4(dev)) {
7531 dev_priv->display.update_wm = i965_update_wm;
7532 } else if (IS_GEN3(dev)) {
7533 dev_priv->display.update_wm = i9xx_update_wm;
7534 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7535 } else if (IS_GEN2(dev)) {
7536 if (INTEL_INFO(dev)->num_pipes == 1) {
7537 dev_priv->display.update_wm = i845_update_wm;
7538 dev_priv->display.get_fifo_size = i845_get_fifo_size;
7539 } else {
7540 dev_priv->display.update_wm = i9xx_update_wm;
7541 dev_priv->display.get_fifo_size = i830_get_fifo_size;
7542 }
7543 } else {
7544 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
7545 }
7546 }
7547
7548 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
7549 {
7550 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7551
7552 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7553 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7554 return -EAGAIN;
7555 }
7556
7557 I915_WRITE(GEN6_PCODE_DATA, *val);
7558 I915_WRITE(GEN6_PCODE_DATA1, 0);
7559 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7560
7561 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7562 500)) {
7563 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7564 return -ETIMEDOUT;
7565 }
7566
7567 *val = I915_READ(GEN6_PCODE_DATA);
7568 I915_WRITE(GEN6_PCODE_DATA, 0);
7569
7570 return 0;
7571 }
7572
7573 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val)
7574 {
7575 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7576
7577 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7578 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7579 return -EAGAIN;
7580 }
7581
7582 I915_WRITE(GEN6_PCODE_DATA, val);
7583 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7584
7585 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7586 500)) {
7587 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7588 return -ETIMEDOUT;
7589 }
7590
7591 I915_WRITE(GEN6_PCODE_DATA, 0);
7592
7593 return 0;
7594 }
7595
7596 static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7597 {
7598 /*
7599 * N = val - 0xb7
7600 * Slow = Fast = GPLL ref * N
7601 */
7602 return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * (val - 0xb7), 1000);
7603 }
7604
7605 static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
7606 {
7607 return DIV_ROUND_CLOSEST(1000 * val, dev_priv->rps.gpll_ref_freq) + 0xb7;
7608 }
7609
7610 static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
7611 {
7612 /*
7613 * N = val / 2
7614 * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2
7615 */
7616 return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * val, 2 * 2 * 1000);
7617 }
7618
7619 static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
7620 {
7621 /* CHV needs even values */
7622 return DIV_ROUND_CLOSEST(2 * 1000 * val, dev_priv->rps.gpll_ref_freq) * 2;
7623 }
7624
7625 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
7626 {
7627 if (IS_GEN9(dev_priv))
7628 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
7629 GEN9_FREQ_SCALER);
7630 else if (IS_CHERRYVIEW(dev_priv))
7631 return chv_gpu_freq(dev_priv, val);
7632 else if (IS_VALLEYVIEW(dev_priv))
7633 return byt_gpu_freq(dev_priv, val);
7634 else
7635 return val * GT_FREQUENCY_MULTIPLIER;
7636 }
7637
7638 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7639 {
7640 if (IS_GEN9(dev_priv))
7641 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
7642 GT_FREQUENCY_MULTIPLIER);
7643 else if (IS_CHERRYVIEW(dev_priv))
7644 return chv_freq_opcode(dev_priv, val);
7645 else if (IS_VALLEYVIEW(dev_priv))
7646 return byt_freq_opcode(dev_priv, val);
7647 else
7648 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
7649 }
7650
7651 struct request_boost {
7652 struct work_struct work;
7653 struct drm_i915_gem_request *req;
7654 };
7655
7656 static void __intel_rps_boost_work(struct work_struct *work)
7657 {
7658 struct request_boost *boost = container_of(work, struct request_boost, work);
7659 struct drm_i915_gem_request *req = boost->req;
7660
7661 if (!i915_gem_request_completed(req, true))
7662 gen6_rps_boost(req->i915, NULL, req->emitted_jiffies);
7663
7664 i915_gem_request_unreference(req);
7665 kfree(boost);
7666 }
7667
7668 void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req)
7669 {
7670 struct request_boost *boost;
7671
7672 if (req == NULL || INTEL_GEN(req->i915) < 6)
7673 return;
7674
7675 if (i915_gem_request_completed(req, true))
7676 return;
7677
7678 boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
7679 if (boost == NULL)
7680 return;
7681
7682 i915_gem_request_reference(req);
7683 boost->req = req;
7684
7685 INIT_WORK(&boost->work, __intel_rps_boost_work);
7686 queue_work(req->i915->wq, &boost->work);
7687 }
7688
7689 void intel_pm_setup(struct drm_device *dev)
7690 {
7691 struct drm_i915_private *dev_priv = dev->dev_private;
7692
7693 mutex_init(&dev_priv->rps.hw_lock);
7694 spin_lock_init(&dev_priv->rps.client_lock);
7695
7696 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
7697 intel_gen6_powersave_work);
7698 INIT_LIST_HEAD(&dev_priv->rps.clients);
7699 INIT_LIST_HEAD(&dev_priv->rps.semaphores.link);
7700 INIT_LIST_HEAD(&dev_priv->rps.mmioflips.link);
7701
7702 dev_priv->pm.suspended = false;
7703 atomic_set(&dev_priv->pm.wakeref_count, 0);
7704 atomic_set(&dev_priv->pm.atomic_seq, 0);
7705 }
Linux kernel - Deliverables
This page took 0.208991 seconds and 5 git commands to generate.