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drm/i195/fbc: Add WaFbcNukeOnHostModify
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_pm.c
1 /*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28 #include <linux/cpufreq.h>
29 #include <drm/drm_plane_helper.h>
30 #include "i915_drv.h"
31 #include "intel_drv.h"
32 #include "../../../platform/x86/intel_ips.h"
33 #include <linux/module.h>
34
35 /**
36 * DOC: RC6
37 *
38 * RC6 is a special power stage which allows the GPU to enter an very
39 * low-voltage mode when idle, using down to 0V while at this stage. This
40 * stage is entered automatically when the GPU is idle when RC6 support is
41 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
42 *
43 * There are different RC6 modes available in Intel GPU, which differentiate
44 * among each other with the latency required to enter and leave RC6 and
45 * voltage consumed by the GPU in different states.
46 *
47 * The combination of the following flags define which states GPU is allowed
48 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
49 * RC6pp is deepest RC6. Their support by hardware varies according to the
50 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
51 * which brings the most power savings; deeper states save more power, but
52 * require higher latency to switch to and wake up.
53 */
54 #define INTEL_RC6_ENABLE (1<<0)
55 #define INTEL_RC6p_ENABLE (1<<1)
56 #define INTEL_RC6pp_ENABLE (1<<2)
57
58 static void gen9_init_clock_gating(struct drm_device *dev)
59 {
60 struct drm_i915_private *dev_priv = dev->dev_private;
61
62 /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl */
63 I915_WRITE(CHICKEN_PAR1_1,
64 I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
65
66 I915_WRITE(GEN8_CONFIG0,
67 I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);
68
69 /* WaEnableChickenDCPR:skl,bxt,kbl */
70 I915_WRITE(GEN8_CHICKEN_DCPR_1,
71 I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
72
73 /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */
74 /* WaFbcWakeMemOn:skl,bxt,kbl */
75 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
76 DISP_FBC_WM_DIS |
77 DISP_FBC_MEMORY_WAKE);
78 }
79
80 static void bxt_init_clock_gating(struct drm_device *dev)
81 {
82 struct drm_i915_private *dev_priv = dev->dev_private;
83
84 gen9_init_clock_gating(dev);
85
86 /* WaDisableSDEUnitClockGating:bxt */
87 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
88 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
89
90 /*
91 * FIXME:
92 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
93 */
94 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
95 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
96
97 /*
98 * Wa: Backlight PWM may stop in the asserted state, causing backlight
99 * to stay fully on.
100 */
101 if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
102 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
103 PWM1_GATING_DIS | PWM2_GATING_DIS);
104 }
105
106 static void i915_pineview_get_mem_freq(struct drm_device *dev)
107 {
108 struct drm_i915_private *dev_priv = dev->dev_private;
109 u32 tmp;
110
111 tmp = I915_READ(CLKCFG);
112
113 switch (tmp & CLKCFG_FSB_MASK) {
114 case CLKCFG_FSB_533:
115 dev_priv->fsb_freq = 533; /* 133*4 */
116 break;
117 case CLKCFG_FSB_800:
118 dev_priv->fsb_freq = 800; /* 200*4 */
119 break;
120 case CLKCFG_FSB_667:
121 dev_priv->fsb_freq = 667; /* 167*4 */
122 break;
123 case CLKCFG_FSB_400:
124 dev_priv->fsb_freq = 400; /* 100*4 */
125 break;
126 }
127
128 switch (tmp & CLKCFG_MEM_MASK) {
129 case CLKCFG_MEM_533:
130 dev_priv->mem_freq = 533;
131 break;
132 case CLKCFG_MEM_667:
133 dev_priv->mem_freq = 667;
134 break;
135 case CLKCFG_MEM_800:
136 dev_priv->mem_freq = 800;
137 break;
138 }
139
140 /* detect pineview DDR3 setting */
141 tmp = I915_READ(CSHRDDR3CTL);
142 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
143 }
144
145 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
146 {
147 struct drm_i915_private *dev_priv = dev->dev_private;
148 u16 ddrpll, csipll;
149
150 ddrpll = I915_READ16(DDRMPLL1);
151 csipll = I915_READ16(CSIPLL0);
152
153 switch (ddrpll & 0xff) {
154 case 0xc:
155 dev_priv->mem_freq = 800;
156 break;
157 case 0x10:
158 dev_priv->mem_freq = 1066;
159 break;
160 case 0x14:
161 dev_priv->mem_freq = 1333;
162 break;
163 case 0x18:
164 dev_priv->mem_freq = 1600;
165 break;
166 default:
167 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
168 ddrpll & 0xff);
169 dev_priv->mem_freq = 0;
170 break;
171 }
172
173 dev_priv->ips.r_t = dev_priv->mem_freq;
174
175 switch (csipll & 0x3ff) {
176 case 0x00c:
177 dev_priv->fsb_freq = 3200;
178 break;
179 case 0x00e:
180 dev_priv->fsb_freq = 3733;
181 break;
182 case 0x010:
183 dev_priv->fsb_freq = 4266;
184 break;
185 case 0x012:
186 dev_priv->fsb_freq = 4800;
187 break;
188 case 0x014:
189 dev_priv->fsb_freq = 5333;
190 break;
191 case 0x016:
192 dev_priv->fsb_freq = 5866;
193 break;
194 case 0x018:
195 dev_priv->fsb_freq = 6400;
196 break;
197 default:
198 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
199 csipll & 0x3ff);
200 dev_priv->fsb_freq = 0;
201 break;
202 }
203
204 if (dev_priv->fsb_freq == 3200) {
205 dev_priv->ips.c_m = 0;
206 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
207 dev_priv->ips.c_m = 1;
208 } else {
209 dev_priv->ips.c_m = 2;
210 }
211 }
212
213 static const struct cxsr_latency cxsr_latency_table[] = {
214 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
215 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
216 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
217 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
218 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
219
220 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
221 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
222 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
223 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
224 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
225
226 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
227 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
228 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
229 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
230 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
231
232 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
233 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
234 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
235 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
236 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
237
238 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
239 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
240 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
241 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
242 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
243
244 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
245 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
246 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
247 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
248 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
249 };
250
251 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
252 int is_ddr3,
253 int fsb,
254 int mem)
255 {
256 const struct cxsr_latency *latency;
257 int i;
258
259 if (fsb == 0 || mem == 0)
260 return NULL;
261
262 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
263 latency = &cxsr_latency_table[i];
264 if (is_desktop == latency->is_desktop &&
265 is_ddr3 == latency->is_ddr3 &&
266 fsb == latency->fsb_freq && mem == latency->mem_freq)
267 return latency;
268 }
269
270 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
271
272 return NULL;
273 }
274
275 static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
276 {
277 u32 val;
278
279 mutex_lock(&dev_priv->rps.hw_lock);
280
281 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
282 if (enable)
283 val &= ~FORCE_DDR_HIGH_FREQ;
284 else
285 val |= FORCE_DDR_HIGH_FREQ;
286 val &= ~FORCE_DDR_LOW_FREQ;
287 val |= FORCE_DDR_FREQ_REQ_ACK;
288 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
289
290 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
291 FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
292 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
293
294 mutex_unlock(&dev_priv->rps.hw_lock);
295 }
296
297 static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
298 {
299 u32 val;
300
301 mutex_lock(&dev_priv->rps.hw_lock);
302
303 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
304 if (enable)
305 val |= DSP_MAXFIFO_PM5_ENABLE;
306 else
307 val &= ~DSP_MAXFIFO_PM5_ENABLE;
308 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
309
310 mutex_unlock(&dev_priv->rps.hw_lock);
311 }
312
313 #define FW_WM(value, plane) \
314 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
315
316 void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
317 {
318 struct drm_device *dev = dev_priv->dev;
319 u32 val;
320
321 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
322 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
323 POSTING_READ(FW_BLC_SELF_VLV);
324 dev_priv->wm.vlv.cxsr = enable;
325 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
326 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
327 POSTING_READ(FW_BLC_SELF);
328 } else if (IS_PINEVIEW(dev)) {
329 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
330 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
331 I915_WRITE(DSPFW3, val);
332 POSTING_READ(DSPFW3);
333 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
334 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
335 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
336 I915_WRITE(FW_BLC_SELF, val);
337 POSTING_READ(FW_BLC_SELF);
338 } else if (IS_I915GM(dev)) {
339 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
340 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
341 I915_WRITE(INSTPM, val);
342 POSTING_READ(INSTPM);
343 } else {
344 return;
345 }
346
347 DRM_DEBUG_KMS("memory self-refresh is %s\n",
348 enable ? "enabled" : "disabled");
349 }
350
351
352 /*
353 * Latency for FIFO fetches is dependent on several factors:
354 * - memory configuration (speed, channels)
355 * - chipset
356 * - current MCH state
357 * It can be fairly high in some situations, so here we assume a fairly
358 * pessimal value. It's a tradeoff between extra memory fetches (if we
359 * set this value too high, the FIFO will fetch frequently to stay full)
360 * and power consumption (set it too low to save power and we might see
361 * FIFO underruns and display "flicker").
362 *
363 * A value of 5us seems to be a good balance; safe for very low end
364 * platforms but not overly aggressive on lower latency configs.
365 */
366 static const int pessimal_latency_ns = 5000;
367
368 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
369 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
370
371 static int vlv_get_fifo_size(struct drm_device *dev,
372 enum pipe pipe, int plane)
373 {
374 struct drm_i915_private *dev_priv = dev->dev_private;
375 int sprite0_start, sprite1_start, size;
376
377 switch (pipe) {
378 uint32_t dsparb, dsparb2, dsparb3;
379 case PIPE_A:
380 dsparb = I915_READ(DSPARB);
381 dsparb2 = I915_READ(DSPARB2);
382 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
383 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
384 break;
385 case PIPE_B:
386 dsparb = I915_READ(DSPARB);
387 dsparb2 = I915_READ(DSPARB2);
388 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
389 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
390 break;
391 case PIPE_C:
392 dsparb2 = I915_READ(DSPARB2);
393 dsparb3 = I915_READ(DSPARB3);
394 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
395 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
396 break;
397 default:
398 return 0;
399 }
400
401 switch (plane) {
402 case 0:
403 size = sprite0_start;
404 break;
405 case 1:
406 size = sprite1_start - sprite0_start;
407 break;
408 case 2:
409 size = 512 - 1 - sprite1_start;
410 break;
411 default:
412 return 0;
413 }
414
415 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
416 pipe_name(pipe), plane == 0 ? "primary" : "sprite",
417 plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
418 size);
419
420 return size;
421 }
422
423 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
424 {
425 struct drm_i915_private *dev_priv = dev->dev_private;
426 uint32_t dsparb = I915_READ(DSPARB);
427 int size;
428
429 size = dsparb & 0x7f;
430 if (plane)
431 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
432
433 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
434 plane ? "B" : "A", size);
435
436 return size;
437 }
438
439 static int i830_get_fifo_size(struct drm_device *dev, int plane)
440 {
441 struct drm_i915_private *dev_priv = dev->dev_private;
442 uint32_t dsparb = I915_READ(DSPARB);
443 int size;
444
445 size = dsparb & 0x1ff;
446 if (plane)
447 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
448 size >>= 1; /* Convert to cachelines */
449
450 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
451 plane ? "B" : "A", size);
452
453 return size;
454 }
455
456 static int i845_get_fifo_size(struct drm_device *dev, int plane)
457 {
458 struct drm_i915_private *dev_priv = dev->dev_private;
459 uint32_t dsparb = I915_READ(DSPARB);
460 int size;
461
462 size = dsparb & 0x7f;
463 size >>= 2; /* Convert to cachelines */
464
465 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
466 plane ? "B" : "A",
467 size);
468
469 return size;
470 }
471
472 /* Pineview has different values for various configs */
473 static const struct intel_watermark_params pineview_display_wm = {
474 .fifo_size = PINEVIEW_DISPLAY_FIFO,
475 .max_wm = PINEVIEW_MAX_WM,
476 .default_wm = PINEVIEW_DFT_WM,
477 .guard_size = PINEVIEW_GUARD_WM,
478 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
479 };
480 static const struct intel_watermark_params pineview_display_hplloff_wm = {
481 .fifo_size = PINEVIEW_DISPLAY_FIFO,
482 .max_wm = PINEVIEW_MAX_WM,
483 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
484 .guard_size = PINEVIEW_GUARD_WM,
485 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
486 };
487 static const struct intel_watermark_params pineview_cursor_wm = {
488 .fifo_size = PINEVIEW_CURSOR_FIFO,
489 .max_wm = PINEVIEW_CURSOR_MAX_WM,
490 .default_wm = PINEVIEW_CURSOR_DFT_WM,
491 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
492 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
493 };
494 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
495 .fifo_size = PINEVIEW_CURSOR_FIFO,
496 .max_wm = PINEVIEW_CURSOR_MAX_WM,
497 .default_wm = PINEVIEW_CURSOR_DFT_WM,
498 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
499 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
500 };
501 static const struct intel_watermark_params g4x_wm_info = {
502 .fifo_size = G4X_FIFO_SIZE,
503 .max_wm = G4X_MAX_WM,
504 .default_wm = G4X_MAX_WM,
505 .guard_size = 2,
506 .cacheline_size = G4X_FIFO_LINE_SIZE,
507 };
508 static const struct intel_watermark_params g4x_cursor_wm_info = {
509 .fifo_size = I965_CURSOR_FIFO,
510 .max_wm = I965_CURSOR_MAX_WM,
511 .default_wm = I965_CURSOR_DFT_WM,
512 .guard_size = 2,
513 .cacheline_size = G4X_FIFO_LINE_SIZE,
514 };
515 static const struct intel_watermark_params i965_cursor_wm_info = {
516 .fifo_size = I965_CURSOR_FIFO,
517 .max_wm = I965_CURSOR_MAX_WM,
518 .default_wm = I965_CURSOR_DFT_WM,
519 .guard_size = 2,
520 .cacheline_size = I915_FIFO_LINE_SIZE,
521 };
522 static const struct intel_watermark_params i945_wm_info = {
523 .fifo_size = I945_FIFO_SIZE,
524 .max_wm = I915_MAX_WM,
525 .default_wm = 1,
526 .guard_size = 2,
527 .cacheline_size = I915_FIFO_LINE_SIZE,
528 };
529 static const struct intel_watermark_params i915_wm_info = {
530 .fifo_size = I915_FIFO_SIZE,
531 .max_wm = I915_MAX_WM,
532 .default_wm = 1,
533 .guard_size = 2,
534 .cacheline_size = I915_FIFO_LINE_SIZE,
535 };
536 static const struct intel_watermark_params i830_a_wm_info = {
537 .fifo_size = I855GM_FIFO_SIZE,
538 .max_wm = I915_MAX_WM,
539 .default_wm = 1,
540 .guard_size = 2,
541 .cacheline_size = I830_FIFO_LINE_SIZE,
542 };
543 static const struct intel_watermark_params i830_bc_wm_info = {
544 .fifo_size = I855GM_FIFO_SIZE,
545 .max_wm = I915_MAX_WM/2,
546 .default_wm = 1,
547 .guard_size = 2,
548 .cacheline_size = I830_FIFO_LINE_SIZE,
549 };
550 static const struct intel_watermark_params i845_wm_info = {
551 .fifo_size = I830_FIFO_SIZE,
552 .max_wm = I915_MAX_WM,
553 .default_wm = 1,
554 .guard_size = 2,
555 .cacheline_size = I830_FIFO_LINE_SIZE,
556 };
557
558 /**
559 * intel_calculate_wm - calculate watermark level
560 * @clock_in_khz: pixel clock
561 * @wm: chip FIFO params
562 * @cpp: bytes per pixel
563 * @latency_ns: memory latency for the platform
564 *
565 * Calculate the watermark level (the level at which the display plane will
566 * start fetching from memory again). Each chip has a different display
567 * FIFO size and allocation, so the caller needs to figure that out and pass
568 * in the correct intel_watermark_params structure.
569 *
570 * As the pixel clock runs, the FIFO will be drained at a rate that depends
571 * on the pixel size. When it reaches the watermark level, it'll start
572 * fetching FIFO line sized based chunks from memory until the FIFO fills
573 * past the watermark point. If the FIFO drains completely, a FIFO underrun
574 * will occur, and a display engine hang could result.
575 */
576 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
577 const struct intel_watermark_params *wm,
578 int fifo_size, int cpp,
579 unsigned long latency_ns)
580 {
581 long entries_required, wm_size;
582
583 /*
584 * Note: we need to make sure we don't overflow for various clock &
585 * latency values.
586 * clocks go from a few thousand to several hundred thousand.
587 * latency is usually a few thousand
588 */
589 entries_required = ((clock_in_khz / 1000) * cpp * latency_ns) /
590 1000;
591 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
592
593 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
594
595 wm_size = fifo_size - (entries_required + wm->guard_size);
596
597 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
598
599 /* Don't promote wm_size to unsigned... */
600 if (wm_size > (long)wm->max_wm)
601 wm_size = wm->max_wm;
602 if (wm_size <= 0)
603 wm_size = wm->default_wm;
604
605 /*
606 * Bspec seems to indicate that the value shouldn't be lower than
607 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
608 * Lets go for 8 which is the burst size since certain platforms
609 * already use a hardcoded 8 (which is what the spec says should be
610 * done).
611 */
612 if (wm_size <= 8)
613 wm_size = 8;
614
615 return wm_size;
616 }
617
618 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
619 {
620 struct drm_crtc *crtc, *enabled = NULL;
621
622 for_each_crtc(dev, crtc) {
623 if (intel_crtc_active(crtc)) {
624 if (enabled)
625 return NULL;
626 enabled = crtc;
627 }
628 }
629
630 return enabled;
631 }
632
633 static void pineview_update_wm(struct drm_crtc *unused_crtc)
634 {
635 struct drm_device *dev = unused_crtc->dev;
636 struct drm_i915_private *dev_priv = dev->dev_private;
637 struct drm_crtc *crtc;
638 const struct cxsr_latency *latency;
639 u32 reg;
640 unsigned long wm;
641
642 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
643 dev_priv->fsb_freq, dev_priv->mem_freq);
644 if (!latency) {
645 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
646 intel_set_memory_cxsr(dev_priv, false);
647 return;
648 }
649
650 crtc = single_enabled_crtc(dev);
651 if (crtc) {
652 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
653 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
654 int clock = adjusted_mode->crtc_clock;
655
656 /* Display SR */
657 wm = intel_calculate_wm(clock, &pineview_display_wm,
658 pineview_display_wm.fifo_size,
659 cpp, latency->display_sr);
660 reg = I915_READ(DSPFW1);
661 reg &= ~DSPFW_SR_MASK;
662 reg |= FW_WM(wm, SR);
663 I915_WRITE(DSPFW1, reg);
664 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
665
666 /* cursor SR */
667 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
668 pineview_display_wm.fifo_size,
669 cpp, latency->cursor_sr);
670 reg = I915_READ(DSPFW3);
671 reg &= ~DSPFW_CURSOR_SR_MASK;
672 reg |= FW_WM(wm, CURSOR_SR);
673 I915_WRITE(DSPFW3, reg);
674
675 /* Display HPLL off SR */
676 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
677 pineview_display_hplloff_wm.fifo_size,
678 cpp, latency->display_hpll_disable);
679 reg = I915_READ(DSPFW3);
680 reg &= ~DSPFW_HPLL_SR_MASK;
681 reg |= FW_WM(wm, HPLL_SR);
682 I915_WRITE(DSPFW3, reg);
683
684 /* cursor HPLL off SR */
685 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
686 pineview_display_hplloff_wm.fifo_size,
687 cpp, latency->cursor_hpll_disable);
688 reg = I915_READ(DSPFW3);
689 reg &= ~DSPFW_HPLL_CURSOR_MASK;
690 reg |= FW_WM(wm, HPLL_CURSOR);
691 I915_WRITE(DSPFW3, reg);
692 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
693
694 intel_set_memory_cxsr(dev_priv, true);
695 } else {
696 intel_set_memory_cxsr(dev_priv, false);
697 }
698 }
699
700 static bool g4x_compute_wm0(struct drm_device *dev,
701 int plane,
702 const struct intel_watermark_params *display,
703 int display_latency_ns,
704 const struct intel_watermark_params *cursor,
705 int cursor_latency_ns,
706 int *plane_wm,
707 int *cursor_wm)
708 {
709 struct drm_crtc *crtc;
710 const struct drm_display_mode *adjusted_mode;
711 int htotal, hdisplay, clock, cpp;
712 int line_time_us, line_count;
713 int entries, tlb_miss;
714
715 crtc = intel_get_crtc_for_plane(dev, plane);
716 if (!intel_crtc_active(crtc)) {
717 *cursor_wm = cursor->guard_size;
718 *plane_wm = display->guard_size;
719 return false;
720 }
721
722 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
723 clock = adjusted_mode->crtc_clock;
724 htotal = adjusted_mode->crtc_htotal;
725 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
726 cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
727
728 /* Use the small buffer method to calculate plane watermark */
729 entries = ((clock * cpp / 1000) * display_latency_ns) / 1000;
730 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
731 if (tlb_miss > 0)
732 entries += tlb_miss;
733 entries = DIV_ROUND_UP(entries, display->cacheline_size);
734 *plane_wm = entries + display->guard_size;
735 if (*plane_wm > (int)display->max_wm)
736 *plane_wm = display->max_wm;
737
738 /* Use the large buffer method to calculate cursor watermark */
739 line_time_us = max(htotal * 1000 / clock, 1);
740 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
741 entries = line_count * crtc->cursor->state->crtc_w * cpp;
742 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
743 if (tlb_miss > 0)
744 entries += tlb_miss;
745 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
746 *cursor_wm = entries + cursor->guard_size;
747 if (*cursor_wm > (int)cursor->max_wm)
748 *cursor_wm = (int)cursor->max_wm;
749
750 return true;
751 }
752
753 /*
754 * Check the wm result.
755 *
756 * If any calculated watermark values is larger than the maximum value that
757 * can be programmed into the associated watermark register, that watermark
758 * must be disabled.
759 */
760 static bool g4x_check_srwm(struct drm_device *dev,
761 int display_wm, int cursor_wm,
762 const struct intel_watermark_params *display,
763 const struct intel_watermark_params *cursor)
764 {
765 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
766 display_wm, cursor_wm);
767
768 if (display_wm > display->max_wm) {
769 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
770 display_wm, display->max_wm);
771 return false;
772 }
773
774 if (cursor_wm > cursor->max_wm) {
775 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
776 cursor_wm, cursor->max_wm);
777 return false;
778 }
779
780 if (!(display_wm || cursor_wm)) {
781 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
782 return false;
783 }
784
785 return true;
786 }
787
788 static bool g4x_compute_srwm(struct drm_device *dev,
789 int plane,
790 int latency_ns,
791 const struct intel_watermark_params *display,
792 const struct intel_watermark_params *cursor,
793 int *display_wm, int *cursor_wm)
794 {
795 struct drm_crtc *crtc;
796 const struct drm_display_mode *adjusted_mode;
797 int hdisplay, htotal, cpp, clock;
798 unsigned long line_time_us;
799 int line_count, line_size;
800 int small, large;
801 int entries;
802
803 if (!latency_ns) {
804 *display_wm = *cursor_wm = 0;
805 return false;
806 }
807
808 crtc = intel_get_crtc_for_plane(dev, plane);
809 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
810 clock = adjusted_mode->crtc_clock;
811 htotal = adjusted_mode->crtc_htotal;
812 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
813 cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
814
815 line_time_us = max(htotal * 1000 / clock, 1);
816 line_count = (latency_ns / line_time_us + 1000) / 1000;
817 line_size = hdisplay * cpp;
818
819 /* Use the minimum of the small and large buffer method for primary */
820 small = ((clock * cpp / 1000) * latency_ns) / 1000;
821 large = line_count * line_size;
822
823 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
824 *display_wm = entries + display->guard_size;
825
826 /* calculate the self-refresh watermark for display cursor */
827 entries = line_count * cpp * crtc->cursor->state->crtc_w;
828 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
829 *cursor_wm = entries + cursor->guard_size;
830
831 return g4x_check_srwm(dev,
832 *display_wm, *cursor_wm,
833 display, cursor);
834 }
835
836 #define FW_WM_VLV(value, plane) \
837 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
838
839 static void vlv_write_wm_values(struct intel_crtc *crtc,
840 const struct vlv_wm_values *wm)
841 {
842 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
843 enum pipe pipe = crtc->pipe;
844
845 I915_WRITE(VLV_DDL(pipe),
846 (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
847 (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
848 (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
849 (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
850
851 I915_WRITE(DSPFW1,
852 FW_WM(wm->sr.plane, SR) |
853 FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
854 FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
855 FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
856 I915_WRITE(DSPFW2,
857 FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
858 FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
859 FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
860 I915_WRITE(DSPFW3,
861 FW_WM(wm->sr.cursor, CURSOR_SR));
862
863 if (IS_CHERRYVIEW(dev_priv)) {
864 I915_WRITE(DSPFW7_CHV,
865 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
866 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
867 I915_WRITE(DSPFW8_CHV,
868 FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
869 FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
870 I915_WRITE(DSPFW9_CHV,
871 FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
872 FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
873 I915_WRITE(DSPHOWM,
874 FW_WM(wm->sr.plane >> 9, SR_HI) |
875 FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
876 FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
877 FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
878 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
879 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
880 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
881 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
882 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
883 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
884 } else {
885 I915_WRITE(DSPFW7,
886 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
887 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
888 I915_WRITE(DSPHOWM,
889 FW_WM(wm->sr.plane >> 9, SR_HI) |
890 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
891 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
892 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
893 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
894 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
895 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
896 }
897
898 /* zero (unused) WM1 watermarks */
899 I915_WRITE(DSPFW4, 0);
900 I915_WRITE(DSPFW5, 0);
901 I915_WRITE(DSPFW6, 0);
902 I915_WRITE(DSPHOWM1, 0);
903
904 POSTING_READ(DSPFW1);
905 }
906
907 #undef FW_WM_VLV
908
909 enum vlv_wm_level {
910 VLV_WM_LEVEL_PM2,
911 VLV_WM_LEVEL_PM5,
912 VLV_WM_LEVEL_DDR_DVFS,
913 };
914
915 /* latency must be in 0.1us units. */
916 static unsigned int vlv_wm_method2(unsigned int pixel_rate,
917 unsigned int pipe_htotal,
918 unsigned int horiz_pixels,
919 unsigned int cpp,
920 unsigned int latency)
921 {
922 unsigned int ret;
923
924 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
925 ret = (ret + 1) * horiz_pixels * cpp;
926 ret = DIV_ROUND_UP(ret, 64);
927
928 return ret;
929 }
930
931 static void vlv_setup_wm_latency(struct drm_device *dev)
932 {
933 struct drm_i915_private *dev_priv = dev->dev_private;
934
935 /* all latencies in usec */
936 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
937
938 dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
939
940 if (IS_CHERRYVIEW(dev_priv)) {
941 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
942 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
943
944 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
945 }
946 }
947
948 static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
949 struct intel_crtc *crtc,
950 const struct intel_plane_state *state,
951 int level)
952 {
953 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
954 int clock, htotal, cpp, width, wm;
955
956 if (dev_priv->wm.pri_latency[level] == 0)
957 return USHRT_MAX;
958
959 if (!state->visible)
960 return 0;
961
962 cpp = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
963 clock = crtc->config->base.adjusted_mode.crtc_clock;
964 htotal = crtc->config->base.adjusted_mode.crtc_htotal;
965 width = crtc->config->pipe_src_w;
966 if (WARN_ON(htotal == 0))
967 htotal = 1;
968
969 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
970 /*
971 * FIXME the formula gives values that are
972 * too big for the cursor FIFO, and hence we
973 * would never be able to use cursors. For
974 * now just hardcode the watermark.
975 */
976 wm = 63;
977 } else {
978 wm = vlv_wm_method2(clock, htotal, width, cpp,
979 dev_priv->wm.pri_latency[level] * 10);
980 }
981
982 return min_t(int, wm, USHRT_MAX);
983 }
984
985 static void vlv_compute_fifo(struct intel_crtc *crtc)
986 {
987 struct drm_device *dev = crtc->base.dev;
988 struct vlv_wm_state *wm_state = &crtc->wm_state;
989 struct intel_plane *plane;
990 unsigned int total_rate = 0;
991 const int fifo_size = 512 - 1;
992 int fifo_extra, fifo_left = fifo_size;
993
994 for_each_intel_plane_on_crtc(dev, crtc, plane) {
995 struct intel_plane_state *state =
996 to_intel_plane_state(plane->base.state);
997
998 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
999 continue;
1000
1001 if (state->visible) {
1002 wm_state->num_active_planes++;
1003 total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1004 }
1005 }
1006
1007 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1008 struct intel_plane_state *state =
1009 to_intel_plane_state(plane->base.state);
1010 unsigned int rate;
1011
1012 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1013 plane->wm.fifo_size = 63;
1014 continue;
1015 }
1016
1017 if (!state->visible) {
1018 plane->wm.fifo_size = 0;
1019 continue;
1020 }
1021
1022 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1023 plane->wm.fifo_size = fifo_size * rate / total_rate;
1024 fifo_left -= plane->wm.fifo_size;
1025 }
1026
1027 fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1028
1029 /* spread the remainder evenly */
1030 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1031 int plane_extra;
1032
1033 if (fifo_left == 0)
1034 break;
1035
1036 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1037 continue;
1038
1039 /* give it all to the first plane if none are active */
1040 if (plane->wm.fifo_size == 0 &&
1041 wm_state->num_active_planes)
1042 continue;
1043
1044 plane_extra = min(fifo_extra, fifo_left);
1045 plane->wm.fifo_size += plane_extra;
1046 fifo_left -= plane_extra;
1047 }
1048
1049 WARN_ON(fifo_left != 0);
1050 }
1051
1052 static void vlv_invert_wms(struct intel_crtc *crtc)
1053 {
1054 struct vlv_wm_state *wm_state = &crtc->wm_state;
1055 int level;
1056
1057 for (level = 0; level < wm_state->num_levels; level++) {
1058 struct drm_device *dev = crtc->base.dev;
1059 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1060 struct intel_plane *plane;
1061
1062 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1063 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1064
1065 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1066 switch (plane->base.type) {
1067 int sprite;
1068 case DRM_PLANE_TYPE_CURSOR:
1069 wm_state->wm[level].cursor = plane->wm.fifo_size -
1070 wm_state->wm[level].cursor;
1071 break;
1072 case DRM_PLANE_TYPE_PRIMARY:
1073 wm_state->wm[level].primary = plane->wm.fifo_size -
1074 wm_state->wm[level].primary;
1075 break;
1076 case DRM_PLANE_TYPE_OVERLAY:
1077 sprite = plane->plane;
1078 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1079 wm_state->wm[level].sprite[sprite];
1080 break;
1081 }
1082 }
1083 }
1084 }
1085
1086 static void vlv_compute_wm(struct intel_crtc *crtc)
1087 {
1088 struct drm_device *dev = crtc->base.dev;
1089 struct vlv_wm_state *wm_state = &crtc->wm_state;
1090 struct intel_plane *plane;
1091 int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1092 int level;
1093
1094 memset(wm_state, 0, sizeof(*wm_state));
1095
1096 wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
1097 wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
1098
1099 wm_state->num_active_planes = 0;
1100
1101 vlv_compute_fifo(crtc);
1102
1103 if (wm_state->num_active_planes != 1)
1104 wm_state->cxsr = false;
1105
1106 if (wm_state->cxsr) {
1107 for (level = 0; level < wm_state->num_levels; level++) {
1108 wm_state->sr[level].plane = sr_fifo_size;
1109 wm_state->sr[level].cursor = 63;
1110 }
1111 }
1112
1113 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1114 struct intel_plane_state *state =
1115 to_intel_plane_state(plane->base.state);
1116
1117 if (!state->visible)
1118 continue;
1119
1120 /* normal watermarks */
1121 for (level = 0; level < wm_state->num_levels; level++) {
1122 int wm = vlv_compute_wm_level(plane, crtc, state, level);
1123 int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1124
1125 /* hack */
1126 if (WARN_ON(level == 0 && wm > max_wm))
1127 wm = max_wm;
1128
1129 if (wm > plane->wm.fifo_size)
1130 break;
1131
1132 switch (plane->base.type) {
1133 int sprite;
1134 case DRM_PLANE_TYPE_CURSOR:
1135 wm_state->wm[level].cursor = wm;
1136 break;
1137 case DRM_PLANE_TYPE_PRIMARY:
1138 wm_state->wm[level].primary = wm;
1139 break;
1140 case DRM_PLANE_TYPE_OVERLAY:
1141 sprite = plane->plane;
1142 wm_state->wm[level].sprite[sprite] = wm;
1143 break;
1144 }
1145 }
1146
1147 wm_state->num_levels = level;
1148
1149 if (!wm_state->cxsr)
1150 continue;
1151
1152 /* maxfifo watermarks */
1153 switch (plane->base.type) {
1154 int sprite, level;
1155 case DRM_PLANE_TYPE_CURSOR:
1156 for (level = 0; level < wm_state->num_levels; level++)
1157 wm_state->sr[level].cursor =
1158 wm_state->wm[level].cursor;
1159 break;
1160 case DRM_PLANE_TYPE_PRIMARY:
1161 for (level = 0; level < wm_state->num_levels; level++)
1162 wm_state->sr[level].plane =
1163 min(wm_state->sr[level].plane,
1164 wm_state->wm[level].primary);
1165 break;
1166 case DRM_PLANE_TYPE_OVERLAY:
1167 sprite = plane->plane;
1168 for (level = 0; level < wm_state->num_levels; level++)
1169 wm_state->sr[level].plane =
1170 min(wm_state->sr[level].plane,
1171 wm_state->wm[level].sprite[sprite]);
1172 break;
1173 }
1174 }
1175
1176 /* clear any (partially) filled invalid levels */
1177 for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
1178 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1179 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1180 }
1181
1182 vlv_invert_wms(crtc);
1183 }
1184
1185 #define VLV_FIFO(plane, value) \
1186 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1187
1188 static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1189 {
1190 struct drm_device *dev = crtc->base.dev;
1191 struct drm_i915_private *dev_priv = to_i915(dev);
1192 struct intel_plane *plane;
1193 int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1194
1195 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1196 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1197 WARN_ON(plane->wm.fifo_size != 63);
1198 continue;
1199 }
1200
1201 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1202 sprite0_start = plane->wm.fifo_size;
1203 else if (plane->plane == 0)
1204 sprite1_start = sprite0_start + plane->wm.fifo_size;
1205 else
1206 fifo_size = sprite1_start + plane->wm.fifo_size;
1207 }
1208
1209 WARN_ON(fifo_size != 512 - 1);
1210
1211 DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1212 pipe_name(crtc->pipe), sprite0_start,
1213 sprite1_start, fifo_size);
1214
1215 switch (crtc->pipe) {
1216 uint32_t dsparb, dsparb2, dsparb3;
1217 case PIPE_A:
1218 dsparb = I915_READ(DSPARB);
1219 dsparb2 = I915_READ(DSPARB2);
1220
1221 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1222 VLV_FIFO(SPRITEB, 0xff));
1223 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1224 VLV_FIFO(SPRITEB, sprite1_start));
1225
1226 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1227 VLV_FIFO(SPRITEB_HI, 0x1));
1228 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1229 VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1230
1231 I915_WRITE(DSPARB, dsparb);
1232 I915_WRITE(DSPARB2, dsparb2);
1233 break;
1234 case PIPE_B:
1235 dsparb = I915_READ(DSPARB);
1236 dsparb2 = I915_READ(DSPARB2);
1237
1238 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1239 VLV_FIFO(SPRITED, 0xff));
1240 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1241 VLV_FIFO(SPRITED, sprite1_start));
1242
1243 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1244 VLV_FIFO(SPRITED_HI, 0xff));
1245 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1246 VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1247
1248 I915_WRITE(DSPARB, dsparb);
1249 I915_WRITE(DSPARB2, dsparb2);
1250 break;
1251 case PIPE_C:
1252 dsparb3 = I915_READ(DSPARB3);
1253 dsparb2 = I915_READ(DSPARB2);
1254
1255 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1256 VLV_FIFO(SPRITEF, 0xff));
1257 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1258 VLV_FIFO(SPRITEF, sprite1_start));
1259
1260 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1261 VLV_FIFO(SPRITEF_HI, 0xff));
1262 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1263 VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1264
1265 I915_WRITE(DSPARB3, dsparb3);
1266 I915_WRITE(DSPARB2, dsparb2);
1267 break;
1268 default:
1269 break;
1270 }
1271 }
1272
1273 #undef VLV_FIFO
1274
1275 static void vlv_merge_wm(struct drm_device *dev,
1276 struct vlv_wm_values *wm)
1277 {
1278 struct intel_crtc *crtc;
1279 int num_active_crtcs = 0;
1280
1281 wm->level = to_i915(dev)->wm.max_level;
1282 wm->cxsr = true;
1283
1284 for_each_intel_crtc(dev, crtc) {
1285 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1286
1287 if (!crtc->active)
1288 continue;
1289
1290 if (!wm_state->cxsr)
1291 wm->cxsr = false;
1292
1293 num_active_crtcs++;
1294 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1295 }
1296
1297 if (num_active_crtcs != 1)
1298 wm->cxsr = false;
1299
1300 if (num_active_crtcs > 1)
1301 wm->level = VLV_WM_LEVEL_PM2;
1302
1303 for_each_intel_crtc(dev, crtc) {
1304 struct vlv_wm_state *wm_state = &crtc->wm_state;
1305 enum pipe pipe = crtc->pipe;
1306
1307 if (!crtc->active)
1308 continue;
1309
1310 wm->pipe[pipe] = wm_state->wm[wm->level];
1311 if (wm->cxsr)
1312 wm->sr = wm_state->sr[wm->level];
1313
1314 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1315 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1316 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1317 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1318 }
1319 }
1320
1321 static void vlv_update_wm(struct drm_crtc *crtc)
1322 {
1323 struct drm_device *dev = crtc->dev;
1324 struct drm_i915_private *dev_priv = dev->dev_private;
1325 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1326 enum pipe pipe = intel_crtc->pipe;
1327 struct vlv_wm_values wm = {};
1328
1329 vlv_compute_wm(intel_crtc);
1330 vlv_merge_wm(dev, &wm);
1331
1332 if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1333 /* FIXME should be part of crtc atomic commit */
1334 vlv_pipe_set_fifo_size(intel_crtc);
1335 return;
1336 }
1337
1338 if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1339 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1340 chv_set_memory_dvfs(dev_priv, false);
1341
1342 if (wm.level < VLV_WM_LEVEL_PM5 &&
1343 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1344 chv_set_memory_pm5(dev_priv, false);
1345
1346 if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
1347 intel_set_memory_cxsr(dev_priv, false);
1348
1349 /* FIXME should be part of crtc atomic commit */
1350 vlv_pipe_set_fifo_size(intel_crtc);
1351
1352 vlv_write_wm_values(intel_crtc, &wm);
1353
1354 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1355 "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1356 pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1357 wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1358 wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1359
1360 if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
1361 intel_set_memory_cxsr(dev_priv, true);
1362
1363 if (wm.level >= VLV_WM_LEVEL_PM5 &&
1364 dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1365 chv_set_memory_pm5(dev_priv, true);
1366
1367 if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1368 dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1369 chv_set_memory_dvfs(dev_priv, true);
1370
1371 dev_priv->wm.vlv = wm;
1372 }
1373
1374 #define single_plane_enabled(mask) is_power_of_2(mask)
1375
1376 static void g4x_update_wm(struct drm_crtc *crtc)
1377 {
1378 struct drm_device *dev = crtc->dev;
1379 static const int sr_latency_ns = 12000;
1380 struct drm_i915_private *dev_priv = dev->dev_private;
1381 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1382 int plane_sr, cursor_sr;
1383 unsigned int enabled = 0;
1384 bool cxsr_enabled;
1385
1386 if (g4x_compute_wm0(dev, PIPE_A,
1387 &g4x_wm_info, pessimal_latency_ns,
1388 &g4x_cursor_wm_info, pessimal_latency_ns,
1389 &planea_wm, &cursora_wm))
1390 enabled |= 1 << PIPE_A;
1391
1392 if (g4x_compute_wm0(dev, PIPE_B,
1393 &g4x_wm_info, pessimal_latency_ns,
1394 &g4x_cursor_wm_info, pessimal_latency_ns,
1395 &planeb_wm, &cursorb_wm))
1396 enabled |= 1 << PIPE_B;
1397
1398 if (single_plane_enabled(enabled) &&
1399 g4x_compute_srwm(dev, ffs(enabled) - 1,
1400 sr_latency_ns,
1401 &g4x_wm_info,
1402 &g4x_cursor_wm_info,
1403 &plane_sr, &cursor_sr)) {
1404 cxsr_enabled = true;
1405 } else {
1406 cxsr_enabled = false;
1407 intel_set_memory_cxsr(dev_priv, false);
1408 plane_sr = cursor_sr = 0;
1409 }
1410
1411 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1412 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1413 planea_wm, cursora_wm,
1414 planeb_wm, cursorb_wm,
1415 plane_sr, cursor_sr);
1416
1417 I915_WRITE(DSPFW1,
1418 FW_WM(plane_sr, SR) |
1419 FW_WM(cursorb_wm, CURSORB) |
1420 FW_WM(planeb_wm, PLANEB) |
1421 FW_WM(planea_wm, PLANEA));
1422 I915_WRITE(DSPFW2,
1423 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1424 FW_WM(cursora_wm, CURSORA));
1425 /* HPLL off in SR has some issues on G4x... disable it */
1426 I915_WRITE(DSPFW3,
1427 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1428 FW_WM(cursor_sr, CURSOR_SR));
1429
1430 if (cxsr_enabled)
1431 intel_set_memory_cxsr(dev_priv, true);
1432 }
1433
1434 static void i965_update_wm(struct drm_crtc *unused_crtc)
1435 {
1436 struct drm_device *dev = unused_crtc->dev;
1437 struct drm_i915_private *dev_priv = dev->dev_private;
1438 struct drm_crtc *crtc;
1439 int srwm = 1;
1440 int cursor_sr = 16;
1441 bool cxsr_enabled;
1442
1443 /* Calc sr entries for one plane configs */
1444 crtc = single_enabled_crtc(dev);
1445 if (crtc) {
1446 /* self-refresh has much higher latency */
1447 static const int sr_latency_ns = 12000;
1448 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1449 int clock = adjusted_mode->crtc_clock;
1450 int htotal = adjusted_mode->crtc_htotal;
1451 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
1452 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
1453 unsigned long line_time_us;
1454 int entries;
1455
1456 line_time_us = max(htotal * 1000 / clock, 1);
1457
1458 /* Use ns/us then divide to preserve precision */
1459 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1460 cpp * hdisplay;
1461 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1462 srwm = I965_FIFO_SIZE - entries;
1463 if (srwm < 0)
1464 srwm = 1;
1465 srwm &= 0x1ff;
1466 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1467 entries, srwm);
1468
1469 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1470 cpp * crtc->cursor->state->crtc_w;
1471 entries = DIV_ROUND_UP(entries,
1472 i965_cursor_wm_info.cacheline_size);
1473 cursor_sr = i965_cursor_wm_info.fifo_size -
1474 (entries + i965_cursor_wm_info.guard_size);
1475
1476 if (cursor_sr > i965_cursor_wm_info.max_wm)
1477 cursor_sr = i965_cursor_wm_info.max_wm;
1478
1479 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1480 "cursor %d\n", srwm, cursor_sr);
1481
1482 cxsr_enabled = true;
1483 } else {
1484 cxsr_enabled = false;
1485 /* Turn off self refresh if both pipes are enabled */
1486 intel_set_memory_cxsr(dev_priv, false);
1487 }
1488
1489 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1490 srwm);
1491
1492 /* 965 has limitations... */
1493 I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1494 FW_WM(8, CURSORB) |
1495 FW_WM(8, PLANEB) |
1496 FW_WM(8, PLANEA));
1497 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1498 FW_WM(8, PLANEC_OLD));
1499 /* update cursor SR watermark */
1500 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
1501
1502 if (cxsr_enabled)
1503 intel_set_memory_cxsr(dev_priv, true);
1504 }
1505
1506 #undef FW_WM
1507
1508 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1509 {
1510 struct drm_device *dev = unused_crtc->dev;
1511 struct drm_i915_private *dev_priv = dev->dev_private;
1512 const struct intel_watermark_params *wm_info;
1513 uint32_t fwater_lo;
1514 uint32_t fwater_hi;
1515 int cwm, srwm = 1;
1516 int fifo_size;
1517 int planea_wm, planeb_wm;
1518 struct drm_crtc *crtc, *enabled = NULL;
1519
1520 if (IS_I945GM(dev))
1521 wm_info = &i945_wm_info;
1522 else if (!IS_GEN2(dev))
1523 wm_info = &i915_wm_info;
1524 else
1525 wm_info = &i830_a_wm_info;
1526
1527 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1528 crtc = intel_get_crtc_for_plane(dev, 0);
1529 if (intel_crtc_active(crtc)) {
1530 const struct drm_display_mode *adjusted_mode;
1531 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
1532 if (IS_GEN2(dev))
1533 cpp = 4;
1534
1535 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1536 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1537 wm_info, fifo_size, cpp,
1538 pessimal_latency_ns);
1539 enabled = crtc;
1540 } else {
1541 planea_wm = fifo_size - wm_info->guard_size;
1542 if (planea_wm > (long)wm_info->max_wm)
1543 planea_wm = wm_info->max_wm;
1544 }
1545
1546 if (IS_GEN2(dev))
1547 wm_info = &i830_bc_wm_info;
1548
1549 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1550 crtc = intel_get_crtc_for_plane(dev, 1);
1551 if (intel_crtc_active(crtc)) {
1552 const struct drm_display_mode *adjusted_mode;
1553 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
1554 if (IS_GEN2(dev))
1555 cpp = 4;
1556
1557 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1558 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1559 wm_info, fifo_size, cpp,
1560 pessimal_latency_ns);
1561 if (enabled == NULL)
1562 enabled = crtc;
1563 else
1564 enabled = NULL;
1565 } else {
1566 planeb_wm = fifo_size - wm_info->guard_size;
1567 if (planeb_wm > (long)wm_info->max_wm)
1568 planeb_wm = wm_info->max_wm;
1569 }
1570
1571 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1572
1573 if (IS_I915GM(dev) && enabled) {
1574 struct drm_i915_gem_object *obj;
1575
1576 obj = intel_fb_obj(enabled->primary->state->fb);
1577
1578 /* self-refresh seems busted with untiled */
1579 if (obj->tiling_mode == I915_TILING_NONE)
1580 enabled = NULL;
1581 }
1582
1583 /*
1584 * Overlay gets an aggressive default since video jitter is bad.
1585 */
1586 cwm = 2;
1587
1588 /* Play safe and disable self-refresh before adjusting watermarks. */
1589 intel_set_memory_cxsr(dev_priv, false);
1590
1591 /* Calc sr entries for one plane configs */
1592 if (HAS_FW_BLC(dev) && enabled) {
1593 /* self-refresh has much higher latency */
1594 static const int sr_latency_ns = 6000;
1595 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode;
1596 int clock = adjusted_mode->crtc_clock;
1597 int htotal = adjusted_mode->crtc_htotal;
1598 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
1599 int cpp = drm_format_plane_cpp(enabled->primary->state->fb->pixel_format, 0);
1600 unsigned long line_time_us;
1601 int entries;
1602
1603 line_time_us = max(htotal * 1000 / clock, 1);
1604
1605 /* Use ns/us then divide to preserve precision */
1606 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1607 cpp * hdisplay;
1608 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1609 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1610 srwm = wm_info->fifo_size - entries;
1611 if (srwm < 0)
1612 srwm = 1;
1613
1614 if (IS_I945G(dev) || IS_I945GM(dev))
1615 I915_WRITE(FW_BLC_SELF,
1616 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1617 else if (IS_I915GM(dev))
1618 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1619 }
1620
1621 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1622 planea_wm, planeb_wm, cwm, srwm);
1623
1624 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1625 fwater_hi = (cwm & 0x1f);
1626
1627 /* Set request length to 8 cachelines per fetch */
1628 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1629 fwater_hi = fwater_hi | (1 << 8);
1630
1631 I915_WRITE(FW_BLC, fwater_lo);
1632 I915_WRITE(FW_BLC2, fwater_hi);
1633
1634 if (enabled)
1635 intel_set_memory_cxsr(dev_priv, true);
1636 }
1637
1638 static void i845_update_wm(struct drm_crtc *unused_crtc)
1639 {
1640 struct drm_device *dev = unused_crtc->dev;
1641 struct drm_i915_private *dev_priv = dev->dev_private;
1642 struct drm_crtc *crtc;
1643 const struct drm_display_mode *adjusted_mode;
1644 uint32_t fwater_lo;
1645 int planea_wm;
1646
1647 crtc = single_enabled_crtc(dev);
1648 if (crtc == NULL)
1649 return;
1650
1651 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1652 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1653 &i845_wm_info,
1654 dev_priv->display.get_fifo_size(dev, 0),
1655 4, pessimal_latency_ns);
1656 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1657 fwater_lo |= (3<<8) | planea_wm;
1658
1659 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1660
1661 I915_WRITE(FW_BLC, fwater_lo);
1662 }
1663
1664 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
1665 {
1666 uint32_t pixel_rate;
1667
1668 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
1669
1670 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1671 * adjust the pixel_rate here. */
1672
1673 if (pipe_config->pch_pfit.enabled) {
1674 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1675 uint32_t pfit_size = pipe_config->pch_pfit.size;
1676
1677 pipe_w = pipe_config->pipe_src_w;
1678 pipe_h = pipe_config->pipe_src_h;
1679
1680 pfit_w = (pfit_size >> 16) & 0xFFFF;
1681 pfit_h = pfit_size & 0xFFFF;
1682 if (pipe_w < pfit_w)
1683 pipe_w = pfit_w;
1684 if (pipe_h < pfit_h)
1685 pipe_h = pfit_h;
1686
1687 if (WARN_ON(!pfit_w || !pfit_h))
1688 return pixel_rate;
1689
1690 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1691 pfit_w * pfit_h);
1692 }
1693
1694 return pixel_rate;
1695 }
1696
1697 /* latency must be in 0.1us units. */
1698 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
1699 {
1700 uint64_t ret;
1701
1702 if (WARN(latency == 0, "Latency value missing\n"))
1703 return UINT_MAX;
1704
1705 ret = (uint64_t) pixel_rate * cpp * latency;
1706 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1707
1708 return ret;
1709 }
1710
1711 /* latency must be in 0.1us units. */
1712 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1713 uint32_t horiz_pixels, uint8_t cpp,
1714 uint32_t latency)
1715 {
1716 uint32_t ret;
1717
1718 if (WARN(latency == 0, "Latency value missing\n"))
1719 return UINT_MAX;
1720 if (WARN_ON(!pipe_htotal))
1721 return UINT_MAX;
1722
1723 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1724 ret = (ret + 1) * horiz_pixels * cpp;
1725 ret = DIV_ROUND_UP(ret, 64) + 2;
1726 return ret;
1727 }
1728
1729 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1730 uint8_t cpp)
1731 {
1732 /*
1733 * Neither of these should be possible since this function shouldn't be
1734 * called if the CRTC is off or the plane is invisible. But let's be
1735 * extra paranoid to avoid a potential divide-by-zero if we screw up
1736 * elsewhere in the driver.
1737 */
1738 if (WARN_ON(!cpp))
1739 return 0;
1740 if (WARN_ON(!horiz_pixels))
1741 return 0;
1742
1743 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
1744 }
1745
1746 struct ilk_wm_maximums {
1747 uint16_t pri;
1748 uint16_t spr;
1749 uint16_t cur;
1750 uint16_t fbc;
1751 };
1752
1753 /*
1754 * For both WM_PIPE and WM_LP.
1755 * mem_value must be in 0.1us units.
1756 */
1757 static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
1758 const struct intel_plane_state *pstate,
1759 uint32_t mem_value,
1760 bool is_lp)
1761 {
1762 int cpp = pstate->base.fb ?
1763 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1764 uint32_t method1, method2;
1765
1766 if (!cstate->base.active || !pstate->visible)
1767 return 0;
1768
1769 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
1770
1771 if (!is_lp)
1772 return method1;
1773
1774 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1775 cstate->base.adjusted_mode.crtc_htotal,
1776 drm_rect_width(&pstate->dst),
1777 cpp, mem_value);
1778
1779 return min(method1, method2);
1780 }
1781
1782 /*
1783 * For both WM_PIPE and WM_LP.
1784 * mem_value must be in 0.1us units.
1785 */
1786 static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
1787 const struct intel_plane_state *pstate,
1788 uint32_t mem_value)
1789 {
1790 int cpp = pstate->base.fb ?
1791 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1792 uint32_t method1, method2;
1793
1794 if (!cstate->base.active || !pstate->visible)
1795 return 0;
1796
1797 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
1798 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1799 cstate->base.adjusted_mode.crtc_htotal,
1800 drm_rect_width(&pstate->dst),
1801 cpp, mem_value);
1802 return min(method1, method2);
1803 }
1804
1805 /*
1806 * For both WM_PIPE and WM_LP.
1807 * mem_value must be in 0.1us units.
1808 */
1809 static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
1810 const struct intel_plane_state *pstate,
1811 uint32_t mem_value)
1812 {
1813 /*
1814 * We treat the cursor plane as always-on for the purposes of watermark
1815 * calculation. Until we have two-stage watermark programming merged,
1816 * this is necessary to avoid flickering.
1817 */
1818 int cpp = 4;
1819 int width = pstate->visible ? pstate->base.crtc_w : 64;
1820
1821 if (!cstate->base.active)
1822 return 0;
1823
1824 return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1825 cstate->base.adjusted_mode.crtc_htotal,
1826 width, cpp, mem_value);
1827 }
1828
1829 /* Only for WM_LP. */
1830 static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
1831 const struct intel_plane_state *pstate,
1832 uint32_t pri_val)
1833 {
1834 int cpp = pstate->base.fb ?
1835 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1836
1837 if (!cstate->base.active || !pstate->visible)
1838 return 0;
1839
1840 return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->dst), cpp);
1841 }
1842
1843 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1844 {
1845 if (INTEL_INFO(dev)->gen >= 8)
1846 return 3072;
1847 else if (INTEL_INFO(dev)->gen >= 7)
1848 return 768;
1849 else
1850 return 512;
1851 }
1852
1853 static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1854 int level, bool is_sprite)
1855 {
1856 if (INTEL_INFO(dev)->gen >= 8)
1857 /* BDW primary/sprite plane watermarks */
1858 return level == 0 ? 255 : 2047;
1859 else if (INTEL_INFO(dev)->gen >= 7)
1860 /* IVB/HSW primary/sprite plane watermarks */
1861 return level == 0 ? 127 : 1023;
1862 else if (!is_sprite)
1863 /* ILK/SNB primary plane watermarks */
1864 return level == 0 ? 127 : 511;
1865 else
1866 /* ILK/SNB sprite plane watermarks */
1867 return level == 0 ? 63 : 255;
1868 }
1869
1870 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1871 int level)
1872 {
1873 if (INTEL_INFO(dev)->gen >= 7)
1874 return level == 0 ? 63 : 255;
1875 else
1876 return level == 0 ? 31 : 63;
1877 }
1878
1879 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1880 {
1881 if (INTEL_INFO(dev)->gen >= 8)
1882 return 31;
1883 else
1884 return 15;
1885 }
1886
1887 /* Calculate the maximum primary/sprite plane watermark */
1888 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1889 int level,
1890 const struct intel_wm_config *config,
1891 enum intel_ddb_partitioning ddb_partitioning,
1892 bool is_sprite)
1893 {
1894 unsigned int fifo_size = ilk_display_fifo_size(dev);
1895
1896 /* if sprites aren't enabled, sprites get nothing */
1897 if (is_sprite && !config->sprites_enabled)
1898 return 0;
1899
1900 /* HSW allows LP1+ watermarks even with multiple pipes */
1901 if (level == 0 || config->num_pipes_active > 1) {
1902 fifo_size /= INTEL_INFO(dev)->num_pipes;
1903
1904 /*
1905 * For some reason the non self refresh
1906 * FIFO size is only half of the self
1907 * refresh FIFO size on ILK/SNB.
1908 */
1909 if (INTEL_INFO(dev)->gen <= 6)
1910 fifo_size /= 2;
1911 }
1912
1913 if (config->sprites_enabled) {
1914 /* level 0 is always calculated with 1:1 split */
1915 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1916 if (is_sprite)
1917 fifo_size *= 5;
1918 fifo_size /= 6;
1919 } else {
1920 fifo_size /= 2;
1921 }
1922 }
1923
1924 /* clamp to max that the registers can hold */
1925 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
1926 }
1927
1928 /* Calculate the maximum cursor plane watermark */
1929 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
1930 int level,
1931 const struct intel_wm_config *config)
1932 {
1933 /* HSW LP1+ watermarks w/ multiple pipes */
1934 if (level > 0 && config->num_pipes_active > 1)
1935 return 64;
1936
1937 /* otherwise just report max that registers can hold */
1938 return ilk_cursor_wm_reg_max(dev, level);
1939 }
1940
1941 static void ilk_compute_wm_maximums(const struct drm_device *dev,
1942 int level,
1943 const struct intel_wm_config *config,
1944 enum intel_ddb_partitioning ddb_partitioning,
1945 struct ilk_wm_maximums *max)
1946 {
1947 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1948 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1949 max->cur = ilk_cursor_wm_max(dev, level, config);
1950 max->fbc = ilk_fbc_wm_reg_max(dev);
1951 }
1952
1953 static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1954 int level,
1955 struct ilk_wm_maximums *max)
1956 {
1957 max->pri = ilk_plane_wm_reg_max(dev, level, false);
1958 max->spr = ilk_plane_wm_reg_max(dev, level, true);
1959 max->cur = ilk_cursor_wm_reg_max(dev, level);
1960 max->fbc = ilk_fbc_wm_reg_max(dev);
1961 }
1962
1963 static bool ilk_validate_wm_level(int level,
1964 const struct ilk_wm_maximums *max,
1965 struct intel_wm_level *result)
1966 {
1967 bool ret;
1968
1969 /* already determined to be invalid? */
1970 if (!result->enable)
1971 return false;
1972
1973 result->enable = result->pri_val <= max->pri &&
1974 result->spr_val <= max->spr &&
1975 result->cur_val <= max->cur;
1976
1977 ret = result->enable;
1978
1979 /*
1980 * HACK until we can pre-compute everything,
1981 * and thus fail gracefully if LP0 watermarks
1982 * are exceeded...
1983 */
1984 if (level == 0 && !result->enable) {
1985 if (result->pri_val > max->pri)
1986 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1987 level, result->pri_val, max->pri);
1988 if (result->spr_val > max->spr)
1989 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1990 level, result->spr_val, max->spr);
1991 if (result->cur_val > max->cur)
1992 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1993 level, result->cur_val, max->cur);
1994
1995 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
1996 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
1997 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
1998 result->enable = true;
1999 }
2000
2001 return ret;
2002 }
2003
2004 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
2005 const struct intel_crtc *intel_crtc,
2006 int level,
2007 struct intel_crtc_state *cstate,
2008 struct intel_plane_state *pristate,
2009 struct intel_plane_state *sprstate,
2010 struct intel_plane_state *curstate,
2011 struct intel_wm_level *result)
2012 {
2013 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2014 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2015 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2016
2017 /* WM1+ latency values stored in 0.5us units */
2018 if (level > 0) {
2019 pri_latency *= 5;
2020 spr_latency *= 5;
2021 cur_latency *= 5;
2022 }
2023
2024 if (pristate) {
2025 result->pri_val = ilk_compute_pri_wm(cstate, pristate,
2026 pri_latency, level);
2027 result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
2028 }
2029
2030 if (sprstate)
2031 result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
2032
2033 if (curstate)
2034 result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
2035
2036 result->enable = true;
2037 }
2038
2039 static uint32_t
2040 hsw_compute_linetime_wm(const struct intel_crtc_state *cstate)
2041 {
2042 const struct intel_atomic_state *intel_state =
2043 to_intel_atomic_state(cstate->base.state);
2044 const struct drm_display_mode *adjusted_mode =
2045 &cstate->base.adjusted_mode;
2046 u32 linetime, ips_linetime;
2047
2048 if (!cstate->base.active)
2049 return 0;
2050 if (WARN_ON(adjusted_mode->crtc_clock == 0))
2051 return 0;
2052 if (WARN_ON(intel_state->cdclk == 0))
2053 return 0;
2054
2055 /* The WM are computed with base on how long it takes to fill a single
2056 * row at the given clock rate, multiplied by 8.
2057 * */
2058 linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2059 adjusted_mode->crtc_clock);
2060 ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2061 intel_state->cdclk);
2062
2063 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2064 PIPE_WM_LINETIME_TIME(linetime);
2065 }
2066
2067 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
2068 {
2069 struct drm_i915_private *dev_priv = dev->dev_private;
2070
2071 if (IS_GEN9(dev)) {
2072 uint32_t val;
2073 int ret, i;
2074 int level, max_level = ilk_wm_max_level(dev);
2075
2076 /* read the first set of memory latencies[0:3] */
2077 val = 0; /* data0 to be programmed to 0 for first set */
2078 mutex_lock(&dev_priv->rps.hw_lock);
2079 ret = sandybridge_pcode_read(dev_priv,
2080 GEN9_PCODE_READ_MEM_LATENCY,
2081 &val);
2082 mutex_unlock(&dev_priv->rps.hw_lock);
2083
2084 if (ret) {
2085 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2086 return;
2087 }
2088
2089 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2090 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2091 GEN9_MEM_LATENCY_LEVEL_MASK;
2092 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2093 GEN9_MEM_LATENCY_LEVEL_MASK;
2094 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2095 GEN9_MEM_LATENCY_LEVEL_MASK;
2096
2097 /* read the second set of memory latencies[4:7] */
2098 val = 1; /* data0 to be programmed to 1 for second set */
2099 mutex_lock(&dev_priv->rps.hw_lock);
2100 ret = sandybridge_pcode_read(dev_priv,
2101 GEN9_PCODE_READ_MEM_LATENCY,
2102 &val);
2103 mutex_unlock(&dev_priv->rps.hw_lock);
2104 if (ret) {
2105 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2106 return;
2107 }
2108
2109 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2110 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2111 GEN9_MEM_LATENCY_LEVEL_MASK;
2112 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2113 GEN9_MEM_LATENCY_LEVEL_MASK;
2114 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2115 GEN9_MEM_LATENCY_LEVEL_MASK;
2116
2117 /*
2118 * WaWmMemoryReadLatency:skl
2119 *
2120 * punit doesn't take into account the read latency so we need
2121 * to add 2us to the various latency levels we retrieve from
2122 * the punit.
2123 * - W0 is a bit special in that it's the only level that
2124 * can't be disabled if we want to have display working, so
2125 * we always add 2us there.
2126 * - For levels >=1, punit returns 0us latency when they are
2127 * disabled, so we respect that and don't add 2us then
2128 *
2129 * Additionally, if a level n (n > 1) has a 0us latency, all
2130 * levels m (m >= n) need to be disabled. We make sure to
2131 * sanitize the values out of the punit to satisfy this
2132 * requirement.
2133 */
2134 wm[0] += 2;
2135 for (level = 1; level <= max_level; level++)
2136 if (wm[level] != 0)
2137 wm[level] += 2;
2138 else {
2139 for (i = level + 1; i <= max_level; i++)
2140 wm[i] = 0;
2141
2142 break;
2143 }
2144 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2145 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2146
2147 wm[0] = (sskpd >> 56) & 0xFF;
2148 if (wm[0] == 0)
2149 wm[0] = sskpd & 0xF;
2150 wm[1] = (sskpd >> 4) & 0xFF;
2151 wm[2] = (sskpd >> 12) & 0xFF;
2152 wm[3] = (sskpd >> 20) & 0x1FF;
2153 wm[4] = (sskpd >> 32) & 0x1FF;
2154 } else if (INTEL_INFO(dev)->gen >= 6) {
2155 uint32_t sskpd = I915_READ(MCH_SSKPD);
2156
2157 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2158 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2159 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2160 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2161 } else if (INTEL_INFO(dev)->gen >= 5) {
2162 uint32_t mltr = I915_READ(MLTR_ILK);
2163
2164 /* ILK primary LP0 latency is 700 ns */
2165 wm[0] = 7;
2166 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2167 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2168 }
2169 }
2170
2171 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2172 {
2173 /* ILK sprite LP0 latency is 1300 ns */
2174 if (IS_GEN5(dev))
2175 wm[0] = 13;
2176 }
2177
2178 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2179 {
2180 /* ILK cursor LP0 latency is 1300 ns */
2181 if (IS_GEN5(dev))
2182 wm[0] = 13;
2183
2184 /* WaDoubleCursorLP3Latency:ivb */
2185 if (IS_IVYBRIDGE(dev))
2186 wm[3] *= 2;
2187 }
2188
2189 int ilk_wm_max_level(const struct drm_device *dev)
2190 {
2191 /* how many WM levels are we expecting */
2192 if (INTEL_INFO(dev)->gen >= 9)
2193 return 7;
2194 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2195 return 4;
2196 else if (INTEL_INFO(dev)->gen >= 6)
2197 return 3;
2198 else
2199 return 2;
2200 }
2201
2202 static void intel_print_wm_latency(struct drm_device *dev,
2203 const char *name,
2204 const uint16_t wm[8])
2205 {
2206 int level, max_level = ilk_wm_max_level(dev);
2207
2208 for (level = 0; level <= max_level; level++) {
2209 unsigned int latency = wm[level];
2210
2211 if (latency == 0) {
2212 DRM_ERROR("%s WM%d latency not provided\n",
2213 name, level);
2214 continue;
2215 }
2216
2217 /*
2218 * - latencies are in us on gen9.
2219 * - before then, WM1+ latency values are in 0.5us units
2220 */
2221 if (IS_GEN9(dev))
2222 latency *= 10;
2223 else if (level > 0)
2224 latency *= 5;
2225
2226 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2227 name, level, wm[level],
2228 latency / 10, latency % 10);
2229 }
2230 }
2231
2232 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2233 uint16_t wm[5], uint16_t min)
2234 {
2235 int level, max_level = ilk_wm_max_level(dev_priv->dev);
2236
2237 if (wm[0] >= min)
2238 return false;
2239
2240 wm[0] = max(wm[0], min);
2241 for (level = 1; level <= max_level; level++)
2242 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2243
2244 return true;
2245 }
2246
2247 static void snb_wm_latency_quirk(struct drm_device *dev)
2248 {
2249 struct drm_i915_private *dev_priv = dev->dev_private;
2250 bool changed;
2251
2252 /*
2253 * The BIOS provided WM memory latency values are often
2254 * inadequate for high resolution displays. Adjust them.
2255 */
2256 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2257 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2258 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2259
2260 if (!changed)
2261 return;
2262
2263 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2264 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2265 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2266 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2267 }
2268
2269 static void ilk_setup_wm_latency(struct drm_device *dev)
2270 {
2271 struct drm_i915_private *dev_priv = dev->dev_private;
2272
2273 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2274
2275 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2276 sizeof(dev_priv->wm.pri_latency));
2277 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2278 sizeof(dev_priv->wm.pri_latency));
2279
2280 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2281 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2282
2283 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2284 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2285 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2286
2287 if (IS_GEN6(dev))
2288 snb_wm_latency_quirk(dev);
2289 }
2290
2291 static void skl_setup_wm_latency(struct drm_device *dev)
2292 {
2293 struct drm_i915_private *dev_priv = dev->dev_private;
2294
2295 intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2296 intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2297 }
2298
2299 static bool ilk_validate_pipe_wm(struct drm_device *dev,
2300 struct intel_pipe_wm *pipe_wm)
2301 {
2302 /* LP0 watermark maximums depend on this pipe alone */
2303 const struct intel_wm_config config = {
2304 .num_pipes_active = 1,
2305 .sprites_enabled = pipe_wm->sprites_enabled,
2306 .sprites_scaled = pipe_wm->sprites_scaled,
2307 };
2308 struct ilk_wm_maximums max;
2309
2310 /* LP0 watermarks always use 1/2 DDB partitioning */
2311 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2312
2313 /* At least LP0 must be valid */
2314 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
2315 DRM_DEBUG_KMS("LP0 watermark invalid\n");
2316 return false;
2317 }
2318
2319 return true;
2320 }
2321
2322 /* Compute new watermarks for the pipe */
2323 static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
2324 {
2325 struct drm_atomic_state *state = cstate->base.state;
2326 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
2327 struct intel_pipe_wm *pipe_wm;
2328 struct drm_device *dev = state->dev;
2329 const struct drm_i915_private *dev_priv = dev->dev_private;
2330 struct intel_plane *intel_plane;
2331 struct intel_plane_state *pristate = NULL;
2332 struct intel_plane_state *sprstate = NULL;
2333 struct intel_plane_state *curstate = NULL;
2334 int level, max_level = ilk_wm_max_level(dev), usable_level;
2335 struct ilk_wm_maximums max;
2336
2337 pipe_wm = &cstate->wm.ilk.optimal;
2338
2339 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2340 struct intel_plane_state *ps;
2341
2342 ps = intel_atomic_get_existing_plane_state(state,
2343 intel_plane);
2344 if (!ps)
2345 continue;
2346
2347 if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
2348 pristate = ps;
2349 else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
2350 sprstate = ps;
2351 else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
2352 curstate = ps;
2353 }
2354
2355 pipe_wm->pipe_enabled = cstate->base.active;
2356 if (sprstate) {
2357 pipe_wm->sprites_enabled = sprstate->visible;
2358 pipe_wm->sprites_scaled = sprstate->visible &&
2359 (drm_rect_width(&sprstate->dst) != drm_rect_width(&sprstate->src) >> 16 ||
2360 drm_rect_height(&sprstate->dst) != drm_rect_height(&sprstate->src) >> 16);
2361 }
2362
2363 usable_level = max_level;
2364
2365 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2366 if (INTEL_INFO(dev)->gen <= 6 && pipe_wm->sprites_enabled)
2367 usable_level = 1;
2368
2369 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2370 if (pipe_wm->sprites_scaled)
2371 usable_level = 0;
2372
2373 ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
2374 pristate, sprstate, curstate, &pipe_wm->raw_wm[0]);
2375
2376 memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
2377 pipe_wm->wm[0] = pipe_wm->raw_wm[0];
2378
2379 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2380 pipe_wm->linetime = hsw_compute_linetime_wm(cstate);
2381
2382 if (!ilk_validate_pipe_wm(dev, pipe_wm))
2383 return -EINVAL;
2384
2385 ilk_compute_wm_reg_maximums(dev, 1, &max);
2386
2387 for (level = 1; level <= max_level; level++) {
2388 struct intel_wm_level *wm = &pipe_wm->raw_wm[level];
2389
2390 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
2391 pristate, sprstate, curstate, wm);
2392
2393 /*
2394 * Disable any watermark level that exceeds the
2395 * register maximums since such watermarks are
2396 * always invalid.
2397 */
2398 if (level > usable_level)
2399 continue;
2400
2401 if (ilk_validate_wm_level(level, &max, wm))
2402 pipe_wm->wm[level] = *wm;
2403 else
2404 usable_level = level;
2405 }
2406
2407 return 0;
2408 }
2409
2410 /*
2411 * Build a set of 'intermediate' watermark values that satisfy both the old
2412 * state and the new state. These can be programmed to the hardware
2413 * immediately.
2414 */
2415 static int ilk_compute_intermediate_wm(struct drm_device *dev,
2416 struct intel_crtc *intel_crtc,
2417 struct intel_crtc_state *newstate)
2418 {
2419 struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate;
2420 struct intel_pipe_wm *b = &intel_crtc->wm.active.ilk;
2421 int level, max_level = ilk_wm_max_level(dev);
2422
2423 /*
2424 * Start with the final, target watermarks, then combine with the
2425 * currently active watermarks to get values that are safe both before
2426 * and after the vblank.
2427 */
2428 *a = newstate->wm.ilk.optimal;
2429 a->pipe_enabled |= b->pipe_enabled;
2430 a->sprites_enabled |= b->sprites_enabled;
2431 a->sprites_scaled |= b->sprites_scaled;
2432
2433 for (level = 0; level <= max_level; level++) {
2434 struct intel_wm_level *a_wm = &a->wm[level];
2435 const struct intel_wm_level *b_wm = &b->wm[level];
2436
2437 a_wm->enable &= b_wm->enable;
2438 a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val);
2439 a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val);
2440 a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val);
2441 a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val);
2442 }
2443
2444 /*
2445 * We need to make sure that these merged watermark values are
2446 * actually a valid configuration themselves. If they're not,
2447 * there's no safe way to transition from the old state to
2448 * the new state, so we need to fail the atomic transaction.
2449 */
2450 if (!ilk_validate_pipe_wm(dev, a))
2451 return -EINVAL;
2452
2453 /*
2454 * If our intermediate WM are identical to the final WM, then we can
2455 * omit the post-vblank programming; only update if it's different.
2456 */
2457 if (memcmp(a, &newstate->wm.ilk.optimal, sizeof(*a)) == 0)
2458 newstate->wm.need_postvbl_update = false;
2459
2460 return 0;
2461 }
2462
2463 /*
2464 * Merge the watermarks from all active pipes for a specific level.
2465 */
2466 static void ilk_merge_wm_level(struct drm_device *dev,
2467 int level,
2468 struct intel_wm_level *ret_wm)
2469 {
2470 const struct intel_crtc *intel_crtc;
2471
2472 ret_wm->enable = true;
2473
2474 for_each_intel_crtc(dev, intel_crtc) {
2475 const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk;
2476 const struct intel_wm_level *wm = &active->wm[level];
2477
2478 if (!active->pipe_enabled)
2479 continue;
2480
2481 /*
2482 * The watermark values may have been used in the past,
2483 * so we must maintain them in the registers for some
2484 * time even if the level is now disabled.
2485 */
2486 if (!wm->enable)
2487 ret_wm->enable = false;
2488
2489 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2490 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2491 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2492 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2493 }
2494 }
2495
2496 /*
2497 * Merge all low power watermarks for all active pipes.
2498 */
2499 static void ilk_wm_merge(struct drm_device *dev,
2500 const struct intel_wm_config *config,
2501 const struct ilk_wm_maximums *max,
2502 struct intel_pipe_wm *merged)
2503 {
2504 struct drm_i915_private *dev_priv = dev->dev_private;
2505 int level, max_level = ilk_wm_max_level(dev);
2506 int last_enabled_level = max_level;
2507
2508 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2509 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2510 config->num_pipes_active > 1)
2511 last_enabled_level = 0;
2512
2513 /* ILK: FBC WM must be disabled always */
2514 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
2515
2516 /* merge each WM1+ level */
2517 for (level = 1; level <= max_level; level++) {
2518 struct intel_wm_level *wm = &merged->wm[level];
2519
2520 ilk_merge_wm_level(dev, level, wm);
2521
2522 if (level > last_enabled_level)
2523 wm->enable = false;
2524 else if (!ilk_validate_wm_level(level, max, wm))
2525 /* make sure all following levels get disabled */
2526 last_enabled_level = level - 1;
2527
2528 /*
2529 * The spec says it is preferred to disable
2530 * FBC WMs instead of disabling a WM level.
2531 */
2532 if (wm->fbc_val > max->fbc) {
2533 if (wm->enable)
2534 merged->fbc_wm_enabled = false;
2535 wm->fbc_val = 0;
2536 }
2537 }
2538
2539 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2540 /*
2541 * FIXME this is racy. FBC might get enabled later.
2542 * What we should check here is whether FBC can be
2543 * enabled sometime later.
2544 */
2545 if (IS_GEN5(dev) && !merged->fbc_wm_enabled &&
2546 intel_fbc_is_active(dev_priv)) {
2547 for (level = 2; level <= max_level; level++) {
2548 struct intel_wm_level *wm = &merged->wm[level];
2549
2550 wm->enable = false;
2551 }
2552 }
2553 }
2554
2555 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2556 {
2557 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2558 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2559 }
2560
2561 /* The value we need to program into the WM_LPx latency field */
2562 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2563 {
2564 struct drm_i915_private *dev_priv = dev->dev_private;
2565
2566 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2567 return 2 * level;
2568 else
2569 return dev_priv->wm.pri_latency[level];
2570 }
2571
2572 static void ilk_compute_wm_results(struct drm_device *dev,
2573 const struct intel_pipe_wm *merged,
2574 enum intel_ddb_partitioning partitioning,
2575 struct ilk_wm_values *results)
2576 {
2577 struct intel_crtc *intel_crtc;
2578 int level, wm_lp;
2579
2580 results->enable_fbc_wm = merged->fbc_wm_enabled;
2581 results->partitioning = partitioning;
2582
2583 /* LP1+ register values */
2584 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2585 const struct intel_wm_level *r;
2586
2587 level = ilk_wm_lp_to_level(wm_lp, merged);
2588
2589 r = &merged->wm[level];
2590
2591 /*
2592 * Maintain the watermark values even if the level is
2593 * disabled. Doing otherwise could cause underruns.
2594 */
2595 results->wm_lp[wm_lp - 1] =
2596 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2597 (r->pri_val << WM1_LP_SR_SHIFT) |
2598 r->cur_val;
2599
2600 if (r->enable)
2601 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2602
2603 if (INTEL_INFO(dev)->gen >= 8)
2604 results->wm_lp[wm_lp - 1] |=
2605 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2606 else
2607 results->wm_lp[wm_lp - 1] |=
2608 r->fbc_val << WM1_LP_FBC_SHIFT;
2609
2610 /*
2611 * Always set WM1S_LP_EN when spr_val != 0, even if the
2612 * level is disabled. Doing otherwise could cause underruns.
2613 */
2614 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2615 WARN_ON(wm_lp != 1);
2616 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2617 } else
2618 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2619 }
2620
2621 /* LP0 register values */
2622 for_each_intel_crtc(dev, intel_crtc) {
2623 enum pipe pipe = intel_crtc->pipe;
2624 const struct intel_wm_level *r =
2625 &intel_crtc->wm.active.ilk.wm[0];
2626
2627 if (WARN_ON(!r->enable))
2628 continue;
2629
2630 results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime;
2631
2632 results->wm_pipe[pipe] =
2633 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2634 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2635 r->cur_val;
2636 }
2637 }
2638
2639 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2640 * case both are at the same level. Prefer r1 in case they're the same. */
2641 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2642 struct intel_pipe_wm *r1,
2643 struct intel_pipe_wm *r2)
2644 {
2645 int level, max_level = ilk_wm_max_level(dev);
2646 int level1 = 0, level2 = 0;
2647
2648 for (level = 1; level <= max_level; level++) {
2649 if (r1->wm[level].enable)
2650 level1 = level;
2651 if (r2->wm[level].enable)
2652 level2 = level;
2653 }
2654
2655 if (level1 == level2) {
2656 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2657 return r2;
2658 else
2659 return r1;
2660 } else if (level1 > level2) {
2661 return r1;
2662 } else {
2663 return r2;
2664 }
2665 }
2666
2667 /* dirty bits used to track which watermarks need changes */
2668 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2669 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2670 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2671 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2672 #define WM_DIRTY_FBC (1 << 24)
2673 #define WM_DIRTY_DDB (1 << 25)
2674
2675 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
2676 const struct ilk_wm_values *old,
2677 const struct ilk_wm_values *new)
2678 {
2679 unsigned int dirty = 0;
2680 enum pipe pipe;
2681 int wm_lp;
2682
2683 for_each_pipe(dev_priv, pipe) {
2684 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2685 dirty |= WM_DIRTY_LINETIME(pipe);
2686 /* Must disable LP1+ watermarks too */
2687 dirty |= WM_DIRTY_LP_ALL;
2688 }
2689
2690 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2691 dirty |= WM_DIRTY_PIPE(pipe);
2692 /* Must disable LP1+ watermarks too */
2693 dirty |= WM_DIRTY_LP_ALL;
2694 }
2695 }
2696
2697 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2698 dirty |= WM_DIRTY_FBC;
2699 /* Must disable LP1+ watermarks too */
2700 dirty |= WM_DIRTY_LP_ALL;
2701 }
2702
2703 if (old->partitioning != new->partitioning) {
2704 dirty |= WM_DIRTY_DDB;
2705 /* Must disable LP1+ watermarks too */
2706 dirty |= WM_DIRTY_LP_ALL;
2707 }
2708
2709 /* LP1+ watermarks already deemed dirty, no need to continue */
2710 if (dirty & WM_DIRTY_LP_ALL)
2711 return dirty;
2712
2713 /* Find the lowest numbered LP1+ watermark in need of an update... */
2714 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2715 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2716 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2717 break;
2718 }
2719
2720 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2721 for (; wm_lp <= 3; wm_lp++)
2722 dirty |= WM_DIRTY_LP(wm_lp);
2723
2724 return dirty;
2725 }
2726
2727 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2728 unsigned int dirty)
2729 {
2730 struct ilk_wm_values *previous = &dev_priv->wm.hw;
2731 bool changed = false;
2732
2733 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2734 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2735 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2736 changed = true;
2737 }
2738 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2739 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2740 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2741 changed = true;
2742 }
2743 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2744 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2745 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2746 changed = true;
2747 }
2748
2749 /*
2750 * Don't touch WM1S_LP_EN here.
2751 * Doing so could cause underruns.
2752 */
2753
2754 return changed;
2755 }
2756
2757 /*
2758 * The spec says we shouldn't write when we don't need, because every write
2759 * causes WMs to be re-evaluated, expending some power.
2760 */
2761 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2762 struct ilk_wm_values *results)
2763 {
2764 struct drm_device *dev = dev_priv->dev;
2765 struct ilk_wm_values *previous = &dev_priv->wm.hw;
2766 unsigned int dirty;
2767 uint32_t val;
2768
2769 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
2770 if (!dirty)
2771 return;
2772
2773 _ilk_disable_lp_wm(dev_priv, dirty);
2774
2775 if (dirty & WM_DIRTY_PIPE(PIPE_A))
2776 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2777 if (dirty & WM_DIRTY_PIPE(PIPE_B))
2778 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2779 if (dirty & WM_DIRTY_PIPE(PIPE_C))
2780 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2781
2782 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2783 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2784 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2785 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2786 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2787 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2788
2789 if (dirty & WM_DIRTY_DDB) {
2790 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2791 val = I915_READ(WM_MISC);
2792 if (results->partitioning == INTEL_DDB_PART_1_2)
2793 val &= ~WM_MISC_DATA_PARTITION_5_6;
2794 else
2795 val |= WM_MISC_DATA_PARTITION_5_6;
2796 I915_WRITE(WM_MISC, val);
2797 } else {
2798 val = I915_READ(DISP_ARB_CTL2);
2799 if (results->partitioning == INTEL_DDB_PART_1_2)
2800 val &= ~DISP_DATA_PARTITION_5_6;
2801 else
2802 val |= DISP_DATA_PARTITION_5_6;
2803 I915_WRITE(DISP_ARB_CTL2, val);
2804 }
2805 }
2806
2807 if (dirty & WM_DIRTY_FBC) {
2808 val = I915_READ(DISP_ARB_CTL);
2809 if (results->enable_fbc_wm)
2810 val &= ~DISP_FBC_WM_DIS;
2811 else
2812 val |= DISP_FBC_WM_DIS;
2813 I915_WRITE(DISP_ARB_CTL, val);
2814 }
2815
2816 if (dirty & WM_DIRTY_LP(1) &&
2817 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2818 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2819
2820 if (INTEL_INFO(dev)->gen >= 7) {
2821 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2822 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2823 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2824 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2825 }
2826
2827 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2828 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2829 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2830 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2831 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2832 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2833
2834 dev_priv->wm.hw = *results;
2835 }
2836
2837 bool ilk_disable_lp_wm(struct drm_device *dev)
2838 {
2839 struct drm_i915_private *dev_priv = dev->dev_private;
2840
2841 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2842 }
2843
2844 /*
2845 * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2846 * different active planes.
2847 */
2848
2849 #define SKL_DDB_SIZE 896 /* in blocks */
2850 #define BXT_DDB_SIZE 512
2851
2852 /*
2853 * Return the index of a plane in the SKL DDB and wm result arrays. Primary
2854 * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
2855 * other universal planes are in indices 1..n. Note that this may leave unused
2856 * indices between the top "sprite" plane and the cursor.
2857 */
2858 static int
2859 skl_wm_plane_id(const struct intel_plane *plane)
2860 {
2861 switch (plane->base.type) {
2862 case DRM_PLANE_TYPE_PRIMARY:
2863 return 0;
2864 case DRM_PLANE_TYPE_CURSOR:
2865 return PLANE_CURSOR;
2866 case DRM_PLANE_TYPE_OVERLAY:
2867 return plane->plane + 1;
2868 default:
2869 MISSING_CASE(plane->base.type);
2870 return plane->plane;
2871 }
2872 }
2873
2874 static void
2875 skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
2876 const struct intel_crtc_state *cstate,
2877 struct skl_ddb_entry *alloc, /* out */
2878 int *num_active /* out */)
2879 {
2880 struct drm_atomic_state *state = cstate->base.state;
2881 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
2882 struct drm_i915_private *dev_priv = to_i915(dev);
2883 struct drm_crtc *for_crtc = cstate->base.crtc;
2884 unsigned int pipe_size, ddb_size;
2885 int nth_active_pipe;
2886 int pipe = to_intel_crtc(for_crtc)->pipe;
2887
2888 if (WARN_ON(!state) || !cstate->base.active) {
2889 alloc->start = 0;
2890 alloc->end = 0;
2891 *num_active = hweight32(dev_priv->active_crtcs);
2892 return;
2893 }
2894
2895 if (intel_state->active_pipe_changes)
2896 *num_active = hweight32(intel_state->active_crtcs);
2897 else
2898 *num_active = hweight32(dev_priv->active_crtcs);
2899
2900 if (IS_BROXTON(dev))
2901 ddb_size = BXT_DDB_SIZE;
2902 else
2903 ddb_size = SKL_DDB_SIZE;
2904
2905 ddb_size -= 4; /* 4 blocks for bypass path allocation */
2906
2907 /*
2908 * If the state doesn't change the active CRTC's, then there's
2909 * no need to recalculate; the existing pipe allocation limits
2910 * should remain unchanged. Note that we're safe from racing
2911 * commits since any racing commit that changes the active CRTC
2912 * list would need to grab _all_ crtc locks, including the one
2913 * we currently hold.
2914 */
2915 if (!intel_state->active_pipe_changes) {
2916 *alloc = dev_priv->wm.skl_hw.ddb.pipe[pipe];
2917 return;
2918 }
2919
2920 nth_active_pipe = hweight32(intel_state->active_crtcs &
2921 (drm_crtc_mask(for_crtc) - 1));
2922 pipe_size = ddb_size / hweight32(intel_state->active_crtcs);
2923 alloc->start = nth_active_pipe * ddb_size / *num_active;
2924 alloc->end = alloc->start + pipe_size;
2925 }
2926
2927 static unsigned int skl_cursor_allocation(int num_active)
2928 {
2929 if (num_active == 1)
2930 return 32;
2931
2932 return 8;
2933 }
2934
2935 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
2936 {
2937 entry->start = reg & 0x3ff;
2938 entry->end = (reg >> 16) & 0x3ff;
2939 if (entry->end)
2940 entry->end += 1;
2941 }
2942
2943 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2944 struct skl_ddb_allocation *ddb /* out */)
2945 {
2946 enum pipe pipe;
2947 int plane;
2948 u32 val;
2949
2950 memset(ddb, 0, sizeof(*ddb));
2951
2952 for_each_pipe(dev_priv, pipe) {
2953 enum intel_display_power_domain power_domain;
2954
2955 power_domain = POWER_DOMAIN_PIPE(pipe);
2956 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
2957 continue;
2958
2959 for_each_plane(dev_priv, pipe, plane) {
2960 val = I915_READ(PLANE_BUF_CFG(pipe, plane));
2961 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
2962 val);
2963 }
2964
2965 val = I915_READ(CUR_BUF_CFG(pipe));
2966 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
2967 val);
2968
2969 intel_display_power_put(dev_priv, power_domain);
2970 }
2971 }
2972
2973 /*
2974 * Determines the downscale amount of a plane for the purposes of watermark calculations.
2975 * The bspec defines downscale amount as:
2976 *
2977 * """
2978 * Horizontal down scale amount = maximum[1, Horizontal source size /
2979 * Horizontal destination size]
2980 * Vertical down scale amount = maximum[1, Vertical source size /
2981 * Vertical destination size]
2982 * Total down scale amount = Horizontal down scale amount *
2983 * Vertical down scale amount
2984 * """
2985 *
2986 * Return value is provided in 16.16 fixed point form to retain fractional part.
2987 * Caller should take care of dividing & rounding off the value.
2988 */
2989 static uint32_t
2990 skl_plane_downscale_amount(const struct intel_plane_state *pstate)
2991 {
2992 uint32_t downscale_h, downscale_w;
2993 uint32_t src_w, src_h, dst_w, dst_h;
2994
2995 if (WARN_ON(!pstate->visible))
2996 return DRM_PLANE_HELPER_NO_SCALING;
2997
2998 /* n.b., src is 16.16 fixed point, dst is whole integer */
2999 src_w = drm_rect_width(&pstate->src);
3000 src_h = drm_rect_height(&pstate->src);
3001 dst_w = drm_rect_width(&pstate->dst);
3002 dst_h = drm_rect_height(&pstate->dst);
3003 if (intel_rotation_90_or_270(pstate->base.rotation))
3004 swap(dst_w, dst_h);
3005
3006 downscale_h = max(src_h / dst_h, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3007 downscale_w = max(src_w / dst_w, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3008
3009 /* Provide result in 16.16 fixed point */
3010 return (uint64_t)downscale_w * downscale_h >> 16;
3011 }
3012
3013 static unsigned int
3014 skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
3015 const struct drm_plane_state *pstate,
3016 int y)
3017 {
3018 struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
3019 struct drm_framebuffer *fb = pstate->fb;
3020 uint32_t down_scale_amount, data_rate;
3021 uint32_t width = 0, height = 0;
3022 unsigned format = fb ? fb->pixel_format : DRM_FORMAT_XRGB8888;
3023
3024 if (!intel_pstate->visible)
3025 return 0;
3026 if (pstate->plane->type == DRM_PLANE_TYPE_CURSOR)
3027 return 0;
3028 if (y && format != DRM_FORMAT_NV12)
3029 return 0;
3030
3031 width = drm_rect_width(&intel_pstate->src) >> 16;
3032 height = drm_rect_height(&intel_pstate->src) >> 16;
3033
3034 if (intel_rotation_90_or_270(pstate->rotation))
3035 swap(width, height);
3036
3037 /* for planar format */
3038 if (format == DRM_FORMAT_NV12) {
3039 if (y) /* y-plane data rate */
3040 data_rate = width * height *
3041 drm_format_plane_cpp(format, 0);
3042 else /* uv-plane data rate */
3043 data_rate = (width / 2) * (height / 2) *
3044 drm_format_plane_cpp(format, 1);
3045 } else {
3046 /* for packed formats */
3047 data_rate = width * height * drm_format_plane_cpp(format, 0);
3048 }
3049
3050 down_scale_amount = skl_plane_downscale_amount(intel_pstate);
3051
3052 return (uint64_t)data_rate * down_scale_amount >> 16;
3053 }
3054
3055 /*
3056 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
3057 * a 8192x4096@32bpp framebuffer:
3058 * 3 * 4096 * 8192 * 4 < 2^32
3059 */
3060 static unsigned int
3061 skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate)
3062 {
3063 struct drm_crtc_state *cstate = &intel_cstate->base;
3064 struct drm_atomic_state *state = cstate->state;
3065 struct drm_crtc *crtc = cstate->crtc;
3066 struct drm_device *dev = crtc->dev;
3067 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3068 const struct drm_plane *plane;
3069 const struct intel_plane *intel_plane;
3070 struct drm_plane_state *pstate;
3071 unsigned int rate, total_data_rate = 0;
3072 int id;
3073 int i;
3074
3075 if (WARN_ON(!state))
3076 return 0;
3077
3078 /* Calculate and cache data rate for each plane */
3079 for_each_plane_in_state(state, plane, pstate, i) {
3080 id = skl_wm_plane_id(to_intel_plane(plane));
3081 intel_plane = to_intel_plane(plane);
3082
3083 if (intel_plane->pipe != intel_crtc->pipe)
3084 continue;
3085
3086 /* packed/uv */
3087 rate = skl_plane_relative_data_rate(intel_cstate,
3088 pstate, 0);
3089 intel_cstate->wm.skl.plane_data_rate[id] = rate;
3090
3091 /* y-plane */
3092 rate = skl_plane_relative_data_rate(intel_cstate,
3093 pstate, 1);
3094 intel_cstate->wm.skl.plane_y_data_rate[id] = rate;
3095 }
3096
3097 /* Calculate CRTC's total data rate from cached values */
3098 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3099 int id = skl_wm_plane_id(intel_plane);
3100
3101 /* packed/uv */
3102 total_data_rate += intel_cstate->wm.skl.plane_data_rate[id];
3103 total_data_rate += intel_cstate->wm.skl.plane_y_data_rate[id];
3104 }
3105
3106 WARN_ON(cstate->plane_mask && total_data_rate == 0);
3107
3108 return total_data_rate;
3109 }
3110
3111 static uint16_t
3112 skl_ddb_min_alloc(const struct drm_plane_state *pstate,
3113 const int y)
3114 {
3115 struct drm_framebuffer *fb = pstate->fb;
3116 struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
3117 uint32_t src_w, src_h;
3118 uint32_t min_scanlines = 8;
3119 uint8_t plane_bpp;
3120
3121 if (WARN_ON(!fb))
3122 return 0;
3123
3124 /* For packed formats, no y-plane, return 0 */
3125 if (y && fb->pixel_format != DRM_FORMAT_NV12)
3126 return 0;
3127
3128 /* For Non Y-tile return 8-blocks */
3129 if (fb->modifier[0] != I915_FORMAT_MOD_Y_TILED &&
3130 fb->modifier[0] != I915_FORMAT_MOD_Yf_TILED)
3131 return 8;
3132
3133 src_w = drm_rect_width(&intel_pstate->src) >> 16;
3134 src_h = drm_rect_height(&intel_pstate->src) >> 16;
3135
3136 if (intel_rotation_90_or_270(pstate->rotation))
3137 swap(src_w, src_h);
3138
3139 /* Halve UV plane width and height for NV12 */
3140 if (fb->pixel_format == DRM_FORMAT_NV12 && !y) {
3141 src_w /= 2;
3142 src_h /= 2;
3143 }
3144
3145 if (fb->pixel_format == DRM_FORMAT_NV12 && !y)
3146 plane_bpp = drm_format_plane_cpp(fb->pixel_format, 1);
3147 else
3148 plane_bpp = drm_format_plane_cpp(fb->pixel_format, 0);
3149
3150 if (intel_rotation_90_or_270(pstate->rotation)) {
3151 switch (plane_bpp) {
3152 case 1:
3153 min_scanlines = 32;
3154 break;
3155 case 2:
3156 min_scanlines = 16;
3157 break;
3158 case 4:
3159 min_scanlines = 8;
3160 break;
3161 case 8:
3162 min_scanlines = 4;
3163 break;
3164 default:
3165 WARN(1, "Unsupported pixel depth %u for rotation",
3166 plane_bpp);
3167 min_scanlines = 32;
3168 }
3169 }
3170
3171 return DIV_ROUND_UP((4 * src_w * plane_bpp), 512) * min_scanlines/4 + 3;
3172 }
3173
3174 static int
3175 skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
3176 struct skl_ddb_allocation *ddb /* out */)
3177 {
3178 struct drm_atomic_state *state = cstate->base.state;
3179 struct drm_crtc *crtc = cstate->base.crtc;
3180 struct drm_device *dev = crtc->dev;
3181 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3182 struct intel_plane *intel_plane;
3183 struct drm_plane *plane;
3184 struct drm_plane_state *pstate;
3185 enum pipe pipe = intel_crtc->pipe;
3186 struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
3187 uint16_t alloc_size, start, cursor_blocks;
3188 uint16_t *minimum = cstate->wm.skl.minimum_blocks;
3189 uint16_t *y_minimum = cstate->wm.skl.minimum_y_blocks;
3190 unsigned int total_data_rate;
3191 int num_active;
3192 int id, i;
3193
3194 if (WARN_ON(!state))
3195 return 0;
3196
3197 if (!cstate->base.active) {
3198 ddb->pipe[pipe].start = ddb->pipe[pipe].end = 0;
3199 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3200 memset(ddb->y_plane[pipe], 0, sizeof(ddb->y_plane[pipe]));
3201 return 0;
3202 }
3203
3204 skl_ddb_get_pipe_allocation_limits(dev, cstate, alloc, &num_active);
3205 alloc_size = skl_ddb_entry_size(alloc);
3206 if (alloc_size == 0) {
3207 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3208 return 0;
3209 }
3210
3211 cursor_blocks = skl_cursor_allocation(num_active);
3212 ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks;
3213 ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
3214
3215 alloc_size -= cursor_blocks;
3216
3217 /* 1. Allocate the mininum required blocks for each active plane */
3218 for_each_plane_in_state(state, plane, pstate, i) {
3219 intel_plane = to_intel_plane(plane);
3220 id = skl_wm_plane_id(intel_plane);
3221
3222 if (intel_plane->pipe != pipe)
3223 continue;
3224
3225 if (!to_intel_plane_state(pstate)->visible) {
3226 minimum[id] = 0;
3227 y_minimum[id] = 0;
3228 continue;
3229 }
3230 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
3231 minimum[id] = 0;
3232 y_minimum[id] = 0;
3233 continue;
3234 }
3235
3236 minimum[id] = skl_ddb_min_alloc(pstate, 0);
3237 y_minimum[id] = skl_ddb_min_alloc(pstate, 1);
3238 }
3239
3240 for (i = 0; i < PLANE_CURSOR; i++) {
3241 alloc_size -= minimum[i];
3242 alloc_size -= y_minimum[i];
3243 }
3244
3245 /*
3246 * 2. Distribute the remaining space in proportion to the amount of
3247 * data each plane needs to fetch from memory.
3248 *
3249 * FIXME: we may not allocate every single block here.
3250 */
3251 total_data_rate = skl_get_total_relative_data_rate(cstate);
3252 if (total_data_rate == 0)
3253 return 0;
3254
3255 start = alloc->start;
3256 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3257 unsigned int data_rate, y_data_rate;
3258 uint16_t plane_blocks, y_plane_blocks = 0;
3259 int id = skl_wm_plane_id(intel_plane);
3260
3261 data_rate = cstate->wm.skl.plane_data_rate[id];
3262
3263 /*
3264 * allocation for (packed formats) or (uv-plane part of planar format):
3265 * promote the expression to 64 bits to avoid overflowing, the
3266 * result is < available as data_rate / total_data_rate < 1
3267 */
3268 plane_blocks = minimum[id];
3269 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3270 total_data_rate);
3271
3272 /* Leave disabled planes at (0,0) */
3273 if (data_rate) {
3274 ddb->plane[pipe][id].start = start;
3275 ddb->plane[pipe][id].end = start + plane_blocks;
3276 }
3277
3278 start += plane_blocks;
3279
3280 /*
3281 * allocation for y_plane part of planar format:
3282 */
3283 y_data_rate = cstate->wm.skl.plane_y_data_rate[id];
3284
3285 y_plane_blocks = y_minimum[id];
3286 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3287 total_data_rate);
3288
3289 if (y_data_rate) {
3290 ddb->y_plane[pipe][id].start = start;
3291 ddb->y_plane[pipe][id].end = start + y_plane_blocks;
3292 }
3293
3294 start += y_plane_blocks;
3295 }
3296
3297 return 0;
3298 }
3299
3300 static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
3301 {
3302 /* TODO: Take into account the scalers once we support them */
3303 return config->base.adjusted_mode.crtc_clock;
3304 }
3305
3306 /*
3307 * The max latency should be 257 (max the punit can code is 255 and we add 2us
3308 * for the read latency) and cpp should always be <= 8, so that
3309 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3310 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3311 */
3312 static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
3313 {
3314 uint32_t wm_intermediate_val, ret;
3315
3316 if (latency == 0)
3317 return UINT_MAX;
3318
3319 wm_intermediate_val = latency * pixel_rate * cpp / 512;
3320 ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3321
3322 return ret;
3323 }
3324
3325 static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
3326 uint32_t horiz_pixels, uint8_t cpp,
3327 uint64_t tiling, uint32_t latency)
3328 {
3329 uint32_t ret;
3330 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3331 uint32_t wm_intermediate_val;
3332
3333 if (latency == 0)
3334 return UINT_MAX;
3335
3336 plane_bytes_per_line = horiz_pixels * cpp;
3337
3338 if (tiling == I915_FORMAT_MOD_Y_TILED ||
3339 tiling == I915_FORMAT_MOD_Yf_TILED) {
3340 plane_bytes_per_line *= 4;
3341 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3342 plane_blocks_per_line /= 4;
3343 } else {
3344 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3345 }
3346
3347 wm_intermediate_val = latency * pixel_rate;
3348 ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
3349 plane_blocks_per_line;
3350
3351 return ret;
3352 }
3353
3354 static uint32_t skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cstate,
3355 struct intel_plane_state *pstate)
3356 {
3357 uint64_t adjusted_pixel_rate;
3358 uint64_t downscale_amount;
3359 uint64_t pixel_rate;
3360
3361 /* Shouldn't reach here on disabled planes... */
3362 if (WARN_ON(!pstate->visible))
3363 return 0;
3364
3365 /*
3366 * Adjusted plane pixel rate is just the pipe's adjusted pixel rate
3367 * with additional adjustments for plane-specific scaling.
3368 */
3369 adjusted_pixel_rate = skl_pipe_pixel_rate(cstate);
3370 downscale_amount = skl_plane_downscale_amount(pstate);
3371
3372 pixel_rate = adjusted_pixel_rate * downscale_amount >> 16;
3373 WARN_ON(pixel_rate != clamp_t(uint32_t, pixel_rate, 0, ~0));
3374
3375 return pixel_rate;
3376 }
3377
3378 static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3379 struct intel_crtc_state *cstate,
3380 struct intel_plane_state *intel_pstate,
3381 uint16_t ddb_allocation,
3382 int level,
3383 uint16_t *out_blocks, /* out */
3384 uint8_t *out_lines, /* out */
3385 bool *enabled /* out */)
3386 {
3387 struct drm_plane_state *pstate = &intel_pstate->base;
3388 struct drm_framebuffer *fb = pstate->fb;
3389 uint32_t latency = dev_priv->wm.skl_latency[level];
3390 uint32_t method1, method2;
3391 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3392 uint32_t res_blocks, res_lines;
3393 uint32_t selected_result;
3394 uint8_t cpp;
3395 uint32_t width = 0, height = 0;
3396 uint32_t plane_pixel_rate;
3397
3398 if (latency == 0 || !cstate->base.active || !intel_pstate->visible) {
3399 *enabled = false;
3400 return 0;
3401 }
3402
3403 width = drm_rect_width(&intel_pstate->src) >> 16;
3404 height = drm_rect_height(&intel_pstate->src) >> 16;
3405
3406 if (intel_rotation_90_or_270(pstate->rotation))
3407 swap(width, height);
3408
3409 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
3410 plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate, intel_pstate);
3411
3412 method1 = skl_wm_method1(plane_pixel_rate, cpp, latency);
3413 method2 = skl_wm_method2(plane_pixel_rate,
3414 cstate->base.adjusted_mode.crtc_htotal,
3415 width,
3416 cpp,
3417 fb->modifier[0],
3418 latency);
3419
3420 plane_bytes_per_line = width * cpp;
3421 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3422
3423 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3424 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
3425 uint32_t min_scanlines = 4;
3426 uint32_t y_tile_minimum;
3427 if (intel_rotation_90_or_270(pstate->rotation)) {
3428 int cpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
3429 drm_format_plane_cpp(fb->pixel_format, 1) :
3430 drm_format_plane_cpp(fb->pixel_format, 0);
3431
3432 switch (cpp) {
3433 case 1:
3434 min_scanlines = 16;
3435 break;
3436 case 2:
3437 min_scanlines = 8;
3438 break;
3439 case 8:
3440 WARN(1, "Unsupported pixel depth for rotation");
3441 }
3442 }
3443 y_tile_minimum = plane_blocks_per_line * min_scanlines;
3444 selected_result = max(method2, y_tile_minimum);
3445 } else {
3446 if ((ddb_allocation / plane_blocks_per_line) >= 1)
3447 selected_result = min(method1, method2);
3448 else
3449 selected_result = method1;
3450 }
3451
3452 res_blocks = selected_result + 1;
3453 res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
3454
3455 if (level >= 1 && level <= 7) {
3456 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3457 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED)
3458 res_lines += 4;
3459 else
3460 res_blocks++;
3461 }
3462
3463 if (res_blocks >= ddb_allocation || res_lines > 31) {
3464 *enabled = false;
3465
3466 /*
3467 * If there are no valid level 0 watermarks, then we can't
3468 * support this display configuration.
3469 */
3470 if (level) {
3471 return 0;
3472 } else {
3473 DRM_DEBUG_KMS("Requested display configuration exceeds system watermark limitations\n");
3474 DRM_DEBUG_KMS("Plane %d.%d: blocks required = %u/%u, lines required = %u/31\n",
3475 to_intel_crtc(cstate->base.crtc)->pipe,
3476 skl_wm_plane_id(to_intel_plane(pstate->plane)),
3477 res_blocks, ddb_allocation, res_lines);
3478
3479 return -EINVAL;
3480 }
3481 }
3482
3483 *out_blocks = res_blocks;
3484 *out_lines = res_lines;
3485 *enabled = true;
3486
3487 return 0;
3488 }
3489
3490 static int
3491 skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3492 struct skl_ddb_allocation *ddb,
3493 struct intel_crtc_state *cstate,
3494 int level,
3495 struct skl_wm_level *result)
3496 {
3497 struct drm_device *dev = dev_priv->dev;
3498 struct drm_atomic_state *state = cstate->base.state;
3499 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
3500 struct drm_plane *plane;
3501 struct intel_plane *intel_plane;
3502 struct intel_plane_state *intel_pstate;
3503 uint16_t ddb_blocks;
3504 enum pipe pipe = intel_crtc->pipe;
3505 int ret;
3506
3507 /*
3508 * We'll only calculate watermarks for planes that are actually
3509 * enabled, so make sure all other planes are set as disabled.
3510 */
3511 memset(result, 0, sizeof(*result));
3512
3513 for_each_intel_plane_mask(dev, intel_plane, cstate->base.plane_mask) {
3514 int i = skl_wm_plane_id(intel_plane);
3515
3516 plane = &intel_plane->base;
3517 intel_pstate = NULL;
3518 if (state)
3519 intel_pstate =
3520 intel_atomic_get_existing_plane_state(state,
3521 intel_plane);
3522
3523 /*
3524 * Note: If we start supporting multiple pending atomic commits
3525 * against the same planes/CRTC's in the future, plane->state
3526 * will no longer be the correct pre-state to use for the
3527 * calculations here and we'll need to change where we get the
3528 * 'unchanged' plane data from.
3529 *
3530 * For now this is fine because we only allow one queued commit
3531 * against a CRTC. Even if the plane isn't modified by this
3532 * transaction and we don't have a plane lock, we still have
3533 * the CRTC's lock, so we know that no other transactions are
3534 * racing with us to update it.
3535 */
3536 if (!intel_pstate)
3537 intel_pstate = to_intel_plane_state(plane->state);
3538
3539 WARN_ON(!intel_pstate->base.fb);
3540
3541 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3542
3543 ret = skl_compute_plane_wm(dev_priv,
3544 cstate,
3545 intel_pstate,
3546 ddb_blocks,
3547 level,
3548 &result->plane_res_b[i],
3549 &result->plane_res_l[i],
3550 &result->plane_en[i]);
3551 if (ret)
3552 return ret;
3553 }
3554
3555 return 0;
3556 }
3557
3558 static uint32_t
3559 skl_compute_linetime_wm(struct intel_crtc_state *cstate)
3560 {
3561 if (!cstate->base.active)
3562 return 0;
3563
3564 if (WARN_ON(skl_pipe_pixel_rate(cstate) == 0))
3565 return 0;
3566
3567 return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
3568 skl_pipe_pixel_rate(cstate));
3569 }
3570
3571 static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
3572 struct skl_wm_level *trans_wm /* out */)
3573 {
3574 struct drm_crtc *crtc = cstate->base.crtc;
3575 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3576 struct intel_plane *intel_plane;
3577
3578 if (!cstate->base.active)
3579 return;
3580
3581 /* Until we know more, just disable transition WMs */
3582 for_each_intel_plane_on_crtc(crtc->dev, intel_crtc, intel_plane) {
3583 int i = skl_wm_plane_id(intel_plane);
3584
3585 trans_wm->plane_en[i] = false;
3586 }
3587 }
3588
3589 static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
3590 struct skl_ddb_allocation *ddb,
3591 struct skl_pipe_wm *pipe_wm)
3592 {
3593 struct drm_device *dev = cstate->base.crtc->dev;
3594 const struct drm_i915_private *dev_priv = dev->dev_private;
3595 int level, max_level = ilk_wm_max_level(dev);
3596 int ret;
3597
3598 for (level = 0; level <= max_level; level++) {
3599 ret = skl_compute_wm_level(dev_priv, ddb, cstate,
3600 level, &pipe_wm->wm[level]);
3601 if (ret)
3602 return ret;
3603 }
3604 pipe_wm->linetime = skl_compute_linetime_wm(cstate);
3605
3606 skl_compute_transition_wm(cstate, &pipe_wm->trans_wm);
3607
3608 return 0;
3609 }
3610
3611 static void skl_compute_wm_results(struct drm_device *dev,
3612 struct skl_pipe_wm *p_wm,
3613 struct skl_wm_values *r,
3614 struct intel_crtc *intel_crtc)
3615 {
3616 int level, max_level = ilk_wm_max_level(dev);
3617 enum pipe pipe = intel_crtc->pipe;
3618 uint32_t temp;
3619 int i;
3620
3621 for (level = 0; level <= max_level; level++) {
3622 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3623 temp = 0;
3624
3625 temp |= p_wm->wm[level].plane_res_l[i] <<
3626 PLANE_WM_LINES_SHIFT;
3627 temp |= p_wm->wm[level].plane_res_b[i];
3628 if (p_wm->wm[level].plane_en[i])
3629 temp |= PLANE_WM_EN;
3630
3631 r->plane[pipe][i][level] = temp;
3632 }
3633
3634 temp = 0;
3635
3636 temp |= p_wm->wm[level].plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3637 temp |= p_wm->wm[level].plane_res_b[PLANE_CURSOR];
3638
3639 if (p_wm->wm[level].plane_en[PLANE_CURSOR])
3640 temp |= PLANE_WM_EN;
3641
3642 r->plane[pipe][PLANE_CURSOR][level] = temp;
3643
3644 }
3645
3646 /* transition WMs */
3647 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3648 temp = 0;
3649 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3650 temp |= p_wm->trans_wm.plane_res_b[i];
3651 if (p_wm->trans_wm.plane_en[i])
3652 temp |= PLANE_WM_EN;
3653
3654 r->plane_trans[pipe][i] = temp;
3655 }
3656
3657 temp = 0;
3658 temp |= p_wm->trans_wm.plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3659 temp |= p_wm->trans_wm.plane_res_b[PLANE_CURSOR];
3660 if (p_wm->trans_wm.plane_en[PLANE_CURSOR])
3661 temp |= PLANE_WM_EN;
3662
3663 r->plane_trans[pipe][PLANE_CURSOR] = temp;
3664
3665 r->wm_linetime[pipe] = p_wm->linetime;
3666 }
3667
3668 static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
3669 i915_reg_t reg,
3670 const struct skl_ddb_entry *entry)
3671 {
3672 if (entry->end)
3673 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3674 else
3675 I915_WRITE(reg, 0);
3676 }
3677
3678 static void skl_write_wm_values(struct drm_i915_private *dev_priv,
3679 const struct skl_wm_values *new)
3680 {
3681 struct drm_device *dev = dev_priv->dev;
3682 struct intel_crtc *crtc;
3683
3684 for_each_intel_crtc(dev, crtc) {
3685 int i, level, max_level = ilk_wm_max_level(dev);
3686 enum pipe pipe = crtc->pipe;
3687
3688 if ((new->dirty_pipes & drm_crtc_mask(&crtc->base)) == 0)
3689 continue;
3690 if (!crtc->active)
3691 continue;
3692
3693 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]);
3694
3695 for (level = 0; level <= max_level; level++) {
3696 for (i = 0; i < intel_num_planes(crtc); i++)
3697 I915_WRITE(PLANE_WM(pipe, i, level),
3698 new->plane[pipe][i][level]);
3699 I915_WRITE(CUR_WM(pipe, level),
3700 new->plane[pipe][PLANE_CURSOR][level]);
3701 }
3702 for (i = 0; i < intel_num_planes(crtc); i++)
3703 I915_WRITE(PLANE_WM_TRANS(pipe, i),
3704 new->plane_trans[pipe][i]);
3705 I915_WRITE(CUR_WM_TRANS(pipe),
3706 new->plane_trans[pipe][PLANE_CURSOR]);
3707
3708 for (i = 0; i < intel_num_planes(crtc); i++) {
3709 skl_ddb_entry_write(dev_priv,
3710 PLANE_BUF_CFG(pipe, i),
3711 &new->ddb.plane[pipe][i]);
3712 skl_ddb_entry_write(dev_priv,
3713 PLANE_NV12_BUF_CFG(pipe, i),
3714 &new->ddb.y_plane[pipe][i]);
3715 }
3716
3717 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3718 &new->ddb.plane[pipe][PLANE_CURSOR]);
3719 }
3720 }
3721
3722 /*
3723 * When setting up a new DDB allocation arrangement, we need to correctly
3724 * sequence the times at which the new allocations for the pipes are taken into
3725 * account or we'll have pipes fetching from space previously allocated to
3726 * another pipe.
3727 *
3728 * Roughly the sequence looks like:
3729 * 1. re-allocate the pipe(s) with the allocation being reduced and not
3730 * overlapping with a previous light-up pipe (another way to put it is:
3731 * pipes with their new allocation strickly included into their old ones).
3732 * 2. re-allocate the other pipes that get their allocation reduced
3733 * 3. allocate the pipes having their allocation increased
3734 *
3735 * Steps 1. and 2. are here to take care of the following case:
3736 * - Initially DDB looks like this:
3737 * | B | C |
3738 * - enable pipe A.
3739 * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
3740 * allocation
3741 * | A | B | C |
3742 *
3743 * We need to sequence the re-allocation: C, B, A (and not B, C, A).
3744 */
3745
3746 static void
3747 skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass)
3748 {
3749 int plane;
3750
3751 DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);
3752
3753 for_each_plane(dev_priv, pipe, plane) {
3754 I915_WRITE(PLANE_SURF(pipe, plane),
3755 I915_READ(PLANE_SURF(pipe, plane)));
3756 }
3757 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3758 }
3759
3760 static bool
3761 skl_ddb_allocation_included(const struct skl_ddb_allocation *old,
3762 const struct skl_ddb_allocation *new,
3763 enum pipe pipe)
3764 {
3765 uint16_t old_size, new_size;
3766
3767 old_size = skl_ddb_entry_size(&old->pipe[pipe]);
3768 new_size = skl_ddb_entry_size(&new->pipe[pipe]);
3769
3770 return old_size != new_size &&
3771 new->pipe[pipe].start >= old->pipe[pipe].start &&
3772 new->pipe[pipe].end <= old->pipe[pipe].end;
3773 }
3774
3775 static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
3776 struct skl_wm_values *new_values)
3777 {
3778 struct drm_device *dev = dev_priv->dev;
3779 struct skl_ddb_allocation *cur_ddb, *new_ddb;
3780 bool reallocated[I915_MAX_PIPES] = {};
3781 struct intel_crtc *crtc;
3782 enum pipe pipe;
3783
3784 new_ddb = &new_values->ddb;
3785 cur_ddb = &dev_priv->wm.skl_hw.ddb;
3786
3787 /*
3788 * First pass: flush the pipes with the new allocation contained into
3789 * the old space.
3790 *
3791 * We'll wait for the vblank on those pipes to ensure we can safely
3792 * re-allocate the freed space without this pipe fetching from it.
3793 */
3794 for_each_intel_crtc(dev, crtc) {
3795 if (!crtc->active)
3796 continue;
3797
3798 pipe = crtc->pipe;
3799
3800 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))
3801 continue;
3802
3803 skl_wm_flush_pipe(dev_priv, pipe, 1);
3804 intel_wait_for_vblank(dev, pipe);
3805
3806 reallocated[pipe] = true;
3807 }
3808
3809
3810 /*
3811 * Second pass: flush the pipes that are having their allocation
3812 * reduced, but overlapping with a previous allocation.
3813 *
3814 * Here as well we need to wait for the vblank to make sure the freed
3815 * space is not used anymore.
3816 */
3817 for_each_intel_crtc(dev, crtc) {
3818 if (!crtc->active)
3819 continue;
3820
3821 pipe = crtc->pipe;
3822
3823 if (reallocated[pipe])
3824 continue;
3825
3826 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <
3827 skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
3828 skl_wm_flush_pipe(dev_priv, pipe, 2);
3829 intel_wait_for_vblank(dev, pipe);
3830 reallocated[pipe] = true;
3831 }
3832 }
3833
3834 /*
3835 * Third pass: flush the pipes that got more space allocated.
3836 *
3837 * We don't need to actively wait for the update here, next vblank
3838 * will just get more DDB space with the correct WM values.
3839 */
3840 for_each_intel_crtc(dev, crtc) {
3841 if (!crtc->active)
3842 continue;
3843
3844 pipe = crtc->pipe;
3845
3846 /*
3847 * At this point, only the pipes more space than before are
3848 * left to re-allocate.
3849 */
3850 if (reallocated[pipe])
3851 continue;
3852
3853 skl_wm_flush_pipe(dev_priv, pipe, 3);
3854 }
3855 }
3856
3857 static int skl_update_pipe_wm(struct drm_crtc_state *cstate,
3858 struct skl_ddb_allocation *ddb, /* out */
3859 struct skl_pipe_wm *pipe_wm, /* out */
3860 bool *changed /* out */)
3861 {
3862 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->crtc);
3863 struct intel_crtc_state *intel_cstate = to_intel_crtc_state(cstate);
3864 int ret;
3865
3866 ret = skl_build_pipe_wm(intel_cstate, ddb, pipe_wm);
3867 if (ret)
3868 return ret;
3869
3870 if (!memcmp(&intel_crtc->wm.active.skl, pipe_wm, sizeof(*pipe_wm)))
3871 *changed = false;
3872 else
3873 *changed = true;
3874
3875 return 0;
3876 }
3877
3878 static int
3879 skl_compute_ddb(struct drm_atomic_state *state)
3880 {
3881 struct drm_device *dev = state->dev;
3882 struct drm_i915_private *dev_priv = to_i915(dev);
3883 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3884 struct intel_crtc *intel_crtc;
3885 struct skl_ddb_allocation *ddb = &intel_state->wm_results.ddb;
3886 unsigned realloc_pipes = dev_priv->active_crtcs;
3887 int ret;
3888
3889 /*
3890 * If this is our first atomic update following hardware readout,
3891 * we can't trust the DDB that the BIOS programmed for us. Let's
3892 * pretend that all pipes switched active status so that we'll
3893 * ensure a full DDB recompute.
3894 */
3895 if (dev_priv->wm.distrust_bios_wm)
3896 intel_state->active_pipe_changes = ~0;
3897
3898 /*
3899 * If the modeset changes which CRTC's are active, we need to
3900 * recompute the DDB allocation for *all* active pipes, even
3901 * those that weren't otherwise being modified in any way by this
3902 * atomic commit. Due to the shrinking of the per-pipe allocations
3903 * when new active CRTC's are added, it's possible for a pipe that
3904 * we were already using and aren't changing at all here to suddenly
3905 * become invalid if its DDB needs exceeds its new allocation.
3906 *
3907 * Note that if we wind up doing a full DDB recompute, we can't let
3908 * any other display updates race with this transaction, so we need
3909 * to grab the lock on *all* CRTC's.
3910 */
3911 if (intel_state->active_pipe_changes) {
3912 realloc_pipes = ~0;
3913 intel_state->wm_results.dirty_pipes = ~0;
3914 }
3915
3916 for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) {
3917 struct intel_crtc_state *cstate;
3918
3919 cstate = intel_atomic_get_crtc_state(state, intel_crtc);
3920 if (IS_ERR(cstate))
3921 return PTR_ERR(cstate);
3922
3923 ret = skl_allocate_pipe_ddb(cstate, ddb);
3924 if (ret)
3925 return ret;
3926 }
3927
3928 return 0;
3929 }
3930
3931 static int
3932 skl_compute_wm(struct drm_atomic_state *state)
3933 {
3934 struct drm_crtc *crtc;
3935 struct drm_crtc_state *cstate;
3936 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3937 struct skl_wm_values *results = &intel_state->wm_results;
3938 struct skl_pipe_wm *pipe_wm;
3939 bool changed = false;
3940 int ret, i;
3941
3942 /*
3943 * If this transaction isn't actually touching any CRTC's, don't
3944 * bother with watermark calculation. Note that if we pass this
3945 * test, we're guaranteed to hold at least one CRTC state mutex,
3946 * which means we can safely use values like dev_priv->active_crtcs
3947 * since any racing commits that want to update them would need to
3948 * hold _all_ CRTC state mutexes.
3949 */
3950 for_each_crtc_in_state(state, crtc, cstate, i)
3951 changed = true;
3952 if (!changed)
3953 return 0;
3954
3955 /* Clear all dirty flags */
3956 results->dirty_pipes = 0;
3957
3958 ret = skl_compute_ddb(state);
3959 if (ret)
3960 return ret;
3961
3962 /*
3963 * Calculate WM's for all pipes that are part of this transaction.
3964 * Note that the DDB allocation above may have added more CRTC's that
3965 * weren't otherwise being modified (and set bits in dirty_pipes) if
3966 * pipe allocations had to change.
3967 *
3968 * FIXME: Now that we're doing this in the atomic check phase, we
3969 * should allow skl_update_pipe_wm() to return failure in cases where
3970 * no suitable watermark values can be found.
3971 */
3972 for_each_crtc_in_state(state, crtc, cstate, i) {
3973 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3974 struct intel_crtc_state *intel_cstate =
3975 to_intel_crtc_state(cstate);
3976
3977 pipe_wm = &intel_cstate->wm.skl.optimal;
3978 ret = skl_update_pipe_wm(cstate, &results->ddb, pipe_wm,
3979 &changed);
3980 if (ret)
3981 return ret;
3982
3983 if (changed)
3984 results->dirty_pipes |= drm_crtc_mask(crtc);
3985
3986 if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
3987 /* This pipe's WM's did not change */
3988 continue;
3989
3990 intel_cstate->update_wm_pre = true;
3991 skl_compute_wm_results(crtc->dev, pipe_wm, results, intel_crtc);
3992 }
3993
3994 return 0;
3995 }
3996
3997 static void skl_update_wm(struct drm_crtc *crtc)
3998 {
3999 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4000 struct drm_device *dev = crtc->dev;
4001 struct drm_i915_private *dev_priv = dev->dev_private;
4002 struct skl_wm_values *results = &dev_priv->wm.skl_results;
4003 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
4004 struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;
4005
4006 if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
4007 return;
4008
4009 intel_crtc->wm.active.skl = *pipe_wm;
4010
4011 mutex_lock(&dev_priv->wm.wm_mutex);
4012
4013 skl_write_wm_values(dev_priv, results);
4014 skl_flush_wm_values(dev_priv, results);
4015
4016 /* store the new configuration */
4017 dev_priv->wm.skl_hw = *results;
4018
4019 mutex_unlock(&dev_priv->wm.wm_mutex);
4020 }
4021
4022 static void ilk_compute_wm_config(struct drm_device *dev,
4023 struct intel_wm_config *config)
4024 {
4025 struct intel_crtc *crtc;
4026
4027 /* Compute the currently _active_ config */
4028 for_each_intel_crtc(dev, crtc) {
4029 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
4030
4031 if (!wm->pipe_enabled)
4032 continue;
4033
4034 config->sprites_enabled |= wm->sprites_enabled;
4035 config->sprites_scaled |= wm->sprites_scaled;
4036 config->num_pipes_active++;
4037 }
4038 }
4039
4040 static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
4041 {
4042 struct drm_device *dev = dev_priv->dev;
4043 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
4044 struct ilk_wm_maximums max;
4045 struct intel_wm_config config = {};
4046 struct ilk_wm_values results = {};
4047 enum intel_ddb_partitioning partitioning;
4048
4049 ilk_compute_wm_config(dev, &config);
4050
4051 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
4052 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
4053
4054 /* 5/6 split only in single pipe config on IVB+ */
4055 if (INTEL_INFO(dev)->gen >= 7 &&
4056 config.num_pipes_active == 1 && config.sprites_enabled) {
4057 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
4058 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
4059
4060 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
4061 } else {
4062 best_lp_wm = &lp_wm_1_2;
4063 }
4064
4065 partitioning = (best_lp_wm == &lp_wm_1_2) ?
4066 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
4067
4068 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
4069
4070 ilk_write_wm_values(dev_priv, &results);
4071 }
4072
4073 static void ilk_initial_watermarks(struct intel_crtc_state *cstate)
4074 {
4075 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4076 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
4077
4078 mutex_lock(&dev_priv->wm.wm_mutex);
4079 intel_crtc->wm.active.ilk = cstate->wm.ilk.intermediate;
4080 ilk_program_watermarks(dev_priv);
4081 mutex_unlock(&dev_priv->wm.wm_mutex);
4082 }
4083
4084 static void ilk_optimize_watermarks(struct intel_crtc_state *cstate)
4085 {
4086 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4087 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
4088
4089 mutex_lock(&dev_priv->wm.wm_mutex);
4090 if (cstate->wm.need_postvbl_update) {
4091 intel_crtc->wm.active.ilk = cstate->wm.ilk.optimal;
4092 ilk_program_watermarks(dev_priv);
4093 }
4094 mutex_unlock(&dev_priv->wm.wm_mutex);
4095 }
4096
4097 static void skl_pipe_wm_active_state(uint32_t val,
4098 struct skl_pipe_wm *active,
4099 bool is_transwm,
4100 bool is_cursor,
4101 int i,
4102 int level)
4103 {
4104 bool is_enabled = (val & PLANE_WM_EN) != 0;
4105
4106 if (!is_transwm) {
4107 if (!is_cursor) {
4108 active->wm[level].plane_en[i] = is_enabled;
4109 active->wm[level].plane_res_b[i] =
4110 val & PLANE_WM_BLOCKS_MASK;
4111 active->wm[level].plane_res_l[i] =
4112 (val >> PLANE_WM_LINES_SHIFT) &
4113 PLANE_WM_LINES_MASK;
4114 } else {
4115 active->wm[level].plane_en[PLANE_CURSOR] = is_enabled;
4116 active->wm[level].plane_res_b[PLANE_CURSOR] =
4117 val & PLANE_WM_BLOCKS_MASK;
4118 active->wm[level].plane_res_l[PLANE_CURSOR] =
4119 (val >> PLANE_WM_LINES_SHIFT) &
4120 PLANE_WM_LINES_MASK;
4121 }
4122 } else {
4123 if (!is_cursor) {
4124 active->trans_wm.plane_en[i] = is_enabled;
4125 active->trans_wm.plane_res_b[i] =
4126 val & PLANE_WM_BLOCKS_MASK;
4127 active->trans_wm.plane_res_l[i] =
4128 (val >> PLANE_WM_LINES_SHIFT) &
4129 PLANE_WM_LINES_MASK;
4130 } else {
4131 active->trans_wm.plane_en[PLANE_CURSOR] = is_enabled;
4132 active->trans_wm.plane_res_b[PLANE_CURSOR] =
4133 val & PLANE_WM_BLOCKS_MASK;
4134 active->trans_wm.plane_res_l[PLANE_CURSOR] =
4135 (val >> PLANE_WM_LINES_SHIFT) &
4136 PLANE_WM_LINES_MASK;
4137 }
4138 }
4139 }
4140
4141 static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
4142 {
4143 struct drm_device *dev = crtc->dev;
4144 struct drm_i915_private *dev_priv = dev->dev_private;
4145 struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
4146 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4147 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
4148 struct skl_pipe_wm *active = &cstate->wm.skl.optimal;
4149 enum pipe pipe = intel_crtc->pipe;
4150 int level, i, max_level;
4151 uint32_t temp;
4152
4153 max_level = ilk_wm_max_level(dev);
4154
4155 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
4156
4157 for (level = 0; level <= max_level; level++) {
4158 for (i = 0; i < intel_num_planes(intel_crtc); i++)
4159 hw->plane[pipe][i][level] =
4160 I915_READ(PLANE_WM(pipe, i, level));
4161 hw->plane[pipe][PLANE_CURSOR][level] = I915_READ(CUR_WM(pipe, level));
4162 }
4163
4164 for (i = 0; i < intel_num_planes(intel_crtc); i++)
4165 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
4166 hw->plane_trans[pipe][PLANE_CURSOR] = I915_READ(CUR_WM_TRANS(pipe));
4167
4168 if (!intel_crtc->active)
4169 return;
4170
4171 hw->dirty_pipes |= drm_crtc_mask(crtc);
4172
4173 active->linetime = hw->wm_linetime[pipe];
4174
4175 for (level = 0; level <= max_level; level++) {
4176 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
4177 temp = hw->plane[pipe][i][level];
4178 skl_pipe_wm_active_state(temp, active, false,
4179 false, i, level);
4180 }
4181 temp = hw->plane[pipe][PLANE_CURSOR][level];
4182 skl_pipe_wm_active_state(temp, active, false, true, i, level);
4183 }
4184
4185 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
4186 temp = hw->plane_trans[pipe][i];
4187 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
4188 }
4189
4190 temp = hw->plane_trans[pipe][PLANE_CURSOR];
4191 skl_pipe_wm_active_state(temp, active, true, true, i, 0);
4192
4193 intel_crtc->wm.active.skl = *active;
4194 }
4195
4196 void skl_wm_get_hw_state(struct drm_device *dev)
4197 {
4198 struct drm_i915_private *dev_priv = dev->dev_private;
4199 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
4200 struct drm_crtc *crtc;
4201
4202 skl_ddb_get_hw_state(dev_priv, ddb);
4203 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
4204 skl_pipe_wm_get_hw_state(crtc);
4205
4206 if (dev_priv->active_crtcs) {
4207 /* Fully recompute DDB on first atomic commit */
4208 dev_priv->wm.distrust_bios_wm = true;
4209 } else {
4210 /* Easy/common case; just sanitize DDB now if everything off */
4211 memset(ddb, 0, sizeof(*ddb));
4212 }
4213 }
4214
4215 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
4216 {
4217 struct drm_device *dev = crtc->dev;
4218 struct drm_i915_private *dev_priv = dev->dev_private;
4219 struct ilk_wm_values *hw = &dev_priv->wm.hw;
4220 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4221 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
4222 struct intel_pipe_wm *active = &cstate->wm.ilk.optimal;
4223 enum pipe pipe = intel_crtc->pipe;
4224 static const i915_reg_t wm0_pipe_reg[] = {
4225 [PIPE_A] = WM0_PIPEA_ILK,
4226 [PIPE_B] = WM0_PIPEB_ILK,
4227 [PIPE_C] = WM0_PIPEC_IVB,
4228 };
4229
4230 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
4231 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4232 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
4233
4234 memset(active, 0, sizeof(*active));
4235
4236 active->pipe_enabled = intel_crtc->active;
4237
4238 if (active->pipe_enabled) {
4239 u32 tmp = hw->wm_pipe[pipe];
4240
4241 /*
4242 * For active pipes LP0 watermark is marked as
4243 * enabled, and LP1+ watermaks as disabled since
4244 * we can't really reverse compute them in case
4245 * multiple pipes are active.
4246 */
4247 active->wm[0].enable = true;
4248 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
4249 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
4250 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
4251 active->linetime = hw->wm_linetime[pipe];
4252 } else {
4253 int level, max_level = ilk_wm_max_level(dev);
4254
4255 /*
4256 * For inactive pipes, all watermark levels
4257 * should be marked as enabled but zeroed,
4258 * which is what we'd compute them to.
4259 */
4260 for (level = 0; level <= max_level; level++)
4261 active->wm[level].enable = true;
4262 }
4263
4264 intel_crtc->wm.active.ilk = *active;
4265 }
4266
4267 #define _FW_WM(value, plane) \
4268 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
4269 #define _FW_WM_VLV(value, plane) \
4270 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
4271
4272 static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
4273 struct vlv_wm_values *wm)
4274 {
4275 enum pipe pipe;
4276 uint32_t tmp;
4277
4278 for_each_pipe(dev_priv, pipe) {
4279 tmp = I915_READ(VLV_DDL(pipe));
4280
4281 wm->ddl[pipe].primary =
4282 (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4283 wm->ddl[pipe].cursor =
4284 (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4285 wm->ddl[pipe].sprite[0] =
4286 (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4287 wm->ddl[pipe].sprite[1] =
4288 (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4289 }
4290
4291 tmp = I915_READ(DSPFW1);
4292 wm->sr.plane = _FW_WM(tmp, SR);
4293 wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
4294 wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
4295 wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
4296
4297 tmp = I915_READ(DSPFW2);
4298 wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
4299 wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
4300 wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
4301
4302 tmp = I915_READ(DSPFW3);
4303 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
4304
4305 if (IS_CHERRYVIEW(dev_priv)) {
4306 tmp = I915_READ(DSPFW7_CHV);
4307 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4308 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4309
4310 tmp = I915_READ(DSPFW8_CHV);
4311 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
4312 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
4313
4314 tmp = I915_READ(DSPFW9_CHV);
4315 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
4316 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
4317
4318 tmp = I915_READ(DSPHOWM);
4319 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4320 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
4321 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
4322 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
4323 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4324 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4325 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4326 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4327 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4328 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4329 } else {
4330 tmp = I915_READ(DSPFW7);
4331 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4332 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4333
4334 tmp = I915_READ(DSPHOWM);
4335 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4336 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4337 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4338 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4339 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4340 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4341 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4342 }
4343 }
4344
4345 #undef _FW_WM
4346 #undef _FW_WM_VLV
4347
4348 void vlv_wm_get_hw_state(struct drm_device *dev)
4349 {
4350 struct drm_i915_private *dev_priv = to_i915(dev);
4351 struct vlv_wm_values *wm = &dev_priv->wm.vlv;
4352 struct intel_plane *plane;
4353 enum pipe pipe;
4354 u32 val;
4355
4356 vlv_read_wm_values(dev_priv, wm);
4357
4358 for_each_intel_plane(dev, plane) {
4359 switch (plane->base.type) {
4360 int sprite;
4361 case DRM_PLANE_TYPE_CURSOR:
4362 plane->wm.fifo_size = 63;
4363 break;
4364 case DRM_PLANE_TYPE_PRIMARY:
4365 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
4366 break;
4367 case DRM_PLANE_TYPE_OVERLAY:
4368 sprite = plane->plane;
4369 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
4370 break;
4371 }
4372 }
4373
4374 wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4375 wm->level = VLV_WM_LEVEL_PM2;
4376
4377 if (IS_CHERRYVIEW(dev_priv)) {
4378 mutex_lock(&dev_priv->rps.hw_lock);
4379
4380 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4381 if (val & DSP_MAXFIFO_PM5_ENABLE)
4382 wm->level = VLV_WM_LEVEL_PM5;
4383
4384 /*
4385 * If DDR DVFS is disabled in the BIOS, Punit
4386 * will never ack the request. So if that happens
4387 * assume we don't have to enable/disable DDR DVFS
4388 * dynamically. To test that just set the REQ_ACK
4389 * bit to poke the Punit, but don't change the
4390 * HIGH/LOW bits so that we don't actually change
4391 * the current state.
4392 */
4393 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4394 val |= FORCE_DDR_FREQ_REQ_ACK;
4395 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
4396
4397 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
4398 FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
4399 DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4400 "assuming DDR DVFS is disabled\n");
4401 dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
4402 } else {
4403 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4404 if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4405 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4406 }
4407
4408 mutex_unlock(&dev_priv->rps.hw_lock);
4409 }
4410
4411 for_each_pipe(dev_priv, pipe)
4412 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4413 pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4414 wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4415
4416 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4417 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4418 }
4419
4420 void ilk_wm_get_hw_state(struct drm_device *dev)
4421 {
4422 struct drm_i915_private *dev_priv = dev->dev_private;
4423 struct ilk_wm_values *hw = &dev_priv->wm.hw;
4424 struct drm_crtc *crtc;
4425
4426 for_each_crtc(dev, crtc)
4427 ilk_pipe_wm_get_hw_state(crtc);
4428
4429 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4430 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4431 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4432
4433 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
4434 if (INTEL_INFO(dev)->gen >= 7) {
4435 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4436 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4437 }
4438
4439 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4440 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4441 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4442 else if (IS_IVYBRIDGE(dev))
4443 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4444 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4445
4446 hw->enable_fbc_wm =
4447 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4448 }
4449
4450 /**
4451 * intel_update_watermarks - update FIFO watermark values based on current modes
4452 *
4453 * Calculate watermark values for the various WM regs based on current mode
4454 * and plane configuration.
4455 *
4456 * There are several cases to deal with here:
4457 * - normal (i.e. non-self-refresh)
4458 * - self-refresh (SR) mode
4459 * - lines are large relative to FIFO size (buffer can hold up to 2)
4460 * - lines are small relative to FIFO size (buffer can hold more than 2
4461 * lines), so need to account for TLB latency
4462 *
4463 * The normal calculation is:
4464 * watermark = dotclock * bytes per pixel * latency
4465 * where latency is platform & configuration dependent (we assume pessimal
4466 * values here).
4467 *
4468 * The SR calculation is:
4469 * watermark = (trunc(latency/line time)+1) * surface width *
4470 * bytes per pixel
4471 * where
4472 * line time = htotal / dotclock
4473 * surface width = hdisplay for normal plane and 64 for cursor
4474 * and latency is assumed to be high, as above.
4475 *
4476 * The final value programmed to the register should always be rounded up,
4477 * and include an extra 2 entries to account for clock crossings.
4478 *
4479 * We don't use the sprite, so we can ignore that. And on Crestline we have
4480 * to set the non-SR watermarks to 8.
4481 */
4482 void intel_update_watermarks(struct drm_crtc *crtc)
4483 {
4484 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4485
4486 if (dev_priv->display.update_wm)
4487 dev_priv->display.update_wm(crtc);
4488 }
4489
4490 /*
4491 * Lock protecting IPS related data structures
4492 */
4493 DEFINE_SPINLOCK(mchdev_lock);
4494
4495 /* Global for IPS driver to get at the current i915 device. Protected by
4496 * mchdev_lock. */
4497 static struct drm_i915_private *i915_mch_dev;
4498
4499 bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val)
4500 {
4501 u16 rgvswctl;
4502
4503 assert_spin_locked(&mchdev_lock);
4504
4505 rgvswctl = I915_READ16(MEMSWCTL);
4506 if (rgvswctl & MEMCTL_CMD_STS) {
4507 DRM_DEBUG("gpu busy, RCS change rejected\n");
4508 return false; /* still busy with another command */
4509 }
4510
4511 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4512 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4513 I915_WRITE16(MEMSWCTL, rgvswctl);
4514 POSTING_READ16(MEMSWCTL);
4515
4516 rgvswctl |= MEMCTL_CMD_STS;
4517 I915_WRITE16(MEMSWCTL, rgvswctl);
4518
4519 return true;
4520 }
4521
4522 static void ironlake_enable_drps(struct drm_i915_private *dev_priv)
4523 {
4524 u32 rgvmodectl;
4525 u8 fmax, fmin, fstart, vstart;
4526
4527 spin_lock_irq(&mchdev_lock);
4528
4529 rgvmodectl = I915_READ(MEMMODECTL);
4530
4531 /* Enable temp reporting */
4532 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4533 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4534
4535 /* 100ms RC evaluation intervals */
4536 I915_WRITE(RCUPEI, 100000);
4537 I915_WRITE(RCDNEI, 100000);
4538
4539 /* Set max/min thresholds to 90ms and 80ms respectively */
4540 I915_WRITE(RCBMAXAVG, 90000);
4541 I915_WRITE(RCBMINAVG, 80000);
4542
4543 I915_WRITE(MEMIHYST, 1);
4544
4545 /* Set up min, max, and cur for interrupt handling */
4546 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4547 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4548 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4549 MEMMODE_FSTART_SHIFT;
4550
4551 vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
4552 PXVFREQ_PX_SHIFT;
4553
4554 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4555 dev_priv->ips.fstart = fstart;
4556
4557 dev_priv->ips.max_delay = fstart;
4558 dev_priv->ips.min_delay = fmin;
4559 dev_priv->ips.cur_delay = fstart;
4560
4561 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4562 fmax, fmin, fstart);
4563
4564 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4565
4566 /*
4567 * Interrupts will be enabled in ironlake_irq_postinstall
4568 */
4569
4570 I915_WRITE(VIDSTART, vstart);
4571 POSTING_READ(VIDSTART);
4572
4573 rgvmodectl |= MEMMODE_SWMODE_EN;
4574 I915_WRITE(MEMMODECTL, rgvmodectl);
4575
4576 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
4577 DRM_ERROR("stuck trying to change perf mode\n");
4578 mdelay(1);
4579
4580 ironlake_set_drps(dev_priv, fstart);
4581
4582 dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4583 I915_READ(DDREC) + I915_READ(CSIEC);
4584 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
4585 dev_priv->ips.last_count2 = I915_READ(GFXEC);
4586 dev_priv->ips.last_time2 = ktime_get_raw_ns();
4587
4588 spin_unlock_irq(&mchdev_lock);
4589 }
4590
4591 static void ironlake_disable_drps(struct drm_i915_private *dev_priv)
4592 {
4593 u16 rgvswctl;
4594
4595 spin_lock_irq(&mchdev_lock);
4596
4597 rgvswctl = I915_READ16(MEMSWCTL);
4598
4599 /* Ack interrupts, disable EFC interrupt */
4600 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4601 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4602 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4603 I915_WRITE(DEIIR, DE_PCU_EVENT);
4604 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4605
4606 /* Go back to the starting frequency */
4607 ironlake_set_drps(dev_priv, dev_priv->ips.fstart);
4608 mdelay(1);
4609 rgvswctl |= MEMCTL_CMD_STS;
4610 I915_WRITE(MEMSWCTL, rgvswctl);
4611 mdelay(1);
4612
4613 spin_unlock_irq(&mchdev_lock);
4614 }
4615
4616 /* There's a funny hw issue where the hw returns all 0 when reading from
4617 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4618 * ourselves, instead of doing a rmw cycle (which might result in us clearing
4619 * all limits and the gpu stuck at whatever frequency it is at atm).
4620 */
4621 static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
4622 {
4623 u32 limits;
4624
4625 /* Only set the down limit when we've reached the lowest level to avoid
4626 * getting more interrupts, otherwise leave this clear. This prevents a
4627 * race in the hw when coming out of rc6: There's a tiny window where
4628 * the hw runs at the minimal clock before selecting the desired
4629 * frequency, if the down threshold expires in that window we will not
4630 * receive a down interrupt. */
4631 if (IS_GEN9(dev_priv)) {
4632 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4633 if (val <= dev_priv->rps.min_freq_softlimit)
4634 limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4635 } else {
4636 limits = dev_priv->rps.max_freq_softlimit << 24;
4637 if (val <= dev_priv->rps.min_freq_softlimit)
4638 limits |= dev_priv->rps.min_freq_softlimit << 16;
4639 }
4640
4641 return limits;
4642 }
4643
4644 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4645 {
4646 int new_power;
4647 u32 threshold_up = 0, threshold_down = 0; /* in % */
4648 u32 ei_up = 0, ei_down = 0;
4649
4650 new_power = dev_priv->rps.power;
4651 switch (dev_priv->rps.power) {
4652 case LOW_POWER:
4653 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
4654 new_power = BETWEEN;
4655 break;
4656
4657 case BETWEEN:
4658 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
4659 new_power = LOW_POWER;
4660 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
4661 new_power = HIGH_POWER;
4662 break;
4663
4664 case HIGH_POWER:
4665 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
4666 new_power = BETWEEN;
4667 break;
4668 }
4669 /* Max/min bins are special */
4670 if (val <= dev_priv->rps.min_freq_softlimit)
4671 new_power = LOW_POWER;
4672 if (val >= dev_priv->rps.max_freq_softlimit)
4673 new_power = HIGH_POWER;
4674 if (new_power == dev_priv->rps.power)
4675 return;
4676
4677 /* Note the units here are not exactly 1us, but 1280ns. */
4678 switch (new_power) {
4679 case LOW_POWER:
4680 /* Upclock if more than 95% busy over 16ms */
4681 ei_up = 16000;
4682 threshold_up = 95;
4683
4684 /* Downclock if less than 85% busy over 32ms */
4685 ei_down = 32000;
4686 threshold_down = 85;
4687 break;
4688
4689 case BETWEEN:
4690 /* Upclock if more than 90% busy over 13ms */
4691 ei_up = 13000;
4692 threshold_up = 90;
4693
4694 /* Downclock if less than 75% busy over 32ms */
4695 ei_down = 32000;
4696 threshold_down = 75;
4697 break;
4698
4699 case HIGH_POWER:
4700 /* Upclock if more than 85% busy over 10ms */
4701 ei_up = 10000;
4702 threshold_up = 85;
4703
4704 /* Downclock if less than 60% busy over 32ms */
4705 ei_down = 32000;
4706 threshold_down = 60;
4707 break;
4708 }
4709
4710 I915_WRITE(GEN6_RP_UP_EI,
4711 GT_INTERVAL_FROM_US(dev_priv, ei_up));
4712 I915_WRITE(GEN6_RP_UP_THRESHOLD,
4713 GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100)));
4714
4715 I915_WRITE(GEN6_RP_DOWN_EI,
4716 GT_INTERVAL_FROM_US(dev_priv, ei_down));
4717 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4718 GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100)));
4719
4720 I915_WRITE(GEN6_RP_CONTROL,
4721 GEN6_RP_MEDIA_TURBO |
4722 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4723 GEN6_RP_MEDIA_IS_GFX |
4724 GEN6_RP_ENABLE |
4725 GEN6_RP_UP_BUSY_AVG |
4726 GEN6_RP_DOWN_IDLE_AVG);
4727
4728 dev_priv->rps.power = new_power;
4729 dev_priv->rps.up_threshold = threshold_up;
4730 dev_priv->rps.down_threshold = threshold_down;
4731 dev_priv->rps.last_adj = 0;
4732 }
4733
4734 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4735 {
4736 u32 mask = 0;
4737
4738 if (val > dev_priv->rps.min_freq_softlimit)
4739 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
4740 if (val < dev_priv->rps.max_freq_softlimit)
4741 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
4742
4743 mask &= dev_priv->pm_rps_events;
4744
4745 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
4746 }
4747
4748 /* gen6_set_rps is called to update the frequency request, but should also be
4749 * called when the range (min_delay and max_delay) is modified so that we can
4750 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
4751 static void gen6_set_rps(struct drm_i915_private *dev_priv, u8 val)
4752 {
4753 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4754 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
4755 return;
4756
4757 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4758 WARN_ON(val > dev_priv->rps.max_freq);
4759 WARN_ON(val < dev_priv->rps.min_freq);
4760
4761 /* min/max delay may still have been modified so be sure to
4762 * write the limits value.
4763 */
4764 if (val != dev_priv->rps.cur_freq) {
4765 gen6_set_rps_thresholds(dev_priv, val);
4766
4767 if (IS_GEN9(dev_priv))
4768 I915_WRITE(GEN6_RPNSWREQ,
4769 GEN9_FREQUENCY(val));
4770 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
4771 I915_WRITE(GEN6_RPNSWREQ,
4772 HSW_FREQUENCY(val));
4773 else
4774 I915_WRITE(GEN6_RPNSWREQ,
4775 GEN6_FREQUENCY(val) |
4776 GEN6_OFFSET(0) |
4777 GEN6_AGGRESSIVE_TURBO);
4778 }
4779
4780 /* Make sure we continue to get interrupts
4781 * until we hit the minimum or maximum frequencies.
4782 */
4783 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
4784 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4785
4786 POSTING_READ(GEN6_RPNSWREQ);
4787
4788 dev_priv->rps.cur_freq = val;
4789 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4790 }
4791
4792 static void valleyview_set_rps(struct drm_i915_private *dev_priv, u8 val)
4793 {
4794 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4795 WARN_ON(val > dev_priv->rps.max_freq);
4796 WARN_ON(val < dev_priv->rps.min_freq);
4797
4798 if (WARN_ONCE(IS_CHERRYVIEW(dev_priv) && (val & 1),
4799 "Odd GPU freq value\n"))
4800 val &= ~1;
4801
4802 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4803
4804 if (val != dev_priv->rps.cur_freq) {
4805 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
4806 if (!IS_CHERRYVIEW(dev_priv))
4807 gen6_set_rps_thresholds(dev_priv, val);
4808 }
4809
4810 dev_priv->rps.cur_freq = val;
4811 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4812 }
4813
4814 /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
4815 *
4816 * * If Gfx is Idle, then
4817 * 1. Forcewake Media well.
4818 * 2. Request idle freq.
4819 * 3. Release Forcewake of Media well.
4820 */
4821 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4822 {
4823 u32 val = dev_priv->rps.idle_freq;
4824
4825 if (dev_priv->rps.cur_freq <= val)
4826 return;
4827
4828 /* Wake up the media well, as that takes a lot less
4829 * power than the Render well. */
4830 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
4831 valleyview_set_rps(dev_priv, val);
4832 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
4833 }
4834
4835 void gen6_rps_busy(struct drm_i915_private *dev_priv)
4836 {
4837 mutex_lock(&dev_priv->rps.hw_lock);
4838 if (dev_priv->rps.enabled) {
4839 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
4840 gen6_rps_reset_ei(dev_priv);
4841 I915_WRITE(GEN6_PMINTRMSK,
4842 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
4843 }
4844 mutex_unlock(&dev_priv->rps.hw_lock);
4845 }
4846
4847 void gen6_rps_idle(struct drm_i915_private *dev_priv)
4848 {
4849 mutex_lock(&dev_priv->rps.hw_lock);
4850 if (dev_priv->rps.enabled) {
4851 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4852 vlv_set_rps_idle(dev_priv);
4853 else
4854 gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
4855 dev_priv->rps.last_adj = 0;
4856 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
4857 }
4858 mutex_unlock(&dev_priv->rps.hw_lock);
4859
4860 spin_lock(&dev_priv->rps.client_lock);
4861 while (!list_empty(&dev_priv->rps.clients))
4862 list_del_init(dev_priv->rps.clients.next);
4863 spin_unlock(&dev_priv->rps.client_lock);
4864 }
4865
4866 void gen6_rps_boost(struct drm_i915_private *dev_priv,
4867 struct intel_rps_client *rps,
4868 unsigned long submitted)
4869 {
4870 /* This is intentionally racy! We peek at the state here, then
4871 * validate inside the RPS worker.
4872 */
4873 if (!(dev_priv->mm.busy &&
4874 dev_priv->rps.enabled &&
4875 dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit))
4876 return;
4877
4878 /* Force a RPS boost (and don't count it against the client) if
4879 * the GPU is severely congested.
4880 */
4881 if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
4882 rps = NULL;
4883
4884 spin_lock(&dev_priv->rps.client_lock);
4885 if (rps == NULL || list_empty(&rps->link)) {
4886 spin_lock_irq(&dev_priv->irq_lock);
4887 if (dev_priv->rps.interrupts_enabled) {
4888 dev_priv->rps.client_boost = true;
4889 queue_work(dev_priv->wq, &dev_priv->rps.work);
4890 }
4891 spin_unlock_irq(&dev_priv->irq_lock);
4892
4893 if (rps != NULL) {
4894 list_add(&rps->link, &dev_priv->rps.clients);
4895 rps->boosts++;
4896 } else
4897 dev_priv->rps.boosts++;
4898 }
4899 spin_unlock(&dev_priv->rps.client_lock);
4900 }
4901
4902 void intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
4903 {
4904 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4905 valleyview_set_rps(dev_priv, val);
4906 else
4907 gen6_set_rps(dev_priv, val);
4908 }
4909
4910 static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
4911 {
4912 I915_WRITE(GEN6_RC_CONTROL, 0);
4913 I915_WRITE(GEN9_PG_ENABLE, 0);
4914 }
4915
4916 static void gen9_disable_rps(struct drm_i915_private *dev_priv)
4917 {
4918 I915_WRITE(GEN6_RP_CONTROL, 0);
4919 }
4920
4921 static void gen6_disable_rps(struct drm_i915_private *dev_priv)
4922 {
4923 I915_WRITE(GEN6_RC_CONTROL, 0);
4924 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
4925 I915_WRITE(GEN6_RP_CONTROL, 0);
4926 }
4927
4928 static void cherryview_disable_rps(struct drm_i915_private *dev_priv)
4929 {
4930 I915_WRITE(GEN6_RC_CONTROL, 0);
4931 }
4932
4933 static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
4934 {
4935 /* we're doing forcewake before Disabling RC6,
4936 * This what the BIOS expects when going into suspend */
4937 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4938
4939 I915_WRITE(GEN6_RC_CONTROL, 0);
4940
4941 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4942 }
4943
4944 static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode)
4945 {
4946 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
4947 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
4948 mode = GEN6_RC_CTL_RC6_ENABLE;
4949 else
4950 mode = 0;
4951 }
4952 if (HAS_RC6p(dev_priv))
4953 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
4954 onoff(mode & GEN6_RC_CTL_RC6_ENABLE),
4955 onoff(mode & GEN6_RC_CTL_RC6p_ENABLE),
4956 onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE));
4957
4958 else
4959 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
4960 onoff(mode & GEN6_RC_CTL_RC6_ENABLE));
4961 }
4962
4963 static bool bxt_check_bios_rc6_setup(struct drm_i915_private *dev_priv)
4964 {
4965 struct i915_ggtt *ggtt = &dev_priv->ggtt;
4966 bool enable_rc6 = true;
4967 unsigned long rc6_ctx_base;
4968
4969 if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
4970 DRM_DEBUG_KMS("RC6 Base location not set properly.\n");
4971 enable_rc6 = false;
4972 }
4973
4974 /*
4975 * The exact context size is not known for BXT, so assume a page size
4976 * for this check.
4977 */
4978 rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
4979 if (!((rc6_ctx_base >= ggtt->stolen_reserved_base) &&
4980 (rc6_ctx_base + PAGE_SIZE <= ggtt->stolen_reserved_base +
4981 ggtt->stolen_reserved_size))) {
4982 DRM_DEBUG_KMS("RC6 Base address not as expected.\n");
4983 enable_rc6 = false;
4984 }
4985
4986 if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) &&
4987 ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) &&
4988 ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) &&
4989 ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) {
4990 DRM_DEBUG_KMS("Engine Idle wait time not set properly.\n");
4991 enable_rc6 = false;
4992 }
4993
4994 if (!(I915_READ(GEN6_RC_CONTROL) & (GEN6_RC_CTL_RC6_ENABLE |
4995 GEN6_RC_CTL_HW_ENABLE)) &&
4996 ((I915_READ(GEN6_RC_CONTROL) & GEN6_RC_CTL_HW_ENABLE) ||
4997 !(I915_READ(GEN6_RC_STATE) & RC6_STATE))) {
4998 DRM_DEBUG_KMS("HW/SW RC6 is not enabled by BIOS.\n");
4999 enable_rc6 = false;
5000 }
5001
5002 return enable_rc6;
5003 }
5004
5005 int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6)
5006 {
5007 /* No RC6 before Ironlake and code is gone for ilk. */
5008 if (INTEL_INFO(dev_priv)->gen < 6)
5009 return 0;
5010
5011 if (!enable_rc6)
5012 return 0;
5013
5014 if (IS_BROXTON(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) {
5015 DRM_INFO("RC6 disabled by BIOS\n");
5016 return 0;
5017 }
5018
5019 /* Respect the kernel parameter if it is set */
5020 if (enable_rc6 >= 0) {
5021 int mask;
5022
5023 if (HAS_RC6p(dev_priv))
5024 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
5025 INTEL_RC6pp_ENABLE;
5026 else
5027 mask = INTEL_RC6_ENABLE;
5028
5029 if ((enable_rc6 & mask) != enable_rc6)
5030 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
5031 enable_rc6 & mask, enable_rc6, mask);
5032
5033 return enable_rc6 & mask;
5034 }
5035
5036 if (IS_IVYBRIDGE(dev_priv))
5037 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
5038
5039 return INTEL_RC6_ENABLE;
5040 }
5041
5042 static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
5043 {
5044 uint32_t rp_state_cap;
5045 u32 ddcc_status = 0;
5046 int ret;
5047
5048 /* All of these values are in units of 50MHz */
5049 dev_priv->rps.cur_freq = 0;
5050 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
5051 if (IS_BROXTON(dev_priv)) {
5052 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
5053 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
5054 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
5055 dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff;
5056 } else {
5057 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
5058 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
5059 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
5060 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
5061 }
5062
5063 /* hw_max = RP0 until we check for overclocking */
5064 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
5065
5066 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
5067 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
5068 IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5069 ret = sandybridge_pcode_read(dev_priv,
5070 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
5071 &ddcc_status);
5072 if (0 == ret)
5073 dev_priv->rps.efficient_freq =
5074 clamp_t(u8,
5075 ((ddcc_status >> 8) & 0xff),
5076 dev_priv->rps.min_freq,
5077 dev_priv->rps.max_freq);
5078 }
5079
5080 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5081 /* Store the frequency values in 16.66 MHZ units, which is
5082 the natural hardware unit for SKL */
5083 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
5084 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
5085 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
5086 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
5087 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
5088 }
5089
5090 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5091
5092 /* Preserve min/max settings in case of re-init */
5093 if (dev_priv->rps.max_freq_softlimit == 0)
5094 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5095
5096 if (dev_priv->rps.min_freq_softlimit == 0) {
5097 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5098 dev_priv->rps.min_freq_softlimit =
5099 max_t(int, dev_priv->rps.efficient_freq,
5100 intel_freq_opcode(dev_priv, 450));
5101 else
5102 dev_priv->rps.min_freq_softlimit =
5103 dev_priv->rps.min_freq;
5104 }
5105 }
5106
5107 /* See the Gen9_GT_PM_Programming_Guide doc for the below */
5108 static void gen9_enable_rps(struct drm_i915_private *dev_priv)
5109 {
5110 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5111
5112 gen6_init_rps_frequencies(dev_priv);
5113
5114 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
5115 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
5116 /*
5117 * BIOS could leave the Hw Turbo enabled, so need to explicitly
5118 * clear out the Control register just to avoid inconsitency
5119 * with debugfs interface, which will show Turbo as enabled
5120 * only and that is not expected by the User after adding the
5121 * WaGsvDisableTurbo. Apart from this there is no problem even
5122 * if the Turbo is left enabled in the Control register, as the
5123 * Up/Down interrupts would remain masked.
5124 */
5125 gen9_disable_rps(dev_priv);
5126 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5127 return;
5128 }
5129
5130 /* Program defaults and thresholds for RPS*/
5131 I915_WRITE(GEN6_RC_VIDEO_FREQ,
5132 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
5133
5134 /* 1 second timeout*/
5135 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
5136 GT_INTERVAL_FROM_US(dev_priv, 1000000));
5137
5138 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
5139
5140 /* Leaning on the below call to gen6_set_rps to program/setup the
5141 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
5142 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
5143 dev_priv->rps.power = HIGH_POWER; /* force a reset */
5144 gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
5145
5146 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5147 }
5148
5149 static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
5150 {
5151 struct intel_engine_cs *engine;
5152 uint32_t rc6_mask = 0;
5153
5154 /* 1a: Software RC state - RC0 */
5155 I915_WRITE(GEN6_RC_STATE, 0);
5156
5157 /* 1b: Get forcewake during program sequence. Although the driver
5158 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5159 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5160
5161 /* 2a: Disable RC states. */
5162 I915_WRITE(GEN6_RC_CONTROL, 0);
5163
5164 /* 2b: Program RC6 thresholds.*/
5165
5166 /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
5167 if (IS_SKYLAKE(dev_priv))
5168 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
5169 else
5170 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
5171 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5172 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5173 for_each_engine(engine, dev_priv)
5174 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5175
5176 if (HAS_GUC(dev_priv))
5177 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
5178
5179 I915_WRITE(GEN6_RC_SLEEP, 0);
5180
5181 /* 2c: Program Coarse Power Gating Policies. */
5182 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
5183 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
5184
5185 /* 3a: Enable RC6 */
5186 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
5187 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
5188 DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
5189 /* WaRsUseTimeoutMode */
5190 if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_D0) ||
5191 IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
5192 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
5193 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5194 GEN7_RC_CTL_TO_MODE |
5195 rc6_mask);
5196 } else {
5197 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
5198 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5199 GEN6_RC_CTL_EI_MODE(1) |
5200 rc6_mask);
5201 }
5202
5203 /*
5204 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
5205 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
5206 */
5207 if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
5208 I915_WRITE(GEN9_PG_ENABLE, 0);
5209 else
5210 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
5211 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
5212
5213 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5214 }
5215
5216 static void gen8_enable_rps(struct drm_i915_private *dev_priv)
5217 {
5218 struct intel_engine_cs *engine;
5219 uint32_t rc6_mask = 0;
5220
5221 /* 1a: Software RC state - RC0 */
5222 I915_WRITE(GEN6_RC_STATE, 0);
5223
5224 /* 1c & 1d: Get forcewake during program sequence. Although the driver
5225 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5226 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5227
5228 /* 2a: Disable RC states. */
5229 I915_WRITE(GEN6_RC_CONTROL, 0);
5230
5231 /* Initialize rps frequencies */
5232 gen6_init_rps_frequencies(dev_priv);
5233
5234 /* 2b: Program RC6 thresholds.*/
5235 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5236 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5237 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5238 for_each_engine(engine, dev_priv)
5239 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5240 I915_WRITE(GEN6_RC_SLEEP, 0);
5241 if (IS_BROADWELL(dev_priv))
5242 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
5243 else
5244 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
5245
5246 /* 3: Enable RC6 */
5247 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
5248 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
5249 intel_print_rc6_info(dev_priv, rc6_mask);
5250 if (IS_BROADWELL(dev_priv))
5251 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5252 GEN7_RC_CTL_TO_MODE |
5253 rc6_mask);
5254 else
5255 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5256 GEN6_RC_CTL_EI_MODE(1) |
5257 rc6_mask);
5258
5259 /* 4 Program defaults and thresholds for RPS*/
5260 I915_WRITE(GEN6_RPNSWREQ,
5261 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
5262 I915_WRITE(GEN6_RC_VIDEO_FREQ,
5263 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
5264 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
5265 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
5266
5267 /* Docs recommend 900MHz, and 300 MHz respectively */
5268 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
5269 dev_priv->rps.max_freq_softlimit << 24 |
5270 dev_priv->rps.min_freq_softlimit << 16);
5271
5272 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
5273 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
5274 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
5275 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
5276
5277 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5278
5279 /* 5: Enable RPS */
5280 I915_WRITE(GEN6_RP_CONTROL,
5281 GEN6_RP_MEDIA_TURBO |
5282 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5283 GEN6_RP_MEDIA_IS_GFX |
5284 GEN6_RP_ENABLE |
5285 GEN6_RP_UP_BUSY_AVG |
5286 GEN6_RP_DOWN_IDLE_AVG);
5287
5288 /* 6: Ring frequency + overclocking (our driver does this later */
5289
5290 dev_priv->rps.power = HIGH_POWER; /* force a reset */
5291 gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
5292
5293 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5294 }
5295
5296 static void gen6_enable_rps(struct drm_i915_private *dev_priv)
5297 {
5298 struct intel_engine_cs *engine;
5299 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
5300 u32 gtfifodbg;
5301 int rc6_mode;
5302 int ret;
5303
5304 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5305
5306 /* Here begins a magic sequence of register writes to enable
5307 * auto-downclocking.
5308 *
5309 * Perhaps there might be some value in exposing these to
5310 * userspace...
5311 */
5312 I915_WRITE(GEN6_RC_STATE, 0);
5313
5314 /* Clear the DBG now so we don't confuse earlier errors */
5315 gtfifodbg = I915_READ(GTFIFODBG);
5316 if (gtfifodbg) {
5317 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
5318 I915_WRITE(GTFIFODBG, gtfifodbg);
5319 }
5320
5321 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5322
5323 /* Initialize rps frequencies */
5324 gen6_init_rps_frequencies(dev_priv);
5325
5326 /* disable the counters and set deterministic thresholds */
5327 I915_WRITE(GEN6_RC_CONTROL, 0);
5328
5329 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
5330 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
5331 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
5332 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5333 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5334
5335 for_each_engine(engine, dev_priv)
5336 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5337
5338 I915_WRITE(GEN6_RC_SLEEP, 0);
5339 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
5340 if (IS_IVYBRIDGE(dev_priv))
5341 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
5342 else
5343 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
5344 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
5345 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
5346
5347 /* Check if we are enabling RC6 */
5348 rc6_mode = intel_enable_rc6();
5349 if (rc6_mode & INTEL_RC6_ENABLE)
5350 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
5351
5352 /* We don't use those on Haswell */
5353 if (!IS_HASWELL(dev_priv)) {
5354 if (rc6_mode & INTEL_RC6p_ENABLE)
5355 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
5356
5357 if (rc6_mode & INTEL_RC6pp_ENABLE)
5358 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
5359 }
5360
5361 intel_print_rc6_info(dev_priv, rc6_mask);
5362
5363 I915_WRITE(GEN6_RC_CONTROL,
5364 rc6_mask |
5365 GEN6_RC_CTL_EI_MODE(1) |
5366 GEN6_RC_CTL_HW_ENABLE);
5367
5368 /* Power down if completely idle for over 50ms */
5369 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
5370 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5371
5372 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
5373 if (ret)
5374 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
5375
5376 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
5377 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
5378 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
5379 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
5380 (pcu_mbox & 0xff) * 50);
5381 dev_priv->rps.max_freq = pcu_mbox & 0xff;
5382 }
5383
5384 dev_priv->rps.power = HIGH_POWER; /* force a reset */
5385 gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
5386
5387 rc6vids = 0;
5388 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
5389 if (IS_GEN6(dev_priv) && ret) {
5390 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
5391 } else if (IS_GEN6(dev_priv) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
5392 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5393 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5394 rc6vids &= 0xffff00;
5395 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5396 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5397 if (ret)
5398 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5399 }
5400
5401 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5402 }
5403
5404 static void __gen6_update_ring_freq(struct drm_i915_private *dev_priv)
5405 {
5406 int min_freq = 15;
5407 unsigned int gpu_freq;
5408 unsigned int max_ia_freq, min_ring_freq;
5409 unsigned int max_gpu_freq, min_gpu_freq;
5410 int scaling_factor = 180;
5411 struct cpufreq_policy *policy;
5412
5413 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5414
5415 policy = cpufreq_cpu_get(0);
5416 if (policy) {
5417 max_ia_freq = policy->cpuinfo.max_freq;
5418 cpufreq_cpu_put(policy);
5419 } else {
5420 /*
5421 * Default to measured freq if none found, PCU will ensure we
5422 * don't go over
5423 */
5424 max_ia_freq = tsc_khz;
5425 }
5426
5427 /* Convert from kHz to MHz */
5428 max_ia_freq /= 1000;
5429
5430 min_ring_freq = I915_READ(DCLK) & 0xf;
5431 /* convert DDR frequency from units of 266.6MHz to bandwidth */
5432 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
5433
5434 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5435 /* Convert GT frequency to 50 HZ units */
5436 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5437 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5438 } else {
5439 min_gpu_freq = dev_priv->rps.min_freq;
5440 max_gpu_freq = dev_priv->rps.max_freq;
5441 }
5442
5443 /*
5444 * For each potential GPU frequency, load a ring frequency we'd like
5445 * to use for memory access. We do this by specifying the IA frequency
5446 * the PCU should use as a reference to determine the ring frequency.
5447 */
5448 for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5449 int diff = max_gpu_freq - gpu_freq;
5450 unsigned int ia_freq = 0, ring_freq = 0;
5451
5452 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5453 /*
5454 * ring_freq = 2 * GT. ring_freq is in 100MHz units
5455 * No floor required for ring frequency on SKL.
5456 */
5457 ring_freq = gpu_freq;
5458 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
5459 /* max(2 * GT, DDR). NB: GT is 50MHz units */
5460 ring_freq = max(min_ring_freq, gpu_freq);
5461 } else if (IS_HASWELL(dev_priv)) {
5462 ring_freq = mult_frac(gpu_freq, 5, 4);
5463 ring_freq = max(min_ring_freq, ring_freq);
5464 /* leave ia_freq as the default, chosen by cpufreq */
5465 } else {
5466 /* On older processors, there is no separate ring
5467 * clock domain, so in order to boost the bandwidth
5468 * of the ring, we need to upclock the CPU (ia_freq).
5469 *
5470 * For GPU frequencies less than 750MHz,
5471 * just use the lowest ring freq.
5472 */
5473 if (gpu_freq < min_freq)
5474 ia_freq = 800;
5475 else
5476 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5477 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5478 }
5479
5480 sandybridge_pcode_write(dev_priv,
5481 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
5482 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5483 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5484 gpu_freq);
5485 }
5486 }
5487
5488 void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
5489 {
5490 if (!HAS_CORE_RING_FREQ(dev_priv))
5491 return;
5492
5493 mutex_lock(&dev_priv->rps.hw_lock);
5494 __gen6_update_ring_freq(dev_priv);
5495 mutex_unlock(&dev_priv->rps.hw_lock);
5496 }
5497
5498 static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
5499 {
5500 u32 val, rp0;
5501
5502 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5503
5504 switch (INTEL_INFO(dev_priv)->eu_total) {
5505 case 8:
5506 /* (2 * 4) config */
5507 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5508 break;
5509 case 12:
5510 /* (2 * 6) config */
5511 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5512 break;
5513 case 16:
5514 /* (2 * 8) config */
5515 default:
5516 /* Setting (2 * 8) Min RP0 for any other combination */
5517 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5518 break;
5519 }
5520
5521 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5522
5523 return rp0;
5524 }
5525
5526 static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5527 {
5528 u32 val, rpe;
5529
5530 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5531 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5532
5533 return rpe;
5534 }
5535
5536 static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5537 {
5538 u32 val, rp1;
5539
5540 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5541 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5542
5543 return rp1;
5544 }
5545
5546 static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5547 {
5548 u32 val, rp1;
5549
5550 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5551
5552 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5553
5554 return rp1;
5555 }
5556
5557 static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
5558 {
5559 u32 val, rp0;
5560
5561 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5562
5563 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5564 /* Clamp to max */
5565 rp0 = min_t(u32, rp0, 0xea);
5566
5567 return rp0;
5568 }
5569
5570 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5571 {
5572 u32 val, rpe;
5573
5574 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
5575 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
5576 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
5577 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5578
5579 return rpe;
5580 }
5581
5582 static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
5583 {
5584 u32 val;
5585
5586 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5587 /*
5588 * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
5589 * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
5590 * a BYT-M B0 the above register contains 0xbf. Moreover when setting
5591 * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
5592 * to make sure it matches what Punit accepts.
5593 */
5594 return max_t(u32, val, 0xc0);
5595 }
5596
5597 /* Check that the pctx buffer wasn't move under us. */
5598 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5599 {
5600 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5601
5602 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5603 dev_priv->vlv_pctx->stolen->start);
5604 }
5605
5606
5607 /* Check that the pcbr address is not empty. */
5608 static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5609 {
5610 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5611
5612 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5613 }
5614
5615 static void cherryview_setup_pctx(struct drm_i915_private *dev_priv)
5616 {
5617 struct i915_ggtt *ggtt = &dev_priv->ggtt;
5618 unsigned long pctx_paddr, paddr;
5619 u32 pcbr;
5620 int pctx_size = 32*1024;
5621
5622 pcbr = I915_READ(VLV_PCBR);
5623 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
5624 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5625 paddr = (dev_priv->mm.stolen_base +
5626 (ggtt->stolen_size - pctx_size));
5627
5628 pctx_paddr = (paddr & (~4095));
5629 I915_WRITE(VLV_PCBR, pctx_paddr);
5630 }
5631
5632 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5633 }
5634
5635 static void valleyview_setup_pctx(struct drm_i915_private *dev_priv)
5636 {
5637 struct drm_i915_gem_object *pctx;
5638 unsigned long pctx_paddr;
5639 u32 pcbr;
5640 int pctx_size = 24*1024;
5641
5642 mutex_lock(&dev_priv->dev->struct_mutex);
5643
5644 pcbr = I915_READ(VLV_PCBR);
5645 if (pcbr) {
5646 /* BIOS set it up already, grab the pre-alloc'd space */
5647 int pcbr_offset;
5648
5649 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
5650 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
5651 pcbr_offset,
5652 I915_GTT_OFFSET_NONE,
5653 pctx_size);
5654 goto out;
5655 }
5656
5657 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5658
5659 /*
5660 * From the Gunit register HAS:
5661 * The Gfx driver is expected to program this register and ensure
5662 * proper allocation within Gfx stolen memory. For example, this
5663 * register should be programmed such than the PCBR range does not
5664 * overlap with other ranges, such as the frame buffer, protected
5665 * memory, or any other relevant ranges.
5666 */
5667 pctx = i915_gem_object_create_stolen(dev_priv->dev, pctx_size);
5668 if (!pctx) {
5669 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
5670 goto out;
5671 }
5672
5673 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5674 I915_WRITE(VLV_PCBR, pctx_paddr);
5675
5676 out:
5677 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5678 dev_priv->vlv_pctx = pctx;
5679 mutex_unlock(&dev_priv->dev->struct_mutex);
5680 }
5681
5682 static void valleyview_cleanup_pctx(struct drm_i915_private *dev_priv)
5683 {
5684 if (WARN_ON(!dev_priv->vlv_pctx))
5685 return;
5686
5687 drm_gem_object_unreference_unlocked(&dev_priv->vlv_pctx->base);
5688 dev_priv->vlv_pctx = NULL;
5689 }
5690
5691 static void vlv_init_gpll_ref_freq(struct drm_i915_private *dev_priv)
5692 {
5693 dev_priv->rps.gpll_ref_freq =
5694 vlv_get_cck_clock(dev_priv, "GPLL ref",
5695 CCK_GPLL_CLOCK_CONTROL,
5696 dev_priv->czclk_freq);
5697
5698 DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n",
5699 dev_priv->rps.gpll_ref_freq);
5700 }
5701
5702 static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv)
5703 {
5704 u32 val;
5705
5706 valleyview_setup_pctx(dev_priv);
5707
5708 vlv_init_gpll_ref_freq(dev_priv);
5709
5710 mutex_lock(&dev_priv->rps.hw_lock);
5711
5712 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5713 switch ((val >> 6) & 3) {
5714 case 0:
5715 case 1:
5716 dev_priv->mem_freq = 800;
5717 break;
5718 case 2:
5719 dev_priv->mem_freq = 1066;
5720 break;
5721 case 3:
5722 dev_priv->mem_freq = 1333;
5723 break;
5724 }
5725 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5726
5727 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5728 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5729 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5730 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5731 dev_priv->rps.max_freq);
5732
5733 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5734 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5735 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5736 dev_priv->rps.efficient_freq);
5737
5738 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5739 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
5740 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5741 dev_priv->rps.rp1_freq);
5742
5743 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5744 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5745 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5746 dev_priv->rps.min_freq);
5747
5748 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5749
5750 /* Preserve min/max settings in case of re-init */
5751 if (dev_priv->rps.max_freq_softlimit == 0)
5752 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5753
5754 if (dev_priv->rps.min_freq_softlimit == 0)
5755 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5756
5757 mutex_unlock(&dev_priv->rps.hw_lock);
5758 }
5759
5760 static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv)
5761 {
5762 u32 val;
5763
5764 cherryview_setup_pctx(dev_priv);
5765
5766 vlv_init_gpll_ref_freq(dev_priv);
5767
5768 mutex_lock(&dev_priv->rps.hw_lock);
5769
5770 mutex_lock(&dev_priv->sb_lock);
5771 val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
5772 mutex_unlock(&dev_priv->sb_lock);
5773
5774 switch ((val >> 2) & 0x7) {
5775 case 3:
5776 dev_priv->mem_freq = 2000;
5777 break;
5778 default:
5779 dev_priv->mem_freq = 1600;
5780 break;
5781 }
5782 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5783
5784 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5785 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5786 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5787 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5788 dev_priv->rps.max_freq);
5789
5790 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5791 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5792 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5793 dev_priv->rps.efficient_freq);
5794
5795 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5796 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
5797 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5798 dev_priv->rps.rp1_freq);
5799
5800 /* PUnit validated range is only [RPe, RP0] */
5801 dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
5802 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5803 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5804 dev_priv->rps.min_freq);
5805
5806 WARN_ONCE((dev_priv->rps.max_freq |
5807 dev_priv->rps.efficient_freq |
5808 dev_priv->rps.rp1_freq |
5809 dev_priv->rps.min_freq) & 1,
5810 "Odd GPU freq values\n");
5811
5812 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5813
5814 /* Preserve min/max settings in case of re-init */
5815 if (dev_priv->rps.max_freq_softlimit == 0)
5816 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5817
5818 if (dev_priv->rps.min_freq_softlimit == 0)
5819 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5820
5821 mutex_unlock(&dev_priv->rps.hw_lock);
5822 }
5823
5824 static void valleyview_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
5825 {
5826 valleyview_cleanup_pctx(dev_priv);
5827 }
5828
5829 static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
5830 {
5831 struct intel_engine_cs *engine;
5832 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
5833
5834 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5835
5836 gtfifodbg = I915_READ(GTFIFODBG) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV |
5837 GT_FIFO_FREE_ENTRIES_CHV);
5838 if (gtfifodbg) {
5839 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5840 gtfifodbg);
5841 I915_WRITE(GTFIFODBG, gtfifodbg);
5842 }
5843
5844 cherryview_check_pctx(dev_priv);
5845
5846 /* 1a & 1b: Get forcewake during program sequence. Although the driver
5847 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5848 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5849
5850 /* Disable RC states. */
5851 I915_WRITE(GEN6_RC_CONTROL, 0);
5852
5853 /* 2a: Program RC6 thresholds.*/
5854 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5855 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5856 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5857
5858 for_each_engine(engine, dev_priv)
5859 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5860 I915_WRITE(GEN6_RC_SLEEP, 0);
5861
5862 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
5863 I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
5864
5865 /* allows RC6 residency counter to work */
5866 I915_WRITE(VLV_COUNTER_CONTROL,
5867 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
5868 VLV_MEDIA_RC6_COUNT_EN |
5869 VLV_RENDER_RC6_COUNT_EN));
5870
5871 /* For now we assume BIOS is allocating and populating the PCBR */
5872 pcbr = I915_READ(VLV_PCBR);
5873
5874 /* 3: Enable RC6 */
5875 if ((intel_enable_rc6() & INTEL_RC6_ENABLE) &&
5876 (pcbr >> VLV_PCBR_ADDR_SHIFT))
5877 rc6_mode = GEN7_RC_CTL_TO_MODE;
5878
5879 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5880
5881 /* 4 Program defaults and thresholds for RPS*/
5882 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
5883 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5884 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5885 I915_WRITE(GEN6_RP_UP_EI, 66000);
5886 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5887
5888 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5889
5890 /* 5: Enable RPS */
5891 I915_WRITE(GEN6_RP_CONTROL,
5892 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5893 GEN6_RP_MEDIA_IS_GFX |
5894 GEN6_RP_ENABLE |
5895 GEN6_RP_UP_BUSY_AVG |
5896 GEN6_RP_DOWN_IDLE_AVG);
5897
5898 /* Setting Fixed Bias */
5899 val = VLV_OVERRIDE_EN |
5900 VLV_SOC_TDP_EN |
5901 CHV_BIAS_CPU_50_SOC_50;
5902 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5903
5904 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5905
5906 /* RPS code assumes GPLL is used */
5907 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5908
5909 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
5910 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5911
5912 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5913 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5914 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
5915 dev_priv->rps.cur_freq);
5916
5917 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5918 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq),
5919 dev_priv->rps.idle_freq);
5920
5921 valleyview_set_rps(dev_priv, dev_priv->rps.idle_freq);
5922
5923 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5924 }
5925
5926 static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
5927 {
5928 struct intel_engine_cs *engine;
5929 u32 gtfifodbg, val, rc6_mode = 0;
5930
5931 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5932
5933 valleyview_check_pctx(dev_priv);
5934
5935 gtfifodbg = I915_READ(GTFIFODBG);
5936 if (gtfifodbg) {
5937 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5938 gtfifodbg);
5939 I915_WRITE(GTFIFODBG, gtfifodbg);
5940 }
5941
5942 /* If VLV, Forcewake all wells, else re-direct to regular path */
5943 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5944
5945 /* Disable RC states. */
5946 I915_WRITE(GEN6_RC_CONTROL, 0);
5947
5948 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
5949 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5950 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5951 I915_WRITE(GEN6_RP_UP_EI, 66000);
5952 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5953
5954 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5955
5956 I915_WRITE(GEN6_RP_CONTROL,
5957 GEN6_RP_MEDIA_TURBO |
5958 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5959 GEN6_RP_MEDIA_IS_GFX |
5960 GEN6_RP_ENABLE |
5961 GEN6_RP_UP_BUSY_AVG |
5962 GEN6_RP_DOWN_IDLE_CONT);
5963
5964 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
5965 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5966 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5967
5968 for_each_engine(engine, dev_priv)
5969 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5970
5971 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
5972
5973 /* allows RC6 residency counter to work */
5974 I915_WRITE(VLV_COUNTER_CONTROL,
5975 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
5976 VLV_RENDER_RC0_COUNT_EN |
5977 VLV_MEDIA_RC6_COUNT_EN |
5978 VLV_RENDER_RC6_COUNT_EN));
5979
5980 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
5981 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
5982
5983 intel_print_rc6_info(dev_priv, rc6_mode);
5984
5985 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5986
5987 /* Setting Fixed Bias */
5988 val = VLV_OVERRIDE_EN |
5989 VLV_SOC_TDP_EN |
5990 VLV_BIAS_CPU_125_SOC_875;
5991 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5992
5993 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5994
5995 /* RPS code assumes GPLL is used */
5996 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5997
5998 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
5999 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
6000
6001 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
6002 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
6003 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
6004 dev_priv->rps.cur_freq);
6005
6006 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
6007 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq),
6008 dev_priv->rps.idle_freq);
6009
6010 valleyview_set_rps(dev_priv, dev_priv->rps.idle_freq);
6011
6012 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6013 }
6014
6015 static unsigned long intel_pxfreq(u32 vidfreq)
6016 {
6017 unsigned long freq;
6018 int div = (vidfreq & 0x3f0000) >> 16;
6019 int post = (vidfreq & 0x3000) >> 12;
6020 int pre = (vidfreq & 0x7);
6021
6022 if (!pre)
6023 return 0;
6024
6025 freq = ((div * 133333) / ((1<<post) * pre));
6026
6027 return freq;
6028 }
6029
6030 static const struct cparams {
6031 u16 i;
6032 u16 t;
6033 u16 m;
6034 u16 c;
6035 } cparams[] = {
6036 { 1, 1333, 301, 28664 },
6037 { 1, 1066, 294, 24460 },
6038 { 1, 800, 294, 25192 },
6039 { 0, 1333, 276, 27605 },
6040 { 0, 1066, 276, 27605 },
6041 { 0, 800, 231, 23784 },
6042 };
6043
6044 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
6045 {
6046 u64 total_count, diff, ret;
6047 u32 count1, count2, count3, m = 0, c = 0;
6048 unsigned long now = jiffies_to_msecs(jiffies), diff1;
6049 int i;
6050
6051 assert_spin_locked(&mchdev_lock);
6052
6053 diff1 = now - dev_priv->ips.last_time1;
6054
6055 /* Prevent division-by-zero if we are asking too fast.
6056 * Also, we don't get interesting results if we are polling
6057 * faster than once in 10ms, so just return the saved value
6058 * in such cases.
6059 */
6060 if (diff1 <= 10)
6061 return dev_priv->ips.chipset_power;
6062
6063 count1 = I915_READ(DMIEC);
6064 count2 = I915_READ(DDREC);
6065 count3 = I915_READ(CSIEC);
6066
6067 total_count = count1 + count2 + count3;
6068
6069 /* FIXME: handle per-counter overflow */
6070 if (total_count < dev_priv->ips.last_count1) {
6071 diff = ~0UL - dev_priv->ips.last_count1;
6072 diff += total_count;
6073 } else {
6074 diff = total_count - dev_priv->ips.last_count1;
6075 }
6076
6077 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
6078 if (cparams[i].i == dev_priv->ips.c_m &&
6079 cparams[i].t == dev_priv->ips.r_t) {
6080 m = cparams[i].m;
6081 c = cparams[i].c;
6082 break;
6083 }
6084 }
6085
6086 diff = div_u64(diff, diff1);
6087 ret = ((m * diff) + c);
6088 ret = div_u64(ret, 10);
6089
6090 dev_priv->ips.last_count1 = total_count;
6091 dev_priv->ips.last_time1 = now;
6092
6093 dev_priv->ips.chipset_power = ret;
6094
6095 return ret;
6096 }
6097
6098 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
6099 {
6100 unsigned long val;
6101
6102 if (INTEL_INFO(dev_priv)->gen != 5)
6103 return 0;
6104
6105 spin_lock_irq(&mchdev_lock);
6106
6107 val = __i915_chipset_val(dev_priv);
6108
6109 spin_unlock_irq(&mchdev_lock);
6110
6111 return val;
6112 }
6113
6114 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
6115 {
6116 unsigned long m, x, b;
6117 u32 tsfs;
6118
6119 tsfs = I915_READ(TSFS);
6120
6121 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
6122 x = I915_READ8(TR1);
6123
6124 b = tsfs & TSFS_INTR_MASK;
6125
6126 return ((m * x) / 127) - b;
6127 }
6128
6129 static int _pxvid_to_vd(u8 pxvid)
6130 {
6131 if (pxvid == 0)
6132 return 0;
6133
6134 if (pxvid >= 8 && pxvid < 31)
6135 pxvid = 31;
6136
6137 return (pxvid + 2) * 125;
6138 }
6139
6140 static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
6141 {
6142 const int vd = _pxvid_to_vd(pxvid);
6143 const int vm = vd - 1125;
6144
6145 if (INTEL_INFO(dev_priv)->is_mobile)
6146 return vm > 0 ? vm : 0;
6147
6148 return vd;
6149 }
6150
6151 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
6152 {
6153 u64 now, diff, diffms;
6154 u32 count;
6155
6156 assert_spin_locked(&mchdev_lock);
6157
6158 now = ktime_get_raw_ns();
6159 diffms = now - dev_priv->ips.last_time2;
6160 do_div(diffms, NSEC_PER_MSEC);
6161
6162 /* Don't divide by 0 */
6163 if (!diffms)
6164 return;
6165
6166 count = I915_READ(GFXEC);
6167
6168 if (count < dev_priv->ips.last_count2) {
6169 diff = ~0UL - dev_priv->ips.last_count2;
6170 diff += count;
6171 } else {
6172 diff = count - dev_priv->ips.last_count2;
6173 }
6174
6175 dev_priv->ips.last_count2 = count;
6176 dev_priv->ips.last_time2 = now;
6177
6178 /* More magic constants... */
6179 diff = diff * 1181;
6180 diff = div_u64(diff, diffms * 10);
6181 dev_priv->ips.gfx_power = diff;
6182 }
6183
6184 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
6185 {
6186 if (INTEL_INFO(dev_priv)->gen != 5)
6187 return;
6188
6189 spin_lock_irq(&mchdev_lock);
6190
6191 __i915_update_gfx_val(dev_priv);
6192
6193 spin_unlock_irq(&mchdev_lock);
6194 }
6195
6196 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
6197 {
6198 unsigned long t, corr, state1, corr2, state2;
6199 u32 pxvid, ext_v;
6200
6201 assert_spin_locked(&mchdev_lock);
6202
6203 pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
6204 pxvid = (pxvid >> 24) & 0x7f;
6205 ext_v = pvid_to_extvid(dev_priv, pxvid);
6206
6207 state1 = ext_v;
6208
6209 t = i915_mch_val(dev_priv);
6210
6211 /* Revel in the empirically derived constants */
6212
6213 /* Correction factor in 1/100000 units */
6214 if (t > 80)
6215 corr = ((t * 2349) + 135940);
6216 else if (t >= 50)
6217 corr = ((t * 964) + 29317);
6218 else /* < 50 */
6219 corr = ((t * 301) + 1004);
6220
6221 corr = corr * ((150142 * state1) / 10000 - 78642);
6222 corr /= 100000;
6223 corr2 = (corr * dev_priv->ips.corr);
6224
6225 state2 = (corr2 * state1) / 10000;
6226 state2 /= 100; /* convert to mW */
6227
6228 __i915_update_gfx_val(dev_priv);
6229
6230 return dev_priv->ips.gfx_power + state2;
6231 }
6232
6233 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
6234 {
6235 unsigned long val;
6236
6237 if (INTEL_INFO(dev_priv)->gen != 5)
6238 return 0;
6239
6240 spin_lock_irq(&mchdev_lock);
6241
6242 val = __i915_gfx_val(dev_priv);
6243
6244 spin_unlock_irq(&mchdev_lock);
6245
6246 return val;
6247 }
6248
6249 /**
6250 * i915_read_mch_val - return value for IPS use
6251 *
6252 * Calculate and return a value for the IPS driver to use when deciding whether
6253 * we have thermal and power headroom to increase CPU or GPU power budget.
6254 */
6255 unsigned long i915_read_mch_val(void)
6256 {
6257 struct drm_i915_private *dev_priv;
6258 unsigned long chipset_val, graphics_val, ret = 0;
6259
6260 spin_lock_irq(&mchdev_lock);
6261 if (!i915_mch_dev)
6262 goto out_unlock;
6263 dev_priv = i915_mch_dev;
6264
6265 chipset_val = __i915_chipset_val(dev_priv);
6266 graphics_val = __i915_gfx_val(dev_priv);
6267
6268 ret = chipset_val + graphics_val;
6269
6270 out_unlock:
6271 spin_unlock_irq(&mchdev_lock);
6272
6273 return ret;
6274 }
6275 EXPORT_SYMBOL_GPL(i915_read_mch_val);
6276
6277 /**
6278 * i915_gpu_raise - raise GPU frequency limit
6279 *
6280 * Raise the limit; IPS indicates we have thermal headroom.
6281 */
6282 bool i915_gpu_raise(void)
6283 {
6284 struct drm_i915_private *dev_priv;
6285 bool ret = true;
6286
6287 spin_lock_irq(&mchdev_lock);
6288 if (!i915_mch_dev) {
6289 ret = false;
6290 goto out_unlock;
6291 }
6292 dev_priv = i915_mch_dev;
6293
6294 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
6295 dev_priv->ips.max_delay--;
6296
6297 out_unlock:
6298 spin_unlock_irq(&mchdev_lock);
6299
6300 return ret;
6301 }
6302 EXPORT_SYMBOL_GPL(i915_gpu_raise);
6303
6304 /**
6305 * i915_gpu_lower - lower GPU frequency limit
6306 *
6307 * IPS indicates we're close to a thermal limit, so throttle back the GPU
6308 * frequency maximum.
6309 */
6310 bool i915_gpu_lower(void)
6311 {
6312 struct drm_i915_private *dev_priv;
6313 bool ret = true;
6314
6315 spin_lock_irq(&mchdev_lock);
6316 if (!i915_mch_dev) {
6317 ret = false;
6318 goto out_unlock;
6319 }
6320 dev_priv = i915_mch_dev;
6321
6322 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
6323 dev_priv->ips.max_delay++;
6324
6325 out_unlock:
6326 spin_unlock_irq(&mchdev_lock);
6327
6328 return ret;
6329 }
6330 EXPORT_SYMBOL_GPL(i915_gpu_lower);
6331
6332 /**
6333 * i915_gpu_busy - indicate GPU business to IPS
6334 *
6335 * Tell the IPS driver whether or not the GPU is busy.
6336 */
6337 bool i915_gpu_busy(void)
6338 {
6339 struct drm_i915_private *dev_priv;
6340 struct intel_engine_cs *engine;
6341 bool ret = false;
6342
6343 spin_lock_irq(&mchdev_lock);
6344 if (!i915_mch_dev)
6345 goto out_unlock;
6346 dev_priv = i915_mch_dev;
6347
6348 for_each_engine(engine, dev_priv)
6349 ret |= !list_empty(&engine->request_list);
6350
6351 out_unlock:
6352 spin_unlock_irq(&mchdev_lock);
6353
6354 return ret;
6355 }
6356 EXPORT_SYMBOL_GPL(i915_gpu_busy);
6357
6358 /**
6359 * i915_gpu_turbo_disable - disable graphics turbo
6360 *
6361 * Disable graphics turbo by resetting the max frequency and setting the
6362 * current frequency to the default.
6363 */
6364 bool i915_gpu_turbo_disable(void)
6365 {
6366 struct drm_i915_private *dev_priv;
6367 bool ret = true;
6368
6369 spin_lock_irq(&mchdev_lock);
6370 if (!i915_mch_dev) {
6371 ret = false;
6372 goto out_unlock;
6373 }
6374 dev_priv = i915_mch_dev;
6375
6376 dev_priv->ips.max_delay = dev_priv->ips.fstart;
6377
6378 if (!ironlake_set_drps(dev_priv, dev_priv->ips.fstart))
6379 ret = false;
6380
6381 out_unlock:
6382 spin_unlock_irq(&mchdev_lock);
6383
6384 return ret;
6385 }
6386 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6387
6388 /**
6389 * Tells the intel_ips driver that the i915 driver is now loaded, if
6390 * IPS got loaded first.
6391 *
6392 * This awkward dance is so that neither module has to depend on the
6393 * other in order for IPS to do the appropriate communication of
6394 * GPU turbo limits to i915.
6395 */
6396 static void
6397 ips_ping_for_i915_load(void)
6398 {
6399 void (*link)(void);
6400
6401 link = symbol_get(ips_link_to_i915_driver);
6402 if (link) {
6403 link();
6404 symbol_put(ips_link_to_i915_driver);
6405 }
6406 }
6407
6408 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6409 {
6410 /* We only register the i915 ips part with intel-ips once everything is
6411 * set up, to avoid intel-ips sneaking in and reading bogus values. */
6412 spin_lock_irq(&mchdev_lock);
6413 i915_mch_dev = dev_priv;
6414 spin_unlock_irq(&mchdev_lock);
6415
6416 ips_ping_for_i915_load();
6417 }
6418
6419 void intel_gpu_ips_teardown(void)
6420 {
6421 spin_lock_irq(&mchdev_lock);
6422 i915_mch_dev = NULL;
6423 spin_unlock_irq(&mchdev_lock);
6424 }
6425
6426 static void intel_init_emon(struct drm_i915_private *dev_priv)
6427 {
6428 u32 lcfuse;
6429 u8 pxw[16];
6430 int i;
6431
6432 /* Disable to program */
6433 I915_WRITE(ECR, 0);
6434 POSTING_READ(ECR);
6435
6436 /* Program energy weights for various events */
6437 I915_WRITE(SDEW, 0x15040d00);
6438 I915_WRITE(CSIEW0, 0x007f0000);
6439 I915_WRITE(CSIEW1, 0x1e220004);
6440 I915_WRITE(CSIEW2, 0x04000004);
6441
6442 for (i = 0; i < 5; i++)
6443 I915_WRITE(PEW(i), 0);
6444 for (i = 0; i < 3; i++)
6445 I915_WRITE(DEW(i), 0);
6446
6447 /* Program P-state weights to account for frequency power adjustment */
6448 for (i = 0; i < 16; i++) {
6449 u32 pxvidfreq = I915_READ(PXVFREQ(i));
6450 unsigned long freq = intel_pxfreq(pxvidfreq);
6451 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6452 PXVFREQ_PX_SHIFT;
6453 unsigned long val;
6454
6455 val = vid * vid;
6456 val *= (freq / 1000);
6457 val *= 255;
6458 val /= (127*127*900);
6459 if (val > 0xff)
6460 DRM_ERROR("bad pxval: %ld\n", val);
6461 pxw[i] = val;
6462 }
6463 /* Render standby states get 0 weight */
6464 pxw[14] = 0;
6465 pxw[15] = 0;
6466
6467 for (i = 0; i < 4; i++) {
6468 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6469 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
6470 I915_WRITE(PXW(i), val);
6471 }
6472
6473 /* Adjust magic regs to magic values (more experimental results) */
6474 I915_WRITE(OGW0, 0);
6475 I915_WRITE(OGW1, 0);
6476 I915_WRITE(EG0, 0x00007f00);
6477 I915_WRITE(EG1, 0x0000000e);
6478 I915_WRITE(EG2, 0x000e0000);
6479 I915_WRITE(EG3, 0x68000300);
6480 I915_WRITE(EG4, 0x42000000);
6481 I915_WRITE(EG5, 0x00140031);
6482 I915_WRITE(EG6, 0);
6483 I915_WRITE(EG7, 0);
6484
6485 for (i = 0; i < 8; i++)
6486 I915_WRITE(PXWL(i), 0);
6487
6488 /* Enable PMON + select events */
6489 I915_WRITE(ECR, 0x80000019);
6490
6491 lcfuse = I915_READ(LCFUSE02);
6492
6493 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
6494 }
6495
6496 void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
6497 {
6498 /*
6499 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6500 * requirement.
6501 */
6502 if (!i915.enable_rc6) {
6503 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6504 intel_runtime_pm_get(dev_priv);
6505 }
6506
6507 if (IS_CHERRYVIEW(dev_priv))
6508 cherryview_init_gt_powersave(dev_priv);
6509 else if (IS_VALLEYVIEW(dev_priv))
6510 valleyview_init_gt_powersave(dev_priv);
6511 }
6512
6513 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
6514 {
6515 if (IS_CHERRYVIEW(dev_priv))
6516 return;
6517 else if (IS_VALLEYVIEW(dev_priv))
6518 valleyview_cleanup_gt_powersave(dev_priv);
6519
6520 if (!i915.enable_rc6)
6521 intel_runtime_pm_put(dev_priv);
6522 }
6523
6524 static void gen6_suspend_rps(struct drm_i915_private *dev_priv)
6525 {
6526 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
6527
6528 gen6_disable_rps_interrupts(dev_priv);
6529 }
6530
6531 /**
6532 * intel_suspend_gt_powersave - suspend PM work and helper threads
6533 * @dev_priv: i915 device
6534 *
6535 * We don't want to disable RC6 or other features here, we just want
6536 * to make sure any work we've queued has finished and won't bother
6537 * us while we're suspended.
6538 */
6539 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
6540 {
6541 if (INTEL_GEN(dev_priv) < 6)
6542 return;
6543
6544 gen6_suspend_rps(dev_priv);
6545
6546 /* Force GPU to min freq during suspend */
6547 gen6_rps_idle(dev_priv);
6548 }
6549
6550 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
6551 {
6552 if (IS_IRONLAKE_M(dev_priv)) {
6553 ironlake_disable_drps(dev_priv);
6554 } else if (INTEL_INFO(dev_priv)->gen >= 6) {
6555 intel_suspend_gt_powersave(dev_priv);
6556
6557 mutex_lock(&dev_priv->rps.hw_lock);
6558 if (INTEL_INFO(dev_priv)->gen >= 9) {
6559 gen9_disable_rc6(dev_priv);
6560 gen9_disable_rps(dev_priv);
6561 } else if (IS_CHERRYVIEW(dev_priv))
6562 cherryview_disable_rps(dev_priv);
6563 else if (IS_VALLEYVIEW(dev_priv))
6564 valleyview_disable_rps(dev_priv);
6565 else
6566 gen6_disable_rps(dev_priv);
6567
6568 dev_priv->rps.enabled = false;
6569 mutex_unlock(&dev_priv->rps.hw_lock);
6570 }
6571 }
6572
6573 static void intel_gen6_powersave_work(struct work_struct *work)
6574 {
6575 struct drm_i915_private *dev_priv =
6576 container_of(work, struct drm_i915_private,
6577 rps.delayed_resume_work.work);
6578
6579 mutex_lock(&dev_priv->rps.hw_lock);
6580
6581 gen6_reset_rps_interrupts(dev_priv);
6582
6583 if (IS_CHERRYVIEW(dev_priv)) {
6584 cherryview_enable_rps(dev_priv);
6585 } else if (IS_VALLEYVIEW(dev_priv)) {
6586 valleyview_enable_rps(dev_priv);
6587 } else if (INTEL_INFO(dev_priv)->gen >= 9) {
6588 gen9_enable_rc6(dev_priv);
6589 gen9_enable_rps(dev_priv);
6590 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
6591 __gen6_update_ring_freq(dev_priv);
6592 } else if (IS_BROADWELL(dev_priv)) {
6593 gen8_enable_rps(dev_priv);
6594 __gen6_update_ring_freq(dev_priv);
6595 } else {
6596 gen6_enable_rps(dev_priv);
6597 __gen6_update_ring_freq(dev_priv);
6598 }
6599
6600 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6601 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6602
6603 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6604 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6605
6606 dev_priv->rps.enabled = true;
6607
6608 gen6_enable_rps_interrupts(dev_priv);
6609
6610 mutex_unlock(&dev_priv->rps.hw_lock);
6611
6612 intel_runtime_pm_put(dev_priv);
6613 }
6614
6615 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
6616 {
6617 /* Powersaving is controlled by the host when inside a VM */
6618 if (intel_vgpu_active(dev_priv))
6619 return;
6620
6621 if (IS_IRONLAKE_M(dev_priv)) {
6622 ironlake_enable_drps(dev_priv);
6623 mutex_lock(&dev_priv->dev->struct_mutex);
6624 intel_init_emon(dev_priv);
6625 mutex_unlock(&dev_priv->dev->struct_mutex);
6626 } else if (INTEL_INFO(dev_priv)->gen >= 6) {
6627 /*
6628 * PCU communication is slow and this doesn't need to be
6629 * done at any specific time, so do this out of our fast path
6630 * to make resume and init faster.
6631 *
6632 * We depend on the HW RC6 power context save/restore
6633 * mechanism when entering D3 through runtime PM suspend. So
6634 * disable RPM until RPS/RC6 is properly setup. We can only
6635 * get here via the driver load/system resume/runtime resume
6636 * paths, so the _noresume version is enough (and in case of
6637 * runtime resume it's necessary).
6638 */
6639 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
6640 round_jiffies_up_relative(HZ)))
6641 intel_runtime_pm_get_noresume(dev_priv);
6642 }
6643 }
6644
6645 void intel_reset_gt_powersave(struct drm_i915_private *dev_priv)
6646 {
6647 if (INTEL_INFO(dev_priv)->gen < 6)
6648 return;
6649
6650 gen6_suspend_rps(dev_priv);
6651 dev_priv->rps.enabled = false;
6652 }
6653
6654 static void ibx_init_clock_gating(struct drm_device *dev)
6655 {
6656 struct drm_i915_private *dev_priv = dev->dev_private;
6657
6658 /*
6659 * On Ibex Peak and Cougar Point, we need to disable clock
6660 * gating for the panel power sequencer or it will fail to
6661 * start up when no ports are active.
6662 */
6663 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6664 }
6665
6666 static void g4x_disable_trickle_feed(struct drm_device *dev)
6667 {
6668 struct drm_i915_private *dev_priv = dev->dev_private;
6669 enum pipe pipe;
6670
6671 for_each_pipe(dev_priv, pipe) {
6672 I915_WRITE(DSPCNTR(pipe),
6673 I915_READ(DSPCNTR(pipe)) |
6674 DISPPLANE_TRICKLE_FEED_DISABLE);
6675
6676 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6677 POSTING_READ(DSPSURF(pipe));
6678 }
6679 }
6680
6681 static void ilk_init_lp_watermarks(struct drm_device *dev)
6682 {
6683 struct drm_i915_private *dev_priv = dev->dev_private;
6684
6685 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6686 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6687 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6688
6689 /*
6690 * Don't touch WM1S_LP_EN here.
6691 * Doing so could cause underruns.
6692 */
6693 }
6694
6695 static void ironlake_init_clock_gating(struct drm_device *dev)
6696 {
6697 struct drm_i915_private *dev_priv = dev->dev_private;
6698 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6699
6700 /*
6701 * Required for FBC
6702 * WaFbcDisableDpfcClockGating:ilk
6703 */
6704 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6705 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6706 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6707
6708 I915_WRITE(PCH_3DCGDIS0,
6709 MARIUNIT_CLOCK_GATE_DISABLE |
6710 SVSMUNIT_CLOCK_GATE_DISABLE);
6711 I915_WRITE(PCH_3DCGDIS1,
6712 VFMUNIT_CLOCK_GATE_DISABLE);
6713
6714 /*
6715 * According to the spec the following bits should be set in
6716 * order to enable memory self-refresh
6717 * The bit 22/21 of 0x42004
6718 * The bit 5 of 0x42020
6719 * The bit 15 of 0x45000
6720 */
6721 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6722 (I915_READ(ILK_DISPLAY_CHICKEN2) |
6723 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
6724 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6725 I915_WRITE(DISP_ARB_CTL,
6726 (I915_READ(DISP_ARB_CTL) |
6727 DISP_FBC_WM_DIS));
6728
6729 ilk_init_lp_watermarks(dev);
6730
6731 /*
6732 * Based on the document from hardware guys the following bits
6733 * should be set unconditionally in order to enable FBC.
6734 * The bit 22 of 0x42000
6735 * The bit 22 of 0x42004
6736 * The bit 7,8,9 of 0x42020.
6737 */
6738 if (IS_IRONLAKE_M(dev)) {
6739 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6740 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6741 I915_READ(ILK_DISPLAY_CHICKEN1) |
6742 ILK_FBCQ_DIS);
6743 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6744 I915_READ(ILK_DISPLAY_CHICKEN2) |
6745 ILK_DPARB_GATE);
6746 }
6747
6748 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6749
6750 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6751 I915_READ(ILK_DISPLAY_CHICKEN2) |
6752 ILK_ELPIN_409_SELECT);
6753 I915_WRITE(_3D_CHICKEN2,
6754 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6755 _3D_CHICKEN2_WM_READ_PIPELINED);
6756
6757 /* WaDisableRenderCachePipelinedFlush:ilk */
6758 I915_WRITE(CACHE_MODE_0,
6759 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6760
6761 /* WaDisable_RenderCache_OperationalFlush:ilk */
6762 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6763
6764 g4x_disable_trickle_feed(dev);
6765
6766 ibx_init_clock_gating(dev);
6767 }
6768
6769 static void cpt_init_clock_gating(struct drm_device *dev)
6770 {
6771 struct drm_i915_private *dev_priv = dev->dev_private;
6772 int pipe;
6773 uint32_t val;
6774
6775 /*
6776 * On Ibex Peak and Cougar Point, we need to disable clock
6777 * gating for the panel power sequencer or it will fail to
6778 * start up when no ports are active.
6779 */
6780 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6781 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6782 PCH_CPUNIT_CLOCK_GATE_DISABLE);
6783 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6784 DPLS_EDP_PPS_FIX_DIS);
6785 /* The below fixes the weird display corruption, a few pixels shifted
6786 * downward, on (only) LVDS of some HP laptops with IVY.
6787 */
6788 for_each_pipe(dev_priv, pipe) {
6789 val = I915_READ(TRANS_CHICKEN2(pipe));
6790 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6791 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6792 if (dev_priv->vbt.fdi_rx_polarity_inverted)
6793 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6794 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6795 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6796 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
6797 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6798 }
6799 /* WADP0ClockGatingDisable */
6800 for_each_pipe(dev_priv, pipe) {
6801 I915_WRITE(TRANS_CHICKEN1(pipe),
6802 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6803 }
6804 }
6805
6806 static void gen6_check_mch_setup(struct drm_device *dev)
6807 {
6808 struct drm_i915_private *dev_priv = dev->dev_private;
6809 uint32_t tmp;
6810
6811 tmp = I915_READ(MCH_SSKPD);
6812 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6813 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6814 tmp);
6815 }
6816
6817 static void gen6_init_clock_gating(struct drm_device *dev)
6818 {
6819 struct drm_i915_private *dev_priv = dev->dev_private;
6820 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6821
6822 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6823
6824 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6825 I915_READ(ILK_DISPLAY_CHICKEN2) |
6826 ILK_ELPIN_409_SELECT);
6827
6828 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
6829 I915_WRITE(_3D_CHICKEN,
6830 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
6831
6832 /* WaDisable_RenderCache_OperationalFlush:snb */
6833 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6834
6835 /*
6836 * BSpec recoomends 8x4 when MSAA is used,
6837 * however in practice 16x4 seems fastest.
6838 *
6839 * Note that PS/WM thread counts depend on the WIZ hashing
6840 * disable bit, which we don't touch here, but it's good
6841 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6842 */
6843 I915_WRITE(GEN6_GT_MODE,
6844 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6845
6846 ilk_init_lp_watermarks(dev);
6847
6848 I915_WRITE(CACHE_MODE_0,
6849 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6850
6851 I915_WRITE(GEN6_UCGCTL1,
6852 I915_READ(GEN6_UCGCTL1) |
6853 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
6854 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6855
6856 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
6857 * gating disable must be set. Failure to set it results in
6858 * flickering pixels due to Z write ordering failures after
6859 * some amount of runtime in the Mesa "fire" demo, and Unigine
6860 * Sanctuary and Tropics, and apparently anything else with
6861 * alpha test or pixel discard.
6862 *
6863 * According to the spec, bit 11 (RCCUNIT) must also be set,
6864 * but we didn't debug actual testcases to find it out.
6865 *
6866 * WaDisableRCCUnitClockGating:snb
6867 * WaDisableRCPBUnitClockGating:snb
6868 */
6869 I915_WRITE(GEN6_UCGCTL2,
6870 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
6871 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
6872
6873 /* WaStripsFansDisableFastClipPerformanceFix:snb */
6874 I915_WRITE(_3D_CHICKEN3,
6875 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6876
6877 /*
6878 * Bspec says:
6879 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
6880 * 3DSTATE_SF number of SF output attributes is more than 16."
6881 */
6882 I915_WRITE(_3D_CHICKEN3,
6883 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
6884
6885 /*
6886 * According to the spec the following bits should be
6887 * set in order to enable memory self-refresh and fbc:
6888 * The bit21 and bit22 of 0x42000
6889 * The bit21 and bit22 of 0x42004
6890 * The bit5 and bit7 of 0x42020
6891 * The bit14 of 0x70180
6892 * The bit14 of 0x71180
6893 *
6894 * WaFbcAsynchFlipDisableFbcQueue:snb
6895 */
6896 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6897 I915_READ(ILK_DISPLAY_CHICKEN1) |
6898 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6899 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6900 I915_READ(ILK_DISPLAY_CHICKEN2) |
6901 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
6902 I915_WRITE(ILK_DSPCLK_GATE_D,
6903 I915_READ(ILK_DSPCLK_GATE_D) |
6904 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
6905 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6906
6907 g4x_disable_trickle_feed(dev);
6908
6909 cpt_init_clock_gating(dev);
6910
6911 gen6_check_mch_setup(dev);
6912 }
6913
6914 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
6915 {
6916 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
6917
6918 /*
6919 * WaVSThreadDispatchOverride:ivb,vlv
6920 *
6921 * This actually overrides the dispatch
6922 * mode for all thread types.
6923 */
6924 reg &= ~GEN7_FF_SCHED_MASK;
6925 reg |= GEN7_FF_TS_SCHED_HW;
6926 reg |= GEN7_FF_VS_SCHED_HW;
6927 reg |= GEN7_FF_DS_SCHED_HW;
6928
6929 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
6930 }
6931
6932 static void lpt_init_clock_gating(struct drm_device *dev)
6933 {
6934 struct drm_i915_private *dev_priv = dev->dev_private;
6935
6936 /*
6937 * TODO: this bit should only be enabled when really needed, then
6938 * disabled when not needed anymore in order to save power.
6939 */
6940 if (HAS_PCH_LPT_LP(dev))
6941 I915_WRITE(SOUTH_DSPCLK_GATE_D,
6942 I915_READ(SOUTH_DSPCLK_GATE_D) |
6943 PCH_LP_PARTITION_LEVEL_DISABLE);
6944
6945 /* WADPOClockGatingDisable:hsw */
6946 I915_WRITE(TRANS_CHICKEN1(PIPE_A),
6947 I915_READ(TRANS_CHICKEN1(PIPE_A)) |
6948 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6949 }
6950
6951 static void lpt_suspend_hw(struct drm_device *dev)
6952 {
6953 struct drm_i915_private *dev_priv = dev->dev_private;
6954
6955 if (HAS_PCH_LPT_LP(dev)) {
6956 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
6957
6958 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6959 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6960 }
6961 }
6962
6963 static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
6964 int general_prio_credits,
6965 int high_prio_credits)
6966 {
6967 u32 misccpctl;
6968
6969 /* WaTempDisableDOPClkGating:bdw */
6970 misccpctl = I915_READ(GEN7_MISCCPCTL);
6971 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
6972
6973 I915_WRITE(GEN8_L3SQCREG1,
6974 L3_GENERAL_PRIO_CREDITS(general_prio_credits) |
6975 L3_HIGH_PRIO_CREDITS(high_prio_credits));
6976
6977 /*
6978 * Wait at least 100 clocks before re-enabling clock gating.
6979 * See the definition of L3SQCREG1 in BSpec.
6980 */
6981 POSTING_READ(GEN8_L3SQCREG1);
6982 udelay(1);
6983 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
6984 }
6985
6986 static void kabylake_init_clock_gating(struct drm_device *dev)
6987 {
6988 struct drm_i915_private *dev_priv = dev->dev_private;
6989
6990 gen9_init_clock_gating(dev);
6991
6992 /* WaDisableSDEUnitClockGating:kbl */
6993 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
6994 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6995 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6996
6997 /* WaDisableGamClockGating:kbl */
6998 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
6999 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7000 GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
7001
7002 /* WaFbcNukeOnHostModify:kbl */
7003 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7004 ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
7005 }
7006
7007 static void skylake_init_clock_gating(struct drm_device *dev)
7008 {
7009 struct drm_i915_private *dev_priv = dev->dev_private;
7010
7011 gen9_init_clock_gating(dev);
7012
7013 /* WAC6entrylatency:skl */
7014 I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
7015 FBC_LLC_FULLY_OPEN);
7016
7017 /* WaFbcNukeOnHostModify:skl */
7018 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7019 ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
7020 }
7021
7022 static void broadwell_init_clock_gating(struct drm_device *dev)
7023 {
7024 struct drm_i915_private *dev_priv = dev->dev_private;
7025 enum pipe pipe;
7026
7027 ilk_init_lp_watermarks(dev);
7028
7029 /* WaSwitchSolVfFArbitrationPriority:bdw */
7030 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
7031
7032 /* WaPsrDPAMaskVBlankInSRD:bdw */
7033 I915_WRITE(CHICKEN_PAR1_1,
7034 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
7035
7036 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
7037 for_each_pipe(dev_priv, pipe) {
7038 I915_WRITE(CHICKEN_PIPESL_1(pipe),
7039 I915_READ(CHICKEN_PIPESL_1(pipe)) |
7040 BDW_DPRS_MASK_VBLANK_SRD);
7041 }
7042
7043 /* WaVSRefCountFullforceMissDisable:bdw */
7044 /* WaDSRefCountFullforceMissDisable:bdw */
7045 I915_WRITE(GEN7_FF_THREAD_MODE,
7046 I915_READ(GEN7_FF_THREAD_MODE) &
7047 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
7048
7049 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7050 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
7051
7052 /* WaDisableSDEUnitClockGating:bdw */
7053 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7054 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7055
7056 /* WaProgramL3SqcReg1Default:bdw */
7057 gen8_set_l3sqc_credits(dev_priv, 30, 2);
7058
7059 /*
7060 * WaGttCachingOffByDefault:bdw
7061 * GTT cache may not work with big pages, so if those
7062 * are ever enabled GTT cache may need to be disabled.
7063 */
7064 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
7065
7066 /* WaKVMNotificationOnConfigChange:bdw */
7067 I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
7068 | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
7069
7070 lpt_init_clock_gating(dev);
7071 }
7072
7073 static void haswell_init_clock_gating(struct drm_device *dev)
7074 {
7075 struct drm_i915_private *dev_priv = dev->dev_private;
7076
7077 ilk_init_lp_watermarks(dev);
7078
7079 /* L3 caching of data atomics doesn't work -- disable it. */
7080 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
7081 I915_WRITE(HSW_ROW_CHICKEN3,
7082 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
7083
7084 /* This is required by WaCatErrorRejectionIssue:hsw */
7085 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7086 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7087 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7088
7089 /* WaVSRefCountFullforceMissDisable:hsw */
7090 I915_WRITE(GEN7_FF_THREAD_MODE,
7091 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
7092
7093 /* WaDisable_RenderCache_OperationalFlush:hsw */
7094 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7095
7096 /* enable HiZ Raw Stall Optimization */
7097 I915_WRITE(CACHE_MODE_0_GEN7,
7098 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7099
7100 /* WaDisable4x2SubspanOptimization:hsw */
7101 I915_WRITE(CACHE_MODE_1,
7102 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7103
7104 /*
7105 * BSpec recommends 8x4 when MSAA is used,
7106 * however in practice 16x4 seems fastest.
7107 *
7108 * Note that PS/WM thread counts depend on the WIZ hashing
7109 * disable bit, which we don't touch here, but it's good
7110 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7111 */
7112 I915_WRITE(GEN7_GT_MODE,
7113 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7114
7115 /* WaSampleCChickenBitEnable:hsw */
7116 I915_WRITE(HALF_SLICE_CHICKEN3,
7117 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
7118
7119 /* WaSwitchSolVfFArbitrationPriority:hsw */
7120 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
7121
7122 /* WaRsPkgCStateDisplayPMReq:hsw */
7123 I915_WRITE(CHICKEN_PAR1_1,
7124 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
7125
7126 lpt_init_clock_gating(dev);
7127 }
7128
7129 static void ivybridge_init_clock_gating(struct drm_device *dev)
7130 {
7131 struct drm_i915_private *dev_priv = dev->dev_private;
7132 uint32_t snpcr;
7133
7134 ilk_init_lp_watermarks(dev);
7135
7136 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
7137
7138 /* WaDisableEarlyCull:ivb */
7139 I915_WRITE(_3D_CHICKEN3,
7140 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7141
7142 /* WaDisableBackToBackFlipFix:ivb */
7143 I915_WRITE(IVB_CHICKEN3,
7144 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7145 CHICKEN3_DGMG_DONE_FIX_DISABLE);
7146
7147 /* WaDisablePSDDualDispatchEnable:ivb */
7148 if (IS_IVB_GT1(dev))
7149 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
7150 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
7151
7152 /* WaDisable_RenderCache_OperationalFlush:ivb */
7153 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7154
7155 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
7156 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
7157 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
7158
7159 /* WaApplyL3ControlAndL3ChickenMode:ivb */
7160 I915_WRITE(GEN7_L3CNTLREG1,
7161 GEN7_WA_FOR_GEN7_L3_CONTROL);
7162 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
7163 GEN7_WA_L3_CHICKEN_MODE);
7164 if (IS_IVB_GT1(dev))
7165 I915_WRITE(GEN7_ROW_CHICKEN2,
7166 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7167 else {
7168 /* must write both registers */
7169 I915_WRITE(GEN7_ROW_CHICKEN2,
7170 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7171 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
7172 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7173 }
7174
7175 /* WaForceL3Serialization:ivb */
7176 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7177 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7178
7179 /*
7180 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
7181 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
7182 */
7183 I915_WRITE(GEN6_UCGCTL2,
7184 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
7185
7186 /* This is required by WaCatErrorRejectionIssue:ivb */
7187 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7188 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7189 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7190
7191 g4x_disable_trickle_feed(dev);
7192
7193 gen7_setup_fixed_func_scheduler(dev_priv);
7194
7195 if (0) { /* causes HiZ corruption on ivb:gt1 */
7196 /* enable HiZ Raw Stall Optimization */
7197 I915_WRITE(CACHE_MODE_0_GEN7,
7198 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7199 }
7200
7201 /* WaDisable4x2SubspanOptimization:ivb */
7202 I915_WRITE(CACHE_MODE_1,
7203 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7204
7205 /*
7206 * BSpec recommends 8x4 when MSAA is used,
7207 * however in practice 16x4 seems fastest.
7208 *
7209 * Note that PS/WM thread counts depend on the WIZ hashing
7210 * disable bit, which we don't touch here, but it's good
7211 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7212 */
7213 I915_WRITE(GEN7_GT_MODE,
7214 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7215
7216 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
7217 snpcr &= ~GEN6_MBC_SNPCR_MASK;
7218 snpcr |= GEN6_MBC_SNPCR_MED;
7219 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
7220
7221 if (!HAS_PCH_NOP(dev))
7222 cpt_init_clock_gating(dev);
7223
7224 gen6_check_mch_setup(dev);
7225 }
7226
7227 static void valleyview_init_clock_gating(struct drm_device *dev)
7228 {
7229 struct drm_i915_private *dev_priv = dev->dev_private;
7230
7231 /* WaDisableEarlyCull:vlv */
7232 I915_WRITE(_3D_CHICKEN3,
7233 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7234
7235 /* WaDisableBackToBackFlipFix:vlv */
7236 I915_WRITE(IVB_CHICKEN3,
7237 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7238 CHICKEN3_DGMG_DONE_FIX_DISABLE);
7239
7240 /* WaPsdDispatchEnable:vlv */
7241 /* WaDisablePSDDualDispatchEnable:vlv */
7242 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
7243 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
7244 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
7245
7246 /* WaDisable_RenderCache_OperationalFlush:vlv */
7247 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7248
7249 /* WaForceL3Serialization:vlv */
7250 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7251 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7252
7253 /* WaDisableDopClockGating:vlv */
7254 I915_WRITE(GEN7_ROW_CHICKEN2,
7255 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7256
7257 /* This is required by WaCatErrorRejectionIssue:vlv */
7258 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7259 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7260 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7261
7262 gen7_setup_fixed_func_scheduler(dev_priv);
7263
7264 /*
7265 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
7266 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
7267 */
7268 I915_WRITE(GEN6_UCGCTL2,
7269 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
7270
7271 /* WaDisableL3Bank2xClockGate:vlv
7272 * Disabling L3 clock gating- MMIO 940c[25] = 1
7273 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
7274 I915_WRITE(GEN7_UCGCTL4,
7275 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
7276
7277 /*
7278 * BSpec says this must be set, even though
7279 * WaDisable4x2SubspanOptimization isn't listed for VLV.
7280 */
7281 I915_WRITE(CACHE_MODE_1,
7282 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7283
7284 /*
7285 * BSpec recommends 8x4 when MSAA is used,
7286 * however in practice 16x4 seems fastest.
7287 *
7288 * Note that PS/WM thread counts depend on the WIZ hashing
7289 * disable bit, which we don't touch here, but it's good
7290 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7291 */
7292 I915_WRITE(GEN7_GT_MODE,
7293 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7294
7295 /*
7296 * WaIncreaseL3CreditsForVLVB0:vlv
7297 * This is the hardware default actually.
7298 */
7299 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
7300
7301 /*
7302 * WaDisableVLVClockGating_VBIIssue:vlv
7303 * Disable clock gating on th GCFG unit to prevent a delay
7304 * in the reporting of vblank events.
7305 */
7306 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
7307 }
7308
7309 static void cherryview_init_clock_gating(struct drm_device *dev)
7310 {
7311 struct drm_i915_private *dev_priv = dev->dev_private;
7312
7313 /* WaVSRefCountFullforceMissDisable:chv */
7314 /* WaDSRefCountFullforceMissDisable:chv */
7315 I915_WRITE(GEN7_FF_THREAD_MODE,
7316 I915_READ(GEN7_FF_THREAD_MODE) &
7317 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
7318
7319 /* WaDisableSemaphoreAndSyncFlipWait:chv */
7320 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7321 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
7322
7323 /* WaDisableCSUnitClockGating:chv */
7324 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7325 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
7326
7327 /* WaDisableSDEUnitClockGating:chv */
7328 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7329 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7330
7331 /*
7332 * WaProgramL3SqcReg1Default:chv
7333 * See gfxspecs/Related Documents/Performance Guide/
7334 * LSQC Setting Recommendations.
7335 */
7336 gen8_set_l3sqc_credits(dev_priv, 38, 2);
7337
7338 /*
7339 * GTT cache may not work with big pages, so if those
7340 * are ever enabled GTT cache may need to be disabled.
7341 */
7342 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
7343 }
7344
7345 static void g4x_init_clock_gating(struct drm_device *dev)
7346 {
7347 struct drm_i915_private *dev_priv = dev->dev_private;
7348 uint32_t dspclk_gate;
7349
7350 I915_WRITE(RENCLK_GATE_D1, 0);
7351 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7352 GS_UNIT_CLOCK_GATE_DISABLE |
7353 CL_UNIT_CLOCK_GATE_DISABLE);
7354 I915_WRITE(RAMCLK_GATE_D, 0);
7355 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7356 OVRUNIT_CLOCK_GATE_DISABLE |
7357 OVCUNIT_CLOCK_GATE_DISABLE;
7358 if (IS_GM45(dev))
7359 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7360 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
7361
7362 /* WaDisableRenderCachePipelinedFlush */
7363 I915_WRITE(CACHE_MODE_0,
7364 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
7365
7366 /* WaDisable_RenderCache_OperationalFlush:g4x */
7367 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7368
7369 g4x_disable_trickle_feed(dev);
7370 }
7371
7372 static void crestline_init_clock_gating(struct drm_device *dev)
7373 {
7374 struct drm_i915_private *dev_priv = dev->dev_private;
7375
7376 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7377 I915_WRITE(RENCLK_GATE_D2, 0);
7378 I915_WRITE(DSPCLK_GATE_D, 0);
7379 I915_WRITE(RAMCLK_GATE_D, 0);
7380 I915_WRITE16(DEUC, 0);
7381 I915_WRITE(MI_ARB_STATE,
7382 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7383
7384 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7385 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7386 }
7387
7388 static void broadwater_init_clock_gating(struct drm_device *dev)
7389 {
7390 struct drm_i915_private *dev_priv = dev->dev_private;
7391
7392 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7393 I965_RCC_CLOCK_GATE_DISABLE |
7394 I965_RCPB_CLOCK_GATE_DISABLE |
7395 I965_ISC_CLOCK_GATE_DISABLE |
7396 I965_FBC_CLOCK_GATE_DISABLE);
7397 I915_WRITE(RENCLK_GATE_D2, 0);
7398 I915_WRITE(MI_ARB_STATE,
7399 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7400
7401 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7402 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7403 }
7404
7405 static void gen3_init_clock_gating(struct drm_device *dev)
7406 {
7407 struct drm_i915_private *dev_priv = dev->dev_private;
7408 u32 dstate = I915_READ(D_STATE);
7409
7410 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7411 DSTATE_DOT_CLOCK_GATING;
7412 I915_WRITE(D_STATE, dstate);
7413
7414 if (IS_PINEVIEW(dev))
7415 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
7416
7417 /* IIR "flip pending" means done if this bit is set */
7418 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
7419
7420 /* interrupts should cause a wake up from C3 */
7421 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
7422
7423 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7424 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
7425
7426 I915_WRITE(MI_ARB_STATE,
7427 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7428 }
7429
7430 static void i85x_init_clock_gating(struct drm_device *dev)
7431 {
7432 struct drm_i915_private *dev_priv = dev->dev_private;
7433
7434 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7435
7436 /* interrupts should cause a wake up from C3 */
7437 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7438 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
7439
7440 I915_WRITE(MEM_MODE,
7441 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
7442 }
7443
7444 static void i830_init_clock_gating(struct drm_device *dev)
7445 {
7446 struct drm_i915_private *dev_priv = dev->dev_private;
7447
7448 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
7449
7450 I915_WRITE(MEM_MODE,
7451 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7452 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
7453 }
7454
7455 void intel_init_clock_gating(struct drm_device *dev)
7456 {
7457 struct drm_i915_private *dev_priv = dev->dev_private;
7458
7459 dev_priv->display.init_clock_gating(dev);
7460 }
7461
7462 void intel_suspend_hw(struct drm_device *dev)
7463 {
7464 if (HAS_PCH_LPT(dev))
7465 lpt_suspend_hw(dev);
7466 }
7467
7468 static void nop_init_clock_gating(struct drm_device *dev)
7469 {
7470 DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n");
7471 }
7472
7473 /**
7474 * intel_init_clock_gating_hooks - setup the clock gating hooks
7475 * @dev_priv: device private
7476 *
7477 * Setup the hooks that configure which clocks of a given platform can be
7478 * gated and also apply various GT and display specific workarounds for these
7479 * platforms. Note that some GT specific workarounds are applied separately
7480 * when GPU contexts or batchbuffers start their execution.
7481 */
7482 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
7483 {
7484 if (IS_SKYLAKE(dev_priv))
7485 dev_priv->display.init_clock_gating = skylake_init_clock_gating;
7486 else if (IS_KABYLAKE(dev_priv))
7487 dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
7488 else if (IS_BROXTON(dev_priv))
7489 dev_priv->display.init_clock_gating = bxt_init_clock_gating;
7490 else if (IS_BROADWELL(dev_priv))
7491 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7492 else if (IS_CHERRYVIEW(dev_priv))
7493 dev_priv->display.init_clock_gating = cherryview_init_clock_gating;
7494 else if (IS_HASWELL(dev_priv))
7495 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7496 else if (IS_IVYBRIDGE(dev_priv))
7497 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7498 else if (IS_VALLEYVIEW(dev_priv))
7499 dev_priv->display.init_clock_gating = valleyview_init_clock_gating;
7500 else if (IS_GEN6(dev_priv))
7501 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7502 else if (IS_GEN5(dev_priv))
7503 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7504 else if (IS_G4X(dev_priv))
7505 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7506 else if (IS_CRESTLINE(dev_priv))
7507 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7508 else if (IS_BROADWATER(dev_priv))
7509 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7510 else if (IS_GEN3(dev_priv))
7511 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7512 else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
7513 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7514 else if (IS_GEN2(dev_priv))
7515 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7516 else {
7517 MISSING_CASE(INTEL_DEVID(dev_priv));
7518 dev_priv->display.init_clock_gating = nop_init_clock_gating;
7519 }
7520 }
7521
7522 /* Set up chip specific power management-related functions */
7523 void intel_init_pm(struct drm_device *dev)
7524 {
7525 struct drm_i915_private *dev_priv = dev->dev_private;
7526
7527 intel_fbc_init(dev_priv);
7528
7529 /* For cxsr */
7530 if (IS_PINEVIEW(dev))
7531 i915_pineview_get_mem_freq(dev);
7532 else if (IS_GEN5(dev))
7533 i915_ironlake_get_mem_freq(dev);
7534
7535 /* For FIFO watermark updates */
7536 if (INTEL_INFO(dev)->gen >= 9) {
7537 skl_setup_wm_latency(dev);
7538 dev_priv->display.update_wm = skl_update_wm;
7539 dev_priv->display.compute_global_watermarks = skl_compute_wm;
7540 } else if (HAS_PCH_SPLIT(dev)) {
7541 ilk_setup_wm_latency(dev);
7542
7543 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
7544 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7545 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7546 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
7547 dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
7548 dev_priv->display.compute_intermediate_wm =
7549 ilk_compute_intermediate_wm;
7550 dev_priv->display.initial_watermarks =
7551 ilk_initial_watermarks;
7552 dev_priv->display.optimize_watermarks =
7553 ilk_optimize_watermarks;
7554 } else {
7555 DRM_DEBUG_KMS("Failed to read display plane latency. "
7556 "Disable CxSR\n");
7557 }
7558 } else if (IS_CHERRYVIEW(dev)) {
7559 vlv_setup_wm_latency(dev);
7560 dev_priv->display.update_wm = vlv_update_wm;
7561 } else if (IS_VALLEYVIEW(dev)) {
7562 vlv_setup_wm_latency(dev);
7563 dev_priv->display.update_wm = vlv_update_wm;
7564 } else if (IS_PINEVIEW(dev)) {
7565 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7566 dev_priv->is_ddr3,
7567 dev_priv->fsb_freq,
7568 dev_priv->mem_freq)) {
7569 DRM_INFO("failed to find known CxSR latency "
7570 "(found ddr%s fsb freq %d, mem freq %d), "
7571 "disabling CxSR\n",
7572 (dev_priv->is_ddr3 == 1) ? "3" : "2",
7573 dev_priv->fsb_freq, dev_priv->mem_freq);
7574 /* Disable CxSR and never update its watermark again */
7575 intel_set_memory_cxsr(dev_priv, false);
7576 dev_priv->display.update_wm = NULL;
7577 } else
7578 dev_priv->display.update_wm = pineview_update_wm;
7579 } else if (IS_G4X(dev)) {
7580 dev_priv->display.update_wm = g4x_update_wm;
7581 } else if (IS_GEN4(dev)) {
7582 dev_priv->display.update_wm = i965_update_wm;
7583 } else if (IS_GEN3(dev)) {
7584 dev_priv->display.update_wm = i9xx_update_wm;
7585 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7586 } else if (IS_GEN2(dev)) {
7587 if (INTEL_INFO(dev)->num_pipes == 1) {
7588 dev_priv->display.update_wm = i845_update_wm;
7589 dev_priv->display.get_fifo_size = i845_get_fifo_size;
7590 } else {
7591 dev_priv->display.update_wm = i9xx_update_wm;
7592 dev_priv->display.get_fifo_size = i830_get_fifo_size;
7593 }
7594 } else {
7595 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
7596 }
7597 }
7598
7599 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
7600 {
7601 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7602
7603 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7604 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7605 return -EAGAIN;
7606 }
7607
7608 I915_WRITE(GEN6_PCODE_DATA, *val);
7609 I915_WRITE(GEN6_PCODE_DATA1, 0);
7610 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7611
7612 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7613 500)) {
7614 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7615 return -ETIMEDOUT;
7616 }
7617
7618 *val = I915_READ(GEN6_PCODE_DATA);
7619 I915_WRITE(GEN6_PCODE_DATA, 0);
7620
7621 return 0;
7622 }
7623
7624 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val)
7625 {
7626 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7627
7628 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7629 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7630 return -EAGAIN;
7631 }
7632
7633 I915_WRITE(GEN6_PCODE_DATA, val);
7634 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7635
7636 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7637 500)) {
7638 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7639 return -ETIMEDOUT;
7640 }
7641
7642 I915_WRITE(GEN6_PCODE_DATA, 0);
7643
7644 return 0;
7645 }
7646
7647 static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7648 {
7649 /*
7650 * N = val - 0xb7
7651 * Slow = Fast = GPLL ref * N
7652 */
7653 return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * (val - 0xb7), 1000);
7654 }
7655
7656 static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
7657 {
7658 return DIV_ROUND_CLOSEST(1000 * val, dev_priv->rps.gpll_ref_freq) + 0xb7;
7659 }
7660
7661 static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
7662 {
7663 /*
7664 * N = val / 2
7665 * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2
7666 */
7667 return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * val, 2 * 2 * 1000);
7668 }
7669
7670 static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
7671 {
7672 /* CHV needs even values */
7673 return DIV_ROUND_CLOSEST(2 * 1000 * val, dev_priv->rps.gpll_ref_freq) * 2;
7674 }
7675
7676 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
7677 {
7678 if (IS_GEN9(dev_priv))
7679 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
7680 GEN9_FREQ_SCALER);
7681 else if (IS_CHERRYVIEW(dev_priv))
7682 return chv_gpu_freq(dev_priv, val);
7683 else if (IS_VALLEYVIEW(dev_priv))
7684 return byt_gpu_freq(dev_priv, val);
7685 else
7686 return val * GT_FREQUENCY_MULTIPLIER;
7687 }
7688
7689 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7690 {
7691 if (IS_GEN9(dev_priv))
7692 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
7693 GT_FREQUENCY_MULTIPLIER);
7694 else if (IS_CHERRYVIEW(dev_priv))
7695 return chv_freq_opcode(dev_priv, val);
7696 else if (IS_VALLEYVIEW(dev_priv))
7697 return byt_freq_opcode(dev_priv, val);
7698 else
7699 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
7700 }
7701
7702 struct request_boost {
7703 struct work_struct work;
7704 struct drm_i915_gem_request *req;
7705 };
7706
7707 static void __intel_rps_boost_work(struct work_struct *work)
7708 {
7709 struct request_boost *boost = container_of(work, struct request_boost, work);
7710 struct drm_i915_gem_request *req = boost->req;
7711
7712 if (!i915_gem_request_completed(req, true))
7713 gen6_rps_boost(req->i915, NULL, req->emitted_jiffies);
7714
7715 i915_gem_request_unreference(req);
7716 kfree(boost);
7717 }
7718
7719 void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req)
7720 {
7721 struct request_boost *boost;
7722
7723 if (req == NULL || INTEL_GEN(req->i915) < 6)
7724 return;
7725
7726 if (i915_gem_request_completed(req, true))
7727 return;
7728
7729 boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
7730 if (boost == NULL)
7731 return;
7732
7733 i915_gem_request_reference(req);
7734 boost->req = req;
7735
7736 INIT_WORK(&boost->work, __intel_rps_boost_work);
7737 queue_work(req->i915->wq, &boost->work);
7738 }
7739
7740 void intel_pm_setup(struct drm_device *dev)
7741 {
7742 struct drm_i915_private *dev_priv = dev->dev_private;
7743
7744 mutex_init(&dev_priv->rps.hw_lock);
7745 spin_lock_init(&dev_priv->rps.client_lock);
7746
7747 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
7748 intel_gen6_powersave_work);
7749 INIT_LIST_HEAD(&dev_priv->rps.clients);
7750 INIT_LIST_HEAD(&dev_priv->rps.semaphores.link);
7751 INIT_LIST_HEAD(&dev_priv->rps.mmioflips.link);
7752
7753 dev_priv->pm.suspended = false;
7754 atomic_set(&dev_priv->pm.wakeref_count, 0);
7755 atomic_set(&dev_priv->pm.atomic_seq, 0);
7756 }
Linux kernel - Deliverables
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