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drm/i915/bdw: Clock gating init
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_pm.c
1 /*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28 #include <linux/cpufreq.h>
29 #include "i915_drv.h"
30 #include "intel_drv.h"
31 #include "../../../platform/x86/intel_ips.h"
32 #include <linux/module.h>
33 #include <drm/i915_powerwell.h>
34
35 /**
36 * RC6 is a special power stage which allows the GPU to enter an very
37 * low-voltage mode when idle, using down to 0V while at this stage. This
38 * stage is entered automatically when the GPU is idle when RC6 support is
39 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
40 *
41 * There are different RC6 modes available in Intel GPU, which differentiate
42 * among each other with the latency required to enter and leave RC6 and
43 * voltage consumed by the GPU in different states.
44 *
45 * The combination of the following flags define which states GPU is allowed
46 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
47 * RC6pp is deepest RC6. Their support by hardware varies according to the
48 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
49 * which brings the most power savings; deeper states save more power, but
50 * require higher latency to switch to and wake up.
51 */
52 #define INTEL_RC6_ENABLE (1<<0)
53 #define INTEL_RC6p_ENABLE (1<<1)
54 #define INTEL_RC6pp_ENABLE (1<<2)
55
56 /* FBC, or Frame Buffer Compression, is a technique employed to compress the
57 * framebuffer contents in-memory, aiming at reducing the required bandwidth
58 * during in-memory transfers and, therefore, reduce the power packet.
59 *
60 * The benefits of FBC are mostly visible with solid backgrounds and
61 * variation-less patterns.
62 *
63 * FBC-related functionality can be enabled by the means of the
64 * i915.i915_enable_fbc parameter
65 */
66
67 static void i8xx_disable_fbc(struct drm_device *dev)
68 {
69 struct drm_i915_private *dev_priv = dev->dev_private;
70 u32 fbc_ctl;
71
72 /* Disable compression */
73 fbc_ctl = I915_READ(FBC_CONTROL);
74 if ((fbc_ctl & FBC_CTL_EN) == 0)
75 return;
76
77 fbc_ctl &= ~FBC_CTL_EN;
78 I915_WRITE(FBC_CONTROL, fbc_ctl);
79
80 /* Wait for compressing bit to clear */
81 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
82 DRM_DEBUG_KMS("FBC idle timed out\n");
83 return;
84 }
85
86 DRM_DEBUG_KMS("disabled FBC\n");
87 }
88
89 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
90 {
91 struct drm_device *dev = crtc->dev;
92 struct drm_i915_private *dev_priv = dev->dev_private;
93 struct drm_framebuffer *fb = crtc->fb;
94 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
95 struct drm_i915_gem_object *obj = intel_fb->obj;
96 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
97 int cfb_pitch;
98 int plane, i;
99 u32 fbc_ctl, fbc_ctl2;
100
101 cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
102 if (fb->pitches[0] < cfb_pitch)
103 cfb_pitch = fb->pitches[0];
104
105 /* FBC_CTL wants 64B units */
106 cfb_pitch = (cfb_pitch / 64) - 1;
107 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
108
109 /* Clear old tags */
110 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
111 I915_WRITE(FBC_TAG + (i * 4), 0);
112
113 /* Set it up... */
114 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
115 fbc_ctl2 |= plane;
116 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
117 I915_WRITE(FBC_FENCE_OFF, crtc->y);
118
119 /* enable it... */
120 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
121 if (IS_I945GM(dev))
122 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
123 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
124 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
125 fbc_ctl |= obj->fence_reg;
126 I915_WRITE(FBC_CONTROL, fbc_ctl);
127
128 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c, ",
129 cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
130 }
131
132 static bool i8xx_fbc_enabled(struct drm_device *dev)
133 {
134 struct drm_i915_private *dev_priv = dev->dev_private;
135
136 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
137 }
138
139 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
140 {
141 struct drm_device *dev = crtc->dev;
142 struct drm_i915_private *dev_priv = dev->dev_private;
143 struct drm_framebuffer *fb = crtc->fb;
144 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
145 struct drm_i915_gem_object *obj = intel_fb->obj;
146 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
147 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
148 unsigned long stall_watermark = 200;
149 u32 dpfc_ctl;
150
151 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
152 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
153 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
154
155 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
156 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
157 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
158 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
159
160 /* enable it... */
161 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
162
163 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
164 }
165
166 static void g4x_disable_fbc(struct drm_device *dev)
167 {
168 struct drm_i915_private *dev_priv = dev->dev_private;
169 u32 dpfc_ctl;
170
171 /* Disable compression */
172 dpfc_ctl = I915_READ(DPFC_CONTROL);
173 if (dpfc_ctl & DPFC_CTL_EN) {
174 dpfc_ctl &= ~DPFC_CTL_EN;
175 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
176
177 DRM_DEBUG_KMS("disabled FBC\n");
178 }
179 }
180
181 static bool g4x_fbc_enabled(struct drm_device *dev)
182 {
183 struct drm_i915_private *dev_priv = dev->dev_private;
184
185 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
186 }
187
188 static void sandybridge_blit_fbc_update(struct drm_device *dev)
189 {
190 struct drm_i915_private *dev_priv = dev->dev_private;
191 u32 blt_ecoskpd;
192
193 /* Make sure blitter notifies FBC of writes */
194 gen6_gt_force_wake_get(dev_priv);
195 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
196 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
197 GEN6_BLITTER_LOCK_SHIFT;
198 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
199 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
200 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
201 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
202 GEN6_BLITTER_LOCK_SHIFT);
203 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
204 POSTING_READ(GEN6_BLITTER_ECOSKPD);
205 gen6_gt_force_wake_put(dev_priv);
206 }
207
208 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
209 {
210 struct drm_device *dev = crtc->dev;
211 struct drm_i915_private *dev_priv = dev->dev_private;
212 struct drm_framebuffer *fb = crtc->fb;
213 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
214 struct drm_i915_gem_object *obj = intel_fb->obj;
215 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
216 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
217 unsigned long stall_watermark = 200;
218 u32 dpfc_ctl;
219
220 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
221 dpfc_ctl &= DPFC_RESERVED;
222 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
223 /* Set persistent mode for front-buffer rendering, ala X. */
224 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
225 dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
226 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
227
228 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
229 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
230 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
231 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
232 I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
233 /* enable it... */
234 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
235
236 if (IS_GEN6(dev)) {
237 I915_WRITE(SNB_DPFC_CTL_SA,
238 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
239 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
240 sandybridge_blit_fbc_update(dev);
241 }
242
243 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
244 }
245
246 static void ironlake_disable_fbc(struct drm_device *dev)
247 {
248 struct drm_i915_private *dev_priv = dev->dev_private;
249 u32 dpfc_ctl;
250
251 /* Disable compression */
252 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
253 if (dpfc_ctl & DPFC_CTL_EN) {
254 dpfc_ctl &= ~DPFC_CTL_EN;
255 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
256
257 DRM_DEBUG_KMS("disabled FBC\n");
258 }
259 }
260
261 static bool ironlake_fbc_enabled(struct drm_device *dev)
262 {
263 struct drm_i915_private *dev_priv = dev->dev_private;
264
265 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
266 }
267
268 static void gen7_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
269 {
270 struct drm_device *dev = crtc->dev;
271 struct drm_i915_private *dev_priv = dev->dev_private;
272 struct drm_framebuffer *fb = crtc->fb;
273 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
274 struct drm_i915_gem_object *obj = intel_fb->obj;
275 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
276
277 I915_WRITE(IVB_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj));
278
279 I915_WRITE(ILK_DPFC_CONTROL, DPFC_CTL_EN | DPFC_CTL_LIMIT_1X |
280 IVB_DPFC_CTL_FENCE_EN |
281 intel_crtc->plane << IVB_DPFC_CTL_PLANE_SHIFT);
282
283 if (IS_IVYBRIDGE(dev)) {
284 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
285 I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS);
286 } else {
287 /* WaFbcAsynchFlipDisableFbcQueue:hsw */
288 I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe),
289 HSW_BYPASS_FBC_QUEUE);
290 }
291
292 I915_WRITE(SNB_DPFC_CTL_SA,
293 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
294 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
295
296 sandybridge_blit_fbc_update(dev);
297
298 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
299 }
300
301 bool intel_fbc_enabled(struct drm_device *dev)
302 {
303 struct drm_i915_private *dev_priv = dev->dev_private;
304
305 if (!dev_priv->display.fbc_enabled)
306 return false;
307
308 return dev_priv->display.fbc_enabled(dev);
309 }
310
311 static void intel_fbc_work_fn(struct work_struct *__work)
312 {
313 struct intel_fbc_work *work =
314 container_of(to_delayed_work(__work),
315 struct intel_fbc_work, work);
316 struct drm_device *dev = work->crtc->dev;
317 struct drm_i915_private *dev_priv = dev->dev_private;
318
319 mutex_lock(&dev->struct_mutex);
320 if (work == dev_priv->fbc.fbc_work) {
321 /* Double check that we haven't switched fb without cancelling
322 * the prior work.
323 */
324 if (work->crtc->fb == work->fb) {
325 dev_priv->display.enable_fbc(work->crtc,
326 work->interval);
327
328 dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;
329 dev_priv->fbc.fb_id = work->crtc->fb->base.id;
330 dev_priv->fbc.y = work->crtc->y;
331 }
332
333 dev_priv->fbc.fbc_work = NULL;
334 }
335 mutex_unlock(&dev->struct_mutex);
336
337 kfree(work);
338 }
339
340 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
341 {
342 if (dev_priv->fbc.fbc_work == NULL)
343 return;
344
345 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
346
347 /* Synchronisation is provided by struct_mutex and checking of
348 * dev_priv->fbc.fbc_work, so we can perform the cancellation
349 * entirely asynchronously.
350 */
351 if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
352 /* tasklet was killed before being run, clean up */
353 kfree(dev_priv->fbc.fbc_work);
354
355 /* Mark the work as no longer wanted so that if it does
356 * wake-up (because the work was already running and waiting
357 * for our mutex), it will discover that is no longer
358 * necessary to run.
359 */
360 dev_priv->fbc.fbc_work = NULL;
361 }
362
363 static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
364 {
365 struct intel_fbc_work *work;
366 struct drm_device *dev = crtc->dev;
367 struct drm_i915_private *dev_priv = dev->dev_private;
368
369 if (!dev_priv->display.enable_fbc)
370 return;
371
372 intel_cancel_fbc_work(dev_priv);
373
374 work = kzalloc(sizeof(*work), GFP_KERNEL);
375 if (work == NULL) {
376 DRM_ERROR("Failed to allocate FBC work structure\n");
377 dev_priv->display.enable_fbc(crtc, interval);
378 return;
379 }
380
381 work->crtc = crtc;
382 work->fb = crtc->fb;
383 work->interval = interval;
384 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
385
386 dev_priv->fbc.fbc_work = work;
387
388 /* Delay the actual enabling to let pageflipping cease and the
389 * display to settle before starting the compression. Note that
390 * this delay also serves a second purpose: it allows for a
391 * vblank to pass after disabling the FBC before we attempt
392 * to modify the control registers.
393 *
394 * A more complicated solution would involve tracking vblanks
395 * following the termination of the page-flipping sequence
396 * and indeed performing the enable as a co-routine and not
397 * waiting synchronously upon the vblank.
398 *
399 * WaFbcWaitForVBlankBeforeEnable:ilk,snb
400 */
401 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
402 }
403
404 void intel_disable_fbc(struct drm_device *dev)
405 {
406 struct drm_i915_private *dev_priv = dev->dev_private;
407
408 intel_cancel_fbc_work(dev_priv);
409
410 if (!dev_priv->display.disable_fbc)
411 return;
412
413 dev_priv->display.disable_fbc(dev);
414 dev_priv->fbc.plane = -1;
415 }
416
417 static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
418 enum no_fbc_reason reason)
419 {
420 if (dev_priv->fbc.no_fbc_reason == reason)
421 return false;
422
423 dev_priv->fbc.no_fbc_reason = reason;
424 return true;
425 }
426
427 /**
428 * intel_update_fbc - enable/disable FBC as needed
429 * @dev: the drm_device
430 *
431 * Set up the framebuffer compression hardware at mode set time. We
432 * enable it if possible:
433 * - plane A only (on pre-965)
434 * - no pixel mulitply/line duplication
435 * - no alpha buffer discard
436 * - no dual wide
437 * - framebuffer <= max_hdisplay in width, max_vdisplay in height
438 *
439 * We can't assume that any compression will take place (worst case),
440 * so the compressed buffer has to be the same size as the uncompressed
441 * one. It also must reside (along with the line length buffer) in
442 * stolen memory.
443 *
444 * We need to enable/disable FBC on a global basis.
445 */
446 void intel_update_fbc(struct drm_device *dev)
447 {
448 struct drm_i915_private *dev_priv = dev->dev_private;
449 struct drm_crtc *crtc = NULL, *tmp_crtc;
450 struct intel_crtc *intel_crtc;
451 struct drm_framebuffer *fb;
452 struct intel_framebuffer *intel_fb;
453 struct drm_i915_gem_object *obj;
454 const struct drm_display_mode *adjusted_mode;
455 unsigned int max_width, max_height;
456
457 if (!I915_HAS_FBC(dev)) {
458 set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED);
459 return;
460 }
461
462 if (!i915_powersave) {
463 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
464 DRM_DEBUG_KMS("fbc disabled per module param\n");
465 return;
466 }
467
468 /*
469 * If FBC is already on, we just have to verify that we can
470 * keep it that way...
471 * Need to disable if:
472 * - more than one pipe is active
473 * - changing FBC params (stride, fence, mode)
474 * - new fb is too large to fit in compressed buffer
475 * - going to an unsupported config (interlace, pixel multiply, etc.)
476 */
477 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
478 if (intel_crtc_active(tmp_crtc) &&
479 to_intel_crtc(tmp_crtc)->primary_enabled) {
480 if (crtc) {
481 if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
482 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
483 goto out_disable;
484 }
485 crtc = tmp_crtc;
486 }
487 }
488
489 if (!crtc || crtc->fb == NULL) {
490 if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
491 DRM_DEBUG_KMS("no output, disabling\n");
492 goto out_disable;
493 }
494
495 intel_crtc = to_intel_crtc(crtc);
496 fb = crtc->fb;
497 intel_fb = to_intel_framebuffer(fb);
498 obj = intel_fb->obj;
499 adjusted_mode = &intel_crtc->config.adjusted_mode;
500
501 if (i915_enable_fbc < 0 &&
502 INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) {
503 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
504 DRM_DEBUG_KMS("disabled per chip default\n");
505 goto out_disable;
506 }
507 if (!i915_enable_fbc) {
508 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
509 DRM_DEBUG_KMS("fbc disabled per module param\n");
510 goto out_disable;
511 }
512 if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ||
513 (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
514 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
515 DRM_DEBUG_KMS("mode incompatible with compression, "
516 "disabling\n");
517 goto out_disable;
518 }
519
520 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
521 max_width = 4096;
522 max_height = 2048;
523 } else {
524 max_width = 2048;
525 max_height = 1536;
526 }
527 if (intel_crtc->config.pipe_src_w > max_width ||
528 intel_crtc->config.pipe_src_h > max_height) {
529 if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
530 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
531 goto out_disable;
532 }
533 if ((IS_I915GM(dev) || IS_I945GM(dev) || IS_HASWELL(dev)) &&
534 intel_crtc->plane != 0) {
535 if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
536 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
537 goto out_disable;
538 }
539
540 /* The use of a CPU fence is mandatory in order to detect writes
541 * by the CPU to the scanout and trigger updates to the FBC.
542 */
543 if (obj->tiling_mode != I915_TILING_X ||
544 obj->fence_reg == I915_FENCE_REG_NONE) {
545 if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED))
546 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
547 goto out_disable;
548 }
549
550 /* If the kernel debugger is active, always disable compression */
551 if (in_dbg_master())
552 goto out_disable;
553
554 if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) {
555 if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL))
556 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
557 goto out_disable;
558 }
559
560 /* If the scanout has not changed, don't modify the FBC settings.
561 * Note that we make the fundamental assumption that the fb->obj
562 * cannot be unpinned (and have its GTT offset and fence revoked)
563 * without first being decoupled from the scanout and FBC disabled.
564 */
565 if (dev_priv->fbc.plane == intel_crtc->plane &&
566 dev_priv->fbc.fb_id == fb->base.id &&
567 dev_priv->fbc.y == crtc->y)
568 return;
569
570 if (intel_fbc_enabled(dev)) {
571 /* We update FBC along two paths, after changing fb/crtc
572 * configuration (modeswitching) and after page-flipping
573 * finishes. For the latter, we know that not only did
574 * we disable the FBC at the start of the page-flip
575 * sequence, but also more than one vblank has passed.
576 *
577 * For the former case of modeswitching, it is possible
578 * to switch between two FBC valid configurations
579 * instantaneously so we do need to disable the FBC
580 * before we can modify its control registers. We also
581 * have to wait for the next vblank for that to take
582 * effect. However, since we delay enabling FBC we can
583 * assume that a vblank has passed since disabling and
584 * that we can safely alter the registers in the deferred
585 * callback.
586 *
587 * In the scenario that we go from a valid to invalid
588 * and then back to valid FBC configuration we have
589 * no strict enforcement that a vblank occurred since
590 * disabling the FBC. However, along all current pipe
591 * disabling paths we do need to wait for a vblank at
592 * some point. And we wait before enabling FBC anyway.
593 */
594 DRM_DEBUG_KMS("disabling active FBC for update\n");
595 intel_disable_fbc(dev);
596 }
597
598 intel_enable_fbc(crtc, 500);
599 dev_priv->fbc.no_fbc_reason = FBC_OK;
600 return;
601
602 out_disable:
603 /* Multiple disables should be harmless */
604 if (intel_fbc_enabled(dev)) {
605 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
606 intel_disable_fbc(dev);
607 }
608 i915_gem_stolen_cleanup_compression(dev);
609 }
610
611 static void i915_pineview_get_mem_freq(struct drm_device *dev)
612 {
613 drm_i915_private_t *dev_priv = dev->dev_private;
614 u32 tmp;
615
616 tmp = I915_READ(CLKCFG);
617
618 switch (tmp & CLKCFG_FSB_MASK) {
619 case CLKCFG_FSB_533:
620 dev_priv->fsb_freq = 533; /* 133*4 */
621 break;
622 case CLKCFG_FSB_800:
623 dev_priv->fsb_freq = 800; /* 200*4 */
624 break;
625 case CLKCFG_FSB_667:
626 dev_priv->fsb_freq = 667; /* 167*4 */
627 break;
628 case CLKCFG_FSB_400:
629 dev_priv->fsb_freq = 400; /* 100*4 */
630 break;
631 }
632
633 switch (tmp & CLKCFG_MEM_MASK) {
634 case CLKCFG_MEM_533:
635 dev_priv->mem_freq = 533;
636 break;
637 case CLKCFG_MEM_667:
638 dev_priv->mem_freq = 667;
639 break;
640 case CLKCFG_MEM_800:
641 dev_priv->mem_freq = 800;
642 break;
643 }
644
645 /* detect pineview DDR3 setting */
646 tmp = I915_READ(CSHRDDR3CTL);
647 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
648 }
649
650 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
651 {
652 drm_i915_private_t *dev_priv = dev->dev_private;
653 u16 ddrpll, csipll;
654
655 ddrpll = I915_READ16(DDRMPLL1);
656 csipll = I915_READ16(CSIPLL0);
657
658 switch (ddrpll & 0xff) {
659 case 0xc:
660 dev_priv->mem_freq = 800;
661 break;
662 case 0x10:
663 dev_priv->mem_freq = 1066;
664 break;
665 case 0x14:
666 dev_priv->mem_freq = 1333;
667 break;
668 case 0x18:
669 dev_priv->mem_freq = 1600;
670 break;
671 default:
672 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
673 ddrpll & 0xff);
674 dev_priv->mem_freq = 0;
675 break;
676 }
677
678 dev_priv->ips.r_t = dev_priv->mem_freq;
679
680 switch (csipll & 0x3ff) {
681 case 0x00c:
682 dev_priv->fsb_freq = 3200;
683 break;
684 case 0x00e:
685 dev_priv->fsb_freq = 3733;
686 break;
687 case 0x010:
688 dev_priv->fsb_freq = 4266;
689 break;
690 case 0x012:
691 dev_priv->fsb_freq = 4800;
692 break;
693 case 0x014:
694 dev_priv->fsb_freq = 5333;
695 break;
696 case 0x016:
697 dev_priv->fsb_freq = 5866;
698 break;
699 case 0x018:
700 dev_priv->fsb_freq = 6400;
701 break;
702 default:
703 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
704 csipll & 0x3ff);
705 dev_priv->fsb_freq = 0;
706 break;
707 }
708
709 if (dev_priv->fsb_freq == 3200) {
710 dev_priv->ips.c_m = 0;
711 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
712 dev_priv->ips.c_m = 1;
713 } else {
714 dev_priv->ips.c_m = 2;
715 }
716 }
717
718 static const struct cxsr_latency cxsr_latency_table[] = {
719 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
720 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
721 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
722 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
723 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
724
725 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
726 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
727 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
728 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
729 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
730
731 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
732 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
733 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
734 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
735 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
736
737 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
738 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
739 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
740 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
741 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
742
743 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
744 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
745 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
746 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
747 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
748
749 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
750 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
751 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
752 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
753 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
754 };
755
756 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
757 int is_ddr3,
758 int fsb,
759 int mem)
760 {
761 const struct cxsr_latency *latency;
762 int i;
763
764 if (fsb == 0 || mem == 0)
765 return NULL;
766
767 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
768 latency = &cxsr_latency_table[i];
769 if (is_desktop == latency->is_desktop &&
770 is_ddr3 == latency->is_ddr3 &&
771 fsb == latency->fsb_freq && mem == latency->mem_freq)
772 return latency;
773 }
774
775 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
776
777 return NULL;
778 }
779
780 static void pineview_disable_cxsr(struct drm_device *dev)
781 {
782 struct drm_i915_private *dev_priv = dev->dev_private;
783
784 /* deactivate cxsr */
785 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
786 }
787
788 /*
789 * Latency for FIFO fetches is dependent on several factors:
790 * - memory configuration (speed, channels)
791 * - chipset
792 * - current MCH state
793 * It can be fairly high in some situations, so here we assume a fairly
794 * pessimal value. It's a tradeoff between extra memory fetches (if we
795 * set this value too high, the FIFO will fetch frequently to stay full)
796 * and power consumption (set it too low to save power and we might see
797 * FIFO underruns and display "flicker").
798 *
799 * A value of 5us seems to be a good balance; safe for very low end
800 * platforms but not overly aggressive on lower latency configs.
801 */
802 static const int latency_ns = 5000;
803
804 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
805 {
806 struct drm_i915_private *dev_priv = dev->dev_private;
807 uint32_t dsparb = I915_READ(DSPARB);
808 int size;
809
810 size = dsparb & 0x7f;
811 if (plane)
812 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
813
814 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
815 plane ? "B" : "A", size);
816
817 return size;
818 }
819
820 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
821 {
822 struct drm_i915_private *dev_priv = dev->dev_private;
823 uint32_t dsparb = I915_READ(DSPARB);
824 int size;
825
826 size = dsparb & 0x1ff;
827 if (plane)
828 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
829 size >>= 1; /* Convert to cachelines */
830
831 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
832 plane ? "B" : "A", size);
833
834 return size;
835 }
836
837 static int i845_get_fifo_size(struct drm_device *dev, int plane)
838 {
839 struct drm_i915_private *dev_priv = dev->dev_private;
840 uint32_t dsparb = I915_READ(DSPARB);
841 int size;
842
843 size = dsparb & 0x7f;
844 size >>= 2; /* Convert to cachelines */
845
846 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
847 plane ? "B" : "A",
848 size);
849
850 return size;
851 }
852
853 static int i830_get_fifo_size(struct drm_device *dev, int plane)
854 {
855 struct drm_i915_private *dev_priv = dev->dev_private;
856 uint32_t dsparb = I915_READ(DSPARB);
857 int size;
858
859 size = dsparb & 0x7f;
860 size >>= 1; /* Convert to cachelines */
861
862 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
863 plane ? "B" : "A", size);
864
865 return size;
866 }
867
868 /* Pineview has different values for various configs */
869 static const struct intel_watermark_params pineview_display_wm = {
870 PINEVIEW_DISPLAY_FIFO,
871 PINEVIEW_MAX_WM,
872 PINEVIEW_DFT_WM,
873 PINEVIEW_GUARD_WM,
874 PINEVIEW_FIFO_LINE_SIZE
875 };
876 static const struct intel_watermark_params pineview_display_hplloff_wm = {
877 PINEVIEW_DISPLAY_FIFO,
878 PINEVIEW_MAX_WM,
879 PINEVIEW_DFT_HPLLOFF_WM,
880 PINEVIEW_GUARD_WM,
881 PINEVIEW_FIFO_LINE_SIZE
882 };
883 static const struct intel_watermark_params pineview_cursor_wm = {
884 PINEVIEW_CURSOR_FIFO,
885 PINEVIEW_CURSOR_MAX_WM,
886 PINEVIEW_CURSOR_DFT_WM,
887 PINEVIEW_CURSOR_GUARD_WM,
888 PINEVIEW_FIFO_LINE_SIZE,
889 };
890 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
891 PINEVIEW_CURSOR_FIFO,
892 PINEVIEW_CURSOR_MAX_WM,
893 PINEVIEW_CURSOR_DFT_WM,
894 PINEVIEW_CURSOR_GUARD_WM,
895 PINEVIEW_FIFO_LINE_SIZE
896 };
897 static const struct intel_watermark_params g4x_wm_info = {
898 G4X_FIFO_SIZE,
899 G4X_MAX_WM,
900 G4X_MAX_WM,
901 2,
902 G4X_FIFO_LINE_SIZE,
903 };
904 static const struct intel_watermark_params g4x_cursor_wm_info = {
905 I965_CURSOR_FIFO,
906 I965_CURSOR_MAX_WM,
907 I965_CURSOR_DFT_WM,
908 2,
909 G4X_FIFO_LINE_SIZE,
910 };
911 static const struct intel_watermark_params valleyview_wm_info = {
912 VALLEYVIEW_FIFO_SIZE,
913 VALLEYVIEW_MAX_WM,
914 VALLEYVIEW_MAX_WM,
915 2,
916 G4X_FIFO_LINE_SIZE,
917 };
918 static const struct intel_watermark_params valleyview_cursor_wm_info = {
919 I965_CURSOR_FIFO,
920 VALLEYVIEW_CURSOR_MAX_WM,
921 I965_CURSOR_DFT_WM,
922 2,
923 G4X_FIFO_LINE_SIZE,
924 };
925 static const struct intel_watermark_params i965_cursor_wm_info = {
926 I965_CURSOR_FIFO,
927 I965_CURSOR_MAX_WM,
928 I965_CURSOR_DFT_WM,
929 2,
930 I915_FIFO_LINE_SIZE,
931 };
932 static const struct intel_watermark_params i945_wm_info = {
933 I945_FIFO_SIZE,
934 I915_MAX_WM,
935 1,
936 2,
937 I915_FIFO_LINE_SIZE
938 };
939 static const struct intel_watermark_params i915_wm_info = {
940 I915_FIFO_SIZE,
941 I915_MAX_WM,
942 1,
943 2,
944 I915_FIFO_LINE_SIZE
945 };
946 static const struct intel_watermark_params i855_wm_info = {
947 I855GM_FIFO_SIZE,
948 I915_MAX_WM,
949 1,
950 2,
951 I830_FIFO_LINE_SIZE
952 };
953 static const struct intel_watermark_params i830_wm_info = {
954 I830_FIFO_SIZE,
955 I915_MAX_WM,
956 1,
957 2,
958 I830_FIFO_LINE_SIZE
959 };
960
961 static const struct intel_watermark_params ironlake_display_wm_info = {
962 ILK_DISPLAY_FIFO,
963 ILK_DISPLAY_MAXWM,
964 ILK_DISPLAY_DFTWM,
965 2,
966 ILK_FIFO_LINE_SIZE
967 };
968 static const struct intel_watermark_params ironlake_cursor_wm_info = {
969 ILK_CURSOR_FIFO,
970 ILK_CURSOR_MAXWM,
971 ILK_CURSOR_DFTWM,
972 2,
973 ILK_FIFO_LINE_SIZE
974 };
975 static const struct intel_watermark_params ironlake_display_srwm_info = {
976 ILK_DISPLAY_SR_FIFO,
977 ILK_DISPLAY_MAX_SRWM,
978 ILK_DISPLAY_DFT_SRWM,
979 2,
980 ILK_FIFO_LINE_SIZE
981 };
982 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
983 ILK_CURSOR_SR_FIFO,
984 ILK_CURSOR_MAX_SRWM,
985 ILK_CURSOR_DFT_SRWM,
986 2,
987 ILK_FIFO_LINE_SIZE
988 };
989
990 static const struct intel_watermark_params sandybridge_display_wm_info = {
991 SNB_DISPLAY_FIFO,
992 SNB_DISPLAY_MAXWM,
993 SNB_DISPLAY_DFTWM,
994 2,
995 SNB_FIFO_LINE_SIZE
996 };
997 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
998 SNB_CURSOR_FIFO,
999 SNB_CURSOR_MAXWM,
1000 SNB_CURSOR_DFTWM,
1001 2,
1002 SNB_FIFO_LINE_SIZE
1003 };
1004 static const struct intel_watermark_params sandybridge_display_srwm_info = {
1005 SNB_DISPLAY_SR_FIFO,
1006 SNB_DISPLAY_MAX_SRWM,
1007 SNB_DISPLAY_DFT_SRWM,
1008 2,
1009 SNB_FIFO_LINE_SIZE
1010 };
1011 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
1012 SNB_CURSOR_SR_FIFO,
1013 SNB_CURSOR_MAX_SRWM,
1014 SNB_CURSOR_DFT_SRWM,
1015 2,
1016 SNB_FIFO_LINE_SIZE
1017 };
1018
1019
1020 /**
1021 * intel_calculate_wm - calculate watermark level
1022 * @clock_in_khz: pixel clock
1023 * @wm: chip FIFO params
1024 * @pixel_size: display pixel size
1025 * @latency_ns: memory latency for the platform
1026 *
1027 * Calculate the watermark level (the level at which the display plane will
1028 * start fetching from memory again). Each chip has a different display
1029 * FIFO size and allocation, so the caller needs to figure that out and pass
1030 * in the correct intel_watermark_params structure.
1031 *
1032 * As the pixel clock runs, the FIFO will be drained at a rate that depends
1033 * on the pixel size. When it reaches the watermark level, it'll start
1034 * fetching FIFO line sized based chunks from memory until the FIFO fills
1035 * past the watermark point. If the FIFO drains completely, a FIFO underrun
1036 * will occur, and a display engine hang could result.
1037 */
1038 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
1039 const struct intel_watermark_params *wm,
1040 int fifo_size,
1041 int pixel_size,
1042 unsigned long latency_ns)
1043 {
1044 long entries_required, wm_size;
1045
1046 /*
1047 * Note: we need to make sure we don't overflow for various clock &
1048 * latency values.
1049 * clocks go from a few thousand to several hundred thousand.
1050 * latency is usually a few thousand
1051 */
1052 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
1053 1000;
1054 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
1055
1056 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
1057
1058 wm_size = fifo_size - (entries_required + wm->guard_size);
1059
1060 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
1061
1062 /* Don't promote wm_size to unsigned... */
1063 if (wm_size > (long)wm->max_wm)
1064 wm_size = wm->max_wm;
1065 if (wm_size <= 0)
1066 wm_size = wm->default_wm;
1067 return wm_size;
1068 }
1069
1070 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1071 {
1072 struct drm_crtc *crtc, *enabled = NULL;
1073
1074 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1075 if (intel_crtc_active(crtc)) {
1076 if (enabled)
1077 return NULL;
1078 enabled = crtc;
1079 }
1080 }
1081
1082 return enabled;
1083 }
1084
1085 static void pineview_update_wm(struct drm_crtc *unused_crtc)
1086 {
1087 struct drm_device *dev = unused_crtc->dev;
1088 struct drm_i915_private *dev_priv = dev->dev_private;
1089 struct drm_crtc *crtc;
1090 const struct cxsr_latency *latency;
1091 u32 reg;
1092 unsigned long wm;
1093
1094 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1095 dev_priv->fsb_freq, dev_priv->mem_freq);
1096 if (!latency) {
1097 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1098 pineview_disable_cxsr(dev);
1099 return;
1100 }
1101
1102 crtc = single_enabled_crtc(dev);
1103 if (crtc) {
1104 const struct drm_display_mode *adjusted_mode;
1105 int pixel_size = crtc->fb->bits_per_pixel / 8;
1106 int clock;
1107
1108 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1109 clock = adjusted_mode->crtc_clock;
1110
1111 /* Display SR */
1112 wm = intel_calculate_wm(clock, &pineview_display_wm,
1113 pineview_display_wm.fifo_size,
1114 pixel_size, latency->display_sr);
1115 reg = I915_READ(DSPFW1);
1116 reg &= ~DSPFW_SR_MASK;
1117 reg |= wm << DSPFW_SR_SHIFT;
1118 I915_WRITE(DSPFW1, reg);
1119 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1120
1121 /* cursor SR */
1122 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1123 pineview_display_wm.fifo_size,
1124 pixel_size, latency->cursor_sr);
1125 reg = I915_READ(DSPFW3);
1126 reg &= ~DSPFW_CURSOR_SR_MASK;
1127 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1128 I915_WRITE(DSPFW3, reg);
1129
1130 /* Display HPLL off SR */
1131 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1132 pineview_display_hplloff_wm.fifo_size,
1133 pixel_size, latency->display_hpll_disable);
1134 reg = I915_READ(DSPFW3);
1135 reg &= ~DSPFW_HPLL_SR_MASK;
1136 reg |= wm & DSPFW_HPLL_SR_MASK;
1137 I915_WRITE(DSPFW3, reg);
1138
1139 /* cursor HPLL off SR */
1140 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1141 pineview_display_hplloff_wm.fifo_size,
1142 pixel_size, latency->cursor_hpll_disable);
1143 reg = I915_READ(DSPFW3);
1144 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1145 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1146 I915_WRITE(DSPFW3, reg);
1147 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1148
1149 /* activate cxsr */
1150 I915_WRITE(DSPFW3,
1151 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1152 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1153 } else {
1154 pineview_disable_cxsr(dev);
1155 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1156 }
1157 }
1158
1159 static bool g4x_compute_wm0(struct drm_device *dev,
1160 int plane,
1161 const struct intel_watermark_params *display,
1162 int display_latency_ns,
1163 const struct intel_watermark_params *cursor,
1164 int cursor_latency_ns,
1165 int *plane_wm,
1166 int *cursor_wm)
1167 {
1168 struct drm_crtc *crtc;
1169 const struct drm_display_mode *adjusted_mode;
1170 int htotal, hdisplay, clock, pixel_size;
1171 int line_time_us, line_count;
1172 int entries, tlb_miss;
1173
1174 crtc = intel_get_crtc_for_plane(dev, plane);
1175 if (!intel_crtc_active(crtc)) {
1176 *cursor_wm = cursor->guard_size;
1177 *plane_wm = display->guard_size;
1178 return false;
1179 }
1180
1181 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1182 clock = adjusted_mode->crtc_clock;
1183 htotal = adjusted_mode->htotal;
1184 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1185 pixel_size = crtc->fb->bits_per_pixel / 8;
1186
1187 /* Use the small buffer method to calculate plane watermark */
1188 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1189 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1190 if (tlb_miss > 0)
1191 entries += tlb_miss;
1192 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1193 *plane_wm = entries + display->guard_size;
1194 if (*plane_wm > (int)display->max_wm)
1195 *plane_wm = display->max_wm;
1196
1197 /* Use the large buffer method to calculate cursor watermark */
1198 line_time_us = ((htotal * 1000) / clock);
1199 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1200 entries = line_count * 64 * pixel_size;
1201 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1202 if (tlb_miss > 0)
1203 entries += tlb_miss;
1204 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1205 *cursor_wm = entries + cursor->guard_size;
1206 if (*cursor_wm > (int)cursor->max_wm)
1207 *cursor_wm = (int)cursor->max_wm;
1208
1209 return true;
1210 }
1211
1212 /*
1213 * Check the wm result.
1214 *
1215 * If any calculated watermark values is larger than the maximum value that
1216 * can be programmed into the associated watermark register, that watermark
1217 * must be disabled.
1218 */
1219 static bool g4x_check_srwm(struct drm_device *dev,
1220 int display_wm, int cursor_wm,
1221 const struct intel_watermark_params *display,
1222 const struct intel_watermark_params *cursor)
1223 {
1224 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1225 display_wm, cursor_wm);
1226
1227 if (display_wm > display->max_wm) {
1228 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1229 display_wm, display->max_wm);
1230 return false;
1231 }
1232
1233 if (cursor_wm > cursor->max_wm) {
1234 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1235 cursor_wm, cursor->max_wm);
1236 return false;
1237 }
1238
1239 if (!(display_wm || cursor_wm)) {
1240 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1241 return false;
1242 }
1243
1244 return true;
1245 }
1246
1247 static bool g4x_compute_srwm(struct drm_device *dev,
1248 int plane,
1249 int latency_ns,
1250 const struct intel_watermark_params *display,
1251 const struct intel_watermark_params *cursor,
1252 int *display_wm, int *cursor_wm)
1253 {
1254 struct drm_crtc *crtc;
1255 const struct drm_display_mode *adjusted_mode;
1256 int hdisplay, htotal, pixel_size, clock;
1257 unsigned long line_time_us;
1258 int line_count, line_size;
1259 int small, large;
1260 int entries;
1261
1262 if (!latency_ns) {
1263 *display_wm = *cursor_wm = 0;
1264 return false;
1265 }
1266
1267 crtc = intel_get_crtc_for_plane(dev, plane);
1268 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1269 clock = adjusted_mode->crtc_clock;
1270 htotal = adjusted_mode->htotal;
1271 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1272 pixel_size = crtc->fb->bits_per_pixel / 8;
1273
1274 line_time_us = (htotal * 1000) / clock;
1275 line_count = (latency_ns / line_time_us + 1000) / 1000;
1276 line_size = hdisplay * pixel_size;
1277
1278 /* Use the minimum of the small and large buffer method for primary */
1279 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1280 large = line_count * line_size;
1281
1282 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1283 *display_wm = entries + display->guard_size;
1284
1285 /* calculate the self-refresh watermark for display cursor */
1286 entries = line_count * pixel_size * 64;
1287 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1288 *cursor_wm = entries + cursor->guard_size;
1289
1290 return g4x_check_srwm(dev,
1291 *display_wm, *cursor_wm,
1292 display, cursor);
1293 }
1294
1295 static bool vlv_compute_drain_latency(struct drm_device *dev,
1296 int plane,
1297 int *plane_prec_mult,
1298 int *plane_dl,
1299 int *cursor_prec_mult,
1300 int *cursor_dl)
1301 {
1302 struct drm_crtc *crtc;
1303 int clock, pixel_size;
1304 int entries;
1305
1306 crtc = intel_get_crtc_for_plane(dev, plane);
1307 if (!intel_crtc_active(crtc))
1308 return false;
1309
1310 clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
1311 pixel_size = crtc->fb->bits_per_pixel / 8; /* BPP */
1312
1313 entries = (clock / 1000) * pixel_size;
1314 *plane_prec_mult = (entries > 256) ?
1315 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1316 *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1317 pixel_size);
1318
1319 entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */
1320 *cursor_prec_mult = (entries > 256) ?
1321 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1322 *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1323
1324 return true;
1325 }
1326
1327 /*
1328 * Update drain latency registers of memory arbiter
1329 *
1330 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1331 * to be programmed. Each plane has a drain latency multiplier and a drain
1332 * latency value.
1333 */
1334
1335 static void vlv_update_drain_latency(struct drm_device *dev)
1336 {
1337 struct drm_i915_private *dev_priv = dev->dev_private;
1338 int planea_prec, planea_dl, planeb_prec, planeb_dl;
1339 int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1340 int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1341 either 16 or 32 */
1342
1343 /* For plane A, Cursor A */
1344 if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1345 &cursor_prec_mult, &cursora_dl)) {
1346 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1347 DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1348 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1349 DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1350
1351 I915_WRITE(VLV_DDL1, cursora_prec |
1352 (cursora_dl << DDL_CURSORA_SHIFT) |
1353 planea_prec | planea_dl);
1354 }
1355
1356 /* For plane B, Cursor B */
1357 if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1358 &cursor_prec_mult, &cursorb_dl)) {
1359 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1360 DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1361 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1362 DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1363
1364 I915_WRITE(VLV_DDL2, cursorb_prec |
1365 (cursorb_dl << DDL_CURSORB_SHIFT) |
1366 planeb_prec | planeb_dl);
1367 }
1368 }
1369
1370 #define single_plane_enabled(mask) is_power_of_2(mask)
1371
1372 static void valleyview_update_wm(struct drm_crtc *crtc)
1373 {
1374 struct drm_device *dev = crtc->dev;
1375 static const int sr_latency_ns = 12000;
1376 struct drm_i915_private *dev_priv = dev->dev_private;
1377 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1378 int plane_sr, cursor_sr;
1379 int ignore_plane_sr, ignore_cursor_sr;
1380 unsigned int enabled = 0;
1381
1382 vlv_update_drain_latency(dev);
1383
1384 if (g4x_compute_wm0(dev, PIPE_A,
1385 &valleyview_wm_info, latency_ns,
1386 &valleyview_cursor_wm_info, latency_ns,
1387 &planea_wm, &cursora_wm))
1388 enabled |= 1 << PIPE_A;
1389
1390 if (g4x_compute_wm0(dev, PIPE_B,
1391 &valleyview_wm_info, latency_ns,
1392 &valleyview_cursor_wm_info, latency_ns,
1393 &planeb_wm, &cursorb_wm))
1394 enabled |= 1 << PIPE_B;
1395
1396 if (single_plane_enabled(enabled) &&
1397 g4x_compute_srwm(dev, ffs(enabled) - 1,
1398 sr_latency_ns,
1399 &valleyview_wm_info,
1400 &valleyview_cursor_wm_info,
1401 &plane_sr, &ignore_cursor_sr) &&
1402 g4x_compute_srwm(dev, ffs(enabled) - 1,
1403 2*sr_latency_ns,
1404 &valleyview_wm_info,
1405 &valleyview_cursor_wm_info,
1406 &ignore_plane_sr, &cursor_sr)) {
1407 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
1408 } else {
1409 I915_WRITE(FW_BLC_SELF_VLV,
1410 I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
1411 plane_sr = cursor_sr = 0;
1412 }
1413
1414 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1415 planea_wm, cursora_wm,
1416 planeb_wm, cursorb_wm,
1417 plane_sr, cursor_sr);
1418
1419 I915_WRITE(DSPFW1,
1420 (plane_sr << DSPFW_SR_SHIFT) |
1421 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1422 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1423 planea_wm);
1424 I915_WRITE(DSPFW2,
1425 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1426 (cursora_wm << DSPFW_CURSORA_SHIFT));
1427 I915_WRITE(DSPFW3,
1428 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1429 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1430 }
1431
1432 static void g4x_update_wm(struct drm_crtc *crtc)
1433 {
1434 struct drm_device *dev = crtc->dev;
1435 static const int sr_latency_ns = 12000;
1436 struct drm_i915_private *dev_priv = dev->dev_private;
1437 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1438 int plane_sr, cursor_sr;
1439 unsigned int enabled = 0;
1440
1441 if (g4x_compute_wm0(dev, PIPE_A,
1442 &g4x_wm_info, latency_ns,
1443 &g4x_cursor_wm_info, latency_ns,
1444 &planea_wm, &cursora_wm))
1445 enabled |= 1 << PIPE_A;
1446
1447 if (g4x_compute_wm0(dev, PIPE_B,
1448 &g4x_wm_info, latency_ns,
1449 &g4x_cursor_wm_info, latency_ns,
1450 &planeb_wm, &cursorb_wm))
1451 enabled |= 1 << PIPE_B;
1452
1453 if (single_plane_enabled(enabled) &&
1454 g4x_compute_srwm(dev, ffs(enabled) - 1,
1455 sr_latency_ns,
1456 &g4x_wm_info,
1457 &g4x_cursor_wm_info,
1458 &plane_sr, &cursor_sr)) {
1459 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1460 } else {
1461 I915_WRITE(FW_BLC_SELF,
1462 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
1463 plane_sr = cursor_sr = 0;
1464 }
1465
1466 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1467 planea_wm, cursora_wm,
1468 planeb_wm, cursorb_wm,
1469 plane_sr, cursor_sr);
1470
1471 I915_WRITE(DSPFW1,
1472 (plane_sr << DSPFW_SR_SHIFT) |
1473 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1474 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1475 planea_wm);
1476 I915_WRITE(DSPFW2,
1477 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1478 (cursora_wm << DSPFW_CURSORA_SHIFT));
1479 /* HPLL off in SR has some issues on G4x... disable it */
1480 I915_WRITE(DSPFW3,
1481 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1482 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1483 }
1484
1485 static void i965_update_wm(struct drm_crtc *unused_crtc)
1486 {
1487 struct drm_device *dev = unused_crtc->dev;
1488 struct drm_i915_private *dev_priv = dev->dev_private;
1489 struct drm_crtc *crtc;
1490 int srwm = 1;
1491 int cursor_sr = 16;
1492
1493 /* Calc sr entries for one plane configs */
1494 crtc = single_enabled_crtc(dev);
1495 if (crtc) {
1496 /* self-refresh has much higher latency */
1497 static const int sr_latency_ns = 12000;
1498 const struct drm_display_mode *adjusted_mode =
1499 &to_intel_crtc(crtc)->config.adjusted_mode;
1500 int clock = adjusted_mode->crtc_clock;
1501 int htotal = adjusted_mode->htotal;
1502 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1503 int pixel_size = crtc->fb->bits_per_pixel / 8;
1504 unsigned long line_time_us;
1505 int entries;
1506
1507 line_time_us = ((htotal * 1000) / clock);
1508
1509 /* Use ns/us then divide to preserve precision */
1510 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1511 pixel_size * hdisplay;
1512 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1513 srwm = I965_FIFO_SIZE - entries;
1514 if (srwm < 0)
1515 srwm = 1;
1516 srwm &= 0x1ff;
1517 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1518 entries, srwm);
1519
1520 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1521 pixel_size * 64;
1522 entries = DIV_ROUND_UP(entries,
1523 i965_cursor_wm_info.cacheline_size);
1524 cursor_sr = i965_cursor_wm_info.fifo_size -
1525 (entries + i965_cursor_wm_info.guard_size);
1526
1527 if (cursor_sr > i965_cursor_wm_info.max_wm)
1528 cursor_sr = i965_cursor_wm_info.max_wm;
1529
1530 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1531 "cursor %d\n", srwm, cursor_sr);
1532
1533 if (IS_CRESTLINE(dev))
1534 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1535 } else {
1536 /* Turn off self refresh if both pipes are enabled */
1537 if (IS_CRESTLINE(dev))
1538 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1539 & ~FW_BLC_SELF_EN);
1540 }
1541
1542 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1543 srwm);
1544
1545 /* 965 has limitations... */
1546 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1547 (8 << 16) | (8 << 8) | (8 << 0));
1548 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1549 /* update cursor SR watermark */
1550 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1551 }
1552
1553 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1554 {
1555 struct drm_device *dev = unused_crtc->dev;
1556 struct drm_i915_private *dev_priv = dev->dev_private;
1557 const struct intel_watermark_params *wm_info;
1558 uint32_t fwater_lo;
1559 uint32_t fwater_hi;
1560 int cwm, srwm = 1;
1561 int fifo_size;
1562 int planea_wm, planeb_wm;
1563 struct drm_crtc *crtc, *enabled = NULL;
1564
1565 if (IS_I945GM(dev))
1566 wm_info = &i945_wm_info;
1567 else if (!IS_GEN2(dev))
1568 wm_info = &i915_wm_info;
1569 else
1570 wm_info = &i855_wm_info;
1571
1572 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1573 crtc = intel_get_crtc_for_plane(dev, 0);
1574 if (intel_crtc_active(crtc)) {
1575 const struct drm_display_mode *adjusted_mode;
1576 int cpp = crtc->fb->bits_per_pixel / 8;
1577 if (IS_GEN2(dev))
1578 cpp = 4;
1579
1580 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1581 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1582 wm_info, fifo_size, cpp,
1583 latency_ns);
1584 enabled = crtc;
1585 } else
1586 planea_wm = fifo_size - wm_info->guard_size;
1587
1588 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1589 crtc = intel_get_crtc_for_plane(dev, 1);
1590 if (intel_crtc_active(crtc)) {
1591 const struct drm_display_mode *adjusted_mode;
1592 int cpp = crtc->fb->bits_per_pixel / 8;
1593 if (IS_GEN2(dev))
1594 cpp = 4;
1595
1596 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1597 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1598 wm_info, fifo_size, cpp,
1599 latency_ns);
1600 if (enabled == NULL)
1601 enabled = crtc;
1602 else
1603 enabled = NULL;
1604 } else
1605 planeb_wm = fifo_size - wm_info->guard_size;
1606
1607 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1608
1609 /*
1610 * Overlay gets an aggressive default since video jitter is bad.
1611 */
1612 cwm = 2;
1613
1614 /* Play safe and disable self-refresh before adjusting watermarks. */
1615 if (IS_I945G(dev) || IS_I945GM(dev))
1616 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1617 else if (IS_I915GM(dev))
1618 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
1619
1620 /* Calc sr entries for one plane configs */
1621 if (HAS_FW_BLC(dev) && enabled) {
1622 /* self-refresh has much higher latency */
1623 static const int sr_latency_ns = 6000;
1624 const struct drm_display_mode *adjusted_mode =
1625 &to_intel_crtc(enabled)->config.adjusted_mode;
1626 int clock = adjusted_mode->crtc_clock;
1627 int htotal = adjusted_mode->htotal;
1628 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1629 int pixel_size = enabled->fb->bits_per_pixel / 8;
1630 unsigned long line_time_us;
1631 int entries;
1632
1633 line_time_us = (htotal * 1000) / clock;
1634
1635 /* Use ns/us then divide to preserve precision */
1636 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1637 pixel_size * hdisplay;
1638 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1639 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1640 srwm = wm_info->fifo_size - entries;
1641 if (srwm < 0)
1642 srwm = 1;
1643
1644 if (IS_I945G(dev) || IS_I945GM(dev))
1645 I915_WRITE(FW_BLC_SELF,
1646 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1647 else if (IS_I915GM(dev))
1648 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1649 }
1650
1651 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1652 planea_wm, planeb_wm, cwm, srwm);
1653
1654 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1655 fwater_hi = (cwm & 0x1f);
1656
1657 /* Set request length to 8 cachelines per fetch */
1658 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1659 fwater_hi = fwater_hi | (1 << 8);
1660
1661 I915_WRITE(FW_BLC, fwater_lo);
1662 I915_WRITE(FW_BLC2, fwater_hi);
1663
1664 if (HAS_FW_BLC(dev)) {
1665 if (enabled) {
1666 if (IS_I945G(dev) || IS_I945GM(dev))
1667 I915_WRITE(FW_BLC_SELF,
1668 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1669 else if (IS_I915GM(dev))
1670 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
1671 DRM_DEBUG_KMS("memory self refresh enabled\n");
1672 } else
1673 DRM_DEBUG_KMS("memory self refresh disabled\n");
1674 }
1675 }
1676
1677 static void i830_update_wm(struct drm_crtc *unused_crtc)
1678 {
1679 struct drm_device *dev = unused_crtc->dev;
1680 struct drm_i915_private *dev_priv = dev->dev_private;
1681 struct drm_crtc *crtc;
1682 const struct drm_display_mode *adjusted_mode;
1683 uint32_t fwater_lo;
1684 int planea_wm;
1685
1686 crtc = single_enabled_crtc(dev);
1687 if (crtc == NULL)
1688 return;
1689
1690 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1691 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1692 &i830_wm_info,
1693 dev_priv->display.get_fifo_size(dev, 0),
1694 4, latency_ns);
1695 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1696 fwater_lo |= (3<<8) | planea_wm;
1697
1698 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1699
1700 I915_WRITE(FW_BLC, fwater_lo);
1701 }
1702
1703 /*
1704 * Check the wm result.
1705 *
1706 * If any calculated watermark values is larger than the maximum value that
1707 * can be programmed into the associated watermark register, that watermark
1708 * must be disabled.
1709 */
1710 static bool ironlake_check_srwm(struct drm_device *dev, int level,
1711 int fbc_wm, int display_wm, int cursor_wm,
1712 const struct intel_watermark_params *display,
1713 const struct intel_watermark_params *cursor)
1714 {
1715 struct drm_i915_private *dev_priv = dev->dev_private;
1716
1717 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
1718 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
1719
1720 if (fbc_wm > SNB_FBC_MAX_SRWM) {
1721 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
1722 fbc_wm, SNB_FBC_MAX_SRWM, level);
1723
1724 /* fbc has it's own way to disable FBC WM */
1725 I915_WRITE(DISP_ARB_CTL,
1726 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
1727 return false;
1728 } else if (INTEL_INFO(dev)->gen >= 6) {
1729 /* enable FBC WM (except on ILK, where it must remain off) */
1730 I915_WRITE(DISP_ARB_CTL,
1731 I915_READ(DISP_ARB_CTL) & ~DISP_FBC_WM_DIS);
1732 }
1733
1734 if (display_wm > display->max_wm) {
1735 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
1736 display_wm, SNB_DISPLAY_MAX_SRWM, level);
1737 return false;
1738 }
1739
1740 if (cursor_wm > cursor->max_wm) {
1741 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
1742 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1743 return false;
1744 }
1745
1746 if (!(fbc_wm || display_wm || cursor_wm)) {
1747 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
1748 return false;
1749 }
1750
1751 return true;
1752 }
1753
1754 /*
1755 * Compute watermark values of WM[1-3],
1756 */
1757 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
1758 int latency_ns,
1759 const struct intel_watermark_params *display,
1760 const struct intel_watermark_params *cursor,
1761 int *fbc_wm, int *display_wm, int *cursor_wm)
1762 {
1763 struct drm_crtc *crtc;
1764 const struct drm_display_mode *adjusted_mode;
1765 unsigned long line_time_us;
1766 int hdisplay, htotal, pixel_size, clock;
1767 int line_count, line_size;
1768 int small, large;
1769 int entries;
1770
1771 if (!latency_ns) {
1772 *fbc_wm = *display_wm = *cursor_wm = 0;
1773 return false;
1774 }
1775
1776 crtc = intel_get_crtc_for_plane(dev, plane);
1777 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1778 clock = adjusted_mode->crtc_clock;
1779 htotal = adjusted_mode->htotal;
1780 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1781 pixel_size = crtc->fb->bits_per_pixel / 8;
1782
1783 line_time_us = (htotal * 1000) / clock;
1784 line_count = (latency_ns / line_time_us + 1000) / 1000;
1785 line_size = hdisplay * pixel_size;
1786
1787 /* Use the minimum of the small and large buffer method for primary */
1788 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1789 large = line_count * line_size;
1790
1791 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1792 *display_wm = entries + display->guard_size;
1793
1794 /*
1795 * Spec says:
1796 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
1797 */
1798 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
1799
1800 /* calculate the self-refresh watermark for display cursor */
1801 entries = line_count * pixel_size * 64;
1802 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1803 *cursor_wm = entries + cursor->guard_size;
1804
1805 return ironlake_check_srwm(dev, level,
1806 *fbc_wm, *display_wm, *cursor_wm,
1807 display, cursor);
1808 }
1809
1810 static void ironlake_update_wm(struct drm_crtc *crtc)
1811 {
1812 struct drm_device *dev = crtc->dev;
1813 struct drm_i915_private *dev_priv = dev->dev_private;
1814 int fbc_wm, plane_wm, cursor_wm;
1815 unsigned int enabled;
1816
1817 enabled = 0;
1818 if (g4x_compute_wm0(dev, PIPE_A,
1819 &ironlake_display_wm_info,
1820 dev_priv->wm.pri_latency[0] * 100,
1821 &ironlake_cursor_wm_info,
1822 dev_priv->wm.cur_latency[0] * 100,
1823 &plane_wm, &cursor_wm)) {
1824 I915_WRITE(WM0_PIPEA_ILK,
1825 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1826 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1827 " plane %d, " "cursor: %d\n",
1828 plane_wm, cursor_wm);
1829 enabled |= 1 << PIPE_A;
1830 }
1831
1832 if (g4x_compute_wm0(dev, PIPE_B,
1833 &ironlake_display_wm_info,
1834 dev_priv->wm.pri_latency[0] * 100,
1835 &ironlake_cursor_wm_info,
1836 dev_priv->wm.cur_latency[0] * 100,
1837 &plane_wm, &cursor_wm)) {
1838 I915_WRITE(WM0_PIPEB_ILK,
1839 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1840 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1841 " plane %d, cursor: %d\n",
1842 plane_wm, cursor_wm);
1843 enabled |= 1 << PIPE_B;
1844 }
1845
1846 /*
1847 * Calculate and update the self-refresh watermark only when one
1848 * display plane is used.
1849 */
1850 I915_WRITE(WM3_LP_ILK, 0);
1851 I915_WRITE(WM2_LP_ILK, 0);
1852 I915_WRITE(WM1_LP_ILK, 0);
1853
1854 if (!single_plane_enabled(enabled))
1855 return;
1856 enabled = ffs(enabled) - 1;
1857
1858 /* WM1 */
1859 if (!ironlake_compute_srwm(dev, 1, enabled,
1860 dev_priv->wm.pri_latency[1] * 500,
1861 &ironlake_display_srwm_info,
1862 &ironlake_cursor_srwm_info,
1863 &fbc_wm, &plane_wm, &cursor_wm))
1864 return;
1865
1866 I915_WRITE(WM1_LP_ILK,
1867 WM1_LP_SR_EN |
1868 (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
1869 (fbc_wm << WM1_LP_FBC_SHIFT) |
1870 (plane_wm << WM1_LP_SR_SHIFT) |
1871 cursor_wm);
1872
1873 /* WM2 */
1874 if (!ironlake_compute_srwm(dev, 2, enabled,
1875 dev_priv->wm.pri_latency[2] * 500,
1876 &ironlake_display_srwm_info,
1877 &ironlake_cursor_srwm_info,
1878 &fbc_wm, &plane_wm, &cursor_wm))
1879 return;
1880
1881 I915_WRITE(WM2_LP_ILK,
1882 WM2_LP_EN |
1883 (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
1884 (fbc_wm << WM1_LP_FBC_SHIFT) |
1885 (plane_wm << WM1_LP_SR_SHIFT) |
1886 cursor_wm);
1887
1888 /*
1889 * WM3 is unsupported on ILK, probably because we don't have latency
1890 * data for that power state
1891 */
1892 }
1893
1894 static void sandybridge_update_wm(struct drm_crtc *crtc)
1895 {
1896 struct drm_device *dev = crtc->dev;
1897 struct drm_i915_private *dev_priv = dev->dev_private;
1898 int latency = dev_priv->wm.pri_latency[0] * 100; /* In unit 0.1us */
1899 u32 val;
1900 int fbc_wm, plane_wm, cursor_wm;
1901 unsigned int enabled;
1902
1903 enabled = 0;
1904 if (g4x_compute_wm0(dev, PIPE_A,
1905 &sandybridge_display_wm_info, latency,
1906 &sandybridge_cursor_wm_info, latency,
1907 &plane_wm, &cursor_wm)) {
1908 val = I915_READ(WM0_PIPEA_ILK);
1909 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1910 I915_WRITE(WM0_PIPEA_ILK, val |
1911 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1912 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1913 " plane %d, " "cursor: %d\n",
1914 plane_wm, cursor_wm);
1915 enabled |= 1 << PIPE_A;
1916 }
1917
1918 if (g4x_compute_wm0(dev, PIPE_B,
1919 &sandybridge_display_wm_info, latency,
1920 &sandybridge_cursor_wm_info, latency,
1921 &plane_wm, &cursor_wm)) {
1922 val = I915_READ(WM0_PIPEB_ILK);
1923 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1924 I915_WRITE(WM0_PIPEB_ILK, val |
1925 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1926 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1927 " plane %d, cursor: %d\n",
1928 plane_wm, cursor_wm);
1929 enabled |= 1 << PIPE_B;
1930 }
1931
1932 /*
1933 * Calculate and update the self-refresh watermark only when one
1934 * display plane is used.
1935 *
1936 * SNB support 3 levels of watermark.
1937 *
1938 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1939 * and disabled in the descending order
1940 *
1941 */
1942 I915_WRITE(WM3_LP_ILK, 0);
1943 I915_WRITE(WM2_LP_ILK, 0);
1944 I915_WRITE(WM1_LP_ILK, 0);
1945
1946 if (!single_plane_enabled(enabled) ||
1947 dev_priv->sprite_scaling_enabled)
1948 return;
1949 enabled = ffs(enabled) - 1;
1950
1951 /* WM1 */
1952 if (!ironlake_compute_srwm(dev, 1, enabled,
1953 dev_priv->wm.pri_latency[1] * 500,
1954 &sandybridge_display_srwm_info,
1955 &sandybridge_cursor_srwm_info,
1956 &fbc_wm, &plane_wm, &cursor_wm))
1957 return;
1958
1959 I915_WRITE(WM1_LP_ILK,
1960 WM1_LP_SR_EN |
1961 (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
1962 (fbc_wm << WM1_LP_FBC_SHIFT) |
1963 (plane_wm << WM1_LP_SR_SHIFT) |
1964 cursor_wm);
1965
1966 /* WM2 */
1967 if (!ironlake_compute_srwm(dev, 2, enabled,
1968 dev_priv->wm.pri_latency[2] * 500,
1969 &sandybridge_display_srwm_info,
1970 &sandybridge_cursor_srwm_info,
1971 &fbc_wm, &plane_wm, &cursor_wm))
1972 return;
1973
1974 I915_WRITE(WM2_LP_ILK,
1975 WM2_LP_EN |
1976 (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
1977 (fbc_wm << WM1_LP_FBC_SHIFT) |
1978 (plane_wm << WM1_LP_SR_SHIFT) |
1979 cursor_wm);
1980
1981 /* WM3 */
1982 if (!ironlake_compute_srwm(dev, 3, enabled,
1983 dev_priv->wm.pri_latency[3] * 500,
1984 &sandybridge_display_srwm_info,
1985 &sandybridge_cursor_srwm_info,
1986 &fbc_wm, &plane_wm, &cursor_wm))
1987 return;
1988
1989 I915_WRITE(WM3_LP_ILK,
1990 WM3_LP_EN |
1991 (dev_priv->wm.pri_latency[3] << WM1_LP_LATENCY_SHIFT) |
1992 (fbc_wm << WM1_LP_FBC_SHIFT) |
1993 (plane_wm << WM1_LP_SR_SHIFT) |
1994 cursor_wm);
1995 }
1996
1997 static void ivybridge_update_wm(struct drm_crtc *crtc)
1998 {
1999 struct drm_device *dev = crtc->dev;
2000 struct drm_i915_private *dev_priv = dev->dev_private;
2001 int latency = dev_priv->wm.pri_latency[0] * 100; /* In unit 0.1us */
2002 u32 val;
2003 int fbc_wm, plane_wm, cursor_wm;
2004 int ignore_fbc_wm, ignore_plane_wm, ignore_cursor_wm;
2005 unsigned int enabled;
2006
2007 enabled = 0;
2008 if (g4x_compute_wm0(dev, PIPE_A,
2009 &sandybridge_display_wm_info, latency,
2010 &sandybridge_cursor_wm_info, latency,
2011 &plane_wm, &cursor_wm)) {
2012 val = I915_READ(WM0_PIPEA_ILK);
2013 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2014 I915_WRITE(WM0_PIPEA_ILK, val |
2015 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2016 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
2017 " plane %d, " "cursor: %d\n",
2018 plane_wm, cursor_wm);
2019 enabled |= 1 << PIPE_A;
2020 }
2021
2022 if (g4x_compute_wm0(dev, PIPE_B,
2023 &sandybridge_display_wm_info, latency,
2024 &sandybridge_cursor_wm_info, latency,
2025 &plane_wm, &cursor_wm)) {
2026 val = I915_READ(WM0_PIPEB_ILK);
2027 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2028 I915_WRITE(WM0_PIPEB_ILK, val |
2029 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2030 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
2031 " plane %d, cursor: %d\n",
2032 plane_wm, cursor_wm);
2033 enabled |= 1 << PIPE_B;
2034 }
2035
2036 if (g4x_compute_wm0(dev, PIPE_C,
2037 &sandybridge_display_wm_info, latency,
2038 &sandybridge_cursor_wm_info, latency,
2039 &plane_wm, &cursor_wm)) {
2040 val = I915_READ(WM0_PIPEC_IVB);
2041 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2042 I915_WRITE(WM0_PIPEC_IVB, val |
2043 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2044 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
2045 " plane %d, cursor: %d\n",
2046 plane_wm, cursor_wm);
2047 enabled |= 1 << PIPE_C;
2048 }
2049
2050 /*
2051 * Calculate and update the self-refresh watermark only when one
2052 * display plane is used.
2053 *
2054 * SNB support 3 levels of watermark.
2055 *
2056 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
2057 * and disabled in the descending order
2058 *
2059 */
2060 I915_WRITE(WM3_LP_ILK, 0);
2061 I915_WRITE(WM2_LP_ILK, 0);
2062 I915_WRITE(WM1_LP_ILK, 0);
2063
2064 if (!single_plane_enabled(enabled) ||
2065 dev_priv->sprite_scaling_enabled)
2066 return;
2067 enabled = ffs(enabled) - 1;
2068
2069 /* WM1 */
2070 if (!ironlake_compute_srwm(dev, 1, enabled,
2071 dev_priv->wm.pri_latency[1] * 500,
2072 &sandybridge_display_srwm_info,
2073 &sandybridge_cursor_srwm_info,
2074 &fbc_wm, &plane_wm, &cursor_wm))
2075 return;
2076
2077 I915_WRITE(WM1_LP_ILK,
2078 WM1_LP_SR_EN |
2079 (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
2080 (fbc_wm << WM1_LP_FBC_SHIFT) |
2081 (plane_wm << WM1_LP_SR_SHIFT) |
2082 cursor_wm);
2083
2084 /* WM2 */
2085 if (!ironlake_compute_srwm(dev, 2, enabled,
2086 dev_priv->wm.pri_latency[2] * 500,
2087 &sandybridge_display_srwm_info,
2088 &sandybridge_cursor_srwm_info,
2089 &fbc_wm, &plane_wm, &cursor_wm))
2090 return;
2091
2092 I915_WRITE(WM2_LP_ILK,
2093 WM2_LP_EN |
2094 (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
2095 (fbc_wm << WM1_LP_FBC_SHIFT) |
2096 (plane_wm << WM1_LP_SR_SHIFT) |
2097 cursor_wm);
2098
2099 /* WM3, note we have to correct the cursor latency */
2100 if (!ironlake_compute_srwm(dev, 3, enabled,
2101 dev_priv->wm.pri_latency[3] * 500,
2102 &sandybridge_display_srwm_info,
2103 &sandybridge_cursor_srwm_info,
2104 &fbc_wm, &plane_wm, &ignore_cursor_wm) ||
2105 !ironlake_compute_srwm(dev, 3, enabled,
2106 dev_priv->wm.cur_latency[3] * 500,
2107 &sandybridge_display_srwm_info,
2108 &sandybridge_cursor_srwm_info,
2109 &ignore_fbc_wm, &ignore_plane_wm, &cursor_wm))
2110 return;
2111
2112 I915_WRITE(WM3_LP_ILK,
2113 WM3_LP_EN |
2114 (dev_priv->wm.pri_latency[3] << WM1_LP_LATENCY_SHIFT) |
2115 (fbc_wm << WM1_LP_FBC_SHIFT) |
2116 (plane_wm << WM1_LP_SR_SHIFT) |
2117 cursor_wm);
2118 }
2119
2120 static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
2121 struct drm_crtc *crtc)
2122 {
2123 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2124 uint32_t pixel_rate;
2125
2126 pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock;
2127
2128 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
2129 * adjust the pixel_rate here. */
2130
2131 if (intel_crtc->config.pch_pfit.enabled) {
2132 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
2133 uint32_t pfit_size = intel_crtc->config.pch_pfit.size;
2134
2135 pipe_w = intel_crtc->config.pipe_src_w;
2136 pipe_h = intel_crtc->config.pipe_src_h;
2137 pfit_w = (pfit_size >> 16) & 0xFFFF;
2138 pfit_h = pfit_size & 0xFFFF;
2139 if (pipe_w < pfit_w)
2140 pipe_w = pfit_w;
2141 if (pipe_h < pfit_h)
2142 pipe_h = pfit_h;
2143
2144 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
2145 pfit_w * pfit_h);
2146 }
2147
2148 return pixel_rate;
2149 }
2150
2151 /* latency must be in 0.1us units. */
2152 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
2153 uint32_t latency)
2154 {
2155 uint64_t ret;
2156
2157 if (WARN(latency == 0, "Latency value missing\n"))
2158 return UINT_MAX;
2159
2160 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
2161 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
2162
2163 return ret;
2164 }
2165
2166 /* latency must be in 0.1us units. */
2167 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
2168 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
2169 uint32_t latency)
2170 {
2171 uint32_t ret;
2172
2173 if (WARN(latency == 0, "Latency value missing\n"))
2174 return UINT_MAX;
2175
2176 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
2177 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
2178 ret = DIV_ROUND_UP(ret, 64) + 2;
2179 return ret;
2180 }
2181
2182 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
2183 uint8_t bytes_per_pixel)
2184 {
2185 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
2186 }
2187
2188 struct hsw_pipe_wm_parameters {
2189 bool active;
2190 uint32_t pipe_htotal;
2191 uint32_t pixel_rate;
2192 struct intel_plane_wm_parameters pri;
2193 struct intel_plane_wm_parameters spr;
2194 struct intel_plane_wm_parameters cur;
2195 };
2196
2197 struct hsw_wm_maximums {
2198 uint16_t pri;
2199 uint16_t spr;
2200 uint16_t cur;
2201 uint16_t fbc;
2202 };
2203
2204 /* used in computing the new watermarks state */
2205 struct intel_wm_config {
2206 unsigned int num_pipes_active;
2207 bool sprites_enabled;
2208 bool sprites_scaled;
2209 };
2210
2211 /*
2212 * For both WM_PIPE and WM_LP.
2213 * mem_value must be in 0.1us units.
2214 */
2215 static uint32_t ilk_compute_pri_wm(const struct hsw_pipe_wm_parameters *params,
2216 uint32_t mem_value,
2217 bool is_lp)
2218 {
2219 uint32_t method1, method2;
2220
2221 if (!params->active || !params->pri.enabled)
2222 return 0;
2223
2224 method1 = ilk_wm_method1(params->pixel_rate,
2225 params->pri.bytes_per_pixel,
2226 mem_value);
2227
2228 if (!is_lp)
2229 return method1;
2230
2231 method2 = ilk_wm_method2(params->pixel_rate,
2232 params->pipe_htotal,
2233 params->pri.horiz_pixels,
2234 params->pri.bytes_per_pixel,
2235 mem_value);
2236
2237 return min(method1, method2);
2238 }
2239
2240 /*
2241 * For both WM_PIPE and WM_LP.
2242 * mem_value must be in 0.1us units.
2243 */
2244 static uint32_t ilk_compute_spr_wm(const struct hsw_pipe_wm_parameters *params,
2245 uint32_t mem_value)
2246 {
2247 uint32_t method1, method2;
2248
2249 if (!params->active || !params->spr.enabled)
2250 return 0;
2251
2252 method1 = ilk_wm_method1(params->pixel_rate,
2253 params->spr.bytes_per_pixel,
2254 mem_value);
2255 method2 = ilk_wm_method2(params->pixel_rate,
2256 params->pipe_htotal,
2257 params->spr.horiz_pixels,
2258 params->spr.bytes_per_pixel,
2259 mem_value);
2260 return min(method1, method2);
2261 }
2262
2263 /*
2264 * For both WM_PIPE and WM_LP.
2265 * mem_value must be in 0.1us units.
2266 */
2267 static uint32_t ilk_compute_cur_wm(const struct hsw_pipe_wm_parameters *params,
2268 uint32_t mem_value)
2269 {
2270 if (!params->active || !params->cur.enabled)
2271 return 0;
2272
2273 return ilk_wm_method2(params->pixel_rate,
2274 params->pipe_htotal,
2275 params->cur.horiz_pixels,
2276 params->cur.bytes_per_pixel,
2277 mem_value);
2278 }
2279
2280 /* Only for WM_LP. */
2281 static uint32_t ilk_compute_fbc_wm(const struct hsw_pipe_wm_parameters *params,
2282 uint32_t pri_val)
2283 {
2284 if (!params->active || !params->pri.enabled)
2285 return 0;
2286
2287 return ilk_wm_fbc(pri_val,
2288 params->pri.horiz_pixels,
2289 params->pri.bytes_per_pixel);
2290 }
2291
2292 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
2293 {
2294 if (INTEL_INFO(dev)->gen >= 7)
2295 return 768;
2296 else
2297 return 512;
2298 }
2299
2300 /* Calculate the maximum primary/sprite plane watermark */
2301 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
2302 int level,
2303 const struct intel_wm_config *config,
2304 enum intel_ddb_partitioning ddb_partitioning,
2305 bool is_sprite)
2306 {
2307 unsigned int fifo_size = ilk_display_fifo_size(dev);
2308 unsigned int max;
2309
2310 /* if sprites aren't enabled, sprites get nothing */
2311 if (is_sprite && !config->sprites_enabled)
2312 return 0;
2313
2314 /* HSW allows LP1+ watermarks even with multiple pipes */
2315 if (level == 0 || config->num_pipes_active > 1) {
2316 fifo_size /= INTEL_INFO(dev)->num_pipes;
2317
2318 /*
2319 * For some reason the non self refresh
2320 * FIFO size is only half of the self
2321 * refresh FIFO size on ILK/SNB.
2322 */
2323 if (INTEL_INFO(dev)->gen <= 6)
2324 fifo_size /= 2;
2325 }
2326
2327 if (config->sprites_enabled) {
2328 /* level 0 is always calculated with 1:1 split */
2329 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
2330 if (is_sprite)
2331 fifo_size *= 5;
2332 fifo_size /= 6;
2333 } else {
2334 fifo_size /= 2;
2335 }
2336 }
2337
2338 /* clamp to max that the registers can hold */
2339 if (INTEL_INFO(dev)->gen >= 7)
2340 /* IVB/HSW primary/sprite plane watermarks */
2341 max = level == 0 ? 127 : 1023;
2342 else if (!is_sprite)
2343 /* ILK/SNB primary plane watermarks */
2344 max = level == 0 ? 127 : 511;
2345 else
2346 /* ILK/SNB sprite plane watermarks */
2347 max = level == 0 ? 63 : 255;
2348
2349 return min(fifo_size, max);
2350 }
2351
2352 /* Calculate the maximum cursor plane watermark */
2353 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
2354 int level,
2355 const struct intel_wm_config *config)
2356 {
2357 /* HSW LP1+ watermarks w/ multiple pipes */
2358 if (level > 0 && config->num_pipes_active > 1)
2359 return 64;
2360
2361 /* otherwise just report max that registers can hold */
2362 if (INTEL_INFO(dev)->gen >= 7)
2363 return level == 0 ? 63 : 255;
2364 else
2365 return level == 0 ? 31 : 63;
2366 }
2367
2368 /* Calculate the maximum FBC watermark */
2369 static unsigned int ilk_fbc_wm_max(void)
2370 {
2371 /* max that registers can hold */
2372 return 15;
2373 }
2374
2375 static void ilk_compute_wm_maximums(struct drm_device *dev,
2376 int level,
2377 const struct intel_wm_config *config,
2378 enum intel_ddb_partitioning ddb_partitioning,
2379 struct hsw_wm_maximums *max)
2380 {
2381 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
2382 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
2383 max->cur = ilk_cursor_wm_max(dev, level, config);
2384 max->fbc = ilk_fbc_wm_max();
2385 }
2386
2387 static bool ilk_validate_wm_level(int level,
2388 const struct hsw_wm_maximums *max,
2389 struct intel_wm_level *result)
2390 {
2391 bool ret;
2392
2393 /* already determined to be invalid? */
2394 if (!result->enable)
2395 return false;
2396
2397 result->enable = result->pri_val <= max->pri &&
2398 result->spr_val <= max->spr &&
2399 result->cur_val <= max->cur;
2400
2401 ret = result->enable;
2402
2403 /*
2404 * HACK until we can pre-compute everything,
2405 * and thus fail gracefully if LP0 watermarks
2406 * are exceeded...
2407 */
2408 if (level == 0 && !result->enable) {
2409 if (result->pri_val > max->pri)
2410 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2411 level, result->pri_val, max->pri);
2412 if (result->spr_val > max->spr)
2413 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2414 level, result->spr_val, max->spr);
2415 if (result->cur_val > max->cur)
2416 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2417 level, result->cur_val, max->cur);
2418
2419 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2420 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2421 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2422 result->enable = true;
2423 }
2424
2425 return ret;
2426 }
2427
2428 static void ilk_compute_wm_level(struct drm_i915_private *dev_priv,
2429 int level,
2430 const struct hsw_pipe_wm_parameters *p,
2431 struct intel_wm_level *result)
2432 {
2433 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2434 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2435 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2436
2437 /* WM1+ latency values stored in 0.5us units */
2438 if (level > 0) {
2439 pri_latency *= 5;
2440 spr_latency *= 5;
2441 cur_latency *= 5;
2442 }
2443
2444 result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
2445 result->spr_val = ilk_compute_spr_wm(p, spr_latency);
2446 result->cur_val = ilk_compute_cur_wm(p, cur_latency);
2447 result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
2448 result->enable = true;
2449 }
2450
2451 static uint32_t
2452 hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
2453 {
2454 struct drm_i915_private *dev_priv = dev->dev_private;
2455 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2456 struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
2457 u32 linetime, ips_linetime;
2458
2459 if (!intel_crtc_active(crtc))
2460 return 0;
2461
2462 /* The WM are computed with base on how long it takes to fill a single
2463 * row at the given clock rate, multiplied by 8.
2464 * */
2465 linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8, mode->clock);
2466 ips_linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8,
2467 intel_ddi_get_cdclk_freq(dev_priv));
2468
2469 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2470 PIPE_WM_LINETIME_TIME(linetime);
2471 }
2472
2473 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5])
2474 {
2475 struct drm_i915_private *dev_priv = dev->dev_private;
2476
2477 if (IS_HASWELL(dev)) {
2478 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2479
2480 wm[0] = (sskpd >> 56) & 0xFF;
2481 if (wm[0] == 0)
2482 wm[0] = sskpd & 0xF;
2483 wm[1] = (sskpd >> 4) & 0xFF;
2484 wm[2] = (sskpd >> 12) & 0xFF;
2485 wm[3] = (sskpd >> 20) & 0x1FF;
2486 wm[4] = (sskpd >> 32) & 0x1FF;
2487 } else if (INTEL_INFO(dev)->gen >= 6) {
2488 uint32_t sskpd = I915_READ(MCH_SSKPD);
2489
2490 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2491 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2492 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2493 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2494 } else if (INTEL_INFO(dev)->gen >= 5) {
2495 uint32_t mltr = I915_READ(MLTR_ILK);
2496
2497 /* ILK primary LP0 latency is 700 ns */
2498 wm[0] = 7;
2499 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2500 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2501 }
2502 }
2503
2504 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2505 {
2506 /* ILK sprite LP0 latency is 1300 ns */
2507 if (INTEL_INFO(dev)->gen == 5)
2508 wm[0] = 13;
2509 }
2510
2511 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2512 {
2513 /* ILK cursor LP0 latency is 1300 ns */
2514 if (INTEL_INFO(dev)->gen == 5)
2515 wm[0] = 13;
2516
2517 /* WaDoubleCursorLP3Latency:ivb */
2518 if (IS_IVYBRIDGE(dev))
2519 wm[3] *= 2;
2520 }
2521
2522 static int ilk_wm_max_level(const struct drm_device *dev)
2523 {
2524 /* how many WM levels are we expecting */
2525 if (IS_HASWELL(dev))
2526 return 4;
2527 else if (INTEL_INFO(dev)->gen >= 6)
2528 return 3;
2529 else
2530 return 2;
2531 }
2532
2533 static void intel_print_wm_latency(struct drm_device *dev,
2534 const char *name,
2535 const uint16_t wm[5])
2536 {
2537 int level, max_level = ilk_wm_max_level(dev);
2538
2539 for (level = 0; level <= max_level; level++) {
2540 unsigned int latency = wm[level];
2541
2542 if (latency == 0) {
2543 DRM_ERROR("%s WM%d latency not provided\n",
2544 name, level);
2545 continue;
2546 }
2547
2548 /* WM1+ latency values in 0.5us units */
2549 if (level > 0)
2550 latency *= 5;
2551
2552 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2553 name, level, wm[level],
2554 latency / 10, latency % 10);
2555 }
2556 }
2557
2558 static void intel_setup_wm_latency(struct drm_device *dev)
2559 {
2560 struct drm_i915_private *dev_priv = dev->dev_private;
2561
2562 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2563
2564 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2565 sizeof(dev_priv->wm.pri_latency));
2566 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2567 sizeof(dev_priv->wm.pri_latency));
2568
2569 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2570 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2571
2572 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2573 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2574 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2575 }
2576
2577 static void hsw_compute_wm_parameters(struct drm_crtc *crtc,
2578 struct hsw_pipe_wm_parameters *p,
2579 struct intel_wm_config *config)
2580 {
2581 struct drm_device *dev = crtc->dev;
2582 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2583 enum pipe pipe = intel_crtc->pipe;
2584 struct drm_plane *plane;
2585
2586 p->active = intel_crtc_active(crtc);
2587 if (p->active) {
2588 p->pipe_htotal = intel_crtc->config.adjusted_mode.htotal;
2589 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
2590 p->pri.bytes_per_pixel = crtc->fb->bits_per_pixel / 8;
2591 p->cur.bytes_per_pixel = 4;
2592 p->pri.horiz_pixels = intel_crtc->config.pipe_src_w;
2593 p->cur.horiz_pixels = 64;
2594 /* TODO: for now, assume primary and cursor planes are always enabled. */
2595 p->pri.enabled = true;
2596 p->cur.enabled = true;
2597 }
2598
2599 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
2600 config->num_pipes_active += intel_crtc_active(crtc);
2601
2602 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2603 struct intel_plane *intel_plane = to_intel_plane(plane);
2604
2605 if (intel_plane->pipe == pipe)
2606 p->spr = intel_plane->wm;
2607
2608 config->sprites_enabled |= intel_plane->wm.enabled;
2609 config->sprites_scaled |= intel_plane->wm.scaled;
2610 }
2611 }
2612
2613 /* Compute new watermarks for the pipe */
2614 static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
2615 const struct hsw_pipe_wm_parameters *params,
2616 struct intel_pipe_wm *pipe_wm)
2617 {
2618 struct drm_device *dev = crtc->dev;
2619 struct drm_i915_private *dev_priv = dev->dev_private;
2620 int level, max_level = ilk_wm_max_level(dev);
2621 /* LP0 watermark maximums depend on this pipe alone */
2622 struct intel_wm_config config = {
2623 .num_pipes_active = 1,
2624 .sprites_enabled = params->spr.enabled,
2625 .sprites_scaled = params->spr.scaled,
2626 };
2627 struct hsw_wm_maximums max;
2628
2629 /* LP0 watermarks always use 1/2 DDB partitioning */
2630 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2631
2632 for (level = 0; level <= max_level; level++)
2633 ilk_compute_wm_level(dev_priv, level, params,
2634 &pipe_wm->wm[level]);
2635
2636 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
2637
2638 /* At least LP0 must be valid */
2639 return ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]);
2640 }
2641
2642 /*
2643 * Merge the watermarks from all active pipes for a specific level.
2644 */
2645 static void ilk_merge_wm_level(struct drm_device *dev,
2646 int level,
2647 struct intel_wm_level *ret_wm)
2648 {
2649 const struct intel_crtc *intel_crtc;
2650
2651 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) {
2652 const struct intel_wm_level *wm =
2653 &intel_crtc->wm.active.wm[level];
2654
2655 if (!wm->enable)
2656 return;
2657
2658 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2659 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2660 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2661 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2662 }
2663
2664 ret_wm->enable = true;
2665 }
2666
2667 /*
2668 * Merge all low power watermarks for all active pipes.
2669 */
2670 static void ilk_wm_merge(struct drm_device *dev,
2671 const struct hsw_wm_maximums *max,
2672 struct intel_pipe_wm *merged)
2673 {
2674 int level, max_level = ilk_wm_max_level(dev);
2675
2676 merged->fbc_wm_enabled = true;
2677
2678 /* merge each WM1+ level */
2679 for (level = 1; level <= max_level; level++) {
2680 struct intel_wm_level *wm = &merged->wm[level];
2681
2682 ilk_merge_wm_level(dev, level, wm);
2683
2684 if (!ilk_validate_wm_level(level, max, wm))
2685 break;
2686
2687 /*
2688 * The spec says it is preferred to disable
2689 * FBC WMs instead of disabling a WM level.
2690 */
2691 if (wm->fbc_val > max->fbc) {
2692 merged->fbc_wm_enabled = false;
2693 wm->fbc_val = 0;
2694 }
2695 }
2696 }
2697
2698 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2699 {
2700 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2701 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2702 }
2703
2704 static void hsw_compute_wm_results(struct drm_device *dev,
2705 const struct intel_pipe_wm *merged,
2706 enum intel_ddb_partitioning partitioning,
2707 struct hsw_wm_values *results)
2708 {
2709 struct intel_crtc *intel_crtc;
2710 int level, wm_lp;
2711
2712 results->enable_fbc_wm = merged->fbc_wm_enabled;
2713 results->partitioning = partitioning;
2714
2715 /* LP1+ register values */
2716 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2717 const struct intel_wm_level *r;
2718
2719 level = ilk_wm_lp_to_level(wm_lp, merged);
2720
2721 r = &merged->wm[level];
2722 if (!r->enable)
2723 break;
2724
2725 results->wm_lp[wm_lp - 1] = HSW_WM_LP_VAL(level * 2,
2726 r->fbc_val,
2727 r->pri_val,
2728 r->cur_val);
2729 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2730 }
2731
2732 /* LP0 register values */
2733 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) {
2734 enum pipe pipe = intel_crtc->pipe;
2735 const struct intel_wm_level *r =
2736 &intel_crtc->wm.active.wm[0];
2737
2738 if (WARN_ON(!r->enable))
2739 continue;
2740
2741 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
2742
2743 results->wm_pipe[pipe] =
2744 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2745 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2746 r->cur_val;
2747 }
2748 }
2749
2750 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2751 * case both are at the same level. Prefer r1 in case they're the same. */
2752 static struct intel_pipe_wm *hsw_find_best_result(struct drm_device *dev,
2753 struct intel_pipe_wm *r1,
2754 struct intel_pipe_wm *r2)
2755 {
2756 int level, max_level = ilk_wm_max_level(dev);
2757 int level1 = 0, level2 = 0;
2758
2759 for (level = 1; level <= max_level; level++) {
2760 if (r1->wm[level].enable)
2761 level1 = level;
2762 if (r2->wm[level].enable)
2763 level2 = level;
2764 }
2765
2766 if (level1 == level2) {
2767 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2768 return r2;
2769 else
2770 return r1;
2771 } else if (level1 > level2) {
2772 return r1;
2773 } else {
2774 return r2;
2775 }
2776 }
2777
2778 /* dirty bits used to track which watermarks need changes */
2779 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2780 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2781 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2782 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2783 #define WM_DIRTY_FBC (1 << 24)
2784 #define WM_DIRTY_DDB (1 << 25)
2785
2786 static unsigned int ilk_compute_wm_dirty(struct drm_device *dev,
2787 const struct hsw_wm_values *old,
2788 const struct hsw_wm_values *new)
2789 {
2790 unsigned int dirty = 0;
2791 enum pipe pipe;
2792 int wm_lp;
2793
2794 for_each_pipe(pipe) {
2795 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2796 dirty |= WM_DIRTY_LINETIME(pipe);
2797 /* Must disable LP1+ watermarks too */
2798 dirty |= WM_DIRTY_LP_ALL;
2799 }
2800
2801 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2802 dirty |= WM_DIRTY_PIPE(pipe);
2803 /* Must disable LP1+ watermarks too */
2804 dirty |= WM_DIRTY_LP_ALL;
2805 }
2806 }
2807
2808 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2809 dirty |= WM_DIRTY_FBC;
2810 /* Must disable LP1+ watermarks too */
2811 dirty |= WM_DIRTY_LP_ALL;
2812 }
2813
2814 if (old->partitioning != new->partitioning) {
2815 dirty |= WM_DIRTY_DDB;
2816 /* Must disable LP1+ watermarks too */
2817 dirty |= WM_DIRTY_LP_ALL;
2818 }
2819
2820 /* LP1+ watermarks already deemed dirty, no need to continue */
2821 if (dirty & WM_DIRTY_LP_ALL)
2822 return dirty;
2823
2824 /* Find the lowest numbered LP1+ watermark in need of an update... */
2825 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2826 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2827 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2828 break;
2829 }
2830
2831 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2832 for (; wm_lp <= 3; wm_lp++)
2833 dirty |= WM_DIRTY_LP(wm_lp);
2834
2835 return dirty;
2836 }
2837
2838 /*
2839 * The spec says we shouldn't write when we don't need, because every write
2840 * causes WMs to be re-evaluated, expending some power.
2841 */
2842 static void hsw_write_wm_values(struct drm_i915_private *dev_priv,
2843 struct hsw_wm_values *results)
2844 {
2845 struct hsw_wm_values *previous = &dev_priv->wm.hw;
2846 unsigned int dirty;
2847 uint32_t val;
2848
2849 dirty = ilk_compute_wm_dirty(dev_priv->dev, previous, results);
2850 if (!dirty)
2851 return;
2852
2853 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != 0)
2854 I915_WRITE(WM3_LP_ILK, 0);
2855 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != 0)
2856 I915_WRITE(WM2_LP_ILK, 0);
2857 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != 0)
2858 I915_WRITE(WM1_LP_ILK, 0);
2859
2860 if (dirty & WM_DIRTY_PIPE(PIPE_A))
2861 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2862 if (dirty & WM_DIRTY_PIPE(PIPE_B))
2863 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2864 if (dirty & WM_DIRTY_PIPE(PIPE_C))
2865 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2866
2867 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2868 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2869 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2870 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2871 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2872 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2873
2874 if (dirty & WM_DIRTY_DDB) {
2875 val = I915_READ(WM_MISC);
2876 if (results->partitioning == INTEL_DDB_PART_1_2)
2877 val &= ~WM_MISC_DATA_PARTITION_5_6;
2878 else
2879 val |= WM_MISC_DATA_PARTITION_5_6;
2880 I915_WRITE(WM_MISC, val);
2881 }
2882
2883 if (dirty & WM_DIRTY_FBC) {
2884 val = I915_READ(DISP_ARB_CTL);
2885 if (results->enable_fbc_wm)
2886 val &= ~DISP_FBC_WM_DIS;
2887 else
2888 val |= DISP_FBC_WM_DIS;
2889 I915_WRITE(DISP_ARB_CTL, val);
2890 }
2891
2892 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2893 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2894 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2895 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2896 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2897 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2898
2899 if (dirty & WM_DIRTY_LP(1) && results->wm_lp[0] != 0)
2900 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2901 if (dirty & WM_DIRTY_LP(2) && results->wm_lp[1] != 0)
2902 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2903 if (dirty & WM_DIRTY_LP(3) && results->wm_lp[2] != 0)
2904 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2905
2906 dev_priv->wm.hw = *results;
2907 }
2908
2909 static void haswell_update_wm(struct drm_crtc *crtc)
2910 {
2911 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2912 struct drm_device *dev = crtc->dev;
2913 struct drm_i915_private *dev_priv = dev->dev_private;
2914 struct hsw_wm_maximums max;
2915 struct hsw_pipe_wm_parameters params = {};
2916 struct hsw_wm_values results = {};
2917 enum intel_ddb_partitioning partitioning;
2918 struct intel_pipe_wm pipe_wm = {};
2919 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
2920 struct intel_wm_config config = {};
2921
2922 hsw_compute_wm_parameters(crtc, &params, &config);
2923
2924 intel_compute_pipe_wm(crtc, &params, &pipe_wm);
2925
2926 if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
2927 return;
2928
2929 intel_crtc->wm.active = pipe_wm;
2930
2931 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
2932 ilk_wm_merge(dev, &max, &lp_wm_1_2);
2933
2934 /* 5/6 split only in single pipe config on IVB+ */
2935 if (INTEL_INFO(dev)->gen >= 7 &&
2936 config.num_pipes_active == 1 && config.sprites_enabled) {
2937 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
2938 ilk_wm_merge(dev, &max, &lp_wm_5_6);
2939
2940 best_lp_wm = hsw_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
2941 } else {
2942 best_lp_wm = &lp_wm_1_2;
2943 }
2944
2945 partitioning = (best_lp_wm == &lp_wm_1_2) ?
2946 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
2947
2948 hsw_compute_wm_results(dev, best_lp_wm, partitioning, &results);
2949
2950 hsw_write_wm_values(dev_priv, &results);
2951 }
2952
2953 static void haswell_update_sprite_wm(struct drm_plane *plane,
2954 struct drm_crtc *crtc,
2955 uint32_t sprite_width, int pixel_size,
2956 bool enabled, bool scaled)
2957 {
2958 struct intel_plane *intel_plane = to_intel_plane(plane);
2959
2960 intel_plane->wm.enabled = enabled;
2961 intel_plane->wm.scaled = scaled;
2962 intel_plane->wm.horiz_pixels = sprite_width;
2963 intel_plane->wm.bytes_per_pixel = pixel_size;
2964
2965 haswell_update_wm(crtc);
2966 }
2967
2968 static bool
2969 sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
2970 uint32_t sprite_width, int pixel_size,
2971 const struct intel_watermark_params *display,
2972 int display_latency_ns, int *sprite_wm)
2973 {
2974 struct drm_crtc *crtc;
2975 int clock;
2976 int entries, tlb_miss;
2977
2978 crtc = intel_get_crtc_for_plane(dev, plane);
2979 if (!intel_crtc_active(crtc)) {
2980 *sprite_wm = display->guard_size;
2981 return false;
2982 }
2983
2984 clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
2985
2986 /* Use the small buffer method to calculate the sprite watermark */
2987 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
2988 tlb_miss = display->fifo_size*display->cacheline_size -
2989 sprite_width * 8;
2990 if (tlb_miss > 0)
2991 entries += tlb_miss;
2992 entries = DIV_ROUND_UP(entries, display->cacheline_size);
2993 *sprite_wm = entries + display->guard_size;
2994 if (*sprite_wm > (int)display->max_wm)
2995 *sprite_wm = display->max_wm;
2996
2997 return true;
2998 }
2999
3000 static bool
3001 sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
3002 uint32_t sprite_width, int pixel_size,
3003 const struct intel_watermark_params *display,
3004 int latency_ns, int *sprite_wm)
3005 {
3006 struct drm_crtc *crtc;
3007 unsigned long line_time_us;
3008 int clock;
3009 int line_count, line_size;
3010 int small, large;
3011 int entries;
3012
3013 if (!latency_ns) {
3014 *sprite_wm = 0;
3015 return false;
3016 }
3017
3018 crtc = intel_get_crtc_for_plane(dev, plane);
3019 clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3020 if (!clock) {
3021 *sprite_wm = 0;
3022 return false;
3023 }
3024
3025 line_time_us = (sprite_width * 1000) / clock;
3026 if (!line_time_us) {
3027 *sprite_wm = 0;
3028 return false;
3029 }
3030
3031 line_count = (latency_ns / line_time_us + 1000) / 1000;
3032 line_size = sprite_width * pixel_size;
3033
3034 /* Use the minimum of the small and large buffer method for primary */
3035 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
3036 large = line_count * line_size;
3037
3038 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
3039 *sprite_wm = entries + display->guard_size;
3040
3041 return *sprite_wm > 0x3ff ? false : true;
3042 }
3043
3044 static void sandybridge_update_sprite_wm(struct drm_plane *plane,
3045 struct drm_crtc *crtc,
3046 uint32_t sprite_width, int pixel_size,
3047 bool enabled, bool scaled)
3048 {
3049 struct drm_device *dev = plane->dev;
3050 struct drm_i915_private *dev_priv = dev->dev_private;
3051 int pipe = to_intel_plane(plane)->pipe;
3052 int latency = dev_priv->wm.spr_latency[0] * 100; /* In unit 0.1us */
3053 u32 val;
3054 int sprite_wm, reg;
3055 int ret;
3056
3057 if (!enabled)
3058 return;
3059
3060 switch (pipe) {
3061 case 0:
3062 reg = WM0_PIPEA_ILK;
3063 break;
3064 case 1:
3065 reg = WM0_PIPEB_ILK;
3066 break;
3067 case 2:
3068 reg = WM0_PIPEC_IVB;
3069 break;
3070 default:
3071 return; /* bad pipe */
3072 }
3073
3074 ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
3075 &sandybridge_display_wm_info,
3076 latency, &sprite_wm);
3077 if (!ret) {
3078 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %c\n",
3079 pipe_name(pipe));
3080 return;
3081 }
3082
3083 val = I915_READ(reg);
3084 val &= ~WM0_PIPE_SPRITE_MASK;
3085 I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
3086 DRM_DEBUG_KMS("sprite watermarks For pipe %c - %d\n", pipe_name(pipe), sprite_wm);
3087
3088
3089 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
3090 pixel_size,
3091 &sandybridge_display_srwm_info,
3092 dev_priv->wm.spr_latency[1] * 500,
3093 &sprite_wm);
3094 if (!ret) {
3095 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %c\n",
3096 pipe_name(pipe));
3097 return;
3098 }
3099 I915_WRITE(WM1S_LP_ILK, sprite_wm);
3100
3101 /* Only IVB has two more LP watermarks for sprite */
3102 if (!IS_IVYBRIDGE(dev))
3103 return;
3104
3105 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
3106 pixel_size,
3107 &sandybridge_display_srwm_info,
3108 dev_priv->wm.spr_latency[2] * 500,
3109 &sprite_wm);
3110 if (!ret) {
3111 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %c\n",
3112 pipe_name(pipe));
3113 return;
3114 }
3115 I915_WRITE(WM2S_LP_IVB, sprite_wm);
3116
3117 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
3118 pixel_size,
3119 &sandybridge_display_srwm_info,
3120 dev_priv->wm.spr_latency[3] * 500,
3121 &sprite_wm);
3122 if (!ret) {
3123 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %c\n",
3124 pipe_name(pipe));
3125 return;
3126 }
3127 I915_WRITE(WM3S_LP_IVB, sprite_wm);
3128 }
3129
3130 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3131 {
3132 struct drm_device *dev = crtc->dev;
3133 struct drm_i915_private *dev_priv = dev->dev_private;
3134 struct hsw_wm_values *hw = &dev_priv->wm.hw;
3135 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3136 struct intel_pipe_wm *active = &intel_crtc->wm.active;
3137 enum pipe pipe = intel_crtc->pipe;
3138 static const unsigned int wm0_pipe_reg[] = {
3139 [PIPE_A] = WM0_PIPEA_ILK,
3140 [PIPE_B] = WM0_PIPEB_ILK,
3141 [PIPE_C] = WM0_PIPEC_IVB,
3142 };
3143
3144 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
3145 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3146
3147 if (intel_crtc_active(crtc)) {
3148 u32 tmp = hw->wm_pipe[pipe];
3149
3150 /*
3151 * For active pipes LP0 watermark is marked as
3152 * enabled, and LP1+ watermaks as disabled since
3153 * we can't really reverse compute them in case
3154 * multiple pipes are active.
3155 */
3156 active->wm[0].enable = true;
3157 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3158 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3159 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3160 active->linetime = hw->wm_linetime[pipe];
3161 } else {
3162 int level, max_level = ilk_wm_max_level(dev);
3163
3164 /*
3165 * For inactive pipes, all watermark levels
3166 * should be marked as enabled but zeroed,
3167 * which is what we'd compute them to.
3168 */
3169 for (level = 0; level <= max_level; level++)
3170 active->wm[level].enable = true;
3171 }
3172 }
3173
3174 void ilk_wm_get_hw_state(struct drm_device *dev)
3175 {
3176 struct drm_i915_private *dev_priv = dev->dev_private;
3177 struct hsw_wm_values *hw = &dev_priv->wm.hw;
3178 struct drm_crtc *crtc;
3179
3180 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3181 ilk_pipe_wm_get_hw_state(crtc);
3182
3183 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
3184 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
3185 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
3186
3187 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
3188 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
3189 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
3190
3191 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
3192 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
3193
3194 hw->enable_fbc_wm =
3195 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
3196 }
3197
3198 /**
3199 * intel_update_watermarks - update FIFO watermark values based on current modes
3200 *
3201 * Calculate watermark values for the various WM regs based on current mode
3202 * and plane configuration.
3203 *
3204 * There are several cases to deal with here:
3205 * - normal (i.e. non-self-refresh)
3206 * - self-refresh (SR) mode
3207 * - lines are large relative to FIFO size (buffer can hold up to 2)
3208 * - lines are small relative to FIFO size (buffer can hold more than 2
3209 * lines), so need to account for TLB latency
3210 *
3211 * The normal calculation is:
3212 * watermark = dotclock * bytes per pixel * latency
3213 * where latency is platform & configuration dependent (we assume pessimal
3214 * values here).
3215 *
3216 * The SR calculation is:
3217 * watermark = (trunc(latency/line time)+1) * surface width *
3218 * bytes per pixel
3219 * where
3220 * line time = htotal / dotclock
3221 * surface width = hdisplay for normal plane and 64 for cursor
3222 * and latency is assumed to be high, as above.
3223 *
3224 * The final value programmed to the register should always be rounded up,
3225 * and include an extra 2 entries to account for clock crossings.
3226 *
3227 * We don't use the sprite, so we can ignore that. And on Crestline we have
3228 * to set the non-SR watermarks to 8.
3229 */
3230 void intel_update_watermarks(struct drm_crtc *crtc)
3231 {
3232 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
3233
3234 if (dev_priv->display.update_wm)
3235 dev_priv->display.update_wm(crtc);
3236 }
3237
3238 void intel_update_sprite_watermarks(struct drm_plane *plane,
3239 struct drm_crtc *crtc,
3240 uint32_t sprite_width, int pixel_size,
3241 bool enabled, bool scaled)
3242 {
3243 struct drm_i915_private *dev_priv = plane->dev->dev_private;
3244
3245 if (dev_priv->display.update_sprite_wm)
3246 dev_priv->display.update_sprite_wm(plane, crtc, sprite_width,
3247 pixel_size, enabled, scaled);
3248 }
3249
3250 static struct drm_i915_gem_object *
3251 intel_alloc_context_page(struct drm_device *dev)
3252 {
3253 struct drm_i915_gem_object *ctx;
3254 int ret;
3255
3256 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3257
3258 ctx = i915_gem_alloc_object(dev, 4096);
3259 if (!ctx) {
3260 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
3261 return NULL;
3262 }
3263
3264 ret = i915_gem_obj_ggtt_pin(ctx, 4096, true, false);
3265 if (ret) {
3266 DRM_ERROR("failed to pin power context: %d\n", ret);
3267 goto err_unref;
3268 }
3269
3270 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
3271 if (ret) {
3272 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
3273 goto err_unpin;
3274 }
3275
3276 return ctx;
3277
3278 err_unpin:
3279 i915_gem_object_unpin(ctx);
3280 err_unref:
3281 drm_gem_object_unreference(&ctx->base);
3282 return NULL;
3283 }
3284
3285 /**
3286 * Lock protecting IPS related data structures
3287 */
3288 DEFINE_SPINLOCK(mchdev_lock);
3289
3290 /* Global for IPS driver to get at the current i915 device. Protected by
3291 * mchdev_lock. */
3292 static struct drm_i915_private *i915_mch_dev;
3293
3294 bool ironlake_set_drps(struct drm_device *dev, u8 val)
3295 {
3296 struct drm_i915_private *dev_priv = dev->dev_private;
3297 u16 rgvswctl;
3298
3299 assert_spin_locked(&mchdev_lock);
3300
3301 rgvswctl = I915_READ16(MEMSWCTL);
3302 if (rgvswctl & MEMCTL_CMD_STS) {
3303 DRM_DEBUG("gpu busy, RCS change rejected\n");
3304 return false; /* still busy with another command */
3305 }
3306
3307 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
3308 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
3309 I915_WRITE16(MEMSWCTL, rgvswctl);
3310 POSTING_READ16(MEMSWCTL);
3311
3312 rgvswctl |= MEMCTL_CMD_STS;
3313 I915_WRITE16(MEMSWCTL, rgvswctl);
3314
3315 return true;
3316 }
3317
3318 static void ironlake_enable_drps(struct drm_device *dev)
3319 {
3320 struct drm_i915_private *dev_priv = dev->dev_private;
3321 u32 rgvmodectl = I915_READ(MEMMODECTL);
3322 u8 fmax, fmin, fstart, vstart;
3323
3324 spin_lock_irq(&mchdev_lock);
3325
3326 /* Enable temp reporting */
3327 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
3328 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
3329
3330 /* 100ms RC evaluation intervals */
3331 I915_WRITE(RCUPEI, 100000);
3332 I915_WRITE(RCDNEI, 100000);
3333
3334 /* Set max/min thresholds to 90ms and 80ms respectively */
3335 I915_WRITE(RCBMAXAVG, 90000);
3336 I915_WRITE(RCBMINAVG, 80000);
3337
3338 I915_WRITE(MEMIHYST, 1);
3339
3340 /* Set up min, max, and cur for interrupt handling */
3341 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
3342 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
3343 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
3344 MEMMODE_FSTART_SHIFT;
3345
3346 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
3347 PXVFREQ_PX_SHIFT;
3348
3349 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
3350 dev_priv->ips.fstart = fstart;
3351
3352 dev_priv->ips.max_delay = fstart;
3353 dev_priv->ips.min_delay = fmin;
3354 dev_priv->ips.cur_delay = fstart;
3355
3356 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
3357 fmax, fmin, fstart);
3358
3359 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
3360
3361 /*
3362 * Interrupts will be enabled in ironlake_irq_postinstall
3363 */
3364
3365 I915_WRITE(VIDSTART, vstart);
3366 POSTING_READ(VIDSTART);
3367
3368 rgvmodectl |= MEMMODE_SWMODE_EN;
3369 I915_WRITE(MEMMODECTL, rgvmodectl);
3370
3371 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
3372 DRM_ERROR("stuck trying to change perf mode\n");
3373 mdelay(1);
3374
3375 ironlake_set_drps(dev, fstart);
3376
3377 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
3378 I915_READ(0x112e0);
3379 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
3380 dev_priv->ips.last_count2 = I915_READ(0x112f4);
3381 getrawmonotonic(&dev_priv->ips.last_time2);
3382
3383 spin_unlock_irq(&mchdev_lock);
3384 }
3385
3386 static void ironlake_disable_drps(struct drm_device *dev)
3387 {
3388 struct drm_i915_private *dev_priv = dev->dev_private;
3389 u16 rgvswctl;
3390
3391 spin_lock_irq(&mchdev_lock);
3392
3393 rgvswctl = I915_READ16(MEMSWCTL);
3394
3395 /* Ack interrupts, disable EFC interrupt */
3396 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
3397 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
3398 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
3399 I915_WRITE(DEIIR, DE_PCU_EVENT);
3400 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
3401
3402 /* Go back to the starting frequency */
3403 ironlake_set_drps(dev, dev_priv->ips.fstart);
3404 mdelay(1);
3405 rgvswctl |= MEMCTL_CMD_STS;
3406 I915_WRITE(MEMSWCTL, rgvswctl);
3407 mdelay(1);
3408
3409 spin_unlock_irq(&mchdev_lock);
3410 }
3411
3412 /* There's a funny hw issue where the hw returns all 0 when reading from
3413 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3414 * ourselves, instead of doing a rmw cycle (which might result in us clearing
3415 * all limits and the gpu stuck at whatever frequency it is at atm).
3416 */
3417 static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 *val)
3418 {
3419 u32 limits;
3420
3421 limits = 0;
3422
3423 if (*val >= dev_priv->rps.max_delay)
3424 *val = dev_priv->rps.max_delay;
3425 limits |= dev_priv->rps.max_delay << 24;
3426
3427 /* Only set the down limit when we've reached the lowest level to avoid
3428 * getting more interrupts, otherwise leave this clear. This prevents a
3429 * race in the hw when coming out of rc6: There's a tiny window where
3430 * the hw runs at the minimal clock before selecting the desired
3431 * frequency, if the down threshold expires in that window we will not
3432 * receive a down interrupt. */
3433 if (*val <= dev_priv->rps.min_delay) {
3434 *val = dev_priv->rps.min_delay;
3435 limits |= dev_priv->rps.min_delay << 16;
3436 }
3437
3438 return limits;
3439 }
3440
3441 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
3442 {
3443 int new_power;
3444
3445 new_power = dev_priv->rps.power;
3446 switch (dev_priv->rps.power) {
3447 case LOW_POWER:
3448 if (val > dev_priv->rps.rpe_delay + 1 && val > dev_priv->rps.cur_delay)
3449 new_power = BETWEEN;
3450 break;
3451
3452 case BETWEEN:
3453 if (val <= dev_priv->rps.rpe_delay && val < dev_priv->rps.cur_delay)
3454 new_power = LOW_POWER;
3455 else if (val >= dev_priv->rps.rp0_delay && val > dev_priv->rps.cur_delay)
3456 new_power = HIGH_POWER;
3457 break;
3458
3459 case HIGH_POWER:
3460 if (val < (dev_priv->rps.rp1_delay + dev_priv->rps.rp0_delay) >> 1 && val < dev_priv->rps.cur_delay)
3461 new_power = BETWEEN;
3462 break;
3463 }
3464 /* Max/min bins are special */
3465 if (val == dev_priv->rps.min_delay)
3466 new_power = LOW_POWER;
3467 if (val == dev_priv->rps.max_delay)
3468 new_power = HIGH_POWER;
3469 if (new_power == dev_priv->rps.power)
3470 return;
3471
3472 /* Note the units here are not exactly 1us, but 1280ns. */
3473 switch (new_power) {
3474 case LOW_POWER:
3475 /* Upclock if more than 95% busy over 16ms */
3476 I915_WRITE(GEN6_RP_UP_EI, 12500);
3477 I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800);
3478
3479 /* Downclock if less than 85% busy over 32ms */
3480 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3481 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250);
3482
3483 I915_WRITE(GEN6_RP_CONTROL,
3484 GEN6_RP_MEDIA_TURBO |
3485 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3486 GEN6_RP_MEDIA_IS_GFX |
3487 GEN6_RP_ENABLE |
3488 GEN6_RP_UP_BUSY_AVG |
3489 GEN6_RP_DOWN_IDLE_AVG);
3490 break;
3491
3492 case BETWEEN:
3493 /* Upclock if more than 90% busy over 13ms */
3494 I915_WRITE(GEN6_RP_UP_EI, 10250);
3495 I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225);
3496
3497 /* Downclock if less than 75% busy over 32ms */
3498 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3499 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750);
3500
3501 I915_WRITE(GEN6_RP_CONTROL,
3502 GEN6_RP_MEDIA_TURBO |
3503 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3504 GEN6_RP_MEDIA_IS_GFX |
3505 GEN6_RP_ENABLE |
3506 GEN6_RP_UP_BUSY_AVG |
3507 GEN6_RP_DOWN_IDLE_AVG);
3508 break;
3509
3510 case HIGH_POWER:
3511 /* Upclock if more than 85% busy over 10ms */
3512 I915_WRITE(GEN6_RP_UP_EI, 8000);
3513 I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800);
3514
3515 /* Downclock if less than 60% busy over 32ms */
3516 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3517 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000);
3518
3519 I915_WRITE(GEN6_RP_CONTROL,
3520 GEN6_RP_MEDIA_TURBO |
3521 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3522 GEN6_RP_MEDIA_IS_GFX |
3523 GEN6_RP_ENABLE |
3524 GEN6_RP_UP_BUSY_AVG |
3525 GEN6_RP_DOWN_IDLE_AVG);
3526 break;
3527 }
3528
3529 dev_priv->rps.power = new_power;
3530 dev_priv->rps.last_adj = 0;
3531 }
3532
3533 void gen6_set_rps(struct drm_device *dev, u8 val)
3534 {
3535 struct drm_i915_private *dev_priv = dev->dev_private;
3536 u32 limits = gen6_rps_limits(dev_priv, &val);
3537
3538 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3539 WARN_ON(val > dev_priv->rps.max_delay);
3540 WARN_ON(val < dev_priv->rps.min_delay);
3541
3542 if (val == dev_priv->rps.cur_delay)
3543 return;
3544
3545 gen6_set_rps_thresholds(dev_priv, val);
3546
3547 if (IS_HASWELL(dev))
3548 I915_WRITE(GEN6_RPNSWREQ,
3549 HSW_FREQUENCY(val));
3550 else
3551 I915_WRITE(GEN6_RPNSWREQ,
3552 GEN6_FREQUENCY(val) |
3553 GEN6_OFFSET(0) |
3554 GEN6_AGGRESSIVE_TURBO);
3555
3556 /* Make sure we continue to get interrupts
3557 * until we hit the minimum or maximum frequencies.
3558 */
3559 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
3560
3561 POSTING_READ(GEN6_RPNSWREQ);
3562
3563 dev_priv->rps.cur_delay = val;
3564
3565 trace_intel_gpu_freq_change(val * 50);
3566 }
3567
3568 void gen6_rps_idle(struct drm_i915_private *dev_priv)
3569 {
3570 mutex_lock(&dev_priv->rps.hw_lock);
3571 if (dev_priv->rps.enabled) {
3572 if (dev_priv->info->is_valleyview)
3573 valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
3574 else
3575 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
3576 dev_priv->rps.last_adj = 0;
3577 }
3578 mutex_unlock(&dev_priv->rps.hw_lock);
3579 }
3580
3581 void gen6_rps_boost(struct drm_i915_private *dev_priv)
3582 {
3583 mutex_lock(&dev_priv->rps.hw_lock);
3584 if (dev_priv->rps.enabled) {
3585 if (dev_priv->info->is_valleyview)
3586 valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_delay);
3587 else
3588 gen6_set_rps(dev_priv->dev, dev_priv->rps.max_delay);
3589 dev_priv->rps.last_adj = 0;
3590 }
3591 mutex_unlock(&dev_priv->rps.hw_lock);
3592 }
3593
3594 /*
3595 * Wait until the previous freq change has completed,
3596 * or the timeout elapsed, and then update our notion
3597 * of the current GPU frequency.
3598 */
3599 static void vlv_update_rps_cur_delay(struct drm_i915_private *dev_priv)
3600 {
3601 u32 pval;
3602
3603 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3604
3605 if (wait_for(((pval = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS)) & GENFREQSTATUS) == 0, 10))
3606 DRM_DEBUG_DRIVER("timed out waiting for Punit\n");
3607
3608 pval >>= 8;
3609
3610 if (pval != dev_priv->rps.cur_delay)
3611 DRM_DEBUG_DRIVER("Punit overrode GPU freq: %d MHz (%u) requested, but got %d Mhz (%u)\n",
3612 vlv_gpu_freq(dev_priv->mem_freq, dev_priv->rps.cur_delay),
3613 dev_priv->rps.cur_delay,
3614 vlv_gpu_freq(dev_priv->mem_freq, pval), pval);
3615
3616 dev_priv->rps.cur_delay = pval;
3617 }
3618
3619 void valleyview_set_rps(struct drm_device *dev, u8 val)
3620 {
3621 struct drm_i915_private *dev_priv = dev->dev_private;
3622
3623 gen6_rps_limits(dev_priv, &val);
3624
3625 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3626 WARN_ON(val > dev_priv->rps.max_delay);
3627 WARN_ON(val < dev_priv->rps.min_delay);
3628
3629 vlv_update_rps_cur_delay(dev_priv);
3630
3631 DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
3632 vlv_gpu_freq(dev_priv->mem_freq,
3633 dev_priv->rps.cur_delay),
3634 dev_priv->rps.cur_delay,
3635 vlv_gpu_freq(dev_priv->mem_freq, val), val);
3636
3637 if (val == dev_priv->rps.cur_delay)
3638 return;
3639
3640 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
3641
3642 dev_priv->rps.cur_delay = val;
3643
3644 trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv->mem_freq, val));
3645 }
3646
3647 static void gen6_disable_rps_interrupts(struct drm_device *dev)
3648 {
3649 struct drm_i915_private *dev_priv = dev->dev_private;
3650
3651 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3652 I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) & ~GEN6_PM_RPS_EVENTS);
3653 /* Complete PM interrupt masking here doesn't race with the rps work
3654 * item again unmasking PM interrupts because that is using a different
3655 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3656 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3657
3658 spin_lock_irq(&dev_priv->irq_lock);
3659 dev_priv->rps.pm_iir = 0;
3660 spin_unlock_irq(&dev_priv->irq_lock);
3661
3662 I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
3663 }
3664
3665 static void gen6_disable_rps(struct drm_device *dev)
3666 {
3667 struct drm_i915_private *dev_priv = dev->dev_private;
3668
3669 I915_WRITE(GEN6_RC_CONTROL, 0);
3670 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
3671
3672 gen6_disable_rps_interrupts(dev);
3673 }
3674
3675 static void valleyview_disable_rps(struct drm_device *dev)
3676 {
3677 struct drm_i915_private *dev_priv = dev->dev_private;
3678
3679 I915_WRITE(GEN6_RC_CONTROL, 0);
3680
3681 gen6_disable_rps_interrupts(dev);
3682
3683 if (dev_priv->vlv_pctx) {
3684 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
3685 dev_priv->vlv_pctx = NULL;
3686 }
3687 }
3688
3689 static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
3690 {
3691 if (IS_GEN6(dev))
3692 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
3693
3694 if (IS_HASWELL(dev))
3695 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
3696
3697 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
3698 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3699 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3700 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
3701 }
3702
3703 int intel_enable_rc6(const struct drm_device *dev)
3704 {
3705 /* No RC6 before Ironlake */
3706 if (INTEL_INFO(dev)->gen < 5)
3707 return 0;
3708
3709 /* Respect the kernel parameter if it is set */
3710 if (i915_enable_rc6 >= 0)
3711 return i915_enable_rc6;
3712
3713 /* Disable RC6 on Ironlake */
3714 if (INTEL_INFO(dev)->gen == 5)
3715 return 0;
3716
3717 if (IS_HASWELL(dev))
3718 return INTEL_RC6_ENABLE;
3719
3720 /* snb/ivb have more than one rc6 state. */
3721 if (INTEL_INFO(dev)->gen == 6)
3722 return INTEL_RC6_ENABLE;
3723
3724 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
3725 }
3726
3727 static void gen6_enable_rps_interrupts(struct drm_device *dev)
3728 {
3729 struct drm_i915_private *dev_priv = dev->dev_private;
3730 u32 enabled_intrs;
3731
3732 spin_lock_irq(&dev_priv->irq_lock);
3733 WARN_ON(dev_priv->rps.pm_iir);
3734 snb_enable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS);
3735 I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
3736 spin_unlock_irq(&dev_priv->irq_lock);
3737
3738 /* only unmask PM interrupts we need. Mask all others. */
3739 enabled_intrs = GEN6_PM_RPS_EVENTS;
3740
3741 /* IVB and SNB hard hangs on looping batchbuffer
3742 * if GEN6_PM_UP_EI_EXPIRED is masked.
3743 */
3744 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
3745 enabled_intrs |= GEN6_PM_RP_UP_EI_EXPIRED;
3746
3747 I915_WRITE(GEN6_PMINTRMSK, ~enabled_intrs);
3748 }
3749
3750 static void gen6_enable_rps(struct drm_device *dev)
3751 {
3752 struct drm_i915_private *dev_priv = dev->dev_private;
3753 struct intel_ring_buffer *ring;
3754 u32 rp_state_cap;
3755 u32 gt_perf_status;
3756 u32 rc6vids, pcu_mbox, rc6_mask = 0;
3757 u32 gtfifodbg;
3758 int rc6_mode;
3759 int i, ret;
3760
3761 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3762
3763 /* Here begins a magic sequence of register writes to enable
3764 * auto-downclocking.
3765 *
3766 * Perhaps there might be some value in exposing these to
3767 * userspace...
3768 */
3769 I915_WRITE(GEN6_RC_STATE, 0);
3770
3771 /* Clear the DBG now so we don't confuse earlier errors */
3772 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3773 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3774 I915_WRITE(GTFIFODBG, gtfifodbg);
3775 }
3776
3777 gen6_gt_force_wake_get(dev_priv);
3778
3779 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3780 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
3781
3782 /* In units of 50MHz */
3783 dev_priv->rps.hw_max = dev_priv->rps.max_delay = rp_state_cap & 0xff;
3784 dev_priv->rps.min_delay = (rp_state_cap >> 16) & 0xff;
3785 dev_priv->rps.rp1_delay = (rp_state_cap >> 8) & 0xff;
3786 dev_priv->rps.rp0_delay = (rp_state_cap >> 0) & 0xff;
3787 dev_priv->rps.rpe_delay = dev_priv->rps.rp1_delay;
3788 dev_priv->rps.cur_delay = 0;
3789
3790 /* disable the counters and set deterministic thresholds */
3791 I915_WRITE(GEN6_RC_CONTROL, 0);
3792
3793 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
3794 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
3795 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
3796 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3797 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3798
3799 for_each_ring(ring, dev_priv, i)
3800 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3801
3802 I915_WRITE(GEN6_RC_SLEEP, 0);
3803 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
3804 if (INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev))
3805 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
3806 else
3807 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
3808 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
3809 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
3810
3811 /* Check if we are enabling RC6 */
3812 rc6_mode = intel_enable_rc6(dev_priv->dev);
3813 if (rc6_mode & INTEL_RC6_ENABLE)
3814 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
3815
3816 /* We don't use those on Haswell */
3817 if (!IS_HASWELL(dev)) {
3818 if (rc6_mode & INTEL_RC6p_ENABLE)
3819 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
3820
3821 if (rc6_mode & INTEL_RC6pp_ENABLE)
3822 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
3823 }
3824
3825 intel_print_rc6_info(dev, rc6_mask);
3826
3827 I915_WRITE(GEN6_RC_CONTROL,
3828 rc6_mask |
3829 GEN6_RC_CTL_EI_MODE(1) |
3830 GEN6_RC_CTL_HW_ENABLE);
3831
3832 /* Power down if completely idle for over 50ms */
3833 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
3834 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3835
3836 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
3837 if (!ret) {
3838 pcu_mbox = 0;
3839 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
3840 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
3841 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
3842 (dev_priv->rps.max_delay & 0xff) * 50,
3843 (pcu_mbox & 0xff) * 50);
3844 dev_priv->rps.hw_max = pcu_mbox & 0xff;
3845 }
3846 } else {
3847 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
3848 }
3849
3850 dev_priv->rps.power = HIGH_POWER; /* force a reset */
3851 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
3852
3853 gen6_enable_rps_interrupts(dev);
3854
3855 rc6vids = 0;
3856 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
3857 if (IS_GEN6(dev) && ret) {
3858 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
3859 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
3860 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
3861 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
3862 rc6vids &= 0xffff00;
3863 rc6vids |= GEN6_ENCODE_RC6_VID(450);
3864 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
3865 if (ret)
3866 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
3867 }
3868
3869 gen6_gt_force_wake_put(dev_priv);
3870 }
3871
3872 void gen6_update_ring_freq(struct drm_device *dev)
3873 {
3874 struct drm_i915_private *dev_priv = dev->dev_private;
3875 int min_freq = 15;
3876 unsigned int gpu_freq;
3877 unsigned int max_ia_freq, min_ring_freq;
3878 int scaling_factor = 180;
3879 struct cpufreq_policy *policy;
3880
3881 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3882
3883 policy = cpufreq_cpu_get(0);
3884 if (policy) {
3885 max_ia_freq = policy->cpuinfo.max_freq;
3886 cpufreq_cpu_put(policy);
3887 } else {
3888 /*
3889 * Default to measured freq if none found, PCU will ensure we
3890 * don't go over
3891 */
3892 max_ia_freq = tsc_khz;
3893 }
3894
3895 /* Convert from kHz to MHz */
3896 max_ia_freq /= 1000;
3897
3898 min_ring_freq = I915_READ(DCLK) & 0xf;
3899 /* convert DDR frequency from units of 266.6MHz to bandwidth */
3900 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3901
3902 /*
3903 * For each potential GPU frequency, load a ring frequency we'd like
3904 * to use for memory access. We do this by specifying the IA frequency
3905 * the PCU should use as a reference to determine the ring frequency.
3906 */
3907 for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay;
3908 gpu_freq--) {
3909 int diff = dev_priv->rps.max_delay - gpu_freq;
3910 unsigned int ia_freq = 0, ring_freq = 0;
3911
3912 if (IS_HASWELL(dev)) {
3913 ring_freq = mult_frac(gpu_freq, 5, 4);
3914 ring_freq = max(min_ring_freq, ring_freq);
3915 /* leave ia_freq as the default, chosen by cpufreq */
3916 } else {
3917 /* On older processors, there is no separate ring
3918 * clock domain, so in order to boost the bandwidth
3919 * of the ring, we need to upclock the CPU (ia_freq).
3920 *
3921 * For GPU frequencies less than 750MHz,
3922 * just use the lowest ring freq.
3923 */
3924 if (gpu_freq < min_freq)
3925 ia_freq = 800;
3926 else
3927 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
3928 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
3929 }
3930
3931 sandybridge_pcode_write(dev_priv,
3932 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3933 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
3934 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
3935 gpu_freq);
3936 }
3937 }
3938
3939 int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
3940 {
3941 u32 val, rp0;
3942
3943 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
3944
3945 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
3946 /* Clamp to max */
3947 rp0 = min_t(u32, rp0, 0xea);
3948
3949 return rp0;
3950 }
3951
3952 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
3953 {
3954 u32 val, rpe;
3955
3956 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
3957 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
3958 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
3959 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
3960
3961 return rpe;
3962 }
3963
3964 int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
3965 {
3966 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
3967 }
3968
3969 static void valleyview_setup_pctx(struct drm_device *dev)
3970 {
3971 struct drm_i915_private *dev_priv = dev->dev_private;
3972 struct drm_i915_gem_object *pctx;
3973 unsigned long pctx_paddr;
3974 u32 pcbr;
3975 int pctx_size = 24*1024;
3976
3977 pcbr = I915_READ(VLV_PCBR);
3978 if (pcbr) {
3979 /* BIOS set it up already, grab the pre-alloc'd space */
3980 int pcbr_offset;
3981
3982 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
3983 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
3984 pcbr_offset,
3985 I915_GTT_OFFSET_NONE,
3986 pctx_size);
3987 goto out;
3988 }
3989
3990 /*
3991 * From the Gunit register HAS:
3992 * The Gfx driver is expected to program this register and ensure
3993 * proper allocation within Gfx stolen memory. For example, this
3994 * register should be programmed such than the PCBR range does not
3995 * overlap with other ranges, such as the frame buffer, protected
3996 * memory, or any other relevant ranges.
3997 */
3998 pctx = i915_gem_object_create_stolen(dev, pctx_size);
3999 if (!pctx) {
4000 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
4001 return;
4002 }
4003
4004 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
4005 I915_WRITE(VLV_PCBR, pctx_paddr);
4006
4007 out:
4008 dev_priv->vlv_pctx = pctx;
4009 }
4010
4011 static void valleyview_enable_rps(struct drm_device *dev)
4012 {
4013 struct drm_i915_private *dev_priv = dev->dev_private;
4014 struct intel_ring_buffer *ring;
4015 u32 gtfifodbg, val, rc6_mode = 0;
4016 int i;
4017
4018 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4019
4020 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
4021 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4022 gtfifodbg);
4023 I915_WRITE(GTFIFODBG, gtfifodbg);
4024 }
4025
4026 valleyview_setup_pctx(dev);
4027
4028 gen6_gt_force_wake_get(dev_priv);
4029
4030 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
4031 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
4032 I915_WRITE(GEN6_RP_UP_EI, 66000);
4033 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
4034
4035 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4036
4037 I915_WRITE(GEN6_RP_CONTROL,
4038 GEN6_RP_MEDIA_TURBO |
4039 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4040 GEN6_RP_MEDIA_IS_GFX |
4041 GEN6_RP_ENABLE |
4042 GEN6_RP_UP_BUSY_AVG |
4043 GEN6_RP_DOWN_IDLE_CONT);
4044
4045 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
4046 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4047 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4048
4049 for_each_ring(ring, dev_priv, i)
4050 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4051
4052 I915_WRITE(GEN6_RC6_THRESHOLD, 0xc350);
4053
4054 /* allows RC6 residency counter to work */
4055 I915_WRITE(VLV_COUNTER_CONTROL,
4056 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
4057 VLV_MEDIA_RC6_COUNT_EN |
4058 VLV_RENDER_RC6_COUNT_EN));
4059 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4060 rc6_mode = GEN7_RC_CTL_TO_MODE;
4061
4062 intel_print_rc6_info(dev, rc6_mode);
4063
4064 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
4065
4066 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4067 switch ((val >> 6) & 3) {
4068 case 0:
4069 case 1:
4070 dev_priv->mem_freq = 800;
4071 break;
4072 case 2:
4073 dev_priv->mem_freq = 1066;
4074 break;
4075 case 3:
4076 dev_priv->mem_freq = 1333;
4077 break;
4078 }
4079 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
4080
4081 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
4082 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
4083
4084 dev_priv->rps.cur_delay = (val >> 8) & 0xff;
4085 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
4086 vlv_gpu_freq(dev_priv->mem_freq,
4087 dev_priv->rps.cur_delay),
4088 dev_priv->rps.cur_delay);
4089
4090 dev_priv->rps.max_delay = valleyview_rps_max_freq(dev_priv);
4091 dev_priv->rps.hw_max = dev_priv->rps.max_delay;
4092 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
4093 vlv_gpu_freq(dev_priv->mem_freq,
4094 dev_priv->rps.max_delay),
4095 dev_priv->rps.max_delay);
4096
4097 dev_priv->rps.rpe_delay = valleyview_rps_rpe_freq(dev_priv);
4098 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
4099 vlv_gpu_freq(dev_priv->mem_freq,
4100 dev_priv->rps.rpe_delay),
4101 dev_priv->rps.rpe_delay);
4102
4103 dev_priv->rps.min_delay = valleyview_rps_min_freq(dev_priv);
4104 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
4105 vlv_gpu_freq(dev_priv->mem_freq,
4106 dev_priv->rps.min_delay),
4107 dev_priv->rps.min_delay);
4108
4109 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
4110 vlv_gpu_freq(dev_priv->mem_freq,
4111 dev_priv->rps.rpe_delay),
4112 dev_priv->rps.rpe_delay);
4113
4114 valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
4115
4116 gen6_enable_rps_interrupts(dev);
4117
4118 gen6_gt_force_wake_put(dev_priv);
4119 }
4120
4121 void ironlake_teardown_rc6(struct drm_device *dev)
4122 {
4123 struct drm_i915_private *dev_priv = dev->dev_private;
4124
4125 if (dev_priv->ips.renderctx) {
4126 i915_gem_object_unpin(dev_priv->ips.renderctx);
4127 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
4128 dev_priv->ips.renderctx = NULL;
4129 }
4130
4131 if (dev_priv->ips.pwrctx) {
4132 i915_gem_object_unpin(dev_priv->ips.pwrctx);
4133 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
4134 dev_priv->ips.pwrctx = NULL;
4135 }
4136 }
4137
4138 static void ironlake_disable_rc6(struct drm_device *dev)
4139 {
4140 struct drm_i915_private *dev_priv = dev->dev_private;
4141
4142 if (I915_READ(PWRCTXA)) {
4143 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
4144 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
4145 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
4146 50);
4147
4148 I915_WRITE(PWRCTXA, 0);
4149 POSTING_READ(PWRCTXA);
4150
4151 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
4152 POSTING_READ(RSTDBYCTL);
4153 }
4154 }
4155
4156 static int ironlake_setup_rc6(struct drm_device *dev)
4157 {
4158 struct drm_i915_private *dev_priv = dev->dev_private;
4159
4160 if (dev_priv->ips.renderctx == NULL)
4161 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
4162 if (!dev_priv->ips.renderctx)
4163 return -ENOMEM;
4164
4165 if (dev_priv->ips.pwrctx == NULL)
4166 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
4167 if (!dev_priv->ips.pwrctx) {
4168 ironlake_teardown_rc6(dev);
4169 return -ENOMEM;
4170 }
4171
4172 return 0;
4173 }
4174
4175 static void ironlake_enable_rc6(struct drm_device *dev)
4176 {
4177 struct drm_i915_private *dev_priv = dev->dev_private;
4178 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
4179 bool was_interruptible;
4180 int ret;
4181
4182 /* rc6 disabled by default due to repeated reports of hanging during
4183 * boot and resume.
4184 */
4185 if (!intel_enable_rc6(dev))
4186 return;
4187
4188 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4189
4190 ret = ironlake_setup_rc6(dev);
4191 if (ret)
4192 return;
4193
4194 was_interruptible = dev_priv->mm.interruptible;
4195 dev_priv->mm.interruptible = false;
4196
4197 /*
4198 * GPU can automatically power down the render unit if given a page
4199 * to save state.
4200 */
4201 ret = intel_ring_begin(ring, 6);
4202 if (ret) {
4203 ironlake_teardown_rc6(dev);
4204 dev_priv->mm.interruptible = was_interruptible;
4205 return;
4206 }
4207
4208 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
4209 intel_ring_emit(ring, MI_SET_CONTEXT);
4210 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) |
4211 MI_MM_SPACE_GTT |
4212 MI_SAVE_EXT_STATE_EN |
4213 MI_RESTORE_EXT_STATE_EN |
4214 MI_RESTORE_INHIBIT);
4215 intel_ring_emit(ring, MI_SUSPEND_FLUSH);
4216 intel_ring_emit(ring, MI_NOOP);
4217 intel_ring_emit(ring, MI_FLUSH);
4218 intel_ring_advance(ring);
4219
4220 /*
4221 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
4222 * does an implicit flush, combined with MI_FLUSH above, it should be
4223 * safe to assume that renderctx is valid
4224 */
4225 ret = intel_ring_idle(ring);
4226 dev_priv->mm.interruptible = was_interruptible;
4227 if (ret) {
4228 DRM_ERROR("failed to enable ironlake power savings\n");
4229 ironlake_teardown_rc6(dev);
4230 return;
4231 }
4232
4233 I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN);
4234 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
4235
4236 intel_print_rc6_info(dev, INTEL_RC6_ENABLE);
4237 }
4238
4239 static unsigned long intel_pxfreq(u32 vidfreq)
4240 {
4241 unsigned long freq;
4242 int div = (vidfreq & 0x3f0000) >> 16;
4243 int post = (vidfreq & 0x3000) >> 12;
4244 int pre = (vidfreq & 0x7);
4245
4246 if (!pre)
4247 return 0;
4248
4249 freq = ((div * 133333) / ((1<<post) * pre));
4250
4251 return freq;
4252 }
4253
4254 static const struct cparams {
4255 u16 i;
4256 u16 t;
4257 u16 m;
4258 u16 c;
4259 } cparams[] = {
4260 { 1, 1333, 301, 28664 },
4261 { 1, 1066, 294, 24460 },
4262 { 1, 800, 294, 25192 },
4263 { 0, 1333, 276, 27605 },
4264 { 0, 1066, 276, 27605 },
4265 { 0, 800, 231, 23784 },
4266 };
4267
4268 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
4269 {
4270 u64 total_count, diff, ret;
4271 u32 count1, count2, count3, m = 0, c = 0;
4272 unsigned long now = jiffies_to_msecs(jiffies), diff1;
4273 int i;
4274
4275 assert_spin_locked(&mchdev_lock);
4276
4277 diff1 = now - dev_priv->ips.last_time1;
4278
4279 /* Prevent division-by-zero if we are asking too fast.
4280 * Also, we don't get interesting results if we are polling
4281 * faster than once in 10ms, so just return the saved value
4282 * in such cases.
4283 */
4284 if (diff1 <= 10)
4285 return dev_priv->ips.chipset_power;
4286
4287 count1 = I915_READ(DMIEC);
4288 count2 = I915_READ(DDREC);
4289 count3 = I915_READ(CSIEC);
4290
4291 total_count = count1 + count2 + count3;
4292
4293 /* FIXME: handle per-counter overflow */
4294 if (total_count < dev_priv->ips.last_count1) {
4295 diff = ~0UL - dev_priv->ips.last_count1;
4296 diff += total_count;
4297 } else {
4298 diff = total_count - dev_priv->ips.last_count1;
4299 }
4300
4301 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
4302 if (cparams[i].i == dev_priv->ips.c_m &&
4303 cparams[i].t == dev_priv->ips.r_t) {
4304 m = cparams[i].m;
4305 c = cparams[i].c;
4306 break;
4307 }
4308 }
4309
4310 diff = div_u64(diff, diff1);
4311 ret = ((m * diff) + c);
4312 ret = div_u64(ret, 10);
4313
4314 dev_priv->ips.last_count1 = total_count;
4315 dev_priv->ips.last_time1 = now;
4316
4317 dev_priv->ips.chipset_power = ret;
4318
4319 return ret;
4320 }
4321
4322 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
4323 {
4324 unsigned long val;
4325
4326 if (dev_priv->info->gen != 5)
4327 return 0;
4328
4329 spin_lock_irq(&mchdev_lock);
4330
4331 val = __i915_chipset_val(dev_priv);
4332
4333 spin_unlock_irq(&mchdev_lock);
4334
4335 return val;
4336 }
4337
4338 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
4339 {
4340 unsigned long m, x, b;
4341 u32 tsfs;
4342
4343 tsfs = I915_READ(TSFS);
4344
4345 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
4346 x = I915_READ8(TR1);
4347
4348 b = tsfs & TSFS_INTR_MASK;
4349
4350 return ((m * x) / 127) - b;
4351 }
4352
4353 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
4354 {
4355 static const struct v_table {
4356 u16 vd; /* in .1 mil */
4357 u16 vm; /* in .1 mil */
4358 } v_table[] = {
4359 { 0, 0, },
4360 { 375, 0, },
4361 { 500, 0, },
4362 { 625, 0, },
4363 { 750, 0, },
4364 { 875, 0, },
4365 { 1000, 0, },
4366 { 1125, 0, },
4367 { 4125, 3000, },
4368 { 4125, 3000, },
4369 { 4125, 3000, },
4370 { 4125, 3000, },
4371 { 4125, 3000, },
4372 { 4125, 3000, },
4373 { 4125, 3000, },
4374 { 4125, 3000, },
4375 { 4125, 3000, },
4376 { 4125, 3000, },
4377 { 4125, 3000, },
4378 { 4125, 3000, },
4379 { 4125, 3000, },
4380 { 4125, 3000, },
4381 { 4125, 3000, },
4382 { 4125, 3000, },
4383 { 4125, 3000, },
4384 { 4125, 3000, },
4385 { 4125, 3000, },
4386 { 4125, 3000, },
4387 { 4125, 3000, },
4388 { 4125, 3000, },
4389 { 4125, 3000, },
4390 { 4125, 3000, },
4391 { 4250, 3125, },
4392 { 4375, 3250, },
4393 { 4500, 3375, },
4394 { 4625, 3500, },
4395 { 4750, 3625, },
4396 { 4875, 3750, },
4397 { 5000, 3875, },
4398 { 5125, 4000, },
4399 { 5250, 4125, },
4400 { 5375, 4250, },
4401 { 5500, 4375, },
4402 { 5625, 4500, },
4403 { 5750, 4625, },
4404 { 5875, 4750, },
4405 { 6000, 4875, },
4406 { 6125, 5000, },
4407 { 6250, 5125, },
4408 { 6375, 5250, },
4409 { 6500, 5375, },
4410 { 6625, 5500, },
4411 { 6750, 5625, },
4412 { 6875, 5750, },
4413 { 7000, 5875, },
4414 { 7125, 6000, },
4415 { 7250, 6125, },
4416 { 7375, 6250, },
4417 { 7500, 6375, },
4418 { 7625, 6500, },
4419 { 7750, 6625, },
4420 { 7875, 6750, },
4421 { 8000, 6875, },
4422 { 8125, 7000, },
4423 { 8250, 7125, },
4424 { 8375, 7250, },
4425 { 8500, 7375, },
4426 { 8625, 7500, },
4427 { 8750, 7625, },
4428 { 8875, 7750, },
4429 { 9000, 7875, },
4430 { 9125, 8000, },
4431 { 9250, 8125, },
4432 { 9375, 8250, },
4433 { 9500, 8375, },
4434 { 9625, 8500, },
4435 { 9750, 8625, },
4436 { 9875, 8750, },
4437 { 10000, 8875, },
4438 { 10125, 9000, },
4439 { 10250, 9125, },
4440 { 10375, 9250, },
4441 { 10500, 9375, },
4442 { 10625, 9500, },
4443 { 10750, 9625, },
4444 { 10875, 9750, },
4445 { 11000, 9875, },
4446 { 11125, 10000, },
4447 { 11250, 10125, },
4448 { 11375, 10250, },
4449 { 11500, 10375, },
4450 { 11625, 10500, },
4451 { 11750, 10625, },
4452 { 11875, 10750, },
4453 { 12000, 10875, },
4454 { 12125, 11000, },
4455 { 12250, 11125, },
4456 { 12375, 11250, },
4457 { 12500, 11375, },
4458 { 12625, 11500, },
4459 { 12750, 11625, },
4460 { 12875, 11750, },
4461 { 13000, 11875, },
4462 { 13125, 12000, },
4463 { 13250, 12125, },
4464 { 13375, 12250, },
4465 { 13500, 12375, },
4466 { 13625, 12500, },
4467 { 13750, 12625, },
4468 { 13875, 12750, },
4469 { 14000, 12875, },
4470 { 14125, 13000, },
4471 { 14250, 13125, },
4472 { 14375, 13250, },
4473 { 14500, 13375, },
4474 { 14625, 13500, },
4475 { 14750, 13625, },
4476 { 14875, 13750, },
4477 { 15000, 13875, },
4478 { 15125, 14000, },
4479 { 15250, 14125, },
4480 { 15375, 14250, },
4481 { 15500, 14375, },
4482 { 15625, 14500, },
4483 { 15750, 14625, },
4484 { 15875, 14750, },
4485 { 16000, 14875, },
4486 { 16125, 15000, },
4487 };
4488 if (dev_priv->info->is_mobile)
4489 return v_table[pxvid].vm;
4490 else
4491 return v_table[pxvid].vd;
4492 }
4493
4494 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
4495 {
4496 struct timespec now, diff1;
4497 u64 diff;
4498 unsigned long diffms;
4499 u32 count;
4500
4501 assert_spin_locked(&mchdev_lock);
4502
4503 getrawmonotonic(&now);
4504 diff1 = timespec_sub(now, dev_priv->ips.last_time2);
4505
4506 /* Don't divide by 0 */
4507 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
4508 if (!diffms)
4509 return;
4510
4511 count = I915_READ(GFXEC);
4512
4513 if (count < dev_priv->ips.last_count2) {
4514 diff = ~0UL - dev_priv->ips.last_count2;
4515 diff += count;
4516 } else {
4517 diff = count - dev_priv->ips.last_count2;
4518 }
4519
4520 dev_priv->ips.last_count2 = count;
4521 dev_priv->ips.last_time2 = now;
4522
4523 /* More magic constants... */
4524 diff = diff * 1181;
4525 diff = div_u64(diff, diffms * 10);
4526 dev_priv->ips.gfx_power = diff;
4527 }
4528
4529 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
4530 {
4531 if (dev_priv->info->gen != 5)
4532 return;
4533
4534 spin_lock_irq(&mchdev_lock);
4535
4536 __i915_update_gfx_val(dev_priv);
4537
4538 spin_unlock_irq(&mchdev_lock);
4539 }
4540
4541 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
4542 {
4543 unsigned long t, corr, state1, corr2, state2;
4544 u32 pxvid, ext_v;
4545
4546 assert_spin_locked(&mchdev_lock);
4547
4548 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4));
4549 pxvid = (pxvid >> 24) & 0x7f;
4550 ext_v = pvid_to_extvid(dev_priv, pxvid);
4551
4552 state1 = ext_v;
4553
4554 t = i915_mch_val(dev_priv);
4555
4556 /* Revel in the empirically derived constants */
4557
4558 /* Correction factor in 1/100000 units */
4559 if (t > 80)
4560 corr = ((t * 2349) + 135940);
4561 else if (t >= 50)
4562 corr = ((t * 964) + 29317);
4563 else /* < 50 */
4564 corr = ((t * 301) + 1004);
4565
4566 corr = corr * ((150142 * state1) / 10000 - 78642);
4567 corr /= 100000;
4568 corr2 = (corr * dev_priv->ips.corr);
4569
4570 state2 = (corr2 * state1) / 10000;
4571 state2 /= 100; /* convert to mW */
4572
4573 __i915_update_gfx_val(dev_priv);
4574
4575 return dev_priv->ips.gfx_power + state2;
4576 }
4577
4578 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
4579 {
4580 unsigned long val;
4581
4582 if (dev_priv->info->gen != 5)
4583 return 0;
4584
4585 spin_lock_irq(&mchdev_lock);
4586
4587 val = __i915_gfx_val(dev_priv);
4588
4589 spin_unlock_irq(&mchdev_lock);
4590
4591 return val;
4592 }
4593
4594 /**
4595 * i915_read_mch_val - return value for IPS use
4596 *
4597 * Calculate and return a value for the IPS driver to use when deciding whether
4598 * we have thermal and power headroom to increase CPU or GPU power budget.
4599 */
4600 unsigned long i915_read_mch_val(void)
4601 {
4602 struct drm_i915_private *dev_priv;
4603 unsigned long chipset_val, graphics_val, ret = 0;
4604
4605 spin_lock_irq(&mchdev_lock);
4606 if (!i915_mch_dev)
4607 goto out_unlock;
4608 dev_priv = i915_mch_dev;
4609
4610 chipset_val = __i915_chipset_val(dev_priv);
4611 graphics_val = __i915_gfx_val(dev_priv);
4612
4613 ret = chipset_val + graphics_val;
4614
4615 out_unlock:
4616 spin_unlock_irq(&mchdev_lock);
4617
4618 return ret;
4619 }
4620 EXPORT_SYMBOL_GPL(i915_read_mch_val);
4621
4622 /**
4623 * i915_gpu_raise - raise GPU frequency limit
4624 *
4625 * Raise the limit; IPS indicates we have thermal headroom.
4626 */
4627 bool i915_gpu_raise(void)
4628 {
4629 struct drm_i915_private *dev_priv;
4630 bool ret = true;
4631
4632 spin_lock_irq(&mchdev_lock);
4633 if (!i915_mch_dev) {
4634 ret = false;
4635 goto out_unlock;
4636 }
4637 dev_priv = i915_mch_dev;
4638
4639 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
4640 dev_priv->ips.max_delay--;
4641
4642 out_unlock:
4643 spin_unlock_irq(&mchdev_lock);
4644
4645 return ret;
4646 }
4647 EXPORT_SYMBOL_GPL(i915_gpu_raise);
4648
4649 /**
4650 * i915_gpu_lower - lower GPU frequency limit
4651 *
4652 * IPS indicates we're close to a thermal limit, so throttle back the GPU
4653 * frequency maximum.
4654 */
4655 bool i915_gpu_lower(void)
4656 {
4657 struct drm_i915_private *dev_priv;
4658 bool ret = true;
4659
4660 spin_lock_irq(&mchdev_lock);
4661 if (!i915_mch_dev) {
4662 ret = false;
4663 goto out_unlock;
4664 }
4665 dev_priv = i915_mch_dev;
4666
4667 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
4668 dev_priv->ips.max_delay++;
4669
4670 out_unlock:
4671 spin_unlock_irq(&mchdev_lock);
4672
4673 return ret;
4674 }
4675 EXPORT_SYMBOL_GPL(i915_gpu_lower);
4676
4677 /**
4678 * i915_gpu_busy - indicate GPU business to IPS
4679 *
4680 * Tell the IPS driver whether or not the GPU is busy.
4681 */
4682 bool i915_gpu_busy(void)
4683 {
4684 struct drm_i915_private *dev_priv;
4685 struct intel_ring_buffer *ring;
4686 bool ret = false;
4687 int i;
4688
4689 spin_lock_irq(&mchdev_lock);
4690 if (!i915_mch_dev)
4691 goto out_unlock;
4692 dev_priv = i915_mch_dev;
4693
4694 for_each_ring(ring, dev_priv, i)
4695 ret |= !list_empty(&ring->request_list);
4696
4697 out_unlock:
4698 spin_unlock_irq(&mchdev_lock);
4699
4700 return ret;
4701 }
4702 EXPORT_SYMBOL_GPL(i915_gpu_busy);
4703
4704 /**
4705 * i915_gpu_turbo_disable - disable graphics turbo
4706 *
4707 * Disable graphics turbo by resetting the max frequency and setting the
4708 * current frequency to the default.
4709 */
4710 bool i915_gpu_turbo_disable(void)
4711 {
4712 struct drm_i915_private *dev_priv;
4713 bool ret = true;
4714
4715 spin_lock_irq(&mchdev_lock);
4716 if (!i915_mch_dev) {
4717 ret = false;
4718 goto out_unlock;
4719 }
4720 dev_priv = i915_mch_dev;
4721
4722 dev_priv->ips.max_delay = dev_priv->ips.fstart;
4723
4724 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
4725 ret = false;
4726
4727 out_unlock:
4728 spin_unlock_irq(&mchdev_lock);
4729
4730 return ret;
4731 }
4732 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
4733
4734 /**
4735 * Tells the intel_ips driver that the i915 driver is now loaded, if
4736 * IPS got loaded first.
4737 *
4738 * This awkward dance is so that neither module has to depend on the
4739 * other in order for IPS to do the appropriate communication of
4740 * GPU turbo limits to i915.
4741 */
4742 static void
4743 ips_ping_for_i915_load(void)
4744 {
4745 void (*link)(void);
4746
4747 link = symbol_get(ips_link_to_i915_driver);
4748 if (link) {
4749 link();
4750 symbol_put(ips_link_to_i915_driver);
4751 }
4752 }
4753
4754 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
4755 {
4756 /* We only register the i915 ips part with intel-ips once everything is
4757 * set up, to avoid intel-ips sneaking in and reading bogus values. */
4758 spin_lock_irq(&mchdev_lock);
4759 i915_mch_dev = dev_priv;
4760 spin_unlock_irq(&mchdev_lock);
4761
4762 ips_ping_for_i915_load();
4763 }
4764
4765 void intel_gpu_ips_teardown(void)
4766 {
4767 spin_lock_irq(&mchdev_lock);
4768 i915_mch_dev = NULL;
4769 spin_unlock_irq(&mchdev_lock);
4770 }
4771 static void intel_init_emon(struct drm_device *dev)
4772 {
4773 struct drm_i915_private *dev_priv = dev->dev_private;
4774 u32 lcfuse;
4775 u8 pxw[16];
4776 int i;
4777
4778 /* Disable to program */
4779 I915_WRITE(ECR, 0);
4780 POSTING_READ(ECR);
4781
4782 /* Program energy weights for various events */
4783 I915_WRITE(SDEW, 0x15040d00);
4784 I915_WRITE(CSIEW0, 0x007f0000);
4785 I915_WRITE(CSIEW1, 0x1e220004);
4786 I915_WRITE(CSIEW2, 0x04000004);
4787
4788 for (i = 0; i < 5; i++)
4789 I915_WRITE(PEW + (i * 4), 0);
4790 for (i = 0; i < 3; i++)
4791 I915_WRITE(DEW + (i * 4), 0);
4792
4793 /* Program P-state weights to account for frequency power adjustment */
4794 for (i = 0; i < 16; i++) {
4795 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
4796 unsigned long freq = intel_pxfreq(pxvidfreq);
4797 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
4798 PXVFREQ_PX_SHIFT;
4799 unsigned long val;
4800
4801 val = vid * vid;
4802 val *= (freq / 1000);
4803 val *= 255;
4804 val /= (127*127*900);
4805 if (val > 0xff)
4806 DRM_ERROR("bad pxval: %ld\n", val);
4807 pxw[i] = val;
4808 }
4809 /* Render standby states get 0 weight */
4810 pxw[14] = 0;
4811 pxw[15] = 0;
4812
4813 for (i = 0; i < 4; i++) {
4814 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
4815 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
4816 I915_WRITE(PXW + (i * 4), val);
4817 }
4818
4819 /* Adjust magic regs to magic values (more experimental results) */
4820 I915_WRITE(OGW0, 0);
4821 I915_WRITE(OGW1, 0);
4822 I915_WRITE(EG0, 0x00007f00);
4823 I915_WRITE(EG1, 0x0000000e);
4824 I915_WRITE(EG2, 0x000e0000);
4825 I915_WRITE(EG3, 0x68000300);
4826 I915_WRITE(EG4, 0x42000000);
4827 I915_WRITE(EG5, 0x00140031);
4828 I915_WRITE(EG6, 0);
4829 I915_WRITE(EG7, 0);
4830
4831 for (i = 0; i < 8; i++)
4832 I915_WRITE(PXWL + (i * 4), 0);
4833
4834 /* Enable PMON + select events */
4835 I915_WRITE(ECR, 0x80000019);
4836
4837 lcfuse = I915_READ(LCFUSE02);
4838
4839 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
4840 }
4841
4842 void intel_disable_gt_powersave(struct drm_device *dev)
4843 {
4844 struct drm_i915_private *dev_priv = dev->dev_private;
4845
4846 /* Interrupts should be disabled already to avoid re-arming. */
4847 WARN_ON(dev->irq_enabled);
4848
4849 if (IS_IRONLAKE_M(dev)) {
4850 ironlake_disable_drps(dev);
4851 ironlake_disable_rc6(dev);
4852 } else if (INTEL_INFO(dev)->gen >= 6) {
4853 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
4854 cancel_work_sync(&dev_priv->rps.work);
4855 mutex_lock(&dev_priv->rps.hw_lock);
4856 if (IS_VALLEYVIEW(dev))
4857 valleyview_disable_rps(dev);
4858 else
4859 gen6_disable_rps(dev);
4860 dev_priv->rps.enabled = false;
4861 mutex_unlock(&dev_priv->rps.hw_lock);
4862 }
4863 }
4864
4865 static void intel_gen6_powersave_work(struct work_struct *work)
4866 {
4867 struct drm_i915_private *dev_priv =
4868 container_of(work, struct drm_i915_private,
4869 rps.delayed_resume_work.work);
4870 struct drm_device *dev = dev_priv->dev;
4871
4872 mutex_lock(&dev_priv->rps.hw_lock);
4873
4874 if (IS_VALLEYVIEW(dev)) {
4875 valleyview_enable_rps(dev);
4876 } else {
4877 gen6_enable_rps(dev);
4878 gen6_update_ring_freq(dev);
4879 }
4880 dev_priv->rps.enabled = true;
4881 mutex_unlock(&dev_priv->rps.hw_lock);
4882 }
4883
4884 void intel_enable_gt_powersave(struct drm_device *dev)
4885 {
4886 struct drm_i915_private *dev_priv = dev->dev_private;
4887
4888 if (IS_IRONLAKE_M(dev)) {
4889 ironlake_enable_drps(dev);
4890 ironlake_enable_rc6(dev);
4891 intel_init_emon(dev);
4892 } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
4893 /*
4894 * PCU communication is slow and this doesn't need to be
4895 * done at any specific time, so do this out of our fast path
4896 * to make resume and init faster.
4897 */
4898 schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
4899 round_jiffies_up_relative(HZ));
4900 }
4901 }
4902
4903 static void ibx_init_clock_gating(struct drm_device *dev)
4904 {
4905 struct drm_i915_private *dev_priv = dev->dev_private;
4906
4907 /*
4908 * On Ibex Peak and Cougar Point, we need to disable clock
4909 * gating for the panel power sequencer or it will fail to
4910 * start up when no ports are active.
4911 */
4912 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
4913 }
4914
4915 static void g4x_disable_trickle_feed(struct drm_device *dev)
4916 {
4917 struct drm_i915_private *dev_priv = dev->dev_private;
4918 int pipe;
4919
4920 for_each_pipe(pipe) {
4921 I915_WRITE(DSPCNTR(pipe),
4922 I915_READ(DSPCNTR(pipe)) |
4923 DISPPLANE_TRICKLE_FEED_DISABLE);
4924 intel_flush_primary_plane(dev_priv, pipe);
4925 }
4926 }
4927
4928 static void ironlake_init_clock_gating(struct drm_device *dev)
4929 {
4930 struct drm_i915_private *dev_priv = dev->dev_private;
4931 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
4932
4933 /*
4934 * Required for FBC
4935 * WaFbcDisableDpfcClockGating:ilk
4936 */
4937 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
4938 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
4939 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
4940
4941 I915_WRITE(PCH_3DCGDIS0,
4942 MARIUNIT_CLOCK_GATE_DISABLE |
4943 SVSMUNIT_CLOCK_GATE_DISABLE);
4944 I915_WRITE(PCH_3DCGDIS1,
4945 VFMUNIT_CLOCK_GATE_DISABLE);
4946
4947 /*
4948 * According to the spec the following bits should be set in
4949 * order to enable memory self-refresh
4950 * The bit 22/21 of 0x42004
4951 * The bit 5 of 0x42020
4952 * The bit 15 of 0x45000
4953 */
4954 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4955 (I915_READ(ILK_DISPLAY_CHICKEN2) |
4956 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4957 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
4958 I915_WRITE(DISP_ARB_CTL,
4959 (I915_READ(DISP_ARB_CTL) |
4960 DISP_FBC_WM_DIS));
4961 I915_WRITE(WM3_LP_ILK, 0);
4962 I915_WRITE(WM2_LP_ILK, 0);
4963 I915_WRITE(WM1_LP_ILK, 0);
4964
4965 /*
4966 * Based on the document from hardware guys the following bits
4967 * should be set unconditionally in order to enable FBC.
4968 * The bit 22 of 0x42000
4969 * The bit 22 of 0x42004
4970 * The bit 7,8,9 of 0x42020.
4971 */
4972 if (IS_IRONLAKE_M(dev)) {
4973 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
4974 I915_WRITE(ILK_DISPLAY_CHICKEN1,
4975 I915_READ(ILK_DISPLAY_CHICKEN1) |
4976 ILK_FBCQ_DIS);
4977 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4978 I915_READ(ILK_DISPLAY_CHICKEN2) |
4979 ILK_DPARB_GATE);
4980 }
4981
4982 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
4983
4984 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4985 I915_READ(ILK_DISPLAY_CHICKEN2) |
4986 ILK_ELPIN_409_SELECT);
4987 I915_WRITE(_3D_CHICKEN2,
4988 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
4989 _3D_CHICKEN2_WM_READ_PIPELINED);
4990
4991 /* WaDisableRenderCachePipelinedFlush:ilk */
4992 I915_WRITE(CACHE_MODE_0,
4993 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
4994
4995 g4x_disable_trickle_feed(dev);
4996
4997 ibx_init_clock_gating(dev);
4998 }
4999
5000 static void cpt_init_clock_gating(struct drm_device *dev)
5001 {
5002 struct drm_i915_private *dev_priv = dev->dev_private;
5003 int pipe;
5004 uint32_t val;
5005
5006 /*
5007 * On Ibex Peak and Cougar Point, we need to disable clock
5008 * gating for the panel power sequencer or it will fail to
5009 * start up when no ports are active.
5010 */
5011 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
5012 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
5013 PCH_CPUNIT_CLOCK_GATE_DISABLE);
5014 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
5015 DPLS_EDP_PPS_FIX_DIS);
5016 /* The below fixes the weird display corruption, a few pixels shifted
5017 * downward, on (only) LVDS of some HP laptops with IVY.
5018 */
5019 for_each_pipe(pipe) {
5020 val = I915_READ(TRANS_CHICKEN2(pipe));
5021 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
5022 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
5023 if (dev_priv->vbt.fdi_rx_polarity_inverted)
5024 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
5025 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
5026 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
5027 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
5028 I915_WRITE(TRANS_CHICKEN2(pipe), val);
5029 }
5030 /* WADP0ClockGatingDisable */
5031 for_each_pipe(pipe) {
5032 I915_WRITE(TRANS_CHICKEN1(pipe),
5033 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
5034 }
5035 }
5036
5037 static void gen6_check_mch_setup(struct drm_device *dev)
5038 {
5039 struct drm_i915_private *dev_priv = dev->dev_private;
5040 uint32_t tmp;
5041
5042 tmp = I915_READ(MCH_SSKPD);
5043 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) {
5044 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp);
5045 DRM_INFO("This can cause pipe underruns and display issues.\n");
5046 DRM_INFO("Please upgrade your BIOS to fix this.\n");
5047 }
5048 }
5049
5050 static void gen6_init_clock_gating(struct drm_device *dev)
5051 {
5052 struct drm_i915_private *dev_priv = dev->dev_private;
5053 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
5054
5055 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
5056
5057 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5058 I915_READ(ILK_DISPLAY_CHICKEN2) |
5059 ILK_ELPIN_409_SELECT);
5060
5061 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
5062 I915_WRITE(_3D_CHICKEN,
5063 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
5064
5065 /* WaSetupGtModeTdRowDispatch:snb */
5066 if (IS_SNB_GT1(dev))
5067 I915_WRITE(GEN6_GT_MODE,
5068 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
5069
5070 I915_WRITE(WM3_LP_ILK, 0);
5071 I915_WRITE(WM2_LP_ILK, 0);
5072 I915_WRITE(WM1_LP_ILK, 0);
5073
5074 I915_WRITE(CACHE_MODE_0,
5075 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
5076
5077 I915_WRITE(GEN6_UCGCTL1,
5078 I915_READ(GEN6_UCGCTL1) |
5079 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
5080 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
5081
5082 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5083 * gating disable must be set. Failure to set it results in
5084 * flickering pixels due to Z write ordering failures after
5085 * some amount of runtime in the Mesa "fire" demo, and Unigine
5086 * Sanctuary and Tropics, and apparently anything else with
5087 * alpha test or pixel discard.
5088 *
5089 * According to the spec, bit 11 (RCCUNIT) must also be set,
5090 * but we didn't debug actual testcases to find it out.
5091 *
5092 * Also apply WaDisableVDSUnitClockGating:snb and
5093 * WaDisableRCPBUnitClockGating:snb.
5094 */
5095 I915_WRITE(GEN6_UCGCTL2,
5096 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
5097 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
5098 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5099
5100 /* Bspec says we need to always set all mask bits. */
5101 I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) |
5102 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL);
5103
5104 /*
5105 * According to the spec the following bits should be
5106 * set in order to enable memory self-refresh and fbc:
5107 * The bit21 and bit22 of 0x42000
5108 * The bit21 and bit22 of 0x42004
5109 * The bit5 and bit7 of 0x42020
5110 * The bit14 of 0x70180
5111 * The bit14 of 0x71180
5112 *
5113 * WaFbcAsynchFlipDisableFbcQueue:snb
5114 */
5115 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5116 I915_READ(ILK_DISPLAY_CHICKEN1) |
5117 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
5118 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5119 I915_READ(ILK_DISPLAY_CHICKEN2) |
5120 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
5121 I915_WRITE(ILK_DSPCLK_GATE_D,
5122 I915_READ(ILK_DSPCLK_GATE_D) |
5123 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
5124 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
5125
5126 g4x_disable_trickle_feed(dev);
5127
5128 /* The default value should be 0x200 according to docs, but the two
5129 * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
5130 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff));
5131 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
5132
5133 cpt_init_clock_gating(dev);
5134
5135 gen6_check_mch_setup(dev);
5136 }
5137
5138 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
5139 {
5140 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
5141
5142 reg &= ~GEN7_FF_SCHED_MASK;
5143 reg |= GEN7_FF_TS_SCHED_HW;
5144 reg |= GEN7_FF_VS_SCHED_HW;
5145 reg |= GEN7_FF_DS_SCHED_HW;
5146
5147 if (IS_HASWELL(dev_priv->dev))
5148 reg &= ~GEN7_FF_VS_REF_CNT_FFME;
5149
5150 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
5151 }
5152
5153 static void lpt_init_clock_gating(struct drm_device *dev)
5154 {
5155 struct drm_i915_private *dev_priv = dev->dev_private;
5156
5157 /*
5158 * TODO: this bit should only be enabled when really needed, then
5159 * disabled when not needed anymore in order to save power.
5160 */
5161 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
5162 I915_WRITE(SOUTH_DSPCLK_GATE_D,
5163 I915_READ(SOUTH_DSPCLK_GATE_D) |
5164 PCH_LP_PARTITION_LEVEL_DISABLE);
5165
5166 /* WADPOClockGatingDisable:hsw */
5167 I915_WRITE(_TRANSA_CHICKEN1,
5168 I915_READ(_TRANSA_CHICKEN1) |
5169 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
5170 }
5171
5172 static void lpt_suspend_hw(struct drm_device *dev)
5173 {
5174 struct drm_i915_private *dev_priv = dev->dev_private;
5175
5176 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
5177 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
5178
5179 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
5180 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
5181 }
5182 }
5183
5184 static void gen8_init_clock_gating(struct drm_device *dev)
5185 {
5186 struct drm_i915_private *dev_priv = dev->dev_private;
5187
5188 I915_WRITE(WM3_LP_ILK, 0);
5189 I915_WRITE(WM2_LP_ILK, 0);
5190 I915_WRITE(WM1_LP_ILK, 0);
5191 }
5192
5193 static void haswell_init_clock_gating(struct drm_device *dev)
5194 {
5195 struct drm_i915_private *dev_priv = dev->dev_private;
5196
5197 I915_WRITE(WM3_LP_ILK, 0);
5198 I915_WRITE(WM2_LP_ILK, 0);
5199 I915_WRITE(WM1_LP_ILK, 0);
5200
5201 /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5202 * This implements the WaDisableRCZUnitClockGating:hsw workaround.
5203 */
5204 I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
5205
5206 /* Apply the WaDisableRHWOOptimizationForRenderHang:hsw workaround. */
5207 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5208 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5209
5210 /* WaApplyL3ControlAndL3ChickenMode:hsw */
5211 I915_WRITE(GEN7_L3CNTLREG1,
5212 GEN7_WA_FOR_GEN7_L3_CONTROL);
5213 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
5214 GEN7_WA_L3_CHICKEN_MODE);
5215
5216 /* L3 caching of data atomics doesn't work -- disable it. */
5217 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
5218 I915_WRITE(HSW_ROW_CHICKEN3,
5219 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
5220
5221 /* This is required by WaCatErrorRejectionIssue:hsw */
5222 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5223 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5224 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5225
5226 /* WaVSRefCountFullforceMissDisable:hsw */
5227 gen7_setup_fixed_func_scheduler(dev_priv);
5228
5229 /* WaDisable4x2SubspanOptimization:hsw */
5230 I915_WRITE(CACHE_MODE_1,
5231 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5232
5233 /* WaSwitchSolVfFArbitrationPriority:hsw */
5234 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
5235
5236 /* WaRsPkgCStateDisplayPMReq:hsw */
5237 I915_WRITE(CHICKEN_PAR1_1,
5238 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
5239
5240 lpt_init_clock_gating(dev);
5241 }
5242
5243 static void ivybridge_init_clock_gating(struct drm_device *dev)
5244 {
5245 struct drm_i915_private *dev_priv = dev->dev_private;
5246 uint32_t snpcr;
5247
5248 I915_WRITE(WM3_LP_ILK, 0);
5249 I915_WRITE(WM2_LP_ILK, 0);
5250 I915_WRITE(WM1_LP_ILK, 0);
5251
5252 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
5253
5254 /* WaDisableEarlyCull:ivb */
5255 I915_WRITE(_3D_CHICKEN3,
5256 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5257
5258 /* WaDisableBackToBackFlipFix:ivb */
5259 I915_WRITE(IVB_CHICKEN3,
5260 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5261 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5262
5263 /* WaDisablePSDDualDispatchEnable:ivb */
5264 if (IS_IVB_GT1(dev))
5265 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5266 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5267 else
5268 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
5269 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5270
5271 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
5272 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5273 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5274
5275 /* WaApplyL3ControlAndL3ChickenMode:ivb */
5276 I915_WRITE(GEN7_L3CNTLREG1,
5277 GEN7_WA_FOR_GEN7_L3_CONTROL);
5278 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
5279 GEN7_WA_L3_CHICKEN_MODE);
5280 if (IS_IVB_GT1(dev))
5281 I915_WRITE(GEN7_ROW_CHICKEN2,
5282 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5283 else
5284 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
5285 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5286
5287
5288 /* WaForceL3Serialization:ivb */
5289 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5290 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5291
5292 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5293 * gating disable must be set. Failure to set it results in
5294 * flickering pixels due to Z write ordering failures after
5295 * some amount of runtime in the Mesa "fire" demo, and Unigine
5296 * Sanctuary and Tropics, and apparently anything else with
5297 * alpha test or pixel discard.
5298 *
5299 * According to the spec, bit 11 (RCCUNIT) must also be set,
5300 * but we didn't debug actual testcases to find it out.
5301 *
5302 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5303 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
5304 */
5305 I915_WRITE(GEN6_UCGCTL2,
5306 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
5307 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5308
5309 /* This is required by WaCatErrorRejectionIssue:ivb */
5310 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5311 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5312 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5313
5314 g4x_disable_trickle_feed(dev);
5315
5316 /* WaVSRefCountFullforceMissDisable:ivb */
5317 gen7_setup_fixed_func_scheduler(dev_priv);
5318
5319 /* WaDisable4x2SubspanOptimization:ivb */
5320 I915_WRITE(CACHE_MODE_1,
5321 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5322
5323 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5324 snpcr &= ~GEN6_MBC_SNPCR_MASK;
5325 snpcr |= GEN6_MBC_SNPCR_MED;
5326 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5327
5328 if (!HAS_PCH_NOP(dev))
5329 cpt_init_clock_gating(dev);
5330
5331 gen6_check_mch_setup(dev);
5332 }
5333
5334 static void valleyview_init_clock_gating(struct drm_device *dev)
5335 {
5336 struct drm_i915_private *dev_priv = dev->dev_private;
5337
5338 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
5339
5340 /* WaDisableEarlyCull:vlv */
5341 I915_WRITE(_3D_CHICKEN3,
5342 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5343
5344 /* WaDisableBackToBackFlipFix:vlv */
5345 I915_WRITE(IVB_CHICKEN3,
5346 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5347 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5348
5349 /* WaDisablePSDDualDispatchEnable:vlv */
5350 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5351 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
5352 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5353
5354 /* Apply the WaDisableRHWOOptimizationForRenderHang:vlv workaround. */
5355 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5356 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5357
5358 /* WaApplyL3ControlAndL3ChickenMode:vlv */
5359 I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
5360 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
5361
5362 /* WaForceL3Serialization:vlv */
5363 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5364 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5365
5366 /* WaDisableDopClockGating:vlv */
5367 I915_WRITE(GEN7_ROW_CHICKEN2,
5368 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5369
5370 /* This is required by WaCatErrorRejectionIssue:vlv */
5371 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5372 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5373 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5374
5375 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5376 * gating disable must be set. Failure to set it results in
5377 * flickering pixels due to Z write ordering failures after
5378 * some amount of runtime in the Mesa "fire" demo, and Unigine
5379 * Sanctuary and Tropics, and apparently anything else with
5380 * alpha test or pixel discard.
5381 *
5382 * According to the spec, bit 11 (RCCUNIT) must also be set,
5383 * but we didn't debug actual testcases to find it out.
5384 *
5385 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5386 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
5387 *
5388 * Also apply WaDisableVDSUnitClockGating:vlv and
5389 * WaDisableRCPBUnitClockGating:vlv.
5390 */
5391 I915_WRITE(GEN6_UCGCTL2,
5392 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
5393 GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
5394 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
5395 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
5396 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5397
5398 I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
5399
5400 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
5401
5402 I915_WRITE(CACHE_MODE_1,
5403 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5404
5405 /*
5406 * WaDisableVLVClockGating_VBIIssue:vlv
5407 * Disable clock gating on th GCFG unit to prevent a delay
5408 * in the reporting of vblank events.
5409 */
5410 I915_WRITE(VLV_GUNIT_CLOCK_GATE, 0xffffffff);
5411
5412 /* Conservative clock gating settings for now */
5413 I915_WRITE(0x9400, 0xffffffff);
5414 I915_WRITE(0x9404, 0xffffffff);
5415 I915_WRITE(0x9408, 0xffffffff);
5416 I915_WRITE(0x940c, 0xffffffff);
5417 I915_WRITE(0x9410, 0xffffffff);
5418 I915_WRITE(0x9414, 0xffffffff);
5419 I915_WRITE(0x9418, 0xffffffff);
5420 }
5421
5422 static void g4x_init_clock_gating(struct drm_device *dev)
5423 {
5424 struct drm_i915_private *dev_priv = dev->dev_private;
5425 uint32_t dspclk_gate;
5426
5427 I915_WRITE(RENCLK_GATE_D1, 0);
5428 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5429 GS_UNIT_CLOCK_GATE_DISABLE |
5430 CL_UNIT_CLOCK_GATE_DISABLE);
5431 I915_WRITE(RAMCLK_GATE_D, 0);
5432 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5433 OVRUNIT_CLOCK_GATE_DISABLE |
5434 OVCUNIT_CLOCK_GATE_DISABLE;
5435 if (IS_GM45(dev))
5436 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5437 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5438
5439 /* WaDisableRenderCachePipelinedFlush */
5440 I915_WRITE(CACHE_MODE_0,
5441 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
5442
5443 g4x_disable_trickle_feed(dev);
5444 }
5445
5446 static void crestline_init_clock_gating(struct drm_device *dev)
5447 {
5448 struct drm_i915_private *dev_priv = dev->dev_private;
5449
5450 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5451 I915_WRITE(RENCLK_GATE_D2, 0);
5452 I915_WRITE(DSPCLK_GATE_D, 0);
5453 I915_WRITE(RAMCLK_GATE_D, 0);
5454 I915_WRITE16(DEUC, 0);
5455 I915_WRITE(MI_ARB_STATE,
5456 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
5457 }
5458
5459 static void broadwater_init_clock_gating(struct drm_device *dev)
5460 {
5461 struct drm_i915_private *dev_priv = dev->dev_private;
5462
5463 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5464 I965_RCC_CLOCK_GATE_DISABLE |
5465 I965_RCPB_CLOCK_GATE_DISABLE |
5466 I965_ISC_CLOCK_GATE_DISABLE |
5467 I965_FBC_CLOCK_GATE_DISABLE);
5468 I915_WRITE(RENCLK_GATE_D2, 0);
5469 I915_WRITE(MI_ARB_STATE,
5470 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
5471 }
5472
5473 static void gen3_init_clock_gating(struct drm_device *dev)
5474 {
5475 struct drm_i915_private *dev_priv = dev->dev_private;
5476 u32 dstate = I915_READ(D_STATE);
5477
5478 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5479 DSTATE_DOT_CLOCK_GATING;
5480 I915_WRITE(D_STATE, dstate);
5481
5482 if (IS_PINEVIEW(dev))
5483 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
5484
5485 /* IIR "flip pending" means done if this bit is set */
5486 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
5487 }
5488
5489 static void i85x_init_clock_gating(struct drm_device *dev)
5490 {
5491 struct drm_i915_private *dev_priv = dev->dev_private;
5492
5493 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5494 }
5495
5496 static void i830_init_clock_gating(struct drm_device *dev)
5497 {
5498 struct drm_i915_private *dev_priv = dev->dev_private;
5499
5500 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5501 }
5502
5503 void intel_init_clock_gating(struct drm_device *dev)
5504 {
5505 struct drm_i915_private *dev_priv = dev->dev_private;
5506
5507 dev_priv->display.init_clock_gating(dev);
5508 }
5509
5510 void intel_suspend_hw(struct drm_device *dev)
5511 {
5512 if (HAS_PCH_LPT(dev))
5513 lpt_suspend_hw(dev);
5514 }
5515
5516 static bool is_always_on_power_domain(struct drm_device *dev,
5517 enum intel_display_power_domain domain)
5518 {
5519 unsigned long always_on_domains;
5520
5521 BUG_ON(BIT(domain) & ~POWER_DOMAIN_MASK);
5522
5523 if (IS_HASWELL(dev)) {
5524 always_on_domains = HSW_ALWAYS_ON_POWER_DOMAINS;
5525 } else {
5526 WARN_ON(1);
5527 return true;
5528 }
5529
5530 return BIT(domain) & always_on_domains;
5531 }
5532
5533 /**
5534 * We should only use the power well if we explicitly asked the hardware to
5535 * enable it, so check if it's enabled and also check if we've requested it to
5536 * be enabled.
5537 */
5538 bool intel_display_power_enabled(struct drm_device *dev,
5539 enum intel_display_power_domain domain)
5540 {
5541 struct drm_i915_private *dev_priv = dev->dev_private;
5542
5543 if (!HAS_POWER_WELL(dev))
5544 return true;
5545
5546 if (is_always_on_power_domain(dev, domain))
5547 return true;
5548
5549 return I915_READ(HSW_PWR_WELL_DRIVER) ==
5550 (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
5551 }
5552
5553 static void __intel_set_power_well(struct drm_device *dev, bool enable)
5554 {
5555 struct drm_i915_private *dev_priv = dev->dev_private;
5556 bool is_enabled, enable_requested;
5557 uint32_t tmp;
5558
5559 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
5560 is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
5561 enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
5562
5563 if (enable) {
5564 if (!enable_requested)
5565 I915_WRITE(HSW_PWR_WELL_DRIVER,
5566 HSW_PWR_WELL_ENABLE_REQUEST);
5567
5568 if (!is_enabled) {
5569 DRM_DEBUG_KMS("Enabling power well\n");
5570 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
5571 HSW_PWR_WELL_STATE_ENABLED), 20))
5572 DRM_ERROR("Timeout enabling power well\n");
5573 }
5574 } else {
5575 if (enable_requested) {
5576 unsigned long irqflags;
5577 enum pipe p;
5578
5579 I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
5580 POSTING_READ(HSW_PWR_WELL_DRIVER);
5581 DRM_DEBUG_KMS("Requesting to disable the power well\n");
5582
5583 /*
5584 * After this, the registers on the pipes that are part
5585 * of the power well will become zero, so we have to
5586 * adjust our counters according to that.
5587 *
5588 * FIXME: Should we do this in general in
5589 * drm_vblank_post_modeset?
5590 */
5591 spin_lock_irqsave(&dev->vbl_lock, irqflags);
5592 for_each_pipe(p)
5593 if (p != PIPE_A)
5594 dev->vblank[p].last = 0;
5595 spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
5596 }
5597 }
5598 }
5599
5600 static void __intel_power_well_get(struct drm_device *dev,
5601 struct i915_power_well *power_well)
5602 {
5603 if (!power_well->count++)
5604 __intel_set_power_well(dev, true);
5605 }
5606
5607 static void __intel_power_well_put(struct drm_device *dev,
5608 struct i915_power_well *power_well)
5609 {
5610 WARN_ON(!power_well->count);
5611 if (!--power_well->count && i915_disable_power_well)
5612 __intel_set_power_well(dev, false);
5613 }
5614
5615 void intel_display_power_get(struct drm_device *dev,
5616 enum intel_display_power_domain domain)
5617 {
5618 struct drm_i915_private *dev_priv = dev->dev_private;
5619 struct i915_power_domains *power_domains;
5620
5621 if (!HAS_POWER_WELL(dev))
5622 return;
5623
5624 if (is_always_on_power_domain(dev, domain))
5625 return;
5626
5627 power_domains = &dev_priv->power_domains;
5628
5629 mutex_lock(&power_domains->lock);
5630 __intel_power_well_get(dev, &power_domains->power_wells[0]);
5631 mutex_unlock(&power_domains->lock);
5632 }
5633
5634 void intel_display_power_put(struct drm_device *dev,
5635 enum intel_display_power_domain domain)
5636 {
5637 struct drm_i915_private *dev_priv = dev->dev_private;
5638 struct i915_power_domains *power_domains;
5639
5640 if (!HAS_POWER_WELL(dev))
5641 return;
5642
5643 if (is_always_on_power_domain(dev, domain))
5644 return;
5645
5646 power_domains = &dev_priv->power_domains;
5647
5648 mutex_lock(&power_domains->lock);
5649 __intel_power_well_put(dev, &power_domains->power_wells[0]);
5650 mutex_unlock(&power_domains->lock);
5651 }
5652
5653 static struct i915_power_domains *hsw_pwr;
5654
5655 /* Display audio driver power well request */
5656 void i915_request_power_well(void)
5657 {
5658 struct drm_i915_private *dev_priv;
5659
5660 if (WARN_ON(!hsw_pwr))
5661 return;
5662
5663 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
5664 power_domains);
5665
5666 mutex_lock(&hsw_pwr->lock);
5667 __intel_power_well_get(dev_priv->dev, &hsw_pwr->power_wells[0]);
5668 mutex_unlock(&hsw_pwr->lock);
5669 }
5670 EXPORT_SYMBOL_GPL(i915_request_power_well);
5671
5672 /* Display audio driver power well release */
5673 void i915_release_power_well(void)
5674 {
5675 struct drm_i915_private *dev_priv;
5676
5677 if (WARN_ON(!hsw_pwr))
5678 return;
5679
5680 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
5681 power_domains);
5682
5683 mutex_lock(&hsw_pwr->lock);
5684 __intel_power_well_put(dev_priv->dev, &hsw_pwr->power_wells[0]);
5685 mutex_unlock(&hsw_pwr->lock);
5686 }
5687 EXPORT_SYMBOL_GPL(i915_release_power_well);
5688
5689 int intel_power_domains_init(struct drm_device *dev)
5690 {
5691 struct drm_i915_private *dev_priv = dev->dev_private;
5692 struct i915_power_domains *power_domains = &dev_priv->power_domains;
5693 struct i915_power_well *power_well;
5694
5695 mutex_init(&power_domains->lock);
5696 hsw_pwr = power_domains;
5697
5698 power_well = &power_domains->power_wells[0];
5699 power_well->count = 0;
5700
5701 return 0;
5702 }
5703
5704 void intel_power_domains_remove(struct drm_device *dev)
5705 {
5706 hsw_pwr = NULL;
5707 }
5708
5709 static void intel_power_domains_resume(struct drm_device *dev)
5710 {
5711 struct drm_i915_private *dev_priv = dev->dev_private;
5712 struct i915_power_domains *power_domains = &dev_priv->power_domains;
5713 struct i915_power_well *power_well;
5714
5715 if (!HAS_POWER_WELL(dev))
5716 return;
5717
5718 mutex_lock(&power_domains->lock);
5719
5720 power_well = &power_domains->power_wells[0];
5721 __intel_set_power_well(dev, power_well->count > 0);
5722
5723 mutex_unlock(&power_domains->lock);
5724 }
5725
5726 /*
5727 * Starting with Haswell, we have a "Power Down Well" that can be turned off
5728 * when not needed anymore. We have 4 registers that can request the power well
5729 * to be enabled, and it will only be disabled if none of the registers is
5730 * requesting it to be enabled.
5731 */
5732 void intel_power_domains_init_hw(struct drm_device *dev)
5733 {
5734 struct drm_i915_private *dev_priv = dev->dev_private;
5735
5736 if (!HAS_POWER_WELL(dev))
5737 return;
5738
5739 /* For now, we need the power well to be always enabled. */
5740 intel_display_set_init_power(dev, true);
5741 intel_power_domains_resume(dev);
5742
5743 /* We're taking over the BIOS, so clear any requests made by it since
5744 * the driver is in charge now. */
5745 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
5746 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
5747 }
5748
5749 /* Disables PC8 so we can use the GMBUS and DP AUX interrupts. */
5750 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)
5751 {
5752 hsw_disable_package_c8(dev_priv);
5753 }
5754
5755 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)
5756 {
5757 hsw_enable_package_c8(dev_priv);
5758 }
5759
5760 /* Set up chip specific power management-related functions */
5761 void intel_init_pm(struct drm_device *dev)
5762 {
5763 struct drm_i915_private *dev_priv = dev->dev_private;
5764
5765 if (I915_HAS_FBC(dev)) {
5766 if (HAS_PCH_SPLIT(dev)) {
5767 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
5768 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
5769 dev_priv->display.enable_fbc =
5770 gen7_enable_fbc;
5771 else
5772 dev_priv->display.enable_fbc =
5773 ironlake_enable_fbc;
5774 dev_priv->display.disable_fbc = ironlake_disable_fbc;
5775 } else if (IS_GM45(dev)) {
5776 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5777 dev_priv->display.enable_fbc = g4x_enable_fbc;
5778 dev_priv->display.disable_fbc = g4x_disable_fbc;
5779 } else if (IS_CRESTLINE(dev)) {
5780 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5781 dev_priv->display.enable_fbc = i8xx_enable_fbc;
5782 dev_priv->display.disable_fbc = i8xx_disable_fbc;
5783 }
5784 /* 855GM needs testing */
5785 }
5786
5787 /* For cxsr */
5788 if (IS_PINEVIEW(dev))
5789 i915_pineview_get_mem_freq(dev);
5790 else if (IS_GEN5(dev))
5791 i915_ironlake_get_mem_freq(dev);
5792
5793 /* For FIFO watermark updates */
5794 if (HAS_PCH_SPLIT(dev)) {
5795 intel_setup_wm_latency(dev);
5796
5797 if (IS_GEN5(dev)) {
5798 if (dev_priv->wm.pri_latency[1] &&
5799 dev_priv->wm.spr_latency[1] &&
5800 dev_priv->wm.cur_latency[1])
5801 dev_priv->display.update_wm = ironlake_update_wm;
5802 else {
5803 DRM_DEBUG_KMS("Failed to get proper latency. "
5804 "Disable CxSR\n");
5805 dev_priv->display.update_wm = NULL;
5806 }
5807 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
5808 } else if (IS_GEN6(dev)) {
5809 if (dev_priv->wm.pri_latency[0] &&
5810 dev_priv->wm.spr_latency[0] &&
5811 dev_priv->wm.cur_latency[0]) {
5812 dev_priv->display.update_wm = sandybridge_update_wm;
5813 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
5814 } else {
5815 DRM_DEBUG_KMS("Failed to read display plane latency. "
5816 "Disable CxSR\n");
5817 dev_priv->display.update_wm = NULL;
5818 }
5819 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
5820 } else if (IS_IVYBRIDGE(dev)) {
5821 if (dev_priv->wm.pri_latency[0] &&
5822 dev_priv->wm.spr_latency[0] &&
5823 dev_priv->wm.cur_latency[0]) {
5824 dev_priv->display.update_wm = ivybridge_update_wm;
5825 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
5826 } else {
5827 DRM_DEBUG_KMS("Failed to read display plane latency. "
5828 "Disable CxSR\n");
5829 dev_priv->display.update_wm = NULL;
5830 }
5831 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
5832 } else if (IS_HASWELL(dev)) {
5833 if (dev_priv->wm.pri_latency[0] &&
5834 dev_priv->wm.spr_latency[0] &&
5835 dev_priv->wm.cur_latency[0]) {
5836 dev_priv->display.update_wm = haswell_update_wm;
5837 dev_priv->display.update_sprite_wm =
5838 haswell_update_sprite_wm;
5839 } else {
5840 DRM_DEBUG_KMS("Failed to read display plane latency. "
5841 "Disable CxSR\n");
5842 dev_priv->display.update_wm = NULL;
5843 }
5844 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
5845 } else if (INTEL_INFO(dev)->gen == 8) {
5846 dev_priv->display.init_clock_gating = gen8_init_clock_gating;
5847 } else
5848 dev_priv->display.update_wm = NULL;
5849 } else if (IS_VALLEYVIEW(dev)) {
5850 dev_priv->display.update_wm = valleyview_update_wm;
5851 dev_priv->display.init_clock_gating =
5852 valleyview_init_clock_gating;
5853 } else if (IS_PINEVIEW(dev)) {
5854 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5855 dev_priv->is_ddr3,
5856 dev_priv->fsb_freq,
5857 dev_priv->mem_freq)) {
5858 DRM_INFO("failed to find known CxSR latency "
5859 "(found ddr%s fsb freq %d, mem freq %d), "
5860 "disabling CxSR\n",
5861 (dev_priv->is_ddr3 == 1) ? "3" : "2",
5862 dev_priv->fsb_freq, dev_priv->mem_freq);
5863 /* Disable CxSR and never update its watermark again */
5864 pineview_disable_cxsr(dev);
5865 dev_priv->display.update_wm = NULL;
5866 } else
5867 dev_priv->display.update_wm = pineview_update_wm;
5868 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
5869 } else if (IS_G4X(dev)) {
5870 dev_priv->display.update_wm = g4x_update_wm;
5871 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
5872 } else if (IS_GEN4(dev)) {
5873 dev_priv->display.update_wm = i965_update_wm;
5874 if (IS_CRESTLINE(dev))
5875 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
5876 else if (IS_BROADWATER(dev))
5877 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
5878 } else if (IS_GEN3(dev)) {
5879 dev_priv->display.update_wm = i9xx_update_wm;
5880 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5881 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
5882 } else if (IS_I865G(dev)) {
5883 dev_priv->display.update_wm = i830_update_wm;
5884 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
5885 dev_priv->display.get_fifo_size = i830_get_fifo_size;
5886 } else if (IS_I85X(dev)) {
5887 dev_priv->display.update_wm = i9xx_update_wm;
5888 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
5889 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
5890 } else {
5891 dev_priv->display.update_wm = i830_update_wm;
5892 dev_priv->display.init_clock_gating = i830_init_clock_gating;
5893 if (IS_845G(dev))
5894 dev_priv->display.get_fifo_size = i845_get_fifo_size;
5895 else
5896 dev_priv->display.get_fifo_size = i830_get_fifo_size;
5897 }
5898 }
5899
5900 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
5901 {
5902 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5903
5904 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
5905 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
5906 return -EAGAIN;
5907 }
5908
5909 I915_WRITE(GEN6_PCODE_DATA, *val);
5910 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
5911
5912 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
5913 500)) {
5914 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
5915 return -ETIMEDOUT;
5916 }
5917
5918 *val = I915_READ(GEN6_PCODE_DATA);
5919 I915_WRITE(GEN6_PCODE_DATA, 0);
5920
5921 return 0;
5922 }
5923
5924 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
5925 {
5926 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5927
5928 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
5929 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
5930 return -EAGAIN;
5931 }
5932
5933 I915_WRITE(GEN6_PCODE_DATA, val);
5934 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
5935
5936 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
5937 500)) {
5938 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
5939 return -ETIMEDOUT;
5940 }
5941
5942 I915_WRITE(GEN6_PCODE_DATA, 0);
5943
5944 return 0;
5945 }
5946
5947 int vlv_gpu_freq(int ddr_freq, int val)
5948 {
5949 int mult, base;
5950
5951 switch (ddr_freq) {
5952 case 800:
5953 mult = 20;
5954 base = 120;
5955 break;
5956 case 1066:
5957 mult = 22;
5958 base = 133;
5959 break;
5960 case 1333:
5961 mult = 21;
5962 base = 125;
5963 break;
5964 default:
5965 return -1;
5966 }
5967
5968 return ((val - 0xbd) * mult) + base;
5969 }
5970
5971 int vlv_freq_opcode(int ddr_freq, int val)
5972 {
5973 int mult, base;
5974
5975 switch (ddr_freq) {
5976 case 800:
5977 mult = 20;
5978 base = 120;
5979 break;
5980 case 1066:
5981 mult = 22;
5982 base = 133;
5983 break;
5984 case 1333:
5985 mult = 21;
5986 base = 125;
5987 break;
5988 default:
5989 return -1;
5990 }
5991
5992 val /= mult;
5993 val -= base / mult;
5994 val += 0xbd;
5995
5996 if (val > 0xea)
5997 val = 0xea;
5998
5999 return val;
6000 }
6001
6002 void intel_pm_init(struct drm_device *dev)
6003 {
6004 struct drm_i915_private *dev_priv = dev->dev_private;
6005
6006 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
6007 intel_gen6_powersave_work);
6008 }
6009
Linux kernel - Deliverables
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