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41cfb2624cdc04f7648cadf24ccf8557a26d30ea
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_pm.c
1 /*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28 #include <linux/cpufreq.h>
29 #include "i915_drv.h"
30 #include "intel_drv.h"
31 #include "../../../platform/x86/intel_ips.h"
32 #include <linux/module.h>
33
34 /**
35 * RC6 is a special power stage which allows the GPU to enter an very
36 * low-voltage mode when idle, using down to 0V while at this stage. This
37 * stage is entered automatically when the GPU is idle when RC6 support is
38 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
39 *
40 * There are different RC6 modes available in Intel GPU, which differentiate
41 * among each other with the latency required to enter and leave RC6 and
42 * voltage consumed by the GPU in different states.
43 *
44 * The combination of the following flags define which states GPU is allowed
45 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
46 * RC6pp is deepest RC6. Their support by hardware varies according to the
47 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
48 * which brings the most power savings; deeper states save more power, but
49 * require higher latency to switch to and wake up.
50 */
51 #define INTEL_RC6_ENABLE (1<<0)
52 #define INTEL_RC6p_ENABLE (1<<1)
53 #define INTEL_RC6pp_ENABLE (1<<2)
54
55 /* FBC, or Frame Buffer Compression, is a technique employed to compress the
56 * framebuffer contents in-memory, aiming at reducing the required bandwidth
57 * during in-memory transfers and, therefore, reduce the power packet.
58 *
59 * The benefits of FBC are mostly visible with solid backgrounds and
60 * variation-less patterns.
61 *
62 * FBC-related functionality can be enabled by the means of the
63 * i915.i915_enable_fbc parameter
64 */
65
66 static void gen9_init_clock_gating(struct drm_device *dev)
67 {
68 struct drm_i915_private *dev_priv = dev->dev_private;
69
70 /*
71 * WaDisableSDEUnitClockGating:skl
72 * This seems to be a pre-production w/a.
73 */
74 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
75 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
76
77 /*
78 * WaDisableDgMirrorFixInHalfSliceChicken5:skl
79 * This is a pre-production w/a.
80 */
81 I915_WRITE(GEN9_HALF_SLICE_CHICKEN5,
82 I915_READ(GEN9_HALF_SLICE_CHICKEN5) &
83 ~GEN9_DG_MIRROR_FIX_ENABLE);
84
85 /* Wa4x4STCOptimizationDisable:skl */
86 I915_WRITE(CACHE_MODE_1,
87 _MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE));
88 }
89
90 static void i8xx_disable_fbc(struct drm_device *dev)
91 {
92 struct drm_i915_private *dev_priv = dev->dev_private;
93 u32 fbc_ctl;
94
95 dev_priv->fbc.enabled = false;
96
97 /* Disable compression */
98 fbc_ctl = I915_READ(FBC_CONTROL);
99 if ((fbc_ctl & FBC_CTL_EN) == 0)
100 return;
101
102 fbc_ctl &= ~FBC_CTL_EN;
103 I915_WRITE(FBC_CONTROL, fbc_ctl);
104
105 /* Wait for compressing bit to clear */
106 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
107 DRM_DEBUG_KMS("FBC idle timed out\n");
108 return;
109 }
110
111 DRM_DEBUG_KMS("disabled FBC\n");
112 }
113
114 static void i8xx_enable_fbc(struct drm_crtc *crtc)
115 {
116 struct drm_device *dev = crtc->dev;
117 struct drm_i915_private *dev_priv = dev->dev_private;
118 struct drm_framebuffer *fb = crtc->primary->fb;
119 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
120 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
121 int cfb_pitch;
122 int i;
123 u32 fbc_ctl;
124
125 dev_priv->fbc.enabled = true;
126
127 cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
128 if (fb->pitches[0] < cfb_pitch)
129 cfb_pitch = fb->pitches[0];
130
131 /* FBC_CTL wants 32B or 64B units */
132 if (IS_GEN2(dev))
133 cfb_pitch = (cfb_pitch / 32) - 1;
134 else
135 cfb_pitch = (cfb_pitch / 64) - 1;
136
137 /* Clear old tags */
138 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
139 I915_WRITE(FBC_TAG + (i * 4), 0);
140
141 if (IS_GEN4(dev)) {
142 u32 fbc_ctl2;
143
144 /* Set it up... */
145 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
146 fbc_ctl2 |= FBC_CTL_PLANE(intel_crtc->plane);
147 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
148 I915_WRITE(FBC_FENCE_OFF, crtc->y);
149 }
150
151 /* enable it... */
152 fbc_ctl = I915_READ(FBC_CONTROL);
153 fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT;
154 fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
155 if (IS_I945GM(dev))
156 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
157 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
158 fbc_ctl |= obj->fence_reg;
159 I915_WRITE(FBC_CONTROL, fbc_ctl);
160
161 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c\n",
162 cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
163 }
164
165 static bool i8xx_fbc_enabled(struct drm_device *dev)
166 {
167 struct drm_i915_private *dev_priv = dev->dev_private;
168
169 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
170 }
171
172 static void g4x_enable_fbc(struct drm_crtc *crtc)
173 {
174 struct drm_device *dev = crtc->dev;
175 struct drm_i915_private *dev_priv = dev->dev_private;
176 struct drm_framebuffer *fb = crtc->primary->fb;
177 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
178 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
179 u32 dpfc_ctl;
180
181 dev_priv->fbc.enabled = true;
182
183 dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane) | DPFC_SR_EN;
184 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
185 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
186 else
187 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
188 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
189
190 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
191
192 /* enable it... */
193 I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
194
195 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
196 }
197
198 static void g4x_disable_fbc(struct drm_device *dev)
199 {
200 struct drm_i915_private *dev_priv = dev->dev_private;
201 u32 dpfc_ctl;
202
203 dev_priv->fbc.enabled = false;
204
205 /* Disable compression */
206 dpfc_ctl = I915_READ(DPFC_CONTROL);
207 if (dpfc_ctl & DPFC_CTL_EN) {
208 dpfc_ctl &= ~DPFC_CTL_EN;
209 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
210
211 DRM_DEBUG_KMS("disabled FBC\n");
212 }
213 }
214
215 static bool g4x_fbc_enabled(struct drm_device *dev)
216 {
217 struct drm_i915_private *dev_priv = dev->dev_private;
218
219 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
220 }
221
222 static void sandybridge_blit_fbc_update(struct drm_device *dev)
223 {
224 struct drm_i915_private *dev_priv = dev->dev_private;
225 u32 blt_ecoskpd;
226
227 /* Make sure blitter notifies FBC of writes */
228
229 /* Blitter is part of Media powerwell on VLV. No impact of
230 * his param in other platforms for now */
231 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_MEDIA);
232
233 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
234 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
235 GEN6_BLITTER_LOCK_SHIFT;
236 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
237 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
238 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
239 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
240 GEN6_BLITTER_LOCK_SHIFT);
241 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
242 POSTING_READ(GEN6_BLITTER_ECOSKPD);
243
244 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_MEDIA);
245 }
246
247 static void ironlake_enable_fbc(struct drm_crtc *crtc)
248 {
249 struct drm_device *dev = crtc->dev;
250 struct drm_i915_private *dev_priv = dev->dev_private;
251 struct drm_framebuffer *fb = crtc->primary->fb;
252 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
253 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
254 u32 dpfc_ctl;
255
256 dev_priv->fbc.enabled = true;
257
258 dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane);
259 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
260 dev_priv->fbc.threshold++;
261
262 switch (dev_priv->fbc.threshold) {
263 case 4:
264 case 3:
265 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
266 break;
267 case 2:
268 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
269 break;
270 case 1:
271 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
272 break;
273 }
274 dpfc_ctl |= DPFC_CTL_FENCE_EN;
275 if (IS_GEN5(dev))
276 dpfc_ctl |= obj->fence_reg;
277
278 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
279 I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
280 /* enable it... */
281 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
282
283 if (IS_GEN6(dev)) {
284 I915_WRITE(SNB_DPFC_CTL_SA,
285 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
286 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
287 sandybridge_blit_fbc_update(dev);
288 }
289
290 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
291 }
292
293 static void ironlake_disable_fbc(struct drm_device *dev)
294 {
295 struct drm_i915_private *dev_priv = dev->dev_private;
296 u32 dpfc_ctl;
297
298 dev_priv->fbc.enabled = false;
299
300 /* Disable compression */
301 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
302 if (dpfc_ctl & DPFC_CTL_EN) {
303 dpfc_ctl &= ~DPFC_CTL_EN;
304 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
305
306 DRM_DEBUG_KMS("disabled FBC\n");
307 }
308 }
309
310 static bool ironlake_fbc_enabled(struct drm_device *dev)
311 {
312 struct drm_i915_private *dev_priv = dev->dev_private;
313
314 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
315 }
316
317 static void gen7_enable_fbc(struct drm_crtc *crtc)
318 {
319 struct drm_device *dev = crtc->dev;
320 struct drm_i915_private *dev_priv = dev->dev_private;
321 struct drm_framebuffer *fb = crtc->primary->fb;
322 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
323 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
324 u32 dpfc_ctl;
325
326 dev_priv->fbc.enabled = true;
327
328 dpfc_ctl = IVB_DPFC_CTL_PLANE(intel_crtc->plane);
329 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
330 dev_priv->fbc.threshold++;
331
332 switch (dev_priv->fbc.threshold) {
333 case 4:
334 case 3:
335 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
336 break;
337 case 2:
338 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
339 break;
340 case 1:
341 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
342 break;
343 }
344
345 dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
346
347 if (dev_priv->fbc.false_color)
348 dpfc_ctl |= FBC_CTL_FALSE_COLOR;
349
350 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
351
352 if (IS_IVYBRIDGE(dev)) {
353 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
354 I915_WRITE(ILK_DISPLAY_CHICKEN1,
355 I915_READ(ILK_DISPLAY_CHICKEN1) |
356 ILK_FBCQ_DIS);
357 } else {
358 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
359 I915_WRITE(CHICKEN_PIPESL_1(intel_crtc->pipe),
360 I915_READ(CHICKEN_PIPESL_1(intel_crtc->pipe)) |
361 HSW_FBCQ_DIS);
362 }
363
364 I915_WRITE(SNB_DPFC_CTL_SA,
365 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
366 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
367
368 sandybridge_blit_fbc_update(dev);
369
370 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
371 }
372
373 bool intel_fbc_enabled(struct drm_device *dev)
374 {
375 struct drm_i915_private *dev_priv = dev->dev_private;
376
377 return dev_priv->fbc.enabled;
378 }
379
380 void bdw_fbc_sw_flush(struct drm_device *dev, u32 value)
381 {
382 struct drm_i915_private *dev_priv = dev->dev_private;
383
384 if (!IS_GEN8(dev))
385 return;
386
387 if (!intel_fbc_enabled(dev))
388 return;
389
390 I915_WRITE(MSG_FBC_REND_STATE, value);
391 }
392
393 static void intel_fbc_work_fn(struct work_struct *__work)
394 {
395 struct intel_fbc_work *work =
396 container_of(to_delayed_work(__work),
397 struct intel_fbc_work, work);
398 struct drm_device *dev = work->crtc->dev;
399 struct drm_i915_private *dev_priv = dev->dev_private;
400
401 mutex_lock(&dev->struct_mutex);
402 if (work == dev_priv->fbc.fbc_work) {
403 /* Double check that we haven't switched fb without cancelling
404 * the prior work.
405 */
406 if (work->crtc->primary->fb == work->fb) {
407 dev_priv->display.enable_fbc(work->crtc);
408
409 dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;
410 dev_priv->fbc.fb_id = work->crtc->primary->fb->base.id;
411 dev_priv->fbc.y = work->crtc->y;
412 }
413
414 dev_priv->fbc.fbc_work = NULL;
415 }
416 mutex_unlock(&dev->struct_mutex);
417
418 kfree(work);
419 }
420
421 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
422 {
423 if (dev_priv->fbc.fbc_work == NULL)
424 return;
425
426 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
427
428 /* Synchronisation is provided by struct_mutex and checking of
429 * dev_priv->fbc.fbc_work, so we can perform the cancellation
430 * entirely asynchronously.
431 */
432 if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
433 /* tasklet was killed before being run, clean up */
434 kfree(dev_priv->fbc.fbc_work);
435
436 /* Mark the work as no longer wanted so that if it does
437 * wake-up (because the work was already running and waiting
438 * for our mutex), it will discover that is no longer
439 * necessary to run.
440 */
441 dev_priv->fbc.fbc_work = NULL;
442 }
443
444 static void intel_enable_fbc(struct drm_crtc *crtc)
445 {
446 struct intel_fbc_work *work;
447 struct drm_device *dev = crtc->dev;
448 struct drm_i915_private *dev_priv = dev->dev_private;
449
450 if (!dev_priv->display.enable_fbc)
451 return;
452
453 intel_cancel_fbc_work(dev_priv);
454
455 work = kzalloc(sizeof(*work), GFP_KERNEL);
456 if (work == NULL) {
457 DRM_ERROR("Failed to allocate FBC work structure\n");
458 dev_priv->display.enable_fbc(crtc);
459 return;
460 }
461
462 work->crtc = crtc;
463 work->fb = crtc->primary->fb;
464 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
465
466 dev_priv->fbc.fbc_work = work;
467
468 /* Delay the actual enabling to let pageflipping cease and the
469 * display to settle before starting the compression. Note that
470 * this delay also serves a second purpose: it allows for a
471 * vblank to pass after disabling the FBC before we attempt
472 * to modify the control registers.
473 *
474 * A more complicated solution would involve tracking vblanks
475 * following the termination of the page-flipping sequence
476 * and indeed performing the enable as a co-routine and not
477 * waiting synchronously upon the vblank.
478 *
479 * WaFbcWaitForVBlankBeforeEnable:ilk,snb
480 */
481 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
482 }
483
484 void intel_disable_fbc(struct drm_device *dev)
485 {
486 struct drm_i915_private *dev_priv = dev->dev_private;
487
488 intel_cancel_fbc_work(dev_priv);
489
490 if (!dev_priv->display.disable_fbc)
491 return;
492
493 dev_priv->display.disable_fbc(dev);
494 dev_priv->fbc.plane = -1;
495 }
496
497 static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
498 enum no_fbc_reason reason)
499 {
500 if (dev_priv->fbc.no_fbc_reason == reason)
501 return false;
502
503 dev_priv->fbc.no_fbc_reason = reason;
504 return true;
505 }
506
507 /**
508 * intel_update_fbc - enable/disable FBC as needed
509 * @dev: the drm_device
510 *
511 * Set up the framebuffer compression hardware at mode set time. We
512 * enable it if possible:
513 * - plane A only (on pre-965)
514 * - no pixel mulitply/line duplication
515 * - no alpha buffer discard
516 * - no dual wide
517 * - framebuffer <= max_hdisplay in width, max_vdisplay in height
518 *
519 * We can't assume that any compression will take place (worst case),
520 * so the compressed buffer has to be the same size as the uncompressed
521 * one. It also must reside (along with the line length buffer) in
522 * stolen memory.
523 *
524 * We need to enable/disable FBC on a global basis.
525 */
526 void intel_update_fbc(struct drm_device *dev)
527 {
528 struct drm_i915_private *dev_priv = dev->dev_private;
529 struct drm_crtc *crtc = NULL, *tmp_crtc;
530 struct intel_crtc *intel_crtc;
531 struct drm_framebuffer *fb;
532 struct drm_i915_gem_object *obj;
533 const struct drm_display_mode *adjusted_mode;
534 unsigned int max_width, max_height;
535
536 if (!HAS_FBC(dev)) {
537 set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED);
538 return;
539 }
540
541 if (!i915.powersave) {
542 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
543 DRM_DEBUG_KMS("fbc disabled per module param\n");
544 return;
545 }
546
547 /*
548 * If FBC is already on, we just have to verify that we can
549 * keep it that way...
550 * Need to disable if:
551 * - more than one pipe is active
552 * - changing FBC params (stride, fence, mode)
553 * - new fb is too large to fit in compressed buffer
554 * - going to an unsupported config (interlace, pixel multiply, etc.)
555 */
556 for_each_crtc(dev, tmp_crtc) {
557 if (intel_crtc_active(tmp_crtc) &&
558 to_intel_crtc(tmp_crtc)->primary_enabled) {
559 if (crtc) {
560 if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
561 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
562 goto out_disable;
563 }
564 crtc = tmp_crtc;
565 }
566 }
567
568 if (!crtc || crtc->primary->fb == NULL) {
569 if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
570 DRM_DEBUG_KMS("no output, disabling\n");
571 goto out_disable;
572 }
573
574 intel_crtc = to_intel_crtc(crtc);
575 fb = crtc->primary->fb;
576 obj = intel_fb_obj(fb);
577 adjusted_mode = &intel_crtc->config.adjusted_mode;
578
579 if (i915.enable_fbc < 0) {
580 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
581 DRM_DEBUG_KMS("disabled per chip default\n");
582 goto out_disable;
583 }
584 if (!i915.enable_fbc) {
585 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
586 DRM_DEBUG_KMS("fbc disabled per module param\n");
587 goto out_disable;
588 }
589 if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ||
590 (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
591 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
592 DRM_DEBUG_KMS("mode incompatible with compression, "
593 "disabling\n");
594 goto out_disable;
595 }
596
597 if (INTEL_INFO(dev)->gen >= 8 || IS_HASWELL(dev)) {
598 max_width = 4096;
599 max_height = 4096;
600 } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
601 max_width = 4096;
602 max_height = 2048;
603 } else {
604 max_width = 2048;
605 max_height = 1536;
606 }
607 if (intel_crtc->config.pipe_src_w > max_width ||
608 intel_crtc->config.pipe_src_h > max_height) {
609 if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
610 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
611 goto out_disable;
612 }
613 if ((INTEL_INFO(dev)->gen < 4 || HAS_DDI(dev)) &&
614 intel_crtc->plane != PLANE_A) {
615 if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
616 DRM_DEBUG_KMS("plane not A, disabling compression\n");
617 goto out_disable;
618 }
619
620 /* The use of a CPU fence is mandatory in order to detect writes
621 * by the CPU to the scanout and trigger updates to the FBC.
622 */
623 if (obj->tiling_mode != I915_TILING_X ||
624 obj->fence_reg == I915_FENCE_REG_NONE) {
625 if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED))
626 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
627 goto out_disable;
628 }
629 if (INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
630 to_intel_plane(crtc->primary)->rotation != BIT(DRM_ROTATE_0)) {
631 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
632 DRM_DEBUG_KMS("Rotation unsupported, disabling\n");
633 goto out_disable;
634 }
635
636 /* If the kernel debugger is active, always disable compression */
637 if (in_dbg_master())
638 goto out_disable;
639
640 if (i915_gem_stolen_setup_compression(dev, obj->base.size,
641 drm_format_plane_cpp(fb->pixel_format, 0))) {
642 if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL))
643 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
644 goto out_disable;
645 }
646
647 /* If the scanout has not changed, don't modify the FBC settings.
648 * Note that we make the fundamental assumption that the fb->obj
649 * cannot be unpinned (and have its GTT offset and fence revoked)
650 * without first being decoupled from the scanout and FBC disabled.
651 */
652 if (dev_priv->fbc.plane == intel_crtc->plane &&
653 dev_priv->fbc.fb_id == fb->base.id &&
654 dev_priv->fbc.y == crtc->y)
655 return;
656
657 if (intel_fbc_enabled(dev)) {
658 /* We update FBC along two paths, after changing fb/crtc
659 * configuration (modeswitching) and after page-flipping
660 * finishes. For the latter, we know that not only did
661 * we disable the FBC at the start of the page-flip
662 * sequence, but also more than one vblank has passed.
663 *
664 * For the former case of modeswitching, it is possible
665 * to switch between two FBC valid configurations
666 * instantaneously so we do need to disable the FBC
667 * before we can modify its control registers. We also
668 * have to wait for the next vblank for that to take
669 * effect. However, since we delay enabling FBC we can
670 * assume that a vblank has passed since disabling and
671 * that we can safely alter the registers in the deferred
672 * callback.
673 *
674 * In the scenario that we go from a valid to invalid
675 * and then back to valid FBC configuration we have
676 * no strict enforcement that a vblank occurred since
677 * disabling the FBC. However, along all current pipe
678 * disabling paths we do need to wait for a vblank at
679 * some point. And we wait before enabling FBC anyway.
680 */
681 DRM_DEBUG_KMS("disabling active FBC for update\n");
682 intel_disable_fbc(dev);
683 }
684
685 intel_enable_fbc(crtc);
686 dev_priv->fbc.no_fbc_reason = FBC_OK;
687 return;
688
689 out_disable:
690 /* Multiple disables should be harmless */
691 if (intel_fbc_enabled(dev)) {
692 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
693 intel_disable_fbc(dev);
694 }
695 i915_gem_stolen_cleanup_compression(dev);
696 }
697
698 static void i915_pineview_get_mem_freq(struct drm_device *dev)
699 {
700 struct drm_i915_private *dev_priv = dev->dev_private;
701 u32 tmp;
702
703 tmp = I915_READ(CLKCFG);
704
705 switch (tmp & CLKCFG_FSB_MASK) {
706 case CLKCFG_FSB_533:
707 dev_priv->fsb_freq = 533; /* 133*4 */
708 break;
709 case CLKCFG_FSB_800:
710 dev_priv->fsb_freq = 800; /* 200*4 */
711 break;
712 case CLKCFG_FSB_667:
713 dev_priv->fsb_freq = 667; /* 167*4 */
714 break;
715 case CLKCFG_FSB_400:
716 dev_priv->fsb_freq = 400; /* 100*4 */
717 break;
718 }
719
720 switch (tmp & CLKCFG_MEM_MASK) {
721 case CLKCFG_MEM_533:
722 dev_priv->mem_freq = 533;
723 break;
724 case CLKCFG_MEM_667:
725 dev_priv->mem_freq = 667;
726 break;
727 case CLKCFG_MEM_800:
728 dev_priv->mem_freq = 800;
729 break;
730 }
731
732 /* detect pineview DDR3 setting */
733 tmp = I915_READ(CSHRDDR3CTL);
734 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
735 }
736
737 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
738 {
739 struct drm_i915_private *dev_priv = dev->dev_private;
740 u16 ddrpll, csipll;
741
742 ddrpll = I915_READ16(DDRMPLL1);
743 csipll = I915_READ16(CSIPLL0);
744
745 switch (ddrpll & 0xff) {
746 case 0xc:
747 dev_priv->mem_freq = 800;
748 break;
749 case 0x10:
750 dev_priv->mem_freq = 1066;
751 break;
752 case 0x14:
753 dev_priv->mem_freq = 1333;
754 break;
755 case 0x18:
756 dev_priv->mem_freq = 1600;
757 break;
758 default:
759 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
760 ddrpll & 0xff);
761 dev_priv->mem_freq = 0;
762 break;
763 }
764
765 dev_priv->ips.r_t = dev_priv->mem_freq;
766
767 switch (csipll & 0x3ff) {
768 case 0x00c:
769 dev_priv->fsb_freq = 3200;
770 break;
771 case 0x00e:
772 dev_priv->fsb_freq = 3733;
773 break;
774 case 0x010:
775 dev_priv->fsb_freq = 4266;
776 break;
777 case 0x012:
778 dev_priv->fsb_freq = 4800;
779 break;
780 case 0x014:
781 dev_priv->fsb_freq = 5333;
782 break;
783 case 0x016:
784 dev_priv->fsb_freq = 5866;
785 break;
786 case 0x018:
787 dev_priv->fsb_freq = 6400;
788 break;
789 default:
790 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
791 csipll & 0x3ff);
792 dev_priv->fsb_freq = 0;
793 break;
794 }
795
796 if (dev_priv->fsb_freq == 3200) {
797 dev_priv->ips.c_m = 0;
798 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
799 dev_priv->ips.c_m = 1;
800 } else {
801 dev_priv->ips.c_m = 2;
802 }
803 }
804
805 static const struct cxsr_latency cxsr_latency_table[] = {
806 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
807 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
808 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
809 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
810 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
811
812 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
813 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
814 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
815 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
816 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
817
818 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
819 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
820 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
821 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
822 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
823
824 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
825 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
826 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
827 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
828 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
829
830 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
831 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
832 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
833 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
834 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
835
836 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
837 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
838 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
839 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
840 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
841 };
842
843 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
844 int is_ddr3,
845 int fsb,
846 int mem)
847 {
848 const struct cxsr_latency *latency;
849 int i;
850
851 if (fsb == 0 || mem == 0)
852 return NULL;
853
854 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
855 latency = &cxsr_latency_table[i];
856 if (is_desktop == latency->is_desktop &&
857 is_ddr3 == latency->is_ddr3 &&
858 fsb == latency->fsb_freq && mem == latency->mem_freq)
859 return latency;
860 }
861
862 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
863
864 return NULL;
865 }
866
867 void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
868 {
869 struct drm_device *dev = dev_priv->dev;
870 u32 val;
871
872 if (IS_VALLEYVIEW(dev)) {
873 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
874 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
875 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
876 } else if (IS_PINEVIEW(dev)) {
877 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
878 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
879 I915_WRITE(DSPFW3, val);
880 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
881 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
882 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
883 I915_WRITE(FW_BLC_SELF, val);
884 } else if (IS_I915GM(dev)) {
885 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
886 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
887 I915_WRITE(INSTPM, val);
888 } else {
889 return;
890 }
891
892 DRM_DEBUG_KMS("memory self-refresh is %s\n",
893 enable ? "enabled" : "disabled");
894 }
895
896 /*
897 * Latency for FIFO fetches is dependent on several factors:
898 * - memory configuration (speed, channels)
899 * - chipset
900 * - current MCH state
901 * It can be fairly high in some situations, so here we assume a fairly
902 * pessimal value. It's a tradeoff between extra memory fetches (if we
903 * set this value too high, the FIFO will fetch frequently to stay full)
904 * and power consumption (set it too low to save power and we might see
905 * FIFO underruns and display "flicker").
906 *
907 * A value of 5us seems to be a good balance; safe for very low end
908 * platforms but not overly aggressive on lower latency configs.
909 */
910 static const int pessimal_latency_ns = 5000;
911
912 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
913 {
914 struct drm_i915_private *dev_priv = dev->dev_private;
915 uint32_t dsparb = I915_READ(DSPARB);
916 int size;
917
918 size = dsparb & 0x7f;
919 if (plane)
920 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
921
922 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
923 plane ? "B" : "A", size);
924
925 return size;
926 }
927
928 static int i830_get_fifo_size(struct drm_device *dev, int plane)
929 {
930 struct drm_i915_private *dev_priv = dev->dev_private;
931 uint32_t dsparb = I915_READ(DSPARB);
932 int size;
933
934 size = dsparb & 0x1ff;
935 if (plane)
936 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
937 size >>= 1; /* Convert to cachelines */
938
939 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
940 plane ? "B" : "A", size);
941
942 return size;
943 }
944
945 static int i845_get_fifo_size(struct drm_device *dev, int plane)
946 {
947 struct drm_i915_private *dev_priv = dev->dev_private;
948 uint32_t dsparb = I915_READ(DSPARB);
949 int size;
950
951 size = dsparb & 0x7f;
952 size >>= 2; /* Convert to cachelines */
953
954 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
955 plane ? "B" : "A",
956 size);
957
958 return size;
959 }
960
961 /* Pineview has different values for various configs */
962 static const struct intel_watermark_params pineview_display_wm = {
963 .fifo_size = PINEVIEW_DISPLAY_FIFO,
964 .max_wm = PINEVIEW_MAX_WM,
965 .default_wm = PINEVIEW_DFT_WM,
966 .guard_size = PINEVIEW_GUARD_WM,
967 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
968 };
969 static const struct intel_watermark_params pineview_display_hplloff_wm = {
970 .fifo_size = PINEVIEW_DISPLAY_FIFO,
971 .max_wm = PINEVIEW_MAX_WM,
972 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
973 .guard_size = PINEVIEW_GUARD_WM,
974 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
975 };
976 static const struct intel_watermark_params pineview_cursor_wm = {
977 .fifo_size = PINEVIEW_CURSOR_FIFO,
978 .max_wm = PINEVIEW_CURSOR_MAX_WM,
979 .default_wm = PINEVIEW_CURSOR_DFT_WM,
980 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
981 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
982 };
983 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
984 .fifo_size = PINEVIEW_CURSOR_FIFO,
985 .max_wm = PINEVIEW_CURSOR_MAX_WM,
986 .default_wm = PINEVIEW_CURSOR_DFT_WM,
987 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
988 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
989 };
990 static const struct intel_watermark_params g4x_wm_info = {
991 .fifo_size = G4X_FIFO_SIZE,
992 .max_wm = G4X_MAX_WM,
993 .default_wm = G4X_MAX_WM,
994 .guard_size = 2,
995 .cacheline_size = G4X_FIFO_LINE_SIZE,
996 };
997 static const struct intel_watermark_params g4x_cursor_wm_info = {
998 .fifo_size = I965_CURSOR_FIFO,
999 .max_wm = I965_CURSOR_MAX_WM,
1000 .default_wm = I965_CURSOR_DFT_WM,
1001 .guard_size = 2,
1002 .cacheline_size = G4X_FIFO_LINE_SIZE,
1003 };
1004 static const struct intel_watermark_params valleyview_wm_info = {
1005 .fifo_size = VALLEYVIEW_FIFO_SIZE,
1006 .max_wm = VALLEYVIEW_MAX_WM,
1007 .default_wm = VALLEYVIEW_MAX_WM,
1008 .guard_size = 2,
1009 .cacheline_size = G4X_FIFO_LINE_SIZE,
1010 };
1011 static const struct intel_watermark_params valleyview_cursor_wm_info = {
1012 .fifo_size = I965_CURSOR_FIFO,
1013 .max_wm = VALLEYVIEW_CURSOR_MAX_WM,
1014 .default_wm = I965_CURSOR_DFT_WM,
1015 .guard_size = 2,
1016 .cacheline_size = G4X_FIFO_LINE_SIZE,
1017 };
1018 static const struct intel_watermark_params i965_cursor_wm_info = {
1019 .fifo_size = I965_CURSOR_FIFO,
1020 .max_wm = I965_CURSOR_MAX_WM,
1021 .default_wm = I965_CURSOR_DFT_WM,
1022 .guard_size = 2,
1023 .cacheline_size = I915_FIFO_LINE_SIZE,
1024 };
1025 static const struct intel_watermark_params i945_wm_info = {
1026 .fifo_size = I945_FIFO_SIZE,
1027 .max_wm = I915_MAX_WM,
1028 .default_wm = 1,
1029 .guard_size = 2,
1030 .cacheline_size = I915_FIFO_LINE_SIZE,
1031 };
1032 static const struct intel_watermark_params i915_wm_info = {
1033 .fifo_size = I915_FIFO_SIZE,
1034 .max_wm = I915_MAX_WM,
1035 .default_wm = 1,
1036 .guard_size = 2,
1037 .cacheline_size = I915_FIFO_LINE_SIZE,
1038 };
1039 static const struct intel_watermark_params i830_a_wm_info = {
1040 .fifo_size = I855GM_FIFO_SIZE,
1041 .max_wm = I915_MAX_WM,
1042 .default_wm = 1,
1043 .guard_size = 2,
1044 .cacheline_size = I830_FIFO_LINE_SIZE,
1045 };
1046 static const struct intel_watermark_params i830_bc_wm_info = {
1047 .fifo_size = I855GM_FIFO_SIZE,
1048 .max_wm = I915_MAX_WM/2,
1049 .default_wm = 1,
1050 .guard_size = 2,
1051 .cacheline_size = I830_FIFO_LINE_SIZE,
1052 };
1053 static const struct intel_watermark_params i845_wm_info = {
1054 .fifo_size = I830_FIFO_SIZE,
1055 .max_wm = I915_MAX_WM,
1056 .default_wm = 1,
1057 .guard_size = 2,
1058 .cacheline_size = I830_FIFO_LINE_SIZE,
1059 };
1060
1061 /**
1062 * intel_calculate_wm - calculate watermark level
1063 * @clock_in_khz: pixel clock
1064 * @wm: chip FIFO params
1065 * @pixel_size: display pixel size
1066 * @latency_ns: memory latency for the platform
1067 *
1068 * Calculate the watermark level (the level at which the display plane will
1069 * start fetching from memory again). Each chip has a different display
1070 * FIFO size and allocation, so the caller needs to figure that out and pass
1071 * in the correct intel_watermark_params structure.
1072 *
1073 * As the pixel clock runs, the FIFO will be drained at a rate that depends
1074 * on the pixel size. When it reaches the watermark level, it'll start
1075 * fetching FIFO line sized based chunks from memory until the FIFO fills
1076 * past the watermark point. If the FIFO drains completely, a FIFO underrun
1077 * will occur, and a display engine hang could result.
1078 */
1079 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
1080 const struct intel_watermark_params *wm,
1081 int fifo_size,
1082 int pixel_size,
1083 unsigned long latency_ns)
1084 {
1085 long entries_required, wm_size;
1086
1087 /*
1088 * Note: we need to make sure we don't overflow for various clock &
1089 * latency values.
1090 * clocks go from a few thousand to several hundred thousand.
1091 * latency is usually a few thousand
1092 */
1093 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
1094 1000;
1095 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
1096
1097 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
1098
1099 wm_size = fifo_size - (entries_required + wm->guard_size);
1100
1101 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
1102
1103 /* Don't promote wm_size to unsigned... */
1104 if (wm_size > (long)wm->max_wm)
1105 wm_size = wm->max_wm;
1106 if (wm_size <= 0)
1107 wm_size = wm->default_wm;
1108
1109 /*
1110 * Bspec seems to indicate that the value shouldn't be lower than
1111 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
1112 * Lets go for 8 which is the burst size since certain platforms
1113 * already use a hardcoded 8 (which is what the spec says should be
1114 * done).
1115 */
1116 if (wm_size <= 8)
1117 wm_size = 8;
1118
1119 return wm_size;
1120 }
1121
1122 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1123 {
1124 struct drm_crtc *crtc, *enabled = NULL;
1125
1126 for_each_crtc(dev, crtc) {
1127 if (intel_crtc_active(crtc)) {
1128 if (enabled)
1129 return NULL;
1130 enabled = crtc;
1131 }
1132 }
1133
1134 return enabled;
1135 }
1136
1137 static void pineview_update_wm(struct drm_crtc *unused_crtc)
1138 {
1139 struct drm_device *dev = unused_crtc->dev;
1140 struct drm_i915_private *dev_priv = dev->dev_private;
1141 struct drm_crtc *crtc;
1142 const struct cxsr_latency *latency;
1143 u32 reg;
1144 unsigned long wm;
1145
1146 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1147 dev_priv->fsb_freq, dev_priv->mem_freq);
1148 if (!latency) {
1149 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1150 intel_set_memory_cxsr(dev_priv, false);
1151 return;
1152 }
1153
1154 crtc = single_enabled_crtc(dev);
1155 if (crtc) {
1156 const struct drm_display_mode *adjusted_mode;
1157 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1158 int clock;
1159
1160 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1161 clock = adjusted_mode->crtc_clock;
1162
1163 /* Display SR */
1164 wm = intel_calculate_wm(clock, &pineview_display_wm,
1165 pineview_display_wm.fifo_size,
1166 pixel_size, latency->display_sr);
1167 reg = I915_READ(DSPFW1);
1168 reg &= ~DSPFW_SR_MASK;
1169 reg |= wm << DSPFW_SR_SHIFT;
1170 I915_WRITE(DSPFW1, reg);
1171 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1172
1173 /* cursor SR */
1174 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1175 pineview_display_wm.fifo_size,
1176 pixel_size, latency->cursor_sr);
1177 reg = I915_READ(DSPFW3);
1178 reg &= ~DSPFW_CURSOR_SR_MASK;
1179 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1180 I915_WRITE(DSPFW3, reg);
1181
1182 /* Display HPLL off SR */
1183 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1184 pineview_display_hplloff_wm.fifo_size,
1185 pixel_size, latency->display_hpll_disable);
1186 reg = I915_READ(DSPFW3);
1187 reg &= ~DSPFW_HPLL_SR_MASK;
1188 reg |= wm & DSPFW_HPLL_SR_MASK;
1189 I915_WRITE(DSPFW3, reg);
1190
1191 /* cursor HPLL off SR */
1192 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1193 pineview_display_hplloff_wm.fifo_size,
1194 pixel_size, latency->cursor_hpll_disable);
1195 reg = I915_READ(DSPFW3);
1196 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1197 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1198 I915_WRITE(DSPFW3, reg);
1199 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1200
1201 intel_set_memory_cxsr(dev_priv, true);
1202 } else {
1203 intel_set_memory_cxsr(dev_priv, false);
1204 }
1205 }
1206
1207 static bool g4x_compute_wm0(struct drm_device *dev,
1208 int plane,
1209 const struct intel_watermark_params *display,
1210 int display_latency_ns,
1211 const struct intel_watermark_params *cursor,
1212 int cursor_latency_ns,
1213 int *plane_wm,
1214 int *cursor_wm)
1215 {
1216 struct drm_crtc *crtc;
1217 const struct drm_display_mode *adjusted_mode;
1218 int htotal, hdisplay, clock, pixel_size;
1219 int line_time_us, line_count;
1220 int entries, tlb_miss;
1221
1222 crtc = intel_get_crtc_for_plane(dev, plane);
1223 if (!intel_crtc_active(crtc)) {
1224 *cursor_wm = cursor->guard_size;
1225 *plane_wm = display->guard_size;
1226 return false;
1227 }
1228
1229 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1230 clock = adjusted_mode->crtc_clock;
1231 htotal = adjusted_mode->crtc_htotal;
1232 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1233 pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1234
1235 /* Use the small buffer method to calculate plane watermark */
1236 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1237 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1238 if (tlb_miss > 0)
1239 entries += tlb_miss;
1240 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1241 *plane_wm = entries + display->guard_size;
1242 if (*plane_wm > (int)display->max_wm)
1243 *plane_wm = display->max_wm;
1244
1245 /* Use the large buffer method to calculate cursor watermark */
1246 line_time_us = max(htotal * 1000 / clock, 1);
1247 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1248 entries = line_count * to_intel_crtc(crtc)->cursor_width * pixel_size;
1249 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1250 if (tlb_miss > 0)
1251 entries += tlb_miss;
1252 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1253 *cursor_wm = entries + cursor->guard_size;
1254 if (*cursor_wm > (int)cursor->max_wm)
1255 *cursor_wm = (int)cursor->max_wm;
1256
1257 return true;
1258 }
1259
1260 /*
1261 * Check the wm result.
1262 *
1263 * If any calculated watermark values is larger than the maximum value that
1264 * can be programmed into the associated watermark register, that watermark
1265 * must be disabled.
1266 */
1267 static bool g4x_check_srwm(struct drm_device *dev,
1268 int display_wm, int cursor_wm,
1269 const struct intel_watermark_params *display,
1270 const struct intel_watermark_params *cursor)
1271 {
1272 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1273 display_wm, cursor_wm);
1274
1275 if (display_wm > display->max_wm) {
1276 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1277 display_wm, display->max_wm);
1278 return false;
1279 }
1280
1281 if (cursor_wm > cursor->max_wm) {
1282 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1283 cursor_wm, cursor->max_wm);
1284 return false;
1285 }
1286
1287 if (!(display_wm || cursor_wm)) {
1288 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1289 return false;
1290 }
1291
1292 return true;
1293 }
1294
1295 static bool g4x_compute_srwm(struct drm_device *dev,
1296 int plane,
1297 int latency_ns,
1298 const struct intel_watermark_params *display,
1299 const struct intel_watermark_params *cursor,
1300 int *display_wm, int *cursor_wm)
1301 {
1302 struct drm_crtc *crtc;
1303 const struct drm_display_mode *adjusted_mode;
1304 int hdisplay, htotal, pixel_size, clock;
1305 unsigned long line_time_us;
1306 int line_count, line_size;
1307 int small, large;
1308 int entries;
1309
1310 if (!latency_ns) {
1311 *display_wm = *cursor_wm = 0;
1312 return false;
1313 }
1314
1315 crtc = intel_get_crtc_for_plane(dev, plane);
1316 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1317 clock = adjusted_mode->crtc_clock;
1318 htotal = adjusted_mode->crtc_htotal;
1319 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1320 pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1321
1322 line_time_us = max(htotal * 1000 / clock, 1);
1323 line_count = (latency_ns / line_time_us + 1000) / 1000;
1324 line_size = hdisplay * pixel_size;
1325
1326 /* Use the minimum of the small and large buffer method for primary */
1327 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1328 large = line_count * line_size;
1329
1330 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1331 *display_wm = entries + display->guard_size;
1332
1333 /* calculate the self-refresh watermark for display cursor */
1334 entries = line_count * pixel_size * to_intel_crtc(crtc)->cursor_width;
1335 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1336 *cursor_wm = entries + cursor->guard_size;
1337
1338 return g4x_check_srwm(dev,
1339 *display_wm, *cursor_wm,
1340 display, cursor);
1341 }
1342
1343 static bool vlv_compute_drain_latency(struct drm_crtc *crtc,
1344 int pixel_size,
1345 int *prec_mult,
1346 int *drain_latency)
1347 {
1348 struct drm_device *dev = crtc->dev;
1349 int entries;
1350 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
1351
1352 if (WARN(clock == 0, "Pixel clock is zero!\n"))
1353 return false;
1354
1355 if (WARN(pixel_size == 0, "Pixel size is zero!\n"))
1356 return false;
1357
1358 entries = DIV_ROUND_UP(clock, 1000) * pixel_size;
1359 if (IS_CHERRYVIEW(dev))
1360 *prec_mult = (entries > 128) ? DRAIN_LATENCY_PRECISION_32 :
1361 DRAIN_LATENCY_PRECISION_16;
1362 else
1363 *prec_mult = (entries > 128) ? DRAIN_LATENCY_PRECISION_64 :
1364 DRAIN_LATENCY_PRECISION_32;
1365 *drain_latency = (64 * (*prec_mult) * 4) / entries;
1366
1367 if (*drain_latency > DRAIN_LATENCY_MASK)
1368 *drain_latency = DRAIN_LATENCY_MASK;
1369
1370 return true;
1371 }
1372
1373 /*
1374 * Update drain latency registers of memory arbiter
1375 *
1376 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1377 * to be programmed. Each plane has a drain latency multiplier and a drain
1378 * latency value.
1379 */
1380
1381 static void vlv_update_drain_latency(struct drm_crtc *crtc)
1382 {
1383 struct drm_device *dev = crtc->dev;
1384 struct drm_i915_private *dev_priv = dev->dev_private;
1385 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1386 int pixel_size;
1387 int drain_latency;
1388 enum pipe pipe = intel_crtc->pipe;
1389 int plane_prec, prec_mult, plane_dl;
1390 const int high_precision = IS_CHERRYVIEW(dev) ?
1391 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_64;
1392
1393 plane_dl = I915_READ(VLV_DDL(pipe)) & ~(DDL_PLANE_PRECISION_HIGH |
1394 DRAIN_LATENCY_MASK | DDL_CURSOR_PRECISION_HIGH |
1395 (DRAIN_LATENCY_MASK << DDL_CURSOR_SHIFT));
1396
1397 if (!intel_crtc_active(crtc)) {
1398 I915_WRITE(VLV_DDL(pipe), plane_dl);
1399 return;
1400 }
1401
1402 /* Primary plane Drain Latency */
1403 pixel_size = crtc->primary->fb->bits_per_pixel / 8; /* BPP */
1404 if (vlv_compute_drain_latency(crtc, pixel_size, &prec_mult, &drain_latency)) {
1405 plane_prec = (prec_mult == high_precision) ?
1406 DDL_PLANE_PRECISION_HIGH :
1407 DDL_PLANE_PRECISION_LOW;
1408 plane_dl |= plane_prec | drain_latency;
1409 }
1410
1411 /* Cursor Drain Latency
1412 * BPP is always 4 for cursor
1413 */
1414 pixel_size = 4;
1415
1416 /* Program cursor DL only if it is enabled */
1417 if (intel_crtc->cursor_base &&
1418 vlv_compute_drain_latency(crtc, pixel_size, &prec_mult, &drain_latency)) {
1419 plane_prec = (prec_mult == high_precision) ?
1420 DDL_CURSOR_PRECISION_HIGH :
1421 DDL_CURSOR_PRECISION_LOW;
1422 plane_dl |= plane_prec | (drain_latency << DDL_CURSOR_SHIFT);
1423 }
1424
1425 I915_WRITE(VLV_DDL(pipe), plane_dl);
1426 }
1427
1428 #define single_plane_enabled(mask) is_power_of_2(mask)
1429
1430 static void valleyview_update_wm(struct drm_crtc *crtc)
1431 {
1432 struct drm_device *dev = crtc->dev;
1433 static const int sr_latency_ns = 12000;
1434 struct drm_i915_private *dev_priv = dev->dev_private;
1435 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1436 int plane_sr, cursor_sr;
1437 int ignore_plane_sr, ignore_cursor_sr;
1438 unsigned int enabled = 0;
1439 bool cxsr_enabled;
1440
1441 vlv_update_drain_latency(crtc);
1442
1443 if (g4x_compute_wm0(dev, PIPE_A,
1444 &valleyview_wm_info, pessimal_latency_ns,
1445 &valleyview_cursor_wm_info, pessimal_latency_ns,
1446 &planea_wm, &cursora_wm))
1447 enabled |= 1 << PIPE_A;
1448
1449 if (g4x_compute_wm0(dev, PIPE_B,
1450 &valleyview_wm_info, pessimal_latency_ns,
1451 &valleyview_cursor_wm_info, pessimal_latency_ns,
1452 &planeb_wm, &cursorb_wm))
1453 enabled |= 1 << PIPE_B;
1454
1455 if (single_plane_enabled(enabled) &&
1456 g4x_compute_srwm(dev, ffs(enabled) - 1,
1457 sr_latency_ns,
1458 &valleyview_wm_info,
1459 &valleyview_cursor_wm_info,
1460 &plane_sr, &ignore_cursor_sr) &&
1461 g4x_compute_srwm(dev, ffs(enabled) - 1,
1462 2*sr_latency_ns,
1463 &valleyview_wm_info,
1464 &valleyview_cursor_wm_info,
1465 &ignore_plane_sr, &cursor_sr)) {
1466 cxsr_enabled = true;
1467 } else {
1468 cxsr_enabled = false;
1469 intel_set_memory_cxsr(dev_priv, false);
1470 plane_sr = cursor_sr = 0;
1471 }
1472
1473 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1474 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1475 planea_wm, cursora_wm,
1476 planeb_wm, cursorb_wm,
1477 plane_sr, cursor_sr);
1478
1479 I915_WRITE(DSPFW1,
1480 (plane_sr << DSPFW_SR_SHIFT) |
1481 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1482 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1483 (planea_wm << DSPFW_PLANEA_SHIFT));
1484 I915_WRITE(DSPFW2,
1485 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1486 (cursora_wm << DSPFW_CURSORA_SHIFT));
1487 I915_WRITE(DSPFW3,
1488 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1489 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1490
1491 if (cxsr_enabled)
1492 intel_set_memory_cxsr(dev_priv, true);
1493 }
1494
1495 static void cherryview_update_wm(struct drm_crtc *crtc)
1496 {
1497 struct drm_device *dev = crtc->dev;
1498 static const int sr_latency_ns = 12000;
1499 struct drm_i915_private *dev_priv = dev->dev_private;
1500 int planea_wm, planeb_wm, planec_wm;
1501 int cursora_wm, cursorb_wm, cursorc_wm;
1502 int plane_sr, cursor_sr;
1503 int ignore_plane_sr, ignore_cursor_sr;
1504 unsigned int enabled = 0;
1505 bool cxsr_enabled;
1506
1507 vlv_update_drain_latency(crtc);
1508
1509 if (g4x_compute_wm0(dev, PIPE_A,
1510 &valleyview_wm_info, pessimal_latency_ns,
1511 &valleyview_cursor_wm_info, pessimal_latency_ns,
1512 &planea_wm, &cursora_wm))
1513 enabled |= 1 << PIPE_A;
1514
1515 if (g4x_compute_wm0(dev, PIPE_B,
1516 &valleyview_wm_info, pessimal_latency_ns,
1517 &valleyview_cursor_wm_info, pessimal_latency_ns,
1518 &planeb_wm, &cursorb_wm))
1519 enabled |= 1 << PIPE_B;
1520
1521 if (g4x_compute_wm0(dev, PIPE_C,
1522 &valleyview_wm_info, pessimal_latency_ns,
1523 &valleyview_cursor_wm_info, pessimal_latency_ns,
1524 &planec_wm, &cursorc_wm))
1525 enabled |= 1 << PIPE_C;
1526
1527 if (single_plane_enabled(enabled) &&
1528 g4x_compute_srwm(dev, ffs(enabled) - 1,
1529 sr_latency_ns,
1530 &valleyview_wm_info,
1531 &valleyview_cursor_wm_info,
1532 &plane_sr, &ignore_cursor_sr) &&
1533 g4x_compute_srwm(dev, ffs(enabled) - 1,
1534 2*sr_latency_ns,
1535 &valleyview_wm_info,
1536 &valleyview_cursor_wm_info,
1537 &ignore_plane_sr, &cursor_sr)) {
1538 cxsr_enabled = true;
1539 } else {
1540 cxsr_enabled = false;
1541 intel_set_memory_cxsr(dev_priv, false);
1542 plane_sr = cursor_sr = 0;
1543 }
1544
1545 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1546 "B: plane=%d, cursor=%d, C: plane=%d, cursor=%d, "
1547 "SR: plane=%d, cursor=%d\n",
1548 planea_wm, cursora_wm,
1549 planeb_wm, cursorb_wm,
1550 planec_wm, cursorc_wm,
1551 plane_sr, cursor_sr);
1552
1553 I915_WRITE(DSPFW1,
1554 (plane_sr << DSPFW_SR_SHIFT) |
1555 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1556 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1557 (planea_wm << DSPFW_PLANEA_SHIFT));
1558 I915_WRITE(DSPFW2,
1559 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1560 (cursora_wm << DSPFW_CURSORA_SHIFT));
1561 I915_WRITE(DSPFW3,
1562 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1563 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1564 I915_WRITE(DSPFW9_CHV,
1565 (I915_READ(DSPFW9_CHV) & ~(DSPFW_PLANEC_MASK |
1566 DSPFW_CURSORC_MASK)) |
1567 (planec_wm << DSPFW_PLANEC_SHIFT) |
1568 (cursorc_wm << DSPFW_CURSORC_SHIFT));
1569
1570 if (cxsr_enabled)
1571 intel_set_memory_cxsr(dev_priv, true);
1572 }
1573
1574 static void valleyview_update_sprite_wm(struct drm_plane *plane,
1575 struct drm_crtc *crtc,
1576 uint32_t sprite_width,
1577 uint32_t sprite_height,
1578 int pixel_size,
1579 bool enabled, bool scaled)
1580 {
1581 struct drm_device *dev = crtc->dev;
1582 struct drm_i915_private *dev_priv = dev->dev_private;
1583 int pipe = to_intel_plane(plane)->pipe;
1584 int sprite = to_intel_plane(plane)->plane;
1585 int drain_latency;
1586 int plane_prec;
1587 int sprite_dl;
1588 int prec_mult;
1589 const int high_precision = IS_CHERRYVIEW(dev) ?
1590 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_64;
1591
1592 sprite_dl = I915_READ(VLV_DDL(pipe)) & ~(DDL_SPRITE_PRECISION_HIGH(sprite) |
1593 (DRAIN_LATENCY_MASK << DDL_SPRITE_SHIFT(sprite)));
1594
1595 if (enabled && vlv_compute_drain_latency(crtc, pixel_size, &prec_mult,
1596 &drain_latency)) {
1597 plane_prec = (prec_mult == high_precision) ?
1598 DDL_SPRITE_PRECISION_HIGH(sprite) :
1599 DDL_SPRITE_PRECISION_LOW(sprite);
1600 sprite_dl |= plane_prec |
1601 (drain_latency << DDL_SPRITE_SHIFT(sprite));
1602 }
1603
1604 I915_WRITE(VLV_DDL(pipe), sprite_dl);
1605 }
1606
1607 static void g4x_update_wm(struct drm_crtc *crtc)
1608 {
1609 struct drm_device *dev = crtc->dev;
1610 static const int sr_latency_ns = 12000;
1611 struct drm_i915_private *dev_priv = dev->dev_private;
1612 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1613 int plane_sr, cursor_sr;
1614 unsigned int enabled = 0;
1615 bool cxsr_enabled;
1616
1617 if (g4x_compute_wm0(dev, PIPE_A,
1618 &g4x_wm_info, pessimal_latency_ns,
1619 &g4x_cursor_wm_info, pessimal_latency_ns,
1620 &planea_wm, &cursora_wm))
1621 enabled |= 1 << PIPE_A;
1622
1623 if (g4x_compute_wm0(dev, PIPE_B,
1624 &g4x_wm_info, pessimal_latency_ns,
1625 &g4x_cursor_wm_info, pessimal_latency_ns,
1626 &planeb_wm, &cursorb_wm))
1627 enabled |= 1 << PIPE_B;
1628
1629 if (single_plane_enabled(enabled) &&
1630 g4x_compute_srwm(dev, ffs(enabled) - 1,
1631 sr_latency_ns,
1632 &g4x_wm_info,
1633 &g4x_cursor_wm_info,
1634 &plane_sr, &cursor_sr)) {
1635 cxsr_enabled = true;
1636 } else {
1637 cxsr_enabled = false;
1638 intel_set_memory_cxsr(dev_priv, false);
1639 plane_sr = cursor_sr = 0;
1640 }
1641
1642 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1643 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1644 planea_wm, cursora_wm,
1645 planeb_wm, cursorb_wm,
1646 plane_sr, cursor_sr);
1647
1648 I915_WRITE(DSPFW1,
1649 (plane_sr << DSPFW_SR_SHIFT) |
1650 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1651 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1652 (planea_wm << DSPFW_PLANEA_SHIFT));
1653 I915_WRITE(DSPFW2,
1654 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1655 (cursora_wm << DSPFW_CURSORA_SHIFT));
1656 /* HPLL off in SR has some issues on G4x... disable it */
1657 I915_WRITE(DSPFW3,
1658 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1659 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1660
1661 if (cxsr_enabled)
1662 intel_set_memory_cxsr(dev_priv, true);
1663 }
1664
1665 static void i965_update_wm(struct drm_crtc *unused_crtc)
1666 {
1667 struct drm_device *dev = unused_crtc->dev;
1668 struct drm_i915_private *dev_priv = dev->dev_private;
1669 struct drm_crtc *crtc;
1670 int srwm = 1;
1671 int cursor_sr = 16;
1672 bool cxsr_enabled;
1673
1674 /* Calc sr entries for one plane configs */
1675 crtc = single_enabled_crtc(dev);
1676 if (crtc) {
1677 /* self-refresh has much higher latency */
1678 static const int sr_latency_ns = 12000;
1679 const struct drm_display_mode *adjusted_mode =
1680 &to_intel_crtc(crtc)->config.adjusted_mode;
1681 int clock = adjusted_mode->crtc_clock;
1682 int htotal = adjusted_mode->crtc_htotal;
1683 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1684 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1685 unsigned long line_time_us;
1686 int entries;
1687
1688 line_time_us = max(htotal * 1000 / clock, 1);
1689
1690 /* Use ns/us then divide to preserve precision */
1691 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1692 pixel_size * hdisplay;
1693 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1694 srwm = I965_FIFO_SIZE - entries;
1695 if (srwm < 0)
1696 srwm = 1;
1697 srwm &= 0x1ff;
1698 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1699 entries, srwm);
1700
1701 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1702 pixel_size * to_intel_crtc(crtc)->cursor_width;
1703 entries = DIV_ROUND_UP(entries,
1704 i965_cursor_wm_info.cacheline_size);
1705 cursor_sr = i965_cursor_wm_info.fifo_size -
1706 (entries + i965_cursor_wm_info.guard_size);
1707
1708 if (cursor_sr > i965_cursor_wm_info.max_wm)
1709 cursor_sr = i965_cursor_wm_info.max_wm;
1710
1711 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1712 "cursor %d\n", srwm, cursor_sr);
1713
1714 cxsr_enabled = true;
1715 } else {
1716 cxsr_enabled = false;
1717 /* Turn off self refresh if both pipes are enabled */
1718 intel_set_memory_cxsr(dev_priv, false);
1719 }
1720
1721 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1722 srwm);
1723
1724 /* 965 has limitations... */
1725 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1726 (8 << DSPFW_CURSORB_SHIFT) |
1727 (8 << DSPFW_PLANEB_SHIFT) |
1728 (8 << DSPFW_PLANEA_SHIFT));
1729 I915_WRITE(DSPFW2, (8 << DSPFW_CURSORA_SHIFT) |
1730 (8 << DSPFW_PLANEC_SHIFT_OLD));
1731 /* update cursor SR watermark */
1732 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1733
1734 if (cxsr_enabled)
1735 intel_set_memory_cxsr(dev_priv, true);
1736 }
1737
1738 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1739 {
1740 struct drm_device *dev = unused_crtc->dev;
1741 struct drm_i915_private *dev_priv = dev->dev_private;
1742 const struct intel_watermark_params *wm_info;
1743 uint32_t fwater_lo;
1744 uint32_t fwater_hi;
1745 int cwm, srwm = 1;
1746 int fifo_size;
1747 int planea_wm, planeb_wm;
1748 struct drm_crtc *crtc, *enabled = NULL;
1749
1750 if (IS_I945GM(dev))
1751 wm_info = &i945_wm_info;
1752 else if (!IS_GEN2(dev))
1753 wm_info = &i915_wm_info;
1754 else
1755 wm_info = &i830_a_wm_info;
1756
1757 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1758 crtc = intel_get_crtc_for_plane(dev, 0);
1759 if (intel_crtc_active(crtc)) {
1760 const struct drm_display_mode *adjusted_mode;
1761 int cpp = crtc->primary->fb->bits_per_pixel / 8;
1762 if (IS_GEN2(dev))
1763 cpp = 4;
1764
1765 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1766 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1767 wm_info, fifo_size, cpp,
1768 pessimal_latency_ns);
1769 enabled = crtc;
1770 } else {
1771 planea_wm = fifo_size - wm_info->guard_size;
1772 if (planea_wm > (long)wm_info->max_wm)
1773 planea_wm = wm_info->max_wm;
1774 }
1775
1776 if (IS_GEN2(dev))
1777 wm_info = &i830_bc_wm_info;
1778
1779 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1780 crtc = intel_get_crtc_for_plane(dev, 1);
1781 if (intel_crtc_active(crtc)) {
1782 const struct drm_display_mode *adjusted_mode;
1783 int cpp = crtc->primary->fb->bits_per_pixel / 8;
1784 if (IS_GEN2(dev))
1785 cpp = 4;
1786
1787 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1788 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1789 wm_info, fifo_size, cpp,
1790 pessimal_latency_ns);
1791 if (enabled == NULL)
1792 enabled = crtc;
1793 else
1794 enabled = NULL;
1795 } else {
1796 planeb_wm = fifo_size - wm_info->guard_size;
1797 if (planeb_wm > (long)wm_info->max_wm)
1798 planeb_wm = wm_info->max_wm;
1799 }
1800
1801 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1802
1803 if (IS_I915GM(dev) && enabled) {
1804 struct drm_i915_gem_object *obj;
1805
1806 obj = intel_fb_obj(enabled->primary->fb);
1807
1808 /* self-refresh seems busted with untiled */
1809 if (obj->tiling_mode == I915_TILING_NONE)
1810 enabled = NULL;
1811 }
1812
1813 /*
1814 * Overlay gets an aggressive default since video jitter is bad.
1815 */
1816 cwm = 2;
1817
1818 /* Play safe and disable self-refresh before adjusting watermarks. */
1819 intel_set_memory_cxsr(dev_priv, false);
1820
1821 /* Calc sr entries for one plane configs */
1822 if (HAS_FW_BLC(dev) && enabled) {
1823 /* self-refresh has much higher latency */
1824 static const int sr_latency_ns = 6000;
1825 const struct drm_display_mode *adjusted_mode =
1826 &to_intel_crtc(enabled)->config.adjusted_mode;
1827 int clock = adjusted_mode->crtc_clock;
1828 int htotal = adjusted_mode->crtc_htotal;
1829 int hdisplay = to_intel_crtc(enabled)->config.pipe_src_w;
1830 int pixel_size = enabled->primary->fb->bits_per_pixel / 8;
1831 unsigned long line_time_us;
1832 int entries;
1833
1834 line_time_us = max(htotal * 1000 / clock, 1);
1835
1836 /* Use ns/us then divide to preserve precision */
1837 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1838 pixel_size * hdisplay;
1839 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1840 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1841 srwm = wm_info->fifo_size - entries;
1842 if (srwm < 0)
1843 srwm = 1;
1844
1845 if (IS_I945G(dev) || IS_I945GM(dev))
1846 I915_WRITE(FW_BLC_SELF,
1847 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1848 else if (IS_I915GM(dev))
1849 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1850 }
1851
1852 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1853 planea_wm, planeb_wm, cwm, srwm);
1854
1855 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1856 fwater_hi = (cwm & 0x1f);
1857
1858 /* Set request length to 8 cachelines per fetch */
1859 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1860 fwater_hi = fwater_hi | (1 << 8);
1861
1862 I915_WRITE(FW_BLC, fwater_lo);
1863 I915_WRITE(FW_BLC2, fwater_hi);
1864
1865 if (enabled)
1866 intel_set_memory_cxsr(dev_priv, true);
1867 }
1868
1869 static void i845_update_wm(struct drm_crtc *unused_crtc)
1870 {
1871 struct drm_device *dev = unused_crtc->dev;
1872 struct drm_i915_private *dev_priv = dev->dev_private;
1873 struct drm_crtc *crtc;
1874 const struct drm_display_mode *adjusted_mode;
1875 uint32_t fwater_lo;
1876 int planea_wm;
1877
1878 crtc = single_enabled_crtc(dev);
1879 if (crtc == NULL)
1880 return;
1881
1882 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1883 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1884 &i845_wm_info,
1885 dev_priv->display.get_fifo_size(dev, 0),
1886 4, pessimal_latency_ns);
1887 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1888 fwater_lo |= (3<<8) | planea_wm;
1889
1890 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1891
1892 I915_WRITE(FW_BLC, fwater_lo);
1893 }
1894
1895 static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
1896 struct drm_crtc *crtc)
1897 {
1898 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1899 uint32_t pixel_rate;
1900
1901 pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock;
1902
1903 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1904 * adjust the pixel_rate here. */
1905
1906 if (intel_crtc->config.pch_pfit.enabled) {
1907 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1908 uint32_t pfit_size = intel_crtc->config.pch_pfit.size;
1909
1910 pipe_w = intel_crtc->config.pipe_src_w;
1911 pipe_h = intel_crtc->config.pipe_src_h;
1912 pfit_w = (pfit_size >> 16) & 0xFFFF;
1913 pfit_h = pfit_size & 0xFFFF;
1914 if (pipe_w < pfit_w)
1915 pipe_w = pfit_w;
1916 if (pipe_h < pfit_h)
1917 pipe_h = pfit_h;
1918
1919 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1920 pfit_w * pfit_h);
1921 }
1922
1923 return pixel_rate;
1924 }
1925
1926 /* latency must be in 0.1us units. */
1927 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
1928 uint32_t latency)
1929 {
1930 uint64_t ret;
1931
1932 if (WARN(latency == 0, "Latency value missing\n"))
1933 return UINT_MAX;
1934
1935 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1936 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1937
1938 return ret;
1939 }
1940
1941 /* latency must be in 0.1us units. */
1942 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1943 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1944 uint32_t latency)
1945 {
1946 uint32_t ret;
1947
1948 if (WARN(latency == 0, "Latency value missing\n"))
1949 return UINT_MAX;
1950
1951 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1952 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1953 ret = DIV_ROUND_UP(ret, 64) + 2;
1954 return ret;
1955 }
1956
1957 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1958 uint8_t bytes_per_pixel)
1959 {
1960 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1961 }
1962
1963 struct skl_pipe_wm_parameters {
1964 bool active;
1965 uint32_t pipe_htotal;
1966 uint32_t pixel_rate; /* in KHz */
1967 struct intel_plane_wm_parameters plane[I915_MAX_PLANES];
1968 struct intel_plane_wm_parameters cursor;
1969 };
1970
1971 struct ilk_pipe_wm_parameters {
1972 bool active;
1973 uint32_t pipe_htotal;
1974 uint32_t pixel_rate;
1975 struct intel_plane_wm_parameters pri;
1976 struct intel_plane_wm_parameters spr;
1977 struct intel_plane_wm_parameters cur;
1978 };
1979
1980 struct ilk_wm_maximums {
1981 uint16_t pri;
1982 uint16_t spr;
1983 uint16_t cur;
1984 uint16_t fbc;
1985 };
1986
1987 /* used in computing the new watermarks state */
1988 struct intel_wm_config {
1989 unsigned int num_pipes_active;
1990 bool sprites_enabled;
1991 bool sprites_scaled;
1992 };
1993
1994 /*
1995 * For both WM_PIPE and WM_LP.
1996 * mem_value must be in 0.1us units.
1997 */
1998 static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params,
1999 uint32_t mem_value,
2000 bool is_lp)
2001 {
2002 uint32_t method1, method2;
2003
2004 if (!params->active || !params->pri.enabled)
2005 return 0;
2006
2007 method1 = ilk_wm_method1(params->pixel_rate,
2008 params->pri.bytes_per_pixel,
2009 mem_value);
2010
2011 if (!is_lp)
2012 return method1;
2013
2014 method2 = ilk_wm_method2(params->pixel_rate,
2015 params->pipe_htotal,
2016 params->pri.horiz_pixels,
2017 params->pri.bytes_per_pixel,
2018 mem_value);
2019
2020 return min(method1, method2);
2021 }
2022
2023 /*
2024 * For both WM_PIPE and WM_LP.
2025 * mem_value must be in 0.1us units.
2026 */
2027 static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params,
2028 uint32_t mem_value)
2029 {
2030 uint32_t method1, method2;
2031
2032 if (!params->active || !params->spr.enabled)
2033 return 0;
2034
2035 method1 = ilk_wm_method1(params->pixel_rate,
2036 params->spr.bytes_per_pixel,
2037 mem_value);
2038 method2 = ilk_wm_method2(params->pixel_rate,
2039 params->pipe_htotal,
2040 params->spr.horiz_pixels,
2041 params->spr.bytes_per_pixel,
2042 mem_value);
2043 return min(method1, method2);
2044 }
2045
2046 /*
2047 * For both WM_PIPE and WM_LP.
2048 * mem_value must be in 0.1us units.
2049 */
2050 static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params,
2051 uint32_t mem_value)
2052 {
2053 if (!params->active || !params->cur.enabled)
2054 return 0;
2055
2056 return ilk_wm_method2(params->pixel_rate,
2057 params->pipe_htotal,
2058 params->cur.horiz_pixels,
2059 params->cur.bytes_per_pixel,
2060 mem_value);
2061 }
2062
2063 /* Only for WM_LP. */
2064 static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params,
2065 uint32_t pri_val)
2066 {
2067 if (!params->active || !params->pri.enabled)
2068 return 0;
2069
2070 return ilk_wm_fbc(pri_val,
2071 params->pri.horiz_pixels,
2072 params->pri.bytes_per_pixel);
2073 }
2074
2075 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
2076 {
2077 if (INTEL_INFO(dev)->gen >= 8)
2078 return 3072;
2079 else if (INTEL_INFO(dev)->gen >= 7)
2080 return 768;
2081 else
2082 return 512;
2083 }
2084
2085 static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
2086 int level, bool is_sprite)
2087 {
2088 if (INTEL_INFO(dev)->gen >= 8)
2089 /* BDW primary/sprite plane watermarks */
2090 return level == 0 ? 255 : 2047;
2091 else if (INTEL_INFO(dev)->gen >= 7)
2092 /* IVB/HSW primary/sprite plane watermarks */
2093 return level == 0 ? 127 : 1023;
2094 else if (!is_sprite)
2095 /* ILK/SNB primary plane watermarks */
2096 return level == 0 ? 127 : 511;
2097 else
2098 /* ILK/SNB sprite plane watermarks */
2099 return level == 0 ? 63 : 255;
2100 }
2101
2102 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
2103 int level)
2104 {
2105 if (INTEL_INFO(dev)->gen >= 7)
2106 return level == 0 ? 63 : 255;
2107 else
2108 return level == 0 ? 31 : 63;
2109 }
2110
2111 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
2112 {
2113 if (INTEL_INFO(dev)->gen >= 8)
2114 return 31;
2115 else
2116 return 15;
2117 }
2118
2119 /* Calculate the maximum primary/sprite plane watermark */
2120 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
2121 int level,
2122 const struct intel_wm_config *config,
2123 enum intel_ddb_partitioning ddb_partitioning,
2124 bool is_sprite)
2125 {
2126 unsigned int fifo_size = ilk_display_fifo_size(dev);
2127
2128 /* if sprites aren't enabled, sprites get nothing */
2129 if (is_sprite && !config->sprites_enabled)
2130 return 0;
2131
2132 /* HSW allows LP1+ watermarks even with multiple pipes */
2133 if (level == 0 || config->num_pipes_active > 1) {
2134 fifo_size /= INTEL_INFO(dev)->num_pipes;
2135
2136 /*
2137 * For some reason the non self refresh
2138 * FIFO size is only half of the self
2139 * refresh FIFO size on ILK/SNB.
2140 */
2141 if (INTEL_INFO(dev)->gen <= 6)
2142 fifo_size /= 2;
2143 }
2144
2145 if (config->sprites_enabled) {
2146 /* level 0 is always calculated with 1:1 split */
2147 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
2148 if (is_sprite)
2149 fifo_size *= 5;
2150 fifo_size /= 6;
2151 } else {
2152 fifo_size /= 2;
2153 }
2154 }
2155
2156 /* clamp to max that the registers can hold */
2157 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
2158 }
2159
2160 /* Calculate the maximum cursor plane watermark */
2161 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
2162 int level,
2163 const struct intel_wm_config *config)
2164 {
2165 /* HSW LP1+ watermarks w/ multiple pipes */
2166 if (level > 0 && config->num_pipes_active > 1)
2167 return 64;
2168
2169 /* otherwise just report max that registers can hold */
2170 return ilk_cursor_wm_reg_max(dev, level);
2171 }
2172
2173 static void ilk_compute_wm_maximums(const struct drm_device *dev,
2174 int level,
2175 const struct intel_wm_config *config,
2176 enum intel_ddb_partitioning ddb_partitioning,
2177 struct ilk_wm_maximums *max)
2178 {
2179 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
2180 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
2181 max->cur = ilk_cursor_wm_max(dev, level, config);
2182 max->fbc = ilk_fbc_wm_reg_max(dev);
2183 }
2184
2185 static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
2186 int level,
2187 struct ilk_wm_maximums *max)
2188 {
2189 max->pri = ilk_plane_wm_reg_max(dev, level, false);
2190 max->spr = ilk_plane_wm_reg_max(dev, level, true);
2191 max->cur = ilk_cursor_wm_reg_max(dev, level);
2192 max->fbc = ilk_fbc_wm_reg_max(dev);
2193 }
2194
2195 static bool ilk_validate_wm_level(int level,
2196 const struct ilk_wm_maximums *max,
2197 struct intel_wm_level *result)
2198 {
2199 bool ret;
2200
2201 /* already determined to be invalid? */
2202 if (!result->enable)
2203 return false;
2204
2205 result->enable = result->pri_val <= max->pri &&
2206 result->spr_val <= max->spr &&
2207 result->cur_val <= max->cur;
2208
2209 ret = result->enable;
2210
2211 /*
2212 * HACK until we can pre-compute everything,
2213 * and thus fail gracefully if LP0 watermarks
2214 * are exceeded...
2215 */
2216 if (level == 0 && !result->enable) {
2217 if (result->pri_val > max->pri)
2218 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2219 level, result->pri_val, max->pri);
2220 if (result->spr_val > max->spr)
2221 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2222 level, result->spr_val, max->spr);
2223 if (result->cur_val > max->cur)
2224 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2225 level, result->cur_val, max->cur);
2226
2227 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2228 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2229 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2230 result->enable = true;
2231 }
2232
2233 return ret;
2234 }
2235
2236 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
2237 int level,
2238 const struct ilk_pipe_wm_parameters *p,
2239 struct intel_wm_level *result)
2240 {
2241 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2242 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2243 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2244
2245 /* WM1+ latency values stored in 0.5us units */
2246 if (level > 0) {
2247 pri_latency *= 5;
2248 spr_latency *= 5;
2249 cur_latency *= 5;
2250 }
2251
2252 result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
2253 result->spr_val = ilk_compute_spr_wm(p, spr_latency);
2254 result->cur_val = ilk_compute_cur_wm(p, cur_latency);
2255 result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
2256 result->enable = true;
2257 }
2258
2259 static uint32_t
2260 hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
2261 {
2262 struct drm_i915_private *dev_priv = dev->dev_private;
2263 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2264 struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
2265 u32 linetime, ips_linetime;
2266
2267 if (!intel_crtc_active(crtc))
2268 return 0;
2269
2270 /* The WM are computed with base on how long it takes to fill a single
2271 * row at the given clock rate, multiplied by 8.
2272 * */
2273 linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
2274 mode->crtc_clock);
2275 ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
2276 intel_ddi_get_cdclk_freq(dev_priv));
2277
2278 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2279 PIPE_WM_LINETIME_TIME(linetime);
2280 }
2281
2282 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
2283 {
2284 struct drm_i915_private *dev_priv = dev->dev_private;
2285
2286 if (IS_GEN9(dev)) {
2287 uint32_t val;
2288 int ret, i;
2289 int level, max_level = ilk_wm_max_level(dev);
2290
2291 /* read the first set of memory latencies[0:3] */
2292 val = 0; /* data0 to be programmed to 0 for first set */
2293 mutex_lock(&dev_priv->rps.hw_lock);
2294 ret = sandybridge_pcode_read(dev_priv,
2295 GEN9_PCODE_READ_MEM_LATENCY,
2296 &val);
2297 mutex_unlock(&dev_priv->rps.hw_lock);
2298
2299 if (ret) {
2300 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2301 return;
2302 }
2303
2304 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2305 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2306 GEN9_MEM_LATENCY_LEVEL_MASK;
2307 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2308 GEN9_MEM_LATENCY_LEVEL_MASK;
2309 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2310 GEN9_MEM_LATENCY_LEVEL_MASK;
2311
2312 /* read the second set of memory latencies[4:7] */
2313 val = 1; /* data0 to be programmed to 1 for second set */
2314 mutex_lock(&dev_priv->rps.hw_lock);
2315 ret = sandybridge_pcode_read(dev_priv,
2316 GEN9_PCODE_READ_MEM_LATENCY,
2317 &val);
2318 mutex_unlock(&dev_priv->rps.hw_lock);
2319 if (ret) {
2320 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2321 return;
2322 }
2323
2324 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2325 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2326 GEN9_MEM_LATENCY_LEVEL_MASK;
2327 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2328 GEN9_MEM_LATENCY_LEVEL_MASK;
2329 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2330 GEN9_MEM_LATENCY_LEVEL_MASK;
2331
2332 /*
2333 * punit doesn't take into account the read latency so we need
2334 * to add 2us to the various latency levels we retrieve from
2335 * the punit.
2336 * - W0 is a bit special in that it's the only level that
2337 * can't be disabled if we want to have display working, so
2338 * we always add 2us there.
2339 * - For levels >=1, punit returns 0us latency when they are
2340 * disabled, so we respect that and don't add 2us then
2341 *
2342 * Additionally, if a level n (n > 1) has a 0us latency, all
2343 * levels m (m >= n) need to be disabled. We make sure to
2344 * sanitize the values out of the punit to satisfy this
2345 * requirement.
2346 */
2347 wm[0] += 2;
2348 for (level = 1; level <= max_level; level++)
2349 if (wm[level] != 0)
2350 wm[level] += 2;
2351 else {
2352 for (i = level + 1; i <= max_level; i++)
2353 wm[i] = 0;
2354
2355 break;
2356 }
2357 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2358 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2359
2360 wm[0] = (sskpd >> 56) & 0xFF;
2361 if (wm[0] == 0)
2362 wm[0] = sskpd & 0xF;
2363 wm[1] = (sskpd >> 4) & 0xFF;
2364 wm[2] = (sskpd >> 12) & 0xFF;
2365 wm[3] = (sskpd >> 20) & 0x1FF;
2366 wm[4] = (sskpd >> 32) & 0x1FF;
2367 } else if (INTEL_INFO(dev)->gen >= 6) {
2368 uint32_t sskpd = I915_READ(MCH_SSKPD);
2369
2370 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2371 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2372 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2373 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2374 } else if (INTEL_INFO(dev)->gen >= 5) {
2375 uint32_t mltr = I915_READ(MLTR_ILK);
2376
2377 /* ILK primary LP0 latency is 700 ns */
2378 wm[0] = 7;
2379 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2380 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2381 }
2382 }
2383
2384 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2385 {
2386 /* ILK sprite LP0 latency is 1300 ns */
2387 if (INTEL_INFO(dev)->gen == 5)
2388 wm[0] = 13;
2389 }
2390
2391 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2392 {
2393 /* ILK cursor LP0 latency is 1300 ns */
2394 if (INTEL_INFO(dev)->gen == 5)
2395 wm[0] = 13;
2396
2397 /* WaDoubleCursorLP3Latency:ivb */
2398 if (IS_IVYBRIDGE(dev))
2399 wm[3] *= 2;
2400 }
2401
2402 int ilk_wm_max_level(const struct drm_device *dev)
2403 {
2404 /* how many WM levels are we expecting */
2405 if (IS_GEN9(dev))
2406 return 7;
2407 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2408 return 4;
2409 else if (INTEL_INFO(dev)->gen >= 6)
2410 return 3;
2411 else
2412 return 2;
2413 }
2414
2415 static void intel_print_wm_latency(struct drm_device *dev,
2416 const char *name,
2417 const uint16_t wm[8])
2418 {
2419 int level, max_level = ilk_wm_max_level(dev);
2420
2421 for (level = 0; level <= max_level; level++) {
2422 unsigned int latency = wm[level];
2423
2424 if (latency == 0) {
2425 DRM_ERROR("%s WM%d latency not provided\n",
2426 name, level);
2427 continue;
2428 }
2429
2430 /*
2431 * - latencies are in us on gen9.
2432 * - before then, WM1+ latency values are in 0.5us units
2433 */
2434 if (IS_GEN9(dev))
2435 latency *= 10;
2436 else if (level > 0)
2437 latency *= 5;
2438
2439 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2440 name, level, wm[level],
2441 latency / 10, latency % 10);
2442 }
2443 }
2444
2445 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2446 uint16_t wm[5], uint16_t min)
2447 {
2448 int level, max_level = ilk_wm_max_level(dev_priv->dev);
2449
2450 if (wm[0] >= min)
2451 return false;
2452
2453 wm[0] = max(wm[0], min);
2454 for (level = 1; level <= max_level; level++)
2455 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2456
2457 return true;
2458 }
2459
2460 static void snb_wm_latency_quirk(struct drm_device *dev)
2461 {
2462 struct drm_i915_private *dev_priv = dev->dev_private;
2463 bool changed;
2464
2465 /*
2466 * The BIOS provided WM memory latency values are often
2467 * inadequate for high resolution displays. Adjust them.
2468 */
2469 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2470 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2471 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2472
2473 if (!changed)
2474 return;
2475
2476 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2477 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2478 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2479 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2480 }
2481
2482 static void ilk_setup_wm_latency(struct drm_device *dev)
2483 {
2484 struct drm_i915_private *dev_priv = dev->dev_private;
2485
2486 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2487
2488 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2489 sizeof(dev_priv->wm.pri_latency));
2490 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2491 sizeof(dev_priv->wm.pri_latency));
2492
2493 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2494 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2495
2496 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2497 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2498 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2499
2500 if (IS_GEN6(dev))
2501 snb_wm_latency_quirk(dev);
2502 }
2503
2504 static void skl_setup_wm_latency(struct drm_device *dev)
2505 {
2506 struct drm_i915_private *dev_priv = dev->dev_private;
2507
2508 intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2509 intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2510 }
2511
2512 static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
2513 struct ilk_pipe_wm_parameters *p)
2514 {
2515 struct drm_device *dev = crtc->dev;
2516 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2517 enum pipe pipe = intel_crtc->pipe;
2518 struct drm_plane *plane;
2519
2520 if (!intel_crtc_active(crtc))
2521 return;
2522
2523 p->active = true;
2524 p->pipe_htotal = intel_crtc->config.adjusted_mode.crtc_htotal;
2525 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
2526 p->pri.bytes_per_pixel = crtc->primary->fb->bits_per_pixel / 8;
2527 p->cur.bytes_per_pixel = 4;
2528 p->pri.horiz_pixels = intel_crtc->config.pipe_src_w;
2529 p->cur.horiz_pixels = intel_crtc->cursor_width;
2530 /* TODO: for now, assume primary and cursor planes are always enabled. */
2531 p->pri.enabled = true;
2532 p->cur.enabled = true;
2533
2534 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
2535 struct intel_plane *intel_plane = to_intel_plane(plane);
2536
2537 if (intel_plane->pipe == pipe) {
2538 p->spr = intel_plane->wm;
2539 break;
2540 }
2541 }
2542 }
2543
2544 static void ilk_compute_wm_config(struct drm_device *dev,
2545 struct intel_wm_config *config)
2546 {
2547 struct intel_crtc *intel_crtc;
2548
2549 /* Compute the currently _active_ config */
2550 for_each_intel_crtc(dev, intel_crtc) {
2551 const struct intel_pipe_wm *wm = &intel_crtc->wm.active;
2552
2553 if (!wm->pipe_enabled)
2554 continue;
2555
2556 config->sprites_enabled |= wm->sprites_enabled;
2557 config->sprites_scaled |= wm->sprites_scaled;
2558 config->num_pipes_active++;
2559 }
2560 }
2561
2562 /* Compute new watermarks for the pipe */
2563 static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
2564 const struct ilk_pipe_wm_parameters *params,
2565 struct intel_pipe_wm *pipe_wm)
2566 {
2567 struct drm_device *dev = crtc->dev;
2568 const struct drm_i915_private *dev_priv = dev->dev_private;
2569 int level, max_level = ilk_wm_max_level(dev);
2570 /* LP0 watermark maximums depend on this pipe alone */
2571 struct intel_wm_config config = {
2572 .num_pipes_active = 1,
2573 .sprites_enabled = params->spr.enabled,
2574 .sprites_scaled = params->spr.scaled,
2575 };
2576 struct ilk_wm_maximums max;
2577
2578 pipe_wm->pipe_enabled = params->active;
2579 pipe_wm->sprites_enabled = params->spr.enabled;
2580 pipe_wm->sprites_scaled = params->spr.scaled;
2581
2582 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2583 if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled)
2584 max_level = 1;
2585
2586 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2587 if (params->spr.scaled)
2588 max_level = 0;
2589
2590 ilk_compute_wm_level(dev_priv, 0, params, &pipe_wm->wm[0]);
2591
2592 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2593 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
2594
2595 /* LP0 watermarks always use 1/2 DDB partitioning */
2596 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2597
2598 /* At least LP0 must be valid */
2599 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
2600 return false;
2601
2602 ilk_compute_wm_reg_maximums(dev, 1, &max);
2603
2604 for (level = 1; level <= max_level; level++) {
2605 struct intel_wm_level wm = {};
2606
2607 ilk_compute_wm_level(dev_priv, level, params, &wm);
2608
2609 /*
2610 * Disable any watermark level that exceeds the
2611 * register maximums since such watermarks are
2612 * always invalid.
2613 */
2614 if (!ilk_validate_wm_level(level, &max, &wm))
2615 break;
2616
2617 pipe_wm->wm[level] = wm;
2618 }
2619
2620 return true;
2621 }
2622
2623 /*
2624 * Merge the watermarks from all active pipes for a specific level.
2625 */
2626 static void ilk_merge_wm_level(struct drm_device *dev,
2627 int level,
2628 struct intel_wm_level *ret_wm)
2629 {
2630 const struct intel_crtc *intel_crtc;
2631
2632 ret_wm->enable = true;
2633
2634 for_each_intel_crtc(dev, intel_crtc) {
2635 const struct intel_pipe_wm *active = &intel_crtc->wm.active;
2636 const struct intel_wm_level *wm = &active->wm[level];
2637
2638 if (!active->pipe_enabled)
2639 continue;
2640
2641 /*
2642 * The watermark values may have been used in the past,
2643 * so we must maintain them in the registers for some
2644 * time even if the level is now disabled.
2645 */
2646 if (!wm->enable)
2647 ret_wm->enable = false;
2648
2649 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2650 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2651 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2652 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2653 }
2654 }
2655
2656 /*
2657 * Merge all low power watermarks for all active pipes.
2658 */
2659 static void ilk_wm_merge(struct drm_device *dev,
2660 const struct intel_wm_config *config,
2661 const struct ilk_wm_maximums *max,
2662 struct intel_pipe_wm *merged)
2663 {
2664 int level, max_level = ilk_wm_max_level(dev);
2665 int last_enabled_level = max_level;
2666
2667 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2668 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2669 config->num_pipes_active > 1)
2670 return;
2671
2672 /* ILK: FBC WM must be disabled always */
2673 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
2674
2675 /* merge each WM1+ level */
2676 for (level = 1; level <= max_level; level++) {
2677 struct intel_wm_level *wm = &merged->wm[level];
2678
2679 ilk_merge_wm_level(dev, level, wm);
2680
2681 if (level > last_enabled_level)
2682 wm->enable = false;
2683 else if (!ilk_validate_wm_level(level, max, wm))
2684 /* make sure all following levels get disabled */
2685 last_enabled_level = level - 1;
2686
2687 /*
2688 * The spec says it is preferred to disable
2689 * FBC WMs instead of disabling a WM level.
2690 */
2691 if (wm->fbc_val > max->fbc) {
2692 if (wm->enable)
2693 merged->fbc_wm_enabled = false;
2694 wm->fbc_val = 0;
2695 }
2696 }
2697
2698 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2699 /*
2700 * FIXME this is racy. FBC might get enabled later.
2701 * What we should check here is whether FBC can be
2702 * enabled sometime later.
2703 */
2704 if (IS_GEN5(dev) && !merged->fbc_wm_enabled && intel_fbc_enabled(dev)) {
2705 for (level = 2; level <= max_level; level++) {
2706 struct intel_wm_level *wm = &merged->wm[level];
2707
2708 wm->enable = false;
2709 }
2710 }
2711 }
2712
2713 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2714 {
2715 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2716 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2717 }
2718
2719 /* The value we need to program into the WM_LPx latency field */
2720 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2721 {
2722 struct drm_i915_private *dev_priv = dev->dev_private;
2723
2724 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2725 return 2 * level;
2726 else
2727 return dev_priv->wm.pri_latency[level];
2728 }
2729
2730 static void ilk_compute_wm_results(struct drm_device *dev,
2731 const struct intel_pipe_wm *merged,
2732 enum intel_ddb_partitioning partitioning,
2733 struct ilk_wm_values *results)
2734 {
2735 struct intel_crtc *intel_crtc;
2736 int level, wm_lp;
2737
2738 results->enable_fbc_wm = merged->fbc_wm_enabled;
2739 results->partitioning = partitioning;
2740
2741 /* LP1+ register values */
2742 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2743 const struct intel_wm_level *r;
2744
2745 level = ilk_wm_lp_to_level(wm_lp, merged);
2746
2747 r = &merged->wm[level];
2748
2749 /*
2750 * Maintain the watermark values even if the level is
2751 * disabled. Doing otherwise could cause underruns.
2752 */
2753 results->wm_lp[wm_lp - 1] =
2754 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2755 (r->pri_val << WM1_LP_SR_SHIFT) |
2756 r->cur_val;
2757
2758 if (r->enable)
2759 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2760
2761 if (INTEL_INFO(dev)->gen >= 8)
2762 results->wm_lp[wm_lp - 1] |=
2763 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2764 else
2765 results->wm_lp[wm_lp - 1] |=
2766 r->fbc_val << WM1_LP_FBC_SHIFT;
2767
2768 /*
2769 * Always set WM1S_LP_EN when spr_val != 0, even if the
2770 * level is disabled. Doing otherwise could cause underruns.
2771 */
2772 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2773 WARN_ON(wm_lp != 1);
2774 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2775 } else
2776 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2777 }
2778
2779 /* LP0 register values */
2780 for_each_intel_crtc(dev, intel_crtc) {
2781 enum pipe pipe = intel_crtc->pipe;
2782 const struct intel_wm_level *r =
2783 &intel_crtc->wm.active.wm[0];
2784
2785 if (WARN_ON(!r->enable))
2786 continue;
2787
2788 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
2789
2790 results->wm_pipe[pipe] =
2791 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2792 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2793 r->cur_val;
2794 }
2795 }
2796
2797 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2798 * case both are at the same level. Prefer r1 in case they're the same. */
2799 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2800 struct intel_pipe_wm *r1,
2801 struct intel_pipe_wm *r2)
2802 {
2803 int level, max_level = ilk_wm_max_level(dev);
2804 int level1 = 0, level2 = 0;
2805
2806 for (level = 1; level <= max_level; level++) {
2807 if (r1->wm[level].enable)
2808 level1 = level;
2809 if (r2->wm[level].enable)
2810 level2 = level;
2811 }
2812
2813 if (level1 == level2) {
2814 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2815 return r2;
2816 else
2817 return r1;
2818 } else if (level1 > level2) {
2819 return r1;
2820 } else {
2821 return r2;
2822 }
2823 }
2824
2825 /* dirty bits used to track which watermarks need changes */
2826 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2827 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2828 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2829 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2830 #define WM_DIRTY_FBC (1 << 24)
2831 #define WM_DIRTY_DDB (1 << 25)
2832
2833 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
2834 const struct ilk_wm_values *old,
2835 const struct ilk_wm_values *new)
2836 {
2837 unsigned int dirty = 0;
2838 enum pipe pipe;
2839 int wm_lp;
2840
2841 for_each_pipe(dev_priv, pipe) {
2842 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2843 dirty |= WM_DIRTY_LINETIME(pipe);
2844 /* Must disable LP1+ watermarks too */
2845 dirty |= WM_DIRTY_LP_ALL;
2846 }
2847
2848 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2849 dirty |= WM_DIRTY_PIPE(pipe);
2850 /* Must disable LP1+ watermarks too */
2851 dirty |= WM_DIRTY_LP_ALL;
2852 }
2853 }
2854
2855 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2856 dirty |= WM_DIRTY_FBC;
2857 /* Must disable LP1+ watermarks too */
2858 dirty |= WM_DIRTY_LP_ALL;
2859 }
2860
2861 if (old->partitioning != new->partitioning) {
2862 dirty |= WM_DIRTY_DDB;
2863 /* Must disable LP1+ watermarks too */
2864 dirty |= WM_DIRTY_LP_ALL;
2865 }
2866
2867 /* LP1+ watermarks already deemed dirty, no need to continue */
2868 if (dirty & WM_DIRTY_LP_ALL)
2869 return dirty;
2870
2871 /* Find the lowest numbered LP1+ watermark in need of an update... */
2872 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2873 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2874 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2875 break;
2876 }
2877
2878 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2879 for (; wm_lp <= 3; wm_lp++)
2880 dirty |= WM_DIRTY_LP(wm_lp);
2881
2882 return dirty;
2883 }
2884
2885 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2886 unsigned int dirty)
2887 {
2888 struct ilk_wm_values *previous = &dev_priv->wm.hw;
2889 bool changed = false;
2890
2891 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2892 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2893 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2894 changed = true;
2895 }
2896 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2897 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2898 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2899 changed = true;
2900 }
2901 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2902 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2903 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2904 changed = true;
2905 }
2906
2907 /*
2908 * Don't touch WM1S_LP_EN here.
2909 * Doing so could cause underruns.
2910 */
2911
2912 return changed;
2913 }
2914
2915 /*
2916 * The spec says we shouldn't write when we don't need, because every write
2917 * causes WMs to be re-evaluated, expending some power.
2918 */
2919 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2920 struct ilk_wm_values *results)
2921 {
2922 struct drm_device *dev = dev_priv->dev;
2923 struct ilk_wm_values *previous = &dev_priv->wm.hw;
2924 unsigned int dirty;
2925 uint32_t val;
2926
2927 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
2928 if (!dirty)
2929 return;
2930
2931 _ilk_disable_lp_wm(dev_priv, dirty);
2932
2933 if (dirty & WM_DIRTY_PIPE(PIPE_A))
2934 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2935 if (dirty & WM_DIRTY_PIPE(PIPE_B))
2936 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2937 if (dirty & WM_DIRTY_PIPE(PIPE_C))
2938 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2939
2940 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2941 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2942 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2943 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2944 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2945 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2946
2947 if (dirty & WM_DIRTY_DDB) {
2948 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2949 val = I915_READ(WM_MISC);
2950 if (results->partitioning == INTEL_DDB_PART_1_2)
2951 val &= ~WM_MISC_DATA_PARTITION_5_6;
2952 else
2953 val |= WM_MISC_DATA_PARTITION_5_6;
2954 I915_WRITE(WM_MISC, val);
2955 } else {
2956 val = I915_READ(DISP_ARB_CTL2);
2957 if (results->partitioning == INTEL_DDB_PART_1_2)
2958 val &= ~DISP_DATA_PARTITION_5_6;
2959 else
2960 val |= DISP_DATA_PARTITION_5_6;
2961 I915_WRITE(DISP_ARB_CTL2, val);
2962 }
2963 }
2964
2965 if (dirty & WM_DIRTY_FBC) {
2966 val = I915_READ(DISP_ARB_CTL);
2967 if (results->enable_fbc_wm)
2968 val &= ~DISP_FBC_WM_DIS;
2969 else
2970 val |= DISP_FBC_WM_DIS;
2971 I915_WRITE(DISP_ARB_CTL, val);
2972 }
2973
2974 if (dirty & WM_DIRTY_LP(1) &&
2975 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2976 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2977
2978 if (INTEL_INFO(dev)->gen >= 7) {
2979 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2980 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2981 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2982 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2983 }
2984
2985 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2986 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2987 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2988 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2989 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2990 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2991
2992 dev_priv->wm.hw = *results;
2993 }
2994
2995 static bool ilk_disable_lp_wm(struct drm_device *dev)
2996 {
2997 struct drm_i915_private *dev_priv = dev->dev_private;
2998
2999 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
3000 }
3001
3002 /*
3003 * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
3004 * different active planes.
3005 */
3006
3007 #define SKL_DDB_SIZE 896 /* in blocks */
3008
3009 static void
3010 skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
3011 struct drm_crtc *for_crtc,
3012 const struct intel_wm_config *config,
3013 const struct skl_pipe_wm_parameters *params,
3014 struct skl_ddb_entry *alloc /* out */)
3015 {
3016 struct drm_crtc *crtc;
3017 unsigned int pipe_size, ddb_size;
3018 int nth_active_pipe;
3019
3020 if (!params->active) {
3021 alloc->start = 0;
3022 alloc->end = 0;
3023 return;
3024 }
3025
3026 ddb_size = SKL_DDB_SIZE;
3027
3028 ddb_size -= 4; /* 4 blocks for bypass path allocation */
3029
3030 nth_active_pipe = 0;
3031 for_each_crtc(dev, crtc) {
3032 if (!intel_crtc_active(crtc))
3033 continue;
3034
3035 if (crtc == for_crtc)
3036 break;
3037
3038 nth_active_pipe++;
3039 }
3040
3041 pipe_size = ddb_size / config->num_pipes_active;
3042 alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active;
3043 alloc->end = alloc->start + pipe_size;
3044 }
3045
3046 static unsigned int skl_cursor_allocation(const struct intel_wm_config *config)
3047 {
3048 if (config->num_pipes_active == 1)
3049 return 32;
3050
3051 return 8;
3052 }
3053
3054 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
3055 {
3056 entry->start = reg & 0x3ff;
3057 entry->end = (reg >> 16) & 0x3ff;
3058 if (entry->end)
3059 entry->end += 1;
3060 }
3061
3062 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
3063 struct skl_ddb_allocation *ddb /* out */)
3064 {
3065 struct drm_device *dev = dev_priv->dev;
3066 enum pipe pipe;
3067 int plane;
3068 u32 val;
3069
3070 for_each_pipe(dev_priv, pipe) {
3071 for_each_plane(pipe, plane) {
3072 val = I915_READ(PLANE_BUF_CFG(pipe, plane));
3073 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
3074 val);
3075 }
3076
3077 val = I915_READ(CUR_BUF_CFG(pipe));
3078 skl_ddb_entry_init_from_hw(&ddb->cursor[pipe], val);
3079 }
3080 }
3081
3082 static unsigned int
3083 skl_plane_relative_data_rate(const struct intel_plane_wm_parameters *p)
3084 {
3085 return p->horiz_pixels * p->vert_pixels * p->bytes_per_pixel;
3086 }
3087
3088 /*
3089 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
3090 * a 8192x4096@32bpp framebuffer:
3091 * 3 * 4096 * 8192 * 4 < 2^32
3092 */
3093 static unsigned int
3094 skl_get_total_relative_data_rate(struct intel_crtc *intel_crtc,
3095 const struct skl_pipe_wm_parameters *params)
3096 {
3097 unsigned int total_data_rate = 0;
3098 int plane;
3099
3100 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
3101 const struct intel_plane_wm_parameters *p;
3102
3103 p = &params->plane[plane];
3104 if (!p->enabled)
3105 continue;
3106
3107 total_data_rate += skl_plane_relative_data_rate(p);
3108 }
3109
3110 return total_data_rate;
3111 }
3112
3113 static void
3114 skl_allocate_pipe_ddb(struct drm_crtc *crtc,
3115 const struct intel_wm_config *config,
3116 const struct skl_pipe_wm_parameters *params,
3117 struct skl_ddb_allocation *ddb /* out */)
3118 {
3119 struct drm_device *dev = crtc->dev;
3120 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3121 enum pipe pipe = intel_crtc->pipe;
3122 struct skl_ddb_entry alloc;
3123 uint16_t alloc_size, start, cursor_blocks;
3124 unsigned int total_data_rate;
3125 int plane;
3126
3127 skl_ddb_get_pipe_allocation_limits(dev, crtc, config, params, &alloc);
3128 alloc_size = skl_ddb_entry_size(&alloc);
3129 if (alloc_size == 0) {
3130 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3131 memset(&ddb->cursor[pipe], 0, sizeof(ddb->cursor[pipe]));
3132 return;
3133 }
3134
3135 cursor_blocks = skl_cursor_allocation(config);
3136 ddb->cursor[pipe].start = alloc.end - cursor_blocks;
3137 ddb->cursor[pipe].end = alloc.end;
3138
3139 alloc_size -= cursor_blocks;
3140 alloc.end -= cursor_blocks;
3141
3142 /*
3143 * Each active plane get a portion of the remaining space, in
3144 * proportion to the amount of data they need to fetch from memory.
3145 *
3146 * FIXME: we may not allocate every single block here.
3147 */
3148 total_data_rate = skl_get_total_relative_data_rate(intel_crtc, params);
3149
3150 start = alloc.start;
3151 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
3152 const struct intel_plane_wm_parameters *p;
3153 unsigned int data_rate;
3154 uint16_t plane_blocks;
3155
3156 p = &params->plane[plane];
3157 if (!p->enabled)
3158 continue;
3159
3160 data_rate = skl_plane_relative_data_rate(p);
3161
3162 /*
3163 * promote the expression to 64 bits to avoid overflowing, the
3164 * result is < available as data_rate / total_data_rate < 1
3165 */
3166 plane_blocks = div_u64((uint64_t)alloc_size * data_rate,
3167 total_data_rate);
3168
3169 ddb->plane[pipe][plane].start = start;
3170 ddb->plane[pipe][plane].end = start + plane_blocks;
3171
3172 start += plane_blocks;
3173 }
3174
3175 }
3176
3177 static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_config *config)
3178 {
3179 /* TODO: Take into account the scalers once we support them */
3180 return config->adjusted_mode.crtc_clock;
3181 }
3182
3183 /*
3184 * The max latency should be 257 (max the punit can code is 255 and we add 2us
3185 * for the read latency) and bytes_per_pixel should always be <= 8, so that
3186 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3187 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3188 */
3189 static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
3190 uint32_t latency)
3191 {
3192 uint32_t wm_intermediate_val, ret;
3193
3194 if (latency == 0)
3195 return UINT_MAX;
3196
3197 wm_intermediate_val = latency * pixel_rate * bytes_per_pixel;
3198 ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3199
3200 return ret;
3201 }
3202
3203 static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
3204 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
3205 uint32_t latency)
3206 {
3207 uint32_t ret, plane_bytes_per_line, wm_intermediate_val;
3208
3209 if (latency == 0)
3210 return UINT_MAX;
3211
3212 plane_bytes_per_line = horiz_pixels * bytes_per_pixel;
3213 wm_intermediate_val = latency * pixel_rate;
3214 ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
3215 plane_bytes_per_line;
3216
3217 return ret;
3218 }
3219
3220 static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb,
3221 const struct intel_crtc *intel_crtc)
3222 {
3223 struct drm_device *dev = intel_crtc->base.dev;
3224 struct drm_i915_private *dev_priv = dev->dev_private;
3225 const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
3226 enum pipe pipe = intel_crtc->pipe;
3227
3228 if (memcmp(new_ddb->plane[pipe], cur_ddb->plane[pipe],
3229 sizeof(new_ddb->plane[pipe])))
3230 return true;
3231
3232 if (memcmp(&new_ddb->cursor[pipe], &cur_ddb->cursor[pipe],
3233 sizeof(new_ddb->cursor[pipe])))
3234 return true;
3235
3236 return false;
3237 }
3238
3239 static void skl_compute_wm_global_parameters(struct drm_device *dev,
3240 struct intel_wm_config *config)
3241 {
3242 struct drm_crtc *crtc;
3243 struct drm_plane *plane;
3244
3245 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3246 config->num_pipes_active += intel_crtc_active(crtc);
3247
3248 /* FIXME: I don't think we need those two global parameters on SKL */
3249 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
3250 struct intel_plane *intel_plane = to_intel_plane(plane);
3251
3252 config->sprites_enabled |= intel_plane->wm.enabled;
3253 config->sprites_scaled |= intel_plane->wm.scaled;
3254 }
3255 }
3256
3257 static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,
3258 struct skl_pipe_wm_parameters *p)
3259 {
3260 struct drm_device *dev = crtc->dev;
3261 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3262 enum pipe pipe = intel_crtc->pipe;
3263 struct drm_plane *plane;
3264 int i = 1; /* Index for sprite planes start */
3265
3266 p->active = intel_crtc_active(crtc);
3267 if (p->active) {
3268 p->pipe_htotal = intel_crtc->config.adjusted_mode.crtc_htotal;
3269 p->pixel_rate = skl_pipe_pixel_rate(&intel_crtc->config);
3270
3271 /*
3272 * For now, assume primary and cursor planes are always enabled.
3273 */
3274 p->plane[0].enabled = true;
3275 p->plane[0].bytes_per_pixel =
3276 crtc->primary->fb->bits_per_pixel / 8;
3277 p->plane[0].horiz_pixels = intel_crtc->config.pipe_src_w;
3278 p->plane[0].vert_pixels = intel_crtc->config.pipe_src_h;
3279
3280 p->cursor.enabled = true;
3281 p->cursor.bytes_per_pixel = 4;
3282 p->cursor.horiz_pixels = intel_crtc->cursor_width ?
3283 intel_crtc->cursor_width : 64;
3284 }
3285
3286 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
3287 struct intel_plane *intel_plane = to_intel_plane(plane);
3288
3289 if (intel_plane->pipe == pipe)
3290 p->plane[i++] = intel_plane->wm;
3291 }
3292 }
3293
3294 static bool skl_compute_plane_wm(struct skl_pipe_wm_parameters *p,
3295 struct intel_plane_wm_parameters *p_params,
3296 uint16_t ddb_allocation,
3297 uint32_t mem_value,
3298 uint16_t *out_blocks, /* out */
3299 uint8_t *out_lines /* out */)
3300 {
3301 uint32_t method1, method2, plane_bytes_per_line, res_blocks, res_lines;
3302 uint32_t result_bytes;
3303
3304 if (mem_value == 0 || !p->active || !p_params->enabled)
3305 return false;
3306
3307 method1 = skl_wm_method1(p->pixel_rate,
3308 p_params->bytes_per_pixel,
3309 mem_value);
3310 method2 = skl_wm_method2(p->pixel_rate,
3311 p->pipe_htotal,
3312 p_params->horiz_pixels,
3313 p_params->bytes_per_pixel,
3314 mem_value);
3315
3316 plane_bytes_per_line = p_params->horiz_pixels *
3317 p_params->bytes_per_pixel;
3318
3319 /* For now xtile and linear */
3320 if (((ddb_allocation * 512) / plane_bytes_per_line) >= 1)
3321 result_bytes = min(method1, method2);
3322 else
3323 result_bytes = method1;
3324
3325 res_blocks = DIV_ROUND_UP(result_bytes, 512) + 1;
3326 res_lines = DIV_ROUND_UP(result_bytes, plane_bytes_per_line);
3327
3328 if (res_blocks > ddb_allocation || res_lines > 31)
3329 return false;
3330
3331 *out_blocks = res_blocks;
3332 *out_lines = res_lines;
3333
3334 return true;
3335 }
3336
3337 static void skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3338 struct skl_ddb_allocation *ddb,
3339 struct skl_pipe_wm_parameters *p,
3340 enum pipe pipe,
3341 int level,
3342 int num_planes,
3343 struct skl_wm_level *result)
3344 {
3345 uint16_t latency = dev_priv->wm.skl_latency[level];
3346 uint16_t ddb_blocks;
3347 int i;
3348
3349 for (i = 0; i < num_planes; i++) {
3350 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3351
3352 result->plane_en[i] = skl_compute_plane_wm(p, &p->plane[i],
3353 ddb_blocks,
3354 latency,
3355 &result->plane_res_b[i],
3356 &result->plane_res_l[i]);
3357 }
3358
3359 ddb_blocks = skl_ddb_entry_size(&ddb->cursor[pipe]);
3360 result->cursor_en = skl_compute_plane_wm(p, &p->cursor, ddb_blocks,
3361 latency, &result->cursor_res_b,
3362 &result->cursor_res_l);
3363 }
3364
3365 static uint32_t
3366 skl_compute_linetime_wm(struct drm_crtc *crtc, struct skl_pipe_wm_parameters *p)
3367 {
3368 if (!intel_crtc_active(crtc))
3369 return 0;
3370
3371 return DIV_ROUND_UP(8 * p->pipe_htotal * 1000, p->pixel_rate);
3372
3373 }
3374
3375 static void skl_compute_transition_wm(struct drm_crtc *crtc,
3376 struct skl_pipe_wm_parameters *params,
3377 struct skl_wm_level *trans_wm /* out */)
3378 {
3379 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3380 int i;
3381
3382 if (!params->active)
3383 return;
3384
3385 /* Until we know more, just disable transition WMs */
3386 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3387 trans_wm->plane_en[i] = false;
3388 trans_wm->cursor_en = false;
3389 }
3390
3391 static void skl_compute_pipe_wm(struct drm_crtc *crtc,
3392 struct skl_ddb_allocation *ddb,
3393 struct skl_pipe_wm_parameters *params,
3394 struct skl_pipe_wm *pipe_wm)
3395 {
3396 struct drm_device *dev = crtc->dev;
3397 const struct drm_i915_private *dev_priv = dev->dev_private;
3398 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3399 int level, max_level = ilk_wm_max_level(dev);
3400
3401 for (level = 0; level <= max_level; level++) {
3402 skl_compute_wm_level(dev_priv, ddb, params, intel_crtc->pipe,
3403 level, intel_num_planes(intel_crtc),
3404 &pipe_wm->wm[level]);
3405 }
3406 pipe_wm->linetime = skl_compute_linetime_wm(crtc, params);
3407
3408 skl_compute_transition_wm(crtc, params, &pipe_wm->trans_wm);
3409 }
3410
3411 static void skl_compute_wm_results(struct drm_device *dev,
3412 struct skl_pipe_wm_parameters *p,
3413 struct skl_pipe_wm *p_wm,
3414 struct skl_wm_values *r,
3415 struct intel_crtc *intel_crtc)
3416 {
3417 int level, max_level = ilk_wm_max_level(dev);
3418 enum pipe pipe = intel_crtc->pipe;
3419 uint32_t temp;
3420 int i;
3421
3422 for (level = 0; level <= max_level; level++) {
3423 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3424 temp = 0;
3425
3426 temp |= p_wm->wm[level].plane_res_l[i] <<
3427 PLANE_WM_LINES_SHIFT;
3428 temp |= p_wm->wm[level].plane_res_b[i];
3429 if (p_wm->wm[level].plane_en[i])
3430 temp |= PLANE_WM_EN;
3431
3432 r->plane[pipe][i][level] = temp;
3433 }
3434
3435 temp = 0;
3436
3437 temp |= p_wm->wm[level].cursor_res_l << PLANE_WM_LINES_SHIFT;
3438 temp |= p_wm->wm[level].cursor_res_b;
3439
3440 if (p_wm->wm[level].cursor_en)
3441 temp |= PLANE_WM_EN;
3442
3443 r->cursor[pipe][level] = temp;
3444
3445 }
3446
3447 /* transition WMs */
3448 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3449 temp = 0;
3450 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3451 temp |= p_wm->trans_wm.plane_res_b[i];
3452 if (p_wm->trans_wm.plane_en[i])
3453 temp |= PLANE_WM_EN;
3454
3455 r->plane_trans[pipe][i] = temp;
3456 }
3457
3458 temp = 0;
3459 temp |= p_wm->trans_wm.cursor_res_l << PLANE_WM_LINES_SHIFT;
3460 temp |= p_wm->trans_wm.cursor_res_b;
3461 if (p_wm->trans_wm.cursor_en)
3462 temp |= PLANE_WM_EN;
3463
3464 r->cursor_trans[pipe] = temp;
3465
3466 r->wm_linetime[pipe] = p_wm->linetime;
3467 }
3468
3469 static void skl_ddb_entry_write(struct drm_i915_private *dev_priv, uint32_t reg,
3470 const struct skl_ddb_entry *entry)
3471 {
3472 if (entry->end)
3473 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3474 else
3475 I915_WRITE(reg, 0);
3476 }
3477
3478 static void skl_write_wm_values(struct drm_i915_private *dev_priv,
3479 const struct skl_wm_values *new)
3480 {
3481 struct drm_device *dev = dev_priv->dev;
3482 struct intel_crtc *crtc;
3483
3484 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
3485 int i, level, max_level = ilk_wm_max_level(dev);
3486 enum pipe pipe = crtc->pipe;
3487
3488 if (new->dirty[pipe]) {
3489 I915_WRITE(PIPE_WM_LINETIME(pipe),
3490 new->wm_linetime[pipe]);
3491
3492 for (level = 0; level <= max_level; level++) {
3493 for (i = 0; i < intel_num_planes(crtc); i++)
3494 I915_WRITE(PLANE_WM(pipe, i, level),
3495 new->plane[pipe][i][level]);
3496 I915_WRITE(CUR_WM(pipe, level),
3497 new->cursor[pipe][level]);
3498 }
3499 for (i = 0; i < intel_num_planes(crtc); i++)
3500 I915_WRITE(PLANE_WM_TRANS(pipe, i),
3501 new->plane_trans[pipe][i]);
3502 I915_WRITE(CUR_WM_TRANS(pipe), new->cursor_trans[pipe]);
3503
3504 for (i = 0; i < intel_num_planes(crtc); i++)
3505 skl_ddb_entry_write(dev_priv,
3506 PLANE_BUF_CFG(pipe, i),
3507 &new->ddb.plane[pipe][i]);
3508
3509 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3510 &new->ddb.cursor[pipe]);
3511 }
3512 }
3513 }
3514
3515 static bool skl_update_pipe_wm(struct drm_crtc *crtc,
3516 struct skl_pipe_wm_parameters *params,
3517 struct intel_wm_config *config,
3518 struct skl_ddb_allocation *ddb, /* out */
3519 struct skl_pipe_wm *pipe_wm /* out */)
3520 {
3521 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3522
3523 skl_compute_wm_pipe_parameters(crtc, params);
3524 skl_allocate_pipe_ddb(crtc, config, params, ddb);
3525 skl_compute_pipe_wm(crtc, ddb, params, pipe_wm);
3526
3527 if (!memcmp(&intel_crtc->wm.skl_active, pipe_wm, sizeof(*pipe_wm)))
3528 return false;
3529
3530 intel_crtc->wm.skl_active = *pipe_wm;
3531 return true;
3532 }
3533
3534 static void skl_update_other_pipe_wm(struct drm_device *dev,
3535 struct drm_crtc *crtc,
3536 struct intel_wm_config *config,
3537 struct skl_wm_values *r)
3538 {
3539 struct intel_crtc *intel_crtc;
3540 struct intel_crtc *this_crtc = to_intel_crtc(crtc);
3541
3542 /*
3543 * If the WM update hasn't changed the allocation for this_crtc (the
3544 * crtc we are currently computing the new WM values for), other
3545 * enabled crtcs will keep the same allocation and we don't need to
3546 * recompute anything for them.
3547 */
3548 if (!skl_ddb_allocation_changed(&r->ddb, this_crtc))
3549 return;
3550
3551 /*
3552 * Otherwise, because of this_crtc being freshly enabled/disabled, the
3553 * other active pipes need new DDB allocation and WM values.
3554 */
3555 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
3556 base.head) {
3557 struct skl_pipe_wm_parameters params = {};
3558 struct skl_pipe_wm pipe_wm = {};
3559 bool wm_changed;
3560
3561 if (this_crtc->pipe == intel_crtc->pipe)
3562 continue;
3563
3564 if (!intel_crtc->active)
3565 continue;
3566
3567 wm_changed = skl_update_pipe_wm(&intel_crtc->base,
3568 &params, config,
3569 &r->ddb, &pipe_wm);
3570
3571 /*
3572 * If we end up re-computing the other pipe WM values, it's
3573 * because it was really needed, so we expect the WM values to
3574 * be different.
3575 */
3576 WARN_ON(!wm_changed);
3577
3578 skl_compute_wm_results(dev, &params, &pipe_wm, r, intel_crtc);
3579 r->dirty[intel_crtc->pipe] = true;
3580 }
3581 }
3582
3583 static void skl_update_wm(struct drm_crtc *crtc)
3584 {
3585 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3586 struct drm_device *dev = crtc->dev;
3587 struct drm_i915_private *dev_priv = dev->dev_private;
3588 struct skl_pipe_wm_parameters params = {};
3589 struct skl_wm_values *results = &dev_priv->wm.skl_results;
3590 struct skl_pipe_wm pipe_wm = {};
3591 struct intel_wm_config config = {};
3592
3593 memset(results, 0, sizeof(*results));
3594
3595 skl_compute_wm_global_parameters(dev, &config);
3596
3597 if (!skl_update_pipe_wm(crtc, &params, &config,
3598 &results->ddb, &pipe_wm))
3599 return;
3600
3601 skl_compute_wm_results(dev, &params, &pipe_wm, results, intel_crtc);
3602 results->dirty[intel_crtc->pipe] = true;
3603
3604 skl_update_other_pipe_wm(dev, crtc, &config, results);
3605 skl_write_wm_values(dev_priv, results);
3606
3607 /* store the new configuration */
3608 dev_priv->wm.skl_hw = *results;
3609 }
3610
3611 static void
3612 skl_update_sprite_wm(struct drm_plane *plane, struct drm_crtc *crtc,
3613 uint32_t sprite_width, uint32_t sprite_height,
3614 int pixel_size, bool enabled, bool scaled)
3615 {
3616 struct intel_plane *intel_plane = to_intel_plane(plane);
3617
3618 intel_plane->wm.enabled = enabled;
3619 intel_plane->wm.scaled = scaled;
3620 intel_plane->wm.horiz_pixels = sprite_width;
3621 intel_plane->wm.vert_pixels = sprite_height;
3622 intel_plane->wm.bytes_per_pixel = pixel_size;
3623
3624 skl_update_wm(crtc);
3625 }
3626
3627 static void ilk_update_wm(struct drm_crtc *crtc)
3628 {
3629 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3630 struct drm_device *dev = crtc->dev;
3631 struct drm_i915_private *dev_priv = dev->dev_private;
3632 struct ilk_wm_maximums max;
3633 struct ilk_pipe_wm_parameters params = {};
3634 struct ilk_wm_values results = {};
3635 enum intel_ddb_partitioning partitioning;
3636 struct intel_pipe_wm pipe_wm = {};
3637 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
3638 struct intel_wm_config config = {};
3639
3640 ilk_compute_wm_parameters(crtc, &params);
3641
3642 intel_compute_pipe_wm(crtc, &params, &pipe_wm);
3643
3644 if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
3645 return;
3646
3647 intel_crtc->wm.active = pipe_wm;
3648
3649 ilk_compute_wm_config(dev, &config);
3650
3651 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
3652 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
3653
3654 /* 5/6 split only in single pipe config on IVB+ */
3655 if (INTEL_INFO(dev)->gen >= 7 &&
3656 config.num_pipes_active == 1 && config.sprites_enabled) {
3657 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
3658 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
3659
3660 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
3661 } else {
3662 best_lp_wm = &lp_wm_1_2;
3663 }
3664
3665 partitioning = (best_lp_wm == &lp_wm_1_2) ?
3666 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
3667
3668 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
3669
3670 ilk_write_wm_values(dev_priv, &results);
3671 }
3672
3673 static void
3674 ilk_update_sprite_wm(struct drm_plane *plane,
3675 struct drm_crtc *crtc,
3676 uint32_t sprite_width, uint32_t sprite_height,
3677 int pixel_size, bool enabled, bool scaled)
3678 {
3679 struct drm_device *dev = plane->dev;
3680 struct intel_plane *intel_plane = to_intel_plane(plane);
3681
3682 intel_plane->wm.enabled = enabled;
3683 intel_plane->wm.scaled = scaled;
3684 intel_plane->wm.horiz_pixels = sprite_width;
3685 intel_plane->wm.vert_pixels = sprite_width;
3686 intel_plane->wm.bytes_per_pixel = pixel_size;
3687
3688 /*
3689 * IVB workaround: must disable low power watermarks for at least
3690 * one frame before enabling scaling. LP watermarks can be re-enabled
3691 * when scaling is disabled.
3692 *
3693 * WaCxSRDisabledForSpriteScaling:ivb
3694 */
3695 if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev))
3696 intel_wait_for_vblank(dev, intel_plane->pipe);
3697
3698 ilk_update_wm(crtc);
3699 }
3700
3701 static void skl_pipe_wm_active_state(uint32_t val,
3702 struct skl_pipe_wm *active,
3703 bool is_transwm,
3704 bool is_cursor,
3705 int i,
3706 int level)
3707 {
3708 bool is_enabled = (val & PLANE_WM_EN) != 0;
3709
3710 if (!is_transwm) {
3711 if (!is_cursor) {
3712 active->wm[level].plane_en[i] = is_enabled;
3713 active->wm[level].plane_res_b[i] =
3714 val & PLANE_WM_BLOCKS_MASK;
3715 active->wm[level].plane_res_l[i] =
3716 (val >> PLANE_WM_LINES_SHIFT) &
3717 PLANE_WM_LINES_MASK;
3718 } else {
3719 active->wm[level].cursor_en = is_enabled;
3720 active->wm[level].cursor_res_b =
3721 val & PLANE_WM_BLOCKS_MASK;
3722 active->wm[level].cursor_res_l =
3723 (val >> PLANE_WM_LINES_SHIFT) &
3724 PLANE_WM_LINES_MASK;
3725 }
3726 } else {
3727 if (!is_cursor) {
3728 active->trans_wm.plane_en[i] = is_enabled;
3729 active->trans_wm.plane_res_b[i] =
3730 val & PLANE_WM_BLOCKS_MASK;
3731 active->trans_wm.plane_res_l[i] =
3732 (val >> PLANE_WM_LINES_SHIFT) &
3733 PLANE_WM_LINES_MASK;
3734 } else {
3735 active->trans_wm.cursor_en = is_enabled;
3736 active->trans_wm.cursor_res_b =
3737 val & PLANE_WM_BLOCKS_MASK;
3738 active->trans_wm.cursor_res_l =
3739 (val >> PLANE_WM_LINES_SHIFT) &
3740 PLANE_WM_LINES_MASK;
3741 }
3742 }
3743 }
3744
3745 static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3746 {
3747 struct drm_device *dev = crtc->dev;
3748 struct drm_i915_private *dev_priv = dev->dev_private;
3749 struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
3750 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3751 struct skl_pipe_wm *active = &intel_crtc->wm.skl_active;
3752 enum pipe pipe = intel_crtc->pipe;
3753 int level, i, max_level;
3754 uint32_t temp;
3755
3756 max_level = ilk_wm_max_level(dev);
3757
3758 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3759
3760 for (level = 0; level <= max_level; level++) {
3761 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3762 hw->plane[pipe][i][level] =
3763 I915_READ(PLANE_WM(pipe, i, level));
3764 hw->cursor[pipe][level] = I915_READ(CUR_WM(pipe, level));
3765 }
3766
3767 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3768 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
3769 hw->cursor_trans[pipe] = I915_READ(CUR_WM_TRANS(pipe));
3770
3771 if (!intel_crtc_active(crtc))
3772 return;
3773
3774 hw->dirty[pipe] = true;
3775
3776 active->linetime = hw->wm_linetime[pipe];
3777
3778 for (level = 0; level <= max_level; level++) {
3779 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3780 temp = hw->plane[pipe][i][level];
3781 skl_pipe_wm_active_state(temp, active, false,
3782 false, i, level);
3783 }
3784 temp = hw->cursor[pipe][level];
3785 skl_pipe_wm_active_state(temp, active, false, true, i, level);
3786 }
3787
3788 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3789 temp = hw->plane_trans[pipe][i];
3790 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
3791 }
3792
3793 temp = hw->cursor_trans[pipe];
3794 skl_pipe_wm_active_state(temp, active, true, true, i, 0);
3795 }
3796
3797 void skl_wm_get_hw_state(struct drm_device *dev)
3798 {
3799 struct drm_i915_private *dev_priv = dev->dev_private;
3800 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3801 struct drm_crtc *crtc;
3802
3803 skl_ddb_get_hw_state(dev_priv, ddb);
3804 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3805 skl_pipe_wm_get_hw_state(crtc);
3806 }
3807
3808 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3809 {
3810 struct drm_device *dev = crtc->dev;
3811 struct drm_i915_private *dev_priv = dev->dev_private;
3812 struct ilk_wm_values *hw = &dev_priv->wm.hw;
3813 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3814 struct intel_pipe_wm *active = &intel_crtc->wm.active;
3815 enum pipe pipe = intel_crtc->pipe;
3816 static const unsigned int wm0_pipe_reg[] = {
3817 [PIPE_A] = WM0_PIPEA_ILK,
3818 [PIPE_B] = WM0_PIPEB_ILK,
3819 [PIPE_C] = WM0_PIPEC_IVB,
3820 };
3821
3822 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
3823 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3824 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3825
3826 active->pipe_enabled = intel_crtc_active(crtc);
3827
3828 if (active->pipe_enabled) {
3829 u32 tmp = hw->wm_pipe[pipe];
3830
3831 /*
3832 * For active pipes LP0 watermark is marked as
3833 * enabled, and LP1+ watermaks as disabled since
3834 * we can't really reverse compute them in case
3835 * multiple pipes are active.
3836 */
3837 active->wm[0].enable = true;
3838 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3839 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3840 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3841 active->linetime = hw->wm_linetime[pipe];
3842 } else {
3843 int level, max_level = ilk_wm_max_level(dev);
3844
3845 /*
3846 * For inactive pipes, all watermark levels
3847 * should be marked as enabled but zeroed,
3848 * which is what we'd compute them to.
3849 */
3850 for (level = 0; level <= max_level; level++)
3851 active->wm[level].enable = true;
3852 }
3853 }
3854
3855 void ilk_wm_get_hw_state(struct drm_device *dev)
3856 {
3857 struct drm_i915_private *dev_priv = dev->dev_private;
3858 struct ilk_wm_values *hw = &dev_priv->wm.hw;
3859 struct drm_crtc *crtc;
3860
3861 for_each_crtc(dev, crtc)
3862 ilk_pipe_wm_get_hw_state(crtc);
3863
3864 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
3865 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
3866 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
3867
3868 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
3869 if (INTEL_INFO(dev)->gen >= 7) {
3870 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
3871 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
3872 }
3873
3874 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3875 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
3876 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
3877 else if (IS_IVYBRIDGE(dev))
3878 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
3879 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
3880
3881 hw->enable_fbc_wm =
3882 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
3883 }
3884
3885 /**
3886 * intel_update_watermarks - update FIFO watermark values based on current modes
3887 *
3888 * Calculate watermark values for the various WM regs based on current mode
3889 * and plane configuration.
3890 *
3891 * There are several cases to deal with here:
3892 * - normal (i.e. non-self-refresh)
3893 * - self-refresh (SR) mode
3894 * - lines are large relative to FIFO size (buffer can hold up to 2)
3895 * - lines are small relative to FIFO size (buffer can hold more than 2
3896 * lines), so need to account for TLB latency
3897 *
3898 * The normal calculation is:
3899 * watermark = dotclock * bytes per pixel * latency
3900 * where latency is platform & configuration dependent (we assume pessimal
3901 * values here).
3902 *
3903 * The SR calculation is:
3904 * watermark = (trunc(latency/line time)+1) * surface width *
3905 * bytes per pixel
3906 * where
3907 * line time = htotal / dotclock
3908 * surface width = hdisplay for normal plane and 64 for cursor
3909 * and latency is assumed to be high, as above.
3910 *
3911 * The final value programmed to the register should always be rounded up,
3912 * and include an extra 2 entries to account for clock crossings.
3913 *
3914 * We don't use the sprite, so we can ignore that. And on Crestline we have
3915 * to set the non-SR watermarks to 8.
3916 */
3917 void intel_update_watermarks(struct drm_crtc *crtc)
3918 {
3919 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
3920
3921 if (dev_priv->display.update_wm)
3922 dev_priv->display.update_wm(crtc);
3923 }
3924
3925 void intel_update_sprite_watermarks(struct drm_plane *plane,
3926 struct drm_crtc *crtc,
3927 uint32_t sprite_width,
3928 uint32_t sprite_height,
3929 int pixel_size,
3930 bool enabled, bool scaled)
3931 {
3932 struct drm_i915_private *dev_priv = plane->dev->dev_private;
3933
3934 if (dev_priv->display.update_sprite_wm)
3935 dev_priv->display.update_sprite_wm(plane, crtc,
3936 sprite_width, sprite_height,
3937 pixel_size, enabled, scaled);
3938 }
3939
3940 static struct drm_i915_gem_object *
3941 intel_alloc_context_page(struct drm_device *dev)
3942 {
3943 struct drm_i915_gem_object *ctx;
3944 int ret;
3945
3946 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3947
3948 ctx = i915_gem_alloc_object(dev, 4096);
3949 if (!ctx) {
3950 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
3951 return NULL;
3952 }
3953
3954 ret = i915_gem_obj_ggtt_pin(ctx, 4096, 0);
3955 if (ret) {
3956 DRM_ERROR("failed to pin power context: %d\n", ret);
3957 goto err_unref;
3958 }
3959
3960 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
3961 if (ret) {
3962 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
3963 goto err_unpin;
3964 }
3965
3966 return ctx;
3967
3968 err_unpin:
3969 i915_gem_object_ggtt_unpin(ctx);
3970 err_unref:
3971 drm_gem_object_unreference(&ctx->base);
3972 return NULL;
3973 }
3974
3975 /**
3976 * Lock protecting IPS related data structures
3977 */
3978 DEFINE_SPINLOCK(mchdev_lock);
3979
3980 /* Global for IPS driver to get at the current i915 device. Protected by
3981 * mchdev_lock. */
3982 static struct drm_i915_private *i915_mch_dev;
3983
3984 bool ironlake_set_drps(struct drm_device *dev, u8 val)
3985 {
3986 struct drm_i915_private *dev_priv = dev->dev_private;
3987 u16 rgvswctl;
3988
3989 assert_spin_locked(&mchdev_lock);
3990
3991 rgvswctl = I915_READ16(MEMSWCTL);
3992 if (rgvswctl & MEMCTL_CMD_STS) {
3993 DRM_DEBUG("gpu busy, RCS change rejected\n");
3994 return false; /* still busy with another command */
3995 }
3996
3997 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
3998 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
3999 I915_WRITE16(MEMSWCTL, rgvswctl);
4000 POSTING_READ16(MEMSWCTL);
4001
4002 rgvswctl |= MEMCTL_CMD_STS;
4003 I915_WRITE16(MEMSWCTL, rgvswctl);
4004
4005 return true;
4006 }
4007
4008 static void ironlake_enable_drps(struct drm_device *dev)
4009 {
4010 struct drm_i915_private *dev_priv = dev->dev_private;
4011 u32 rgvmodectl = I915_READ(MEMMODECTL);
4012 u8 fmax, fmin, fstart, vstart;
4013
4014 spin_lock_irq(&mchdev_lock);
4015
4016 /* Enable temp reporting */
4017 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4018 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4019
4020 /* 100ms RC evaluation intervals */
4021 I915_WRITE(RCUPEI, 100000);
4022 I915_WRITE(RCDNEI, 100000);
4023
4024 /* Set max/min thresholds to 90ms and 80ms respectively */
4025 I915_WRITE(RCBMAXAVG, 90000);
4026 I915_WRITE(RCBMINAVG, 80000);
4027
4028 I915_WRITE(MEMIHYST, 1);
4029
4030 /* Set up min, max, and cur for interrupt handling */
4031 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4032 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4033 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4034 MEMMODE_FSTART_SHIFT;
4035
4036 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
4037 PXVFREQ_PX_SHIFT;
4038
4039 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4040 dev_priv->ips.fstart = fstart;
4041
4042 dev_priv->ips.max_delay = fstart;
4043 dev_priv->ips.min_delay = fmin;
4044 dev_priv->ips.cur_delay = fstart;
4045
4046 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4047 fmax, fmin, fstart);
4048
4049 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4050
4051 /*
4052 * Interrupts will be enabled in ironlake_irq_postinstall
4053 */
4054
4055 I915_WRITE(VIDSTART, vstart);
4056 POSTING_READ(VIDSTART);
4057
4058 rgvmodectl |= MEMMODE_SWMODE_EN;
4059 I915_WRITE(MEMMODECTL, rgvmodectl);
4060
4061 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
4062 DRM_ERROR("stuck trying to change perf mode\n");
4063 mdelay(1);
4064
4065 ironlake_set_drps(dev, fstart);
4066
4067 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
4068 I915_READ(0x112e0);
4069 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
4070 dev_priv->ips.last_count2 = I915_READ(0x112f4);
4071 dev_priv->ips.last_time2 = ktime_get_raw_ns();
4072
4073 spin_unlock_irq(&mchdev_lock);
4074 }
4075
4076 static void ironlake_disable_drps(struct drm_device *dev)
4077 {
4078 struct drm_i915_private *dev_priv = dev->dev_private;
4079 u16 rgvswctl;
4080
4081 spin_lock_irq(&mchdev_lock);
4082
4083 rgvswctl = I915_READ16(MEMSWCTL);
4084
4085 /* Ack interrupts, disable EFC interrupt */
4086 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4087 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4088 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4089 I915_WRITE(DEIIR, DE_PCU_EVENT);
4090 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4091
4092 /* Go back to the starting frequency */
4093 ironlake_set_drps(dev, dev_priv->ips.fstart);
4094 mdelay(1);
4095 rgvswctl |= MEMCTL_CMD_STS;
4096 I915_WRITE(MEMSWCTL, rgvswctl);
4097 mdelay(1);
4098
4099 spin_unlock_irq(&mchdev_lock);
4100 }
4101
4102 /* There's a funny hw issue where the hw returns all 0 when reading from
4103 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4104 * ourselves, instead of doing a rmw cycle (which might result in us clearing
4105 * all limits and the gpu stuck at whatever frequency it is at atm).
4106 */
4107 static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)
4108 {
4109 u32 limits;
4110
4111 /* Only set the down limit when we've reached the lowest level to avoid
4112 * getting more interrupts, otherwise leave this clear. This prevents a
4113 * race in the hw when coming out of rc6: There's a tiny window where
4114 * the hw runs at the minimal clock before selecting the desired
4115 * frequency, if the down threshold expires in that window we will not
4116 * receive a down interrupt. */
4117 limits = dev_priv->rps.max_freq_softlimit << 24;
4118 if (val <= dev_priv->rps.min_freq_softlimit)
4119 limits |= dev_priv->rps.min_freq_softlimit << 16;
4120
4121 return limits;
4122 }
4123
4124 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4125 {
4126 int new_power;
4127
4128 new_power = dev_priv->rps.power;
4129 switch (dev_priv->rps.power) {
4130 case LOW_POWER:
4131 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
4132 new_power = BETWEEN;
4133 break;
4134
4135 case BETWEEN:
4136 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
4137 new_power = LOW_POWER;
4138 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
4139 new_power = HIGH_POWER;
4140 break;
4141
4142 case HIGH_POWER:
4143 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
4144 new_power = BETWEEN;
4145 break;
4146 }
4147 /* Max/min bins are special */
4148 if (val == dev_priv->rps.min_freq_softlimit)
4149 new_power = LOW_POWER;
4150 if (val == dev_priv->rps.max_freq_softlimit)
4151 new_power = HIGH_POWER;
4152 if (new_power == dev_priv->rps.power)
4153 return;
4154
4155 /* Note the units here are not exactly 1us, but 1280ns. */
4156 switch (new_power) {
4157 case LOW_POWER:
4158 /* Upclock if more than 95% busy over 16ms */
4159 I915_WRITE(GEN6_RP_UP_EI, 12500);
4160 I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800);
4161
4162 /* Downclock if less than 85% busy over 32ms */
4163 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
4164 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250);
4165
4166 I915_WRITE(GEN6_RP_CONTROL,
4167 GEN6_RP_MEDIA_TURBO |
4168 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4169 GEN6_RP_MEDIA_IS_GFX |
4170 GEN6_RP_ENABLE |
4171 GEN6_RP_UP_BUSY_AVG |
4172 GEN6_RP_DOWN_IDLE_AVG);
4173 break;
4174
4175 case BETWEEN:
4176 /* Upclock if more than 90% busy over 13ms */
4177 I915_WRITE(GEN6_RP_UP_EI, 10250);
4178 I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225);
4179
4180 /* Downclock if less than 75% busy over 32ms */
4181 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
4182 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750);
4183
4184 I915_WRITE(GEN6_RP_CONTROL,
4185 GEN6_RP_MEDIA_TURBO |
4186 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4187 GEN6_RP_MEDIA_IS_GFX |
4188 GEN6_RP_ENABLE |
4189 GEN6_RP_UP_BUSY_AVG |
4190 GEN6_RP_DOWN_IDLE_AVG);
4191 break;
4192
4193 case HIGH_POWER:
4194 /* Upclock if more than 85% busy over 10ms */
4195 I915_WRITE(GEN6_RP_UP_EI, 8000);
4196 I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800);
4197
4198 /* Downclock if less than 60% busy over 32ms */
4199 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
4200 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000);
4201
4202 I915_WRITE(GEN6_RP_CONTROL,
4203 GEN6_RP_MEDIA_TURBO |
4204 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4205 GEN6_RP_MEDIA_IS_GFX |
4206 GEN6_RP_ENABLE |
4207 GEN6_RP_UP_BUSY_AVG |
4208 GEN6_RP_DOWN_IDLE_AVG);
4209 break;
4210 }
4211
4212 dev_priv->rps.power = new_power;
4213 dev_priv->rps.last_adj = 0;
4214 }
4215
4216 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4217 {
4218 u32 mask = 0;
4219
4220 if (val > dev_priv->rps.min_freq_softlimit)
4221 mask |= GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
4222 if (val < dev_priv->rps.max_freq_softlimit)
4223 mask |= GEN6_PM_RP_UP_THRESHOLD;
4224
4225 mask |= dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED);
4226 mask &= dev_priv->pm_rps_events;
4227
4228 /* IVB and SNB hard hangs on looping batchbuffer
4229 * if GEN6_PM_UP_EI_EXPIRED is masked.
4230 */
4231 if (INTEL_INFO(dev_priv->dev)->gen <= 7 && !IS_HASWELL(dev_priv->dev))
4232 mask |= GEN6_PM_RP_UP_EI_EXPIRED;
4233
4234 if (IS_GEN8(dev_priv->dev))
4235 mask |= GEN8_PMINTR_REDIRECT_TO_NON_DISP;
4236
4237 return ~mask;
4238 }
4239
4240 /* gen6_set_rps is called to update the frequency request, but should also be
4241 * called when the range (min_delay and max_delay) is modified so that we can
4242 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
4243 void gen6_set_rps(struct drm_device *dev, u8 val)
4244 {
4245 struct drm_i915_private *dev_priv = dev->dev_private;
4246
4247 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4248 WARN_ON(val > dev_priv->rps.max_freq_softlimit);
4249 WARN_ON(val < dev_priv->rps.min_freq_softlimit);
4250
4251 /* min/max delay may still have been modified so be sure to
4252 * write the limits value.
4253 */
4254 if (val != dev_priv->rps.cur_freq) {
4255 gen6_set_rps_thresholds(dev_priv, val);
4256
4257 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4258 I915_WRITE(GEN6_RPNSWREQ,
4259 HSW_FREQUENCY(val));
4260 else
4261 I915_WRITE(GEN6_RPNSWREQ,
4262 GEN6_FREQUENCY(val) |
4263 GEN6_OFFSET(0) |
4264 GEN6_AGGRESSIVE_TURBO);
4265 }
4266
4267 /* Make sure we continue to get interrupts
4268 * until we hit the minimum or maximum frequencies.
4269 */
4270 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, gen6_rps_limits(dev_priv, val));
4271 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4272
4273 POSTING_READ(GEN6_RPNSWREQ);
4274
4275 dev_priv->rps.cur_freq = val;
4276 trace_intel_gpu_freq_change(val * 50);
4277 }
4278
4279 /* vlv_set_rps_idle: Set the frequency to Rpn if Gfx clocks are down
4280 *
4281 * * If Gfx is Idle, then
4282 * 1. Mask Turbo interrupts
4283 * 2. Bring up Gfx clock
4284 * 3. Change the freq to Rpn and wait till P-Unit updates freq
4285 * 4. Clear the Force GFX CLK ON bit so that Gfx can down
4286 * 5. Unmask Turbo interrupts
4287 */
4288 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4289 {
4290 struct drm_device *dev = dev_priv->dev;
4291
4292 /* Latest VLV doesn't need to force the gfx clock */
4293 if (dev->pdev->revision >= 0xd) {
4294 valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
4295 return;
4296 }
4297
4298 /*
4299 * When we are idle. Drop to min voltage state.
4300 */
4301
4302 if (dev_priv->rps.cur_freq <= dev_priv->rps.min_freq_softlimit)
4303 return;
4304
4305 /* Mask turbo interrupt so that they will not come in between */
4306 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
4307
4308 vlv_force_gfx_clock(dev_priv, true);
4309
4310 dev_priv->rps.cur_freq = dev_priv->rps.min_freq_softlimit;
4311
4312 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ,
4313 dev_priv->rps.min_freq_softlimit);
4314
4315 if (wait_for(((vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS))
4316 & GENFREQSTATUS) == 0, 5))
4317 DRM_ERROR("timed out waiting for Punit\n");
4318
4319 vlv_force_gfx_clock(dev_priv, false);
4320
4321 I915_WRITE(GEN6_PMINTRMSK,
4322 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
4323 }
4324
4325 void gen6_rps_idle(struct drm_i915_private *dev_priv)
4326 {
4327 struct drm_device *dev = dev_priv->dev;
4328
4329 mutex_lock(&dev_priv->rps.hw_lock);
4330 if (dev_priv->rps.enabled) {
4331 if (IS_CHERRYVIEW(dev))
4332 valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
4333 else if (IS_VALLEYVIEW(dev))
4334 vlv_set_rps_idle(dev_priv);
4335 else
4336 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
4337 dev_priv->rps.last_adj = 0;
4338 }
4339 mutex_unlock(&dev_priv->rps.hw_lock);
4340 }
4341
4342 void gen6_rps_boost(struct drm_i915_private *dev_priv)
4343 {
4344 struct drm_device *dev = dev_priv->dev;
4345
4346 mutex_lock(&dev_priv->rps.hw_lock);
4347 if (dev_priv->rps.enabled) {
4348 if (IS_VALLEYVIEW(dev))
4349 valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
4350 else
4351 gen6_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
4352 dev_priv->rps.last_adj = 0;
4353 }
4354 mutex_unlock(&dev_priv->rps.hw_lock);
4355 }
4356
4357 void valleyview_set_rps(struct drm_device *dev, u8 val)
4358 {
4359 struct drm_i915_private *dev_priv = dev->dev_private;
4360
4361 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4362 WARN_ON(val > dev_priv->rps.max_freq_softlimit);
4363 WARN_ON(val < dev_priv->rps.min_freq_softlimit);
4364
4365 if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1),
4366 "Odd GPU freq value\n"))
4367 val &= ~1;
4368
4369 if (val != dev_priv->rps.cur_freq) {
4370 DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
4371 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
4372 dev_priv->rps.cur_freq,
4373 vlv_gpu_freq(dev_priv, val), val);
4374
4375 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
4376 }
4377
4378 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4379
4380 dev_priv->rps.cur_freq = val;
4381 trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val));
4382 }
4383
4384 static void gen8_disable_rps_interrupts(struct drm_device *dev)
4385 {
4386 struct drm_i915_private *dev_priv = dev->dev_private;
4387
4388 I915_WRITE(GEN6_PMINTRMSK, ~GEN8_PMINTR_REDIRECT_TO_NON_DISP);
4389 I915_WRITE(GEN8_GT_IER(2), I915_READ(GEN8_GT_IER(2)) &
4390 ~dev_priv->pm_rps_events);
4391 /* Complete PM interrupt masking here doesn't race with the rps work
4392 * item again unmasking PM interrupts because that is using a different
4393 * register (GEN8_GT_IMR(2)) to mask PM interrupts. The only risk is in
4394 * leaving stale bits in GEN8_GT_IIR(2) and GEN8_GT_IMR(2) which
4395 * gen8_enable_rps will clean up. */
4396
4397 spin_lock_irq(&dev_priv->irq_lock);
4398 dev_priv->rps.pm_iir = 0;
4399 spin_unlock_irq(&dev_priv->irq_lock);
4400
4401 I915_WRITE(GEN8_GT_IIR(2), dev_priv->pm_rps_events);
4402 }
4403
4404 static void gen6_disable_rps_interrupts(struct drm_device *dev)
4405 {
4406 struct drm_i915_private *dev_priv = dev->dev_private;
4407
4408 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
4409 I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) &
4410 ~dev_priv->pm_rps_events);
4411 /* Complete PM interrupt masking here doesn't race with the rps work
4412 * item again unmasking PM interrupts because that is using a different
4413 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
4414 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
4415
4416 spin_lock_irq(&dev_priv->irq_lock);
4417 dev_priv->rps.pm_iir = 0;
4418 spin_unlock_irq(&dev_priv->irq_lock);
4419
4420 I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events);
4421 }
4422
4423 static void gen6_disable_rps(struct drm_device *dev)
4424 {
4425 struct drm_i915_private *dev_priv = dev->dev_private;
4426
4427 I915_WRITE(GEN6_RC_CONTROL, 0);
4428 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
4429
4430 if (IS_BROADWELL(dev))
4431 gen8_disable_rps_interrupts(dev);
4432 else
4433 gen6_disable_rps_interrupts(dev);
4434 }
4435
4436 static void cherryview_disable_rps(struct drm_device *dev)
4437 {
4438 struct drm_i915_private *dev_priv = dev->dev_private;
4439
4440 I915_WRITE(GEN6_RC_CONTROL, 0);
4441
4442 gen8_disable_rps_interrupts(dev);
4443 }
4444
4445 static void valleyview_disable_rps(struct drm_device *dev)
4446 {
4447 struct drm_i915_private *dev_priv = dev->dev_private;
4448
4449 /* we're doing forcewake before Disabling RC6,
4450 * This what the BIOS expects when going into suspend */
4451 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
4452
4453 I915_WRITE(GEN6_RC_CONTROL, 0);
4454
4455 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
4456
4457 gen6_disable_rps_interrupts(dev);
4458 }
4459
4460 static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
4461 {
4462 if (IS_VALLEYVIEW(dev)) {
4463 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
4464 mode = GEN6_RC_CTL_RC6_ENABLE;
4465 else
4466 mode = 0;
4467 }
4468 if (HAS_RC6p(dev))
4469 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
4470 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
4471 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
4472 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
4473
4474 else
4475 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
4476 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off");
4477 }
4478
4479 static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
4480 {
4481 /* No RC6 before Ironlake */
4482 if (INTEL_INFO(dev)->gen < 5)
4483 return 0;
4484
4485 /* RC6 is only on Ironlake mobile not on desktop */
4486 if (INTEL_INFO(dev)->gen == 5 && !IS_IRONLAKE_M(dev))
4487 return 0;
4488
4489 /* Respect the kernel parameter if it is set */
4490 if (enable_rc6 >= 0) {
4491 int mask;
4492
4493 if (HAS_RC6p(dev))
4494 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
4495 INTEL_RC6pp_ENABLE;
4496 else
4497 mask = INTEL_RC6_ENABLE;
4498
4499 if ((enable_rc6 & mask) != enable_rc6)
4500 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
4501 enable_rc6 & mask, enable_rc6, mask);
4502
4503 return enable_rc6 & mask;
4504 }
4505
4506 /* Disable RC6 on Ironlake */
4507 if (INTEL_INFO(dev)->gen == 5)
4508 return 0;
4509
4510 if (IS_IVYBRIDGE(dev))
4511 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
4512
4513 return INTEL_RC6_ENABLE;
4514 }
4515
4516 int intel_enable_rc6(const struct drm_device *dev)
4517 {
4518 return i915.enable_rc6;
4519 }
4520
4521 static void gen8_enable_rps_interrupts(struct drm_device *dev)
4522 {
4523 struct drm_i915_private *dev_priv = dev->dev_private;
4524
4525 spin_lock_irq(&dev_priv->irq_lock);
4526 WARN_ON(dev_priv->rps.pm_iir);
4527 gen8_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
4528 I915_WRITE(GEN8_GT_IIR(2), dev_priv->pm_rps_events);
4529 spin_unlock_irq(&dev_priv->irq_lock);
4530 }
4531
4532 static void gen6_enable_rps_interrupts(struct drm_device *dev)
4533 {
4534 struct drm_i915_private *dev_priv = dev->dev_private;
4535
4536 spin_lock_irq(&dev_priv->irq_lock);
4537 WARN_ON(dev_priv->rps.pm_iir);
4538 gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
4539 I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events);
4540 spin_unlock_irq(&dev_priv->irq_lock);
4541 }
4542
4543 static void parse_rp_state_cap(struct drm_i915_private *dev_priv, u32 rp_state_cap)
4544 {
4545 /* All of these values are in units of 50MHz */
4546 dev_priv->rps.cur_freq = 0;
4547 /* static values from HW: RP0 < RPe < RP1 < RPn (min_freq) */
4548 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
4549 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
4550 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
4551 /* XXX: only BYT has a special efficient freq */
4552 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
4553 /* hw_max = RP0 until we check for overclocking */
4554 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
4555
4556 /* Preserve min/max settings in case of re-init */
4557 if (dev_priv->rps.max_freq_softlimit == 0)
4558 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4559
4560 if (dev_priv->rps.min_freq_softlimit == 0)
4561 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
4562 }
4563
4564 static void gen8_enable_rps(struct drm_device *dev)
4565 {
4566 struct drm_i915_private *dev_priv = dev->dev_private;
4567 struct intel_engine_cs *ring;
4568 uint32_t rc6_mask = 0, rp_state_cap;
4569 int unused;
4570
4571 /* 1a: Software RC state - RC0 */
4572 I915_WRITE(GEN6_RC_STATE, 0);
4573
4574 /* 1c & 1d: Get forcewake during program sequence. Although the driver
4575 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4576 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
4577
4578 /* 2a: Disable RC states. */
4579 I915_WRITE(GEN6_RC_CONTROL, 0);
4580
4581 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
4582 parse_rp_state_cap(dev_priv, rp_state_cap);
4583
4584 /* 2b: Program RC6 thresholds.*/
4585 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4586 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4587 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4588 for_each_ring(ring, dev_priv, unused)
4589 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4590 I915_WRITE(GEN6_RC_SLEEP, 0);
4591 if (IS_BROADWELL(dev))
4592 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
4593 else
4594 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
4595
4596 /* 3: Enable RC6 */
4597 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4598 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4599 intel_print_rc6_info(dev, rc6_mask);
4600 if (IS_BROADWELL(dev))
4601 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4602 GEN7_RC_CTL_TO_MODE |
4603 rc6_mask);
4604 else
4605 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4606 GEN6_RC_CTL_EI_MODE(1) |
4607 rc6_mask);
4608
4609 /* 4 Program defaults and thresholds for RPS*/
4610 I915_WRITE(GEN6_RPNSWREQ,
4611 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4612 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4613 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4614 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
4615 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
4616
4617 /* Docs recommend 900MHz, and 300 MHz respectively */
4618 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
4619 dev_priv->rps.max_freq_softlimit << 24 |
4620 dev_priv->rps.min_freq_softlimit << 16);
4621
4622 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
4623 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
4624 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
4625 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
4626
4627 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4628
4629 /* 5: Enable RPS */
4630 I915_WRITE(GEN6_RP_CONTROL,
4631 GEN6_RP_MEDIA_TURBO |
4632 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4633 GEN6_RP_MEDIA_IS_GFX |
4634 GEN6_RP_ENABLE |
4635 GEN6_RP_UP_BUSY_AVG |
4636 GEN6_RP_DOWN_IDLE_AVG);
4637
4638 /* 6: Ring frequency + overclocking (our driver does this later */
4639
4640 gen6_set_rps(dev, (I915_READ(GEN6_GT_PERF_STATUS) & 0xff00) >> 8);
4641
4642 gen8_enable_rps_interrupts(dev);
4643
4644 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
4645 }
4646
4647 static void gen6_enable_rps(struct drm_device *dev)
4648 {
4649 struct drm_i915_private *dev_priv = dev->dev_private;
4650 struct intel_engine_cs *ring;
4651 u32 rp_state_cap;
4652 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
4653 u32 gtfifodbg;
4654 int rc6_mode;
4655 int i, ret;
4656
4657 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4658
4659 /* Here begins a magic sequence of register writes to enable
4660 * auto-downclocking.
4661 *
4662 * Perhaps there might be some value in exposing these to
4663 * userspace...
4664 */
4665 I915_WRITE(GEN6_RC_STATE, 0);
4666
4667 /* Clear the DBG now so we don't confuse earlier errors */
4668 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
4669 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
4670 I915_WRITE(GTFIFODBG, gtfifodbg);
4671 }
4672
4673 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
4674
4675 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
4676
4677 parse_rp_state_cap(dev_priv, rp_state_cap);
4678
4679 /* disable the counters and set deterministic thresholds */
4680 I915_WRITE(GEN6_RC_CONTROL, 0);
4681
4682 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
4683 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
4684 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
4685 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4686 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4687
4688 for_each_ring(ring, dev_priv, i)
4689 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4690
4691 I915_WRITE(GEN6_RC_SLEEP, 0);
4692 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
4693 if (IS_IVYBRIDGE(dev))
4694 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
4695 else
4696 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
4697 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
4698 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
4699
4700 /* Check if we are enabling RC6 */
4701 rc6_mode = intel_enable_rc6(dev_priv->dev);
4702 if (rc6_mode & INTEL_RC6_ENABLE)
4703 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
4704
4705 /* We don't use those on Haswell */
4706 if (!IS_HASWELL(dev)) {
4707 if (rc6_mode & INTEL_RC6p_ENABLE)
4708 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
4709
4710 if (rc6_mode & INTEL_RC6pp_ENABLE)
4711 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
4712 }
4713
4714 intel_print_rc6_info(dev, rc6_mask);
4715
4716 I915_WRITE(GEN6_RC_CONTROL,
4717 rc6_mask |
4718 GEN6_RC_CTL_EI_MODE(1) |
4719 GEN6_RC_CTL_HW_ENABLE);
4720
4721 /* Power down if completely idle for over 50ms */
4722 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
4723 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4724
4725 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
4726 if (ret)
4727 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
4728
4729 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
4730 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
4731 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
4732 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
4733 (pcu_mbox & 0xff) * 50);
4734 dev_priv->rps.max_freq = pcu_mbox & 0xff;
4735 }
4736
4737 dev_priv->rps.power = HIGH_POWER; /* force a reset */
4738 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
4739
4740 gen6_enable_rps_interrupts(dev);
4741
4742 rc6vids = 0;
4743 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
4744 if (IS_GEN6(dev) && ret) {
4745 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
4746 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
4747 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
4748 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
4749 rc6vids &= 0xffff00;
4750 rc6vids |= GEN6_ENCODE_RC6_VID(450);
4751 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
4752 if (ret)
4753 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
4754 }
4755
4756 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
4757 }
4758
4759 static void __gen6_update_ring_freq(struct drm_device *dev)
4760 {
4761 struct drm_i915_private *dev_priv = dev->dev_private;
4762 int min_freq = 15;
4763 unsigned int gpu_freq;
4764 unsigned int max_ia_freq, min_ring_freq;
4765 int scaling_factor = 180;
4766 struct cpufreq_policy *policy;
4767
4768 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4769
4770 policy = cpufreq_cpu_get(0);
4771 if (policy) {
4772 max_ia_freq = policy->cpuinfo.max_freq;
4773 cpufreq_cpu_put(policy);
4774 } else {
4775 /*
4776 * Default to measured freq if none found, PCU will ensure we
4777 * don't go over
4778 */
4779 max_ia_freq = tsc_khz;
4780 }
4781
4782 /* Convert from kHz to MHz */
4783 max_ia_freq /= 1000;
4784
4785 min_ring_freq = I915_READ(DCLK) & 0xf;
4786 /* convert DDR frequency from units of 266.6MHz to bandwidth */
4787 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
4788
4789 /*
4790 * For each potential GPU frequency, load a ring frequency we'd like
4791 * to use for memory access. We do this by specifying the IA frequency
4792 * the PCU should use as a reference to determine the ring frequency.
4793 */
4794 for (gpu_freq = dev_priv->rps.max_freq_softlimit; gpu_freq >= dev_priv->rps.min_freq_softlimit;
4795 gpu_freq--) {
4796 int diff = dev_priv->rps.max_freq_softlimit - gpu_freq;
4797 unsigned int ia_freq = 0, ring_freq = 0;
4798
4799 if (INTEL_INFO(dev)->gen >= 8) {
4800 /* max(2 * GT, DDR). NB: GT is 50MHz units */
4801 ring_freq = max(min_ring_freq, gpu_freq);
4802 } else if (IS_HASWELL(dev)) {
4803 ring_freq = mult_frac(gpu_freq, 5, 4);
4804 ring_freq = max(min_ring_freq, ring_freq);
4805 /* leave ia_freq as the default, chosen by cpufreq */
4806 } else {
4807 /* On older processors, there is no separate ring
4808 * clock domain, so in order to boost the bandwidth
4809 * of the ring, we need to upclock the CPU (ia_freq).
4810 *
4811 * For GPU frequencies less than 750MHz,
4812 * just use the lowest ring freq.
4813 */
4814 if (gpu_freq < min_freq)
4815 ia_freq = 800;
4816 else
4817 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
4818 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
4819 }
4820
4821 sandybridge_pcode_write(dev_priv,
4822 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
4823 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
4824 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
4825 gpu_freq);
4826 }
4827 }
4828
4829 void gen6_update_ring_freq(struct drm_device *dev)
4830 {
4831 struct drm_i915_private *dev_priv = dev->dev_private;
4832
4833 if (INTEL_INFO(dev)->gen < 6 || IS_VALLEYVIEW(dev))
4834 return;
4835
4836 mutex_lock(&dev_priv->rps.hw_lock);
4837 __gen6_update_ring_freq(dev);
4838 mutex_unlock(&dev_priv->rps.hw_lock);
4839 }
4840
4841 static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
4842 {
4843 u32 val, rp0;
4844
4845 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
4846 rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & PUNIT_GPU_STATUS_MAX_FREQ_MASK;
4847
4848 return rp0;
4849 }
4850
4851 static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
4852 {
4853 u32 val, rpe;
4854
4855 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
4856 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
4857
4858 return rpe;
4859 }
4860
4861 static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
4862 {
4863 u32 val, rp1;
4864
4865 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4866 rp1 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & PUNIT_GPU_STATUS_MAX_FREQ_MASK;
4867
4868 return rp1;
4869 }
4870
4871 static int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
4872 {
4873 u32 val, rpn;
4874
4875 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
4876 rpn = (val >> PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT) & PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK;
4877 return rpn;
4878 }
4879
4880 static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
4881 {
4882 u32 val, rp1;
4883
4884 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
4885
4886 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
4887
4888 return rp1;
4889 }
4890
4891 static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
4892 {
4893 u32 val, rp0;
4894
4895 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
4896
4897 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
4898 /* Clamp to max */
4899 rp0 = min_t(u32, rp0, 0xea);
4900
4901 return rp0;
4902 }
4903
4904 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
4905 {
4906 u32 val, rpe;
4907
4908 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
4909 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
4910 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
4911 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
4912
4913 return rpe;
4914 }
4915
4916 static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
4917 {
4918 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
4919 }
4920
4921 /* Check that the pctx buffer wasn't move under us. */
4922 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
4923 {
4924 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
4925
4926 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
4927 dev_priv->vlv_pctx->stolen->start);
4928 }
4929
4930
4931 /* Check that the pcbr address is not empty. */
4932 static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
4933 {
4934 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
4935
4936 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
4937 }
4938
4939 static void cherryview_setup_pctx(struct drm_device *dev)
4940 {
4941 struct drm_i915_private *dev_priv = dev->dev_private;
4942 unsigned long pctx_paddr, paddr;
4943 struct i915_gtt *gtt = &dev_priv->gtt;
4944 u32 pcbr;
4945 int pctx_size = 32*1024;
4946
4947 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4948
4949 pcbr = I915_READ(VLV_PCBR);
4950 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
4951 paddr = (dev_priv->mm.stolen_base +
4952 (gtt->stolen_size - pctx_size));
4953
4954 pctx_paddr = (paddr & (~4095));
4955 I915_WRITE(VLV_PCBR, pctx_paddr);
4956 }
4957 }
4958
4959 static void valleyview_setup_pctx(struct drm_device *dev)
4960 {
4961 struct drm_i915_private *dev_priv = dev->dev_private;
4962 struct drm_i915_gem_object *pctx;
4963 unsigned long pctx_paddr;
4964 u32 pcbr;
4965 int pctx_size = 24*1024;
4966
4967 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4968
4969 pcbr = I915_READ(VLV_PCBR);
4970 if (pcbr) {
4971 /* BIOS set it up already, grab the pre-alloc'd space */
4972 int pcbr_offset;
4973
4974 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
4975 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
4976 pcbr_offset,
4977 I915_GTT_OFFSET_NONE,
4978 pctx_size);
4979 goto out;
4980 }
4981
4982 /*
4983 * From the Gunit register HAS:
4984 * The Gfx driver is expected to program this register and ensure
4985 * proper allocation within Gfx stolen memory. For example, this
4986 * register should be programmed such than the PCBR range does not
4987 * overlap with other ranges, such as the frame buffer, protected
4988 * memory, or any other relevant ranges.
4989 */
4990 pctx = i915_gem_object_create_stolen(dev, pctx_size);
4991 if (!pctx) {
4992 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
4993 return;
4994 }
4995
4996 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
4997 I915_WRITE(VLV_PCBR, pctx_paddr);
4998
4999 out:
5000 dev_priv->vlv_pctx = pctx;
5001 }
5002
5003 static void valleyview_cleanup_pctx(struct drm_device *dev)
5004 {
5005 struct drm_i915_private *dev_priv = dev->dev_private;
5006
5007 if (WARN_ON(!dev_priv->vlv_pctx))
5008 return;
5009
5010 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
5011 dev_priv->vlv_pctx = NULL;
5012 }
5013
5014 static void valleyview_init_gt_powersave(struct drm_device *dev)
5015 {
5016 struct drm_i915_private *dev_priv = dev->dev_private;
5017 u32 val;
5018
5019 valleyview_setup_pctx(dev);
5020
5021 mutex_lock(&dev_priv->rps.hw_lock);
5022
5023 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5024 switch ((val >> 6) & 3) {
5025 case 0:
5026 case 1:
5027 dev_priv->mem_freq = 800;
5028 break;
5029 case 2:
5030 dev_priv->mem_freq = 1066;
5031 break;
5032 case 3:
5033 dev_priv->mem_freq = 1333;
5034 break;
5035 }
5036 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
5037
5038 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5039 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5040 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5041 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5042 dev_priv->rps.max_freq);
5043
5044 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5045 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5046 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5047 dev_priv->rps.efficient_freq);
5048
5049 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5050 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
5051 vlv_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5052 dev_priv->rps.rp1_freq);
5053
5054 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5055 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5056 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5057 dev_priv->rps.min_freq);
5058
5059 /* Preserve min/max settings in case of re-init */
5060 if (dev_priv->rps.max_freq_softlimit == 0)
5061 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5062
5063 if (dev_priv->rps.min_freq_softlimit == 0)
5064 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5065
5066 mutex_unlock(&dev_priv->rps.hw_lock);
5067 }
5068
5069 static void cherryview_init_gt_powersave(struct drm_device *dev)
5070 {
5071 struct drm_i915_private *dev_priv = dev->dev_private;
5072 u32 val;
5073
5074 cherryview_setup_pctx(dev);
5075
5076 mutex_lock(&dev_priv->rps.hw_lock);
5077
5078 val = vlv_punit_read(dev_priv, CCK_FUSE_REG);
5079 switch ((val >> 2) & 0x7) {
5080 case 0:
5081 case 1:
5082 dev_priv->rps.cz_freq = 200;
5083 dev_priv->mem_freq = 1600;
5084 break;
5085 case 2:
5086 dev_priv->rps.cz_freq = 267;
5087 dev_priv->mem_freq = 1600;
5088 break;
5089 case 3:
5090 dev_priv->rps.cz_freq = 333;
5091 dev_priv->mem_freq = 2000;
5092 break;
5093 case 4:
5094 dev_priv->rps.cz_freq = 320;
5095 dev_priv->mem_freq = 1600;
5096 break;
5097 case 5:
5098 dev_priv->rps.cz_freq = 400;
5099 dev_priv->mem_freq = 1600;
5100 break;
5101 }
5102 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
5103
5104 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5105 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5106 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5107 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5108 dev_priv->rps.max_freq);
5109
5110 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5111 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5112 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5113 dev_priv->rps.efficient_freq);
5114
5115 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5116 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
5117 vlv_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5118 dev_priv->rps.rp1_freq);
5119
5120 dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv);
5121 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5122 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5123 dev_priv->rps.min_freq);
5124
5125 WARN_ONCE((dev_priv->rps.max_freq |
5126 dev_priv->rps.efficient_freq |
5127 dev_priv->rps.rp1_freq |
5128 dev_priv->rps.min_freq) & 1,
5129 "Odd GPU freq values\n");
5130
5131 /* Preserve min/max settings in case of re-init */
5132 if (dev_priv->rps.max_freq_softlimit == 0)
5133 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5134
5135 if (dev_priv->rps.min_freq_softlimit == 0)
5136 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5137
5138 mutex_unlock(&dev_priv->rps.hw_lock);
5139 }
5140
5141 static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
5142 {
5143 valleyview_cleanup_pctx(dev);
5144 }
5145
5146 static void cherryview_enable_rps(struct drm_device *dev)
5147 {
5148 struct drm_i915_private *dev_priv = dev->dev_private;
5149 struct intel_engine_cs *ring;
5150 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
5151 int i;
5152
5153 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5154
5155 gtfifodbg = I915_READ(GTFIFODBG);
5156 if (gtfifodbg) {
5157 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5158 gtfifodbg);
5159 I915_WRITE(GTFIFODBG, gtfifodbg);
5160 }
5161
5162 cherryview_check_pctx(dev_priv);
5163
5164 /* 1a & 1b: Get forcewake during program sequence. Although the driver
5165 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5166 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
5167
5168 /* 2a: Program RC6 thresholds.*/
5169 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5170 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5171 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5172
5173 for_each_ring(ring, dev_priv, i)
5174 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5175 I915_WRITE(GEN6_RC_SLEEP, 0);
5176
5177 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
5178
5179 /* allows RC6 residency counter to work */
5180 I915_WRITE(VLV_COUNTER_CONTROL,
5181 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
5182 VLV_MEDIA_RC6_COUNT_EN |
5183 VLV_RENDER_RC6_COUNT_EN));
5184
5185 /* For now we assume BIOS is allocating and populating the PCBR */
5186 pcbr = I915_READ(VLV_PCBR);
5187
5188 DRM_DEBUG_DRIVER("PCBR offset : 0x%x\n", pcbr);
5189
5190 /* 3: Enable RC6 */
5191 if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
5192 (pcbr >> VLV_PCBR_ADDR_SHIFT))
5193 rc6_mode = GEN6_RC_CTL_EI_MODE(1);
5194
5195 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5196
5197 /* 4 Program defaults and thresholds for RPS*/
5198 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5199 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5200 I915_WRITE(GEN6_RP_UP_EI, 66000);
5201 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5202
5203 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5204
5205 /* WaDisablePwrmtrEvent:chv (pre-production hw) */
5206 I915_WRITE(0xA80C, I915_READ(0xA80C) & 0x00ffffff);
5207 I915_WRITE(0xA810, I915_READ(0xA810) & 0xffffff00);
5208
5209 /* 5: Enable RPS */
5210 I915_WRITE(GEN6_RP_CONTROL,
5211 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5212 GEN6_RP_MEDIA_IS_GFX | /* WaSetMaskForGfxBusyness:chv (pre-production hw ?) */
5213 GEN6_RP_ENABLE |
5214 GEN6_RP_UP_BUSY_AVG |
5215 GEN6_RP_DOWN_IDLE_AVG);
5216
5217 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5218
5219 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
5220 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5221
5222 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5223 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5224 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
5225 dev_priv->rps.cur_freq);
5226
5227 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5228 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5229 dev_priv->rps.efficient_freq);
5230
5231 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5232
5233 gen8_enable_rps_interrupts(dev);
5234
5235 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
5236 }
5237
5238 static void valleyview_enable_rps(struct drm_device *dev)
5239 {
5240 struct drm_i915_private *dev_priv = dev->dev_private;
5241 struct intel_engine_cs *ring;
5242 u32 gtfifodbg, val, rc6_mode = 0;
5243 int i;
5244
5245 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5246
5247 valleyview_check_pctx(dev_priv);
5248
5249 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
5250 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5251 gtfifodbg);
5252 I915_WRITE(GTFIFODBG, gtfifodbg);
5253 }
5254
5255 /* If VLV, Forcewake all wells, else re-direct to regular path */
5256 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
5257
5258 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5259 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5260 I915_WRITE(GEN6_RP_UP_EI, 66000);
5261 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5262
5263 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5264 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 0xf4240);
5265
5266 I915_WRITE(GEN6_RP_CONTROL,
5267 GEN6_RP_MEDIA_TURBO |
5268 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5269 GEN6_RP_MEDIA_IS_GFX |
5270 GEN6_RP_ENABLE |
5271 GEN6_RP_UP_BUSY_AVG |
5272 GEN6_RP_DOWN_IDLE_CONT);
5273
5274 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
5275 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5276 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5277
5278 for_each_ring(ring, dev_priv, i)
5279 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5280
5281 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
5282
5283 /* allows RC6 residency counter to work */
5284 I915_WRITE(VLV_COUNTER_CONTROL,
5285 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
5286 VLV_RENDER_RC0_COUNT_EN |
5287 VLV_MEDIA_RC6_COUNT_EN |
5288 VLV_RENDER_RC6_COUNT_EN));
5289
5290 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
5291 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
5292
5293 intel_print_rc6_info(dev, rc6_mode);
5294
5295 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5296
5297 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5298
5299 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
5300 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5301
5302 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5303 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5304 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
5305 dev_priv->rps.cur_freq);
5306
5307 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5308 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5309 dev_priv->rps.efficient_freq);
5310
5311 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5312
5313 gen6_enable_rps_interrupts(dev);
5314
5315 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
5316 }
5317
5318 void ironlake_teardown_rc6(struct drm_device *dev)
5319 {
5320 struct drm_i915_private *dev_priv = dev->dev_private;
5321
5322 if (dev_priv->ips.renderctx) {
5323 i915_gem_object_ggtt_unpin(dev_priv->ips.renderctx);
5324 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
5325 dev_priv->ips.renderctx = NULL;
5326 }
5327
5328 if (dev_priv->ips.pwrctx) {
5329 i915_gem_object_ggtt_unpin(dev_priv->ips.pwrctx);
5330 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
5331 dev_priv->ips.pwrctx = NULL;
5332 }
5333 }
5334
5335 static void ironlake_disable_rc6(struct drm_device *dev)
5336 {
5337 struct drm_i915_private *dev_priv = dev->dev_private;
5338
5339 if (I915_READ(PWRCTXA)) {
5340 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
5341 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
5342 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
5343 50);
5344
5345 I915_WRITE(PWRCTXA, 0);
5346 POSTING_READ(PWRCTXA);
5347
5348 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
5349 POSTING_READ(RSTDBYCTL);
5350 }
5351 }
5352
5353 static int ironlake_setup_rc6(struct drm_device *dev)
5354 {
5355 struct drm_i915_private *dev_priv = dev->dev_private;
5356
5357 if (dev_priv->ips.renderctx == NULL)
5358 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
5359 if (!dev_priv->ips.renderctx)
5360 return -ENOMEM;
5361
5362 if (dev_priv->ips.pwrctx == NULL)
5363 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
5364 if (!dev_priv->ips.pwrctx) {
5365 ironlake_teardown_rc6(dev);
5366 return -ENOMEM;
5367 }
5368
5369 return 0;
5370 }
5371
5372 static void ironlake_enable_rc6(struct drm_device *dev)
5373 {
5374 struct drm_i915_private *dev_priv = dev->dev_private;
5375 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
5376 bool was_interruptible;
5377 int ret;
5378
5379 /* rc6 disabled by default due to repeated reports of hanging during
5380 * boot and resume.
5381 */
5382 if (!intel_enable_rc6(dev))
5383 return;
5384
5385 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
5386
5387 ret = ironlake_setup_rc6(dev);
5388 if (ret)
5389 return;
5390
5391 was_interruptible = dev_priv->mm.interruptible;
5392 dev_priv->mm.interruptible = false;
5393
5394 /*
5395 * GPU can automatically power down the render unit if given a page
5396 * to save state.
5397 */
5398 ret = intel_ring_begin(ring, 6);
5399 if (ret) {
5400 ironlake_teardown_rc6(dev);
5401 dev_priv->mm.interruptible = was_interruptible;
5402 return;
5403 }
5404
5405 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
5406 intel_ring_emit(ring, MI_SET_CONTEXT);
5407 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) |
5408 MI_MM_SPACE_GTT |
5409 MI_SAVE_EXT_STATE_EN |
5410 MI_RESTORE_EXT_STATE_EN |
5411 MI_RESTORE_INHIBIT);
5412 intel_ring_emit(ring, MI_SUSPEND_FLUSH);
5413 intel_ring_emit(ring, MI_NOOP);
5414 intel_ring_emit(ring, MI_FLUSH);
5415 intel_ring_advance(ring);
5416
5417 /*
5418 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
5419 * does an implicit flush, combined with MI_FLUSH above, it should be
5420 * safe to assume that renderctx is valid
5421 */
5422 ret = intel_ring_idle(ring);
5423 dev_priv->mm.interruptible = was_interruptible;
5424 if (ret) {
5425 DRM_ERROR("failed to enable ironlake power savings\n");
5426 ironlake_teardown_rc6(dev);
5427 return;
5428 }
5429
5430 I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN);
5431 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
5432
5433 intel_print_rc6_info(dev, GEN6_RC_CTL_RC6_ENABLE);
5434 }
5435
5436 static unsigned long intel_pxfreq(u32 vidfreq)
5437 {
5438 unsigned long freq;
5439 int div = (vidfreq & 0x3f0000) >> 16;
5440 int post = (vidfreq & 0x3000) >> 12;
5441 int pre = (vidfreq & 0x7);
5442
5443 if (!pre)
5444 return 0;
5445
5446 freq = ((div * 133333) / ((1<<post) * pre));
5447
5448 return freq;
5449 }
5450
5451 static const struct cparams {
5452 u16 i;
5453 u16 t;
5454 u16 m;
5455 u16 c;
5456 } cparams[] = {
5457 { 1, 1333, 301, 28664 },
5458 { 1, 1066, 294, 24460 },
5459 { 1, 800, 294, 25192 },
5460 { 0, 1333, 276, 27605 },
5461 { 0, 1066, 276, 27605 },
5462 { 0, 800, 231, 23784 },
5463 };
5464
5465 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
5466 {
5467 u64 total_count, diff, ret;
5468 u32 count1, count2, count3, m = 0, c = 0;
5469 unsigned long now = jiffies_to_msecs(jiffies), diff1;
5470 int i;
5471
5472 assert_spin_locked(&mchdev_lock);
5473
5474 diff1 = now - dev_priv->ips.last_time1;
5475
5476 /* Prevent division-by-zero if we are asking too fast.
5477 * Also, we don't get interesting results if we are polling
5478 * faster than once in 10ms, so just return the saved value
5479 * in such cases.
5480 */
5481 if (diff1 <= 10)
5482 return dev_priv->ips.chipset_power;
5483
5484 count1 = I915_READ(DMIEC);
5485 count2 = I915_READ(DDREC);
5486 count3 = I915_READ(CSIEC);
5487
5488 total_count = count1 + count2 + count3;
5489
5490 /* FIXME: handle per-counter overflow */
5491 if (total_count < dev_priv->ips.last_count1) {
5492 diff = ~0UL - dev_priv->ips.last_count1;
5493 diff += total_count;
5494 } else {
5495 diff = total_count - dev_priv->ips.last_count1;
5496 }
5497
5498 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
5499 if (cparams[i].i == dev_priv->ips.c_m &&
5500 cparams[i].t == dev_priv->ips.r_t) {
5501 m = cparams[i].m;
5502 c = cparams[i].c;
5503 break;
5504 }
5505 }
5506
5507 diff = div_u64(diff, diff1);
5508 ret = ((m * diff) + c);
5509 ret = div_u64(ret, 10);
5510
5511 dev_priv->ips.last_count1 = total_count;
5512 dev_priv->ips.last_time1 = now;
5513
5514 dev_priv->ips.chipset_power = ret;
5515
5516 return ret;
5517 }
5518
5519 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
5520 {
5521 struct drm_device *dev = dev_priv->dev;
5522 unsigned long val;
5523
5524 if (INTEL_INFO(dev)->gen != 5)
5525 return 0;
5526
5527 spin_lock_irq(&mchdev_lock);
5528
5529 val = __i915_chipset_val(dev_priv);
5530
5531 spin_unlock_irq(&mchdev_lock);
5532
5533 return val;
5534 }
5535
5536 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
5537 {
5538 unsigned long m, x, b;
5539 u32 tsfs;
5540
5541 tsfs = I915_READ(TSFS);
5542
5543 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
5544 x = I915_READ8(TR1);
5545
5546 b = tsfs & TSFS_INTR_MASK;
5547
5548 return ((m * x) / 127) - b;
5549 }
5550
5551 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
5552 {
5553 struct drm_device *dev = dev_priv->dev;
5554 static const struct v_table {
5555 u16 vd; /* in .1 mil */
5556 u16 vm; /* in .1 mil */
5557 } v_table[] = {
5558 { 0, 0, },
5559 { 375, 0, },
5560 { 500, 0, },
5561 { 625, 0, },
5562 { 750, 0, },
5563 { 875, 0, },
5564 { 1000, 0, },
5565 { 1125, 0, },
5566 { 4125, 3000, },
5567 { 4125, 3000, },
5568 { 4125, 3000, },
5569 { 4125, 3000, },
5570 { 4125, 3000, },
5571 { 4125, 3000, },
5572 { 4125, 3000, },
5573 { 4125, 3000, },
5574 { 4125, 3000, },
5575 { 4125, 3000, },
5576 { 4125, 3000, },
5577 { 4125, 3000, },
5578 { 4125, 3000, },
5579 { 4125, 3000, },
5580 { 4125, 3000, },
5581 { 4125, 3000, },
5582 { 4125, 3000, },
5583 { 4125, 3000, },
5584 { 4125, 3000, },
5585 { 4125, 3000, },
5586 { 4125, 3000, },
5587 { 4125, 3000, },
5588 { 4125, 3000, },
5589 { 4125, 3000, },
5590 { 4250, 3125, },
5591 { 4375, 3250, },
5592 { 4500, 3375, },
5593 { 4625, 3500, },
5594 { 4750, 3625, },
5595 { 4875, 3750, },
5596 { 5000, 3875, },
5597 { 5125, 4000, },
5598 { 5250, 4125, },
5599 { 5375, 4250, },
5600 { 5500, 4375, },
5601 { 5625, 4500, },
5602 { 5750, 4625, },
5603 { 5875, 4750, },
5604 { 6000, 4875, },
5605 { 6125, 5000, },
5606 { 6250, 5125, },
5607 { 6375, 5250, },
5608 { 6500, 5375, },
5609 { 6625, 5500, },
5610 { 6750, 5625, },
5611 { 6875, 5750, },
5612 { 7000, 5875, },
5613 { 7125, 6000, },
5614 { 7250, 6125, },
5615 { 7375, 6250, },
5616 { 7500, 6375, },
5617 { 7625, 6500, },
5618 { 7750, 6625, },
5619 { 7875, 6750, },
5620 { 8000, 6875, },
5621 { 8125, 7000, },
5622 { 8250, 7125, },
5623 { 8375, 7250, },
5624 { 8500, 7375, },
5625 { 8625, 7500, },
5626 { 8750, 7625, },
5627 { 8875, 7750, },
5628 { 9000, 7875, },
5629 { 9125, 8000, },
5630 { 9250, 8125, },
5631 { 9375, 8250, },
5632 { 9500, 8375, },
5633 { 9625, 8500, },
5634 { 9750, 8625, },
5635 { 9875, 8750, },
5636 { 10000, 8875, },
5637 { 10125, 9000, },
5638 { 10250, 9125, },
5639 { 10375, 9250, },
5640 { 10500, 9375, },
5641 { 10625, 9500, },
5642 { 10750, 9625, },
5643 { 10875, 9750, },
5644 { 11000, 9875, },
5645 { 11125, 10000, },
5646 { 11250, 10125, },
5647 { 11375, 10250, },
5648 { 11500, 10375, },
5649 { 11625, 10500, },
5650 { 11750, 10625, },
5651 { 11875, 10750, },
5652 { 12000, 10875, },
5653 { 12125, 11000, },
5654 { 12250, 11125, },
5655 { 12375, 11250, },
5656 { 12500, 11375, },
5657 { 12625, 11500, },
5658 { 12750, 11625, },
5659 { 12875, 11750, },
5660 { 13000, 11875, },
5661 { 13125, 12000, },
5662 { 13250, 12125, },
5663 { 13375, 12250, },
5664 { 13500, 12375, },
5665 { 13625, 12500, },
5666 { 13750, 12625, },
5667 { 13875, 12750, },
5668 { 14000, 12875, },
5669 { 14125, 13000, },
5670 { 14250, 13125, },
5671 { 14375, 13250, },
5672 { 14500, 13375, },
5673 { 14625, 13500, },
5674 { 14750, 13625, },
5675 { 14875, 13750, },
5676 { 15000, 13875, },
5677 { 15125, 14000, },
5678 { 15250, 14125, },
5679 { 15375, 14250, },
5680 { 15500, 14375, },
5681 { 15625, 14500, },
5682 { 15750, 14625, },
5683 { 15875, 14750, },
5684 { 16000, 14875, },
5685 { 16125, 15000, },
5686 };
5687 if (INTEL_INFO(dev)->is_mobile)
5688 return v_table[pxvid].vm;
5689 else
5690 return v_table[pxvid].vd;
5691 }
5692
5693 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
5694 {
5695 u64 now, diff, diffms;
5696 u32 count;
5697
5698 assert_spin_locked(&mchdev_lock);
5699
5700 now = ktime_get_raw_ns();
5701 diffms = now - dev_priv->ips.last_time2;
5702 do_div(diffms, NSEC_PER_MSEC);
5703
5704 /* Don't divide by 0 */
5705 if (!diffms)
5706 return;
5707
5708 count = I915_READ(GFXEC);
5709
5710 if (count < dev_priv->ips.last_count2) {
5711 diff = ~0UL - dev_priv->ips.last_count2;
5712 diff += count;
5713 } else {
5714 diff = count - dev_priv->ips.last_count2;
5715 }
5716
5717 dev_priv->ips.last_count2 = count;
5718 dev_priv->ips.last_time2 = now;
5719
5720 /* More magic constants... */
5721 diff = diff * 1181;
5722 diff = div_u64(diff, diffms * 10);
5723 dev_priv->ips.gfx_power = diff;
5724 }
5725
5726 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
5727 {
5728 struct drm_device *dev = dev_priv->dev;
5729
5730 if (INTEL_INFO(dev)->gen != 5)
5731 return;
5732
5733 spin_lock_irq(&mchdev_lock);
5734
5735 __i915_update_gfx_val(dev_priv);
5736
5737 spin_unlock_irq(&mchdev_lock);
5738 }
5739
5740 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
5741 {
5742 unsigned long t, corr, state1, corr2, state2;
5743 u32 pxvid, ext_v;
5744
5745 assert_spin_locked(&mchdev_lock);
5746
5747 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_freq * 4));
5748 pxvid = (pxvid >> 24) & 0x7f;
5749 ext_v = pvid_to_extvid(dev_priv, pxvid);
5750
5751 state1 = ext_v;
5752
5753 t = i915_mch_val(dev_priv);
5754
5755 /* Revel in the empirically derived constants */
5756
5757 /* Correction factor in 1/100000 units */
5758 if (t > 80)
5759 corr = ((t * 2349) + 135940);
5760 else if (t >= 50)
5761 corr = ((t * 964) + 29317);
5762 else /* < 50 */
5763 corr = ((t * 301) + 1004);
5764
5765 corr = corr * ((150142 * state1) / 10000 - 78642);
5766 corr /= 100000;
5767 corr2 = (corr * dev_priv->ips.corr);
5768
5769 state2 = (corr2 * state1) / 10000;
5770 state2 /= 100; /* convert to mW */
5771
5772 __i915_update_gfx_val(dev_priv);
5773
5774 return dev_priv->ips.gfx_power + state2;
5775 }
5776
5777 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
5778 {
5779 struct drm_device *dev = dev_priv->dev;
5780 unsigned long val;
5781
5782 if (INTEL_INFO(dev)->gen != 5)
5783 return 0;
5784
5785 spin_lock_irq(&mchdev_lock);
5786
5787 val = __i915_gfx_val(dev_priv);
5788
5789 spin_unlock_irq(&mchdev_lock);
5790
5791 return val;
5792 }
5793
5794 /**
5795 * i915_read_mch_val - return value for IPS use
5796 *
5797 * Calculate and return a value for the IPS driver to use when deciding whether
5798 * we have thermal and power headroom to increase CPU or GPU power budget.
5799 */
5800 unsigned long i915_read_mch_val(void)
5801 {
5802 struct drm_i915_private *dev_priv;
5803 unsigned long chipset_val, graphics_val, ret = 0;
5804
5805 spin_lock_irq(&mchdev_lock);
5806 if (!i915_mch_dev)
5807 goto out_unlock;
5808 dev_priv = i915_mch_dev;
5809
5810 chipset_val = __i915_chipset_val(dev_priv);
5811 graphics_val = __i915_gfx_val(dev_priv);
5812
5813 ret = chipset_val + graphics_val;
5814
5815 out_unlock:
5816 spin_unlock_irq(&mchdev_lock);
5817
5818 return ret;
5819 }
5820 EXPORT_SYMBOL_GPL(i915_read_mch_val);
5821
5822 /**
5823 * i915_gpu_raise - raise GPU frequency limit
5824 *
5825 * Raise the limit; IPS indicates we have thermal headroom.
5826 */
5827 bool i915_gpu_raise(void)
5828 {
5829 struct drm_i915_private *dev_priv;
5830 bool ret = true;
5831
5832 spin_lock_irq(&mchdev_lock);
5833 if (!i915_mch_dev) {
5834 ret = false;
5835 goto out_unlock;
5836 }
5837 dev_priv = i915_mch_dev;
5838
5839 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
5840 dev_priv->ips.max_delay--;
5841
5842 out_unlock:
5843 spin_unlock_irq(&mchdev_lock);
5844
5845 return ret;
5846 }
5847 EXPORT_SYMBOL_GPL(i915_gpu_raise);
5848
5849 /**
5850 * i915_gpu_lower - lower GPU frequency limit
5851 *
5852 * IPS indicates we're close to a thermal limit, so throttle back the GPU
5853 * frequency maximum.
5854 */
5855 bool i915_gpu_lower(void)
5856 {
5857 struct drm_i915_private *dev_priv;
5858 bool ret = true;
5859
5860 spin_lock_irq(&mchdev_lock);
5861 if (!i915_mch_dev) {
5862 ret = false;
5863 goto out_unlock;
5864 }
5865 dev_priv = i915_mch_dev;
5866
5867 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
5868 dev_priv->ips.max_delay++;
5869
5870 out_unlock:
5871 spin_unlock_irq(&mchdev_lock);
5872
5873 return ret;
5874 }
5875 EXPORT_SYMBOL_GPL(i915_gpu_lower);
5876
5877 /**
5878 * i915_gpu_busy - indicate GPU business to IPS
5879 *
5880 * Tell the IPS driver whether or not the GPU is busy.
5881 */
5882 bool i915_gpu_busy(void)
5883 {
5884 struct drm_i915_private *dev_priv;
5885 struct intel_engine_cs *ring;
5886 bool ret = false;
5887 int i;
5888
5889 spin_lock_irq(&mchdev_lock);
5890 if (!i915_mch_dev)
5891 goto out_unlock;
5892 dev_priv = i915_mch_dev;
5893
5894 for_each_ring(ring, dev_priv, i)
5895 ret |= !list_empty(&ring->request_list);
5896
5897 out_unlock:
5898 spin_unlock_irq(&mchdev_lock);
5899
5900 return ret;
5901 }
5902 EXPORT_SYMBOL_GPL(i915_gpu_busy);
5903
5904 /**
5905 * i915_gpu_turbo_disable - disable graphics turbo
5906 *
5907 * Disable graphics turbo by resetting the max frequency and setting the
5908 * current frequency to the default.
5909 */
5910 bool i915_gpu_turbo_disable(void)
5911 {
5912 struct drm_i915_private *dev_priv;
5913 bool ret = true;
5914
5915 spin_lock_irq(&mchdev_lock);
5916 if (!i915_mch_dev) {
5917 ret = false;
5918 goto out_unlock;
5919 }
5920 dev_priv = i915_mch_dev;
5921
5922 dev_priv->ips.max_delay = dev_priv->ips.fstart;
5923
5924 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
5925 ret = false;
5926
5927 out_unlock:
5928 spin_unlock_irq(&mchdev_lock);
5929
5930 return ret;
5931 }
5932 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
5933
5934 /**
5935 * Tells the intel_ips driver that the i915 driver is now loaded, if
5936 * IPS got loaded first.
5937 *
5938 * This awkward dance is so that neither module has to depend on the
5939 * other in order for IPS to do the appropriate communication of
5940 * GPU turbo limits to i915.
5941 */
5942 static void
5943 ips_ping_for_i915_load(void)
5944 {
5945 void (*link)(void);
5946
5947 link = symbol_get(ips_link_to_i915_driver);
5948 if (link) {
5949 link();
5950 symbol_put(ips_link_to_i915_driver);
5951 }
5952 }
5953
5954 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
5955 {
5956 /* We only register the i915 ips part with intel-ips once everything is
5957 * set up, to avoid intel-ips sneaking in and reading bogus values. */
5958 spin_lock_irq(&mchdev_lock);
5959 i915_mch_dev = dev_priv;
5960 spin_unlock_irq(&mchdev_lock);
5961
5962 ips_ping_for_i915_load();
5963 }
5964
5965 void intel_gpu_ips_teardown(void)
5966 {
5967 spin_lock_irq(&mchdev_lock);
5968 i915_mch_dev = NULL;
5969 spin_unlock_irq(&mchdev_lock);
5970 }
5971
5972 static void intel_init_emon(struct drm_device *dev)
5973 {
5974 struct drm_i915_private *dev_priv = dev->dev_private;
5975 u32 lcfuse;
5976 u8 pxw[16];
5977 int i;
5978
5979 /* Disable to program */
5980 I915_WRITE(ECR, 0);
5981 POSTING_READ(ECR);
5982
5983 /* Program energy weights for various events */
5984 I915_WRITE(SDEW, 0x15040d00);
5985 I915_WRITE(CSIEW0, 0x007f0000);
5986 I915_WRITE(CSIEW1, 0x1e220004);
5987 I915_WRITE(CSIEW2, 0x04000004);
5988
5989 for (i = 0; i < 5; i++)
5990 I915_WRITE(PEW + (i * 4), 0);
5991 for (i = 0; i < 3; i++)
5992 I915_WRITE(DEW + (i * 4), 0);
5993
5994 /* Program P-state weights to account for frequency power adjustment */
5995 for (i = 0; i < 16; i++) {
5996 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
5997 unsigned long freq = intel_pxfreq(pxvidfreq);
5998 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5999 PXVFREQ_PX_SHIFT;
6000 unsigned long val;
6001
6002 val = vid * vid;
6003 val *= (freq / 1000);
6004 val *= 255;
6005 val /= (127*127*900);
6006 if (val > 0xff)
6007 DRM_ERROR("bad pxval: %ld\n", val);
6008 pxw[i] = val;
6009 }
6010 /* Render standby states get 0 weight */
6011 pxw[14] = 0;
6012 pxw[15] = 0;
6013
6014 for (i = 0; i < 4; i++) {
6015 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6016 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
6017 I915_WRITE(PXW + (i * 4), val);
6018 }
6019
6020 /* Adjust magic regs to magic values (more experimental results) */
6021 I915_WRITE(OGW0, 0);
6022 I915_WRITE(OGW1, 0);
6023 I915_WRITE(EG0, 0x00007f00);
6024 I915_WRITE(EG1, 0x0000000e);
6025 I915_WRITE(EG2, 0x000e0000);
6026 I915_WRITE(EG3, 0x68000300);
6027 I915_WRITE(EG4, 0x42000000);
6028 I915_WRITE(EG5, 0x00140031);
6029 I915_WRITE(EG6, 0);
6030 I915_WRITE(EG7, 0);
6031
6032 for (i = 0; i < 8; i++)
6033 I915_WRITE(PXWL + (i * 4), 0);
6034
6035 /* Enable PMON + select events */
6036 I915_WRITE(ECR, 0x80000019);
6037
6038 lcfuse = I915_READ(LCFUSE02);
6039
6040 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
6041 }
6042
6043 void intel_init_gt_powersave(struct drm_device *dev)
6044 {
6045 i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
6046
6047 if (IS_CHERRYVIEW(dev))
6048 cherryview_init_gt_powersave(dev);
6049 else if (IS_VALLEYVIEW(dev))
6050 valleyview_init_gt_powersave(dev);
6051 }
6052
6053 void intel_cleanup_gt_powersave(struct drm_device *dev)
6054 {
6055 if (IS_CHERRYVIEW(dev))
6056 return;
6057 else if (IS_VALLEYVIEW(dev))
6058 valleyview_cleanup_gt_powersave(dev);
6059 }
6060
6061 /**
6062 * intel_suspend_gt_powersave - suspend PM work and helper threads
6063 * @dev: drm device
6064 *
6065 * We don't want to disable RC6 or other features here, we just want
6066 * to make sure any work we've queued has finished and won't bother
6067 * us while we're suspended.
6068 */
6069 void intel_suspend_gt_powersave(struct drm_device *dev)
6070 {
6071 struct drm_i915_private *dev_priv = dev->dev_private;
6072
6073 /* Interrupts should be disabled already to avoid re-arming. */
6074 WARN_ON(intel_irqs_enabled(dev_priv));
6075
6076 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
6077
6078 cancel_work_sync(&dev_priv->rps.work);
6079
6080 /* Force GPU to min freq during suspend */
6081 gen6_rps_idle(dev_priv);
6082 }
6083
6084 void intel_disable_gt_powersave(struct drm_device *dev)
6085 {
6086 struct drm_i915_private *dev_priv = dev->dev_private;
6087
6088 /* Interrupts should be disabled already to avoid re-arming. */
6089 WARN_ON(intel_irqs_enabled(dev_priv));
6090
6091 if (IS_IRONLAKE_M(dev)) {
6092 ironlake_disable_drps(dev);
6093 ironlake_disable_rc6(dev);
6094 } else if (INTEL_INFO(dev)->gen >= 6) {
6095 intel_suspend_gt_powersave(dev);
6096
6097 mutex_lock(&dev_priv->rps.hw_lock);
6098 if (IS_CHERRYVIEW(dev))
6099 cherryview_disable_rps(dev);
6100 else if (IS_VALLEYVIEW(dev))
6101 valleyview_disable_rps(dev);
6102 else
6103 gen6_disable_rps(dev);
6104 dev_priv->rps.enabled = false;
6105 mutex_unlock(&dev_priv->rps.hw_lock);
6106 }
6107 }
6108
6109 static void intel_gen6_powersave_work(struct work_struct *work)
6110 {
6111 struct drm_i915_private *dev_priv =
6112 container_of(work, struct drm_i915_private,
6113 rps.delayed_resume_work.work);
6114 struct drm_device *dev = dev_priv->dev;
6115
6116 mutex_lock(&dev_priv->rps.hw_lock);
6117
6118 if (IS_CHERRYVIEW(dev)) {
6119 cherryview_enable_rps(dev);
6120 } else if (IS_VALLEYVIEW(dev)) {
6121 valleyview_enable_rps(dev);
6122 } else if (IS_BROADWELL(dev)) {
6123 gen8_enable_rps(dev);
6124 __gen6_update_ring_freq(dev);
6125 } else {
6126 gen6_enable_rps(dev);
6127 __gen6_update_ring_freq(dev);
6128 }
6129 dev_priv->rps.enabled = true;
6130 mutex_unlock(&dev_priv->rps.hw_lock);
6131
6132 intel_runtime_pm_put(dev_priv);
6133 }
6134
6135 void intel_enable_gt_powersave(struct drm_device *dev)
6136 {
6137 struct drm_i915_private *dev_priv = dev->dev_private;
6138
6139 if (IS_IRONLAKE_M(dev)) {
6140 mutex_lock(&dev->struct_mutex);
6141 ironlake_enable_drps(dev);
6142 ironlake_enable_rc6(dev);
6143 intel_init_emon(dev);
6144 mutex_unlock(&dev->struct_mutex);
6145 } else if (INTEL_INFO(dev)->gen >= 6) {
6146 /*
6147 * PCU communication is slow and this doesn't need to be
6148 * done at any specific time, so do this out of our fast path
6149 * to make resume and init faster.
6150 *
6151 * We depend on the HW RC6 power context save/restore
6152 * mechanism when entering D3 through runtime PM suspend. So
6153 * disable RPM until RPS/RC6 is properly setup. We can only
6154 * get here via the driver load/system resume/runtime resume
6155 * paths, so the _noresume version is enough (and in case of
6156 * runtime resume it's necessary).
6157 */
6158 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
6159 round_jiffies_up_relative(HZ)))
6160 intel_runtime_pm_get_noresume(dev_priv);
6161 }
6162 }
6163
6164 void intel_reset_gt_powersave(struct drm_device *dev)
6165 {
6166 struct drm_i915_private *dev_priv = dev->dev_private;
6167
6168 dev_priv->rps.enabled = false;
6169 intel_enable_gt_powersave(dev);
6170 }
6171
6172 static void ibx_init_clock_gating(struct drm_device *dev)
6173 {
6174 struct drm_i915_private *dev_priv = dev->dev_private;
6175
6176 /*
6177 * On Ibex Peak and Cougar Point, we need to disable clock
6178 * gating for the panel power sequencer or it will fail to
6179 * start up when no ports are active.
6180 */
6181 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6182 }
6183
6184 static void g4x_disable_trickle_feed(struct drm_device *dev)
6185 {
6186 struct drm_i915_private *dev_priv = dev->dev_private;
6187 int pipe;
6188
6189 for_each_pipe(dev_priv, pipe) {
6190 I915_WRITE(DSPCNTR(pipe),
6191 I915_READ(DSPCNTR(pipe)) |
6192 DISPPLANE_TRICKLE_FEED_DISABLE);
6193 intel_flush_primary_plane(dev_priv, pipe);
6194 }
6195 }
6196
6197 static void ilk_init_lp_watermarks(struct drm_device *dev)
6198 {
6199 struct drm_i915_private *dev_priv = dev->dev_private;
6200
6201 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6202 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6203 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6204
6205 /*
6206 * Don't touch WM1S_LP_EN here.
6207 * Doing so could cause underruns.
6208 */
6209 }
6210
6211 static void ironlake_init_clock_gating(struct drm_device *dev)
6212 {
6213 struct drm_i915_private *dev_priv = dev->dev_private;
6214 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6215
6216 /*
6217 * Required for FBC
6218 * WaFbcDisableDpfcClockGating:ilk
6219 */
6220 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6221 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6222 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6223
6224 I915_WRITE(PCH_3DCGDIS0,
6225 MARIUNIT_CLOCK_GATE_DISABLE |
6226 SVSMUNIT_CLOCK_GATE_DISABLE);
6227 I915_WRITE(PCH_3DCGDIS1,
6228 VFMUNIT_CLOCK_GATE_DISABLE);
6229
6230 /*
6231 * According to the spec the following bits should be set in
6232 * order to enable memory self-refresh
6233 * The bit 22/21 of 0x42004
6234 * The bit 5 of 0x42020
6235 * The bit 15 of 0x45000
6236 */
6237 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6238 (I915_READ(ILK_DISPLAY_CHICKEN2) |
6239 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
6240 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6241 I915_WRITE(DISP_ARB_CTL,
6242 (I915_READ(DISP_ARB_CTL) |
6243 DISP_FBC_WM_DIS));
6244
6245 ilk_init_lp_watermarks(dev);
6246
6247 /*
6248 * Based on the document from hardware guys the following bits
6249 * should be set unconditionally in order to enable FBC.
6250 * The bit 22 of 0x42000
6251 * The bit 22 of 0x42004
6252 * The bit 7,8,9 of 0x42020.
6253 */
6254 if (IS_IRONLAKE_M(dev)) {
6255 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6256 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6257 I915_READ(ILK_DISPLAY_CHICKEN1) |
6258 ILK_FBCQ_DIS);
6259 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6260 I915_READ(ILK_DISPLAY_CHICKEN2) |
6261 ILK_DPARB_GATE);
6262 }
6263
6264 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6265
6266 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6267 I915_READ(ILK_DISPLAY_CHICKEN2) |
6268 ILK_ELPIN_409_SELECT);
6269 I915_WRITE(_3D_CHICKEN2,
6270 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6271 _3D_CHICKEN2_WM_READ_PIPELINED);
6272
6273 /* WaDisableRenderCachePipelinedFlush:ilk */
6274 I915_WRITE(CACHE_MODE_0,
6275 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6276
6277 /* WaDisable_RenderCache_OperationalFlush:ilk */
6278 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6279
6280 g4x_disable_trickle_feed(dev);
6281
6282 ibx_init_clock_gating(dev);
6283 }
6284
6285 static void cpt_init_clock_gating(struct drm_device *dev)
6286 {
6287 struct drm_i915_private *dev_priv = dev->dev_private;
6288 int pipe;
6289 uint32_t val;
6290
6291 /*
6292 * On Ibex Peak and Cougar Point, we need to disable clock
6293 * gating for the panel power sequencer or it will fail to
6294 * start up when no ports are active.
6295 */
6296 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6297 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6298 PCH_CPUNIT_CLOCK_GATE_DISABLE);
6299 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6300 DPLS_EDP_PPS_FIX_DIS);
6301 /* The below fixes the weird display corruption, a few pixels shifted
6302 * downward, on (only) LVDS of some HP laptops with IVY.
6303 */
6304 for_each_pipe(dev_priv, pipe) {
6305 val = I915_READ(TRANS_CHICKEN2(pipe));
6306 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6307 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6308 if (dev_priv->vbt.fdi_rx_polarity_inverted)
6309 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6310 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6311 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6312 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
6313 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6314 }
6315 /* WADP0ClockGatingDisable */
6316 for_each_pipe(dev_priv, pipe) {
6317 I915_WRITE(TRANS_CHICKEN1(pipe),
6318 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6319 }
6320 }
6321
6322 static void gen6_check_mch_setup(struct drm_device *dev)
6323 {
6324 struct drm_i915_private *dev_priv = dev->dev_private;
6325 uint32_t tmp;
6326
6327 tmp = I915_READ(MCH_SSKPD);
6328 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6329 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6330 tmp);
6331 }
6332
6333 static void gen6_init_clock_gating(struct drm_device *dev)
6334 {
6335 struct drm_i915_private *dev_priv = dev->dev_private;
6336 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6337
6338 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6339
6340 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6341 I915_READ(ILK_DISPLAY_CHICKEN2) |
6342 ILK_ELPIN_409_SELECT);
6343
6344 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
6345 I915_WRITE(_3D_CHICKEN,
6346 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
6347
6348 /* WaSetupGtModeTdRowDispatch:snb */
6349 if (IS_SNB_GT1(dev))
6350 I915_WRITE(GEN6_GT_MODE,
6351 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
6352
6353 /* WaDisable_RenderCache_OperationalFlush:snb */
6354 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6355
6356 /*
6357 * BSpec recoomends 8x4 when MSAA is used,
6358 * however in practice 16x4 seems fastest.
6359 *
6360 * Note that PS/WM thread counts depend on the WIZ hashing
6361 * disable bit, which we don't touch here, but it's good
6362 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6363 */
6364 I915_WRITE(GEN6_GT_MODE,
6365 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
6366
6367 ilk_init_lp_watermarks(dev);
6368
6369 I915_WRITE(CACHE_MODE_0,
6370 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6371
6372 I915_WRITE(GEN6_UCGCTL1,
6373 I915_READ(GEN6_UCGCTL1) |
6374 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
6375 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6376
6377 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
6378 * gating disable must be set. Failure to set it results in
6379 * flickering pixels due to Z write ordering failures after
6380 * some amount of runtime in the Mesa "fire" demo, and Unigine
6381 * Sanctuary and Tropics, and apparently anything else with
6382 * alpha test or pixel discard.
6383 *
6384 * According to the spec, bit 11 (RCCUNIT) must also be set,
6385 * but we didn't debug actual testcases to find it out.
6386 *
6387 * WaDisableRCCUnitClockGating:snb
6388 * WaDisableRCPBUnitClockGating:snb
6389 */
6390 I915_WRITE(GEN6_UCGCTL2,
6391 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
6392 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
6393
6394 /* WaStripsFansDisableFastClipPerformanceFix:snb */
6395 I915_WRITE(_3D_CHICKEN3,
6396 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6397
6398 /*
6399 * Bspec says:
6400 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
6401 * 3DSTATE_SF number of SF output attributes is more than 16."
6402 */
6403 I915_WRITE(_3D_CHICKEN3,
6404 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
6405
6406 /*
6407 * According to the spec the following bits should be
6408 * set in order to enable memory self-refresh and fbc:
6409 * The bit21 and bit22 of 0x42000
6410 * The bit21 and bit22 of 0x42004
6411 * The bit5 and bit7 of 0x42020
6412 * The bit14 of 0x70180
6413 * The bit14 of 0x71180
6414 *
6415 * WaFbcAsynchFlipDisableFbcQueue:snb
6416 */
6417 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6418 I915_READ(ILK_DISPLAY_CHICKEN1) |
6419 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6420 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6421 I915_READ(ILK_DISPLAY_CHICKEN2) |
6422 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
6423 I915_WRITE(ILK_DSPCLK_GATE_D,
6424 I915_READ(ILK_DSPCLK_GATE_D) |
6425 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
6426 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6427
6428 g4x_disable_trickle_feed(dev);
6429
6430 cpt_init_clock_gating(dev);
6431
6432 gen6_check_mch_setup(dev);
6433 }
6434
6435 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
6436 {
6437 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
6438
6439 /*
6440 * WaVSThreadDispatchOverride:ivb,vlv
6441 *
6442 * This actually overrides the dispatch
6443 * mode for all thread types.
6444 */
6445 reg &= ~GEN7_FF_SCHED_MASK;
6446 reg |= GEN7_FF_TS_SCHED_HW;
6447 reg |= GEN7_FF_VS_SCHED_HW;
6448 reg |= GEN7_FF_DS_SCHED_HW;
6449
6450 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
6451 }
6452
6453 static void lpt_init_clock_gating(struct drm_device *dev)
6454 {
6455 struct drm_i915_private *dev_priv = dev->dev_private;
6456
6457 /*
6458 * TODO: this bit should only be enabled when really needed, then
6459 * disabled when not needed anymore in order to save power.
6460 */
6461 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
6462 I915_WRITE(SOUTH_DSPCLK_GATE_D,
6463 I915_READ(SOUTH_DSPCLK_GATE_D) |
6464 PCH_LP_PARTITION_LEVEL_DISABLE);
6465
6466 /* WADPOClockGatingDisable:hsw */
6467 I915_WRITE(_TRANSA_CHICKEN1,
6468 I915_READ(_TRANSA_CHICKEN1) |
6469 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6470 }
6471
6472 static void lpt_suspend_hw(struct drm_device *dev)
6473 {
6474 struct drm_i915_private *dev_priv = dev->dev_private;
6475
6476 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6477 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
6478
6479 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6480 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6481 }
6482 }
6483
6484 static void broadwell_init_clock_gating(struct drm_device *dev)
6485 {
6486 struct drm_i915_private *dev_priv = dev->dev_private;
6487 enum pipe pipe;
6488
6489 I915_WRITE(WM3_LP_ILK, 0);
6490 I915_WRITE(WM2_LP_ILK, 0);
6491 I915_WRITE(WM1_LP_ILK, 0);
6492
6493 /* WaSwitchSolVfFArbitrationPriority:bdw */
6494 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6495
6496 /* WaPsrDPAMaskVBlankInSRD:bdw */
6497 I915_WRITE(CHICKEN_PAR1_1,
6498 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
6499
6500 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
6501 for_each_pipe(dev_priv, pipe) {
6502 I915_WRITE(CHICKEN_PIPESL_1(pipe),
6503 I915_READ(CHICKEN_PIPESL_1(pipe)) |
6504 BDW_DPRS_MASK_VBLANK_SRD);
6505 }
6506
6507 /* WaVSRefCountFullforceMissDisable:bdw */
6508 /* WaDSRefCountFullforceMissDisable:bdw */
6509 I915_WRITE(GEN7_FF_THREAD_MODE,
6510 I915_READ(GEN7_FF_THREAD_MODE) &
6511 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
6512
6513 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6514 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
6515
6516 /* WaDisableSDEUnitClockGating:bdw */
6517 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6518 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6519
6520 lpt_init_clock_gating(dev);
6521 }
6522
6523 static void haswell_init_clock_gating(struct drm_device *dev)
6524 {
6525 struct drm_i915_private *dev_priv = dev->dev_private;
6526
6527 ilk_init_lp_watermarks(dev);
6528
6529 /* L3 caching of data atomics doesn't work -- disable it. */
6530 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
6531 I915_WRITE(HSW_ROW_CHICKEN3,
6532 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
6533
6534 /* This is required by WaCatErrorRejectionIssue:hsw */
6535 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6536 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6537 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6538
6539 /* WaVSRefCountFullforceMissDisable:hsw */
6540 I915_WRITE(GEN7_FF_THREAD_MODE,
6541 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
6542
6543 /* WaDisable_RenderCache_OperationalFlush:hsw */
6544 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6545
6546 /* enable HiZ Raw Stall Optimization */
6547 I915_WRITE(CACHE_MODE_0_GEN7,
6548 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6549
6550 /* WaDisable4x2SubspanOptimization:hsw */
6551 I915_WRITE(CACHE_MODE_1,
6552 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6553
6554 /*
6555 * BSpec recommends 8x4 when MSAA is used,
6556 * however in practice 16x4 seems fastest.
6557 *
6558 * Note that PS/WM thread counts depend on the WIZ hashing
6559 * disable bit, which we don't touch here, but it's good
6560 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6561 */
6562 I915_WRITE(GEN7_GT_MODE,
6563 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
6564
6565 /* WaSwitchSolVfFArbitrationPriority:hsw */
6566 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6567
6568 /* WaRsPkgCStateDisplayPMReq:hsw */
6569 I915_WRITE(CHICKEN_PAR1_1,
6570 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
6571
6572 lpt_init_clock_gating(dev);
6573 }
6574
6575 static void ivybridge_init_clock_gating(struct drm_device *dev)
6576 {
6577 struct drm_i915_private *dev_priv = dev->dev_private;
6578 uint32_t snpcr;
6579
6580 ilk_init_lp_watermarks(dev);
6581
6582 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6583
6584 /* WaDisableEarlyCull:ivb */
6585 I915_WRITE(_3D_CHICKEN3,
6586 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6587
6588 /* WaDisableBackToBackFlipFix:ivb */
6589 I915_WRITE(IVB_CHICKEN3,
6590 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6591 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6592
6593 /* WaDisablePSDDualDispatchEnable:ivb */
6594 if (IS_IVB_GT1(dev))
6595 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6596 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
6597
6598 /* WaDisable_RenderCache_OperationalFlush:ivb */
6599 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6600
6601 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6602 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
6603 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
6604
6605 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6606 I915_WRITE(GEN7_L3CNTLREG1,
6607 GEN7_WA_FOR_GEN7_L3_CONTROL);
6608 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
6609 GEN7_WA_L3_CHICKEN_MODE);
6610 if (IS_IVB_GT1(dev))
6611 I915_WRITE(GEN7_ROW_CHICKEN2,
6612 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6613 else {
6614 /* must write both registers */
6615 I915_WRITE(GEN7_ROW_CHICKEN2,
6616 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6617 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
6618 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6619 }
6620
6621 /* WaForceL3Serialization:ivb */
6622 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6623 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6624
6625 /*
6626 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6627 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
6628 */
6629 I915_WRITE(GEN6_UCGCTL2,
6630 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
6631
6632 /* This is required by WaCatErrorRejectionIssue:ivb */
6633 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6634 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6635 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6636
6637 g4x_disable_trickle_feed(dev);
6638
6639 gen7_setup_fixed_func_scheduler(dev_priv);
6640
6641 if (0) { /* causes HiZ corruption on ivb:gt1 */
6642 /* enable HiZ Raw Stall Optimization */
6643 I915_WRITE(CACHE_MODE_0_GEN7,
6644 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6645 }
6646
6647 /* WaDisable4x2SubspanOptimization:ivb */
6648 I915_WRITE(CACHE_MODE_1,
6649 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6650
6651 /*
6652 * BSpec recommends 8x4 when MSAA is used,
6653 * however in practice 16x4 seems fastest.
6654 *
6655 * Note that PS/WM thread counts depend on the WIZ hashing
6656 * disable bit, which we don't touch here, but it's good
6657 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6658 */
6659 I915_WRITE(GEN7_GT_MODE,
6660 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
6661
6662 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
6663 snpcr &= ~GEN6_MBC_SNPCR_MASK;
6664 snpcr |= GEN6_MBC_SNPCR_MED;
6665 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
6666
6667 if (!HAS_PCH_NOP(dev))
6668 cpt_init_clock_gating(dev);
6669
6670 gen6_check_mch_setup(dev);
6671 }
6672
6673 static void valleyview_init_clock_gating(struct drm_device *dev)
6674 {
6675 struct drm_i915_private *dev_priv = dev->dev_private;
6676
6677 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6678
6679 /* WaDisableEarlyCull:vlv */
6680 I915_WRITE(_3D_CHICKEN3,
6681 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6682
6683 /* WaDisableBackToBackFlipFix:vlv */
6684 I915_WRITE(IVB_CHICKEN3,
6685 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6686 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6687
6688 /* WaPsdDispatchEnable:vlv */
6689 /* WaDisablePSDDualDispatchEnable:vlv */
6690 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6691 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
6692 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
6693
6694 /* WaDisable_RenderCache_OperationalFlush:vlv */
6695 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6696
6697 /* WaForceL3Serialization:vlv */
6698 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6699 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6700
6701 /* WaDisableDopClockGating:vlv */
6702 I915_WRITE(GEN7_ROW_CHICKEN2,
6703 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6704
6705 /* This is required by WaCatErrorRejectionIssue:vlv */
6706 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6707 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6708 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6709
6710 gen7_setup_fixed_func_scheduler(dev_priv);
6711
6712 /*
6713 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6714 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
6715 */
6716 I915_WRITE(GEN6_UCGCTL2,
6717 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
6718
6719 /* WaDisableL3Bank2xClockGate:vlv
6720 * Disabling L3 clock gating- MMIO 940c[25] = 1
6721 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
6722 I915_WRITE(GEN7_UCGCTL4,
6723 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
6724
6725 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6726
6727 /*
6728 * BSpec says this must be set, even though
6729 * WaDisable4x2SubspanOptimization isn't listed for VLV.
6730 */
6731 I915_WRITE(CACHE_MODE_1,
6732 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6733
6734 /*
6735 * WaIncreaseL3CreditsForVLVB0:vlv
6736 * This is the hardware default actually.
6737 */
6738 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
6739
6740 /*
6741 * WaDisableVLVClockGating_VBIIssue:vlv
6742 * Disable clock gating on th GCFG unit to prevent a delay
6743 * in the reporting of vblank events.
6744 */
6745 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6746 }
6747
6748 static void cherryview_init_clock_gating(struct drm_device *dev)
6749 {
6750 struct drm_i915_private *dev_priv = dev->dev_private;
6751
6752 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6753
6754 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6755
6756 /* WaVSRefCountFullforceMissDisable:chv */
6757 /* WaDSRefCountFullforceMissDisable:chv */
6758 I915_WRITE(GEN7_FF_THREAD_MODE,
6759 I915_READ(GEN7_FF_THREAD_MODE) &
6760 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
6761
6762 /* WaDisableSemaphoreAndSyncFlipWait:chv */
6763 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6764 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
6765
6766 /* WaDisableCSUnitClockGating:chv */
6767 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
6768 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6769
6770 /* WaDisableSDEUnitClockGating:chv */
6771 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6772 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6773
6774 /* WaDisableGunitClockGating:chv (pre-production hw) */
6775 I915_WRITE(VLV_GUNIT_CLOCK_GATE, I915_READ(VLV_GUNIT_CLOCK_GATE) |
6776 GINT_DIS);
6777
6778 /* WaDisableFfDopClockGating:chv (pre-production hw) */
6779 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6780 _MASKED_BIT_ENABLE(GEN8_FF_DOP_CLOCK_GATE_DISABLE));
6781
6782 /* WaDisableDopClockGating:chv (pre-production hw) */
6783 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
6784 GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
6785 }
6786
6787 static void g4x_init_clock_gating(struct drm_device *dev)
6788 {
6789 struct drm_i915_private *dev_priv = dev->dev_private;
6790 uint32_t dspclk_gate;
6791
6792 I915_WRITE(RENCLK_GATE_D1, 0);
6793 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
6794 GS_UNIT_CLOCK_GATE_DISABLE |
6795 CL_UNIT_CLOCK_GATE_DISABLE);
6796 I915_WRITE(RAMCLK_GATE_D, 0);
6797 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
6798 OVRUNIT_CLOCK_GATE_DISABLE |
6799 OVCUNIT_CLOCK_GATE_DISABLE;
6800 if (IS_GM45(dev))
6801 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
6802 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
6803
6804 /* WaDisableRenderCachePipelinedFlush */
6805 I915_WRITE(CACHE_MODE_0,
6806 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6807
6808 /* WaDisable_RenderCache_OperationalFlush:g4x */
6809 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6810
6811 g4x_disable_trickle_feed(dev);
6812 }
6813
6814 static void crestline_init_clock_gating(struct drm_device *dev)
6815 {
6816 struct drm_i915_private *dev_priv = dev->dev_private;
6817
6818 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
6819 I915_WRITE(RENCLK_GATE_D2, 0);
6820 I915_WRITE(DSPCLK_GATE_D, 0);
6821 I915_WRITE(RAMCLK_GATE_D, 0);
6822 I915_WRITE16(DEUC, 0);
6823 I915_WRITE(MI_ARB_STATE,
6824 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6825
6826 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6827 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6828 }
6829
6830 static void broadwater_init_clock_gating(struct drm_device *dev)
6831 {
6832 struct drm_i915_private *dev_priv = dev->dev_private;
6833
6834 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
6835 I965_RCC_CLOCK_GATE_DISABLE |
6836 I965_RCPB_CLOCK_GATE_DISABLE |
6837 I965_ISC_CLOCK_GATE_DISABLE |
6838 I965_FBC_CLOCK_GATE_DISABLE);
6839 I915_WRITE(RENCLK_GATE_D2, 0);
6840 I915_WRITE(MI_ARB_STATE,
6841 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6842
6843 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6844 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6845 }
6846
6847 static void gen3_init_clock_gating(struct drm_device *dev)
6848 {
6849 struct drm_i915_private *dev_priv = dev->dev_private;
6850 u32 dstate = I915_READ(D_STATE);
6851
6852 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
6853 DSTATE_DOT_CLOCK_GATING;
6854 I915_WRITE(D_STATE, dstate);
6855
6856 if (IS_PINEVIEW(dev))
6857 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
6858
6859 /* IIR "flip pending" means done if this bit is set */
6860 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
6861
6862 /* interrupts should cause a wake up from C3 */
6863 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
6864
6865 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
6866 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
6867
6868 I915_WRITE(MI_ARB_STATE,
6869 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6870 }
6871
6872 static void i85x_init_clock_gating(struct drm_device *dev)
6873 {
6874 struct drm_i915_private *dev_priv = dev->dev_private;
6875
6876 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
6877
6878 /* interrupts should cause a wake up from C3 */
6879 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
6880 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
6881
6882 I915_WRITE(MEM_MODE,
6883 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
6884 }
6885
6886 static void i830_init_clock_gating(struct drm_device *dev)
6887 {
6888 struct drm_i915_private *dev_priv = dev->dev_private;
6889
6890 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
6891
6892 I915_WRITE(MEM_MODE,
6893 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
6894 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
6895 }
6896
6897 void intel_init_clock_gating(struct drm_device *dev)
6898 {
6899 struct drm_i915_private *dev_priv = dev->dev_private;
6900
6901 dev_priv->display.init_clock_gating(dev);
6902 }
6903
6904 void intel_suspend_hw(struct drm_device *dev)
6905 {
6906 if (HAS_PCH_LPT(dev))
6907 lpt_suspend_hw(dev);
6908 }
6909
6910 static void intel_init_fbc(struct drm_i915_private *dev_priv)
6911 {
6912 if (!HAS_FBC(dev_priv)) {
6913 dev_priv->fbc.enabled = false;
6914 return;
6915 }
6916
6917 if (INTEL_INFO(dev_priv)->gen >= 7) {
6918 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
6919 dev_priv->display.enable_fbc = gen7_enable_fbc;
6920 dev_priv->display.disable_fbc = ironlake_disable_fbc;
6921 } else if (INTEL_INFO(dev_priv)->gen >= 5) {
6922 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
6923 dev_priv->display.enable_fbc = ironlake_enable_fbc;
6924 dev_priv->display.disable_fbc = ironlake_disable_fbc;
6925 } else if (IS_GM45(dev_priv)) {
6926 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
6927 dev_priv->display.enable_fbc = g4x_enable_fbc;
6928 dev_priv->display.disable_fbc = g4x_disable_fbc;
6929 } else {
6930 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
6931 dev_priv->display.enable_fbc = i8xx_enable_fbc;
6932 dev_priv->display.disable_fbc = i8xx_disable_fbc;
6933
6934 /* This value was pulled out of someone's hat */
6935 I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);
6936 }
6937
6938 dev_priv->fbc.enabled = dev_priv->display.fbc_enabled(dev_priv->dev);
6939 }
6940
6941 /* Set up chip specific power management-related functions */
6942 void intel_init_pm(struct drm_device *dev)
6943 {
6944 struct drm_i915_private *dev_priv = dev->dev_private;
6945
6946 intel_init_fbc(dev_priv);
6947
6948 /* For cxsr */
6949 if (IS_PINEVIEW(dev))
6950 i915_pineview_get_mem_freq(dev);
6951 else if (IS_GEN5(dev))
6952 i915_ironlake_get_mem_freq(dev);
6953
6954 /* For FIFO watermark updates */
6955 if (IS_GEN9(dev)) {
6956 skl_setup_wm_latency(dev);
6957
6958 dev_priv->display.init_clock_gating = gen9_init_clock_gating;
6959 dev_priv->display.update_wm = skl_update_wm;
6960 dev_priv->display.update_sprite_wm = skl_update_sprite_wm;
6961 } else if (HAS_PCH_SPLIT(dev)) {
6962 ilk_setup_wm_latency(dev);
6963
6964 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
6965 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
6966 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
6967 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
6968 dev_priv->display.update_wm = ilk_update_wm;
6969 dev_priv->display.update_sprite_wm = ilk_update_sprite_wm;
6970 } else {
6971 DRM_DEBUG_KMS("Failed to read display plane latency. "
6972 "Disable CxSR\n");
6973 }
6974
6975 if (IS_GEN5(dev))
6976 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
6977 else if (IS_GEN6(dev))
6978 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
6979 else if (IS_IVYBRIDGE(dev))
6980 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
6981 else if (IS_HASWELL(dev))
6982 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
6983 else if (INTEL_INFO(dev)->gen == 8)
6984 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
6985 } else if (IS_CHERRYVIEW(dev)) {
6986 dev_priv->display.update_wm = cherryview_update_wm;
6987 dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;
6988 dev_priv->display.init_clock_gating =
6989 cherryview_init_clock_gating;
6990 } else if (IS_VALLEYVIEW(dev)) {
6991 dev_priv->display.update_wm = valleyview_update_wm;
6992 dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;
6993 dev_priv->display.init_clock_gating =
6994 valleyview_init_clock_gating;
6995 } else if (IS_PINEVIEW(dev)) {
6996 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
6997 dev_priv->is_ddr3,
6998 dev_priv->fsb_freq,
6999 dev_priv->mem_freq)) {
7000 DRM_INFO("failed to find known CxSR latency "
7001 "(found ddr%s fsb freq %d, mem freq %d), "
7002 "disabling CxSR\n",
7003 (dev_priv->is_ddr3 == 1) ? "3" : "2",
7004 dev_priv->fsb_freq, dev_priv->mem_freq);
7005 /* Disable CxSR and never update its watermark again */
7006 intel_set_memory_cxsr(dev_priv, false);
7007 dev_priv->display.update_wm = NULL;
7008 } else
7009 dev_priv->display.update_wm = pineview_update_wm;
7010 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7011 } else if (IS_G4X(dev)) {
7012 dev_priv->display.update_wm = g4x_update_wm;
7013 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7014 } else if (IS_GEN4(dev)) {
7015 dev_priv->display.update_wm = i965_update_wm;
7016 if (IS_CRESTLINE(dev))
7017 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7018 else if (IS_BROADWATER(dev))
7019 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7020 } else if (IS_GEN3(dev)) {
7021 dev_priv->display.update_wm = i9xx_update_wm;
7022 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7023 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7024 } else if (IS_GEN2(dev)) {
7025 if (INTEL_INFO(dev)->num_pipes == 1) {
7026 dev_priv->display.update_wm = i845_update_wm;
7027 dev_priv->display.get_fifo_size = i845_get_fifo_size;
7028 } else {
7029 dev_priv->display.update_wm = i9xx_update_wm;
7030 dev_priv->display.get_fifo_size = i830_get_fifo_size;
7031 }
7032
7033 if (IS_I85X(dev) || IS_I865G(dev))
7034 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7035 else
7036 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7037 } else {
7038 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
7039 }
7040 }
7041
7042 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
7043 {
7044 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7045
7046 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7047 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7048 return -EAGAIN;
7049 }
7050
7051 I915_WRITE(GEN6_PCODE_DATA, *val);
7052 if (INTEL_INFO(dev_priv)->gen >= 9)
7053 I915_WRITE(GEN9_PCODE_DATA1, 0);
7054 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7055
7056 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7057 500)) {
7058 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7059 return -ETIMEDOUT;
7060 }
7061
7062 *val = I915_READ(GEN6_PCODE_DATA);
7063 I915_WRITE(GEN6_PCODE_DATA, 0);
7064
7065 return 0;
7066 }
7067
7068 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
7069 {
7070 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7071
7072 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7073 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7074 return -EAGAIN;
7075 }
7076
7077 I915_WRITE(GEN6_PCODE_DATA, val);
7078 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7079
7080 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7081 500)) {
7082 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7083 return -ETIMEDOUT;
7084 }
7085
7086 I915_WRITE(GEN6_PCODE_DATA, 0);
7087
7088 return 0;
7089 }
7090
7091 static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7092 {
7093 int div;
7094
7095 /* 4 x czclk */
7096 switch (dev_priv->mem_freq) {
7097 case 800:
7098 div = 10;
7099 break;
7100 case 1066:
7101 div = 12;
7102 break;
7103 case 1333:
7104 div = 16;
7105 break;
7106 default:
7107 return -1;
7108 }
7109
7110 return DIV_ROUND_CLOSEST(dev_priv->mem_freq * (val + 6 - 0xbd), 4 * div);
7111 }
7112
7113 static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
7114 {
7115 int mul;
7116
7117 /* 4 x czclk */
7118 switch (dev_priv->mem_freq) {
7119 case 800:
7120 mul = 10;
7121 break;
7122 case 1066:
7123 mul = 12;
7124 break;
7125 case 1333:
7126 mul = 16;
7127 break;
7128 default:
7129 return -1;
7130 }
7131
7132 return DIV_ROUND_CLOSEST(4 * mul * val, dev_priv->mem_freq) + 0xbd - 6;
7133 }
7134
7135 static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
7136 {
7137 int div, freq;
7138
7139 switch (dev_priv->rps.cz_freq) {
7140 case 200:
7141 div = 5;
7142 break;
7143 case 267:
7144 div = 6;
7145 break;
7146 case 320:
7147 case 333:
7148 case 400:
7149 div = 8;
7150 break;
7151 default:
7152 return -1;
7153 }
7154
7155 freq = (DIV_ROUND_CLOSEST((dev_priv->rps.cz_freq * val), 2 * div) / 2);
7156
7157 return freq;
7158 }
7159
7160 static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
7161 {
7162 int mul, opcode;
7163
7164 switch (dev_priv->rps.cz_freq) {
7165 case 200:
7166 mul = 5;
7167 break;
7168 case 267:
7169 mul = 6;
7170 break;
7171 case 320:
7172 case 333:
7173 case 400:
7174 mul = 8;
7175 break;
7176 default:
7177 return -1;
7178 }
7179
7180 /* CHV needs even values */
7181 opcode = (DIV_ROUND_CLOSEST((val * 2 * mul), dev_priv->rps.cz_freq) * 2);
7182
7183 return opcode;
7184 }
7185
7186 int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val)
7187 {
7188 int ret = -1;
7189
7190 if (IS_CHERRYVIEW(dev_priv->dev))
7191 ret = chv_gpu_freq(dev_priv, val);
7192 else if (IS_VALLEYVIEW(dev_priv->dev))
7193 ret = byt_gpu_freq(dev_priv, val);
7194
7195 return ret;
7196 }
7197
7198 int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val)
7199 {
7200 int ret = -1;
7201
7202 if (IS_CHERRYVIEW(dev_priv->dev))
7203 ret = chv_freq_opcode(dev_priv, val);
7204 else if (IS_VALLEYVIEW(dev_priv->dev))
7205 ret = byt_freq_opcode(dev_priv, val);
7206
7207 return ret;
7208 }
7209
7210 void intel_pm_setup(struct drm_device *dev)
7211 {
7212 struct drm_i915_private *dev_priv = dev->dev_private;
7213
7214 mutex_init(&dev_priv->rps.hw_lock);
7215
7216 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
7217 intel_gen6_powersave_work);
7218
7219 dev_priv->pm.suspended = false;
7220 }
Linux kernel - Deliverables
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