projects / deliverable / linux.git / blob
? search:


48283167c19521dd31bee08cb2e101efaad1b8c7
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_pm.c
1 /*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28 #include <linux/cpufreq.h>
29 #include "i915_drv.h"
30 #include "intel_drv.h"
31 #include "../../../platform/x86/intel_ips.h"
32 #include <linux/module.h>
33
34 #define FORCEWAKE_ACK_TIMEOUT_MS 2
35
36 /* FBC, or Frame Buffer Compression, is a technique employed to compress the
37 * framebuffer contents in-memory, aiming at reducing the required bandwidth
38 * during in-memory transfers and, therefore, reduce the power packet.
39 *
40 * The benefits of FBC are mostly visible with solid backgrounds and
41 * variation-less patterns.
42 *
43 * FBC-related functionality can be enabled by the means of the
44 * i915.i915_enable_fbc parameter
45 */
46
47 static bool intel_crtc_active(struct drm_crtc *crtc)
48 {
49 /* Be paranoid as we can arrive here with only partial
50 * state retrieved from the hardware during setup.
51 */
52 return to_intel_crtc(crtc)->active && crtc->fb && crtc->mode.clock;
53 }
54
55 static void i8xx_disable_fbc(struct drm_device *dev)
56 {
57 struct drm_i915_private *dev_priv = dev->dev_private;
58 u32 fbc_ctl;
59
60 /* Disable compression */
61 fbc_ctl = I915_READ(FBC_CONTROL);
62 if ((fbc_ctl & FBC_CTL_EN) == 0)
63 return;
64
65 fbc_ctl &= ~FBC_CTL_EN;
66 I915_WRITE(FBC_CONTROL, fbc_ctl);
67
68 /* Wait for compressing bit to clear */
69 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
70 DRM_DEBUG_KMS("FBC idle timed out\n");
71 return;
72 }
73
74 DRM_DEBUG_KMS("disabled FBC\n");
75 }
76
77 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
78 {
79 struct drm_device *dev = crtc->dev;
80 struct drm_i915_private *dev_priv = dev->dev_private;
81 struct drm_framebuffer *fb = crtc->fb;
82 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
83 struct drm_i915_gem_object *obj = intel_fb->obj;
84 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
85 int cfb_pitch;
86 int plane, i;
87 u32 fbc_ctl, fbc_ctl2;
88
89 cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
90 if (fb->pitches[0] < cfb_pitch)
91 cfb_pitch = fb->pitches[0];
92
93 /* FBC_CTL wants 64B units */
94 cfb_pitch = (cfb_pitch / 64) - 1;
95 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
96
97 /* Clear old tags */
98 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
99 I915_WRITE(FBC_TAG + (i * 4), 0);
100
101 /* Set it up... */
102 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
103 fbc_ctl2 |= plane;
104 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
105 I915_WRITE(FBC_FENCE_OFF, crtc->y);
106
107 /* enable it... */
108 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
109 if (IS_I945GM(dev))
110 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
111 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
112 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
113 fbc_ctl |= obj->fence_reg;
114 I915_WRITE(FBC_CONTROL, fbc_ctl);
115
116 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c, ",
117 cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
118 }
119
120 static bool i8xx_fbc_enabled(struct drm_device *dev)
121 {
122 struct drm_i915_private *dev_priv = dev->dev_private;
123
124 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
125 }
126
127 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
128 {
129 struct drm_device *dev = crtc->dev;
130 struct drm_i915_private *dev_priv = dev->dev_private;
131 struct drm_framebuffer *fb = crtc->fb;
132 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
133 struct drm_i915_gem_object *obj = intel_fb->obj;
134 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
135 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
136 unsigned long stall_watermark = 200;
137 u32 dpfc_ctl;
138
139 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
140 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
141 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
142
143 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
144 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
145 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
146 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
147
148 /* enable it... */
149 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
150
151 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
152 }
153
154 static void g4x_disable_fbc(struct drm_device *dev)
155 {
156 struct drm_i915_private *dev_priv = dev->dev_private;
157 u32 dpfc_ctl;
158
159 /* Disable compression */
160 dpfc_ctl = I915_READ(DPFC_CONTROL);
161 if (dpfc_ctl & DPFC_CTL_EN) {
162 dpfc_ctl &= ~DPFC_CTL_EN;
163 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
164
165 DRM_DEBUG_KMS("disabled FBC\n");
166 }
167 }
168
169 static bool g4x_fbc_enabled(struct drm_device *dev)
170 {
171 struct drm_i915_private *dev_priv = dev->dev_private;
172
173 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
174 }
175
176 static void sandybridge_blit_fbc_update(struct drm_device *dev)
177 {
178 struct drm_i915_private *dev_priv = dev->dev_private;
179 u32 blt_ecoskpd;
180
181 /* Make sure blitter notifies FBC of writes */
182 gen6_gt_force_wake_get(dev_priv);
183 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
184 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
185 GEN6_BLITTER_LOCK_SHIFT;
186 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
187 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
188 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
189 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
190 GEN6_BLITTER_LOCK_SHIFT);
191 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
192 POSTING_READ(GEN6_BLITTER_ECOSKPD);
193 gen6_gt_force_wake_put(dev_priv);
194 }
195
196 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
197 {
198 struct drm_device *dev = crtc->dev;
199 struct drm_i915_private *dev_priv = dev->dev_private;
200 struct drm_framebuffer *fb = crtc->fb;
201 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
202 struct drm_i915_gem_object *obj = intel_fb->obj;
203 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
204 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
205 unsigned long stall_watermark = 200;
206 u32 dpfc_ctl;
207
208 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
209 dpfc_ctl &= DPFC_RESERVED;
210 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
211 /* Set persistent mode for front-buffer rendering, ala X. */
212 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
213 dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
214 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
215
216 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
217 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
218 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
219 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
220 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
221 /* enable it... */
222 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
223
224 if (IS_GEN6(dev)) {
225 I915_WRITE(SNB_DPFC_CTL_SA,
226 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
227 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
228 sandybridge_blit_fbc_update(dev);
229 }
230
231 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
232 }
233
234 static void ironlake_disable_fbc(struct drm_device *dev)
235 {
236 struct drm_i915_private *dev_priv = dev->dev_private;
237 u32 dpfc_ctl;
238
239 /* Disable compression */
240 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
241 if (dpfc_ctl & DPFC_CTL_EN) {
242 dpfc_ctl &= ~DPFC_CTL_EN;
243 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
244
245 DRM_DEBUG_KMS("disabled FBC\n");
246 }
247 }
248
249 static bool ironlake_fbc_enabled(struct drm_device *dev)
250 {
251 struct drm_i915_private *dev_priv = dev->dev_private;
252
253 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
254 }
255
256 static void gen7_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
257 {
258 struct drm_device *dev = crtc->dev;
259 struct drm_i915_private *dev_priv = dev->dev_private;
260 struct drm_framebuffer *fb = crtc->fb;
261 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
262 struct drm_i915_gem_object *obj = intel_fb->obj;
263 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
264
265 I915_WRITE(IVB_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
266
267 I915_WRITE(ILK_DPFC_CONTROL, DPFC_CTL_EN | DPFC_CTL_LIMIT_1X |
268 IVB_DPFC_CTL_FENCE_EN |
269 intel_crtc->plane << IVB_DPFC_CTL_PLANE_SHIFT);
270
271 /* WaFbcAsynchFlipDisableFbcQueue */
272 I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS);
273 I915_WRITE(SNB_DPFC_CTL_SA,
274 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
275 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
276
277 sandybridge_blit_fbc_update(dev);
278
279 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
280 }
281
282 bool intel_fbc_enabled(struct drm_device *dev)
283 {
284 struct drm_i915_private *dev_priv = dev->dev_private;
285
286 if (!dev_priv->display.fbc_enabled)
287 return false;
288
289 return dev_priv->display.fbc_enabled(dev);
290 }
291
292 static void intel_fbc_work_fn(struct work_struct *__work)
293 {
294 struct intel_fbc_work *work =
295 container_of(to_delayed_work(__work),
296 struct intel_fbc_work, work);
297 struct drm_device *dev = work->crtc->dev;
298 struct drm_i915_private *dev_priv = dev->dev_private;
299
300 mutex_lock(&dev->struct_mutex);
301 if (work == dev_priv->fbc_work) {
302 /* Double check that we haven't switched fb without cancelling
303 * the prior work.
304 */
305 if (work->crtc->fb == work->fb) {
306 dev_priv->display.enable_fbc(work->crtc,
307 work->interval);
308
309 dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
310 dev_priv->cfb_fb = work->crtc->fb->base.id;
311 dev_priv->cfb_y = work->crtc->y;
312 }
313
314 dev_priv->fbc_work = NULL;
315 }
316 mutex_unlock(&dev->struct_mutex);
317
318 kfree(work);
319 }
320
321 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
322 {
323 if (dev_priv->fbc_work == NULL)
324 return;
325
326 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
327
328 /* Synchronisation is provided by struct_mutex and checking of
329 * dev_priv->fbc_work, so we can perform the cancellation
330 * entirely asynchronously.
331 */
332 if (cancel_delayed_work(&dev_priv->fbc_work->work))
333 /* tasklet was killed before being run, clean up */
334 kfree(dev_priv->fbc_work);
335
336 /* Mark the work as no longer wanted so that if it does
337 * wake-up (because the work was already running and waiting
338 * for our mutex), it will discover that is no longer
339 * necessary to run.
340 */
341 dev_priv->fbc_work = NULL;
342 }
343
344 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
345 {
346 struct intel_fbc_work *work;
347 struct drm_device *dev = crtc->dev;
348 struct drm_i915_private *dev_priv = dev->dev_private;
349
350 if (!dev_priv->display.enable_fbc)
351 return;
352
353 intel_cancel_fbc_work(dev_priv);
354
355 work = kzalloc(sizeof *work, GFP_KERNEL);
356 if (work == NULL) {
357 dev_priv->display.enable_fbc(crtc, interval);
358 return;
359 }
360
361 work->crtc = crtc;
362 work->fb = crtc->fb;
363 work->interval = interval;
364 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
365
366 dev_priv->fbc_work = work;
367
368 DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
369
370 /* Delay the actual enabling to let pageflipping cease and the
371 * display to settle before starting the compression. Note that
372 * this delay also serves a second purpose: it allows for a
373 * vblank to pass after disabling the FBC before we attempt
374 * to modify the control registers.
375 *
376 * A more complicated solution would involve tracking vblanks
377 * following the termination of the page-flipping sequence
378 * and indeed performing the enable as a co-routine and not
379 * waiting synchronously upon the vblank.
380 */
381 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
382 }
383
384 void intel_disable_fbc(struct drm_device *dev)
385 {
386 struct drm_i915_private *dev_priv = dev->dev_private;
387
388 intel_cancel_fbc_work(dev_priv);
389
390 if (!dev_priv->display.disable_fbc)
391 return;
392
393 dev_priv->display.disable_fbc(dev);
394 dev_priv->cfb_plane = -1;
395 }
396
397 /**
398 * intel_update_fbc - enable/disable FBC as needed
399 * @dev: the drm_device
400 *
401 * Set up the framebuffer compression hardware at mode set time. We
402 * enable it if possible:
403 * - plane A only (on pre-965)
404 * - no pixel mulitply/line duplication
405 * - no alpha buffer discard
406 * - no dual wide
407 * - framebuffer <= 2048 in width, 1536 in height
408 *
409 * We can't assume that any compression will take place (worst case),
410 * so the compressed buffer has to be the same size as the uncompressed
411 * one. It also must reside (along with the line length buffer) in
412 * stolen memory.
413 *
414 * We need to enable/disable FBC on a global basis.
415 */
416 void intel_update_fbc(struct drm_device *dev)
417 {
418 struct drm_i915_private *dev_priv = dev->dev_private;
419 struct drm_crtc *crtc = NULL, *tmp_crtc;
420 struct intel_crtc *intel_crtc;
421 struct drm_framebuffer *fb;
422 struct intel_framebuffer *intel_fb;
423 struct drm_i915_gem_object *obj;
424 int enable_fbc;
425
426 if (!i915_powersave)
427 return;
428
429 if (!I915_HAS_FBC(dev))
430 return;
431
432 /*
433 * If FBC is already on, we just have to verify that we can
434 * keep it that way...
435 * Need to disable if:
436 * - more than one pipe is active
437 * - changing FBC params (stride, fence, mode)
438 * - new fb is too large to fit in compressed buffer
439 * - going to an unsupported config (interlace, pixel multiply, etc.)
440 */
441 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
442 if (intel_crtc_active(tmp_crtc) &&
443 !to_intel_crtc(tmp_crtc)->primary_disabled) {
444 if (crtc) {
445 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
446 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
447 goto out_disable;
448 }
449 crtc = tmp_crtc;
450 }
451 }
452
453 if (!crtc || crtc->fb == NULL) {
454 DRM_DEBUG_KMS("no output, disabling\n");
455 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
456 goto out_disable;
457 }
458
459 intel_crtc = to_intel_crtc(crtc);
460 fb = crtc->fb;
461 intel_fb = to_intel_framebuffer(fb);
462 obj = intel_fb->obj;
463
464 enable_fbc = i915_enable_fbc;
465 if (enable_fbc < 0) {
466 DRM_DEBUG_KMS("fbc set to per-chip default\n");
467 enable_fbc = 1;
468 if (INTEL_INFO(dev)->gen <= 7)
469 enable_fbc = 0;
470 }
471 if (!enable_fbc) {
472 DRM_DEBUG_KMS("fbc disabled per module param\n");
473 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
474 goto out_disable;
475 }
476 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
477 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
478 DRM_DEBUG_KMS("mode incompatible with compression, "
479 "disabling\n");
480 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
481 goto out_disable;
482 }
483 if ((crtc->mode.hdisplay > 2048) ||
484 (crtc->mode.vdisplay > 1536)) {
485 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
486 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
487 goto out_disable;
488 }
489 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
490 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
491 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
492 goto out_disable;
493 }
494
495 /* The use of a CPU fence is mandatory in order to detect writes
496 * by the CPU to the scanout and trigger updates to the FBC.
497 */
498 if (obj->tiling_mode != I915_TILING_X ||
499 obj->fence_reg == I915_FENCE_REG_NONE) {
500 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
501 dev_priv->no_fbc_reason = FBC_NOT_TILED;
502 goto out_disable;
503 }
504
505 /* If the kernel debugger is active, always disable compression */
506 if (in_dbg_master())
507 goto out_disable;
508
509 if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) {
510 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
511 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
512 goto out_disable;
513 }
514
515 /* If the scanout has not changed, don't modify the FBC settings.
516 * Note that we make the fundamental assumption that the fb->obj
517 * cannot be unpinned (and have its GTT offset and fence revoked)
518 * without first being decoupled from the scanout and FBC disabled.
519 */
520 if (dev_priv->cfb_plane == intel_crtc->plane &&
521 dev_priv->cfb_fb == fb->base.id &&
522 dev_priv->cfb_y == crtc->y)
523 return;
524
525 if (intel_fbc_enabled(dev)) {
526 /* We update FBC along two paths, after changing fb/crtc
527 * configuration (modeswitching) and after page-flipping
528 * finishes. For the latter, we know that not only did
529 * we disable the FBC at the start of the page-flip
530 * sequence, but also more than one vblank has passed.
531 *
532 * For the former case of modeswitching, it is possible
533 * to switch between two FBC valid configurations
534 * instantaneously so we do need to disable the FBC
535 * before we can modify its control registers. We also
536 * have to wait for the next vblank for that to take
537 * effect. However, since we delay enabling FBC we can
538 * assume that a vblank has passed since disabling and
539 * that we can safely alter the registers in the deferred
540 * callback.
541 *
542 * In the scenario that we go from a valid to invalid
543 * and then back to valid FBC configuration we have
544 * no strict enforcement that a vblank occurred since
545 * disabling the FBC. However, along all current pipe
546 * disabling paths we do need to wait for a vblank at
547 * some point. And we wait before enabling FBC anyway.
548 */
549 DRM_DEBUG_KMS("disabling active FBC for update\n");
550 intel_disable_fbc(dev);
551 }
552
553 intel_enable_fbc(crtc, 500);
554 return;
555
556 out_disable:
557 /* Multiple disables should be harmless */
558 if (intel_fbc_enabled(dev)) {
559 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
560 intel_disable_fbc(dev);
561 }
562 i915_gem_stolen_cleanup_compression(dev);
563 }
564
565 static void i915_pineview_get_mem_freq(struct drm_device *dev)
566 {
567 drm_i915_private_t *dev_priv = dev->dev_private;
568 u32 tmp;
569
570 tmp = I915_READ(CLKCFG);
571
572 switch (tmp & CLKCFG_FSB_MASK) {
573 case CLKCFG_FSB_533:
574 dev_priv->fsb_freq = 533; /* 133*4 */
575 break;
576 case CLKCFG_FSB_800:
577 dev_priv->fsb_freq = 800; /* 200*4 */
578 break;
579 case CLKCFG_FSB_667:
580 dev_priv->fsb_freq = 667; /* 167*4 */
581 break;
582 case CLKCFG_FSB_400:
583 dev_priv->fsb_freq = 400; /* 100*4 */
584 break;
585 }
586
587 switch (tmp & CLKCFG_MEM_MASK) {
588 case CLKCFG_MEM_533:
589 dev_priv->mem_freq = 533;
590 break;
591 case CLKCFG_MEM_667:
592 dev_priv->mem_freq = 667;
593 break;
594 case CLKCFG_MEM_800:
595 dev_priv->mem_freq = 800;
596 break;
597 }
598
599 /* detect pineview DDR3 setting */
600 tmp = I915_READ(CSHRDDR3CTL);
601 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
602 }
603
604 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
605 {
606 drm_i915_private_t *dev_priv = dev->dev_private;
607 u16 ddrpll, csipll;
608
609 ddrpll = I915_READ16(DDRMPLL1);
610 csipll = I915_READ16(CSIPLL0);
611
612 switch (ddrpll & 0xff) {
613 case 0xc:
614 dev_priv->mem_freq = 800;
615 break;
616 case 0x10:
617 dev_priv->mem_freq = 1066;
618 break;
619 case 0x14:
620 dev_priv->mem_freq = 1333;
621 break;
622 case 0x18:
623 dev_priv->mem_freq = 1600;
624 break;
625 default:
626 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
627 ddrpll & 0xff);
628 dev_priv->mem_freq = 0;
629 break;
630 }
631
632 dev_priv->ips.r_t = dev_priv->mem_freq;
633
634 switch (csipll & 0x3ff) {
635 case 0x00c:
636 dev_priv->fsb_freq = 3200;
637 break;
638 case 0x00e:
639 dev_priv->fsb_freq = 3733;
640 break;
641 case 0x010:
642 dev_priv->fsb_freq = 4266;
643 break;
644 case 0x012:
645 dev_priv->fsb_freq = 4800;
646 break;
647 case 0x014:
648 dev_priv->fsb_freq = 5333;
649 break;
650 case 0x016:
651 dev_priv->fsb_freq = 5866;
652 break;
653 case 0x018:
654 dev_priv->fsb_freq = 6400;
655 break;
656 default:
657 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
658 csipll & 0x3ff);
659 dev_priv->fsb_freq = 0;
660 break;
661 }
662
663 if (dev_priv->fsb_freq == 3200) {
664 dev_priv->ips.c_m = 0;
665 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
666 dev_priv->ips.c_m = 1;
667 } else {
668 dev_priv->ips.c_m = 2;
669 }
670 }
671
672 static const struct cxsr_latency cxsr_latency_table[] = {
673 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
674 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
675 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
676 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
677 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
678
679 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
680 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
681 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
682 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
683 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
684
685 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
686 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
687 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
688 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
689 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
690
691 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
692 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
693 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
694 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
695 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
696
697 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
698 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
699 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
700 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
701 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
702
703 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
704 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
705 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
706 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
707 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
708 };
709
710 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
711 int is_ddr3,
712 int fsb,
713 int mem)
714 {
715 const struct cxsr_latency *latency;
716 int i;
717
718 if (fsb == 0 || mem == 0)
719 return NULL;
720
721 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
722 latency = &cxsr_latency_table[i];
723 if (is_desktop == latency->is_desktop &&
724 is_ddr3 == latency->is_ddr3 &&
725 fsb == latency->fsb_freq && mem == latency->mem_freq)
726 return latency;
727 }
728
729 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
730
731 return NULL;
732 }
733
734 static void pineview_disable_cxsr(struct drm_device *dev)
735 {
736 struct drm_i915_private *dev_priv = dev->dev_private;
737
738 /* deactivate cxsr */
739 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
740 }
741
742 /*
743 * Latency for FIFO fetches is dependent on several factors:
744 * - memory configuration (speed, channels)
745 * - chipset
746 * - current MCH state
747 * It can be fairly high in some situations, so here we assume a fairly
748 * pessimal value. It's a tradeoff between extra memory fetches (if we
749 * set this value too high, the FIFO will fetch frequently to stay full)
750 * and power consumption (set it too low to save power and we might see
751 * FIFO underruns and display "flicker").
752 *
753 * A value of 5us seems to be a good balance; safe for very low end
754 * platforms but not overly aggressive on lower latency configs.
755 */
756 static const int latency_ns = 5000;
757
758 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
759 {
760 struct drm_i915_private *dev_priv = dev->dev_private;
761 uint32_t dsparb = I915_READ(DSPARB);
762 int size;
763
764 size = dsparb & 0x7f;
765 if (plane)
766 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
767
768 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
769 plane ? "B" : "A", size);
770
771 return size;
772 }
773
774 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
775 {
776 struct drm_i915_private *dev_priv = dev->dev_private;
777 uint32_t dsparb = I915_READ(DSPARB);
778 int size;
779
780 size = dsparb & 0x1ff;
781 if (plane)
782 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
783 size >>= 1; /* Convert to cachelines */
784
785 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
786 plane ? "B" : "A", size);
787
788 return size;
789 }
790
791 static int i845_get_fifo_size(struct drm_device *dev, int plane)
792 {
793 struct drm_i915_private *dev_priv = dev->dev_private;
794 uint32_t dsparb = I915_READ(DSPARB);
795 int size;
796
797 size = dsparb & 0x7f;
798 size >>= 2; /* Convert to cachelines */
799
800 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
801 plane ? "B" : "A",
802 size);
803
804 return size;
805 }
806
807 static int i830_get_fifo_size(struct drm_device *dev, int plane)
808 {
809 struct drm_i915_private *dev_priv = dev->dev_private;
810 uint32_t dsparb = I915_READ(DSPARB);
811 int size;
812
813 size = dsparb & 0x7f;
814 size >>= 1; /* Convert to cachelines */
815
816 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
817 plane ? "B" : "A", size);
818
819 return size;
820 }
821
822 /* Pineview has different values for various configs */
823 static const struct intel_watermark_params pineview_display_wm = {
824 PINEVIEW_DISPLAY_FIFO,
825 PINEVIEW_MAX_WM,
826 PINEVIEW_DFT_WM,
827 PINEVIEW_GUARD_WM,
828 PINEVIEW_FIFO_LINE_SIZE
829 };
830 static const struct intel_watermark_params pineview_display_hplloff_wm = {
831 PINEVIEW_DISPLAY_FIFO,
832 PINEVIEW_MAX_WM,
833 PINEVIEW_DFT_HPLLOFF_WM,
834 PINEVIEW_GUARD_WM,
835 PINEVIEW_FIFO_LINE_SIZE
836 };
837 static const struct intel_watermark_params pineview_cursor_wm = {
838 PINEVIEW_CURSOR_FIFO,
839 PINEVIEW_CURSOR_MAX_WM,
840 PINEVIEW_CURSOR_DFT_WM,
841 PINEVIEW_CURSOR_GUARD_WM,
842 PINEVIEW_FIFO_LINE_SIZE,
843 };
844 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
845 PINEVIEW_CURSOR_FIFO,
846 PINEVIEW_CURSOR_MAX_WM,
847 PINEVIEW_CURSOR_DFT_WM,
848 PINEVIEW_CURSOR_GUARD_WM,
849 PINEVIEW_FIFO_LINE_SIZE
850 };
851 static const struct intel_watermark_params g4x_wm_info = {
852 G4X_FIFO_SIZE,
853 G4X_MAX_WM,
854 G4X_MAX_WM,
855 2,
856 G4X_FIFO_LINE_SIZE,
857 };
858 static const struct intel_watermark_params g4x_cursor_wm_info = {
859 I965_CURSOR_FIFO,
860 I965_CURSOR_MAX_WM,
861 I965_CURSOR_DFT_WM,
862 2,
863 G4X_FIFO_LINE_SIZE,
864 };
865 static const struct intel_watermark_params valleyview_wm_info = {
866 VALLEYVIEW_FIFO_SIZE,
867 VALLEYVIEW_MAX_WM,
868 VALLEYVIEW_MAX_WM,
869 2,
870 G4X_FIFO_LINE_SIZE,
871 };
872 static const struct intel_watermark_params valleyview_cursor_wm_info = {
873 I965_CURSOR_FIFO,
874 VALLEYVIEW_CURSOR_MAX_WM,
875 I965_CURSOR_DFT_WM,
876 2,
877 G4X_FIFO_LINE_SIZE,
878 };
879 static const struct intel_watermark_params i965_cursor_wm_info = {
880 I965_CURSOR_FIFO,
881 I965_CURSOR_MAX_WM,
882 I965_CURSOR_DFT_WM,
883 2,
884 I915_FIFO_LINE_SIZE,
885 };
886 static const struct intel_watermark_params i945_wm_info = {
887 I945_FIFO_SIZE,
888 I915_MAX_WM,
889 1,
890 2,
891 I915_FIFO_LINE_SIZE
892 };
893 static const struct intel_watermark_params i915_wm_info = {
894 I915_FIFO_SIZE,
895 I915_MAX_WM,
896 1,
897 2,
898 I915_FIFO_LINE_SIZE
899 };
900 static const struct intel_watermark_params i855_wm_info = {
901 I855GM_FIFO_SIZE,
902 I915_MAX_WM,
903 1,
904 2,
905 I830_FIFO_LINE_SIZE
906 };
907 static const struct intel_watermark_params i830_wm_info = {
908 I830_FIFO_SIZE,
909 I915_MAX_WM,
910 1,
911 2,
912 I830_FIFO_LINE_SIZE
913 };
914
915 static const struct intel_watermark_params ironlake_display_wm_info = {
916 ILK_DISPLAY_FIFO,
917 ILK_DISPLAY_MAXWM,
918 ILK_DISPLAY_DFTWM,
919 2,
920 ILK_FIFO_LINE_SIZE
921 };
922 static const struct intel_watermark_params ironlake_cursor_wm_info = {
923 ILK_CURSOR_FIFO,
924 ILK_CURSOR_MAXWM,
925 ILK_CURSOR_DFTWM,
926 2,
927 ILK_FIFO_LINE_SIZE
928 };
929 static const struct intel_watermark_params ironlake_display_srwm_info = {
930 ILK_DISPLAY_SR_FIFO,
931 ILK_DISPLAY_MAX_SRWM,
932 ILK_DISPLAY_DFT_SRWM,
933 2,
934 ILK_FIFO_LINE_SIZE
935 };
936 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
937 ILK_CURSOR_SR_FIFO,
938 ILK_CURSOR_MAX_SRWM,
939 ILK_CURSOR_DFT_SRWM,
940 2,
941 ILK_FIFO_LINE_SIZE
942 };
943
944 static const struct intel_watermark_params sandybridge_display_wm_info = {
945 SNB_DISPLAY_FIFO,
946 SNB_DISPLAY_MAXWM,
947 SNB_DISPLAY_DFTWM,
948 2,
949 SNB_FIFO_LINE_SIZE
950 };
951 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
952 SNB_CURSOR_FIFO,
953 SNB_CURSOR_MAXWM,
954 SNB_CURSOR_DFTWM,
955 2,
956 SNB_FIFO_LINE_SIZE
957 };
958 static const struct intel_watermark_params sandybridge_display_srwm_info = {
959 SNB_DISPLAY_SR_FIFO,
960 SNB_DISPLAY_MAX_SRWM,
961 SNB_DISPLAY_DFT_SRWM,
962 2,
963 SNB_FIFO_LINE_SIZE
964 };
965 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
966 SNB_CURSOR_SR_FIFO,
967 SNB_CURSOR_MAX_SRWM,
968 SNB_CURSOR_DFT_SRWM,
969 2,
970 SNB_FIFO_LINE_SIZE
971 };
972
973
974 /**
975 * intel_calculate_wm - calculate watermark level
976 * @clock_in_khz: pixel clock
977 * @wm: chip FIFO params
978 * @pixel_size: display pixel size
979 * @latency_ns: memory latency for the platform
980 *
981 * Calculate the watermark level (the level at which the display plane will
982 * start fetching from memory again). Each chip has a different display
983 * FIFO size and allocation, so the caller needs to figure that out and pass
984 * in the correct intel_watermark_params structure.
985 *
986 * As the pixel clock runs, the FIFO will be drained at a rate that depends
987 * on the pixel size. When it reaches the watermark level, it'll start
988 * fetching FIFO line sized based chunks from memory until the FIFO fills
989 * past the watermark point. If the FIFO drains completely, a FIFO underrun
990 * will occur, and a display engine hang could result.
991 */
992 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
993 const struct intel_watermark_params *wm,
994 int fifo_size,
995 int pixel_size,
996 unsigned long latency_ns)
997 {
998 long entries_required, wm_size;
999
1000 /*
1001 * Note: we need to make sure we don't overflow for various clock &
1002 * latency values.
1003 * clocks go from a few thousand to several hundred thousand.
1004 * latency is usually a few thousand
1005 */
1006 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
1007 1000;
1008 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
1009
1010 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
1011
1012 wm_size = fifo_size - (entries_required + wm->guard_size);
1013
1014 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
1015
1016 /* Don't promote wm_size to unsigned... */
1017 if (wm_size > (long)wm->max_wm)
1018 wm_size = wm->max_wm;
1019 if (wm_size <= 0)
1020 wm_size = wm->default_wm;
1021 return wm_size;
1022 }
1023
1024 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1025 {
1026 struct drm_crtc *crtc, *enabled = NULL;
1027
1028 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1029 if (intel_crtc_active(crtc)) {
1030 if (enabled)
1031 return NULL;
1032 enabled = crtc;
1033 }
1034 }
1035
1036 return enabled;
1037 }
1038
1039 static void pineview_update_wm(struct drm_device *dev)
1040 {
1041 struct drm_i915_private *dev_priv = dev->dev_private;
1042 struct drm_crtc *crtc;
1043 const struct cxsr_latency *latency;
1044 u32 reg;
1045 unsigned long wm;
1046
1047 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1048 dev_priv->fsb_freq, dev_priv->mem_freq);
1049 if (!latency) {
1050 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1051 pineview_disable_cxsr(dev);
1052 return;
1053 }
1054
1055 crtc = single_enabled_crtc(dev);
1056 if (crtc) {
1057 int clock = crtc->mode.clock;
1058 int pixel_size = crtc->fb->bits_per_pixel / 8;
1059
1060 /* Display SR */
1061 wm = intel_calculate_wm(clock, &pineview_display_wm,
1062 pineview_display_wm.fifo_size,
1063 pixel_size, latency->display_sr);
1064 reg = I915_READ(DSPFW1);
1065 reg &= ~DSPFW_SR_MASK;
1066 reg |= wm << DSPFW_SR_SHIFT;
1067 I915_WRITE(DSPFW1, reg);
1068 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1069
1070 /* cursor SR */
1071 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1072 pineview_display_wm.fifo_size,
1073 pixel_size, latency->cursor_sr);
1074 reg = I915_READ(DSPFW3);
1075 reg &= ~DSPFW_CURSOR_SR_MASK;
1076 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1077 I915_WRITE(DSPFW3, reg);
1078
1079 /* Display HPLL off SR */
1080 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1081 pineview_display_hplloff_wm.fifo_size,
1082 pixel_size, latency->display_hpll_disable);
1083 reg = I915_READ(DSPFW3);
1084 reg &= ~DSPFW_HPLL_SR_MASK;
1085 reg |= wm & DSPFW_HPLL_SR_MASK;
1086 I915_WRITE(DSPFW3, reg);
1087
1088 /* cursor HPLL off SR */
1089 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1090 pineview_display_hplloff_wm.fifo_size,
1091 pixel_size, latency->cursor_hpll_disable);
1092 reg = I915_READ(DSPFW3);
1093 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1094 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1095 I915_WRITE(DSPFW3, reg);
1096 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1097
1098 /* activate cxsr */
1099 I915_WRITE(DSPFW3,
1100 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1101 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1102 } else {
1103 pineview_disable_cxsr(dev);
1104 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1105 }
1106 }
1107
1108 static bool g4x_compute_wm0(struct drm_device *dev,
1109 int plane,
1110 const struct intel_watermark_params *display,
1111 int display_latency_ns,
1112 const struct intel_watermark_params *cursor,
1113 int cursor_latency_ns,
1114 int *plane_wm,
1115 int *cursor_wm)
1116 {
1117 struct drm_crtc *crtc;
1118 int htotal, hdisplay, clock, pixel_size;
1119 int line_time_us, line_count;
1120 int entries, tlb_miss;
1121
1122 crtc = intel_get_crtc_for_plane(dev, plane);
1123 if (!intel_crtc_active(crtc)) {
1124 *cursor_wm = cursor->guard_size;
1125 *plane_wm = display->guard_size;
1126 return false;
1127 }
1128
1129 htotal = crtc->mode.htotal;
1130 hdisplay = crtc->mode.hdisplay;
1131 clock = crtc->mode.clock;
1132 pixel_size = crtc->fb->bits_per_pixel / 8;
1133
1134 /* Use the small buffer method to calculate plane watermark */
1135 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1136 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1137 if (tlb_miss > 0)
1138 entries += tlb_miss;
1139 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1140 *plane_wm = entries + display->guard_size;
1141 if (*plane_wm > (int)display->max_wm)
1142 *plane_wm = display->max_wm;
1143
1144 /* Use the large buffer method to calculate cursor watermark */
1145 line_time_us = ((htotal * 1000) / clock);
1146 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1147 entries = line_count * 64 * pixel_size;
1148 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1149 if (tlb_miss > 0)
1150 entries += tlb_miss;
1151 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1152 *cursor_wm = entries + cursor->guard_size;
1153 if (*cursor_wm > (int)cursor->max_wm)
1154 *cursor_wm = (int)cursor->max_wm;
1155
1156 return true;
1157 }
1158
1159 /*
1160 * Check the wm result.
1161 *
1162 * If any calculated watermark values is larger than the maximum value that
1163 * can be programmed into the associated watermark register, that watermark
1164 * must be disabled.
1165 */
1166 static bool g4x_check_srwm(struct drm_device *dev,
1167 int display_wm, int cursor_wm,
1168 const struct intel_watermark_params *display,
1169 const struct intel_watermark_params *cursor)
1170 {
1171 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1172 display_wm, cursor_wm);
1173
1174 if (display_wm > display->max_wm) {
1175 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1176 display_wm, display->max_wm);
1177 return false;
1178 }
1179
1180 if (cursor_wm > cursor->max_wm) {
1181 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1182 cursor_wm, cursor->max_wm);
1183 return false;
1184 }
1185
1186 if (!(display_wm || cursor_wm)) {
1187 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1188 return false;
1189 }
1190
1191 return true;
1192 }
1193
1194 static bool g4x_compute_srwm(struct drm_device *dev,
1195 int plane,
1196 int latency_ns,
1197 const struct intel_watermark_params *display,
1198 const struct intel_watermark_params *cursor,
1199 int *display_wm, int *cursor_wm)
1200 {
1201 struct drm_crtc *crtc;
1202 int hdisplay, htotal, pixel_size, clock;
1203 unsigned long line_time_us;
1204 int line_count, line_size;
1205 int small, large;
1206 int entries;
1207
1208 if (!latency_ns) {
1209 *display_wm = *cursor_wm = 0;
1210 return false;
1211 }
1212
1213 crtc = intel_get_crtc_for_plane(dev, plane);
1214 hdisplay = crtc->mode.hdisplay;
1215 htotal = crtc->mode.htotal;
1216 clock = crtc->mode.clock;
1217 pixel_size = crtc->fb->bits_per_pixel / 8;
1218
1219 line_time_us = (htotal * 1000) / clock;
1220 line_count = (latency_ns / line_time_us + 1000) / 1000;
1221 line_size = hdisplay * pixel_size;
1222
1223 /* Use the minimum of the small and large buffer method for primary */
1224 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1225 large = line_count * line_size;
1226
1227 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1228 *display_wm = entries + display->guard_size;
1229
1230 /* calculate the self-refresh watermark for display cursor */
1231 entries = line_count * pixel_size * 64;
1232 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1233 *cursor_wm = entries + cursor->guard_size;
1234
1235 return g4x_check_srwm(dev,
1236 *display_wm, *cursor_wm,
1237 display, cursor);
1238 }
1239
1240 static bool vlv_compute_drain_latency(struct drm_device *dev,
1241 int plane,
1242 int *plane_prec_mult,
1243 int *plane_dl,
1244 int *cursor_prec_mult,
1245 int *cursor_dl)
1246 {
1247 struct drm_crtc *crtc;
1248 int clock, pixel_size;
1249 int entries;
1250
1251 crtc = intel_get_crtc_for_plane(dev, plane);
1252 if (!intel_crtc_active(crtc))
1253 return false;
1254
1255 clock = crtc->mode.clock; /* VESA DOT Clock */
1256 pixel_size = crtc->fb->bits_per_pixel / 8; /* BPP */
1257
1258 entries = (clock / 1000) * pixel_size;
1259 *plane_prec_mult = (entries > 256) ?
1260 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1261 *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1262 pixel_size);
1263
1264 entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */
1265 *cursor_prec_mult = (entries > 256) ?
1266 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1267 *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1268
1269 return true;
1270 }
1271
1272 /*
1273 * Update drain latency registers of memory arbiter
1274 *
1275 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1276 * to be programmed. Each plane has a drain latency multiplier and a drain
1277 * latency value.
1278 */
1279
1280 static void vlv_update_drain_latency(struct drm_device *dev)
1281 {
1282 struct drm_i915_private *dev_priv = dev->dev_private;
1283 int planea_prec, planea_dl, planeb_prec, planeb_dl;
1284 int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1285 int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1286 either 16 or 32 */
1287
1288 /* For plane A, Cursor A */
1289 if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1290 &cursor_prec_mult, &cursora_dl)) {
1291 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1292 DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1293 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1294 DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1295
1296 I915_WRITE(VLV_DDL1, cursora_prec |
1297 (cursora_dl << DDL_CURSORA_SHIFT) |
1298 planea_prec | planea_dl);
1299 }
1300
1301 /* For plane B, Cursor B */
1302 if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1303 &cursor_prec_mult, &cursorb_dl)) {
1304 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1305 DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1306 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1307 DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1308
1309 I915_WRITE(VLV_DDL2, cursorb_prec |
1310 (cursorb_dl << DDL_CURSORB_SHIFT) |
1311 planeb_prec | planeb_dl);
1312 }
1313 }
1314
1315 #define single_plane_enabled(mask) is_power_of_2(mask)
1316
1317 static void valleyview_update_wm(struct drm_device *dev)
1318 {
1319 static const int sr_latency_ns = 12000;
1320 struct drm_i915_private *dev_priv = dev->dev_private;
1321 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1322 int plane_sr, cursor_sr;
1323 int ignore_plane_sr, ignore_cursor_sr;
1324 unsigned int enabled = 0;
1325
1326 vlv_update_drain_latency(dev);
1327
1328 if (g4x_compute_wm0(dev, 0,
1329 &valleyview_wm_info, latency_ns,
1330 &valleyview_cursor_wm_info, latency_ns,
1331 &planea_wm, &cursora_wm))
1332 enabled |= 1;
1333
1334 if (g4x_compute_wm0(dev, 1,
1335 &valleyview_wm_info, latency_ns,
1336 &valleyview_cursor_wm_info, latency_ns,
1337 &planeb_wm, &cursorb_wm))
1338 enabled |= 2;
1339
1340 if (single_plane_enabled(enabled) &&
1341 g4x_compute_srwm(dev, ffs(enabled) - 1,
1342 sr_latency_ns,
1343 &valleyview_wm_info,
1344 &valleyview_cursor_wm_info,
1345 &plane_sr, &ignore_cursor_sr) &&
1346 g4x_compute_srwm(dev, ffs(enabled) - 1,
1347 2*sr_latency_ns,
1348 &valleyview_wm_info,
1349 &valleyview_cursor_wm_info,
1350 &ignore_plane_sr, &cursor_sr)) {
1351 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
1352 } else {
1353 I915_WRITE(FW_BLC_SELF_VLV,
1354 I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
1355 plane_sr = cursor_sr = 0;
1356 }
1357
1358 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1359 planea_wm, cursora_wm,
1360 planeb_wm, cursorb_wm,
1361 plane_sr, cursor_sr);
1362
1363 I915_WRITE(DSPFW1,
1364 (plane_sr << DSPFW_SR_SHIFT) |
1365 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1366 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1367 planea_wm);
1368 I915_WRITE(DSPFW2,
1369 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1370 (cursora_wm << DSPFW_CURSORA_SHIFT));
1371 I915_WRITE(DSPFW3,
1372 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1373 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1374 }
1375
1376 static void g4x_update_wm(struct drm_device *dev)
1377 {
1378 static const int sr_latency_ns = 12000;
1379 struct drm_i915_private *dev_priv = dev->dev_private;
1380 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1381 int plane_sr, cursor_sr;
1382 unsigned int enabled = 0;
1383
1384 if (g4x_compute_wm0(dev, 0,
1385 &g4x_wm_info, latency_ns,
1386 &g4x_cursor_wm_info, latency_ns,
1387 &planea_wm, &cursora_wm))
1388 enabled |= 1;
1389
1390 if (g4x_compute_wm0(dev, 1,
1391 &g4x_wm_info, latency_ns,
1392 &g4x_cursor_wm_info, latency_ns,
1393 &planeb_wm, &cursorb_wm))
1394 enabled |= 2;
1395
1396 if (single_plane_enabled(enabled) &&
1397 g4x_compute_srwm(dev, ffs(enabled) - 1,
1398 sr_latency_ns,
1399 &g4x_wm_info,
1400 &g4x_cursor_wm_info,
1401 &plane_sr, &cursor_sr)) {
1402 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1403 } else {
1404 I915_WRITE(FW_BLC_SELF,
1405 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
1406 plane_sr = cursor_sr = 0;
1407 }
1408
1409 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1410 planea_wm, cursora_wm,
1411 planeb_wm, cursorb_wm,
1412 plane_sr, cursor_sr);
1413
1414 I915_WRITE(DSPFW1,
1415 (plane_sr << DSPFW_SR_SHIFT) |
1416 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1417 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1418 planea_wm);
1419 I915_WRITE(DSPFW2,
1420 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1421 (cursora_wm << DSPFW_CURSORA_SHIFT));
1422 /* HPLL off in SR has some issues on G4x... disable it */
1423 I915_WRITE(DSPFW3,
1424 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1425 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1426 }
1427
1428 static void i965_update_wm(struct drm_device *dev)
1429 {
1430 struct drm_i915_private *dev_priv = dev->dev_private;
1431 struct drm_crtc *crtc;
1432 int srwm = 1;
1433 int cursor_sr = 16;
1434
1435 /* Calc sr entries for one plane configs */
1436 crtc = single_enabled_crtc(dev);
1437 if (crtc) {
1438 /* self-refresh has much higher latency */
1439 static const int sr_latency_ns = 12000;
1440 int clock = crtc->mode.clock;
1441 int htotal = crtc->mode.htotal;
1442 int hdisplay = crtc->mode.hdisplay;
1443 int pixel_size = crtc->fb->bits_per_pixel / 8;
1444 unsigned long line_time_us;
1445 int entries;
1446
1447 line_time_us = ((htotal * 1000) / clock);
1448
1449 /* Use ns/us then divide to preserve precision */
1450 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1451 pixel_size * hdisplay;
1452 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1453 srwm = I965_FIFO_SIZE - entries;
1454 if (srwm < 0)
1455 srwm = 1;
1456 srwm &= 0x1ff;
1457 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1458 entries, srwm);
1459
1460 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1461 pixel_size * 64;
1462 entries = DIV_ROUND_UP(entries,
1463 i965_cursor_wm_info.cacheline_size);
1464 cursor_sr = i965_cursor_wm_info.fifo_size -
1465 (entries + i965_cursor_wm_info.guard_size);
1466
1467 if (cursor_sr > i965_cursor_wm_info.max_wm)
1468 cursor_sr = i965_cursor_wm_info.max_wm;
1469
1470 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1471 "cursor %d\n", srwm, cursor_sr);
1472
1473 if (IS_CRESTLINE(dev))
1474 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1475 } else {
1476 /* Turn off self refresh if both pipes are enabled */
1477 if (IS_CRESTLINE(dev))
1478 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1479 & ~FW_BLC_SELF_EN);
1480 }
1481
1482 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1483 srwm);
1484
1485 /* 965 has limitations... */
1486 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1487 (8 << 16) | (8 << 8) | (8 << 0));
1488 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1489 /* update cursor SR watermark */
1490 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1491 }
1492
1493 static void i9xx_update_wm(struct drm_device *dev)
1494 {
1495 struct drm_i915_private *dev_priv = dev->dev_private;
1496 const struct intel_watermark_params *wm_info;
1497 uint32_t fwater_lo;
1498 uint32_t fwater_hi;
1499 int cwm, srwm = 1;
1500 int fifo_size;
1501 int planea_wm, planeb_wm;
1502 struct drm_crtc *crtc, *enabled = NULL;
1503
1504 if (IS_I945GM(dev))
1505 wm_info = &i945_wm_info;
1506 else if (!IS_GEN2(dev))
1507 wm_info = &i915_wm_info;
1508 else
1509 wm_info = &i855_wm_info;
1510
1511 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1512 crtc = intel_get_crtc_for_plane(dev, 0);
1513 if (intel_crtc_active(crtc)) {
1514 int cpp = crtc->fb->bits_per_pixel / 8;
1515 if (IS_GEN2(dev))
1516 cpp = 4;
1517
1518 planea_wm = intel_calculate_wm(crtc->mode.clock,
1519 wm_info, fifo_size, cpp,
1520 latency_ns);
1521 enabled = crtc;
1522 } else
1523 planea_wm = fifo_size - wm_info->guard_size;
1524
1525 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1526 crtc = intel_get_crtc_for_plane(dev, 1);
1527 if (intel_crtc_active(crtc)) {
1528 int cpp = crtc->fb->bits_per_pixel / 8;
1529 if (IS_GEN2(dev))
1530 cpp = 4;
1531
1532 planeb_wm = intel_calculate_wm(crtc->mode.clock,
1533 wm_info, fifo_size, cpp,
1534 latency_ns);
1535 if (enabled == NULL)
1536 enabled = crtc;
1537 else
1538 enabled = NULL;
1539 } else
1540 planeb_wm = fifo_size - wm_info->guard_size;
1541
1542 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1543
1544 /*
1545 * Overlay gets an aggressive default since video jitter is bad.
1546 */
1547 cwm = 2;
1548
1549 /* Play safe and disable self-refresh before adjusting watermarks. */
1550 if (IS_I945G(dev) || IS_I945GM(dev))
1551 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1552 else if (IS_I915GM(dev))
1553 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
1554
1555 /* Calc sr entries for one plane configs */
1556 if (HAS_FW_BLC(dev) && enabled) {
1557 /* self-refresh has much higher latency */
1558 static const int sr_latency_ns = 6000;
1559 int clock = enabled->mode.clock;
1560 int htotal = enabled->mode.htotal;
1561 int hdisplay = enabled->mode.hdisplay;
1562 int pixel_size = enabled->fb->bits_per_pixel / 8;
1563 unsigned long line_time_us;
1564 int entries;
1565
1566 line_time_us = (htotal * 1000) / clock;
1567
1568 /* Use ns/us then divide to preserve precision */
1569 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1570 pixel_size * hdisplay;
1571 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1572 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1573 srwm = wm_info->fifo_size - entries;
1574 if (srwm < 0)
1575 srwm = 1;
1576
1577 if (IS_I945G(dev) || IS_I945GM(dev))
1578 I915_WRITE(FW_BLC_SELF,
1579 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1580 else if (IS_I915GM(dev))
1581 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1582 }
1583
1584 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1585 planea_wm, planeb_wm, cwm, srwm);
1586
1587 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1588 fwater_hi = (cwm & 0x1f);
1589
1590 /* Set request length to 8 cachelines per fetch */
1591 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1592 fwater_hi = fwater_hi | (1 << 8);
1593
1594 I915_WRITE(FW_BLC, fwater_lo);
1595 I915_WRITE(FW_BLC2, fwater_hi);
1596
1597 if (HAS_FW_BLC(dev)) {
1598 if (enabled) {
1599 if (IS_I945G(dev) || IS_I945GM(dev))
1600 I915_WRITE(FW_BLC_SELF,
1601 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1602 else if (IS_I915GM(dev))
1603 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
1604 DRM_DEBUG_KMS("memory self refresh enabled\n");
1605 } else
1606 DRM_DEBUG_KMS("memory self refresh disabled\n");
1607 }
1608 }
1609
1610 static void i830_update_wm(struct drm_device *dev)
1611 {
1612 struct drm_i915_private *dev_priv = dev->dev_private;
1613 struct drm_crtc *crtc;
1614 uint32_t fwater_lo;
1615 int planea_wm;
1616
1617 crtc = single_enabled_crtc(dev);
1618 if (crtc == NULL)
1619 return;
1620
1621 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
1622 dev_priv->display.get_fifo_size(dev, 0),
1623 4, latency_ns);
1624 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1625 fwater_lo |= (3<<8) | planea_wm;
1626
1627 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1628
1629 I915_WRITE(FW_BLC, fwater_lo);
1630 }
1631
1632 #define ILK_LP0_PLANE_LATENCY 700
1633 #define ILK_LP0_CURSOR_LATENCY 1300
1634
1635 /*
1636 * Check the wm result.
1637 *
1638 * If any calculated watermark values is larger than the maximum value that
1639 * can be programmed into the associated watermark register, that watermark
1640 * must be disabled.
1641 */
1642 static bool ironlake_check_srwm(struct drm_device *dev, int level,
1643 int fbc_wm, int display_wm, int cursor_wm,
1644 const struct intel_watermark_params *display,
1645 const struct intel_watermark_params *cursor)
1646 {
1647 struct drm_i915_private *dev_priv = dev->dev_private;
1648
1649 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
1650 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
1651
1652 if (fbc_wm > SNB_FBC_MAX_SRWM) {
1653 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
1654 fbc_wm, SNB_FBC_MAX_SRWM, level);
1655
1656 /* fbc has it's own way to disable FBC WM */
1657 I915_WRITE(DISP_ARB_CTL,
1658 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
1659 return false;
1660 } else if (INTEL_INFO(dev)->gen >= 6) {
1661 /* enable FBC WM (except on ILK, where it must remain off) */
1662 I915_WRITE(DISP_ARB_CTL,
1663 I915_READ(DISP_ARB_CTL) & ~DISP_FBC_WM_DIS);
1664 }
1665
1666 if (display_wm > display->max_wm) {
1667 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
1668 display_wm, SNB_DISPLAY_MAX_SRWM, level);
1669 return false;
1670 }
1671
1672 if (cursor_wm > cursor->max_wm) {
1673 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
1674 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1675 return false;
1676 }
1677
1678 if (!(fbc_wm || display_wm || cursor_wm)) {
1679 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
1680 return false;
1681 }
1682
1683 return true;
1684 }
1685
1686 /*
1687 * Compute watermark values of WM[1-3],
1688 */
1689 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
1690 int latency_ns,
1691 const struct intel_watermark_params *display,
1692 const struct intel_watermark_params *cursor,
1693 int *fbc_wm, int *display_wm, int *cursor_wm)
1694 {
1695 struct drm_crtc *crtc;
1696 unsigned long line_time_us;
1697 int hdisplay, htotal, pixel_size, clock;
1698 int line_count, line_size;
1699 int small, large;
1700 int entries;
1701
1702 if (!latency_ns) {
1703 *fbc_wm = *display_wm = *cursor_wm = 0;
1704 return false;
1705 }
1706
1707 crtc = intel_get_crtc_for_plane(dev, plane);
1708 hdisplay = crtc->mode.hdisplay;
1709 htotal = crtc->mode.htotal;
1710 clock = crtc->mode.clock;
1711 pixel_size = crtc->fb->bits_per_pixel / 8;
1712
1713 line_time_us = (htotal * 1000) / clock;
1714 line_count = (latency_ns / line_time_us + 1000) / 1000;
1715 line_size = hdisplay * pixel_size;
1716
1717 /* Use the minimum of the small and large buffer method for primary */
1718 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1719 large = line_count * line_size;
1720
1721 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1722 *display_wm = entries + display->guard_size;
1723
1724 /*
1725 * Spec says:
1726 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
1727 */
1728 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
1729
1730 /* calculate the self-refresh watermark for display cursor */
1731 entries = line_count * pixel_size * 64;
1732 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1733 *cursor_wm = entries + cursor->guard_size;
1734
1735 return ironlake_check_srwm(dev, level,
1736 *fbc_wm, *display_wm, *cursor_wm,
1737 display, cursor);
1738 }
1739
1740 static void ironlake_update_wm(struct drm_device *dev)
1741 {
1742 struct drm_i915_private *dev_priv = dev->dev_private;
1743 int fbc_wm, plane_wm, cursor_wm;
1744 unsigned int enabled;
1745
1746 enabled = 0;
1747 if (g4x_compute_wm0(dev, 0,
1748 &ironlake_display_wm_info,
1749 ILK_LP0_PLANE_LATENCY,
1750 &ironlake_cursor_wm_info,
1751 ILK_LP0_CURSOR_LATENCY,
1752 &plane_wm, &cursor_wm)) {
1753 I915_WRITE(WM0_PIPEA_ILK,
1754 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1755 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1756 " plane %d, " "cursor: %d\n",
1757 plane_wm, cursor_wm);
1758 enabled |= 1;
1759 }
1760
1761 if (g4x_compute_wm0(dev, 1,
1762 &ironlake_display_wm_info,
1763 ILK_LP0_PLANE_LATENCY,
1764 &ironlake_cursor_wm_info,
1765 ILK_LP0_CURSOR_LATENCY,
1766 &plane_wm, &cursor_wm)) {
1767 I915_WRITE(WM0_PIPEB_ILK,
1768 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1769 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1770 " plane %d, cursor: %d\n",
1771 plane_wm, cursor_wm);
1772 enabled |= 2;
1773 }
1774
1775 /*
1776 * Calculate and update the self-refresh watermark only when one
1777 * display plane is used.
1778 */
1779 I915_WRITE(WM3_LP_ILK, 0);
1780 I915_WRITE(WM2_LP_ILK, 0);
1781 I915_WRITE(WM1_LP_ILK, 0);
1782
1783 if (!single_plane_enabled(enabled))
1784 return;
1785 enabled = ffs(enabled) - 1;
1786
1787 /* WM1 */
1788 if (!ironlake_compute_srwm(dev, 1, enabled,
1789 ILK_READ_WM1_LATENCY() * 500,
1790 &ironlake_display_srwm_info,
1791 &ironlake_cursor_srwm_info,
1792 &fbc_wm, &plane_wm, &cursor_wm))
1793 return;
1794
1795 I915_WRITE(WM1_LP_ILK,
1796 WM1_LP_SR_EN |
1797 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1798 (fbc_wm << WM1_LP_FBC_SHIFT) |
1799 (plane_wm << WM1_LP_SR_SHIFT) |
1800 cursor_wm);
1801
1802 /* WM2 */
1803 if (!ironlake_compute_srwm(dev, 2, enabled,
1804 ILK_READ_WM2_LATENCY() * 500,
1805 &ironlake_display_srwm_info,
1806 &ironlake_cursor_srwm_info,
1807 &fbc_wm, &plane_wm, &cursor_wm))
1808 return;
1809
1810 I915_WRITE(WM2_LP_ILK,
1811 WM2_LP_EN |
1812 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1813 (fbc_wm << WM1_LP_FBC_SHIFT) |
1814 (plane_wm << WM1_LP_SR_SHIFT) |
1815 cursor_wm);
1816
1817 /*
1818 * WM3 is unsupported on ILK, probably because we don't have latency
1819 * data for that power state
1820 */
1821 }
1822
1823 static void sandybridge_update_wm(struct drm_device *dev)
1824 {
1825 struct drm_i915_private *dev_priv = dev->dev_private;
1826 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
1827 u32 val;
1828 int fbc_wm, plane_wm, cursor_wm;
1829 unsigned int enabled;
1830
1831 enabled = 0;
1832 if (g4x_compute_wm0(dev, 0,
1833 &sandybridge_display_wm_info, latency,
1834 &sandybridge_cursor_wm_info, latency,
1835 &plane_wm, &cursor_wm)) {
1836 val = I915_READ(WM0_PIPEA_ILK);
1837 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1838 I915_WRITE(WM0_PIPEA_ILK, val |
1839 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1840 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1841 " plane %d, " "cursor: %d\n",
1842 plane_wm, cursor_wm);
1843 enabled |= 1;
1844 }
1845
1846 if (g4x_compute_wm0(dev, 1,
1847 &sandybridge_display_wm_info, latency,
1848 &sandybridge_cursor_wm_info, latency,
1849 &plane_wm, &cursor_wm)) {
1850 val = I915_READ(WM0_PIPEB_ILK);
1851 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1852 I915_WRITE(WM0_PIPEB_ILK, val |
1853 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1854 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1855 " plane %d, cursor: %d\n",
1856 plane_wm, cursor_wm);
1857 enabled |= 2;
1858 }
1859
1860 /*
1861 * Calculate and update the self-refresh watermark only when one
1862 * display plane is used.
1863 *
1864 * SNB support 3 levels of watermark.
1865 *
1866 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1867 * and disabled in the descending order
1868 *
1869 */
1870 I915_WRITE(WM3_LP_ILK, 0);
1871 I915_WRITE(WM2_LP_ILK, 0);
1872 I915_WRITE(WM1_LP_ILK, 0);
1873
1874 if (!single_plane_enabled(enabled) ||
1875 dev_priv->sprite_scaling_enabled)
1876 return;
1877 enabled = ffs(enabled) - 1;
1878
1879 /* WM1 */
1880 if (!ironlake_compute_srwm(dev, 1, enabled,
1881 SNB_READ_WM1_LATENCY() * 500,
1882 &sandybridge_display_srwm_info,
1883 &sandybridge_cursor_srwm_info,
1884 &fbc_wm, &plane_wm, &cursor_wm))
1885 return;
1886
1887 I915_WRITE(WM1_LP_ILK,
1888 WM1_LP_SR_EN |
1889 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1890 (fbc_wm << WM1_LP_FBC_SHIFT) |
1891 (plane_wm << WM1_LP_SR_SHIFT) |
1892 cursor_wm);
1893
1894 /* WM2 */
1895 if (!ironlake_compute_srwm(dev, 2, enabled,
1896 SNB_READ_WM2_LATENCY() * 500,
1897 &sandybridge_display_srwm_info,
1898 &sandybridge_cursor_srwm_info,
1899 &fbc_wm, &plane_wm, &cursor_wm))
1900 return;
1901
1902 I915_WRITE(WM2_LP_ILK,
1903 WM2_LP_EN |
1904 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1905 (fbc_wm << WM1_LP_FBC_SHIFT) |
1906 (plane_wm << WM1_LP_SR_SHIFT) |
1907 cursor_wm);
1908
1909 /* WM3 */
1910 if (!ironlake_compute_srwm(dev, 3, enabled,
1911 SNB_READ_WM3_LATENCY() * 500,
1912 &sandybridge_display_srwm_info,
1913 &sandybridge_cursor_srwm_info,
1914 &fbc_wm, &plane_wm, &cursor_wm))
1915 return;
1916
1917 I915_WRITE(WM3_LP_ILK,
1918 WM3_LP_EN |
1919 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1920 (fbc_wm << WM1_LP_FBC_SHIFT) |
1921 (plane_wm << WM1_LP_SR_SHIFT) |
1922 cursor_wm);
1923 }
1924
1925 static void ivybridge_update_wm(struct drm_device *dev)
1926 {
1927 struct drm_i915_private *dev_priv = dev->dev_private;
1928 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
1929 u32 val;
1930 int fbc_wm, plane_wm, cursor_wm;
1931 int ignore_fbc_wm, ignore_plane_wm, ignore_cursor_wm;
1932 unsigned int enabled;
1933
1934 enabled = 0;
1935 if (g4x_compute_wm0(dev, 0,
1936 &sandybridge_display_wm_info, latency,
1937 &sandybridge_cursor_wm_info, latency,
1938 &plane_wm, &cursor_wm)) {
1939 val = I915_READ(WM0_PIPEA_ILK);
1940 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1941 I915_WRITE(WM0_PIPEA_ILK, val |
1942 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1943 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1944 " plane %d, " "cursor: %d\n",
1945 plane_wm, cursor_wm);
1946 enabled |= 1;
1947 }
1948
1949 if (g4x_compute_wm0(dev, 1,
1950 &sandybridge_display_wm_info, latency,
1951 &sandybridge_cursor_wm_info, latency,
1952 &plane_wm, &cursor_wm)) {
1953 val = I915_READ(WM0_PIPEB_ILK);
1954 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1955 I915_WRITE(WM0_PIPEB_ILK, val |
1956 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1957 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1958 " plane %d, cursor: %d\n",
1959 plane_wm, cursor_wm);
1960 enabled |= 2;
1961 }
1962
1963 if (g4x_compute_wm0(dev, 2,
1964 &sandybridge_display_wm_info, latency,
1965 &sandybridge_cursor_wm_info, latency,
1966 &plane_wm, &cursor_wm)) {
1967 val = I915_READ(WM0_PIPEC_IVB);
1968 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1969 I915_WRITE(WM0_PIPEC_IVB, val |
1970 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1971 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
1972 " plane %d, cursor: %d\n",
1973 plane_wm, cursor_wm);
1974 enabled |= 3;
1975 }
1976
1977 /*
1978 * Calculate and update the self-refresh watermark only when one
1979 * display plane is used.
1980 *
1981 * SNB support 3 levels of watermark.
1982 *
1983 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1984 * and disabled in the descending order
1985 *
1986 */
1987 I915_WRITE(WM3_LP_ILK, 0);
1988 I915_WRITE(WM2_LP_ILK, 0);
1989 I915_WRITE(WM1_LP_ILK, 0);
1990
1991 if (!single_plane_enabled(enabled) ||
1992 dev_priv->sprite_scaling_enabled)
1993 return;
1994 enabled = ffs(enabled) - 1;
1995
1996 /* WM1 */
1997 if (!ironlake_compute_srwm(dev, 1, enabled,
1998 SNB_READ_WM1_LATENCY() * 500,
1999 &sandybridge_display_srwm_info,
2000 &sandybridge_cursor_srwm_info,
2001 &fbc_wm, &plane_wm, &cursor_wm))
2002 return;
2003
2004 I915_WRITE(WM1_LP_ILK,
2005 WM1_LP_SR_EN |
2006 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
2007 (fbc_wm << WM1_LP_FBC_SHIFT) |
2008 (plane_wm << WM1_LP_SR_SHIFT) |
2009 cursor_wm);
2010
2011 /* WM2 */
2012 if (!ironlake_compute_srwm(dev, 2, enabled,
2013 SNB_READ_WM2_LATENCY() * 500,
2014 &sandybridge_display_srwm_info,
2015 &sandybridge_cursor_srwm_info,
2016 &fbc_wm, &plane_wm, &cursor_wm))
2017 return;
2018
2019 I915_WRITE(WM2_LP_ILK,
2020 WM2_LP_EN |
2021 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
2022 (fbc_wm << WM1_LP_FBC_SHIFT) |
2023 (plane_wm << WM1_LP_SR_SHIFT) |
2024 cursor_wm);
2025
2026 /* WM3, note we have to correct the cursor latency */
2027 if (!ironlake_compute_srwm(dev, 3, enabled,
2028 SNB_READ_WM3_LATENCY() * 500,
2029 &sandybridge_display_srwm_info,
2030 &sandybridge_cursor_srwm_info,
2031 &fbc_wm, &plane_wm, &ignore_cursor_wm) ||
2032 !ironlake_compute_srwm(dev, 3, enabled,
2033 2 * SNB_READ_WM3_LATENCY() * 500,
2034 &sandybridge_display_srwm_info,
2035 &sandybridge_cursor_srwm_info,
2036 &ignore_fbc_wm, &ignore_plane_wm, &cursor_wm))
2037 return;
2038
2039 I915_WRITE(WM3_LP_ILK,
2040 WM3_LP_EN |
2041 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
2042 (fbc_wm << WM1_LP_FBC_SHIFT) |
2043 (plane_wm << WM1_LP_SR_SHIFT) |
2044 cursor_wm);
2045 }
2046
2047 static void
2048 haswell_update_linetime_wm(struct drm_device *dev, int pipe,
2049 struct drm_display_mode *mode)
2050 {
2051 struct drm_i915_private *dev_priv = dev->dev_private;
2052 u32 temp;
2053
2054 temp = I915_READ(PIPE_WM_LINETIME(pipe));
2055 temp &= ~PIPE_WM_LINETIME_MASK;
2056
2057 /* The WM are computed with base on how long it takes to fill a single
2058 * row at the given clock rate, multiplied by 8.
2059 * */
2060 temp |= PIPE_WM_LINETIME_TIME(
2061 ((mode->crtc_hdisplay * 1000) / mode->clock) * 8);
2062
2063 /* IPS watermarks are only used by pipe A, and are ignored by
2064 * pipes B and C. They are calculated similarly to the common
2065 * linetime values, except that we are using CD clock frequency
2066 * in MHz instead of pixel rate for the division.
2067 *
2068 * This is a placeholder for the IPS watermark calculation code.
2069 */
2070
2071 I915_WRITE(PIPE_WM_LINETIME(pipe), temp);
2072 }
2073
2074 static bool
2075 sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
2076 uint32_t sprite_width, int pixel_size,
2077 const struct intel_watermark_params *display,
2078 int display_latency_ns, int *sprite_wm)
2079 {
2080 struct drm_crtc *crtc;
2081 int clock;
2082 int entries, tlb_miss;
2083
2084 crtc = intel_get_crtc_for_plane(dev, plane);
2085 if (!intel_crtc_active(crtc)) {
2086 *sprite_wm = display->guard_size;
2087 return false;
2088 }
2089
2090 clock = crtc->mode.clock;
2091
2092 /* Use the small buffer method to calculate the sprite watermark */
2093 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
2094 tlb_miss = display->fifo_size*display->cacheline_size -
2095 sprite_width * 8;
2096 if (tlb_miss > 0)
2097 entries += tlb_miss;
2098 entries = DIV_ROUND_UP(entries, display->cacheline_size);
2099 *sprite_wm = entries + display->guard_size;
2100 if (*sprite_wm > (int)display->max_wm)
2101 *sprite_wm = display->max_wm;
2102
2103 return true;
2104 }
2105
2106 static bool
2107 sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
2108 uint32_t sprite_width, int pixel_size,
2109 const struct intel_watermark_params *display,
2110 int latency_ns, int *sprite_wm)
2111 {
2112 struct drm_crtc *crtc;
2113 unsigned long line_time_us;
2114 int clock;
2115 int line_count, line_size;
2116 int small, large;
2117 int entries;
2118
2119 if (!latency_ns) {
2120 *sprite_wm = 0;
2121 return false;
2122 }
2123
2124 crtc = intel_get_crtc_for_plane(dev, plane);
2125 clock = crtc->mode.clock;
2126 if (!clock) {
2127 *sprite_wm = 0;
2128 return false;
2129 }
2130
2131 line_time_us = (sprite_width * 1000) / clock;
2132 if (!line_time_us) {
2133 *sprite_wm = 0;
2134 return false;
2135 }
2136
2137 line_count = (latency_ns / line_time_us + 1000) / 1000;
2138 line_size = sprite_width * pixel_size;
2139
2140 /* Use the minimum of the small and large buffer method for primary */
2141 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
2142 large = line_count * line_size;
2143
2144 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
2145 *sprite_wm = entries + display->guard_size;
2146
2147 return *sprite_wm > 0x3ff ? false : true;
2148 }
2149
2150 static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
2151 uint32_t sprite_width, int pixel_size)
2152 {
2153 struct drm_i915_private *dev_priv = dev->dev_private;
2154 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
2155 u32 val;
2156 int sprite_wm, reg;
2157 int ret;
2158
2159 switch (pipe) {
2160 case 0:
2161 reg = WM0_PIPEA_ILK;
2162 break;
2163 case 1:
2164 reg = WM0_PIPEB_ILK;
2165 break;
2166 case 2:
2167 reg = WM0_PIPEC_IVB;
2168 break;
2169 default:
2170 return; /* bad pipe */
2171 }
2172
2173 ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
2174 &sandybridge_display_wm_info,
2175 latency, &sprite_wm);
2176 if (!ret) {
2177 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %c\n",
2178 pipe_name(pipe));
2179 return;
2180 }
2181
2182 val = I915_READ(reg);
2183 val &= ~WM0_PIPE_SPRITE_MASK;
2184 I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
2185 DRM_DEBUG_KMS("sprite watermarks For pipe %c - %d\n", pipe_name(pipe), sprite_wm);
2186
2187
2188 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2189 pixel_size,
2190 &sandybridge_display_srwm_info,
2191 SNB_READ_WM1_LATENCY() * 500,
2192 &sprite_wm);
2193 if (!ret) {
2194 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %c\n",
2195 pipe_name(pipe));
2196 return;
2197 }
2198 I915_WRITE(WM1S_LP_ILK, sprite_wm);
2199
2200 /* Only IVB has two more LP watermarks for sprite */
2201 if (!IS_IVYBRIDGE(dev))
2202 return;
2203
2204 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2205 pixel_size,
2206 &sandybridge_display_srwm_info,
2207 SNB_READ_WM2_LATENCY() * 500,
2208 &sprite_wm);
2209 if (!ret) {
2210 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %c\n",
2211 pipe_name(pipe));
2212 return;
2213 }
2214 I915_WRITE(WM2S_LP_IVB, sprite_wm);
2215
2216 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2217 pixel_size,
2218 &sandybridge_display_srwm_info,
2219 SNB_READ_WM3_LATENCY() * 500,
2220 &sprite_wm);
2221 if (!ret) {
2222 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %c\n",
2223 pipe_name(pipe));
2224 return;
2225 }
2226 I915_WRITE(WM3S_LP_IVB, sprite_wm);
2227 }
2228
2229 /**
2230 * intel_update_watermarks - update FIFO watermark values based on current modes
2231 *
2232 * Calculate watermark values for the various WM regs based on current mode
2233 * and plane configuration.
2234 *
2235 * There are several cases to deal with here:
2236 * - normal (i.e. non-self-refresh)
2237 * - self-refresh (SR) mode
2238 * - lines are large relative to FIFO size (buffer can hold up to 2)
2239 * - lines are small relative to FIFO size (buffer can hold more than 2
2240 * lines), so need to account for TLB latency
2241 *
2242 * The normal calculation is:
2243 * watermark = dotclock * bytes per pixel * latency
2244 * where latency is platform & configuration dependent (we assume pessimal
2245 * values here).
2246 *
2247 * The SR calculation is:
2248 * watermark = (trunc(latency/line time)+1) * surface width *
2249 * bytes per pixel
2250 * where
2251 * line time = htotal / dotclock
2252 * surface width = hdisplay for normal plane and 64 for cursor
2253 * and latency is assumed to be high, as above.
2254 *
2255 * The final value programmed to the register should always be rounded up,
2256 * and include an extra 2 entries to account for clock crossings.
2257 *
2258 * We don't use the sprite, so we can ignore that. And on Crestline we have
2259 * to set the non-SR watermarks to 8.
2260 */
2261 void intel_update_watermarks(struct drm_device *dev)
2262 {
2263 struct drm_i915_private *dev_priv = dev->dev_private;
2264
2265 if (dev_priv->display.update_wm)
2266 dev_priv->display.update_wm(dev);
2267 }
2268
2269 void intel_update_linetime_watermarks(struct drm_device *dev,
2270 int pipe, struct drm_display_mode *mode)
2271 {
2272 struct drm_i915_private *dev_priv = dev->dev_private;
2273
2274 if (dev_priv->display.update_linetime_wm)
2275 dev_priv->display.update_linetime_wm(dev, pipe, mode);
2276 }
2277
2278 void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
2279 uint32_t sprite_width, int pixel_size)
2280 {
2281 struct drm_i915_private *dev_priv = dev->dev_private;
2282
2283 if (dev_priv->display.update_sprite_wm)
2284 dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
2285 pixel_size);
2286 }
2287
2288 static struct drm_i915_gem_object *
2289 intel_alloc_context_page(struct drm_device *dev)
2290 {
2291 struct drm_i915_gem_object *ctx;
2292 int ret;
2293
2294 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2295
2296 ctx = i915_gem_alloc_object(dev, 4096);
2297 if (!ctx) {
2298 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
2299 return NULL;
2300 }
2301
2302 ret = i915_gem_object_pin(ctx, 4096, true, false);
2303 if (ret) {
2304 DRM_ERROR("failed to pin power context: %d\n", ret);
2305 goto err_unref;
2306 }
2307
2308 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
2309 if (ret) {
2310 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
2311 goto err_unpin;
2312 }
2313
2314 return ctx;
2315
2316 err_unpin:
2317 i915_gem_object_unpin(ctx);
2318 err_unref:
2319 drm_gem_object_unreference(&ctx->base);
2320 return NULL;
2321 }
2322
2323 /**
2324 * Lock protecting IPS related data structures
2325 */
2326 DEFINE_SPINLOCK(mchdev_lock);
2327
2328 /* Global for IPS driver to get at the current i915 device. Protected by
2329 * mchdev_lock. */
2330 static struct drm_i915_private *i915_mch_dev;
2331
2332 bool ironlake_set_drps(struct drm_device *dev, u8 val)
2333 {
2334 struct drm_i915_private *dev_priv = dev->dev_private;
2335 u16 rgvswctl;
2336
2337 assert_spin_locked(&mchdev_lock);
2338
2339 rgvswctl = I915_READ16(MEMSWCTL);
2340 if (rgvswctl & MEMCTL_CMD_STS) {
2341 DRM_DEBUG("gpu busy, RCS change rejected\n");
2342 return false; /* still busy with another command */
2343 }
2344
2345 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
2346 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
2347 I915_WRITE16(MEMSWCTL, rgvswctl);
2348 POSTING_READ16(MEMSWCTL);
2349
2350 rgvswctl |= MEMCTL_CMD_STS;
2351 I915_WRITE16(MEMSWCTL, rgvswctl);
2352
2353 return true;
2354 }
2355
2356 static void ironlake_enable_drps(struct drm_device *dev)
2357 {
2358 struct drm_i915_private *dev_priv = dev->dev_private;
2359 u32 rgvmodectl = I915_READ(MEMMODECTL);
2360 u8 fmax, fmin, fstart, vstart;
2361
2362 spin_lock_irq(&mchdev_lock);
2363
2364 /* Enable temp reporting */
2365 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
2366 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
2367
2368 /* 100ms RC evaluation intervals */
2369 I915_WRITE(RCUPEI, 100000);
2370 I915_WRITE(RCDNEI, 100000);
2371
2372 /* Set max/min thresholds to 90ms and 80ms respectively */
2373 I915_WRITE(RCBMAXAVG, 90000);
2374 I915_WRITE(RCBMINAVG, 80000);
2375
2376 I915_WRITE(MEMIHYST, 1);
2377
2378 /* Set up min, max, and cur for interrupt handling */
2379 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
2380 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
2381 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
2382 MEMMODE_FSTART_SHIFT;
2383
2384 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
2385 PXVFREQ_PX_SHIFT;
2386
2387 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
2388 dev_priv->ips.fstart = fstart;
2389
2390 dev_priv->ips.max_delay = fstart;
2391 dev_priv->ips.min_delay = fmin;
2392 dev_priv->ips.cur_delay = fstart;
2393
2394 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
2395 fmax, fmin, fstart);
2396
2397 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
2398
2399 /*
2400 * Interrupts will be enabled in ironlake_irq_postinstall
2401 */
2402
2403 I915_WRITE(VIDSTART, vstart);
2404 POSTING_READ(VIDSTART);
2405
2406 rgvmodectl |= MEMMODE_SWMODE_EN;
2407 I915_WRITE(MEMMODECTL, rgvmodectl);
2408
2409 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2410 DRM_ERROR("stuck trying to change perf mode\n");
2411 mdelay(1);
2412
2413 ironlake_set_drps(dev, fstart);
2414
2415 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2416 I915_READ(0x112e0);
2417 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
2418 dev_priv->ips.last_count2 = I915_READ(0x112f4);
2419 getrawmonotonic(&dev_priv->ips.last_time2);
2420
2421 spin_unlock_irq(&mchdev_lock);
2422 }
2423
2424 static void ironlake_disable_drps(struct drm_device *dev)
2425 {
2426 struct drm_i915_private *dev_priv = dev->dev_private;
2427 u16 rgvswctl;
2428
2429 spin_lock_irq(&mchdev_lock);
2430
2431 rgvswctl = I915_READ16(MEMSWCTL);
2432
2433 /* Ack interrupts, disable EFC interrupt */
2434 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
2435 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
2436 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
2437 I915_WRITE(DEIIR, DE_PCU_EVENT);
2438 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
2439
2440 /* Go back to the starting frequency */
2441 ironlake_set_drps(dev, dev_priv->ips.fstart);
2442 mdelay(1);
2443 rgvswctl |= MEMCTL_CMD_STS;
2444 I915_WRITE(MEMSWCTL, rgvswctl);
2445 mdelay(1);
2446
2447 spin_unlock_irq(&mchdev_lock);
2448 }
2449
2450 /* There's a funny hw issue where the hw returns all 0 when reading from
2451 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
2452 * ourselves, instead of doing a rmw cycle (which might result in us clearing
2453 * all limits and the gpu stuck at whatever frequency it is at atm).
2454 */
2455 static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 *val)
2456 {
2457 u32 limits;
2458
2459 limits = 0;
2460
2461 if (*val >= dev_priv->rps.max_delay)
2462 *val = dev_priv->rps.max_delay;
2463 limits |= dev_priv->rps.max_delay << 24;
2464
2465 /* Only set the down limit when we've reached the lowest level to avoid
2466 * getting more interrupts, otherwise leave this clear. This prevents a
2467 * race in the hw when coming out of rc6: There's a tiny window where
2468 * the hw runs at the minimal clock before selecting the desired
2469 * frequency, if the down threshold expires in that window we will not
2470 * receive a down interrupt. */
2471 if (*val <= dev_priv->rps.min_delay) {
2472 *val = dev_priv->rps.min_delay;
2473 limits |= dev_priv->rps.min_delay << 16;
2474 }
2475
2476 return limits;
2477 }
2478
2479 void gen6_set_rps(struct drm_device *dev, u8 val)
2480 {
2481 struct drm_i915_private *dev_priv = dev->dev_private;
2482 u32 limits = gen6_rps_limits(dev_priv, &val);
2483
2484 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
2485 WARN_ON(val > dev_priv->rps.max_delay);
2486 WARN_ON(val < dev_priv->rps.min_delay);
2487
2488 if (val == dev_priv->rps.cur_delay)
2489 return;
2490
2491 if (IS_HASWELL(dev))
2492 I915_WRITE(GEN6_RPNSWREQ,
2493 HSW_FREQUENCY(val));
2494 else
2495 I915_WRITE(GEN6_RPNSWREQ,
2496 GEN6_FREQUENCY(val) |
2497 GEN6_OFFSET(0) |
2498 GEN6_AGGRESSIVE_TURBO);
2499
2500 /* Make sure we continue to get interrupts
2501 * until we hit the minimum or maximum frequencies.
2502 */
2503 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
2504
2505 POSTING_READ(GEN6_RPNSWREQ);
2506
2507 dev_priv->rps.cur_delay = val;
2508
2509 trace_intel_gpu_freq_change(val * 50);
2510 }
2511
2512 void valleyview_set_rps(struct drm_device *dev, u8 val)
2513 {
2514 struct drm_i915_private *dev_priv = dev->dev_private;
2515 unsigned long timeout = jiffies + msecs_to_jiffies(10);
2516 u32 limits = gen6_rps_limits(dev_priv, &val);
2517 u32 pval;
2518
2519 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
2520 WARN_ON(val > dev_priv->rps.max_delay);
2521 WARN_ON(val < dev_priv->rps.min_delay);
2522
2523 DRM_DEBUG_DRIVER("gpu freq request from %d to %d\n",
2524 vlv_gpu_freq(dev_priv->mem_freq,
2525 dev_priv->rps.cur_delay),
2526 vlv_gpu_freq(dev_priv->mem_freq, val));
2527
2528 if (val == dev_priv->rps.cur_delay)
2529 return;
2530
2531 valleyview_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
2532
2533 do {
2534 valleyview_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS, &pval);
2535 if (time_after(jiffies, timeout)) {
2536 DRM_DEBUG_DRIVER("timed out waiting for Punit\n");
2537 break;
2538 }
2539 udelay(10);
2540 } while (pval & 1);
2541
2542 valleyview_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS, &pval);
2543 if ((pval >> 8) != val)
2544 DRM_DEBUG_DRIVER("punit overrode freq: %d requested, but got %d\n",
2545 val, pval >> 8);
2546
2547 /* Make sure we continue to get interrupts
2548 * until we hit the minimum or maximum frequencies.
2549 */
2550 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
2551
2552 dev_priv->rps.cur_delay = pval >> 8;
2553
2554 trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv->mem_freq, val));
2555 }
2556
2557
2558 static void gen6_disable_rps(struct drm_device *dev)
2559 {
2560 struct drm_i915_private *dev_priv = dev->dev_private;
2561
2562 I915_WRITE(GEN6_RC_CONTROL, 0);
2563 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
2564 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
2565 I915_WRITE(GEN6_PMIER, 0);
2566 /* Complete PM interrupt masking here doesn't race with the rps work
2567 * item again unmasking PM interrupts because that is using a different
2568 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
2569 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
2570
2571 spin_lock_irq(&dev_priv->rps.lock);
2572 dev_priv->rps.pm_iir = 0;
2573 spin_unlock_irq(&dev_priv->rps.lock);
2574
2575 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
2576 }
2577
2578 static void valleyview_disable_rps(struct drm_device *dev)
2579 {
2580 struct drm_i915_private *dev_priv = dev->dev_private;
2581
2582 I915_WRITE(GEN6_RC_CONTROL, 0);
2583 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
2584 I915_WRITE(GEN6_PMIER, 0);
2585 /* Complete PM interrupt masking here doesn't race with the rps work
2586 * item again unmasking PM interrupts because that is using a different
2587 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
2588 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
2589
2590 spin_lock_irq(&dev_priv->rps.lock);
2591 dev_priv->rps.pm_iir = 0;
2592 spin_unlock_irq(&dev_priv->rps.lock);
2593
2594 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
2595
2596 if (dev_priv->vlv_pctx) {
2597 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
2598 dev_priv->vlv_pctx = NULL;
2599 }
2600 }
2601
2602 int intel_enable_rc6(const struct drm_device *dev)
2603 {
2604 /* Respect the kernel parameter if it is set */
2605 if (i915_enable_rc6 >= 0)
2606 return i915_enable_rc6;
2607
2608 /* Disable RC6 on Ironlake */
2609 if (INTEL_INFO(dev)->gen == 5)
2610 return 0;
2611
2612 if (IS_HASWELL(dev)) {
2613 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
2614 return INTEL_RC6_ENABLE;
2615 }
2616
2617 /* snb/ivb have more than one rc6 state. */
2618 if (INTEL_INFO(dev)->gen == 6) {
2619 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
2620 return INTEL_RC6_ENABLE;
2621 }
2622
2623 DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n");
2624 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
2625 }
2626
2627 static void gen6_enable_rps(struct drm_device *dev)
2628 {
2629 struct drm_i915_private *dev_priv = dev->dev_private;
2630 struct intel_ring_buffer *ring;
2631 u32 rp_state_cap;
2632 u32 gt_perf_status;
2633 u32 rc6vids, pcu_mbox, rc6_mask = 0;
2634 u32 gtfifodbg;
2635 int rc6_mode;
2636 int i, ret;
2637
2638 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
2639
2640 /* Here begins a magic sequence of register writes to enable
2641 * auto-downclocking.
2642 *
2643 * Perhaps there might be some value in exposing these to
2644 * userspace...
2645 */
2646 I915_WRITE(GEN6_RC_STATE, 0);
2647
2648 /* Clear the DBG now so we don't confuse earlier errors */
2649 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
2650 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
2651 I915_WRITE(GTFIFODBG, gtfifodbg);
2652 }
2653
2654 gen6_gt_force_wake_get(dev_priv);
2655
2656 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
2657 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
2658
2659 /* In units of 50MHz */
2660 dev_priv->rps.hw_max = dev_priv->rps.max_delay = rp_state_cap & 0xff;
2661 dev_priv->rps.min_delay = (rp_state_cap & 0xff0000) >> 16;
2662 dev_priv->rps.cur_delay = 0;
2663
2664 /* disable the counters and set deterministic thresholds */
2665 I915_WRITE(GEN6_RC_CONTROL, 0);
2666
2667 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
2668 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
2669 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
2670 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
2671 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
2672
2673 for_each_ring(ring, dev_priv, i)
2674 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2675
2676 I915_WRITE(GEN6_RC_SLEEP, 0);
2677 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
2678 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
2679 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2680 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
2681
2682 /* Check if we are enabling RC6 */
2683 rc6_mode = intel_enable_rc6(dev_priv->dev);
2684 if (rc6_mode & INTEL_RC6_ENABLE)
2685 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
2686
2687 /* We don't use those on Haswell */
2688 if (!IS_HASWELL(dev)) {
2689 if (rc6_mode & INTEL_RC6p_ENABLE)
2690 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2691
2692 if (rc6_mode & INTEL_RC6pp_ENABLE)
2693 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
2694 }
2695
2696 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
2697 (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
2698 (rc6_mask & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
2699 (rc6_mask & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
2700
2701 I915_WRITE(GEN6_RC_CONTROL,
2702 rc6_mask |
2703 GEN6_RC_CTL_EI_MODE(1) |
2704 GEN6_RC_CTL_HW_ENABLE);
2705
2706 if (IS_HASWELL(dev)) {
2707 I915_WRITE(GEN6_RPNSWREQ,
2708 HSW_FREQUENCY(10));
2709 I915_WRITE(GEN6_RC_VIDEO_FREQ,
2710 HSW_FREQUENCY(12));
2711 } else {
2712 I915_WRITE(GEN6_RPNSWREQ,
2713 GEN6_FREQUENCY(10) |
2714 GEN6_OFFSET(0) |
2715 GEN6_AGGRESSIVE_TURBO);
2716 I915_WRITE(GEN6_RC_VIDEO_FREQ,
2717 GEN6_FREQUENCY(12));
2718 }
2719
2720 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
2721 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
2722 dev_priv->rps.max_delay << 24 |
2723 dev_priv->rps.min_delay << 16);
2724
2725 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
2726 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
2727 I915_WRITE(GEN6_RP_UP_EI, 66000);
2728 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
2729
2730 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2731 I915_WRITE(GEN6_RP_CONTROL,
2732 GEN6_RP_MEDIA_TURBO |
2733 GEN6_RP_MEDIA_HW_NORMAL_MODE |
2734 GEN6_RP_MEDIA_IS_GFX |
2735 GEN6_RP_ENABLE |
2736 GEN6_RP_UP_BUSY_AVG |
2737 (IS_HASWELL(dev) ? GEN7_RP_DOWN_IDLE_AVG : GEN6_RP_DOWN_IDLE_CONT));
2738
2739 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
2740 if (!ret && (IS_GEN6(dev) || IS_IVYBRIDGE(dev))) {
2741 pcu_mbox = 0;
2742 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
2743 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
2744 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
2745 (dev_priv->rps.max_delay & 0xff) * 50,
2746 (pcu_mbox & 0xff) * 50);
2747 dev_priv->rps.hw_max = pcu_mbox & 0xff;
2748 }
2749 } else {
2750 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
2751 }
2752
2753 gen6_set_rps(dev_priv->dev, (gt_perf_status & 0xff00) >> 8);
2754
2755 /* requires MSI enabled */
2756 I915_WRITE(GEN6_PMIER, GEN6_PM_DEFERRED_EVENTS);
2757 spin_lock_irq(&dev_priv->rps.lock);
2758 WARN_ON(dev_priv->rps.pm_iir != 0);
2759 I915_WRITE(GEN6_PMIMR, 0);
2760 spin_unlock_irq(&dev_priv->rps.lock);
2761 /* enable all PM interrupts */
2762 I915_WRITE(GEN6_PMINTRMSK, 0);
2763
2764 rc6vids = 0;
2765 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
2766 if (IS_GEN6(dev) && ret) {
2767 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
2768 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
2769 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
2770 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
2771 rc6vids &= 0xffff00;
2772 rc6vids |= GEN6_ENCODE_RC6_VID(450);
2773 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
2774 if (ret)
2775 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
2776 }
2777
2778 gen6_gt_force_wake_put(dev_priv);
2779 }
2780
2781 static void gen6_update_ring_freq(struct drm_device *dev)
2782 {
2783 struct drm_i915_private *dev_priv = dev->dev_private;
2784 int min_freq = 15;
2785 unsigned int gpu_freq;
2786 unsigned int max_ia_freq, min_ring_freq;
2787 int scaling_factor = 180;
2788
2789 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
2790
2791 max_ia_freq = cpufreq_quick_get_max(0);
2792 /*
2793 * Default to measured freq if none found, PCU will ensure we don't go
2794 * over
2795 */
2796 if (!max_ia_freq)
2797 max_ia_freq = tsc_khz;
2798
2799 /* Convert from kHz to MHz */
2800 max_ia_freq /= 1000;
2801
2802 min_ring_freq = I915_READ(MCHBAR_MIRROR_BASE_SNB + DCLK);
2803 /* convert DDR frequency from units of 133.3MHz to bandwidth */
2804 min_ring_freq = (2 * 4 * min_ring_freq + 2) / 3;
2805
2806 /*
2807 * For each potential GPU frequency, load a ring frequency we'd like
2808 * to use for memory access. We do this by specifying the IA frequency
2809 * the PCU should use as a reference to determine the ring frequency.
2810 */
2811 for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay;
2812 gpu_freq--) {
2813 int diff = dev_priv->rps.max_delay - gpu_freq;
2814 unsigned int ia_freq = 0, ring_freq = 0;
2815
2816 if (IS_HASWELL(dev)) {
2817 ring_freq = (gpu_freq * 5 + 3) / 4;
2818 ring_freq = max(min_ring_freq, ring_freq);
2819 /* leave ia_freq as the default, chosen by cpufreq */
2820 } else {
2821 /* On older processors, there is no separate ring
2822 * clock domain, so in order to boost the bandwidth
2823 * of the ring, we need to upclock the CPU (ia_freq).
2824 *
2825 * For GPU frequencies less than 750MHz,
2826 * just use the lowest ring freq.
2827 */
2828 if (gpu_freq < min_freq)
2829 ia_freq = 800;
2830 else
2831 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
2832 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
2833 }
2834
2835 sandybridge_pcode_write(dev_priv,
2836 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
2837 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
2838 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
2839 gpu_freq);
2840 }
2841 }
2842
2843 int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
2844 {
2845 u32 val, rp0;
2846
2847 valleyview_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE, &val);
2848
2849 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
2850 /* Clamp to max */
2851 rp0 = min_t(u32, rp0, 0xea);
2852
2853 return rp0;
2854 }
2855
2856 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
2857 {
2858 u32 val, rpe;
2859
2860 valleyview_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO, &val);
2861 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
2862 valleyview_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI, &val);
2863 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
2864
2865 return rpe;
2866 }
2867
2868 int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
2869 {
2870 u32 val;
2871
2872 valleyview_punit_read(dev_priv, PUNIT_REG_GPU_LFM, &val);
2873
2874 return val & 0xff;
2875 }
2876
2877 static void vlv_rps_timer_work(struct work_struct *work)
2878 {
2879 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
2880 rps.vlv_work.work);
2881
2882 /*
2883 * Timer fired, we must be idle. Drop to min voltage state.
2884 * Note: we use RPe here since it should match the
2885 * Vmin we were shooting for. That should give us better
2886 * perf when we come back out of RC6 than if we used the
2887 * min freq available.
2888 */
2889 mutex_lock(&dev_priv->rps.hw_lock);
2890 valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
2891 mutex_unlock(&dev_priv->rps.hw_lock);
2892 }
2893
2894 static void valleyview_setup_pctx(struct drm_device *dev)
2895 {
2896 struct drm_i915_private *dev_priv = dev->dev_private;
2897 struct drm_i915_gem_object *pctx;
2898 unsigned long pctx_paddr;
2899 u32 pcbr;
2900 int pctx_size = 24*1024;
2901
2902 pcbr = I915_READ(VLV_PCBR);
2903 if (pcbr) {
2904 /* BIOS set it up already, grab the pre-alloc'd space */
2905 int pcbr_offset;
2906
2907 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
2908 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
2909 pcbr_offset,
2910 -1,
2911 pctx_size);
2912 goto out;
2913 }
2914
2915 /*
2916 * From the Gunit register HAS:
2917 * The Gfx driver is expected to program this register and ensure
2918 * proper allocation within Gfx stolen memory. For example, this
2919 * register should be programmed such than the PCBR range does not
2920 * overlap with other ranges, such as the frame buffer, protected
2921 * memory, or any other relevant ranges.
2922 */
2923 pctx = i915_gem_object_create_stolen(dev, pctx_size);
2924 if (!pctx) {
2925 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
2926 return;
2927 }
2928
2929 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
2930 I915_WRITE(VLV_PCBR, pctx_paddr);
2931
2932 out:
2933 dev_priv->vlv_pctx = pctx;
2934 }
2935
2936 static void valleyview_enable_rps(struct drm_device *dev)
2937 {
2938 struct drm_i915_private *dev_priv = dev->dev_private;
2939 struct intel_ring_buffer *ring;
2940 u32 gtfifodbg, val, rpe;
2941 int i;
2942
2943 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
2944
2945 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
2946 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
2947 I915_WRITE(GTFIFODBG, gtfifodbg);
2948 }
2949
2950 valleyview_setup_pctx(dev);
2951
2952 gen6_gt_force_wake_get(dev_priv);
2953
2954 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
2955 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
2956 I915_WRITE(GEN6_RP_UP_EI, 66000);
2957 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
2958
2959 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2960
2961 I915_WRITE(GEN6_RP_CONTROL,
2962 GEN6_RP_MEDIA_TURBO |
2963 GEN6_RP_MEDIA_HW_NORMAL_MODE |
2964 GEN6_RP_MEDIA_IS_GFX |
2965 GEN6_RP_ENABLE |
2966 GEN6_RP_UP_BUSY_AVG |
2967 GEN6_RP_DOWN_IDLE_CONT);
2968
2969 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
2970 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
2971 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
2972
2973 for_each_ring(ring, dev_priv, i)
2974 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2975
2976 I915_WRITE(GEN6_RC6_THRESHOLD, 0xc350);
2977
2978 /* allows RC6 residency counter to work */
2979 I915_WRITE(0x138104, _MASKED_BIT_ENABLE(0x3));
2980 I915_WRITE(GEN6_RC_CONTROL,
2981 GEN7_RC_CTL_TO_MODE);
2982
2983 valleyview_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS, &val);
2984 switch ((val >> 6) & 3) {
2985 case 0:
2986 case 1:
2987 dev_priv->mem_freq = 800;
2988 break;
2989 case 2:
2990 dev_priv->mem_freq = 1066;
2991 break;
2992 case 3:
2993 dev_priv->mem_freq = 1333;
2994 break;
2995 }
2996 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
2997
2998 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
2999 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
3000
3001 DRM_DEBUG_DRIVER("current GPU freq: %d\n",
3002 vlv_gpu_freq(dev_priv->mem_freq, (val >> 8) & 0xff));
3003 dev_priv->rps.cur_delay = (val >> 8) & 0xff;
3004
3005 dev_priv->rps.max_delay = valleyview_rps_max_freq(dev_priv);
3006 dev_priv->rps.hw_max = dev_priv->rps.max_delay;
3007 DRM_DEBUG_DRIVER("max GPU freq: %d\n", vlv_gpu_freq(dev_priv->mem_freq,
3008 dev_priv->rps.max_delay));
3009
3010 rpe = valleyview_rps_rpe_freq(dev_priv);
3011 DRM_DEBUG_DRIVER("RPe GPU freq: %d\n",
3012 vlv_gpu_freq(dev_priv->mem_freq, rpe));
3013 dev_priv->rps.rpe_delay = rpe;
3014
3015 val = valleyview_rps_min_freq(dev_priv);
3016 DRM_DEBUG_DRIVER("min GPU freq: %d\n", vlv_gpu_freq(dev_priv->mem_freq,
3017 val));
3018 dev_priv->rps.min_delay = val;
3019
3020 DRM_DEBUG_DRIVER("setting GPU freq to %d\n",
3021 vlv_gpu_freq(dev_priv->mem_freq, rpe));
3022
3023 INIT_DELAYED_WORK(&dev_priv->rps.vlv_work, vlv_rps_timer_work);
3024
3025 valleyview_set_rps(dev_priv->dev, rpe);
3026
3027 /* requires MSI enabled */
3028 I915_WRITE(GEN6_PMIER, GEN6_PM_DEFERRED_EVENTS);
3029 spin_lock_irq(&dev_priv->rps.lock);
3030 WARN_ON(dev_priv->rps.pm_iir != 0);
3031 I915_WRITE(GEN6_PMIMR, 0);
3032 spin_unlock_irq(&dev_priv->rps.lock);
3033 /* enable all PM interrupts */
3034 I915_WRITE(GEN6_PMINTRMSK, 0);
3035
3036 gen6_gt_force_wake_put(dev_priv);
3037 }
3038
3039 void ironlake_teardown_rc6(struct drm_device *dev)
3040 {
3041 struct drm_i915_private *dev_priv = dev->dev_private;
3042
3043 if (dev_priv->ips.renderctx) {
3044 i915_gem_object_unpin(dev_priv->ips.renderctx);
3045 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
3046 dev_priv->ips.renderctx = NULL;
3047 }
3048
3049 if (dev_priv->ips.pwrctx) {
3050 i915_gem_object_unpin(dev_priv->ips.pwrctx);
3051 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
3052 dev_priv->ips.pwrctx = NULL;
3053 }
3054 }
3055
3056 static void ironlake_disable_rc6(struct drm_device *dev)
3057 {
3058 struct drm_i915_private *dev_priv = dev->dev_private;
3059
3060 if (I915_READ(PWRCTXA)) {
3061 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
3062 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
3063 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
3064 50);
3065
3066 I915_WRITE(PWRCTXA, 0);
3067 POSTING_READ(PWRCTXA);
3068
3069 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
3070 POSTING_READ(RSTDBYCTL);
3071 }
3072 }
3073
3074 static int ironlake_setup_rc6(struct drm_device *dev)
3075 {
3076 struct drm_i915_private *dev_priv = dev->dev_private;
3077
3078 if (dev_priv->ips.renderctx == NULL)
3079 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
3080 if (!dev_priv->ips.renderctx)
3081 return -ENOMEM;
3082
3083 if (dev_priv->ips.pwrctx == NULL)
3084 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
3085 if (!dev_priv->ips.pwrctx) {
3086 ironlake_teardown_rc6(dev);
3087 return -ENOMEM;
3088 }
3089
3090 return 0;
3091 }
3092
3093 static void ironlake_enable_rc6(struct drm_device *dev)
3094 {
3095 struct drm_i915_private *dev_priv = dev->dev_private;
3096 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
3097 bool was_interruptible;
3098 int ret;
3099
3100 /* rc6 disabled by default due to repeated reports of hanging during
3101 * boot and resume.
3102 */
3103 if (!intel_enable_rc6(dev))
3104 return;
3105
3106 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3107
3108 ret = ironlake_setup_rc6(dev);
3109 if (ret)
3110 return;
3111
3112 was_interruptible = dev_priv->mm.interruptible;
3113 dev_priv->mm.interruptible = false;
3114
3115 /*
3116 * GPU can automatically power down the render unit if given a page
3117 * to save state.
3118 */
3119 ret = intel_ring_begin(ring, 6);
3120 if (ret) {
3121 ironlake_teardown_rc6(dev);
3122 dev_priv->mm.interruptible = was_interruptible;
3123 return;
3124 }
3125
3126 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
3127 intel_ring_emit(ring, MI_SET_CONTEXT);
3128 intel_ring_emit(ring, dev_priv->ips.renderctx->gtt_offset |
3129 MI_MM_SPACE_GTT |
3130 MI_SAVE_EXT_STATE_EN |
3131 MI_RESTORE_EXT_STATE_EN |
3132 MI_RESTORE_INHIBIT);
3133 intel_ring_emit(ring, MI_SUSPEND_FLUSH);
3134 intel_ring_emit(ring, MI_NOOP);
3135 intel_ring_emit(ring, MI_FLUSH);
3136 intel_ring_advance(ring);
3137
3138 /*
3139 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
3140 * does an implicit flush, combined with MI_FLUSH above, it should be
3141 * safe to assume that renderctx is valid
3142 */
3143 ret = intel_ring_idle(ring);
3144 dev_priv->mm.interruptible = was_interruptible;
3145 if (ret) {
3146 DRM_ERROR("failed to enable ironlake power savings\n");
3147 ironlake_teardown_rc6(dev);
3148 return;
3149 }
3150
3151 I915_WRITE(PWRCTXA, dev_priv->ips.pwrctx->gtt_offset | PWRCTX_EN);
3152 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
3153 }
3154
3155 static unsigned long intel_pxfreq(u32 vidfreq)
3156 {
3157 unsigned long freq;
3158 int div = (vidfreq & 0x3f0000) >> 16;
3159 int post = (vidfreq & 0x3000) >> 12;
3160 int pre = (vidfreq & 0x7);
3161
3162 if (!pre)
3163 return 0;
3164
3165 freq = ((div * 133333) / ((1<<post) * pre));
3166
3167 return freq;
3168 }
3169
3170 static const struct cparams {
3171 u16 i;
3172 u16 t;
3173 u16 m;
3174 u16 c;
3175 } cparams[] = {
3176 { 1, 1333, 301, 28664 },
3177 { 1, 1066, 294, 24460 },
3178 { 1, 800, 294, 25192 },
3179 { 0, 1333, 276, 27605 },
3180 { 0, 1066, 276, 27605 },
3181 { 0, 800, 231, 23784 },
3182 };
3183
3184 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
3185 {
3186 u64 total_count, diff, ret;
3187 u32 count1, count2, count3, m = 0, c = 0;
3188 unsigned long now = jiffies_to_msecs(jiffies), diff1;
3189 int i;
3190
3191 assert_spin_locked(&mchdev_lock);
3192
3193 diff1 = now - dev_priv->ips.last_time1;
3194
3195 /* Prevent division-by-zero if we are asking too fast.
3196 * Also, we don't get interesting results if we are polling
3197 * faster than once in 10ms, so just return the saved value
3198 * in such cases.
3199 */
3200 if (diff1 <= 10)
3201 return dev_priv->ips.chipset_power;
3202
3203 count1 = I915_READ(DMIEC);
3204 count2 = I915_READ(DDREC);
3205 count3 = I915_READ(CSIEC);
3206
3207 total_count = count1 + count2 + count3;
3208
3209 /* FIXME: handle per-counter overflow */
3210 if (total_count < dev_priv->ips.last_count1) {
3211 diff = ~0UL - dev_priv->ips.last_count1;
3212 diff += total_count;
3213 } else {
3214 diff = total_count - dev_priv->ips.last_count1;
3215 }
3216
3217 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
3218 if (cparams[i].i == dev_priv->ips.c_m &&
3219 cparams[i].t == dev_priv->ips.r_t) {
3220 m = cparams[i].m;
3221 c = cparams[i].c;
3222 break;
3223 }
3224 }
3225
3226 diff = div_u64(diff, diff1);
3227 ret = ((m * diff) + c);
3228 ret = div_u64(ret, 10);
3229
3230 dev_priv->ips.last_count1 = total_count;
3231 dev_priv->ips.last_time1 = now;
3232
3233 dev_priv->ips.chipset_power = ret;
3234
3235 return ret;
3236 }
3237
3238 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
3239 {
3240 unsigned long val;
3241
3242 if (dev_priv->info->gen != 5)
3243 return 0;
3244
3245 spin_lock_irq(&mchdev_lock);
3246
3247 val = __i915_chipset_val(dev_priv);
3248
3249 spin_unlock_irq(&mchdev_lock);
3250
3251 return val;
3252 }
3253
3254 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
3255 {
3256 unsigned long m, x, b;
3257 u32 tsfs;
3258
3259 tsfs = I915_READ(TSFS);
3260
3261 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
3262 x = I915_READ8(TR1);
3263
3264 b = tsfs & TSFS_INTR_MASK;
3265
3266 return ((m * x) / 127) - b;
3267 }
3268
3269 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
3270 {
3271 static const struct v_table {
3272 u16 vd; /* in .1 mil */
3273 u16 vm; /* in .1 mil */
3274 } v_table[] = {
3275 { 0, 0, },
3276 { 375, 0, },
3277 { 500, 0, },
3278 { 625, 0, },
3279 { 750, 0, },
3280 { 875, 0, },
3281 { 1000, 0, },
3282 { 1125, 0, },
3283 { 4125, 3000, },
3284 { 4125, 3000, },
3285 { 4125, 3000, },
3286 { 4125, 3000, },
3287 { 4125, 3000, },
3288 { 4125, 3000, },
3289 { 4125, 3000, },
3290 { 4125, 3000, },
3291 { 4125, 3000, },
3292 { 4125, 3000, },
3293 { 4125, 3000, },
3294 { 4125, 3000, },
3295 { 4125, 3000, },
3296 { 4125, 3000, },
3297 { 4125, 3000, },
3298 { 4125, 3000, },
3299 { 4125, 3000, },
3300 { 4125, 3000, },
3301 { 4125, 3000, },
3302 { 4125, 3000, },
3303 { 4125, 3000, },
3304 { 4125, 3000, },
3305 { 4125, 3000, },
3306 { 4125, 3000, },
3307 { 4250, 3125, },
3308 { 4375, 3250, },
3309 { 4500, 3375, },
3310 { 4625, 3500, },
3311 { 4750, 3625, },
3312 { 4875, 3750, },
3313 { 5000, 3875, },
3314 { 5125, 4000, },
3315 { 5250, 4125, },
3316 { 5375, 4250, },
3317 { 5500, 4375, },
3318 { 5625, 4500, },
3319 { 5750, 4625, },
3320 { 5875, 4750, },
3321 { 6000, 4875, },
3322 { 6125, 5000, },
3323 { 6250, 5125, },
3324 { 6375, 5250, },
3325 { 6500, 5375, },
3326 { 6625, 5500, },
3327 { 6750, 5625, },
3328 { 6875, 5750, },
3329 { 7000, 5875, },
3330 { 7125, 6000, },
3331 { 7250, 6125, },
3332 { 7375, 6250, },
3333 { 7500, 6375, },
3334 { 7625, 6500, },
3335 { 7750, 6625, },
3336 { 7875, 6750, },
3337 { 8000, 6875, },
3338 { 8125, 7000, },
3339 { 8250, 7125, },
3340 { 8375, 7250, },
3341 { 8500, 7375, },
3342 { 8625, 7500, },
3343 { 8750, 7625, },
3344 { 8875, 7750, },
3345 { 9000, 7875, },
3346 { 9125, 8000, },
3347 { 9250, 8125, },
3348 { 9375, 8250, },
3349 { 9500, 8375, },
3350 { 9625, 8500, },
3351 { 9750, 8625, },
3352 { 9875, 8750, },
3353 { 10000, 8875, },
3354 { 10125, 9000, },
3355 { 10250, 9125, },
3356 { 10375, 9250, },
3357 { 10500, 9375, },
3358 { 10625, 9500, },
3359 { 10750, 9625, },
3360 { 10875, 9750, },
3361 { 11000, 9875, },
3362 { 11125, 10000, },
3363 { 11250, 10125, },
3364 { 11375, 10250, },
3365 { 11500, 10375, },
3366 { 11625, 10500, },
3367 { 11750, 10625, },
3368 { 11875, 10750, },
3369 { 12000, 10875, },
3370 { 12125, 11000, },
3371 { 12250, 11125, },
3372 { 12375, 11250, },
3373 { 12500, 11375, },
3374 { 12625, 11500, },
3375 { 12750, 11625, },
3376 { 12875, 11750, },
3377 { 13000, 11875, },
3378 { 13125, 12000, },
3379 { 13250, 12125, },
3380 { 13375, 12250, },
3381 { 13500, 12375, },
3382 { 13625, 12500, },
3383 { 13750, 12625, },
3384 { 13875, 12750, },
3385 { 14000, 12875, },
3386 { 14125, 13000, },
3387 { 14250, 13125, },
3388 { 14375, 13250, },
3389 { 14500, 13375, },
3390 { 14625, 13500, },
3391 { 14750, 13625, },
3392 { 14875, 13750, },
3393 { 15000, 13875, },
3394 { 15125, 14000, },
3395 { 15250, 14125, },
3396 { 15375, 14250, },
3397 { 15500, 14375, },
3398 { 15625, 14500, },
3399 { 15750, 14625, },
3400 { 15875, 14750, },
3401 { 16000, 14875, },
3402 { 16125, 15000, },
3403 };
3404 if (dev_priv->info->is_mobile)
3405 return v_table[pxvid].vm;
3406 else
3407 return v_table[pxvid].vd;
3408 }
3409
3410 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
3411 {
3412 struct timespec now, diff1;
3413 u64 diff;
3414 unsigned long diffms;
3415 u32 count;
3416
3417 assert_spin_locked(&mchdev_lock);
3418
3419 getrawmonotonic(&now);
3420 diff1 = timespec_sub(now, dev_priv->ips.last_time2);
3421
3422 /* Don't divide by 0 */
3423 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
3424 if (!diffms)
3425 return;
3426
3427 count = I915_READ(GFXEC);
3428
3429 if (count < dev_priv->ips.last_count2) {
3430 diff = ~0UL - dev_priv->ips.last_count2;
3431 diff += count;
3432 } else {
3433 diff = count - dev_priv->ips.last_count2;
3434 }
3435
3436 dev_priv->ips.last_count2 = count;
3437 dev_priv->ips.last_time2 = now;
3438
3439 /* More magic constants... */
3440 diff = diff * 1181;
3441 diff = div_u64(diff, diffms * 10);
3442 dev_priv->ips.gfx_power = diff;
3443 }
3444
3445 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
3446 {
3447 if (dev_priv->info->gen != 5)
3448 return;
3449
3450 spin_lock_irq(&mchdev_lock);
3451
3452 __i915_update_gfx_val(dev_priv);
3453
3454 spin_unlock_irq(&mchdev_lock);
3455 }
3456
3457 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
3458 {
3459 unsigned long t, corr, state1, corr2, state2;
3460 u32 pxvid, ext_v;
3461
3462 assert_spin_locked(&mchdev_lock);
3463
3464 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4));
3465 pxvid = (pxvid >> 24) & 0x7f;
3466 ext_v = pvid_to_extvid(dev_priv, pxvid);
3467
3468 state1 = ext_v;
3469
3470 t = i915_mch_val(dev_priv);
3471
3472 /* Revel in the empirically derived constants */
3473
3474 /* Correction factor in 1/100000 units */
3475 if (t > 80)
3476 corr = ((t * 2349) + 135940);
3477 else if (t >= 50)
3478 corr = ((t * 964) + 29317);
3479 else /* < 50 */
3480 corr = ((t * 301) + 1004);
3481
3482 corr = corr * ((150142 * state1) / 10000 - 78642);
3483 corr /= 100000;
3484 corr2 = (corr * dev_priv->ips.corr);
3485
3486 state2 = (corr2 * state1) / 10000;
3487 state2 /= 100; /* convert to mW */
3488
3489 __i915_update_gfx_val(dev_priv);
3490
3491 return dev_priv->ips.gfx_power + state2;
3492 }
3493
3494 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
3495 {
3496 unsigned long val;
3497
3498 if (dev_priv->info->gen != 5)
3499 return 0;
3500
3501 spin_lock_irq(&mchdev_lock);
3502
3503 val = __i915_gfx_val(dev_priv);
3504
3505 spin_unlock_irq(&mchdev_lock);
3506
3507 return val;
3508 }
3509
3510 /**
3511 * i915_read_mch_val - return value for IPS use
3512 *
3513 * Calculate and return a value for the IPS driver to use when deciding whether
3514 * we have thermal and power headroom to increase CPU or GPU power budget.
3515 */
3516 unsigned long i915_read_mch_val(void)
3517 {
3518 struct drm_i915_private *dev_priv;
3519 unsigned long chipset_val, graphics_val, ret = 0;
3520
3521 spin_lock_irq(&mchdev_lock);
3522 if (!i915_mch_dev)
3523 goto out_unlock;
3524 dev_priv = i915_mch_dev;
3525
3526 chipset_val = __i915_chipset_val(dev_priv);
3527 graphics_val = __i915_gfx_val(dev_priv);
3528
3529 ret = chipset_val + graphics_val;
3530
3531 out_unlock:
3532 spin_unlock_irq(&mchdev_lock);
3533
3534 return ret;
3535 }
3536 EXPORT_SYMBOL_GPL(i915_read_mch_val);
3537
3538 /**
3539 * i915_gpu_raise - raise GPU frequency limit
3540 *
3541 * Raise the limit; IPS indicates we have thermal headroom.
3542 */
3543 bool i915_gpu_raise(void)
3544 {
3545 struct drm_i915_private *dev_priv;
3546 bool ret = true;
3547
3548 spin_lock_irq(&mchdev_lock);
3549 if (!i915_mch_dev) {
3550 ret = false;
3551 goto out_unlock;
3552 }
3553 dev_priv = i915_mch_dev;
3554
3555 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
3556 dev_priv->ips.max_delay--;
3557
3558 out_unlock:
3559 spin_unlock_irq(&mchdev_lock);
3560
3561 return ret;
3562 }
3563 EXPORT_SYMBOL_GPL(i915_gpu_raise);
3564
3565 /**
3566 * i915_gpu_lower - lower GPU frequency limit
3567 *
3568 * IPS indicates we're close to a thermal limit, so throttle back the GPU
3569 * frequency maximum.
3570 */
3571 bool i915_gpu_lower(void)
3572 {
3573 struct drm_i915_private *dev_priv;
3574 bool ret = true;
3575
3576 spin_lock_irq(&mchdev_lock);
3577 if (!i915_mch_dev) {
3578 ret = false;
3579 goto out_unlock;
3580 }
3581 dev_priv = i915_mch_dev;
3582
3583 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
3584 dev_priv->ips.max_delay++;
3585
3586 out_unlock:
3587 spin_unlock_irq(&mchdev_lock);
3588
3589 return ret;
3590 }
3591 EXPORT_SYMBOL_GPL(i915_gpu_lower);
3592
3593 /**
3594 * i915_gpu_busy - indicate GPU business to IPS
3595 *
3596 * Tell the IPS driver whether or not the GPU is busy.
3597 */
3598 bool i915_gpu_busy(void)
3599 {
3600 struct drm_i915_private *dev_priv;
3601 struct intel_ring_buffer *ring;
3602 bool ret = false;
3603 int i;
3604
3605 spin_lock_irq(&mchdev_lock);
3606 if (!i915_mch_dev)
3607 goto out_unlock;
3608 dev_priv = i915_mch_dev;
3609
3610 for_each_ring(ring, dev_priv, i)
3611 ret |= !list_empty(&ring->request_list);
3612
3613 out_unlock:
3614 spin_unlock_irq(&mchdev_lock);
3615
3616 return ret;
3617 }
3618 EXPORT_SYMBOL_GPL(i915_gpu_busy);
3619
3620 /**
3621 * i915_gpu_turbo_disable - disable graphics turbo
3622 *
3623 * Disable graphics turbo by resetting the max frequency and setting the
3624 * current frequency to the default.
3625 */
3626 bool i915_gpu_turbo_disable(void)
3627 {
3628 struct drm_i915_private *dev_priv;
3629 bool ret = true;
3630
3631 spin_lock_irq(&mchdev_lock);
3632 if (!i915_mch_dev) {
3633 ret = false;
3634 goto out_unlock;
3635 }
3636 dev_priv = i915_mch_dev;
3637
3638 dev_priv->ips.max_delay = dev_priv->ips.fstart;
3639
3640 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
3641 ret = false;
3642
3643 out_unlock:
3644 spin_unlock_irq(&mchdev_lock);
3645
3646 return ret;
3647 }
3648 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
3649
3650 /**
3651 * Tells the intel_ips driver that the i915 driver is now loaded, if
3652 * IPS got loaded first.
3653 *
3654 * This awkward dance is so that neither module has to depend on the
3655 * other in order for IPS to do the appropriate communication of
3656 * GPU turbo limits to i915.
3657 */
3658 static void
3659 ips_ping_for_i915_load(void)
3660 {
3661 void (*link)(void);
3662
3663 link = symbol_get(ips_link_to_i915_driver);
3664 if (link) {
3665 link();
3666 symbol_put(ips_link_to_i915_driver);
3667 }
3668 }
3669
3670 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
3671 {
3672 /* We only register the i915 ips part with intel-ips once everything is
3673 * set up, to avoid intel-ips sneaking in and reading bogus values. */
3674 spin_lock_irq(&mchdev_lock);
3675 i915_mch_dev = dev_priv;
3676 spin_unlock_irq(&mchdev_lock);
3677
3678 ips_ping_for_i915_load();
3679 }
3680
3681 void intel_gpu_ips_teardown(void)
3682 {
3683 spin_lock_irq(&mchdev_lock);
3684 i915_mch_dev = NULL;
3685 spin_unlock_irq(&mchdev_lock);
3686 }
3687 static void intel_init_emon(struct drm_device *dev)
3688 {
3689 struct drm_i915_private *dev_priv = dev->dev_private;
3690 u32 lcfuse;
3691 u8 pxw[16];
3692 int i;
3693
3694 /* Disable to program */
3695 I915_WRITE(ECR, 0);
3696 POSTING_READ(ECR);
3697
3698 /* Program energy weights for various events */
3699 I915_WRITE(SDEW, 0x15040d00);
3700 I915_WRITE(CSIEW0, 0x007f0000);
3701 I915_WRITE(CSIEW1, 0x1e220004);
3702 I915_WRITE(CSIEW2, 0x04000004);
3703
3704 for (i = 0; i < 5; i++)
3705 I915_WRITE(PEW + (i * 4), 0);
3706 for (i = 0; i < 3; i++)
3707 I915_WRITE(DEW + (i * 4), 0);
3708
3709 /* Program P-state weights to account for frequency power adjustment */
3710 for (i = 0; i < 16; i++) {
3711 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
3712 unsigned long freq = intel_pxfreq(pxvidfreq);
3713 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
3714 PXVFREQ_PX_SHIFT;
3715 unsigned long val;
3716
3717 val = vid * vid;
3718 val *= (freq / 1000);
3719 val *= 255;
3720 val /= (127*127*900);
3721 if (val > 0xff)
3722 DRM_ERROR("bad pxval: %ld\n", val);
3723 pxw[i] = val;
3724 }
3725 /* Render standby states get 0 weight */
3726 pxw[14] = 0;
3727 pxw[15] = 0;
3728
3729 for (i = 0; i < 4; i++) {
3730 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
3731 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
3732 I915_WRITE(PXW + (i * 4), val);
3733 }
3734
3735 /* Adjust magic regs to magic values (more experimental results) */
3736 I915_WRITE(OGW0, 0);
3737 I915_WRITE(OGW1, 0);
3738 I915_WRITE(EG0, 0x00007f00);
3739 I915_WRITE(EG1, 0x0000000e);
3740 I915_WRITE(EG2, 0x000e0000);
3741 I915_WRITE(EG3, 0x68000300);
3742 I915_WRITE(EG4, 0x42000000);
3743 I915_WRITE(EG5, 0x00140031);
3744 I915_WRITE(EG6, 0);
3745 I915_WRITE(EG7, 0);
3746
3747 for (i = 0; i < 8; i++)
3748 I915_WRITE(PXWL + (i * 4), 0);
3749
3750 /* Enable PMON + select events */
3751 I915_WRITE(ECR, 0x80000019);
3752
3753 lcfuse = I915_READ(LCFUSE02);
3754
3755 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
3756 }
3757
3758 void intel_disable_gt_powersave(struct drm_device *dev)
3759 {
3760 struct drm_i915_private *dev_priv = dev->dev_private;
3761
3762 /* Interrupts should be disabled already to avoid re-arming. */
3763 WARN_ON(dev->irq_enabled);
3764
3765 if (IS_IRONLAKE_M(dev)) {
3766 ironlake_disable_drps(dev);
3767 ironlake_disable_rc6(dev);
3768 } else if (INTEL_INFO(dev)->gen >= 6) {
3769 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
3770 cancel_work_sync(&dev_priv->rps.work);
3771 if (IS_VALLEYVIEW(dev))
3772 cancel_delayed_work_sync(&dev_priv->rps.vlv_work);
3773 mutex_lock(&dev_priv->rps.hw_lock);
3774 if (IS_VALLEYVIEW(dev))
3775 valleyview_disable_rps(dev);
3776 else
3777 gen6_disable_rps(dev);
3778 mutex_unlock(&dev_priv->rps.hw_lock);
3779 }
3780 }
3781
3782 static void intel_gen6_powersave_work(struct work_struct *work)
3783 {
3784 struct drm_i915_private *dev_priv =
3785 container_of(work, struct drm_i915_private,
3786 rps.delayed_resume_work.work);
3787 struct drm_device *dev = dev_priv->dev;
3788
3789 mutex_lock(&dev_priv->rps.hw_lock);
3790
3791 if (IS_VALLEYVIEW(dev)) {
3792 valleyview_enable_rps(dev);
3793 } else {
3794 gen6_enable_rps(dev);
3795 gen6_update_ring_freq(dev);
3796 }
3797 mutex_unlock(&dev_priv->rps.hw_lock);
3798 }
3799
3800 void intel_enable_gt_powersave(struct drm_device *dev)
3801 {
3802 struct drm_i915_private *dev_priv = dev->dev_private;
3803
3804 if (IS_IRONLAKE_M(dev)) {
3805 ironlake_enable_drps(dev);
3806 ironlake_enable_rc6(dev);
3807 intel_init_emon(dev);
3808 } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
3809 /*
3810 * PCU communication is slow and this doesn't need to be
3811 * done at any specific time, so do this out of our fast path
3812 * to make resume and init faster.
3813 */
3814 schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
3815 round_jiffies_up_relative(HZ));
3816 }
3817 }
3818
3819 static void ibx_init_clock_gating(struct drm_device *dev)
3820 {
3821 struct drm_i915_private *dev_priv = dev->dev_private;
3822
3823 /*
3824 * On Ibex Peak and Cougar Point, we need to disable clock
3825 * gating for the panel power sequencer or it will fail to
3826 * start up when no ports are active.
3827 */
3828 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
3829 }
3830
3831 static void ironlake_init_clock_gating(struct drm_device *dev)
3832 {
3833 struct drm_i915_private *dev_priv = dev->dev_private;
3834 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
3835
3836 /* Required for FBC */
3837 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
3838 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
3839 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
3840
3841 I915_WRITE(PCH_3DCGDIS0,
3842 MARIUNIT_CLOCK_GATE_DISABLE |
3843 SVSMUNIT_CLOCK_GATE_DISABLE);
3844 I915_WRITE(PCH_3DCGDIS1,
3845 VFMUNIT_CLOCK_GATE_DISABLE);
3846
3847 /*
3848 * According to the spec the following bits should be set in
3849 * order to enable memory self-refresh
3850 * The bit 22/21 of 0x42004
3851 * The bit 5 of 0x42020
3852 * The bit 15 of 0x45000
3853 */
3854 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3855 (I915_READ(ILK_DISPLAY_CHICKEN2) |
3856 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
3857 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
3858 I915_WRITE(DISP_ARB_CTL,
3859 (I915_READ(DISP_ARB_CTL) |
3860 DISP_FBC_WM_DIS));
3861 I915_WRITE(WM3_LP_ILK, 0);
3862 I915_WRITE(WM2_LP_ILK, 0);
3863 I915_WRITE(WM1_LP_ILK, 0);
3864
3865 /*
3866 * Based on the document from hardware guys the following bits
3867 * should be set unconditionally in order to enable FBC.
3868 * The bit 22 of 0x42000
3869 * The bit 22 of 0x42004
3870 * The bit 7,8,9 of 0x42020.
3871 */
3872 if (IS_IRONLAKE_M(dev)) {
3873 I915_WRITE(ILK_DISPLAY_CHICKEN1,
3874 I915_READ(ILK_DISPLAY_CHICKEN1) |
3875 ILK_FBCQ_DIS);
3876 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3877 I915_READ(ILK_DISPLAY_CHICKEN2) |
3878 ILK_DPARB_GATE);
3879 }
3880
3881 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
3882
3883 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3884 I915_READ(ILK_DISPLAY_CHICKEN2) |
3885 ILK_ELPIN_409_SELECT);
3886 I915_WRITE(_3D_CHICKEN2,
3887 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
3888 _3D_CHICKEN2_WM_READ_PIPELINED);
3889
3890 /* WaDisableRenderCachePipelinedFlush:ilk */
3891 I915_WRITE(CACHE_MODE_0,
3892 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3893
3894 ibx_init_clock_gating(dev);
3895 }
3896
3897 static void cpt_init_clock_gating(struct drm_device *dev)
3898 {
3899 struct drm_i915_private *dev_priv = dev->dev_private;
3900 int pipe;
3901 uint32_t val;
3902
3903 /*
3904 * On Ibex Peak and Cougar Point, we need to disable clock
3905 * gating for the panel power sequencer or it will fail to
3906 * start up when no ports are active.
3907 */
3908 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
3909 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
3910 DPLS_EDP_PPS_FIX_DIS);
3911 /* The below fixes the weird display corruption, a few pixels shifted
3912 * downward, on (only) LVDS of some HP laptops with IVY.
3913 */
3914 for_each_pipe(pipe) {
3915 val = I915_READ(TRANS_CHICKEN2(pipe));
3916 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
3917 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
3918 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3919 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
3920 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
3921 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
3922 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3923 I915_WRITE(TRANS_CHICKEN2(pipe), val);
3924 }
3925 /* WADP0ClockGatingDisable */
3926 for_each_pipe(pipe) {
3927 I915_WRITE(TRANS_CHICKEN1(pipe),
3928 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
3929 }
3930 }
3931
3932 static void gen6_check_mch_setup(struct drm_device *dev)
3933 {
3934 struct drm_i915_private *dev_priv = dev->dev_private;
3935 uint32_t tmp;
3936
3937 tmp = I915_READ(MCH_SSKPD);
3938 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) {
3939 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp);
3940 DRM_INFO("This can cause pipe underruns and display issues.\n");
3941 DRM_INFO("Please upgrade your BIOS to fix this.\n");
3942 }
3943 }
3944
3945 static void gen6_init_clock_gating(struct drm_device *dev)
3946 {
3947 struct drm_i915_private *dev_priv = dev->dev_private;
3948 int pipe;
3949 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
3950
3951 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
3952
3953 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3954 I915_READ(ILK_DISPLAY_CHICKEN2) |
3955 ILK_ELPIN_409_SELECT);
3956
3957 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
3958 I915_WRITE(_3D_CHICKEN,
3959 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
3960
3961 /* WaSetupGtModeTdRowDispatch:snb */
3962 if (IS_SNB_GT1(dev))
3963 I915_WRITE(GEN6_GT_MODE,
3964 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
3965
3966 I915_WRITE(WM3_LP_ILK, 0);
3967 I915_WRITE(WM2_LP_ILK, 0);
3968 I915_WRITE(WM1_LP_ILK, 0);
3969
3970 I915_WRITE(CACHE_MODE_0,
3971 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
3972
3973 I915_WRITE(GEN6_UCGCTL1,
3974 I915_READ(GEN6_UCGCTL1) |
3975 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
3976 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
3977
3978 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
3979 * gating disable must be set. Failure to set it results in
3980 * flickering pixels due to Z write ordering failures after
3981 * some amount of runtime in the Mesa "fire" demo, and Unigine
3982 * Sanctuary and Tropics, and apparently anything else with
3983 * alpha test or pixel discard.
3984 *
3985 * According to the spec, bit 11 (RCCUNIT) must also be set,
3986 * but we didn't debug actual testcases to find it out.
3987 *
3988 * Also apply WaDisableVDSUnitClockGating:snb and
3989 * WaDisableRCPBUnitClockGating:snb.
3990 */
3991 I915_WRITE(GEN6_UCGCTL2,
3992 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
3993 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
3994 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
3995
3996 /* Bspec says we need to always set all mask bits. */
3997 I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) |
3998 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL);
3999
4000 /*
4001 * According to the spec the following bits should be
4002 * set in order to enable memory self-refresh and fbc:
4003 * The bit21 and bit22 of 0x42000
4004 * The bit21 and bit22 of 0x42004
4005 * The bit5 and bit7 of 0x42020
4006 * The bit14 of 0x70180
4007 * The bit14 of 0x71180
4008 */
4009 I915_WRITE(ILK_DISPLAY_CHICKEN1,
4010 I915_READ(ILK_DISPLAY_CHICKEN1) |
4011 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
4012 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4013 I915_READ(ILK_DISPLAY_CHICKEN2) |
4014 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
4015 I915_WRITE(ILK_DSPCLK_GATE_D,
4016 I915_READ(ILK_DSPCLK_GATE_D) |
4017 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
4018 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
4019
4020 /* WaMbcDriverBootEnable:snb */
4021 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4022 GEN6_MBCTL_ENABLE_BOOT_FETCH);
4023
4024 for_each_pipe(pipe) {
4025 I915_WRITE(DSPCNTR(pipe),
4026 I915_READ(DSPCNTR(pipe)) |
4027 DISPPLANE_TRICKLE_FEED_DISABLE);
4028 intel_flush_display_plane(dev_priv, pipe);
4029 }
4030
4031 /* The default value should be 0x200 according to docs, but the two
4032 * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
4033 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff));
4034 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
4035
4036 cpt_init_clock_gating(dev);
4037
4038 gen6_check_mch_setup(dev);
4039 }
4040
4041 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
4042 {
4043 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
4044
4045 reg &= ~GEN7_FF_SCHED_MASK;
4046 reg |= GEN7_FF_TS_SCHED_HW;
4047 reg |= GEN7_FF_VS_SCHED_HW;
4048 reg |= GEN7_FF_DS_SCHED_HW;
4049
4050 if (IS_HASWELL(dev_priv->dev))
4051 reg &= ~GEN7_FF_VS_REF_CNT_FFME;
4052
4053 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
4054 }
4055
4056 static void lpt_init_clock_gating(struct drm_device *dev)
4057 {
4058 struct drm_i915_private *dev_priv = dev->dev_private;
4059
4060 /*
4061 * TODO: this bit should only be enabled when really needed, then
4062 * disabled when not needed anymore in order to save power.
4063 */
4064 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
4065 I915_WRITE(SOUTH_DSPCLK_GATE_D,
4066 I915_READ(SOUTH_DSPCLK_GATE_D) |
4067 PCH_LP_PARTITION_LEVEL_DISABLE);
4068 }
4069
4070 static void lpt_suspend_hw(struct drm_device *dev)
4071 {
4072 struct drm_i915_private *dev_priv = dev->dev_private;
4073
4074 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
4075 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
4076
4077 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
4078 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
4079 }
4080 }
4081
4082 static void haswell_init_clock_gating(struct drm_device *dev)
4083 {
4084 struct drm_i915_private *dev_priv = dev->dev_private;
4085 int pipe;
4086
4087 I915_WRITE(WM3_LP_ILK, 0);
4088 I915_WRITE(WM2_LP_ILK, 0);
4089 I915_WRITE(WM1_LP_ILK, 0);
4090
4091 /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
4092 * This implements the WaDisableRCZUnitClockGating:hsw workaround.
4093 */
4094 I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
4095
4096 /* Apply the WaDisableRHWOOptimizationForRenderHang:hsw workaround. */
4097 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4098 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4099
4100 /* WaApplyL3ControlAndL3ChickenMode:hsw */
4101 I915_WRITE(GEN7_L3CNTLREG1,
4102 GEN7_WA_FOR_GEN7_L3_CONTROL);
4103 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
4104 GEN7_WA_L3_CHICKEN_MODE);
4105
4106 /* This is required by WaCatErrorRejectionIssue:hsw */
4107 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4108 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4109 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4110
4111 for_each_pipe(pipe) {
4112 I915_WRITE(DSPCNTR(pipe),
4113 I915_READ(DSPCNTR(pipe)) |
4114 DISPPLANE_TRICKLE_FEED_DISABLE);
4115 intel_flush_display_plane(dev_priv, pipe);
4116 }
4117
4118 /* WaVSRefCountFullforceMissDisable:hsw */
4119 gen7_setup_fixed_func_scheduler(dev_priv);
4120
4121 /* WaDisable4x2SubspanOptimization:hsw */
4122 I915_WRITE(CACHE_MODE_1,
4123 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
4124
4125 /* WaMbcDriverBootEnable:hsw */
4126 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4127 GEN6_MBCTL_ENABLE_BOOT_FETCH);
4128
4129 /* WaSwitchSolVfFArbitrationPriority:hsw */
4130 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
4131
4132 /* XXX: This is a workaround for early silicon revisions and should be
4133 * removed later.
4134 */
4135 I915_WRITE(WM_DBG,
4136 I915_READ(WM_DBG) |
4137 WM_DBG_DISALLOW_MULTIPLE_LP |
4138 WM_DBG_DISALLOW_SPRITE |
4139 WM_DBG_DISALLOW_MAXFIFO);
4140
4141 lpt_init_clock_gating(dev);
4142 }
4143
4144 static void ivybridge_init_clock_gating(struct drm_device *dev)
4145 {
4146 struct drm_i915_private *dev_priv = dev->dev_private;
4147 int pipe;
4148 uint32_t snpcr;
4149
4150 I915_WRITE(WM3_LP_ILK, 0);
4151 I915_WRITE(WM2_LP_ILK, 0);
4152 I915_WRITE(WM1_LP_ILK, 0);
4153
4154 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
4155
4156 /* WaDisableEarlyCull:ivb */
4157 I915_WRITE(_3D_CHICKEN3,
4158 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
4159
4160 /* WaDisableBackToBackFlipFix:ivb */
4161 I915_WRITE(IVB_CHICKEN3,
4162 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
4163 CHICKEN3_DGMG_DONE_FIX_DISABLE);
4164
4165 /* WaDisablePSDDualDispatchEnable:ivb */
4166 if (IS_IVB_GT1(dev))
4167 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
4168 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
4169 else
4170 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
4171 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
4172
4173 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
4174 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4175 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4176
4177 /* WaApplyL3ControlAndL3ChickenMode:ivb */
4178 I915_WRITE(GEN7_L3CNTLREG1,
4179 GEN7_WA_FOR_GEN7_L3_CONTROL);
4180 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
4181 GEN7_WA_L3_CHICKEN_MODE);
4182 if (IS_IVB_GT1(dev))
4183 I915_WRITE(GEN7_ROW_CHICKEN2,
4184 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4185 else
4186 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
4187 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4188
4189
4190 /* WaForceL3Serialization:ivb */
4191 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
4192 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
4193
4194 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4195 * gating disable must be set. Failure to set it results in
4196 * flickering pixels due to Z write ordering failures after
4197 * some amount of runtime in the Mesa "fire" demo, and Unigine
4198 * Sanctuary and Tropics, and apparently anything else with
4199 * alpha test or pixel discard.
4200 *
4201 * According to the spec, bit 11 (RCCUNIT) must also be set,
4202 * but we didn't debug actual testcases to find it out.
4203 *
4204 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
4205 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
4206 */
4207 I915_WRITE(GEN6_UCGCTL2,
4208 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
4209 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4210
4211 /* This is required by WaCatErrorRejectionIssue:ivb */
4212 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4213 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4214 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4215
4216 for_each_pipe(pipe) {
4217 I915_WRITE(DSPCNTR(pipe),
4218 I915_READ(DSPCNTR(pipe)) |
4219 DISPPLANE_TRICKLE_FEED_DISABLE);
4220 intel_flush_display_plane(dev_priv, pipe);
4221 }
4222
4223 /* WaMbcDriverBootEnable:ivb */
4224 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4225 GEN6_MBCTL_ENABLE_BOOT_FETCH);
4226
4227 /* WaVSRefCountFullforceMissDisable:ivb */
4228 gen7_setup_fixed_func_scheduler(dev_priv);
4229
4230 /* WaDisable4x2SubspanOptimization:ivb */
4231 I915_WRITE(CACHE_MODE_1,
4232 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
4233
4234 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4235 snpcr &= ~GEN6_MBC_SNPCR_MASK;
4236 snpcr |= GEN6_MBC_SNPCR_MED;
4237 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
4238
4239 if (!HAS_PCH_NOP(dev))
4240 cpt_init_clock_gating(dev);
4241
4242 gen6_check_mch_setup(dev);
4243 }
4244
4245 static void valleyview_init_clock_gating(struct drm_device *dev)
4246 {
4247 struct drm_i915_private *dev_priv = dev->dev_private;
4248 int pipe;
4249
4250 I915_WRITE(WM3_LP_ILK, 0);
4251 I915_WRITE(WM2_LP_ILK, 0);
4252 I915_WRITE(WM1_LP_ILK, 0);
4253
4254 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
4255
4256 /* WaDisableEarlyCull:vlv */
4257 I915_WRITE(_3D_CHICKEN3,
4258 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
4259
4260 /* WaDisableBackToBackFlipFix:vlv */
4261 I915_WRITE(IVB_CHICKEN3,
4262 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
4263 CHICKEN3_DGMG_DONE_FIX_DISABLE);
4264
4265 /* WaDisablePSDDualDispatchEnable:vlv */
4266 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
4267 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
4268 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
4269
4270 /* Apply the WaDisableRHWOOptimizationForRenderHang:vlv workaround. */
4271 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4272 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4273
4274 /* WaApplyL3ControlAndL3ChickenMode:vlv */
4275 I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
4276 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
4277
4278 /* WaForceL3Serialization:vlv */
4279 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
4280 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
4281
4282 /* WaDisableDopClockGating:vlv */
4283 I915_WRITE(GEN7_ROW_CHICKEN2,
4284 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4285
4286 /* WaForceL3Serialization:vlv */
4287 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
4288 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
4289
4290 /* This is required by WaCatErrorRejectionIssue:vlv */
4291 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4292 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4293 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4294
4295 /* WaMbcDriverBootEnable:vlv */
4296 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4297 GEN6_MBCTL_ENABLE_BOOT_FETCH);
4298
4299
4300 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4301 * gating disable must be set. Failure to set it results in
4302 * flickering pixels due to Z write ordering failures after
4303 * some amount of runtime in the Mesa "fire" demo, and Unigine
4304 * Sanctuary and Tropics, and apparently anything else with
4305 * alpha test or pixel discard.
4306 *
4307 * According to the spec, bit 11 (RCCUNIT) must also be set,
4308 * but we didn't debug actual testcases to find it out.
4309 *
4310 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
4311 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
4312 *
4313 * Also apply WaDisableVDSUnitClockGating:vlv and
4314 * WaDisableRCPBUnitClockGating:vlv.
4315 */
4316 I915_WRITE(GEN6_UCGCTL2,
4317 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
4318 GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
4319 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
4320 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
4321 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4322
4323 I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
4324
4325 for_each_pipe(pipe) {
4326 I915_WRITE(DSPCNTR(pipe),
4327 I915_READ(DSPCNTR(pipe)) |
4328 DISPPLANE_TRICKLE_FEED_DISABLE);
4329 intel_flush_display_plane(dev_priv, pipe);
4330 }
4331
4332 I915_WRITE(CACHE_MODE_1,
4333 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
4334
4335 /*
4336 * WaDisableVLVClockGating_VBIIssue:vlv
4337 * Disable clock gating on th GCFG unit to prevent a delay
4338 * in the reporting of vblank events.
4339 */
4340 I915_WRITE(VLV_GUNIT_CLOCK_GATE, 0xffffffff);
4341
4342 /* Conservative clock gating settings for now */
4343 I915_WRITE(0x9400, 0xffffffff);
4344 I915_WRITE(0x9404, 0xffffffff);
4345 I915_WRITE(0x9408, 0xffffffff);
4346 I915_WRITE(0x940c, 0xffffffff);
4347 I915_WRITE(0x9410, 0xffffffff);
4348 I915_WRITE(0x9414, 0xffffffff);
4349 I915_WRITE(0x9418, 0xffffffff);
4350 }
4351
4352 static void g4x_init_clock_gating(struct drm_device *dev)
4353 {
4354 struct drm_i915_private *dev_priv = dev->dev_private;
4355 uint32_t dspclk_gate;
4356
4357 I915_WRITE(RENCLK_GATE_D1, 0);
4358 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
4359 GS_UNIT_CLOCK_GATE_DISABLE |
4360 CL_UNIT_CLOCK_GATE_DISABLE);
4361 I915_WRITE(RAMCLK_GATE_D, 0);
4362 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
4363 OVRUNIT_CLOCK_GATE_DISABLE |
4364 OVCUNIT_CLOCK_GATE_DISABLE;
4365 if (IS_GM45(dev))
4366 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
4367 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4368
4369 /* WaDisableRenderCachePipelinedFlush */
4370 I915_WRITE(CACHE_MODE_0,
4371 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
4372 }
4373
4374 static void crestline_init_clock_gating(struct drm_device *dev)
4375 {
4376 struct drm_i915_private *dev_priv = dev->dev_private;
4377
4378 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
4379 I915_WRITE(RENCLK_GATE_D2, 0);
4380 I915_WRITE(DSPCLK_GATE_D, 0);
4381 I915_WRITE(RAMCLK_GATE_D, 0);
4382 I915_WRITE16(DEUC, 0);
4383 }
4384
4385 static void broadwater_init_clock_gating(struct drm_device *dev)
4386 {
4387 struct drm_i915_private *dev_priv = dev->dev_private;
4388
4389 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
4390 I965_RCC_CLOCK_GATE_DISABLE |
4391 I965_RCPB_CLOCK_GATE_DISABLE |
4392 I965_ISC_CLOCK_GATE_DISABLE |
4393 I965_FBC_CLOCK_GATE_DISABLE);
4394 I915_WRITE(RENCLK_GATE_D2, 0);
4395 }
4396
4397 static void gen3_init_clock_gating(struct drm_device *dev)
4398 {
4399 struct drm_i915_private *dev_priv = dev->dev_private;
4400 u32 dstate = I915_READ(D_STATE);
4401
4402 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
4403 DSTATE_DOT_CLOCK_GATING;
4404 I915_WRITE(D_STATE, dstate);
4405
4406 if (IS_PINEVIEW(dev))
4407 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
4408
4409 /* IIR "flip pending" means done if this bit is set */
4410 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
4411 }
4412
4413 static void i85x_init_clock_gating(struct drm_device *dev)
4414 {
4415 struct drm_i915_private *dev_priv = dev->dev_private;
4416
4417 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
4418 }
4419
4420 static void i830_init_clock_gating(struct drm_device *dev)
4421 {
4422 struct drm_i915_private *dev_priv = dev->dev_private;
4423
4424 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
4425 }
4426
4427 void intel_init_clock_gating(struct drm_device *dev)
4428 {
4429 struct drm_i915_private *dev_priv = dev->dev_private;
4430
4431 dev_priv->display.init_clock_gating(dev);
4432 }
4433
4434 void intel_suspend_hw(struct drm_device *dev)
4435 {
4436 if (HAS_PCH_LPT(dev))
4437 lpt_suspend_hw(dev);
4438 }
4439
4440 /**
4441 * We should only use the power well if we explicitly asked the hardware to
4442 * enable it, so check if it's enabled and also check if we've requested it to
4443 * be enabled.
4444 */
4445 bool intel_display_power_enabled(struct drm_device *dev,
4446 enum intel_display_power_domain domain)
4447 {
4448 struct drm_i915_private *dev_priv = dev->dev_private;
4449
4450 if (!HAS_POWER_WELL(dev))
4451 return true;
4452
4453 switch (domain) {
4454 case POWER_DOMAIN_PIPE_A:
4455 case POWER_DOMAIN_TRANSCODER_EDP:
4456 return true;
4457 case POWER_DOMAIN_PIPE_B:
4458 case POWER_DOMAIN_PIPE_C:
4459 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
4460 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
4461 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
4462 case POWER_DOMAIN_TRANSCODER_A:
4463 case POWER_DOMAIN_TRANSCODER_B:
4464 case POWER_DOMAIN_TRANSCODER_C:
4465 return I915_READ(HSW_PWR_WELL_DRIVER) ==
4466 (HSW_PWR_WELL_ENABLE | HSW_PWR_WELL_STATE);
4467 default:
4468 BUG();
4469 }
4470 }
4471
4472 void intel_set_power_well(struct drm_device *dev, bool enable)
4473 {
4474 struct drm_i915_private *dev_priv = dev->dev_private;
4475 bool is_enabled, enable_requested;
4476 uint32_t tmp;
4477
4478 if (!HAS_POWER_WELL(dev))
4479 return;
4480
4481 if (!i915_disable_power_well && !enable)
4482 return;
4483
4484 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
4485 is_enabled = tmp & HSW_PWR_WELL_STATE;
4486 enable_requested = tmp & HSW_PWR_WELL_ENABLE;
4487
4488 if (enable) {
4489 if (!enable_requested)
4490 I915_WRITE(HSW_PWR_WELL_DRIVER, HSW_PWR_WELL_ENABLE);
4491
4492 if (!is_enabled) {
4493 DRM_DEBUG_KMS("Enabling power well\n");
4494 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
4495 HSW_PWR_WELL_STATE), 20))
4496 DRM_ERROR("Timeout enabling power well\n");
4497 }
4498 } else {
4499 if (enable_requested) {
4500 I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
4501 DRM_DEBUG_KMS("Requesting to disable the power well\n");
4502 }
4503 }
4504 }
4505
4506 /*
4507 * Starting with Haswell, we have a "Power Down Well" that can be turned off
4508 * when not needed anymore. We have 4 registers that can request the power well
4509 * to be enabled, and it will only be disabled if none of the registers is
4510 * requesting it to be enabled.
4511 */
4512 void intel_init_power_well(struct drm_device *dev)
4513 {
4514 struct drm_i915_private *dev_priv = dev->dev_private;
4515
4516 if (!HAS_POWER_WELL(dev))
4517 return;
4518
4519 /* For now, we need the power well to be always enabled. */
4520 intel_set_power_well(dev, true);
4521
4522 /* We're taking over the BIOS, so clear any requests made by it since
4523 * the driver is in charge now. */
4524 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE)
4525 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
4526 }
4527
4528 /* Set up chip specific power management-related functions */
4529 void intel_init_pm(struct drm_device *dev)
4530 {
4531 struct drm_i915_private *dev_priv = dev->dev_private;
4532
4533 if (I915_HAS_FBC(dev)) {
4534 if (HAS_PCH_SPLIT(dev)) {
4535 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
4536 if (IS_IVYBRIDGE(dev))
4537 dev_priv->display.enable_fbc =
4538 gen7_enable_fbc;
4539 else
4540 dev_priv->display.enable_fbc =
4541 ironlake_enable_fbc;
4542 dev_priv->display.disable_fbc = ironlake_disable_fbc;
4543 } else if (IS_GM45(dev)) {
4544 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
4545 dev_priv->display.enable_fbc = g4x_enable_fbc;
4546 dev_priv->display.disable_fbc = g4x_disable_fbc;
4547 } else if (IS_CRESTLINE(dev)) {
4548 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
4549 dev_priv->display.enable_fbc = i8xx_enable_fbc;
4550 dev_priv->display.disable_fbc = i8xx_disable_fbc;
4551 }
4552 /* 855GM needs testing */
4553 }
4554
4555 /* For cxsr */
4556 if (IS_PINEVIEW(dev))
4557 i915_pineview_get_mem_freq(dev);
4558 else if (IS_GEN5(dev))
4559 i915_ironlake_get_mem_freq(dev);
4560
4561 /* For FIFO watermark updates */
4562 if (HAS_PCH_SPLIT(dev)) {
4563 if (IS_GEN5(dev)) {
4564 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
4565 dev_priv->display.update_wm = ironlake_update_wm;
4566 else {
4567 DRM_DEBUG_KMS("Failed to get proper latency. "
4568 "Disable CxSR\n");
4569 dev_priv->display.update_wm = NULL;
4570 }
4571 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
4572 } else if (IS_GEN6(dev)) {
4573 if (SNB_READ_WM0_LATENCY()) {
4574 dev_priv->display.update_wm = sandybridge_update_wm;
4575 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
4576 } else {
4577 DRM_DEBUG_KMS("Failed to read display plane latency. "
4578 "Disable CxSR\n");
4579 dev_priv->display.update_wm = NULL;
4580 }
4581 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
4582 } else if (IS_IVYBRIDGE(dev)) {
4583 if (SNB_READ_WM0_LATENCY()) {
4584 dev_priv->display.update_wm = ivybridge_update_wm;
4585 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
4586 } else {
4587 DRM_DEBUG_KMS("Failed to read display plane latency. "
4588 "Disable CxSR\n");
4589 dev_priv->display.update_wm = NULL;
4590 }
4591 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
4592 } else if (IS_HASWELL(dev)) {
4593 if (SNB_READ_WM0_LATENCY()) {
4594 dev_priv->display.update_wm = sandybridge_update_wm;
4595 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
4596 dev_priv->display.update_linetime_wm = haswell_update_linetime_wm;
4597 } else {
4598 DRM_DEBUG_KMS("Failed to read display plane latency. "
4599 "Disable CxSR\n");
4600 dev_priv->display.update_wm = NULL;
4601 }
4602 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
4603 } else
4604 dev_priv->display.update_wm = NULL;
4605 } else if (IS_VALLEYVIEW(dev)) {
4606 dev_priv->display.update_wm = valleyview_update_wm;
4607 dev_priv->display.init_clock_gating =
4608 valleyview_init_clock_gating;
4609 } else if (IS_PINEVIEW(dev)) {
4610 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
4611 dev_priv->is_ddr3,
4612 dev_priv->fsb_freq,
4613 dev_priv->mem_freq)) {
4614 DRM_INFO("failed to find known CxSR latency "
4615 "(found ddr%s fsb freq %d, mem freq %d), "
4616 "disabling CxSR\n",
4617 (dev_priv->is_ddr3 == 1) ? "3" : "2",
4618 dev_priv->fsb_freq, dev_priv->mem_freq);
4619 /* Disable CxSR and never update its watermark again */
4620 pineview_disable_cxsr(dev);
4621 dev_priv->display.update_wm = NULL;
4622 } else
4623 dev_priv->display.update_wm = pineview_update_wm;
4624 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
4625 } else if (IS_G4X(dev)) {
4626 dev_priv->display.update_wm = g4x_update_wm;
4627 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
4628 } else if (IS_GEN4(dev)) {
4629 dev_priv->display.update_wm = i965_update_wm;
4630 if (IS_CRESTLINE(dev))
4631 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
4632 else if (IS_BROADWATER(dev))
4633 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
4634 } else if (IS_GEN3(dev)) {
4635 dev_priv->display.update_wm = i9xx_update_wm;
4636 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
4637 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
4638 } else if (IS_I865G(dev)) {
4639 dev_priv->display.update_wm = i830_update_wm;
4640 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
4641 dev_priv->display.get_fifo_size = i830_get_fifo_size;
4642 } else if (IS_I85X(dev)) {
4643 dev_priv->display.update_wm = i9xx_update_wm;
4644 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
4645 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
4646 } else {
4647 dev_priv->display.update_wm = i830_update_wm;
4648 dev_priv->display.init_clock_gating = i830_init_clock_gating;
4649 if (IS_845G(dev))
4650 dev_priv->display.get_fifo_size = i845_get_fifo_size;
4651 else
4652 dev_priv->display.get_fifo_size = i830_get_fifo_size;
4653 }
4654 }
4655
4656 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
4657 {
4658 u32 gt_thread_status_mask;
4659
4660 if (IS_HASWELL(dev_priv->dev))
4661 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK_HSW;
4662 else
4663 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK;
4664
4665 /* w/a for a sporadic read returning 0 by waiting for the GT
4666 * thread to wake up.
4667 */
4668 if (wait_for_atomic_us((I915_READ_NOTRACE(GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_mask) == 0, 500))
4669 DRM_ERROR("GT thread status wait timed out\n");
4670 }
4671
4672 static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv)
4673 {
4674 I915_WRITE_NOTRACE(FORCEWAKE, 0);
4675 POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
4676 }
4677
4678 static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
4679 {
4680 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0,
4681 FORCEWAKE_ACK_TIMEOUT_MS))
4682 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
4683
4684 I915_WRITE_NOTRACE(FORCEWAKE, 1);
4685 POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
4686
4687 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK) & 1),
4688 FORCEWAKE_ACK_TIMEOUT_MS))
4689 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
4690
4691 /* WaRsForcewakeWaitTC0:snb */
4692 __gen6_gt_wait_for_thread_c0(dev_priv);
4693 }
4694
4695 static void __gen6_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv)
4696 {
4697 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff));
4698 /* something from same cacheline, but !FORCEWAKE_MT */
4699 POSTING_READ(ECOBUS);
4700 }
4701
4702 static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
4703 {
4704 u32 forcewake_ack;
4705
4706 if (IS_HASWELL(dev_priv->dev))
4707 forcewake_ack = FORCEWAKE_ACK_HSW;
4708 else
4709 forcewake_ack = FORCEWAKE_MT_ACK;
4710
4711 if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & FORCEWAKE_KERNEL) == 0,
4712 FORCEWAKE_ACK_TIMEOUT_MS))
4713 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
4714
4715 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
4716 /* something from same cacheline, but !FORCEWAKE_MT */
4717 POSTING_READ(ECOBUS);
4718
4719 if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & FORCEWAKE_KERNEL),
4720 FORCEWAKE_ACK_TIMEOUT_MS))
4721 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
4722
4723 /* WaRsForcewakeWaitTC0:ivb,hsw */
4724 __gen6_gt_wait_for_thread_c0(dev_priv);
4725 }
4726
4727 /*
4728 * Generally this is called implicitly by the register read function. However,
4729 * if some sequence requires the GT to not power down then this function should
4730 * be called at the beginning of the sequence followed by a call to
4731 * gen6_gt_force_wake_put() at the end of the sequence.
4732 */
4733 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
4734 {
4735 unsigned long irqflags;
4736
4737 spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
4738 if (dev_priv->forcewake_count++ == 0)
4739 dev_priv->gt.force_wake_get(dev_priv);
4740 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
4741 }
4742
4743 void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
4744 {
4745 u32 gtfifodbg;
4746 gtfifodbg = I915_READ_NOTRACE(GTFIFODBG);
4747 if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK,
4748 "MMIO read or write has been dropped %x\n", gtfifodbg))
4749 I915_WRITE_NOTRACE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK);
4750 }
4751
4752 static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
4753 {
4754 I915_WRITE_NOTRACE(FORCEWAKE, 0);
4755 /* something from same cacheline, but !FORCEWAKE */
4756 POSTING_READ(ECOBUS);
4757 gen6_gt_check_fifodbg(dev_priv);
4758 }
4759
4760 static void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
4761 {
4762 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
4763 /* something from same cacheline, but !FORCEWAKE_MT */
4764 POSTING_READ(ECOBUS);
4765 gen6_gt_check_fifodbg(dev_priv);
4766 }
4767
4768 /*
4769 * see gen6_gt_force_wake_get()
4770 */
4771 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
4772 {
4773 unsigned long irqflags;
4774
4775 spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
4776 if (--dev_priv->forcewake_count == 0)
4777 dev_priv->gt.force_wake_put(dev_priv);
4778 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
4779 }
4780
4781 int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
4782 {
4783 int ret = 0;
4784
4785 if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
4786 int loop = 500;
4787 u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
4788 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
4789 udelay(10);
4790 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
4791 }
4792 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
4793 ++ret;
4794 dev_priv->gt_fifo_count = fifo;
4795 }
4796 dev_priv->gt_fifo_count--;
4797
4798 return ret;
4799 }
4800
4801 static void vlv_force_wake_reset(struct drm_i915_private *dev_priv)
4802 {
4803 I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(0xffff));
4804 /* something from same cacheline, but !FORCEWAKE_VLV */
4805 POSTING_READ(FORCEWAKE_ACK_VLV);
4806 }
4807
4808 static void vlv_force_wake_get(struct drm_i915_private *dev_priv)
4809 {
4810 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & FORCEWAKE_KERNEL) == 0,
4811 FORCEWAKE_ACK_TIMEOUT_MS))
4812 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
4813
4814 I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
4815 I915_WRITE_NOTRACE(FORCEWAKE_MEDIA_VLV,
4816 _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
4817
4818 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & FORCEWAKE_KERNEL),
4819 FORCEWAKE_ACK_TIMEOUT_MS))
4820 DRM_ERROR("Timed out waiting for GT to ack forcewake request.\n");
4821
4822 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_MEDIA_VLV) &
4823 FORCEWAKE_KERNEL),
4824 FORCEWAKE_ACK_TIMEOUT_MS))
4825 DRM_ERROR("Timed out waiting for media to ack forcewake request.\n");
4826
4827 /* WaRsForcewakeWaitTC0:vlv */
4828 __gen6_gt_wait_for_thread_c0(dev_priv);
4829 }
4830
4831 static void vlv_force_wake_put(struct drm_i915_private *dev_priv)
4832 {
4833 I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
4834 I915_WRITE_NOTRACE(FORCEWAKE_MEDIA_VLV,
4835 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
4836 /* The below doubles as a POSTING_READ */
4837 gen6_gt_check_fifodbg(dev_priv);
4838 }
4839
4840 void intel_gt_reset(struct drm_device *dev)
4841 {
4842 struct drm_i915_private *dev_priv = dev->dev_private;
4843
4844 if (IS_VALLEYVIEW(dev)) {
4845 vlv_force_wake_reset(dev_priv);
4846 } else if (INTEL_INFO(dev)->gen >= 6) {
4847 __gen6_gt_force_wake_reset(dev_priv);
4848 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4849 __gen6_gt_force_wake_mt_reset(dev_priv);
4850 }
4851 }
4852
4853 void intel_gt_init(struct drm_device *dev)
4854 {
4855 struct drm_i915_private *dev_priv = dev->dev_private;
4856
4857 spin_lock_init(&dev_priv->gt_lock);
4858
4859 intel_gt_reset(dev);
4860
4861 if (IS_VALLEYVIEW(dev)) {
4862 dev_priv->gt.force_wake_get = vlv_force_wake_get;
4863 dev_priv->gt.force_wake_put = vlv_force_wake_put;
4864 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
4865 dev_priv->gt.force_wake_get = __gen6_gt_force_wake_mt_get;
4866 dev_priv->gt.force_wake_put = __gen6_gt_force_wake_mt_put;
4867 } else if (IS_GEN6(dev)) {
4868 dev_priv->gt.force_wake_get = __gen6_gt_force_wake_get;
4869 dev_priv->gt.force_wake_put = __gen6_gt_force_wake_put;
4870 }
4871 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
4872 intel_gen6_powersave_work);
4873 }
4874
4875 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
4876 {
4877 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4878
4879 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
4880 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
4881 return -EAGAIN;
4882 }
4883
4884 I915_WRITE(GEN6_PCODE_DATA, *val);
4885 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
4886
4887 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
4888 500)) {
4889 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
4890 return -ETIMEDOUT;
4891 }
4892
4893 *val = I915_READ(GEN6_PCODE_DATA);
4894 I915_WRITE(GEN6_PCODE_DATA, 0);
4895
4896 return 0;
4897 }
4898
4899 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
4900 {
4901 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4902
4903 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
4904 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
4905 return -EAGAIN;
4906 }
4907
4908 I915_WRITE(GEN6_PCODE_DATA, val);
4909 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
4910
4911 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
4912 500)) {
4913 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
4914 return -ETIMEDOUT;
4915 }
4916
4917 I915_WRITE(GEN6_PCODE_DATA, 0);
4918
4919 return 0;
4920 }
4921
4922 static int vlv_punit_rw(struct drm_i915_private *dev_priv, u32 port, u8 opcode,
4923 u8 addr, u32 *val)
4924 {
4925 u32 cmd, devfn, be, bar;
4926
4927 bar = 0;
4928 be = 0xf;
4929 devfn = PCI_DEVFN(2, 0);
4930
4931 cmd = (devfn << IOSF_DEVFN_SHIFT) | (opcode << IOSF_OPCODE_SHIFT) |
4932 (port << IOSF_PORT_SHIFT) | (be << IOSF_BYTE_ENABLES_SHIFT) |
4933 (bar << IOSF_BAR_SHIFT);
4934
4935 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4936
4937 if (I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) {
4938 DRM_DEBUG_DRIVER("warning: pcode (%s) mailbox access failed\n",
4939 opcode == PUNIT_OPCODE_REG_READ ?
4940 "read" : "write");
4941 return -EAGAIN;
4942 }
4943
4944 I915_WRITE(VLV_IOSF_ADDR, addr);
4945 if (opcode == PUNIT_OPCODE_REG_WRITE)
4946 I915_WRITE(VLV_IOSF_DATA, *val);
4947 I915_WRITE(VLV_IOSF_DOORBELL_REQ, cmd);
4948
4949 if (wait_for((I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) == 0,
4950 5)) {
4951 DRM_ERROR("timeout waiting for pcode %s (%d) to finish\n",
4952 opcode == PUNIT_OPCODE_REG_READ ? "read" : "write",
4953 addr);
4954 return -ETIMEDOUT;
4955 }
4956
4957 if (opcode == PUNIT_OPCODE_REG_READ)
4958 *val = I915_READ(VLV_IOSF_DATA);
4959 I915_WRITE(VLV_IOSF_DATA, 0);
4960
4961 return 0;
4962 }
4963
4964 int valleyview_punit_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val)
4965 {
4966 return vlv_punit_rw(dev_priv, IOSF_PORT_PUNIT, PUNIT_OPCODE_REG_READ,
4967 addr, val);
4968 }
4969
4970 int valleyview_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val)
4971 {
4972 return vlv_punit_rw(dev_priv, IOSF_PORT_PUNIT, PUNIT_OPCODE_REG_WRITE,
4973 addr, &val);
4974 }
4975
4976 int valleyview_nc_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val)
4977 {
4978 return vlv_punit_rw(dev_priv, IOSF_PORT_NC, PUNIT_OPCODE_REG_READ,
4979 addr, val);
4980 }
4981
4982 int vlv_gpu_freq(int ddr_freq, int val)
4983 {
4984 int mult, base;
4985
4986 switch (ddr_freq) {
4987 case 800:
4988 mult = 20;
4989 base = 120;
4990 break;
4991 case 1066:
4992 mult = 22;
4993 base = 133;
4994 break;
4995 case 1333:
4996 mult = 21;
4997 base = 125;
4998 break;
4999 default:
5000 return -1;
5001 }
5002
5003 return ((val - 0xbd) * mult) + base;
5004 }
5005
5006 int vlv_freq_opcode(int ddr_freq, int val)
5007 {
5008 int mult, base;
5009
5010 switch (ddr_freq) {
5011 case 800:
5012 mult = 20;
5013 base = 120;
5014 break;
5015 case 1066:
5016 mult = 22;
5017 base = 133;
5018 break;
5019 case 1333:
5020 mult = 21;
5021 base = 125;
5022 break;
5023 default:
5024 return -1;
5025 }
5026
5027 val /= mult;
5028 val -= base / mult;
5029 val += 0xbd;
5030
5031 if (val > 0xea)
5032 val = 0xea;
5033
5034 return val;
5035 }
5036
Linux kernel - Deliverables
This page took 0.130723 seconds and 4 git commands to generate.