2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
28 #include <linux/cpufreq.h>
30 #include "intel_drv.h"
31 #include "../../../platform/x86/intel_ips.h"
32 #include <linux/module.h>
33 #include <drm/i915_powerwell.h>
35 #define FORCEWAKE_ACK_TIMEOUT_MS 2
37 /* FBC, or Frame Buffer Compression, is a technique employed to compress the
38 * framebuffer contents in-memory, aiming at reducing the required bandwidth
39 * during in-memory transfers and, therefore, reduce the power packet.
41 * The benefits of FBC are mostly visible with solid backgrounds and
42 * variation-less patterns.
44 * FBC-related functionality can be enabled by the means of the
45 * i915.i915_enable_fbc parameter
48 static bool intel_crtc_active(struct drm_crtc
*crtc
)
50 /* Be paranoid as we can arrive here with only partial
51 * state retrieved from the hardware during setup.
53 return to_intel_crtc(crtc
)->active
&& crtc
->fb
&& crtc
->mode
.clock
;
56 static void i8xx_disable_fbc(struct drm_device
*dev
)
58 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
61 /* Disable compression */
62 fbc_ctl
= I915_READ(FBC_CONTROL
);
63 if ((fbc_ctl
& FBC_CTL_EN
) == 0)
66 fbc_ctl
&= ~FBC_CTL_EN
;
67 I915_WRITE(FBC_CONTROL
, fbc_ctl
);
69 /* Wait for compressing bit to clear */
70 if (wait_for((I915_READ(FBC_STATUS
) & FBC_STAT_COMPRESSING
) == 0, 10)) {
71 DRM_DEBUG_KMS("FBC idle timed out\n");
75 DRM_DEBUG_KMS("disabled FBC\n");
78 static void i8xx_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
80 struct drm_device
*dev
= crtc
->dev
;
81 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
82 struct drm_framebuffer
*fb
= crtc
->fb
;
83 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
84 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
85 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
88 u32 fbc_ctl
, fbc_ctl2
;
90 cfb_pitch
= dev_priv
->fbc
.size
/ FBC_LL_SIZE
;
91 if (fb
->pitches
[0] < cfb_pitch
)
92 cfb_pitch
= fb
->pitches
[0];
94 /* FBC_CTL wants 64B units */
95 cfb_pitch
= (cfb_pitch
/ 64) - 1;
96 plane
= intel_crtc
->plane
== 0 ? FBC_CTL_PLANEA
: FBC_CTL_PLANEB
;
99 for (i
= 0; i
< (FBC_LL_SIZE
/ 32) + 1; i
++)
100 I915_WRITE(FBC_TAG
+ (i
* 4), 0);
103 fbc_ctl2
= FBC_CTL_FENCE_DBL
| FBC_CTL_IDLE_IMM
| FBC_CTL_CPU_FENCE
;
105 I915_WRITE(FBC_CONTROL2
, fbc_ctl2
);
106 I915_WRITE(FBC_FENCE_OFF
, crtc
->y
);
109 fbc_ctl
= FBC_CTL_EN
| FBC_CTL_PERIODIC
;
111 fbc_ctl
|= FBC_CTL_C3_IDLE
; /* 945 needs special SR handling */
112 fbc_ctl
|= (cfb_pitch
& 0xff) << FBC_CTL_STRIDE_SHIFT
;
113 fbc_ctl
|= (interval
& 0x2fff) << FBC_CTL_INTERVAL_SHIFT
;
114 fbc_ctl
|= obj
->fence_reg
;
115 I915_WRITE(FBC_CONTROL
, fbc_ctl
);
117 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c, ",
118 cfb_pitch
, crtc
->y
, plane_name(intel_crtc
->plane
));
121 static bool i8xx_fbc_enabled(struct drm_device
*dev
)
123 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
125 return I915_READ(FBC_CONTROL
) & FBC_CTL_EN
;
128 static void g4x_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
130 struct drm_device
*dev
= crtc
->dev
;
131 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
132 struct drm_framebuffer
*fb
= crtc
->fb
;
133 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
134 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
135 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
136 int plane
= intel_crtc
->plane
== 0 ? DPFC_CTL_PLANEA
: DPFC_CTL_PLANEB
;
137 unsigned long stall_watermark
= 200;
140 dpfc_ctl
= plane
| DPFC_SR_EN
| DPFC_CTL_LIMIT_1X
;
141 dpfc_ctl
|= DPFC_CTL_FENCE_EN
| obj
->fence_reg
;
142 I915_WRITE(DPFC_CHICKEN
, DPFC_HT_MODIFY
);
144 I915_WRITE(DPFC_RECOMP_CTL
, DPFC_RECOMP_STALL_EN
|
145 (stall_watermark
<< DPFC_RECOMP_STALL_WM_SHIFT
) |
146 (interval
<< DPFC_RECOMP_TIMER_COUNT_SHIFT
));
147 I915_WRITE(DPFC_FENCE_YOFF
, crtc
->y
);
150 I915_WRITE(DPFC_CONTROL
, I915_READ(DPFC_CONTROL
) | DPFC_CTL_EN
);
152 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc
->plane
));
155 static void g4x_disable_fbc(struct drm_device
*dev
)
157 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
160 /* Disable compression */
161 dpfc_ctl
= I915_READ(DPFC_CONTROL
);
162 if (dpfc_ctl
& DPFC_CTL_EN
) {
163 dpfc_ctl
&= ~DPFC_CTL_EN
;
164 I915_WRITE(DPFC_CONTROL
, dpfc_ctl
);
166 DRM_DEBUG_KMS("disabled FBC\n");
170 static bool g4x_fbc_enabled(struct drm_device
*dev
)
172 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
174 return I915_READ(DPFC_CONTROL
) & DPFC_CTL_EN
;
177 static void sandybridge_blit_fbc_update(struct drm_device
*dev
)
179 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
182 /* Make sure blitter notifies FBC of writes */
183 gen6_gt_force_wake_get(dev_priv
);
184 blt_ecoskpd
= I915_READ(GEN6_BLITTER_ECOSKPD
);
185 blt_ecoskpd
|= GEN6_BLITTER_FBC_NOTIFY
<<
186 GEN6_BLITTER_LOCK_SHIFT
;
187 I915_WRITE(GEN6_BLITTER_ECOSKPD
, blt_ecoskpd
);
188 blt_ecoskpd
|= GEN6_BLITTER_FBC_NOTIFY
;
189 I915_WRITE(GEN6_BLITTER_ECOSKPD
, blt_ecoskpd
);
190 blt_ecoskpd
&= ~(GEN6_BLITTER_FBC_NOTIFY
<<
191 GEN6_BLITTER_LOCK_SHIFT
);
192 I915_WRITE(GEN6_BLITTER_ECOSKPD
, blt_ecoskpd
);
193 POSTING_READ(GEN6_BLITTER_ECOSKPD
);
194 gen6_gt_force_wake_put(dev_priv
);
197 static void ironlake_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
199 struct drm_device
*dev
= crtc
->dev
;
200 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
201 struct drm_framebuffer
*fb
= crtc
->fb
;
202 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
203 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
204 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
205 int plane
= intel_crtc
->plane
== 0 ? DPFC_CTL_PLANEA
: DPFC_CTL_PLANEB
;
206 unsigned long stall_watermark
= 200;
209 dpfc_ctl
= I915_READ(ILK_DPFC_CONTROL
);
210 dpfc_ctl
&= DPFC_RESERVED
;
211 dpfc_ctl
|= (plane
| DPFC_CTL_LIMIT_1X
);
212 /* Set persistent mode for front-buffer rendering, ala X. */
213 dpfc_ctl
|= DPFC_CTL_PERSISTENT_MODE
;
214 dpfc_ctl
|= (DPFC_CTL_FENCE_EN
| obj
->fence_reg
);
215 I915_WRITE(ILK_DPFC_CHICKEN
, DPFC_HT_MODIFY
);
217 I915_WRITE(ILK_DPFC_RECOMP_CTL
, DPFC_RECOMP_STALL_EN
|
218 (stall_watermark
<< DPFC_RECOMP_STALL_WM_SHIFT
) |
219 (interval
<< DPFC_RECOMP_TIMER_COUNT_SHIFT
));
220 I915_WRITE(ILK_DPFC_FENCE_YOFF
, crtc
->y
);
221 I915_WRITE(ILK_FBC_RT_BASE
, obj
->gtt_offset
| ILK_FBC_RT_VALID
);
223 I915_WRITE(ILK_DPFC_CONTROL
, dpfc_ctl
| DPFC_CTL_EN
);
226 I915_WRITE(SNB_DPFC_CTL_SA
,
227 SNB_CPU_FENCE_ENABLE
| obj
->fence_reg
);
228 I915_WRITE(DPFC_CPU_FENCE_OFFSET
, crtc
->y
);
229 sandybridge_blit_fbc_update(dev
);
232 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc
->plane
));
235 static void ironlake_disable_fbc(struct drm_device
*dev
)
237 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
240 /* Disable compression */
241 dpfc_ctl
= I915_READ(ILK_DPFC_CONTROL
);
242 if (dpfc_ctl
& DPFC_CTL_EN
) {
243 dpfc_ctl
&= ~DPFC_CTL_EN
;
244 I915_WRITE(ILK_DPFC_CONTROL
, dpfc_ctl
);
246 if (IS_IVYBRIDGE(dev
))
247 /* WaFbcDisableDpfcClockGating:ivb */
248 I915_WRITE(ILK_DSPCLK_GATE_D
,
249 I915_READ(ILK_DSPCLK_GATE_D
) &
250 ~ILK_DPFCUNIT_CLOCK_GATE_DISABLE
);
253 /* WaFbcDisableDpfcClockGating:hsw */
254 I915_WRITE(HSW_CLKGATE_DISABLE_PART_1
,
255 I915_READ(HSW_CLKGATE_DISABLE_PART_1
) &
256 ~HSW_DPFC_GATING_DISABLE
);
258 DRM_DEBUG_KMS("disabled FBC\n");
262 static bool ironlake_fbc_enabled(struct drm_device
*dev
)
264 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
266 return I915_READ(ILK_DPFC_CONTROL
) & DPFC_CTL_EN
;
269 static void gen7_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
271 struct drm_device
*dev
= crtc
->dev
;
272 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
273 struct drm_framebuffer
*fb
= crtc
->fb
;
274 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
275 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
276 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
278 I915_WRITE(IVB_FBC_RT_BASE
, obj
->gtt_offset
);
280 I915_WRITE(ILK_DPFC_CONTROL
, DPFC_CTL_EN
| DPFC_CTL_LIMIT_1X
|
281 IVB_DPFC_CTL_FENCE_EN
|
282 intel_crtc
->plane
<< IVB_DPFC_CTL_PLANE_SHIFT
);
284 if (IS_IVYBRIDGE(dev
)) {
285 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
286 I915_WRITE(ILK_DISPLAY_CHICKEN1
, ILK_FBCQ_DIS
);
287 /* WaFbcDisableDpfcClockGating:ivb */
288 I915_WRITE(ILK_DSPCLK_GATE_D
,
289 I915_READ(ILK_DSPCLK_GATE_D
) |
290 ILK_DPFCUNIT_CLOCK_GATE_DISABLE
);
292 /* WaFbcAsynchFlipDisableFbcQueue:hsw */
293 I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc
->pipe
),
294 HSW_BYPASS_FBC_QUEUE
);
295 /* WaFbcDisableDpfcClockGating:hsw */
296 I915_WRITE(HSW_CLKGATE_DISABLE_PART_1
,
297 I915_READ(HSW_CLKGATE_DISABLE_PART_1
) |
298 HSW_DPFC_GATING_DISABLE
);
301 I915_WRITE(SNB_DPFC_CTL_SA
,
302 SNB_CPU_FENCE_ENABLE
| obj
->fence_reg
);
303 I915_WRITE(DPFC_CPU_FENCE_OFFSET
, crtc
->y
);
305 sandybridge_blit_fbc_update(dev
);
307 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc
->plane
);
310 bool intel_fbc_enabled(struct drm_device
*dev
)
312 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
314 if (!dev_priv
->display
.fbc_enabled
)
317 return dev_priv
->display
.fbc_enabled(dev
);
320 static void intel_fbc_work_fn(struct work_struct
*__work
)
322 struct intel_fbc_work
*work
=
323 container_of(to_delayed_work(__work
),
324 struct intel_fbc_work
, work
);
325 struct drm_device
*dev
= work
->crtc
->dev
;
326 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
328 mutex_lock(&dev
->struct_mutex
);
329 if (work
== dev_priv
->fbc
.fbc_work
) {
330 /* Double check that we haven't switched fb without cancelling
333 if (work
->crtc
->fb
== work
->fb
) {
334 dev_priv
->display
.enable_fbc(work
->crtc
,
337 dev_priv
->fbc
.plane
= to_intel_crtc(work
->crtc
)->plane
;
338 dev_priv
->fbc
.fb_id
= work
->crtc
->fb
->base
.id
;
339 dev_priv
->fbc
.y
= work
->crtc
->y
;
342 dev_priv
->fbc
.fbc_work
= NULL
;
344 mutex_unlock(&dev
->struct_mutex
);
349 static void intel_cancel_fbc_work(struct drm_i915_private
*dev_priv
)
351 if (dev_priv
->fbc
.fbc_work
== NULL
)
354 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
356 /* Synchronisation is provided by struct_mutex and checking of
357 * dev_priv->fbc.fbc_work, so we can perform the cancellation
358 * entirely asynchronously.
360 if (cancel_delayed_work(&dev_priv
->fbc
.fbc_work
->work
))
361 /* tasklet was killed before being run, clean up */
362 kfree(dev_priv
->fbc
.fbc_work
);
364 /* Mark the work as no longer wanted so that if it does
365 * wake-up (because the work was already running and waiting
366 * for our mutex), it will discover that is no longer
369 dev_priv
->fbc
.fbc_work
= NULL
;
372 static void intel_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
374 struct intel_fbc_work
*work
;
375 struct drm_device
*dev
= crtc
->dev
;
376 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
378 if (!dev_priv
->display
.enable_fbc
)
381 intel_cancel_fbc_work(dev_priv
);
383 work
= kzalloc(sizeof *work
, GFP_KERNEL
);
385 DRM_ERROR("Failed to allocate FBC work structure\n");
386 dev_priv
->display
.enable_fbc(crtc
, interval
);
392 work
->interval
= interval
;
393 INIT_DELAYED_WORK(&work
->work
, intel_fbc_work_fn
);
395 dev_priv
->fbc
.fbc_work
= work
;
397 /* Delay the actual enabling to let pageflipping cease and the
398 * display to settle before starting the compression. Note that
399 * this delay also serves a second purpose: it allows for a
400 * vblank to pass after disabling the FBC before we attempt
401 * to modify the control registers.
403 * A more complicated solution would involve tracking vblanks
404 * following the termination of the page-flipping sequence
405 * and indeed performing the enable as a co-routine and not
406 * waiting synchronously upon the vblank.
408 schedule_delayed_work(&work
->work
, msecs_to_jiffies(50));
411 void intel_disable_fbc(struct drm_device
*dev
)
413 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
415 intel_cancel_fbc_work(dev_priv
);
417 if (!dev_priv
->display
.disable_fbc
)
420 dev_priv
->display
.disable_fbc(dev
);
421 dev_priv
->fbc
.plane
= -1;
425 * intel_update_fbc - enable/disable FBC as needed
426 * @dev: the drm_device
428 * Set up the framebuffer compression hardware at mode set time. We
429 * enable it if possible:
430 * - plane A only (on pre-965)
431 * - no pixel mulitply/line duplication
432 * - no alpha buffer discard
434 * - framebuffer <= max_hdisplay in width, max_vdisplay in height
436 * We can't assume that any compression will take place (worst case),
437 * so the compressed buffer has to be the same size as the uncompressed
438 * one. It also must reside (along with the line length buffer) in
441 * We need to enable/disable FBC on a global basis.
443 void intel_update_fbc(struct drm_device
*dev
)
445 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
446 struct drm_crtc
*crtc
= NULL
, *tmp_crtc
;
447 struct intel_crtc
*intel_crtc
;
448 struct drm_framebuffer
*fb
;
449 struct intel_framebuffer
*intel_fb
;
450 struct drm_i915_gem_object
*obj
;
451 unsigned int max_hdisplay
, max_vdisplay
;
456 if (!I915_HAS_FBC(dev
))
460 * If FBC is already on, we just have to verify that we can
461 * keep it that way...
462 * Need to disable if:
463 * - more than one pipe is active
464 * - changing FBC params (stride, fence, mode)
465 * - new fb is too large to fit in compressed buffer
466 * - going to an unsupported config (interlace, pixel multiply, etc.)
468 list_for_each_entry(tmp_crtc
, &dev
->mode_config
.crtc_list
, head
) {
469 if (intel_crtc_active(tmp_crtc
) &&
470 !to_intel_crtc(tmp_crtc
)->primary_disabled
) {
472 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
473 dev_priv
->fbc
.no_fbc_reason
=
481 if (!crtc
|| crtc
->fb
== NULL
) {
482 DRM_DEBUG_KMS("no output, disabling\n");
483 dev_priv
->fbc
.no_fbc_reason
= FBC_NO_OUTPUT
;
487 intel_crtc
= to_intel_crtc(crtc
);
489 intel_fb
= to_intel_framebuffer(fb
);
492 if (i915_enable_fbc
< 0 &&
493 INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
)) {
494 DRM_DEBUG_KMS("disabled per chip default\n");
495 dev_priv
->fbc
.no_fbc_reason
= FBC_CHIP_DEFAULT
;
498 if (!i915_enable_fbc
) {
499 DRM_DEBUG_KMS("fbc disabled per module param\n");
500 dev_priv
->fbc
.no_fbc_reason
= FBC_MODULE_PARAM
;
503 if ((crtc
->mode
.flags
& DRM_MODE_FLAG_INTERLACE
) ||
504 (crtc
->mode
.flags
& DRM_MODE_FLAG_DBLSCAN
)) {
505 DRM_DEBUG_KMS("mode incompatible with compression, "
507 dev_priv
->fbc
.no_fbc_reason
= FBC_UNSUPPORTED_MODE
;
511 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5) {
518 if ((crtc
->mode
.hdisplay
> max_hdisplay
) ||
519 (crtc
->mode
.vdisplay
> max_vdisplay
)) {
520 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
521 dev_priv
->fbc
.no_fbc_reason
= FBC_MODE_TOO_LARGE
;
524 if ((IS_I915GM(dev
) || IS_I945GM(dev
) || IS_HASWELL(dev
)) &&
525 intel_crtc
->plane
!= 0) {
526 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
527 dev_priv
->fbc
.no_fbc_reason
= FBC_BAD_PLANE
;
531 /* The use of a CPU fence is mandatory in order to detect writes
532 * by the CPU to the scanout and trigger updates to the FBC.
534 if (obj
->tiling_mode
!= I915_TILING_X
||
535 obj
->fence_reg
== I915_FENCE_REG_NONE
) {
536 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
537 dev_priv
->fbc
.no_fbc_reason
= FBC_NOT_TILED
;
541 /* If the kernel debugger is active, always disable compression */
545 if (i915_gem_stolen_setup_compression(dev
, intel_fb
->obj
->base
.size
)) {
546 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
547 dev_priv
->fbc
.no_fbc_reason
= FBC_STOLEN_TOO_SMALL
;
551 /* If the scanout has not changed, don't modify the FBC settings.
552 * Note that we make the fundamental assumption that the fb->obj
553 * cannot be unpinned (and have its GTT offset and fence revoked)
554 * without first being decoupled from the scanout and FBC disabled.
556 if (dev_priv
->fbc
.plane
== intel_crtc
->plane
&&
557 dev_priv
->fbc
.fb_id
== fb
->base
.id
&&
558 dev_priv
->fbc
.y
== crtc
->y
)
561 if (intel_fbc_enabled(dev
)) {
562 /* We update FBC along two paths, after changing fb/crtc
563 * configuration (modeswitching) and after page-flipping
564 * finishes. For the latter, we know that not only did
565 * we disable the FBC at the start of the page-flip
566 * sequence, but also more than one vblank has passed.
568 * For the former case of modeswitching, it is possible
569 * to switch between two FBC valid configurations
570 * instantaneously so we do need to disable the FBC
571 * before we can modify its control registers. We also
572 * have to wait for the next vblank for that to take
573 * effect. However, since we delay enabling FBC we can
574 * assume that a vblank has passed since disabling and
575 * that we can safely alter the registers in the deferred
578 * In the scenario that we go from a valid to invalid
579 * and then back to valid FBC configuration we have
580 * no strict enforcement that a vblank occurred since
581 * disabling the FBC. However, along all current pipe
582 * disabling paths we do need to wait for a vblank at
583 * some point. And we wait before enabling FBC anyway.
585 DRM_DEBUG_KMS("disabling active FBC for update\n");
586 intel_disable_fbc(dev
);
589 intel_enable_fbc(crtc
, 500);
593 /* Multiple disables should be harmless */
594 if (intel_fbc_enabled(dev
)) {
595 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
596 intel_disable_fbc(dev
);
598 i915_gem_stolen_cleanup_compression(dev
);
601 static void i915_pineview_get_mem_freq(struct drm_device
*dev
)
603 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
606 tmp
= I915_READ(CLKCFG
);
608 switch (tmp
& CLKCFG_FSB_MASK
) {
610 dev_priv
->fsb_freq
= 533; /* 133*4 */
613 dev_priv
->fsb_freq
= 800; /* 200*4 */
616 dev_priv
->fsb_freq
= 667; /* 167*4 */
619 dev_priv
->fsb_freq
= 400; /* 100*4 */
623 switch (tmp
& CLKCFG_MEM_MASK
) {
625 dev_priv
->mem_freq
= 533;
628 dev_priv
->mem_freq
= 667;
631 dev_priv
->mem_freq
= 800;
635 /* detect pineview DDR3 setting */
636 tmp
= I915_READ(CSHRDDR3CTL
);
637 dev_priv
->is_ddr3
= (tmp
& CSHRDDR3CTL_DDR3
) ? 1 : 0;
640 static void i915_ironlake_get_mem_freq(struct drm_device
*dev
)
642 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
645 ddrpll
= I915_READ16(DDRMPLL1
);
646 csipll
= I915_READ16(CSIPLL0
);
648 switch (ddrpll
& 0xff) {
650 dev_priv
->mem_freq
= 800;
653 dev_priv
->mem_freq
= 1066;
656 dev_priv
->mem_freq
= 1333;
659 dev_priv
->mem_freq
= 1600;
662 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
664 dev_priv
->mem_freq
= 0;
668 dev_priv
->ips
.r_t
= dev_priv
->mem_freq
;
670 switch (csipll
& 0x3ff) {
672 dev_priv
->fsb_freq
= 3200;
675 dev_priv
->fsb_freq
= 3733;
678 dev_priv
->fsb_freq
= 4266;
681 dev_priv
->fsb_freq
= 4800;
684 dev_priv
->fsb_freq
= 5333;
687 dev_priv
->fsb_freq
= 5866;
690 dev_priv
->fsb_freq
= 6400;
693 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
695 dev_priv
->fsb_freq
= 0;
699 if (dev_priv
->fsb_freq
== 3200) {
700 dev_priv
->ips
.c_m
= 0;
701 } else if (dev_priv
->fsb_freq
> 3200 && dev_priv
->fsb_freq
<= 4800) {
702 dev_priv
->ips
.c_m
= 1;
704 dev_priv
->ips
.c_m
= 2;
708 static const struct cxsr_latency cxsr_latency_table
[] = {
709 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
710 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
711 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
712 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
713 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
715 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
716 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
717 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
718 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
719 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
721 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
722 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
723 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
724 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
725 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
727 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
728 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
729 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
730 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
731 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
733 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
734 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
735 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
736 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
737 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
739 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
740 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
741 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
742 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
743 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
746 static const struct cxsr_latency
*intel_get_cxsr_latency(int is_desktop
,
751 const struct cxsr_latency
*latency
;
754 if (fsb
== 0 || mem
== 0)
757 for (i
= 0; i
< ARRAY_SIZE(cxsr_latency_table
); i
++) {
758 latency
= &cxsr_latency_table
[i
];
759 if (is_desktop
== latency
->is_desktop
&&
760 is_ddr3
== latency
->is_ddr3
&&
761 fsb
== latency
->fsb_freq
&& mem
== latency
->mem_freq
)
765 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
770 static void pineview_disable_cxsr(struct drm_device
*dev
)
772 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
774 /* deactivate cxsr */
775 I915_WRITE(DSPFW3
, I915_READ(DSPFW3
) & ~PINEVIEW_SELF_REFRESH_EN
);
779 * Latency for FIFO fetches is dependent on several factors:
780 * - memory configuration (speed, channels)
782 * - current MCH state
783 * It can be fairly high in some situations, so here we assume a fairly
784 * pessimal value. It's a tradeoff between extra memory fetches (if we
785 * set this value too high, the FIFO will fetch frequently to stay full)
786 * and power consumption (set it too low to save power and we might see
787 * FIFO underruns and display "flicker").
789 * A value of 5us seems to be a good balance; safe for very low end
790 * platforms but not overly aggressive on lower latency configs.
792 static const int latency_ns
= 5000;
794 static int i9xx_get_fifo_size(struct drm_device
*dev
, int plane
)
796 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
797 uint32_t dsparb
= I915_READ(DSPARB
);
800 size
= dsparb
& 0x7f;
802 size
= ((dsparb
>> DSPARB_CSTART_SHIFT
) & 0x7f) - size
;
804 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
805 plane
? "B" : "A", size
);
810 static int i85x_get_fifo_size(struct drm_device
*dev
, int plane
)
812 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
813 uint32_t dsparb
= I915_READ(DSPARB
);
816 size
= dsparb
& 0x1ff;
818 size
= ((dsparb
>> DSPARB_BEND_SHIFT
) & 0x1ff) - size
;
819 size
>>= 1; /* Convert to cachelines */
821 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
822 plane
? "B" : "A", size
);
827 static int i845_get_fifo_size(struct drm_device
*dev
, int plane
)
829 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
830 uint32_t dsparb
= I915_READ(DSPARB
);
833 size
= dsparb
& 0x7f;
834 size
>>= 2; /* Convert to cachelines */
836 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
843 static int i830_get_fifo_size(struct drm_device
*dev
, int plane
)
845 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
846 uint32_t dsparb
= I915_READ(DSPARB
);
849 size
= dsparb
& 0x7f;
850 size
>>= 1; /* Convert to cachelines */
852 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
853 plane
? "B" : "A", size
);
858 /* Pineview has different values for various configs */
859 static const struct intel_watermark_params pineview_display_wm
= {
860 PINEVIEW_DISPLAY_FIFO
,
864 PINEVIEW_FIFO_LINE_SIZE
866 static const struct intel_watermark_params pineview_display_hplloff_wm
= {
867 PINEVIEW_DISPLAY_FIFO
,
869 PINEVIEW_DFT_HPLLOFF_WM
,
871 PINEVIEW_FIFO_LINE_SIZE
873 static const struct intel_watermark_params pineview_cursor_wm
= {
874 PINEVIEW_CURSOR_FIFO
,
875 PINEVIEW_CURSOR_MAX_WM
,
876 PINEVIEW_CURSOR_DFT_WM
,
877 PINEVIEW_CURSOR_GUARD_WM
,
878 PINEVIEW_FIFO_LINE_SIZE
,
880 static const struct intel_watermark_params pineview_cursor_hplloff_wm
= {
881 PINEVIEW_CURSOR_FIFO
,
882 PINEVIEW_CURSOR_MAX_WM
,
883 PINEVIEW_CURSOR_DFT_WM
,
884 PINEVIEW_CURSOR_GUARD_WM
,
885 PINEVIEW_FIFO_LINE_SIZE
887 static const struct intel_watermark_params g4x_wm_info
= {
894 static const struct intel_watermark_params g4x_cursor_wm_info
= {
901 static const struct intel_watermark_params valleyview_wm_info
= {
902 VALLEYVIEW_FIFO_SIZE
,
908 static const struct intel_watermark_params valleyview_cursor_wm_info
= {
910 VALLEYVIEW_CURSOR_MAX_WM
,
915 static const struct intel_watermark_params i965_cursor_wm_info
= {
922 static const struct intel_watermark_params i945_wm_info
= {
929 static const struct intel_watermark_params i915_wm_info
= {
936 static const struct intel_watermark_params i855_wm_info
= {
943 static const struct intel_watermark_params i830_wm_info
= {
951 static const struct intel_watermark_params ironlake_display_wm_info
= {
958 static const struct intel_watermark_params ironlake_cursor_wm_info
= {
965 static const struct intel_watermark_params ironlake_display_srwm_info
= {
967 ILK_DISPLAY_MAX_SRWM
,
968 ILK_DISPLAY_DFT_SRWM
,
972 static const struct intel_watermark_params ironlake_cursor_srwm_info
= {
980 static const struct intel_watermark_params sandybridge_display_wm_info
= {
987 static const struct intel_watermark_params sandybridge_cursor_wm_info
= {
994 static const struct intel_watermark_params sandybridge_display_srwm_info
= {
996 SNB_DISPLAY_MAX_SRWM
,
997 SNB_DISPLAY_DFT_SRWM
,
1001 static const struct intel_watermark_params sandybridge_cursor_srwm_info
= {
1003 SNB_CURSOR_MAX_SRWM
,
1004 SNB_CURSOR_DFT_SRWM
,
1011 * intel_calculate_wm - calculate watermark level
1012 * @clock_in_khz: pixel clock
1013 * @wm: chip FIFO params
1014 * @pixel_size: display pixel size
1015 * @latency_ns: memory latency for the platform
1017 * Calculate the watermark level (the level at which the display plane will
1018 * start fetching from memory again). Each chip has a different display
1019 * FIFO size and allocation, so the caller needs to figure that out and pass
1020 * in the correct intel_watermark_params structure.
1022 * As the pixel clock runs, the FIFO will be drained at a rate that depends
1023 * on the pixel size. When it reaches the watermark level, it'll start
1024 * fetching FIFO line sized based chunks from memory until the FIFO fills
1025 * past the watermark point. If the FIFO drains completely, a FIFO underrun
1026 * will occur, and a display engine hang could result.
1028 static unsigned long intel_calculate_wm(unsigned long clock_in_khz
,
1029 const struct intel_watermark_params
*wm
,
1032 unsigned long latency_ns
)
1034 long entries_required
, wm_size
;
1037 * Note: we need to make sure we don't overflow for various clock &
1039 * clocks go from a few thousand to several hundred thousand.
1040 * latency is usually a few thousand
1042 entries_required
= ((clock_in_khz
/ 1000) * pixel_size
* latency_ns
) /
1044 entries_required
= DIV_ROUND_UP(entries_required
, wm
->cacheline_size
);
1046 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required
);
1048 wm_size
= fifo_size
- (entries_required
+ wm
->guard_size
);
1050 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size
);
1052 /* Don't promote wm_size to unsigned... */
1053 if (wm_size
> (long)wm
->max_wm
)
1054 wm_size
= wm
->max_wm
;
1056 wm_size
= wm
->default_wm
;
1060 static struct drm_crtc
*single_enabled_crtc(struct drm_device
*dev
)
1062 struct drm_crtc
*crtc
, *enabled
= NULL
;
1064 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
1065 if (intel_crtc_active(crtc
)) {
1075 static void pineview_update_wm(struct drm_device
*dev
)
1077 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1078 struct drm_crtc
*crtc
;
1079 const struct cxsr_latency
*latency
;
1083 latency
= intel_get_cxsr_latency(IS_PINEVIEW_G(dev
), dev_priv
->is_ddr3
,
1084 dev_priv
->fsb_freq
, dev_priv
->mem_freq
);
1086 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1087 pineview_disable_cxsr(dev
);
1091 crtc
= single_enabled_crtc(dev
);
1093 int clock
= crtc
->mode
.clock
;
1094 int pixel_size
= crtc
->fb
->bits_per_pixel
/ 8;
1097 wm
= intel_calculate_wm(clock
, &pineview_display_wm
,
1098 pineview_display_wm
.fifo_size
,
1099 pixel_size
, latency
->display_sr
);
1100 reg
= I915_READ(DSPFW1
);
1101 reg
&= ~DSPFW_SR_MASK
;
1102 reg
|= wm
<< DSPFW_SR_SHIFT
;
1103 I915_WRITE(DSPFW1
, reg
);
1104 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg
);
1107 wm
= intel_calculate_wm(clock
, &pineview_cursor_wm
,
1108 pineview_display_wm
.fifo_size
,
1109 pixel_size
, latency
->cursor_sr
);
1110 reg
= I915_READ(DSPFW3
);
1111 reg
&= ~DSPFW_CURSOR_SR_MASK
;
1112 reg
|= (wm
& 0x3f) << DSPFW_CURSOR_SR_SHIFT
;
1113 I915_WRITE(DSPFW3
, reg
);
1115 /* Display HPLL off SR */
1116 wm
= intel_calculate_wm(clock
, &pineview_display_hplloff_wm
,
1117 pineview_display_hplloff_wm
.fifo_size
,
1118 pixel_size
, latency
->display_hpll_disable
);
1119 reg
= I915_READ(DSPFW3
);
1120 reg
&= ~DSPFW_HPLL_SR_MASK
;
1121 reg
|= wm
& DSPFW_HPLL_SR_MASK
;
1122 I915_WRITE(DSPFW3
, reg
);
1124 /* cursor HPLL off SR */
1125 wm
= intel_calculate_wm(clock
, &pineview_cursor_hplloff_wm
,
1126 pineview_display_hplloff_wm
.fifo_size
,
1127 pixel_size
, latency
->cursor_hpll_disable
);
1128 reg
= I915_READ(DSPFW3
);
1129 reg
&= ~DSPFW_HPLL_CURSOR_MASK
;
1130 reg
|= (wm
& 0x3f) << DSPFW_HPLL_CURSOR_SHIFT
;
1131 I915_WRITE(DSPFW3
, reg
);
1132 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg
);
1136 I915_READ(DSPFW3
) | PINEVIEW_SELF_REFRESH_EN
);
1137 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1139 pineview_disable_cxsr(dev
);
1140 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1144 static bool g4x_compute_wm0(struct drm_device
*dev
,
1146 const struct intel_watermark_params
*display
,
1147 int display_latency_ns
,
1148 const struct intel_watermark_params
*cursor
,
1149 int cursor_latency_ns
,
1153 struct drm_crtc
*crtc
;
1154 int htotal
, hdisplay
, clock
, pixel_size
;
1155 int line_time_us
, line_count
;
1156 int entries
, tlb_miss
;
1158 crtc
= intel_get_crtc_for_plane(dev
, plane
);
1159 if (!intel_crtc_active(crtc
)) {
1160 *cursor_wm
= cursor
->guard_size
;
1161 *plane_wm
= display
->guard_size
;
1165 htotal
= crtc
->mode
.htotal
;
1166 hdisplay
= crtc
->mode
.hdisplay
;
1167 clock
= crtc
->mode
.clock
;
1168 pixel_size
= crtc
->fb
->bits_per_pixel
/ 8;
1170 /* Use the small buffer method to calculate plane watermark */
1171 entries
= ((clock
* pixel_size
/ 1000) * display_latency_ns
) / 1000;
1172 tlb_miss
= display
->fifo_size
*display
->cacheline_size
- hdisplay
* 8;
1174 entries
+= tlb_miss
;
1175 entries
= DIV_ROUND_UP(entries
, display
->cacheline_size
);
1176 *plane_wm
= entries
+ display
->guard_size
;
1177 if (*plane_wm
> (int)display
->max_wm
)
1178 *plane_wm
= display
->max_wm
;
1180 /* Use the large buffer method to calculate cursor watermark */
1181 line_time_us
= ((htotal
* 1000) / clock
);
1182 line_count
= (cursor_latency_ns
/ line_time_us
+ 1000) / 1000;
1183 entries
= line_count
* 64 * pixel_size
;
1184 tlb_miss
= cursor
->fifo_size
*cursor
->cacheline_size
- hdisplay
* 8;
1186 entries
+= tlb_miss
;
1187 entries
= DIV_ROUND_UP(entries
, cursor
->cacheline_size
);
1188 *cursor_wm
= entries
+ cursor
->guard_size
;
1189 if (*cursor_wm
> (int)cursor
->max_wm
)
1190 *cursor_wm
= (int)cursor
->max_wm
;
1196 * Check the wm result.
1198 * If any calculated watermark values is larger than the maximum value that
1199 * can be programmed into the associated watermark register, that watermark
1202 static bool g4x_check_srwm(struct drm_device
*dev
,
1203 int display_wm
, int cursor_wm
,
1204 const struct intel_watermark_params
*display
,
1205 const struct intel_watermark_params
*cursor
)
1207 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1208 display_wm
, cursor_wm
);
1210 if (display_wm
> display
->max_wm
) {
1211 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1212 display_wm
, display
->max_wm
);
1216 if (cursor_wm
> cursor
->max_wm
) {
1217 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1218 cursor_wm
, cursor
->max_wm
);
1222 if (!(display_wm
|| cursor_wm
)) {
1223 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1230 static bool g4x_compute_srwm(struct drm_device
*dev
,
1233 const struct intel_watermark_params
*display
,
1234 const struct intel_watermark_params
*cursor
,
1235 int *display_wm
, int *cursor_wm
)
1237 struct drm_crtc
*crtc
;
1238 int hdisplay
, htotal
, pixel_size
, clock
;
1239 unsigned long line_time_us
;
1240 int line_count
, line_size
;
1245 *display_wm
= *cursor_wm
= 0;
1249 crtc
= intel_get_crtc_for_plane(dev
, plane
);
1250 hdisplay
= crtc
->mode
.hdisplay
;
1251 htotal
= crtc
->mode
.htotal
;
1252 clock
= crtc
->mode
.clock
;
1253 pixel_size
= crtc
->fb
->bits_per_pixel
/ 8;
1255 line_time_us
= (htotal
* 1000) / clock
;
1256 line_count
= (latency_ns
/ line_time_us
+ 1000) / 1000;
1257 line_size
= hdisplay
* pixel_size
;
1259 /* Use the minimum of the small and large buffer method for primary */
1260 small
= ((clock
* pixel_size
/ 1000) * latency_ns
) / 1000;
1261 large
= line_count
* line_size
;
1263 entries
= DIV_ROUND_UP(min(small
, large
), display
->cacheline_size
);
1264 *display_wm
= entries
+ display
->guard_size
;
1266 /* calculate the self-refresh watermark for display cursor */
1267 entries
= line_count
* pixel_size
* 64;
1268 entries
= DIV_ROUND_UP(entries
, cursor
->cacheline_size
);
1269 *cursor_wm
= entries
+ cursor
->guard_size
;
1271 return g4x_check_srwm(dev
,
1272 *display_wm
, *cursor_wm
,
1276 static bool vlv_compute_drain_latency(struct drm_device
*dev
,
1278 int *plane_prec_mult
,
1280 int *cursor_prec_mult
,
1283 struct drm_crtc
*crtc
;
1284 int clock
, pixel_size
;
1287 crtc
= intel_get_crtc_for_plane(dev
, plane
);
1288 if (!intel_crtc_active(crtc
))
1291 clock
= crtc
->mode
.clock
; /* VESA DOT Clock */
1292 pixel_size
= crtc
->fb
->bits_per_pixel
/ 8; /* BPP */
1294 entries
= (clock
/ 1000) * pixel_size
;
1295 *plane_prec_mult
= (entries
> 256) ?
1296 DRAIN_LATENCY_PRECISION_32
: DRAIN_LATENCY_PRECISION_16
;
1297 *plane_dl
= (64 * (*plane_prec_mult
) * 4) / ((clock
/ 1000) *
1300 entries
= (clock
/ 1000) * 4; /* BPP is always 4 for cursor */
1301 *cursor_prec_mult
= (entries
> 256) ?
1302 DRAIN_LATENCY_PRECISION_32
: DRAIN_LATENCY_PRECISION_16
;
1303 *cursor_dl
= (64 * (*cursor_prec_mult
) * 4) / ((clock
/ 1000) * 4);
1309 * Update drain latency registers of memory arbiter
1311 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1312 * to be programmed. Each plane has a drain latency multiplier and a drain
1316 static void vlv_update_drain_latency(struct drm_device
*dev
)
1318 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1319 int planea_prec
, planea_dl
, planeb_prec
, planeb_dl
;
1320 int cursora_prec
, cursora_dl
, cursorb_prec
, cursorb_dl
;
1321 int plane_prec_mult
, cursor_prec_mult
; /* Precision multiplier is
1324 /* For plane A, Cursor A */
1325 if (vlv_compute_drain_latency(dev
, 0, &plane_prec_mult
, &planea_dl
,
1326 &cursor_prec_mult
, &cursora_dl
)) {
1327 cursora_prec
= (cursor_prec_mult
== DRAIN_LATENCY_PRECISION_32
) ?
1328 DDL_CURSORA_PRECISION_32
: DDL_CURSORA_PRECISION_16
;
1329 planea_prec
= (plane_prec_mult
== DRAIN_LATENCY_PRECISION_32
) ?
1330 DDL_PLANEA_PRECISION_32
: DDL_PLANEA_PRECISION_16
;
1332 I915_WRITE(VLV_DDL1
, cursora_prec
|
1333 (cursora_dl
<< DDL_CURSORA_SHIFT
) |
1334 planea_prec
| planea_dl
);
1337 /* For plane B, Cursor B */
1338 if (vlv_compute_drain_latency(dev
, 1, &plane_prec_mult
, &planeb_dl
,
1339 &cursor_prec_mult
, &cursorb_dl
)) {
1340 cursorb_prec
= (cursor_prec_mult
== DRAIN_LATENCY_PRECISION_32
) ?
1341 DDL_CURSORB_PRECISION_32
: DDL_CURSORB_PRECISION_16
;
1342 planeb_prec
= (plane_prec_mult
== DRAIN_LATENCY_PRECISION_32
) ?
1343 DDL_PLANEB_PRECISION_32
: DDL_PLANEB_PRECISION_16
;
1345 I915_WRITE(VLV_DDL2
, cursorb_prec
|
1346 (cursorb_dl
<< DDL_CURSORB_SHIFT
) |
1347 planeb_prec
| planeb_dl
);
1351 #define single_plane_enabled(mask) is_power_of_2(mask)
1353 static void valleyview_update_wm(struct drm_device
*dev
)
1355 static const int sr_latency_ns
= 12000;
1356 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1357 int planea_wm
, planeb_wm
, cursora_wm
, cursorb_wm
;
1358 int plane_sr
, cursor_sr
;
1359 int ignore_plane_sr
, ignore_cursor_sr
;
1360 unsigned int enabled
= 0;
1362 vlv_update_drain_latency(dev
);
1364 if (g4x_compute_wm0(dev
, PIPE_A
,
1365 &valleyview_wm_info
, latency_ns
,
1366 &valleyview_cursor_wm_info
, latency_ns
,
1367 &planea_wm
, &cursora_wm
))
1368 enabled
|= 1 << PIPE_A
;
1370 if (g4x_compute_wm0(dev
, PIPE_B
,
1371 &valleyview_wm_info
, latency_ns
,
1372 &valleyview_cursor_wm_info
, latency_ns
,
1373 &planeb_wm
, &cursorb_wm
))
1374 enabled
|= 1 << PIPE_B
;
1376 if (single_plane_enabled(enabled
) &&
1377 g4x_compute_srwm(dev
, ffs(enabled
) - 1,
1379 &valleyview_wm_info
,
1380 &valleyview_cursor_wm_info
,
1381 &plane_sr
, &ignore_cursor_sr
) &&
1382 g4x_compute_srwm(dev
, ffs(enabled
) - 1,
1384 &valleyview_wm_info
,
1385 &valleyview_cursor_wm_info
,
1386 &ignore_plane_sr
, &cursor_sr
)) {
1387 I915_WRITE(FW_BLC_SELF_VLV
, FW_CSPWRDWNEN
);
1389 I915_WRITE(FW_BLC_SELF_VLV
,
1390 I915_READ(FW_BLC_SELF_VLV
) & ~FW_CSPWRDWNEN
);
1391 plane_sr
= cursor_sr
= 0;
1394 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1395 planea_wm
, cursora_wm
,
1396 planeb_wm
, cursorb_wm
,
1397 plane_sr
, cursor_sr
);
1400 (plane_sr
<< DSPFW_SR_SHIFT
) |
1401 (cursorb_wm
<< DSPFW_CURSORB_SHIFT
) |
1402 (planeb_wm
<< DSPFW_PLANEB_SHIFT
) |
1405 (I915_READ(DSPFW2
) & ~DSPFW_CURSORA_MASK
) |
1406 (cursora_wm
<< DSPFW_CURSORA_SHIFT
));
1408 (I915_READ(DSPFW3
) & ~DSPFW_CURSOR_SR_MASK
) |
1409 (cursor_sr
<< DSPFW_CURSOR_SR_SHIFT
));
1412 static void g4x_update_wm(struct drm_device
*dev
)
1414 static const int sr_latency_ns
= 12000;
1415 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1416 int planea_wm
, planeb_wm
, cursora_wm
, cursorb_wm
;
1417 int plane_sr
, cursor_sr
;
1418 unsigned int enabled
= 0;
1420 if (g4x_compute_wm0(dev
, PIPE_A
,
1421 &g4x_wm_info
, latency_ns
,
1422 &g4x_cursor_wm_info
, latency_ns
,
1423 &planea_wm
, &cursora_wm
))
1424 enabled
|= 1 << PIPE_A
;
1426 if (g4x_compute_wm0(dev
, PIPE_B
,
1427 &g4x_wm_info
, latency_ns
,
1428 &g4x_cursor_wm_info
, latency_ns
,
1429 &planeb_wm
, &cursorb_wm
))
1430 enabled
|= 1 << PIPE_B
;
1432 if (single_plane_enabled(enabled
) &&
1433 g4x_compute_srwm(dev
, ffs(enabled
) - 1,
1436 &g4x_cursor_wm_info
,
1437 &plane_sr
, &cursor_sr
)) {
1438 I915_WRITE(FW_BLC_SELF
, FW_BLC_SELF_EN
);
1440 I915_WRITE(FW_BLC_SELF
,
1441 I915_READ(FW_BLC_SELF
) & ~FW_BLC_SELF_EN
);
1442 plane_sr
= cursor_sr
= 0;
1445 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1446 planea_wm
, cursora_wm
,
1447 planeb_wm
, cursorb_wm
,
1448 plane_sr
, cursor_sr
);
1451 (plane_sr
<< DSPFW_SR_SHIFT
) |
1452 (cursorb_wm
<< DSPFW_CURSORB_SHIFT
) |
1453 (planeb_wm
<< DSPFW_PLANEB_SHIFT
) |
1456 (I915_READ(DSPFW2
) & ~DSPFW_CURSORA_MASK
) |
1457 (cursora_wm
<< DSPFW_CURSORA_SHIFT
));
1458 /* HPLL off in SR has some issues on G4x... disable it */
1460 (I915_READ(DSPFW3
) & ~(DSPFW_HPLL_SR_EN
| DSPFW_CURSOR_SR_MASK
)) |
1461 (cursor_sr
<< DSPFW_CURSOR_SR_SHIFT
));
1464 static void i965_update_wm(struct drm_device
*dev
)
1466 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1467 struct drm_crtc
*crtc
;
1471 /* Calc sr entries for one plane configs */
1472 crtc
= single_enabled_crtc(dev
);
1474 /* self-refresh has much higher latency */
1475 static const int sr_latency_ns
= 12000;
1476 int clock
= crtc
->mode
.clock
;
1477 int htotal
= crtc
->mode
.htotal
;
1478 int hdisplay
= crtc
->mode
.hdisplay
;
1479 int pixel_size
= crtc
->fb
->bits_per_pixel
/ 8;
1480 unsigned long line_time_us
;
1483 line_time_us
= ((htotal
* 1000) / clock
);
1485 /* Use ns/us then divide to preserve precision */
1486 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
1487 pixel_size
* hdisplay
;
1488 entries
= DIV_ROUND_UP(entries
, I915_FIFO_LINE_SIZE
);
1489 srwm
= I965_FIFO_SIZE
- entries
;
1493 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1496 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
1498 entries
= DIV_ROUND_UP(entries
,
1499 i965_cursor_wm_info
.cacheline_size
);
1500 cursor_sr
= i965_cursor_wm_info
.fifo_size
-
1501 (entries
+ i965_cursor_wm_info
.guard_size
);
1503 if (cursor_sr
> i965_cursor_wm_info
.max_wm
)
1504 cursor_sr
= i965_cursor_wm_info
.max_wm
;
1506 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1507 "cursor %d\n", srwm
, cursor_sr
);
1509 if (IS_CRESTLINE(dev
))
1510 I915_WRITE(FW_BLC_SELF
, FW_BLC_SELF_EN
);
1512 /* Turn off self refresh if both pipes are enabled */
1513 if (IS_CRESTLINE(dev
))
1514 I915_WRITE(FW_BLC_SELF
, I915_READ(FW_BLC_SELF
)
1518 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1521 /* 965 has limitations... */
1522 I915_WRITE(DSPFW1
, (srwm
<< DSPFW_SR_SHIFT
) |
1523 (8 << 16) | (8 << 8) | (8 << 0));
1524 I915_WRITE(DSPFW2
, (8 << 8) | (8 << 0));
1525 /* update cursor SR watermark */
1526 I915_WRITE(DSPFW3
, (cursor_sr
<< DSPFW_CURSOR_SR_SHIFT
));
1529 static void i9xx_update_wm(struct drm_device
*dev
)
1531 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1532 const struct intel_watermark_params
*wm_info
;
1537 int planea_wm
, planeb_wm
;
1538 struct drm_crtc
*crtc
, *enabled
= NULL
;
1541 wm_info
= &i945_wm_info
;
1542 else if (!IS_GEN2(dev
))
1543 wm_info
= &i915_wm_info
;
1545 wm_info
= &i855_wm_info
;
1547 fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 0);
1548 crtc
= intel_get_crtc_for_plane(dev
, 0);
1549 if (intel_crtc_active(crtc
)) {
1550 int cpp
= crtc
->fb
->bits_per_pixel
/ 8;
1554 planea_wm
= intel_calculate_wm(crtc
->mode
.clock
,
1555 wm_info
, fifo_size
, cpp
,
1559 planea_wm
= fifo_size
- wm_info
->guard_size
;
1561 fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 1);
1562 crtc
= intel_get_crtc_for_plane(dev
, 1);
1563 if (intel_crtc_active(crtc
)) {
1564 int cpp
= crtc
->fb
->bits_per_pixel
/ 8;
1568 planeb_wm
= intel_calculate_wm(crtc
->mode
.clock
,
1569 wm_info
, fifo_size
, cpp
,
1571 if (enabled
== NULL
)
1576 planeb_wm
= fifo_size
- wm_info
->guard_size
;
1578 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm
, planeb_wm
);
1581 * Overlay gets an aggressive default since video jitter is bad.
1585 /* Play safe and disable self-refresh before adjusting watermarks. */
1586 if (IS_I945G(dev
) || IS_I945GM(dev
))
1587 I915_WRITE(FW_BLC_SELF
, FW_BLC_SELF_EN_MASK
| 0);
1588 else if (IS_I915GM(dev
))
1589 I915_WRITE(INSTPM
, I915_READ(INSTPM
) & ~INSTPM_SELF_EN
);
1591 /* Calc sr entries for one plane configs */
1592 if (HAS_FW_BLC(dev
) && enabled
) {
1593 /* self-refresh has much higher latency */
1594 static const int sr_latency_ns
= 6000;
1595 int clock
= enabled
->mode
.clock
;
1596 int htotal
= enabled
->mode
.htotal
;
1597 int hdisplay
= enabled
->mode
.hdisplay
;
1598 int pixel_size
= enabled
->fb
->bits_per_pixel
/ 8;
1599 unsigned long line_time_us
;
1602 line_time_us
= (htotal
* 1000) / clock
;
1604 /* Use ns/us then divide to preserve precision */
1605 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
1606 pixel_size
* hdisplay
;
1607 entries
= DIV_ROUND_UP(entries
, wm_info
->cacheline_size
);
1608 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries
);
1609 srwm
= wm_info
->fifo_size
- entries
;
1613 if (IS_I945G(dev
) || IS_I945GM(dev
))
1614 I915_WRITE(FW_BLC_SELF
,
1615 FW_BLC_SELF_FIFO_MASK
| (srwm
& 0xff));
1616 else if (IS_I915GM(dev
))
1617 I915_WRITE(FW_BLC_SELF
, srwm
& 0x3f);
1620 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1621 planea_wm
, planeb_wm
, cwm
, srwm
);
1623 fwater_lo
= ((planeb_wm
& 0x3f) << 16) | (planea_wm
& 0x3f);
1624 fwater_hi
= (cwm
& 0x1f);
1626 /* Set request length to 8 cachelines per fetch */
1627 fwater_lo
= fwater_lo
| (1 << 24) | (1 << 8);
1628 fwater_hi
= fwater_hi
| (1 << 8);
1630 I915_WRITE(FW_BLC
, fwater_lo
);
1631 I915_WRITE(FW_BLC2
, fwater_hi
);
1633 if (HAS_FW_BLC(dev
)) {
1635 if (IS_I945G(dev
) || IS_I945GM(dev
))
1636 I915_WRITE(FW_BLC_SELF
,
1637 FW_BLC_SELF_EN_MASK
| FW_BLC_SELF_EN
);
1638 else if (IS_I915GM(dev
))
1639 I915_WRITE(INSTPM
, I915_READ(INSTPM
) | INSTPM_SELF_EN
);
1640 DRM_DEBUG_KMS("memory self refresh enabled\n");
1642 DRM_DEBUG_KMS("memory self refresh disabled\n");
1646 static void i830_update_wm(struct drm_device
*dev
)
1648 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1649 struct drm_crtc
*crtc
;
1653 crtc
= single_enabled_crtc(dev
);
1657 planea_wm
= intel_calculate_wm(crtc
->mode
.clock
, &i830_wm_info
,
1658 dev_priv
->display
.get_fifo_size(dev
, 0),
1660 fwater_lo
= I915_READ(FW_BLC
) & ~0xfff;
1661 fwater_lo
|= (3<<8) | planea_wm
;
1663 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm
);
1665 I915_WRITE(FW_BLC
, fwater_lo
);
1668 #define ILK_LP0_PLANE_LATENCY 700
1669 #define ILK_LP0_CURSOR_LATENCY 1300
1672 * Check the wm result.
1674 * If any calculated watermark values is larger than the maximum value that
1675 * can be programmed into the associated watermark register, that watermark
1678 static bool ironlake_check_srwm(struct drm_device
*dev
, int level
,
1679 int fbc_wm
, int display_wm
, int cursor_wm
,
1680 const struct intel_watermark_params
*display
,
1681 const struct intel_watermark_params
*cursor
)
1683 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1685 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
1686 " cursor %d\n", level
, display_wm
, fbc_wm
, cursor_wm
);
1688 if (fbc_wm
> SNB_FBC_MAX_SRWM
) {
1689 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
1690 fbc_wm
, SNB_FBC_MAX_SRWM
, level
);
1692 /* fbc has it's own way to disable FBC WM */
1693 I915_WRITE(DISP_ARB_CTL
,
1694 I915_READ(DISP_ARB_CTL
) | DISP_FBC_WM_DIS
);
1696 } else if (INTEL_INFO(dev
)->gen
>= 6) {
1697 /* enable FBC WM (except on ILK, where it must remain off) */
1698 I915_WRITE(DISP_ARB_CTL
,
1699 I915_READ(DISP_ARB_CTL
) & ~DISP_FBC_WM_DIS
);
1702 if (display_wm
> display
->max_wm
) {
1703 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
1704 display_wm
, SNB_DISPLAY_MAX_SRWM
, level
);
1708 if (cursor_wm
> cursor
->max_wm
) {
1709 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
1710 cursor_wm
, SNB_CURSOR_MAX_SRWM
, level
);
1714 if (!(fbc_wm
|| display_wm
|| cursor_wm
)) {
1715 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level
, level
);
1723 * Compute watermark values of WM[1-3],
1725 static bool ironlake_compute_srwm(struct drm_device
*dev
, int level
, int plane
,
1727 const struct intel_watermark_params
*display
,
1728 const struct intel_watermark_params
*cursor
,
1729 int *fbc_wm
, int *display_wm
, int *cursor_wm
)
1731 struct drm_crtc
*crtc
;
1732 unsigned long line_time_us
;
1733 int hdisplay
, htotal
, pixel_size
, clock
;
1734 int line_count
, line_size
;
1739 *fbc_wm
= *display_wm
= *cursor_wm
= 0;
1743 crtc
= intel_get_crtc_for_plane(dev
, plane
);
1744 hdisplay
= crtc
->mode
.hdisplay
;
1745 htotal
= crtc
->mode
.htotal
;
1746 clock
= crtc
->mode
.clock
;
1747 pixel_size
= crtc
->fb
->bits_per_pixel
/ 8;
1749 line_time_us
= (htotal
* 1000) / clock
;
1750 line_count
= (latency_ns
/ line_time_us
+ 1000) / 1000;
1751 line_size
= hdisplay
* pixel_size
;
1753 /* Use the minimum of the small and large buffer method for primary */
1754 small
= ((clock
* pixel_size
/ 1000) * latency_ns
) / 1000;
1755 large
= line_count
* line_size
;
1757 entries
= DIV_ROUND_UP(min(small
, large
), display
->cacheline_size
);
1758 *display_wm
= entries
+ display
->guard_size
;
1762 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
1764 *fbc_wm
= DIV_ROUND_UP(*display_wm
* 64, line_size
) + 2;
1766 /* calculate the self-refresh watermark for display cursor */
1767 entries
= line_count
* pixel_size
* 64;
1768 entries
= DIV_ROUND_UP(entries
, cursor
->cacheline_size
);
1769 *cursor_wm
= entries
+ cursor
->guard_size
;
1771 return ironlake_check_srwm(dev
, level
,
1772 *fbc_wm
, *display_wm
, *cursor_wm
,
1776 static void ironlake_update_wm(struct drm_device
*dev
)
1778 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1779 int fbc_wm
, plane_wm
, cursor_wm
;
1780 unsigned int enabled
;
1783 if (g4x_compute_wm0(dev
, PIPE_A
,
1784 &ironlake_display_wm_info
,
1785 ILK_LP0_PLANE_LATENCY
,
1786 &ironlake_cursor_wm_info
,
1787 ILK_LP0_CURSOR_LATENCY
,
1788 &plane_wm
, &cursor_wm
)) {
1789 I915_WRITE(WM0_PIPEA_ILK
,
1790 (plane_wm
<< WM0_PIPE_PLANE_SHIFT
) | cursor_wm
);
1791 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1792 " plane %d, " "cursor: %d\n",
1793 plane_wm
, cursor_wm
);
1794 enabled
|= 1 << PIPE_A
;
1797 if (g4x_compute_wm0(dev
, PIPE_B
,
1798 &ironlake_display_wm_info
,
1799 ILK_LP0_PLANE_LATENCY
,
1800 &ironlake_cursor_wm_info
,
1801 ILK_LP0_CURSOR_LATENCY
,
1802 &plane_wm
, &cursor_wm
)) {
1803 I915_WRITE(WM0_PIPEB_ILK
,
1804 (plane_wm
<< WM0_PIPE_PLANE_SHIFT
) | cursor_wm
);
1805 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1806 " plane %d, cursor: %d\n",
1807 plane_wm
, cursor_wm
);
1808 enabled
|= 1 << PIPE_B
;
1812 * Calculate and update the self-refresh watermark only when one
1813 * display plane is used.
1815 I915_WRITE(WM3_LP_ILK
, 0);
1816 I915_WRITE(WM2_LP_ILK
, 0);
1817 I915_WRITE(WM1_LP_ILK
, 0);
1819 if (!single_plane_enabled(enabled
))
1821 enabled
= ffs(enabled
) - 1;
1824 if (!ironlake_compute_srwm(dev
, 1, enabled
,
1825 ILK_READ_WM1_LATENCY() * 500,
1826 &ironlake_display_srwm_info
,
1827 &ironlake_cursor_srwm_info
,
1828 &fbc_wm
, &plane_wm
, &cursor_wm
))
1831 I915_WRITE(WM1_LP_ILK
,
1833 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT
) |
1834 (fbc_wm
<< WM1_LP_FBC_SHIFT
) |
1835 (plane_wm
<< WM1_LP_SR_SHIFT
) |
1839 if (!ironlake_compute_srwm(dev
, 2, enabled
,
1840 ILK_READ_WM2_LATENCY() * 500,
1841 &ironlake_display_srwm_info
,
1842 &ironlake_cursor_srwm_info
,
1843 &fbc_wm
, &plane_wm
, &cursor_wm
))
1846 I915_WRITE(WM2_LP_ILK
,
1848 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT
) |
1849 (fbc_wm
<< WM1_LP_FBC_SHIFT
) |
1850 (plane_wm
<< WM1_LP_SR_SHIFT
) |
1854 * WM3 is unsupported on ILK, probably because we don't have latency
1855 * data for that power state
1859 static void sandybridge_update_wm(struct drm_device
*dev
)
1861 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1862 int latency
= SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
1864 int fbc_wm
, plane_wm
, cursor_wm
;
1865 unsigned int enabled
;
1868 if (g4x_compute_wm0(dev
, PIPE_A
,
1869 &sandybridge_display_wm_info
, latency
,
1870 &sandybridge_cursor_wm_info
, latency
,
1871 &plane_wm
, &cursor_wm
)) {
1872 val
= I915_READ(WM0_PIPEA_ILK
);
1873 val
&= ~(WM0_PIPE_PLANE_MASK
| WM0_PIPE_CURSOR_MASK
);
1874 I915_WRITE(WM0_PIPEA_ILK
, val
|
1875 ((plane_wm
<< WM0_PIPE_PLANE_SHIFT
) | cursor_wm
));
1876 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1877 " plane %d, " "cursor: %d\n",
1878 plane_wm
, cursor_wm
);
1879 enabled
|= 1 << PIPE_A
;
1882 if (g4x_compute_wm0(dev
, PIPE_B
,
1883 &sandybridge_display_wm_info
, latency
,
1884 &sandybridge_cursor_wm_info
, latency
,
1885 &plane_wm
, &cursor_wm
)) {
1886 val
= I915_READ(WM0_PIPEB_ILK
);
1887 val
&= ~(WM0_PIPE_PLANE_MASK
| WM0_PIPE_CURSOR_MASK
);
1888 I915_WRITE(WM0_PIPEB_ILK
, val
|
1889 ((plane_wm
<< WM0_PIPE_PLANE_SHIFT
) | cursor_wm
));
1890 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1891 " plane %d, cursor: %d\n",
1892 plane_wm
, cursor_wm
);
1893 enabled
|= 1 << PIPE_B
;
1897 * Calculate and update the self-refresh watermark only when one
1898 * display plane is used.
1900 * SNB support 3 levels of watermark.
1902 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1903 * and disabled in the descending order
1906 I915_WRITE(WM3_LP_ILK
, 0);
1907 I915_WRITE(WM2_LP_ILK
, 0);
1908 I915_WRITE(WM1_LP_ILK
, 0);
1910 if (!single_plane_enabled(enabled
) ||
1911 dev_priv
->sprite_scaling_enabled
)
1913 enabled
= ffs(enabled
) - 1;
1916 if (!ironlake_compute_srwm(dev
, 1, enabled
,
1917 SNB_READ_WM1_LATENCY() * 500,
1918 &sandybridge_display_srwm_info
,
1919 &sandybridge_cursor_srwm_info
,
1920 &fbc_wm
, &plane_wm
, &cursor_wm
))
1923 I915_WRITE(WM1_LP_ILK
,
1925 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT
) |
1926 (fbc_wm
<< WM1_LP_FBC_SHIFT
) |
1927 (plane_wm
<< WM1_LP_SR_SHIFT
) |
1931 if (!ironlake_compute_srwm(dev
, 2, enabled
,
1932 SNB_READ_WM2_LATENCY() * 500,
1933 &sandybridge_display_srwm_info
,
1934 &sandybridge_cursor_srwm_info
,
1935 &fbc_wm
, &plane_wm
, &cursor_wm
))
1938 I915_WRITE(WM2_LP_ILK
,
1940 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT
) |
1941 (fbc_wm
<< WM1_LP_FBC_SHIFT
) |
1942 (plane_wm
<< WM1_LP_SR_SHIFT
) |
1946 if (!ironlake_compute_srwm(dev
, 3, enabled
,
1947 SNB_READ_WM3_LATENCY() * 500,
1948 &sandybridge_display_srwm_info
,
1949 &sandybridge_cursor_srwm_info
,
1950 &fbc_wm
, &plane_wm
, &cursor_wm
))
1953 I915_WRITE(WM3_LP_ILK
,
1955 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT
) |
1956 (fbc_wm
<< WM1_LP_FBC_SHIFT
) |
1957 (plane_wm
<< WM1_LP_SR_SHIFT
) |
1961 static void ivybridge_update_wm(struct drm_device
*dev
)
1963 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1964 int latency
= SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
1966 int fbc_wm
, plane_wm
, cursor_wm
;
1967 int ignore_fbc_wm
, ignore_plane_wm
, ignore_cursor_wm
;
1968 unsigned int enabled
;
1971 if (g4x_compute_wm0(dev
, PIPE_A
,
1972 &sandybridge_display_wm_info
, latency
,
1973 &sandybridge_cursor_wm_info
, latency
,
1974 &plane_wm
, &cursor_wm
)) {
1975 val
= I915_READ(WM0_PIPEA_ILK
);
1976 val
&= ~(WM0_PIPE_PLANE_MASK
| WM0_PIPE_CURSOR_MASK
);
1977 I915_WRITE(WM0_PIPEA_ILK
, val
|
1978 ((plane_wm
<< WM0_PIPE_PLANE_SHIFT
) | cursor_wm
));
1979 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1980 " plane %d, " "cursor: %d\n",
1981 plane_wm
, cursor_wm
);
1982 enabled
|= 1 << PIPE_A
;
1985 if (g4x_compute_wm0(dev
, PIPE_B
,
1986 &sandybridge_display_wm_info
, latency
,
1987 &sandybridge_cursor_wm_info
, latency
,
1988 &plane_wm
, &cursor_wm
)) {
1989 val
= I915_READ(WM0_PIPEB_ILK
);
1990 val
&= ~(WM0_PIPE_PLANE_MASK
| WM0_PIPE_CURSOR_MASK
);
1991 I915_WRITE(WM0_PIPEB_ILK
, val
|
1992 ((plane_wm
<< WM0_PIPE_PLANE_SHIFT
) | cursor_wm
));
1993 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1994 " plane %d, cursor: %d\n",
1995 plane_wm
, cursor_wm
);
1996 enabled
|= 1 << PIPE_B
;
1999 if (g4x_compute_wm0(dev
, PIPE_C
,
2000 &sandybridge_display_wm_info
, latency
,
2001 &sandybridge_cursor_wm_info
, latency
,
2002 &plane_wm
, &cursor_wm
)) {
2003 val
= I915_READ(WM0_PIPEC_IVB
);
2004 val
&= ~(WM0_PIPE_PLANE_MASK
| WM0_PIPE_CURSOR_MASK
);
2005 I915_WRITE(WM0_PIPEC_IVB
, val
|
2006 ((plane_wm
<< WM0_PIPE_PLANE_SHIFT
) | cursor_wm
));
2007 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
2008 " plane %d, cursor: %d\n",
2009 plane_wm
, cursor_wm
);
2010 enabled
|= 1 << PIPE_C
;
2014 * Calculate and update the self-refresh watermark only when one
2015 * display plane is used.
2017 * SNB support 3 levels of watermark.
2019 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
2020 * and disabled in the descending order
2023 I915_WRITE(WM3_LP_ILK
, 0);
2024 I915_WRITE(WM2_LP_ILK
, 0);
2025 I915_WRITE(WM1_LP_ILK
, 0);
2027 if (!single_plane_enabled(enabled
) ||
2028 dev_priv
->sprite_scaling_enabled
)
2030 enabled
= ffs(enabled
) - 1;
2033 if (!ironlake_compute_srwm(dev
, 1, enabled
,
2034 SNB_READ_WM1_LATENCY() * 500,
2035 &sandybridge_display_srwm_info
,
2036 &sandybridge_cursor_srwm_info
,
2037 &fbc_wm
, &plane_wm
, &cursor_wm
))
2040 I915_WRITE(WM1_LP_ILK
,
2042 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT
) |
2043 (fbc_wm
<< WM1_LP_FBC_SHIFT
) |
2044 (plane_wm
<< WM1_LP_SR_SHIFT
) |
2048 if (!ironlake_compute_srwm(dev
, 2, enabled
,
2049 SNB_READ_WM2_LATENCY() * 500,
2050 &sandybridge_display_srwm_info
,
2051 &sandybridge_cursor_srwm_info
,
2052 &fbc_wm
, &plane_wm
, &cursor_wm
))
2055 I915_WRITE(WM2_LP_ILK
,
2057 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT
) |
2058 (fbc_wm
<< WM1_LP_FBC_SHIFT
) |
2059 (plane_wm
<< WM1_LP_SR_SHIFT
) |
2062 /* WM3, note we have to correct the cursor latency */
2063 if (!ironlake_compute_srwm(dev
, 3, enabled
,
2064 SNB_READ_WM3_LATENCY() * 500,
2065 &sandybridge_display_srwm_info
,
2066 &sandybridge_cursor_srwm_info
,
2067 &fbc_wm
, &plane_wm
, &ignore_cursor_wm
) ||
2068 !ironlake_compute_srwm(dev
, 3, enabled
,
2069 2 * SNB_READ_WM3_LATENCY() * 500,
2070 &sandybridge_display_srwm_info
,
2071 &sandybridge_cursor_srwm_info
,
2072 &ignore_fbc_wm
, &ignore_plane_wm
, &cursor_wm
))
2075 I915_WRITE(WM3_LP_ILK
,
2077 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT
) |
2078 (fbc_wm
<< WM1_LP_FBC_SHIFT
) |
2079 (plane_wm
<< WM1_LP_SR_SHIFT
) |
2083 static uint32_t hsw_wm_get_pixel_rate(struct drm_device
*dev
,
2084 struct drm_crtc
*crtc
)
2086 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2087 uint32_t pixel_rate
, pfit_size
;
2089 pixel_rate
= intel_crtc
->config
.adjusted_mode
.clock
;
2091 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
2092 * adjust the pixel_rate here. */
2094 pfit_size
= intel_crtc
->config
.pch_pfit
.size
;
2096 uint64_t pipe_w
, pipe_h
, pfit_w
, pfit_h
;
2098 pipe_w
= intel_crtc
->config
.requested_mode
.hdisplay
;
2099 pipe_h
= intel_crtc
->config
.requested_mode
.vdisplay
;
2100 pfit_w
= (pfit_size
>> 16) & 0xFFFF;
2101 pfit_h
= pfit_size
& 0xFFFF;
2102 if (pipe_w
< pfit_w
)
2104 if (pipe_h
< pfit_h
)
2107 pixel_rate
= div_u64((uint64_t) pixel_rate
* pipe_w
* pipe_h
,
2114 static uint32_t hsw_wm_method1(uint32_t pixel_rate
, uint8_t bytes_per_pixel
,
2119 ret
= (uint64_t) pixel_rate
* bytes_per_pixel
* latency
;
2120 ret
= DIV_ROUND_UP_ULL(ret
, 64 * 10000) + 2;
2125 static uint32_t hsw_wm_method2(uint32_t pixel_rate
, uint32_t pipe_htotal
,
2126 uint32_t horiz_pixels
, uint8_t bytes_per_pixel
,
2131 ret
= (latency
* pixel_rate
) / (pipe_htotal
* 10000);
2132 ret
= (ret
+ 1) * horiz_pixels
* bytes_per_pixel
;
2133 ret
= DIV_ROUND_UP(ret
, 64) + 2;
2137 static uint32_t hsw_wm_fbc(uint32_t pri_val
, uint32_t horiz_pixels
,
2138 uint8_t bytes_per_pixel
)
2140 return DIV_ROUND_UP(pri_val
* 64, horiz_pixels
* bytes_per_pixel
) + 2;
2143 struct hsw_pipe_wm_parameters
{
2145 bool sprite_enabled
;
2146 uint8_t pri_bytes_per_pixel
;
2147 uint8_t spr_bytes_per_pixel
;
2148 uint8_t cur_bytes_per_pixel
;
2149 uint32_t pri_horiz_pixels
;
2150 uint32_t spr_horiz_pixels
;
2151 uint32_t cur_horiz_pixels
;
2152 uint32_t pipe_htotal
;
2153 uint32_t pixel_rate
;
2156 struct hsw_wm_maximums
{
2163 struct hsw_lp_wm_result
{
2172 struct hsw_wm_values
{
2173 uint32_t wm_pipe
[3];
2175 uint32_t wm_lp_spr
[3];
2176 uint32_t wm_linetime
[3];
2180 enum hsw_data_buf_partitioning
{
2181 HSW_DATA_BUF_PART_1_2
,
2182 HSW_DATA_BUF_PART_5_6
,
2185 /* For both WM_PIPE and WM_LP. */
2186 static uint32_t hsw_compute_pri_wm(struct hsw_pipe_wm_parameters
*params
,
2190 uint32_t method1
, method2
;
2192 /* TODO: for now, assume the primary plane is always enabled. */
2193 if (!params
->active
)
2196 method1
= hsw_wm_method1(params
->pixel_rate
,
2197 params
->pri_bytes_per_pixel
,
2203 method2
= hsw_wm_method2(params
->pixel_rate
,
2204 params
->pipe_htotal
,
2205 params
->pri_horiz_pixels
,
2206 params
->pri_bytes_per_pixel
,
2209 return min(method1
, method2
);
2212 /* For both WM_PIPE and WM_LP. */
2213 static uint32_t hsw_compute_spr_wm(struct hsw_pipe_wm_parameters
*params
,
2216 uint32_t method1
, method2
;
2218 if (!params
->active
|| !params
->sprite_enabled
)
2221 method1
= hsw_wm_method1(params
->pixel_rate
,
2222 params
->spr_bytes_per_pixel
,
2224 method2
= hsw_wm_method2(params
->pixel_rate
,
2225 params
->pipe_htotal
,
2226 params
->spr_horiz_pixels
,
2227 params
->spr_bytes_per_pixel
,
2229 return min(method1
, method2
);
2232 /* For both WM_PIPE and WM_LP. */
2233 static uint32_t hsw_compute_cur_wm(struct hsw_pipe_wm_parameters
*params
,
2236 if (!params
->active
)
2239 return hsw_wm_method2(params
->pixel_rate
,
2240 params
->pipe_htotal
,
2241 params
->cur_horiz_pixels
,
2242 params
->cur_bytes_per_pixel
,
2246 /* Only for WM_LP. */
2247 static uint32_t hsw_compute_fbc_wm(struct hsw_pipe_wm_parameters
*params
,
2251 if (!params
->active
)
2254 return hsw_wm_fbc(pri_val
,
2255 params
->pri_horiz_pixels
,
2256 params
->pri_bytes_per_pixel
);
2259 static bool hsw_compute_lp_wm(uint32_t mem_value
, struct hsw_wm_maximums
*max
,
2260 struct hsw_pipe_wm_parameters
*params
,
2261 struct hsw_lp_wm_result
*result
)
2264 uint32_t pri_val
[3], spr_val
[3], cur_val
[3], fbc_val
[3];
2266 for (pipe
= PIPE_A
; pipe
<= PIPE_C
; pipe
++) {
2267 struct hsw_pipe_wm_parameters
*p
= ¶ms
[pipe
];
2269 pri_val
[pipe
] = hsw_compute_pri_wm(p
, mem_value
, true);
2270 spr_val
[pipe
] = hsw_compute_spr_wm(p
, mem_value
);
2271 cur_val
[pipe
] = hsw_compute_cur_wm(p
, mem_value
);
2272 fbc_val
[pipe
] = hsw_compute_fbc_wm(p
, pri_val
[pipe
], mem_value
);
2275 result
->pri_val
= max3(pri_val
[0], pri_val
[1], pri_val
[2]);
2276 result
->spr_val
= max3(spr_val
[0], spr_val
[1], spr_val
[2]);
2277 result
->cur_val
= max3(cur_val
[0], cur_val
[1], cur_val
[2]);
2278 result
->fbc_val
= max3(fbc_val
[0], fbc_val
[1], fbc_val
[2]);
2280 if (result
->fbc_val
> max
->fbc
) {
2281 result
->fbc_enable
= false;
2282 result
->fbc_val
= 0;
2284 result
->fbc_enable
= true;
2287 result
->enable
= result
->pri_val
<= max
->pri
&&
2288 result
->spr_val
<= max
->spr
&&
2289 result
->cur_val
<= max
->cur
;
2290 return result
->enable
;
2293 static uint32_t hsw_compute_wm_pipe(struct drm_i915_private
*dev_priv
,
2294 uint32_t mem_value
, enum pipe pipe
,
2295 struct hsw_pipe_wm_parameters
*params
)
2297 uint32_t pri_val
, cur_val
, spr_val
;
2299 pri_val
= hsw_compute_pri_wm(params
, mem_value
, false);
2300 spr_val
= hsw_compute_spr_wm(params
, mem_value
);
2301 cur_val
= hsw_compute_cur_wm(params
, mem_value
);
2304 "Primary WM error, mode not supported for pipe %c\n",
2307 "Sprite WM error, mode not supported for pipe %c\n",
2310 "Cursor WM error, mode not supported for pipe %c\n",
2313 return (pri_val
<< WM0_PIPE_PLANE_SHIFT
) |
2314 (spr_val
<< WM0_PIPE_SPRITE_SHIFT
) |
2319 hsw_compute_linetime_wm(struct drm_device
*dev
, struct drm_crtc
*crtc
)
2321 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2322 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2323 struct drm_display_mode
*mode
= &intel_crtc
->config
.adjusted_mode
;
2324 u32 linetime
, ips_linetime
;
2326 if (!intel_crtc_active(crtc
))
2329 /* The WM are computed with base on how long it takes to fill a single
2330 * row at the given clock rate, multiplied by 8.
2332 linetime
= DIV_ROUND_CLOSEST(mode
->htotal
* 1000 * 8, mode
->clock
);
2333 ips_linetime
= DIV_ROUND_CLOSEST(mode
->htotal
* 1000 * 8,
2334 intel_ddi_get_cdclk_freq(dev_priv
));
2336 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime
) |
2337 PIPE_WM_LINETIME_TIME(linetime
);
2340 static void hsw_compute_wm_parameters(struct drm_device
*dev
,
2341 struct hsw_pipe_wm_parameters
*params
,
2343 struct hsw_wm_maximums
*lp_max_1_2
,
2344 struct hsw_wm_maximums
*lp_max_5_6
)
2346 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2347 struct drm_crtc
*crtc
;
2348 struct drm_plane
*plane
;
2349 uint64_t sskpd
= I915_READ64(MCH_SSKPD
);
2351 int pipes_active
= 0, sprites_enabled
= 0;
2353 if ((sskpd
>> 56) & 0xFF)
2354 wm
[0] = (sskpd
>> 56) & 0xFF;
2356 wm
[0] = sskpd
& 0xF;
2357 wm
[1] = ((sskpd
>> 4) & 0xFF) * 5;
2358 wm
[2] = ((sskpd
>> 12) & 0xFF) * 5;
2359 wm
[3] = ((sskpd
>> 20) & 0x1FF) * 5;
2360 wm
[4] = ((sskpd
>> 32) & 0x1FF) * 5;
2362 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
2363 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2364 struct hsw_pipe_wm_parameters
*p
;
2366 pipe
= intel_crtc
->pipe
;
2369 p
->active
= intel_crtc_active(crtc
);
2375 p
->pipe_htotal
= intel_crtc
->config
.adjusted_mode
.htotal
;
2376 p
->pixel_rate
= hsw_wm_get_pixel_rate(dev
, crtc
);
2377 p
->pri_bytes_per_pixel
= crtc
->fb
->bits_per_pixel
/ 8;
2378 p
->cur_bytes_per_pixel
= 4;
2379 p
->pri_horiz_pixels
=
2380 intel_crtc
->config
.requested_mode
.hdisplay
;
2381 p
->cur_horiz_pixels
= 64;
2384 list_for_each_entry(plane
, &dev
->mode_config
.plane_list
, head
) {
2385 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
2386 struct hsw_pipe_wm_parameters
*p
;
2388 pipe
= intel_plane
->pipe
;
2391 p
->sprite_enabled
= intel_plane
->wm
.enable
;
2392 p
->spr_bytes_per_pixel
= intel_plane
->wm
.bytes_per_pixel
;
2393 p
->spr_horiz_pixels
= intel_plane
->wm
.horiz_pixels
;
2395 if (p
->sprite_enabled
)
2399 if (pipes_active
> 1) {
2400 lp_max_1_2
->pri
= lp_max_5_6
->pri
= sprites_enabled
? 128 : 256;
2401 lp_max_1_2
->spr
= lp_max_5_6
->spr
= 128;
2402 lp_max_1_2
->cur
= lp_max_5_6
->cur
= 64;
2404 lp_max_1_2
->pri
= sprites_enabled
? 384 : 768;
2405 lp_max_5_6
->pri
= sprites_enabled
? 128 : 768;
2406 lp_max_1_2
->spr
= 384;
2407 lp_max_5_6
->spr
= 640;
2408 lp_max_1_2
->cur
= lp_max_5_6
->cur
= 255;
2410 lp_max_1_2
->fbc
= lp_max_5_6
->fbc
= 15;
2413 static void hsw_compute_wm_results(struct drm_device
*dev
,
2414 struct hsw_pipe_wm_parameters
*params
,
2416 struct hsw_wm_maximums
*lp_maximums
,
2417 struct hsw_wm_values
*results
)
2419 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2420 struct drm_crtc
*crtc
;
2421 struct hsw_lp_wm_result lp_results
[4] = {};
2423 int level
, max_level
, wm_lp
;
2425 for (level
= 1; level
<= 4; level
++)
2426 if (!hsw_compute_lp_wm(wm
[level
], lp_maximums
, params
,
2427 &lp_results
[level
- 1]))
2429 max_level
= level
- 1;
2431 /* The spec says it is preferred to disable FBC WMs instead of disabling
2433 results
->enable_fbc_wm
= true;
2434 for (level
= 1; level
<= max_level
; level
++) {
2435 if (!lp_results
[level
- 1].fbc_enable
) {
2436 results
->enable_fbc_wm
= false;
2441 memset(results
, 0, sizeof(*results
));
2442 for (wm_lp
= 1; wm_lp
<= 3; wm_lp
++) {
2443 const struct hsw_lp_wm_result
*r
;
2445 level
= (max_level
== 4 && wm_lp
> 1) ? wm_lp
+ 1 : wm_lp
;
2446 if (level
> max_level
)
2449 r
= &lp_results
[level
- 1];
2450 results
->wm_lp
[wm_lp
- 1] = HSW_WM_LP_VAL(level
* 2,
2454 results
->wm_lp_spr
[wm_lp
- 1] = r
->spr_val
;
2458 results
->wm_pipe
[pipe
] = hsw_compute_wm_pipe(dev_priv
, wm
[0],
2462 for_each_pipe(pipe
) {
2463 crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
2464 results
->wm_linetime
[pipe
] = hsw_compute_linetime_wm(dev
, crtc
);
2468 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2469 * case both are at the same level. Prefer r1 in case they're the same. */
2470 static struct hsw_wm_values
*hsw_find_best_result(struct hsw_wm_values
*r1
,
2471 struct hsw_wm_values
*r2
)
2473 int i
, val_r1
= 0, val_r2
= 0;
2475 for (i
= 0; i
< 3; i
++) {
2476 if (r1
->wm_lp
[i
] & WM3_LP_EN
)
2477 val_r1
= r1
->wm_lp
[i
] & WM1_LP_LATENCY_MASK
;
2478 if (r2
->wm_lp
[i
] & WM3_LP_EN
)
2479 val_r2
= r2
->wm_lp
[i
] & WM1_LP_LATENCY_MASK
;
2482 if (val_r1
== val_r2
) {
2483 if (r2
->enable_fbc_wm
&& !r1
->enable_fbc_wm
)
2487 } else if (val_r1
> val_r2
) {
2495 * The spec says we shouldn't write when we don't need, because every write
2496 * causes WMs to be re-evaluated, expending some power.
2498 static void hsw_write_wm_values(struct drm_i915_private
*dev_priv
,
2499 struct hsw_wm_values
*results
,
2500 enum hsw_data_buf_partitioning partitioning
)
2502 struct hsw_wm_values previous
;
2504 enum hsw_data_buf_partitioning prev_partitioning
;
2505 bool prev_enable_fbc_wm
;
2507 previous
.wm_pipe
[0] = I915_READ(WM0_PIPEA_ILK
);
2508 previous
.wm_pipe
[1] = I915_READ(WM0_PIPEB_ILK
);
2509 previous
.wm_pipe
[2] = I915_READ(WM0_PIPEC_IVB
);
2510 previous
.wm_lp
[0] = I915_READ(WM1_LP_ILK
);
2511 previous
.wm_lp
[1] = I915_READ(WM2_LP_ILK
);
2512 previous
.wm_lp
[2] = I915_READ(WM3_LP_ILK
);
2513 previous
.wm_lp_spr
[0] = I915_READ(WM1S_LP_ILK
);
2514 previous
.wm_lp_spr
[1] = I915_READ(WM2S_LP_IVB
);
2515 previous
.wm_lp_spr
[2] = I915_READ(WM3S_LP_IVB
);
2516 previous
.wm_linetime
[0] = I915_READ(PIPE_WM_LINETIME(PIPE_A
));
2517 previous
.wm_linetime
[1] = I915_READ(PIPE_WM_LINETIME(PIPE_B
));
2518 previous
.wm_linetime
[2] = I915_READ(PIPE_WM_LINETIME(PIPE_C
));
2520 prev_partitioning
= (I915_READ(WM_MISC
) & WM_MISC_DATA_PARTITION_5_6
) ?
2521 HSW_DATA_BUF_PART_5_6
: HSW_DATA_BUF_PART_1_2
;
2523 prev_enable_fbc_wm
= !(I915_READ(DISP_ARB_CTL
) & DISP_FBC_WM_DIS
);
2525 if (memcmp(results
->wm_pipe
, previous
.wm_pipe
,
2526 sizeof(results
->wm_pipe
)) == 0 &&
2527 memcmp(results
->wm_lp
, previous
.wm_lp
,
2528 sizeof(results
->wm_lp
)) == 0 &&
2529 memcmp(results
->wm_lp_spr
, previous
.wm_lp_spr
,
2530 sizeof(results
->wm_lp_spr
)) == 0 &&
2531 memcmp(results
->wm_linetime
, previous
.wm_linetime
,
2532 sizeof(results
->wm_linetime
)) == 0 &&
2533 partitioning
== prev_partitioning
&&
2534 results
->enable_fbc_wm
== prev_enable_fbc_wm
)
2537 if (previous
.wm_lp
[2] != 0)
2538 I915_WRITE(WM3_LP_ILK
, 0);
2539 if (previous
.wm_lp
[1] != 0)
2540 I915_WRITE(WM2_LP_ILK
, 0);
2541 if (previous
.wm_lp
[0] != 0)
2542 I915_WRITE(WM1_LP_ILK
, 0);
2544 if (previous
.wm_pipe
[0] != results
->wm_pipe
[0])
2545 I915_WRITE(WM0_PIPEA_ILK
, results
->wm_pipe
[0]);
2546 if (previous
.wm_pipe
[1] != results
->wm_pipe
[1])
2547 I915_WRITE(WM0_PIPEB_ILK
, results
->wm_pipe
[1]);
2548 if (previous
.wm_pipe
[2] != results
->wm_pipe
[2])
2549 I915_WRITE(WM0_PIPEC_IVB
, results
->wm_pipe
[2]);
2551 if (previous
.wm_linetime
[0] != results
->wm_linetime
[0])
2552 I915_WRITE(PIPE_WM_LINETIME(PIPE_A
), results
->wm_linetime
[0]);
2553 if (previous
.wm_linetime
[1] != results
->wm_linetime
[1])
2554 I915_WRITE(PIPE_WM_LINETIME(PIPE_B
), results
->wm_linetime
[1]);
2555 if (previous
.wm_linetime
[2] != results
->wm_linetime
[2])
2556 I915_WRITE(PIPE_WM_LINETIME(PIPE_C
), results
->wm_linetime
[2]);
2558 if (prev_partitioning
!= partitioning
) {
2559 val
= I915_READ(WM_MISC
);
2560 if (partitioning
== HSW_DATA_BUF_PART_1_2
)
2561 val
&= ~WM_MISC_DATA_PARTITION_5_6
;
2563 val
|= WM_MISC_DATA_PARTITION_5_6
;
2564 I915_WRITE(WM_MISC
, val
);
2567 if (prev_enable_fbc_wm
!= results
->enable_fbc_wm
) {
2568 val
= I915_READ(DISP_ARB_CTL
);
2569 if (results
->enable_fbc_wm
)
2570 val
&= ~DISP_FBC_WM_DIS
;
2572 val
|= DISP_FBC_WM_DIS
;
2573 I915_WRITE(DISP_ARB_CTL
, val
);
2576 if (previous
.wm_lp_spr
[0] != results
->wm_lp_spr
[0])
2577 I915_WRITE(WM1S_LP_ILK
, results
->wm_lp_spr
[0]);
2578 if (previous
.wm_lp_spr
[1] != results
->wm_lp_spr
[1])
2579 I915_WRITE(WM2S_LP_IVB
, results
->wm_lp_spr
[1]);
2580 if (previous
.wm_lp_spr
[2] != results
->wm_lp_spr
[2])
2581 I915_WRITE(WM3S_LP_IVB
, results
->wm_lp_spr
[2]);
2583 if (results
->wm_lp
[0] != 0)
2584 I915_WRITE(WM1_LP_ILK
, results
->wm_lp
[0]);
2585 if (results
->wm_lp
[1] != 0)
2586 I915_WRITE(WM2_LP_ILK
, results
->wm_lp
[1]);
2587 if (results
->wm_lp
[2] != 0)
2588 I915_WRITE(WM3_LP_ILK
, results
->wm_lp
[2]);
2591 static void haswell_update_wm(struct drm_device
*dev
)
2593 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2594 struct hsw_wm_maximums lp_max_1_2
, lp_max_5_6
;
2595 struct hsw_pipe_wm_parameters params
[3];
2596 struct hsw_wm_values results_1_2
, results_5_6
, *best_results
;
2598 enum hsw_data_buf_partitioning partitioning
;
2600 hsw_compute_wm_parameters(dev
, params
, wm
, &lp_max_1_2
, &lp_max_5_6
);
2602 hsw_compute_wm_results(dev
, params
, wm
, &lp_max_1_2
, &results_1_2
);
2603 if (lp_max_1_2
.pri
!= lp_max_5_6
.pri
) {
2604 hsw_compute_wm_results(dev
, params
, wm
, &lp_max_5_6
,
2606 best_results
= hsw_find_best_result(&results_1_2
, &results_5_6
);
2608 best_results
= &results_1_2
;
2611 partitioning
= (best_results
== &results_1_2
) ?
2612 HSW_DATA_BUF_PART_1_2
: HSW_DATA_BUF_PART_5_6
;
2614 hsw_write_wm_values(dev_priv
, best_results
, partitioning
);
2617 static void haswell_update_sprite_wm(struct drm_device
*dev
, int pipe
,
2618 uint32_t sprite_width
, int pixel_size
,
2621 struct drm_plane
*plane
;
2623 list_for_each_entry(plane
, &dev
->mode_config
.plane_list
, head
) {
2624 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
2626 if (intel_plane
->pipe
== pipe
) {
2627 intel_plane
->wm
.enable
= enable
;
2628 intel_plane
->wm
.horiz_pixels
= sprite_width
+ 1;
2629 intel_plane
->wm
.bytes_per_pixel
= pixel_size
;
2634 haswell_update_wm(dev
);
2638 sandybridge_compute_sprite_wm(struct drm_device
*dev
, int plane
,
2639 uint32_t sprite_width
, int pixel_size
,
2640 const struct intel_watermark_params
*display
,
2641 int display_latency_ns
, int *sprite_wm
)
2643 struct drm_crtc
*crtc
;
2645 int entries
, tlb_miss
;
2647 crtc
= intel_get_crtc_for_plane(dev
, plane
);
2648 if (!intel_crtc_active(crtc
)) {
2649 *sprite_wm
= display
->guard_size
;
2653 clock
= crtc
->mode
.clock
;
2655 /* Use the small buffer method to calculate the sprite watermark */
2656 entries
= ((clock
* pixel_size
/ 1000) * display_latency_ns
) / 1000;
2657 tlb_miss
= display
->fifo_size
*display
->cacheline_size
-
2660 entries
+= tlb_miss
;
2661 entries
= DIV_ROUND_UP(entries
, display
->cacheline_size
);
2662 *sprite_wm
= entries
+ display
->guard_size
;
2663 if (*sprite_wm
> (int)display
->max_wm
)
2664 *sprite_wm
= display
->max_wm
;
2670 sandybridge_compute_sprite_srwm(struct drm_device
*dev
, int plane
,
2671 uint32_t sprite_width
, int pixel_size
,
2672 const struct intel_watermark_params
*display
,
2673 int latency_ns
, int *sprite_wm
)
2675 struct drm_crtc
*crtc
;
2676 unsigned long line_time_us
;
2678 int line_count
, line_size
;
2687 crtc
= intel_get_crtc_for_plane(dev
, plane
);
2688 clock
= crtc
->mode
.clock
;
2694 line_time_us
= (sprite_width
* 1000) / clock
;
2695 if (!line_time_us
) {
2700 line_count
= (latency_ns
/ line_time_us
+ 1000) / 1000;
2701 line_size
= sprite_width
* pixel_size
;
2703 /* Use the minimum of the small and large buffer method for primary */
2704 small
= ((clock
* pixel_size
/ 1000) * latency_ns
) / 1000;
2705 large
= line_count
* line_size
;
2707 entries
= DIV_ROUND_UP(min(small
, large
), display
->cacheline_size
);
2708 *sprite_wm
= entries
+ display
->guard_size
;
2710 return *sprite_wm
> 0x3ff ? false : true;
2713 static void sandybridge_update_sprite_wm(struct drm_device
*dev
, int pipe
,
2714 uint32_t sprite_width
, int pixel_size
,
2717 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2718 int latency
= SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
2728 reg
= WM0_PIPEA_ILK
;
2731 reg
= WM0_PIPEB_ILK
;
2734 reg
= WM0_PIPEC_IVB
;
2737 return; /* bad pipe */
2740 ret
= sandybridge_compute_sprite_wm(dev
, pipe
, sprite_width
, pixel_size
,
2741 &sandybridge_display_wm_info
,
2742 latency
, &sprite_wm
);
2744 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %c\n",
2749 val
= I915_READ(reg
);
2750 val
&= ~WM0_PIPE_SPRITE_MASK
;
2751 I915_WRITE(reg
, val
| (sprite_wm
<< WM0_PIPE_SPRITE_SHIFT
));
2752 DRM_DEBUG_KMS("sprite watermarks For pipe %c - %d\n", pipe_name(pipe
), sprite_wm
);
2755 ret
= sandybridge_compute_sprite_srwm(dev
, pipe
, sprite_width
,
2757 &sandybridge_display_srwm_info
,
2758 SNB_READ_WM1_LATENCY() * 500,
2761 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %c\n",
2765 I915_WRITE(WM1S_LP_ILK
, sprite_wm
);
2767 /* Only IVB has two more LP watermarks for sprite */
2768 if (!IS_IVYBRIDGE(dev
))
2771 ret
= sandybridge_compute_sprite_srwm(dev
, pipe
, sprite_width
,
2773 &sandybridge_display_srwm_info
,
2774 SNB_READ_WM2_LATENCY() * 500,
2777 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %c\n",
2781 I915_WRITE(WM2S_LP_IVB
, sprite_wm
);
2783 ret
= sandybridge_compute_sprite_srwm(dev
, pipe
, sprite_width
,
2785 &sandybridge_display_srwm_info
,
2786 SNB_READ_WM3_LATENCY() * 500,
2789 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %c\n",
2793 I915_WRITE(WM3S_LP_IVB
, sprite_wm
);
2797 * intel_update_watermarks - update FIFO watermark values based on current modes
2799 * Calculate watermark values for the various WM regs based on current mode
2800 * and plane configuration.
2802 * There are several cases to deal with here:
2803 * - normal (i.e. non-self-refresh)
2804 * - self-refresh (SR) mode
2805 * - lines are large relative to FIFO size (buffer can hold up to 2)
2806 * - lines are small relative to FIFO size (buffer can hold more than 2
2807 * lines), so need to account for TLB latency
2809 * The normal calculation is:
2810 * watermark = dotclock * bytes per pixel * latency
2811 * where latency is platform & configuration dependent (we assume pessimal
2814 * The SR calculation is:
2815 * watermark = (trunc(latency/line time)+1) * surface width *
2818 * line time = htotal / dotclock
2819 * surface width = hdisplay for normal plane and 64 for cursor
2820 * and latency is assumed to be high, as above.
2822 * The final value programmed to the register should always be rounded up,
2823 * and include an extra 2 entries to account for clock crossings.
2825 * We don't use the sprite, so we can ignore that. And on Crestline we have
2826 * to set the non-SR watermarks to 8.
2828 void intel_update_watermarks(struct drm_device
*dev
)
2830 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2832 if (dev_priv
->display
.update_wm
)
2833 dev_priv
->display
.update_wm(dev
);
2836 void intel_update_sprite_watermarks(struct drm_device
*dev
, int pipe
,
2837 uint32_t sprite_width
, int pixel_size
,
2840 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2842 if (dev_priv
->display
.update_sprite_wm
)
2843 dev_priv
->display
.update_sprite_wm(dev
, pipe
, sprite_width
,
2844 pixel_size
, enable
);
2847 static struct drm_i915_gem_object
*
2848 intel_alloc_context_page(struct drm_device
*dev
)
2850 struct drm_i915_gem_object
*ctx
;
2853 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
2855 ctx
= i915_gem_alloc_object(dev
, 4096);
2857 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
2861 ret
= i915_gem_object_pin(ctx
, 4096, true, false);
2863 DRM_ERROR("failed to pin power context: %d\n", ret
);
2867 ret
= i915_gem_object_set_to_gtt_domain(ctx
, 1);
2869 DRM_ERROR("failed to set-domain on power context: %d\n", ret
);
2876 i915_gem_object_unpin(ctx
);
2878 drm_gem_object_unreference(&ctx
->base
);
2883 * Lock protecting IPS related data structures
2885 DEFINE_SPINLOCK(mchdev_lock
);
2887 /* Global for IPS driver to get at the current i915 device. Protected by
2889 static struct drm_i915_private
*i915_mch_dev
;
2891 bool ironlake_set_drps(struct drm_device
*dev
, u8 val
)
2893 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2896 assert_spin_locked(&mchdev_lock
);
2898 rgvswctl
= I915_READ16(MEMSWCTL
);
2899 if (rgvswctl
& MEMCTL_CMD_STS
) {
2900 DRM_DEBUG("gpu busy, RCS change rejected\n");
2901 return false; /* still busy with another command */
2904 rgvswctl
= (MEMCTL_CMD_CHFREQ
<< MEMCTL_CMD_SHIFT
) |
2905 (val
<< MEMCTL_FREQ_SHIFT
) | MEMCTL_SFCAVM
;
2906 I915_WRITE16(MEMSWCTL
, rgvswctl
);
2907 POSTING_READ16(MEMSWCTL
);
2909 rgvswctl
|= MEMCTL_CMD_STS
;
2910 I915_WRITE16(MEMSWCTL
, rgvswctl
);
2915 static void ironlake_enable_drps(struct drm_device
*dev
)
2917 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2918 u32 rgvmodectl
= I915_READ(MEMMODECTL
);
2919 u8 fmax
, fmin
, fstart
, vstart
;
2921 spin_lock_irq(&mchdev_lock
);
2923 /* Enable temp reporting */
2924 I915_WRITE16(PMMISC
, I915_READ(PMMISC
) | MCPPCE_EN
);
2925 I915_WRITE16(TSC1
, I915_READ(TSC1
) | TSE
);
2927 /* 100ms RC evaluation intervals */
2928 I915_WRITE(RCUPEI
, 100000);
2929 I915_WRITE(RCDNEI
, 100000);
2931 /* Set max/min thresholds to 90ms and 80ms respectively */
2932 I915_WRITE(RCBMAXAVG
, 90000);
2933 I915_WRITE(RCBMINAVG
, 80000);
2935 I915_WRITE(MEMIHYST
, 1);
2937 /* Set up min, max, and cur for interrupt handling */
2938 fmax
= (rgvmodectl
& MEMMODE_FMAX_MASK
) >> MEMMODE_FMAX_SHIFT
;
2939 fmin
= (rgvmodectl
& MEMMODE_FMIN_MASK
);
2940 fstart
= (rgvmodectl
& MEMMODE_FSTART_MASK
) >>
2941 MEMMODE_FSTART_SHIFT
;
2943 vstart
= (I915_READ(PXVFREQ_BASE
+ (fstart
* 4)) & PXVFREQ_PX_MASK
) >>
2946 dev_priv
->ips
.fmax
= fmax
; /* IPS callback will increase this */
2947 dev_priv
->ips
.fstart
= fstart
;
2949 dev_priv
->ips
.max_delay
= fstart
;
2950 dev_priv
->ips
.min_delay
= fmin
;
2951 dev_priv
->ips
.cur_delay
= fstart
;
2953 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
2954 fmax
, fmin
, fstart
);
2956 I915_WRITE(MEMINTREN
, MEMINT_CX_SUPR_EN
| MEMINT_EVAL_CHG_EN
);
2959 * Interrupts will be enabled in ironlake_irq_postinstall
2962 I915_WRITE(VIDSTART
, vstart
);
2963 POSTING_READ(VIDSTART
);
2965 rgvmodectl
|= MEMMODE_SWMODE_EN
;
2966 I915_WRITE(MEMMODECTL
, rgvmodectl
);
2968 if (wait_for_atomic((I915_READ(MEMSWCTL
) & MEMCTL_CMD_STS
) == 0, 10))
2969 DRM_ERROR("stuck trying to change perf mode\n");
2972 ironlake_set_drps(dev
, fstart
);
2974 dev_priv
->ips
.last_count1
= I915_READ(0x112e4) + I915_READ(0x112e8) +
2976 dev_priv
->ips
.last_time1
= jiffies_to_msecs(jiffies
);
2977 dev_priv
->ips
.last_count2
= I915_READ(0x112f4);
2978 getrawmonotonic(&dev_priv
->ips
.last_time2
);
2980 spin_unlock_irq(&mchdev_lock
);
2983 static void ironlake_disable_drps(struct drm_device
*dev
)
2985 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2988 spin_lock_irq(&mchdev_lock
);
2990 rgvswctl
= I915_READ16(MEMSWCTL
);
2992 /* Ack interrupts, disable EFC interrupt */
2993 I915_WRITE(MEMINTREN
, I915_READ(MEMINTREN
) & ~MEMINT_EVAL_CHG_EN
);
2994 I915_WRITE(MEMINTRSTS
, MEMINT_EVAL_CHG
);
2995 I915_WRITE(DEIER
, I915_READ(DEIER
) & ~DE_PCU_EVENT
);
2996 I915_WRITE(DEIIR
, DE_PCU_EVENT
);
2997 I915_WRITE(DEIMR
, I915_READ(DEIMR
) | DE_PCU_EVENT
);
2999 /* Go back to the starting frequency */
3000 ironlake_set_drps(dev
, dev_priv
->ips
.fstart
);
3002 rgvswctl
|= MEMCTL_CMD_STS
;
3003 I915_WRITE(MEMSWCTL
, rgvswctl
);
3006 spin_unlock_irq(&mchdev_lock
);
3009 /* There's a funny hw issue where the hw returns all 0 when reading from
3010 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3011 * ourselves, instead of doing a rmw cycle (which might result in us clearing
3012 * all limits and the gpu stuck at whatever frequency it is at atm).
3014 static u32
gen6_rps_limits(struct drm_i915_private
*dev_priv
, u8
*val
)
3020 if (*val
>= dev_priv
->rps
.max_delay
)
3021 *val
= dev_priv
->rps
.max_delay
;
3022 limits
|= dev_priv
->rps
.max_delay
<< 24;
3024 /* Only set the down limit when we've reached the lowest level to avoid
3025 * getting more interrupts, otherwise leave this clear. This prevents a
3026 * race in the hw when coming out of rc6: There's a tiny window where
3027 * the hw runs at the minimal clock before selecting the desired
3028 * frequency, if the down threshold expires in that window we will not
3029 * receive a down interrupt. */
3030 if (*val
<= dev_priv
->rps
.min_delay
) {
3031 *val
= dev_priv
->rps
.min_delay
;
3032 limits
|= dev_priv
->rps
.min_delay
<< 16;
3038 void gen6_set_rps(struct drm_device
*dev
, u8 val
)
3040 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3041 u32 limits
= gen6_rps_limits(dev_priv
, &val
);
3043 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
3044 WARN_ON(val
> dev_priv
->rps
.max_delay
);
3045 WARN_ON(val
< dev_priv
->rps
.min_delay
);
3047 if (val
== dev_priv
->rps
.cur_delay
)
3050 if (IS_HASWELL(dev
))
3051 I915_WRITE(GEN6_RPNSWREQ
,
3052 HSW_FREQUENCY(val
));
3054 I915_WRITE(GEN6_RPNSWREQ
,
3055 GEN6_FREQUENCY(val
) |
3057 GEN6_AGGRESSIVE_TURBO
);
3059 /* Make sure we continue to get interrupts
3060 * until we hit the minimum or maximum frequencies.
3062 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS
, limits
);
3064 POSTING_READ(GEN6_RPNSWREQ
);
3066 dev_priv
->rps
.cur_delay
= val
;
3068 trace_intel_gpu_freq_change(val
* 50);
3072 * Wait until the previous freq change has completed,
3073 * or the timeout elapsed, and then update our notion
3074 * of the current GPU frequency.
3076 static void vlv_update_rps_cur_delay(struct drm_i915_private
*dev_priv
)
3078 unsigned long timeout
= jiffies
+ msecs_to_jiffies(10);
3081 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
3084 pval
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
3085 if (time_after(jiffies
, timeout
)) {
3086 DRM_DEBUG_DRIVER("timed out waiting for Punit\n");
3094 if (pval
!= dev_priv
->rps
.cur_delay
)
3095 DRM_DEBUG_DRIVER("Punit overrode GPU freq: %d MHz (%u) requested, but got %d Mhz (%u)\n",
3096 vlv_gpu_freq(dev_priv
->mem_freq
, dev_priv
->rps
.cur_delay
),
3097 dev_priv
->rps
.cur_delay
,
3098 vlv_gpu_freq(dev_priv
->mem_freq
, pval
), pval
);
3100 dev_priv
->rps
.cur_delay
= pval
;
3103 void valleyview_set_rps(struct drm_device
*dev
, u8 val
)
3105 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3107 gen6_rps_limits(dev_priv
, &val
);
3109 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
3110 WARN_ON(val
> dev_priv
->rps
.max_delay
);
3111 WARN_ON(val
< dev_priv
->rps
.min_delay
);
3113 vlv_update_rps_cur_delay(dev_priv
);
3115 DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
3116 vlv_gpu_freq(dev_priv
->mem_freq
,
3117 dev_priv
->rps
.cur_delay
),
3118 dev_priv
->rps
.cur_delay
,
3119 vlv_gpu_freq(dev_priv
->mem_freq
, val
), val
);
3121 if (val
== dev_priv
->rps
.cur_delay
)
3124 vlv_punit_write(dev_priv
, PUNIT_REG_GPU_FREQ_REQ
, val
);
3126 dev_priv
->rps
.cur_delay
= val
;
3128 trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv
->mem_freq
, val
));
3132 static void gen6_disable_rps(struct drm_device
*dev
)
3134 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3136 I915_WRITE(GEN6_RC_CONTROL
, 0);
3137 I915_WRITE(GEN6_RPNSWREQ
, 1 << 31);
3138 I915_WRITE(GEN6_PMINTRMSK
, 0xffffffff);
3139 I915_WRITE(GEN6_PMIER
, I915_READ(GEN6_PMIER
) & ~GEN6_PM_RPS_EVENTS
);
3140 /* Complete PM interrupt masking here doesn't race with the rps work
3141 * item again unmasking PM interrupts because that is using a different
3142 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3143 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3145 spin_lock_irq(&dev_priv
->rps
.lock
);
3146 dev_priv
->rps
.pm_iir
= 0;
3147 spin_unlock_irq(&dev_priv
->rps
.lock
);
3149 I915_WRITE(GEN6_PMIIR
, GEN6_PM_RPS_EVENTS
);
3152 static void valleyview_disable_rps(struct drm_device
*dev
)
3154 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3156 I915_WRITE(GEN6_RC_CONTROL
, 0);
3157 I915_WRITE(GEN6_PMINTRMSK
, 0xffffffff);
3158 I915_WRITE(GEN6_PMIER
, 0);
3159 /* Complete PM interrupt masking here doesn't race with the rps work
3160 * item again unmasking PM interrupts because that is using a different
3161 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3162 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3164 spin_lock_irq(&dev_priv
->rps
.lock
);
3165 dev_priv
->rps
.pm_iir
= 0;
3166 spin_unlock_irq(&dev_priv
->rps
.lock
);
3168 I915_WRITE(GEN6_PMIIR
, I915_READ(GEN6_PMIIR
));
3170 if (dev_priv
->vlv_pctx
) {
3171 drm_gem_object_unreference(&dev_priv
->vlv_pctx
->base
);
3172 dev_priv
->vlv_pctx
= NULL
;
3176 int intel_enable_rc6(const struct drm_device
*dev
)
3178 /* Respect the kernel parameter if it is set */
3179 if (i915_enable_rc6
>= 0)
3180 return i915_enable_rc6
;
3182 /* Disable RC6 on Ironlake */
3183 if (INTEL_INFO(dev
)->gen
== 5)
3186 if (IS_HASWELL(dev
)) {
3187 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
3188 return INTEL_RC6_ENABLE
;
3191 /* snb/ivb have more than one rc6 state. */
3192 if (INTEL_INFO(dev
)->gen
== 6) {
3193 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
3194 return INTEL_RC6_ENABLE
;
3197 DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n");
3198 return (INTEL_RC6_ENABLE
| INTEL_RC6p_ENABLE
);
3201 static void gen6_enable_rps(struct drm_device
*dev
)
3203 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3204 struct intel_ring_buffer
*ring
;
3207 u32 rc6vids
, pcu_mbox
, rc6_mask
= 0;
3212 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
3214 /* Here begins a magic sequence of register writes to enable
3215 * auto-downclocking.
3217 * Perhaps there might be some value in exposing these to
3220 I915_WRITE(GEN6_RC_STATE
, 0);
3222 /* Clear the DBG now so we don't confuse earlier errors */
3223 if ((gtfifodbg
= I915_READ(GTFIFODBG
))) {
3224 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg
);
3225 I915_WRITE(GTFIFODBG
, gtfifodbg
);
3228 gen6_gt_force_wake_get(dev_priv
);
3230 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
3231 gt_perf_status
= I915_READ(GEN6_GT_PERF_STATUS
);
3233 /* In units of 50MHz */
3234 dev_priv
->rps
.hw_max
= dev_priv
->rps
.max_delay
= rp_state_cap
& 0xff;
3235 dev_priv
->rps
.min_delay
= (rp_state_cap
& 0xff0000) >> 16;
3236 dev_priv
->rps
.cur_delay
= 0;
3238 /* disable the counters and set deterministic thresholds */
3239 I915_WRITE(GEN6_RC_CONTROL
, 0);
3241 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT
, 1000 << 16);
3242 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 40 << 16 | 30);
3243 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT
, 30);
3244 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000);
3245 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25);
3247 for_each_ring(ring
, dev_priv
, i
)
3248 I915_WRITE(RING_MAX_IDLE(ring
->mmio_base
), 10);
3250 I915_WRITE(GEN6_RC_SLEEP
, 0);
3251 I915_WRITE(GEN6_RC1e_THRESHOLD
, 1000);
3252 I915_WRITE(GEN6_RC6_THRESHOLD
, 50000);
3253 I915_WRITE(GEN6_RC6p_THRESHOLD
, 150000);
3254 I915_WRITE(GEN6_RC6pp_THRESHOLD
, 64000); /* unused */
3256 /* Check if we are enabling RC6 */
3257 rc6_mode
= intel_enable_rc6(dev_priv
->dev
);
3258 if (rc6_mode
& INTEL_RC6_ENABLE
)
3259 rc6_mask
|= GEN6_RC_CTL_RC6_ENABLE
;
3261 /* We don't use those on Haswell */
3262 if (!IS_HASWELL(dev
)) {
3263 if (rc6_mode
& INTEL_RC6p_ENABLE
)
3264 rc6_mask
|= GEN6_RC_CTL_RC6p_ENABLE
;
3266 if (rc6_mode
& INTEL_RC6pp_ENABLE
)
3267 rc6_mask
|= GEN6_RC_CTL_RC6pp_ENABLE
;
3270 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
3271 (rc6_mask
& GEN6_RC_CTL_RC6_ENABLE
) ? "on" : "off",
3272 (rc6_mask
& GEN6_RC_CTL_RC6p_ENABLE
) ? "on" : "off",
3273 (rc6_mask
& GEN6_RC_CTL_RC6pp_ENABLE
) ? "on" : "off");
3275 I915_WRITE(GEN6_RC_CONTROL
,
3277 GEN6_RC_CTL_EI_MODE(1) |
3278 GEN6_RC_CTL_HW_ENABLE
);
3280 if (IS_HASWELL(dev
)) {
3281 I915_WRITE(GEN6_RPNSWREQ
,
3283 I915_WRITE(GEN6_RC_VIDEO_FREQ
,
3286 I915_WRITE(GEN6_RPNSWREQ
,
3287 GEN6_FREQUENCY(10) |
3289 GEN6_AGGRESSIVE_TURBO
);
3290 I915_WRITE(GEN6_RC_VIDEO_FREQ
,
3291 GEN6_FREQUENCY(12));
3294 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 1000000);
3295 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS
,
3296 dev_priv
->rps
.max_delay
<< 24 |
3297 dev_priv
->rps
.min_delay
<< 16);
3299 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 59400);
3300 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 245000);
3301 I915_WRITE(GEN6_RP_UP_EI
, 66000);
3302 I915_WRITE(GEN6_RP_DOWN_EI
, 350000);
3304 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
3305 I915_WRITE(GEN6_RP_CONTROL
,
3306 GEN6_RP_MEDIA_TURBO
|
3307 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
3308 GEN6_RP_MEDIA_IS_GFX
|
3310 GEN6_RP_UP_BUSY_AVG
|
3311 (IS_HASWELL(dev
) ? GEN7_RP_DOWN_IDLE_AVG
: GEN6_RP_DOWN_IDLE_CONT
));
3313 ret
= sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_MIN_FREQ_TABLE
, 0);
3316 ret
= sandybridge_pcode_read(dev_priv
, GEN6_READ_OC_PARAMS
, &pcu_mbox
);
3317 if (!ret
&& (pcu_mbox
& (1<<31))) { /* OC supported */
3318 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
3319 (dev_priv
->rps
.max_delay
& 0xff) * 50,
3320 (pcu_mbox
& 0xff) * 50);
3321 dev_priv
->rps
.hw_max
= pcu_mbox
& 0xff;
3324 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
3327 gen6_set_rps(dev_priv
->dev
, (gt_perf_status
& 0xff00) >> 8);
3329 /* requires MSI enabled */
3330 I915_WRITE(GEN6_PMIER
, I915_READ(GEN6_PMIER
) | GEN6_PM_RPS_EVENTS
);
3331 spin_lock_irq(&dev_priv
->rps
.lock
);
3332 /* FIXME: Our interrupt enabling sequence is bonghits.
3333 * dev_priv->rps.pm_iir really should be 0 here. */
3334 dev_priv
->rps
.pm_iir
= 0;
3335 I915_WRITE(GEN6_PMIMR
, I915_READ(GEN6_PMIMR
) & ~GEN6_PM_RPS_EVENTS
);
3336 I915_WRITE(GEN6_PMIIR
, GEN6_PM_RPS_EVENTS
);
3337 spin_unlock_irq(&dev_priv
->rps
.lock
);
3338 /* unmask all PM interrupts */
3339 I915_WRITE(GEN6_PMINTRMSK
, 0);
3342 ret
= sandybridge_pcode_read(dev_priv
, GEN6_PCODE_READ_RC6VIDS
, &rc6vids
);
3343 if (IS_GEN6(dev
) && ret
) {
3344 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
3345 } else if (IS_GEN6(dev
) && (GEN6_DECODE_RC6_VID(rc6vids
& 0xff) < 450)) {
3346 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
3347 GEN6_DECODE_RC6_VID(rc6vids
& 0xff), 450);
3348 rc6vids
&= 0xffff00;
3349 rc6vids
|= GEN6_ENCODE_RC6_VID(450);
3350 ret
= sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_RC6VIDS
, rc6vids
);
3352 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
3355 gen6_gt_force_wake_put(dev_priv
);
3358 static void gen6_update_ring_freq(struct drm_device
*dev
)
3360 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3362 unsigned int gpu_freq
;
3363 unsigned int max_ia_freq
, min_ring_freq
;
3364 int scaling_factor
= 180;
3366 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
3368 max_ia_freq
= cpufreq_quick_get_max(0);
3370 * Default to measured freq if none found, PCU will ensure we don't go
3374 max_ia_freq
= tsc_khz
;
3376 /* Convert from kHz to MHz */
3377 max_ia_freq
/= 1000;
3379 min_ring_freq
= I915_READ(MCHBAR_MIRROR_BASE_SNB
+ DCLK
);
3380 /* convert DDR frequency from units of 133.3MHz to bandwidth */
3381 min_ring_freq
= (2 * 4 * min_ring_freq
+ 2) / 3;
3384 * For each potential GPU frequency, load a ring frequency we'd like
3385 * to use for memory access. We do this by specifying the IA frequency
3386 * the PCU should use as a reference to determine the ring frequency.
3388 for (gpu_freq
= dev_priv
->rps
.max_delay
; gpu_freq
>= dev_priv
->rps
.min_delay
;
3390 int diff
= dev_priv
->rps
.max_delay
- gpu_freq
;
3391 unsigned int ia_freq
= 0, ring_freq
= 0;
3393 if (IS_HASWELL(dev
)) {
3394 ring_freq
= (gpu_freq
* 5 + 3) / 4;
3395 ring_freq
= max(min_ring_freq
, ring_freq
);
3396 /* leave ia_freq as the default, chosen by cpufreq */
3398 /* On older processors, there is no separate ring
3399 * clock domain, so in order to boost the bandwidth
3400 * of the ring, we need to upclock the CPU (ia_freq).
3402 * For GPU frequencies less than 750MHz,
3403 * just use the lowest ring freq.
3405 if (gpu_freq
< min_freq
)
3408 ia_freq
= max_ia_freq
- ((diff
* scaling_factor
) / 2);
3409 ia_freq
= DIV_ROUND_CLOSEST(ia_freq
, 100);
3412 sandybridge_pcode_write(dev_priv
,
3413 GEN6_PCODE_WRITE_MIN_FREQ_TABLE
,
3414 ia_freq
<< GEN6_PCODE_FREQ_IA_RATIO_SHIFT
|
3415 ring_freq
<< GEN6_PCODE_FREQ_RING_RATIO_SHIFT
|
3420 int valleyview_rps_max_freq(struct drm_i915_private
*dev_priv
)
3424 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FREQ_FUSE
);
3426 rp0
= (val
& FB_GFX_MAX_FREQ_FUSE_MASK
) >> FB_GFX_MAX_FREQ_FUSE_SHIFT
;
3428 rp0
= min_t(u32
, rp0
, 0xea);
3433 static int valleyview_rps_rpe_freq(struct drm_i915_private
*dev_priv
)
3437 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FMAX_FUSE_LO
);
3438 rpe
= (val
& FB_FMAX_VMIN_FREQ_LO_MASK
) >> FB_FMAX_VMIN_FREQ_LO_SHIFT
;
3439 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FMAX_FUSE_HI
);
3440 rpe
|= (val
& FB_FMAX_VMIN_FREQ_HI_MASK
) << 5;
3445 int valleyview_rps_min_freq(struct drm_i915_private
*dev_priv
)
3447 return vlv_punit_read(dev_priv
, PUNIT_REG_GPU_LFM
) & 0xff;
3450 static void vlv_rps_timer_work(struct work_struct
*work
)
3452 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
3456 * Timer fired, we must be idle. Drop to min voltage state.
3457 * Note: we use RPe here since it should match the
3458 * Vmin we were shooting for. That should give us better
3459 * perf when we come back out of RC6 than if we used the
3460 * min freq available.
3462 mutex_lock(&dev_priv
->rps
.hw_lock
);
3463 if (dev_priv
->rps
.cur_delay
> dev_priv
->rps
.rpe_delay
)
3464 valleyview_set_rps(dev_priv
->dev
, dev_priv
->rps
.rpe_delay
);
3465 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3468 static void valleyview_setup_pctx(struct drm_device
*dev
)
3470 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3471 struct drm_i915_gem_object
*pctx
;
3472 unsigned long pctx_paddr
;
3474 int pctx_size
= 24*1024;
3476 pcbr
= I915_READ(VLV_PCBR
);
3478 /* BIOS set it up already, grab the pre-alloc'd space */
3481 pcbr_offset
= (pcbr
& (~4095)) - dev_priv
->mm
.stolen_base
;
3482 pctx
= i915_gem_object_create_stolen_for_preallocated(dev_priv
->dev
,
3490 * From the Gunit register HAS:
3491 * The Gfx driver is expected to program this register and ensure
3492 * proper allocation within Gfx stolen memory. For example, this
3493 * register should be programmed such than the PCBR range does not
3494 * overlap with other ranges, such as the frame buffer, protected
3495 * memory, or any other relevant ranges.
3497 pctx
= i915_gem_object_create_stolen(dev
, pctx_size
);
3499 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
3503 pctx_paddr
= dev_priv
->mm
.stolen_base
+ pctx
->stolen
->start
;
3504 I915_WRITE(VLV_PCBR
, pctx_paddr
);
3507 dev_priv
->vlv_pctx
= pctx
;
3510 static void valleyview_enable_rps(struct drm_device
*dev
)
3512 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3513 struct intel_ring_buffer
*ring
;
3517 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
3519 if ((gtfifodbg
= I915_READ(GTFIFODBG
))) {
3520 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg
);
3521 I915_WRITE(GTFIFODBG
, gtfifodbg
);
3524 valleyview_setup_pctx(dev
);
3526 gen6_gt_force_wake_get(dev_priv
);
3528 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 59400);
3529 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 245000);
3530 I915_WRITE(GEN6_RP_UP_EI
, 66000);
3531 I915_WRITE(GEN6_RP_DOWN_EI
, 350000);
3533 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
3535 I915_WRITE(GEN6_RP_CONTROL
,
3536 GEN6_RP_MEDIA_TURBO
|
3537 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
3538 GEN6_RP_MEDIA_IS_GFX
|
3540 GEN6_RP_UP_BUSY_AVG
|
3541 GEN6_RP_DOWN_IDLE_CONT
);
3543 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 0x00280000);
3544 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000);
3545 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25);
3547 for_each_ring(ring
, dev_priv
, i
)
3548 I915_WRITE(RING_MAX_IDLE(ring
->mmio_base
), 10);
3550 I915_WRITE(GEN6_RC6_THRESHOLD
, 0xc350);
3552 /* allows RC6 residency counter to work */
3553 I915_WRITE(0x138104, _MASKED_BIT_ENABLE(0x3));
3554 I915_WRITE(GEN6_RC_CONTROL
,
3555 GEN7_RC_CTL_TO_MODE
);
3557 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
3558 switch ((val
>> 6) & 3) {
3561 dev_priv
->mem_freq
= 800;
3564 dev_priv
->mem_freq
= 1066;
3567 dev_priv
->mem_freq
= 1333;
3570 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv
->mem_freq
);
3572 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val
& 0x10 ? "yes" : "no");
3573 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val
);
3575 dev_priv
->rps
.cur_delay
= (val
>> 8) & 0xff;
3576 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
3577 vlv_gpu_freq(dev_priv
->mem_freq
,
3578 dev_priv
->rps
.cur_delay
),
3579 dev_priv
->rps
.cur_delay
);
3581 dev_priv
->rps
.max_delay
= valleyview_rps_max_freq(dev_priv
);
3582 dev_priv
->rps
.hw_max
= dev_priv
->rps
.max_delay
;
3583 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
3584 vlv_gpu_freq(dev_priv
->mem_freq
,
3585 dev_priv
->rps
.max_delay
),
3586 dev_priv
->rps
.max_delay
);
3588 dev_priv
->rps
.rpe_delay
= valleyview_rps_rpe_freq(dev_priv
);
3589 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
3590 vlv_gpu_freq(dev_priv
->mem_freq
,
3591 dev_priv
->rps
.rpe_delay
),
3592 dev_priv
->rps
.rpe_delay
);
3594 dev_priv
->rps
.min_delay
= valleyview_rps_min_freq(dev_priv
);
3595 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
3596 vlv_gpu_freq(dev_priv
->mem_freq
,
3597 dev_priv
->rps
.min_delay
),
3598 dev_priv
->rps
.min_delay
);
3600 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
3601 vlv_gpu_freq(dev_priv
->mem_freq
,
3602 dev_priv
->rps
.rpe_delay
),
3603 dev_priv
->rps
.rpe_delay
);
3605 INIT_DELAYED_WORK(&dev_priv
->rps
.vlv_work
, vlv_rps_timer_work
);
3607 valleyview_set_rps(dev_priv
->dev
, dev_priv
->rps
.rpe_delay
);
3609 /* requires MSI enabled */
3610 I915_WRITE(GEN6_PMIER
, GEN6_PM_RPS_EVENTS
);
3611 spin_lock_irq(&dev_priv
->rps
.lock
);
3612 WARN_ON(dev_priv
->rps
.pm_iir
!= 0);
3613 I915_WRITE(GEN6_PMIMR
, 0);
3614 spin_unlock_irq(&dev_priv
->rps
.lock
);
3615 /* enable all PM interrupts */
3616 I915_WRITE(GEN6_PMINTRMSK
, 0);
3618 gen6_gt_force_wake_put(dev_priv
);
3621 void ironlake_teardown_rc6(struct drm_device
*dev
)
3623 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3625 if (dev_priv
->ips
.renderctx
) {
3626 i915_gem_object_unpin(dev_priv
->ips
.renderctx
);
3627 drm_gem_object_unreference(&dev_priv
->ips
.renderctx
->base
);
3628 dev_priv
->ips
.renderctx
= NULL
;
3631 if (dev_priv
->ips
.pwrctx
) {
3632 i915_gem_object_unpin(dev_priv
->ips
.pwrctx
);
3633 drm_gem_object_unreference(&dev_priv
->ips
.pwrctx
->base
);
3634 dev_priv
->ips
.pwrctx
= NULL
;
3638 static void ironlake_disable_rc6(struct drm_device
*dev
)
3640 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3642 if (I915_READ(PWRCTXA
)) {
3643 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
3644 I915_WRITE(RSTDBYCTL
, I915_READ(RSTDBYCTL
) | RCX_SW_EXIT
);
3645 wait_for(((I915_READ(RSTDBYCTL
) & RSX_STATUS_MASK
) == RSX_STATUS_ON
),
3648 I915_WRITE(PWRCTXA
, 0);
3649 POSTING_READ(PWRCTXA
);
3651 I915_WRITE(RSTDBYCTL
, I915_READ(RSTDBYCTL
) & ~RCX_SW_EXIT
);
3652 POSTING_READ(RSTDBYCTL
);
3656 static int ironlake_setup_rc6(struct drm_device
*dev
)
3658 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3660 if (dev_priv
->ips
.renderctx
== NULL
)
3661 dev_priv
->ips
.renderctx
= intel_alloc_context_page(dev
);
3662 if (!dev_priv
->ips
.renderctx
)
3665 if (dev_priv
->ips
.pwrctx
== NULL
)
3666 dev_priv
->ips
.pwrctx
= intel_alloc_context_page(dev
);
3667 if (!dev_priv
->ips
.pwrctx
) {
3668 ironlake_teardown_rc6(dev
);
3675 static void ironlake_enable_rc6(struct drm_device
*dev
)
3677 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3678 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
3679 bool was_interruptible
;
3682 /* rc6 disabled by default due to repeated reports of hanging during
3685 if (!intel_enable_rc6(dev
))
3688 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
3690 ret
= ironlake_setup_rc6(dev
);
3694 was_interruptible
= dev_priv
->mm
.interruptible
;
3695 dev_priv
->mm
.interruptible
= false;
3698 * GPU can automatically power down the render unit if given a page
3701 ret
= intel_ring_begin(ring
, 6);
3703 ironlake_teardown_rc6(dev
);
3704 dev_priv
->mm
.interruptible
= was_interruptible
;
3708 intel_ring_emit(ring
, MI_SUSPEND_FLUSH
| MI_SUSPEND_FLUSH_EN
);
3709 intel_ring_emit(ring
, MI_SET_CONTEXT
);
3710 intel_ring_emit(ring
, dev_priv
->ips
.renderctx
->gtt_offset
|
3712 MI_SAVE_EXT_STATE_EN
|
3713 MI_RESTORE_EXT_STATE_EN
|
3714 MI_RESTORE_INHIBIT
);
3715 intel_ring_emit(ring
, MI_SUSPEND_FLUSH
);
3716 intel_ring_emit(ring
, MI_NOOP
);
3717 intel_ring_emit(ring
, MI_FLUSH
);
3718 intel_ring_advance(ring
);
3721 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
3722 * does an implicit flush, combined with MI_FLUSH above, it should be
3723 * safe to assume that renderctx is valid
3725 ret
= intel_ring_idle(ring
);
3726 dev_priv
->mm
.interruptible
= was_interruptible
;
3728 DRM_ERROR("failed to enable ironlake power savings\n");
3729 ironlake_teardown_rc6(dev
);
3733 I915_WRITE(PWRCTXA
, dev_priv
->ips
.pwrctx
->gtt_offset
| PWRCTX_EN
);
3734 I915_WRITE(RSTDBYCTL
, I915_READ(RSTDBYCTL
) & ~RCX_SW_EXIT
);
3737 static unsigned long intel_pxfreq(u32 vidfreq
)
3740 int div
= (vidfreq
& 0x3f0000) >> 16;
3741 int post
= (vidfreq
& 0x3000) >> 12;
3742 int pre
= (vidfreq
& 0x7);
3747 freq
= ((div
* 133333) / ((1<<post
) * pre
));
3752 static const struct cparams
{
3758 { 1, 1333, 301, 28664 },
3759 { 1, 1066, 294, 24460 },
3760 { 1, 800, 294, 25192 },
3761 { 0, 1333, 276, 27605 },
3762 { 0, 1066, 276, 27605 },
3763 { 0, 800, 231, 23784 },
3766 static unsigned long __i915_chipset_val(struct drm_i915_private
*dev_priv
)
3768 u64 total_count
, diff
, ret
;
3769 u32 count1
, count2
, count3
, m
= 0, c
= 0;
3770 unsigned long now
= jiffies_to_msecs(jiffies
), diff1
;
3773 assert_spin_locked(&mchdev_lock
);
3775 diff1
= now
- dev_priv
->ips
.last_time1
;
3777 /* Prevent division-by-zero if we are asking too fast.
3778 * Also, we don't get interesting results if we are polling
3779 * faster than once in 10ms, so just return the saved value
3783 return dev_priv
->ips
.chipset_power
;
3785 count1
= I915_READ(DMIEC
);
3786 count2
= I915_READ(DDREC
);
3787 count3
= I915_READ(CSIEC
);
3789 total_count
= count1
+ count2
+ count3
;
3791 /* FIXME: handle per-counter overflow */
3792 if (total_count
< dev_priv
->ips
.last_count1
) {
3793 diff
= ~0UL - dev_priv
->ips
.last_count1
;
3794 diff
+= total_count
;
3796 diff
= total_count
- dev_priv
->ips
.last_count1
;
3799 for (i
= 0; i
< ARRAY_SIZE(cparams
); i
++) {
3800 if (cparams
[i
].i
== dev_priv
->ips
.c_m
&&
3801 cparams
[i
].t
== dev_priv
->ips
.r_t
) {
3808 diff
= div_u64(diff
, diff1
);
3809 ret
= ((m
* diff
) + c
);
3810 ret
= div_u64(ret
, 10);
3812 dev_priv
->ips
.last_count1
= total_count
;
3813 dev_priv
->ips
.last_time1
= now
;
3815 dev_priv
->ips
.chipset_power
= ret
;
3820 unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
)
3824 if (dev_priv
->info
->gen
!= 5)
3827 spin_lock_irq(&mchdev_lock
);
3829 val
= __i915_chipset_val(dev_priv
);
3831 spin_unlock_irq(&mchdev_lock
);
3836 unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
)
3838 unsigned long m
, x
, b
;
3841 tsfs
= I915_READ(TSFS
);
3843 m
= ((tsfs
& TSFS_SLOPE_MASK
) >> TSFS_SLOPE_SHIFT
);
3844 x
= I915_READ8(TR1
);
3846 b
= tsfs
& TSFS_INTR_MASK
;
3848 return ((m
* x
) / 127) - b
;
3851 static u16
pvid_to_extvid(struct drm_i915_private
*dev_priv
, u8 pxvid
)
3853 static const struct v_table
{
3854 u16 vd
; /* in .1 mil */
3855 u16 vm
; /* in .1 mil */
3986 if (dev_priv
->info
->is_mobile
)
3987 return v_table
[pxvid
].vm
;
3989 return v_table
[pxvid
].vd
;
3992 static void __i915_update_gfx_val(struct drm_i915_private
*dev_priv
)
3994 struct timespec now
, diff1
;
3996 unsigned long diffms
;
3999 assert_spin_locked(&mchdev_lock
);
4001 getrawmonotonic(&now
);
4002 diff1
= timespec_sub(now
, dev_priv
->ips
.last_time2
);
4004 /* Don't divide by 0 */
4005 diffms
= diff1
.tv_sec
* 1000 + diff1
.tv_nsec
/ 1000000;
4009 count
= I915_READ(GFXEC
);
4011 if (count
< dev_priv
->ips
.last_count2
) {
4012 diff
= ~0UL - dev_priv
->ips
.last_count2
;
4015 diff
= count
- dev_priv
->ips
.last_count2
;
4018 dev_priv
->ips
.last_count2
= count
;
4019 dev_priv
->ips
.last_time2
= now
;
4021 /* More magic constants... */
4023 diff
= div_u64(diff
, diffms
* 10);
4024 dev_priv
->ips
.gfx_power
= diff
;
4027 void i915_update_gfx_val(struct drm_i915_private
*dev_priv
)
4029 if (dev_priv
->info
->gen
!= 5)
4032 spin_lock_irq(&mchdev_lock
);
4034 __i915_update_gfx_val(dev_priv
);
4036 spin_unlock_irq(&mchdev_lock
);
4039 static unsigned long __i915_gfx_val(struct drm_i915_private
*dev_priv
)
4041 unsigned long t
, corr
, state1
, corr2
, state2
;
4044 assert_spin_locked(&mchdev_lock
);
4046 pxvid
= I915_READ(PXVFREQ_BASE
+ (dev_priv
->rps
.cur_delay
* 4));
4047 pxvid
= (pxvid
>> 24) & 0x7f;
4048 ext_v
= pvid_to_extvid(dev_priv
, pxvid
);
4052 t
= i915_mch_val(dev_priv
);
4054 /* Revel in the empirically derived constants */
4056 /* Correction factor in 1/100000 units */
4058 corr
= ((t
* 2349) + 135940);
4060 corr
= ((t
* 964) + 29317);
4062 corr
= ((t
* 301) + 1004);
4064 corr
= corr
* ((150142 * state1
) / 10000 - 78642);
4066 corr2
= (corr
* dev_priv
->ips
.corr
);
4068 state2
= (corr2
* state1
) / 10000;
4069 state2
/= 100; /* convert to mW */
4071 __i915_update_gfx_val(dev_priv
);
4073 return dev_priv
->ips
.gfx_power
+ state2
;
4076 unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
)
4080 if (dev_priv
->info
->gen
!= 5)
4083 spin_lock_irq(&mchdev_lock
);
4085 val
= __i915_gfx_val(dev_priv
);
4087 spin_unlock_irq(&mchdev_lock
);
4093 * i915_read_mch_val - return value for IPS use
4095 * Calculate and return a value for the IPS driver to use when deciding whether
4096 * we have thermal and power headroom to increase CPU or GPU power budget.
4098 unsigned long i915_read_mch_val(void)
4100 struct drm_i915_private
*dev_priv
;
4101 unsigned long chipset_val
, graphics_val
, ret
= 0;
4103 spin_lock_irq(&mchdev_lock
);
4106 dev_priv
= i915_mch_dev
;
4108 chipset_val
= __i915_chipset_val(dev_priv
);
4109 graphics_val
= __i915_gfx_val(dev_priv
);
4111 ret
= chipset_val
+ graphics_val
;
4114 spin_unlock_irq(&mchdev_lock
);
4118 EXPORT_SYMBOL_GPL(i915_read_mch_val
);
4121 * i915_gpu_raise - raise GPU frequency limit
4123 * Raise the limit; IPS indicates we have thermal headroom.
4125 bool i915_gpu_raise(void)
4127 struct drm_i915_private
*dev_priv
;
4130 spin_lock_irq(&mchdev_lock
);
4131 if (!i915_mch_dev
) {
4135 dev_priv
= i915_mch_dev
;
4137 if (dev_priv
->ips
.max_delay
> dev_priv
->ips
.fmax
)
4138 dev_priv
->ips
.max_delay
--;
4141 spin_unlock_irq(&mchdev_lock
);
4145 EXPORT_SYMBOL_GPL(i915_gpu_raise
);
4148 * i915_gpu_lower - lower GPU frequency limit
4150 * IPS indicates we're close to a thermal limit, so throttle back the GPU
4151 * frequency maximum.
4153 bool i915_gpu_lower(void)
4155 struct drm_i915_private
*dev_priv
;
4158 spin_lock_irq(&mchdev_lock
);
4159 if (!i915_mch_dev
) {
4163 dev_priv
= i915_mch_dev
;
4165 if (dev_priv
->ips
.max_delay
< dev_priv
->ips
.min_delay
)
4166 dev_priv
->ips
.max_delay
++;
4169 spin_unlock_irq(&mchdev_lock
);
4173 EXPORT_SYMBOL_GPL(i915_gpu_lower
);
4176 * i915_gpu_busy - indicate GPU business to IPS
4178 * Tell the IPS driver whether or not the GPU is busy.
4180 bool i915_gpu_busy(void)
4182 struct drm_i915_private
*dev_priv
;
4183 struct intel_ring_buffer
*ring
;
4187 spin_lock_irq(&mchdev_lock
);
4190 dev_priv
= i915_mch_dev
;
4192 for_each_ring(ring
, dev_priv
, i
)
4193 ret
|= !list_empty(&ring
->request_list
);
4196 spin_unlock_irq(&mchdev_lock
);
4200 EXPORT_SYMBOL_GPL(i915_gpu_busy
);
4203 * i915_gpu_turbo_disable - disable graphics turbo
4205 * Disable graphics turbo by resetting the max frequency and setting the
4206 * current frequency to the default.
4208 bool i915_gpu_turbo_disable(void)
4210 struct drm_i915_private
*dev_priv
;
4213 spin_lock_irq(&mchdev_lock
);
4214 if (!i915_mch_dev
) {
4218 dev_priv
= i915_mch_dev
;
4220 dev_priv
->ips
.max_delay
= dev_priv
->ips
.fstart
;
4222 if (!ironlake_set_drps(dev_priv
->dev
, dev_priv
->ips
.fstart
))
4226 spin_unlock_irq(&mchdev_lock
);
4230 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable
);
4233 * Tells the intel_ips driver that the i915 driver is now loaded, if
4234 * IPS got loaded first.
4236 * This awkward dance is so that neither module has to depend on the
4237 * other in order for IPS to do the appropriate communication of
4238 * GPU turbo limits to i915.
4241 ips_ping_for_i915_load(void)
4245 link
= symbol_get(ips_link_to_i915_driver
);
4248 symbol_put(ips_link_to_i915_driver
);
4252 void intel_gpu_ips_init(struct drm_i915_private
*dev_priv
)
4254 /* We only register the i915 ips part with intel-ips once everything is
4255 * set up, to avoid intel-ips sneaking in and reading bogus values. */
4256 spin_lock_irq(&mchdev_lock
);
4257 i915_mch_dev
= dev_priv
;
4258 spin_unlock_irq(&mchdev_lock
);
4260 ips_ping_for_i915_load();
4263 void intel_gpu_ips_teardown(void)
4265 spin_lock_irq(&mchdev_lock
);
4266 i915_mch_dev
= NULL
;
4267 spin_unlock_irq(&mchdev_lock
);
4269 static void intel_init_emon(struct drm_device
*dev
)
4271 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4276 /* Disable to program */
4280 /* Program energy weights for various events */
4281 I915_WRITE(SDEW
, 0x15040d00);
4282 I915_WRITE(CSIEW0
, 0x007f0000);
4283 I915_WRITE(CSIEW1
, 0x1e220004);
4284 I915_WRITE(CSIEW2
, 0x04000004);
4286 for (i
= 0; i
< 5; i
++)
4287 I915_WRITE(PEW
+ (i
* 4), 0);
4288 for (i
= 0; i
< 3; i
++)
4289 I915_WRITE(DEW
+ (i
* 4), 0);
4291 /* Program P-state weights to account for frequency power adjustment */
4292 for (i
= 0; i
< 16; i
++) {
4293 u32 pxvidfreq
= I915_READ(PXVFREQ_BASE
+ (i
* 4));
4294 unsigned long freq
= intel_pxfreq(pxvidfreq
);
4295 unsigned long vid
= (pxvidfreq
& PXVFREQ_PX_MASK
) >>
4300 val
*= (freq
/ 1000);
4302 val
/= (127*127*900);
4304 DRM_ERROR("bad pxval: %ld\n", val
);
4307 /* Render standby states get 0 weight */
4311 for (i
= 0; i
< 4; i
++) {
4312 u32 val
= (pxw
[i
*4] << 24) | (pxw
[(i
*4)+1] << 16) |
4313 (pxw
[(i
*4)+2] << 8) | (pxw
[(i
*4)+3]);
4314 I915_WRITE(PXW
+ (i
* 4), val
);
4317 /* Adjust magic regs to magic values (more experimental results) */
4318 I915_WRITE(OGW0
, 0);
4319 I915_WRITE(OGW1
, 0);
4320 I915_WRITE(EG0
, 0x00007f00);
4321 I915_WRITE(EG1
, 0x0000000e);
4322 I915_WRITE(EG2
, 0x000e0000);
4323 I915_WRITE(EG3
, 0x68000300);
4324 I915_WRITE(EG4
, 0x42000000);
4325 I915_WRITE(EG5
, 0x00140031);
4329 for (i
= 0; i
< 8; i
++)
4330 I915_WRITE(PXWL
+ (i
* 4), 0);
4332 /* Enable PMON + select events */
4333 I915_WRITE(ECR
, 0x80000019);
4335 lcfuse
= I915_READ(LCFUSE02
);
4337 dev_priv
->ips
.corr
= (lcfuse
& LCFUSE_HIV_MASK
);
4340 void intel_disable_gt_powersave(struct drm_device
*dev
)
4342 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4344 /* Interrupts should be disabled already to avoid re-arming. */
4345 WARN_ON(dev
->irq_enabled
);
4347 if (IS_IRONLAKE_M(dev
)) {
4348 ironlake_disable_drps(dev
);
4349 ironlake_disable_rc6(dev
);
4350 } else if (INTEL_INFO(dev
)->gen
>= 6) {
4351 cancel_delayed_work_sync(&dev_priv
->rps
.delayed_resume_work
);
4352 cancel_work_sync(&dev_priv
->rps
.work
);
4353 if (IS_VALLEYVIEW(dev
))
4354 cancel_delayed_work_sync(&dev_priv
->rps
.vlv_work
);
4355 mutex_lock(&dev_priv
->rps
.hw_lock
);
4356 if (IS_VALLEYVIEW(dev
))
4357 valleyview_disable_rps(dev
);
4359 gen6_disable_rps(dev
);
4360 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4364 static void intel_gen6_powersave_work(struct work_struct
*work
)
4366 struct drm_i915_private
*dev_priv
=
4367 container_of(work
, struct drm_i915_private
,
4368 rps
.delayed_resume_work
.work
);
4369 struct drm_device
*dev
= dev_priv
->dev
;
4371 mutex_lock(&dev_priv
->rps
.hw_lock
);
4373 if (IS_VALLEYVIEW(dev
)) {
4374 valleyview_enable_rps(dev
);
4376 gen6_enable_rps(dev
);
4377 gen6_update_ring_freq(dev
);
4379 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4382 void intel_enable_gt_powersave(struct drm_device
*dev
)
4384 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4386 if (IS_IRONLAKE_M(dev
)) {
4387 ironlake_enable_drps(dev
);
4388 ironlake_enable_rc6(dev
);
4389 intel_init_emon(dev
);
4390 } else if (IS_GEN6(dev
) || IS_GEN7(dev
)) {
4392 * PCU communication is slow and this doesn't need to be
4393 * done at any specific time, so do this out of our fast path
4394 * to make resume and init faster.
4396 schedule_delayed_work(&dev_priv
->rps
.delayed_resume_work
,
4397 round_jiffies_up_relative(HZ
));
4401 static void ibx_init_clock_gating(struct drm_device
*dev
)
4403 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4406 * On Ibex Peak and Cougar Point, we need to disable clock
4407 * gating for the panel power sequencer or it will fail to
4408 * start up when no ports are active.
4410 I915_WRITE(SOUTH_DSPCLK_GATE_D
, PCH_DPLSUNIT_CLOCK_GATE_DISABLE
);
4413 static void g4x_disable_trickle_feed(struct drm_device
*dev
)
4415 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4418 for_each_pipe(pipe
) {
4419 I915_WRITE(DSPCNTR(pipe
),
4420 I915_READ(DSPCNTR(pipe
)) |
4421 DISPPLANE_TRICKLE_FEED_DISABLE
);
4422 intel_flush_display_plane(dev_priv
, pipe
);
4426 static void ironlake_init_clock_gating(struct drm_device
*dev
)
4428 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4429 uint32_t dspclk_gate
= ILK_VRHUNIT_CLOCK_GATE_DISABLE
;
4431 /* Required for FBC */
4432 dspclk_gate
|= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE
|
4433 ILK_DPFCUNIT_CLOCK_GATE_DISABLE
|
4434 ILK_DPFDUNIT_CLOCK_GATE_ENABLE
;
4436 I915_WRITE(PCH_3DCGDIS0
,
4437 MARIUNIT_CLOCK_GATE_DISABLE
|
4438 SVSMUNIT_CLOCK_GATE_DISABLE
);
4439 I915_WRITE(PCH_3DCGDIS1
,
4440 VFMUNIT_CLOCK_GATE_DISABLE
);
4443 * According to the spec the following bits should be set in
4444 * order to enable memory self-refresh
4445 * The bit 22/21 of 0x42004
4446 * The bit 5 of 0x42020
4447 * The bit 15 of 0x45000
4449 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
4450 (I915_READ(ILK_DISPLAY_CHICKEN2
) |
4451 ILK_DPARB_GATE
| ILK_VSDPFD_FULL
));
4452 dspclk_gate
|= ILK_DPARBUNIT_CLOCK_GATE_ENABLE
;
4453 I915_WRITE(DISP_ARB_CTL
,
4454 (I915_READ(DISP_ARB_CTL
) |
4456 I915_WRITE(WM3_LP_ILK
, 0);
4457 I915_WRITE(WM2_LP_ILK
, 0);
4458 I915_WRITE(WM1_LP_ILK
, 0);
4461 * Based on the document from hardware guys the following bits
4462 * should be set unconditionally in order to enable FBC.
4463 * The bit 22 of 0x42000
4464 * The bit 22 of 0x42004
4465 * The bit 7,8,9 of 0x42020.
4467 if (IS_IRONLAKE_M(dev
)) {
4468 I915_WRITE(ILK_DISPLAY_CHICKEN1
,
4469 I915_READ(ILK_DISPLAY_CHICKEN1
) |
4471 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
4472 I915_READ(ILK_DISPLAY_CHICKEN2
) |
4476 I915_WRITE(ILK_DSPCLK_GATE_D
, dspclk_gate
);
4478 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
4479 I915_READ(ILK_DISPLAY_CHICKEN2
) |
4480 ILK_ELPIN_409_SELECT
);
4481 I915_WRITE(_3D_CHICKEN2
,
4482 _3D_CHICKEN2_WM_READ_PIPELINED
<< 16 |
4483 _3D_CHICKEN2_WM_READ_PIPELINED
);
4485 /* WaDisableRenderCachePipelinedFlush:ilk */
4486 I915_WRITE(CACHE_MODE_0
,
4487 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE
));
4489 g4x_disable_trickle_feed(dev
);
4491 ibx_init_clock_gating(dev
);
4494 static void cpt_init_clock_gating(struct drm_device
*dev
)
4496 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4501 * On Ibex Peak and Cougar Point, we need to disable clock
4502 * gating for the panel power sequencer or it will fail to
4503 * start up when no ports are active.
4505 I915_WRITE(SOUTH_DSPCLK_GATE_D
, PCH_DPLSUNIT_CLOCK_GATE_DISABLE
);
4506 I915_WRITE(SOUTH_CHICKEN2
, I915_READ(SOUTH_CHICKEN2
) |
4507 DPLS_EDP_PPS_FIX_DIS
);
4508 /* The below fixes the weird display corruption, a few pixels shifted
4509 * downward, on (only) LVDS of some HP laptops with IVY.
4511 for_each_pipe(pipe
) {
4512 val
= I915_READ(TRANS_CHICKEN2(pipe
));
4513 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
4514 val
&= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED
;
4515 if (dev_priv
->vbt
.fdi_rx_polarity_inverted
)
4516 val
|= TRANS_CHICKEN2_FDI_POLARITY_REVERSED
;
4517 val
&= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK
;
4518 val
&= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER
;
4519 val
&= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH
;
4520 I915_WRITE(TRANS_CHICKEN2(pipe
), val
);
4522 /* WADP0ClockGatingDisable */
4523 for_each_pipe(pipe
) {
4524 I915_WRITE(TRANS_CHICKEN1(pipe
),
4525 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE
);
4529 static void gen6_check_mch_setup(struct drm_device
*dev
)
4531 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4534 tmp
= I915_READ(MCH_SSKPD
);
4535 if ((tmp
& MCH_SSKPD_WM0_MASK
) != MCH_SSKPD_WM0_VAL
) {
4536 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp
);
4537 DRM_INFO("This can cause pipe underruns and display issues.\n");
4538 DRM_INFO("Please upgrade your BIOS to fix this.\n");
4542 static void gen6_init_clock_gating(struct drm_device
*dev
)
4544 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4545 uint32_t dspclk_gate
= ILK_VRHUNIT_CLOCK_GATE_DISABLE
;
4547 I915_WRITE(ILK_DSPCLK_GATE_D
, dspclk_gate
);
4549 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
4550 I915_READ(ILK_DISPLAY_CHICKEN2
) |
4551 ILK_ELPIN_409_SELECT
);
4553 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4554 I915_WRITE(_3D_CHICKEN
,
4555 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB
));
4557 /* WaSetupGtModeTdRowDispatch:snb */
4558 if (IS_SNB_GT1(dev
))
4559 I915_WRITE(GEN6_GT_MODE
,
4560 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE
));
4562 I915_WRITE(WM3_LP_ILK
, 0);
4563 I915_WRITE(WM2_LP_ILK
, 0);
4564 I915_WRITE(WM1_LP_ILK
, 0);
4566 I915_WRITE(CACHE_MODE_0
,
4567 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB
));
4569 I915_WRITE(GEN6_UCGCTL1
,
4570 I915_READ(GEN6_UCGCTL1
) |
4571 GEN6_BLBUNIT_CLOCK_GATE_DISABLE
|
4572 GEN6_CSUNIT_CLOCK_GATE_DISABLE
);
4574 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4575 * gating disable must be set. Failure to set it results in
4576 * flickering pixels due to Z write ordering failures after
4577 * some amount of runtime in the Mesa "fire" demo, and Unigine
4578 * Sanctuary and Tropics, and apparently anything else with
4579 * alpha test or pixel discard.
4581 * According to the spec, bit 11 (RCCUNIT) must also be set,
4582 * but we didn't debug actual testcases to find it out.
4584 * Also apply WaDisableVDSUnitClockGating:snb and
4585 * WaDisableRCPBUnitClockGating:snb.
4587 I915_WRITE(GEN6_UCGCTL2
,
4588 GEN7_VDSUNIT_CLOCK_GATE_DISABLE
|
4589 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE
|
4590 GEN6_RCCUNIT_CLOCK_GATE_DISABLE
);
4592 /* Bspec says we need to always set all mask bits. */
4593 I915_WRITE(_3D_CHICKEN3
, (0xFFFF << 16) |
4594 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL
);
4597 * According to the spec the following bits should be
4598 * set in order to enable memory self-refresh and fbc:
4599 * The bit21 and bit22 of 0x42000
4600 * The bit21 and bit22 of 0x42004
4601 * The bit5 and bit7 of 0x42020
4602 * The bit14 of 0x70180
4603 * The bit14 of 0x71180
4605 I915_WRITE(ILK_DISPLAY_CHICKEN1
,
4606 I915_READ(ILK_DISPLAY_CHICKEN1
) |
4607 ILK_FBCQ_DIS
| ILK_PABSTRETCH_DIS
);
4608 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
4609 I915_READ(ILK_DISPLAY_CHICKEN2
) |
4610 ILK_DPARB_GATE
| ILK_VSDPFD_FULL
);
4611 I915_WRITE(ILK_DSPCLK_GATE_D
,
4612 I915_READ(ILK_DSPCLK_GATE_D
) |
4613 ILK_DPARBUNIT_CLOCK_GATE_ENABLE
|
4614 ILK_DPFDUNIT_CLOCK_GATE_ENABLE
);
4616 /* WaMbcDriverBootEnable:snb */
4617 I915_WRITE(GEN6_MBCTL
, I915_READ(GEN6_MBCTL
) |
4618 GEN6_MBCTL_ENABLE_BOOT_FETCH
);
4620 g4x_disable_trickle_feed(dev
);
4622 /* The default value should be 0x200 according to docs, but the two
4623 * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
4624 I915_WRITE(GEN6_GT_MODE
, _MASKED_BIT_DISABLE(0xffff));
4625 I915_WRITE(GEN6_GT_MODE
, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI
));
4627 cpt_init_clock_gating(dev
);
4629 gen6_check_mch_setup(dev
);
4632 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private
*dev_priv
)
4634 uint32_t reg
= I915_READ(GEN7_FF_THREAD_MODE
);
4636 reg
&= ~GEN7_FF_SCHED_MASK
;
4637 reg
|= GEN7_FF_TS_SCHED_HW
;
4638 reg
|= GEN7_FF_VS_SCHED_HW
;
4639 reg
|= GEN7_FF_DS_SCHED_HW
;
4641 if (IS_HASWELL(dev_priv
->dev
))
4642 reg
&= ~GEN7_FF_VS_REF_CNT_FFME
;
4644 I915_WRITE(GEN7_FF_THREAD_MODE
, reg
);
4647 static void lpt_init_clock_gating(struct drm_device
*dev
)
4649 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4652 * TODO: this bit should only be enabled when really needed, then
4653 * disabled when not needed anymore in order to save power.
4655 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
)
4656 I915_WRITE(SOUTH_DSPCLK_GATE_D
,
4657 I915_READ(SOUTH_DSPCLK_GATE_D
) |
4658 PCH_LP_PARTITION_LEVEL_DISABLE
);
4660 /* WADPOClockGatingDisable:hsw */
4661 I915_WRITE(_TRANSA_CHICKEN1
,
4662 I915_READ(_TRANSA_CHICKEN1
) |
4663 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE
);
4666 static void lpt_suspend_hw(struct drm_device
*dev
)
4668 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4670 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
4671 uint32_t val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
4673 val
&= ~PCH_LP_PARTITION_LEVEL_DISABLE
;
4674 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
4678 static void haswell_init_clock_gating(struct drm_device
*dev
)
4680 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4682 I915_WRITE(WM3_LP_ILK
, 0);
4683 I915_WRITE(WM2_LP_ILK
, 0);
4684 I915_WRITE(WM1_LP_ILK
, 0);
4686 /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
4687 * This implements the WaDisableRCZUnitClockGating:hsw workaround.
4689 I915_WRITE(GEN6_UCGCTL2
, GEN6_RCZUNIT_CLOCK_GATE_DISABLE
);
4691 /* Apply the WaDisableRHWOOptimizationForRenderHang:hsw workaround. */
4692 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1
,
4693 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC
);
4695 /* WaApplyL3ControlAndL3ChickenMode:hsw */
4696 I915_WRITE(GEN7_L3CNTLREG1
,
4697 GEN7_WA_FOR_GEN7_L3_CONTROL
);
4698 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER
,
4699 GEN7_WA_L3_CHICKEN_MODE
);
4701 /* This is required by WaCatErrorRejectionIssue:hsw */
4702 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
4703 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
4704 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
4706 g4x_disable_trickle_feed(dev
);
4708 /* WaVSRefCountFullforceMissDisable:hsw */
4709 gen7_setup_fixed_func_scheduler(dev_priv
);
4711 /* WaDisable4x2SubspanOptimization:hsw */
4712 I915_WRITE(CACHE_MODE_1
,
4713 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
));
4715 /* WaMbcDriverBootEnable:hsw */
4716 I915_WRITE(GEN6_MBCTL
, I915_READ(GEN6_MBCTL
) |
4717 GEN6_MBCTL_ENABLE_BOOT_FETCH
);
4719 /* WaSwitchSolVfFArbitrationPriority:hsw */
4720 I915_WRITE(GAM_ECOCHK
, I915_READ(GAM_ECOCHK
) | HSW_ECOCHK_ARB_PRIO_SOL
);
4722 /* WaRsPkgCStateDisplayPMReq:hsw */
4723 I915_WRITE(CHICKEN_PAR1_1
,
4724 I915_READ(CHICKEN_PAR1_1
) | FORCE_ARB_IDLE_PLANES
);
4726 lpt_init_clock_gating(dev
);
4729 static void ivybridge_init_clock_gating(struct drm_device
*dev
)
4731 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4734 I915_WRITE(WM3_LP_ILK
, 0);
4735 I915_WRITE(WM2_LP_ILK
, 0);
4736 I915_WRITE(WM1_LP_ILK
, 0);
4738 I915_WRITE(ILK_DSPCLK_GATE_D
, ILK_VRHUNIT_CLOCK_GATE_DISABLE
);
4740 /* WaDisableEarlyCull:ivb */
4741 I915_WRITE(_3D_CHICKEN3
,
4742 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL
));
4744 /* WaDisableBackToBackFlipFix:ivb */
4745 I915_WRITE(IVB_CHICKEN3
,
4746 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE
|
4747 CHICKEN3_DGMG_DONE_FIX_DISABLE
);
4749 /* WaDisablePSDDualDispatchEnable:ivb */
4750 if (IS_IVB_GT1(dev
))
4751 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1
,
4752 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE
));
4754 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2
,
4755 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE
));
4757 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
4758 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1
,
4759 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC
);
4761 /* WaApplyL3ControlAndL3ChickenMode:ivb */
4762 I915_WRITE(GEN7_L3CNTLREG1
,
4763 GEN7_WA_FOR_GEN7_L3_CONTROL
);
4764 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER
,
4765 GEN7_WA_L3_CHICKEN_MODE
);
4766 if (IS_IVB_GT1(dev
))
4767 I915_WRITE(GEN7_ROW_CHICKEN2
,
4768 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
4770 I915_WRITE(GEN7_ROW_CHICKEN2_GT2
,
4771 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
4774 /* WaForceL3Serialization:ivb */
4775 I915_WRITE(GEN7_L3SQCREG4
, I915_READ(GEN7_L3SQCREG4
) &
4776 ~L3SQ_URB_READ_CAM_MATCH_DISABLE
);
4778 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4779 * gating disable must be set. Failure to set it results in
4780 * flickering pixels due to Z write ordering failures after
4781 * some amount of runtime in the Mesa "fire" demo, and Unigine
4782 * Sanctuary and Tropics, and apparently anything else with
4783 * alpha test or pixel discard.
4785 * According to the spec, bit 11 (RCCUNIT) must also be set,
4786 * but we didn't debug actual testcases to find it out.
4788 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
4789 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
4791 I915_WRITE(GEN6_UCGCTL2
,
4792 GEN6_RCZUNIT_CLOCK_GATE_DISABLE
|
4793 GEN6_RCCUNIT_CLOCK_GATE_DISABLE
);
4795 /* This is required by WaCatErrorRejectionIssue:ivb */
4796 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
4797 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
4798 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
4800 g4x_disable_trickle_feed(dev
);
4802 /* WaMbcDriverBootEnable:ivb */
4803 I915_WRITE(GEN6_MBCTL
, I915_READ(GEN6_MBCTL
) |
4804 GEN6_MBCTL_ENABLE_BOOT_FETCH
);
4806 /* WaVSRefCountFullforceMissDisable:ivb */
4807 gen7_setup_fixed_func_scheduler(dev_priv
);
4809 /* WaDisable4x2SubspanOptimization:ivb */
4810 I915_WRITE(CACHE_MODE_1
,
4811 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
));
4813 snpcr
= I915_READ(GEN6_MBCUNIT_SNPCR
);
4814 snpcr
&= ~GEN6_MBC_SNPCR_MASK
;
4815 snpcr
|= GEN6_MBC_SNPCR_MED
;
4816 I915_WRITE(GEN6_MBCUNIT_SNPCR
, snpcr
);
4818 if (!HAS_PCH_NOP(dev
))
4819 cpt_init_clock_gating(dev
);
4821 gen6_check_mch_setup(dev
);
4824 static void valleyview_init_clock_gating(struct drm_device
*dev
)
4826 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4828 I915_WRITE(DSPCLK_GATE_D
, VRHUNIT_CLOCK_GATE_DISABLE
);
4830 /* WaDisableEarlyCull:vlv */
4831 I915_WRITE(_3D_CHICKEN3
,
4832 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL
));
4834 /* WaDisableBackToBackFlipFix:vlv */
4835 I915_WRITE(IVB_CHICKEN3
,
4836 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE
|
4837 CHICKEN3_DGMG_DONE_FIX_DISABLE
);
4839 /* WaDisablePSDDualDispatchEnable:vlv */
4840 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1
,
4841 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP
|
4842 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE
));
4844 /* Apply the WaDisableRHWOOptimizationForRenderHang:vlv workaround. */
4845 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1
,
4846 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC
);
4848 /* WaApplyL3ControlAndL3ChickenMode:vlv */
4849 I915_WRITE(GEN7_L3CNTLREG1
, I915_READ(GEN7_L3CNTLREG1
) | GEN7_L3AGDIS
);
4850 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER
, GEN7_WA_L3_CHICKEN_MODE
);
4852 /* WaForceL3Serialization:vlv */
4853 I915_WRITE(GEN7_L3SQCREG4
, I915_READ(GEN7_L3SQCREG4
) &
4854 ~L3SQ_URB_READ_CAM_MATCH_DISABLE
);
4856 /* WaDisableDopClockGating:vlv */
4857 I915_WRITE(GEN7_ROW_CHICKEN2
,
4858 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
4860 /* This is required by WaCatErrorRejectionIssue:vlv */
4861 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
4862 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
4863 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
4865 /* WaMbcDriverBootEnable:vlv */
4866 I915_WRITE(GEN6_MBCTL
, I915_READ(GEN6_MBCTL
) |
4867 GEN6_MBCTL_ENABLE_BOOT_FETCH
);
4870 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4871 * gating disable must be set. Failure to set it results in
4872 * flickering pixels due to Z write ordering failures after
4873 * some amount of runtime in the Mesa "fire" demo, and Unigine
4874 * Sanctuary and Tropics, and apparently anything else with
4875 * alpha test or pixel discard.
4877 * According to the spec, bit 11 (RCCUNIT) must also be set,
4878 * but we didn't debug actual testcases to find it out.
4880 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
4881 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
4883 * Also apply WaDisableVDSUnitClockGating:vlv and
4884 * WaDisableRCPBUnitClockGating:vlv.
4886 I915_WRITE(GEN6_UCGCTL2
,
4887 GEN7_VDSUNIT_CLOCK_GATE_DISABLE
|
4888 GEN7_TDLUNIT_CLOCK_GATE_DISABLE
|
4889 GEN6_RCZUNIT_CLOCK_GATE_DISABLE
|
4890 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE
|
4891 GEN6_RCCUNIT_CLOCK_GATE_DISABLE
);
4893 I915_WRITE(GEN7_UCGCTL4
, GEN7_L3BANK2X_CLOCK_GATE_DISABLE
);
4895 I915_WRITE(MI_ARB_VLV
, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
);
4897 I915_WRITE(CACHE_MODE_1
,
4898 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
));
4901 * WaDisableVLVClockGating_VBIIssue:vlv
4902 * Disable clock gating on th GCFG unit to prevent a delay
4903 * in the reporting of vblank events.
4905 I915_WRITE(VLV_GUNIT_CLOCK_GATE
, 0xffffffff);
4907 /* Conservative clock gating settings for now */
4908 I915_WRITE(0x9400, 0xffffffff);
4909 I915_WRITE(0x9404, 0xffffffff);
4910 I915_WRITE(0x9408, 0xffffffff);
4911 I915_WRITE(0x940c, 0xffffffff);
4912 I915_WRITE(0x9410, 0xffffffff);
4913 I915_WRITE(0x9414, 0xffffffff);
4914 I915_WRITE(0x9418, 0xffffffff);
4917 static void g4x_init_clock_gating(struct drm_device
*dev
)
4919 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4920 uint32_t dspclk_gate
;
4922 I915_WRITE(RENCLK_GATE_D1
, 0);
4923 I915_WRITE(RENCLK_GATE_D2
, VF_UNIT_CLOCK_GATE_DISABLE
|
4924 GS_UNIT_CLOCK_GATE_DISABLE
|
4925 CL_UNIT_CLOCK_GATE_DISABLE
);
4926 I915_WRITE(RAMCLK_GATE_D
, 0);
4927 dspclk_gate
= VRHUNIT_CLOCK_GATE_DISABLE
|
4928 OVRUNIT_CLOCK_GATE_DISABLE
|
4929 OVCUNIT_CLOCK_GATE_DISABLE
;
4931 dspclk_gate
|= DSSUNIT_CLOCK_GATE_DISABLE
;
4932 I915_WRITE(DSPCLK_GATE_D
, dspclk_gate
);
4934 /* WaDisableRenderCachePipelinedFlush */
4935 I915_WRITE(CACHE_MODE_0
,
4936 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE
));
4938 g4x_disable_trickle_feed(dev
);
4941 static void crestline_init_clock_gating(struct drm_device
*dev
)
4943 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4945 I915_WRITE(RENCLK_GATE_D1
, I965_RCC_CLOCK_GATE_DISABLE
);
4946 I915_WRITE(RENCLK_GATE_D2
, 0);
4947 I915_WRITE(DSPCLK_GATE_D
, 0);
4948 I915_WRITE(RAMCLK_GATE_D
, 0);
4949 I915_WRITE16(DEUC
, 0);
4950 I915_WRITE(MI_ARB_STATE
,
4951 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
));
4954 static void broadwater_init_clock_gating(struct drm_device
*dev
)
4956 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4958 I915_WRITE(RENCLK_GATE_D1
, I965_RCZ_CLOCK_GATE_DISABLE
|
4959 I965_RCC_CLOCK_GATE_DISABLE
|
4960 I965_RCPB_CLOCK_GATE_DISABLE
|
4961 I965_ISC_CLOCK_GATE_DISABLE
|
4962 I965_FBC_CLOCK_GATE_DISABLE
);
4963 I915_WRITE(RENCLK_GATE_D2
, 0);
4964 I915_WRITE(MI_ARB_STATE
,
4965 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
));
4968 static void gen3_init_clock_gating(struct drm_device
*dev
)
4970 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4971 u32 dstate
= I915_READ(D_STATE
);
4973 dstate
|= DSTATE_PLL_D3_OFF
| DSTATE_GFX_CLOCK_GATING
|
4974 DSTATE_DOT_CLOCK_GATING
;
4975 I915_WRITE(D_STATE
, dstate
);
4977 if (IS_PINEVIEW(dev
))
4978 I915_WRITE(ECOSKPD
, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY
));
4980 /* IIR "flip pending" means done if this bit is set */
4981 I915_WRITE(ECOSKPD
, _MASKED_BIT_DISABLE(ECO_FLIP_DONE
));
4984 static void i85x_init_clock_gating(struct drm_device
*dev
)
4986 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4988 I915_WRITE(RENCLK_GATE_D1
, SV_CLOCK_GATE_DISABLE
);
4991 static void i830_init_clock_gating(struct drm_device
*dev
)
4993 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4995 I915_WRITE(DSPCLK_GATE_D
, OVRUNIT_CLOCK_GATE_DISABLE
);
4998 void intel_init_clock_gating(struct drm_device
*dev
)
5000 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5002 dev_priv
->display
.init_clock_gating(dev
);
5005 void intel_suspend_hw(struct drm_device
*dev
)
5007 if (HAS_PCH_LPT(dev
))
5008 lpt_suspend_hw(dev
);
5012 * We should only use the power well if we explicitly asked the hardware to
5013 * enable it, so check if it's enabled and also check if we've requested it to
5016 bool intel_display_power_enabled(struct drm_device
*dev
,
5017 enum intel_display_power_domain domain
)
5019 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5021 if (!HAS_POWER_WELL(dev
))
5025 case POWER_DOMAIN_PIPE_A
:
5026 case POWER_DOMAIN_TRANSCODER_EDP
:
5028 case POWER_DOMAIN_PIPE_B
:
5029 case POWER_DOMAIN_PIPE_C
:
5030 case POWER_DOMAIN_PIPE_A_PANEL_FITTER
:
5031 case POWER_DOMAIN_PIPE_B_PANEL_FITTER
:
5032 case POWER_DOMAIN_PIPE_C_PANEL_FITTER
:
5033 case POWER_DOMAIN_TRANSCODER_A
:
5034 case POWER_DOMAIN_TRANSCODER_B
:
5035 case POWER_DOMAIN_TRANSCODER_C
:
5036 return I915_READ(HSW_PWR_WELL_DRIVER
) ==
5037 (HSW_PWR_WELL_ENABLE
| HSW_PWR_WELL_STATE
);
5043 static void __intel_set_power_well(struct drm_device
*dev
, bool enable
)
5045 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5046 bool is_enabled
, enable_requested
;
5049 tmp
= I915_READ(HSW_PWR_WELL_DRIVER
);
5050 is_enabled
= tmp
& HSW_PWR_WELL_STATE
;
5051 enable_requested
= tmp
& HSW_PWR_WELL_ENABLE
;
5054 if (!enable_requested
)
5055 I915_WRITE(HSW_PWR_WELL_DRIVER
, HSW_PWR_WELL_ENABLE
);
5058 DRM_DEBUG_KMS("Enabling power well\n");
5059 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER
) &
5060 HSW_PWR_WELL_STATE
), 20))
5061 DRM_ERROR("Timeout enabling power well\n");
5064 if (enable_requested
) {
5065 I915_WRITE(HSW_PWR_WELL_DRIVER
, 0);
5066 DRM_DEBUG_KMS("Requesting to disable the power well\n");
5071 static struct i915_power_well
*hsw_pwr
;
5073 /* Display audio driver power well request */
5074 void i915_request_power_well(void)
5076 if (WARN_ON(!hsw_pwr
))
5079 spin_lock_irq(&hsw_pwr
->lock
);
5080 if (!hsw_pwr
->count
++ &&
5081 !hsw_pwr
->i915_request
)
5082 __intel_set_power_well(hsw_pwr
->device
, true);
5083 spin_unlock_irq(&hsw_pwr
->lock
);
5085 EXPORT_SYMBOL_GPL(i915_request_power_well
);
5087 /* Display audio driver power well release */
5088 void i915_release_power_well(void)
5090 if (WARN_ON(!hsw_pwr
))
5093 spin_lock_irq(&hsw_pwr
->lock
);
5094 WARN_ON(!hsw_pwr
->count
);
5095 if (!--hsw_pwr
->count
&&
5096 !hsw_pwr
->i915_request
)
5097 __intel_set_power_well(hsw_pwr
->device
, false);
5098 spin_unlock_irq(&hsw_pwr
->lock
);
5100 EXPORT_SYMBOL_GPL(i915_release_power_well
);
5102 int i915_init_power_well(struct drm_device
*dev
)
5104 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5106 hsw_pwr
= &dev_priv
->power_well
;
5108 hsw_pwr
->device
= dev
;
5109 spin_lock_init(&hsw_pwr
->lock
);
5115 void i915_remove_power_well(struct drm_device
*dev
)
5120 void intel_set_power_well(struct drm_device
*dev
, bool enable
)
5122 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5123 struct i915_power_well
*power_well
= &dev_priv
->power_well
;
5125 if (!HAS_POWER_WELL(dev
))
5128 if (!i915_disable_power_well
&& !enable
)
5131 spin_lock_irq(&power_well
->lock
);
5132 power_well
->i915_request
= enable
;
5134 /* only reject "disable" power well request */
5135 if (power_well
->count
&& !enable
) {
5136 spin_unlock_irq(&power_well
->lock
);
5140 __intel_set_power_well(dev
, enable
);
5141 spin_unlock_irq(&power_well
->lock
);
5145 * Starting with Haswell, we have a "Power Down Well" that can be turned off
5146 * when not needed anymore. We have 4 registers that can request the power well
5147 * to be enabled, and it will only be disabled if none of the registers is
5148 * requesting it to be enabled.
5150 void intel_init_power_well(struct drm_device
*dev
)
5152 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5154 if (!HAS_POWER_WELL(dev
))
5157 /* For now, we need the power well to be always enabled. */
5158 intel_set_power_well(dev
, true);
5160 /* We're taking over the BIOS, so clear any requests made by it since
5161 * the driver is in charge now. */
5162 if (I915_READ(HSW_PWR_WELL_BIOS
) & HSW_PWR_WELL_ENABLE
)
5163 I915_WRITE(HSW_PWR_WELL_BIOS
, 0);
5166 /* Set up chip specific power management-related functions */
5167 void intel_init_pm(struct drm_device
*dev
)
5169 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5171 if (I915_HAS_FBC(dev
)) {
5172 if (HAS_PCH_SPLIT(dev
)) {
5173 dev_priv
->display
.fbc_enabled
= ironlake_fbc_enabled
;
5174 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
))
5175 dev_priv
->display
.enable_fbc
=
5178 dev_priv
->display
.enable_fbc
=
5179 ironlake_enable_fbc
;
5180 dev_priv
->display
.disable_fbc
= ironlake_disable_fbc
;
5181 } else if (IS_GM45(dev
)) {
5182 dev_priv
->display
.fbc_enabled
= g4x_fbc_enabled
;
5183 dev_priv
->display
.enable_fbc
= g4x_enable_fbc
;
5184 dev_priv
->display
.disable_fbc
= g4x_disable_fbc
;
5185 } else if (IS_CRESTLINE(dev
)) {
5186 dev_priv
->display
.fbc_enabled
= i8xx_fbc_enabled
;
5187 dev_priv
->display
.enable_fbc
= i8xx_enable_fbc
;
5188 dev_priv
->display
.disable_fbc
= i8xx_disable_fbc
;
5190 /* 855GM needs testing */
5194 if (IS_PINEVIEW(dev
))
5195 i915_pineview_get_mem_freq(dev
);
5196 else if (IS_GEN5(dev
))
5197 i915_ironlake_get_mem_freq(dev
);
5199 /* For FIFO watermark updates */
5200 if (HAS_PCH_SPLIT(dev
)) {
5202 if (I915_READ(MLTR_ILK
) & ILK_SRLT_MASK
)
5203 dev_priv
->display
.update_wm
= ironlake_update_wm
;
5205 DRM_DEBUG_KMS("Failed to get proper latency. "
5207 dev_priv
->display
.update_wm
= NULL
;
5209 dev_priv
->display
.init_clock_gating
= ironlake_init_clock_gating
;
5210 } else if (IS_GEN6(dev
)) {
5211 if (SNB_READ_WM0_LATENCY()) {
5212 dev_priv
->display
.update_wm
= sandybridge_update_wm
;
5213 dev_priv
->display
.update_sprite_wm
= sandybridge_update_sprite_wm
;
5215 DRM_DEBUG_KMS("Failed to read display plane latency. "
5217 dev_priv
->display
.update_wm
= NULL
;
5219 dev_priv
->display
.init_clock_gating
= gen6_init_clock_gating
;
5220 } else if (IS_IVYBRIDGE(dev
)) {
5221 if (SNB_READ_WM0_LATENCY()) {
5222 dev_priv
->display
.update_wm
= ivybridge_update_wm
;
5223 dev_priv
->display
.update_sprite_wm
= sandybridge_update_sprite_wm
;
5225 DRM_DEBUG_KMS("Failed to read display plane latency. "
5227 dev_priv
->display
.update_wm
= NULL
;
5229 dev_priv
->display
.init_clock_gating
= ivybridge_init_clock_gating
;
5230 } else if (IS_HASWELL(dev
)) {
5231 if (I915_READ64(MCH_SSKPD
)) {
5232 dev_priv
->display
.update_wm
= haswell_update_wm
;
5233 dev_priv
->display
.update_sprite_wm
=
5234 haswell_update_sprite_wm
;
5236 DRM_DEBUG_KMS("Failed to read display plane latency. "
5238 dev_priv
->display
.update_wm
= NULL
;
5240 dev_priv
->display
.init_clock_gating
= haswell_init_clock_gating
;
5242 dev_priv
->display
.update_wm
= NULL
;
5243 } else if (IS_VALLEYVIEW(dev
)) {
5244 dev_priv
->display
.update_wm
= valleyview_update_wm
;
5245 dev_priv
->display
.init_clock_gating
=
5246 valleyview_init_clock_gating
;
5247 } else if (IS_PINEVIEW(dev
)) {
5248 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev
),
5251 dev_priv
->mem_freq
)) {
5252 DRM_INFO("failed to find known CxSR latency "
5253 "(found ddr%s fsb freq %d, mem freq %d), "
5255 (dev_priv
->is_ddr3
== 1) ? "3" : "2",
5256 dev_priv
->fsb_freq
, dev_priv
->mem_freq
);
5257 /* Disable CxSR and never update its watermark again */
5258 pineview_disable_cxsr(dev
);
5259 dev_priv
->display
.update_wm
= NULL
;
5261 dev_priv
->display
.update_wm
= pineview_update_wm
;
5262 dev_priv
->display
.init_clock_gating
= gen3_init_clock_gating
;
5263 } else if (IS_G4X(dev
)) {
5264 dev_priv
->display
.update_wm
= g4x_update_wm
;
5265 dev_priv
->display
.init_clock_gating
= g4x_init_clock_gating
;
5266 } else if (IS_GEN4(dev
)) {
5267 dev_priv
->display
.update_wm
= i965_update_wm
;
5268 if (IS_CRESTLINE(dev
))
5269 dev_priv
->display
.init_clock_gating
= crestline_init_clock_gating
;
5270 else if (IS_BROADWATER(dev
))
5271 dev_priv
->display
.init_clock_gating
= broadwater_init_clock_gating
;
5272 } else if (IS_GEN3(dev
)) {
5273 dev_priv
->display
.update_wm
= i9xx_update_wm
;
5274 dev_priv
->display
.get_fifo_size
= i9xx_get_fifo_size
;
5275 dev_priv
->display
.init_clock_gating
= gen3_init_clock_gating
;
5276 } else if (IS_I865G(dev
)) {
5277 dev_priv
->display
.update_wm
= i830_update_wm
;
5278 dev_priv
->display
.init_clock_gating
= i85x_init_clock_gating
;
5279 dev_priv
->display
.get_fifo_size
= i830_get_fifo_size
;
5280 } else if (IS_I85X(dev
)) {
5281 dev_priv
->display
.update_wm
= i9xx_update_wm
;
5282 dev_priv
->display
.get_fifo_size
= i85x_get_fifo_size
;
5283 dev_priv
->display
.init_clock_gating
= i85x_init_clock_gating
;
5285 dev_priv
->display
.update_wm
= i830_update_wm
;
5286 dev_priv
->display
.init_clock_gating
= i830_init_clock_gating
;
5288 dev_priv
->display
.get_fifo_size
= i845_get_fifo_size
;
5290 dev_priv
->display
.get_fifo_size
= i830_get_fifo_size
;
5294 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private
*dev_priv
)
5296 u32 gt_thread_status_mask
;
5298 if (IS_HASWELL(dev_priv
->dev
))
5299 gt_thread_status_mask
= GEN6_GT_THREAD_STATUS_CORE_MASK_HSW
;
5301 gt_thread_status_mask
= GEN6_GT_THREAD_STATUS_CORE_MASK
;
5303 /* w/a for a sporadic read returning 0 by waiting for the GT
5304 * thread to wake up.
5306 if (wait_for_atomic_us((I915_READ_NOTRACE(GEN6_GT_THREAD_STATUS_REG
) & gt_thread_status_mask
) == 0, 500))
5307 DRM_ERROR("GT thread status wait timed out\n");
5310 static void __gen6_gt_force_wake_reset(struct drm_i915_private
*dev_priv
)
5312 I915_WRITE_NOTRACE(FORCEWAKE
, 0);
5313 POSTING_READ(ECOBUS
); /* something from same cacheline, but !FORCEWAKE */
5316 static void __gen6_gt_force_wake_get(struct drm_i915_private
*dev_priv
)
5318 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK
) & 1) == 0,
5319 FORCEWAKE_ACK_TIMEOUT_MS
))
5320 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
5322 I915_WRITE_NOTRACE(FORCEWAKE
, 1);
5323 POSTING_READ(ECOBUS
); /* something from same cacheline, but !FORCEWAKE */
5325 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK
) & 1),
5326 FORCEWAKE_ACK_TIMEOUT_MS
))
5327 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
5329 /* WaRsForcewakeWaitTC0:snb */
5330 __gen6_gt_wait_for_thread_c0(dev_priv
);
5333 static void __gen6_gt_force_wake_mt_reset(struct drm_i915_private
*dev_priv
)
5335 I915_WRITE_NOTRACE(FORCEWAKE_MT
, _MASKED_BIT_DISABLE(0xffff));
5336 /* something from same cacheline, but !FORCEWAKE_MT */
5337 POSTING_READ(ECOBUS
);
5340 static void __gen6_gt_force_wake_mt_get(struct drm_i915_private
*dev_priv
)
5344 if (IS_HASWELL(dev_priv
->dev
))
5345 forcewake_ack
= FORCEWAKE_ACK_HSW
;
5347 forcewake_ack
= FORCEWAKE_MT_ACK
;
5349 if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack
) & FORCEWAKE_KERNEL
) == 0,
5350 FORCEWAKE_ACK_TIMEOUT_MS
))
5351 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
5353 I915_WRITE_NOTRACE(FORCEWAKE_MT
, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL
));
5354 /* something from same cacheline, but !FORCEWAKE_MT */
5355 POSTING_READ(ECOBUS
);
5357 if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack
) & FORCEWAKE_KERNEL
),
5358 FORCEWAKE_ACK_TIMEOUT_MS
))
5359 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
5361 /* WaRsForcewakeWaitTC0:ivb,hsw */
5362 __gen6_gt_wait_for_thread_c0(dev_priv
);
5366 * Generally this is called implicitly by the register read function. However,
5367 * if some sequence requires the GT to not power down then this function should
5368 * be called at the beginning of the sequence followed by a call to
5369 * gen6_gt_force_wake_put() at the end of the sequence.
5371 void gen6_gt_force_wake_get(struct drm_i915_private
*dev_priv
)
5373 unsigned long irqflags
;
5375 spin_lock_irqsave(&dev_priv
->gt_lock
, irqflags
);
5376 if (dev_priv
->forcewake_count
++ == 0)
5377 dev_priv
->gt
.force_wake_get(dev_priv
);
5378 spin_unlock_irqrestore(&dev_priv
->gt_lock
, irqflags
);
5381 void gen6_gt_check_fifodbg(struct drm_i915_private
*dev_priv
)
5384 gtfifodbg
= I915_READ_NOTRACE(GTFIFODBG
);
5385 if (WARN(gtfifodbg
& GT_FIFO_CPU_ERROR_MASK
,
5386 "MMIO read or write has been dropped %x\n", gtfifodbg
))
5387 I915_WRITE_NOTRACE(GTFIFODBG
, GT_FIFO_CPU_ERROR_MASK
);
5390 static void __gen6_gt_force_wake_put(struct drm_i915_private
*dev_priv
)
5392 I915_WRITE_NOTRACE(FORCEWAKE
, 0);
5393 /* something from same cacheline, but !FORCEWAKE */
5394 POSTING_READ(ECOBUS
);
5395 gen6_gt_check_fifodbg(dev_priv
);
5398 static void __gen6_gt_force_wake_mt_put(struct drm_i915_private
*dev_priv
)
5400 I915_WRITE_NOTRACE(FORCEWAKE_MT
, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL
));
5401 /* something from same cacheline, but !FORCEWAKE_MT */
5402 POSTING_READ(ECOBUS
);
5403 gen6_gt_check_fifodbg(dev_priv
);
5407 * see gen6_gt_force_wake_get()
5409 void gen6_gt_force_wake_put(struct drm_i915_private
*dev_priv
)
5411 unsigned long irqflags
;
5413 spin_lock_irqsave(&dev_priv
->gt_lock
, irqflags
);
5414 if (--dev_priv
->forcewake_count
== 0)
5415 dev_priv
->gt
.force_wake_put(dev_priv
);
5416 spin_unlock_irqrestore(&dev_priv
->gt_lock
, irqflags
);
5419 int __gen6_gt_wait_for_fifo(struct drm_i915_private
*dev_priv
)
5423 if (dev_priv
->gt_fifo_count
< GT_FIFO_NUM_RESERVED_ENTRIES
) {
5425 u32 fifo
= I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES
);
5426 while (fifo
<= GT_FIFO_NUM_RESERVED_ENTRIES
&& loop
--) {
5428 fifo
= I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES
);
5430 if (WARN_ON(loop
< 0 && fifo
<= GT_FIFO_NUM_RESERVED_ENTRIES
))
5432 dev_priv
->gt_fifo_count
= fifo
;
5434 dev_priv
->gt_fifo_count
--;
5439 static void vlv_force_wake_reset(struct drm_i915_private
*dev_priv
)
5441 I915_WRITE_NOTRACE(FORCEWAKE_VLV
, _MASKED_BIT_DISABLE(0xffff));
5442 /* something from same cacheline, but !FORCEWAKE_VLV */
5443 POSTING_READ(FORCEWAKE_ACK_VLV
);
5446 static void vlv_force_wake_get(struct drm_i915_private
*dev_priv
)
5448 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV
) & FORCEWAKE_KERNEL
) == 0,
5449 FORCEWAKE_ACK_TIMEOUT_MS
))
5450 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
5452 I915_WRITE_NOTRACE(FORCEWAKE_VLV
, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL
));
5453 I915_WRITE_NOTRACE(FORCEWAKE_MEDIA_VLV
,
5454 _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL
));
5456 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV
) & FORCEWAKE_KERNEL
),
5457 FORCEWAKE_ACK_TIMEOUT_MS
))
5458 DRM_ERROR("Timed out waiting for GT to ack forcewake request.\n");
5460 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_MEDIA_VLV
) &
5462 FORCEWAKE_ACK_TIMEOUT_MS
))
5463 DRM_ERROR("Timed out waiting for media to ack forcewake request.\n");
5465 /* WaRsForcewakeWaitTC0:vlv */
5466 __gen6_gt_wait_for_thread_c0(dev_priv
);
5469 static void vlv_force_wake_put(struct drm_i915_private
*dev_priv
)
5471 I915_WRITE_NOTRACE(FORCEWAKE_VLV
, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL
));
5472 I915_WRITE_NOTRACE(FORCEWAKE_MEDIA_VLV
,
5473 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL
));
5474 /* The below doubles as a POSTING_READ */
5475 gen6_gt_check_fifodbg(dev_priv
);
5478 void intel_gt_reset(struct drm_device
*dev
)
5480 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5482 if (IS_VALLEYVIEW(dev
)) {
5483 vlv_force_wake_reset(dev_priv
);
5484 } else if (INTEL_INFO(dev
)->gen
>= 6) {
5485 __gen6_gt_force_wake_reset(dev_priv
);
5486 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
))
5487 __gen6_gt_force_wake_mt_reset(dev_priv
);
5491 void intel_gt_init(struct drm_device
*dev
)
5493 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5495 spin_lock_init(&dev_priv
->gt_lock
);
5497 intel_gt_reset(dev
);
5499 if (IS_VALLEYVIEW(dev
)) {
5500 dev_priv
->gt
.force_wake_get
= vlv_force_wake_get
;
5501 dev_priv
->gt
.force_wake_put
= vlv_force_wake_put
;
5502 } else if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
)) {
5503 dev_priv
->gt
.force_wake_get
= __gen6_gt_force_wake_mt_get
;
5504 dev_priv
->gt
.force_wake_put
= __gen6_gt_force_wake_mt_put
;
5505 } else if (IS_GEN6(dev
)) {
5506 dev_priv
->gt
.force_wake_get
= __gen6_gt_force_wake_get
;
5507 dev_priv
->gt
.force_wake_put
= __gen6_gt_force_wake_put
;
5509 INIT_DELAYED_WORK(&dev_priv
->rps
.delayed_resume_work
,
5510 intel_gen6_powersave_work
);
5513 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u8 mbox
, u32
*val
)
5515 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
5517 if (I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) {
5518 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
5522 I915_WRITE(GEN6_PCODE_DATA
, *val
);
5523 I915_WRITE(GEN6_PCODE_MAILBOX
, GEN6_PCODE_READY
| mbox
);
5525 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) == 0,
5527 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox
);
5531 *val
= I915_READ(GEN6_PCODE_DATA
);
5532 I915_WRITE(GEN6_PCODE_DATA
, 0);
5537 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
, u8 mbox
, u32 val
)
5539 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
5541 if (I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) {
5542 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
5546 I915_WRITE(GEN6_PCODE_DATA
, val
);
5547 I915_WRITE(GEN6_PCODE_MAILBOX
, GEN6_PCODE_READY
| mbox
);
5549 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) == 0,
5551 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox
);
5555 I915_WRITE(GEN6_PCODE_DATA
, 0);
5560 int vlv_gpu_freq(int ddr_freq
, int val
)
5581 return ((val
- 0xbd) * mult
) + base
;
5584 int vlv_freq_opcode(int ddr_freq
, int val
)