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drm/i915: Use drm_i915_private as the native pointer for intel_uncore.c
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_pm.c
1 /*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28 #include <linux/cpufreq.h>
29 #include "i915_drv.h"
30 #include "intel_drv.h"
31 #include "../../../platform/x86/intel_ips.h"
32 #include <linux/module.h>
33
34 /**
35 * DOC: RC6
36 *
37 * RC6 is a special power stage which allows the GPU to enter an very
38 * low-voltage mode when idle, using down to 0V while at this stage. This
39 * stage is entered automatically when the GPU is idle when RC6 support is
40 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
41 *
42 * There are different RC6 modes available in Intel GPU, which differentiate
43 * among each other with the latency required to enter and leave RC6 and
44 * voltage consumed by the GPU in different states.
45 *
46 * The combination of the following flags define which states GPU is allowed
47 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
48 * RC6pp is deepest RC6. Their support by hardware varies according to the
49 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
50 * which brings the most power savings; deeper states save more power, but
51 * require higher latency to switch to and wake up.
52 */
53 #define INTEL_RC6_ENABLE (1<<0)
54 #define INTEL_RC6p_ENABLE (1<<1)
55 #define INTEL_RC6pp_ENABLE (1<<2)
56
57 static void bxt_init_clock_gating(struct drm_device *dev)
58 {
59 struct drm_i915_private *dev_priv = dev->dev_private;
60
61 /* WaDisableSDEUnitClockGating:bxt */
62 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
63 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
64
65 /*
66 * FIXME:
67 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
68 */
69 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
70 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
71
72 /*
73 * Wa: Backlight PWM may stop in the asserted state, causing backlight
74 * to stay fully on.
75 */
76 if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
77 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
78 PWM1_GATING_DIS | PWM2_GATING_DIS);
79 }
80
81 static void i915_pineview_get_mem_freq(struct drm_device *dev)
82 {
83 struct drm_i915_private *dev_priv = dev->dev_private;
84 u32 tmp;
85
86 tmp = I915_READ(CLKCFG);
87
88 switch (tmp & CLKCFG_FSB_MASK) {
89 case CLKCFG_FSB_533:
90 dev_priv->fsb_freq = 533; /* 133*4 */
91 break;
92 case CLKCFG_FSB_800:
93 dev_priv->fsb_freq = 800; /* 200*4 */
94 break;
95 case CLKCFG_FSB_667:
96 dev_priv->fsb_freq = 667; /* 167*4 */
97 break;
98 case CLKCFG_FSB_400:
99 dev_priv->fsb_freq = 400; /* 100*4 */
100 break;
101 }
102
103 switch (tmp & CLKCFG_MEM_MASK) {
104 case CLKCFG_MEM_533:
105 dev_priv->mem_freq = 533;
106 break;
107 case CLKCFG_MEM_667:
108 dev_priv->mem_freq = 667;
109 break;
110 case CLKCFG_MEM_800:
111 dev_priv->mem_freq = 800;
112 break;
113 }
114
115 /* detect pineview DDR3 setting */
116 tmp = I915_READ(CSHRDDR3CTL);
117 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
118 }
119
120 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
121 {
122 struct drm_i915_private *dev_priv = dev->dev_private;
123 u16 ddrpll, csipll;
124
125 ddrpll = I915_READ16(DDRMPLL1);
126 csipll = I915_READ16(CSIPLL0);
127
128 switch (ddrpll & 0xff) {
129 case 0xc:
130 dev_priv->mem_freq = 800;
131 break;
132 case 0x10:
133 dev_priv->mem_freq = 1066;
134 break;
135 case 0x14:
136 dev_priv->mem_freq = 1333;
137 break;
138 case 0x18:
139 dev_priv->mem_freq = 1600;
140 break;
141 default:
142 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
143 ddrpll & 0xff);
144 dev_priv->mem_freq = 0;
145 break;
146 }
147
148 dev_priv->ips.r_t = dev_priv->mem_freq;
149
150 switch (csipll & 0x3ff) {
151 case 0x00c:
152 dev_priv->fsb_freq = 3200;
153 break;
154 case 0x00e:
155 dev_priv->fsb_freq = 3733;
156 break;
157 case 0x010:
158 dev_priv->fsb_freq = 4266;
159 break;
160 case 0x012:
161 dev_priv->fsb_freq = 4800;
162 break;
163 case 0x014:
164 dev_priv->fsb_freq = 5333;
165 break;
166 case 0x016:
167 dev_priv->fsb_freq = 5866;
168 break;
169 case 0x018:
170 dev_priv->fsb_freq = 6400;
171 break;
172 default:
173 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
174 csipll & 0x3ff);
175 dev_priv->fsb_freq = 0;
176 break;
177 }
178
179 if (dev_priv->fsb_freq == 3200) {
180 dev_priv->ips.c_m = 0;
181 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
182 dev_priv->ips.c_m = 1;
183 } else {
184 dev_priv->ips.c_m = 2;
185 }
186 }
187
188 static const struct cxsr_latency cxsr_latency_table[] = {
189 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
190 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
191 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
192 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
193 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
194
195 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
196 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
197 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
198 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
199 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
200
201 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
202 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
203 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
204 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
205 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
206
207 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
208 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
209 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
210 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
211 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
212
213 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
214 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
215 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
216 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
217 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
218
219 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
220 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
221 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
222 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
223 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
224 };
225
226 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
227 int is_ddr3,
228 int fsb,
229 int mem)
230 {
231 const struct cxsr_latency *latency;
232 int i;
233
234 if (fsb == 0 || mem == 0)
235 return NULL;
236
237 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
238 latency = &cxsr_latency_table[i];
239 if (is_desktop == latency->is_desktop &&
240 is_ddr3 == latency->is_ddr3 &&
241 fsb == latency->fsb_freq && mem == latency->mem_freq)
242 return latency;
243 }
244
245 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
246
247 return NULL;
248 }
249
250 static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
251 {
252 u32 val;
253
254 mutex_lock(&dev_priv->rps.hw_lock);
255
256 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
257 if (enable)
258 val &= ~FORCE_DDR_HIGH_FREQ;
259 else
260 val |= FORCE_DDR_HIGH_FREQ;
261 val &= ~FORCE_DDR_LOW_FREQ;
262 val |= FORCE_DDR_FREQ_REQ_ACK;
263 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
264
265 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
266 FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
267 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
268
269 mutex_unlock(&dev_priv->rps.hw_lock);
270 }
271
272 static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
273 {
274 u32 val;
275
276 mutex_lock(&dev_priv->rps.hw_lock);
277
278 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
279 if (enable)
280 val |= DSP_MAXFIFO_PM5_ENABLE;
281 else
282 val &= ~DSP_MAXFIFO_PM5_ENABLE;
283 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
284
285 mutex_unlock(&dev_priv->rps.hw_lock);
286 }
287
288 #define FW_WM(value, plane) \
289 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
290
291 void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
292 {
293 struct drm_device *dev = dev_priv->dev;
294 u32 val;
295
296 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
297 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
298 POSTING_READ(FW_BLC_SELF_VLV);
299 dev_priv->wm.vlv.cxsr = enable;
300 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
301 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
302 POSTING_READ(FW_BLC_SELF);
303 } else if (IS_PINEVIEW(dev)) {
304 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
305 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
306 I915_WRITE(DSPFW3, val);
307 POSTING_READ(DSPFW3);
308 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
309 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
310 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
311 I915_WRITE(FW_BLC_SELF, val);
312 POSTING_READ(FW_BLC_SELF);
313 } else if (IS_I915GM(dev)) {
314 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
315 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
316 I915_WRITE(INSTPM, val);
317 POSTING_READ(INSTPM);
318 } else {
319 return;
320 }
321
322 DRM_DEBUG_KMS("memory self-refresh is %s\n",
323 enable ? "enabled" : "disabled");
324 }
325
326
327 /*
328 * Latency for FIFO fetches is dependent on several factors:
329 * - memory configuration (speed, channels)
330 * - chipset
331 * - current MCH state
332 * It can be fairly high in some situations, so here we assume a fairly
333 * pessimal value. It's a tradeoff between extra memory fetches (if we
334 * set this value too high, the FIFO will fetch frequently to stay full)
335 * and power consumption (set it too low to save power and we might see
336 * FIFO underruns and display "flicker").
337 *
338 * A value of 5us seems to be a good balance; safe for very low end
339 * platforms but not overly aggressive on lower latency configs.
340 */
341 static const int pessimal_latency_ns = 5000;
342
343 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
344 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
345
346 static int vlv_get_fifo_size(struct drm_device *dev,
347 enum pipe pipe, int plane)
348 {
349 struct drm_i915_private *dev_priv = dev->dev_private;
350 int sprite0_start, sprite1_start, size;
351
352 switch (pipe) {
353 uint32_t dsparb, dsparb2, dsparb3;
354 case PIPE_A:
355 dsparb = I915_READ(DSPARB);
356 dsparb2 = I915_READ(DSPARB2);
357 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
358 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
359 break;
360 case PIPE_B:
361 dsparb = I915_READ(DSPARB);
362 dsparb2 = I915_READ(DSPARB2);
363 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
364 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
365 break;
366 case PIPE_C:
367 dsparb2 = I915_READ(DSPARB2);
368 dsparb3 = I915_READ(DSPARB3);
369 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
370 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
371 break;
372 default:
373 return 0;
374 }
375
376 switch (plane) {
377 case 0:
378 size = sprite0_start;
379 break;
380 case 1:
381 size = sprite1_start - sprite0_start;
382 break;
383 case 2:
384 size = 512 - 1 - sprite1_start;
385 break;
386 default:
387 return 0;
388 }
389
390 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
391 pipe_name(pipe), plane == 0 ? "primary" : "sprite",
392 plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
393 size);
394
395 return size;
396 }
397
398 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
399 {
400 struct drm_i915_private *dev_priv = dev->dev_private;
401 uint32_t dsparb = I915_READ(DSPARB);
402 int size;
403
404 size = dsparb & 0x7f;
405 if (plane)
406 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
407
408 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
409 plane ? "B" : "A", size);
410
411 return size;
412 }
413
414 static int i830_get_fifo_size(struct drm_device *dev, int plane)
415 {
416 struct drm_i915_private *dev_priv = dev->dev_private;
417 uint32_t dsparb = I915_READ(DSPARB);
418 int size;
419
420 size = dsparb & 0x1ff;
421 if (plane)
422 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
423 size >>= 1; /* Convert to cachelines */
424
425 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
426 plane ? "B" : "A", size);
427
428 return size;
429 }
430
431 static int i845_get_fifo_size(struct drm_device *dev, int plane)
432 {
433 struct drm_i915_private *dev_priv = dev->dev_private;
434 uint32_t dsparb = I915_READ(DSPARB);
435 int size;
436
437 size = dsparb & 0x7f;
438 size >>= 2; /* Convert to cachelines */
439
440 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
441 plane ? "B" : "A",
442 size);
443
444 return size;
445 }
446
447 /* Pineview has different values for various configs */
448 static const struct intel_watermark_params pineview_display_wm = {
449 .fifo_size = PINEVIEW_DISPLAY_FIFO,
450 .max_wm = PINEVIEW_MAX_WM,
451 .default_wm = PINEVIEW_DFT_WM,
452 .guard_size = PINEVIEW_GUARD_WM,
453 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
454 };
455 static const struct intel_watermark_params pineview_display_hplloff_wm = {
456 .fifo_size = PINEVIEW_DISPLAY_FIFO,
457 .max_wm = PINEVIEW_MAX_WM,
458 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
459 .guard_size = PINEVIEW_GUARD_WM,
460 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
461 };
462 static const struct intel_watermark_params pineview_cursor_wm = {
463 .fifo_size = PINEVIEW_CURSOR_FIFO,
464 .max_wm = PINEVIEW_CURSOR_MAX_WM,
465 .default_wm = PINEVIEW_CURSOR_DFT_WM,
466 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
467 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
468 };
469 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
470 .fifo_size = PINEVIEW_CURSOR_FIFO,
471 .max_wm = PINEVIEW_CURSOR_MAX_WM,
472 .default_wm = PINEVIEW_CURSOR_DFT_WM,
473 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
474 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
475 };
476 static const struct intel_watermark_params g4x_wm_info = {
477 .fifo_size = G4X_FIFO_SIZE,
478 .max_wm = G4X_MAX_WM,
479 .default_wm = G4X_MAX_WM,
480 .guard_size = 2,
481 .cacheline_size = G4X_FIFO_LINE_SIZE,
482 };
483 static const struct intel_watermark_params g4x_cursor_wm_info = {
484 .fifo_size = I965_CURSOR_FIFO,
485 .max_wm = I965_CURSOR_MAX_WM,
486 .default_wm = I965_CURSOR_DFT_WM,
487 .guard_size = 2,
488 .cacheline_size = G4X_FIFO_LINE_SIZE,
489 };
490 static const struct intel_watermark_params i965_cursor_wm_info = {
491 .fifo_size = I965_CURSOR_FIFO,
492 .max_wm = I965_CURSOR_MAX_WM,
493 .default_wm = I965_CURSOR_DFT_WM,
494 .guard_size = 2,
495 .cacheline_size = I915_FIFO_LINE_SIZE,
496 };
497 static const struct intel_watermark_params i945_wm_info = {
498 .fifo_size = I945_FIFO_SIZE,
499 .max_wm = I915_MAX_WM,
500 .default_wm = 1,
501 .guard_size = 2,
502 .cacheline_size = I915_FIFO_LINE_SIZE,
503 };
504 static const struct intel_watermark_params i915_wm_info = {
505 .fifo_size = I915_FIFO_SIZE,
506 .max_wm = I915_MAX_WM,
507 .default_wm = 1,
508 .guard_size = 2,
509 .cacheline_size = I915_FIFO_LINE_SIZE,
510 };
511 static const struct intel_watermark_params i830_a_wm_info = {
512 .fifo_size = I855GM_FIFO_SIZE,
513 .max_wm = I915_MAX_WM,
514 .default_wm = 1,
515 .guard_size = 2,
516 .cacheline_size = I830_FIFO_LINE_SIZE,
517 };
518 static const struct intel_watermark_params i830_bc_wm_info = {
519 .fifo_size = I855GM_FIFO_SIZE,
520 .max_wm = I915_MAX_WM/2,
521 .default_wm = 1,
522 .guard_size = 2,
523 .cacheline_size = I830_FIFO_LINE_SIZE,
524 };
525 static const struct intel_watermark_params i845_wm_info = {
526 .fifo_size = I830_FIFO_SIZE,
527 .max_wm = I915_MAX_WM,
528 .default_wm = 1,
529 .guard_size = 2,
530 .cacheline_size = I830_FIFO_LINE_SIZE,
531 };
532
533 /**
534 * intel_calculate_wm - calculate watermark level
535 * @clock_in_khz: pixel clock
536 * @wm: chip FIFO params
537 * @cpp: bytes per pixel
538 * @latency_ns: memory latency for the platform
539 *
540 * Calculate the watermark level (the level at which the display plane will
541 * start fetching from memory again). Each chip has a different display
542 * FIFO size and allocation, so the caller needs to figure that out and pass
543 * in the correct intel_watermark_params structure.
544 *
545 * As the pixel clock runs, the FIFO will be drained at a rate that depends
546 * on the pixel size. When it reaches the watermark level, it'll start
547 * fetching FIFO line sized based chunks from memory until the FIFO fills
548 * past the watermark point. If the FIFO drains completely, a FIFO underrun
549 * will occur, and a display engine hang could result.
550 */
551 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
552 const struct intel_watermark_params *wm,
553 int fifo_size, int cpp,
554 unsigned long latency_ns)
555 {
556 long entries_required, wm_size;
557
558 /*
559 * Note: we need to make sure we don't overflow for various clock &
560 * latency values.
561 * clocks go from a few thousand to several hundred thousand.
562 * latency is usually a few thousand
563 */
564 entries_required = ((clock_in_khz / 1000) * cpp * latency_ns) /
565 1000;
566 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
567
568 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
569
570 wm_size = fifo_size - (entries_required + wm->guard_size);
571
572 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
573
574 /* Don't promote wm_size to unsigned... */
575 if (wm_size > (long)wm->max_wm)
576 wm_size = wm->max_wm;
577 if (wm_size <= 0)
578 wm_size = wm->default_wm;
579
580 /*
581 * Bspec seems to indicate that the value shouldn't be lower than
582 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
583 * Lets go for 8 which is the burst size since certain platforms
584 * already use a hardcoded 8 (which is what the spec says should be
585 * done).
586 */
587 if (wm_size <= 8)
588 wm_size = 8;
589
590 return wm_size;
591 }
592
593 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
594 {
595 struct drm_crtc *crtc, *enabled = NULL;
596
597 for_each_crtc(dev, crtc) {
598 if (intel_crtc_active(crtc)) {
599 if (enabled)
600 return NULL;
601 enabled = crtc;
602 }
603 }
604
605 return enabled;
606 }
607
608 static void pineview_update_wm(struct drm_crtc *unused_crtc)
609 {
610 struct drm_device *dev = unused_crtc->dev;
611 struct drm_i915_private *dev_priv = dev->dev_private;
612 struct drm_crtc *crtc;
613 const struct cxsr_latency *latency;
614 u32 reg;
615 unsigned long wm;
616
617 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
618 dev_priv->fsb_freq, dev_priv->mem_freq);
619 if (!latency) {
620 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
621 intel_set_memory_cxsr(dev_priv, false);
622 return;
623 }
624
625 crtc = single_enabled_crtc(dev);
626 if (crtc) {
627 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
628 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
629 int clock = adjusted_mode->crtc_clock;
630
631 /* Display SR */
632 wm = intel_calculate_wm(clock, &pineview_display_wm,
633 pineview_display_wm.fifo_size,
634 cpp, latency->display_sr);
635 reg = I915_READ(DSPFW1);
636 reg &= ~DSPFW_SR_MASK;
637 reg |= FW_WM(wm, SR);
638 I915_WRITE(DSPFW1, reg);
639 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
640
641 /* cursor SR */
642 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
643 pineview_display_wm.fifo_size,
644 cpp, latency->cursor_sr);
645 reg = I915_READ(DSPFW3);
646 reg &= ~DSPFW_CURSOR_SR_MASK;
647 reg |= FW_WM(wm, CURSOR_SR);
648 I915_WRITE(DSPFW3, reg);
649
650 /* Display HPLL off SR */
651 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
652 pineview_display_hplloff_wm.fifo_size,
653 cpp, latency->display_hpll_disable);
654 reg = I915_READ(DSPFW3);
655 reg &= ~DSPFW_HPLL_SR_MASK;
656 reg |= FW_WM(wm, HPLL_SR);
657 I915_WRITE(DSPFW3, reg);
658
659 /* cursor HPLL off SR */
660 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
661 pineview_display_hplloff_wm.fifo_size,
662 cpp, latency->cursor_hpll_disable);
663 reg = I915_READ(DSPFW3);
664 reg &= ~DSPFW_HPLL_CURSOR_MASK;
665 reg |= FW_WM(wm, HPLL_CURSOR);
666 I915_WRITE(DSPFW3, reg);
667 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
668
669 intel_set_memory_cxsr(dev_priv, true);
670 } else {
671 intel_set_memory_cxsr(dev_priv, false);
672 }
673 }
674
675 static bool g4x_compute_wm0(struct drm_device *dev,
676 int plane,
677 const struct intel_watermark_params *display,
678 int display_latency_ns,
679 const struct intel_watermark_params *cursor,
680 int cursor_latency_ns,
681 int *plane_wm,
682 int *cursor_wm)
683 {
684 struct drm_crtc *crtc;
685 const struct drm_display_mode *adjusted_mode;
686 int htotal, hdisplay, clock, cpp;
687 int line_time_us, line_count;
688 int entries, tlb_miss;
689
690 crtc = intel_get_crtc_for_plane(dev, plane);
691 if (!intel_crtc_active(crtc)) {
692 *cursor_wm = cursor->guard_size;
693 *plane_wm = display->guard_size;
694 return false;
695 }
696
697 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
698 clock = adjusted_mode->crtc_clock;
699 htotal = adjusted_mode->crtc_htotal;
700 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
701 cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
702
703 /* Use the small buffer method to calculate plane watermark */
704 entries = ((clock * cpp / 1000) * display_latency_ns) / 1000;
705 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
706 if (tlb_miss > 0)
707 entries += tlb_miss;
708 entries = DIV_ROUND_UP(entries, display->cacheline_size);
709 *plane_wm = entries + display->guard_size;
710 if (*plane_wm > (int)display->max_wm)
711 *plane_wm = display->max_wm;
712
713 /* Use the large buffer method to calculate cursor watermark */
714 line_time_us = max(htotal * 1000 / clock, 1);
715 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
716 entries = line_count * crtc->cursor->state->crtc_w * cpp;
717 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
718 if (tlb_miss > 0)
719 entries += tlb_miss;
720 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
721 *cursor_wm = entries + cursor->guard_size;
722 if (*cursor_wm > (int)cursor->max_wm)
723 *cursor_wm = (int)cursor->max_wm;
724
725 return true;
726 }
727
728 /*
729 * Check the wm result.
730 *
731 * If any calculated watermark values is larger than the maximum value that
732 * can be programmed into the associated watermark register, that watermark
733 * must be disabled.
734 */
735 static bool g4x_check_srwm(struct drm_device *dev,
736 int display_wm, int cursor_wm,
737 const struct intel_watermark_params *display,
738 const struct intel_watermark_params *cursor)
739 {
740 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
741 display_wm, cursor_wm);
742
743 if (display_wm > display->max_wm) {
744 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
745 display_wm, display->max_wm);
746 return false;
747 }
748
749 if (cursor_wm > cursor->max_wm) {
750 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
751 cursor_wm, cursor->max_wm);
752 return false;
753 }
754
755 if (!(display_wm || cursor_wm)) {
756 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
757 return false;
758 }
759
760 return true;
761 }
762
763 static bool g4x_compute_srwm(struct drm_device *dev,
764 int plane,
765 int latency_ns,
766 const struct intel_watermark_params *display,
767 const struct intel_watermark_params *cursor,
768 int *display_wm, int *cursor_wm)
769 {
770 struct drm_crtc *crtc;
771 const struct drm_display_mode *adjusted_mode;
772 int hdisplay, htotal, cpp, clock;
773 unsigned long line_time_us;
774 int line_count, line_size;
775 int small, large;
776 int entries;
777
778 if (!latency_ns) {
779 *display_wm = *cursor_wm = 0;
780 return false;
781 }
782
783 crtc = intel_get_crtc_for_plane(dev, plane);
784 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
785 clock = adjusted_mode->crtc_clock;
786 htotal = adjusted_mode->crtc_htotal;
787 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
788 cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
789
790 line_time_us = max(htotal * 1000 / clock, 1);
791 line_count = (latency_ns / line_time_us + 1000) / 1000;
792 line_size = hdisplay * cpp;
793
794 /* Use the minimum of the small and large buffer method for primary */
795 small = ((clock * cpp / 1000) * latency_ns) / 1000;
796 large = line_count * line_size;
797
798 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
799 *display_wm = entries + display->guard_size;
800
801 /* calculate the self-refresh watermark for display cursor */
802 entries = line_count * cpp * crtc->cursor->state->crtc_w;
803 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
804 *cursor_wm = entries + cursor->guard_size;
805
806 return g4x_check_srwm(dev,
807 *display_wm, *cursor_wm,
808 display, cursor);
809 }
810
811 #define FW_WM_VLV(value, plane) \
812 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
813
814 static void vlv_write_wm_values(struct intel_crtc *crtc,
815 const struct vlv_wm_values *wm)
816 {
817 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
818 enum pipe pipe = crtc->pipe;
819
820 I915_WRITE(VLV_DDL(pipe),
821 (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
822 (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
823 (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
824 (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
825
826 I915_WRITE(DSPFW1,
827 FW_WM(wm->sr.plane, SR) |
828 FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
829 FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
830 FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
831 I915_WRITE(DSPFW2,
832 FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
833 FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
834 FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
835 I915_WRITE(DSPFW3,
836 FW_WM(wm->sr.cursor, CURSOR_SR));
837
838 if (IS_CHERRYVIEW(dev_priv)) {
839 I915_WRITE(DSPFW7_CHV,
840 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
841 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
842 I915_WRITE(DSPFW8_CHV,
843 FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
844 FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
845 I915_WRITE(DSPFW9_CHV,
846 FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
847 FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
848 I915_WRITE(DSPHOWM,
849 FW_WM(wm->sr.plane >> 9, SR_HI) |
850 FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
851 FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
852 FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
853 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
854 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
855 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
856 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
857 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
858 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
859 } else {
860 I915_WRITE(DSPFW7,
861 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
862 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
863 I915_WRITE(DSPHOWM,
864 FW_WM(wm->sr.plane >> 9, SR_HI) |
865 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
866 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
867 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
868 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
869 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
870 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
871 }
872
873 /* zero (unused) WM1 watermarks */
874 I915_WRITE(DSPFW4, 0);
875 I915_WRITE(DSPFW5, 0);
876 I915_WRITE(DSPFW6, 0);
877 I915_WRITE(DSPHOWM1, 0);
878
879 POSTING_READ(DSPFW1);
880 }
881
882 #undef FW_WM_VLV
883
884 enum vlv_wm_level {
885 VLV_WM_LEVEL_PM2,
886 VLV_WM_LEVEL_PM5,
887 VLV_WM_LEVEL_DDR_DVFS,
888 };
889
890 /* latency must be in 0.1us units. */
891 static unsigned int vlv_wm_method2(unsigned int pixel_rate,
892 unsigned int pipe_htotal,
893 unsigned int horiz_pixels,
894 unsigned int cpp,
895 unsigned int latency)
896 {
897 unsigned int ret;
898
899 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
900 ret = (ret + 1) * horiz_pixels * cpp;
901 ret = DIV_ROUND_UP(ret, 64);
902
903 return ret;
904 }
905
906 static void vlv_setup_wm_latency(struct drm_device *dev)
907 {
908 struct drm_i915_private *dev_priv = dev->dev_private;
909
910 /* all latencies in usec */
911 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
912
913 dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
914
915 if (IS_CHERRYVIEW(dev_priv)) {
916 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
917 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
918
919 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
920 }
921 }
922
923 static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
924 struct intel_crtc *crtc,
925 const struct intel_plane_state *state,
926 int level)
927 {
928 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
929 int clock, htotal, cpp, width, wm;
930
931 if (dev_priv->wm.pri_latency[level] == 0)
932 return USHRT_MAX;
933
934 if (!state->visible)
935 return 0;
936
937 cpp = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
938 clock = crtc->config->base.adjusted_mode.crtc_clock;
939 htotal = crtc->config->base.adjusted_mode.crtc_htotal;
940 width = crtc->config->pipe_src_w;
941 if (WARN_ON(htotal == 0))
942 htotal = 1;
943
944 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
945 /*
946 * FIXME the formula gives values that are
947 * too big for the cursor FIFO, and hence we
948 * would never be able to use cursors. For
949 * now just hardcode the watermark.
950 */
951 wm = 63;
952 } else {
953 wm = vlv_wm_method2(clock, htotal, width, cpp,
954 dev_priv->wm.pri_latency[level] * 10);
955 }
956
957 return min_t(int, wm, USHRT_MAX);
958 }
959
960 static void vlv_compute_fifo(struct intel_crtc *crtc)
961 {
962 struct drm_device *dev = crtc->base.dev;
963 struct vlv_wm_state *wm_state = &crtc->wm_state;
964 struct intel_plane *plane;
965 unsigned int total_rate = 0;
966 const int fifo_size = 512 - 1;
967 int fifo_extra, fifo_left = fifo_size;
968
969 for_each_intel_plane_on_crtc(dev, crtc, plane) {
970 struct intel_plane_state *state =
971 to_intel_plane_state(plane->base.state);
972
973 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
974 continue;
975
976 if (state->visible) {
977 wm_state->num_active_planes++;
978 total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
979 }
980 }
981
982 for_each_intel_plane_on_crtc(dev, crtc, plane) {
983 struct intel_plane_state *state =
984 to_intel_plane_state(plane->base.state);
985 unsigned int rate;
986
987 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
988 plane->wm.fifo_size = 63;
989 continue;
990 }
991
992 if (!state->visible) {
993 plane->wm.fifo_size = 0;
994 continue;
995 }
996
997 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
998 plane->wm.fifo_size = fifo_size * rate / total_rate;
999 fifo_left -= plane->wm.fifo_size;
1000 }
1001
1002 fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1003
1004 /* spread the remainder evenly */
1005 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1006 int plane_extra;
1007
1008 if (fifo_left == 0)
1009 break;
1010
1011 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1012 continue;
1013
1014 /* give it all to the first plane if none are active */
1015 if (plane->wm.fifo_size == 0 &&
1016 wm_state->num_active_planes)
1017 continue;
1018
1019 plane_extra = min(fifo_extra, fifo_left);
1020 plane->wm.fifo_size += plane_extra;
1021 fifo_left -= plane_extra;
1022 }
1023
1024 WARN_ON(fifo_left != 0);
1025 }
1026
1027 static void vlv_invert_wms(struct intel_crtc *crtc)
1028 {
1029 struct vlv_wm_state *wm_state = &crtc->wm_state;
1030 int level;
1031
1032 for (level = 0; level < wm_state->num_levels; level++) {
1033 struct drm_device *dev = crtc->base.dev;
1034 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1035 struct intel_plane *plane;
1036
1037 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1038 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1039
1040 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1041 switch (plane->base.type) {
1042 int sprite;
1043 case DRM_PLANE_TYPE_CURSOR:
1044 wm_state->wm[level].cursor = plane->wm.fifo_size -
1045 wm_state->wm[level].cursor;
1046 break;
1047 case DRM_PLANE_TYPE_PRIMARY:
1048 wm_state->wm[level].primary = plane->wm.fifo_size -
1049 wm_state->wm[level].primary;
1050 break;
1051 case DRM_PLANE_TYPE_OVERLAY:
1052 sprite = plane->plane;
1053 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1054 wm_state->wm[level].sprite[sprite];
1055 break;
1056 }
1057 }
1058 }
1059 }
1060
1061 static void vlv_compute_wm(struct intel_crtc *crtc)
1062 {
1063 struct drm_device *dev = crtc->base.dev;
1064 struct vlv_wm_state *wm_state = &crtc->wm_state;
1065 struct intel_plane *plane;
1066 int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1067 int level;
1068
1069 memset(wm_state, 0, sizeof(*wm_state));
1070
1071 wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
1072 wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
1073
1074 wm_state->num_active_planes = 0;
1075
1076 vlv_compute_fifo(crtc);
1077
1078 if (wm_state->num_active_planes != 1)
1079 wm_state->cxsr = false;
1080
1081 if (wm_state->cxsr) {
1082 for (level = 0; level < wm_state->num_levels; level++) {
1083 wm_state->sr[level].plane = sr_fifo_size;
1084 wm_state->sr[level].cursor = 63;
1085 }
1086 }
1087
1088 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1089 struct intel_plane_state *state =
1090 to_intel_plane_state(plane->base.state);
1091
1092 if (!state->visible)
1093 continue;
1094
1095 /* normal watermarks */
1096 for (level = 0; level < wm_state->num_levels; level++) {
1097 int wm = vlv_compute_wm_level(plane, crtc, state, level);
1098 int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1099
1100 /* hack */
1101 if (WARN_ON(level == 0 && wm > max_wm))
1102 wm = max_wm;
1103
1104 if (wm > plane->wm.fifo_size)
1105 break;
1106
1107 switch (plane->base.type) {
1108 int sprite;
1109 case DRM_PLANE_TYPE_CURSOR:
1110 wm_state->wm[level].cursor = wm;
1111 break;
1112 case DRM_PLANE_TYPE_PRIMARY:
1113 wm_state->wm[level].primary = wm;
1114 break;
1115 case DRM_PLANE_TYPE_OVERLAY:
1116 sprite = plane->plane;
1117 wm_state->wm[level].sprite[sprite] = wm;
1118 break;
1119 }
1120 }
1121
1122 wm_state->num_levels = level;
1123
1124 if (!wm_state->cxsr)
1125 continue;
1126
1127 /* maxfifo watermarks */
1128 switch (plane->base.type) {
1129 int sprite, level;
1130 case DRM_PLANE_TYPE_CURSOR:
1131 for (level = 0; level < wm_state->num_levels; level++)
1132 wm_state->sr[level].cursor =
1133 wm_state->wm[level].cursor;
1134 break;
1135 case DRM_PLANE_TYPE_PRIMARY:
1136 for (level = 0; level < wm_state->num_levels; level++)
1137 wm_state->sr[level].plane =
1138 min(wm_state->sr[level].plane,
1139 wm_state->wm[level].primary);
1140 break;
1141 case DRM_PLANE_TYPE_OVERLAY:
1142 sprite = plane->plane;
1143 for (level = 0; level < wm_state->num_levels; level++)
1144 wm_state->sr[level].plane =
1145 min(wm_state->sr[level].plane,
1146 wm_state->wm[level].sprite[sprite]);
1147 break;
1148 }
1149 }
1150
1151 /* clear any (partially) filled invalid levels */
1152 for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
1153 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1154 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1155 }
1156
1157 vlv_invert_wms(crtc);
1158 }
1159
1160 #define VLV_FIFO(plane, value) \
1161 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1162
1163 static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1164 {
1165 struct drm_device *dev = crtc->base.dev;
1166 struct drm_i915_private *dev_priv = to_i915(dev);
1167 struct intel_plane *plane;
1168 int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1169
1170 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1171 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1172 WARN_ON(plane->wm.fifo_size != 63);
1173 continue;
1174 }
1175
1176 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1177 sprite0_start = plane->wm.fifo_size;
1178 else if (plane->plane == 0)
1179 sprite1_start = sprite0_start + plane->wm.fifo_size;
1180 else
1181 fifo_size = sprite1_start + plane->wm.fifo_size;
1182 }
1183
1184 WARN_ON(fifo_size != 512 - 1);
1185
1186 DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1187 pipe_name(crtc->pipe), sprite0_start,
1188 sprite1_start, fifo_size);
1189
1190 switch (crtc->pipe) {
1191 uint32_t dsparb, dsparb2, dsparb3;
1192 case PIPE_A:
1193 dsparb = I915_READ(DSPARB);
1194 dsparb2 = I915_READ(DSPARB2);
1195
1196 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1197 VLV_FIFO(SPRITEB, 0xff));
1198 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1199 VLV_FIFO(SPRITEB, sprite1_start));
1200
1201 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1202 VLV_FIFO(SPRITEB_HI, 0x1));
1203 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1204 VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1205
1206 I915_WRITE(DSPARB, dsparb);
1207 I915_WRITE(DSPARB2, dsparb2);
1208 break;
1209 case PIPE_B:
1210 dsparb = I915_READ(DSPARB);
1211 dsparb2 = I915_READ(DSPARB2);
1212
1213 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1214 VLV_FIFO(SPRITED, 0xff));
1215 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1216 VLV_FIFO(SPRITED, sprite1_start));
1217
1218 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1219 VLV_FIFO(SPRITED_HI, 0xff));
1220 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1221 VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1222
1223 I915_WRITE(DSPARB, dsparb);
1224 I915_WRITE(DSPARB2, dsparb2);
1225 break;
1226 case PIPE_C:
1227 dsparb3 = I915_READ(DSPARB3);
1228 dsparb2 = I915_READ(DSPARB2);
1229
1230 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1231 VLV_FIFO(SPRITEF, 0xff));
1232 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1233 VLV_FIFO(SPRITEF, sprite1_start));
1234
1235 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1236 VLV_FIFO(SPRITEF_HI, 0xff));
1237 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1238 VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1239
1240 I915_WRITE(DSPARB3, dsparb3);
1241 I915_WRITE(DSPARB2, dsparb2);
1242 break;
1243 default:
1244 break;
1245 }
1246 }
1247
1248 #undef VLV_FIFO
1249
1250 static void vlv_merge_wm(struct drm_device *dev,
1251 struct vlv_wm_values *wm)
1252 {
1253 struct intel_crtc *crtc;
1254 int num_active_crtcs = 0;
1255
1256 wm->level = to_i915(dev)->wm.max_level;
1257 wm->cxsr = true;
1258
1259 for_each_intel_crtc(dev, crtc) {
1260 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1261
1262 if (!crtc->active)
1263 continue;
1264
1265 if (!wm_state->cxsr)
1266 wm->cxsr = false;
1267
1268 num_active_crtcs++;
1269 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1270 }
1271
1272 if (num_active_crtcs != 1)
1273 wm->cxsr = false;
1274
1275 if (num_active_crtcs > 1)
1276 wm->level = VLV_WM_LEVEL_PM2;
1277
1278 for_each_intel_crtc(dev, crtc) {
1279 struct vlv_wm_state *wm_state = &crtc->wm_state;
1280 enum pipe pipe = crtc->pipe;
1281
1282 if (!crtc->active)
1283 continue;
1284
1285 wm->pipe[pipe] = wm_state->wm[wm->level];
1286 if (wm->cxsr)
1287 wm->sr = wm_state->sr[wm->level];
1288
1289 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1290 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1291 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1292 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1293 }
1294 }
1295
1296 static void vlv_update_wm(struct drm_crtc *crtc)
1297 {
1298 struct drm_device *dev = crtc->dev;
1299 struct drm_i915_private *dev_priv = dev->dev_private;
1300 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1301 enum pipe pipe = intel_crtc->pipe;
1302 struct vlv_wm_values wm = {};
1303
1304 vlv_compute_wm(intel_crtc);
1305 vlv_merge_wm(dev, &wm);
1306
1307 if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1308 /* FIXME should be part of crtc atomic commit */
1309 vlv_pipe_set_fifo_size(intel_crtc);
1310 return;
1311 }
1312
1313 if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1314 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1315 chv_set_memory_dvfs(dev_priv, false);
1316
1317 if (wm.level < VLV_WM_LEVEL_PM5 &&
1318 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1319 chv_set_memory_pm5(dev_priv, false);
1320
1321 if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
1322 intel_set_memory_cxsr(dev_priv, false);
1323
1324 /* FIXME should be part of crtc atomic commit */
1325 vlv_pipe_set_fifo_size(intel_crtc);
1326
1327 vlv_write_wm_values(intel_crtc, &wm);
1328
1329 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1330 "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1331 pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1332 wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1333 wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1334
1335 if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
1336 intel_set_memory_cxsr(dev_priv, true);
1337
1338 if (wm.level >= VLV_WM_LEVEL_PM5 &&
1339 dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1340 chv_set_memory_pm5(dev_priv, true);
1341
1342 if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1343 dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1344 chv_set_memory_dvfs(dev_priv, true);
1345
1346 dev_priv->wm.vlv = wm;
1347 }
1348
1349 #define single_plane_enabled(mask) is_power_of_2(mask)
1350
1351 static void g4x_update_wm(struct drm_crtc *crtc)
1352 {
1353 struct drm_device *dev = crtc->dev;
1354 static const int sr_latency_ns = 12000;
1355 struct drm_i915_private *dev_priv = dev->dev_private;
1356 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1357 int plane_sr, cursor_sr;
1358 unsigned int enabled = 0;
1359 bool cxsr_enabled;
1360
1361 if (g4x_compute_wm0(dev, PIPE_A,
1362 &g4x_wm_info, pessimal_latency_ns,
1363 &g4x_cursor_wm_info, pessimal_latency_ns,
1364 &planea_wm, &cursora_wm))
1365 enabled |= 1 << PIPE_A;
1366
1367 if (g4x_compute_wm0(dev, PIPE_B,
1368 &g4x_wm_info, pessimal_latency_ns,
1369 &g4x_cursor_wm_info, pessimal_latency_ns,
1370 &planeb_wm, &cursorb_wm))
1371 enabled |= 1 << PIPE_B;
1372
1373 if (single_plane_enabled(enabled) &&
1374 g4x_compute_srwm(dev, ffs(enabled) - 1,
1375 sr_latency_ns,
1376 &g4x_wm_info,
1377 &g4x_cursor_wm_info,
1378 &plane_sr, &cursor_sr)) {
1379 cxsr_enabled = true;
1380 } else {
1381 cxsr_enabled = false;
1382 intel_set_memory_cxsr(dev_priv, false);
1383 plane_sr = cursor_sr = 0;
1384 }
1385
1386 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1387 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1388 planea_wm, cursora_wm,
1389 planeb_wm, cursorb_wm,
1390 plane_sr, cursor_sr);
1391
1392 I915_WRITE(DSPFW1,
1393 FW_WM(plane_sr, SR) |
1394 FW_WM(cursorb_wm, CURSORB) |
1395 FW_WM(planeb_wm, PLANEB) |
1396 FW_WM(planea_wm, PLANEA));
1397 I915_WRITE(DSPFW2,
1398 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1399 FW_WM(cursora_wm, CURSORA));
1400 /* HPLL off in SR has some issues on G4x... disable it */
1401 I915_WRITE(DSPFW3,
1402 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1403 FW_WM(cursor_sr, CURSOR_SR));
1404
1405 if (cxsr_enabled)
1406 intel_set_memory_cxsr(dev_priv, true);
1407 }
1408
1409 static void i965_update_wm(struct drm_crtc *unused_crtc)
1410 {
1411 struct drm_device *dev = unused_crtc->dev;
1412 struct drm_i915_private *dev_priv = dev->dev_private;
1413 struct drm_crtc *crtc;
1414 int srwm = 1;
1415 int cursor_sr = 16;
1416 bool cxsr_enabled;
1417
1418 /* Calc sr entries for one plane configs */
1419 crtc = single_enabled_crtc(dev);
1420 if (crtc) {
1421 /* self-refresh has much higher latency */
1422 static const int sr_latency_ns = 12000;
1423 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1424 int clock = adjusted_mode->crtc_clock;
1425 int htotal = adjusted_mode->crtc_htotal;
1426 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
1427 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
1428 unsigned long line_time_us;
1429 int entries;
1430
1431 line_time_us = max(htotal * 1000 / clock, 1);
1432
1433 /* Use ns/us then divide to preserve precision */
1434 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1435 cpp * hdisplay;
1436 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1437 srwm = I965_FIFO_SIZE - entries;
1438 if (srwm < 0)
1439 srwm = 1;
1440 srwm &= 0x1ff;
1441 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1442 entries, srwm);
1443
1444 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1445 cpp * crtc->cursor->state->crtc_w;
1446 entries = DIV_ROUND_UP(entries,
1447 i965_cursor_wm_info.cacheline_size);
1448 cursor_sr = i965_cursor_wm_info.fifo_size -
1449 (entries + i965_cursor_wm_info.guard_size);
1450
1451 if (cursor_sr > i965_cursor_wm_info.max_wm)
1452 cursor_sr = i965_cursor_wm_info.max_wm;
1453
1454 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1455 "cursor %d\n", srwm, cursor_sr);
1456
1457 cxsr_enabled = true;
1458 } else {
1459 cxsr_enabled = false;
1460 /* Turn off self refresh if both pipes are enabled */
1461 intel_set_memory_cxsr(dev_priv, false);
1462 }
1463
1464 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1465 srwm);
1466
1467 /* 965 has limitations... */
1468 I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1469 FW_WM(8, CURSORB) |
1470 FW_WM(8, PLANEB) |
1471 FW_WM(8, PLANEA));
1472 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1473 FW_WM(8, PLANEC_OLD));
1474 /* update cursor SR watermark */
1475 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
1476
1477 if (cxsr_enabled)
1478 intel_set_memory_cxsr(dev_priv, true);
1479 }
1480
1481 #undef FW_WM
1482
1483 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1484 {
1485 struct drm_device *dev = unused_crtc->dev;
1486 struct drm_i915_private *dev_priv = dev->dev_private;
1487 const struct intel_watermark_params *wm_info;
1488 uint32_t fwater_lo;
1489 uint32_t fwater_hi;
1490 int cwm, srwm = 1;
1491 int fifo_size;
1492 int planea_wm, planeb_wm;
1493 struct drm_crtc *crtc, *enabled = NULL;
1494
1495 if (IS_I945GM(dev))
1496 wm_info = &i945_wm_info;
1497 else if (!IS_GEN2(dev))
1498 wm_info = &i915_wm_info;
1499 else
1500 wm_info = &i830_a_wm_info;
1501
1502 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1503 crtc = intel_get_crtc_for_plane(dev, 0);
1504 if (intel_crtc_active(crtc)) {
1505 const struct drm_display_mode *adjusted_mode;
1506 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
1507 if (IS_GEN2(dev))
1508 cpp = 4;
1509
1510 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1511 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1512 wm_info, fifo_size, cpp,
1513 pessimal_latency_ns);
1514 enabled = crtc;
1515 } else {
1516 planea_wm = fifo_size - wm_info->guard_size;
1517 if (planea_wm > (long)wm_info->max_wm)
1518 planea_wm = wm_info->max_wm;
1519 }
1520
1521 if (IS_GEN2(dev))
1522 wm_info = &i830_bc_wm_info;
1523
1524 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1525 crtc = intel_get_crtc_for_plane(dev, 1);
1526 if (intel_crtc_active(crtc)) {
1527 const struct drm_display_mode *adjusted_mode;
1528 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
1529 if (IS_GEN2(dev))
1530 cpp = 4;
1531
1532 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1533 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1534 wm_info, fifo_size, cpp,
1535 pessimal_latency_ns);
1536 if (enabled == NULL)
1537 enabled = crtc;
1538 else
1539 enabled = NULL;
1540 } else {
1541 planeb_wm = fifo_size - wm_info->guard_size;
1542 if (planeb_wm > (long)wm_info->max_wm)
1543 planeb_wm = wm_info->max_wm;
1544 }
1545
1546 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1547
1548 if (IS_I915GM(dev) && enabled) {
1549 struct drm_i915_gem_object *obj;
1550
1551 obj = intel_fb_obj(enabled->primary->state->fb);
1552
1553 /* self-refresh seems busted with untiled */
1554 if (obj->tiling_mode == I915_TILING_NONE)
1555 enabled = NULL;
1556 }
1557
1558 /*
1559 * Overlay gets an aggressive default since video jitter is bad.
1560 */
1561 cwm = 2;
1562
1563 /* Play safe and disable self-refresh before adjusting watermarks. */
1564 intel_set_memory_cxsr(dev_priv, false);
1565
1566 /* Calc sr entries for one plane configs */
1567 if (HAS_FW_BLC(dev) && enabled) {
1568 /* self-refresh has much higher latency */
1569 static const int sr_latency_ns = 6000;
1570 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode;
1571 int clock = adjusted_mode->crtc_clock;
1572 int htotal = adjusted_mode->crtc_htotal;
1573 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
1574 int cpp = drm_format_plane_cpp(enabled->primary->state->fb->pixel_format, 0);
1575 unsigned long line_time_us;
1576 int entries;
1577
1578 line_time_us = max(htotal * 1000 / clock, 1);
1579
1580 /* Use ns/us then divide to preserve precision */
1581 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1582 cpp * hdisplay;
1583 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1584 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1585 srwm = wm_info->fifo_size - entries;
1586 if (srwm < 0)
1587 srwm = 1;
1588
1589 if (IS_I945G(dev) || IS_I945GM(dev))
1590 I915_WRITE(FW_BLC_SELF,
1591 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1592 else if (IS_I915GM(dev))
1593 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1594 }
1595
1596 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1597 planea_wm, planeb_wm, cwm, srwm);
1598
1599 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1600 fwater_hi = (cwm & 0x1f);
1601
1602 /* Set request length to 8 cachelines per fetch */
1603 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1604 fwater_hi = fwater_hi | (1 << 8);
1605
1606 I915_WRITE(FW_BLC, fwater_lo);
1607 I915_WRITE(FW_BLC2, fwater_hi);
1608
1609 if (enabled)
1610 intel_set_memory_cxsr(dev_priv, true);
1611 }
1612
1613 static void i845_update_wm(struct drm_crtc *unused_crtc)
1614 {
1615 struct drm_device *dev = unused_crtc->dev;
1616 struct drm_i915_private *dev_priv = dev->dev_private;
1617 struct drm_crtc *crtc;
1618 const struct drm_display_mode *adjusted_mode;
1619 uint32_t fwater_lo;
1620 int planea_wm;
1621
1622 crtc = single_enabled_crtc(dev);
1623 if (crtc == NULL)
1624 return;
1625
1626 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1627 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1628 &i845_wm_info,
1629 dev_priv->display.get_fifo_size(dev, 0),
1630 4, pessimal_latency_ns);
1631 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1632 fwater_lo |= (3<<8) | planea_wm;
1633
1634 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1635
1636 I915_WRITE(FW_BLC, fwater_lo);
1637 }
1638
1639 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
1640 {
1641 uint32_t pixel_rate;
1642
1643 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
1644
1645 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1646 * adjust the pixel_rate here. */
1647
1648 if (pipe_config->pch_pfit.enabled) {
1649 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1650 uint32_t pfit_size = pipe_config->pch_pfit.size;
1651
1652 pipe_w = pipe_config->pipe_src_w;
1653 pipe_h = pipe_config->pipe_src_h;
1654
1655 pfit_w = (pfit_size >> 16) & 0xFFFF;
1656 pfit_h = pfit_size & 0xFFFF;
1657 if (pipe_w < pfit_w)
1658 pipe_w = pfit_w;
1659 if (pipe_h < pfit_h)
1660 pipe_h = pfit_h;
1661
1662 if (WARN_ON(!pfit_w || !pfit_h))
1663 return pixel_rate;
1664
1665 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1666 pfit_w * pfit_h);
1667 }
1668
1669 return pixel_rate;
1670 }
1671
1672 /* latency must be in 0.1us units. */
1673 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
1674 {
1675 uint64_t ret;
1676
1677 if (WARN(latency == 0, "Latency value missing\n"))
1678 return UINT_MAX;
1679
1680 ret = (uint64_t) pixel_rate * cpp * latency;
1681 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1682
1683 return ret;
1684 }
1685
1686 /* latency must be in 0.1us units. */
1687 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1688 uint32_t horiz_pixels, uint8_t cpp,
1689 uint32_t latency)
1690 {
1691 uint32_t ret;
1692
1693 if (WARN(latency == 0, "Latency value missing\n"))
1694 return UINT_MAX;
1695 if (WARN_ON(!pipe_htotal))
1696 return UINT_MAX;
1697
1698 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1699 ret = (ret + 1) * horiz_pixels * cpp;
1700 ret = DIV_ROUND_UP(ret, 64) + 2;
1701 return ret;
1702 }
1703
1704 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1705 uint8_t cpp)
1706 {
1707 /*
1708 * Neither of these should be possible since this function shouldn't be
1709 * called if the CRTC is off or the plane is invisible. But let's be
1710 * extra paranoid to avoid a potential divide-by-zero if we screw up
1711 * elsewhere in the driver.
1712 */
1713 if (WARN_ON(!cpp))
1714 return 0;
1715 if (WARN_ON(!horiz_pixels))
1716 return 0;
1717
1718 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
1719 }
1720
1721 struct ilk_wm_maximums {
1722 uint16_t pri;
1723 uint16_t spr;
1724 uint16_t cur;
1725 uint16_t fbc;
1726 };
1727
1728 /*
1729 * For both WM_PIPE and WM_LP.
1730 * mem_value must be in 0.1us units.
1731 */
1732 static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
1733 const struct intel_plane_state *pstate,
1734 uint32_t mem_value,
1735 bool is_lp)
1736 {
1737 int cpp = pstate->base.fb ?
1738 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1739 uint32_t method1, method2;
1740
1741 if (!cstate->base.active || !pstate->visible)
1742 return 0;
1743
1744 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
1745
1746 if (!is_lp)
1747 return method1;
1748
1749 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1750 cstate->base.adjusted_mode.crtc_htotal,
1751 drm_rect_width(&pstate->dst),
1752 cpp, mem_value);
1753
1754 return min(method1, method2);
1755 }
1756
1757 /*
1758 * For both WM_PIPE and WM_LP.
1759 * mem_value must be in 0.1us units.
1760 */
1761 static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
1762 const struct intel_plane_state *pstate,
1763 uint32_t mem_value)
1764 {
1765 int cpp = pstate->base.fb ?
1766 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1767 uint32_t method1, method2;
1768
1769 if (!cstate->base.active || !pstate->visible)
1770 return 0;
1771
1772 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
1773 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1774 cstate->base.adjusted_mode.crtc_htotal,
1775 drm_rect_width(&pstate->dst),
1776 cpp, mem_value);
1777 return min(method1, method2);
1778 }
1779
1780 /*
1781 * For both WM_PIPE and WM_LP.
1782 * mem_value must be in 0.1us units.
1783 */
1784 static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
1785 const struct intel_plane_state *pstate,
1786 uint32_t mem_value)
1787 {
1788 /*
1789 * We treat the cursor plane as always-on for the purposes of watermark
1790 * calculation. Until we have two-stage watermark programming merged,
1791 * this is necessary to avoid flickering.
1792 */
1793 int cpp = 4;
1794 int width = pstate->visible ? pstate->base.crtc_w : 64;
1795
1796 if (!cstate->base.active)
1797 return 0;
1798
1799 return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1800 cstate->base.adjusted_mode.crtc_htotal,
1801 width, cpp, mem_value);
1802 }
1803
1804 /* Only for WM_LP. */
1805 static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
1806 const struct intel_plane_state *pstate,
1807 uint32_t pri_val)
1808 {
1809 int cpp = pstate->base.fb ?
1810 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1811
1812 if (!cstate->base.active || !pstate->visible)
1813 return 0;
1814
1815 return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->dst), cpp);
1816 }
1817
1818 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1819 {
1820 if (INTEL_INFO(dev)->gen >= 8)
1821 return 3072;
1822 else if (INTEL_INFO(dev)->gen >= 7)
1823 return 768;
1824 else
1825 return 512;
1826 }
1827
1828 static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1829 int level, bool is_sprite)
1830 {
1831 if (INTEL_INFO(dev)->gen >= 8)
1832 /* BDW primary/sprite plane watermarks */
1833 return level == 0 ? 255 : 2047;
1834 else if (INTEL_INFO(dev)->gen >= 7)
1835 /* IVB/HSW primary/sprite plane watermarks */
1836 return level == 0 ? 127 : 1023;
1837 else if (!is_sprite)
1838 /* ILK/SNB primary plane watermarks */
1839 return level == 0 ? 127 : 511;
1840 else
1841 /* ILK/SNB sprite plane watermarks */
1842 return level == 0 ? 63 : 255;
1843 }
1844
1845 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1846 int level)
1847 {
1848 if (INTEL_INFO(dev)->gen >= 7)
1849 return level == 0 ? 63 : 255;
1850 else
1851 return level == 0 ? 31 : 63;
1852 }
1853
1854 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1855 {
1856 if (INTEL_INFO(dev)->gen >= 8)
1857 return 31;
1858 else
1859 return 15;
1860 }
1861
1862 /* Calculate the maximum primary/sprite plane watermark */
1863 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1864 int level,
1865 const struct intel_wm_config *config,
1866 enum intel_ddb_partitioning ddb_partitioning,
1867 bool is_sprite)
1868 {
1869 unsigned int fifo_size = ilk_display_fifo_size(dev);
1870
1871 /* if sprites aren't enabled, sprites get nothing */
1872 if (is_sprite && !config->sprites_enabled)
1873 return 0;
1874
1875 /* HSW allows LP1+ watermarks even with multiple pipes */
1876 if (level == 0 || config->num_pipes_active > 1) {
1877 fifo_size /= INTEL_INFO(dev)->num_pipes;
1878
1879 /*
1880 * For some reason the non self refresh
1881 * FIFO size is only half of the self
1882 * refresh FIFO size on ILK/SNB.
1883 */
1884 if (INTEL_INFO(dev)->gen <= 6)
1885 fifo_size /= 2;
1886 }
1887
1888 if (config->sprites_enabled) {
1889 /* level 0 is always calculated with 1:1 split */
1890 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1891 if (is_sprite)
1892 fifo_size *= 5;
1893 fifo_size /= 6;
1894 } else {
1895 fifo_size /= 2;
1896 }
1897 }
1898
1899 /* clamp to max that the registers can hold */
1900 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
1901 }
1902
1903 /* Calculate the maximum cursor plane watermark */
1904 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
1905 int level,
1906 const struct intel_wm_config *config)
1907 {
1908 /* HSW LP1+ watermarks w/ multiple pipes */
1909 if (level > 0 && config->num_pipes_active > 1)
1910 return 64;
1911
1912 /* otherwise just report max that registers can hold */
1913 return ilk_cursor_wm_reg_max(dev, level);
1914 }
1915
1916 static void ilk_compute_wm_maximums(const struct drm_device *dev,
1917 int level,
1918 const struct intel_wm_config *config,
1919 enum intel_ddb_partitioning ddb_partitioning,
1920 struct ilk_wm_maximums *max)
1921 {
1922 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1923 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1924 max->cur = ilk_cursor_wm_max(dev, level, config);
1925 max->fbc = ilk_fbc_wm_reg_max(dev);
1926 }
1927
1928 static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1929 int level,
1930 struct ilk_wm_maximums *max)
1931 {
1932 max->pri = ilk_plane_wm_reg_max(dev, level, false);
1933 max->spr = ilk_plane_wm_reg_max(dev, level, true);
1934 max->cur = ilk_cursor_wm_reg_max(dev, level);
1935 max->fbc = ilk_fbc_wm_reg_max(dev);
1936 }
1937
1938 static bool ilk_validate_wm_level(int level,
1939 const struct ilk_wm_maximums *max,
1940 struct intel_wm_level *result)
1941 {
1942 bool ret;
1943
1944 /* already determined to be invalid? */
1945 if (!result->enable)
1946 return false;
1947
1948 result->enable = result->pri_val <= max->pri &&
1949 result->spr_val <= max->spr &&
1950 result->cur_val <= max->cur;
1951
1952 ret = result->enable;
1953
1954 /*
1955 * HACK until we can pre-compute everything,
1956 * and thus fail gracefully if LP0 watermarks
1957 * are exceeded...
1958 */
1959 if (level == 0 && !result->enable) {
1960 if (result->pri_val > max->pri)
1961 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1962 level, result->pri_val, max->pri);
1963 if (result->spr_val > max->spr)
1964 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1965 level, result->spr_val, max->spr);
1966 if (result->cur_val > max->cur)
1967 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1968 level, result->cur_val, max->cur);
1969
1970 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
1971 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
1972 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
1973 result->enable = true;
1974 }
1975
1976 return ret;
1977 }
1978
1979 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
1980 const struct intel_crtc *intel_crtc,
1981 int level,
1982 struct intel_crtc_state *cstate,
1983 struct intel_plane_state *pristate,
1984 struct intel_plane_state *sprstate,
1985 struct intel_plane_state *curstate,
1986 struct intel_wm_level *result)
1987 {
1988 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
1989 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
1990 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
1991
1992 /* WM1+ latency values stored in 0.5us units */
1993 if (level > 0) {
1994 pri_latency *= 5;
1995 spr_latency *= 5;
1996 cur_latency *= 5;
1997 }
1998
1999 if (pristate) {
2000 result->pri_val = ilk_compute_pri_wm(cstate, pristate,
2001 pri_latency, level);
2002 result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
2003 }
2004
2005 if (sprstate)
2006 result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
2007
2008 if (curstate)
2009 result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
2010
2011 result->enable = true;
2012 }
2013
2014 static uint32_t
2015 hsw_compute_linetime_wm(const struct intel_crtc_state *cstate)
2016 {
2017 const struct intel_atomic_state *intel_state =
2018 to_intel_atomic_state(cstate->base.state);
2019 const struct drm_display_mode *adjusted_mode =
2020 &cstate->base.adjusted_mode;
2021 u32 linetime, ips_linetime;
2022
2023 if (!cstate->base.active)
2024 return 0;
2025 if (WARN_ON(adjusted_mode->crtc_clock == 0))
2026 return 0;
2027 if (WARN_ON(intel_state->cdclk == 0))
2028 return 0;
2029
2030 /* The WM are computed with base on how long it takes to fill a single
2031 * row at the given clock rate, multiplied by 8.
2032 * */
2033 linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2034 adjusted_mode->crtc_clock);
2035 ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2036 intel_state->cdclk);
2037
2038 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2039 PIPE_WM_LINETIME_TIME(linetime);
2040 }
2041
2042 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
2043 {
2044 struct drm_i915_private *dev_priv = dev->dev_private;
2045
2046 if (IS_GEN9(dev)) {
2047 uint32_t val;
2048 int ret, i;
2049 int level, max_level = ilk_wm_max_level(dev);
2050
2051 /* read the first set of memory latencies[0:3] */
2052 val = 0; /* data0 to be programmed to 0 for first set */
2053 mutex_lock(&dev_priv->rps.hw_lock);
2054 ret = sandybridge_pcode_read(dev_priv,
2055 GEN9_PCODE_READ_MEM_LATENCY,
2056 &val);
2057 mutex_unlock(&dev_priv->rps.hw_lock);
2058
2059 if (ret) {
2060 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2061 return;
2062 }
2063
2064 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2065 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2066 GEN9_MEM_LATENCY_LEVEL_MASK;
2067 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2068 GEN9_MEM_LATENCY_LEVEL_MASK;
2069 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2070 GEN9_MEM_LATENCY_LEVEL_MASK;
2071
2072 /* read the second set of memory latencies[4:7] */
2073 val = 1; /* data0 to be programmed to 1 for second set */
2074 mutex_lock(&dev_priv->rps.hw_lock);
2075 ret = sandybridge_pcode_read(dev_priv,
2076 GEN9_PCODE_READ_MEM_LATENCY,
2077 &val);
2078 mutex_unlock(&dev_priv->rps.hw_lock);
2079 if (ret) {
2080 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2081 return;
2082 }
2083
2084 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2085 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2086 GEN9_MEM_LATENCY_LEVEL_MASK;
2087 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2088 GEN9_MEM_LATENCY_LEVEL_MASK;
2089 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2090 GEN9_MEM_LATENCY_LEVEL_MASK;
2091
2092 /*
2093 * WaWmMemoryReadLatency:skl
2094 *
2095 * punit doesn't take into account the read latency so we need
2096 * to add 2us to the various latency levels we retrieve from
2097 * the punit.
2098 * - W0 is a bit special in that it's the only level that
2099 * can't be disabled if we want to have display working, so
2100 * we always add 2us there.
2101 * - For levels >=1, punit returns 0us latency when they are
2102 * disabled, so we respect that and don't add 2us then
2103 *
2104 * Additionally, if a level n (n > 1) has a 0us latency, all
2105 * levels m (m >= n) need to be disabled. We make sure to
2106 * sanitize the values out of the punit to satisfy this
2107 * requirement.
2108 */
2109 wm[0] += 2;
2110 for (level = 1; level <= max_level; level++)
2111 if (wm[level] != 0)
2112 wm[level] += 2;
2113 else {
2114 for (i = level + 1; i <= max_level; i++)
2115 wm[i] = 0;
2116
2117 break;
2118 }
2119 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2120 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2121
2122 wm[0] = (sskpd >> 56) & 0xFF;
2123 if (wm[0] == 0)
2124 wm[0] = sskpd & 0xF;
2125 wm[1] = (sskpd >> 4) & 0xFF;
2126 wm[2] = (sskpd >> 12) & 0xFF;
2127 wm[3] = (sskpd >> 20) & 0x1FF;
2128 wm[4] = (sskpd >> 32) & 0x1FF;
2129 } else if (INTEL_INFO(dev)->gen >= 6) {
2130 uint32_t sskpd = I915_READ(MCH_SSKPD);
2131
2132 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2133 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2134 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2135 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2136 } else if (INTEL_INFO(dev)->gen >= 5) {
2137 uint32_t mltr = I915_READ(MLTR_ILK);
2138
2139 /* ILK primary LP0 latency is 700 ns */
2140 wm[0] = 7;
2141 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2142 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2143 }
2144 }
2145
2146 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2147 {
2148 /* ILK sprite LP0 latency is 1300 ns */
2149 if (INTEL_INFO(dev)->gen == 5)
2150 wm[0] = 13;
2151 }
2152
2153 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2154 {
2155 /* ILK cursor LP0 latency is 1300 ns */
2156 if (INTEL_INFO(dev)->gen == 5)
2157 wm[0] = 13;
2158
2159 /* WaDoubleCursorLP3Latency:ivb */
2160 if (IS_IVYBRIDGE(dev))
2161 wm[3] *= 2;
2162 }
2163
2164 int ilk_wm_max_level(const struct drm_device *dev)
2165 {
2166 /* how many WM levels are we expecting */
2167 if (INTEL_INFO(dev)->gen >= 9)
2168 return 7;
2169 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2170 return 4;
2171 else if (INTEL_INFO(dev)->gen >= 6)
2172 return 3;
2173 else
2174 return 2;
2175 }
2176
2177 static void intel_print_wm_latency(struct drm_device *dev,
2178 const char *name,
2179 const uint16_t wm[8])
2180 {
2181 int level, max_level = ilk_wm_max_level(dev);
2182
2183 for (level = 0; level <= max_level; level++) {
2184 unsigned int latency = wm[level];
2185
2186 if (latency == 0) {
2187 DRM_ERROR("%s WM%d latency not provided\n",
2188 name, level);
2189 continue;
2190 }
2191
2192 /*
2193 * - latencies are in us on gen9.
2194 * - before then, WM1+ latency values are in 0.5us units
2195 */
2196 if (IS_GEN9(dev))
2197 latency *= 10;
2198 else if (level > 0)
2199 latency *= 5;
2200
2201 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2202 name, level, wm[level],
2203 latency / 10, latency % 10);
2204 }
2205 }
2206
2207 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2208 uint16_t wm[5], uint16_t min)
2209 {
2210 int level, max_level = ilk_wm_max_level(dev_priv->dev);
2211
2212 if (wm[0] >= min)
2213 return false;
2214
2215 wm[0] = max(wm[0], min);
2216 for (level = 1; level <= max_level; level++)
2217 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2218
2219 return true;
2220 }
2221
2222 static void snb_wm_latency_quirk(struct drm_device *dev)
2223 {
2224 struct drm_i915_private *dev_priv = dev->dev_private;
2225 bool changed;
2226
2227 /*
2228 * The BIOS provided WM memory latency values are often
2229 * inadequate for high resolution displays. Adjust them.
2230 */
2231 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2232 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2233 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2234
2235 if (!changed)
2236 return;
2237
2238 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2239 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2240 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2241 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2242 }
2243
2244 static void ilk_setup_wm_latency(struct drm_device *dev)
2245 {
2246 struct drm_i915_private *dev_priv = dev->dev_private;
2247
2248 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2249
2250 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2251 sizeof(dev_priv->wm.pri_latency));
2252 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2253 sizeof(dev_priv->wm.pri_latency));
2254
2255 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2256 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2257
2258 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2259 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2260 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2261
2262 if (IS_GEN6(dev))
2263 snb_wm_latency_quirk(dev);
2264 }
2265
2266 static void skl_setup_wm_latency(struct drm_device *dev)
2267 {
2268 struct drm_i915_private *dev_priv = dev->dev_private;
2269
2270 intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2271 intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2272 }
2273
2274 static bool ilk_validate_pipe_wm(struct drm_device *dev,
2275 struct intel_pipe_wm *pipe_wm)
2276 {
2277 /* LP0 watermark maximums depend on this pipe alone */
2278 const struct intel_wm_config config = {
2279 .num_pipes_active = 1,
2280 .sprites_enabled = pipe_wm->sprites_enabled,
2281 .sprites_scaled = pipe_wm->sprites_scaled,
2282 };
2283 struct ilk_wm_maximums max;
2284
2285 /* LP0 watermarks always use 1/2 DDB partitioning */
2286 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2287
2288 /* At least LP0 must be valid */
2289 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
2290 DRM_DEBUG_KMS("LP0 watermark invalid\n");
2291 return false;
2292 }
2293
2294 return true;
2295 }
2296
2297 /* Compute new watermarks for the pipe */
2298 static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
2299 {
2300 struct drm_atomic_state *state = cstate->base.state;
2301 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
2302 struct intel_pipe_wm *pipe_wm;
2303 struct drm_device *dev = state->dev;
2304 const struct drm_i915_private *dev_priv = dev->dev_private;
2305 struct intel_plane *intel_plane;
2306 struct intel_plane_state *pristate = NULL;
2307 struct intel_plane_state *sprstate = NULL;
2308 struct intel_plane_state *curstate = NULL;
2309 int level, max_level = ilk_wm_max_level(dev), usable_level;
2310 struct ilk_wm_maximums max;
2311
2312 pipe_wm = &cstate->wm.optimal.ilk;
2313
2314 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2315 struct intel_plane_state *ps;
2316
2317 ps = intel_atomic_get_existing_plane_state(state,
2318 intel_plane);
2319 if (!ps)
2320 continue;
2321
2322 if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
2323 pristate = ps;
2324 else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
2325 sprstate = ps;
2326 else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
2327 curstate = ps;
2328 }
2329
2330 pipe_wm->pipe_enabled = cstate->base.active;
2331 if (sprstate) {
2332 pipe_wm->sprites_enabled = sprstate->visible;
2333 pipe_wm->sprites_scaled = sprstate->visible &&
2334 (drm_rect_width(&sprstate->dst) != drm_rect_width(&sprstate->src) >> 16 ||
2335 drm_rect_height(&sprstate->dst) != drm_rect_height(&sprstate->src) >> 16);
2336 }
2337
2338 usable_level = max_level;
2339
2340 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2341 if (INTEL_INFO(dev)->gen <= 6 && pipe_wm->sprites_enabled)
2342 usable_level = 1;
2343
2344 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2345 if (pipe_wm->sprites_scaled)
2346 usable_level = 0;
2347
2348 ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
2349 pristate, sprstate, curstate, &pipe_wm->raw_wm[0]);
2350
2351 memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
2352 pipe_wm->wm[0] = pipe_wm->raw_wm[0];
2353
2354 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2355 pipe_wm->linetime = hsw_compute_linetime_wm(cstate);
2356
2357 if (!ilk_validate_pipe_wm(dev, pipe_wm))
2358 return -EINVAL;
2359
2360 ilk_compute_wm_reg_maximums(dev, 1, &max);
2361
2362 for (level = 1; level <= max_level; level++) {
2363 struct intel_wm_level *wm = &pipe_wm->raw_wm[level];
2364
2365 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
2366 pristate, sprstate, curstate, wm);
2367
2368 /*
2369 * Disable any watermark level that exceeds the
2370 * register maximums since such watermarks are
2371 * always invalid.
2372 */
2373 if (level > usable_level)
2374 continue;
2375
2376 if (ilk_validate_wm_level(level, &max, wm))
2377 pipe_wm->wm[level] = *wm;
2378 else
2379 usable_level = level;
2380 }
2381
2382 return 0;
2383 }
2384
2385 /*
2386 * Build a set of 'intermediate' watermark values that satisfy both the old
2387 * state and the new state. These can be programmed to the hardware
2388 * immediately.
2389 */
2390 static int ilk_compute_intermediate_wm(struct drm_device *dev,
2391 struct intel_crtc *intel_crtc,
2392 struct intel_crtc_state *newstate)
2393 {
2394 struct intel_pipe_wm *a = &newstate->wm.intermediate;
2395 struct intel_pipe_wm *b = &intel_crtc->wm.active.ilk;
2396 int level, max_level = ilk_wm_max_level(dev);
2397
2398 /*
2399 * Start with the final, target watermarks, then combine with the
2400 * currently active watermarks to get values that are safe both before
2401 * and after the vblank.
2402 */
2403 *a = newstate->wm.optimal.ilk;
2404 a->pipe_enabled |= b->pipe_enabled;
2405 a->sprites_enabled |= b->sprites_enabled;
2406 a->sprites_scaled |= b->sprites_scaled;
2407
2408 for (level = 0; level <= max_level; level++) {
2409 struct intel_wm_level *a_wm = &a->wm[level];
2410 const struct intel_wm_level *b_wm = &b->wm[level];
2411
2412 a_wm->enable &= b_wm->enable;
2413 a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val);
2414 a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val);
2415 a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val);
2416 a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val);
2417 }
2418
2419 /*
2420 * We need to make sure that these merged watermark values are
2421 * actually a valid configuration themselves. If they're not,
2422 * there's no safe way to transition from the old state to
2423 * the new state, so we need to fail the atomic transaction.
2424 */
2425 if (!ilk_validate_pipe_wm(dev, a))
2426 return -EINVAL;
2427
2428 /*
2429 * If our intermediate WM are identical to the final WM, then we can
2430 * omit the post-vblank programming; only update if it's different.
2431 */
2432 if (memcmp(a, &newstate->wm.optimal.ilk, sizeof(*a)) == 0)
2433 newstate->wm.need_postvbl_update = false;
2434
2435 return 0;
2436 }
2437
2438 /*
2439 * Merge the watermarks from all active pipes for a specific level.
2440 */
2441 static void ilk_merge_wm_level(struct drm_device *dev,
2442 int level,
2443 struct intel_wm_level *ret_wm)
2444 {
2445 const struct intel_crtc *intel_crtc;
2446
2447 ret_wm->enable = true;
2448
2449 for_each_intel_crtc(dev, intel_crtc) {
2450 const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk;
2451 const struct intel_wm_level *wm = &active->wm[level];
2452
2453 if (!active->pipe_enabled)
2454 continue;
2455
2456 /*
2457 * The watermark values may have been used in the past,
2458 * so we must maintain them in the registers for some
2459 * time even if the level is now disabled.
2460 */
2461 if (!wm->enable)
2462 ret_wm->enable = false;
2463
2464 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2465 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2466 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2467 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2468 }
2469 }
2470
2471 /*
2472 * Merge all low power watermarks for all active pipes.
2473 */
2474 static void ilk_wm_merge(struct drm_device *dev,
2475 const struct intel_wm_config *config,
2476 const struct ilk_wm_maximums *max,
2477 struct intel_pipe_wm *merged)
2478 {
2479 struct drm_i915_private *dev_priv = dev->dev_private;
2480 int level, max_level = ilk_wm_max_level(dev);
2481 int last_enabled_level = max_level;
2482
2483 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2484 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2485 config->num_pipes_active > 1)
2486 last_enabled_level = 0;
2487
2488 /* ILK: FBC WM must be disabled always */
2489 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
2490
2491 /* merge each WM1+ level */
2492 for (level = 1; level <= max_level; level++) {
2493 struct intel_wm_level *wm = &merged->wm[level];
2494
2495 ilk_merge_wm_level(dev, level, wm);
2496
2497 if (level > last_enabled_level)
2498 wm->enable = false;
2499 else if (!ilk_validate_wm_level(level, max, wm))
2500 /* make sure all following levels get disabled */
2501 last_enabled_level = level - 1;
2502
2503 /*
2504 * The spec says it is preferred to disable
2505 * FBC WMs instead of disabling a WM level.
2506 */
2507 if (wm->fbc_val > max->fbc) {
2508 if (wm->enable)
2509 merged->fbc_wm_enabled = false;
2510 wm->fbc_val = 0;
2511 }
2512 }
2513
2514 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2515 /*
2516 * FIXME this is racy. FBC might get enabled later.
2517 * What we should check here is whether FBC can be
2518 * enabled sometime later.
2519 */
2520 if (IS_GEN5(dev) && !merged->fbc_wm_enabled &&
2521 intel_fbc_is_active(dev_priv)) {
2522 for (level = 2; level <= max_level; level++) {
2523 struct intel_wm_level *wm = &merged->wm[level];
2524
2525 wm->enable = false;
2526 }
2527 }
2528 }
2529
2530 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2531 {
2532 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2533 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2534 }
2535
2536 /* The value we need to program into the WM_LPx latency field */
2537 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2538 {
2539 struct drm_i915_private *dev_priv = dev->dev_private;
2540
2541 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2542 return 2 * level;
2543 else
2544 return dev_priv->wm.pri_latency[level];
2545 }
2546
2547 static void ilk_compute_wm_results(struct drm_device *dev,
2548 const struct intel_pipe_wm *merged,
2549 enum intel_ddb_partitioning partitioning,
2550 struct ilk_wm_values *results)
2551 {
2552 struct intel_crtc *intel_crtc;
2553 int level, wm_lp;
2554
2555 results->enable_fbc_wm = merged->fbc_wm_enabled;
2556 results->partitioning = partitioning;
2557
2558 /* LP1+ register values */
2559 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2560 const struct intel_wm_level *r;
2561
2562 level = ilk_wm_lp_to_level(wm_lp, merged);
2563
2564 r = &merged->wm[level];
2565
2566 /*
2567 * Maintain the watermark values even if the level is
2568 * disabled. Doing otherwise could cause underruns.
2569 */
2570 results->wm_lp[wm_lp - 1] =
2571 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2572 (r->pri_val << WM1_LP_SR_SHIFT) |
2573 r->cur_val;
2574
2575 if (r->enable)
2576 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2577
2578 if (INTEL_INFO(dev)->gen >= 8)
2579 results->wm_lp[wm_lp - 1] |=
2580 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2581 else
2582 results->wm_lp[wm_lp - 1] |=
2583 r->fbc_val << WM1_LP_FBC_SHIFT;
2584
2585 /*
2586 * Always set WM1S_LP_EN when spr_val != 0, even if the
2587 * level is disabled. Doing otherwise could cause underruns.
2588 */
2589 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2590 WARN_ON(wm_lp != 1);
2591 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2592 } else
2593 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2594 }
2595
2596 /* LP0 register values */
2597 for_each_intel_crtc(dev, intel_crtc) {
2598 enum pipe pipe = intel_crtc->pipe;
2599 const struct intel_wm_level *r =
2600 &intel_crtc->wm.active.ilk.wm[0];
2601
2602 if (WARN_ON(!r->enable))
2603 continue;
2604
2605 results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime;
2606
2607 results->wm_pipe[pipe] =
2608 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2609 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2610 r->cur_val;
2611 }
2612 }
2613
2614 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2615 * case both are at the same level. Prefer r1 in case they're the same. */
2616 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2617 struct intel_pipe_wm *r1,
2618 struct intel_pipe_wm *r2)
2619 {
2620 int level, max_level = ilk_wm_max_level(dev);
2621 int level1 = 0, level2 = 0;
2622
2623 for (level = 1; level <= max_level; level++) {
2624 if (r1->wm[level].enable)
2625 level1 = level;
2626 if (r2->wm[level].enable)
2627 level2 = level;
2628 }
2629
2630 if (level1 == level2) {
2631 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2632 return r2;
2633 else
2634 return r1;
2635 } else if (level1 > level2) {
2636 return r1;
2637 } else {
2638 return r2;
2639 }
2640 }
2641
2642 /* dirty bits used to track which watermarks need changes */
2643 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2644 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2645 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2646 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2647 #define WM_DIRTY_FBC (1 << 24)
2648 #define WM_DIRTY_DDB (1 << 25)
2649
2650 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
2651 const struct ilk_wm_values *old,
2652 const struct ilk_wm_values *new)
2653 {
2654 unsigned int dirty = 0;
2655 enum pipe pipe;
2656 int wm_lp;
2657
2658 for_each_pipe(dev_priv, pipe) {
2659 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2660 dirty |= WM_DIRTY_LINETIME(pipe);
2661 /* Must disable LP1+ watermarks too */
2662 dirty |= WM_DIRTY_LP_ALL;
2663 }
2664
2665 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2666 dirty |= WM_DIRTY_PIPE(pipe);
2667 /* Must disable LP1+ watermarks too */
2668 dirty |= WM_DIRTY_LP_ALL;
2669 }
2670 }
2671
2672 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2673 dirty |= WM_DIRTY_FBC;
2674 /* Must disable LP1+ watermarks too */
2675 dirty |= WM_DIRTY_LP_ALL;
2676 }
2677
2678 if (old->partitioning != new->partitioning) {
2679 dirty |= WM_DIRTY_DDB;
2680 /* Must disable LP1+ watermarks too */
2681 dirty |= WM_DIRTY_LP_ALL;
2682 }
2683
2684 /* LP1+ watermarks already deemed dirty, no need to continue */
2685 if (dirty & WM_DIRTY_LP_ALL)
2686 return dirty;
2687
2688 /* Find the lowest numbered LP1+ watermark in need of an update... */
2689 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2690 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2691 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2692 break;
2693 }
2694
2695 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2696 for (; wm_lp <= 3; wm_lp++)
2697 dirty |= WM_DIRTY_LP(wm_lp);
2698
2699 return dirty;
2700 }
2701
2702 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2703 unsigned int dirty)
2704 {
2705 struct ilk_wm_values *previous = &dev_priv->wm.hw;
2706 bool changed = false;
2707
2708 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2709 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2710 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2711 changed = true;
2712 }
2713 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2714 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2715 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2716 changed = true;
2717 }
2718 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2719 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2720 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2721 changed = true;
2722 }
2723
2724 /*
2725 * Don't touch WM1S_LP_EN here.
2726 * Doing so could cause underruns.
2727 */
2728
2729 return changed;
2730 }
2731
2732 /*
2733 * The spec says we shouldn't write when we don't need, because every write
2734 * causes WMs to be re-evaluated, expending some power.
2735 */
2736 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2737 struct ilk_wm_values *results)
2738 {
2739 struct drm_device *dev = dev_priv->dev;
2740 struct ilk_wm_values *previous = &dev_priv->wm.hw;
2741 unsigned int dirty;
2742 uint32_t val;
2743
2744 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
2745 if (!dirty)
2746 return;
2747
2748 _ilk_disable_lp_wm(dev_priv, dirty);
2749
2750 if (dirty & WM_DIRTY_PIPE(PIPE_A))
2751 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2752 if (dirty & WM_DIRTY_PIPE(PIPE_B))
2753 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2754 if (dirty & WM_DIRTY_PIPE(PIPE_C))
2755 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2756
2757 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2758 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2759 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2760 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2761 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2762 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2763
2764 if (dirty & WM_DIRTY_DDB) {
2765 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2766 val = I915_READ(WM_MISC);
2767 if (results->partitioning == INTEL_DDB_PART_1_2)
2768 val &= ~WM_MISC_DATA_PARTITION_5_6;
2769 else
2770 val |= WM_MISC_DATA_PARTITION_5_6;
2771 I915_WRITE(WM_MISC, val);
2772 } else {
2773 val = I915_READ(DISP_ARB_CTL2);
2774 if (results->partitioning == INTEL_DDB_PART_1_2)
2775 val &= ~DISP_DATA_PARTITION_5_6;
2776 else
2777 val |= DISP_DATA_PARTITION_5_6;
2778 I915_WRITE(DISP_ARB_CTL2, val);
2779 }
2780 }
2781
2782 if (dirty & WM_DIRTY_FBC) {
2783 val = I915_READ(DISP_ARB_CTL);
2784 if (results->enable_fbc_wm)
2785 val &= ~DISP_FBC_WM_DIS;
2786 else
2787 val |= DISP_FBC_WM_DIS;
2788 I915_WRITE(DISP_ARB_CTL, val);
2789 }
2790
2791 if (dirty & WM_DIRTY_LP(1) &&
2792 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2793 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2794
2795 if (INTEL_INFO(dev)->gen >= 7) {
2796 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2797 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2798 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2799 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2800 }
2801
2802 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2803 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2804 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2805 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2806 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2807 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2808
2809 dev_priv->wm.hw = *results;
2810 }
2811
2812 bool ilk_disable_lp_wm(struct drm_device *dev)
2813 {
2814 struct drm_i915_private *dev_priv = dev->dev_private;
2815
2816 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2817 }
2818
2819 /*
2820 * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2821 * different active planes.
2822 */
2823
2824 #define SKL_DDB_SIZE 896 /* in blocks */
2825 #define BXT_DDB_SIZE 512
2826
2827 /*
2828 * Return the index of a plane in the SKL DDB and wm result arrays. Primary
2829 * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
2830 * other universal planes are in indices 1..n. Note that this may leave unused
2831 * indices between the top "sprite" plane and the cursor.
2832 */
2833 static int
2834 skl_wm_plane_id(const struct intel_plane *plane)
2835 {
2836 switch (plane->base.type) {
2837 case DRM_PLANE_TYPE_PRIMARY:
2838 return 0;
2839 case DRM_PLANE_TYPE_CURSOR:
2840 return PLANE_CURSOR;
2841 case DRM_PLANE_TYPE_OVERLAY:
2842 return plane->plane + 1;
2843 default:
2844 MISSING_CASE(plane->base.type);
2845 return plane->plane;
2846 }
2847 }
2848
2849 static void
2850 skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
2851 const struct intel_crtc_state *cstate,
2852 const struct intel_wm_config *config,
2853 struct skl_ddb_entry *alloc /* out */)
2854 {
2855 struct drm_crtc *for_crtc = cstate->base.crtc;
2856 struct drm_crtc *crtc;
2857 unsigned int pipe_size, ddb_size;
2858 int nth_active_pipe;
2859
2860 if (!cstate->base.active) {
2861 alloc->start = 0;
2862 alloc->end = 0;
2863 return;
2864 }
2865
2866 if (IS_BROXTON(dev))
2867 ddb_size = BXT_DDB_SIZE;
2868 else
2869 ddb_size = SKL_DDB_SIZE;
2870
2871 ddb_size -= 4; /* 4 blocks for bypass path allocation */
2872
2873 nth_active_pipe = 0;
2874 for_each_crtc(dev, crtc) {
2875 if (!to_intel_crtc(crtc)->active)
2876 continue;
2877
2878 if (crtc == for_crtc)
2879 break;
2880
2881 nth_active_pipe++;
2882 }
2883
2884 pipe_size = ddb_size / config->num_pipes_active;
2885 alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active;
2886 alloc->end = alloc->start + pipe_size;
2887 }
2888
2889 static unsigned int skl_cursor_allocation(const struct intel_wm_config *config)
2890 {
2891 if (config->num_pipes_active == 1)
2892 return 32;
2893
2894 return 8;
2895 }
2896
2897 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
2898 {
2899 entry->start = reg & 0x3ff;
2900 entry->end = (reg >> 16) & 0x3ff;
2901 if (entry->end)
2902 entry->end += 1;
2903 }
2904
2905 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2906 struct skl_ddb_allocation *ddb /* out */)
2907 {
2908 enum pipe pipe;
2909 int plane;
2910 u32 val;
2911
2912 memset(ddb, 0, sizeof(*ddb));
2913
2914 for_each_pipe(dev_priv, pipe) {
2915 enum intel_display_power_domain power_domain;
2916
2917 power_domain = POWER_DOMAIN_PIPE(pipe);
2918 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
2919 continue;
2920
2921 for_each_plane(dev_priv, pipe, plane) {
2922 val = I915_READ(PLANE_BUF_CFG(pipe, plane));
2923 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
2924 val);
2925 }
2926
2927 val = I915_READ(CUR_BUF_CFG(pipe));
2928 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
2929 val);
2930
2931 intel_display_power_put(dev_priv, power_domain);
2932 }
2933 }
2934
2935 static unsigned int
2936 skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
2937 const struct drm_plane_state *pstate,
2938 int y)
2939 {
2940 struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
2941 struct drm_framebuffer *fb = pstate->fb;
2942 uint32_t width = 0, height = 0;
2943
2944 width = drm_rect_width(&intel_pstate->src) >> 16;
2945 height = drm_rect_height(&intel_pstate->src) >> 16;
2946
2947 if (intel_rotation_90_or_270(pstate->rotation))
2948 swap(width, height);
2949
2950 /* for planar format */
2951 if (fb->pixel_format == DRM_FORMAT_NV12) {
2952 if (y) /* y-plane data rate */
2953 return width * height *
2954 drm_format_plane_cpp(fb->pixel_format, 0);
2955 else /* uv-plane data rate */
2956 return (width / 2) * (height / 2) *
2957 drm_format_plane_cpp(fb->pixel_format, 1);
2958 }
2959
2960 /* for packed formats */
2961 return width * height * drm_format_plane_cpp(fb->pixel_format, 0);
2962 }
2963
2964 /*
2965 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
2966 * a 8192x4096@32bpp framebuffer:
2967 * 3 * 4096 * 8192 * 4 < 2^32
2968 */
2969 static unsigned int
2970 skl_get_total_relative_data_rate(const struct intel_crtc_state *cstate)
2971 {
2972 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
2973 struct drm_device *dev = intel_crtc->base.dev;
2974 const struct intel_plane *intel_plane;
2975 unsigned int total_data_rate = 0;
2976
2977 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2978 const struct drm_plane_state *pstate = intel_plane->base.state;
2979
2980 if (pstate->fb == NULL)
2981 continue;
2982
2983 if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
2984 continue;
2985
2986 /* packed/uv */
2987 total_data_rate += skl_plane_relative_data_rate(cstate,
2988 pstate,
2989 0);
2990
2991 if (pstate->fb->pixel_format == DRM_FORMAT_NV12)
2992 /* y-plane */
2993 total_data_rate += skl_plane_relative_data_rate(cstate,
2994 pstate,
2995 1);
2996 }
2997
2998 return total_data_rate;
2999 }
3000
3001 static void
3002 skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
3003 struct skl_ddb_allocation *ddb /* out */)
3004 {
3005 struct drm_crtc *crtc = cstate->base.crtc;
3006 struct drm_device *dev = crtc->dev;
3007 struct drm_i915_private *dev_priv = to_i915(dev);
3008 struct intel_wm_config *config = &dev_priv->wm.config;
3009 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3010 struct intel_plane *intel_plane;
3011 enum pipe pipe = intel_crtc->pipe;
3012 struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
3013 uint16_t alloc_size, start, cursor_blocks;
3014 uint16_t minimum[I915_MAX_PLANES];
3015 uint16_t y_minimum[I915_MAX_PLANES];
3016 unsigned int total_data_rate;
3017
3018 skl_ddb_get_pipe_allocation_limits(dev, cstate, config, alloc);
3019 alloc_size = skl_ddb_entry_size(alloc);
3020 if (alloc_size == 0) {
3021 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3022 memset(&ddb->plane[pipe][PLANE_CURSOR], 0,
3023 sizeof(ddb->plane[pipe][PLANE_CURSOR]));
3024 return;
3025 }
3026
3027 cursor_blocks = skl_cursor_allocation(config);
3028 ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks;
3029 ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
3030
3031 alloc_size -= cursor_blocks;
3032 alloc->end -= cursor_blocks;
3033
3034 /* 1. Allocate the mininum required blocks for each active plane */
3035 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3036 struct drm_plane *plane = &intel_plane->base;
3037 struct drm_framebuffer *fb = plane->state->fb;
3038 int id = skl_wm_plane_id(intel_plane);
3039
3040 if (!to_intel_plane_state(plane->state)->visible)
3041 continue;
3042
3043 if (plane->type == DRM_PLANE_TYPE_CURSOR)
3044 continue;
3045
3046 minimum[id] = 8;
3047 alloc_size -= minimum[id];
3048 y_minimum[id] = (fb->pixel_format == DRM_FORMAT_NV12) ? 8 : 0;
3049 alloc_size -= y_minimum[id];
3050 }
3051
3052 /*
3053 * 2. Distribute the remaining space in proportion to the amount of
3054 * data each plane needs to fetch from memory.
3055 *
3056 * FIXME: we may not allocate every single block here.
3057 */
3058 total_data_rate = skl_get_total_relative_data_rate(cstate);
3059
3060 start = alloc->start;
3061 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3062 struct drm_plane *plane = &intel_plane->base;
3063 struct drm_plane_state *pstate = intel_plane->base.state;
3064 unsigned int data_rate, y_data_rate;
3065 uint16_t plane_blocks, y_plane_blocks = 0;
3066 int id = skl_wm_plane_id(intel_plane);
3067
3068 if (!to_intel_plane_state(pstate)->visible)
3069 continue;
3070 if (plane->type == DRM_PLANE_TYPE_CURSOR)
3071 continue;
3072
3073 data_rate = skl_plane_relative_data_rate(cstate, pstate, 0);
3074
3075 /*
3076 * allocation for (packed formats) or (uv-plane part of planar format):
3077 * promote the expression to 64 bits to avoid overflowing, the
3078 * result is < available as data_rate / total_data_rate < 1
3079 */
3080 plane_blocks = minimum[id];
3081 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3082 total_data_rate);
3083
3084 ddb->plane[pipe][id].start = start;
3085 ddb->plane[pipe][id].end = start + plane_blocks;
3086
3087 start += plane_blocks;
3088
3089 /*
3090 * allocation for y_plane part of planar format:
3091 */
3092 if (pstate->fb->pixel_format == DRM_FORMAT_NV12) {
3093 y_data_rate = skl_plane_relative_data_rate(cstate,
3094 pstate,
3095 1);
3096 y_plane_blocks = y_minimum[id];
3097 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3098 total_data_rate);
3099
3100 ddb->y_plane[pipe][id].start = start;
3101 ddb->y_plane[pipe][id].end = start + y_plane_blocks;
3102
3103 start += y_plane_blocks;
3104 }
3105
3106 }
3107
3108 }
3109
3110 static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
3111 {
3112 /* TODO: Take into account the scalers once we support them */
3113 return config->base.adjusted_mode.crtc_clock;
3114 }
3115
3116 /*
3117 * The max latency should be 257 (max the punit can code is 255 and we add 2us
3118 * for the read latency) and cpp should always be <= 8, so that
3119 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3120 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3121 */
3122 static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
3123 {
3124 uint32_t wm_intermediate_val, ret;
3125
3126 if (latency == 0)
3127 return UINT_MAX;
3128
3129 wm_intermediate_val = latency * pixel_rate * cpp / 512;
3130 ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3131
3132 return ret;
3133 }
3134
3135 static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
3136 uint32_t horiz_pixels, uint8_t cpp,
3137 uint64_t tiling, uint32_t latency)
3138 {
3139 uint32_t ret;
3140 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3141 uint32_t wm_intermediate_val;
3142
3143 if (latency == 0)
3144 return UINT_MAX;
3145
3146 plane_bytes_per_line = horiz_pixels * cpp;
3147
3148 if (tiling == I915_FORMAT_MOD_Y_TILED ||
3149 tiling == I915_FORMAT_MOD_Yf_TILED) {
3150 plane_bytes_per_line *= 4;
3151 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3152 plane_blocks_per_line /= 4;
3153 } else {
3154 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3155 }
3156
3157 wm_intermediate_val = latency * pixel_rate;
3158 ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
3159 plane_blocks_per_line;
3160
3161 return ret;
3162 }
3163
3164 static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb,
3165 const struct intel_crtc *intel_crtc)
3166 {
3167 struct drm_device *dev = intel_crtc->base.dev;
3168 struct drm_i915_private *dev_priv = dev->dev_private;
3169 const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
3170
3171 /*
3172 * If ddb allocation of pipes changed, it may require recalculation of
3173 * watermarks
3174 */
3175 if (memcmp(new_ddb->pipe, cur_ddb->pipe, sizeof(new_ddb->pipe)))
3176 return true;
3177
3178 return false;
3179 }
3180
3181 static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3182 struct intel_crtc_state *cstate,
3183 struct intel_plane *intel_plane,
3184 uint16_t ddb_allocation,
3185 int level,
3186 uint16_t *out_blocks, /* out */
3187 uint8_t *out_lines /* out */)
3188 {
3189 struct drm_plane *plane = &intel_plane->base;
3190 struct drm_framebuffer *fb = plane->state->fb;
3191 struct intel_plane_state *intel_pstate =
3192 to_intel_plane_state(plane->state);
3193 uint32_t latency = dev_priv->wm.skl_latency[level];
3194 uint32_t method1, method2;
3195 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3196 uint32_t res_blocks, res_lines;
3197 uint32_t selected_result;
3198 uint8_t cpp;
3199 uint32_t width = 0, height = 0;
3200
3201 if (latency == 0 || !cstate->base.active || !intel_pstate->visible)
3202 return false;
3203
3204 width = drm_rect_width(&intel_pstate->src) >> 16;
3205 height = drm_rect_height(&intel_pstate->src) >> 16;
3206
3207 if (intel_rotation_90_or_270(plane->state->rotation))
3208 swap(width, height);
3209
3210 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
3211 method1 = skl_wm_method1(skl_pipe_pixel_rate(cstate),
3212 cpp, latency);
3213 method2 = skl_wm_method2(skl_pipe_pixel_rate(cstate),
3214 cstate->base.adjusted_mode.crtc_htotal,
3215 width,
3216 cpp,
3217 fb->modifier[0],
3218 latency);
3219
3220 plane_bytes_per_line = width * cpp;
3221 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3222
3223 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3224 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
3225 uint32_t min_scanlines = 4;
3226 uint32_t y_tile_minimum;
3227 if (intel_rotation_90_or_270(plane->state->rotation)) {
3228 int cpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
3229 drm_format_plane_cpp(fb->pixel_format, 1) :
3230 drm_format_plane_cpp(fb->pixel_format, 0);
3231
3232 switch (cpp) {
3233 case 1:
3234 min_scanlines = 16;
3235 break;
3236 case 2:
3237 min_scanlines = 8;
3238 break;
3239 case 8:
3240 WARN(1, "Unsupported pixel depth for rotation");
3241 }
3242 }
3243 y_tile_minimum = plane_blocks_per_line * min_scanlines;
3244 selected_result = max(method2, y_tile_minimum);
3245 } else {
3246 if ((ddb_allocation / plane_blocks_per_line) >= 1)
3247 selected_result = min(method1, method2);
3248 else
3249 selected_result = method1;
3250 }
3251
3252 res_blocks = selected_result + 1;
3253 res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
3254
3255 if (level >= 1 && level <= 7) {
3256 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3257 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED)
3258 res_lines += 4;
3259 else
3260 res_blocks++;
3261 }
3262
3263 if (res_blocks >= ddb_allocation || res_lines > 31)
3264 return false;
3265
3266 *out_blocks = res_blocks;
3267 *out_lines = res_lines;
3268
3269 return true;
3270 }
3271
3272 static void skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3273 struct skl_ddb_allocation *ddb,
3274 struct intel_crtc_state *cstate,
3275 int level,
3276 struct skl_wm_level *result)
3277 {
3278 struct drm_device *dev = dev_priv->dev;
3279 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
3280 struct intel_plane *intel_plane;
3281 uint16_t ddb_blocks;
3282 enum pipe pipe = intel_crtc->pipe;
3283
3284 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3285 int i = skl_wm_plane_id(intel_plane);
3286
3287 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3288
3289 result->plane_en[i] = skl_compute_plane_wm(dev_priv,
3290 cstate,
3291 intel_plane,
3292 ddb_blocks,
3293 level,
3294 &result->plane_res_b[i],
3295 &result->plane_res_l[i]);
3296 }
3297 }
3298
3299 static uint32_t
3300 skl_compute_linetime_wm(struct intel_crtc_state *cstate)
3301 {
3302 if (!cstate->base.active)
3303 return 0;
3304
3305 if (WARN_ON(skl_pipe_pixel_rate(cstate) == 0))
3306 return 0;
3307
3308 return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
3309 skl_pipe_pixel_rate(cstate));
3310 }
3311
3312 static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
3313 struct skl_wm_level *trans_wm /* out */)
3314 {
3315 struct drm_crtc *crtc = cstate->base.crtc;
3316 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3317 struct intel_plane *intel_plane;
3318
3319 if (!cstate->base.active)
3320 return;
3321
3322 /* Until we know more, just disable transition WMs */
3323 for_each_intel_plane_on_crtc(crtc->dev, intel_crtc, intel_plane) {
3324 int i = skl_wm_plane_id(intel_plane);
3325
3326 trans_wm->plane_en[i] = false;
3327 }
3328 }
3329
3330 static void skl_compute_pipe_wm(struct intel_crtc_state *cstate,
3331 struct skl_ddb_allocation *ddb,
3332 struct skl_pipe_wm *pipe_wm)
3333 {
3334 struct drm_device *dev = cstate->base.crtc->dev;
3335 const struct drm_i915_private *dev_priv = dev->dev_private;
3336 int level, max_level = ilk_wm_max_level(dev);
3337
3338 for (level = 0; level <= max_level; level++) {
3339 skl_compute_wm_level(dev_priv, ddb, cstate,
3340 level, &pipe_wm->wm[level]);
3341 }
3342 pipe_wm->linetime = skl_compute_linetime_wm(cstate);
3343
3344 skl_compute_transition_wm(cstate, &pipe_wm->trans_wm);
3345 }
3346
3347 static void skl_compute_wm_results(struct drm_device *dev,
3348 struct skl_pipe_wm *p_wm,
3349 struct skl_wm_values *r,
3350 struct intel_crtc *intel_crtc)
3351 {
3352 int level, max_level = ilk_wm_max_level(dev);
3353 enum pipe pipe = intel_crtc->pipe;
3354 uint32_t temp;
3355 int i;
3356
3357 for (level = 0; level <= max_level; level++) {
3358 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3359 temp = 0;
3360
3361 temp |= p_wm->wm[level].plane_res_l[i] <<
3362 PLANE_WM_LINES_SHIFT;
3363 temp |= p_wm->wm[level].plane_res_b[i];
3364 if (p_wm->wm[level].plane_en[i])
3365 temp |= PLANE_WM_EN;
3366
3367 r->plane[pipe][i][level] = temp;
3368 }
3369
3370 temp = 0;
3371
3372 temp |= p_wm->wm[level].plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3373 temp |= p_wm->wm[level].plane_res_b[PLANE_CURSOR];
3374
3375 if (p_wm->wm[level].plane_en[PLANE_CURSOR])
3376 temp |= PLANE_WM_EN;
3377
3378 r->plane[pipe][PLANE_CURSOR][level] = temp;
3379
3380 }
3381
3382 /* transition WMs */
3383 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3384 temp = 0;
3385 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3386 temp |= p_wm->trans_wm.plane_res_b[i];
3387 if (p_wm->trans_wm.plane_en[i])
3388 temp |= PLANE_WM_EN;
3389
3390 r->plane_trans[pipe][i] = temp;
3391 }
3392
3393 temp = 0;
3394 temp |= p_wm->trans_wm.plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3395 temp |= p_wm->trans_wm.plane_res_b[PLANE_CURSOR];
3396 if (p_wm->trans_wm.plane_en[PLANE_CURSOR])
3397 temp |= PLANE_WM_EN;
3398
3399 r->plane_trans[pipe][PLANE_CURSOR] = temp;
3400
3401 r->wm_linetime[pipe] = p_wm->linetime;
3402 }
3403
3404 static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
3405 i915_reg_t reg,
3406 const struct skl_ddb_entry *entry)
3407 {
3408 if (entry->end)
3409 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3410 else
3411 I915_WRITE(reg, 0);
3412 }
3413
3414 static void skl_write_wm_values(struct drm_i915_private *dev_priv,
3415 const struct skl_wm_values *new)
3416 {
3417 struct drm_device *dev = dev_priv->dev;
3418 struct intel_crtc *crtc;
3419
3420 for_each_intel_crtc(dev, crtc) {
3421 int i, level, max_level = ilk_wm_max_level(dev);
3422 enum pipe pipe = crtc->pipe;
3423
3424 if (!new->dirty[pipe])
3425 continue;
3426
3427 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]);
3428
3429 for (level = 0; level <= max_level; level++) {
3430 for (i = 0; i < intel_num_planes(crtc); i++)
3431 I915_WRITE(PLANE_WM(pipe, i, level),
3432 new->plane[pipe][i][level]);
3433 I915_WRITE(CUR_WM(pipe, level),
3434 new->plane[pipe][PLANE_CURSOR][level]);
3435 }
3436 for (i = 0; i < intel_num_planes(crtc); i++)
3437 I915_WRITE(PLANE_WM_TRANS(pipe, i),
3438 new->plane_trans[pipe][i]);
3439 I915_WRITE(CUR_WM_TRANS(pipe),
3440 new->plane_trans[pipe][PLANE_CURSOR]);
3441
3442 for (i = 0; i < intel_num_planes(crtc); i++) {
3443 skl_ddb_entry_write(dev_priv,
3444 PLANE_BUF_CFG(pipe, i),
3445 &new->ddb.plane[pipe][i]);
3446 skl_ddb_entry_write(dev_priv,
3447 PLANE_NV12_BUF_CFG(pipe, i),
3448 &new->ddb.y_plane[pipe][i]);
3449 }
3450
3451 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3452 &new->ddb.plane[pipe][PLANE_CURSOR]);
3453 }
3454 }
3455
3456 /*
3457 * When setting up a new DDB allocation arrangement, we need to correctly
3458 * sequence the times at which the new allocations for the pipes are taken into
3459 * account or we'll have pipes fetching from space previously allocated to
3460 * another pipe.
3461 *
3462 * Roughly the sequence looks like:
3463 * 1. re-allocate the pipe(s) with the allocation being reduced and not
3464 * overlapping with a previous light-up pipe (another way to put it is:
3465 * pipes with their new allocation strickly included into their old ones).
3466 * 2. re-allocate the other pipes that get their allocation reduced
3467 * 3. allocate the pipes having their allocation increased
3468 *
3469 * Steps 1. and 2. are here to take care of the following case:
3470 * - Initially DDB looks like this:
3471 * | B | C |
3472 * - enable pipe A.
3473 * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
3474 * allocation
3475 * | A | B | C |
3476 *
3477 * We need to sequence the re-allocation: C, B, A (and not B, C, A).
3478 */
3479
3480 static void
3481 skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass)
3482 {
3483 int plane;
3484
3485 DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);
3486
3487 for_each_plane(dev_priv, pipe, plane) {
3488 I915_WRITE(PLANE_SURF(pipe, plane),
3489 I915_READ(PLANE_SURF(pipe, plane)));
3490 }
3491 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3492 }
3493
3494 static bool
3495 skl_ddb_allocation_included(const struct skl_ddb_allocation *old,
3496 const struct skl_ddb_allocation *new,
3497 enum pipe pipe)
3498 {
3499 uint16_t old_size, new_size;
3500
3501 old_size = skl_ddb_entry_size(&old->pipe[pipe]);
3502 new_size = skl_ddb_entry_size(&new->pipe[pipe]);
3503
3504 return old_size != new_size &&
3505 new->pipe[pipe].start >= old->pipe[pipe].start &&
3506 new->pipe[pipe].end <= old->pipe[pipe].end;
3507 }
3508
3509 static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
3510 struct skl_wm_values *new_values)
3511 {
3512 struct drm_device *dev = dev_priv->dev;
3513 struct skl_ddb_allocation *cur_ddb, *new_ddb;
3514 bool reallocated[I915_MAX_PIPES] = {};
3515 struct intel_crtc *crtc;
3516 enum pipe pipe;
3517
3518 new_ddb = &new_values->ddb;
3519 cur_ddb = &dev_priv->wm.skl_hw.ddb;
3520
3521 /*
3522 * First pass: flush the pipes with the new allocation contained into
3523 * the old space.
3524 *
3525 * We'll wait for the vblank on those pipes to ensure we can safely
3526 * re-allocate the freed space without this pipe fetching from it.
3527 */
3528 for_each_intel_crtc(dev, crtc) {
3529 if (!crtc->active)
3530 continue;
3531
3532 pipe = crtc->pipe;
3533
3534 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))
3535 continue;
3536
3537 skl_wm_flush_pipe(dev_priv, pipe, 1);
3538 intel_wait_for_vblank(dev, pipe);
3539
3540 reallocated[pipe] = true;
3541 }
3542
3543
3544 /*
3545 * Second pass: flush the pipes that are having their allocation
3546 * reduced, but overlapping with a previous allocation.
3547 *
3548 * Here as well we need to wait for the vblank to make sure the freed
3549 * space is not used anymore.
3550 */
3551 for_each_intel_crtc(dev, crtc) {
3552 if (!crtc->active)
3553 continue;
3554
3555 pipe = crtc->pipe;
3556
3557 if (reallocated[pipe])
3558 continue;
3559
3560 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <
3561 skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
3562 skl_wm_flush_pipe(dev_priv, pipe, 2);
3563 intel_wait_for_vblank(dev, pipe);
3564 reallocated[pipe] = true;
3565 }
3566 }
3567
3568 /*
3569 * Third pass: flush the pipes that got more space allocated.
3570 *
3571 * We don't need to actively wait for the update here, next vblank
3572 * will just get more DDB space with the correct WM values.
3573 */
3574 for_each_intel_crtc(dev, crtc) {
3575 if (!crtc->active)
3576 continue;
3577
3578 pipe = crtc->pipe;
3579
3580 /*
3581 * At this point, only the pipes more space than before are
3582 * left to re-allocate.
3583 */
3584 if (reallocated[pipe])
3585 continue;
3586
3587 skl_wm_flush_pipe(dev_priv, pipe, 3);
3588 }
3589 }
3590
3591 static bool skl_update_pipe_wm(struct drm_crtc *crtc,
3592 struct skl_ddb_allocation *ddb, /* out */
3593 struct skl_pipe_wm *pipe_wm /* out */)
3594 {
3595 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3596 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3597
3598 skl_allocate_pipe_ddb(cstate, ddb);
3599 skl_compute_pipe_wm(cstate, ddb, pipe_wm);
3600
3601 if (!memcmp(&intel_crtc->wm.active.skl, pipe_wm, sizeof(*pipe_wm)))
3602 return false;
3603
3604 intel_crtc->wm.active.skl = *pipe_wm;
3605
3606 return true;
3607 }
3608
3609 static void skl_update_other_pipe_wm(struct drm_device *dev,
3610 struct drm_crtc *crtc,
3611 struct skl_wm_values *r)
3612 {
3613 struct intel_crtc *intel_crtc;
3614 struct intel_crtc *this_crtc = to_intel_crtc(crtc);
3615
3616 /*
3617 * If the WM update hasn't changed the allocation for this_crtc (the
3618 * crtc we are currently computing the new WM values for), other
3619 * enabled crtcs will keep the same allocation and we don't need to
3620 * recompute anything for them.
3621 */
3622 if (!skl_ddb_allocation_changed(&r->ddb, this_crtc))
3623 return;
3624
3625 /*
3626 * Otherwise, because of this_crtc being freshly enabled/disabled, the
3627 * other active pipes need new DDB allocation and WM values.
3628 */
3629 for_each_intel_crtc(dev, intel_crtc) {
3630 struct skl_pipe_wm pipe_wm = {};
3631 bool wm_changed;
3632
3633 if (this_crtc->pipe == intel_crtc->pipe)
3634 continue;
3635
3636 if (!intel_crtc->active)
3637 continue;
3638
3639 wm_changed = skl_update_pipe_wm(&intel_crtc->base,
3640 &r->ddb, &pipe_wm);
3641
3642 /*
3643 * If we end up re-computing the other pipe WM values, it's
3644 * because it was really needed, so we expect the WM values to
3645 * be different.
3646 */
3647 WARN_ON(!wm_changed);
3648
3649 skl_compute_wm_results(dev, &pipe_wm, r, intel_crtc);
3650 r->dirty[intel_crtc->pipe] = true;
3651 }
3652 }
3653
3654 static void skl_clear_wm(struct skl_wm_values *watermarks, enum pipe pipe)
3655 {
3656 watermarks->wm_linetime[pipe] = 0;
3657 memset(watermarks->plane[pipe], 0,
3658 sizeof(uint32_t) * 8 * I915_MAX_PLANES);
3659 memset(watermarks->plane_trans[pipe],
3660 0, sizeof(uint32_t) * I915_MAX_PLANES);
3661 watermarks->plane_trans[pipe][PLANE_CURSOR] = 0;
3662
3663 /* Clear ddb entries for pipe */
3664 memset(&watermarks->ddb.pipe[pipe], 0, sizeof(struct skl_ddb_entry));
3665 memset(&watermarks->ddb.plane[pipe], 0,
3666 sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
3667 memset(&watermarks->ddb.y_plane[pipe], 0,
3668 sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
3669 memset(&watermarks->ddb.plane[pipe][PLANE_CURSOR], 0,
3670 sizeof(struct skl_ddb_entry));
3671
3672 }
3673
3674 static void skl_update_wm(struct drm_crtc *crtc)
3675 {
3676 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3677 struct drm_device *dev = crtc->dev;
3678 struct drm_i915_private *dev_priv = dev->dev_private;
3679 struct skl_wm_values *results = &dev_priv->wm.skl_results;
3680 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3681 struct skl_pipe_wm *pipe_wm = &cstate->wm.optimal.skl;
3682
3683
3684 /* Clear all dirty flags */
3685 memset(results->dirty, 0, sizeof(bool) * I915_MAX_PIPES);
3686
3687 skl_clear_wm(results, intel_crtc->pipe);
3688
3689 if (!skl_update_pipe_wm(crtc, &results->ddb, pipe_wm))
3690 return;
3691
3692 skl_compute_wm_results(dev, pipe_wm, results, intel_crtc);
3693 results->dirty[intel_crtc->pipe] = true;
3694
3695 skl_update_other_pipe_wm(dev, crtc, results);
3696 skl_write_wm_values(dev_priv, results);
3697 skl_flush_wm_values(dev_priv, results);
3698
3699 /* store the new configuration */
3700 dev_priv->wm.skl_hw = *results;
3701 }
3702
3703 static void ilk_compute_wm_config(struct drm_device *dev,
3704 struct intel_wm_config *config)
3705 {
3706 struct intel_crtc *crtc;
3707
3708 /* Compute the currently _active_ config */
3709 for_each_intel_crtc(dev, crtc) {
3710 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
3711
3712 if (!wm->pipe_enabled)
3713 continue;
3714
3715 config->sprites_enabled |= wm->sprites_enabled;
3716 config->sprites_scaled |= wm->sprites_scaled;
3717 config->num_pipes_active++;
3718 }
3719 }
3720
3721 static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
3722 {
3723 struct drm_device *dev = dev_priv->dev;
3724 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
3725 struct ilk_wm_maximums max;
3726 struct intel_wm_config config = {};
3727 struct ilk_wm_values results = {};
3728 enum intel_ddb_partitioning partitioning;
3729
3730 ilk_compute_wm_config(dev, &config);
3731
3732 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
3733 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
3734
3735 /* 5/6 split only in single pipe config on IVB+ */
3736 if (INTEL_INFO(dev)->gen >= 7 &&
3737 config.num_pipes_active == 1 && config.sprites_enabled) {
3738 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
3739 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
3740
3741 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
3742 } else {
3743 best_lp_wm = &lp_wm_1_2;
3744 }
3745
3746 partitioning = (best_lp_wm == &lp_wm_1_2) ?
3747 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
3748
3749 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
3750
3751 ilk_write_wm_values(dev_priv, &results);
3752 }
3753
3754 static void ilk_initial_watermarks(struct intel_crtc_state *cstate)
3755 {
3756 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
3757 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
3758
3759 mutex_lock(&dev_priv->wm.wm_mutex);
3760 intel_crtc->wm.active.ilk = cstate->wm.intermediate;
3761 ilk_program_watermarks(dev_priv);
3762 mutex_unlock(&dev_priv->wm.wm_mutex);
3763 }
3764
3765 static void ilk_optimize_watermarks(struct intel_crtc_state *cstate)
3766 {
3767 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
3768 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
3769
3770 mutex_lock(&dev_priv->wm.wm_mutex);
3771 if (cstate->wm.need_postvbl_update) {
3772 intel_crtc->wm.active.ilk = cstate->wm.optimal.ilk;
3773 ilk_program_watermarks(dev_priv);
3774 }
3775 mutex_unlock(&dev_priv->wm.wm_mutex);
3776 }
3777
3778 static void skl_pipe_wm_active_state(uint32_t val,
3779 struct skl_pipe_wm *active,
3780 bool is_transwm,
3781 bool is_cursor,
3782 int i,
3783 int level)
3784 {
3785 bool is_enabled = (val & PLANE_WM_EN) != 0;
3786
3787 if (!is_transwm) {
3788 if (!is_cursor) {
3789 active->wm[level].plane_en[i] = is_enabled;
3790 active->wm[level].plane_res_b[i] =
3791 val & PLANE_WM_BLOCKS_MASK;
3792 active->wm[level].plane_res_l[i] =
3793 (val >> PLANE_WM_LINES_SHIFT) &
3794 PLANE_WM_LINES_MASK;
3795 } else {
3796 active->wm[level].plane_en[PLANE_CURSOR] = is_enabled;
3797 active->wm[level].plane_res_b[PLANE_CURSOR] =
3798 val & PLANE_WM_BLOCKS_MASK;
3799 active->wm[level].plane_res_l[PLANE_CURSOR] =
3800 (val >> PLANE_WM_LINES_SHIFT) &
3801 PLANE_WM_LINES_MASK;
3802 }
3803 } else {
3804 if (!is_cursor) {
3805 active->trans_wm.plane_en[i] = is_enabled;
3806 active->trans_wm.plane_res_b[i] =
3807 val & PLANE_WM_BLOCKS_MASK;
3808 active->trans_wm.plane_res_l[i] =
3809 (val >> PLANE_WM_LINES_SHIFT) &
3810 PLANE_WM_LINES_MASK;
3811 } else {
3812 active->trans_wm.plane_en[PLANE_CURSOR] = is_enabled;
3813 active->trans_wm.plane_res_b[PLANE_CURSOR] =
3814 val & PLANE_WM_BLOCKS_MASK;
3815 active->trans_wm.plane_res_l[PLANE_CURSOR] =
3816 (val >> PLANE_WM_LINES_SHIFT) &
3817 PLANE_WM_LINES_MASK;
3818 }
3819 }
3820 }
3821
3822 static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3823 {
3824 struct drm_device *dev = crtc->dev;
3825 struct drm_i915_private *dev_priv = dev->dev_private;
3826 struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
3827 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3828 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3829 struct skl_pipe_wm *active = &cstate->wm.optimal.skl;
3830 enum pipe pipe = intel_crtc->pipe;
3831 int level, i, max_level;
3832 uint32_t temp;
3833
3834 max_level = ilk_wm_max_level(dev);
3835
3836 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3837
3838 for (level = 0; level <= max_level; level++) {
3839 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3840 hw->plane[pipe][i][level] =
3841 I915_READ(PLANE_WM(pipe, i, level));
3842 hw->plane[pipe][PLANE_CURSOR][level] = I915_READ(CUR_WM(pipe, level));
3843 }
3844
3845 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3846 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
3847 hw->plane_trans[pipe][PLANE_CURSOR] = I915_READ(CUR_WM_TRANS(pipe));
3848
3849 if (!intel_crtc->active)
3850 return;
3851
3852 hw->dirty[pipe] = true;
3853
3854 active->linetime = hw->wm_linetime[pipe];
3855
3856 for (level = 0; level <= max_level; level++) {
3857 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3858 temp = hw->plane[pipe][i][level];
3859 skl_pipe_wm_active_state(temp, active, false,
3860 false, i, level);
3861 }
3862 temp = hw->plane[pipe][PLANE_CURSOR][level];
3863 skl_pipe_wm_active_state(temp, active, false, true, i, level);
3864 }
3865
3866 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3867 temp = hw->plane_trans[pipe][i];
3868 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
3869 }
3870
3871 temp = hw->plane_trans[pipe][PLANE_CURSOR];
3872 skl_pipe_wm_active_state(temp, active, true, true, i, 0);
3873
3874 intel_crtc->wm.active.skl = *active;
3875 }
3876
3877 void skl_wm_get_hw_state(struct drm_device *dev)
3878 {
3879 struct drm_i915_private *dev_priv = dev->dev_private;
3880 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3881 struct drm_crtc *crtc;
3882
3883 skl_ddb_get_hw_state(dev_priv, ddb);
3884 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3885 skl_pipe_wm_get_hw_state(crtc);
3886 }
3887
3888 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3889 {
3890 struct drm_device *dev = crtc->dev;
3891 struct drm_i915_private *dev_priv = dev->dev_private;
3892 struct ilk_wm_values *hw = &dev_priv->wm.hw;
3893 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3894 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3895 struct intel_pipe_wm *active = &cstate->wm.optimal.ilk;
3896 enum pipe pipe = intel_crtc->pipe;
3897 static const i915_reg_t wm0_pipe_reg[] = {
3898 [PIPE_A] = WM0_PIPEA_ILK,
3899 [PIPE_B] = WM0_PIPEB_ILK,
3900 [PIPE_C] = WM0_PIPEC_IVB,
3901 };
3902
3903 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
3904 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3905 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3906
3907 active->pipe_enabled = intel_crtc->active;
3908
3909 if (active->pipe_enabled) {
3910 u32 tmp = hw->wm_pipe[pipe];
3911
3912 /*
3913 * For active pipes LP0 watermark is marked as
3914 * enabled, and LP1+ watermaks as disabled since
3915 * we can't really reverse compute them in case
3916 * multiple pipes are active.
3917 */
3918 active->wm[0].enable = true;
3919 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3920 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3921 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3922 active->linetime = hw->wm_linetime[pipe];
3923 } else {
3924 int level, max_level = ilk_wm_max_level(dev);
3925
3926 /*
3927 * For inactive pipes, all watermark levels
3928 * should be marked as enabled but zeroed,
3929 * which is what we'd compute them to.
3930 */
3931 for (level = 0; level <= max_level; level++)
3932 active->wm[level].enable = true;
3933 }
3934
3935 intel_crtc->wm.active.ilk = *active;
3936 }
3937
3938 #define _FW_WM(value, plane) \
3939 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
3940 #define _FW_WM_VLV(value, plane) \
3941 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
3942
3943 static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
3944 struct vlv_wm_values *wm)
3945 {
3946 enum pipe pipe;
3947 uint32_t tmp;
3948
3949 for_each_pipe(dev_priv, pipe) {
3950 tmp = I915_READ(VLV_DDL(pipe));
3951
3952 wm->ddl[pipe].primary =
3953 (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3954 wm->ddl[pipe].cursor =
3955 (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3956 wm->ddl[pipe].sprite[0] =
3957 (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3958 wm->ddl[pipe].sprite[1] =
3959 (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3960 }
3961
3962 tmp = I915_READ(DSPFW1);
3963 wm->sr.plane = _FW_WM(tmp, SR);
3964 wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
3965 wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
3966 wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
3967
3968 tmp = I915_READ(DSPFW2);
3969 wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
3970 wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
3971 wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
3972
3973 tmp = I915_READ(DSPFW3);
3974 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
3975
3976 if (IS_CHERRYVIEW(dev_priv)) {
3977 tmp = I915_READ(DSPFW7_CHV);
3978 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
3979 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
3980
3981 tmp = I915_READ(DSPFW8_CHV);
3982 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
3983 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
3984
3985 tmp = I915_READ(DSPFW9_CHV);
3986 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
3987 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
3988
3989 tmp = I915_READ(DSPHOWM);
3990 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
3991 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
3992 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
3993 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
3994 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
3995 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
3996 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
3997 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
3998 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
3999 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4000 } else {
4001 tmp = I915_READ(DSPFW7);
4002 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4003 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4004
4005 tmp = I915_READ(DSPHOWM);
4006 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4007 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4008 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4009 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4010 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4011 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4012 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4013 }
4014 }
4015
4016 #undef _FW_WM
4017 #undef _FW_WM_VLV
4018
4019 void vlv_wm_get_hw_state(struct drm_device *dev)
4020 {
4021 struct drm_i915_private *dev_priv = to_i915(dev);
4022 struct vlv_wm_values *wm = &dev_priv->wm.vlv;
4023 struct intel_plane *plane;
4024 enum pipe pipe;
4025 u32 val;
4026
4027 vlv_read_wm_values(dev_priv, wm);
4028
4029 for_each_intel_plane(dev, plane) {
4030 switch (plane->base.type) {
4031 int sprite;
4032 case DRM_PLANE_TYPE_CURSOR:
4033 plane->wm.fifo_size = 63;
4034 break;
4035 case DRM_PLANE_TYPE_PRIMARY:
4036 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
4037 break;
4038 case DRM_PLANE_TYPE_OVERLAY:
4039 sprite = plane->plane;
4040 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
4041 break;
4042 }
4043 }
4044
4045 wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4046 wm->level = VLV_WM_LEVEL_PM2;
4047
4048 if (IS_CHERRYVIEW(dev_priv)) {
4049 mutex_lock(&dev_priv->rps.hw_lock);
4050
4051 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4052 if (val & DSP_MAXFIFO_PM5_ENABLE)
4053 wm->level = VLV_WM_LEVEL_PM5;
4054
4055 /*
4056 * If DDR DVFS is disabled in the BIOS, Punit
4057 * will never ack the request. So if that happens
4058 * assume we don't have to enable/disable DDR DVFS
4059 * dynamically. To test that just set the REQ_ACK
4060 * bit to poke the Punit, but don't change the
4061 * HIGH/LOW bits so that we don't actually change
4062 * the current state.
4063 */
4064 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4065 val |= FORCE_DDR_FREQ_REQ_ACK;
4066 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
4067
4068 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
4069 FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
4070 DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4071 "assuming DDR DVFS is disabled\n");
4072 dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
4073 } else {
4074 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4075 if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4076 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4077 }
4078
4079 mutex_unlock(&dev_priv->rps.hw_lock);
4080 }
4081
4082 for_each_pipe(dev_priv, pipe)
4083 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4084 pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4085 wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4086
4087 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4088 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4089 }
4090
4091 void ilk_wm_get_hw_state(struct drm_device *dev)
4092 {
4093 struct drm_i915_private *dev_priv = dev->dev_private;
4094 struct ilk_wm_values *hw = &dev_priv->wm.hw;
4095 struct drm_crtc *crtc;
4096
4097 for_each_crtc(dev, crtc)
4098 ilk_pipe_wm_get_hw_state(crtc);
4099
4100 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4101 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4102 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4103
4104 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
4105 if (INTEL_INFO(dev)->gen >= 7) {
4106 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4107 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4108 }
4109
4110 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4111 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4112 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4113 else if (IS_IVYBRIDGE(dev))
4114 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4115 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4116
4117 hw->enable_fbc_wm =
4118 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4119 }
4120
4121 /**
4122 * intel_update_watermarks - update FIFO watermark values based on current modes
4123 *
4124 * Calculate watermark values for the various WM regs based on current mode
4125 * and plane configuration.
4126 *
4127 * There are several cases to deal with here:
4128 * - normal (i.e. non-self-refresh)
4129 * - self-refresh (SR) mode
4130 * - lines are large relative to FIFO size (buffer can hold up to 2)
4131 * - lines are small relative to FIFO size (buffer can hold more than 2
4132 * lines), so need to account for TLB latency
4133 *
4134 * The normal calculation is:
4135 * watermark = dotclock * bytes per pixel * latency
4136 * where latency is platform & configuration dependent (we assume pessimal
4137 * values here).
4138 *
4139 * The SR calculation is:
4140 * watermark = (trunc(latency/line time)+1) * surface width *
4141 * bytes per pixel
4142 * where
4143 * line time = htotal / dotclock
4144 * surface width = hdisplay for normal plane and 64 for cursor
4145 * and latency is assumed to be high, as above.
4146 *
4147 * The final value programmed to the register should always be rounded up,
4148 * and include an extra 2 entries to account for clock crossings.
4149 *
4150 * We don't use the sprite, so we can ignore that. And on Crestline we have
4151 * to set the non-SR watermarks to 8.
4152 */
4153 void intel_update_watermarks(struct drm_crtc *crtc)
4154 {
4155 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4156
4157 if (dev_priv->display.update_wm)
4158 dev_priv->display.update_wm(crtc);
4159 }
4160
4161 /*
4162 * Lock protecting IPS related data structures
4163 */
4164 DEFINE_SPINLOCK(mchdev_lock);
4165
4166 /* Global for IPS driver to get at the current i915 device. Protected by
4167 * mchdev_lock. */
4168 static struct drm_i915_private *i915_mch_dev;
4169
4170 bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val)
4171 {
4172 u16 rgvswctl;
4173
4174 assert_spin_locked(&mchdev_lock);
4175
4176 rgvswctl = I915_READ16(MEMSWCTL);
4177 if (rgvswctl & MEMCTL_CMD_STS) {
4178 DRM_DEBUG("gpu busy, RCS change rejected\n");
4179 return false; /* still busy with another command */
4180 }
4181
4182 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4183 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4184 I915_WRITE16(MEMSWCTL, rgvswctl);
4185 POSTING_READ16(MEMSWCTL);
4186
4187 rgvswctl |= MEMCTL_CMD_STS;
4188 I915_WRITE16(MEMSWCTL, rgvswctl);
4189
4190 return true;
4191 }
4192
4193 static void ironlake_enable_drps(struct drm_i915_private *dev_priv)
4194 {
4195 u32 rgvmodectl;
4196 u8 fmax, fmin, fstart, vstart;
4197
4198 spin_lock_irq(&mchdev_lock);
4199
4200 rgvmodectl = I915_READ(MEMMODECTL);
4201
4202 /* Enable temp reporting */
4203 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4204 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4205
4206 /* 100ms RC evaluation intervals */
4207 I915_WRITE(RCUPEI, 100000);
4208 I915_WRITE(RCDNEI, 100000);
4209
4210 /* Set max/min thresholds to 90ms and 80ms respectively */
4211 I915_WRITE(RCBMAXAVG, 90000);
4212 I915_WRITE(RCBMINAVG, 80000);
4213
4214 I915_WRITE(MEMIHYST, 1);
4215
4216 /* Set up min, max, and cur for interrupt handling */
4217 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4218 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4219 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4220 MEMMODE_FSTART_SHIFT;
4221
4222 vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
4223 PXVFREQ_PX_SHIFT;
4224
4225 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4226 dev_priv->ips.fstart = fstart;
4227
4228 dev_priv->ips.max_delay = fstart;
4229 dev_priv->ips.min_delay = fmin;
4230 dev_priv->ips.cur_delay = fstart;
4231
4232 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4233 fmax, fmin, fstart);
4234
4235 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4236
4237 /*
4238 * Interrupts will be enabled in ironlake_irq_postinstall
4239 */
4240
4241 I915_WRITE(VIDSTART, vstart);
4242 POSTING_READ(VIDSTART);
4243
4244 rgvmodectl |= MEMMODE_SWMODE_EN;
4245 I915_WRITE(MEMMODECTL, rgvmodectl);
4246
4247 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
4248 DRM_ERROR("stuck trying to change perf mode\n");
4249 mdelay(1);
4250
4251 ironlake_set_drps(dev_priv, fstart);
4252
4253 dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4254 I915_READ(DDREC) + I915_READ(CSIEC);
4255 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
4256 dev_priv->ips.last_count2 = I915_READ(GFXEC);
4257 dev_priv->ips.last_time2 = ktime_get_raw_ns();
4258
4259 spin_unlock_irq(&mchdev_lock);
4260 }
4261
4262 static void ironlake_disable_drps(struct drm_i915_private *dev_priv)
4263 {
4264 u16 rgvswctl;
4265
4266 spin_lock_irq(&mchdev_lock);
4267
4268 rgvswctl = I915_READ16(MEMSWCTL);
4269
4270 /* Ack interrupts, disable EFC interrupt */
4271 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4272 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4273 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4274 I915_WRITE(DEIIR, DE_PCU_EVENT);
4275 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4276
4277 /* Go back to the starting frequency */
4278 ironlake_set_drps(dev_priv, dev_priv->ips.fstart);
4279 mdelay(1);
4280 rgvswctl |= MEMCTL_CMD_STS;
4281 I915_WRITE(MEMSWCTL, rgvswctl);
4282 mdelay(1);
4283
4284 spin_unlock_irq(&mchdev_lock);
4285 }
4286
4287 /* There's a funny hw issue where the hw returns all 0 when reading from
4288 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4289 * ourselves, instead of doing a rmw cycle (which might result in us clearing
4290 * all limits and the gpu stuck at whatever frequency it is at atm).
4291 */
4292 static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
4293 {
4294 u32 limits;
4295
4296 /* Only set the down limit when we've reached the lowest level to avoid
4297 * getting more interrupts, otherwise leave this clear. This prevents a
4298 * race in the hw when coming out of rc6: There's a tiny window where
4299 * the hw runs at the minimal clock before selecting the desired
4300 * frequency, if the down threshold expires in that window we will not
4301 * receive a down interrupt. */
4302 if (IS_GEN9(dev_priv)) {
4303 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4304 if (val <= dev_priv->rps.min_freq_softlimit)
4305 limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4306 } else {
4307 limits = dev_priv->rps.max_freq_softlimit << 24;
4308 if (val <= dev_priv->rps.min_freq_softlimit)
4309 limits |= dev_priv->rps.min_freq_softlimit << 16;
4310 }
4311
4312 return limits;
4313 }
4314
4315 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4316 {
4317 int new_power;
4318 u32 threshold_up = 0, threshold_down = 0; /* in % */
4319 u32 ei_up = 0, ei_down = 0;
4320
4321 new_power = dev_priv->rps.power;
4322 switch (dev_priv->rps.power) {
4323 case LOW_POWER:
4324 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
4325 new_power = BETWEEN;
4326 break;
4327
4328 case BETWEEN:
4329 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
4330 new_power = LOW_POWER;
4331 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
4332 new_power = HIGH_POWER;
4333 break;
4334
4335 case HIGH_POWER:
4336 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
4337 new_power = BETWEEN;
4338 break;
4339 }
4340 /* Max/min bins are special */
4341 if (val <= dev_priv->rps.min_freq_softlimit)
4342 new_power = LOW_POWER;
4343 if (val >= dev_priv->rps.max_freq_softlimit)
4344 new_power = HIGH_POWER;
4345 if (new_power == dev_priv->rps.power)
4346 return;
4347
4348 /* Note the units here are not exactly 1us, but 1280ns. */
4349 switch (new_power) {
4350 case LOW_POWER:
4351 /* Upclock if more than 95% busy over 16ms */
4352 ei_up = 16000;
4353 threshold_up = 95;
4354
4355 /* Downclock if less than 85% busy over 32ms */
4356 ei_down = 32000;
4357 threshold_down = 85;
4358 break;
4359
4360 case BETWEEN:
4361 /* Upclock if more than 90% busy over 13ms */
4362 ei_up = 13000;
4363 threshold_up = 90;
4364
4365 /* Downclock if less than 75% busy over 32ms */
4366 ei_down = 32000;
4367 threshold_down = 75;
4368 break;
4369
4370 case HIGH_POWER:
4371 /* Upclock if more than 85% busy over 10ms */
4372 ei_up = 10000;
4373 threshold_up = 85;
4374
4375 /* Downclock if less than 60% busy over 32ms */
4376 ei_down = 32000;
4377 threshold_down = 60;
4378 break;
4379 }
4380
4381 I915_WRITE(GEN6_RP_UP_EI,
4382 GT_INTERVAL_FROM_US(dev_priv, ei_up));
4383 I915_WRITE(GEN6_RP_UP_THRESHOLD,
4384 GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100)));
4385
4386 I915_WRITE(GEN6_RP_DOWN_EI,
4387 GT_INTERVAL_FROM_US(dev_priv, ei_down));
4388 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4389 GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100)));
4390
4391 I915_WRITE(GEN6_RP_CONTROL,
4392 GEN6_RP_MEDIA_TURBO |
4393 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4394 GEN6_RP_MEDIA_IS_GFX |
4395 GEN6_RP_ENABLE |
4396 GEN6_RP_UP_BUSY_AVG |
4397 GEN6_RP_DOWN_IDLE_AVG);
4398
4399 dev_priv->rps.power = new_power;
4400 dev_priv->rps.up_threshold = threshold_up;
4401 dev_priv->rps.down_threshold = threshold_down;
4402 dev_priv->rps.last_adj = 0;
4403 }
4404
4405 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4406 {
4407 u32 mask = 0;
4408
4409 if (val > dev_priv->rps.min_freq_softlimit)
4410 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
4411 if (val < dev_priv->rps.max_freq_softlimit)
4412 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
4413
4414 mask &= dev_priv->pm_rps_events;
4415
4416 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
4417 }
4418
4419 /* gen6_set_rps is called to update the frequency request, but should also be
4420 * called when the range (min_delay and max_delay) is modified so that we can
4421 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
4422 static void gen6_set_rps(struct drm_i915_private *dev_priv, u8 val)
4423 {
4424 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4425 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
4426 return;
4427
4428 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4429 WARN_ON(val > dev_priv->rps.max_freq);
4430 WARN_ON(val < dev_priv->rps.min_freq);
4431
4432 /* min/max delay may still have been modified so be sure to
4433 * write the limits value.
4434 */
4435 if (val != dev_priv->rps.cur_freq) {
4436 gen6_set_rps_thresholds(dev_priv, val);
4437
4438 if (IS_GEN9(dev_priv))
4439 I915_WRITE(GEN6_RPNSWREQ,
4440 GEN9_FREQUENCY(val));
4441 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
4442 I915_WRITE(GEN6_RPNSWREQ,
4443 HSW_FREQUENCY(val));
4444 else
4445 I915_WRITE(GEN6_RPNSWREQ,
4446 GEN6_FREQUENCY(val) |
4447 GEN6_OFFSET(0) |
4448 GEN6_AGGRESSIVE_TURBO);
4449 }
4450
4451 /* Make sure we continue to get interrupts
4452 * until we hit the minimum or maximum frequencies.
4453 */
4454 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
4455 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4456
4457 POSTING_READ(GEN6_RPNSWREQ);
4458
4459 dev_priv->rps.cur_freq = val;
4460 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4461 }
4462
4463 static void valleyview_set_rps(struct drm_i915_private *dev_priv, u8 val)
4464 {
4465 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4466 WARN_ON(val > dev_priv->rps.max_freq);
4467 WARN_ON(val < dev_priv->rps.min_freq);
4468
4469 if (WARN_ONCE(IS_CHERRYVIEW(dev_priv) && (val & 1),
4470 "Odd GPU freq value\n"))
4471 val &= ~1;
4472
4473 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4474
4475 if (val != dev_priv->rps.cur_freq) {
4476 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
4477 if (!IS_CHERRYVIEW(dev_priv))
4478 gen6_set_rps_thresholds(dev_priv, val);
4479 }
4480
4481 dev_priv->rps.cur_freq = val;
4482 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4483 }
4484
4485 /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
4486 *
4487 * * If Gfx is Idle, then
4488 * 1. Forcewake Media well.
4489 * 2. Request idle freq.
4490 * 3. Release Forcewake of Media well.
4491 */
4492 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4493 {
4494 u32 val = dev_priv->rps.idle_freq;
4495
4496 if (dev_priv->rps.cur_freq <= val)
4497 return;
4498
4499 /* Wake up the media well, as that takes a lot less
4500 * power than the Render well. */
4501 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
4502 valleyview_set_rps(dev_priv, val);
4503 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
4504 }
4505
4506 void gen6_rps_busy(struct drm_i915_private *dev_priv)
4507 {
4508 mutex_lock(&dev_priv->rps.hw_lock);
4509 if (dev_priv->rps.enabled) {
4510 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
4511 gen6_rps_reset_ei(dev_priv);
4512 I915_WRITE(GEN6_PMINTRMSK,
4513 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
4514 }
4515 mutex_unlock(&dev_priv->rps.hw_lock);
4516 }
4517
4518 void gen6_rps_idle(struct drm_i915_private *dev_priv)
4519 {
4520 mutex_lock(&dev_priv->rps.hw_lock);
4521 if (dev_priv->rps.enabled) {
4522 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4523 vlv_set_rps_idle(dev_priv);
4524 else
4525 gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
4526 dev_priv->rps.last_adj = 0;
4527 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
4528 }
4529 mutex_unlock(&dev_priv->rps.hw_lock);
4530
4531 spin_lock(&dev_priv->rps.client_lock);
4532 while (!list_empty(&dev_priv->rps.clients))
4533 list_del_init(dev_priv->rps.clients.next);
4534 spin_unlock(&dev_priv->rps.client_lock);
4535 }
4536
4537 void gen6_rps_boost(struct drm_i915_private *dev_priv,
4538 struct intel_rps_client *rps,
4539 unsigned long submitted)
4540 {
4541 /* This is intentionally racy! We peek at the state here, then
4542 * validate inside the RPS worker.
4543 */
4544 if (!(dev_priv->mm.busy &&
4545 dev_priv->rps.enabled &&
4546 dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit))
4547 return;
4548
4549 /* Force a RPS boost (and don't count it against the client) if
4550 * the GPU is severely congested.
4551 */
4552 if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
4553 rps = NULL;
4554
4555 spin_lock(&dev_priv->rps.client_lock);
4556 if (rps == NULL || list_empty(&rps->link)) {
4557 spin_lock_irq(&dev_priv->irq_lock);
4558 if (dev_priv->rps.interrupts_enabled) {
4559 dev_priv->rps.client_boost = true;
4560 queue_work(dev_priv->wq, &dev_priv->rps.work);
4561 }
4562 spin_unlock_irq(&dev_priv->irq_lock);
4563
4564 if (rps != NULL) {
4565 list_add(&rps->link, &dev_priv->rps.clients);
4566 rps->boosts++;
4567 } else
4568 dev_priv->rps.boosts++;
4569 }
4570 spin_unlock(&dev_priv->rps.client_lock);
4571 }
4572
4573 void intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
4574 {
4575 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4576 valleyview_set_rps(dev_priv, val);
4577 else
4578 gen6_set_rps(dev_priv, val);
4579 }
4580
4581 static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
4582 {
4583 I915_WRITE(GEN6_RC_CONTROL, 0);
4584 I915_WRITE(GEN9_PG_ENABLE, 0);
4585 }
4586
4587 static void gen9_disable_rps(struct drm_i915_private *dev_priv)
4588 {
4589 I915_WRITE(GEN6_RP_CONTROL, 0);
4590 }
4591
4592 static void gen6_disable_rps(struct drm_i915_private *dev_priv)
4593 {
4594 I915_WRITE(GEN6_RC_CONTROL, 0);
4595 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
4596 I915_WRITE(GEN6_RP_CONTROL, 0);
4597 }
4598
4599 static void cherryview_disable_rps(struct drm_i915_private *dev_priv)
4600 {
4601 I915_WRITE(GEN6_RC_CONTROL, 0);
4602 }
4603
4604 static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
4605 {
4606 /* we're doing forcewake before Disabling RC6,
4607 * This what the BIOS expects when going into suspend */
4608 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4609
4610 I915_WRITE(GEN6_RC_CONTROL, 0);
4611
4612 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4613 }
4614
4615 static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode)
4616 {
4617 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
4618 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
4619 mode = GEN6_RC_CTL_RC6_ENABLE;
4620 else
4621 mode = 0;
4622 }
4623 if (HAS_RC6p(dev_priv))
4624 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
4625 onoff(mode & GEN6_RC_CTL_RC6_ENABLE),
4626 onoff(mode & GEN6_RC_CTL_RC6p_ENABLE),
4627 onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE));
4628
4629 else
4630 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
4631 onoff(mode & GEN6_RC_CTL_RC6_ENABLE));
4632 }
4633
4634 static bool bxt_check_bios_rc6_setup(struct drm_i915_private *dev_priv)
4635 {
4636 struct i915_ggtt *ggtt = &dev_priv->ggtt;
4637 bool enable_rc6 = true;
4638 unsigned long rc6_ctx_base;
4639
4640 if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
4641 DRM_DEBUG_KMS("RC6 Base location not set properly.\n");
4642 enable_rc6 = false;
4643 }
4644
4645 /*
4646 * The exact context size is not known for BXT, so assume a page size
4647 * for this check.
4648 */
4649 rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
4650 if (!((rc6_ctx_base >= ggtt->stolen_reserved_base) &&
4651 (rc6_ctx_base + PAGE_SIZE <= ggtt->stolen_reserved_base +
4652 ggtt->stolen_reserved_size))) {
4653 DRM_DEBUG_KMS("RC6 Base address not as expected.\n");
4654 enable_rc6 = false;
4655 }
4656
4657 if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) &&
4658 ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) &&
4659 ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) &&
4660 ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) {
4661 DRM_DEBUG_KMS("Engine Idle wait time not set properly.\n");
4662 enable_rc6 = false;
4663 }
4664
4665 if (!(I915_READ(GEN6_RC_CONTROL) & (GEN6_RC_CTL_RC6_ENABLE |
4666 GEN6_RC_CTL_HW_ENABLE)) &&
4667 ((I915_READ(GEN6_RC_CONTROL) & GEN6_RC_CTL_HW_ENABLE) ||
4668 !(I915_READ(GEN6_RC_STATE) & RC6_STATE))) {
4669 DRM_DEBUG_KMS("HW/SW RC6 is not enabled by BIOS.\n");
4670 enable_rc6 = false;
4671 }
4672
4673 return enable_rc6;
4674 }
4675
4676 int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6)
4677 {
4678 /* No RC6 before Ironlake and code is gone for ilk. */
4679 if (INTEL_INFO(dev_priv)->gen < 6)
4680 return 0;
4681
4682 if (!enable_rc6)
4683 return 0;
4684
4685 if (IS_BROXTON(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) {
4686 DRM_INFO("RC6 disabled by BIOS\n");
4687 return 0;
4688 }
4689
4690 /* Respect the kernel parameter if it is set */
4691 if (enable_rc6 >= 0) {
4692 int mask;
4693
4694 if (HAS_RC6p(dev_priv))
4695 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
4696 INTEL_RC6pp_ENABLE;
4697 else
4698 mask = INTEL_RC6_ENABLE;
4699
4700 if ((enable_rc6 & mask) != enable_rc6)
4701 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
4702 enable_rc6 & mask, enable_rc6, mask);
4703
4704 return enable_rc6 & mask;
4705 }
4706
4707 if (IS_IVYBRIDGE(dev_priv))
4708 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
4709
4710 return INTEL_RC6_ENABLE;
4711 }
4712
4713 static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
4714 {
4715 uint32_t rp_state_cap;
4716 u32 ddcc_status = 0;
4717 int ret;
4718
4719 /* All of these values are in units of 50MHz */
4720 dev_priv->rps.cur_freq = 0;
4721 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
4722 if (IS_BROXTON(dev_priv)) {
4723 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
4724 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
4725 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
4726 dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff;
4727 } else {
4728 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
4729 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
4730 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
4731 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
4732 }
4733
4734 /* hw_max = RP0 until we check for overclocking */
4735 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
4736
4737 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
4738 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
4739 IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
4740 ret = sandybridge_pcode_read(dev_priv,
4741 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
4742 &ddcc_status);
4743 if (0 == ret)
4744 dev_priv->rps.efficient_freq =
4745 clamp_t(u8,
4746 ((ddcc_status >> 8) & 0xff),
4747 dev_priv->rps.min_freq,
4748 dev_priv->rps.max_freq);
4749 }
4750
4751 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
4752 /* Store the frequency values in 16.66 MHZ units, which is
4753 the natural hardware unit for SKL */
4754 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
4755 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
4756 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
4757 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
4758 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
4759 }
4760
4761 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
4762
4763 /* Preserve min/max settings in case of re-init */
4764 if (dev_priv->rps.max_freq_softlimit == 0)
4765 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4766
4767 if (dev_priv->rps.min_freq_softlimit == 0) {
4768 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
4769 dev_priv->rps.min_freq_softlimit =
4770 max_t(int, dev_priv->rps.efficient_freq,
4771 intel_freq_opcode(dev_priv, 450));
4772 else
4773 dev_priv->rps.min_freq_softlimit =
4774 dev_priv->rps.min_freq;
4775 }
4776 }
4777
4778 /* See the Gen9_GT_PM_Programming_Guide doc for the below */
4779 static void gen9_enable_rps(struct drm_i915_private *dev_priv)
4780 {
4781 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4782
4783 gen6_init_rps_frequencies(dev_priv);
4784
4785 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4786 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
4787 /*
4788 * BIOS could leave the Hw Turbo enabled, so need to explicitly
4789 * clear out the Control register just to avoid inconsitency
4790 * with debugfs interface, which will show Turbo as enabled
4791 * only and that is not expected by the User after adding the
4792 * WaGsvDisableTurbo. Apart from this there is no problem even
4793 * if the Turbo is left enabled in the Control register, as the
4794 * Up/Down interrupts would remain masked.
4795 */
4796 gen9_disable_rps(dev_priv);
4797 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4798 return;
4799 }
4800
4801 /* Program defaults and thresholds for RPS*/
4802 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4803 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
4804
4805 /* 1 second timeout*/
4806 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
4807 GT_INTERVAL_FROM_US(dev_priv, 1000000));
4808
4809 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
4810
4811 /* Leaning on the below call to gen6_set_rps to program/setup the
4812 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
4813 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
4814 dev_priv->rps.power = HIGH_POWER; /* force a reset */
4815 gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
4816
4817 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4818 }
4819
4820 static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
4821 {
4822 struct intel_engine_cs *engine;
4823 uint32_t rc6_mask = 0;
4824
4825 /* 1a: Software RC state - RC0 */
4826 I915_WRITE(GEN6_RC_STATE, 0);
4827
4828 /* 1b: Get forcewake during program sequence. Although the driver
4829 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4830 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4831
4832 /* 2a: Disable RC states. */
4833 I915_WRITE(GEN6_RC_CONTROL, 0);
4834
4835 /* 2b: Program RC6 thresholds.*/
4836
4837 /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
4838 if (IS_SKYLAKE(dev_priv))
4839 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
4840 else
4841 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
4842 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4843 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4844 for_each_engine(engine, dev_priv)
4845 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
4846
4847 if (HAS_GUC_UCODE(dev_priv))
4848 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
4849
4850 I915_WRITE(GEN6_RC_SLEEP, 0);
4851
4852 /* 2c: Program Coarse Power Gating Policies. */
4853 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
4854 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
4855
4856 /* 3a: Enable RC6 */
4857 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
4858 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4859 DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
4860 /* WaRsUseTimeoutMode */
4861 if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_D0) ||
4862 IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
4863 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
4864 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4865 GEN7_RC_CTL_TO_MODE |
4866 rc6_mask);
4867 } else {
4868 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
4869 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4870 GEN6_RC_CTL_EI_MODE(1) |
4871 rc6_mask);
4872 }
4873
4874 /*
4875 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
4876 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
4877 */
4878 if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
4879 I915_WRITE(GEN9_PG_ENABLE, 0);
4880 else
4881 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4882 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
4883
4884 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4885 }
4886
4887 static void gen8_enable_rps(struct drm_i915_private *dev_priv)
4888 {
4889 struct intel_engine_cs *engine;
4890 uint32_t rc6_mask = 0;
4891
4892 /* 1a: Software RC state - RC0 */
4893 I915_WRITE(GEN6_RC_STATE, 0);
4894
4895 /* 1c & 1d: Get forcewake during program sequence. Although the driver
4896 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4897 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4898
4899 /* 2a: Disable RC states. */
4900 I915_WRITE(GEN6_RC_CONTROL, 0);
4901
4902 /* Initialize rps frequencies */
4903 gen6_init_rps_frequencies(dev_priv);
4904
4905 /* 2b: Program RC6 thresholds.*/
4906 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4907 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4908 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4909 for_each_engine(engine, dev_priv)
4910 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
4911 I915_WRITE(GEN6_RC_SLEEP, 0);
4912 if (IS_BROADWELL(dev_priv))
4913 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
4914 else
4915 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
4916
4917 /* 3: Enable RC6 */
4918 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
4919 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4920 intel_print_rc6_info(dev_priv, rc6_mask);
4921 if (IS_BROADWELL(dev_priv))
4922 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4923 GEN7_RC_CTL_TO_MODE |
4924 rc6_mask);
4925 else
4926 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4927 GEN6_RC_CTL_EI_MODE(1) |
4928 rc6_mask);
4929
4930 /* 4 Program defaults and thresholds for RPS*/
4931 I915_WRITE(GEN6_RPNSWREQ,
4932 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4933 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4934 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4935 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
4936 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
4937
4938 /* Docs recommend 900MHz, and 300 MHz respectively */
4939 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
4940 dev_priv->rps.max_freq_softlimit << 24 |
4941 dev_priv->rps.min_freq_softlimit << 16);
4942
4943 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
4944 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
4945 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
4946 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
4947
4948 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4949
4950 /* 5: Enable RPS */
4951 I915_WRITE(GEN6_RP_CONTROL,
4952 GEN6_RP_MEDIA_TURBO |
4953 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4954 GEN6_RP_MEDIA_IS_GFX |
4955 GEN6_RP_ENABLE |
4956 GEN6_RP_UP_BUSY_AVG |
4957 GEN6_RP_DOWN_IDLE_AVG);
4958
4959 /* 6: Ring frequency + overclocking (our driver does this later */
4960
4961 dev_priv->rps.power = HIGH_POWER; /* force a reset */
4962 gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
4963
4964 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4965 }
4966
4967 static void gen6_enable_rps(struct drm_i915_private *dev_priv)
4968 {
4969 struct intel_engine_cs *engine;
4970 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
4971 u32 gtfifodbg;
4972 int rc6_mode;
4973 int ret;
4974
4975 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4976
4977 /* Here begins a magic sequence of register writes to enable
4978 * auto-downclocking.
4979 *
4980 * Perhaps there might be some value in exposing these to
4981 * userspace...
4982 */
4983 I915_WRITE(GEN6_RC_STATE, 0);
4984
4985 /* Clear the DBG now so we don't confuse earlier errors */
4986 gtfifodbg = I915_READ(GTFIFODBG);
4987 if (gtfifodbg) {
4988 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
4989 I915_WRITE(GTFIFODBG, gtfifodbg);
4990 }
4991
4992 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4993
4994 /* Initialize rps frequencies */
4995 gen6_init_rps_frequencies(dev_priv);
4996
4997 /* disable the counters and set deterministic thresholds */
4998 I915_WRITE(GEN6_RC_CONTROL, 0);
4999
5000 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
5001 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
5002 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
5003 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5004 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5005
5006 for_each_engine(engine, dev_priv)
5007 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5008
5009 I915_WRITE(GEN6_RC_SLEEP, 0);
5010 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
5011 if (IS_IVYBRIDGE(dev_priv))
5012 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
5013 else
5014 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
5015 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
5016 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
5017
5018 /* Check if we are enabling RC6 */
5019 rc6_mode = intel_enable_rc6();
5020 if (rc6_mode & INTEL_RC6_ENABLE)
5021 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
5022
5023 /* We don't use those on Haswell */
5024 if (!IS_HASWELL(dev_priv)) {
5025 if (rc6_mode & INTEL_RC6p_ENABLE)
5026 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
5027
5028 if (rc6_mode & INTEL_RC6pp_ENABLE)
5029 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
5030 }
5031
5032 intel_print_rc6_info(dev_priv, rc6_mask);
5033
5034 I915_WRITE(GEN6_RC_CONTROL,
5035 rc6_mask |
5036 GEN6_RC_CTL_EI_MODE(1) |
5037 GEN6_RC_CTL_HW_ENABLE);
5038
5039 /* Power down if completely idle for over 50ms */
5040 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
5041 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5042
5043 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
5044 if (ret)
5045 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
5046
5047 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
5048 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
5049 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
5050 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
5051 (pcu_mbox & 0xff) * 50);
5052 dev_priv->rps.max_freq = pcu_mbox & 0xff;
5053 }
5054
5055 dev_priv->rps.power = HIGH_POWER; /* force a reset */
5056 gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
5057
5058 rc6vids = 0;
5059 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
5060 if (IS_GEN6(dev_priv) && ret) {
5061 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
5062 } else if (IS_GEN6(dev_priv) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
5063 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5064 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5065 rc6vids &= 0xffff00;
5066 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5067 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5068 if (ret)
5069 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5070 }
5071
5072 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5073 }
5074
5075 static void __gen6_update_ring_freq(struct drm_i915_private *dev_priv)
5076 {
5077 int min_freq = 15;
5078 unsigned int gpu_freq;
5079 unsigned int max_ia_freq, min_ring_freq;
5080 unsigned int max_gpu_freq, min_gpu_freq;
5081 int scaling_factor = 180;
5082 struct cpufreq_policy *policy;
5083
5084 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5085
5086 policy = cpufreq_cpu_get(0);
5087 if (policy) {
5088 max_ia_freq = policy->cpuinfo.max_freq;
5089 cpufreq_cpu_put(policy);
5090 } else {
5091 /*
5092 * Default to measured freq if none found, PCU will ensure we
5093 * don't go over
5094 */
5095 max_ia_freq = tsc_khz;
5096 }
5097
5098 /* Convert from kHz to MHz */
5099 max_ia_freq /= 1000;
5100
5101 min_ring_freq = I915_READ(DCLK) & 0xf;
5102 /* convert DDR frequency from units of 266.6MHz to bandwidth */
5103 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
5104
5105 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5106 /* Convert GT frequency to 50 HZ units */
5107 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5108 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5109 } else {
5110 min_gpu_freq = dev_priv->rps.min_freq;
5111 max_gpu_freq = dev_priv->rps.max_freq;
5112 }
5113
5114 /*
5115 * For each potential GPU frequency, load a ring frequency we'd like
5116 * to use for memory access. We do this by specifying the IA frequency
5117 * the PCU should use as a reference to determine the ring frequency.
5118 */
5119 for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5120 int diff = max_gpu_freq - gpu_freq;
5121 unsigned int ia_freq = 0, ring_freq = 0;
5122
5123 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5124 /*
5125 * ring_freq = 2 * GT. ring_freq is in 100MHz units
5126 * No floor required for ring frequency on SKL.
5127 */
5128 ring_freq = gpu_freq;
5129 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
5130 /* max(2 * GT, DDR). NB: GT is 50MHz units */
5131 ring_freq = max(min_ring_freq, gpu_freq);
5132 } else if (IS_HASWELL(dev_priv)) {
5133 ring_freq = mult_frac(gpu_freq, 5, 4);
5134 ring_freq = max(min_ring_freq, ring_freq);
5135 /* leave ia_freq as the default, chosen by cpufreq */
5136 } else {
5137 /* On older processors, there is no separate ring
5138 * clock domain, so in order to boost the bandwidth
5139 * of the ring, we need to upclock the CPU (ia_freq).
5140 *
5141 * For GPU frequencies less than 750MHz,
5142 * just use the lowest ring freq.
5143 */
5144 if (gpu_freq < min_freq)
5145 ia_freq = 800;
5146 else
5147 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5148 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5149 }
5150
5151 sandybridge_pcode_write(dev_priv,
5152 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
5153 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5154 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5155 gpu_freq);
5156 }
5157 }
5158
5159 void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
5160 {
5161 if (!HAS_CORE_RING_FREQ(dev_priv))
5162 return;
5163
5164 mutex_lock(&dev_priv->rps.hw_lock);
5165 __gen6_update_ring_freq(dev_priv);
5166 mutex_unlock(&dev_priv->rps.hw_lock);
5167 }
5168
5169 static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
5170 {
5171 u32 val, rp0;
5172
5173 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5174
5175 switch (INTEL_INFO(dev_priv)->eu_total) {
5176 case 8:
5177 /* (2 * 4) config */
5178 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5179 break;
5180 case 12:
5181 /* (2 * 6) config */
5182 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5183 break;
5184 case 16:
5185 /* (2 * 8) config */
5186 default:
5187 /* Setting (2 * 8) Min RP0 for any other combination */
5188 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5189 break;
5190 }
5191
5192 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5193
5194 return rp0;
5195 }
5196
5197 static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5198 {
5199 u32 val, rpe;
5200
5201 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5202 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5203
5204 return rpe;
5205 }
5206
5207 static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5208 {
5209 u32 val, rp1;
5210
5211 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5212 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5213
5214 return rp1;
5215 }
5216
5217 static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5218 {
5219 u32 val, rp1;
5220
5221 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5222
5223 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5224
5225 return rp1;
5226 }
5227
5228 static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
5229 {
5230 u32 val, rp0;
5231
5232 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5233
5234 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5235 /* Clamp to max */
5236 rp0 = min_t(u32, rp0, 0xea);
5237
5238 return rp0;
5239 }
5240
5241 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5242 {
5243 u32 val, rpe;
5244
5245 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
5246 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
5247 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
5248 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5249
5250 return rpe;
5251 }
5252
5253 static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
5254 {
5255 u32 val;
5256
5257 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5258 /*
5259 * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
5260 * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
5261 * a BYT-M B0 the above register contains 0xbf. Moreover when setting
5262 * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
5263 * to make sure it matches what Punit accepts.
5264 */
5265 return max_t(u32, val, 0xc0);
5266 }
5267
5268 /* Check that the pctx buffer wasn't move under us. */
5269 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5270 {
5271 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5272
5273 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5274 dev_priv->vlv_pctx->stolen->start);
5275 }
5276
5277
5278 /* Check that the pcbr address is not empty. */
5279 static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5280 {
5281 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5282
5283 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5284 }
5285
5286 static void cherryview_setup_pctx(struct drm_i915_private *dev_priv)
5287 {
5288 struct i915_ggtt *ggtt = &dev_priv->ggtt;
5289 unsigned long pctx_paddr, paddr;
5290 u32 pcbr;
5291 int pctx_size = 32*1024;
5292
5293 pcbr = I915_READ(VLV_PCBR);
5294 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
5295 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5296 paddr = (dev_priv->mm.stolen_base +
5297 (ggtt->stolen_size - pctx_size));
5298
5299 pctx_paddr = (paddr & (~4095));
5300 I915_WRITE(VLV_PCBR, pctx_paddr);
5301 }
5302
5303 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5304 }
5305
5306 static void valleyview_setup_pctx(struct drm_i915_private *dev_priv)
5307 {
5308 struct drm_i915_gem_object *pctx;
5309 unsigned long pctx_paddr;
5310 u32 pcbr;
5311 int pctx_size = 24*1024;
5312
5313 mutex_lock(&dev_priv->dev->struct_mutex);
5314
5315 pcbr = I915_READ(VLV_PCBR);
5316 if (pcbr) {
5317 /* BIOS set it up already, grab the pre-alloc'd space */
5318 int pcbr_offset;
5319
5320 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
5321 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
5322 pcbr_offset,
5323 I915_GTT_OFFSET_NONE,
5324 pctx_size);
5325 goto out;
5326 }
5327
5328 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5329
5330 /*
5331 * From the Gunit register HAS:
5332 * The Gfx driver is expected to program this register and ensure
5333 * proper allocation within Gfx stolen memory. For example, this
5334 * register should be programmed such than the PCBR range does not
5335 * overlap with other ranges, such as the frame buffer, protected
5336 * memory, or any other relevant ranges.
5337 */
5338 pctx = i915_gem_object_create_stolen(dev_priv->dev, pctx_size);
5339 if (!pctx) {
5340 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
5341 goto out;
5342 }
5343
5344 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5345 I915_WRITE(VLV_PCBR, pctx_paddr);
5346
5347 out:
5348 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5349 dev_priv->vlv_pctx = pctx;
5350 mutex_unlock(&dev_priv->dev->struct_mutex);
5351 }
5352
5353 static void valleyview_cleanup_pctx(struct drm_i915_private *dev_priv)
5354 {
5355 if (WARN_ON(!dev_priv->vlv_pctx))
5356 return;
5357
5358 drm_gem_object_unreference_unlocked(&dev_priv->vlv_pctx->base);
5359 dev_priv->vlv_pctx = NULL;
5360 }
5361
5362 static void vlv_init_gpll_ref_freq(struct drm_i915_private *dev_priv)
5363 {
5364 dev_priv->rps.gpll_ref_freq =
5365 vlv_get_cck_clock(dev_priv, "GPLL ref",
5366 CCK_GPLL_CLOCK_CONTROL,
5367 dev_priv->czclk_freq);
5368
5369 DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n",
5370 dev_priv->rps.gpll_ref_freq);
5371 }
5372
5373 static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv)
5374 {
5375 u32 val;
5376
5377 valleyview_setup_pctx(dev_priv);
5378
5379 vlv_init_gpll_ref_freq(dev_priv);
5380
5381 mutex_lock(&dev_priv->rps.hw_lock);
5382
5383 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5384 switch ((val >> 6) & 3) {
5385 case 0:
5386 case 1:
5387 dev_priv->mem_freq = 800;
5388 break;
5389 case 2:
5390 dev_priv->mem_freq = 1066;
5391 break;
5392 case 3:
5393 dev_priv->mem_freq = 1333;
5394 break;
5395 }
5396 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5397
5398 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5399 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5400 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5401 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5402 dev_priv->rps.max_freq);
5403
5404 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5405 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5406 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5407 dev_priv->rps.efficient_freq);
5408
5409 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5410 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
5411 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5412 dev_priv->rps.rp1_freq);
5413
5414 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5415 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5416 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5417 dev_priv->rps.min_freq);
5418
5419 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5420
5421 /* Preserve min/max settings in case of re-init */
5422 if (dev_priv->rps.max_freq_softlimit == 0)
5423 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5424
5425 if (dev_priv->rps.min_freq_softlimit == 0)
5426 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5427
5428 mutex_unlock(&dev_priv->rps.hw_lock);
5429 }
5430
5431 static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv)
5432 {
5433 u32 val;
5434
5435 cherryview_setup_pctx(dev_priv);
5436
5437 vlv_init_gpll_ref_freq(dev_priv);
5438
5439 mutex_lock(&dev_priv->rps.hw_lock);
5440
5441 mutex_lock(&dev_priv->sb_lock);
5442 val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
5443 mutex_unlock(&dev_priv->sb_lock);
5444
5445 switch ((val >> 2) & 0x7) {
5446 case 3:
5447 dev_priv->mem_freq = 2000;
5448 break;
5449 default:
5450 dev_priv->mem_freq = 1600;
5451 break;
5452 }
5453 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5454
5455 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5456 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5457 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5458 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5459 dev_priv->rps.max_freq);
5460
5461 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5462 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5463 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5464 dev_priv->rps.efficient_freq);
5465
5466 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5467 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
5468 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5469 dev_priv->rps.rp1_freq);
5470
5471 /* PUnit validated range is only [RPe, RP0] */
5472 dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
5473 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5474 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5475 dev_priv->rps.min_freq);
5476
5477 WARN_ONCE((dev_priv->rps.max_freq |
5478 dev_priv->rps.efficient_freq |
5479 dev_priv->rps.rp1_freq |
5480 dev_priv->rps.min_freq) & 1,
5481 "Odd GPU freq values\n");
5482
5483 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5484
5485 /* Preserve min/max settings in case of re-init */
5486 if (dev_priv->rps.max_freq_softlimit == 0)
5487 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5488
5489 if (dev_priv->rps.min_freq_softlimit == 0)
5490 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5491
5492 mutex_unlock(&dev_priv->rps.hw_lock);
5493 }
5494
5495 static void valleyview_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
5496 {
5497 valleyview_cleanup_pctx(dev_priv);
5498 }
5499
5500 static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
5501 {
5502 struct intel_engine_cs *engine;
5503 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
5504
5505 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5506
5507 gtfifodbg = I915_READ(GTFIFODBG) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV |
5508 GT_FIFO_FREE_ENTRIES_CHV);
5509 if (gtfifodbg) {
5510 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5511 gtfifodbg);
5512 I915_WRITE(GTFIFODBG, gtfifodbg);
5513 }
5514
5515 cherryview_check_pctx(dev_priv);
5516
5517 /* 1a & 1b: Get forcewake during program sequence. Although the driver
5518 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5519 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5520
5521 /* Disable RC states. */
5522 I915_WRITE(GEN6_RC_CONTROL, 0);
5523
5524 /* 2a: Program RC6 thresholds.*/
5525 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5526 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5527 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5528
5529 for_each_engine(engine, dev_priv)
5530 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5531 I915_WRITE(GEN6_RC_SLEEP, 0);
5532
5533 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
5534 I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
5535
5536 /* allows RC6 residency counter to work */
5537 I915_WRITE(VLV_COUNTER_CONTROL,
5538 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
5539 VLV_MEDIA_RC6_COUNT_EN |
5540 VLV_RENDER_RC6_COUNT_EN));
5541
5542 /* For now we assume BIOS is allocating and populating the PCBR */
5543 pcbr = I915_READ(VLV_PCBR);
5544
5545 /* 3: Enable RC6 */
5546 if ((intel_enable_rc6() & INTEL_RC6_ENABLE) &&
5547 (pcbr >> VLV_PCBR_ADDR_SHIFT))
5548 rc6_mode = GEN7_RC_CTL_TO_MODE;
5549
5550 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5551
5552 /* 4 Program defaults and thresholds for RPS*/
5553 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
5554 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5555 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5556 I915_WRITE(GEN6_RP_UP_EI, 66000);
5557 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5558
5559 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5560
5561 /* 5: Enable RPS */
5562 I915_WRITE(GEN6_RP_CONTROL,
5563 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5564 GEN6_RP_MEDIA_IS_GFX |
5565 GEN6_RP_ENABLE |
5566 GEN6_RP_UP_BUSY_AVG |
5567 GEN6_RP_DOWN_IDLE_AVG);
5568
5569 /* Setting Fixed Bias */
5570 val = VLV_OVERRIDE_EN |
5571 VLV_SOC_TDP_EN |
5572 CHV_BIAS_CPU_50_SOC_50;
5573 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5574
5575 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5576
5577 /* RPS code assumes GPLL is used */
5578 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5579
5580 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
5581 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5582
5583 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5584 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5585 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
5586 dev_priv->rps.cur_freq);
5587
5588 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5589 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq),
5590 dev_priv->rps.idle_freq);
5591
5592 valleyview_set_rps(dev_priv, dev_priv->rps.idle_freq);
5593
5594 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5595 }
5596
5597 static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
5598 {
5599 struct intel_engine_cs *engine;
5600 u32 gtfifodbg, val, rc6_mode = 0;
5601
5602 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5603
5604 valleyview_check_pctx(dev_priv);
5605
5606 gtfifodbg = I915_READ(GTFIFODBG);
5607 if (gtfifodbg) {
5608 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5609 gtfifodbg);
5610 I915_WRITE(GTFIFODBG, gtfifodbg);
5611 }
5612
5613 /* If VLV, Forcewake all wells, else re-direct to regular path */
5614 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5615
5616 /* Disable RC states. */
5617 I915_WRITE(GEN6_RC_CONTROL, 0);
5618
5619 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
5620 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5621 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5622 I915_WRITE(GEN6_RP_UP_EI, 66000);
5623 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5624
5625 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5626
5627 I915_WRITE(GEN6_RP_CONTROL,
5628 GEN6_RP_MEDIA_TURBO |
5629 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5630 GEN6_RP_MEDIA_IS_GFX |
5631 GEN6_RP_ENABLE |
5632 GEN6_RP_UP_BUSY_AVG |
5633 GEN6_RP_DOWN_IDLE_CONT);
5634
5635 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
5636 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5637 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5638
5639 for_each_engine(engine, dev_priv)
5640 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5641
5642 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
5643
5644 /* allows RC6 residency counter to work */
5645 I915_WRITE(VLV_COUNTER_CONTROL,
5646 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
5647 VLV_RENDER_RC0_COUNT_EN |
5648 VLV_MEDIA_RC6_COUNT_EN |
5649 VLV_RENDER_RC6_COUNT_EN));
5650
5651 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
5652 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
5653
5654 intel_print_rc6_info(dev_priv, rc6_mode);
5655
5656 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5657
5658 /* Setting Fixed Bias */
5659 val = VLV_OVERRIDE_EN |
5660 VLV_SOC_TDP_EN |
5661 VLV_BIAS_CPU_125_SOC_875;
5662 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5663
5664 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5665
5666 /* RPS code assumes GPLL is used */
5667 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5668
5669 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
5670 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5671
5672 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5673 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5674 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
5675 dev_priv->rps.cur_freq);
5676
5677 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5678 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq),
5679 dev_priv->rps.idle_freq);
5680
5681 valleyview_set_rps(dev_priv, dev_priv->rps.idle_freq);
5682
5683 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5684 }
5685
5686 static unsigned long intel_pxfreq(u32 vidfreq)
5687 {
5688 unsigned long freq;
5689 int div = (vidfreq & 0x3f0000) >> 16;
5690 int post = (vidfreq & 0x3000) >> 12;
5691 int pre = (vidfreq & 0x7);
5692
5693 if (!pre)
5694 return 0;
5695
5696 freq = ((div * 133333) / ((1<<post) * pre));
5697
5698 return freq;
5699 }
5700
5701 static const struct cparams {
5702 u16 i;
5703 u16 t;
5704 u16 m;
5705 u16 c;
5706 } cparams[] = {
5707 { 1, 1333, 301, 28664 },
5708 { 1, 1066, 294, 24460 },
5709 { 1, 800, 294, 25192 },
5710 { 0, 1333, 276, 27605 },
5711 { 0, 1066, 276, 27605 },
5712 { 0, 800, 231, 23784 },
5713 };
5714
5715 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
5716 {
5717 u64 total_count, diff, ret;
5718 u32 count1, count2, count3, m = 0, c = 0;
5719 unsigned long now = jiffies_to_msecs(jiffies), diff1;
5720 int i;
5721
5722 assert_spin_locked(&mchdev_lock);
5723
5724 diff1 = now - dev_priv->ips.last_time1;
5725
5726 /* Prevent division-by-zero if we are asking too fast.
5727 * Also, we don't get interesting results if we are polling
5728 * faster than once in 10ms, so just return the saved value
5729 * in such cases.
5730 */
5731 if (diff1 <= 10)
5732 return dev_priv->ips.chipset_power;
5733
5734 count1 = I915_READ(DMIEC);
5735 count2 = I915_READ(DDREC);
5736 count3 = I915_READ(CSIEC);
5737
5738 total_count = count1 + count2 + count3;
5739
5740 /* FIXME: handle per-counter overflow */
5741 if (total_count < dev_priv->ips.last_count1) {
5742 diff = ~0UL - dev_priv->ips.last_count1;
5743 diff += total_count;
5744 } else {
5745 diff = total_count - dev_priv->ips.last_count1;
5746 }
5747
5748 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
5749 if (cparams[i].i == dev_priv->ips.c_m &&
5750 cparams[i].t == dev_priv->ips.r_t) {
5751 m = cparams[i].m;
5752 c = cparams[i].c;
5753 break;
5754 }
5755 }
5756
5757 diff = div_u64(diff, diff1);
5758 ret = ((m * diff) + c);
5759 ret = div_u64(ret, 10);
5760
5761 dev_priv->ips.last_count1 = total_count;
5762 dev_priv->ips.last_time1 = now;
5763
5764 dev_priv->ips.chipset_power = ret;
5765
5766 return ret;
5767 }
5768
5769 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
5770 {
5771 unsigned long val;
5772
5773 if (INTEL_INFO(dev_priv)->gen != 5)
5774 return 0;
5775
5776 spin_lock_irq(&mchdev_lock);
5777
5778 val = __i915_chipset_val(dev_priv);
5779
5780 spin_unlock_irq(&mchdev_lock);
5781
5782 return val;
5783 }
5784
5785 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
5786 {
5787 unsigned long m, x, b;
5788 u32 tsfs;
5789
5790 tsfs = I915_READ(TSFS);
5791
5792 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
5793 x = I915_READ8(TR1);
5794
5795 b = tsfs & TSFS_INTR_MASK;
5796
5797 return ((m * x) / 127) - b;
5798 }
5799
5800 static int _pxvid_to_vd(u8 pxvid)
5801 {
5802 if (pxvid == 0)
5803 return 0;
5804
5805 if (pxvid >= 8 && pxvid < 31)
5806 pxvid = 31;
5807
5808 return (pxvid + 2) * 125;
5809 }
5810
5811 static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
5812 {
5813 const int vd = _pxvid_to_vd(pxvid);
5814 const int vm = vd - 1125;
5815
5816 if (INTEL_INFO(dev_priv)->is_mobile)
5817 return vm > 0 ? vm : 0;
5818
5819 return vd;
5820 }
5821
5822 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
5823 {
5824 u64 now, diff, diffms;
5825 u32 count;
5826
5827 assert_spin_locked(&mchdev_lock);
5828
5829 now = ktime_get_raw_ns();
5830 diffms = now - dev_priv->ips.last_time2;
5831 do_div(diffms, NSEC_PER_MSEC);
5832
5833 /* Don't divide by 0 */
5834 if (!diffms)
5835 return;
5836
5837 count = I915_READ(GFXEC);
5838
5839 if (count < dev_priv->ips.last_count2) {
5840 diff = ~0UL - dev_priv->ips.last_count2;
5841 diff += count;
5842 } else {
5843 diff = count - dev_priv->ips.last_count2;
5844 }
5845
5846 dev_priv->ips.last_count2 = count;
5847 dev_priv->ips.last_time2 = now;
5848
5849 /* More magic constants... */
5850 diff = diff * 1181;
5851 diff = div_u64(diff, diffms * 10);
5852 dev_priv->ips.gfx_power = diff;
5853 }
5854
5855 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
5856 {
5857 if (INTEL_INFO(dev_priv)->gen != 5)
5858 return;
5859
5860 spin_lock_irq(&mchdev_lock);
5861
5862 __i915_update_gfx_val(dev_priv);
5863
5864 spin_unlock_irq(&mchdev_lock);
5865 }
5866
5867 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
5868 {
5869 unsigned long t, corr, state1, corr2, state2;
5870 u32 pxvid, ext_v;
5871
5872 assert_spin_locked(&mchdev_lock);
5873
5874 pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
5875 pxvid = (pxvid >> 24) & 0x7f;
5876 ext_v = pvid_to_extvid(dev_priv, pxvid);
5877
5878 state1 = ext_v;
5879
5880 t = i915_mch_val(dev_priv);
5881
5882 /* Revel in the empirically derived constants */
5883
5884 /* Correction factor in 1/100000 units */
5885 if (t > 80)
5886 corr = ((t * 2349) + 135940);
5887 else if (t >= 50)
5888 corr = ((t * 964) + 29317);
5889 else /* < 50 */
5890 corr = ((t * 301) + 1004);
5891
5892 corr = corr * ((150142 * state1) / 10000 - 78642);
5893 corr /= 100000;
5894 corr2 = (corr * dev_priv->ips.corr);
5895
5896 state2 = (corr2 * state1) / 10000;
5897 state2 /= 100; /* convert to mW */
5898
5899 __i915_update_gfx_val(dev_priv);
5900
5901 return dev_priv->ips.gfx_power + state2;
5902 }
5903
5904 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
5905 {
5906 unsigned long val;
5907
5908 if (INTEL_INFO(dev_priv)->gen != 5)
5909 return 0;
5910
5911 spin_lock_irq(&mchdev_lock);
5912
5913 val = __i915_gfx_val(dev_priv);
5914
5915 spin_unlock_irq(&mchdev_lock);
5916
5917 return val;
5918 }
5919
5920 /**
5921 * i915_read_mch_val - return value for IPS use
5922 *
5923 * Calculate and return a value for the IPS driver to use when deciding whether
5924 * we have thermal and power headroom to increase CPU or GPU power budget.
5925 */
5926 unsigned long i915_read_mch_val(void)
5927 {
5928 struct drm_i915_private *dev_priv;
5929 unsigned long chipset_val, graphics_val, ret = 0;
5930
5931 spin_lock_irq(&mchdev_lock);
5932 if (!i915_mch_dev)
5933 goto out_unlock;
5934 dev_priv = i915_mch_dev;
5935
5936 chipset_val = __i915_chipset_val(dev_priv);
5937 graphics_val = __i915_gfx_val(dev_priv);
5938
5939 ret = chipset_val + graphics_val;
5940
5941 out_unlock:
5942 spin_unlock_irq(&mchdev_lock);
5943
5944 return ret;
5945 }
5946 EXPORT_SYMBOL_GPL(i915_read_mch_val);
5947
5948 /**
5949 * i915_gpu_raise - raise GPU frequency limit
5950 *
5951 * Raise the limit; IPS indicates we have thermal headroom.
5952 */
5953 bool i915_gpu_raise(void)
5954 {
5955 struct drm_i915_private *dev_priv;
5956 bool ret = true;
5957
5958 spin_lock_irq(&mchdev_lock);
5959 if (!i915_mch_dev) {
5960 ret = false;
5961 goto out_unlock;
5962 }
5963 dev_priv = i915_mch_dev;
5964
5965 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
5966 dev_priv->ips.max_delay--;
5967
5968 out_unlock:
5969 spin_unlock_irq(&mchdev_lock);
5970
5971 return ret;
5972 }
5973 EXPORT_SYMBOL_GPL(i915_gpu_raise);
5974
5975 /**
5976 * i915_gpu_lower - lower GPU frequency limit
5977 *
5978 * IPS indicates we're close to a thermal limit, so throttle back the GPU
5979 * frequency maximum.
5980 */
5981 bool i915_gpu_lower(void)
5982 {
5983 struct drm_i915_private *dev_priv;
5984 bool ret = true;
5985
5986 spin_lock_irq(&mchdev_lock);
5987 if (!i915_mch_dev) {
5988 ret = false;
5989 goto out_unlock;
5990 }
5991 dev_priv = i915_mch_dev;
5992
5993 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
5994 dev_priv->ips.max_delay++;
5995
5996 out_unlock:
5997 spin_unlock_irq(&mchdev_lock);
5998
5999 return ret;
6000 }
6001 EXPORT_SYMBOL_GPL(i915_gpu_lower);
6002
6003 /**
6004 * i915_gpu_busy - indicate GPU business to IPS
6005 *
6006 * Tell the IPS driver whether or not the GPU is busy.
6007 */
6008 bool i915_gpu_busy(void)
6009 {
6010 struct drm_i915_private *dev_priv;
6011 struct intel_engine_cs *engine;
6012 bool ret = false;
6013
6014 spin_lock_irq(&mchdev_lock);
6015 if (!i915_mch_dev)
6016 goto out_unlock;
6017 dev_priv = i915_mch_dev;
6018
6019 for_each_engine(engine, dev_priv)
6020 ret |= !list_empty(&engine->request_list);
6021
6022 out_unlock:
6023 spin_unlock_irq(&mchdev_lock);
6024
6025 return ret;
6026 }
6027 EXPORT_SYMBOL_GPL(i915_gpu_busy);
6028
6029 /**
6030 * i915_gpu_turbo_disable - disable graphics turbo
6031 *
6032 * Disable graphics turbo by resetting the max frequency and setting the
6033 * current frequency to the default.
6034 */
6035 bool i915_gpu_turbo_disable(void)
6036 {
6037 struct drm_i915_private *dev_priv;
6038 bool ret = true;
6039
6040 spin_lock_irq(&mchdev_lock);
6041 if (!i915_mch_dev) {
6042 ret = false;
6043 goto out_unlock;
6044 }
6045 dev_priv = i915_mch_dev;
6046
6047 dev_priv->ips.max_delay = dev_priv->ips.fstart;
6048
6049 if (!ironlake_set_drps(dev_priv, dev_priv->ips.fstart))
6050 ret = false;
6051
6052 out_unlock:
6053 spin_unlock_irq(&mchdev_lock);
6054
6055 return ret;
6056 }
6057 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6058
6059 /**
6060 * Tells the intel_ips driver that the i915 driver is now loaded, if
6061 * IPS got loaded first.
6062 *
6063 * This awkward dance is so that neither module has to depend on the
6064 * other in order for IPS to do the appropriate communication of
6065 * GPU turbo limits to i915.
6066 */
6067 static void
6068 ips_ping_for_i915_load(void)
6069 {
6070 void (*link)(void);
6071
6072 link = symbol_get(ips_link_to_i915_driver);
6073 if (link) {
6074 link();
6075 symbol_put(ips_link_to_i915_driver);
6076 }
6077 }
6078
6079 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6080 {
6081 /* We only register the i915 ips part with intel-ips once everything is
6082 * set up, to avoid intel-ips sneaking in and reading bogus values. */
6083 spin_lock_irq(&mchdev_lock);
6084 i915_mch_dev = dev_priv;
6085 spin_unlock_irq(&mchdev_lock);
6086
6087 ips_ping_for_i915_load();
6088 }
6089
6090 void intel_gpu_ips_teardown(void)
6091 {
6092 spin_lock_irq(&mchdev_lock);
6093 i915_mch_dev = NULL;
6094 spin_unlock_irq(&mchdev_lock);
6095 }
6096
6097 static void intel_init_emon(struct drm_i915_private *dev_priv)
6098 {
6099 u32 lcfuse;
6100 u8 pxw[16];
6101 int i;
6102
6103 /* Disable to program */
6104 I915_WRITE(ECR, 0);
6105 POSTING_READ(ECR);
6106
6107 /* Program energy weights for various events */
6108 I915_WRITE(SDEW, 0x15040d00);
6109 I915_WRITE(CSIEW0, 0x007f0000);
6110 I915_WRITE(CSIEW1, 0x1e220004);
6111 I915_WRITE(CSIEW2, 0x04000004);
6112
6113 for (i = 0; i < 5; i++)
6114 I915_WRITE(PEW(i), 0);
6115 for (i = 0; i < 3; i++)
6116 I915_WRITE(DEW(i), 0);
6117
6118 /* Program P-state weights to account for frequency power adjustment */
6119 for (i = 0; i < 16; i++) {
6120 u32 pxvidfreq = I915_READ(PXVFREQ(i));
6121 unsigned long freq = intel_pxfreq(pxvidfreq);
6122 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6123 PXVFREQ_PX_SHIFT;
6124 unsigned long val;
6125
6126 val = vid * vid;
6127 val *= (freq / 1000);
6128 val *= 255;
6129 val /= (127*127*900);
6130 if (val > 0xff)
6131 DRM_ERROR("bad pxval: %ld\n", val);
6132 pxw[i] = val;
6133 }
6134 /* Render standby states get 0 weight */
6135 pxw[14] = 0;
6136 pxw[15] = 0;
6137
6138 for (i = 0; i < 4; i++) {
6139 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6140 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
6141 I915_WRITE(PXW(i), val);
6142 }
6143
6144 /* Adjust magic regs to magic values (more experimental results) */
6145 I915_WRITE(OGW0, 0);
6146 I915_WRITE(OGW1, 0);
6147 I915_WRITE(EG0, 0x00007f00);
6148 I915_WRITE(EG1, 0x0000000e);
6149 I915_WRITE(EG2, 0x000e0000);
6150 I915_WRITE(EG3, 0x68000300);
6151 I915_WRITE(EG4, 0x42000000);
6152 I915_WRITE(EG5, 0x00140031);
6153 I915_WRITE(EG6, 0);
6154 I915_WRITE(EG7, 0);
6155
6156 for (i = 0; i < 8; i++)
6157 I915_WRITE(PXWL(i), 0);
6158
6159 /* Enable PMON + select events */
6160 I915_WRITE(ECR, 0x80000019);
6161
6162 lcfuse = I915_READ(LCFUSE02);
6163
6164 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
6165 }
6166
6167 void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
6168 {
6169 /*
6170 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6171 * requirement.
6172 */
6173 if (!i915.enable_rc6) {
6174 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6175 intel_runtime_pm_get(dev_priv);
6176 }
6177
6178 if (IS_CHERRYVIEW(dev_priv))
6179 cherryview_init_gt_powersave(dev_priv);
6180 else if (IS_VALLEYVIEW(dev_priv))
6181 valleyview_init_gt_powersave(dev_priv);
6182 }
6183
6184 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
6185 {
6186 if (IS_CHERRYVIEW(dev_priv))
6187 return;
6188 else if (IS_VALLEYVIEW(dev_priv))
6189 valleyview_cleanup_gt_powersave(dev_priv);
6190
6191 if (!i915.enable_rc6)
6192 intel_runtime_pm_put(dev_priv);
6193 }
6194
6195 static void gen6_suspend_rps(struct drm_i915_private *dev_priv)
6196 {
6197 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
6198
6199 gen6_disable_rps_interrupts(dev_priv);
6200 }
6201
6202 /**
6203 * intel_suspend_gt_powersave - suspend PM work and helper threads
6204 * @dev_priv: i915 device
6205 *
6206 * We don't want to disable RC6 or other features here, we just want
6207 * to make sure any work we've queued has finished and won't bother
6208 * us while we're suspended.
6209 */
6210 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
6211 {
6212 if (INTEL_GEN(dev_priv) < 6)
6213 return;
6214
6215 gen6_suspend_rps(dev_priv);
6216
6217 /* Force GPU to min freq during suspend */
6218 gen6_rps_idle(dev_priv);
6219 }
6220
6221 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
6222 {
6223 if (IS_IRONLAKE_M(dev_priv)) {
6224 ironlake_disable_drps(dev_priv);
6225 } else if (INTEL_INFO(dev_priv)->gen >= 6) {
6226 intel_suspend_gt_powersave(dev_priv);
6227
6228 mutex_lock(&dev_priv->rps.hw_lock);
6229 if (INTEL_INFO(dev_priv)->gen >= 9) {
6230 gen9_disable_rc6(dev_priv);
6231 gen9_disable_rps(dev_priv);
6232 } else if (IS_CHERRYVIEW(dev_priv))
6233 cherryview_disable_rps(dev_priv);
6234 else if (IS_VALLEYVIEW(dev_priv))
6235 valleyview_disable_rps(dev_priv);
6236 else
6237 gen6_disable_rps(dev_priv);
6238
6239 dev_priv->rps.enabled = false;
6240 mutex_unlock(&dev_priv->rps.hw_lock);
6241 }
6242 }
6243
6244 static void intel_gen6_powersave_work(struct work_struct *work)
6245 {
6246 struct drm_i915_private *dev_priv =
6247 container_of(work, struct drm_i915_private,
6248 rps.delayed_resume_work.work);
6249
6250 mutex_lock(&dev_priv->rps.hw_lock);
6251
6252 gen6_reset_rps_interrupts(dev_priv);
6253
6254 if (IS_CHERRYVIEW(dev_priv)) {
6255 cherryview_enable_rps(dev_priv);
6256 } else if (IS_VALLEYVIEW(dev_priv)) {
6257 valleyview_enable_rps(dev_priv);
6258 } else if (INTEL_INFO(dev_priv)->gen >= 9) {
6259 gen9_enable_rc6(dev_priv);
6260 gen9_enable_rps(dev_priv);
6261 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
6262 __gen6_update_ring_freq(dev_priv);
6263 } else if (IS_BROADWELL(dev_priv)) {
6264 gen8_enable_rps(dev_priv);
6265 __gen6_update_ring_freq(dev_priv);
6266 } else {
6267 gen6_enable_rps(dev_priv);
6268 __gen6_update_ring_freq(dev_priv);
6269 }
6270
6271 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6272 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6273
6274 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6275 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6276
6277 dev_priv->rps.enabled = true;
6278
6279 gen6_enable_rps_interrupts(dev_priv);
6280
6281 mutex_unlock(&dev_priv->rps.hw_lock);
6282
6283 intel_runtime_pm_put(dev_priv);
6284 }
6285
6286 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
6287 {
6288 /* Powersaving is controlled by the host when inside a VM */
6289 if (intel_vgpu_active(dev_priv))
6290 return;
6291
6292 if (IS_IRONLAKE_M(dev_priv)) {
6293 ironlake_enable_drps(dev_priv);
6294 mutex_lock(&dev_priv->dev->struct_mutex);
6295 intel_init_emon(dev_priv);
6296 mutex_unlock(&dev_priv->dev->struct_mutex);
6297 } else if (INTEL_INFO(dev_priv)->gen >= 6) {
6298 /*
6299 * PCU communication is slow and this doesn't need to be
6300 * done at any specific time, so do this out of our fast path
6301 * to make resume and init faster.
6302 *
6303 * We depend on the HW RC6 power context save/restore
6304 * mechanism when entering D3 through runtime PM suspend. So
6305 * disable RPM until RPS/RC6 is properly setup. We can only
6306 * get here via the driver load/system resume/runtime resume
6307 * paths, so the _noresume version is enough (and in case of
6308 * runtime resume it's necessary).
6309 */
6310 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
6311 round_jiffies_up_relative(HZ)))
6312 intel_runtime_pm_get_noresume(dev_priv);
6313 }
6314 }
6315
6316 void intel_reset_gt_powersave(struct drm_i915_private *dev_priv)
6317 {
6318 if (INTEL_INFO(dev_priv)->gen < 6)
6319 return;
6320
6321 gen6_suspend_rps(dev_priv);
6322 dev_priv->rps.enabled = false;
6323 }
6324
6325 static void ibx_init_clock_gating(struct drm_device *dev)
6326 {
6327 struct drm_i915_private *dev_priv = dev->dev_private;
6328
6329 /*
6330 * On Ibex Peak and Cougar Point, we need to disable clock
6331 * gating for the panel power sequencer or it will fail to
6332 * start up when no ports are active.
6333 */
6334 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6335 }
6336
6337 static void g4x_disable_trickle_feed(struct drm_device *dev)
6338 {
6339 struct drm_i915_private *dev_priv = dev->dev_private;
6340 enum pipe pipe;
6341
6342 for_each_pipe(dev_priv, pipe) {
6343 I915_WRITE(DSPCNTR(pipe),
6344 I915_READ(DSPCNTR(pipe)) |
6345 DISPPLANE_TRICKLE_FEED_DISABLE);
6346
6347 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6348 POSTING_READ(DSPSURF(pipe));
6349 }
6350 }
6351
6352 static void ilk_init_lp_watermarks(struct drm_device *dev)
6353 {
6354 struct drm_i915_private *dev_priv = dev->dev_private;
6355
6356 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6357 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6358 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6359
6360 /*
6361 * Don't touch WM1S_LP_EN here.
6362 * Doing so could cause underruns.
6363 */
6364 }
6365
6366 static void ironlake_init_clock_gating(struct drm_device *dev)
6367 {
6368 struct drm_i915_private *dev_priv = dev->dev_private;
6369 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6370
6371 /*
6372 * Required for FBC
6373 * WaFbcDisableDpfcClockGating:ilk
6374 */
6375 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6376 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6377 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6378
6379 I915_WRITE(PCH_3DCGDIS0,
6380 MARIUNIT_CLOCK_GATE_DISABLE |
6381 SVSMUNIT_CLOCK_GATE_DISABLE);
6382 I915_WRITE(PCH_3DCGDIS1,
6383 VFMUNIT_CLOCK_GATE_DISABLE);
6384
6385 /*
6386 * According to the spec the following bits should be set in
6387 * order to enable memory self-refresh
6388 * The bit 22/21 of 0x42004
6389 * The bit 5 of 0x42020
6390 * The bit 15 of 0x45000
6391 */
6392 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6393 (I915_READ(ILK_DISPLAY_CHICKEN2) |
6394 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
6395 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6396 I915_WRITE(DISP_ARB_CTL,
6397 (I915_READ(DISP_ARB_CTL) |
6398 DISP_FBC_WM_DIS));
6399
6400 ilk_init_lp_watermarks(dev);
6401
6402 /*
6403 * Based on the document from hardware guys the following bits
6404 * should be set unconditionally in order to enable FBC.
6405 * The bit 22 of 0x42000
6406 * The bit 22 of 0x42004
6407 * The bit 7,8,9 of 0x42020.
6408 */
6409 if (IS_IRONLAKE_M(dev)) {
6410 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6411 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6412 I915_READ(ILK_DISPLAY_CHICKEN1) |
6413 ILK_FBCQ_DIS);
6414 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6415 I915_READ(ILK_DISPLAY_CHICKEN2) |
6416 ILK_DPARB_GATE);
6417 }
6418
6419 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6420
6421 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6422 I915_READ(ILK_DISPLAY_CHICKEN2) |
6423 ILK_ELPIN_409_SELECT);
6424 I915_WRITE(_3D_CHICKEN2,
6425 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6426 _3D_CHICKEN2_WM_READ_PIPELINED);
6427
6428 /* WaDisableRenderCachePipelinedFlush:ilk */
6429 I915_WRITE(CACHE_MODE_0,
6430 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6431
6432 /* WaDisable_RenderCache_OperationalFlush:ilk */
6433 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6434
6435 g4x_disable_trickle_feed(dev);
6436
6437 ibx_init_clock_gating(dev);
6438 }
6439
6440 static void cpt_init_clock_gating(struct drm_device *dev)
6441 {
6442 struct drm_i915_private *dev_priv = dev->dev_private;
6443 int pipe;
6444 uint32_t val;
6445
6446 /*
6447 * On Ibex Peak and Cougar Point, we need to disable clock
6448 * gating for the panel power sequencer or it will fail to
6449 * start up when no ports are active.
6450 */
6451 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6452 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6453 PCH_CPUNIT_CLOCK_GATE_DISABLE);
6454 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6455 DPLS_EDP_PPS_FIX_DIS);
6456 /* The below fixes the weird display corruption, a few pixels shifted
6457 * downward, on (only) LVDS of some HP laptops with IVY.
6458 */
6459 for_each_pipe(dev_priv, pipe) {
6460 val = I915_READ(TRANS_CHICKEN2(pipe));
6461 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6462 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6463 if (dev_priv->vbt.fdi_rx_polarity_inverted)
6464 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6465 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6466 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6467 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
6468 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6469 }
6470 /* WADP0ClockGatingDisable */
6471 for_each_pipe(dev_priv, pipe) {
6472 I915_WRITE(TRANS_CHICKEN1(pipe),
6473 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6474 }
6475 }
6476
6477 static void gen6_check_mch_setup(struct drm_device *dev)
6478 {
6479 struct drm_i915_private *dev_priv = dev->dev_private;
6480 uint32_t tmp;
6481
6482 tmp = I915_READ(MCH_SSKPD);
6483 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6484 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6485 tmp);
6486 }
6487
6488 static void gen6_init_clock_gating(struct drm_device *dev)
6489 {
6490 struct drm_i915_private *dev_priv = dev->dev_private;
6491 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6492
6493 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6494
6495 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6496 I915_READ(ILK_DISPLAY_CHICKEN2) |
6497 ILK_ELPIN_409_SELECT);
6498
6499 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
6500 I915_WRITE(_3D_CHICKEN,
6501 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
6502
6503 /* WaDisable_RenderCache_OperationalFlush:snb */
6504 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6505
6506 /*
6507 * BSpec recoomends 8x4 when MSAA is used,
6508 * however in practice 16x4 seems fastest.
6509 *
6510 * Note that PS/WM thread counts depend on the WIZ hashing
6511 * disable bit, which we don't touch here, but it's good
6512 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6513 */
6514 I915_WRITE(GEN6_GT_MODE,
6515 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6516
6517 ilk_init_lp_watermarks(dev);
6518
6519 I915_WRITE(CACHE_MODE_0,
6520 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6521
6522 I915_WRITE(GEN6_UCGCTL1,
6523 I915_READ(GEN6_UCGCTL1) |
6524 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
6525 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6526
6527 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
6528 * gating disable must be set. Failure to set it results in
6529 * flickering pixels due to Z write ordering failures after
6530 * some amount of runtime in the Mesa "fire" demo, and Unigine
6531 * Sanctuary and Tropics, and apparently anything else with
6532 * alpha test or pixel discard.
6533 *
6534 * According to the spec, bit 11 (RCCUNIT) must also be set,
6535 * but we didn't debug actual testcases to find it out.
6536 *
6537 * WaDisableRCCUnitClockGating:snb
6538 * WaDisableRCPBUnitClockGating:snb
6539 */
6540 I915_WRITE(GEN6_UCGCTL2,
6541 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
6542 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
6543
6544 /* WaStripsFansDisableFastClipPerformanceFix:snb */
6545 I915_WRITE(_3D_CHICKEN3,
6546 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6547
6548 /*
6549 * Bspec says:
6550 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
6551 * 3DSTATE_SF number of SF output attributes is more than 16."
6552 */
6553 I915_WRITE(_3D_CHICKEN3,
6554 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
6555
6556 /*
6557 * According to the spec the following bits should be
6558 * set in order to enable memory self-refresh and fbc:
6559 * The bit21 and bit22 of 0x42000
6560 * The bit21 and bit22 of 0x42004
6561 * The bit5 and bit7 of 0x42020
6562 * The bit14 of 0x70180
6563 * The bit14 of 0x71180
6564 *
6565 * WaFbcAsynchFlipDisableFbcQueue:snb
6566 */
6567 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6568 I915_READ(ILK_DISPLAY_CHICKEN1) |
6569 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6570 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6571 I915_READ(ILK_DISPLAY_CHICKEN2) |
6572 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
6573 I915_WRITE(ILK_DSPCLK_GATE_D,
6574 I915_READ(ILK_DSPCLK_GATE_D) |
6575 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
6576 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6577
6578 g4x_disable_trickle_feed(dev);
6579
6580 cpt_init_clock_gating(dev);
6581
6582 gen6_check_mch_setup(dev);
6583 }
6584
6585 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
6586 {
6587 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
6588
6589 /*
6590 * WaVSThreadDispatchOverride:ivb,vlv
6591 *
6592 * This actually overrides the dispatch
6593 * mode for all thread types.
6594 */
6595 reg &= ~GEN7_FF_SCHED_MASK;
6596 reg |= GEN7_FF_TS_SCHED_HW;
6597 reg |= GEN7_FF_VS_SCHED_HW;
6598 reg |= GEN7_FF_DS_SCHED_HW;
6599
6600 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
6601 }
6602
6603 static void lpt_init_clock_gating(struct drm_device *dev)
6604 {
6605 struct drm_i915_private *dev_priv = dev->dev_private;
6606
6607 /*
6608 * TODO: this bit should only be enabled when really needed, then
6609 * disabled when not needed anymore in order to save power.
6610 */
6611 if (HAS_PCH_LPT_LP(dev))
6612 I915_WRITE(SOUTH_DSPCLK_GATE_D,
6613 I915_READ(SOUTH_DSPCLK_GATE_D) |
6614 PCH_LP_PARTITION_LEVEL_DISABLE);
6615
6616 /* WADPOClockGatingDisable:hsw */
6617 I915_WRITE(TRANS_CHICKEN1(PIPE_A),
6618 I915_READ(TRANS_CHICKEN1(PIPE_A)) |
6619 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6620 }
6621
6622 static void lpt_suspend_hw(struct drm_device *dev)
6623 {
6624 struct drm_i915_private *dev_priv = dev->dev_private;
6625
6626 if (HAS_PCH_LPT_LP(dev)) {
6627 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
6628
6629 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6630 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6631 }
6632 }
6633
6634 static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
6635 int general_prio_credits,
6636 int high_prio_credits)
6637 {
6638 u32 misccpctl;
6639
6640 /* WaTempDisableDOPClkGating:bdw */
6641 misccpctl = I915_READ(GEN7_MISCCPCTL);
6642 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
6643
6644 I915_WRITE(GEN8_L3SQCREG1,
6645 L3_GENERAL_PRIO_CREDITS(general_prio_credits) |
6646 L3_HIGH_PRIO_CREDITS(high_prio_credits));
6647
6648 /*
6649 * Wait at least 100 clocks before re-enabling clock gating.
6650 * See the definition of L3SQCREG1 in BSpec.
6651 */
6652 POSTING_READ(GEN8_L3SQCREG1);
6653 udelay(1);
6654 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
6655 }
6656
6657 static void broadwell_init_clock_gating(struct drm_device *dev)
6658 {
6659 struct drm_i915_private *dev_priv = dev->dev_private;
6660 enum pipe pipe;
6661
6662 ilk_init_lp_watermarks(dev);
6663
6664 /* WaSwitchSolVfFArbitrationPriority:bdw */
6665 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6666
6667 /* WaPsrDPAMaskVBlankInSRD:bdw */
6668 I915_WRITE(CHICKEN_PAR1_1,
6669 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
6670
6671 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
6672 for_each_pipe(dev_priv, pipe) {
6673 I915_WRITE(CHICKEN_PIPESL_1(pipe),
6674 I915_READ(CHICKEN_PIPESL_1(pipe)) |
6675 BDW_DPRS_MASK_VBLANK_SRD);
6676 }
6677
6678 /* WaVSRefCountFullforceMissDisable:bdw */
6679 /* WaDSRefCountFullforceMissDisable:bdw */
6680 I915_WRITE(GEN7_FF_THREAD_MODE,
6681 I915_READ(GEN7_FF_THREAD_MODE) &
6682 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
6683
6684 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6685 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
6686
6687 /* WaDisableSDEUnitClockGating:bdw */
6688 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6689 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6690
6691 /* WaProgramL3SqcReg1Default:bdw */
6692 gen8_set_l3sqc_credits(dev_priv, 30, 2);
6693
6694 /*
6695 * WaGttCachingOffByDefault:bdw
6696 * GTT cache may not work with big pages, so if those
6697 * are ever enabled GTT cache may need to be disabled.
6698 */
6699 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
6700
6701 lpt_init_clock_gating(dev);
6702 }
6703
6704 static void haswell_init_clock_gating(struct drm_device *dev)
6705 {
6706 struct drm_i915_private *dev_priv = dev->dev_private;
6707
6708 ilk_init_lp_watermarks(dev);
6709
6710 /* L3 caching of data atomics doesn't work -- disable it. */
6711 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
6712 I915_WRITE(HSW_ROW_CHICKEN3,
6713 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
6714
6715 /* This is required by WaCatErrorRejectionIssue:hsw */
6716 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6717 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6718 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6719
6720 /* WaVSRefCountFullforceMissDisable:hsw */
6721 I915_WRITE(GEN7_FF_THREAD_MODE,
6722 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
6723
6724 /* WaDisable_RenderCache_OperationalFlush:hsw */
6725 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6726
6727 /* enable HiZ Raw Stall Optimization */
6728 I915_WRITE(CACHE_MODE_0_GEN7,
6729 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6730
6731 /* WaDisable4x2SubspanOptimization:hsw */
6732 I915_WRITE(CACHE_MODE_1,
6733 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6734
6735 /*
6736 * BSpec recommends 8x4 when MSAA is used,
6737 * however in practice 16x4 seems fastest.
6738 *
6739 * Note that PS/WM thread counts depend on the WIZ hashing
6740 * disable bit, which we don't touch here, but it's good
6741 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6742 */
6743 I915_WRITE(GEN7_GT_MODE,
6744 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6745
6746 /* WaSampleCChickenBitEnable:hsw */
6747 I915_WRITE(HALF_SLICE_CHICKEN3,
6748 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
6749
6750 /* WaSwitchSolVfFArbitrationPriority:hsw */
6751 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6752
6753 /* WaRsPkgCStateDisplayPMReq:hsw */
6754 I915_WRITE(CHICKEN_PAR1_1,
6755 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
6756
6757 lpt_init_clock_gating(dev);
6758 }
6759
6760 static void ivybridge_init_clock_gating(struct drm_device *dev)
6761 {
6762 struct drm_i915_private *dev_priv = dev->dev_private;
6763 uint32_t snpcr;
6764
6765 ilk_init_lp_watermarks(dev);
6766
6767 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6768
6769 /* WaDisableEarlyCull:ivb */
6770 I915_WRITE(_3D_CHICKEN3,
6771 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6772
6773 /* WaDisableBackToBackFlipFix:ivb */
6774 I915_WRITE(IVB_CHICKEN3,
6775 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6776 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6777
6778 /* WaDisablePSDDualDispatchEnable:ivb */
6779 if (IS_IVB_GT1(dev))
6780 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6781 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
6782
6783 /* WaDisable_RenderCache_OperationalFlush:ivb */
6784 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6785
6786 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6787 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
6788 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
6789
6790 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6791 I915_WRITE(GEN7_L3CNTLREG1,
6792 GEN7_WA_FOR_GEN7_L3_CONTROL);
6793 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
6794 GEN7_WA_L3_CHICKEN_MODE);
6795 if (IS_IVB_GT1(dev))
6796 I915_WRITE(GEN7_ROW_CHICKEN2,
6797 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6798 else {
6799 /* must write both registers */
6800 I915_WRITE(GEN7_ROW_CHICKEN2,
6801 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6802 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
6803 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6804 }
6805
6806 /* WaForceL3Serialization:ivb */
6807 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6808 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6809
6810 /*
6811 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6812 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
6813 */
6814 I915_WRITE(GEN6_UCGCTL2,
6815 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
6816
6817 /* This is required by WaCatErrorRejectionIssue:ivb */
6818 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6819 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6820 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6821
6822 g4x_disable_trickle_feed(dev);
6823
6824 gen7_setup_fixed_func_scheduler(dev_priv);
6825
6826 if (0) { /* causes HiZ corruption on ivb:gt1 */
6827 /* enable HiZ Raw Stall Optimization */
6828 I915_WRITE(CACHE_MODE_0_GEN7,
6829 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6830 }
6831
6832 /* WaDisable4x2SubspanOptimization:ivb */
6833 I915_WRITE(CACHE_MODE_1,
6834 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6835
6836 /*
6837 * BSpec recommends 8x4 when MSAA is used,
6838 * however in practice 16x4 seems fastest.
6839 *
6840 * Note that PS/WM thread counts depend on the WIZ hashing
6841 * disable bit, which we don't touch here, but it's good
6842 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6843 */
6844 I915_WRITE(GEN7_GT_MODE,
6845 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6846
6847 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
6848 snpcr &= ~GEN6_MBC_SNPCR_MASK;
6849 snpcr |= GEN6_MBC_SNPCR_MED;
6850 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
6851
6852 if (!HAS_PCH_NOP(dev))
6853 cpt_init_clock_gating(dev);
6854
6855 gen6_check_mch_setup(dev);
6856 }
6857
6858 static void valleyview_init_clock_gating(struct drm_device *dev)
6859 {
6860 struct drm_i915_private *dev_priv = dev->dev_private;
6861
6862 /* WaDisableEarlyCull:vlv */
6863 I915_WRITE(_3D_CHICKEN3,
6864 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6865
6866 /* WaDisableBackToBackFlipFix:vlv */
6867 I915_WRITE(IVB_CHICKEN3,
6868 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6869 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6870
6871 /* WaPsdDispatchEnable:vlv */
6872 /* WaDisablePSDDualDispatchEnable:vlv */
6873 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6874 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
6875 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
6876
6877 /* WaDisable_RenderCache_OperationalFlush:vlv */
6878 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6879
6880 /* WaForceL3Serialization:vlv */
6881 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6882 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6883
6884 /* WaDisableDopClockGating:vlv */
6885 I915_WRITE(GEN7_ROW_CHICKEN2,
6886 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6887
6888 /* This is required by WaCatErrorRejectionIssue:vlv */
6889 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6890 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6891 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6892
6893 gen7_setup_fixed_func_scheduler(dev_priv);
6894
6895 /*
6896 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6897 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
6898 */
6899 I915_WRITE(GEN6_UCGCTL2,
6900 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
6901
6902 /* WaDisableL3Bank2xClockGate:vlv
6903 * Disabling L3 clock gating- MMIO 940c[25] = 1
6904 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
6905 I915_WRITE(GEN7_UCGCTL4,
6906 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
6907
6908 /*
6909 * BSpec says this must be set, even though
6910 * WaDisable4x2SubspanOptimization isn't listed for VLV.
6911 */
6912 I915_WRITE(CACHE_MODE_1,
6913 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6914
6915 /*
6916 * BSpec recommends 8x4 when MSAA is used,
6917 * however in practice 16x4 seems fastest.
6918 *
6919 * Note that PS/WM thread counts depend on the WIZ hashing
6920 * disable bit, which we don't touch here, but it's good
6921 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6922 */
6923 I915_WRITE(GEN7_GT_MODE,
6924 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6925
6926 /*
6927 * WaIncreaseL3CreditsForVLVB0:vlv
6928 * This is the hardware default actually.
6929 */
6930 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
6931
6932 /*
6933 * WaDisableVLVClockGating_VBIIssue:vlv
6934 * Disable clock gating on th GCFG unit to prevent a delay
6935 * in the reporting of vblank events.
6936 */
6937 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6938 }
6939
6940 static void cherryview_init_clock_gating(struct drm_device *dev)
6941 {
6942 struct drm_i915_private *dev_priv = dev->dev_private;
6943
6944 /* WaVSRefCountFullforceMissDisable:chv */
6945 /* WaDSRefCountFullforceMissDisable:chv */
6946 I915_WRITE(GEN7_FF_THREAD_MODE,
6947 I915_READ(GEN7_FF_THREAD_MODE) &
6948 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
6949
6950 /* WaDisableSemaphoreAndSyncFlipWait:chv */
6951 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6952 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
6953
6954 /* WaDisableCSUnitClockGating:chv */
6955 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
6956 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6957
6958 /* WaDisableSDEUnitClockGating:chv */
6959 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6960 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6961
6962 /*
6963 * WaProgramL3SqcReg1Default:chv
6964 * See gfxspecs/Related Documents/Performance Guide/
6965 * LSQC Setting Recommendations.
6966 */
6967 gen8_set_l3sqc_credits(dev_priv, 38, 2);
6968
6969 /*
6970 * GTT cache may not work with big pages, so if those
6971 * are ever enabled GTT cache may need to be disabled.
6972 */
6973 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
6974 }
6975
6976 static void g4x_init_clock_gating(struct drm_device *dev)
6977 {
6978 struct drm_i915_private *dev_priv = dev->dev_private;
6979 uint32_t dspclk_gate;
6980
6981 I915_WRITE(RENCLK_GATE_D1, 0);
6982 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
6983 GS_UNIT_CLOCK_GATE_DISABLE |
6984 CL_UNIT_CLOCK_GATE_DISABLE);
6985 I915_WRITE(RAMCLK_GATE_D, 0);
6986 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
6987 OVRUNIT_CLOCK_GATE_DISABLE |
6988 OVCUNIT_CLOCK_GATE_DISABLE;
6989 if (IS_GM45(dev))
6990 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
6991 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
6992
6993 /* WaDisableRenderCachePipelinedFlush */
6994 I915_WRITE(CACHE_MODE_0,
6995 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6996
6997 /* WaDisable_RenderCache_OperationalFlush:g4x */
6998 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6999
7000 g4x_disable_trickle_feed(dev);
7001 }
7002
7003 static void crestline_init_clock_gating(struct drm_device *dev)
7004 {
7005 struct drm_i915_private *dev_priv = dev->dev_private;
7006
7007 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7008 I915_WRITE(RENCLK_GATE_D2, 0);
7009 I915_WRITE(DSPCLK_GATE_D, 0);
7010 I915_WRITE(RAMCLK_GATE_D, 0);
7011 I915_WRITE16(DEUC, 0);
7012 I915_WRITE(MI_ARB_STATE,
7013 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7014
7015 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7016 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7017 }
7018
7019 static void broadwater_init_clock_gating(struct drm_device *dev)
7020 {
7021 struct drm_i915_private *dev_priv = dev->dev_private;
7022
7023 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7024 I965_RCC_CLOCK_GATE_DISABLE |
7025 I965_RCPB_CLOCK_GATE_DISABLE |
7026 I965_ISC_CLOCK_GATE_DISABLE |
7027 I965_FBC_CLOCK_GATE_DISABLE);
7028 I915_WRITE(RENCLK_GATE_D2, 0);
7029 I915_WRITE(MI_ARB_STATE,
7030 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7031
7032 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7033 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7034 }
7035
7036 static void gen3_init_clock_gating(struct drm_device *dev)
7037 {
7038 struct drm_i915_private *dev_priv = dev->dev_private;
7039 u32 dstate = I915_READ(D_STATE);
7040
7041 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7042 DSTATE_DOT_CLOCK_GATING;
7043 I915_WRITE(D_STATE, dstate);
7044
7045 if (IS_PINEVIEW(dev))
7046 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
7047
7048 /* IIR "flip pending" means done if this bit is set */
7049 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
7050
7051 /* interrupts should cause a wake up from C3 */
7052 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
7053
7054 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7055 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
7056
7057 I915_WRITE(MI_ARB_STATE,
7058 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7059 }
7060
7061 static void i85x_init_clock_gating(struct drm_device *dev)
7062 {
7063 struct drm_i915_private *dev_priv = dev->dev_private;
7064
7065 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7066
7067 /* interrupts should cause a wake up from C3 */
7068 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7069 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
7070
7071 I915_WRITE(MEM_MODE,
7072 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
7073 }
7074
7075 static void i830_init_clock_gating(struct drm_device *dev)
7076 {
7077 struct drm_i915_private *dev_priv = dev->dev_private;
7078
7079 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
7080
7081 I915_WRITE(MEM_MODE,
7082 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7083 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
7084 }
7085
7086 void intel_init_clock_gating(struct drm_device *dev)
7087 {
7088 struct drm_i915_private *dev_priv = dev->dev_private;
7089
7090 dev_priv->display.init_clock_gating(dev);
7091 }
7092
7093 void intel_suspend_hw(struct drm_device *dev)
7094 {
7095 if (HAS_PCH_LPT(dev))
7096 lpt_suspend_hw(dev);
7097 }
7098
7099 static void nop_init_clock_gating(struct drm_device *dev)
7100 {
7101 DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n");
7102 }
7103
7104 /**
7105 * intel_init_clock_gating_hooks - setup the clock gating hooks
7106 * @dev_priv: device private
7107 *
7108 * Setup the hooks that configure which clocks of a given platform can be
7109 * gated and also apply various GT and display specific workarounds for these
7110 * platforms. Note that some GT specific workarounds are applied separately
7111 * when GPU contexts or batchbuffers start their execution.
7112 */
7113 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
7114 {
7115 if (IS_SKYLAKE(dev_priv))
7116 dev_priv->display.init_clock_gating = nop_init_clock_gating;
7117 else if (IS_KABYLAKE(dev_priv))
7118 dev_priv->display.init_clock_gating = nop_init_clock_gating;
7119 else if (IS_BROXTON(dev_priv))
7120 dev_priv->display.init_clock_gating = bxt_init_clock_gating;
7121 else if (IS_BROADWELL(dev_priv))
7122 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7123 else if (IS_CHERRYVIEW(dev_priv))
7124 dev_priv->display.init_clock_gating = cherryview_init_clock_gating;
7125 else if (IS_HASWELL(dev_priv))
7126 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7127 else if (IS_IVYBRIDGE(dev_priv))
7128 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7129 else if (IS_VALLEYVIEW(dev_priv))
7130 dev_priv->display.init_clock_gating = valleyview_init_clock_gating;
7131 else if (IS_GEN6(dev_priv))
7132 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7133 else if (IS_GEN5(dev_priv))
7134 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7135 else if (IS_G4X(dev_priv))
7136 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7137 else if (IS_CRESTLINE(dev_priv))
7138 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7139 else if (IS_BROADWATER(dev_priv))
7140 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7141 else if (IS_GEN3(dev_priv))
7142 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7143 else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
7144 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7145 else if (IS_GEN2(dev_priv))
7146 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7147 else {
7148 MISSING_CASE(INTEL_DEVID(dev_priv));
7149 dev_priv->display.init_clock_gating = nop_init_clock_gating;
7150 }
7151 }
7152
7153 /* Set up chip specific power management-related functions */
7154 void intel_init_pm(struct drm_device *dev)
7155 {
7156 struct drm_i915_private *dev_priv = dev->dev_private;
7157
7158 intel_fbc_init(dev_priv);
7159
7160 /* For cxsr */
7161 if (IS_PINEVIEW(dev))
7162 i915_pineview_get_mem_freq(dev);
7163 else if (IS_GEN5(dev))
7164 i915_ironlake_get_mem_freq(dev);
7165
7166 /* For FIFO watermark updates */
7167 if (INTEL_INFO(dev)->gen >= 9) {
7168 skl_setup_wm_latency(dev);
7169 dev_priv->display.update_wm = skl_update_wm;
7170 } else if (HAS_PCH_SPLIT(dev)) {
7171 ilk_setup_wm_latency(dev);
7172
7173 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
7174 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7175 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7176 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
7177 dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
7178 dev_priv->display.compute_intermediate_wm =
7179 ilk_compute_intermediate_wm;
7180 dev_priv->display.initial_watermarks =
7181 ilk_initial_watermarks;
7182 dev_priv->display.optimize_watermarks =
7183 ilk_optimize_watermarks;
7184 } else {
7185 DRM_DEBUG_KMS("Failed to read display plane latency. "
7186 "Disable CxSR\n");
7187 }
7188 } else if (IS_CHERRYVIEW(dev)) {
7189 vlv_setup_wm_latency(dev);
7190 dev_priv->display.update_wm = vlv_update_wm;
7191 } else if (IS_VALLEYVIEW(dev)) {
7192 vlv_setup_wm_latency(dev);
7193 dev_priv->display.update_wm = vlv_update_wm;
7194 } else if (IS_PINEVIEW(dev)) {
7195 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7196 dev_priv->is_ddr3,
7197 dev_priv->fsb_freq,
7198 dev_priv->mem_freq)) {
7199 DRM_INFO("failed to find known CxSR latency "
7200 "(found ddr%s fsb freq %d, mem freq %d), "
7201 "disabling CxSR\n",
7202 (dev_priv->is_ddr3 == 1) ? "3" : "2",
7203 dev_priv->fsb_freq, dev_priv->mem_freq);
7204 /* Disable CxSR and never update its watermark again */
7205 intel_set_memory_cxsr(dev_priv, false);
7206 dev_priv->display.update_wm = NULL;
7207 } else
7208 dev_priv->display.update_wm = pineview_update_wm;
7209 } else if (IS_G4X(dev)) {
7210 dev_priv->display.update_wm = g4x_update_wm;
7211 } else if (IS_GEN4(dev)) {
7212 dev_priv->display.update_wm = i965_update_wm;
7213 } else if (IS_GEN3(dev)) {
7214 dev_priv->display.update_wm = i9xx_update_wm;
7215 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7216 } else if (IS_GEN2(dev)) {
7217 if (INTEL_INFO(dev)->num_pipes == 1) {
7218 dev_priv->display.update_wm = i845_update_wm;
7219 dev_priv->display.get_fifo_size = i845_get_fifo_size;
7220 } else {
7221 dev_priv->display.update_wm = i9xx_update_wm;
7222 dev_priv->display.get_fifo_size = i830_get_fifo_size;
7223 }
7224 } else {
7225 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
7226 }
7227 }
7228
7229 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
7230 {
7231 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7232
7233 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7234 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7235 return -EAGAIN;
7236 }
7237
7238 I915_WRITE(GEN6_PCODE_DATA, *val);
7239 I915_WRITE(GEN6_PCODE_DATA1, 0);
7240 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7241
7242 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7243 500)) {
7244 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7245 return -ETIMEDOUT;
7246 }
7247
7248 *val = I915_READ(GEN6_PCODE_DATA);
7249 I915_WRITE(GEN6_PCODE_DATA, 0);
7250
7251 return 0;
7252 }
7253
7254 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val)
7255 {
7256 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7257
7258 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7259 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7260 return -EAGAIN;
7261 }
7262
7263 I915_WRITE(GEN6_PCODE_DATA, val);
7264 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7265
7266 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7267 500)) {
7268 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7269 return -ETIMEDOUT;
7270 }
7271
7272 I915_WRITE(GEN6_PCODE_DATA, 0);
7273
7274 return 0;
7275 }
7276
7277 static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7278 {
7279 /*
7280 * N = val - 0xb7
7281 * Slow = Fast = GPLL ref * N
7282 */
7283 return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * (val - 0xb7), 1000);
7284 }
7285
7286 static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
7287 {
7288 return DIV_ROUND_CLOSEST(1000 * val, dev_priv->rps.gpll_ref_freq) + 0xb7;
7289 }
7290
7291 static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
7292 {
7293 /*
7294 * N = val / 2
7295 * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2
7296 */
7297 return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * val, 2 * 2 * 1000);
7298 }
7299
7300 static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
7301 {
7302 /* CHV needs even values */
7303 return DIV_ROUND_CLOSEST(2 * 1000 * val, dev_priv->rps.gpll_ref_freq) * 2;
7304 }
7305
7306 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
7307 {
7308 if (IS_GEN9(dev_priv))
7309 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
7310 GEN9_FREQ_SCALER);
7311 else if (IS_CHERRYVIEW(dev_priv))
7312 return chv_gpu_freq(dev_priv, val);
7313 else if (IS_VALLEYVIEW(dev_priv))
7314 return byt_gpu_freq(dev_priv, val);
7315 else
7316 return val * GT_FREQUENCY_MULTIPLIER;
7317 }
7318
7319 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7320 {
7321 if (IS_GEN9(dev_priv))
7322 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
7323 GT_FREQUENCY_MULTIPLIER);
7324 else if (IS_CHERRYVIEW(dev_priv))
7325 return chv_freq_opcode(dev_priv, val);
7326 else if (IS_VALLEYVIEW(dev_priv))
7327 return byt_freq_opcode(dev_priv, val);
7328 else
7329 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
7330 }
7331
7332 struct request_boost {
7333 struct work_struct work;
7334 struct drm_i915_gem_request *req;
7335 };
7336
7337 static void __intel_rps_boost_work(struct work_struct *work)
7338 {
7339 struct request_boost *boost = container_of(work, struct request_boost, work);
7340 struct drm_i915_gem_request *req = boost->req;
7341
7342 if (!i915_gem_request_completed(req, true))
7343 gen6_rps_boost(req->i915, NULL, req->emitted_jiffies);
7344
7345 i915_gem_request_unreference(req);
7346 kfree(boost);
7347 }
7348
7349 void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req)
7350 {
7351 struct request_boost *boost;
7352
7353 if (req == NULL || INTEL_GEN(req->i915) < 6)
7354 return;
7355
7356 if (i915_gem_request_completed(req, true))
7357 return;
7358
7359 boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
7360 if (boost == NULL)
7361 return;
7362
7363 i915_gem_request_reference(req);
7364 boost->req = req;
7365
7366 INIT_WORK(&boost->work, __intel_rps_boost_work);
7367 queue_work(req->i915->wq, &boost->work);
7368 }
7369
7370 void intel_pm_setup(struct drm_device *dev)
7371 {
7372 struct drm_i915_private *dev_priv = dev->dev_private;
7373
7374 mutex_init(&dev_priv->rps.hw_lock);
7375 spin_lock_init(&dev_priv->rps.client_lock);
7376
7377 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
7378 intel_gen6_powersave_work);
7379 INIT_LIST_HEAD(&dev_priv->rps.clients);
7380 INIT_LIST_HEAD(&dev_priv->rps.semaphores.link);
7381 INIT_LIST_HEAD(&dev_priv->rps.mmioflips.link);
7382
7383 dev_priv->pm.suspended = false;
7384 atomic_set(&dev_priv->pm.wakeref_count, 0);
7385 atomic_set(&dev_priv->pm.atomic_seq, 0);
7386 }
Linux kernel - Deliverables
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