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drm/i915: Enable querying offset of UV plane with intel_plane_obj_offset
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_pm.c
1 /*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28 #include <linux/cpufreq.h>
29 #include "i915_drv.h"
30 #include "intel_drv.h"
31 #include "../../../platform/x86/intel_ips.h"
32 #include <linux/module.h>
33
34 /**
35 * RC6 is a special power stage which allows the GPU to enter an very
36 * low-voltage mode when idle, using down to 0V while at this stage. This
37 * stage is entered automatically when the GPU is idle when RC6 support is
38 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
39 *
40 * There are different RC6 modes available in Intel GPU, which differentiate
41 * among each other with the latency required to enter and leave RC6 and
42 * voltage consumed by the GPU in different states.
43 *
44 * The combination of the following flags define which states GPU is allowed
45 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
46 * RC6pp is deepest RC6. Their support by hardware varies according to the
47 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
48 * which brings the most power savings; deeper states save more power, but
49 * require higher latency to switch to and wake up.
50 */
51 #define INTEL_RC6_ENABLE (1<<0)
52 #define INTEL_RC6p_ENABLE (1<<1)
53 #define INTEL_RC6pp_ENABLE (1<<2)
54
55 static void gen9_init_clock_gating(struct drm_device *dev)
56 {
57 struct drm_i915_private *dev_priv = dev->dev_private;
58
59 /* WaEnableLbsSlaRetryTimerDecrement:skl */
60 I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
61 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
62
63 /* WaDisableKillLogic:bxt,skl */
64 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
65 ECOCHK_DIS_TLB);
66 }
67
68 static void skl_init_clock_gating(struct drm_device *dev)
69 {
70 struct drm_i915_private *dev_priv = dev->dev_private;
71
72 gen9_init_clock_gating(dev);
73
74 if (INTEL_REVID(dev) <= SKL_REVID_B0) {
75 /*
76 * WaDisableSDEUnitClockGating:skl
77 * WaSetGAPSunitClckGateDisable:skl
78 */
79 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
80 GEN8_GAPSUNIT_CLOCK_GATE_DISABLE |
81 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
82
83 /* WaDisableVFUnitClockGating:skl */
84 I915_WRITE(GEN6_UCGCTL2, I915_READ(GEN6_UCGCTL2) |
85 GEN6_VFUNIT_CLOCK_GATE_DISABLE);
86 }
87
88 if (INTEL_REVID(dev) <= SKL_REVID_D0) {
89 /* WaDisableHDCInvalidation:skl */
90 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
91 BDW_DISABLE_HDC_INVALIDATION);
92
93 /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
94 I915_WRITE(FF_SLICE_CS_CHICKEN2,
95 _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE));
96 }
97
98 /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
99 * involving this register should also be added to WA batch as required.
100 */
101 if (INTEL_REVID(dev) <= SKL_REVID_E0)
102 /* WaDisableLSQCROPERFforOCL:skl */
103 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
104 GEN8_LQSC_RO_PERF_DIS);
105
106 /* WaEnableGapsTsvCreditFix:skl */
107 if (IS_SKYLAKE(dev) && (INTEL_REVID(dev) >= SKL_REVID_C0)) {
108 I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
109 GEN9_GAPS_TSV_CREDIT_DISABLE));
110 }
111 }
112
113 static void bxt_init_clock_gating(struct drm_device *dev)
114 {
115 struct drm_i915_private *dev_priv = dev->dev_private;
116
117 gen9_init_clock_gating(dev);
118
119 /* WaDisableSDEUnitClockGating:bxt */
120 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
121 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
122
123 /*
124 * FIXME:
125 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
126 */
127 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
128 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
129
130 if (INTEL_REVID(dev) == BXT_REVID_A0) {
131 /*
132 * Hardware specification requires this bit to be
133 * set to 1 for A0
134 */
135 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
136 }
137
138 /* WaSetClckGatingDisableMedia:bxt */
139 if (INTEL_REVID(dev) == BXT_REVID_A0) {
140 I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) &
141 ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE));
142 }
143 }
144
145 static void i915_pineview_get_mem_freq(struct drm_device *dev)
146 {
147 struct drm_i915_private *dev_priv = dev->dev_private;
148 u32 tmp;
149
150 tmp = I915_READ(CLKCFG);
151
152 switch (tmp & CLKCFG_FSB_MASK) {
153 case CLKCFG_FSB_533:
154 dev_priv->fsb_freq = 533; /* 133*4 */
155 break;
156 case CLKCFG_FSB_800:
157 dev_priv->fsb_freq = 800; /* 200*4 */
158 break;
159 case CLKCFG_FSB_667:
160 dev_priv->fsb_freq = 667; /* 167*4 */
161 break;
162 case CLKCFG_FSB_400:
163 dev_priv->fsb_freq = 400; /* 100*4 */
164 break;
165 }
166
167 switch (tmp & CLKCFG_MEM_MASK) {
168 case CLKCFG_MEM_533:
169 dev_priv->mem_freq = 533;
170 break;
171 case CLKCFG_MEM_667:
172 dev_priv->mem_freq = 667;
173 break;
174 case CLKCFG_MEM_800:
175 dev_priv->mem_freq = 800;
176 break;
177 }
178
179 /* detect pineview DDR3 setting */
180 tmp = I915_READ(CSHRDDR3CTL);
181 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
182 }
183
184 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
185 {
186 struct drm_i915_private *dev_priv = dev->dev_private;
187 u16 ddrpll, csipll;
188
189 ddrpll = I915_READ16(DDRMPLL1);
190 csipll = I915_READ16(CSIPLL0);
191
192 switch (ddrpll & 0xff) {
193 case 0xc:
194 dev_priv->mem_freq = 800;
195 break;
196 case 0x10:
197 dev_priv->mem_freq = 1066;
198 break;
199 case 0x14:
200 dev_priv->mem_freq = 1333;
201 break;
202 case 0x18:
203 dev_priv->mem_freq = 1600;
204 break;
205 default:
206 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
207 ddrpll & 0xff);
208 dev_priv->mem_freq = 0;
209 break;
210 }
211
212 dev_priv->ips.r_t = dev_priv->mem_freq;
213
214 switch (csipll & 0x3ff) {
215 case 0x00c:
216 dev_priv->fsb_freq = 3200;
217 break;
218 case 0x00e:
219 dev_priv->fsb_freq = 3733;
220 break;
221 case 0x010:
222 dev_priv->fsb_freq = 4266;
223 break;
224 case 0x012:
225 dev_priv->fsb_freq = 4800;
226 break;
227 case 0x014:
228 dev_priv->fsb_freq = 5333;
229 break;
230 case 0x016:
231 dev_priv->fsb_freq = 5866;
232 break;
233 case 0x018:
234 dev_priv->fsb_freq = 6400;
235 break;
236 default:
237 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
238 csipll & 0x3ff);
239 dev_priv->fsb_freq = 0;
240 break;
241 }
242
243 if (dev_priv->fsb_freq == 3200) {
244 dev_priv->ips.c_m = 0;
245 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
246 dev_priv->ips.c_m = 1;
247 } else {
248 dev_priv->ips.c_m = 2;
249 }
250 }
251
252 static const struct cxsr_latency cxsr_latency_table[] = {
253 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
254 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
255 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
256 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
257 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
258
259 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
260 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
261 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
262 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
263 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
264
265 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
266 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
267 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
268 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
269 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
270
271 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
272 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
273 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
274 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
275 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
276
277 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
278 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
279 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
280 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
281 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
282
283 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
284 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
285 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
286 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
287 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
288 };
289
290 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
291 int is_ddr3,
292 int fsb,
293 int mem)
294 {
295 const struct cxsr_latency *latency;
296 int i;
297
298 if (fsb == 0 || mem == 0)
299 return NULL;
300
301 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
302 latency = &cxsr_latency_table[i];
303 if (is_desktop == latency->is_desktop &&
304 is_ddr3 == latency->is_ddr3 &&
305 fsb == latency->fsb_freq && mem == latency->mem_freq)
306 return latency;
307 }
308
309 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
310
311 return NULL;
312 }
313
314 static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
315 {
316 u32 val;
317
318 mutex_lock(&dev_priv->rps.hw_lock);
319
320 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
321 if (enable)
322 val &= ~FORCE_DDR_HIGH_FREQ;
323 else
324 val |= FORCE_DDR_HIGH_FREQ;
325 val &= ~FORCE_DDR_LOW_FREQ;
326 val |= FORCE_DDR_FREQ_REQ_ACK;
327 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
328
329 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
330 FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
331 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
332
333 mutex_unlock(&dev_priv->rps.hw_lock);
334 }
335
336 static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
337 {
338 u32 val;
339
340 mutex_lock(&dev_priv->rps.hw_lock);
341
342 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
343 if (enable)
344 val |= DSP_MAXFIFO_PM5_ENABLE;
345 else
346 val &= ~DSP_MAXFIFO_PM5_ENABLE;
347 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
348
349 mutex_unlock(&dev_priv->rps.hw_lock);
350 }
351
352 #define FW_WM(value, plane) \
353 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
354
355 void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
356 {
357 struct drm_device *dev = dev_priv->dev;
358 u32 val;
359
360 if (IS_VALLEYVIEW(dev)) {
361 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
362 POSTING_READ(FW_BLC_SELF_VLV);
363 dev_priv->wm.vlv.cxsr = enable;
364 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
365 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
366 POSTING_READ(FW_BLC_SELF);
367 } else if (IS_PINEVIEW(dev)) {
368 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
369 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
370 I915_WRITE(DSPFW3, val);
371 POSTING_READ(DSPFW3);
372 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
373 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
374 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
375 I915_WRITE(FW_BLC_SELF, val);
376 POSTING_READ(FW_BLC_SELF);
377 } else if (IS_I915GM(dev)) {
378 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
379 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
380 I915_WRITE(INSTPM, val);
381 POSTING_READ(INSTPM);
382 } else {
383 return;
384 }
385
386 DRM_DEBUG_KMS("memory self-refresh is %s\n",
387 enable ? "enabled" : "disabled");
388 }
389
390
391 /*
392 * Latency for FIFO fetches is dependent on several factors:
393 * - memory configuration (speed, channels)
394 * - chipset
395 * - current MCH state
396 * It can be fairly high in some situations, so here we assume a fairly
397 * pessimal value. It's a tradeoff between extra memory fetches (if we
398 * set this value too high, the FIFO will fetch frequently to stay full)
399 * and power consumption (set it too low to save power and we might see
400 * FIFO underruns and display "flicker").
401 *
402 * A value of 5us seems to be a good balance; safe for very low end
403 * platforms but not overly aggressive on lower latency configs.
404 */
405 static const int pessimal_latency_ns = 5000;
406
407 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
408 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
409
410 static int vlv_get_fifo_size(struct drm_device *dev,
411 enum pipe pipe, int plane)
412 {
413 struct drm_i915_private *dev_priv = dev->dev_private;
414 int sprite0_start, sprite1_start, size;
415
416 switch (pipe) {
417 uint32_t dsparb, dsparb2, dsparb3;
418 case PIPE_A:
419 dsparb = I915_READ(DSPARB);
420 dsparb2 = I915_READ(DSPARB2);
421 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
422 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
423 break;
424 case PIPE_B:
425 dsparb = I915_READ(DSPARB);
426 dsparb2 = I915_READ(DSPARB2);
427 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
428 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
429 break;
430 case PIPE_C:
431 dsparb2 = I915_READ(DSPARB2);
432 dsparb3 = I915_READ(DSPARB3);
433 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
434 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
435 break;
436 default:
437 return 0;
438 }
439
440 switch (plane) {
441 case 0:
442 size = sprite0_start;
443 break;
444 case 1:
445 size = sprite1_start - sprite0_start;
446 break;
447 case 2:
448 size = 512 - 1 - sprite1_start;
449 break;
450 default:
451 return 0;
452 }
453
454 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
455 pipe_name(pipe), plane == 0 ? "primary" : "sprite",
456 plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
457 size);
458
459 return size;
460 }
461
462 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
463 {
464 struct drm_i915_private *dev_priv = dev->dev_private;
465 uint32_t dsparb = I915_READ(DSPARB);
466 int size;
467
468 size = dsparb & 0x7f;
469 if (plane)
470 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
471
472 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
473 plane ? "B" : "A", size);
474
475 return size;
476 }
477
478 static int i830_get_fifo_size(struct drm_device *dev, int plane)
479 {
480 struct drm_i915_private *dev_priv = dev->dev_private;
481 uint32_t dsparb = I915_READ(DSPARB);
482 int size;
483
484 size = dsparb & 0x1ff;
485 if (plane)
486 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
487 size >>= 1; /* Convert to cachelines */
488
489 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
490 plane ? "B" : "A", size);
491
492 return size;
493 }
494
495 static int i845_get_fifo_size(struct drm_device *dev, int plane)
496 {
497 struct drm_i915_private *dev_priv = dev->dev_private;
498 uint32_t dsparb = I915_READ(DSPARB);
499 int size;
500
501 size = dsparb & 0x7f;
502 size >>= 2; /* Convert to cachelines */
503
504 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
505 plane ? "B" : "A",
506 size);
507
508 return size;
509 }
510
511 /* Pineview has different values for various configs */
512 static const struct intel_watermark_params pineview_display_wm = {
513 .fifo_size = PINEVIEW_DISPLAY_FIFO,
514 .max_wm = PINEVIEW_MAX_WM,
515 .default_wm = PINEVIEW_DFT_WM,
516 .guard_size = PINEVIEW_GUARD_WM,
517 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
518 };
519 static const struct intel_watermark_params pineview_display_hplloff_wm = {
520 .fifo_size = PINEVIEW_DISPLAY_FIFO,
521 .max_wm = PINEVIEW_MAX_WM,
522 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
523 .guard_size = PINEVIEW_GUARD_WM,
524 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
525 };
526 static const struct intel_watermark_params pineview_cursor_wm = {
527 .fifo_size = PINEVIEW_CURSOR_FIFO,
528 .max_wm = PINEVIEW_CURSOR_MAX_WM,
529 .default_wm = PINEVIEW_CURSOR_DFT_WM,
530 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
531 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
532 };
533 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
534 .fifo_size = PINEVIEW_CURSOR_FIFO,
535 .max_wm = PINEVIEW_CURSOR_MAX_WM,
536 .default_wm = PINEVIEW_CURSOR_DFT_WM,
537 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
538 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
539 };
540 static const struct intel_watermark_params g4x_wm_info = {
541 .fifo_size = G4X_FIFO_SIZE,
542 .max_wm = G4X_MAX_WM,
543 .default_wm = G4X_MAX_WM,
544 .guard_size = 2,
545 .cacheline_size = G4X_FIFO_LINE_SIZE,
546 };
547 static const struct intel_watermark_params g4x_cursor_wm_info = {
548 .fifo_size = I965_CURSOR_FIFO,
549 .max_wm = I965_CURSOR_MAX_WM,
550 .default_wm = I965_CURSOR_DFT_WM,
551 .guard_size = 2,
552 .cacheline_size = G4X_FIFO_LINE_SIZE,
553 };
554 static const struct intel_watermark_params valleyview_wm_info = {
555 .fifo_size = VALLEYVIEW_FIFO_SIZE,
556 .max_wm = VALLEYVIEW_MAX_WM,
557 .default_wm = VALLEYVIEW_MAX_WM,
558 .guard_size = 2,
559 .cacheline_size = G4X_FIFO_LINE_SIZE,
560 };
561 static const struct intel_watermark_params valleyview_cursor_wm_info = {
562 .fifo_size = I965_CURSOR_FIFO,
563 .max_wm = VALLEYVIEW_CURSOR_MAX_WM,
564 .default_wm = I965_CURSOR_DFT_WM,
565 .guard_size = 2,
566 .cacheline_size = G4X_FIFO_LINE_SIZE,
567 };
568 static const struct intel_watermark_params i965_cursor_wm_info = {
569 .fifo_size = I965_CURSOR_FIFO,
570 .max_wm = I965_CURSOR_MAX_WM,
571 .default_wm = I965_CURSOR_DFT_WM,
572 .guard_size = 2,
573 .cacheline_size = I915_FIFO_LINE_SIZE,
574 };
575 static const struct intel_watermark_params i945_wm_info = {
576 .fifo_size = I945_FIFO_SIZE,
577 .max_wm = I915_MAX_WM,
578 .default_wm = 1,
579 .guard_size = 2,
580 .cacheline_size = I915_FIFO_LINE_SIZE,
581 };
582 static const struct intel_watermark_params i915_wm_info = {
583 .fifo_size = I915_FIFO_SIZE,
584 .max_wm = I915_MAX_WM,
585 .default_wm = 1,
586 .guard_size = 2,
587 .cacheline_size = I915_FIFO_LINE_SIZE,
588 };
589 static const struct intel_watermark_params i830_a_wm_info = {
590 .fifo_size = I855GM_FIFO_SIZE,
591 .max_wm = I915_MAX_WM,
592 .default_wm = 1,
593 .guard_size = 2,
594 .cacheline_size = I830_FIFO_LINE_SIZE,
595 };
596 static const struct intel_watermark_params i830_bc_wm_info = {
597 .fifo_size = I855GM_FIFO_SIZE,
598 .max_wm = I915_MAX_WM/2,
599 .default_wm = 1,
600 .guard_size = 2,
601 .cacheline_size = I830_FIFO_LINE_SIZE,
602 };
603 static const struct intel_watermark_params i845_wm_info = {
604 .fifo_size = I830_FIFO_SIZE,
605 .max_wm = I915_MAX_WM,
606 .default_wm = 1,
607 .guard_size = 2,
608 .cacheline_size = I830_FIFO_LINE_SIZE,
609 };
610
611 /**
612 * intel_calculate_wm - calculate watermark level
613 * @clock_in_khz: pixel clock
614 * @wm: chip FIFO params
615 * @pixel_size: display pixel size
616 * @latency_ns: memory latency for the platform
617 *
618 * Calculate the watermark level (the level at which the display plane will
619 * start fetching from memory again). Each chip has a different display
620 * FIFO size and allocation, so the caller needs to figure that out and pass
621 * in the correct intel_watermark_params structure.
622 *
623 * As the pixel clock runs, the FIFO will be drained at a rate that depends
624 * on the pixel size. When it reaches the watermark level, it'll start
625 * fetching FIFO line sized based chunks from memory until the FIFO fills
626 * past the watermark point. If the FIFO drains completely, a FIFO underrun
627 * will occur, and a display engine hang could result.
628 */
629 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
630 const struct intel_watermark_params *wm,
631 int fifo_size,
632 int pixel_size,
633 unsigned long latency_ns)
634 {
635 long entries_required, wm_size;
636
637 /*
638 * Note: we need to make sure we don't overflow for various clock &
639 * latency values.
640 * clocks go from a few thousand to several hundred thousand.
641 * latency is usually a few thousand
642 */
643 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
644 1000;
645 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
646
647 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
648
649 wm_size = fifo_size - (entries_required + wm->guard_size);
650
651 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
652
653 /* Don't promote wm_size to unsigned... */
654 if (wm_size > (long)wm->max_wm)
655 wm_size = wm->max_wm;
656 if (wm_size <= 0)
657 wm_size = wm->default_wm;
658
659 /*
660 * Bspec seems to indicate that the value shouldn't be lower than
661 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
662 * Lets go for 8 which is the burst size since certain platforms
663 * already use a hardcoded 8 (which is what the spec says should be
664 * done).
665 */
666 if (wm_size <= 8)
667 wm_size = 8;
668
669 return wm_size;
670 }
671
672 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
673 {
674 struct drm_crtc *crtc, *enabled = NULL;
675
676 for_each_crtc(dev, crtc) {
677 if (intel_crtc_active(crtc)) {
678 if (enabled)
679 return NULL;
680 enabled = crtc;
681 }
682 }
683
684 return enabled;
685 }
686
687 static void pineview_update_wm(struct drm_crtc *unused_crtc)
688 {
689 struct drm_device *dev = unused_crtc->dev;
690 struct drm_i915_private *dev_priv = dev->dev_private;
691 struct drm_crtc *crtc;
692 const struct cxsr_latency *latency;
693 u32 reg;
694 unsigned long wm;
695
696 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
697 dev_priv->fsb_freq, dev_priv->mem_freq);
698 if (!latency) {
699 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
700 intel_set_memory_cxsr(dev_priv, false);
701 return;
702 }
703
704 crtc = single_enabled_crtc(dev);
705 if (crtc) {
706 const struct drm_display_mode *adjusted_mode;
707 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
708 int clock;
709
710 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
711 clock = adjusted_mode->crtc_clock;
712
713 /* Display SR */
714 wm = intel_calculate_wm(clock, &pineview_display_wm,
715 pineview_display_wm.fifo_size,
716 pixel_size, latency->display_sr);
717 reg = I915_READ(DSPFW1);
718 reg &= ~DSPFW_SR_MASK;
719 reg |= FW_WM(wm, SR);
720 I915_WRITE(DSPFW1, reg);
721 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
722
723 /* cursor SR */
724 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
725 pineview_display_wm.fifo_size,
726 pixel_size, latency->cursor_sr);
727 reg = I915_READ(DSPFW3);
728 reg &= ~DSPFW_CURSOR_SR_MASK;
729 reg |= FW_WM(wm, CURSOR_SR);
730 I915_WRITE(DSPFW3, reg);
731
732 /* Display HPLL off SR */
733 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
734 pineview_display_hplloff_wm.fifo_size,
735 pixel_size, latency->display_hpll_disable);
736 reg = I915_READ(DSPFW3);
737 reg &= ~DSPFW_HPLL_SR_MASK;
738 reg |= FW_WM(wm, HPLL_SR);
739 I915_WRITE(DSPFW3, reg);
740
741 /* cursor HPLL off SR */
742 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
743 pineview_display_hplloff_wm.fifo_size,
744 pixel_size, latency->cursor_hpll_disable);
745 reg = I915_READ(DSPFW3);
746 reg &= ~DSPFW_HPLL_CURSOR_MASK;
747 reg |= FW_WM(wm, HPLL_CURSOR);
748 I915_WRITE(DSPFW3, reg);
749 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
750
751 intel_set_memory_cxsr(dev_priv, true);
752 } else {
753 intel_set_memory_cxsr(dev_priv, false);
754 }
755 }
756
757 static bool g4x_compute_wm0(struct drm_device *dev,
758 int plane,
759 const struct intel_watermark_params *display,
760 int display_latency_ns,
761 const struct intel_watermark_params *cursor,
762 int cursor_latency_ns,
763 int *plane_wm,
764 int *cursor_wm)
765 {
766 struct drm_crtc *crtc;
767 const struct drm_display_mode *adjusted_mode;
768 int htotal, hdisplay, clock, pixel_size;
769 int line_time_us, line_count;
770 int entries, tlb_miss;
771
772 crtc = intel_get_crtc_for_plane(dev, plane);
773 if (!intel_crtc_active(crtc)) {
774 *cursor_wm = cursor->guard_size;
775 *plane_wm = display->guard_size;
776 return false;
777 }
778
779 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
780 clock = adjusted_mode->crtc_clock;
781 htotal = adjusted_mode->crtc_htotal;
782 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
783 pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
784
785 /* Use the small buffer method to calculate plane watermark */
786 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
787 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
788 if (tlb_miss > 0)
789 entries += tlb_miss;
790 entries = DIV_ROUND_UP(entries, display->cacheline_size);
791 *plane_wm = entries + display->guard_size;
792 if (*plane_wm > (int)display->max_wm)
793 *plane_wm = display->max_wm;
794
795 /* Use the large buffer method to calculate cursor watermark */
796 line_time_us = max(htotal * 1000 / clock, 1);
797 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
798 entries = line_count * crtc->cursor->state->crtc_w * pixel_size;
799 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
800 if (tlb_miss > 0)
801 entries += tlb_miss;
802 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
803 *cursor_wm = entries + cursor->guard_size;
804 if (*cursor_wm > (int)cursor->max_wm)
805 *cursor_wm = (int)cursor->max_wm;
806
807 return true;
808 }
809
810 /*
811 * Check the wm result.
812 *
813 * If any calculated watermark values is larger than the maximum value that
814 * can be programmed into the associated watermark register, that watermark
815 * must be disabled.
816 */
817 static bool g4x_check_srwm(struct drm_device *dev,
818 int display_wm, int cursor_wm,
819 const struct intel_watermark_params *display,
820 const struct intel_watermark_params *cursor)
821 {
822 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
823 display_wm, cursor_wm);
824
825 if (display_wm > display->max_wm) {
826 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
827 display_wm, display->max_wm);
828 return false;
829 }
830
831 if (cursor_wm > cursor->max_wm) {
832 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
833 cursor_wm, cursor->max_wm);
834 return false;
835 }
836
837 if (!(display_wm || cursor_wm)) {
838 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
839 return false;
840 }
841
842 return true;
843 }
844
845 static bool g4x_compute_srwm(struct drm_device *dev,
846 int plane,
847 int latency_ns,
848 const struct intel_watermark_params *display,
849 const struct intel_watermark_params *cursor,
850 int *display_wm, int *cursor_wm)
851 {
852 struct drm_crtc *crtc;
853 const struct drm_display_mode *adjusted_mode;
854 int hdisplay, htotal, pixel_size, clock;
855 unsigned long line_time_us;
856 int line_count, line_size;
857 int small, large;
858 int entries;
859
860 if (!latency_ns) {
861 *display_wm = *cursor_wm = 0;
862 return false;
863 }
864
865 crtc = intel_get_crtc_for_plane(dev, plane);
866 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
867 clock = adjusted_mode->crtc_clock;
868 htotal = adjusted_mode->crtc_htotal;
869 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
870 pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
871
872 line_time_us = max(htotal * 1000 / clock, 1);
873 line_count = (latency_ns / line_time_us + 1000) / 1000;
874 line_size = hdisplay * pixel_size;
875
876 /* Use the minimum of the small and large buffer method for primary */
877 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
878 large = line_count * line_size;
879
880 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
881 *display_wm = entries + display->guard_size;
882
883 /* calculate the self-refresh watermark for display cursor */
884 entries = line_count * pixel_size * crtc->cursor->state->crtc_w;
885 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
886 *cursor_wm = entries + cursor->guard_size;
887
888 return g4x_check_srwm(dev,
889 *display_wm, *cursor_wm,
890 display, cursor);
891 }
892
893 #define FW_WM_VLV(value, plane) \
894 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
895
896 static void vlv_write_wm_values(struct intel_crtc *crtc,
897 const struct vlv_wm_values *wm)
898 {
899 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
900 enum pipe pipe = crtc->pipe;
901
902 I915_WRITE(VLV_DDL(pipe),
903 (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
904 (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
905 (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
906 (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
907
908 I915_WRITE(DSPFW1,
909 FW_WM(wm->sr.plane, SR) |
910 FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
911 FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
912 FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
913 I915_WRITE(DSPFW2,
914 FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
915 FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
916 FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
917 I915_WRITE(DSPFW3,
918 FW_WM(wm->sr.cursor, CURSOR_SR));
919
920 if (IS_CHERRYVIEW(dev_priv)) {
921 I915_WRITE(DSPFW7_CHV,
922 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
923 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
924 I915_WRITE(DSPFW8_CHV,
925 FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
926 FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
927 I915_WRITE(DSPFW9_CHV,
928 FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
929 FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
930 I915_WRITE(DSPHOWM,
931 FW_WM(wm->sr.plane >> 9, SR_HI) |
932 FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
933 FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
934 FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
935 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
936 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
937 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
938 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
939 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
940 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
941 } else {
942 I915_WRITE(DSPFW7,
943 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
944 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
945 I915_WRITE(DSPHOWM,
946 FW_WM(wm->sr.plane >> 9, SR_HI) |
947 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
948 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
949 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
950 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
951 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
952 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
953 }
954
955 /* zero (unused) WM1 watermarks */
956 I915_WRITE(DSPFW4, 0);
957 I915_WRITE(DSPFW5, 0);
958 I915_WRITE(DSPFW6, 0);
959 I915_WRITE(DSPHOWM1, 0);
960
961 POSTING_READ(DSPFW1);
962 }
963
964 #undef FW_WM_VLV
965
966 enum vlv_wm_level {
967 VLV_WM_LEVEL_PM2,
968 VLV_WM_LEVEL_PM5,
969 VLV_WM_LEVEL_DDR_DVFS,
970 CHV_WM_NUM_LEVELS,
971 VLV_WM_NUM_LEVELS = 1,
972 };
973
974 /* latency must be in 0.1us units. */
975 static unsigned int vlv_wm_method2(unsigned int pixel_rate,
976 unsigned int pipe_htotal,
977 unsigned int horiz_pixels,
978 unsigned int bytes_per_pixel,
979 unsigned int latency)
980 {
981 unsigned int ret;
982
983 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
984 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
985 ret = DIV_ROUND_UP(ret, 64);
986
987 return ret;
988 }
989
990 static void vlv_setup_wm_latency(struct drm_device *dev)
991 {
992 struct drm_i915_private *dev_priv = dev->dev_private;
993
994 /* all latencies in usec */
995 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
996
997 if (IS_CHERRYVIEW(dev_priv)) {
998 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
999 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
1000 }
1001 }
1002
1003 static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
1004 struct intel_crtc *crtc,
1005 const struct intel_plane_state *state,
1006 int level)
1007 {
1008 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1009 int clock, htotal, pixel_size, width, wm;
1010
1011 if (dev_priv->wm.pri_latency[level] == 0)
1012 return USHRT_MAX;
1013
1014 if (!state->visible)
1015 return 0;
1016
1017 pixel_size = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1018 clock = crtc->config->base.adjusted_mode.crtc_clock;
1019 htotal = crtc->config->base.adjusted_mode.crtc_htotal;
1020 width = crtc->config->pipe_src_w;
1021 if (WARN_ON(htotal == 0))
1022 htotal = 1;
1023
1024 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1025 /*
1026 * FIXME the formula gives values that are
1027 * too big for the cursor FIFO, and hence we
1028 * would never be able to use cursors. For
1029 * now just hardcode the watermark.
1030 */
1031 wm = 63;
1032 } else {
1033 wm = vlv_wm_method2(clock, htotal, width, pixel_size,
1034 dev_priv->wm.pri_latency[level] * 10);
1035 }
1036
1037 return min_t(int, wm, USHRT_MAX);
1038 }
1039
1040 static void vlv_compute_fifo(struct intel_crtc *crtc)
1041 {
1042 struct drm_device *dev = crtc->base.dev;
1043 struct vlv_wm_state *wm_state = &crtc->wm_state;
1044 struct intel_plane *plane;
1045 unsigned int total_rate = 0;
1046 const int fifo_size = 512 - 1;
1047 int fifo_extra, fifo_left = fifo_size;
1048
1049 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1050 struct intel_plane_state *state =
1051 to_intel_plane_state(plane->base.state);
1052
1053 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1054 continue;
1055
1056 if (state->visible) {
1057 wm_state->num_active_planes++;
1058 total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1059 }
1060 }
1061
1062 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1063 struct intel_plane_state *state =
1064 to_intel_plane_state(plane->base.state);
1065 unsigned int rate;
1066
1067 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1068 plane->wm.fifo_size = 63;
1069 continue;
1070 }
1071
1072 if (!state->visible) {
1073 plane->wm.fifo_size = 0;
1074 continue;
1075 }
1076
1077 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1078 plane->wm.fifo_size = fifo_size * rate / total_rate;
1079 fifo_left -= plane->wm.fifo_size;
1080 }
1081
1082 fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1083
1084 /* spread the remainder evenly */
1085 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1086 int plane_extra;
1087
1088 if (fifo_left == 0)
1089 break;
1090
1091 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1092 continue;
1093
1094 /* give it all to the first plane if none are active */
1095 if (plane->wm.fifo_size == 0 &&
1096 wm_state->num_active_planes)
1097 continue;
1098
1099 plane_extra = min(fifo_extra, fifo_left);
1100 plane->wm.fifo_size += plane_extra;
1101 fifo_left -= plane_extra;
1102 }
1103
1104 WARN_ON(fifo_left != 0);
1105 }
1106
1107 static void vlv_invert_wms(struct intel_crtc *crtc)
1108 {
1109 struct vlv_wm_state *wm_state = &crtc->wm_state;
1110 int level;
1111
1112 for (level = 0; level < wm_state->num_levels; level++) {
1113 struct drm_device *dev = crtc->base.dev;
1114 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1115 struct intel_plane *plane;
1116
1117 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1118 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1119
1120 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1121 switch (plane->base.type) {
1122 int sprite;
1123 case DRM_PLANE_TYPE_CURSOR:
1124 wm_state->wm[level].cursor = plane->wm.fifo_size -
1125 wm_state->wm[level].cursor;
1126 break;
1127 case DRM_PLANE_TYPE_PRIMARY:
1128 wm_state->wm[level].primary = plane->wm.fifo_size -
1129 wm_state->wm[level].primary;
1130 break;
1131 case DRM_PLANE_TYPE_OVERLAY:
1132 sprite = plane->plane;
1133 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1134 wm_state->wm[level].sprite[sprite];
1135 break;
1136 }
1137 }
1138 }
1139 }
1140
1141 static void vlv_compute_wm(struct intel_crtc *crtc)
1142 {
1143 struct drm_device *dev = crtc->base.dev;
1144 struct vlv_wm_state *wm_state = &crtc->wm_state;
1145 struct intel_plane *plane;
1146 int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1147 int level;
1148
1149 memset(wm_state, 0, sizeof(*wm_state));
1150
1151 wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
1152 if (IS_CHERRYVIEW(dev))
1153 wm_state->num_levels = CHV_WM_NUM_LEVELS;
1154 else
1155 wm_state->num_levels = VLV_WM_NUM_LEVELS;
1156
1157 wm_state->num_active_planes = 0;
1158
1159 vlv_compute_fifo(crtc);
1160
1161 if (wm_state->num_active_planes != 1)
1162 wm_state->cxsr = false;
1163
1164 if (wm_state->cxsr) {
1165 for (level = 0; level < wm_state->num_levels; level++) {
1166 wm_state->sr[level].plane = sr_fifo_size;
1167 wm_state->sr[level].cursor = 63;
1168 }
1169 }
1170
1171 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1172 struct intel_plane_state *state =
1173 to_intel_plane_state(plane->base.state);
1174
1175 if (!state->visible)
1176 continue;
1177
1178 /* normal watermarks */
1179 for (level = 0; level < wm_state->num_levels; level++) {
1180 int wm = vlv_compute_wm_level(plane, crtc, state, level);
1181 int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1182
1183 /* hack */
1184 if (WARN_ON(level == 0 && wm > max_wm))
1185 wm = max_wm;
1186
1187 if (wm > plane->wm.fifo_size)
1188 break;
1189
1190 switch (plane->base.type) {
1191 int sprite;
1192 case DRM_PLANE_TYPE_CURSOR:
1193 wm_state->wm[level].cursor = wm;
1194 break;
1195 case DRM_PLANE_TYPE_PRIMARY:
1196 wm_state->wm[level].primary = wm;
1197 break;
1198 case DRM_PLANE_TYPE_OVERLAY:
1199 sprite = plane->plane;
1200 wm_state->wm[level].sprite[sprite] = wm;
1201 break;
1202 }
1203 }
1204
1205 wm_state->num_levels = level;
1206
1207 if (!wm_state->cxsr)
1208 continue;
1209
1210 /* maxfifo watermarks */
1211 switch (plane->base.type) {
1212 int sprite, level;
1213 case DRM_PLANE_TYPE_CURSOR:
1214 for (level = 0; level < wm_state->num_levels; level++)
1215 wm_state->sr[level].cursor =
1216 wm_state->sr[level].cursor;
1217 break;
1218 case DRM_PLANE_TYPE_PRIMARY:
1219 for (level = 0; level < wm_state->num_levels; level++)
1220 wm_state->sr[level].plane =
1221 min(wm_state->sr[level].plane,
1222 wm_state->wm[level].primary);
1223 break;
1224 case DRM_PLANE_TYPE_OVERLAY:
1225 sprite = plane->plane;
1226 for (level = 0; level < wm_state->num_levels; level++)
1227 wm_state->sr[level].plane =
1228 min(wm_state->sr[level].plane,
1229 wm_state->wm[level].sprite[sprite]);
1230 break;
1231 }
1232 }
1233
1234 /* clear any (partially) filled invalid levels */
1235 for (level = wm_state->num_levels; level < CHV_WM_NUM_LEVELS; level++) {
1236 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1237 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1238 }
1239
1240 vlv_invert_wms(crtc);
1241 }
1242
1243 #define VLV_FIFO(plane, value) \
1244 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1245
1246 static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1247 {
1248 struct drm_device *dev = crtc->base.dev;
1249 struct drm_i915_private *dev_priv = to_i915(dev);
1250 struct intel_plane *plane;
1251 int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1252
1253 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1254 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1255 WARN_ON(plane->wm.fifo_size != 63);
1256 continue;
1257 }
1258
1259 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1260 sprite0_start = plane->wm.fifo_size;
1261 else if (plane->plane == 0)
1262 sprite1_start = sprite0_start + plane->wm.fifo_size;
1263 else
1264 fifo_size = sprite1_start + plane->wm.fifo_size;
1265 }
1266
1267 WARN_ON(fifo_size != 512 - 1);
1268
1269 DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1270 pipe_name(crtc->pipe), sprite0_start,
1271 sprite1_start, fifo_size);
1272
1273 switch (crtc->pipe) {
1274 uint32_t dsparb, dsparb2, dsparb3;
1275 case PIPE_A:
1276 dsparb = I915_READ(DSPARB);
1277 dsparb2 = I915_READ(DSPARB2);
1278
1279 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1280 VLV_FIFO(SPRITEB, 0xff));
1281 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1282 VLV_FIFO(SPRITEB, sprite1_start));
1283
1284 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1285 VLV_FIFO(SPRITEB_HI, 0x1));
1286 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1287 VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1288
1289 I915_WRITE(DSPARB, dsparb);
1290 I915_WRITE(DSPARB2, dsparb2);
1291 break;
1292 case PIPE_B:
1293 dsparb = I915_READ(DSPARB);
1294 dsparb2 = I915_READ(DSPARB2);
1295
1296 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1297 VLV_FIFO(SPRITED, 0xff));
1298 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1299 VLV_FIFO(SPRITED, sprite1_start));
1300
1301 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1302 VLV_FIFO(SPRITED_HI, 0xff));
1303 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1304 VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1305
1306 I915_WRITE(DSPARB, dsparb);
1307 I915_WRITE(DSPARB2, dsparb2);
1308 break;
1309 case PIPE_C:
1310 dsparb3 = I915_READ(DSPARB3);
1311 dsparb2 = I915_READ(DSPARB2);
1312
1313 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1314 VLV_FIFO(SPRITEF, 0xff));
1315 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1316 VLV_FIFO(SPRITEF, sprite1_start));
1317
1318 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1319 VLV_FIFO(SPRITEF_HI, 0xff));
1320 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1321 VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1322
1323 I915_WRITE(DSPARB3, dsparb3);
1324 I915_WRITE(DSPARB2, dsparb2);
1325 break;
1326 default:
1327 break;
1328 }
1329 }
1330
1331 #undef VLV_FIFO
1332
1333 static void vlv_merge_wm(struct drm_device *dev,
1334 struct vlv_wm_values *wm)
1335 {
1336 struct intel_crtc *crtc;
1337 int num_active_crtcs = 0;
1338
1339 if (IS_CHERRYVIEW(dev))
1340 wm->level = VLV_WM_LEVEL_DDR_DVFS;
1341 else
1342 wm->level = VLV_WM_LEVEL_PM2;
1343 wm->cxsr = true;
1344
1345 for_each_intel_crtc(dev, crtc) {
1346 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1347
1348 if (!crtc->active)
1349 continue;
1350
1351 if (!wm_state->cxsr)
1352 wm->cxsr = false;
1353
1354 num_active_crtcs++;
1355 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1356 }
1357
1358 if (num_active_crtcs != 1)
1359 wm->cxsr = false;
1360
1361 if (num_active_crtcs > 1)
1362 wm->level = VLV_WM_LEVEL_PM2;
1363
1364 for_each_intel_crtc(dev, crtc) {
1365 struct vlv_wm_state *wm_state = &crtc->wm_state;
1366 enum pipe pipe = crtc->pipe;
1367
1368 if (!crtc->active)
1369 continue;
1370
1371 wm->pipe[pipe] = wm_state->wm[wm->level];
1372 if (wm->cxsr)
1373 wm->sr = wm_state->sr[wm->level];
1374
1375 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1376 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1377 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1378 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1379 }
1380 }
1381
1382 static void vlv_update_wm(struct drm_crtc *crtc)
1383 {
1384 struct drm_device *dev = crtc->dev;
1385 struct drm_i915_private *dev_priv = dev->dev_private;
1386 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1387 enum pipe pipe = intel_crtc->pipe;
1388 struct vlv_wm_values wm = {};
1389
1390 vlv_compute_wm(intel_crtc);
1391 vlv_merge_wm(dev, &wm);
1392
1393 if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1394 /* FIXME should be part of crtc atomic commit */
1395 vlv_pipe_set_fifo_size(intel_crtc);
1396 return;
1397 }
1398
1399 if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1400 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1401 chv_set_memory_dvfs(dev_priv, false);
1402
1403 if (wm.level < VLV_WM_LEVEL_PM5 &&
1404 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1405 chv_set_memory_pm5(dev_priv, false);
1406
1407 if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
1408 intel_set_memory_cxsr(dev_priv, false);
1409
1410 /* FIXME should be part of crtc atomic commit */
1411 vlv_pipe_set_fifo_size(intel_crtc);
1412
1413 vlv_write_wm_values(intel_crtc, &wm);
1414
1415 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1416 "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1417 pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1418 wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1419 wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1420
1421 if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
1422 intel_set_memory_cxsr(dev_priv, true);
1423
1424 if (wm.level >= VLV_WM_LEVEL_PM5 &&
1425 dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1426 chv_set_memory_pm5(dev_priv, true);
1427
1428 if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1429 dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1430 chv_set_memory_dvfs(dev_priv, true);
1431
1432 dev_priv->wm.vlv = wm;
1433 }
1434
1435 #define single_plane_enabled(mask) is_power_of_2(mask)
1436
1437 static void g4x_update_wm(struct drm_crtc *crtc)
1438 {
1439 struct drm_device *dev = crtc->dev;
1440 static const int sr_latency_ns = 12000;
1441 struct drm_i915_private *dev_priv = dev->dev_private;
1442 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1443 int plane_sr, cursor_sr;
1444 unsigned int enabled = 0;
1445 bool cxsr_enabled;
1446
1447 if (g4x_compute_wm0(dev, PIPE_A,
1448 &g4x_wm_info, pessimal_latency_ns,
1449 &g4x_cursor_wm_info, pessimal_latency_ns,
1450 &planea_wm, &cursora_wm))
1451 enabled |= 1 << PIPE_A;
1452
1453 if (g4x_compute_wm0(dev, PIPE_B,
1454 &g4x_wm_info, pessimal_latency_ns,
1455 &g4x_cursor_wm_info, pessimal_latency_ns,
1456 &planeb_wm, &cursorb_wm))
1457 enabled |= 1 << PIPE_B;
1458
1459 if (single_plane_enabled(enabled) &&
1460 g4x_compute_srwm(dev, ffs(enabled) - 1,
1461 sr_latency_ns,
1462 &g4x_wm_info,
1463 &g4x_cursor_wm_info,
1464 &plane_sr, &cursor_sr)) {
1465 cxsr_enabled = true;
1466 } else {
1467 cxsr_enabled = false;
1468 intel_set_memory_cxsr(dev_priv, false);
1469 plane_sr = cursor_sr = 0;
1470 }
1471
1472 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1473 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1474 planea_wm, cursora_wm,
1475 planeb_wm, cursorb_wm,
1476 plane_sr, cursor_sr);
1477
1478 I915_WRITE(DSPFW1,
1479 FW_WM(plane_sr, SR) |
1480 FW_WM(cursorb_wm, CURSORB) |
1481 FW_WM(planeb_wm, PLANEB) |
1482 FW_WM(planea_wm, PLANEA));
1483 I915_WRITE(DSPFW2,
1484 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1485 FW_WM(cursora_wm, CURSORA));
1486 /* HPLL off in SR has some issues on G4x... disable it */
1487 I915_WRITE(DSPFW3,
1488 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1489 FW_WM(cursor_sr, CURSOR_SR));
1490
1491 if (cxsr_enabled)
1492 intel_set_memory_cxsr(dev_priv, true);
1493 }
1494
1495 static void i965_update_wm(struct drm_crtc *unused_crtc)
1496 {
1497 struct drm_device *dev = unused_crtc->dev;
1498 struct drm_i915_private *dev_priv = dev->dev_private;
1499 struct drm_crtc *crtc;
1500 int srwm = 1;
1501 int cursor_sr = 16;
1502 bool cxsr_enabled;
1503
1504 /* Calc sr entries for one plane configs */
1505 crtc = single_enabled_crtc(dev);
1506 if (crtc) {
1507 /* self-refresh has much higher latency */
1508 static const int sr_latency_ns = 12000;
1509 const struct drm_display_mode *adjusted_mode =
1510 &to_intel_crtc(crtc)->config->base.adjusted_mode;
1511 int clock = adjusted_mode->crtc_clock;
1512 int htotal = adjusted_mode->crtc_htotal;
1513 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
1514 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
1515 unsigned long line_time_us;
1516 int entries;
1517
1518 line_time_us = max(htotal * 1000 / clock, 1);
1519
1520 /* Use ns/us then divide to preserve precision */
1521 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1522 pixel_size * hdisplay;
1523 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1524 srwm = I965_FIFO_SIZE - entries;
1525 if (srwm < 0)
1526 srwm = 1;
1527 srwm &= 0x1ff;
1528 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1529 entries, srwm);
1530
1531 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1532 pixel_size * crtc->cursor->state->crtc_w;
1533 entries = DIV_ROUND_UP(entries,
1534 i965_cursor_wm_info.cacheline_size);
1535 cursor_sr = i965_cursor_wm_info.fifo_size -
1536 (entries + i965_cursor_wm_info.guard_size);
1537
1538 if (cursor_sr > i965_cursor_wm_info.max_wm)
1539 cursor_sr = i965_cursor_wm_info.max_wm;
1540
1541 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1542 "cursor %d\n", srwm, cursor_sr);
1543
1544 cxsr_enabled = true;
1545 } else {
1546 cxsr_enabled = false;
1547 /* Turn off self refresh if both pipes are enabled */
1548 intel_set_memory_cxsr(dev_priv, false);
1549 }
1550
1551 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1552 srwm);
1553
1554 /* 965 has limitations... */
1555 I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1556 FW_WM(8, CURSORB) |
1557 FW_WM(8, PLANEB) |
1558 FW_WM(8, PLANEA));
1559 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1560 FW_WM(8, PLANEC_OLD));
1561 /* update cursor SR watermark */
1562 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
1563
1564 if (cxsr_enabled)
1565 intel_set_memory_cxsr(dev_priv, true);
1566 }
1567
1568 #undef FW_WM
1569
1570 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1571 {
1572 struct drm_device *dev = unused_crtc->dev;
1573 struct drm_i915_private *dev_priv = dev->dev_private;
1574 const struct intel_watermark_params *wm_info;
1575 uint32_t fwater_lo;
1576 uint32_t fwater_hi;
1577 int cwm, srwm = 1;
1578 int fifo_size;
1579 int planea_wm, planeb_wm;
1580 struct drm_crtc *crtc, *enabled = NULL;
1581
1582 if (IS_I945GM(dev))
1583 wm_info = &i945_wm_info;
1584 else if (!IS_GEN2(dev))
1585 wm_info = &i915_wm_info;
1586 else
1587 wm_info = &i830_a_wm_info;
1588
1589 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1590 crtc = intel_get_crtc_for_plane(dev, 0);
1591 if (intel_crtc_active(crtc)) {
1592 const struct drm_display_mode *adjusted_mode;
1593 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
1594 if (IS_GEN2(dev))
1595 cpp = 4;
1596
1597 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1598 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1599 wm_info, fifo_size, cpp,
1600 pessimal_latency_ns);
1601 enabled = crtc;
1602 } else {
1603 planea_wm = fifo_size - wm_info->guard_size;
1604 if (planea_wm > (long)wm_info->max_wm)
1605 planea_wm = wm_info->max_wm;
1606 }
1607
1608 if (IS_GEN2(dev))
1609 wm_info = &i830_bc_wm_info;
1610
1611 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1612 crtc = intel_get_crtc_for_plane(dev, 1);
1613 if (intel_crtc_active(crtc)) {
1614 const struct drm_display_mode *adjusted_mode;
1615 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
1616 if (IS_GEN2(dev))
1617 cpp = 4;
1618
1619 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1620 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1621 wm_info, fifo_size, cpp,
1622 pessimal_latency_ns);
1623 if (enabled == NULL)
1624 enabled = crtc;
1625 else
1626 enabled = NULL;
1627 } else {
1628 planeb_wm = fifo_size - wm_info->guard_size;
1629 if (planeb_wm > (long)wm_info->max_wm)
1630 planeb_wm = wm_info->max_wm;
1631 }
1632
1633 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1634
1635 if (IS_I915GM(dev) && enabled) {
1636 struct drm_i915_gem_object *obj;
1637
1638 obj = intel_fb_obj(enabled->primary->state->fb);
1639
1640 /* self-refresh seems busted with untiled */
1641 if (obj->tiling_mode == I915_TILING_NONE)
1642 enabled = NULL;
1643 }
1644
1645 /*
1646 * Overlay gets an aggressive default since video jitter is bad.
1647 */
1648 cwm = 2;
1649
1650 /* Play safe and disable self-refresh before adjusting watermarks. */
1651 intel_set_memory_cxsr(dev_priv, false);
1652
1653 /* Calc sr entries for one plane configs */
1654 if (HAS_FW_BLC(dev) && enabled) {
1655 /* self-refresh has much higher latency */
1656 static const int sr_latency_ns = 6000;
1657 const struct drm_display_mode *adjusted_mode =
1658 &to_intel_crtc(enabled)->config->base.adjusted_mode;
1659 int clock = adjusted_mode->crtc_clock;
1660 int htotal = adjusted_mode->crtc_htotal;
1661 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
1662 int pixel_size = enabled->primary->state->fb->bits_per_pixel / 8;
1663 unsigned long line_time_us;
1664 int entries;
1665
1666 line_time_us = max(htotal * 1000 / clock, 1);
1667
1668 /* Use ns/us then divide to preserve precision */
1669 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1670 pixel_size * hdisplay;
1671 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1672 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1673 srwm = wm_info->fifo_size - entries;
1674 if (srwm < 0)
1675 srwm = 1;
1676
1677 if (IS_I945G(dev) || IS_I945GM(dev))
1678 I915_WRITE(FW_BLC_SELF,
1679 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1680 else if (IS_I915GM(dev))
1681 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1682 }
1683
1684 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1685 planea_wm, planeb_wm, cwm, srwm);
1686
1687 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1688 fwater_hi = (cwm & 0x1f);
1689
1690 /* Set request length to 8 cachelines per fetch */
1691 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1692 fwater_hi = fwater_hi | (1 << 8);
1693
1694 I915_WRITE(FW_BLC, fwater_lo);
1695 I915_WRITE(FW_BLC2, fwater_hi);
1696
1697 if (enabled)
1698 intel_set_memory_cxsr(dev_priv, true);
1699 }
1700
1701 static void i845_update_wm(struct drm_crtc *unused_crtc)
1702 {
1703 struct drm_device *dev = unused_crtc->dev;
1704 struct drm_i915_private *dev_priv = dev->dev_private;
1705 struct drm_crtc *crtc;
1706 const struct drm_display_mode *adjusted_mode;
1707 uint32_t fwater_lo;
1708 int planea_wm;
1709
1710 crtc = single_enabled_crtc(dev);
1711 if (crtc == NULL)
1712 return;
1713
1714 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1715 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1716 &i845_wm_info,
1717 dev_priv->display.get_fifo_size(dev, 0),
1718 4, pessimal_latency_ns);
1719 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1720 fwater_lo |= (3<<8) | planea_wm;
1721
1722 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1723
1724 I915_WRITE(FW_BLC, fwater_lo);
1725 }
1726
1727 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
1728 {
1729 uint32_t pixel_rate;
1730
1731 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
1732
1733 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1734 * adjust the pixel_rate here. */
1735
1736 if (pipe_config->pch_pfit.enabled) {
1737 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1738 uint32_t pfit_size = pipe_config->pch_pfit.size;
1739
1740 pipe_w = pipe_config->pipe_src_w;
1741 pipe_h = pipe_config->pipe_src_h;
1742
1743 pfit_w = (pfit_size >> 16) & 0xFFFF;
1744 pfit_h = pfit_size & 0xFFFF;
1745 if (pipe_w < pfit_w)
1746 pipe_w = pfit_w;
1747 if (pipe_h < pfit_h)
1748 pipe_h = pfit_h;
1749
1750 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1751 pfit_w * pfit_h);
1752 }
1753
1754 return pixel_rate;
1755 }
1756
1757 /* latency must be in 0.1us units. */
1758 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
1759 uint32_t latency)
1760 {
1761 uint64_t ret;
1762
1763 if (WARN(latency == 0, "Latency value missing\n"))
1764 return UINT_MAX;
1765
1766 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1767 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1768
1769 return ret;
1770 }
1771
1772 /* latency must be in 0.1us units. */
1773 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1774 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1775 uint32_t latency)
1776 {
1777 uint32_t ret;
1778
1779 if (WARN(latency == 0, "Latency value missing\n"))
1780 return UINT_MAX;
1781
1782 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1783 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1784 ret = DIV_ROUND_UP(ret, 64) + 2;
1785 return ret;
1786 }
1787
1788 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1789 uint8_t bytes_per_pixel)
1790 {
1791 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1792 }
1793
1794 struct skl_pipe_wm_parameters {
1795 bool active;
1796 uint32_t pipe_htotal;
1797 uint32_t pixel_rate; /* in KHz */
1798 struct intel_plane_wm_parameters plane[I915_MAX_PLANES];
1799 struct intel_plane_wm_parameters cursor;
1800 };
1801
1802 struct ilk_pipe_wm_parameters {
1803 bool active;
1804 uint32_t pipe_htotal;
1805 uint32_t pixel_rate;
1806 struct intel_plane_wm_parameters pri;
1807 struct intel_plane_wm_parameters spr;
1808 struct intel_plane_wm_parameters cur;
1809 };
1810
1811 struct ilk_wm_maximums {
1812 uint16_t pri;
1813 uint16_t spr;
1814 uint16_t cur;
1815 uint16_t fbc;
1816 };
1817
1818 /* used in computing the new watermarks state */
1819 struct intel_wm_config {
1820 unsigned int num_pipes_active;
1821 bool sprites_enabled;
1822 bool sprites_scaled;
1823 };
1824
1825 /*
1826 * For both WM_PIPE and WM_LP.
1827 * mem_value must be in 0.1us units.
1828 */
1829 static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params,
1830 uint32_t mem_value,
1831 bool is_lp)
1832 {
1833 uint32_t method1, method2;
1834
1835 if (!params->active || !params->pri.enabled)
1836 return 0;
1837
1838 method1 = ilk_wm_method1(params->pixel_rate,
1839 params->pri.bytes_per_pixel,
1840 mem_value);
1841
1842 if (!is_lp)
1843 return method1;
1844
1845 method2 = ilk_wm_method2(params->pixel_rate,
1846 params->pipe_htotal,
1847 params->pri.horiz_pixels,
1848 params->pri.bytes_per_pixel,
1849 mem_value);
1850
1851 return min(method1, method2);
1852 }
1853
1854 /*
1855 * For both WM_PIPE and WM_LP.
1856 * mem_value must be in 0.1us units.
1857 */
1858 static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params,
1859 uint32_t mem_value)
1860 {
1861 uint32_t method1, method2;
1862
1863 if (!params->active || !params->spr.enabled)
1864 return 0;
1865
1866 method1 = ilk_wm_method1(params->pixel_rate,
1867 params->spr.bytes_per_pixel,
1868 mem_value);
1869 method2 = ilk_wm_method2(params->pixel_rate,
1870 params->pipe_htotal,
1871 params->spr.horiz_pixels,
1872 params->spr.bytes_per_pixel,
1873 mem_value);
1874 return min(method1, method2);
1875 }
1876
1877 /*
1878 * For both WM_PIPE and WM_LP.
1879 * mem_value must be in 0.1us units.
1880 */
1881 static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params,
1882 uint32_t mem_value)
1883 {
1884 if (!params->active || !params->cur.enabled)
1885 return 0;
1886
1887 return ilk_wm_method2(params->pixel_rate,
1888 params->pipe_htotal,
1889 params->cur.horiz_pixels,
1890 params->cur.bytes_per_pixel,
1891 mem_value);
1892 }
1893
1894 /* Only for WM_LP. */
1895 static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params,
1896 uint32_t pri_val)
1897 {
1898 if (!params->active || !params->pri.enabled)
1899 return 0;
1900
1901 return ilk_wm_fbc(pri_val,
1902 params->pri.horiz_pixels,
1903 params->pri.bytes_per_pixel);
1904 }
1905
1906 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1907 {
1908 if (INTEL_INFO(dev)->gen >= 8)
1909 return 3072;
1910 else if (INTEL_INFO(dev)->gen >= 7)
1911 return 768;
1912 else
1913 return 512;
1914 }
1915
1916 static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1917 int level, bool is_sprite)
1918 {
1919 if (INTEL_INFO(dev)->gen >= 8)
1920 /* BDW primary/sprite plane watermarks */
1921 return level == 0 ? 255 : 2047;
1922 else if (INTEL_INFO(dev)->gen >= 7)
1923 /* IVB/HSW primary/sprite plane watermarks */
1924 return level == 0 ? 127 : 1023;
1925 else if (!is_sprite)
1926 /* ILK/SNB primary plane watermarks */
1927 return level == 0 ? 127 : 511;
1928 else
1929 /* ILK/SNB sprite plane watermarks */
1930 return level == 0 ? 63 : 255;
1931 }
1932
1933 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1934 int level)
1935 {
1936 if (INTEL_INFO(dev)->gen >= 7)
1937 return level == 0 ? 63 : 255;
1938 else
1939 return level == 0 ? 31 : 63;
1940 }
1941
1942 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1943 {
1944 if (INTEL_INFO(dev)->gen >= 8)
1945 return 31;
1946 else
1947 return 15;
1948 }
1949
1950 /* Calculate the maximum primary/sprite plane watermark */
1951 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1952 int level,
1953 const struct intel_wm_config *config,
1954 enum intel_ddb_partitioning ddb_partitioning,
1955 bool is_sprite)
1956 {
1957 unsigned int fifo_size = ilk_display_fifo_size(dev);
1958
1959 /* if sprites aren't enabled, sprites get nothing */
1960 if (is_sprite && !config->sprites_enabled)
1961 return 0;
1962
1963 /* HSW allows LP1+ watermarks even with multiple pipes */
1964 if (level == 0 || config->num_pipes_active > 1) {
1965 fifo_size /= INTEL_INFO(dev)->num_pipes;
1966
1967 /*
1968 * For some reason the non self refresh
1969 * FIFO size is only half of the self
1970 * refresh FIFO size on ILK/SNB.
1971 */
1972 if (INTEL_INFO(dev)->gen <= 6)
1973 fifo_size /= 2;
1974 }
1975
1976 if (config->sprites_enabled) {
1977 /* level 0 is always calculated with 1:1 split */
1978 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1979 if (is_sprite)
1980 fifo_size *= 5;
1981 fifo_size /= 6;
1982 } else {
1983 fifo_size /= 2;
1984 }
1985 }
1986
1987 /* clamp to max that the registers can hold */
1988 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
1989 }
1990
1991 /* Calculate the maximum cursor plane watermark */
1992 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
1993 int level,
1994 const struct intel_wm_config *config)
1995 {
1996 /* HSW LP1+ watermarks w/ multiple pipes */
1997 if (level > 0 && config->num_pipes_active > 1)
1998 return 64;
1999
2000 /* otherwise just report max that registers can hold */
2001 return ilk_cursor_wm_reg_max(dev, level);
2002 }
2003
2004 static void ilk_compute_wm_maximums(const struct drm_device *dev,
2005 int level,
2006 const struct intel_wm_config *config,
2007 enum intel_ddb_partitioning ddb_partitioning,
2008 struct ilk_wm_maximums *max)
2009 {
2010 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
2011 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
2012 max->cur = ilk_cursor_wm_max(dev, level, config);
2013 max->fbc = ilk_fbc_wm_reg_max(dev);
2014 }
2015
2016 static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
2017 int level,
2018 struct ilk_wm_maximums *max)
2019 {
2020 max->pri = ilk_plane_wm_reg_max(dev, level, false);
2021 max->spr = ilk_plane_wm_reg_max(dev, level, true);
2022 max->cur = ilk_cursor_wm_reg_max(dev, level);
2023 max->fbc = ilk_fbc_wm_reg_max(dev);
2024 }
2025
2026 static bool ilk_validate_wm_level(int level,
2027 const struct ilk_wm_maximums *max,
2028 struct intel_wm_level *result)
2029 {
2030 bool ret;
2031
2032 /* already determined to be invalid? */
2033 if (!result->enable)
2034 return false;
2035
2036 result->enable = result->pri_val <= max->pri &&
2037 result->spr_val <= max->spr &&
2038 result->cur_val <= max->cur;
2039
2040 ret = result->enable;
2041
2042 /*
2043 * HACK until we can pre-compute everything,
2044 * and thus fail gracefully if LP0 watermarks
2045 * are exceeded...
2046 */
2047 if (level == 0 && !result->enable) {
2048 if (result->pri_val > max->pri)
2049 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2050 level, result->pri_val, max->pri);
2051 if (result->spr_val > max->spr)
2052 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2053 level, result->spr_val, max->spr);
2054 if (result->cur_val > max->cur)
2055 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2056 level, result->cur_val, max->cur);
2057
2058 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2059 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2060 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2061 result->enable = true;
2062 }
2063
2064 return ret;
2065 }
2066
2067 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
2068 int level,
2069 const struct ilk_pipe_wm_parameters *p,
2070 struct intel_wm_level *result)
2071 {
2072 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2073 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2074 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2075
2076 /* WM1+ latency values stored in 0.5us units */
2077 if (level > 0) {
2078 pri_latency *= 5;
2079 spr_latency *= 5;
2080 cur_latency *= 5;
2081 }
2082
2083 result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
2084 result->spr_val = ilk_compute_spr_wm(p, spr_latency);
2085 result->cur_val = ilk_compute_cur_wm(p, cur_latency);
2086 result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
2087 result->enable = true;
2088 }
2089
2090 static uint32_t
2091 hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
2092 {
2093 struct drm_i915_private *dev_priv = dev->dev_private;
2094 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2095 struct drm_display_mode *mode = &intel_crtc->config->base.adjusted_mode;
2096 u32 linetime, ips_linetime;
2097
2098 if (!intel_crtc->active)
2099 return 0;
2100
2101 /* The WM are computed with base on how long it takes to fill a single
2102 * row at the given clock rate, multiplied by 8.
2103 * */
2104 linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
2105 mode->crtc_clock);
2106 ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
2107 dev_priv->cdclk_freq);
2108
2109 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2110 PIPE_WM_LINETIME_TIME(linetime);
2111 }
2112
2113 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
2114 {
2115 struct drm_i915_private *dev_priv = dev->dev_private;
2116
2117 if (IS_GEN9(dev)) {
2118 uint32_t val;
2119 int ret, i;
2120 int level, max_level = ilk_wm_max_level(dev);
2121
2122 /* read the first set of memory latencies[0:3] */
2123 val = 0; /* data0 to be programmed to 0 for first set */
2124 mutex_lock(&dev_priv->rps.hw_lock);
2125 ret = sandybridge_pcode_read(dev_priv,
2126 GEN9_PCODE_READ_MEM_LATENCY,
2127 &val);
2128 mutex_unlock(&dev_priv->rps.hw_lock);
2129
2130 if (ret) {
2131 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2132 return;
2133 }
2134
2135 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2136 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2137 GEN9_MEM_LATENCY_LEVEL_MASK;
2138 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2139 GEN9_MEM_LATENCY_LEVEL_MASK;
2140 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2141 GEN9_MEM_LATENCY_LEVEL_MASK;
2142
2143 /* read the second set of memory latencies[4:7] */
2144 val = 1; /* data0 to be programmed to 1 for second set */
2145 mutex_lock(&dev_priv->rps.hw_lock);
2146 ret = sandybridge_pcode_read(dev_priv,
2147 GEN9_PCODE_READ_MEM_LATENCY,
2148 &val);
2149 mutex_unlock(&dev_priv->rps.hw_lock);
2150 if (ret) {
2151 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2152 return;
2153 }
2154
2155 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2156 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2157 GEN9_MEM_LATENCY_LEVEL_MASK;
2158 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2159 GEN9_MEM_LATENCY_LEVEL_MASK;
2160 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2161 GEN9_MEM_LATENCY_LEVEL_MASK;
2162
2163 /*
2164 * WaWmMemoryReadLatency:skl
2165 *
2166 * punit doesn't take into account the read latency so we need
2167 * to add 2us to the various latency levels we retrieve from
2168 * the punit.
2169 * - W0 is a bit special in that it's the only level that
2170 * can't be disabled if we want to have display working, so
2171 * we always add 2us there.
2172 * - For levels >=1, punit returns 0us latency when they are
2173 * disabled, so we respect that and don't add 2us then
2174 *
2175 * Additionally, if a level n (n > 1) has a 0us latency, all
2176 * levels m (m >= n) need to be disabled. We make sure to
2177 * sanitize the values out of the punit to satisfy this
2178 * requirement.
2179 */
2180 wm[0] += 2;
2181 for (level = 1; level <= max_level; level++)
2182 if (wm[level] != 0)
2183 wm[level] += 2;
2184 else {
2185 for (i = level + 1; i <= max_level; i++)
2186 wm[i] = 0;
2187
2188 break;
2189 }
2190 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2191 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2192
2193 wm[0] = (sskpd >> 56) & 0xFF;
2194 if (wm[0] == 0)
2195 wm[0] = sskpd & 0xF;
2196 wm[1] = (sskpd >> 4) & 0xFF;
2197 wm[2] = (sskpd >> 12) & 0xFF;
2198 wm[3] = (sskpd >> 20) & 0x1FF;
2199 wm[4] = (sskpd >> 32) & 0x1FF;
2200 } else if (INTEL_INFO(dev)->gen >= 6) {
2201 uint32_t sskpd = I915_READ(MCH_SSKPD);
2202
2203 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2204 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2205 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2206 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2207 } else if (INTEL_INFO(dev)->gen >= 5) {
2208 uint32_t mltr = I915_READ(MLTR_ILK);
2209
2210 /* ILK primary LP0 latency is 700 ns */
2211 wm[0] = 7;
2212 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2213 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2214 }
2215 }
2216
2217 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2218 {
2219 /* ILK sprite LP0 latency is 1300 ns */
2220 if (INTEL_INFO(dev)->gen == 5)
2221 wm[0] = 13;
2222 }
2223
2224 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2225 {
2226 /* ILK cursor LP0 latency is 1300 ns */
2227 if (INTEL_INFO(dev)->gen == 5)
2228 wm[0] = 13;
2229
2230 /* WaDoubleCursorLP3Latency:ivb */
2231 if (IS_IVYBRIDGE(dev))
2232 wm[3] *= 2;
2233 }
2234
2235 int ilk_wm_max_level(const struct drm_device *dev)
2236 {
2237 /* how many WM levels are we expecting */
2238 if (INTEL_INFO(dev)->gen >= 9)
2239 return 7;
2240 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2241 return 4;
2242 else if (INTEL_INFO(dev)->gen >= 6)
2243 return 3;
2244 else
2245 return 2;
2246 }
2247
2248 static void intel_print_wm_latency(struct drm_device *dev,
2249 const char *name,
2250 const uint16_t wm[8])
2251 {
2252 int level, max_level = ilk_wm_max_level(dev);
2253
2254 for (level = 0; level <= max_level; level++) {
2255 unsigned int latency = wm[level];
2256
2257 if (latency == 0) {
2258 DRM_ERROR("%s WM%d latency not provided\n",
2259 name, level);
2260 continue;
2261 }
2262
2263 /*
2264 * - latencies are in us on gen9.
2265 * - before then, WM1+ latency values are in 0.5us units
2266 */
2267 if (IS_GEN9(dev))
2268 latency *= 10;
2269 else if (level > 0)
2270 latency *= 5;
2271
2272 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2273 name, level, wm[level],
2274 latency / 10, latency % 10);
2275 }
2276 }
2277
2278 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2279 uint16_t wm[5], uint16_t min)
2280 {
2281 int level, max_level = ilk_wm_max_level(dev_priv->dev);
2282
2283 if (wm[0] >= min)
2284 return false;
2285
2286 wm[0] = max(wm[0], min);
2287 for (level = 1; level <= max_level; level++)
2288 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2289
2290 return true;
2291 }
2292
2293 static void snb_wm_latency_quirk(struct drm_device *dev)
2294 {
2295 struct drm_i915_private *dev_priv = dev->dev_private;
2296 bool changed;
2297
2298 /*
2299 * The BIOS provided WM memory latency values are often
2300 * inadequate for high resolution displays. Adjust them.
2301 */
2302 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2303 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2304 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2305
2306 if (!changed)
2307 return;
2308
2309 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2310 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2311 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2312 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2313 }
2314
2315 static void ilk_setup_wm_latency(struct drm_device *dev)
2316 {
2317 struct drm_i915_private *dev_priv = dev->dev_private;
2318
2319 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2320
2321 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2322 sizeof(dev_priv->wm.pri_latency));
2323 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2324 sizeof(dev_priv->wm.pri_latency));
2325
2326 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2327 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2328
2329 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2330 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2331 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2332
2333 if (IS_GEN6(dev))
2334 snb_wm_latency_quirk(dev);
2335 }
2336
2337 static void skl_setup_wm_latency(struct drm_device *dev)
2338 {
2339 struct drm_i915_private *dev_priv = dev->dev_private;
2340
2341 intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2342 intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2343 }
2344
2345 static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
2346 struct ilk_pipe_wm_parameters *p)
2347 {
2348 struct drm_device *dev = crtc->dev;
2349 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2350 enum pipe pipe = intel_crtc->pipe;
2351 struct drm_plane *plane;
2352
2353 if (!intel_crtc->active)
2354 return;
2355
2356 p->active = true;
2357 p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;
2358 p->pixel_rate = ilk_pipe_pixel_rate(intel_crtc->config);
2359
2360 if (crtc->primary->state->fb)
2361 p->pri.bytes_per_pixel =
2362 crtc->primary->state->fb->bits_per_pixel / 8;
2363 else
2364 p->pri.bytes_per_pixel = 4;
2365
2366 p->cur.bytes_per_pixel = 4;
2367 /*
2368 * TODO: for now, assume primary and cursor planes are always enabled.
2369 * Setting them to false makes the screen flicker.
2370 */
2371 p->pri.enabled = true;
2372 p->cur.enabled = true;
2373
2374 p->pri.horiz_pixels = intel_crtc->config->pipe_src_w;
2375 p->cur.horiz_pixels = intel_crtc->base.cursor->state->crtc_w;
2376
2377 drm_for_each_legacy_plane(plane, dev) {
2378 struct intel_plane *intel_plane = to_intel_plane(plane);
2379
2380 if (intel_plane->pipe == pipe) {
2381 p->spr = intel_plane->wm;
2382 break;
2383 }
2384 }
2385 }
2386
2387 static void ilk_compute_wm_config(struct drm_device *dev,
2388 struct intel_wm_config *config)
2389 {
2390 struct intel_crtc *intel_crtc;
2391
2392 /* Compute the currently _active_ config */
2393 for_each_intel_crtc(dev, intel_crtc) {
2394 const struct intel_pipe_wm *wm = &intel_crtc->wm.active;
2395
2396 if (!wm->pipe_enabled)
2397 continue;
2398
2399 config->sprites_enabled |= wm->sprites_enabled;
2400 config->sprites_scaled |= wm->sprites_scaled;
2401 config->num_pipes_active++;
2402 }
2403 }
2404
2405 /* Compute new watermarks for the pipe */
2406 static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
2407 const struct ilk_pipe_wm_parameters *params,
2408 struct intel_pipe_wm *pipe_wm)
2409 {
2410 struct drm_device *dev = crtc->dev;
2411 const struct drm_i915_private *dev_priv = dev->dev_private;
2412 int level, max_level = ilk_wm_max_level(dev);
2413 /* LP0 watermark maximums depend on this pipe alone */
2414 struct intel_wm_config config = {
2415 .num_pipes_active = 1,
2416 .sprites_enabled = params->spr.enabled,
2417 .sprites_scaled = params->spr.scaled,
2418 };
2419 struct ilk_wm_maximums max;
2420
2421 pipe_wm->pipe_enabled = params->active;
2422 pipe_wm->sprites_enabled = params->spr.enabled;
2423 pipe_wm->sprites_scaled = params->spr.scaled;
2424
2425 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2426 if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled)
2427 max_level = 1;
2428
2429 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2430 if (params->spr.scaled)
2431 max_level = 0;
2432
2433 ilk_compute_wm_level(dev_priv, 0, params, &pipe_wm->wm[0]);
2434
2435 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2436 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
2437
2438 /* LP0 watermarks always use 1/2 DDB partitioning */
2439 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2440
2441 /* At least LP0 must be valid */
2442 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
2443 return false;
2444
2445 ilk_compute_wm_reg_maximums(dev, 1, &max);
2446
2447 for (level = 1; level <= max_level; level++) {
2448 struct intel_wm_level wm = {};
2449
2450 ilk_compute_wm_level(dev_priv, level, params, &wm);
2451
2452 /*
2453 * Disable any watermark level that exceeds the
2454 * register maximums since such watermarks are
2455 * always invalid.
2456 */
2457 if (!ilk_validate_wm_level(level, &max, &wm))
2458 break;
2459
2460 pipe_wm->wm[level] = wm;
2461 }
2462
2463 return true;
2464 }
2465
2466 /*
2467 * Merge the watermarks from all active pipes for a specific level.
2468 */
2469 static void ilk_merge_wm_level(struct drm_device *dev,
2470 int level,
2471 struct intel_wm_level *ret_wm)
2472 {
2473 const struct intel_crtc *intel_crtc;
2474
2475 ret_wm->enable = true;
2476
2477 for_each_intel_crtc(dev, intel_crtc) {
2478 const struct intel_pipe_wm *active = &intel_crtc->wm.active;
2479 const struct intel_wm_level *wm = &active->wm[level];
2480
2481 if (!active->pipe_enabled)
2482 continue;
2483
2484 /*
2485 * The watermark values may have been used in the past,
2486 * so we must maintain them in the registers for some
2487 * time even if the level is now disabled.
2488 */
2489 if (!wm->enable)
2490 ret_wm->enable = false;
2491
2492 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2493 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2494 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2495 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2496 }
2497 }
2498
2499 /*
2500 * Merge all low power watermarks for all active pipes.
2501 */
2502 static void ilk_wm_merge(struct drm_device *dev,
2503 const struct intel_wm_config *config,
2504 const struct ilk_wm_maximums *max,
2505 struct intel_pipe_wm *merged)
2506 {
2507 struct drm_i915_private *dev_priv = dev->dev_private;
2508 int level, max_level = ilk_wm_max_level(dev);
2509 int last_enabled_level = max_level;
2510
2511 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2512 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2513 config->num_pipes_active > 1)
2514 return;
2515
2516 /* ILK: FBC WM must be disabled always */
2517 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
2518
2519 /* merge each WM1+ level */
2520 for (level = 1; level <= max_level; level++) {
2521 struct intel_wm_level *wm = &merged->wm[level];
2522
2523 ilk_merge_wm_level(dev, level, wm);
2524
2525 if (level > last_enabled_level)
2526 wm->enable = false;
2527 else if (!ilk_validate_wm_level(level, max, wm))
2528 /* make sure all following levels get disabled */
2529 last_enabled_level = level - 1;
2530
2531 /*
2532 * The spec says it is preferred to disable
2533 * FBC WMs instead of disabling a WM level.
2534 */
2535 if (wm->fbc_val > max->fbc) {
2536 if (wm->enable)
2537 merged->fbc_wm_enabled = false;
2538 wm->fbc_val = 0;
2539 }
2540 }
2541
2542 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2543 /*
2544 * FIXME this is racy. FBC might get enabled later.
2545 * What we should check here is whether FBC can be
2546 * enabled sometime later.
2547 */
2548 if (IS_GEN5(dev) && !merged->fbc_wm_enabled &&
2549 intel_fbc_enabled(dev_priv)) {
2550 for (level = 2; level <= max_level; level++) {
2551 struct intel_wm_level *wm = &merged->wm[level];
2552
2553 wm->enable = false;
2554 }
2555 }
2556 }
2557
2558 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2559 {
2560 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2561 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2562 }
2563
2564 /* The value we need to program into the WM_LPx latency field */
2565 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2566 {
2567 struct drm_i915_private *dev_priv = dev->dev_private;
2568
2569 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2570 return 2 * level;
2571 else
2572 return dev_priv->wm.pri_latency[level];
2573 }
2574
2575 static void ilk_compute_wm_results(struct drm_device *dev,
2576 const struct intel_pipe_wm *merged,
2577 enum intel_ddb_partitioning partitioning,
2578 struct ilk_wm_values *results)
2579 {
2580 struct intel_crtc *intel_crtc;
2581 int level, wm_lp;
2582
2583 results->enable_fbc_wm = merged->fbc_wm_enabled;
2584 results->partitioning = partitioning;
2585
2586 /* LP1+ register values */
2587 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2588 const struct intel_wm_level *r;
2589
2590 level = ilk_wm_lp_to_level(wm_lp, merged);
2591
2592 r = &merged->wm[level];
2593
2594 /*
2595 * Maintain the watermark values even if the level is
2596 * disabled. Doing otherwise could cause underruns.
2597 */
2598 results->wm_lp[wm_lp - 1] =
2599 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2600 (r->pri_val << WM1_LP_SR_SHIFT) |
2601 r->cur_val;
2602
2603 if (r->enable)
2604 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2605
2606 if (INTEL_INFO(dev)->gen >= 8)
2607 results->wm_lp[wm_lp - 1] |=
2608 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2609 else
2610 results->wm_lp[wm_lp - 1] |=
2611 r->fbc_val << WM1_LP_FBC_SHIFT;
2612
2613 /*
2614 * Always set WM1S_LP_EN when spr_val != 0, even if the
2615 * level is disabled. Doing otherwise could cause underruns.
2616 */
2617 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2618 WARN_ON(wm_lp != 1);
2619 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2620 } else
2621 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2622 }
2623
2624 /* LP0 register values */
2625 for_each_intel_crtc(dev, intel_crtc) {
2626 enum pipe pipe = intel_crtc->pipe;
2627 const struct intel_wm_level *r =
2628 &intel_crtc->wm.active.wm[0];
2629
2630 if (WARN_ON(!r->enable))
2631 continue;
2632
2633 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
2634
2635 results->wm_pipe[pipe] =
2636 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2637 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2638 r->cur_val;
2639 }
2640 }
2641
2642 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2643 * case both are at the same level. Prefer r1 in case they're the same. */
2644 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2645 struct intel_pipe_wm *r1,
2646 struct intel_pipe_wm *r2)
2647 {
2648 int level, max_level = ilk_wm_max_level(dev);
2649 int level1 = 0, level2 = 0;
2650
2651 for (level = 1; level <= max_level; level++) {
2652 if (r1->wm[level].enable)
2653 level1 = level;
2654 if (r2->wm[level].enable)
2655 level2 = level;
2656 }
2657
2658 if (level1 == level2) {
2659 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2660 return r2;
2661 else
2662 return r1;
2663 } else if (level1 > level2) {
2664 return r1;
2665 } else {
2666 return r2;
2667 }
2668 }
2669
2670 /* dirty bits used to track which watermarks need changes */
2671 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2672 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2673 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2674 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2675 #define WM_DIRTY_FBC (1 << 24)
2676 #define WM_DIRTY_DDB (1 << 25)
2677
2678 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
2679 const struct ilk_wm_values *old,
2680 const struct ilk_wm_values *new)
2681 {
2682 unsigned int dirty = 0;
2683 enum pipe pipe;
2684 int wm_lp;
2685
2686 for_each_pipe(dev_priv, pipe) {
2687 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2688 dirty |= WM_DIRTY_LINETIME(pipe);
2689 /* Must disable LP1+ watermarks too */
2690 dirty |= WM_DIRTY_LP_ALL;
2691 }
2692
2693 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2694 dirty |= WM_DIRTY_PIPE(pipe);
2695 /* Must disable LP1+ watermarks too */
2696 dirty |= WM_DIRTY_LP_ALL;
2697 }
2698 }
2699
2700 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2701 dirty |= WM_DIRTY_FBC;
2702 /* Must disable LP1+ watermarks too */
2703 dirty |= WM_DIRTY_LP_ALL;
2704 }
2705
2706 if (old->partitioning != new->partitioning) {
2707 dirty |= WM_DIRTY_DDB;
2708 /* Must disable LP1+ watermarks too */
2709 dirty |= WM_DIRTY_LP_ALL;
2710 }
2711
2712 /* LP1+ watermarks already deemed dirty, no need to continue */
2713 if (dirty & WM_DIRTY_LP_ALL)
2714 return dirty;
2715
2716 /* Find the lowest numbered LP1+ watermark in need of an update... */
2717 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2718 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2719 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2720 break;
2721 }
2722
2723 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2724 for (; wm_lp <= 3; wm_lp++)
2725 dirty |= WM_DIRTY_LP(wm_lp);
2726
2727 return dirty;
2728 }
2729
2730 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2731 unsigned int dirty)
2732 {
2733 struct ilk_wm_values *previous = &dev_priv->wm.hw;
2734 bool changed = false;
2735
2736 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2737 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2738 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2739 changed = true;
2740 }
2741 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2742 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2743 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2744 changed = true;
2745 }
2746 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2747 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2748 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2749 changed = true;
2750 }
2751
2752 /*
2753 * Don't touch WM1S_LP_EN here.
2754 * Doing so could cause underruns.
2755 */
2756
2757 return changed;
2758 }
2759
2760 /*
2761 * The spec says we shouldn't write when we don't need, because every write
2762 * causes WMs to be re-evaluated, expending some power.
2763 */
2764 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2765 struct ilk_wm_values *results)
2766 {
2767 struct drm_device *dev = dev_priv->dev;
2768 struct ilk_wm_values *previous = &dev_priv->wm.hw;
2769 unsigned int dirty;
2770 uint32_t val;
2771
2772 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
2773 if (!dirty)
2774 return;
2775
2776 _ilk_disable_lp_wm(dev_priv, dirty);
2777
2778 if (dirty & WM_DIRTY_PIPE(PIPE_A))
2779 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2780 if (dirty & WM_DIRTY_PIPE(PIPE_B))
2781 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2782 if (dirty & WM_DIRTY_PIPE(PIPE_C))
2783 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2784
2785 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2786 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2787 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2788 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2789 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2790 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2791
2792 if (dirty & WM_DIRTY_DDB) {
2793 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2794 val = I915_READ(WM_MISC);
2795 if (results->partitioning == INTEL_DDB_PART_1_2)
2796 val &= ~WM_MISC_DATA_PARTITION_5_6;
2797 else
2798 val |= WM_MISC_DATA_PARTITION_5_6;
2799 I915_WRITE(WM_MISC, val);
2800 } else {
2801 val = I915_READ(DISP_ARB_CTL2);
2802 if (results->partitioning == INTEL_DDB_PART_1_2)
2803 val &= ~DISP_DATA_PARTITION_5_6;
2804 else
2805 val |= DISP_DATA_PARTITION_5_6;
2806 I915_WRITE(DISP_ARB_CTL2, val);
2807 }
2808 }
2809
2810 if (dirty & WM_DIRTY_FBC) {
2811 val = I915_READ(DISP_ARB_CTL);
2812 if (results->enable_fbc_wm)
2813 val &= ~DISP_FBC_WM_DIS;
2814 else
2815 val |= DISP_FBC_WM_DIS;
2816 I915_WRITE(DISP_ARB_CTL, val);
2817 }
2818
2819 if (dirty & WM_DIRTY_LP(1) &&
2820 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2821 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2822
2823 if (INTEL_INFO(dev)->gen >= 7) {
2824 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2825 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2826 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2827 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2828 }
2829
2830 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2831 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2832 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2833 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2834 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2835 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2836
2837 dev_priv->wm.hw = *results;
2838 }
2839
2840 static bool ilk_disable_lp_wm(struct drm_device *dev)
2841 {
2842 struct drm_i915_private *dev_priv = dev->dev_private;
2843
2844 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2845 }
2846
2847 /*
2848 * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2849 * different active planes.
2850 */
2851
2852 #define SKL_DDB_SIZE 896 /* in blocks */
2853 #define BXT_DDB_SIZE 512
2854
2855 static void
2856 skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
2857 struct drm_crtc *for_crtc,
2858 const struct intel_wm_config *config,
2859 const struct skl_pipe_wm_parameters *params,
2860 struct skl_ddb_entry *alloc /* out */)
2861 {
2862 struct drm_crtc *crtc;
2863 unsigned int pipe_size, ddb_size;
2864 int nth_active_pipe;
2865
2866 if (!params->active) {
2867 alloc->start = 0;
2868 alloc->end = 0;
2869 return;
2870 }
2871
2872 if (IS_BROXTON(dev))
2873 ddb_size = BXT_DDB_SIZE;
2874 else
2875 ddb_size = SKL_DDB_SIZE;
2876
2877 ddb_size -= 4; /* 4 blocks for bypass path allocation */
2878
2879 nth_active_pipe = 0;
2880 for_each_crtc(dev, crtc) {
2881 if (!to_intel_crtc(crtc)->active)
2882 continue;
2883
2884 if (crtc == for_crtc)
2885 break;
2886
2887 nth_active_pipe++;
2888 }
2889
2890 pipe_size = ddb_size / config->num_pipes_active;
2891 alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active;
2892 alloc->end = alloc->start + pipe_size;
2893 }
2894
2895 static unsigned int skl_cursor_allocation(const struct intel_wm_config *config)
2896 {
2897 if (config->num_pipes_active == 1)
2898 return 32;
2899
2900 return 8;
2901 }
2902
2903 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
2904 {
2905 entry->start = reg & 0x3ff;
2906 entry->end = (reg >> 16) & 0x3ff;
2907 if (entry->end)
2908 entry->end += 1;
2909 }
2910
2911 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2912 struct skl_ddb_allocation *ddb /* out */)
2913 {
2914 enum pipe pipe;
2915 int plane;
2916 u32 val;
2917
2918 for_each_pipe(dev_priv, pipe) {
2919 for_each_plane(dev_priv, pipe, plane) {
2920 val = I915_READ(PLANE_BUF_CFG(pipe, plane));
2921 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
2922 val);
2923 }
2924
2925 val = I915_READ(CUR_BUF_CFG(pipe));
2926 skl_ddb_entry_init_from_hw(&ddb->cursor[pipe], val);
2927 }
2928 }
2929
2930 static unsigned int
2931 skl_plane_relative_data_rate(const struct intel_plane_wm_parameters *p, int y)
2932 {
2933
2934 /* for planar format */
2935 if (p->y_bytes_per_pixel) {
2936 if (y) /* y-plane data rate */
2937 return p->horiz_pixels * p->vert_pixels * p->y_bytes_per_pixel;
2938 else /* uv-plane data rate */
2939 return (p->horiz_pixels/2) * (p->vert_pixels/2) * p->bytes_per_pixel;
2940 }
2941
2942 /* for packed formats */
2943 return p->horiz_pixels * p->vert_pixels * p->bytes_per_pixel;
2944 }
2945
2946 /*
2947 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
2948 * a 8192x4096@32bpp framebuffer:
2949 * 3 * 4096 * 8192 * 4 < 2^32
2950 */
2951 static unsigned int
2952 skl_get_total_relative_data_rate(struct intel_crtc *intel_crtc,
2953 const struct skl_pipe_wm_parameters *params)
2954 {
2955 unsigned int total_data_rate = 0;
2956 int plane;
2957
2958 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
2959 const struct intel_plane_wm_parameters *p;
2960
2961 p = &params->plane[plane];
2962 if (!p->enabled)
2963 continue;
2964
2965 total_data_rate += skl_plane_relative_data_rate(p, 0); /* packed/uv */
2966 if (p->y_bytes_per_pixel) {
2967 total_data_rate += skl_plane_relative_data_rate(p, 1); /* y-plane */
2968 }
2969 }
2970
2971 return total_data_rate;
2972 }
2973
2974 static void
2975 skl_allocate_pipe_ddb(struct drm_crtc *crtc,
2976 const struct intel_wm_config *config,
2977 const struct skl_pipe_wm_parameters *params,
2978 struct skl_ddb_allocation *ddb /* out */)
2979 {
2980 struct drm_device *dev = crtc->dev;
2981 struct drm_i915_private *dev_priv = dev->dev_private;
2982 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2983 enum pipe pipe = intel_crtc->pipe;
2984 struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
2985 uint16_t alloc_size, start, cursor_blocks;
2986 uint16_t minimum[I915_MAX_PLANES];
2987 uint16_t y_minimum[I915_MAX_PLANES];
2988 unsigned int total_data_rate;
2989 int plane;
2990
2991 skl_ddb_get_pipe_allocation_limits(dev, crtc, config, params, alloc);
2992 alloc_size = skl_ddb_entry_size(alloc);
2993 if (alloc_size == 0) {
2994 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
2995 memset(&ddb->cursor[pipe], 0, sizeof(ddb->cursor[pipe]));
2996 return;
2997 }
2998
2999 cursor_blocks = skl_cursor_allocation(config);
3000 ddb->cursor[pipe].start = alloc->end - cursor_blocks;
3001 ddb->cursor[pipe].end = alloc->end;
3002
3003 alloc_size -= cursor_blocks;
3004 alloc->end -= cursor_blocks;
3005
3006 /* 1. Allocate the mininum required blocks for each active plane */
3007 for_each_plane(dev_priv, pipe, plane) {
3008 const struct intel_plane_wm_parameters *p;
3009
3010 p = &params->plane[plane];
3011 if (!p->enabled)
3012 continue;
3013
3014 minimum[plane] = 8;
3015 alloc_size -= minimum[plane];
3016 y_minimum[plane] = p->y_bytes_per_pixel ? 8 : 0;
3017 alloc_size -= y_minimum[plane];
3018 }
3019
3020 /*
3021 * 2. Distribute the remaining space in proportion to the amount of
3022 * data each plane needs to fetch from memory.
3023 *
3024 * FIXME: we may not allocate every single block here.
3025 */
3026 total_data_rate = skl_get_total_relative_data_rate(intel_crtc, params);
3027
3028 start = alloc->start;
3029 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
3030 const struct intel_plane_wm_parameters *p;
3031 unsigned int data_rate, y_data_rate;
3032 uint16_t plane_blocks, y_plane_blocks = 0;
3033
3034 p = &params->plane[plane];
3035 if (!p->enabled)
3036 continue;
3037
3038 data_rate = skl_plane_relative_data_rate(p, 0);
3039
3040 /*
3041 * allocation for (packed formats) or (uv-plane part of planar format):
3042 * promote the expression to 64 bits to avoid overflowing, the
3043 * result is < available as data_rate / total_data_rate < 1
3044 */
3045 plane_blocks = minimum[plane];
3046 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3047 total_data_rate);
3048
3049 ddb->plane[pipe][plane].start = start;
3050 ddb->plane[pipe][plane].end = start + plane_blocks;
3051
3052 start += plane_blocks;
3053
3054 /*
3055 * allocation for y_plane part of planar format:
3056 */
3057 if (p->y_bytes_per_pixel) {
3058 y_data_rate = skl_plane_relative_data_rate(p, 1);
3059 y_plane_blocks = y_minimum[plane];
3060 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3061 total_data_rate);
3062
3063 ddb->y_plane[pipe][plane].start = start;
3064 ddb->y_plane[pipe][plane].end = start + y_plane_blocks;
3065
3066 start += y_plane_blocks;
3067 }
3068
3069 }
3070
3071 }
3072
3073 static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
3074 {
3075 /* TODO: Take into account the scalers once we support them */
3076 return config->base.adjusted_mode.crtc_clock;
3077 }
3078
3079 /*
3080 * The max latency should be 257 (max the punit can code is 255 and we add 2us
3081 * for the read latency) and bytes_per_pixel should always be <= 8, so that
3082 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3083 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3084 */
3085 static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
3086 uint32_t latency)
3087 {
3088 uint32_t wm_intermediate_val, ret;
3089
3090 if (latency == 0)
3091 return UINT_MAX;
3092
3093 wm_intermediate_val = latency * pixel_rate * bytes_per_pixel / 512;
3094 ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3095
3096 return ret;
3097 }
3098
3099 static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
3100 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
3101 uint64_t tiling, uint32_t latency)
3102 {
3103 uint32_t ret;
3104 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3105 uint32_t wm_intermediate_val;
3106
3107 if (latency == 0)
3108 return UINT_MAX;
3109
3110 plane_bytes_per_line = horiz_pixels * bytes_per_pixel;
3111
3112 if (tiling == I915_FORMAT_MOD_Y_TILED ||
3113 tiling == I915_FORMAT_MOD_Yf_TILED) {
3114 plane_bytes_per_line *= 4;
3115 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3116 plane_blocks_per_line /= 4;
3117 } else {
3118 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3119 }
3120
3121 wm_intermediate_val = latency * pixel_rate;
3122 ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
3123 plane_blocks_per_line;
3124
3125 return ret;
3126 }
3127
3128 static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb,
3129 const struct intel_crtc *intel_crtc)
3130 {
3131 struct drm_device *dev = intel_crtc->base.dev;
3132 struct drm_i915_private *dev_priv = dev->dev_private;
3133 const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
3134 enum pipe pipe = intel_crtc->pipe;
3135
3136 if (memcmp(new_ddb->plane[pipe], cur_ddb->plane[pipe],
3137 sizeof(new_ddb->plane[pipe])))
3138 return true;
3139
3140 if (memcmp(&new_ddb->cursor[pipe], &cur_ddb->cursor[pipe],
3141 sizeof(new_ddb->cursor[pipe])))
3142 return true;
3143
3144 return false;
3145 }
3146
3147 static void skl_compute_wm_global_parameters(struct drm_device *dev,
3148 struct intel_wm_config *config)
3149 {
3150 struct drm_crtc *crtc;
3151 struct drm_plane *plane;
3152
3153 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3154 config->num_pipes_active += to_intel_crtc(crtc)->active;
3155
3156 /* FIXME: I don't think we need those two global parameters on SKL */
3157 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
3158 struct intel_plane *intel_plane = to_intel_plane(plane);
3159
3160 config->sprites_enabled |= intel_plane->wm.enabled;
3161 config->sprites_scaled |= intel_plane->wm.scaled;
3162 }
3163 }
3164
3165 static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,
3166 struct skl_pipe_wm_parameters *p)
3167 {
3168 struct drm_device *dev = crtc->dev;
3169 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3170 enum pipe pipe = intel_crtc->pipe;
3171 struct drm_plane *plane;
3172 struct drm_framebuffer *fb;
3173 int i = 1; /* Index for sprite planes start */
3174
3175 p->active = intel_crtc->active;
3176 if (p->active) {
3177 p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;
3178 p->pixel_rate = skl_pipe_pixel_rate(intel_crtc->config);
3179
3180 fb = crtc->primary->state->fb;
3181 /* For planar: Bpp is for uv plane, y_Bpp is for y plane */
3182 if (fb) {
3183 p->plane[0].enabled = true;
3184 p->plane[0].bytes_per_pixel = fb->pixel_format == DRM_FORMAT_NV12 ?
3185 drm_format_plane_cpp(fb->pixel_format, 1) :
3186 drm_format_plane_cpp(fb->pixel_format, 0);
3187 p->plane[0].y_bytes_per_pixel = fb->pixel_format == DRM_FORMAT_NV12 ?
3188 drm_format_plane_cpp(fb->pixel_format, 0) : 0;
3189 p->plane[0].tiling = fb->modifier[0];
3190 } else {
3191 p->plane[0].enabled = false;
3192 p->plane[0].bytes_per_pixel = 0;
3193 p->plane[0].y_bytes_per_pixel = 0;
3194 p->plane[0].tiling = DRM_FORMAT_MOD_NONE;
3195 }
3196 p->plane[0].horiz_pixels = intel_crtc->config->pipe_src_w;
3197 p->plane[0].vert_pixels = intel_crtc->config->pipe_src_h;
3198 p->plane[0].rotation = crtc->primary->state->rotation;
3199
3200 fb = crtc->cursor->state->fb;
3201 p->cursor.y_bytes_per_pixel = 0;
3202 if (fb) {
3203 p->cursor.enabled = true;
3204 p->cursor.bytes_per_pixel = fb->bits_per_pixel / 8;
3205 p->cursor.horiz_pixels = crtc->cursor->state->crtc_w;
3206 p->cursor.vert_pixels = crtc->cursor->state->crtc_h;
3207 } else {
3208 p->cursor.enabled = false;
3209 p->cursor.bytes_per_pixel = 0;
3210 p->cursor.horiz_pixels = 64;
3211 p->cursor.vert_pixels = 64;
3212 }
3213 }
3214
3215 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
3216 struct intel_plane *intel_plane = to_intel_plane(plane);
3217
3218 if (intel_plane->pipe == pipe &&
3219 plane->type == DRM_PLANE_TYPE_OVERLAY)
3220 p->plane[i++] = intel_plane->wm;
3221 }
3222 }
3223
3224 static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3225 struct skl_pipe_wm_parameters *p,
3226 struct intel_plane_wm_parameters *p_params,
3227 uint16_t ddb_allocation,
3228 int level,
3229 uint16_t *out_blocks, /* out */
3230 uint8_t *out_lines /* out */)
3231 {
3232 uint32_t latency = dev_priv->wm.skl_latency[level];
3233 uint32_t method1, method2;
3234 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3235 uint32_t res_blocks, res_lines;
3236 uint32_t selected_result;
3237 uint8_t bytes_per_pixel;
3238
3239 if (latency == 0 || !p->active || !p_params->enabled)
3240 return false;
3241
3242 bytes_per_pixel = p_params->y_bytes_per_pixel ?
3243 p_params->y_bytes_per_pixel :
3244 p_params->bytes_per_pixel;
3245 method1 = skl_wm_method1(p->pixel_rate,
3246 bytes_per_pixel,
3247 latency);
3248 method2 = skl_wm_method2(p->pixel_rate,
3249 p->pipe_htotal,
3250 p_params->horiz_pixels,
3251 bytes_per_pixel,
3252 p_params->tiling,
3253 latency);
3254
3255 plane_bytes_per_line = p_params->horiz_pixels * bytes_per_pixel;
3256 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3257
3258 if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
3259 p_params->tiling == I915_FORMAT_MOD_Yf_TILED) {
3260 uint32_t min_scanlines = 4;
3261 uint32_t y_tile_minimum;
3262 if (intel_rotation_90_or_270(p_params->rotation)) {
3263 switch (p_params->bytes_per_pixel) {
3264 case 1:
3265 min_scanlines = 16;
3266 break;
3267 case 2:
3268 min_scanlines = 8;
3269 break;
3270 case 8:
3271 WARN(1, "Unsupported pixel depth for rotation");
3272 }
3273 }
3274 y_tile_minimum = plane_blocks_per_line * min_scanlines;
3275 selected_result = max(method2, y_tile_minimum);
3276 } else {
3277 if ((ddb_allocation / plane_blocks_per_line) >= 1)
3278 selected_result = min(method1, method2);
3279 else
3280 selected_result = method1;
3281 }
3282
3283 res_blocks = selected_result + 1;
3284 res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
3285
3286 if (level >= 1 && level <= 7) {
3287 if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
3288 p_params->tiling == I915_FORMAT_MOD_Yf_TILED)
3289 res_lines += 4;
3290 else
3291 res_blocks++;
3292 }
3293
3294 if (res_blocks >= ddb_allocation || res_lines > 31)
3295 return false;
3296
3297 *out_blocks = res_blocks;
3298 *out_lines = res_lines;
3299
3300 return true;
3301 }
3302
3303 static void skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3304 struct skl_ddb_allocation *ddb,
3305 struct skl_pipe_wm_parameters *p,
3306 enum pipe pipe,
3307 int level,
3308 int num_planes,
3309 struct skl_wm_level *result)
3310 {
3311 uint16_t ddb_blocks;
3312 int i;
3313
3314 for (i = 0; i < num_planes; i++) {
3315 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3316
3317 result->plane_en[i] = skl_compute_plane_wm(dev_priv,
3318 p, &p->plane[i],
3319 ddb_blocks,
3320 level,
3321 &result->plane_res_b[i],
3322 &result->plane_res_l[i]);
3323 }
3324
3325 ddb_blocks = skl_ddb_entry_size(&ddb->cursor[pipe]);
3326 result->cursor_en = skl_compute_plane_wm(dev_priv, p, &p->cursor,
3327 ddb_blocks, level,
3328 &result->cursor_res_b,
3329 &result->cursor_res_l);
3330 }
3331
3332 static uint32_t
3333 skl_compute_linetime_wm(struct drm_crtc *crtc, struct skl_pipe_wm_parameters *p)
3334 {
3335 if (!to_intel_crtc(crtc)->active)
3336 return 0;
3337
3338 if (WARN_ON(p->pixel_rate == 0))
3339 return 0;
3340
3341 return DIV_ROUND_UP(8 * p->pipe_htotal * 1000, p->pixel_rate);
3342 }
3343
3344 static void skl_compute_transition_wm(struct drm_crtc *crtc,
3345 struct skl_pipe_wm_parameters *params,
3346 struct skl_wm_level *trans_wm /* out */)
3347 {
3348 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3349 int i;
3350
3351 if (!params->active)
3352 return;
3353
3354 /* Until we know more, just disable transition WMs */
3355 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3356 trans_wm->plane_en[i] = false;
3357 trans_wm->cursor_en = false;
3358 }
3359
3360 static void skl_compute_pipe_wm(struct drm_crtc *crtc,
3361 struct skl_ddb_allocation *ddb,
3362 struct skl_pipe_wm_parameters *params,
3363 struct skl_pipe_wm *pipe_wm)
3364 {
3365 struct drm_device *dev = crtc->dev;
3366 const struct drm_i915_private *dev_priv = dev->dev_private;
3367 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3368 int level, max_level = ilk_wm_max_level(dev);
3369
3370 for (level = 0; level <= max_level; level++) {
3371 skl_compute_wm_level(dev_priv, ddb, params, intel_crtc->pipe,
3372 level, intel_num_planes(intel_crtc),
3373 &pipe_wm->wm[level]);
3374 }
3375 pipe_wm->linetime = skl_compute_linetime_wm(crtc, params);
3376
3377 skl_compute_transition_wm(crtc, params, &pipe_wm->trans_wm);
3378 }
3379
3380 static void skl_compute_wm_results(struct drm_device *dev,
3381 struct skl_pipe_wm_parameters *p,
3382 struct skl_pipe_wm *p_wm,
3383 struct skl_wm_values *r,
3384 struct intel_crtc *intel_crtc)
3385 {
3386 int level, max_level = ilk_wm_max_level(dev);
3387 enum pipe pipe = intel_crtc->pipe;
3388 uint32_t temp;
3389 int i;
3390
3391 for (level = 0; level <= max_level; level++) {
3392 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3393 temp = 0;
3394
3395 temp |= p_wm->wm[level].plane_res_l[i] <<
3396 PLANE_WM_LINES_SHIFT;
3397 temp |= p_wm->wm[level].plane_res_b[i];
3398 if (p_wm->wm[level].plane_en[i])
3399 temp |= PLANE_WM_EN;
3400
3401 r->plane[pipe][i][level] = temp;
3402 }
3403
3404 temp = 0;
3405
3406 temp |= p_wm->wm[level].cursor_res_l << PLANE_WM_LINES_SHIFT;
3407 temp |= p_wm->wm[level].cursor_res_b;
3408
3409 if (p_wm->wm[level].cursor_en)
3410 temp |= PLANE_WM_EN;
3411
3412 r->cursor[pipe][level] = temp;
3413
3414 }
3415
3416 /* transition WMs */
3417 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3418 temp = 0;
3419 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3420 temp |= p_wm->trans_wm.plane_res_b[i];
3421 if (p_wm->trans_wm.plane_en[i])
3422 temp |= PLANE_WM_EN;
3423
3424 r->plane_trans[pipe][i] = temp;
3425 }
3426
3427 temp = 0;
3428 temp |= p_wm->trans_wm.cursor_res_l << PLANE_WM_LINES_SHIFT;
3429 temp |= p_wm->trans_wm.cursor_res_b;
3430 if (p_wm->trans_wm.cursor_en)
3431 temp |= PLANE_WM_EN;
3432
3433 r->cursor_trans[pipe] = temp;
3434
3435 r->wm_linetime[pipe] = p_wm->linetime;
3436 }
3437
3438 static void skl_ddb_entry_write(struct drm_i915_private *dev_priv, uint32_t reg,
3439 const struct skl_ddb_entry *entry)
3440 {
3441 if (entry->end)
3442 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3443 else
3444 I915_WRITE(reg, 0);
3445 }
3446
3447 static void skl_write_wm_values(struct drm_i915_private *dev_priv,
3448 const struct skl_wm_values *new)
3449 {
3450 struct drm_device *dev = dev_priv->dev;
3451 struct intel_crtc *crtc;
3452
3453 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
3454 int i, level, max_level = ilk_wm_max_level(dev);
3455 enum pipe pipe = crtc->pipe;
3456
3457 if (!new->dirty[pipe])
3458 continue;
3459
3460 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]);
3461
3462 for (level = 0; level <= max_level; level++) {
3463 for (i = 0; i < intel_num_planes(crtc); i++)
3464 I915_WRITE(PLANE_WM(pipe, i, level),
3465 new->plane[pipe][i][level]);
3466 I915_WRITE(CUR_WM(pipe, level),
3467 new->cursor[pipe][level]);
3468 }
3469 for (i = 0; i < intel_num_planes(crtc); i++)
3470 I915_WRITE(PLANE_WM_TRANS(pipe, i),
3471 new->plane_trans[pipe][i]);
3472 I915_WRITE(CUR_WM_TRANS(pipe), new->cursor_trans[pipe]);
3473
3474 for (i = 0; i < intel_num_planes(crtc); i++) {
3475 skl_ddb_entry_write(dev_priv,
3476 PLANE_BUF_CFG(pipe, i),
3477 &new->ddb.plane[pipe][i]);
3478 skl_ddb_entry_write(dev_priv,
3479 PLANE_NV12_BUF_CFG(pipe, i),
3480 &new->ddb.y_plane[pipe][i]);
3481 }
3482
3483 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3484 &new->ddb.cursor[pipe]);
3485 }
3486 }
3487
3488 /*
3489 * When setting up a new DDB allocation arrangement, we need to correctly
3490 * sequence the times at which the new allocations for the pipes are taken into
3491 * account or we'll have pipes fetching from space previously allocated to
3492 * another pipe.
3493 *
3494 * Roughly the sequence looks like:
3495 * 1. re-allocate the pipe(s) with the allocation being reduced and not
3496 * overlapping with a previous light-up pipe (another way to put it is:
3497 * pipes with their new allocation strickly included into their old ones).
3498 * 2. re-allocate the other pipes that get their allocation reduced
3499 * 3. allocate the pipes having their allocation increased
3500 *
3501 * Steps 1. and 2. are here to take care of the following case:
3502 * - Initially DDB looks like this:
3503 * | B | C |
3504 * - enable pipe A.
3505 * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
3506 * allocation
3507 * | A | B | C |
3508 *
3509 * We need to sequence the re-allocation: C, B, A (and not B, C, A).
3510 */
3511
3512 static void
3513 skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass)
3514 {
3515 int plane;
3516
3517 DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);
3518
3519 for_each_plane(dev_priv, pipe, plane) {
3520 I915_WRITE(PLANE_SURF(pipe, plane),
3521 I915_READ(PLANE_SURF(pipe, plane)));
3522 }
3523 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3524 }
3525
3526 static bool
3527 skl_ddb_allocation_included(const struct skl_ddb_allocation *old,
3528 const struct skl_ddb_allocation *new,
3529 enum pipe pipe)
3530 {
3531 uint16_t old_size, new_size;
3532
3533 old_size = skl_ddb_entry_size(&old->pipe[pipe]);
3534 new_size = skl_ddb_entry_size(&new->pipe[pipe]);
3535
3536 return old_size != new_size &&
3537 new->pipe[pipe].start >= old->pipe[pipe].start &&
3538 new->pipe[pipe].end <= old->pipe[pipe].end;
3539 }
3540
3541 static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
3542 struct skl_wm_values *new_values)
3543 {
3544 struct drm_device *dev = dev_priv->dev;
3545 struct skl_ddb_allocation *cur_ddb, *new_ddb;
3546 bool reallocated[I915_MAX_PIPES] = {};
3547 struct intel_crtc *crtc;
3548 enum pipe pipe;
3549
3550 new_ddb = &new_values->ddb;
3551 cur_ddb = &dev_priv->wm.skl_hw.ddb;
3552
3553 /*
3554 * First pass: flush the pipes with the new allocation contained into
3555 * the old space.
3556 *
3557 * We'll wait for the vblank on those pipes to ensure we can safely
3558 * re-allocate the freed space without this pipe fetching from it.
3559 */
3560 for_each_intel_crtc(dev, crtc) {
3561 if (!crtc->active)
3562 continue;
3563
3564 pipe = crtc->pipe;
3565
3566 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))
3567 continue;
3568
3569 skl_wm_flush_pipe(dev_priv, pipe, 1);
3570 intel_wait_for_vblank(dev, pipe);
3571
3572 reallocated[pipe] = true;
3573 }
3574
3575
3576 /*
3577 * Second pass: flush the pipes that are having their allocation
3578 * reduced, but overlapping with a previous allocation.
3579 *
3580 * Here as well we need to wait for the vblank to make sure the freed
3581 * space is not used anymore.
3582 */
3583 for_each_intel_crtc(dev, crtc) {
3584 if (!crtc->active)
3585 continue;
3586
3587 pipe = crtc->pipe;
3588
3589 if (reallocated[pipe])
3590 continue;
3591
3592 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <
3593 skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
3594 skl_wm_flush_pipe(dev_priv, pipe, 2);
3595 intel_wait_for_vblank(dev, pipe);
3596 reallocated[pipe] = true;
3597 }
3598 }
3599
3600 /*
3601 * Third pass: flush the pipes that got more space allocated.
3602 *
3603 * We don't need to actively wait for the update here, next vblank
3604 * will just get more DDB space with the correct WM values.
3605 */
3606 for_each_intel_crtc(dev, crtc) {
3607 if (!crtc->active)
3608 continue;
3609
3610 pipe = crtc->pipe;
3611
3612 /*
3613 * At this point, only the pipes more space than before are
3614 * left to re-allocate.
3615 */
3616 if (reallocated[pipe])
3617 continue;
3618
3619 skl_wm_flush_pipe(dev_priv, pipe, 3);
3620 }
3621 }
3622
3623 static bool skl_update_pipe_wm(struct drm_crtc *crtc,
3624 struct skl_pipe_wm_parameters *params,
3625 struct intel_wm_config *config,
3626 struct skl_ddb_allocation *ddb, /* out */
3627 struct skl_pipe_wm *pipe_wm /* out */)
3628 {
3629 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3630
3631 skl_compute_wm_pipe_parameters(crtc, params);
3632 skl_allocate_pipe_ddb(crtc, config, params, ddb);
3633 skl_compute_pipe_wm(crtc, ddb, params, pipe_wm);
3634
3635 if (!memcmp(&intel_crtc->wm.skl_active, pipe_wm, sizeof(*pipe_wm)))
3636 return false;
3637
3638 intel_crtc->wm.skl_active = *pipe_wm;
3639
3640 return true;
3641 }
3642
3643 static void skl_update_other_pipe_wm(struct drm_device *dev,
3644 struct drm_crtc *crtc,
3645 struct intel_wm_config *config,
3646 struct skl_wm_values *r)
3647 {
3648 struct intel_crtc *intel_crtc;
3649 struct intel_crtc *this_crtc = to_intel_crtc(crtc);
3650
3651 /*
3652 * If the WM update hasn't changed the allocation for this_crtc (the
3653 * crtc we are currently computing the new WM values for), other
3654 * enabled crtcs will keep the same allocation and we don't need to
3655 * recompute anything for them.
3656 */
3657 if (!skl_ddb_allocation_changed(&r->ddb, this_crtc))
3658 return;
3659
3660 /*
3661 * Otherwise, because of this_crtc being freshly enabled/disabled, the
3662 * other active pipes need new DDB allocation and WM values.
3663 */
3664 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
3665 base.head) {
3666 struct skl_pipe_wm_parameters params = {};
3667 struct skl_pipe_wm pipe_wm = {};
3668 bool wm_changed;
3669
3670 if (this_crtc->pipe == intel_crtc->pipe)
3671 continue;
3672
3673 if (!intel_crtc->active)
3674 continue;
3675
3676 wm_changed = skl_update_pipe_wm(&intel_crtc->base,
3677 &params, config,
3678 &r->ddb, &pipe_wm);
3679
3680 /*
3681 * If we end up re-computing the other pipe WM values, it's
3682 * because it was really needed, so we expect the WM values to
3683 * be different.
3684 */
3685 WARN_ON(!wm_changed);
3686
3687 skl_compute_wm_results(dev, &params, &pipe_wm, r, intel_crtc);
3688 r->dirty[intel_crtc->pipe] = true;
3689 }
3690 }
3691
3692 static void skl_clear_wm(struct skl_wm_values *watermarks, enum pipe pipe)
3693 {
3694 watermarks->wm_linetime[pipe] = 0;
3695 memset(watermarks->plane[pipe], 0,
3696 sizeof(uint32_t) * 8 * I915_MAX_PLANES);
3697 memset(watermarks->cursor[pipe], 0, sizeof(uint32_t) * 8);
3698 memset(watermarks->plane_trans[pipe],
3699 0, sizeof(uint32_t) * I915_MAX_PLANES);
3700 watermarks->cursor_trans[pipe] = 0;
3701
3702 /* Clear ddb entries for pipe */
3703 memset(&watermarks->ddb.pipe[pipe], 0, sizeof(struct skl_ddb_entry));
3704 memset(&watermarks->ddb.plane[pipe], 0,
3705 sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
3706 memset(&watermarks->ddb.y_plane[pipe], 0,
3707 sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
3708 memset(&watermarks->ddb.cursor[pipe], 0, sizeof(struct skl_ddb_entry));
3709
3710 }
3711
3712 static void skl_update_wm(struct drm_crtc *crtc)
3713 {
3714 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3715 struct drm_device *dev = crtc->dev;
3716 struct drm_i915_private *dev_priv = dev->dev_private;
3717 struct skl_pipe_wm_parameters params = {};
3718 struct skl_wm_values *results = &dev_priv->wm.skl_results;
3719 struct skl_pipe_wm pipe_wm = {};
3720 struct intel_wm_config config = {};
3721
3722
3723 /* Clear all dirty flags */
3724 memset(results->dirty, 0, sizeof(bool) * I915_MAX_PIPES);
3725
3726 skl_clear_wm(results, intel_crtc->pipe);
3727
3728 skl_compute_wm_global_parameters(dev, &config);
3729
3730 if (!skl_update_pipe_wm(crtc, &params, &config,
3731 &results->ddb, &pipe_wm))
3732 return;
3733
3734 skl_compute_wm_results(dev, &params, &pipe_wm, results, intel_crtc);
3735 results->dirty[intel_crtc->pipe] = true;
3736
3737 skl_update_other_pipe_wm(dev, crtc, &config, results);
3738 skl_write_wm_values(dev_priv, results);
3739 skl_flush_wm_values(dev_priv, results);
3740
3741 /* store the new configuration */
3742 dev_priv->wm.skl_hw = *results;
3743 }
3744
3745 static void
3746 skl_update_sprite_wm(struct drm_plane *plane, struct drm_crtc *crtc,
3747 uint32_t sprite_width, uint32_t sprite_height,
3748 int pixel_size, bool enabled, bool scaled)
3749 {
3750 struct intel_plane *intel_plane = to_intel_plane(plane);
3751 struct drm_framebuffer *fb = plane->state->fb;
3752
3753 intel_plane->wm.enabled = enabled;
3754 intel_plane->wm.scaled = scaled;
3755 intel_plane->wm.horiz_pixels = sprite_width;
3756 intel_plane->wm.vert_pixels = sprite_height;
3757 intel_plane->wm.tiling = DRM_FORMAT_MOD_NONE;
3758
3759 /* For planar: Bpp is for UV plane, y_Bpp is for Y plane */
3760 intel_plane->wm.bytes_per_pixel =
3761 (fb && fb->pixel_format == DRM_FORMAT_NV12) ?
3762 drm_format_plane_cpp(plane->state->fb->pixel_format, 1) : pixel_size;
3763 intel_plane->wm.y_bytes_per_pixel =
3764 (fb && fb->pixel_format == DRM_FORMAT_NV12) ?
3765 drm_format_plane_cpp(plane->state->fb->pixel_format, 0) : 0;
3766
3767 /*
3768 * Framebuffer can be NULL on plane disable, but it does not
3769 * matter for watermarks if we assume no tiling in that case.
3770 */
3771 if (fb)
3772 intel_plane->wm.tiling = fb->modifier[0];
3773 intel_plane->wm.rotation = plane->state->rotation;
3774
3775 skl_update_wm(crtc);
3776 }
3777
3778 static void ilk_update_wm(struct drm_crtc *crtc)
3779 {
3780 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3781 struct drm_device *dev = crtc->dev;
3782 struct drm_i915_private *dev_priv = dev->dev_private;
3783 struct ilk_wm_maximums max;
3784 struct ilk_pipe_wm_parameters params = {};
3785 struct ilk_wm_values results = {};
3786 enum intel_ddb_partitioning partitioning;
3787 struct intel_pipe_wm pipe_wm = {};
3788 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
3789 struct intel_wm_config config = {};
3790
3791 ilk_compute_wm_parameters(crtc, &params);
3792
3793 intel_compute_pipe_wm(crtc, &params, &pipe_wm);
3794
3795 if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
3796 return;
3797
3798 intel_crtc->wm.active = pipe_wm;
3799
3800 ilk_compute_wm_config(dev, &config);
3801
3802 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
3803 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
3804
3805 /* 5/6 split only in single pipe config on IVB+ */
3806 if (INTEL_INFO(dev)->gen >= 7 &&
3807 config.num_pipes_active == 1 && config.sprites_enabled) {
3808 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
3809 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
3810
3811 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
3812 } else {
3813 best_lp_wm = &lp_wm_1_2;
3814 }
3815
3816 partitioning = (best_lp_wm == &lp_wm_1_2) ?
3817 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
3818
3819 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
3820
3821 ilk_write_wm_values(dev_priv, &results);
3822 }
3823
3824 static void
3825 ilk_update_sprite_wm(struct drm_plane *plane,
3826 struct drm_crtc *crtc,
3827 uint32_t sprite_width, uint32_t sprite_height,
3828 int pixel_size, bool enabled, bool scaled)
3829 {
3830 struct drm_device *dev = plane->dev;
3831 struct intel_plane *intel_plane = to_intel_plane(plane);
3832
3833 intel_plane->wm.enabled = enabled;
3834 intel_plane->wm.scaled = scaled;
3835 intel_plane->wm.horiz_pixels = sprite_width;
3836 intel_plane->wm.vert_pixels = sprite_width;
3837 intel_plane->wm.bytes_per_pixel = pixel_size;
3838
3839 /*
3840 * IVB workaround: must disable low power watermarks for at least
3841 * one frame before enabling scaling. LP watermarks can be re-enabled
3842 * when scaling is disabled.
3843 *
3844 * WaCxSRDisabledForSpriteScaling:ivb
3845 */
3846 if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev))
3847 intel_wait_for_vblank(dev, intel_plane->pipe);
3848
3849 ilk_update_wm(crtc);
3850 }
3851
3852 static void skl_pipe_wm_active_state(uint32_t val,
3853 struct skl_pipe_wm *active,
3854 bool is_transwm,
3855 bool is_cursor,
3856 int i,
3857 int level)
3858 {
3859 bool is_enabled = (val & PLANE_WM_EN) != 0;
3860
3861 if (!is_transwm) {
3862 if (!is_cursor) {
3863 active->wm[level].plane_en[i] = is_enabled;
3864 active->wm[level].plane_res_b[i] =
3865 val & PLANE_WM_BLOCKS_MASK;
3866 active->wm[level].plane_res_l[i] =
3867 (val >> PLANE_WM_LINES_SHIFT) &
3868 PLANE_WM_LINES_MASK;
3869 } else {
3870 active->wm[level].cursor_en = is_enabled;
3871 active->wm[level].cursor_res_b =
3872 val & PLANE_WM_BLOCKS_MASK;
3873 active->wm[level].cursor_res_l =
3874 (val >> PLANE_WM_LINES_SHIFT) &
3875 PLANE_WM_LINES_MASK;
3876 }
3877 } else {
3878 if (!is_cursor) {
3879 active->trans_wm.plane_en[i] = is_enabled;
3880 active->trans_wm.plane_res_b[i] =
3881 val & PLANE_WM_BLOCKS_MASK;
3882 active->trans_wm.plane_res_l[i] =
3883 (val >> PLANE_WM_LINES_SHIFT) &
3884 PLANE_WM_LINES_MASK;
3885 } else {
3886 active->trans_wm.cursor_en = is_enabled;
3887 active->trans_wm.cursor_res_b =
3888 val & PLANE_WM_BLOCKS_MASK;
3889 active->trans_wm.cursor_res_l =
3890 (val >> PLANE_WM_LINES_SHIFT) &
3891 PLANE_WM_LINES_MASK;
3892 }
3893 }
3894 }
3895
3896 static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3897 {
3898 struct drm_device *dev = crtc->dev;
3899 struct drm_i915_private *dev_priv = dev->dev_private;
3900 struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
3901 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3902 struct skl_pipe_wm *active = &intel_crtc->wm.skl_active;
3903 enum pipe pipe = intel_crtc->pipe;
3904 int level, i, max_level;
3905 uint32_t temp;
3906
3907 max_level = ilk_wm_max_level(dev);
3908
3909 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3910
3911 for (level = 0; level <= max_level; level++) {
3912 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3913 hw->plane[pipe][i][level] =
3914 I915_READ(PLANE_WM(pipe, i, level));
3915 hw->cursor[pipe][level] = I915_READ(CUR_WM(pipe, level));
3916 }
3917
3918 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3919 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
3920 hw->cursor_trans[pipe] = I915_READ(CUR_WM_TRANS(pipe));
3921
3922 if (!intel_crtc->active)
3923 return;
3924
3925 hw->dirty[pipe] = true;
3926
3927 active->linetime = hw->wm_linetime[pipe];
3928
3929 for (level = 0; level <= max_level; level++) {
3930 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3931 temp = hw->plane[pipe][i][level];
3932 skl_pipe_wm_active_state(temp, active, false,
3933 false, i, level);
3934 }
3935 temp = hw->cursor[pipe][level];
3936 skl_pipe_wm_active_state(temp, active, false, true, i, level);
3937 }
3938
3939 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3940 temp = hw->plane_trans[pipe][i];
3941 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
3942 }
3943
3944 temp = hw->cursor_trans[pipe];
3945 skl_pipe_wm_active_state(temp, active, true, true, i, 0);
3946 }
3947
3948 void skl_wm_get_hw_state(struct drm_device *dev)
3949 {
3950 struct drm_i915_private *dev_priv = dev->dev_private;
3951 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3952 struct drm_crtc *crtc;
3953
3954 skl_ddb_get_hw_state(dev_priv, ddb);
3955 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3956 skl_pipe_wm_get_hw_state(crtc);
3957 }
3958
3959 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3960 {
3961 struct drm_device *dev = crtc->dev;
3962 struct drm_i915_private *dev_priv = dev->dev_private;
3963 struct ilk_wm_values *hw = &dev_priv->wm.hw;
3964 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3965 struct intel_pipe_wm *active = &intel_crtc->wm.active;
3966 enum pipe pipe = intel_crtc->pipe;
3967 static const unsigned int wm0_pipe_reg[] = {
3968 [PIPE_A] = WM0_PIPEA_ILK,
3969 [PIPE_B] = WM0_PIPEB_ILK,
3970 [PIPE_C] = WM0_PIPEC_IVB,
3971 };
3972
3973 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
3974 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3975 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3976
3977 active->pipe_enabled = intel_crtc->active;
3978
3979 if (active->pipe_enabled) {
3980 u32 tmp = hw->wm_pipe[pipe];
3981
3982 /*
3983 * For active pipes LP0 watermark is marked as
3984 * enabled, and LP1+ watermaks as disabled since
3985 * we can't really reverse compute them in case
3986 * multiple pipes are active.
3987 */
3988 active->wm[0].enable = true;
3989 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3990 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3991 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3992 active->linetime = hw->wm_linetime[pipe];
3993 } else {
3994 int level, max_level = ilk_wm_max_level(dev);
3995
3996 /*
3997 * For inactive pipes, all watermark levels
3998 * should be marked as enabled but zeroed,
3999 * which is what we'd compute them to.
4000 */
4001 for (level = 0; level <= max_level; level++)
4002 active->wm[level].enable = true;
4003 }
4004 }
4005
4006 #define _FW_WM(value, plane) \
4007 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
4008 #define _FW_WM_VLV(value, plane) \
4009 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
4010
4011 static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
4012 struct vlv_wm_values *wm)
4013 {
4014 enum pipe pipe;
4015 uint32_t tmp;
4016
4017 for_each_pipe(dev_priv, pipe) {
4018 tmp = I915_READ(VLV_DDL(pipe));
4019
4020 wm->ddl[pipe].primary =
4021 (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4022 wm->ddl[pipe].cursor =
4023 (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4024 wm->ddl[pipe].sprite[0] =
4025 (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4026 wm->ddl[pipe].sprite[1] =
4027 (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4028 }
4029
4030 tmp = I915_READ(DSPFW1);
4031 wm->sr.plane = _FW_WM(tmp, SR);
4032 wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
4033 wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
4034 wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
4035
4036 tmp = I915_READ(DSPFW2);
4037 wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
4038 wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
4039 wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
4040
4041 tmp = I915_READ(DSPFW3);
4042 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
4043
4044 if (IS_CHERRYVIEW(dev_priv)) {
4045 tmp = I915_READ(DSPFW7_CHV);
4046 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4047 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4048
4049 tmp = I915_READ(DSPFW8_CHV);
4050 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
4051 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
4052
4053 tmp = I915_READ(DSPFW9_CHV);
4054 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
4055 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
4056
4057 tmp = I915_READ(DSPHOWM);
4058 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4059 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
4060 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
4061 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
4062 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4063 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4064 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4065 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4066 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4067 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4068 } else {
4069 tmp = I915_READ(DSPFW7);
4070 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4071 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4072
4073 tmp = I915_READ(DSPHOWM);
4074 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4075 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4076 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4077 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4078 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4079 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4080 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4081 }
4082 }
4083
4084 #undef _FW_WM
4085 #undef _FW_WM_VLV
4086
4087 void vlv_wm_get_hw_state(struct drm_device *dev)
4088 {
4089 struct drm_i915_private *dev_priv = to_i915(dev);
4090 struct vlv_wm_values *wm = &dev_priv->wm.vlv;
4091 struct intel_plane *plane;
4092 enum pipe pipe;
4093 u32 val;
4094
4095 vlv_read_wm_values(dev_priv, wm);
4096
4097 for_each_intel_plane(dev, plane) {
4098 switch (plane->base.type) {
4099 int sprite;
4100 case DRM_PLANE_TYPE_CURSOR:
4101 plane->wm.fifo_size = 63;
4102 break;
4103 case DRM_PLANE_TYPE_PRIMARY:
4104 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
4105 break;
4106 case DRM_PLANE_TYPE_OVERLAY:
4107 sprite = plane->plane;
4108 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
4109 break;
4110 }
4111 }
4112
4113 wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4114 wm->level = VLV_WM_LEVEL_PM2;
4115
4116 if (IS_CHERRYVIEW(dev_priv)) {
4117 mutex_lock(&dev_priv->rps.hw_lock);
4118
4119 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4120 if (val & DSP_MAXFIFO_PM5_ENABLE)
4121 wm->level = VLV_WM_LEVEL_PM5;
4122
4123 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4124 if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4125 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4126
4127 mutex_unlock(&dev_priv->rps.hw_lock);
4128 }
4129
4130 for_each_pipe(dev_priv, pipe)
4131 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4132 pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4133 wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4134
4135 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4136 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4137 }
4138
4139 void ilk_wm_get_hw_state(struct drm_device *dev)
4140 {
4141 struct drm_i915_private *dev_priv = dev->dev_private;
4142 struct ilk_wm_values *hw = &dev_priv->wm.hw;
4143 struct drm_crtc *crtc;
4144
4145 for_each_crtc(dev, crtc)
4146 ilk_pipe_wm_get_hw_state(crtc);
4147
4148 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4149 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4150 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4151
4152 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
4153 if (INTEL_INFO(dev)->gen >= 7) {
4154 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4155 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4156 }
4157
4158 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4159 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4160 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4161 else if (IS_IVYBRIDGE(dev))
4162 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4163 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4164
4165 hw->enable_fbc_wm =
4166 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4167 }
4168
4169 /**
4170 * intel_update_watermarks - update FIFO watermark values based on current modes
4171 *
4172 * Calculate watermark values for the various WM regs based on current mode
4173 * and plane configuration.
4174 *
4175 * There are several cases to deal with here:
4176 * - normal (i.e. non-self-refresh)
4177 * - self-refresh (SR) mode
4178 * - lines are large relative to FIFO size (buffer can hold up to 2)
4179 * - lines are small relative to FIFO size (buffer can hold more than 2
4180 * lines), so need to account for TLB latency
4181 *
4182 * The normal calculation is:
4183 * watermark = dotclock * bytes per pixel * latency
4184 * where latency is platform & configuration dependent (we assume pessimal
4185 * values here).
4186 *
4187 * The SR calculation is:
4188 * watermark = (trunc(latency/line time)+1) * surface width *
4189 * bytes per pixel
4190 * where
4191 * line time = htotal / dotclock
4192 * surface width = hdisplay for normal plane and 64 for cursor
4193 * and latency is assumed to be high, as above.
4194 *
4195 * The final value programmed to the register should always be rounded up,
4196 * and include an extra 2 entries to account for clock crossings.
4197 *
4198 * We don't use the sprite, so we can ignore that. And on Crestline we have
4199 * to set the non-SR watermarks to 8.
4200 */
4201 void intel_update_watermarks(struct drm_crtc *crtc)
4202 {
4203 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4204
4205 if (dev_priv->display.update_wm)
4206 dev_priv->display.update_wm(crtc);
4207 }
4208
4209 void intel_update_sprite_watermarks(struct drm_plane *plane,
4210 struct drm_crtc *crtc,
4211 uint32_t sprite_width,
4212 uint32_t sprite_height,
4213 int pixel_size,
4214 bool enabled, bool scaled)
4215 {
4216 struct drm_i915_private *dev_priv = plane->dev->dev_private;
4217
4218 if (dev_priv->display.update_sprite_wm)
4219 dev_priv->display.update_sprite_wm(plane, crtc,
4220 sprite_width, sprite_height,
4221 pixel_size, enabled, scaled);
4222 }
4223
4224 /**
4225 * Lock protecting IPS related data structures
4226 */
4227 DEFINE_SPINLOCK(mchdev_lock);
4228
4229 /* Global for IPS driver to get at the current i915 device. Protected by
4230 * mchdev_lock. */
4231 static struct drm_i915_private *i915_mch_dev;
4232
4233 bool ironlake_set_drps(struct drm_device *dev, u8 val)
4234 {
4235 struct drm_i915_private *dev_priv = dev->dev_private;
4236 u16 rgvswctl;
4237
4238 assert_spin_locked(&mchdev_lock);
4239
4240 rgvswctl = I915_READ16(MEMSWCTL);
4241 if (rgvswctl & MEMCTL_CMD_STS) {
4242 DRM_DEBUG("gpu busy, RCS change rejected\n");
4243 return false; /* still busy with another command */
4244 }
4245
4246 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4247 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4248 I915_WRITE16(MEMSWCTL, rgvswctl);
4249 POSTING_READ16(MEMSWCTL);
4250
4251 rgvswctl |= MEMCTL_CMD_STS;
4252 I915_WRITE16(MEMSWCTL, rgvswctl);
4253
4254 return true;
4255 }
4256
4257 static void ironlake_enable_drps(struct drm_device *dev)
4258 {
4259 struct drm_i915_private *dev_priv = dev->dev_private;
4260 u32 rgvmodectl = I915_READ(MEMMODECTL);
4261 u8 fmax, fmin, fstart, vstart;
4262
4263 spin_lock_irq(&mchdev_lock);
4264
4265 /* Enable temp reporting */
4266 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4267 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4268
4269 /* 100ms RC evaluation intervals */
4270 I915_WRITE(RCUPEI, 100000);
4271 I915_WRITE(RCDNEI, 100000);
4272
4273 /* Set max/min thresholds to 90ms and 80ms respectively */
4274 I915_WRITE(RCBMAXAVG, 90000);
4275 I915_WRITE(RCBMINAVG, 80000);
4276
4277 I915_WRITE(MEMIHYST, 1);
4278
4279 /* Set up min, max, and cur for interrupt handling */
4280 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4281 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4282 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4283 MEMMODE_FSTART_SHIFT;
4284
4285 vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
4286 PXVFREQ_PX_SHIFT;
4287
4288 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4289 dev_priv->ips.fstart = fstart;
4290
4291 dev_priv->ips.max_delay = fstart;
4292 dev_priv->ips.min_delay = fmin;
4293 dev_priv->ips.cur_delay = fstart;
4294
4295 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4296 fmax, fmin, fstart);
4297
4298 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4299
4300 /*
4301 * Interrupts will be enabled in ironlake_irq_postinstall
4302 */
4303
4304 I915_WRITE(VIDSTART, vstart);
4305 POSTING_READ(VIDSTART);
4306
4307 rgvmodectl |= MEMMODE_SWMODE_EN;
4308 I915_WRITE(MEMMODECTL, rgvmodectl);
4309
4310 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
4311 DRM_ERROR("stuck trying to change perf mode\n");
4312 mdelay(1);
4313
4314 ironlake_set_drps(dev, fstart);
4315
4316 dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4317 I915_READ(DDREC) + I915_READ(CSIEC);
4318 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
4319 dev_priv->ips.last_count2 = I915_READ(GFXEC);
4320 dev_priv->ips.last_time2 = ktime_get_raw_ns();
4321
4322 spin_unlock_irq(&mchdev_lock);
4323 }
4324
4325 static void ironlake_disable_drps(struct drm_device *dev)
4326 {
4327 struct drm_i915_private *dev_priv = dev->dev_private;
4328 u16 rgvswctl;
4329
4330 spin_lock_irq(&mchdev_lock);
4331
4332 rgvswctl = I915_READ16(MEMSWCTL);
4333
4334 /* Ack interrupts, disable EFC interrupt */
4335 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4336 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4337 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4338 I915_WRITE(DEIIR, DE_PCU_EVENT);
4339 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4340
4341 /* Go back to the starting frequency */
4342 ironlake_set_drps(dev, dev_priv->ips.fstart);
4343 mdelay(1);
4344 rgvswctl |= MEMCTL_CMD_STS;
4345 I915_WRITE(MEMSWCTL, rgvswctl);
4346 mdelay(1);
4347
4348 spin_unlock_irq(&mchdev_lock);
4349 }
4350
4351 /* There's a funny hw issue where the hw returns all 0 when reading from
4352 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4353 * ourselves, instead of doing a rmw cycle (which might result in us clearing
4354 * all limits and the gpu stuck at whatever frequency it is at atm).
4355 */
4356 static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
4357 {
4358 u32 limits;
4359
4360 /* Only set the down limit when we've reached the lowest level to avoid
4361 * getting more interrupts, otherwise leave this clear. This prevents a
4362 * race in the hw when coming out of rc6: There's a tiny window where
4363 * the hw runs at the minimal clock before selecting the desired
4364 * frequency, if the down threshold expires in that window we will not
4365 * receive a down interrupt. */
4366 if (IS_GEN9(dev_priv->dev)) {
4367 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4368 if (val <= dev_priv->rps.min_freq_softlimit)
4369 limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4370 } else {
4371 limits = dev_priv->rps.max_freq_softlimit << 24;
4372 if (val <= dev_priv->rps.min_freq_softlimit)
4373 limits |= dev_priv->rps.min_freq_softlimit << 16;
4374 }
4375
4376 return limits;
4377 }
4378
4379 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4380 {
4381 int new_power;
4382 u32 threshold_up = 0, threshold_down = 0; /* in % */
4383 u32 ei_up = 0, ei_down = 0;
4384
4385 new_power = dev_priv->rps.power;
4386 switch (dev_priv->rps.power) {
4387 case LOW_POWER:
4388 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
4389 new_power = BETWEEN;
4390 break;
4391
4392 case BETWEEN:
4393 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
4394 new_power = LOW_POWER;
4395 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
4396 new_power = HIGH_POWER;
4397 break;
4398
4399 case HIGH_POWER:
4400 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
4401 new_power = BETWEEN;
4402 break;
4403 }
4404 /* Max/min bins are special */
4405 if (val <= dev_priv->rps.min_freq_softlimit)
4406 new_power = LOW_POWER;
4407 if (val >= dev_priv->rps.max_freq_softlimit)
4408 new_power = HIGH_POWER;
4409 if (new_power == dev_priv->rps.power)
4410 return;
4411
4412 /* Note the units here are not exactly 1us, but 1280ns. */
4413 switch (new_power) {
4414 case LOW_POWER:
4415 /* Upclock if more than 95% busy over 16ms */
4416 ei_up = 16000;
4417 threshold_up = 95;
4418
4419 /* Downclock if less than 85% busy over 32ms */
4420 ei_down = 32000;
4421 threshold_down = 85;
4422 break;
4423
4424 case BETWEEN:
4425 /* Upclock if more than 90% busy over 13ms */
4426 ei_up = 13000;
4427 threshold_up = 90;
4428
4429 /* Downclock if less than 75% busy over 32ms */
4430 ei_down = 32000;
4431 threshold_down = 75;
4432 break;
4433
4434 case HIGH_POWER:
4435 /* Upclock if more than 85% busy over 10ms */
4436 ei_up = 10000;
4437 threshold_up = 85;
4438
4439 /* Downclock if less than 60% busy over 32ms */
4440 ei_down = 32000;
4441 threshold_down = 60;
4442 break;
4443 }
4444
4445 I915_WRITE(GEN6_RP_UP_EI,
4446 GT_INTERVAL_FROM_US(dev_priv, ei_up));
4447 I915_WRITE(GEN6_RP_UP_THRESHOLD,
4448 GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100)));
4449
4450 I915_WRITE(GEN6_RP_DOWN_EI,
4451 GT_INTERVAL_FROM_US(dev_priv, ei_down));
4452 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4453 GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100)));
4454
4455 I915_WRITE(GEN6_RP_CONTROL,
4456 GEN6_RP_MEDIA_TURBO |
4457 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4458 GEN6_RP_MEDIA_IS_GFX |
4459 GEN6_RP_ENABLE |
4460 GEN6_RP_UP_BUSY_AVG |
4461 GEN6_RP_DOWN_IDLE_AVG);
4462
4463 dev_priv->rps.power = new_power;
4464 dev_priv->rps.up_threshold = threshold_up;
4465 dev_priv->rps.down_threshold = threshold_down;
4466 dev_priv->rps.last_adj = 0;
4467 }
4468
4469 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4470 {
4471 u32 mask = 0;
4472
4473 if (val > dev_priv->rps.min_freq_softlimit)
4474 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
4475 if (val < dev_priv->rps.max_freq_softlimit)
4476 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
4477
4478 mask &= dev_priv->pm_rps_events;
4479
4480 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
4481 }
4482
4483 /* gen6_set_rps is called to update the frequency request, but should also be
4484 * called when the range (min_delay and max_delay) is modified so that we can
4485 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
4486 static void gen6_set_rps(struct drm_device *dev, u8 val)
4487 {
4488 struct drm_i915_private *dev_priv = dev->dev_private;
4489
4490 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4491 if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0))
4492 return;
4493
4494 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4495 WARN_ON(val > dev_priv->rps.max_freq);
4496 WARN_ON(val < dev_priv->rps.min_freq);
4497
4498 /* min/max delay may still have been modified so be sure to
4499 * write the limits value.
4500 */
4501 if (val != dev_priv->rps.cur_freq) {
4502 gen6_set_rps_thresholds(dev_priv, val);
4503
4504 if (IS_GEN9(dev))
4505 I915_WRITE(GEN6_RPNSWREQ,
4506 GEN9_FREQUENCY(val));
4507 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4508 I915_WRITE(GEN6_RPNSWREQ,
4509 HSW_FREQUENCY(val));
4510 else
4511 I915_WRITE(GEN6_RPNSWREQ,
4512 GEN6_FREQUENCY(val) |
4513 GEN6_OFFSET(0) |
4514 GEN6_AGGRESSIVE_TURBO);
4515 }
4516
4517 /* Make sure we continue to get interrupts
4518 * until we hit the minimum or maximum frequencies.
4519 */
4520 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
4521 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4522
4523 POSTING_READ(GEN6_RPNSWREQ);
4524
4525 dev_priv->rps.cur_freq = val;
4526 trace_intel_gpu_freq_change(val * 50);
4527 }
4528
4529 static void valleyview_set_rps(struct drm_device *dev, u8 val)
4530 {
4531 struct drm_i915_private *dev_priv = dev->dev_private;
4532
4533 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4534 WARN_ON(val > dev_priv->rps.max_freq);
4535 WARN_ON(val < dev_priv->rps.min_freq);
4536
4537 if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1),
4538 "Odd GPU freq value\n"))
4539 val &= ~1;
4540
4541 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4542
4543 if (val != dev_priv->rps.cur_freq) {
4544 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
4545 if (!IS_CHERRYVIEW(dev_priv))
4546 gen6_set_rps_thresholds(dev_priv, val);
4547 }
4548
4549 dev_priv->rps.cur_freq = val;
4550 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4551 }
4552
4553 /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
4554 *
4555 * * If Gfx is Idle, then
4556 * 1. Forcewake Media well.
4557 * 2. Request idle freq.
4558 * 3. Release Forcewake of Media well.
4559 */
4560 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4561 {
4562 u32 val = dev_priv->rps.idle_freq;
4563
4564 if (dev_priv->rps.cur_freq <= val)
4565 return;
4566
4567 /* Wake up the media well, as that takes a lot less
4568 * power than the Render well. */
4569 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
4570 valleyview_set_rps(dev_priv->dev, val);
4571 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
4572 }
4573
4574 void gen6_rps_busy(struct drm_i915_private *dev_priv)
4575 {
4576 mutex_lock(&dev_priv->rps.hw_lock);
4577 if (dev_priv->rps.enabled) {
4578 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
4579 gen6_rps_reset_ei(dev_priv);
4580 I915_WRITE(GEN6_PMINTRMSK,
4581 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
4582 }
4583 mutex_unlock(&dev_priv->rps.hw_lock);
4584 }
4585
4586 void gen6_rps_idle(struct drm_i915_private *dev_priv)
4587 {
4588 struct drm_device *dev = dev_priv->dev;
4589
4590 mutex_lock(&dev_priv->rps.hw_lock);
4591 if (dev_priv->rps.enabled) {
4592 if (IS_VALLEYVIEW(dev))
4593 vlv_set_rps_idle(dev_priv);
4594 else
4595 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
4596 dev_priv->rps.last_adj = 0;
4597 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
4598 }
4599 mutex_unlock(&dev_priv->rps.hw_lock);
4600
4601 spin_lock(&dev_priv->rps.client_lock);
4602 while (!list_empty(&dev_priv->rps.clients))
4603 list_del_init(dev_priv->rps.clients.next);
4604 spin_unlock(&dev_priv->rps.client_lock);
4605 }
4606
4607 void gen6_rps_boost(struct drm_i915_private *dev_priv,
4608 struct intel_rps_client *rps,
4609 unsigned long submitted)
4610 {
4611 /* This is intentionally racy! We peek at the state here, then
4612 * validate inside the RPS worker.
4613 */
4614 if (!(dev_priv->mm.busy &&
4615 dev_priv->rps.enabled &&
4616 dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit))
4617 return;
4618
4619 /* Force a RPS boost (and don't count it against the client) if
4620 * the GPU is severely congested.
4621 */
4622 if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
4623 rps = NULL;
4624
4625 spin_lock(&dev_priv->rps.client_lock);
4626 if (rps == NULL || list_empty(&rps->link)) {
4627 spin_lock_irq(&dev_priv->irq_lock);
4628 if (dev_priv->rps.interrupts_enabled) {
4629 dev_priv->rps.client_boost = true;
4630 queue_work(dev_priv->wq, &dev_priv->rps.work);
4631 }
4632 spin_unlock_irq(&dev_priv->irq_lock);
4633
4634 if (rps != NULL) {
4635 list_add(&rps->link, &dev_priv->rps.clients);
4636 rps->boosts++;
4637 } else
4638 dev_priv->rps.boosts++;
4639 }
4640 spin_unlock(&dev_priv->rps.client_lock);
4641 }
4642
4643 void intel_set_rps(struct drm_device *dev, u8 val)
4644 {
4645 if (IS_VALLEYVIEW(dev))
4646 valleyview_set_rps(dev, val);
4647 else
4648 gen6_set_rps(dev, val);
4649 }
4650
4651 static void gen9_disable_rps(struct drm_device *dev)
4652 {
4653 struct drm_i915_private *dev_priv = dev->dev_private;
4654
4655 I915_WRITE(GEN6_RC_CONTROL, 0);
4656 I915_WRITE(GEN9_PG_ENABLE, 0);
4657 }
4658
4659 static void gen6_disable_rps(struct drm_device *dev)
4660 {
4661 struct drm_i915_private *dev_priv = dev->dev_private;
4662
4663 I915_WRITE(GEN6_RC_CONTROL, 0);
4664 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
4665 }
4666
4667 static void cherryview_disable_rps(struct drm_device *dev)
4668 {
4669 struct drm_i915_private *dev_priv = dev->dev_private;
4670
4671 I915_WRITE(GEN6_RC_CONTROL, 0);
4672 }
4673
4674 static void valleyview_disable_rps(struct drm_device *dev)
4675 {
4676 struct drm_i915_private *dev_priv = dev->dev_private;
4677
4678 /* we're doing forcewake before Disabling RC6,
4679 * This what the BIOS expects when going into suspend */
4680 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4681
4682 I915_WRITE(GEN6_RC_CONTROL, 0);
4683
4684 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4685 }
4686
4687 static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
4688 {
4689 if (IS_VALLEYVIEW(dev)) {
4690 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
4691 mode = GEN6_RC_CTL_RC6_ENABLE;
4692 else
4693 mode = 0;
4694 }
4695 if (HAS_RC6p(dev))
4696 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
4697 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
4698 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
4699 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
4700
4701 else
4702 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
4703 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off");
4704 }
4705
4706 static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
4707 {
4708 /* No RC6 before Ironlake and code is gone for ilk. */
4709 if (INTEL_INFO(dev)->gen < 6)
4710 return 0;
4711
4712 /* Respect the kernel parameter if it is set */
4713 if (enable_rc6 >= 0) {
4714 int mask;
4715
4716 if (HAS_RC6p(dev))
4717 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
4718 INTEL_RC6pp_ENABLE;
4719 else
4720 mask = INTEL_RC6_ENABLE;
4721
4722 if ((enable_rc6 & mask) != enable_rc6)
4723 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
4724 enable_rc6 & mask, enable_rc6, mask);
4725
4726 return enable_rc6 & mask;
4727 }
4728
4729 if (IS_IVYBRIDGE(dev))
4730 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
4731
4732 return INTEL_RC6_ENABLE;
4733 }
4734
4735 int intel_enable_rc6(const struct drm_device *dev)
4736 {
4737 return i915.enable_rc6;
4738 }
4739
4740 static void gen6_init_rps_frequencies(struct drm_device *dev)
4741 {
4742 struct drm_i915_private *dev_priv = dev->dev_private;
4743 uint32_t rp_state_cap;
4744 u32 ddcc_status = 0;
4745 int ret;
4746
4747 /* All of these values are in units of 50MHz */
4748 dev_priv->rps.cur_freq = 0;
4749 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
4750 if (IS_BROXTON(dev)) {
4751 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
4752 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
4753 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
4754 dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff;
4755 } else {
4756 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
4757 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
4758 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
4759 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
4760 }
4761
4762 /* hw_max = RP0 until we check for overclocking */
4763 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
4764
4765 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
4766 if (IS_HASWELL(dev) || IS_BROADWELL(dev) || IS_SKYLAKE(dev)) {
4767 ret = sandybridge_pcode_read(dev_priv,
4768 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
4769 &ddcc_status);
4770 if (0 == ret)
4771 dev_priv->rps.efficient_freq =
4772 clamp_t(u8,
4773 ((ddcc_status >> 8) & 0xff),
4774 dev_priv->rps.min_freq,
4775 dev_priv->rps.max_freq);
4776 }
4777
4778 if (IS_SKYLAKE(dev)) {
4779 /* Store the frequency values in 16.66 MHZ units, which is
4780 the natural hardware unit for SKL */
4781 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
4782 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
4783 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
4784 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
4785 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
4786 }
4787
4788 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
4789
4790 /* Preserve min/max settings in case of re-init */
4791 if (dev_priv->rps.max_freq_softlimit == 0)
4792 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4793
4794 if (dev_priv->rps.min_freq_softlimit == 0) {
4795 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4796 dev_priv->rps.min_freq_softlimit =
4797 max_t(int, dev_priv->rps.efficient_freq,
4798 intel_freq_opcode(dev_priv, 450));
4799 else
4800 dev_priv->rps.min_freq_softlimit =
4801 dev_priv->rps.min_freq;
4802 }
4803 }
4804
4805 /* See the Gen9_GT_PM_Programming_Guide doc for the below */
4806 static void gen9_enable_rps(struct drm_device *dev)
4807 {
4808 struct drm_i915_private *dev_priv = dev->dev_private;
4809
4810 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4811
4812 gen6_init_rps_frequencies(dev);
4813
4814 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4815 if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) {
4816 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4817 return;
4818 }
4819
4820 /* Program defaults and thresholds for RPS*/
4821 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4822 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
4823
4824 /* 1 second timeout*/
4825 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
4826 GT_INTERVAL_FROM_US(dev_priv, 1000000));
4827
4828 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
4829
4830 /* Leaning on the below call to gen6_set_rps to program/setup the
4831 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
4832 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
4833 dev_priv->rps.power = HIGH_POWER; /* force a reset */
4834 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
4835
4836 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4837 }
4838
4839 static void gen9_enable_rc6(struct drm_device *dev)
4840 {
4841 struct drm_i915_private *dev_priv = dev->dev_private;
4842 struct intel_engine_cs *ring;
4843 uint32_t rc6_mask = 0;
4844 int unused;
4845
4846 /* 1a: Software RC state - RC0 */
4847 I915_WRITE(GEN6_RC_STATE, 0);
4848
4849 /* 1b: Get forcewake during program sequence. Although the driver
4850 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4851 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4852
4853 /* 2a: Disable RC states. */
4854 I915_WRITE(GEN6_RC_CONTROL, 0);
4855
4856 /* 2b: Program RC6 thresholds.*/
4857
4858 /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
4859 if (IS_SKYLAKE(dev) && !((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) &&
4860 (INTEL_REVID(dev) <= SKL_REVID_E0)))
4861 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
4862 else
4863 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
4864 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4865 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4866 for_each_ring(ring, dev_priv, unused)
4867 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4868
4869 if (HAS_GUC_UCODE(dev))
4870 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
4871
4872 I915_WRITE(GEN6_RC_SLEEP, 0);
4873 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
4874
4875 /* 2c: Program Coarse Power Gating Policies. */
4876 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
4877 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
4878
4879 /* 3a: Enable RC6 */
4880 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4881 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4882 DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4883 "on" : "off");
4884
4885 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_D0) ||
4886 (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A0))
4887 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4888 GEN7_RC_CTL_TO_MODE |
4889 rc6_mask);
4890 else
4891 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4892 GEN6_RC_CTL_EI_MODE(1) |
4893 rc6_mask);
4894
4895 /*
4896 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
4897 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
4898 */
4899 if ((IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) ||
4900 ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && (INTEL_REVID(dev) <= SKL_REVID_E0)))
4901 I915_WRITE(GEN9_PG_ENABLE, 0);
4902 else
4903 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4904 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
4905
4906 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4907
4908 }
4909
4910 static void gen8_enable_rps(struct drm_device *dev)
4911 {
4912 struct drm_i915_private *dev_priv = dev->dev_private;
4913 struct intel_engine_cs *ring;
4914 uint32_t rc6_mask = 0;
4915 int unused;
4916
4917 /* 1a: Software RC state - RC0 */
4918 I915_WRITE(GEN6_RC_STATE, 0);
4919
4920 /* 1c & 1d: Get forcewake during program sequence. Although the driver
4921 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4922 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4923
4924 /* 2a: Disable RC states. */
4925 I915_WRITE(GEN6_RC_CONTROL, 0);
4926
4927 /* Initialize rps frequencies */
4928 gen6_init_rps_frequencies(dev);
4929
4930 /* 2b: Program RC6 thresholds.*/
4931 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4932 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4933 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4934 for_each_ring(ring, dev_priv, unused)
4935 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4936 I915_WRITE(GEN6_RC_SLEEP, 0);
4937 if (IS_BROADWELL(dev))
4938 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
4939 else
4940 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
4941
4942 /* 3: Enable RC6 */
4943 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4944 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4945 intel_print_rc6_info(dev, rc6_mask);
4946 if (IS_BROADWELL(dev))
4947 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4948 GEN7_RC_CTL_TO_MODE |
4949 rc6_mask);
4950 else
4951 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4952 GEN6_RC_CTL_EI_MODE(1) |
4953 rc6_mask);
4954
4955 /* 4 Program defaults and thresholds for RPS*/
4956 I915_WRITE(GEN6_RPNSWREQ,
4957 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4958 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4959 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4960 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
4961 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
4962
4963 /* Docs recommend 900MHz, and 300 MHz respectively */
4964 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
4965 dev_priv->rps.max_freq_softlimit << 24 |
4966 dev_priv->rps.min_freq_softlimit << 16);
4967
4968 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
4969 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
4970 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
4971 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
4972
4973 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4974
4975 /* 5: Enable RPS */
4976 I915_WRITE(GEN6_RP_CONTROL,
4977 GEN6_RP_MEDIA_TURBO |
4978 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4979 GEN6_RP_MEDIA_IS_GFX |
4980 GEN6_RP_ENABLE |
4981 GEN6_RP_UP_BUSY_AVG |
4982 GEN6_RP_DOWN_IDLE_AVG);
4983
4984 /* 6: Ring frequency + overclocking (our driver does this later */
4985
4986 dev_priv->rps.power = HIGH_POWER; /* force a reset */
4987 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
4988
4989 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4990 }
4991
4992 static void gen6_enable_rps(struct drm_device *dev)
4993 {
4994 struct drm_i915_private *dev_priv = dev->dev_private;
4995 struct intel_engine_cs *ring;
4996 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
4997 u32 gtfifodbg;
4998 int rc6_mode;
4999 int i, ret;
5000
5001 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5002
5003 /* Here begins a magic sequence of register writes to enable
5004 * auto-downclocking.
5005 *
5006 * Perhaps there might be some value in exposing these to
5007 * userspace...
5008 */
5009 I915_WRITE(GEN6_RC_STATE, 0);
5010
5011 /* Clear the DBG now so we don't confuse earlier errors */
5012 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
5013 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
5014 I915_WRITE(GTFIFODBG, gtfifodbg);
5015 }
5016
5017 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5018
5019 /* Initialize rps frequencies */
5020 gen6_init_rps_frequencies(dev);
5021
5022 /* disable the counters and set deterministic thresholds */
5023 I915_WRITE(GEN6_RC_CONTROL, 0);
5024
5025 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
5026 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
5027 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
5028 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5029 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5030
5031 for_each_ring(ring, dev_priv, i)
5032 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5033
5034 I915_WRITE(GEN6_RC_SLEEP, 0);
5035 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
5036 if (IS_IVYBRIDGE(dev))
5037 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
5038 else
5039 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
5040 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
5041 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
5042
5043 /* Check if we are enabling RC6 */
5044 rc6_mode = intel_enable_rc6(dev_priv->dev);
5045 if (rc6_mode & INTEL_RC6_ENABLE)
5046 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
5047
5048 /* We don't use those on Haswell */
5049 if (!IS_HASWELL(dev)) {
5050 if (rc6_mode & INTEL_RC6p_ENABLE)
5051 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
5052
5053 if (rc6_mode & INTEL_RC6pp_ENABLE)
5054 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
5055 }
5056
5057 intel_print_rc6_info(dev, rc6_mask);
5058
5059 I915_WRITE(GEN6_RC_CONTROL,
5060 rc6_mask |
5061 GEN6_RC_CTL_EI_MODE(1) |
5062 GEN6_RC_CTL_HW_ENABLE);
5063
5064 /* Power down if completely idle for over 50ms */
5065 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
5066 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5067
5068 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
5069 if (ret)
5070 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
5071
5072 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
5073 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
5074 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
5075 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
5076 (pcu_mbox & 0xff) * 50);
5077 dev_priv->rps.max_freq = pcu_mbox & 0xff;
5078 }
5079
5080 dev_priv->rps.power = HIGH_POWER; /* force a reset */
5081 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
5082
5083 rc6vids = 0;
5084 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
5085 if (IS_GEN6(dev) && ret) {
5086 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
5087 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
5088 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5089 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5090 rc6vids &= 0xffff00;
5091 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5092 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5093 if (ret)
5094 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5095 }
5096
5097 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5098 }
5099
5100 static void __gen6_update_ring_freq(struct drm_device *dev)
5101 {
5102 struct drm_i915_private *dev_priv = dev->dev_private;
5103 int min_freq = 15;
5104 unsigned int gpu_freq;
5105 unsigned int max_ia_freq, min_ring_freq;
5106 unsigned int max_gpu_freq, min_gpu_freq;
5107 int scaling_factor = 180;
5108 struct cpufreq_policy *policy;
5109
5110 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5111
5112 policy = cpufreq_cpu_get(0);
5113 if (policy) {
5114 max_ia_freq = policy->cpuinfo.max_freq;
5115 cpufreq_cpu_put(policy);
5116 } else {
5117 /*
5118 * Default to measured freq if none found, PCU will ensure we
5119 * don't go over
5120 */
5121 max_ia_freq = tsc_khz;
5122 }
5123
5124 /* Convert from kHz to MHz */
5125 max_ia_freq /= 1000;
5126
5127 min_ring_freq = I915_READ(DCLK) & 0xf;
5128 /* convert DDR frequency from units of 266.6MHz to bandwidth */
5129 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
5130
5131 if (IS_SKYLAKE(dev)) {
5132 /* Convert GT frequency to 50 HZ units */
5133 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5134 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5135 } else {
5136 min_gpu_freq = dev_priv->rps.min_freq;
5137 max_gpu_freq = dev_priv->rps.max_freq;
5138 }
5139
5140 /*
5141 * For each potential GPU frequency, load a ring frequency we'd like
5142 * to use for memory access. We do this by specifying the IA frequency
5143 * the PCU should use as a reference to determine the ring frequency.
5144 */
5145 for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5146 int diff = max_gpu_freq - gpu_freq;
5147 unsigned int ia_freq = 0, ring_freq = 0;
5148
5149 if (IS_SKYLAKE(dev)) {
5150 /*
5151 * ring_freq = 2 * GT. ring_freq is in 100MHz units
5152 * No floor required for ring frequency on SKL.
5153 */
5154 ring_freq = gpu_freq;
5155 } else if (INTEL_INFO(dev)->gen >= 8) {
5156 /* max(2 * GT, DDR). NB: GT is 50MHz units */
5157 ring_freq = max(min_ring_freq, gpu_freq);
5158 } else if (IS_HASWELL(dev)) {
5159 ring_freq = mult_frac(gpu_freq, 5, 4);
5160 ring_freq = max(min_ring_freq, ring_freq);
5161 /* leave ia_freq as the default, chosen by cpufreq */
5162 } else {
5163 /* On older processors, there is no separate ring
5164 * clock domain, so in order to boost the bandwidth
5165 * of the ring, we need to upclock the CPU (ia_freq).
5166 *
5167 * For GPU frequencies less than 750MHz,
5168 * just use the lowest ring freq.
5169 */
5170 if (gpu_freq < min_freq)
5171 ia_freq = 800;
5172 else
5173 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5174 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5175 }
5176
5177 sandybridge_pcode_write(dev_priv,
5178 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
5179 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5180 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5181 gpu_freq);
5182 }
5183 }
5184
5185 void gen6_update_ring_freq(struct drm_device *dev)
5186 {
5187 struct drm_i915_private *dev_priv = dev->dev_private;
5188
5189 if (!HAS_CORE_RING_FREQ(dev))
5190 return;
5191
5192 mutex_lock(&dev_priv->rps.hw_lock);
5193 __gen6_update_ring_freq(dev);
5194 mutex_unlock(&dev_priv->rps.hw_lock);
5195 }
5196
5197 static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
5198 {
5199 struct drm_device *dev = dev_priv->dev;
5200 u32 val, rp0;
5201
5202 if (dev->pdev->revision >= 0x20) {
5203 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5204
5205 switch (INTEL_INFO(dev)->eu_total) {
5206 case 8:
5207 /* (2 * 4) config */
5208 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5209 break;
5210 case 12:
5211 /* (2 * 6) config */
5212 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5213 break;
5214 case 16:
5215 /* (2 * 8) config */
5216 default:
5217 /* Setting (2 * 8) Min RP0 for any other combination */
5218 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5219 break;
5220 }
5221 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5222 } else {
5223 /* For pre-production hardware */
5224 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
5225 rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
5226 PUNIT_GPU_STATUS_MAX_FREQ_MASK;
5227 }
5228 return rp0;
5229 }
5230
5231 static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5232 {
5233 u32 val, rpe;
5234
5235 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5236 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5237
5238 return rpe;
5239 }
5240
5241 static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5242 {
5243 struct drm_device *dev = dev_priv->dev;
5244 u32 val, rp1;
5245
5246 if (dev->pdev->revision >= 0x20) {
5247 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5248 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5249 } else {
5250 /* For pre-production hardware */
5251 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5252 rp1 = ((val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
5253 PUNIT_GPU_STATUS_MAX_FREQ_MASK);
5254 }
5255 return rp1;
5256 }
5257
5258 static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5259 {
5260 u32 val, rp1;
5261
5262 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5263
5264 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5265
5266 return rp1;
5267 }
5268
5269 static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
5270 {
5271 u32 val, rp0;
5272
5273 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5274
5275 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5276 /* Clamp to max */
5277 rp0 = min_t(u32, rp0, 0xea);
5278
5279 return rp0;
5280 }
5281
5282 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5283 {
5284 u32 val, rpe;
5285
5286 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
5287 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
5288 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
5289 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5290
5291 return rpe;
5292 }
5293
5294 static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
5295 {
5296 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5297 }
5298
5299 /* Check that the pctx buffer wasn't move under us. */
5300 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5301 {
5302 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5303
5304 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5305 dev_priv->vlv_pctx->stolen->start);
5306 }
5307
5308
5309 /* Check that the pcbr address is not empty. */
5310 static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5311 {
5312 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5313
5314 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5315 }
5316
5317 static void cherryview_setup_pctx(struct drm_device *dev)
5318 {
5319 struct drm_i915_private *dev_priv = dev->dev_private;
5320 unsigned long pctx_paddr, paddr;
5321 struct i915_gtt *gtt = &dev_priv->gtt;
5322 u32 pcbr;
5323 int pctx_size = 32*1024;
5324
5325 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
5326
5327 pcbr = I915_READ(VLV_PCBR);
5328 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
5329 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5330 paddr = (dev_priv->mm.stolen_base +
5331 (gtt->stolen_size - pctx_size));
5332
5333 pctx_paddr = (paddr & (~4095));
5334 I915_WRITE(VLV_PCBR, pctx_paddr);
5335 }
5336
5337 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5338 }
5339
5340 static void valleyview_setup_pctx(struct drm_device *dev)
5341 {
5342 struct drm_i915_private *dev_priv = dev->dev_private;
5343 struct drm_i915_gem_object *pctx;
5344 unsigned long pctx_paddr;
5345 u32 pcbr;
5346 int pctx_size = 24*1024;
5347
5348 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
5349
5350 pcbr = I915_READ(VLV_PCBR);
5351 if (pcbr) {
5352 /* BIOS set it up already, grab the pre-alloc'd space */
5353 int pcbr_offset;
5354
5355 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
5356 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
5357 pcbr_offset,
5358 I915_GTT_OFFSET_NONE,
5359 pctx_size);
5360 goto out;
5361 }
5362
5363 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5364
5365 /*
5366 * From the Gunit register HAS:
5367 * The Gfx driver is expected to program this register and ensure
5368 * proper allocation within Gfx stolen memory. For example, this
5369 * register should be programmed such than the PCBR range does not
5370 * overlap with other ranges, such as the frame buffer, protected
5371 * memory, or any other relevant ranges.
5372 */
5373 pctx = i915_gem_object_create_stolen(dev, pctx_size);
5374 if (!pctx) {
5375 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
5376 return;
5377 }
5378
5379 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5380 I915_WRITE(VLV_PCBR, pctx_paddr);
5381
5382 out:
5383 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5384 dev_priv->vlv_pctx = pctx;
5385 }
5386
5387 static void valleyview_cleanup_pctx(struct drm_device *dev)
5388 {
5389 struct drm_i915_private *dev_priv = dev->dev_private;
5390
5391 if (WARN_ON(!dev_priv->vlv_pctx))
5392 return;
5393
5394 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
5395 dev_priv->vlv_pctx = NULL;
5396 }
5397
5398 static void valleyview_init_gt_powersave(struct drm_device *dev)
5399 {
5400 struct drm_i915_private *dev_priv = dev->dev_private;
5401 u32 val;
5402
5403 valleyview_setup_pctx(dev);
5404
5405 mutex_lock(&dev_priv->rps.hw_lock);
5406
5407 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5408 switch ((val >> 6) & 3) {
5409 case 0:
5410 case 1:
5411 dev_priv->mem_freq = 800;
5412 break;
5413 case 2:
5414 dev_priv->mem_freq = 1066;
5415 break;
5416 case 3:
5417 dev_priv->mem_freq = 1333;
5418 break;
5419 }
5420 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5421
5422 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5423 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5424 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5425 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5426 dev_priv->rps.max_freq);
5427
5428 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5429 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5430 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5431 dev_priv->rps.efficient_freq);
5432
5433 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5434 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
5435 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5436 dev_priv->rps.rp1_freq);
5437
5438 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5439 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5440 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5441 dev_priv->rps.min_freq);
5442
5443 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5444
5445 /* Preserve min/max settings in case of re-init */
5446 if (dev_priv->rps.max_freq_softlimit == 0)
5447 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5448
5449 if (dev_priv->rps.min_freq_softlimit == 0)
5450 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5451
5452 mutex_unlock(&dev_priv->rps.hw_lock);
5453 }
5454
5455 static void cherryview_init_gt_powersave(struct drm_device *dev)
5456 {
5457 struct drm_i915_private *dev_priv = dev->dev_private;
5458 u32 val;
5459
5460 cherryview_setup_pctx(dev);
5461
5462 mutex_lock(&dev_priv->rps.hw_lock);
5463
5464 mutex_lock(&dev_priv->sb_lock);
5465 val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
5466 mutex_unlock(&dev_priv->sb_lock);
5467
5468 switch ((val >> 2) & 0x7) {
5469 case 0:
5470 case 1:
5471 dev_priv->rps.cz_freq = 200;
5472 dev_priv->mem_freq = 1600;
5473 break;
5474 case 2:
5475 dev_priv->rps.cz_freq = 267;
5476 dev_priv->mem_freq = 1600;
5477 break;
5478 case 3:
5479 dev_priv->rps.cz_freq = 333;
5480 dev_priv->mem_freq = 2000;
5481 break;
5482 case 4:
5483 dev_priv->rps.cz_freq = 320;
5484 dev_priv->mem_freq = 1600;
5485 break;
5486 case 5:
5487 dev_priv->rps.cz_freq = 400;
5488 dev_priv->mem_freq = 1600;
5489 break;
5490 }
5491 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5492
5493 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5494 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5495 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5496 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5497 dev_priv->rps.max_freq);
5498
5499 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5500 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5501 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5502 dev_priv->rps.efficient_freq);
5503
5504 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5505 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
5506 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5507 dev_priv->rps.rp1_freq);
5508
5509 /* PUnit validated range is only [RPe, RP0] */
5510 dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
5511 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5512 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5513 dev_priv->rps.min_freq);
5514
5515 WARN_ONCE((dev_priv->rps.max_freq |
5516 dev_priv->rps.efficient_freq |
5517 dev_priv->rps.rp1_freq |
5518 dev_priv->rps.min_freq) & 1,
5519 "Odd GPU freq values\n");
5520
5521 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5522
5523 /* Preserve min/max settings in case of re-init */
5524 if (dev_priv->rps.max_freq_softlimit == 0)
5525 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5526
5527 if (dev_priv->rps.min_freq_softlimit == 0)
5528 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5529
5530 mutex_unlock(&dev_priv->rps.hw_lock);
5531 }
5532
5533 static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
5534 {
5535 valleyview_cleanup_pctx(dev);
5536 }
5537
5538 static void cherryview_enable_rps(struct drm_device *dev)
5539 {
5540 struct drm_i915_private *dev_priv = dev->dev_private;
5541 struct intel_engine_cs *ring;
5542 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
5543 int i;
5544
5545 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5546
5547 gtfifodbg = I915_READ(GTFIFODBG);
5548 if (gtfifodbg) {
5549 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5550 gtfifodbg);
5551 I915_WRITE(GTFIFODBG, gtfifodbg);
5552 }
5553
5554 cherryview_check_pctx(dev_priv);
5555
5556 /* 1a & 1b: Get forcewake during program sequence. Although the driver
5557 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5558 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5559
5560 /* Disable RC states. */
5561 I915_WRITE(GEN6_RC_CONTROL, 0);
5562
5563 /* 2a: Program RC6 thresholds.*/
5564 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5565 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5566 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5567
5568 for_each_ring(ring, dev_priv, i)
5569 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5570 I915_WRITE(GEN6_RC_SLEEP, 0);
5571
5572 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
5573 I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
5574
5575 /* allows RC6 residency counter to work */
5576 I915_WRITE(VLV_COUNTER_CONTROL,
5577 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
5578 VLV_MEDIA_RC6_COUNT_EN |
5579 VLV_RENDER_RC6_COUNT_EN));
5580
5581 /* For now we assume BIOS is allocating and populating the PCBR */
5582 pcbr = I915_READ(VLV_PCBR);
5583
5584 /* 3: Enable RC6 */
5585 if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
5586 (pcbr >> VLV_PCBR_ADDR_SHIFT))
5587 rc6_mode = GEN7_RC_CTL_TO_MODE;
5588
5589 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5590
5591 /* 4 Program defaults and thresholds for RPS*/
5592 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
5593 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5594 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5595 I915_WRITE(GEN6_RP_UP_EI, 66000);
5596 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5597
5598 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5599
5600 /* 5: Enable RPS */
5601 I915_WRITE(GEN6_RP_CONTROL,
5602 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5603 GEN6_RP_MEDIA_IS_GFX |
5604 GEN6_RP_ENABLE |
5605 GEN6_RP_UP_BUSY_AVG |
5606 GEN6_RP_DOWN_IDLE_AVG);
5607
5608 /* Setting Fixed Bias */
5609 val = VLV_OVERRIDE_EN |
5610 VLV_SOC_TDP_EN |
5611 CHV_BIAS_CPU_50_SOC_50;
5612 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5613
5614 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5615
5616 /* RPS code assumes GPLL is used */
5617 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5618
5619 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
5620 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5621
5622 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5623 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5624 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
5625 dev_priv->rps.cur_freq);
5626
5627 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5628 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5629 dev_priv->rps.efficient_freq);
5630
5631 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5632
5633 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5634 }
5635
5636 static void valleyview_enable_rps(struct drm_device *dev)
5637 {
5638 struct drm_i915_private *dev_priv = dev->dev_private;
5639 struct intel_engine_cs *ring;
5640 u32 gtfifodbg, val, rc6_mode = 0;
5641 int i;
5642
5643 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5644
5645 valleyview_check_pctx(dev_priv);
5646
5647 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
5648 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5649 gtfifodbg);
5650 I915_WRITE(GTFIFODBG, gtfifodbg);
5651 }
5652
5653 /* If VLV, Forcewake all wells, else re-direct to regular path */
5654 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5655
5656 /* Disable RC states. */
5657 I915_WRITE(GEN6_RC_CONTROL, 0);
5658
5659 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
5660 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5661 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5662 I915_WRITE(GEN6_RP_UP_EI, 66000);
5663 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5664
5665 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5666
5667 I915_WRITE(GEN6_RP_CONTROL,
5668 GEN6_RP_MEDIA_TURBO |
5669 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5670 GEN6_RP_MEDIA_IS_GFX |
5671 GEN6_RP_ENABLE |
5672 GEN6_RP_UP_BUSY_AVG |
5673 GEN6_RP_DOWN_IDLE_CONT);
5674
5675 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
5676 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5677 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5678
5679 for_each_ring(ring, dev_priv, i)
5680 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5681
5682 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
5683
5684 /* allows RC6 residency counter to work */
5685 I915_WRITE(VLV_COUNTER_CONTROL,
5686 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
5687 VLV_RENDER_RC0_COUNT_EN |
5688 VLV_MEDIA_RC6_COUNT_EN |
5689 VLV_RENDER_RC6_COUNT_EN));
5690
5691 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
5692 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
5693
5694 intel_print_rc6_info(dev, rc6_mode);
5695
5696 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5697
5698 /* Setting Fixed Bias */
5699 val = VLV_OVERRIDE_EN |
5700 VLV_SOC_TDP_EN |
5701 VLV_BIAS_CPU_125_SOC_875;
5702 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5703
5704 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5705
5706 /* RPS code assumes GPLL is used */
5707 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5708
5709 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
5710 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5711
5712 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5713 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5714 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
5715 dev_priv->rps.cur_freq);
5716
5717 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5718 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5719 dev_priv->rps.efficient_freq);
5720
5721 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5722
5723 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5724 }
5725
5726 static unsigned long intel_pxfreq(u32 vidfreq)
5727 {
5728 unsigned long freq;
5729 int div = (vidfreq & 0x3f0000) >> 16;
5730 int post = (vidfreq & 0x3000) >> 12;
5731 int pre = (vidfreq & 0x7);
5732
5733 if (!pre)
5734 return 0;
5735
5736 freq = ((div * 133333) / ((1<<post) * pre));
5737
5738 return freq;
5739 }
5740
5741 static const struct cparams {
5742 u16 i;
5743 u16 t;
5744 u16 m;
5745 u16 c;
5746 } cparams[] = {
5747 { 1, 1333, 301, 28664 },
5748 { 1, 1066, 294, 24460 },
5749 { 1, 800, 294, 25192 },
5750 { 0, 1333, 276, 27605 },
5751 { 0, 1066, 276, 27605 },
5752 { 0, 800, 231, 23784 },
5753 };
5754
5755 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
5756 {
5757 u64 total_count, diff, ret;
5758 u32 count1, count2, count3, m = 0, c = 0;
5759 unsigned long now = jiffies_to_msecs(jiffies), diff1;
5760 int i;
5761
5762 assert_spin_locked(&mchdev_lock);
5763
5764 diff1 = now - dev_priv->ips.last_time1;
5765
5766 /* Prevent division-by-zero if we are asking too fast.
5767 * Also, we don't get interesting results if we are polling
5768 * faster than once in 10ms, so just return the saved value
5769 * in such cases.
5770 */
5771 if (diff1 <= 10)
5772 return dev_priv->ips.chipset_power;
5773
5774 count1 = I915_READ(DMIEC);
5775 count2 = I915_READ(DDREC);
5776 count3 = I915_READ(CSIEC);
5777
5778 total_count = count1 + count2 + count3;
5779
5780 /* FIXME: handle per-counter overflow */
5781 if (total_count < dev_priv->ips.last_count1) {
5782 diff = ~0UL - dev_priv->ips.last_count1;
5783 diff += total_count;
5784 } else {
5785 diff = total_count - dev_priv->ips.last_count1;
5786 }
5787
5788 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
5789 if (cparams[i].i == dev_priv->ips.c_m &&
5790 cparams[i].t == dev_priv->ips.r_t) {
5791 m = cparams[i].m;
5792 c = cparams[i].c;
5793 break;
5794 }
5795 }
5796
5797 diff = div_u64(diff, diff1);
5798 ret = ((m * diff) + c);
5799 ret = div_u64(ret, 10);
5800
5801 dev_priv->ips.last_count1 = total_count;
5802 dev_priv->ips.last_time1 = now;
5803
5804 dev_priv->ips.chipset_power = ret;
5805
5806 return ret;
5807 }
5808
5809 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
5810 {
5811 struct drm_device *dev = dev_priv->dev;
5812 unsigned long val;
5813
5814 if (INTEL_INFO(dev)->gen != 5)
5815 return 0;
5816
5817 spin_lock_irq(&mchdev_lock);
5818
5819 val = __i915_chipset_val(dev_priv);
5820
5821 spin_unlock_irq(&mchdev_lock);
5822
5823 return val;
5824 }
5825
5826 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
5827 {
5828 unsigned long m, x, b;
5829 u32 tsfs;
5830
5831 tsfs = I915_READ(TSFS);
5832
5833 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
5834 x = I915_READ8(TR1);
5835
5836 b = tsfs & TSFS_INTR_MASK;
5837
5838 return ((m * x) / 127) - b;
5839 }
5840
5841 static int _pxvid_to_vd(u8 pxvid)
5842 {
5843 if (pxvid == 0)
5844 return 0;
5845
5846 if (pxvid >= 8 && pxvid < 31)
5847 pxvid = 31;
5848
5849 return (pxvid + 2) * 125;
5850 }
5851
5852 static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
5853 {
5854 struct drm_device *dev = dev_priv->dev;
5855 const int vd = _pxvid_to_vd(pxvid);
5856 const int vm = vd - 1125;
5857
5858 if (INTEL_INFO(dev)->is_mobile)
5859 return vm > 0 ? vm : 0;
5860
5861 return vd;
5862 }
5863
5864 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
5865 {
5866 u64 now, diff, diffms;
5867 u32 count;
5868
5869 assert_spin_locked(&mchdev_lock);
5870
5871 now = ktime_get_raw_ns();
5872 diffms = now - dev_priv->ips.last_time2;
5873 do_div(diffms, NSEC_PER_MSEC);
5874
5875 /* Don't divide by 0 */
5876 if (!diffms)
5877 return;
5878
5879 count = I915_READ(GFXEC);
5880
5881 if (count < dev_priv->ips.last_count2) {
5882 diff = ~0UL - dev_priv->ips.last_count2;
5883 diff += count;
5884 } else {
5885 diff = count - dev_priv->ips.last_count2;
5886 }
5887
5888 dev_priv->ips.last_count2 = count;
5889 dev_priv->ips.last_time2 = now;
5890
5891 /* More magic constants... */
5892 diff = diff * 1181;
5893 diff = div_u64(diff, diffms * 10);
5894 dev_priv->ips.gfx_power = diff;
5895 }
5896
5897 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
5898 {
5899 struct drm_device *dev = dev_priv->dev;
5900
5901 if (INTEL_INFO(dev)->gen != 5)
5902 return;
5903
5904 spin_lock_irq(&mchdev_lock);
5905
5906 __i915_update_gfx_val(dev_priv);
5907
5908 spin_unlock_irq(&mchdev_lock);
5909 }
5910
5911 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
5912 {
5913 unsigned long t, corr, state1, corr2, state2;
5914 u32 pxvid, ext_v;
5915
5916 assert_spin_locked(&mchdev_lock);
5917
5918 pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
5919 pxvid = (pxvid >> 24) & 0x7f;
5920 ext_v = pvid_to_extvid(dev_priv, pxvid);
5921
5922 state1 = ext_v;
5923
5924 t = i915_mch_val(dev_priv);
5925
5926 /* Revel in the empirically derived constants */
5927
5928 /* Correction factor in 1/100000 units */
5929 if (t > 80)
5930 corr = ((t * 2349) + 135940);
5931 else if (t >= 50)
5932 corr = ((t * 964) + 29317);
5933 else /* < 50 */
5934 corr = ((t * 301) + 1004);
5935
5936 corr = corr * ((150142 * state1) / 10000 - 78642);
5937 corr /= 100000;
5938 corr2 = (corr * dev_priv->ips.corr);
5939
5940 state2 = (corr2 * state1) / 10000;
5941 state2 /= 100; /* convert to mW */
5942
5943 __i915_update_gfx_val(dev_priv);
5944
5945 return dev_priv->ips.gfx_power + state2;
5946 }
5947
5948 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
5949 {
5950 struct drm_device *dev = dev_priv->dev;
5951 unsigned long val;
5952
5953 if (INTEL_INFO(dev)->gen != 5)
5954 return 0;
5955
5956 spin_lock_irq(&mchdev_lock);
5957
5958 val = __i915_gfx_val(dev_priv);
5959
5960 spin_unlock_irq(&mchdev_lock);
5961
5962 return val;
5963 }
5964
5965 /**
5966 * i915_read_mch_val - return value for IPS use
5967 *
5968 * Calculate and return a value for the IPS driver to use when deciding whether
5969 * we have thermal and power headroom to increase CPU or GPU power budget.
5970 */
5971 unsigned long i915_read_mch_val(void)
5972 {
5973 struct drm_i915_private *dev_priv;
5974 unsigned long chipset_val, graphics_val, ret = 0;
5975
5976 spin_lock_irq(&mchdev_lock);
5977 if (!i915_mch_dev)
5978 goto out_unlock;
5979 dev_priv = i915_mch_dev;
5980
5981 chipset_val = __i915_chipset_val(dev_priv);
5982 graphics_val = __i915_gfx_val(dev_priv);
5983
5984 ret = chipset_val + graphics_val;
5985
5986 out_unlock:
5987 spin_unlock_irq(&mchdev_lock);
5988
5989 return ret;
5990 }
5991 EXPORT_SYMBOL_GPL(i915_read_mch_val);
5992
5993 /**
5994 * i915_gpu_raise - raise GPU frequency limit
5995 *
5996 * Raise the limit; IPS indicates we have thermal headroom.
5997 */
5998 bool i915_gpu_raise(void)
5999 {
6000 struct drm_i915_private *dev_priv;
6001 bool ret = true;
6002
6003 spin_lock_irq(&mchdev_lock);
6004 if (!i915_mch_dev) {
6005 ret = false;
6006 goto out_unlock;
6007 }
6008 dev_priv = i915_mch_dev;
6009
6010 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
6011 dev_priv->ips.max_delay--;
6012
6013 out_unlock:
6014 spin_unlock_irq(&mchdev_lock);
6015
6016 return ret;
6017 }
6018 EXPORT_SYMBOL_GPL(i915_gpu_raise);
6019
6020 /**
6021 * i915_gpu_lower - lower GPU frequency limit
6022 *
6023 * IPS indicates we're close to a thermal limit, so throttle back the GPU
6024 * frequency maximum.
6025 */
6026 bool i915_gpu_lower(void)
6027 {
6028 struct drm_i915_private *dev_priv;
6029 bool ret = true;
6030
6031 spin_lock_irq(&mchdev_lock);
6032 if (!i915_mch_dev) {
6033 ret = false;
6034 goto out_unlock;
6035 }
6036 dev_priv = i915_mch_dev;
6037
6038 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
6039 dev_priv->ips.max_delay++;
6040
6041 out_unlock:
6042 spin_unlock_irq(&mchdev_lock);
6043
6044 return ret;
6045 }
6046 EXPORT_SYMBOL_GPL(i915_gpu_lower);
6047
6048 /**
6049 * i915_gpu_busy - indicate GPU business to IPS
6050 *
6051 * Tell the IPS driver whether or not the GPU is busy.
6052 */
6053 bool i915_gpu_busy(void)
6054 {
6055 struct drm_i915_private *dev_priv;
6056 struct intel_engine_cs *ring;
6057 bool ret = false;
6058 int i;
6059
6060 spin_lock_irq(&mchdev_lock);
6061 if (!i915_mch_dev)
6062 goto out_unlock;
6063 dev_priv = i915_mch_dev;
6064
6065 for_each_ring(ring, dev_priv, i)
6066 ret |= !list_empty(&ring->request_list);
6067
6068 out_unlock:
6069 spin_unlock_irq(&mchdev_lock);
6070
6071 return ret;
6072 }
6073 EXPORT_SYMBOL_GPL(i915_gpu_busy);
6074
6075 /**
6076 * i915_gpu_turbo_disable - disable graphics turbo
6077 *
6078 * Disable graphics turbo by resetting the max frequency and setting the
6079 * current frequency to the default.
6080 */
6081 bool i915_gpu_turbo_disable(void)
6082 {
6083 struct drm_i915_private *dev_priv;
6084 bool ret = true;
6085
6086 spin_lock_irq(&mchdev_lock);
6087 if (!i915_mch_dev) {
6088 ret = false;
6089 goto out_unlock;
6090 }
6091 dev_priv = i915_mch_dev;
6092
6093 dev_priv->ips.max_delay = dev_priv->ips.fstart;
6094
6095 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
6096 ret = false;
6097
6098 out_unlock:
6099 spin_unlock_irq(&mchdev_lock);
6100
6101 return ret;
6102 }
6103 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6104
6105 /**
6106 * Tells the intel_ips driver that the i915 driver is now loaded, if
6107 * IPS got loaded first.
6108 *
6109 * This awkward dance is so that neither module has to depend on the
6110 * other in order for IPS to do the appropriate communication of
6111 * GPU turbo limits to i915.
6112 */
6113 static void
6114 ips_ping_for_i915_load(void)
6115 {
6116 void (*link)(void);
6117
6118 link = symbol_get(ips_link_to_i915_driver);
6119 if (link) {
6120 link();
6121 symbol_put(ips_link_to_i915_driver);
6122 }
6123 }
6124
6125 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6126 {
6127 /* We only register the i915 ips part with intel-ips once everything is
6128 * set up, to avoid intel-ips sneaking in and reading bogus values. */
6129 spin_lock_irq(&mchdev_lock);
6130 i915_mch_dev = dev_priv;
6131 spin_unlock_irq(&mchdev_lock);
6132
6133 ips_ping_for_i915_load();
6134 }
6135
6136 void intel_gpu_ips_teardown(void)
6137 {
6138 spin_lock_irq(&mchdev_lock);
6139 i915_mch_dev = NULL;
6140 spin_unlock_irq(&mchdev_lock);
6141 }
6142
6143 static void intel_init_emon(struct drm_device *dev)
6144 {
6145 struct drm_i915_private *dev_priv = dev->dev_private;
6146 u32 lcfuse;
6147 u8 pxw[16];
6148 int i;
6149
6150 /* Disable to program */
6151 I915_WRITE(ECR, 0);
6152 POSTING_READ(ECR);
6153
6154 /* Program energy weights for various events */
6155 I915_WRITE(SDEW, 0x15040d00);
6156 I915_WRITE(CSIEW0, 0x007f0000);
6157 I915_WRITE(CSIEW1, 0x1e220004);
6158 I915_WRITE(CSIEW2, 0x04000004);
6159
6160 for (i = 0; i < 5; i++)
6161 I915_WRITE(PEW(i), 0);
6162 for (i = 0; i < 3; i++)
6163 I915_WRITE(DEW(i), 0);
6164
6165 /* Program P-state weights to account for frequency power adjustment */
6166 for (i = 0; i < 16; i++) {
6167 u32 pxvidfreq = I915_READ(PXVFREQ(i));
6168 unsigned long freq = intel_pxfreq(pxvidfreq);
6169 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6170 PXVFREQ_PX_SHIFT;
6171 unsigned long val;
6172
6173 val = vid * vid;
6174 val *= (freq / 1000);
6175 val *= 255;
6176 val /= (127*127*900);
6177 if (val > 0xff)
6178 DRM_ERROR("bad pxval: %ld\n", val);
6179 pxw[i] = val;
6180 }
6181 /* Render standby states get 0 weight */
6182 pxw[14] = 0;
6183 pxw[15] = 0;
6184
6185 for (i = 0; i < 4; i++) {
6186 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6187 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
6188 I915_WRITE(PXW(i), val);
6189 }
6190
6191 /* Adjust magic regs to magic values (more experimental results) */
6192 I915_WRITE(OGW0, 0);
6193 I915_WRITE(OGW1, 0);
6194 I915_WRITE(EG0, 0x00007f00);
6195 I915_WRITE(EG1, 0x0000000e);
6196 I915_WRITE(EG2, 0x000e0000);
6197 I915_WRITE(EG3, 0x68000300);
6198 I915_WRITE(EG4, 0x42000000);
6199 I915_WRITE(EG5, 0x00140031);
6200 I915_WRITE(EG6, 0);
6201 I915_WRITE(EG7, 0);
6202
6203 for (i = 0; i < 8; i++)
6204 I915_WRITE(PXWL(i), 0);
6205
6206 /* Enable PMON + select events */
6207 I915_WRITE(ECR, 0x80000019);
6208
6209 lcfuse = I915_READ(LCFUSE02);
6210
6211 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
6212 }
6213
6214 void intel_init_gt_powersave(struct drm_device *dev)
6215 {
6216 i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
6217
6218 if (IS_CHERRYVIEW(dev))
6219 cherryview_init_gt_powersave(dev);
6220 else if (IS_VALLEYVIEW(dev))
6221 valleyview_init_gt_powersave(dev);
6222 }
6223
6224 void intel_cleanup_gt_powersave(struct drm_device *dev)
6225 {
6226 if (IS_CHERRYVIEW(dev))
6227 return;
6228 else if (IS_VALLEYVIEW(dev))
6229 valleyview_cleanup_gt_powersave(dev);
6230 }
6231
6232 static void gen6_suspend_rps(struct drm_device *dev)
6233 {
6234 struct drm_i915_private *dev_priv = dev->dev_private;
6235
6236 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
6237
6238 gen6_disable_rps_interrupts(dev);
6239 }
6240
6241 /**
6242 * intel_suspend_gt_powersave - suspend PM work and helper threads
6243 * @dev: drm device
6244 *
6245 * We don't want to disable RC6 or other features here, we just want
6246 * to make sure any work we've queued has finished and won't bother
6247 * us while we're suspended.
6248 */
6249 void intel_suspend_gt_powersave(struct drm_device *dev)
6250 {
6251 struct drm_i915_private *dev_priv = dev->dev_private;
6252
6253 if (INTEL_INFO(dev)->gen < 6)
6254 return;
6255
6256 gen6_suspend_rps(dev);
6257
6258 /* Force GPU to min freq during suspend */
6259 gen6_rps_idle(dev_priv);
6260 }
6261
6262 void intel_disable_gt_powersave(struct drm_device *dev)
6263 {
6264 struct drm_i915_private *dev_priv = dev->dev_private;
6265
6266 if (IS_IRONLAKE_M(dev)) {
6267 ironlake_disable_drps(dev);
6268 } else if (INTEL_INFO(dev)->gen >= 6) {
6269 intel_suspend_gt_powersave(dev);
6270
6271 mutex_lock(&dev_priv->rps.hw_lock);
6272 if (INTEL_INFO(dev)->gen >= 9)
6273 gen9_disable_rps(dev);
6274 else if (IS_CHERRYVIEW(dev))
6275 cherryview_disable_rps(dev);
6276 else if (IS_VALLEYVIEW(dev))
6277 valleyview_disable_rps(dev);
6278 else
6279 gen6_disable_rps(dev);
6280
6281 dev_priv->rps.enabled = false;
6282 mutex_unlock(&dev_priv->rps.hw_lock);
6283 }
6284 }
6285
6286 static void intel_gen6_powersave_work(struct work_struct *work)
6287 {
6288 struct drm_i915_private *dev_priv =
6289 container_of(work, struct drm_i915_private,
6290 rps.delayed_resume_work.work);
6291 struct drm_device *dev = dev_priv->dev;
6292
6293 mutex_lock(&dev_priv->rps.hw_lock);
6294
6295 gen6_reset_rps_interrupts(dev);
6296
6297 if (IS_CHERRYVIEW(dev)) {
6298 cherryview_enable_rps(dev);
6299 } else if (IS_VALLEYVIEW(dev)) {
6300 valleyview_enable_rps(dev);
6301 } else if (INTEL_INFO(dev)->gen >= 9) {
6302 gen9_enable_rc6(dev);
6303 gen9_enable_rps(dev);
6304 if (IS_SKYLAKE(dev))
6305 __gen6_update_ring_freq(dev);
6306 } else if (IS_BROADWELL(dev)) {
6307 gen8_enable_rps(dev);
6308 __gen6_update_ring_freq(dev);
6309 } else {
6310 gen6_enable_rps(dev);
6311 __gen6_update_ring_freq(dev);
6312 }
6313
6314 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6315 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6316
6317 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6318 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6319
6320 dev_priv->rps.enabled = true;
6321
6322 gen6_enable_rps_interrupts(dev);
6323
6324 mutex_unlock(&dev_priv->rps.hw_lock);
6325
6326 intel_runtime_pm_put(dev_priv);
6327 }
6328
6329 void intel_enable_gt_powersave(struct drm_device *dev)
6330 {
6331 struct drm_i915_private *dev_priv = dev->dev_private;
6332
6333 /* Powersaving is controlled by the host when inside a VM */
6334 if (intel_vgpu_active(dev))
6335 return;
6336
6337 if (IS_IRONLAKE_M(dev)) {
6338 mutex_lock(&dev->struct_mutex);
6339 ironlake_enable_drps(dev);
6340 intel_init_emon(dev);
6341 mutex_unlock(&dev->struct_mutex);
6342 } else if (INTEL_INFO(dev)->gen >= 6) {
6343 /*
6344 * PCU communication is slow and this doesn't need to be
6345 * done at any specific time, so do this out of our fast path
6346 * to make resume and init faster.
6347 *
6348 * We depend on the HW RC6 power context save/restore
6349 * mechanism when entering D3 through runtime PM suspend. So
6350 * disable RPM until RPS/RC6 is properly setup. We can only
6351 * get here via the driver load/system resume/runtime resume
6352 * paths, so the _noresume version is enough (and in case of
6353 * runtime resume it's necessary).
6354 */
6355 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
6356 round_jiffies_up_relative(HZ)))
6357 intel_runtime_pm_get_noresume(dev_priv);
6358 }
6359 }
6360
6361 void intel_reset_gt_powersave(struct drm_device *dev)
6362 {
6363 struct drm_i915_private *dev_priv = dev->dev_private;
6364
6365 if (INTEL_INFO(dev)->gen < 6)
6366 return;
6367
6368 gen6_suspend_rps(dev);
6369 dev_priv->rps.enabled = false;
6370 }
6371
6372 static void ibx_init_clock_gating(struct drm_device *dev)
6373 {
6374 struct drm_i915_private *dev_priv = dev->dev_private;
6375
6376 /*
6377 * On Ibex Peak and Cougar Point, we need to disable clock
6378 * gating for the panel power sequencer or it will fail to
6379 * start up when no ports are active.
6380 */
6381 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6382 }
6383
6384 static void g4x_disable_trickle_feed(struct drm_device *dev)
6385 {
6386 struct drm_i915_private *dev_priv = dev->dev_private;
6387 enum pipe pipe;
6388
6389 for_each_pipe(dev_priv, pipe) {
6390 I915_WRITE(DSPCNTR(pipe),
6391 I915_READ(DSPCNTR(pipe)) |
6392 DISPPLANE_TRICKLE_FEED_DISABLE);
6393
6394 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6395 POSTING_READ(DSPSURF(pipe));
6396 }
6397 }
6398
6399 static void ilk_init_lp_watermarks(struct drm_device *dev)
6400 {
6401 struct drm_i915_private *dev_priv = dev->dev_private;
6402
6403 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6404 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6405 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6406
6407 /*
6408 * Don't touch WM1S_LP_EN here.
6409 * Doing so could cause underruns.
6410 */
6411 }
6412
6413 static void ironlake_init_clock_gating(struct drm_device *dev)
6414 {
6415 struct drm_i915_private *dev_priv = dev->dev_private;
6416 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6417
6418 /*
6419 * Required for FBC
6420 * WaFbcDisableDpfcClockGating:ilk
6421 */
6422 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6423 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6424 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6425
6426 I915_WRITE(PCH_3DCGDIS0,
6427 MARIUNIT_CLOCK_GATE_DISABLE |
6428 SVSMUNIT_CLOCK_GATE_DISABLE);
6429 I915_WRITE(PCH_3DCGDIS1,
6430 VFMUNIT_CLOCK_GATE_DISABLE);
6431
6432 /*
6433 * According to the spec the following bits should be set in
6434 * order to enable memory self-refresh
6435 * The bit 22/21 of 0x42004
6436 * The bit 5 of 0x42020
6437 * The bit 15 of 0x45000
6438 */
6439 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6440 (I915_READ(ILK_DISPLAY_CHICKEN2) |
6441 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
6442 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6443 I915_WRITE(DISP_ARB_CTL,
6444 (I915_READ(DISP_ARB_CTL) |
6445 DISP_FBC_WM_DIS));
6446
6447 ilk_init_lp_watermarks(dev);
6448
6449 /*
6450 * Based on the document from hardware guys the following bits
6451 * should be set unconditionally in order to enable FBC.
6452 * The bit 22 of 0x42000
6453 * The bit 22 of 0x42004
6454 * The bit 7,8,9 of 0x42020.
6455 */
6456 if (IS_IRONLAKE_M(dev)) {
6457 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6458 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6459 I915_READ(ILK_DISPLAY_CHICKEN1) |
6460 ILK_FBCQ_DIS);
6461 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6462 I915_READ(ILK_DISPLAY_CHICKEN2) |
6463 ILK_DPARB_GATE);
6464 }
6465
6466 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6467
6468 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6469 I915_READ(ILK_DISPLAY_CHICKEN2) |
6470 ILK_ELPIN_409_SELECT);
6471 I915_WRITE(_3D_CHICKEN2,
6472 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6473 _3D_CHICKEN2_WM_READ_PIPELINED);
6474
6475 /* WaDisableRenderCachePipelinedFlush:ilk */
6476 I915_WRITE(CACHE_MODE_0,
6477 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6478
6479 /* WaDisable_RenderCache_OperationalFlush:ilk */
6480 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6481
6482 g4x_disable_trickle_feed(dev);
6483
6484 ibx_init_clock_gating(dev);
6485 }
6486
6487 static void cpt_init_clock_gating(struct drm_device *dev)
6488 {
6489 struct drm_i915_private *dev_priv = dev->dev_private;
6490 int pipe;
6491 uint32_t val;
6492
6493 /*
6494 * On Ibex Peak and Cougar Point, we need to disable clock
6495 * gating for the panel power sequencer or it will fail to
6496 * start up when no ports are active.
6497 */
6498 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6499 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6500 PCH_CPUNIT_CLOCK_GATE_DISABLE);
6501 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6502 DPLS_EDP_PPS_FIX_DIS);
6503 /* The below fixes the weird display corruption, a few pixels shifted
6504 * downward, on (only) LVDS of some HP laptops with IVY.
6505 */
6506 for_each_pipe(dev_priv, pipe) {
6507 val = I915_READ(TRANS_CHICKEN2(pipe));
6508 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6509 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6510 if (dev_priv->vbt.fdi_rx_polarity_inverted)
6511 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6512 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6513 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6514 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
6515 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6516 }
6517 /* WADP0ClockGatingDisable */
6518 for_each_pipe(dev_priv, pipe) {
6519 I915_WRITE(TRANS_CHICKEN1(pipe),
6520 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6521 }
6522 }
6523
6524 static void gen6_check_mch_setup(struct drm_device *dev)
6525 {
6526 struct drm_i915_private *dev_priv = dev->dev_private;
6527 uint32_t tmp;
6528
6529 tmp = I915_READ(MCH_SSKPD);
6530 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6531 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6532 tmp);
6533 }
6534
6535 static void gen6_init_clock_gating(struct drm_device *dev)
6536 {
6537 struct drm_i915_private *dev_priv = dev->dev_private;
6538 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6539
6540 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6541
6542 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6543 I915_READ(ILK_DISPLAY_CHICKEN2) |
6544 ILK_ELPIN_409_SELECT);
6545
6546 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
6547 I915_WRITE(_3D_CHICKEN,
6548 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
6549
6550 /* WaDisable_RenderCache_OperationalFlush:snb */
6551 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6552
6553 /*
6554 * BSpec recoomends 8x4 when MSAA is used,
6555 * however in practice 16x4 seems fastest.
6556 *
6557 * Note that PS/WM thread counts depend on the WIZ hashing
6558 * disable bit, which we don't touch here, but it's good
6559 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6560 */
6561 I915_WRITE(GEN6_GT_MODE,
6562 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6563
6564 ilk_init_lp_watermarks(dev);
6565
6566 I915_WRITE(CACHE_MODE_0,
6567 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6568
6569 I915_WRITE(GEN6_UCGCTL1,
6570 I915_READ(GEN6_UCGCTL1) |
6571 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
6572 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6573
6574 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
6575 * gating disable must be set. Failure to set it results in
6576 * flickering pixels due to Z write ordering failures after
6577 * some amount of runtime in the Mesa "fire" demo, and Unigine
6578 * Sanctuary and Tropics, and apparently anything else with
6579 * alpha test or pixel discard.
6580 *
6581 * According to the spec, bit 11 (RCCUNIT) must also be set,
6582 * but we didn't debug actual testcases to find it out.
6583 *
6584 * WaDisableRCCUnitClockGating:snb
6585 * WaDisableRCPBUnitClockGating:snb
6586 */
6587 I915_WRITE(GEN6_UCGCTL2,
6588 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
6589 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
6590
6591 /* WaStripsFansDisableFastClipPerformanceFix:snb */
6592 I915_WRITE(_3D_CHICKEN3,
6593 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6594
6595 /*
6596 * Bspec says:
6597 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
6598 * 3DSTATE_SF number of SF output attributes is more than 16."
6599 */
6600 I915_WRITE(_3D_CHICKEN3,
6601 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
6602
6603 /*
6604 * According to the spec the following bits should be
6605 * set in order to enable memory self-refresh and fbc:
6606 * The bit21 and bit22 of 0x42000
6607 * The bit21 and bit22 of 0x42004
6608 * The bit5 and bit7 of 0x42020
6609 * The bit14 of 0x70180
6610 * The bit14 of 0x71180
6611 *
6612 * WaFbcAsynchFlipDisableFbcQueue:snb
6613 */
6614 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6615 I915_READ(ILK_DISPLAY_CHICKEN1) |
6616 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6617 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6618 I915_READ(ILK_DISPLAY_CHICKEN2) |
6619 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
6620 I915_WRITE(ILK_DSPCLK_GATE_D,
6621 I915_READ(ILK_DSPCLK_GATE_D) |
6622 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
6623 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6624
6625 g4x_disable_trickle_feed(dev);
6626
6627 cpt_init_clock_gating(dev);
6628
6629 gen6_check_mch_setup(dev);
6630 }
6631
6632 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
6633 {
6634 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
6635
6636 /*
6637 * WaVSThreadDispatchOverride:ivb,vlv
6638 *
6639 * This actually overrides the dispatch
6640 * mode for all thread types.
6641 */
6642 reg &= ~GEN7_FF_SCHED_MASK;
6643 reg |= GEN7_FF_TS_SCHED_HW;
6644 reg |= GEN7_FF_VS_SCHED_HW;
6645 reg |= GEN7_FF_DS_SCHED_HW;
6646
6647 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
6648 }
6649
6650 static void lpt_init_clock_gating(struct drm_device *dev)
6651 {
6652 struct drm_i915_private *dev_priv = dev->dev_private;
6653
6654 /*
6655 * TODO: this bit should only be enabled when really needed, then
6656 * disabled when not needed anymore in order to save power.
6657 */
6658 if (HAS_PCH_LPT_LP(dev))
6659 I915_WRITE(SOUTH_DSPCLK_GATE_D,
6660 I915_READ(SOUTH_DSPCLK_GATE_D) |
6661 PCH_LP_PARTITION_LEVEL_DISABLE);
6662
6663 /* WADPOClockGatingDisable:hsw */
6664 I915_WRITE(_TRANSA_CHICKEN1,
6665 I915_READ(_TRANSA_CHICKEN1) |
6666 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6667 }
6668
6669 static void lpt_suspend_hw(struct drm_device *dev)
6670 {
6671 struct drm_i915_private *dev_priv = dev->dev_private;
6672
6673 if (HAS_PCH_LPT_LP(dev)) {
6674 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
6675
6676 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6677 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6678 }
6679 }
6680
6681 static void broadwell_init_clock_gating(struct drm_device *dev)
6682 {
6683 struct drm_i915_private *dev_priv = dev->dev_private;
6684 enum pipe pipe;
6685 uint32_t misccpctl;
6686
6687 ilk_init_lp_watermarks(dev);
6688
6689 /* WaSwitchSolVfFArbitrationPriority:bdw */
6690 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6691
6692 /* WaPsrDPAMaskVBlankInSRD:bdw */
6693 I915_WRITE(CHICKEN_PAR1_1,
6694 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
6695
6696 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
6697 for_each_pipe(dev_priv, pipe) {
6698 I915_WRITE(CHICKEN_PIPESL_1(pipe),
6699 I915_READ(CHICKEN_PIPESL_1(pipe)) |
6700 BDW_DPRS_MASK_VBLANK_SRD);
6701 }
6702
6703 /* WaVSRefCountFullforceMissDisable:bdw */
6704 /* WaDSRefCountFullforceMissDisable:bdw */
6705 I915_WRITE(GEN7_FF_THREAD_MODE,
6706 I915_READ(GEN7_FF_THREAD_MODE) &
6707 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
6708
6709 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6710 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
6711
6712 /* WaDisableSDEUnitClockGating:bdw */
6713 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6714 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6715
6716 /*
6717 * WaProgramL3SqcReg1Default:bdw
6718 * WaTempDisableDOPClkGating:bdw
6719 */
6720 misccpctl = I915_READ(GEN7_MISCCPCTL);
6721 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
6722 I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
6723 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
6724
6725 /*
6726 * WaGttCachingOffByDefault:bdw
6727 * GTT cache may not work with big pages, so if those
6728 * are ever enabled GTT cache may need to be disabled.
6729 */
6730 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
6731
6732 lpt_init_clock_gating(dev);
6733 }
6734
6735 static void haswell_init_clock_gating(struct drm_device *dev)
6736 {
6737 struct drm_i915_private *dev_priv = dev->dev_private;
6738
6739 ilk_init_lp_watermarks(dev);
6740
6741 /* L3 caching of data atomics doesn't work -- disable it. */
6742 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
6743 I915_WRITE(HSW_ROW_CHICKEN3,
6744 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
6745
6746 /* This is required by WaCatErrorRejectionIssue:hsw */
6747 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6748 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6749 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6750
6751 /* WaVSRefCountFullforceMissDisable:hsw */
6752 I915_WRITE(GEN7_FF_THREAD_MODE,
6753 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
6754
6755 /* WaDisable_RenderCache_OperationalFlush:hsw */
6756 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6757
6758 /* enable HiZ Raw Stall Optimization */
6759 I915_WRITE(CACHE_MODE_0_GEN7,
6760 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6761
6762 /* WaDisable4x2SubspanOptimization:hsw */
6763 I915_WRITE(CACHE_MODE_1,
6764 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6765
6766 /*
6767 * BSpec recommends 8x4 when MSAA is used,
6768 * however in practice 16x4 seems fastest.
6769 *
6770 * Note that PS/WM thread counts depend on the WIZ hashing
6771 * disable bit, which we don't touch here, but it's good
6772 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6773 */
6774 I915_WRITE(GEN7_GT_MODE,
6775 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6776
6777 /* WaSampleCChickenBitEnable:hsw */
6778 I915_WRITE(HALF_SLICE_CHICKEN3,
6779 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
6780
6781 /* WaSwitchSolVfFArbitrationPriority:hsw */
6782 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6783
6784 /* WaRsPkgCStateDisplayPMReq:hsw */
6785 I915_WRITE(CHICKEN_PAR1_1,
6786 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
6787
6788 lpt_init_clock_gating(dev);
6789 }
6790
6791 static void ivybridge_init_clock_gating(struct drm_device *dev)
6792 {
6793 struct drm_i915_private *dev_priv = dev->dev_private;
6794 uint32_t snpcr;
6795
6796 ilk_init_lp_watermarks(dev);
6797
6798 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6799
6800 /* WaDisableEarlyCull:ivb */
6801 I915_WRITE(_3D_CHICKEN3,
6802 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6803
6804 /* WaDisableBackToBackFlipFix:ivb */
6805 I915_WRITE(IVB_CHICKEN3,
6806 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6807 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6808
6809 /* WaDisablePSDDualDispatchEnable:ivb */
6810 if (IS_IVB_GT1(dev))
6811 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6812 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
6813
6814 /* WaDisable_RenderCache_OperationalFlush:ivb */
6815 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6816
6817 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6818 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
6819 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
6820
6821 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6822 I915_WRITE(GEN7_L3CNTLREG1,
6823 GEN7_WA_FOR_GEN7_L3_CONTROL);
6824 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
6825 GEN7_WA_L3_CHICKEN_MODE);
6826 if (IS_IVB_GT1(dev))
6827 I915_WRITE(GEN7_ROW_CHICKEN2,
6828 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6829 else {
6830 /* must write both registers */
6831 I915_WRITE(GEN7_ROW_CHICKEN2,
6832 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6833 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
6834 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6835 }
6836
6837 /* WaForceL3Serialization:ivb */
6838 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6839 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6840
6841 /*
6842 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6843 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
6844 */
6845 I915_WRITE(GEN6_UCGCTL2,
6846 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
6847
6848 /* This is required by WaCatErrorRejectionIssue:ivb */
6849 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6850 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6851 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6852
6853 g4x_disable_trickle_feed(dev);
6854
6855 gen7_setup_fixed_func_scheduler(dev_priv);
6856
6857 if (0) { /* causes HiZ corruption on ivb:gt1 */
6858 /* enable HiZ Raw Stall Optimization */
6859 I915_WRITE(CACHE_MODE_0_GEN7,
6860 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6861 }
6862
6863 /* WaDisable4x2SubspanOptimization:ivb */
6864 I915_WRITE(CACHE_MODE_1,
6865 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6866
6867 /*
6868 * BSpec recommends 8x4 when MSAA is used,
6869 * however in practice 16x4 seems fastest.
6870 *
6871 * Note that PS/WM thread counts depend on the WIZ hashing
6872 * disable bit, which we don't touch here, but it's good
6873 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6874 */
6875 I915_WRITE(GEN7_GT_MODE,
6876 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6877
6878 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
6879 snpcr &= ~GEN6_MBC_SNPCR_MASK;
6880 snpcr |= GEN6_MBC_SNPCR_MED;
6881 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
6882
6883 if (!HAS_PCH_NOP(dev))
6884 cpt_init_clock_gating(dev);
6885
6886 gen6_check_mch_setup(dev);
6887 }
6888
6889 static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
6890 {
6891 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6892
6893 /*
6894 * Disable trickle feed and enable pnd deadline calculation
6895 */
6896 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6897 I915_WRITE(CBR1_VLV, 0);
6898 }
6899
6900 static void valleyview_init_clock_gating(struct drm_device *dev)
6901 {
6902 struct drm_i915_private *dev_priv = dev->dev_private;
6903
6904 vlv_init_display_clock_gating(dev_priv);
6905
6906 /* WaDisableEarlyCull:vlv */
6907 I915_WRITE(_3D_CHICKEN3,
6908 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6909
6910 /* WaDisableBackToBackFlipFix:vlv */
6911 I915_WRITE(IVB_CHICKEN3,
6912 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6913 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6914
6915 /* WaPsdDispatchEnable:vlv */
6916 /* WaDisablePSDDualDispatchEnable:vlv */
6917 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6918 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
6919 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
6920
6921 /* WaDisable_RenderCache_OperationalFlush:vlv */
6922 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6923
6924 /* WaForceL3Serialization:vlv */
6925 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6926 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6927
6928 /* WaDisableDopClockGating:vlv */
6929 I915_WRITE(GEN7_ROW_CHICKEN2,
6930 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6931
6932 /* This is required by WaCatErrorRejectionIssue:vlv */
6933 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6934 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6935 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6936
6937 gen7_setup_fixed_func_scheduler(dev_priv);
6938
6939 /*
6940 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6941 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
6942 */
6943 I915_WRITE(GEN6_UCGCTL2,
6944 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
6945
6946 /* WaDisableL3Bank2xClockGate:vlv
6947 * Disabling L3 clock gating- MMIO 940c[25] = 1
6948 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
6949 I915_WRITE(GEN7_UCGCTL4,
6950 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
6951
6952 /*
6953 * BSpec says this must be set, even though
6954 * WaDisable4x2SubspanOptimization isn't listed for VLV.
6955 */
6956 I915_WRITE(CACHE_MODE_1,
6957 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6958
6959 /*
6960 * BSpec recommends 8x4 when MSAA is used,
6961 * however in practice 16x4 seems fastest.
6962 *
6963 * Note that PS/WM thread counts depend on the WIZ hashing
6964 * disable bit, which we don't touch here, but it's good
6965 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6966 */
6967 I915_WRITE(GEN7_GT_MODE,
6968 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6969
6970 /*
6971 * WaIncreaseL3CreditsForVLVB0:vlv
6972 * This is the hardware default actually.
6973 */
6974 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
6975
6976 /*
6977 * WaDisableVLVClockGating_VBIIssue:vlv
6978 * Disable clock gating on th GCFG unit to prevent a delay
6979 * in the reporting of vblank events.
6980 */
6981 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6982 }
6983
6984 static void cherryview_init_clock_gating(struct drm_device *dev)
6985 {
6986 struct drm_i915_private *dev_priv = dev->dev_private;
6987
6988 vlv_init_display_clock_gating(dev_priv);
6989
6990 /* WaVSRefCountFullforceMissDisable:chv */
6991 /* WaDSRefCountFullforceMissDisable:chv */
6992 I915_WRITE(GEN7_FF_THREAD_MODE,
6993 I915_READ(GEN7_FF_THREAD_MODE) &
6994 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
6995
6996 /* WaDisableSemaphoreAndSyncFlipWait:chv */
6997 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6998 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
6999
7000 /* WaDisableCSUnitClockGating:chv */
7001 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7002 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
7003
7004 /* WaDisableSDEUnitClockGating:chv */
7005 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7006 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7007
7008 /*
7009 * GTT cache may not work with big pages, so if those
7010 * are ever enabled GTT cache may need to be disabled.
7011 */
7012 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
7013 }
7014
7015 static void g4x_init_clock_gating(struct drm_device *dev)
7016 {
7017 struct drm_i915_private *dev_priv = dev->dev_private;
7018 uint32_t dspclk_gate;
7019
7020 I915_WRITE(RENCLK_GATE_D1, 0);
7021 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7022 GS_UNIT_CLOCK_GATE_DISABLE |
7023 CL_UNIT_CLOCK_GATE_DISABLE);
7024 I915_WRITE(RAMCLK_GATE_D, 0);
7025 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7026 OVRUNIT_CLOCK_GATE_DISABLE |
7027 OVCUNIT_CLOCK_GATE_DISABLE;
7028 if (IS_GM45(dev))
7029 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7030 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
7031
7032 /* WaDisableRenderCachePipelinedFlush */
7033 I915_WRITE(CACHE_MODE_0,
7034 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
7035
7036 /* WaDisable_RenderCache_OperationalFlush:g4x */
7037 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7038
7039 g4x_disable_trickle_feed(dev);
7040 }
7041
7042 static void crestline_init_clock_gating(struct drm_device *dev)
7043 {
7044 struct drm_i915_private *dev_priv = dev->dev_private;
7045
7046 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7047 I915_WRITE(RENCLK_GATE_D2, 0);
7048 I915_WRITE(DSPCLK_GATE_D, 0);
7049 I915_WRITE(RAMCLK_GATE_D, 0);
7050 I915_WRITE16(DEUC, 0);
7051 I915_WRITE(MI_ARB_STATE,
7052 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7053
7054 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7055 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7056 }
7057
7058 static void broadwater_init_clock_gating(struct drm_device *dev)
7059 {
7060 struct drm_i915_private *dev_priv = dev->dev_private;
7061
7062 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7063 I965_RCC_CLOCK_GATE_DISABLE |
7064 I965_RCPB_CLOCK_GATE_DISABLE |
7065 I965_ISC_CLOCK_GATE_DISABLE |
7066 I965_FBC_CLOCK_GATE_DISABLE);
7067 I915_WRITE(RENCLK_GATE_D2, 0);
7068 I915_WRITE(MI_ARB_STATE,
7069 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7070
7071 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7072 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7073 }
7074
7075 static void gen3_init_clock_gating(struct drm_device *dev)
7076 {
7077 struct drm_i915_private *dev_priv = dev->dev_private;
7078 u32 dstate = I915_READ(D_STATE);
7079
7080 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7081 DSTATE_DOT_CLOCK_GATING;
7082 I915_WRITE(D_STATE, dstate);
7083
7084 if (IS_PINEVIEW(dev))
7085 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
7086
7087 /* IIR "flip pending" means done if this bit is set */
7088 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
7089
7090 /* interrupts should cause a wake up from C3 */
7091 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
7092
7093 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7094 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
7095
7096 I915_WRITE(MI_ARB_STATE,
7097 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7098 }
7099
7100 static void i85x_init_clock_gating(struct drm_device *dev)
7101 {
7102 struct drm_i915_private *dev_priv = dev->dev_private;
7103
7104 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7105
7106 /* interrupts should cause a wake up from C3 */
7107 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7108 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
7109
7110 I915_WRITE(MEM_MODE,
7111 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
7112 }
7113
7114 static void i830_init_clock_gating(struct drm_device *dev)
7115 {
7116 struct drm_i915_private *dev_priv = dev->dev_private;
7117
7118 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
7119
7120 I915_WRITE(MEM_MODE,
7121 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7122 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
7123 }
7124
7125 void intel_init_clock_gating(struct drm_device *dev)
7126 {
7127 struct drm_i915_private *dev_priv = dev->dev_private;
7128
7129 if (dev_priv->display.init_clock_gating)
7130 dev_priv->display.init_clock_gating(dev);
7131 }
7132
7133 void intel_suspend_hw(struct drm_device *dev)
7134 {
7135 if (HAS_PCH_LPT(dev))
7136 lpt_suspend_hw(dev);
7137 }
7138
7139 /* Set up chip specific power management-related functions */
7140 void intel_init_pm(struct drm_device *dev)
7141 {
7142 struct drm_i915_private *dev_priv = dev->dev_private;
7143
7144 intel_fbc_init(dev_priv);
7145
7146 /* For cxsr */
7147 if (IS_PINEVIEW(dev))
7148 i915_pineview_get_mem_freq(dev);
7149 else if (IS_GEN5(dev))
7150 i915_ironlake_get_mem_freq(dev);
7151
7152 /* For FIFO watermark updates */
7153 if (INTEL_INFO(dev)->gen >= 9) {
7154 skl_setup_wm_latency(dev);
7155
7156 if (IS_BROXTON(dev))
7157 dev_priv->display.init_clock_gating =
7158 bxt_init_clock_gating;
7159 else if (IS_SKYLAKE(dev))
7160 dev_priv->display.init_clock_gating =
7161 skl_init_clock_gating;
7162 dev_priv->display.update_wm = skl_update_wm;
7163 dev_priv->display.update_sprite_wm = skl_update_sprite_wm;
7164 } else if (HAS_PCH_SPLIT(dev)) {
7165 ilk_setup_wm_latency(dev);
7166
7167 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
7168 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7169 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7170 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
7171 dev_priv->display.update_wm = ilk_update_wm;
7172 dev_priv->display.update_sprite_wm = ilk_update_sprite_wm;
7173 } else {
7174 DRM_DEBUG_KMS("Failed to read display plane latency. "
7175 "Disable CxSR\n");
7176 }
7177
7178 if (IS_GEN5(dev))
7179 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7180 else if (IS_GEN6(dev))
7181 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7182 else if (IS_IVYBRIDGE(dev))
7183 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7184 else if (IS_HASWELL(dev))
7185 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7186 else if (INTEL_INFO(dev)->gen == 8)
7187 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7188 } else if (IS_CHERRYVIEW(dev)) {
7189 vlv_setup_wm_latency(dev);
7190
7191 dev_priv->display.update_wm = vlv_update_wm;
7192 dev_priv->display.init_clock_gating =
7193 cherryview_init_clock_gating;
7194 } else if (IS_VALLEYVIEW(dev)) {
7195 vlv_setup_wm_latency(dev);
7196
7197 dev_priv->display.update_wm = vlv_update_wm;
7198 dev_priv->display.init_clock_gating =
7199 valleyview_init_clock_gating;
7200 } else if (IS_PINEVIEW(dev)) {
7201 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7202 dev_priv->is_ddr3,
7203 dev_priv->fsb_freq,
7204 dev_priv->mem_freq)) {
7205 DRM_INFO("failed to find known CxSR latency "
7206 "(found ddr%s fsb freq %d, mem freq %d), "
7207 "disabling CxSR\n",
7208 (dev_priv->is_ddr3 == 1) ? "3" : "2",
7209 dev_priv->fsb_freq, dev_priv->mem_freq);
7210 /* Disable CxSR and never update its watermark again */
7211 intel_set_memory_cxsr(dev_priv, false);
7212 dev_priv->display.update_wm = NULL;
7213 } else
7214 dev_priv->display.update_wm = pineview_update_wm;
7215 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7216 } else if (IS_G4X(dev)) {
7217 dev_priv->display.update_wm = g4x_update_wm;
7218 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7219 } else if (IS_GEN4(dev)) {
7220 dev_priv->display.update_wm = i965_update_wm;
7221 if (IS_CRESTLINE(dev))
7222 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7223 else if (IS_BROADWATER(dev))
7224 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7225 } else if (IS_GEN3(dev)) {
7226 dev_priv->display.update_wm = i9xx_update_wm;
7227 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7228 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7229 } else if (IS_GEN2(dev)) {
7230 if (INTEL_INFO(dev)->num_pipes == 1) {
7231 dev_priv->display.update_wm = i845_update_wm;
7232 dev_priv->display.get_fifo_size = i845_get_fifo_size;
7233 } else {
7234 dev_priv->display.update_wm = i9xx_update_wm;
7235 dev_priv->display.get_fifo_size = i830_get_fifo_size;
7236 }
7237
7238 if (IS_I85X(dev) || IS_I865G(dev))
7239 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7240 else
7241 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7242 } else {
7243 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
7244 }
7245 }
7246
7247 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
7248 {
7249 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7250
7251 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7252 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7253 return -EAGAIN;
7254 }
7255
7256 I915_WRITE(GEN6_PCODE_DATA, *val);
7257 I915_WRITE(GEN6_PCODE_DATA1, 0);
7258 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7259
7260 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7261 500)) {
7262 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7263 return -ETIMEDOUT;
7264 }
7265
7266 *val = I915_READ(GEN6_PCODE_DATA);
7267 I915_WRITE(GEN6_PCODE_DATA, 0);
7268
7269 return 0;
7270 }
7271
7272 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val)
7273 {
7274 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7275
7276 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7277 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7278 return -EAGAIN;
7279 }
7280
7281 I915_WRITE(GEN6_PCODE_DATA, val);
7282 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7283
7284 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7285 500)) {
7286 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7287 return -ETIMEDOUT;
7288 }
7289
7290 I915_WRITE(GEN6_PCODE_DATA, 0);
7291
7292 return 0;
7293 }
7294
7295 static int vlv_gpu_freq_div(unsigned int czclk_freq)
7296 {
7297 switch (czclk_freq) {
7298 case 200:
7299 return 10;
7300 case 267:
7301 return 12;
7302 case 320:
7303 case 333:
7304 return 16;
7305 case 400:
7306 return 20;
7307 default:
7308 return -1;
7309 }
7310 }
7311
7312 static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7313 {
7314 int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->mem_freq, 4);
7315
7316 div = vlv_gpu_freq_div(czclk_freq);
7317 if (div < 0)
7318 return div;
7319
7320 return DIV_ROUND_CLOSEST(czclk_freq * (val + 6 - 0xbd), div);
7321 }
7322
7323 static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
7324 {
7325 int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->mem_freq, 4);
7326
7327 mul = vlv_gpu_freq_div(czclk_freq);
7328 if (mul < 0)
7329 return mul;
7330
7331 return DIV_ROUND_CLOSEST(mul * val, czclk_freq) + 0xbd - 6;
7332 }
7333
7334 static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
7335 {
7336 int div, czclk_freq = dev_priv->rps.cz_freq;
7337
7338 div = vlv_gpu_freq_div(czclk_freq) / 2;
7339 if (div < 0)
7340 return div;
7341
7342 return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2;
7343 }
7344
7345 static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
7346 {
7347 int mul, czclk_freq = dev_priv->rps.cz_freq;
7348
7349 mul = vlv_gpu_freq_div(czclk_freq) / 2;
7350 if (mul < 0)
7351 return mul;
7352
7353 /* CHV needs even values */
7354 return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2;
7355 }
7356
7357 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
7358 {
7359 if (IS_GEN9(dev_priv->dev))
7360 return (val * GT_FREQUENCY_MULTIPLIER) / GEN9_FREQ_SCALER;
7361 else if (IS_CHERRYVIEW(dev_priv->dev))
7362 return chv_gpu_freq(dev_priv, val);
7363 else if (IS_VALLEYVIEW(dev_priv->dev))
7364 return byt_gpu_freq(dev_priv, val);
7365 else
7366 return val * GT_FREQUENCY_MULTIPLIER;
7367 }
7368
7369 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7370 {
7371 if (IS_GEN9(dev_priv->dev))
7372 return (val * GEN9_FREQ_SCALER) / GT_FREQUENCY_MULTIPLIER;
7373 else if (IS_CHERRYVIEW(dev_priv->dev))
7374 return chv_freq_opcode(dev_priv, val);
7375 else if (IS_VALLEYVIEW(dev_priv->dev))
7376 return byt_freq_opcode(dev_priv, val);
7377 else
7378 return val / GT_FREQUENCY_MULTIPLIER;
7379 }
7380
7381 struct request_boost {
7382 struct work_struct work;
7383 struct drm_i915_gem_request *req;
7384 };
7385
7386 static void __intel_rps_boost_work(struct work_struct *work)
7387 {
7388 struct request_boost *boost = container_of(work, struct request_boost, work);
7389 struct drm_i915_gem_request *req = boost->req;
7390
7391 if (!i915_gem_request_completed(req, true))
7392 gen6_rps_boost(to_i915(req->ring->dev), NULL,
7393 req->emitted_jiffies);
7394
7395 i915_gem_request_unreference__unlocked(req);
7396 kfree(boost);
7397 }
7398
7399 void intel_queue_rps_boost_for_request(struct drm_device *dev,
7400 struct drm_i915_gem_request *req)
7401 {
7402 struct request_boost *boost;
7403
7404 if (req == NULL || INTEL_INFO(dev)->gen < 6)
7405 return;
7406
7407 if (i915_gem_request_completed(req, true))
7408 return;
7409
7410 boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
7411 if (boost == NULL)
7412 return;
7413
7414 i915_gem_request_reference(req);
7415 boost->req = req;
7416
7417 INIT_WORK(&boost->work, __intel_rps_boost_work);
7418 queue_work(to_i915(dev)->wq, &boost->work);
7419 }
7420
7421 void intel_pm_setup(struct drm_device *dev)
7422 {
7423 struct drm_i915_private *dev_priv = dev->dev_private;
7424
7425 mutex_init(&dev_priv->rps.hw_lock);
7426 spin_lock_init(&dev_priv->rps.client_lock);
7427
7428 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
7429 intel_gen6_powersave_work);
7430 INIT_LIST_HEAD(&dev_priv->rps.clients);
7431 INIT_LIST_HEAD(&dev_priv->rps.semaphores.link);
7432 INIT_LIST_HEAD(&dev_priv->rps.mmioflips.link);
7433
7434 dev_priv->pm.suspended = false;
7435 }
Linux kernel - Deliverables
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