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drm/i915/chv: Use 16 and 32 for low and high drain latency precision.
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_pm.c
1 /*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28 #include <linux/cpufreq.h>
29 #include "i915_drv.h"
30 #include "intel_drv.h"
31 #include "../../../platform/x86/intel_ips.h"
32 #include <linux/module.h>
33
34 /**
35 * RC6 is a special power stage which allows the GPU to enter an very
36 * low-voltage mode when idle, using down to 0V while at this stage. This
37 * stage is entered automatically when the GPU is idle when RC6 support is
38 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
39 *
40 * There are different RC6 modes available in Intel GPU, which differentiate
41 * among each other with the latency required to enter and leave RC6 and
42 * voltage consumed by the GPU in different states.
43 *
44 * The combination of the following flags define which states GPU is allowed
45 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
46 * RC6pp is deepest RC6. Their support by hardware varies according to the
47 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
48 * which brings the most power savings; deeper states save more power, but
49 * require higher latency to switch to and wake up.
50 */
51 #define INTEL_RC6_ENABLE (1<<0)
52 #define INTEL_RC6p_ENABLE (1<<1)
53 #define INTEL_RC6pp_ENABLE (1<<2)
54
55 /* FBC, or Frame Buffer Compression, is a technique employed to compress the
56 * framebuffer contents in-memory, aiming at reducing the required bandwidth
57 * during in-memory transfers and, therefore, reduce the power packet.
58 *
59 * The benefits of FBC are mostly visible with solid backgrounds and
60 * variation-less patterns.
61 *
62 * FBC-related functionality can be enabled by the means of the
63 * i915.i915_enable_fbc parameter
64 */
65
66 static void gen9_init_clock_gating(struct drm_device *dev)
67 {
68 struct drm_i915_private *dev_priv = dev->dev_private;
69
70 /*
71 * WaDisableSDEUnitClockGating:skl
72 * This seems to be a pre-production w/a.
73 */
74 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
75 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
76
77 /*
78 * WaDisableDgMirrorFixInHalfSliceChicken5:skl
79 * This is a pre-production w/a.
80 */
81 I915_WRITE(GEN9_HALF_SLICE_CHICKEN5,
82 I915_READ(GEN9_HALF_SLICE_CHICKEN5) &
83 ~GEN9_DG_MIRROR_FIX_ENABLE);
84
85 /* Wa4x4STCOptimizationDisable:skl */
86 I915_WRITE(CACHE_MODE_1,
87 _MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE));
88 }
89
90 static void i8xx_disable_fbc(struct drm_device *dev)
91 {
92 struct drm_i915_private *dev_priv = dev->dev_private;
93 u32 fbc_ctl;
94
95 dev_priv->fbc.enabled = false;
96
97 /* Disable compression */
98 fbc_ctl = I915_READ(FBC_CONTROL);
99 if ((fbc_ctl & FBC_CTL_EN) == 0)
100 return;
101
102 fbc_ctl &= ~FBC_CTL_EN;
103 I915_WRITE(FBC_CONTROL, fbc_ctl);
104
105 /* Wait for compressing bit to clear */
106 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
107 DRM_DEBUG_KMS("FBC idle timed out\n");
108 return;
109 }
110
111 DRM_DEBUG_KMS("disabled FBC\n");
112 }
113
114 static void i8xx_enable_fbc(struct drm_crtc *crtc)
115 {
116 struct drm_device *dev = crtc->dev;
117 struct drm_i915_private *dev_priv = dev->dev_private;
118 struct drm_framebuffer *fb = crtc->primary->fb;
119 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
120 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
121 int cfb_pitch;
122 int i;
123 u32 fbc_ctl;
124
125 dev_priv->fbc.enabled = true;
126
127 cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
128 if (fb->pitches[0] < cfb_pitch)
129 cfb_pitch = fb->pitches[0];
130
131 /* FBC_CTL wants 32B or 64B units */
132 if (IS_GEN2(dev))
133 cfb_pitch = (cfb_pitch / 32) - 1;
134 else
135 cfb_pitch = (cfb_pitch / 64) - 1;
136
137 /* Clear old tags */
138 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
139 I915_WRITE(FBC_TAG + (i * 4), 0);
140
141 if (IS_GEN4(dev)) {
142 u32 fbc_ctl2;
143
144 /* Set it up... */
145 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
146 fbc_ctl2 |= FBC_CTL_PLANE(intel_crtc->plane);
147 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
148 I915_WRITE(FBC_FENCE_OFF, crtc->y);
149 }
150
151 /* enable it... */
152 fbc_ctl = I915_READ(FBC_CONTROL);
153 fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT;
154 fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
155 if (IS_I945GM(dev))
156 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
157 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
158 fbc_ctl |= obj->fence_reg;
159 I915_WRITE(FBC_CONTROL, fbc_ctl);
160
161 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c\n",
162 cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
163 }
164
165 static bool i8xx_fbc_enabled(struct drm_device *dev)
166 {
167 struct drm_i915_private *dev_priv = dev->dev_private;
168
169 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
170 }
171
172 static void g4x_enable_fbc(struct drm_crtc *crtc)
173 {
174 struct drm_device *dev = crtc->dev;
175 struct drm_i915_private *dev_priv = dev->dev_private;
176 struct drm_framebuffer *fb = crtc->primary->fb;
177 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
178 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
179 u32 dpfc_ctl;
180
181 dev_priv->fbc.enabled = true;
182
183 dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane) | DPFC_SR_EN;
184 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
185 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
186 else
187 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
188 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
189
190 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
191
192 /* enable it... */
193 I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
194
195 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
196 }
197
198 static void g4x_disable_fbc(struct drm_device *dev)
199 {
200 struct drm_i915_private *dev_priv = dev->dev_private;
201 u32 dpfc_ctl;
202
203 dev_priv->fbc.enabled = false;
204
205 /* Disable compression */
206 dpfc_ctl = I915_READ(DPFC_CONTROL);
207 if (dpfc_ctl & DPFC_CTL_EN) {
208 dpfc_ctl &= ~DPFC_CTL_EN;
209 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
210
211 DRM_DEBUG_KMS("disabled FBC\n");
212 }
213 }
214
215 static bool g4x_fbc_enabled(struct drm_device *dev)
216 {
217 struct drm_i915_private *dev_priv = dev->dev_private;
218
219 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
220 }
221
222 static void sandybridge_blit_fbc_update(struct drm_device *dev)
223 {
224 struct drm_i915_private *dev_priv = dev->dev_private;
225 u32 blt_ecoskpd;
226
227 /* Make sure blitter notifies FBC of writes */
228
229 /* Blitter is part of Media powerwell on VLV. No impact of
230 * his param in other platforms for now */
231 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_MEDIA);
232
233 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
234 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
235 GEN6_BLITTER_LOCK_SHIFT;
236 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
237 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
238 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
239 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
240 GEN6_BLITTER_LOCK_SHIFT);
241 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
242 POSTING_READ(GEN6_BLITTER_ECOSKPD);
243
244 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_MEDIA);
245 }
246
247 static void ironlake_enable_fbc(struct drm_crtc *crtc)
248 {
249 struct drm_device *dev = crtc->dev;
250 struct drm_i915_private *dev_priv = dev->dev_private;
251 struct drm_framebuffer *fb = crtc->primary->fb;
252 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
253 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
254 u32 dpfc_ctl;
255
256 dev_priv->fbc.enabled = true;
257
258 dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane);
259 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
260 dev_priv->fbc.threshold++;
261
262 switch (dev_priv->fbc.threshold) {
263 case 4:
264 case 3:
265 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
266 break;
267 case 2:
268 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
269 break;
270 case 1:
271 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
272 break;
273 }
274 dpfc_ctl |= DPFC_CTL_FENCE_EN;
275 if (IS_GEN5(dev))
276 dpfc_ctl |= obj->fence_reg;
277
278 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
279 I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
280 /* enable it... */
281 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
282
283 if (IS_GEN6(dev)) {
284 I915_WRITE(SNB_DPFC_CTL_SA,
285 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
286 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
287 sandybridge_blit_fbc_update(dev);
288 }
289
290 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
291 }
292
293 static void ironlake_disable_fbc(struct drm_device *dev)
294 {
295 struct drm_i915_private *dev_priv = dev->dev_private;
296 u32 dpfc_ctl;
297
298 dev_priv->fbc.enabled = false;
299
300 /* Disable compression */
301 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
302 if (dpfc_ctl & DPFC_CTL_EN) {
303 dpfc_ctl &= ~DPFC_CTL_EN;
304 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
305
306 DRM_DEBUG_KMS("disabled FBC\n");
307 }
308 }
309
310 static bool ironlake_fbc_enabled(struct drm_device *dev)
311 {
312 struct drm_i915_private *dev_priv = dev->dev_private;
313
314 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
315 }
316
317 static void gen7_enable_fbc(struct drm_crtc *crtc)
318 {
319 struct drm_device *dev = crtc->dev;
320 struct drm_i915_private *dev_priv = dev->dev_private;
321 struct drm_framebuffer *fb = crtc->primary->fb;
322 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
323 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
324 u32 dpfc_ctl;
325
326 dev_priv->fbc.enabled = true;
327
328 dpfc_ctl = IVB_DPFC_CTL_PLANE(intel_crtc->plane);
329 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
330 dev_priv->fbc.threshold++;
331
332 switch (dev_priv->fbc.threshold) {
333 case 4:
334 case 3:
335 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
336 break;
337 case 2:
338 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
339 break;
340 case 1:
341 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
342 break;
343 }
344
345 dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
346
347 if (dev_priv->fbc.false_color)
348 dpfc_ctl |= FBC_CTL_FALSE_COLOR;
349
350 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
351
352 if (IS_IVYBRIDGE(dev)) {
353 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
354 I915_WRITE(ILK_DISPLAY_CHICKEN1,
355 I915_READ(ILK_DISPLAY_CHICKEN1) |
356 ILK_FBCQ_DIS);
357 } else {
358 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
359 I915_WRITE(CHICKEN_PIPESL_1(intel_crtc->pipe),
360 I915_READ(CHICKEN_PIPESL_1(intel_crtc->pipe)) |
361 HSW_FBCQ_DIS);
362 }
363
364 I915_WRITE(SNB_DPFC_CTL_SA,
365 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
366 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
367
368 sandybridge_blit_fbc_update(dev);
369
370 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
371 }
372
373 bool intel_fbc_enabled(struct drm_device *dev)
374 {
375 struct drm_i915_private *dev_priv = dev->dev_private;
376
377 return dev_priv->fbc.enabled;
378 }
379
380 void bdw_fbc_sw_flush(struct drm_device *dev, u32 value)
381 {
382 struct drm_i915_private *dev_priv = dev->dev_private;
383
384 if (!IS_GEN8(dev))
385 return;
386
387 if (!intel_fbc_enabled(dev))
388 return;
389
390 I915_WRITE(MSG_FBC_REND_STATE, value);
391 }
392
393 static void intel_fbc_work_fn(struct work_struct *__work)
394 {
395 struct intel_fbc_work *work =
396 container_of(to_delayed_work(__work),
397 struct intel_fbc_work, work);
398 struct drm_device *dev = work->crtc->dev;
399 struct drm_i915_private *dev_priv = dev->dev_private;
400
401 mutex_lock(&dev->struct_mutex);
402 if (work == dev_priv->fbc.fbc_work) {
403 /* Double check that we haven't switched fb without cancelling
404 * the prior work.
405 */
406 if (work->crtc->primary->fb == work->fb) {
407 dev_priv->display.enable_fbc(work->crtc);
408
409 dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;
410 dev_priv->fbc.fb_id = work->crtc->primary->fb->base.id;
411 dev_priv->fbc.y = work->crtc->y;
412 }
413
414 dev_priv->fbc.fbc_work = NULL;
415 }
416 mutex_unlock(&dev->struct_mutex);
417
418 kfree(work);
419 }
420
421 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
422 {
423 if (dev_priv->fbc.fbc_work == NULL)
424 return;
425
426 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
427
428 /* Synchronisation is provided by struct_mutex and checking of
429 * dev_priv->fbc.fbc_work, so we can perform the cancellation
430 * entirely asynchronously.
431 */
432 if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
433 /* tasklet was killed before being run, clean up */
434 kfree(dev_priv->fbc.fbc_work);
435
436 /* Mark the work as no longer wanted so that if it does
437 * wake-up (because the work was already running and waiting
438 * for our mutex), it will discover that is no longer
439 * necessary to run.
440 */
441 dev_priv->fbc.fbc_work = NULL;
442 }
443
444 static void intel_enable_fbc(struct drm_crtc *crtc)
445 {
446 struct intel_fbc_work *work;
447 struct drm_device *dev = crtc->dev;
448 struct drm_i915_private *dev_priv = dev->dev_private;
449
450 if (!dev_priv->display.enable_fbc)
451 return;
452
453 intel_cancel_fbc_work(dev_priv);
454
455 work = kzalloc(sizeof(*work), GFP_KERNEL);
456 if (work == NULL) {
457 DRM_ERROR("Failed to allocate FBC work structure\n");
458 dev_priv->display.enable_fbc(crtc);
459 return;
460 }
461
462 work->crtc = crtc;
463 work->fb = crtc->primary->fb;
464 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
465
466 dev_priv->fbc.fbc_work = work;
467
468 /* Delay the actual enabling to let pageflipping cease and the
469 * display to settle before starting the compression. Note that
470 * this delay also serves a second purpose: it allows for a
471 * vblank to pass after disabling the FBC before we attempt
472 * to modify the control registers.
473 *
474 * A more complicated solution would involve tracking vblanks
475 * following the termination of the page-flipping sequence
476 * and indeed performing the enable as a co-routine and not
477 * waiting synchronously upon the vblank.
478 *
479 * WaFbcWaitForVBlankBeforeEnable:ilk,snb
480 */
481 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
482 }
483
484 void intel_disable_fbc(struct drm_device *dev)
485 {
486 struct drm_i915_private *dev_priv = dev->dev_private;
487
488 intel_cancel_fbc_work(dev_priv);
489
490 if (!dev_priv->display.disable_fbc)
491 return;
492
493 dev_priv->display.disable_fbc(dev);
494 dev_priv->fbc.plane = -1;
495 }
496
497 static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
498 enum no_fbc_reason reason)
499 {
500 if (dev_priv->fbc.no_fbc_reason == reason)
501 return false;
502
503 dev_priv->fbc.no_fbc_reason = reason;
504 return true;
505 }
506
507 /**
508 * intel_update_fbc - enable/disable FBC as needed
509 * @dev: the drm_device
510 *
511 * Set up the framebuffer compression hardware at mode set time. We
512 * enable it if possible:
513 * - plane A only (on pre-965)
514 * - no pixel mulitply/line duplication
515 * - no alpha buffer discard
516 * - no dual wide
517 * - framebuffer <= max_hdisplay in width, max_vdisplay in height
518 *
519 * We can't assume that any compression will take place (worst case),
520 * so the compressed buffer has to be the same size as the uncompressed
521 * one. It also must reside (along with the line length buffer) in
522 * stolen memory.
523 *
524 * We need to enable/disable FBC on a global basis.
525 */
526 void intel_update_fbc(struct drm_device *dev)
527 {
528 struct drm_i915_private *dev_priv = dev->dev_private;
529 struct drm_crtc *crtc = NULL, *tmp_crtc;
530 struct intel_crtc *intel_crtc;
531 struct drm_framebuffer *fb;
532 struct drm_i915_gem_object *obj;
533 const struct drm_display_mode *adjusted_mode;
534 unsigned int max_width, max_height;
535
536 if (!HAS_FBC(dev)) {
537 set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED);
538 return;
539 }
540
541 if (!i915.powersave) {
542 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
543 DRM_DEBUG_KMS("fbc disabled per module param\n");
544 return;
545 }
546
547 /*
548 * If FBC is already on, we just have to verify that we can
549 * keep it that way...
550 * Need to disable if:
551 * - more than one pipe is active
552 * - changing FBC params (stride, fence, mode)
553 * - new fb is too large to fit in compressed buffer
554 * - going to an unsupported config (interlace, pixel multiply, etc.)
555 */
556 for_each_crtc(dev, tmp_crtc) {
557 if (intel_crtc_active(tmp_crtc) &&
558 to_intel_crtc(tmp_crtc)->primary_enabled) {
559 if (crtc) {
560 if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
561 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
562 goto out_disable;
563 }
564 crtc = tmp_crtc;
565 }
566 }
567
568 if (!crtc || crtc->primary->fb == NULL) {
569 if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
570 DRM_DEBUG_KMS("no output, disabling\n");
571 goto out_disable;
572 }
573
574 intel_crtc = to_intel_crtc(crtc);
575 fb = crtc->primary->fb;
576 obj = intel_fb_obj(fb);
577 adjusted_mode = &intel_crtc->config.adjusted_mode;
578
579 if (i915.enable_fbc < 0) {
580 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
581 DRM_DEBUG_KMS("disabled per chip default\n");
582 goto out_disable;
583 }
584 if (!i915.enable_fbc) {
585 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
586 DRM_DEBUG_KMS("fbc disabled per module param\n");
587 goto out_disable;
588 }
589 if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ||
590 (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
591 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
592 DRM_DEBUG_KMS("mode incompatible with compression, "
593 "disabling\n");
594 goto out_disable;
595 }
596
597 if (INTEL_INFO(dev)->gen >= 8 || IS_HASWELL(dev)) {
598 max_width = 4096;
599 max_height = 4096;
600 } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
601 max_width = 4096;
602 max_height = 2048;
603 } else {
604 max_width = 2048;
605 max_height = 1536;
606 }
607 if (intel_crtc->config.pipe_src_w > max_width ||
608 intel_crtc->config.pipe_src_h > max_height) {
609 if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
610 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
611 goto out_disable;
612 }
613 if ((INTEL_INFO(dev)->gen < 4 || HAS_DDI(dev)) &&
614 intel_crtc->plane != PLANE_A) {
615 if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
616 DRM_DEBUG_KMS("plane not A, disabling compression\n");
617 goto out_disable;
618 }
619
620 /* The use of a CPU fence is mandatory in order to detect writes
621 * by the CPU to the scanout and trigger updates to the FBC.
622 */
623 if (obj->tiling_mode != I915_TILING_X ||
624 obj->fence_reg == I915_FENCE_REG_NONE) {
625 if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED))
626 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
627 goto out_disable;
628 }
629 if (INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
630 to_intel_plane(crtc->primary)->rotation != BIT(DRM_ROTATE_0)) {
631 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
632 DRM_DEBUG_KMS("Rotation unsupported, disabling\n");
633 goto out_disable;
634 }
635
636 /* If the kernel debugger is active, always disable compression */
637 if (in_dbg_master())
638 goto out_disable;
639
640 if (i915_gem_stolen_setup_compression(dev, obj->base.size,
641 drm_format_plane_cpp(fb->pixel_format, 0))) {
642 if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL))
643 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
644 goto out_disable;
645 }
646
647 /* If the scanout has not changed, don't modify the FBC settings.
648 * Note that we make the fundamental assumption that the fb->obj
649 * cannot be unpinned (and have its GTT offset and fence revoked)
650 * without first being decoupled from the scanout and FBC disabled.
651 */
652 if (dev_priv->fbc.plane == intel_crtc->plane &&
653 dev_priv->fbc.fb_id == fb->base.id &&
654 dev_priv->fbc.y == crtc->y)
655 return;
656
657 if (intel_fbc_enabled(dev)) {
658 /* We update FBC along two paths, after changing fb/crtc
659 * configuration (modeswitching) and after page-flipping
660 * finishes. For the latter, we know that not only did
661 * we disable the FBC at the start of the page-flip
662 * sequence, but also more than one vblank has passed.
663 *
664 * For the former case of modeswitching, it is possible
665 * to switch between two FBC valid configurations
666 * instantaneously so we do need to disable the FBC
667 * before we can modify its control registers. We also
668 * have to wait for the next vblank for that to take
669 * effect. However, since we delay enabling FBC we can
670 * assume that a vblank has passed since disabling and
671 * that we can safely alter the registers in the deferred
672 * callback.
673 *
674 * In the scenario that we go from a valid to invalid
675 * and then back to valid FBC configuration we have
676 * no strict enforcement that a vblank occurred since
677 * disabling the FBC. However, along all current pipe
678 * disabling paths we do need to wait for a vblank at
679 * some point. And we wait before enabling FBC anyway.
680 */
681 DRM_DEBUG_KMS("disabling active FBC for update\n");
682 intel_disable_fbc(dev);
683 }
684
685 intel_enable_fbc(crtc);
686 dev_priv->fbc.no_fbc_reason = FBC_OK;
687 return;
688
689 out_disable:
690 /* Multiple disables should be harmless */
691 if (intel_fbc_enabled(dev)) {
692 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
693 intel_disable_fbc(dev);
694 }
695 i915_gem_stolen_cleanup_compression(dev);
696 }
697
698 static void i915_pineview_get_mem_freq(struct drm_device *dev)
699 {
700 struct drm_i915_private *dev_priv = dev->dev_private;
701 u32 tmp;
702
703 tmp = I915_READ(CLKCFG);
704
705 switch (tmp & CLKCFG_FSB_MASK) {
706 case CLKCFG_FSB_533:
707 dev_priv->fsb_freq = 533; /* 133*4 */
708 break;
709 case CLKCFG_FSB_800:
710 dev_priv->fsb_freq = 800; /* 200*4 */
711 break;
712 case CLKCFG_FSB_667:
713 dev_priv->fsb_freq = 667; /* 167*4 */
714 break;
715 case CLKCFG_FSB_400:
716 dev_priv->fsb_freq = 400; /* 100*4 */
717 break;
718 }
719
720 switch (tmp & CLKCFG_MEM_MASK) {
721 case CLKCFG_MEM_533:
722 dev_priv->mem_freq = 533;
723 break;
724 case CLKCFG_MEM_667:
725 dev_priv->mem_freq = 667;
726 break;
727 case CLKCFG_MEM_800:
728 dev_priv->mem_freq = 800;
729 break;
730 }
731
732 /* detect pineview DDR3 setting */
733 tmp = I915_READ(CSHRDDR3CTL);
734 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
735 }
736
737 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
738 {
739 struct drm_i915_private *dev_priv = dev->dev_private;
740 u16 ddrpll, csipll;
741
742 ddrpll = I915_READ16(DDRMPLL1);
743 csipll = I915_READ16(CSIPLL0);
744
745 switch (ddrpll & 0xff) {
746 case 0xc:
747 dev_priv->mem_freq = 800;
748 break;
749 case 0x10:
750 dev_priv->mem_freq = 1066;
751 break;
752 case 0x14:
753 dev_priv->mem_freq = 1333;
754 break;
755 case 0x18:
756 dev_priv->mem_freq = 1600;
757 break;
758 default:
759 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
760 ddrpll & 0xff);
761 dev_priv->mem_freq = 0;
762 break;
763 }
764
765 dev_priv->ips.r_t = dev_priv->mem_freq;
766
767 switch (csipll & 0x3ff) {
768 case 0x00c:
769 dev_priv->fsb_freq = 3200;
770 break;
771 case 0x00e:
772 dev_priv->fsb_freq = 3733;
773 break;
774 case 0x010:
775 dev_priv->fsb_freq = 4266;
776 break;
777 case 0x012:
778 dev_priv->fsb_freq = 4800;
779 break;
780 case 0x014:
781 dev_priv->fsb_freq = 5333;
782 break;
783 case 0x016:
784 dev_priv->fsb_freq = 5866;
785 break;
786 case 0x018:
787 dev_priv->fsb_freq = 6400;
788 break;
789 default:
790 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
791 csipll & 0x3ff);
792 dev_priv->fsb_freq = 0;
793 break;
794 }
795
796 if (dev_priv->fsb_freq == 3200) {
797 dev_priv->ips.c_m = 0;
798 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
799 dev_priv->ips.c_m = 1;
800 } else {
801 dev_priv->ips.c_m = 2;
802 }
803 }
804
805 static const struct cxsr_latency cxsr_latency_table[] = {
806 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
807 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
808 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
809 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
810 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
811
812 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
813 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
814 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
815 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
816 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
817
818 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
819 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
820 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
821 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
822 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
823
824 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
825 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
826 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
827 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
828 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
829
830 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
831 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
832 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
833 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
834 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
835
836 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
837 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
838 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
839 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
840 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
841 };
842
843 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
844 int is_ddr3,
845 int fsb,
846 int mem)
847 {
848 const struct cxsr_latency *latency;
849 int i;
850
851 if (fsb == 0 || mem == 0)
852 return NULL;
853
854 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
855 latency = &cxsr_latency_table[i];
856 if (is_desktop == latency->is_desktop &&
857 is_ddr3 == latency->is_ddr3 &&
858 fsb == latency->fsb_freq && mem == latency->mem_freq)
859 return latency;
860 }
861
862 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
863
864 return NULL;
865 }
866
867 void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
868 {
869 struct drm_device *dev = dev_priv->dev;
870 u32 val;
871
872 if (IS_VALLEYVIEW(dev)) {
873 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
874 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
875 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
876 } else if (IS_PINEVIEW(dev)) {
877 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
878 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
879 I915_WRITE(DSPFW3, val);
880 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
881 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
882 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
883 I915_WRITE(FW_BLC_SELF, val);
884 } else if (IS_I915GM(dev)) {
885 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
886 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
887 I915_WRITE(INSTPM, val);
888 } else {
889 return;
890 }
891
892 DRM_DEBUG_KMS("memory self-refresh is %s\n",
893 enable ? "enabled" : "disabled");
894 }
895
896 /*
897 * Latency for FIFO fetches is dependent on several factors:
898 * - memory configuration (speed, channels)
899 * - chipset
900 * - current MCH state
901 * It can be fairly high in some situations, so here we assume a fairly
902 * pessimal value. It's a tradeoff between extra memory fetches (if we
903 * set this value too high, the FIFO will fetch frequently to stay full)
904 * and power consumption (set it too low to save power and we might see
905 * FIFO underruns and display "flicker").
906 *
907 * A value of 5us seems to be a good balance; safe for very low end
908 * platforms but not overly aggressive on lower latency configs.
909 */
910 static const int pessimal_latency_ns = 5000;
911
912 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
913 {
914 struct drm_i915_private *dev_priv = dev->dev_private;
915 uint32_t dsparb = I915_READ(DSPARB);
916 int size;
917
918 size = dsparb & 0x7f;
919 if (plane)
920 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
921
922 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
923 plane ? "B" : "A", size);
924
925 return size;
926 }
927
928 static int i830_get_fifo_size(struct drm_device *dev, int plane)
929 {
930 struct drm_i915_private *dev_priv = dev->dev_private;
931 uint32_t dsparb = I915_READ(DSPARB);
932 int size;
933
934 size = dsparb & 0x1ff;
935 if (plane)
936 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
937 size >>= 1; /* Convert to cachelines */
938
939 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
940 plane ? "B" : "A", size);
941
942 return size;
943 }
944
945 static int i845_get_fifo_size(struct drm_device *dev, int plane)
946 {
947 struct drm_i915_private *dev_priv = dev->dev_private;
948 uint32_t dsparb = I915_READ(DSPARB);
949 int size;
950
951 size = dsparb & 0x7f;
952 size >>= 2; /* Convert to cachelines */
953
954 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
955 plane ? "B" : "A",
956 size);
957
958 return size;
959 }
960
961 /* Pineview has different values for various configs */
962 static const struct intel_watermark_params pineview_display_wm = {
963 .fifo_size = PINEVIEW_DISPLAY_FIFO,
964 .max_wm = PINEVIEW_MAX_WM,
965 .default_wm = PINEVIEW_DFT_WM,
966 .guard_size = PINEVIEW_GUARD_WM,
967 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
968 };
969 static const struct intel_watermark_params pineview_display_hplloff_wm = {
970 .fifo_size = PINEVIEW_DISPLAY_FIFO,
971 .max_wm = PINEVIEW_MAX_WM,
972 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
973 .guard_size = PINEVIEW_GUARD_WM,
974 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
975 };
976 static const struct intel_watermark_params pineview_cursor_wm = {
977 .fifo_size = PINEVIEW_CURSOR_FIFO,
978 .max_wm = PINEVIEW_CURSOR_MAX_WM,
979 .default_wm = PINEVIEW_CURSOR_DFT_WM,
980 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
981 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
982 };
983 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
984 .fifo_size = PINEVIEW_CURSOR_FIFO,
985 .max_wm = PINEVIEW_CURSOR_MAX_WM,
986 .default_wm = PINEVIEW_CURSOR_DFT_WM,
987 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
988 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
989 };
990 static const struct intel_watermark_params g4x_wm_info = {
991 .fifo_size = G4X_FIFO_SIZE,
992 .max_wm = G4X_MAX_WM,
993 .default_wm = G4X_MAX_WM,
994 .guard_size = 2,
995 .cacheline_size = G4X_FIFO_LINE_SIZE,
996 };
997 static const struct intel_watermark_params g4x_cursor_wm_info = {
998 .fifo_size = I965_CURSOR_FIFO,
999 .max_wm = I965_CURSOR_MAX_WM,
1000 .default_wm = I965_CURSOR_DFT_WM,
1001 .guard_size = 2,
1002 .cacheline_size = G4X_FIFO_LINE_SIZE,
1003 };
1004 static const struct intel_watermark_params valleyview_wm_info = {
1005 .fifo_size = VALLEYVIEW_FIFO_SIZE,
1006 .max_wm = VALLEYVIEW_MAX_WM,
1007 .default_wm = VALLEYVIEW_MAX_WM,
1008 .guard_size = 2,
1009 .cacheline_size = G4X_FIFO_LINE_SIZE,
1010 };
1011 static const struct intel_watermark_params valleyview_cursor_wm_info = {
1012 .fifo_size = I965_CURSOR_FIFO,
1013 .max_wm = VALLEYVIEW_CURSOR_MAX_WM,
1014 .default_wm = I965_CURSOR_DFT_WM,
1015 .guard_size = 2,
1016 .cacheline_size = G4X_FIFO_LINE_SIZE,
1017 };
1018 static const struct intel_watermark_params i965_cursor_wm_info = {
1019 .fifo_size = I965_CURSOR_FIFO,
1020 .max_wm = I965_CURSOR_MAX_WM,
1021 .default_wm = I965_CURSOR_DFT_WM,
1022 .guard_size = 2,
1023 .cacheline_size = I915_FIFO_LINE_SIZE,
1024 };
1025 static const struct intel_watermark_params i945_wm_info = {
1026 .fifo_size = I945_FIFO_SIZE,
1027 .max_wm = I915_MAX_WM,
1028 .default_wm = 1,
1029 .guard_size = 2,
1030 .cacheline_size = I915_FIFO_LINE_SIZE,
1031 };
1032 static const struct intel_watermark_params i915_wm_info = {
1033 .fifo_size = I915_FIFO_SIZE,
1034 .max_wm = I915_MAX_WM,
1035 .default_wm = 1,
1036 .guard_size = 2,
1037 .cacheline_size = I915_FIFO_LINE_SIZE,
1038 };
1039 static const struct intel_watermark_params i830_a_wm_info = {
1040 .fifo_size = I855GM_FIFO_SIZE,
1041 .max_wm = I915_MAX_WM,
1042 .default_wm = 1,
1043 .guard_size = 2,
1044 .cacheline_size = I830_FIFO_LINE_SIZE,
1045 };
1046 static const struct intel_watermark_params i830_bc_wm_info = {
1047 .fifo_size = I855GM_FIFO_SIZE,
1048 .max_wm = I915_MAX_WM/2,
1049 .default_wm = 1,
1050 .guard_size = 2,
1051 .cacheline_size = I830_FIFO_LINE_SIZE,
1052 };
1053 static const struct intel_watermark_params i845_wm_info = {
1054 .fifo_size = I830_FIFO_SIZE,
1055 .max_wm = I915_MAX_WM,
1056 .default_wm = 1,
1057 .guard_size = 2,
1058 .cacheline_size = I830_FIFO_LINE_SIZE,
1059 };
1060
1061 /**
1062 * intel_calculate_wm - calculate watermark level
1063 * @clock_in_khz: pixel clock
1064 * @wm: chip FIFO params
1065 * @pixel_size: display pixel size
1066 * @latency_ns: memory latency for the platform
1067 *
1068 * Calculate the watermark level (the level at which the display plane will
1069 * start fetching from memory again). Each chip has a different display
1070 * FIFO size and allocation, so the caller needs to figure that out and pass
1071 * in the correct intel_watermark_params structure.
1072 *
1073 * As the pixel clock runs, the FIFO will be drained at a rate that depends
1074 * on the pixel size. When it reaches the watermark level, it'll start
1075 * fetching FIFO line sized based chunks from memory until the FIFO fills
1076 * past the watermark point. If the FIFO drains completely, a FIFO underrun
1077 * will occur, and a display engine hang could result.
1078 */
1079 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
1080 const struct intel_watermark_params *wm,
1081 int fifo_size,
1082 int pixel_size,
1083 unsigned long latency_ns)
1084 {
1085 long entries_required, wm_size;
1086
1087 /*
1088 * Note: we need to make sure we don't overflow for various clock &
1089 * latency values.
1090 * clocks go from a few thousand to several hundred thousand.
1091 * latency is usually a few thousand
1092 */
1093 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
1094 1000;
1095 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
1096
1097 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
1098
1099 wm_size = fifo_size - (entries_required + wm->guard_size);
1100
1101 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
1102
1103 /* Don't promote wm_size to unsigned... */
1104 if (wm_size > (long)wm->max_wm)
1105 wm_size = wm->max_wm;
1106 if (wm_size <= 0)
1107 wm_size = wm->default_wm;
1108
1109 /*
1110 * Bspec seems to indicate that the value shouldn't be lower than
1111 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
1112 * Lets go for 8 which is the burst size since certain platforms
1113 * already use a hardcoded 8 (which is what the spec says should be
1114 * done).
1115 */
1116 if (wm_size <= 8)
1117 wm_size = 8;
1118
1119 return wm_size;
1120 }
1121
1122 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1123 {
1124 struct drm_crtc *crtc, *enabled = NULL;
1125
1126 for_each_crtc(dev, crtc) {
1127 if (intel_crtc_active(crtc)) {
1128 if (enabled)
1129 return NULL;
1130 enabled = crtc;
1131 }
1132 }
1133
1134 return enabled;
1135 }
1136
1137 static void pineview_update_wm(struct drm_crtc *unused_crtc)
1138 {
1139 struct drm_device *dev = unused_crtc->dev;
1140 struct drm_i915_private *dev_priv = dev->dev_private;
1141 struct drm_crtc *crtc;
1142 const struct cxsr_latency *latency;
1143 u32 reg;
1144 unsigned long wm;
1145
1146 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1147 dev_priv->fsb_freq, dev_priv->mem_freq);
1148 if (!latency) {
1149 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1150 intel_set_memory_cxsr(dev_priv, false);
1151 return;
1152 }
1153
1154 crtc = single_enabled_crtc(dev);
1155 if (crtc) {
1156 const struct drm_display_mode *adjusted_mode;
1157 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1158 int clock;
1159
1160 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1161 clock = adjusted_mode->crtc_clock;
1162
1163 /* Display SR */
1164 wm = intel_calculate_wm(clock, &pineview_display_wm,
1165 pineview_display_wm.fifo_size,
1166 pixel_size, latency->display_sr);
1167 reg = I915_READ(DSPFW1);
1168 reg &= ~DSPFW_SR_MASK;
1169 reg |= wm << DSPFW_SR_SHIFT;
1170 I915_WRITE(DSPFW1, reg);
1171 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1172
1173 /* cursor SR */
1174 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1175 pineview_display_wm.fifo_size,
1176 pixel_size, latency->cursor_sr);
1177 reg = I915_READ(DSPFW3);
1178 reg &= ~DSPFW_CURSOR_SR_MASK;
1179 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1180 I915_WRITE(DSPFW3, reg);
1181
1182 /* Display HPLL off SR */
1183 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1184 pineview_display_hplloff_wm.fifo_size,
1185 pixel_size, latency->display_hpll_disable);
1186 reg = I915_READ(DSPFW3);
1187 reg &= ~DSPFW_HPLL_SR_MASK;
1188 reg |= wm & DSPFW_HPLL_SR_MASK;
1189 I915_WRITE(DSPFW3, reg);
1190
1191 /* cursor HPLL off SR */
1192 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1193 pineview_display_hplloff_wm.fifo_size,
1194 pixel_size, latency->cursor_hpll_disable);
1195 reg = I915_READ(DSPFW3);
1196 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1197 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1198 I915_WRITE(DSPFW3, reg);
1199 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1200
1201 intel_set_memory_cxsr(dev_priv, true);
1202 } else {
1203 intel_set_memory_cxsr(dev_priv, false);
1204 }
1205 }
1206
1207 static bool g4x_compute_wm0(struct drm_device *dev,
1208 int plane,
1209 const struct intel_watermark_params *display,
1210 int display_latency_ns,
1211 const struct intel_watermark_params *cursor,
1212 int cursor_latency_ns,
1213 int *plane_wm,
1214 int *cursor_wm)
1215 {
1216 struct drm_crtc *crtc;
1217 const struct drm_display_mode *adjusted_mode;
1218 int htotal, hdisplay, clock, pixel_size;
1219 int line_time_us, line_count;
1220 int entries, tlb_miss;
1221
1222 crtc = intel_get_crtc_for_plane(dev, plane);
1223 if (!intel_crtc_active(crtc)) {
1224 *cursor_wm = cursor->guard_size;
1225 *plane_wm = display->guard_size;
1226 return false;
1227 }
1228
1229 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1230 clock = adjusted_mode->crtc_clock;
1231 htotal = adjusted_mode->crtc_htotal;
1232 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1233 pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1234
1235 /* Use the small buffer method to calculate plane watermark */
1236 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1237 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1238 if (tlb_miss > 0)
1239 entries += tlb_miss;
1240 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1241 *plane_wm = entries + display->guard_size;
1242 if (*plane_wm > (int)display->max_wm)
1243 *plane_wm = display->max_wm;
1244
1245 /* Use the large buffer method to calculate cursor watermark */
1246 line_time_us = max(htotal * 1000 / clock, 1);
1247 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1248 entries = line_count * to_intel_crtc(crtc)->cursor_width * pixel_size;
1249 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1250 if (tlb_miss > 0)
1251 entries += tlb_miss;
1252 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1253 *cursor_wm = entries + cursor->guard_size;
1254 if (*cursor_wm > (int)cursor->max_wm)
1255 *cursor_wm = (int)cursor->max_wm;
1256
1257 return true;
1258 }
1259
1260 /*
1261 * Check the wm result.
1262 *
1263 * If any calculated watermark values is larger than the maximum value that
1264 * can be programmed into the associated watermark register, that watermark
1265 * must be disabled.
1266 */
1267 static bool g4x_check_srwm(struct drm_device *dev,
1268 int display_wm, int cursor_wm,
1269 const struct intel_watermark_params *display,
1270 const struct intel_watermark_params *cursor)
1271 {
1272 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1273 display_wm, cursor_wm);
1274
1275 if (display_wm > display->max_wm) {
1276 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1277 display_wm, display->max_wm);
1278 return false;
1279 }
1280
1281 if (cursor_wm > cursor->max_wm) {
1282 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1283 cursor_wm, cursor->max_wm);
1284 return false;
1285 }
1286
1287 if (!(display_wm || cursor_wm)) {
1288 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1289 return false;
1290 }
1291
1292 return true;
1293 }
1294
1295 static bool g4x_compute_srwm(struct drm_device *dev,
1296 int plane,
1297 int latency_ns,
1298 const struct intel_watermark_params *display,
1299 const struct intel_watermark_params *cursor,
1300 int *display_wm, int *cursor_wm)
1301 {
1302 struct drm_crtc *crtc;
1303 const struct drm_display_mode *adjusted_mode;
1304 int hdisplay, htotal, pixel_size, clock;
1305 unsigned long line_time_us;
1306 int line_count, line_size;
1307 int small, large;
1308 int entries;
1309
1310 if (!latency_ns) {
1311 *display_wm = *cursor_wm = 0;
1312 return false;
1313 }
1314
1315 crtc = intel_get_crtc_for_plane(dev, plane);
1316 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1317 clock = adjusted_mode->crtc_clock;
1318 htotal = adjusted_mode->crtc_htotal;
1319 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1320 pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1321
1322 line_time_us = max(htotal * 1000 / clock, 1);
1323 line_count = (latency_ns / line_time_us + 1000) / 1000;
1324 line_size = hdisplay * pixel_size;
1325
1326 /* Use the minimum of the small and large buffer method for primary */
1327 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1328 large = line_count * line_size;
1329
1330 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1331 *display_wm = entries + display->guard_size;
1332
1333 /* calculate the self-refresh watermark for display cursor */
1334 entries = line_count * pixel_size * to_intel_crtc(crtc)->cursor_width;
1335 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1336 *cursor_wm = entries + cursor->guard_size;
1337
1338 return g4x_check_srwm(dev,
1339 *display_wm, *cursor_wm,
1340 display, cursor);
1341 }
1342
1343 static bool vlv_compute_drain_latency(struct drm_crtc *crtc,
1344 int pixel_size,
1345 int *prec_mult,
1346 int *drain_latency)
1347 {
1348 struct drm_device *dev = crtc->dev;
1349 int entries;
1350 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
1351
1352 if (WARN(clock == 0, "Pixel clock is zero!\n"))
1353 return false;
1354
1355 if (WARN(pixel_size == 0, "Pixel size is zero!\n"))
1356 return false;
1357
1358 entries = DIV_ROUND_UP(clock, 1000) * pixel_size;
1359 if (IS_CHERRYVIEW(dev))
1360 *prec_mult = (entries > 128) ? DRAIN_LATENCY_PRECISION_32 :
1361 DRAIN_LATENCY_PRECISION_16;
1362 else
1363 *prec_mult = (entries > 128) ? DRAIN_LATENCY_PRECISION_64 :
1364 DRAIN_LATENCY_PRECISION_32;
1365 *drain_latency = (64 * (*prec_mult) * 4) / entries;
1366
1367 if (*drain_latency > DRAIN_LATENCY_MASK)
1368 *drain_latency = DRAIN_LATENCY_MASK;
1369
1370 return true;
1371 }
1372
1373 /*
1374 * Update drain latency registers of memory arbiter
1375 *
1376 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1377 * to be programmed. Each plane has a drain latency multiplier and a drain
1378 * latency value.
1379 */
1380
1381 static void vlv_update_drain_latency(struct drm_crtc *crtc)
1382 {
1383 struct drm_device *dev = crtc->dev;
1384 struct drm_i915_private *dev_priv = dev->dev_private;
1385 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1386 int pixel_size;
1387 int drain_latency;
1388 enum pipe pipe = intel_crtc->pipe;
1389 int plane_prec, prec_mult, plane_dl;
1390 const int high_precision = IS_CHERRYVIEW(dev) ?
1391 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_64;
1392
1393 plane_dl = I915_READ(VLV_DDL(pipe)) & ~(DDL_PLANE_PRECISION_HIGH |
1394 DRAIN_LATENCY_MASK | DDL_CURSOR_PRECISION_HIGH |
1395 (DRAIN_LATENCY_MASK << DDL_CURSOR_SHIFT));
1396
1397 if (!intel_crtc_active(crtc)) {
1398 I915_WRITE(VLV_DDL(pipe), plane_dl);
1399 return;
1400 }
1401
1402 /* Primary plane Drain Latency */
1403 pixel_size = crtc->primary->fb->bits_per_pixel / 8; /* BPP */
1404 if (vlv_compute_drain_latency(crtc, pixel_size, &prec_mult, &drain_latency)) {
1405 plane_prec = (prec_mult == high_precision) ?
1406 DDL_PLANE_PRECISION_HIGH :
1407 DDL_PLANE_PRECISION_LOW;
1408 plane_dl |= plane_prec | drain_latency;
1409 }
1410
1411 /* Cursor Drain Latency
1412 * BPP is always 4 for cursor
1413 */
1414 pixel_size = 4;
1415
1416 /* Program cursor DL only if it is enabled */
1417 if (intel_crtc->cursor_base &&
1418 vlv_compute_drain_latency(crtc, pixel_size, &prec_mult, &drain_latency)) {
1419 plane_prec = (prec_mult == high_precision) ?
1420 DDL_CURSOR_PRECISION_HIGH :
1421 DDL_CURSOR_PRECISION_LOW;
1422 plane_dl |= plane_prec | (drain_latency << DDL_CURSOR_SHIFT);
1423 }
1424
1425 I915_WRITE(VLV_DDL(pipe), plane_dl);
1426 }
1427
1428 #define single_plane_enabled(mask) is_power_of_2(mask)
1429
1430 static void valleyview_update_wm(struct drm_crtc *crtc)
1431 {
1432 struct drm_device *dev = crtc->dev;
1433 static const int sr_latency_ns = 12000;
1434 struct drm_i915_private *dev_priv = dev->dev_private;
1435 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1436 int plane_sr, cursor_sr;
1437 int ignore_plane_sr, ignore_cursor_sr;
1438 unsigned int enabled = 0;
1439 bool cxsr_enabled;
1440
1441 vlv_update_drain_latency(crtc);
1442
1443 if (g4x_compute_wm0(dev, PIPE_A,
1444 &valleyview_wm_info, pessimal_latency_ns,
1445 &valleyview_cursor_wm_info, pessimal_latency_ns,
1446 &planea_wm, &cursora_wm))
1447 enabled |= 1 << PIPE_A;
1448
1449 if (g4x_compute_wm0(dev, PIPE_B,
1450 &valleyview_wm_info, pessimal_latency_ns,
1451 &valleyview_cursor_wm_info, pessimal_latency_ns,
1452 &planeb_wm, &cursorb_wm))
1453 enabled |= 1 << PIPE_B;
1454
1455 if (single_plane_enabled(enabled) &&
1456 g4x_compute_srwm(dev, ffs(enabled) - 1,
1457 sr_latency_ns,
1458 &valleyview_wm_info,
1459 &valleyview_cursor_wm_info,
1460 &plane_sr, &ignore_cursor_sr) &&
1461 g4x_compute_srwm(dev, ffs(enabled) - 1,
1462 2*sr_latency_ns,
1463 &valleyview_wm_info,
1464 &valleyview_cursor_wm_info,
1465 &ignore_plane_sr, &cursor_sr)) {
1466 cxsr_enabled = true;
1467 } else {
1468 cxsr_enabled = false;
1469 intel_set_memory_cxsr(dev_priv, false);
1470 plane_sr = cursor_sr = 0;
1471 }
1472
1473 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1474 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1475 planea_wm, cursora_wm,
1476 planeb_wm, cursorb_wm,
1477 plane_sr, cursor_sr);
1478
1479 I915_WRITE(DSPFW1,
1480 (plane_sr << DSPFW_SR_SHIFT) |
1481 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1482 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1483 (planea_wm << DSPFW_PLANEA_SHIFT));
1484 I915_WRITE(DSPFW2,
1485 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1486 (cursora_wm << DSPFW_CURSORA_SHIFT));
1487 I915_WRITE(DSPFW3,
1488 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1489 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1490
1491 if (cxsr_enabled)
1492 intel_set_memory_cxsr(dev_priv, true);
1493 }
1494
1495 static void cherryview_update_wm(struct drm_crtc *crtc)
1496 {
1497 struct drm_device *dev = crtc->dev;
1498 static const int sr_latency_ns = 12000;
1499 struct drm_i915_private *dev_priv = dev->dev_private;
1500 int planea_wm, planeb_wm, planec_wm;
1501 int cursora_wm, cursorb_wm, cursorc_wm;
1502 int plane_sr, cursor_sr;
1503 int ignore_plane_sr, ignore_cursor_sr;
1504 unsigned int enabled = 0;
1505 bool cxsr_enabled;
1506
1507 vlv_update_drain_latency(crtc);
1508
1509 if (g4x_compute_wm0(dev, PIPE_A,
1510 &valleyview_wm_info, pessimal_latency_ns,
1511 &valleyview_cursor_wm_info, pessimal_latency_ns,
1512 &planea_wm, &cursora_wm))
1513 enabled |= 1 << PIPE_A;
1514
1515 if (g4x_compute_wm0(dev, PIPE_B,
1516 &valleyview_wm_info, pessimal_latency_ns,
1517 &valleyview_cursor_wm_info, pessimal_latency_ns,
1518 &planeb_wm, &cursorb_wm))
1519 enabled |= 1 << PIPE_B;
1520
1521 if (g4x_compute_wm0(dev, PIPE_C,
1522 &valleyview_wm_info, pessimal_latency_ns,
1523 &valleyview_cursor_wm_info, pessimal_latency_ns,
1524 &planec_wm, &cursorc_wm))
1525 enabled |= 1 << PIPE_C;
1526
1527 if (single_plane_enabled(enabled) &&
1528 g4x_compute_srwm(dev, ffs(enabled) - 1,
1529 sr_latency_ns,
1530 &valleyview_wm_info,
1531 &valleyview_cursor_wm_info,
1532 &plane_sr, &ignore_cursor_sr) &&
1533 g4x_compute_srwm(dev, ffs(enabled) - 1,
1534 2*sr_latency_ns,
1535 &valleyview_wm_info,
1536 &valleyview_cursor_wm_info,
1537 &ignore_plane_sr, &cursor_sr)) {
1538 cxsr_enabled = true;
1539 } else {
1540 cxsr_enabled = false;
1541 intel_set_memory_cxsr(dev_priv, false);
1542 plane_sr = cursor_sr = 0;
1543 }
1544
1545 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1546 "B: plane=%d, cursor=%d, C: plane=%d, cursor=%d, "
1547 "SR: plane=%d, cursor=%d\n",
1548 planea_wm, cursora_wm,
1549 planeb_wm, cursorb_wm,
1550 planec_wm, cursorc_wm,
1551 plane_sr, cursor_sr);
1552
1553 I915_WRITE(DSPFW1,
1554 (plane_sr << DSPFW_SR_SHIFT) |
1555 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1556 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1557 (planea_wm << DSPFW_PLANEA_SHIFT));
1558 I915_WRITE(DSPFW2,
1559 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1560 (cursora_wm << DSPFW_CURSORA_SHIFT));
1561 I915_WRITE(DSPFW3,
1562 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1563 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1564 I915_WRITE(DSPFW9_CHV,
1565 (I915_READ(DSPFW9_CHV) & ~(DSPFW_PLANEC_MASK |
1566 DSPFW_CURSORC_MASK)) |
1567 (planec_wm << DSPFW_PLANEC_SHIFT) |
1568 (cursorc_wm << DSPFW_CURSORC_SHIFT));
1569
1570 if (cxsr_enabled)
1571 intel_set_memory_cxsr(dev_priv, true);
1572 }
1573
1574 static void valleyview_update_sprite_wm(struct drm_plane *plane,
1575 struct drm_crtc *crtc,
1576 uint32_t sprite_width,
1577 uint32_t sprite_height,
1578 int pixel_size,
1579 bool enabled, bool scaled)
1580 {
1581 struct drm_device *dev = crtc->dev;
1582 struct drm_i915_private *dev_priv = dev->dev_private;
1583 int pipe = to_intel_plane(plane)->pipe;
1584 int sprite = to_intel_plane(plane)->plane;
1585 int drain_latency;
1586 int plane_prec;
1587 int sprite_dl;
1588 int prec_mult;
1589 const int high_precision = IS_CHERRYVIEW(dev) ?
1590 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_64;
1591
1592 sprite_dl = I915_READ(VLV_DDL(pipe)) & ~(DDL_SPRITE_PRECISION_HIGH(sprite) |
1593 (DRAIN_LATENCY_MASK << DDL_SPRITE_SHIFT(sprite)));
1594
1595 if (enabled && vlv_compute_drain_latency(crtc, pixel_size, &prec_mult,
1596 &drain_latency)) {
1597 plane_prec = (prec_mult == high_precision) ?
1598 DDL_SPRITE_PRECISION_HIGH(sprite) :
1599 DDL_SPRITE_PRECISION_LOW(sprite);
1600 sprite_dl |= plane_prec |
1601 (drain_latency << DDL_SPRITE_SHIFT(sprite));
1602 }
1603
1604 I915_WRITE(VLV_DDL(pipe), sprite_dl);
1605 }
1606
1607 static void g4x_update_wm(struct drm_crtc *crtc)
1608 {
1609 struct drm_device *dev = crtc->dev;
1610 static const int sr_latency_ns = 12000;
1611 struct drm_i915_private *dev_priv = dev->dev_private;
1612 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1613 int plane_sr, cursor_sr;
1614 unsigned int enabled = 0;
1615 bool cxsr_enabled;
1616
1617 if (g4x_compute_wm0(dev, PIPE_A,
1618 &g4x_wm_info, pessimal_latency_ns,
1619 &g4x_cursor_wm_info, pessimal_latency_ns,
1620 &planea_wm, &cursora_wm))
1621 enabled |= 1 << PIPE_A;
1622
1623 if (g4x_compute_wm0(dev, PIPE_B,
1624 &g4x_wm_info, pessimal_latency_ns,
1625 &g4x_cursor_wm_info, pessimal_latency_ns,
1626 &planeb_wm, &cursorb_wm))
1627 enabled |= 1 << PIPE_B;
1628
1629 if (single_plane_enabled(enabled) &&
1630 g4x_compute_srwm(dev, ffs(enabled) - 1,
1631 sr_latency_ns,
1632 &g4x_wm_info,
1633 &g4x_cursor_wm_info,
1634 &plane_sr, &cursor_sr)) {
1635 cxsr_enabled = true;
1636 } else {
1637 cxsr_enabled = false;
1638 intel_set_memory_cxsr(dev_priv, false);
1639 plane_sr = cursor_sr = 0;
1640 }
1641
1642 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1643 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1644 planea_wm, cursora_wm,
1645 planeb_wm, cursorb_wm,
1646 plane_sr, cursor_sr);
1647
1648 I915_WRITE(DSPFW1,
1649 (plane_sr << DSPFW_SR_SHIFT) |
1650 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1651 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1652 (planea_wm << DSPFW_PLANEA_SHIFT));
1653 I915_WRITE(DSPFW2,
1654 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1655 (cursora_wm << DSPFW_CURSORA_SHIFT));
1656 /* HPLL off in SR has some issues on G4x... disable it */
1657 I915_WRITE(DSPFW3,
1658 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1659 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1660
1661 if (cxsr_enabled)
1662 intel_set_memory_cxsr(dev_priv, true);
1663 }
1664
1665 static void i965_update_wm(struct drm_crtc *unused_crtc)
1666 {
1667 struct drm_device *dev = unused_crtc->dev;
1668 struct drm_i915_private *dev_priv = dev->dev_private;
1669 struct drm_crtc *crtc;
1670 int srwm = 1;
1671 int cursor_sr = 16;
1672 bool cxsr_enabled;
1673
1674 /* Calc sr entries for one plane configs */
1675 crtc = single_enabled_crtc(dev);
1676 if (crtc) {
1677 /* self-refresh has much higher latency */
1678 static const int sr_latency_ns = 12000;
1679 const struct drm_display_mode *adjusted_mode =
1680 &to_intel_crtc(crtc)->config.adjusted_mode;
1681 int clock = adjusted_mode->crtc_clock;
1682 int htotal = adjusted_mode->crtc_htotal;
1683 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1684 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1685 unsigned long line_time_us;
1686 int entries;
1687
1688 line_time_us = max(htotal * 1000 / clock, 1);
1689
1690 /* Use ns/us then divide to preserve precision */
1691 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1692 pixel_size * hdisplay;
1693 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1694 srwm = I965_FIFO_SIZE - entries;
1695 if (srwm < 0)
1696 srwm = 1;
1697 srwm &= 0x1ff;
1698 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1699 entries, srwm);
1700
1701 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1702 pixel_size * to_intel_crtc(crtc)->cursor_width;
1703 entries = DIV_ROUND_UP(entries,
1704 i965_cursor_wm_info.cacheline_size);
1705 cursor_sr = i965_cursor_wm_info.fifo_size -
1706 (entries + i965_cursor_wm_info.guard_size);
1707
1708 if (cursor_sr > i965_cursor_wm_info.max_wm)
1709 cursor_sr = i965_cursor_wm_info.max_wm;
1710
1711 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1712 "cursor %d\n", srwm, cursor_sr);
1713
1714 cxsr_enabled = true;
1715 } else {
1716 cxsr_enabled = false;
1717 /* Turn off self refresh if both pipes are enabled */
1718 intel_set_memory_cxsr(dev_priv, false);
1719 }
1720
1721 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1722 srwm);
1723
1724 /* 965 has limitations... */
1725 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1726 (8 << DSPFW_CURSORB_SHIFT) |
1727 (8 << DSPFW_PLANEB_SHIFT) |
1728 (8 << DSPFW_PLANEA_SHIFT));
1729 I915_WRITE(DSPFW2, (8 << DSPFW_CURSORA_SHIFT) |
1730 (8 << DSPFW_PLANEC_SHIFT_OLD));
1731 /* update cursor SR watermark */
1732 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1733
1734 if (cxsr_enabled)
1735 intel_set_memory_cxsr(dev_priv, true);
1736 }
1737
1738 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1739 {
1740 struct drm_device *dev = unused_crtc->dev;
1741 struct drm_i915_private *dev_priv = dev->dev_private;
1742 const struct intel_watermark_params *wm_info;
1743 uint32_t fwater_lo;
1744 uint32_t fwater_hi;
1745 int cwm, srwm = 1;
1746 int fifo_size;
1747 int planea_wm, planeb_wm;
1748 struct drm_crtc *crtc, *enabled = NULL;
1749
1750 if (IS_I945GM(dev))
1751 wm_info = &i945_wm_info;
1752 else if (!IS_GEN2(dev))
1753 wm_info = &i915_wm_info;
1754 else
1755 wm_info = &i830_a_wm_info;
1756
1757 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1758 crtc = intel_get_crtc_for_plane(dev, 0);
1759 if (intel_crtc_active(crtc)) {
1760 const struct drm_display_mode *adjusted_mode;
1761 int cpp = crtc->primary->fb->bits_per_pixel / 8;
1762 if (IS_GEN2(dev))
1763 cpp = 4;
1764
1765 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1766 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1767 wm_info, fifo_size, cpp,
1768 pessimal_latency_ns);
1769 enabled = crtc;
1770 } else {
1771 planea_wm = fifo_size - wm_info->guard_size;
1772 if (planea_wm > (long)wm_info->max_wm)
1773 planea_wm = wm_info->max_wm;
1774 }
1775
1776 if (IS_GEN2(dev))
1777 wm_info = &i830_bc_wm_info;
1778
1779 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1780 crtc = intel_get_crtc_for_plane(dev, 1);
1781 if (intel_crtc_active(crtc)) {
1782 const struct drm_display_mode *adjusted_mode;
1783 int cpp = crtc->primary->fb->bits_per_pixel / 8;
1784 if (IS_GEN2(dev))
1785 cpp = 4;
1786
1787 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1788 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1789 wm_info, fifo_size, cpp,
1790 pessimal_latency_ns);
1791 if (enabled == NULL)
1792 enabled = crtc;
1793 else
1794 enabled = NULL;
1795 } else {
1796 planeb_wm = fifo_size - wm_info->guard_size;
1797 if (planeb_wm > (long)wm_info->max_wm)
1798 planeb_wm = wm_info->max_wm;
1799 }
1800
1801 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1802
1803 if (IS_I915GM(dev) && enabled) {
1804 struct drm_i915_gem_object *obj;
1805
1806 obj = intel_fb_obj(enabled->primary->fb);
1807
1808 /* self-refresh seems busted with untiled */
1809 if (obj->tiling_mode == I915_TILING_NONE)
1810 enabled = NULL;
1811 }
1812
1813 /*
1814 * Overlay gets an aggressive default since video jitter is bad.
1815 */
1816 cwm = 2;
1817
1818 /* Play safe and disable self-refresh before adjusting watermarks. */
1819 intel_set_memory_cxsr(dev_priv, false);
1820
1821 /* Calc sr entries for one plane configs */
1822 if (HAS_FW_BLC(dev) && enabled) {
1823 /* self-refresh has much higher latency */
1824 static const int sr_latency_ns = 6000;
1825 const struct drm_display_mode *adjusted_mode =
1826 &to_intel_crtc(enabled)->config.adjusted_mode;
1827 int clock = adjusted_mode->crtc_clock;
1828 int htotal = adjusted_mode->crtc_htotal;
1829 int hdisplay = to_intel_crtc(enabled)->config.pipe_src_w;
1830 int pixel_size = enabled->primary->fb->bits_per_pixel / 8;
1831 unsigned long line_time_us;
1832 int entries;
1833
1834 line_time_us = max(htotal * 1000 / clock, 1);
1835
1836 /* Use ns/us then divide to preserve precision */
1837 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1838 pixel_size * hdisplay;
1839 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1840 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1841 srwm = wm_info->fifo_size - entries;
1842 if (srwm < 0)
1843 srwm = 1;
1844
1845 if (IS_I945G(dev) || IS_I945GM(dev))
1846 I915_WRITE(FW_BLC_SELF,
1847 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1848 else if (IS_I915GM(dev))
1849 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1850 }
1851
1852 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1853 planea_wm, planeb_wm, cwm, srwm);
1854
1855 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1856 fwater_hi = (cwm & 0x1f);
1857
1858 /* Set request length to 8 cachelines per fetch */
1859 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1860 fwater_hi = fwater_hi | (1 << 8);
1861
1862 I915_WRITE(FW_BLC, fwater_lo);
1863 I915_WRITE(FW_BLC2, fwater_hi);
1864
1865 if (enabled)
1866 intel_set_memory_cxsr(dev_priv, true);
1867 }
1868
1869 static void i845_update_wm(struct drm_crtc *unused_crtc)
1870 {
1871 struct drm_device *dev = unused_crtc->dev;
1872 struct drm_i915_private *dev_priv = dev->dev_private;
1873 struct drm_crtc *crtc;
1874 const struct drm_display_mode *adjusted_mode;
1875 uint32_t fwater_lo;
1876 int planea_wm;
1877
1878 crtc = single_enabled_crtc(dev);
1879 if (crtc == NULL)
1880 return;
1881
1882 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1883 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1884 &i845_wm_info,
1885 dev_priv->display.get_fifo_size(dev, 0),
1886 4, pessimal_latency_ns);
1887 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1888 fwater_lo |= (3<<8) | planea_wm;
1889
1890 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1891
1892 I915_WRITE(FW_BLC, fwater_lo);
1893 }
1894
1895 static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
1896 struct drm_crtc *crtc)
1897 {
1898 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1899 uint32_t pixel_rate;
1900
1901 pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock;
1902
1903 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1904 * adjust the pixel_rate here. */
1905
1906 if (intel_crtc->config.pch_pfit.enabled) {
1907 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1908 uint32_t pfit_size = intel_crtc->config.pch_pfit.size;
1909
1910 pipe_w = intel_crtc->config.pipe_src_w;
1911 pipe_h = intel_crtc->config.pipe_src_h;
1912 pfit_w = (pfit_size >> 16) & 0xFFFF;
1913 pfit_h = pfit_size & 0xFFFF;
1914 if (pipe_w < pfit_w)
1915 pipe_w = pfit_w;
1916 if (pipe_h < pfit_h)
1917 pipe_h = pfit_h;
1918
1919 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1920 pfit_w * pfit_h);
1921 }
1922
1923 return pixel_rate;
1924 }
1925
1926 /* latency must be in 0.1us units. */
1927 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
1928 uint32_t latency)
1929 {
1930 uint64_t ret;
1931
1932 if (WARN(latency == 0, "Latency value missing\n"))
1933 return UINT_MAX;
1934
1935 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1936 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1937
1938 return ret;
1939 }
1940
1941 /* latency must be in 0.1us units. */
1942 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1943 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1944 uint32_t latency)
1945 {
1946 uint32_t ret;
1947
1948 if (WARN(latency == 0, "Latency value missing\n"))
1949 return UINT_MAX;
1950
1951 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1952 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1953 ret = DIV_ROUND_UP(ret, 64) + 2;
1954 return ret;
1955 }
1956
1957 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1958 uint8_t bytes_per_pixel)
1959 {
1960 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1961 }
1962
1963 struct ilk_pipe_wm_parameters {
1964 bool active;
1965 uint32_t pipe_htotal;
1966 uint32_t pixel_rate;
1967 struct intel_plane_wm_parameters pri;
1968 struct intel_plane_wm_parameters spr;
1969 struct intel_plane_wm_parameters cur;
1970 };
1971
1972 struct ilk_wm_maximums {
1973 uint16_t pri;
1974 uint16_t spr;
1975 uint16_t cur;
1976 uint16_t fbc;
1977 };
1978
1979 /* used in computing the new watermarks state */
1980 struct intel_wm_config {
1981 unsigned int num_pipes_active;
1982 bool sprites_enabled;
1983 bool sprites_scaled;
1984 };
1985
1986 /*
1987 * For both WM_PIPE and WM_LP.
1988 * mem_value must be in 0.1us units.
1989 */
1990 static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params,
1991 uint32_t mem_value,
1992 bool is_lp)
1993 {
1994 uint32_t method1, method2;
1995
1996 if (!params->active || !params->pri.enabled)
1997 return 0;
1998
1999 method1 = ilk_wm_method1(params->pixel_rate,
2000 params->pri.bytes_per_pixel,
2001 mem_value);
2002
2003 if (!is_lp)
2004 return method1;
2005
2006 method2 = ilk_wm_method2(params->pixel_rate,
2007 params->pipe_htotal,
2008 params->pri.horiz_pixels,
2009 params->pri.bytes_per_pixel,
2010 mem_value);
2011
2012 return min(method1, method2);
2013 }
2014
2015 /*
2016 * For both WM_PIPE and WM_LP.
2017 * mem_value must be in 0.1us units.
2018 */
2019 static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params,
2020 uint32_t mem_value)
2021 {
2022 uint32_t method1, method2;
2023
2024 if (!params->active || !params->spr.enabled)
2025 return 0;
2026
2027 method1 = ilk_wm_method1(params->pixel_rate,
2028 params->spr.bytes_per_pixel,
2029 mem_value);
2030 method2 = ilk_wm_method2(params->pixel_rate,
2031 params->pipe_htotal,
2032 params->spr.horiz_pixels,
2033 params->spr.bytes_per_pixel,
2034 mem_value);
2035 return min(method1, method2);
2036 }
2037
2038 /*
2039 * For both WM_PIPE and WM_LP.
2040 * mem_value must be in 0.1us units.
2041 */
2042 static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params,
2043 uint32_t mem_value)
2044 {
2045 if (!params->active || !params->cur.enabled)
2046 return 0;
2047
2048 return ilk_wm_method2(params->pixel_rate,
2049 params->pipe_htotal,
2050 params->cur.horiz_pixels,
2051 params->cur.bytes_per_pixel,
2052 mem_value);
2053 }
2054
2055 /* Only for WM_LP. */
2056 static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params,
2057 uint32_t pri_val)
2058 {
2059 if (!params->active || !params->pri.enabled)
2060 return 0;
2061
2062 return ilk_wm_fbc(pri_val,
2063 params->pri.horiz_pixels,
2064 params->pri.bytes_per_pixel);
2065 }
2066
2067 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
2068 {
2069 if (INTEL_INFO(dev)->gen >= 8)
2070 return 3072;
2071 else if (INTEL_INFO(dev)->gen >= 7)
2072 return 768;
2073 else
2074 return 512;
2075 }
2076
2077 static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
2078 int level, bool is_sprite)
2079 {
2080 if (INTEL_INFO(dev)->gen >= 8)
2081 /* BDW primary/sprite plane watermarks */
2082 return level == 0 ? 255 : 2047;
2083 else if (INTEL_INFO(dev)->gen >= 7)
2084 /* IVB/HSW primary/sprite plane watermarks */
2085 return level == 0 ? 127 : 1023;
2086 else if (!is_sprite)
2087 /* ILK/SNB primary plane watermarks */
2088 return level == 0 ? 127 : 511;
2089 else
2090 /* ILK/SNB sprite plane watermarks */
2091 return level == 0 ? 63 : 255;
2092 }
2093
2094 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
2095 int level)
2096 {
2097 if (INTEL_INFO(dev)->gen >= 7)
2098 return level == 0 ? 63 : 255;
2099 else
2100 return level == 0 ? 31 : 63;
2101 }
2102
2103 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
2104 {
2105 if (INTEL_INFO(dev)->gen >= 8)
2106 return 31;
2107 else
2108 return 15;
2109 }
2110
2111 /* Calculate the maximum primary/sprite plane watermark */
2112 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
2113 int level,
2114 const struct intel_wm_config *config,
2115 enum intel_ddb_partitioning ddb_partitioning,
2116 bool is_sprite)
2117 {
2118 unsigned int fifo_size = ilk_display_fifo_size(dev);
2119
2120 /* if sprites aren't enabled, sprites get nothing */
2121 if (is_sprite && !config->sprites_enabled)
2122 return 0;
2123
2124 /* HSW allows LP1+ watermarks even with multiple pipes */
2125 if (level == 0 || config->num_pipes_active > 1) {
2126 fifo_size /= INTEL_INFO(dev)->num_pipes;
2127
2128 /*
2129 * For some reason the non self refresh
2130 * FIFO size is only half of the self
2131 * refresh FIFO size on ILK/SNB.
2132 */
2133 if (INTEL_INFO(dev)->gen <= 6)
2134 fifo_size /= 2;
2135 }
2136
2137 if (config->sprites_enabled) {
2138 /* level 0 is always calculated with 1:1 split */
2139 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
2140 if (is_sprite)
2141 fifo_size *= 5;
2142 fifo_size /= 6;
2143 } else {
2144 fifo_size /= 2;
2145 }
2146 }
2147
2148 /* clamp to max that the registers can hold */
2149 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
2150 }
2151
2152 /* Calculate the maximum cursor plane watermark */
2153 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
2154 int level,
2155 const struct intel_wm_config *config)
2156 {
2157 /* HSW LP1+ watermarks w/ multiple pipes */
2158 if (level > 0 && config->num_pipes_active > 1)
2159 return 64;
2160
2161 /* otherwise just report max that registers can hold */
2162 return ilk_cursor_wm_reg_max(dev, level);
2163 }
2164
2165 static void ilk_compute_wm_maximums(const struct drm_device *dev,
2166 int level,
2167 const struct intel_wm_config *config,
2168 enum intel_ddb_partitioning ddb_partitioning,
2169 struct ilk_wm_maximums *max)
2170 {
2171 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
2172 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
2173 max->cur = ilk_cursor_wm_max(dev, level, config);
2174 max->fbc = ilk_fbc_wm_reg_max(dev);
2175 }
2176
2177 static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
2178 int level,
2179 struct ilk_wm_maximums *max)
2180 {
2181 max->pri = ilk_plane_wm_reg_max(dev, level, false);
2182 max->spr = ilk_plane_wm_reg_max(dev, level, true);
2183 max->cur = ilk_cursor_wm_reg_max(dev, level);
2184 max->fbc = ilk_fbc_wm_reg_max(dev);
2185 }
2186
2187 static bool ilk_validate_wm_level(int level,
2188 const struct ilk_wm_maximums *max,
2189 struct intel_wm_level *result)
2190 {
2191 bool ret;
2192
2193 /* already determined to be invalid? */
2194 if (!result->enable)
2195 return false;
2196
2197 result->enable = result->pri_val <= max->pri &&
2198 result->spr_val <= max->spr &&
2199 result->cur_val <= max->cur;
2200
2201 ret = result->enable;
2202
2203 /*
2204 * HACK until we can pre-compute everything,
2205 * and thus fail gracefully if LP0 watermarks
2206 * are exceeded...
2207 */
2208 if (level == 0 && !result->enable) {
2209 if (result->pri_val > max->pri)
2210 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2211 level, result->pri_val, max->pri);
2212 if (result->spr_val > max->spr)
2213 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2214 level, result->spr_val, max->spr);
2215 if (result->cur_val > max->cur)
2216 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2217 level, result->cur_val, max->cur);
2218
2219 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2220 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2221 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2222 result->enable = true;
2223 }
2224
2225 return ret;
2226 }
2227
2228 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
2229 int level,
2230 const struct ilk_pipe_wm_parameters *p,
2231 struct intel_wm_level *result)
2232 {
2233 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2234 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2235 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2236
2237 /* WM1+ latency values stored in 0.5us units */
2238 if (level > 0) {
2239 pri_latency *= 5;
2240 spr_latency *= 5;
2241 cur_latency *= 5;
2242 }
2243
2244 result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
2245 result->spr_val = ilk_compute_spr_wm(p, spr_latency);
2246 result->cur_val = ilk_compute_cur_wm(p, cur_latency);
2247 result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
2248 result->enable = true;
2249 }
2250
2251 static uint32_t
2252 hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
2253 {
2254 struct drm_i915_private *dev_priv = dev->dev_private;
2255 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2256 struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
2257 u32 linetime, ips_linetime;
2258
2259 if (!intel_crtc_active(crtc))
2260 return 0;
2261
2262 /* The WM are computed with base on how long it takes to fill a single
2263 * row at the given clock rate, multiplied by 8.
2264 * */
2265 linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
2266 mode->crtc_clock);
2267 ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
2268 intel_ddi_get_cdclk_freq(dev_priv));
2269
2270 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2271 PIPE_WM_LINETIME_TIME(linetime);
2272 }
2273
2274 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5])
2275 {
2276 struct drm_i915_private *dev_priv = dev->dev_private;
2277
2278 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2279 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2280
2281 wm[0] = (sskpd >> 56) & 0xFF;
2282 if (wm[0] == 0)
2283 wm[0] = sskpd & 0xF;
2284 wm[1] = (sskpd >> 4) & 0xFF;
2285 wm[2] = (sskpd >> 12) & 0xFF;
2286 wm[3] = (sskpd >> 20) & 0x1FF;
2287 wm[4] = (sskpd >> 32) & 0x1FF;
2288 } else if (INTEL_INFO(dev)->gen >= 6) {
2289 uint32_t sskpd = I915_READ(MCH_SSKPD);
2290
2291 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2292 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2293 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2294 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2295 } else if (INTEL_INFO(dev)->gen >= 5) {
2296 uint32_t mltr = I915_READ(MLTR_ILK);
2297
2298 /* ILK primary LP0 latency is 700 ns */
2299 wm[0] = 7;
2300 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2301 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2302 }
2303 }
2304
2305 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2306 {
2307 /* ILK sprite LP0 latency is 1300 ns */
2308 if (INTEL_INFO(dev)->gen == 5)
2309 wm[0] = 13;
2310 }
2311
2312 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2313 {
2314 /* ILK cursor LP0 latency is 1300 ns */
2315 if (INTEL_INFO(dev)->gen == 5)
2316 wm[0] = 13;
2317
2318 /* WaDoubleCursorLP3Latency:ivb */
2319 if (IS_IVYBRIDGE(dev))
2320 wm[3] *= 2;
2321 }
2322
2323 int ilk_wm_max_level(const struct drm_device *dev)
2324 {
2325 /* how many WM levels are we expecting */
2326 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2327 return 4;
2328 else if (INTEL_INFO(dev)->gen >= 6)
2329 return 3;
2330 else
2331 return 2;
2332 }
2333
2334 static void intel_print_wm_latency(struct drm_device *dev,
2335 const char *name,
2336 const uint16_t wm[5])
2337 {
2338 int level, max_level = ilk_wm_max_level(dev);
2339
2340 for (level = 0; level <= max_level; level++) {
2341 unsigned int latency = wm[level];
2342
2343 if (latency == 0) {
2344 DRM_ERROR("%s WM%d latency not provided\n",
2345 name, level);
2346 continue;
2347 }
2348
2349 /* WM1+ latency values in 0.5us units */
2350 if (level > 0)
2351 latency *= 5;
2352
2353 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2354 name, level, wm[level],
2355 latency / 10, latency % 10);
2356 }
2357 }
2358
2359 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2360 uint16_t wm[5], uint16_t min)
2361 {
2362 int level, max_level = ilk_wm_max_level(dev_priv->dev);
2363
2364 if (wm[0] >= min)
2365 return false;
2366
2367 wm[0] = max(wm[0], min);
2368 for (level = 1; level <= max_level; level++)
2369 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2370
2371 return true;
2372 }
2373
2374 static void snb_wm_latency_quirk(struct drm_device *dev)
2375 {
2376 struct drm_i915_private *dev_priv = dev->dev_private;
2377 bool changed;
2378
2379 /*
2380 * The BIOS provided WM memory latency values are often
2381 * inadequate for high resolution displays. Adjust them.
2382 */
2383 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2384 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2385 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2386
2387 if (!changed)
2388 return;
2389
2390 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2391 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2392 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2393 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2394 }
2395
2396 static void ilk_setup_wm_latency(struct drm_device *dev)
2397 {
2398 struct drm_i915_private *dev_priv = dev->dev_private;
2399
2400 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2401
2402 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2403 sizeof(dev_priv->wm.pri_latency));
2404 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2405 sizeof(dev_priv->wm.pri_latency));
2406
2407 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2408 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2409
2410 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2411 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2412 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2413
2414 if (IS_GEN6(dev))
2415 snb_wm_latency_quirk(dev);
2416 }
2417
2418 static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
2419 struct ilk_pipe_wm_parameters *p)
2420 {
2421 struct drm_device *dev = crtc->dev;
2422 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2423 enum pipe pipe = intel_crtc->pipe;
2424 struct drm_plane *plane;
2425
2426 if (!intel_crtc_active(crtc))
2427 return;
2428
2429 p->active = true;
2430 p->pipe_htotal = intel_crtc->config.adjusted_mode.crtc_htotal;
2431 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
2432 p->pri.bytes_per_pixel = crtc->primary->fb->bits_per_pixel / 8;
2433 p->cur.bytes_per_pixel = 4;
2434 p->pri.horiz_pixels = intel_crtc->config.pipe_src_w;
2435 p->cur.horiz_pixels = intel_crtc->cursor_width;
2436 /* TODO: for now, assume primary and cursor planes are always enabled. */
2437 p->pri.enabled = true;
2438 p->cur.enabled = true;
2439
2440 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
2441 struct intel_plane *intel_plane = to_intel_plane(plane);
2442
2443 if (intel_plane->pipe == pipe) {
2444 p->spr = intel_plane->wm;
2445 break;
2446 }
2447 }
2448 }
2449
2450 static void ilk_compute_wm_config(struct drm_device *dev,
2451 struct intel_wm_config *config)
2452 {
2453 struct intel_crtc *intel_crtc;
2454
2455 /* Compute the currently _active_ config */
2456 for_each_intel_crtc(dev, intel_crtc) {
2457 const struct intel_pipe_wm *wm = &intel_crtc->wm.active;
2458
2459 if (!wm->pipe_enabled)
2460 continue;
2461
2462 config->sprites_enabled |= wm->sprites_enabled;
2463 config->sprites_scaled |= wm->sprites_scaled;
2464 config->num_pipes_active++;
2465 }
2466 }
2467
2468 /* Compute new watermarks for the pipe */
2469 static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
2470 const struct ilk_pipe_wm_parameters *params,
2471 struct intel_pipe_wm *pipe_wm)
2472 {
2473 struct drm_device *dev = crtc->dev;
2474 const struct drm_i915_private *dev_priv = dev->dev_private;
2475 int level, max_level = ilk_wm_max_level(dev);
2476 /* LP0 watermark maximums depend on this pipe alone */
2477 struct intel_wm_config config = {
2478 .num_pipes_active = 1,
2479 .sprites_enabled = params->spr.enabled,
2480 .sprites_scaled = params->spr.scaled,
2481 };
2482 struct ilk_wm_maximums max;
2483
2484 pipe_wm->pipe_enabled = params->active;
2485 pipe_wm->sprites_enabled = params->spr.enabled;
2486 pipe_wm->sprites_scaled = params->spr.scaled;
2487
2488 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2489 if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled)
2490 max_level = 1;
2491
2492 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2493 if (params->spr.scaled)
2494 max_level = 0;
2495
2496 ilk_compute_wm_level(dev_priv, 0, params, &pipe_wm->wm[0]);
2497
2498 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2499 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
2500
2501 /* LP0 watermarks always use 1/2 DDB partitioning */
2502 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2503
2504 /* At least LP0 must be valid */
2505 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
2506 return false;
2507
2508 ilk_compute_wm_reg_maximums(dev, 1, &max);
2509
2510 for (level = 1; level <= max_level; level++) {
2511 struct intel_wm_level wm = {};
2512
2513 ilk_compute_wm_level(dev_priv, level, params, &wm);
2514
2515 /*
2516 * Disable any watermark level that exceeds the
2517 * register maximums since such watermarks are
2518 * always invalid.
2519 */
2520 if (!ilk_validate_wm_level(level, &max, &wm))
2521 break;
2522
2523 pipe_wm->wm[level] = wm;
2524 }
2525
2526 return true;
2527 }
2528
2529 /*
2530 * Merge the watermarks from all active pipes for a specific level.
2531 */
2532 static void ilk_merge_wm_level(struct drm_device *dev,
2533 int level,
2534 struct intel_wm_level *ret_wm)
2535 {
2536 const struct intel_crtc *intel_crtc;
2537
2538 ret_wm->enable = true;
2539
2540 for_each_intel_crtc(dev, intel_crtc) {
2541 const struct intel_pipe_wm *active = &intel_crtc->wm.active;
2542 const struct intel_wm_level *wm = &active->wm[level];
2543
2544 if (!active->pipe_enabled)
2545 continue;
2546
2547 /*
2548 * The watermark values may have been used in the past,
2549 * so we must maintain them in the registers for some
2550 * time even if the level is now disabled.
2551 */
2552 if (!wm->enable)
2553 ret_wm->enable = false;
2554
2555 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2556 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2557 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2558 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2559 }
2560 }
2561
2562 /*
2563 * Merge all low power watermarks for all active pipes.
2564 */
2565 static void ilk_wm_merge(struct drm_device *dev,
2566 const struct intel_wm_config *config,
2567 const struct ilk_wm_maximums *max,
2568 struct intel_pipe_wm *merged)
2569 {
2570 int level, max_level = ilk_wm_max_level(dev);
2571 int last_enabled_level = max_level;
2572
2573 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2574 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2575 config->num_pipes_active > 1)
2576 return;
2577
2578 /* ILK: FBC WM must be disabled always */
2579 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
2580
2581 /* merge each WM1+ level */
2582 for (level = 1; level <= max_level; level++) {
2583 struct intel_wm_level *wm = &merged->wm[level];
2584
2585 ilk_merge_wm_level(dev, level, wm);
2586
2587 if (level > last_enabled_level)
2588 wm->enable = false;
2589 else if (!ilk_validate_wm_level(level, max, wm))
2590 /* make sure all following levels get disabled */
2591 last_enabled_level = level - 1;
2592
2593 /*
2594 * The spec says it is preferred to disable
2595 * FBC WMs instead of disabling a WM level.
2596 */
2597 if (wm->fbc_val > max->fbc) {
2598 if (wm->enable)
2599 merged->fbc_wm_enabled = false;
2600 wm->fbc_val = 0;
2601 }
2602 }
2603
2604 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2605 /*
2606 * FIXME this is racy. FBC might get enabled later.
2607 * What we should check here is whether FBC can be
2608 * enabled sometime later.
2609 */
2610 if (IS_GEN5(dev) && !merged->fbc_wm_enabled && intel_fbc_enabled(dev)) {
2611 for (level = 2; level <= max_level; level++) {
2612 struct intel_wm_level *wm = &merged->wm[level];
2613
2614 wm->enable = false;
2615 }
2616 }
2617 }
2618
2619 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2620 {
2621 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2622 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2623 }
2624
2625 /* The value we need to program into the WM_LPx latency field */
2626 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2627 {
2628 struct drm_i915_private *dev_priv = dev->dev_private;
2629
2630 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2631 return 2 * level;
2632 else
2633 return dev_priv->wm.pri_latency[level];
2634 }
2635
2636 static void ilk_compute_wm_results(struct drm_device *dev,
2637 const struct intel_pipe_wm *merged,
2638 enum intel_ddb_partitioning partitioning,
2639 struct ilk_wm_values *results)
2640 {
2641 struct intel_crtc *intel_crtc;
2642 int level, wm_lp;
2643
2644 results->enable_fbc_wm = merged->fbc_wm_enabled;
2645 results->partitioning = partitioning;
2646
2647 /* LP1+ register values */
2648 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2649 const struct intel_wm_level *r;
2650
2651 level = ilk_wm_lp_to_level(wm_lp, merged);
2652
2653 r = &merged->wm[level];
2654
2655 /*
2656 * Maintain the watermark values even if the level is
2657 * disabled. Doing otherwise could cause underruns.
2658 */
2659 results->wm_lp[wm_lp - 1] =
2660 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2661 (r->pri_val << WM1_LP_SR_SHIFT) |
2662 r->cur_val;
2663
2664 if (r->enable)
2665 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2666
2667 if (INTEL_INFO(dev)->gen >= 8)
2668 results->wm_lp[wm_lp - 1] |=
2669 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2670 else
2671 results->wm_lp[wm_lp - 1] |=
2672 r->fbc_val << WM1_LP_FBC_SHIFT;
2673
2674 /*
2675 * Always set WM1S_LP_EN when spr_val != 0, even if the
2676 * level is disabled. Doing otherwise could cause underruns.
2677 */
2678 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2679 WARN_ON(wm_lp != 1);
2680 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2681 } else
2682 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2683 }
2684
2685 /* LP0 register values */
2686 for_each_intel_crtc(dev, intel_crtc) {
2687 enum pipe pipe = intel_crtc->pipe;
2688 const struct intel_wm_level *r =
2689 &intel_crtc->wm.active.wm[0];
2690
2691 if (WARN_ON(!r->enable))
2692 continue;
2693
2694 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
2695
2696 results->wm_pipe[pipe] =
2697 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2698 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2699 r->cur_val;
2700 }
2701 }
2702
2703 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2704 * case both are at the same level. Prefer r1 in case they're the same. */
2705 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2706 struct intel_pipe_wm *r1,
2707 struct intel_pipe_wm *r2)
2708 {
2709 int level, max_level = ilk_wm_max_level(dev);
2710 int level1 = 0, level2 = 0;
2711
2712 for (level = 1; level <= max_level; level++) {
2713 if (r1->wm[level].enable)
2714 level1 = level;
2715 if (r2->wm[level].enable)
2716 level2 = level;
2717 }
2718
2719 if (level1 == level2) {
2720 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2721 return r2;
2722 else
2723 return r1;
2724 } else if (level1 > level2) {
2725 return r1;
2726 } else {
2727 return r2;
2728 }
2729 }
2730
2731 /* dirty bits used to track which watermarks need changes */
2732 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2733 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2734 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2735 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2736 #define WM_DIRTY_FBC (1 << 24)
2737 #define WM_DIRTY_DDB (1 << 25)
2738
2739 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
2740 const struct ilk_wm_values *old,
2741 const struct ilk_wm_values *new)
2742 {
2743 unsigned int dirty = 0;
2744 enum pipe pipe;
2745 int wm_lp;
2746
2747 for_each_pipe(dev_priv, pipe) {
2748 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2749 dirty |= WM_DIRTY_LINETIME(pipe);
2750 /* Must disable LP1+ watermarks too */
2751 dirty |= WM_DIRTY_LP_ALL;
2752 }
2753
2754 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2755 dirty |= WM_DIRTY_PIPE(pipe);
2756 /* Must disable LP1+ watermarks too */
2757 dirty |= WM_DIRTY_LP_ALL;
2758 }
2759 }
2760
2761 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2762 dirty |= WM_DIRTY_FBC;
2763 /* Must disable LP1+ watermarks too */
2764 dirty |= WM_DIRTY_LP_ALL;
2765 }
2766
2767 if (old->partitioning != new->partitioning) {
2768 dirty |= WM_DIRTY_DDB;
2769 /* Must disable LP1+ watermarks too */
2770 dirty |= WM_DIRTY_LP_ALL;
2771 }
2772
2773 /* LP1+ watermarks already deemed dirty, no need to continue */
2774 if (dirty & WM_DIRTY_LP_ALL)
2775 return dirty;
2776
2777 /* Find the lowest numbered LP1+ watermark in need of an update... */
2778 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2779 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2780 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2781 break;
2782 }
2783
2784 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2785 for (; wm_lp <= 3; wm_lp++)
2786 dirty |= WM_DIRTY_LP(wm_lp);
2787
2788 return dirty;
2789 }
2790
2791 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2792 unsigned int dirty)
2793 {
2794 struct ilk_wm_values *previous = &dev_priv->wm.hw;
2795 bool changed = false;
2796
2797 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2798 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2799 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2800 changed = true;
2801 }
2802 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2803 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2804 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2805 changed = true;
2806 }
2807 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2808 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2809 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2810 changed = true;
2811 }
2812
2813 /*
2814 * Don't touch WM1S_LP_EN here.
2815 * Doing so could cause underruns.
2816 */
2817
2818 return changed;
2819 }
2820
2821 /*
2822 * The spec says we shouldn't write when we don't need, because every write
2823 * causes WMs to be re-evaluated, expending some power.
2824 */
2825 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2826 struct ilk_wm_values *results)
2827 {
2828 struct drm_device *dev = dev_priv->dev;
2829 struct ilk_wm_values *previous = &dev_priv->wm.hw;
2830 unsigned int dirty;
2831 uint32_t val;
2832
2833 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
2834 if (!dirty)
2835 return;
2836
2837 _ilk_disable_lp_wm(dev_priv, dirty);
2838
2839 if (dirty & WM_DIRTY_PIPE(PIPE_A))
2840 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2841 if (dirty & WM_DIRTY_PIPE(PIPE_B))
2842 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2843 if (dirty & WM_DIRTY_PIPE(PIPE_C))
2844 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2845
2846 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2847 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2848 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2849 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2850 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2851 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2852
2853 if (dirty & WM_DIRTY_DDB) {
2854 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2855 val = I915_READ(WM_MISC);
2856 if (results->partitioning == INTEL_DDB_PART_1_2)
2857 val &= ~WM_MISC_DATA_PARTITION_5_6;
2858 else
2859 val |= WM_MISC_DATA_PARTITION_5_6;
2860 I915_WRITE(WM_MISC, val);
2861 } else {
2862 val = I915_READ(DISP_ARB_CTL2);
2863 if (results->partitioning == INTEL_DDB_PART_1_2)
2864 val &= ~DISP_DATA_PARTITION_5_6;
2865 else
2866 val |= DISP_DATA_PARTITION_5_6;
2867 I915_WRITE(DISP_ARB_CTL2, val);
2868 }
2869 }
2870
2871 if (dirty & WM_DIRTY_FBC) {
2872 val = I915_READ(DISP_ARB_CTL);
2873 if (results->enable_fbc_wm)
2874 val &= ~DISP_FBC_WM_DIS;
2875 else
2876 val |= DISP_FBC_WM_DIS;
2877 I915_WRITE(DISP_ARB_CTL, val);
2878 }
2879
2880 if (dirty & WM_DIRTY_LP(1) &&
2881 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2882 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2883
2884 if (INTEL_INFO(dev)->gen >= 7) {
2885 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2886 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2887 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2888 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2889 }
2890
2891 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2892 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2893 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2894 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2895 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2896 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2897
2898 dev_priv->wm.hw = *results;
2899 }
2900
2901 static bool ilk_disable_lp_wm(struct drm_device *dev)
2902 {
2903 struct drm_i915_private *dev_priv = dev->dev_private;
2904
2905 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2906 }
2907
2908 static void ilk_update_wm(struct drm_crtc *crtc)
2909 {
2910 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2911 struct drm_device *dev = crtc->dev;
2912 struct drm_i915_private *dev_priv = dev->dev_private;
2913 struct ilk_wm_maximums max;
2914 struct ilk_pipe_wm_parameters params = {};
2915 struct ilk_wm_values results = {};
2916 enum intel_ddb_partitioning partitioning;
2917 struct intel_pipe_wm pipe_wm = {};
2918 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
2919 struct intel_wm_config config = {};
2920
2921 ilk_compute_wm_parameters(crtc, &params);
2922
2923 intel_compute_pipe_wm(crtc, &params, &pipe_wm);
2924
2925 if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
2926 return;
2927
2928 intel_crtc->wm.active = pipe_wm;
2929
2930 ilk_compute_wm_config(dev, &config);
2931
2932 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
2933 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
2934
2935 /* 5/6 split only in single pipe config on IVB+ */
2936 if (INTEL_INFO(dev)->gen >= 7 &&
2937 config.num_pipes_active == 1 && config.sprites_enabled) {
2938 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
2939 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
2940
2941 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
2942 } else {
2943 best_lp_wm = &lp_wm_1_2;
2944 }
2945
2946 partitioning = (best_lp_wm == &lp_wm_1_2) ?
2947 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
2948
2949 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
2950
2951 ilk_write_wm_values(dev_priv, &results);
2952 }
2953
2954 static void
2955 ilk_update_sprite_wm(struct drm_plane *plane,
2956 struct drm_crtc *crtc,
2957 uint32_t sprite_width, uint32_t sprite_height,
2958 int pixel_size, bool enabled, bool scaled)
2959 {
2960 struct drm_device *dev = plane->dev;
2961 struct intel_plane *intel_plane = to_intel_plane(plane);
2962
2963 intel_plane->wm.enabled = enabled;
2964 intel_plane->wm.scaled = scaled;
2965 intel_plane->wm.horiz_pixels = sprite_width;
2966 intel_plane->wm.vert_pixels = sprite_width;
2967 intel_plane->wm.bytes_per_pixel = pixel_size;
2968
2969 /*
2970 * IVB workaround: must disable low power watermarks for at least
2971 * one frame before enabling scaling. LP watermarks can be re-enabled
2972 * when scaling is disabled.
2973 *
2974 * WaCxSRDisabledForSpriteScaling:ivb
2975 */
2976 if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev))
2977 intel_wait_for_vblank(dev, intel_plane->pipe);
2978
2979 ilk_update_wm(crtc);
2980 }
2981
2982 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
2983 {
2984 struct drm_device *dev = crtc->dev;
2985 struct drm_i915_private *dev_priv = dev->dev_private;
2986 struct ilk_wm_values *hw = &dev_priv->wm.hw;
2987 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2988 struct intel_pipe_wm *active = &intel_crtc->wm.active;
2989 enum pipe pipe = intel_crtc->pipe;
2990 static const unsigned int wm0_pipe_reg[] = {
2991 [PIPE_A] = WM0_PIPEA_ILK,
2992 [PIPE_B] = WM0_PIPEB_ILK,
2993 [PIPE_C] = WM0_PIPEC_IVB,
2994 };
2995
2996 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
2997 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2998 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
2999
3000 active->pipe_enabled = intel_crtc_active(crtc);
3001
3002 if (active->pipe_enabled) {
3003 u32 tmp = hw->wm_pipe[pipe];
3004
3005 /*
3006 * For active pipes LP0 watermark is marked as
3007 * enabled, and LP1+ watermaks as disabled since
3008 * we can't really reverse compute them in case
3009 * multiple pipes are active.
3010 */
3011 active->wm[0].enable = true;
3012 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3013 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3014 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3015 active->linetime = hw->wm_linetime[pipe];
3016 } else {
3017 int level, max_level = ilk_wm_max_level(dev);
3018
3019 /*
3020 * For inactive pipes, all watermark levels
3021 * should be marked as enabled but zeroed,
3022 * which is what we'd compute them to.
3023 */
3024 for (level = 0; level <= max_level; level++)
3025 active->wm[level].enable = true;
3026 }
3027 }
3028
3029 void ilk_wm_get_hw_state(struct drm_device *dev)
3030 {
3031 struct drm_i915_private *dev_priv = dev->dev_private;
3032 struct ilk_wm_values *hw = &dev_priv->wm.hw;
3033 struct drm_crtc *crtc;
3034
3035 for_each_crtc(dev, crtc)
3036 ilk_pipe_wm_get_hw_state(crtc);
3037
3038 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
3039 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
3040 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
3041
3042 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
3043 if (INTEL_INFO(dev)->gen >= 7) {
3044 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
3045 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
3046 }
3047
3048 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3049 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
3050 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
3051 else if (IS_IVYBRIDGE(dev))
3052 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
3053 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
3054
3055 hw->enable_fbc_wm =
3056 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
3057 }
3058
3059 /**
3060 * intel_update_watermarks - update FIFO watermark values based on current modes
3061 *
3062 * Calculate watermark values for the various WM regs based on current mode
3063 * and plane configuration.
3064 *
3065 * There are several cases to deal with here:
3066 * - normal (i.e. non-self-refresh)
3067 * - self-refresh (SR) mode
3068 * - lines are large relative to FIFO size (buffer can hold up to 2)
3069 * - lines are small relative to FIFO size (buffer can hold more than 2
3070 * lines), so need to account for TLB latency
3071 *
3072 * The normal calculation is:
3073 * watermark = dotclock * bytes per pixel * latency
3074 * where latency is platform & configuration dependent (we assume pessimal
3075 * values here).
3076 *
3077 * The SR calculation is:
3078 * watermark = (trunc(latency/line time)+1) * surface width *
3079 * bytes per pixel
3080 * where
3081 * line time = htotal / dotclock
3082 * surface width = hdisplay for normal plane and 64 for cursor
3083 * and latency is assumed to be high, as above.
3084 *
3085 * The final value programmed to the register should always be rounded up,
3086 * and include an extra 2 entries to account for clock crossings.
3087 *
3088 * We don't use the sprite, so we can ignore that. And on Crestline we have
3089 * to set the non-SR watermarks to 8.
3090 */
3091 void intel_update_watermarks(struct drm_crtc *crtc)
3092 {
3093 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
3094
3095 if (dev_priv->display.update_wm)
3096 dev_priv->display.update_wm(crtc);
3097 }
3098
3099 void intel_update_sprite_watermarks(struct drm_plane *plane,
3100 struct drm_crtc *crtc,
3101 uint32_t sprite_width,
3102 uint32_t sprite_height,
3103 int pixel_size,
3104 bool enabled, bool scaled)
3105 {
3106 struct drm_i915_private *dev_priv = plane->dev->dev_private;
3107
3108 if (dev_priv->display.update_sprite_wm)
3109 dev_priv->display.update_sprite_wm(plane, crtc,
3110 sprite_width, sprite_height,
3111 pixel_size, enabled, scaled);
3112 }
3113
3114 static struct drm_i915_gem_object *
3115 intel_alloc_context_page(struct drm_device *dev)
3116 {
3117 struct drm_i915_gem_object *ctx;
3118 int ret;
3119
3120 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3121
3122 ctx = i915_gem_alloc_object(dev, 4096);
3123 if (!ctx) {
3124 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
3125 return NULL;
3126 }
3127
3128 ret = i915_gem_obj_ggtt_pin(ctx, 4096, 0);
3129 if (ret) {
3130 DRM_ERROR("failed to pin power context: %d\n", ret);
3131 goto err_unref;
3132 }
3133
3134 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
3135 if (ret) {
3136 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
3137 goto err_unpin;
3138 }
3139
3140 return ctx;
3141
3142 err_unpin:
3143 i915_gem_object_ggtt_unpin(ctx);
3144 err_unref:
3145 drm_gem_object_unreference(&ctx->base);
3146 return NULL;
3147 }
3148
3149 /**
3150 * Lock protecting IPS related data structures
3151 */
3152 DEFINE_SPINLOCK(mchdev_lock);
3153
3154 /* Global for IPS driver to get at the current i915 device. Protected by
3155 * mchdev_lock. */
3156 static struct drm_i915_private *i915_mch_dev;
3157
3158 bool ironlake_set_drps(struct drm_device *dev, u8 val)
3159 {
3160 struct drm_i915_private *dev_priv = dev->dev_private;
3161 u16 rgvswctl;
3162
3163 assert_spin_locked(&mchdev_lock);
3164
3165 rgvswctl = I915_READ16(MEMSWCTL);
3166 if (rgvswctl & MEMCTL_CMD_STS) {
3167 DRM_DEBUG("gpu busy, RCS change rejected\n");
3168 return false; /* still busy with another command */
3169 }
3170
3171 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
3172 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
3173 I915_WRITE16(MEMSWCTL, rgvswctl);
3174 POSTING_READ16(MEMSWCTL);
3175
3176 rgvswctl |= MEMCTL_CMD_STS;
3177 I915_WRITE16(MEMSWCTL, rgvswctl);
3178
3179 return true;
3180 }
3181
3182 static void ironlake_enable_drps(struct drm_device *dev)
3183 {
3184 struct drm_i915_private *dev_priv = dev->dev_private;
3185 u32 rgvmodectl = I915_READ(MEMMODECTL);
3186 u8 fmax, fmin, fstart, vstart;
3187
3188 spin_lock_irq(&mchdev_lock);
3189
3190 /* Enable temp reporting */
3191 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
3192 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
3193
3194 /* 100ms RC evaluation intervals */
3195 I915_WRITE(RCUPEI, 100000);
3196 I915_WRITE(RCDNEI, 100000);
3197
3198 /* Set max/min thresholds to 90ms and 80ms respectively */
3199 I915_WRITE(RCBMAXAVG, 90000);
3200 I915_WRITE(RCBMINAVG, 80000);
3201
3202 I915_WRITE(MEMIHYST, 1);
3203
3204 /* Set up min, max, and cur for interrupt handling */
3205 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
3206 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
3207 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
3208 MEMMODE_FSTART_SHIFT;
3209
3210 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
3211 PXVFREQ_PX_SHIFT;
3212
3213 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
3214 dev_priv->ips.fstart = fstart;
3215
3216 dev_priv->ips.max_delay = fstart;
3217 dev_priv->ips.min_delay = fmin;
3218 dev_priv->ips.cur_delay = fstart;
3219
3220 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
3221 fmax, fmin, fstart);
3222
3223 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
3224
3225 /*
3226 * Interrupts will be enabled in ironlake_irq_postinstall
3227 */
3228
3229 I915_WRITE(VIDSTART, vstart);
3230 POSTING_READ(VIDSTART);
3231
3232 rgvmodectl |= MEMMODE_SWMODE_EN;
3233 I915_WRITE(MEMMODECTL, rgvmodectl);
3234
3235 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
3236 DRM_ERROR("stuck trying to change perf mode\n");
3237 mdelay(1);
3238
3239 ironlake_set_drps(dev, fstart);
3240
3241 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
3242 I915_READ(0x112e0);
3243 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
3244 dev_priv->ips.last_count2 = I915_READ(0x112f4);
3245 dev_priv->ips.last_time2 = ktime_get_raw_ns();
3246
3247 spin_unlock_irq(&mchdev_lock);
3248 }
3249
3250 static void ironlake_disable_drps(struct drm_device *dev)
3251 {
3252 struct drm_i915_private *dev_priv = dev->dev_private;
3253 u16 rgvswctl;
3254
3255 spin_lock_irq(&mchdev_lock);
3256
3257 rgvswctl = I915_READ16(MEMSWCTL);
3258
3259 /* Ack interrupts, disable EFC interrupt */
3260 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
3261 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
3262 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
3263 I915_WRITE(DEIIR, DE_PCU_EVENT);
3264 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
3265
3266 /* Go back to the starting frequency */
3267 ironlake_set_drps(dev, dev_priv->ips.fstart);
3268 mdelay(1);
3269 rgvswctl |= MEMCTL_CMD_STS;
3270 I915_WRITE(MEMSWCTL, rgvswctl);
3271 mdelay(1);
3272
3273 spin_unlock_irq(&mchdev_lock);
3274 }
3275
3276 /* There's a funny hw issue where the hw returns all 0 when reading from
3277 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3278 * ourselves, instead of doing a rmw cycle (which might result in us clearing
3279 * all limits and the gpu stuck at whatever frequency it is at atm).
3280 */
3281 static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)
3282 {
3283 u32 limits;
3284
3285 /* Only set the down limit when we've reached the lowest level to avoid
3286 * getting more interrupts, otherwise leave this clear. This prevents a
3287 * race in the hw when coming out of rc6: There's a tiny window where
3288 * the hw runs at the minimal clock before selecting the desired
3289 * frequency, if the down threshold expires in that window we will not
3290 * receive a down interrupt. */
3291 limits = dev_priv->rps.max_freq_softlimit << 24;
3292 if (val <= dev_priv->rps.min_freq_softlimit)
3293 limits |= dev_priv->rps.min_freq_softlimit << 16;
3294
3295 return limits;
3296 }
3297
3298 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
3299 {
3300 int new_power;
3301
3302 new_power = dev_priv->rps.power;
3303 switch (dev_priv->rps.power) {
3304 case LOW_POWER:
3305 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
3306 new_power = BETWEEN;
3307 break;
3308
3309 case BETWEEN:
3310 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
3311 new_power = LOW_POWER;
3312 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
3313 new_power = HIGH_POWER;
3314 break;
3315
3316 case HIGH_POWER:
3317 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
3318 new_power = BETWEEN;
3319 break;
3320 }
3321 /* Max/min bins are special */
3322 if (val == dev_priv->rps.min_freq_softlimit)
3323 new_power = LOW_POWER;
3324 if (val == dev_priv->rps.max_freq_softlimit)
3325 new_power = HIGH_POWER;
3326 if (new_power == dev_priv->rps.power)
3327 return;
3328
3329 /* Note the units here are not exactly 1us, but 1280ns. */
3330 switch (new_power) {
3331 case LOW_POWER:
3332 /* Upclock if more than 95% busy over 16ms */
3333 I915_WRITE(GEN6_RP_UP_EI, 12500);
3334 I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800);
3335
3336 /* Downclock if less than 85% busy over 32ms */
3337 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3338 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250);
3339
3340 I915_WRITE(GEN6_RP_CONTROL,
3341 GEN6_RP_MEDIA_TURBO |
3342 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3343 GEN6_RP_MEDIA_IS_GFX |
3344 GEN6_RP_ENABLE |
3345 GEN6_RP_UP_BUSY_AVG |
3346 GEN6_RP_DOWN_IDLE_AVG);
3347 break;
3348
3349 case BETWEEN:
3350 /* Upclock if more than 90% busy over 13ms */
3351 I915_WRITE(GEN6_RP_UP_EI, 10250);
3352 I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225);
3353
3354 /* Downclock if less than 75% busy over 32ms */
3355 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3356 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750);
3357
3358 I915_WRITE(GEN6_RP_CONTROL,
3359 GEN6_RP_MEDIA_TURBO |
3360 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3361 GEN6_RP_MEDIA_IS_GFX |
3362 GEN6_RP_ENABLE |
3363 GEN6_RP_UP_BUSY_AVG |
3364 GEN6_RP_DOWN_IDLE_AVG);
3365 break;
3366
3367 case HIGH_POWER:
3368 /* Upclock if more than 85% busy over 10ms */
3369 I915_WRITE(GEN6_RP_UP_EI, 8000);
3370 I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800);
3371
3372 /* Downclock if less than 60% busy over 32ms */
3373 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3374 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000);
3375
3376 I915_WRITE(GEN6_RP_CONTROL,
3377 GEN6_RP_MEDIA_TURBO |
3378 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3379 GEN6_RP_MEDIA_IS_GFX |
3380 GEN6_RP_ENABLE |
3381 GEN6_RP_UP_BUSY_AVG |
3382 GEN6_RP_DOWN_IDLE_AVG);
3383 break;
3384 }
3385
3386 dev_priv->rps.power = new_power;
3387 dev_priv->rps.last_adj = 0;
3388 }
3389
3390 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
3391 {
3392 u32 mask = 0;
3393
3394 if (val > dev_priv->rps.min_freq_softlimit)
3395 mask |= GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
3396 if (val < dev_priv->rps.max_freq_softlimit)
3397 mask |= GEN6_PM_RP_UP_THRESHOLD;
3398
3399 mask |= dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED);
3400 mask &= dev_priv->pm_rps_events;
3401
3402 /* IVB and SNB hard hangs on looping batchbuffer
3403 * if GEN6_PM_UP_EI_EXPIRED is masked.
3404 */
3405 if (INTEL_INFO(dev_priv->dev)->gen <= 7 && !IS_HASWELL(dev_priv->dev))
3406 mask |= GEN6_PM_RP_UP_EI_EXPIRED;
3407
3408 if (IS_GEN8(dev_priv->dev))
3409 mask |= GEN8_PMINTR_REDIRECT_TO_NON_DISP;
3410
3411 return ~mask;
3412 }
3413
3414 /* gen6_set_rps is called to update the frequency request, but should also be
3415 * called when the range (min_delay and max_delay) is modified so that we can
3416 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
3417 void gen6_set_rps(struct drm_device *dev, u8 val)
3418 {
3419 struct drm_i915_private *dev_priv = dev->dev_private;
3420
3421 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3422 WARN_ON(val > dev_priv->rps.max_freq_softlimit);
3423 WARN_ON(val < dev_priv->rps.min_freq_softlimit);
3424
3425 /* min/max delay may still have been modified so be sure to
3426 * write the limits value.
3427 */
3428 if (val != dev_priv->rps.cur_freq) {
3429 gen6_set_rps_thresholds(dev_priv, val);
3430
3431 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3432 I915_WRITE(GEN6_RPNSWREQ,
3433 HSW_FREQUENCY(val));
3434 else
3435 I915_WRITE(GEN6_RPNSWREQ,
3436 GEN6_FREQUENCY(val) |
3437 GEN6_OFFSET(0) |
3438 GEN6_AGGRESSIVE_TURBO);
3439 }
3440
3441 /* Make sure we continue to get interrupts
3442 * until we hit the minimum or maximum frequencies.
3443 */
3444 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, gen6_rps_limits(dev_priv, val));
3445 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
3446
3447 POSTING_READ(GEN6_RPNSWREQ);
3448
3449 dev_priv->rps.cur_freq = val;
3450 trace_intel_gpu_freq_change(val * 50);
3451 }
3452
3453 /* vlv_set_rps_idle: Set the frequency to Rpn if Gfx clocks are down
3454 *
3455 * * If Gfx is Idle, then
3456 * 1. Mask Turbo interrupts
3457 * 2. Bring up Gfx clock
3458 * 3. Change the freq to Rpn and wait till P-Unit updates freq
3459 * 4. Clear the Force GFX CLK ON bit so that Gfx can down
3460 * 5. Unmask Turbo interrupts
3461 */
3462 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
3463 {
3464 struct drm_device *dev = dev_priv->dev;
3465
3466 /* Latest VLV doesn't need to force the gfx clock */
3467 if (dev->pdev->revision >= 0xd) {
3468 valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3469 return;
3470 }
3471
3472 /*
3473 * When we are idle. Drop to min voltage state.
3474 */
3475
3476 if (dev_priv->rps.cur_freq <= dev_priv->rps.min_freq_softlimit)
3477 return;
3478
3479 /* Mask turbo interrupt so that they will not come in between */
3480 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3481
3482 vlv_force_gfx_clock(dev_priv, true);
3483
3484 dev_priv->rps.cur_freq = dev_priv->rps.min_freq_softlimit;
3485
3486 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ,
3487 dev_priv->rps.min_freq_softlimit);
3488
3489 if (wait_for(((vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS))
3490 & GENFREQSTATUS) == 0, 5))
3491 DRM_ERROR("timed out waiting for Punit\n");
3492
3493 vlv_force_gfx_clock(dev_priv, false);
3494
3495 I915_WRITE(GEN6_PMINTRMSK,
3496 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
3497 }
3498
3499 void gen6_rps_idle(struct drm_i915_private *dev_priv)
3500 {
3501 struct drm_device *dev = dev_priv->dev;
3502
3503 mutex_lock(&dev_priv->rps.hw_lock);
3504 if (dev_priv->rps.enabled) {
3505 if (IS_CHERRYVIEW(dev))
3506 valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3507 else if (IS_VALLEYVIEW(dev))
3508 vlv_set_rps_idle(dev_priv);
3509 else
3510 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3511 dev_priv->rps.last_adj = 0;
3512 }
3513 mutex_unlock(&dev_priv->rps.hw_lock);
3514 }
3515
3516 void gen6_rps_boost(struct drm_i915_private *dev_priv)
3517 {
3518 struct drm_device *dev = dev_priv->dev;
3519
3520 mutex_lock(&dev_priv->rps.hw_lock);
3521 if (dev_priv->rps.enabled) {
3522 if (IS_VALLEYVIEW(dev))
3523 valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
3524 else
3525 gen6_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
3526 dev_priv->rps.last_adj = 0;
3527 }
3528 mutex_unlock(&dev_priv->rps.hw_lock);
3529 }
3530
3531 void valleyview_set_rps(struct drm_device *dev, u8 val)
3532 {
3533 struct drm_i915_private *dev_priv = dev->dev_private;
3534
3535 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3536 WARN_ON(val > dev_priv->rps.max_freq_softlimit);
3537 WARN_ON(val < dev_priv->rps.min_freq_softlimit);
3538
3539 if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1),
3540 "Odd GPU freq value\n"))
3541 val &= ~1;
3542
3543 if (val != dev_priv->rps.cur_freq) {
3544 DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
3545 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
3546 dev_priv->rps.cur_freq,
3547 vlv_gpu_freq(dev_priv, val), val);
3548
3549 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
3550 }
3551
3552 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
3553
3554 dev_priv->rps.cur_freq = val;
3555 trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val));
3556 }
3557
3558 static void gen8_disable_rps_interrupts(struct drm_device *dev)
3559 {
3560 struct drm_i915_private *dev_priv = dev->dev_private;
3561
3562 I915_WRITE(GEN6_PMINTRMSK, ~GEN8_PMINTR_REDIRECT_TO_NON_DISP);
3563 I915_WRITE(GEN8_GT_IER(2), I915_READ(GEN8_GT_IER(2)) &
3564 ~dev_priv->pm_rps_events);
3565 /* Complete PM interrupt masking here doesn't race with the rps work
3566 * item again unmasking PM interrupts because that is using a different
3567 * register (GEN8_GT_IMR(2)) to mask PM interrupts. The only risk is in
3568 * leaving stale bits in GEN8_GT_IIR(2) and GEN8_GT_IMR(2) which
3569 * gen8_enable_rps will clean up. */
3570
3571 spin_lock_irq(&dev_priv->irq_lock);
3572 dev_priv->rps.pm_iir = 0;
3573 spin_unlock_irq(&dev_priv->irq_lock);
3574
3575 I915_WRITE(GEN8_GT_IIR(2), dev_priv->pm_rps_events);
3576 }
3577
3578 static void gen6_disable_rps_interrupts(struct drm_device *dev)
3579 {
3580 struct drm_i915_private *dev_priv = dev->dev_private;
3581
3582 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3583 I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) &
3584 ~dev_priv->pm_rps_events);
3585 /* Complete PM interrupt masking here doesn't race with the rps work
3586 * item again unmasking PM interrupts because that is using a different
3587 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3588 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3589
3590 spin_lock_irq(&dev_priv->irq_lock);
3591 dev_priv->rps.pm_iir = 0;
3592 spin_unlock_irq(&dev_priv->irq_lock);
3593
3594 I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events);
3595 }
3596
3597 static void gen6_disable_rps(struct drm_device *dev)
3598 {
3599 struct drm_i915_private *dev_priv = dev->dev_private;
3600
3601 I915_WRITE(GEN6_RC_CONTROL, 0);
3602 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
3603
3604 if (IS_BROADWELL(dev))
3605 gen8_disable_rps_interrupts(dev);
3606 else
3607 gen6_disable_rps_interrupts(dev);
3608 }
3609
3610 static void cherryview_disable_rps(struct drm_device *dev)
3611 {
3612 struct drm_i915_private *dev_priv = dev->dev_private;
3613
3614 I915_WRITE(GEN6_RC_CONTROL, 0);
3615
3616 gen8_disable_rps_interrupts(dev);
3617 }
3618
3619 static void valleyview_disable_rps(struct drm_device *dev)
3620 {
3621 struct drm_i915_private *dev_priv = dev->dev_private;
3622
3623 /* we're doing forcewake before Disabling RC6,
3624 * This what the BIOS expects when going into suspend */
3625 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3626
3627 I915_WRITE(GEN6_RC_CONTROL, 0);
3628
3629 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3630
3631 gen6_disable_rps_interrupts(dev);
3632 }
3633
3634 static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
3635 {
3636 if (IS_VALLEYVIEW(dev)) {
3637 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
3638 mode = GEN6_RC_CTL_RC6_ENABLE;
3639 else
3640 mode = 0;
3641 }
3642 if (HAS_RC6p(dev))
3643 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
3644 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3645 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3646 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
3647
3648 else
3649 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
3650 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off");
3651 }
3652
3653 static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
3654 {
3655 /* No RC6 before Ironlake */
3656 if (INTEL_INFO(dev)->gen < 5)
3657 return 0;
3658
3659 /* RC6 is only on Ironlake mobile not on desktop */
3660 if (INTEL_INFO(dev)->gen == 5 && !IS_IRONLAKE_M(dev))
3661 return 0;
3662
3663 /* Respect the kernel parameter if it is set */
3664 if (enable_rc6 >= 0) {
3665 int mask;
3666
3667 if (HAS_RC6p(dev))
3668 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
3669 INTEL_RC6pp_ENABLE;
3670 else
3671 mask = INTEL_RC6_ENABLE;
3672
3673 if ((enable_rc6 & mask) != enable_rc6)
3674 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
3675 enable_rc6 & mask, enable_rc6, mask);
3676
3677 return enable_rc6 & mask;
3678 }
3679
3680 /* Disable RC6 on Ironlake */
3681 if (INTEL_INFO(dev)->gen == 5)
3682 return 0;
3683
3684 if (IS_IVYBRIDGE(dev))
3685 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
3686
3687 return INTEL_RC6_ENABLE;
3688 }
3689
3690 int intel_enable_rc6(const struct drm_device *dev)
3691 {
3692 return i915.enable_rc6;
3693 }
3694
3695 static void gen8_enable_rps_interrupts(struct drm_device *dev)
3696 {
3697 struct drm_i915_private *dev_priv = dev->dev_private;
3698
3699 spin_lock_irq(&dev_priv->irq_lock);
3700 WARN_ON(dev_priv->rps.pm_iir);
3701 gen8_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
3702 I915_WRITE(GEN8_GT_IIR(2), dev_priv->pm_rps_events);
3703 spin_unlock_irq(&dev_priv->irq_lock);
3704 }
3705
3706 static void gen6_enable_rps_interrupts(struct drm_device *dev)
3707 {
3708 struct drm_i915_private *dev_priv = dev->dev_private;
3709
3710 spin_lock_irq(&dev_priv->irq_lock);
3711 WARN_ON(dev_priv->rps.pm_iir);
3712 gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
3713 I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events);
3714 spin_unlock_irq(&dev_priv->irq_lock);
3715 }
3716
3717 static void parse_rp_state_cap(struct drm_i915_private *dev_priv, u32 rp_state_cap)
3718 {
3719 /* All of these values are in units of 50MHz */
3720 dev_priv->rps.cur_freq = 0;
3721 /* static values from HW: RP0 < RPe < RP1 < RPn (min_freq) */
3722 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
3723 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
3724 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
3725 /* XXX: only BYT has a special efficient freq */
3726 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
3727 /* hw_max = RP0 until we check for overclocking */
3728 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
3729
3730 /* Preserve min/max settings in case of re-init */
3731 if (dev_priv->rps.max_freq_softlimit == 0)
3732 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
3733
3734 if (dev_priv->rps.min_freq_softlimit == 0)
3735 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
3736 }
3737
3738 static void gen8_enable_rps(struct drm_device *dev)
3739 {
3740 struct drm_i915_private *dev_priv = dev->dev_private;
3741 struct intel_engine_cs *ring;
3742 uint32_t rc6_mask = 0, rp_state_cap;
3743 int unused;
3744
3745 /* 1a: Software RC state - RC0 */
3746 I915_WRITE(GEN6_RC_STATE, 0);
3747
3748 /* 1c & 1d: Get forcewake during program sequence. Although the driver
3749 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
3750 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3751
3752 /* 2a: Disable RC states. */
3753 I915_WRITE(GEN6_RC_CONTROL, 0);
3754
3755 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3756 parse_rp_state_cap(dev_priv, rp_state_cap);
3757
3758 /* 2b: Program RC6 thresholds.*/
3759 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
3760 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
3761 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
3762 for_each_ring(ring, dev_priv, unused)
3763 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3764 I915_WRITE(GEN6_RC_SLEEP, 0);
3765 if (IS_BROADWELL(dev))
3766 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
3767 else
3768 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
3769
3770 /* 3: Enable RC6 */
3771 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
3772 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
3773 intel_print_rc6_info(dev, rc6_mask);
3774 if (IS_BROADWELL(dev))
3775 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
3776 GEN7_RC_CTL_TO_MODE |
3777 rc6_mask);
3778 else
3779 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
3780 GEN6_RC_CTL_EI_MODE(1) |
3781 rc6_mask);
3782
3783 /* 4 Program defaults and thresholds for RPS*/
3784 I915_WRITE(GEN6_RPNSWREQ,
3785 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
3786 I915_WRITE(GEN6_RC_VIDEO_FREQ,
3787 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
3788 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
3789 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
3790
3791 /* Docs recommend 900MHz, and 300 MHz respectively */
3792 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
3793 dev_priv->rps.max_freq_softlimit << 24 |
3794 dev_priv->rps.min_freq_softlimit << 16);
3795
3796 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
3797 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
3798 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
3799 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
3800
3801 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3802
3803 /* 5: Enable RPS */
3804 I915_WRITE(GEN6_RP_CONTROL,
3805 GEN6_RP_MEDIA_TURBO |
3806 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3807 GEN6_RP_MEDIA_IS_GFX |
3808 GEN6_RP_ENABLE |
3809 GEN6_RP_UP_BUSY_AVG |
3810 GEN6_RP_DOWN_IDLE_AVG);
3811
3812 /* 6: Ring frequency + overclocking (our driver does this later */
3813
3814 gen6_set_rps(dev, (I915_READ(GEN6_GT_PERF_STATUS) & 0xff00) >> 8);
3815
3816 gen8_enable_rps_interrupts(dev);
3817
3818 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3819 }
3820
3821 static void gen6_enable_rps(struct drm_device *dev)
3822 {
3823 struct drm_i915_private *dev_priv = dev->dev_private;
3824 struct intel_engine_cs *ring;
3825 u32 rp_state_cap;
3826 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
3827 u32 gtfifodbg;
3828 int rc6_mode;
3829 int i, ret;
3830
3831 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3832
3833 /* Here begins a magic sequence of register writes to enable
3834 * auto-downclocking.
3835 *
3836 * Perhaps there might be some value in exposing these to
3837 * userspace...
3838 */
3839 I915_WRITE(GEN6_RC_STATE, 0);
3840
3841 /* Clear the DBG now so we don't confuse earlier errors */
3842 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3843 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3844 I915_WRITE(GTFIFODBG, gtfifodbg);
3845 }
3846
3847 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3848
3849 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3850
3851 parse_rp_state_cap(dev_priv, rp_state_cap);
3852
3853 /* disable the counters and set deterministic thresholds */
3854 I915_WRITE(GEN6_RC_CONTROL, 0);
3855
3856 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
3857 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
3858 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
3859 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3860 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3861
3862 for_each_ring(ring, dev_priv, i)
3863 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3864
3865 I915_WRITE(GEN6_RC_SLEEP, 0);
3866 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
3867 if (IS_IVYBRIDGE(dev))
3868 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
3869 else
3870 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
3871 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
3872 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
3873
3874 /* Check if we are enabling RC6 */
3875 rc6_mode = intel_enable_rc6(dev_priv->dev);
3876 if (rc6_mode & INTEL_RC6_ENABLE)
3877 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
3878
3879 /* We don't use those on Haswell */
3880 if (!IS_HASWELL(dev)) {
3881 if (rc6_mode & INTEL_RC6p_ENABLE)
3882 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
3883
3884 if (rc6_mode & INTEL_RC6pp_ENABLE)
3885 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
3886 }
3887
3888 intel_print_rc6_info(dev, rc6_mask);
3889
3890 I915_WRITE(GEN6_RC_CONTROL,
3891 rc6_mask |
3892 GEN6_RC_CTL_EI_MODE(1) |
3893 GEN6_RC_CTL_HW_ENABLE);
3894
3895 /* Power down if completely idle for over 50ms */
3896 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
3897 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3898
3899 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
3900 if (ret)
3901 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
3902
3903 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
3904 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
3905 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
3906 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
3907 (pcu_mbox & 0xff) * 50);
3908 dev_priv->rps.max_freq = pcu_mbox & 0xff;
3909 }
3910
3911 dev_priv->rps.power = HIGH_POWER; /* force a reset */
3912 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3913
3914 gen6_enable_rps_interrupts(dev);
3915
3916 rc6vids = 0;
3917 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
3918 if (IS_GEN6(dev) && ret) {
3919 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
3920 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
3921 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
3922 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
3923 rc6vids &= 0xffff00;
3924 rc6vids |= GEN6_ENCODE_RC6_VID(450);
3925 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
3926 if (ret)
3927 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
3928 }
3929
3930 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3931 }
3932
3933 static void __gen6_update_ring_freq(struct drm_device *dev)
3934 {
3935 struct drm_i915_private *dev_priv = dev->dev_private;
3936 int min_freq = 15;
3937 unsigned int gpu_freq;
3938 unsigned int max_ia_freq, min_ring_freq;
3939 int scaling_factor = 180;
3940 struct cpufreq_policy *policy;
3941
3942 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3943
3944 policy = cpufreq_cpu_get(0);
3945 if (policy) {
3946 max_ia_freq = policy->cpuinfo.max_freq;
3947 cpufreq_cpu_put(policy);
3948 } else {
3949 /*
3950 * Default to measured freq if none found, PCU will ensure we
3951 * don't go over
3952 */
3953 max_ia_freq = tsc_khz;
3954 }
3955
3956 /* Convert from kHz to MHz */
3957 max_ia_freq /= 1000;
3958
3959 min_ring_freq = I915_READ(DCLK) & 0xf;
3960 /* convert DDR frequency from units of 266.6MHz to bandwidth */
3961 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3962
3963 /*
3964 * For each potential GPU frequency, load a ring frequency we'd like
3965 * to use for memory access. We do this by specifying the IA frequency
3966 * the PCU should use as a reference to determine the ring frequency.
3967 */
3968 for (gpu_freq = dev_priv->rps.max_freq_softlimit; gpu_freq >= dev_priv->rps.min_freq_softlimit;
3969 gpu_freq--) {
3970 int diff = dev_priv->rps.max_freq_softlimit - gpu_freq;
3971 unsigned int ia_freq = 0, ring_freq = 0;
3972
3973 if (INTEL_INFO(dev)->gen >= 8) {
3974 /* max(2 * GT, DDR). NB: GT is 50MHz units */
3975 ring_freq = max(min_ring_freq, gpu_freq);
3976 } else if (IS_HASWELL(dev)) {
3977 ring_freq = mult_frac(gpu_freq, 5, 4);
3978 ring_freq = max(min_ring_freq, ring_freq);
3979 /* leave ia_freq as the default, chosen by cpufreq */
3980 } else {
3981 /* On older processors, there is no separate ring
3982 * clock domain, so in order to boost the bandwidth
3983 * of the ring, we need to upclock the CPU (ia_freq).
3984 *
3985 * For GPU frequencies less than 750MHz,
3986 * just use the lowest ring freq.
3987 */
3988 if (gpu_freq < min_freq)
3989 ia_freq = 800;
3990 else
3991 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
3992 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
3993 }
3994
3995 sandybridge_pcode_write(dev_priv,
3996 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3997 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
3998 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
3999 gpu_freq);
4000 }
4001 }
4002
4003 void gen6_update_ring_freq(struct drm_device *dev)
4004 {
4005 struct drm_i915_private *dev_priv = dev->dev_private;
4006
4007 if (INTEL_INFO(dev)->gen < 6 || IS_VALLEYVIEW(dev))
4008 return;
4009
4010 mutex_lock(&dev_priv->rps.hw_lock);
4011 __gen6_update_ring_freq(dev);
4012 mutex_unlock(&dev_priv->rps.hw_lock);
4013 }
4014
4015 static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
4016 {
4017 u32 val, rp0;
4018
4019 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
4020 rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & PUNIT_GPU_STATUS_MAX_FREQ_MASK;
4021
4022 return rp0;
4023 }
4024
4025 static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
4026 {
4027 u32 val, rpe;
4028
4029 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
4030 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
4031
4032 return rpe;
4033 }
4034
4035 static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
4036 {
4037 u32 val, rp1;
4038
4039 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4040 rp1 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & PUNIT_GPU_STATUS_MAX_FREQ_MASK;
4041
4042 return rp1;
4043 }
4044
4045 static int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
4046 {
4047 u32 val, rpn;
4048
4049 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
4050 rpn = (val >> PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT) & PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK;
4051 return rpn;
4052 }
4053
4054 static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
4055 {
4056 u32 val, rp1;
4057
4058 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
4059
4060 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
4061
4062 return rp1;
4063 }
4064
4065 static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
4066 {
4067 u32 val, rp0;
4068
4069 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
4070
4071 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
4072 /* Clamp to max */
4073 rp0 = min_t(u32, rp0, 0xea);
4074
4075 return rp0;
4076 }
4077
4078 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
4079 {
4080 u32 val, rpe;
4081
4082 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
4083 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
4084 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
4085 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
4086
4087 return rpe;
4088 }
4089
4090 static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
4091 {
4092 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
4093 }
4094
4095 /* Check that the pctx buffer wasn't move under us. */
4096 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
4097 {
4098 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
4099
4100 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
4101 dev_priv->vlv_pctx->stolen->start);
4102 }
4103
4104
4105 /* Check that the pcbr address is not empty. */
4106 static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
4107 {
4108 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
4109
4110 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
4111 }
4112
4113 static void cherryview_setup_pctx(struct drm_device *dev)
4114 {
4115 struct drm_i915_private *dev_priv = dev->dev_private;
4116 unsigned long pctx_paddr, paddr;
4117 struct i915_gtt *gtt = &dev_priv->gtt;
4118 u32 pcbr;
4119 int pctx_size = 32*1024;
4120
4121 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4122
4123 pcbr = I915_READ(VLV_PCBR);
4124 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
4125 paddr = (dev_priv->mm.stolen_base +
4126 (gtt->stolen_size - pctx_size));
4127
4128 pctx_paddr = (paddr & (~4095));
4129 I915_WRITE(VLV_PCBR, pctx_paddr);
4130 }
4131 }
4132
4133 static void valleyview_setup_pctx(struct drm_device *dev)
4134 {
4135 struct drm_i915_private *dev_priv = dev->dev_private;
4136 struct drm_i915_gem_object *pctx;
4137 unsigned long pctx_paddr;
4138 u32 pcbr;
4139 int pctx_size = 24*1024;
4140
4141 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4142
4143 pcbr = I915_READ(VLV_PCBR);
4144 if (pcbr) {
4145 /* BIOS set it up already, grab the pre-alloc'd space */
4146 int pcbr_offset;
4147
4148 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
4149 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
4150 pcbr_offset,
4151 I915_GTT_OFFSET_NONE,
4152 pctx_size);
4153 goto out;
4154 }
4155
4156 /*
4157 * From the Gunit register HAS:
4158 * The Gfx driver is expected to program this register and ensure
4159 * proper allocation within Gfx stolen memory. For example, this
4160 * register should be programmed such than the PCBR range does not
4161 * overlap with other ranges, such as the frame buffer, protected
4162 * memory, or any other relevant ranges.
4163 */
4164 pctx = i915_gem_object_create_stolen(dev, pctx_size);
4165 if (!pctx) {
4166 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
4167 return;
4168 }
4169
4170 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
4171 I915_WRITE(VLV_PCBR, pctx_paddr);
4172
4173 out:
4174 dev_priv->vlv_pctx = pctx;
4175 }
4176
4177 static void valleyview_cleanup_pctx(struct drm_device *dev)
4178 {
4179 struct drm_i915_private *dev_priv = dev->dev_private;
4180
4181 if (WARN_ON(!dev_priv->vlv_pctx))
4182 return;
4183
4184 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
4185 dev_priv->vlv_pctx = NULL;
4186 }
4187
4188 static void valleyview_init_gt_powersave(struct drm_device *dev)
4189 {
4190 struct drm_i915_private *dev_priv = dev->dev_private;
4191 u32 val;
4192
4193 valleyview_setup_pctx(dev);
4194
4195 mutex_lock(&dev_priv->rps.hw_lock);
4196
4197 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4198 switch ((val >> 6) & 3) {
4199 case 0:
4200 case 1:
4201 dev_priv->mem_freq = 800;
4202 break;
4203 case 2:
4204 dev_priv->mem_freq = 1066;
4205 break;
4206 case 3:
4207 dev_priv->mem_freq = 1333;
4208 break;
4209 }
4210 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
4211
4212 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
4213 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
4214 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
4215 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4216 dev_priv->rps.max_freq);
4217
4218 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
4219 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
4220 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4221 dev_priv->rps.efficient_freq);
4222
4223 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
4224 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
4225 vlv_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
4226 dev_priv->rps.rp1_freq);
4227
4228 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
4229 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
4230 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4231 dev_priv->rps.min_freq);
4232
4233 /* Preserve min/max settings in case of re-init */
4234 if (dev_priv->rps.max_freq_softlimit == 0)
4235 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4236
4237 if (dev_priv->rps.min_freq_softlimit == 0)
4238 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
4239
4240 mutex_unlock(&dev_priv->rps.hw_lock);
4241 }
4242
4243 static void cherryview_init_gt_powersave(struct drm_device *dev)
4244 {
4245 struct drm_i915_private *dev_priv = dev->dev_private;
4246 u32 val;
4247
4248 cherryview_setup_pctx(dev);
4249
4250 mutex_lock(&dev_priv->rps.hw_lock);
4251
4252 val = vlv_punit_read(dev_priv, CCK_FUSE_REG);
4253 switch ((val >> 2) & 0x7) {
4254 case 0:
4255 case 1:
4256 dev_priv->rps.cz_freq = 200;
4257 dev_priv->mem_freq = 1600;
4258 break;
4259 case 2:
4260 dev_priv->rps.cz_freq = 267;
4261 dev_priv->mem_freq = 1600;
4262 break;
4263 case 3:
4264 dev_priv->rps.cz_freq = 333;
4265 dev_priv->mem_freq = 2000;
4266 break;
4267 case 4:
4268 dev_priv->rps.cz_freq = 320;
4269 dev_priv->mem_freq = 1600;
4270 break;
4271 case 5:
4272 dev_priv->rps.cz_freq = 400;
4273 dev_priv->mem_freq = 1600;
4274 break;
4275 }
4276 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
4277
4278 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
4279 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
4280 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
4281 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4282 dev_priv->rps.max_freq);
4283
4284 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
4285 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
4286 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4287 dev_priv->rps.efficient_freq);
4288
4289 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
4290 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
4291 vlv_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
4292 dev_priv->rps.rp1_freq);
4293
4294 dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv);
4295 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
4296 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4297 dev_priv->rps.min_freq);
4298
4299 WARN_ONCE((dev_priv->rps.max_freq |
4300 dev_priv->rps.efficient_freq |
4301 dev_priv->rps.rp1_freq |
4302 dev_priv->rps.min_freq) & 1,
4303 "Odd GPU freq values\n");
4304
4305 /* Preserve min/max settings in case of re-init */
4306 if (dev_priv->rps.max_freq_softlimit == 0)
4307 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4308
4309 if (dev_priv->rps.min_freq_softlimit == 0)
4310 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
4311
4312 mutex_unlock(&dev_priv->rps.hw_lock);
4313 }
4314
4315 static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
4316 {
4317 valleyview_cleanup_pctx(dev);
4318 }
4319
4320 static void cherryview_enable_rps(struct drm_device *dev)
4321 {
4322 struct drm_i915_private *dev_priv = dev->dev_private;
4323 struct intel_engine_cs *ring;
4324 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
4325 int i;
4326
4327 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4328
4329 gtfifodbg = I915_READ(GTFIFODBG);
4330 if (gtfifodbg) {
4331 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4332 gtfifodbg);
4333 I915_WRITE(GTFIFODBG, gtfifodbg);
4334 }
4335
4336 cherryview_check_pctx(dev_priv);
4337
4338 /* 1a & 1b: Get forcewake during program sequence. Although the driver
4339 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4340 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
4341
4342 /* 2a: Program RC6 thresholds.*/
4343 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4344 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4345 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4346
4347 for_each_ring(ring, dev_priv, i)
4348 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4349 I915_WRITE(GEN6_RC_SLEEP, 0);
4350
4351 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
4352
4353 /* allows RC6 residency counter to work */
4354 I915_WRITE(VLV_COUNTER_CONTROL,
4355 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
4356 VLV_MEDIA_RC6_COUNT_EN |
4357 VLV_RENDER_RC6_COUNT_EN));
4358
4359 /* For now we assume BIOS is allocating and populating the PCBR */
4360 pcbr = I915_READ(VLV_PCBR);
4361
4362 DRM_DEBUG_DRIVER("PCBR offset : 0x%x\n", pcbr);
4363
4364 /* 3: Enable RC6 */
4365 if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
4366 (pcbr >> VLV_PCBR_ADDR_SHIFT))
4367 rc6_mode = GEN6_RC_CTL_EI_MODE(1);
4368
4369 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
4370
4371 /* 4 Program defaults and thresholds for RPS*/
4372 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
4373 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
4374 I915_WRITE(GEN6_RP_UP_EI, 66000);
4375 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
4376
4377 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4378
4379 /* WaDisablePwrmtrEvent:chv (pre-production hw) */
4380 I915_WRITE(0xA80C, I915_READ(0xA80C) & 0x00ffffff);
4381 I915_WRITE(0xA810, I915_READ(0xA810) & 0xffffff00);
4382
4383 /* 5: Enable RPS */
4384 I915_WRITE(GEN6_RP_CONTROL,
4385 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4386 GEN6_RP_MEDIA_IS_GFX | /* WaSetMaskForGfxBusyness:chv (pre-production hw ?) */
4387 GEN6_RP_ENABLE |
4388 GEN6_RP_UP_BUSY_AVG |
4389 GEN6_RP_DOWN_IDLE_AVG);
4390
4391 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4392
4393 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
4394 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
4395
4396 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
4397 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
4398 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
4399 dev_priv->rps.cur_freq);
4400
4401 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
4402 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4403 dev_priv->rps.efficient_freq);
4404
4405 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
4406
4407 gen8_enable_rps_interrupts(dev);
4408
4409 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
4410 }
4411
4412 static void valleyview_enable_rps(struct drm_device *dev)
4413 {
4414 struct drm_i915_private *dev_priv = dev->dev_private;
4415 struct intel_engine_cs *ring;
4416 u32 gtfifodbg, val, rc6_mode = 0;
4417 int i;
4418
4419 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4420
4421 valleyview_check_pctx(dev_priv);
4422
4423 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
4424 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4425 gtfifodbg);
4426 I915_WRITE(GTFIFODBG, gtfifodbg);
4427 }
4428
4429 /* If VLV, Forcewake all wells, else re-direct to regular path */
4430 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
4431
4432 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
4433 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
4434 I915_WRITE(GEN6_RP_UP_EI, 66000);
4435 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
4436
4437 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4438 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 0xf4240);
4439
4440 I915_WRITE(GEN6_RP_CONTROL,
4441 GEN6_RP_MEDIA_TURBO |
4442 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4443 GEN6_RP_MEDIA_IS_GFX |
4444 GEN6_RP_ENABLE |
4445 GEN6_RP_UP_BUSY_AVG |
4446 GEN6_RP_DOWN_IDLE_CONT);
4447
4448 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
4449 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4450 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4451
4452 for_each_ring(ring, dev_priv, i)
4453 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4454
4455 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
4456
4457 /* allows RC6 residency counter to work */
4458 I915_WRITE(VLV_COUNTER_CONTROL,
4459 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
4460 VLV_RENDER_RC0_COUNT_EN |
4461 VLV_MEDIA_RC6_COUNT_EN |
4462 VLV_RENDER_RC6_COUNT_EN));
4463
4464 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4465 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
4466
4467 intel_print_rc6_info(dev, rc6_mode);
4468
4469 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
4470
4471 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4472
4473 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
4474 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
4475
4476 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
4477 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
4478 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
4479 dev_priv->rps.cur_freq);
4480
4481 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
4482 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4483 dev_priv->rps.efficient_freq);
4484
4485 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
4486
4487 gen6_enable_rps_interrupts(dev);
4488
4489 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
4490 }
4491
4492 void ironlake_teardown_rc6(struct drm_device *dev)
4493 {
4494 struct drm_i915_private *dev_priv = dev->dev_private;
4495
4496 if (dev_priv->ips.renderctx) {
4497 i915_gem_object_ggtt_unpin(dev_priv->ips.renderctx);
4498 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
4499 dev_priv->ips.renderctx = NULL;
4500 }
4501
4502 if (dev_priv->ips.pwrctx) {
4503 i915_gem_object_ggtt_unpin(dev_priv->ips.pwrctx);
4504 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
4505 dev_priv->ips.pwrctx = NULL;
4506 }
4507 }
4508
4509 static void ironlake_disable_rc6(struct drm_device *dev)
4510 {
4511 struct drm_i915_private *dev_priv = dev->dev_private;
4512
4513 if (I915_READ(PWRCTXA)) {
4514 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
4515 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
4516 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
4517 50);
4518
4519 I915_WRITE(PWRCTXA, 0);
4520 POSTING_READ(PWRCTXA);
4521
4522 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
4523 POSTING_READ(RSTDBYCTL);
4524 }
4525 }
4526
4527 static int ironlake_setup_rc6(struct drm_device *dev)
4528 {
4529 struct drm_i915_private *dev_priv = dev->dev_private;
4530
4531 if (dev_priv->ips.renderctx == NULL)
4532 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
4533 if (!dev_priv->ips.renderctx)
4534 return -ENOMEM;
4535
4536 if (dev_priv->ips.pwrctx == NULL)
4537 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
4538 if (!dev_priv->ips.pwrctx) {
4539 ironlake_teardown_rc6(dev);
4540 return -ENOMEM;
4541 }
4542
4543 return 0;
4544 }
4545
4546 static void ironlake_enable_rc6(struct drm_device *dev)
4547 {
4548 struct drm_i915_private *dev_priv = dev->dev_private;
4549 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
4550 bool was_interruptible;
4551 int ret;
4552
4553 /* rc6 disabled by default due to repeated reports of hanging during
4554 * boot and resume.
4555 */
4556 if (!intel_enable_rc6(dev))
4557 return;
4558
4559 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4560
4561 ret = ironlake_setup_rc6(dev);
4562 if (ret)
4563 return;
4564
4565 was_interruptible = dev_priv->mm.interruptible;
4566 dev_priv->mm.interruptible = false;
4567
4568 /*
4569 * GPU can automatically power down the render unit if given a page
4570 * to save state.
4571 */
4572 ret = intel_ring_begin(ring, 6);
4573 if (ret) {
4574 ironlake_teardown_rc6(dev);
4575 dev_priv->mm.interruptible = was_interruptible;
4576 return;
4577 }
4578
4579 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
4580 intel_ring_emit(ring, MI_SET_CONTEXT);
4581 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) |
4582 MI_MM_SPACE_GTT |
4583 MI_SAVE_EXT_STATE_EN |
4584 MI_RESTORE_EXT_STATE_EN |
4585 MI_RESTORE_INHIBIT);
4586 intel_ring_emit(ring, MI_SUSPEND_FLUSH);
4587 intel_ring_emit(ring, MI_NOOP);
4588 intel_ring_emit(ring, MI_FLUSH);
4589 intel_ring_advance(ring);
4590
4591 /*
4592 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
4593 * does an implicit flush, combined with MI_FLUSH above, it should be
4594 * safe to assume that renderctx is valid
4595 */
4596 ret = intel_ring_idle(ring);
4597 dev_priv->mm.interruptible = was_interruptible;
4598 if (ret) {
4599 DRM_ERROR("failed to enable ironlake power savings\n");
4600 ironlake_teardown_rc6(dev);
4601 return;
4602 }
4603
4604 I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN);
4605 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
4606
4607 intel_print_rc6_info(dev, GEN6_RC_CTL_RC6_ENABLE);
4608 }
4609
4610 static unsigned long intel_pxfreq(u32 vidfreq)
4611 {
4612 unsigned long freq;
4613 int div = (vidfreq & 0x3f0000) >> 16;
4614 int post = (vidfreq & 0x3000) >> 12;
4615 int pre = (vidfreq & 0x7);
4616
4617 if (!pre)
4618 return 0;
4619
4620 freq = ((div * 133333) / ((1<<post) * pre));
4621
4622 return freq;
4623 }
4624
4625 static const struct cparams {
4626 u16 i;
4627 u16 t;
4628 u16 m;
4629 u16 c;
4630 } cparams[] = {
4631 { 1, 1333, 301, 28664 },
4632 { 1, 1066, 294, 24460 },
4633 { 1, 800, 294, 25192 },
4634 { 0, 1333, 276, 27605 },
4635 { 0, 1066, 276, 27605 },
4636 { 0, 800, 231, 23784 },
4637 };
4638
4639 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
4640 {
4641 u64 total_count, diff, ret;
4642 u32 count1, count2, count3, m = 0, c = 0;
4643 unsigned long now = jiffies_to_msecs(jiffies), diff1;
4644 int i;
4645
4646 assert_spin_locked(&mchdev_lock);
4647
4648 diff1 = now - dev_priv->ips.last_time1;
4649
4650 /* Prevent division-by-zero if we are asking too fast.
4651 * Also, we don't get interesting results if we are polling
4652 * faster than once in 10ms, so just return the saved value
4653 * in such cases.
4654 */
4655 if (diff1 <= 10)
4656 return dev_priv->ips.chipset_power;
4657
4658 count1 = I915_READ(DMIEC);
4659 count2 = I915_READ(DDREC);
4660 count3 = I915_READ(CSIEC);
4661
4662 total_count = count1 + count2 + count3;
4663
4664 /* FIXME: handle per-counter overflow */
4665 if (total_count < dev_priv->ips.last_count1) {
4666 diff = ~0UL - dev_priv->ips.last_count1;
4667 diff += total_count;
4668 } else {
4669 diff = total_count - dev_priv->ips.last_count1;
4670 }
4671
4672 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
4673 if (cparams[i].i == dev_priv->ips.c_m &&
4674 cparams[i].t == dev_priv->ips.r_t) {
4675 m = cparams[i].m;
4676 c = cparams[i].c;
4677 break;
4678 }
4679 }
4680
4681 diff = div_u64(diff, diff1);
4682 ret = ((m * diff) + c);
4683 ret = div_u64(ret, 10);
4684
4685 dev_priv->ips.last_count1 = total_count;
4686 dev_priv->ips.last_time1 = now;
4687
4688 dev_priv->ips.chipset_power = ret;
4689
4690 return ret;
4691 }
4692
4693 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
4694 {
4695 struct drm_device *dev = dev_priv->dev;
4696 unsigned long val;
4697
4698 if (INTEL_INFO(dev)->gen != 5)
4699 return 0;
4700
4701 spin_lock_irq(&mchdev_lock);
4702
4703 val = __i915_chipset_val(dev_priv);
4704
4705 spin_unlock_irq(&mchdev_lock);
4706
4707 return val;
4708 }
4709
4710 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
4711 {
4712 unsigned long m, x, b;
4713 u32 tsfs;
4714
4715 tsfs = I915_READ(TSFS);
4716
4717 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
4718 x = I915_READ8(TR1);
4719
4720 b = tsfs & TSFS_INTR_MASK;
4721
4722 return ((m * x) / 127) - b;
4723 }
4724
4725 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
4726 {
4727 struct drm_device *dev = dev_priv->dev;
4728 static const struct v_table {
4729 u16 vd; /* in .1 mil */
4730 u16 vm; /* in .1 mil */
4731 } v_table[] = {
4732 { 0, 0, },
4733 { 375, 0, },
4734 { 500, 0, },
4735 { 625, 0, },
4736 { 750, 0, },
4737 { 875, 0, },
4738 { 1000, 0, },
4739 { 1125, 0, },
4740 { 4125, 3000, },
4741 { 4125, 3000, },
4742 { 4125, 3000, },
4743 { 4125, 3000, },
4744 { 4125, 3000, },
4745 { 4125, 3000, },
4746 { 4125, 3000, },
4747 { 4125, 3000, },
4748 { 4125, 3000, },
4749 { 4125, 3000, },
4750 { 4125, 3000, },
4751 { 4125, 3000, },
4752 { 4125, 3000, },
4753 { 4125, 3000, },
4754 { 4125, 3000, },
4755 { 4125, 3000, },
4756 { 4125, 3000, },
4757 { 4125, 3000, },
4758 { 4125, 3000, },
4759 { 4125, 3000, },
4760 { 4125, 3000, },
4761 { 4125, 3000, },
4762 { 4125, 3000, },
4763 { 4125, 3000, },
4764 { 4250, 3125, },
4765 { 4375, 3250, },
4766 { 4500, 3375, },
4767 { 4625, 3500, },
4768 { 4750, 3625, },
4769 { 4875, 3750, },
4770 { 5000, 3875, },
4771 { 5125, 4000, },
4772 { 5250, 4125, },
4773 { 5375, 4250, },
4774 { 5500, 4375, },
4775 { 5625, 4500, },
4776 { 5750, 4625, },
4777 { 5875, 4750, },
4778 { 6000, 4875, },
4779 { 6125, 5000, },
4780 { 6250, 5125, },
4781 { 6375, 5250, },
4782 { 6500, 5375, },
4783 { 6625, 5500, },
4784 { 6750, 5625, },
4785 { 6875, 5750, },
4786 { 7000, 5875, },
4787 { 7125, 6000, },
4788 { 7250, 6125, },
4789 { 7375, 6250, },
4790 { 7500, 6375, },
4791 { 7625, 6500, },
4792 { 7750, 6625, },
4793 { 7875, 6750, },
4794 { 8000, 6875, },
4795 { 8125, 7000, },
4796 { 8250, 7125, },
4797 { 8375, 7250, },
4798 { 8500, 7375, },
4799 { 8625, 7500, },
4800 { 8750, 7625, },
4801 { 8875, 7750, },
4802 { 9000, 7875, },
4803 { 9125, 8000, },
4804 { 9250, 8125, },
4805 { 9375, 8250, },
4806 { 9500, 8375, },
4807 { 9625, 8500, },
4808 { 9750, 8625, },
4809 { 9875, 8750, },
4810 { 10000, 8875, },
4811 { 10125, 9000, },
4812 { 10250, 9125, },
4813 { 10375, 9250, },
4814 { 10500, 9375, },
4815 { 10625, 9500, },
4816 { 10750, 9625, },
4817 { 10875, 9750, },
4818 { 11000, 9875, },
4819 { 11125, 10000, },
4820 { 11250, 10125, },
4821 { 11375, 10250, },
4822 { 11500, 10375, },
4823 { 11625, 10500, },
4824 { 11750, 10625, },
4825 { 11875, 10750, },
4826 { 12000, 10875, },
4827 { 12125, 11000, },
4828 { 12250, 11125, },
4829 { 12375, 11250, },
4830 { 12500, 11375, },
4831 { 12625, 11500, },
4832 { 12750, 11625, },
4833 { 12875, 11750, },
4834 { 13000, 11875, },
4835 { 13125, 12000, },
4836 { 13250, 12125, },
4837 { 13375, 12250, },
4838 { 13500, 12375, },
4839 { 13625, 12500, },
4840 { 13750, 12625, },
4841 { 13875, 12750, },
4842 { 14000, 12875, },
4843 { 14125, 13000, },
4844 { 14250, 13125, },
4845 { 14375, 13250, },
4846 { 14500, 13375, },
4847 { 14625, 13500, },
4848 { 14750, 13625, },
4849 { 14875, 13750, },
4850 { 15000, 13875, },
4851 { 15125, 14000, },
4852 { 15250, 14125, },
4853 { 15375, 14250, },
4854 { 15500, 14375, },
4855 { 15625, 14500, },
4856 { 15750, 14625, },
4857 { 15875, 14750, },
4858 { 16000, 14875, },
4859 { 16125, 15000, },
4860 };
4861 if (INTEL_INFO(dev)->is_mobile)
4862 return v_table[pxvid].vm;
4863 else
4864 return v_table[pxvid].vd;
4865 }
4866
4867 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
4868 {
4869 u64 now, diff, diffms;
4870 u32 count;
4871
4872 assert_spin_locked(&mchdev_lock);
4873
4874 now = ktime_get_raw_ns();
4875 diffms = now - dev_priv->ips.last_time2;
4876 do_div(diffms, NSEC_PER_MSEC);
4877
4878 /* Don't divide by 0 */
4879 if (!diffms)
4880 return;
4881
4882 count = I915_READ(GFXEC);
4883
4884 if (count < dev_priv->ips.last_count2) {
4885 diff = ~0UL - dev_priv->ips.last_count2;
4886 diff += count;
4887 } else {
4888 diff = count - dev_priv->ips.last_count2;
4889 }
4890
4891 dev_priv->ips.last_count2 = count;
4892 dev_priv->ips.last_time2 = now;
4893
4894 /* More magic constants... */
4895 diff = diff * 1181;
4896 diff = div_u64(diff, diffms * 10);
4897 dev_priv->ips.gfx_power = diff;
4898 }
4899
4900 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
4901 {
4902 struct drm_device *dev = dev_priv->dev;
4903
4904 if (INTEL_INFO(dev)->gen != 5)
4905 return;
4906
4907 spin_lock_irq(&mchdev_lock);
4908
4909 __i915_update_gfx_val(dev_priv);
4910
4911 spin_unlock_irq(&mchdev_lock);
4912 }
4913
4914 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
4915 {
4916 unsigned long t, corr, state1, corr2, state2;
4917 u32 pxvid, ext_v;
4918
4919 assert_spin_locked(&mchdev_lock);
4920
4921 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_freq * 4));
4922 pxvid = (pxvid >> 24) & 0x7f;
4923 ext_v = pvid_to_extvid(dev_priv, pxvid);
4924
4925 state1 = ext_v;
4926
4927 t = i915_mch_val(dev_priv);
4928
4929 /* Revel in the empirically derived constants */
4930
4931 /* Correction factor in 1/100000 units */
4932 if (t > 80)
4933 corr = ((t * 2349) + 135940);
4934 else if (t >= 50)
4935 corr = ((t * 964) + 29317);
4936 else /* < 50 */
4937 corr = ((t * 301) + 1004);
4938
4939 corr = corr * ((150142 * state1) / 10000 - 78642);
4940 corr /= 100000;
4941 corr2 = (corr * dev_priv->ips.corr);
4942
4943 state2 = (corr2 * state1) / 10000;
4944 state2 /= 100; /* convert to mW */
4945
4946 __i915_update_gfx_val(dev_priv);
4947
4948 return dev_priv->ips.gfx_power + state2;
4949 }
4950
4951 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
4952 {
4953 struct drm_device *dev = dev_priv->dev;
4954 unsigned long val;
4955
4956 if (INTEL_INFO(dev)->gen != 5)
4957 return 0;
4958
4959 spin_lock_irq(&mchdev_lock);
4960
4961 val = __i915_gfx_val(dev_priv);
4962
4963 spin_unlock_irq(&mchdev_lock);
4964
4965 return val;
4966 }
4967
4968 /**
4969 * i915_read_mch_val - return value for IPS use
4970 *
4971 * Calculate and return a value for the IPS driver to use when deciding whether
4972 * we have thermal and power headroom to increase CPU or GPU power budget.
4973 */
4974 unsigned long i915_read_mch_val(void)
4975 {
4976 struct drm_i915_private *dev_priv;
4977 unsigned long chipset_val, graphics_val, ret = 0;
4978
4979 spin_lock_irq(&mchdev_lock);
4980 if (!i915_mch_dev)
4981 goto out_unlock;
4982 dev_priv = i915_mch_dev;
4983
4984 chipset_val = __i915_chipset_val(dev_priv);
4985 graphics_val = __i915_gfx_val(dev_priv);
4986
4987 ret = chipset_val + graphics_val;
4988
4989 out_unlock:
4990 spin_unlock_irq(&mchdev_lock);
4991
4992 return ret;
4993 }
4994 EXPORT_SYMBOL_GPL(i915_read_mch_val);
4995
4996 /**
4997 * i915_gpu_raise - raise GPU frequency limit
4998 *
4999 * Raise the limit; IPS indicates we have thermal headroom.
5000 */
5001 bool i915_gpu_raise(void)
5002 {
5003 struct drm_i915_private *dev_priv;
5004 bool ret = true;
5005
5006 spin_lock_irq(&mchdev_lock);
5007 if (!i915_mch_dev) {
5008 ret = false;
5009 goto out_unlock;
5010 }
5011 dev_priv = i915_mch_dev;
5012
5013 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
5014 dev_priv->ips.max_delay--;
5015
5016 out_unlock:
5017 spin_unlock_irq(&mchdev_lock);
5018
5019 return ret;
5020 }
5021 EXPORT_SYMBOL_GPL(i915_gpu_raise);
5022
5023 /**
5024 * i915_gpu_lower - lower GPU frequency limit
5025 *
5026 * IPS indicates we're close to a thermal limit, so throttle back the GPU
5027 * frequency maximum.
5028 */
5029 bool i915_gpu_lower(void)
5030 {
5031 struct drm_i915_private *dev_priv;
5032 bool ret = true;
5033
5034 spin_lock_irq(&mchdev_lock);
5035 if (!i915_mch_dev) {
5036 ret = false;
5037 goto out_unlock;
5038 }
5039 dev_priv = i915_mch_dev;
5040
5041 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
5042 dev_priv->ips.max_delay++;
5043
5044 out_unlock:
5045 spin_unlock_irq(&mchdev_lock);
5046
5047 return ret;
5048 }
5049 EXPORT_SYMBOL_GPL(i915_gpu_lower);
5050
5051 /**
5052 * i915_gpu_busy - indicate GPU business to IPS
5053 *
5054 * Tell the IPS driver whether or not the GPU is busy.
5055 */
5056 bool i915_gpu_busy(void)
5057 {
5058 struct drm_i915_private *dev_priv;
5059 struct intel_engine_cs *ring;
5060 bool ret = false;
5061 int i;
5062
5063 spin_lock_irq(&mchdev_lock);
5064 if (!i915_mch_dev)
5065 goto out_unlock;
5066 dev_priv = i915_mch_dev;
5067
5068 for_each_ring(ring, dev_priv, i)
5069 ret |= !list_empty(&ring->request_list);
5070
5071 out_unlock:
5072 spin_unlock_irq(&mchdev_lock);
5073
5074 return ret;
5075 }
5076 EXPORT_SYMBOL_GPL(i915_gpu_busy);
5077
5078 /**
5079 * i915_gpu_turbo_disable - disable graphics turbo
5080 *
5081 * Disable graphics turbo by resetting the max frequency and setting the
5082 * current frequency to the default.
5083 */
5084 bool i915_gpu_turbo_disable(void)
5085 {
5086 struct drm_i915_private *dev_priv;
5087 bool ret = true;
5088
5089 spin_lock_irq(&mchdev_lock);
5090 if (!i915_mch_dev) {
5091 ret = false;
5092 goto out_unlock;
5093 }
5094 dev_priv = i915_mch_dev;
5095
5096 dev_priv->ips.max_delay = dev_priv->ips.fstart;
5097
5098 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
5099 ret = false;
5100
5101 out_unlock:
5102 spin_unlock_irq(&mchdev_lock);
5103
5104 return ret;
5105 }
5106 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
5107
5108 /**
5109 * Tells the intel_ips driver that the i915 driver is now loaded, if
5110 * IPS got loaded first.
5111 *
5112 * This awkward dance is so that neither module has to depend on the
5113 * other in order for IPS to do the appropriate communication of
5114 * GPU turbo limits to i915.
5115 */
5116 static void
5117 ips_ping_for_i915_load(void)
5118 {
5119 void (*link)(void);
5120
5121 link = symbol_get(ips_link_to_i915_driver);
5122 if (link) {
5123 link();
5124 symbol_put(ips_link_to_i915_driver);
5125 }
5126 }
5127
5128 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
5129 {
5130 /* We only register the i915 ips part with intel-ips once everything is
5131 * set up, to avoid intel-ips sneaking in and reading bogus values. */
5132 spin_lock_irq(&mchdev_lock);
5133 i915_mch_dev = dev_priv;
5134 spin_unlock_irq(&mchdev_lock);
5135
5136 ips_ping_for_i915_load();
5137 }
5138
5139 void intel_gpu_ips_teardown(void)
5140 {
5141 spin_lock_irq(&mchdev_lock);
5142 i915_mch_dev = NULL;
5143 spin_unlock_irq(&mchdev_lock);
5144 }
5145
5146 static void intel_init_emon(struct drm_device *dev)
5147 {
5148 struct drm_i915_private *dev_priv = dev->dev_private;
5149 u32 lcfuse;
5150 u8 pxw[16];
5151 int i;
5152
5153 /* Disable to program */
5154 I915_WRITE(ECR, 0);
5155 POSTING_READ(ECR);
5156
5157 /* Program energy weights for various events */
5158 I915_WRITE(SDEW, 0x15040d00);
5159 I915_WRITE(CSIEW0, 0x007f0000);
5160 I915_WRITE(CSIEW1, 0x1e220004);
5161 I915_WRITE(CSIEW2, 0x04000004);
5162
5163 for (i = 0; i < 5; i++)
5164 I915_WRITE(PEW + (i * 4), 0);
5165 for (i = 0; i < 3; i++)
5166 I915_WRITE(DEW + (i * 4), 0);
5167
5168 /* Program P-state weights to account for frequency power adjustment */
5169 for (i = 0; i < 16; i++) {
5170 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
5171 unsigned long freq = intel_pxfreq(pxvidfreq);
5172 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5173 PXVFREQ_PX_SHIFT;
5174 unsigned long val;
5175
5176 val = vid * vid;
5177 val *= (freq / 1000);
5178 val *= 255;
5179 val /= (127*127*900);
5180 if (val > 0xff)
5181 DRM_ERROR("bad pxval: %ld\n", val);
5182 pxw[i] = val;
5183 }
5184 /* Render standby states get 0 weight */
5185 pxw[14] = 0;
5186 pxw[15] = 0;
5187
5188 for (i = 0; i < 4; i++) {
5189 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5190 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
5191 I915_WRITE(PXW + (i * 4), val);
5192 }
5193
5194 /* Adjust magic regs to magic values (more experimental results) */
5195 I915_WRITE(OGW0, 0);
5196 I915_WRITE(OGW1, 0);
5197 I915_WRITE(EG0, 0x00007f00);
5198 I915_WRITE(EG1, 0x0000000e);
5199 I915_WRITE(EG2, 0x000e0000);
5200 I915_WRITE(EG3, 0x68000300);
5201 I915_WRITE(EG4, 0x42000000);
5202 I915_WRITE(EG5, 0x00140031);
5203 I915_WRITE(EG6, 0);
5204 I915_WRITE(EG7, 0);
5205
5206 for (i = 0; i < 8; i++)
5207 I915_WRITE(PXWL + (i * 4), 0);
5208
5209 /* Enable PMON + select events */
5210 I915_WRITE(ECR, 0x80000019);
5211
5212 lcfuse = I915_READ(LCFUSE02);
5213
5214 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
5215 }
5216
5217 void intel_init_gt_powersave(struct drm_device *dev)
5218 {
5219 i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
5220
5221 if (IS_CHERRYVIEW(dev))
5222 cherryview_init_gt_powersave(dev);
5223 else if (IS_VALLEYVIEW(dev))
5224 valleyview_init_gt_powersave(dev);
5225 }
5226
5227 void intel_cleanup_gt_powersave(struct drm_device *dev)
5228 {
5229 if (IS_CHERRYVIEW(dev))
5230 return;
5231 else if (IS_VALLEYVIEW(dev))
5232 valleyview_cleanup_gt_powersave(dev);
5233 }
5234
5235 /**
5236 * intel_suspend_gt_powersave - suspend PM work and helper threads
5237 * @dev: drm device
5238 *
5239 * We don't want to disable RC6 or other features here, we just want
5240 * to make sure any work we've queued has finished and won't bother
5241 * us while we're suspended.
5242 */
5243 void intel_suspend_gt_powersave(struct drm_device *dev)
5244 {
5245 struct drm_i915_private *dev_priv = dev->dev_private;
5246
5247 /* Interrupts should be disabled already to avoid re-arming. */
5248 WARN_ON(intel_irqs_enabled(dev_priv));
5249
5250 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
5251
5252 cancel_work_sync(&dev_priv->rps.work);
5253
5254 /* Force GPU to min freq during suspend */
5255 gen6_rps_idle(dev_priv);
5256 }
5257
5258 void intel_disable_gt_powersave(struct drm_device *dev)
5259 {
5260 struct drm_i915_private *dev_priv = dev->dev_private;
5261
5262 /* Interrupts should be disabled already to avoid re-arming. */
5263 WARN_ON(intel_irqs_enabled(dev_priv));
5264
5265 if (IS_IRONLAKE_M(dev)) {
5266 ironlake_disable_drps(dev);
5267 ironlake_disable_rc6(dev);
5268 } else if (INTEL_INFO(dev)->gen >= 6) {
5269 intel_suspend_gt_powersave(dev);
5270
5271 mutex_lock(&dev_priv->rps.hw_lock);
5272 if (IS_CHERRYVIEW(dev))
5273 cherryview_disable_rps(dev);
5274 else if (IS_VALLEYVIEW(dev))
5275 valleyview_disable_rps(dev);
5276 else
5277 gen6_disable_rps(dev);
5278 dev_priv->rps.enabled = false;
5279 mutex_unlock(&dev_priv->rps.hw_lock);
5280 }
5281 }
5282
5283 static void intel_gen6_powersave_work(struct work_struct *work)
5284 {
5285 struct drm_i915_private *dev_priv =
5286 container_of(work, struct drm_i915_private,
5287 rps.delayed_resume_work.work);
5288 struct drm_device *dev = dev_priv->dev;
5289
5290 mutex_lock(&dev_priv->rps.hw_lock);
5291
5292 if (IS_CHERRYVIEW(dev)) {
5293 cherryview_enable_rps(dev);
5294 } else if (IS_VALLEYVIEW(dev)) {
5295 valleyview_enable_rps(dev);
5296 } else if (IS_BROADWELL(dev)) {
5297 gen8_enable_rps(dev);
5298 __gen6_update_ring_freq(dev);
5299 } else {
5300 gen6_enable_rps(dev);
5301 __gen6_update_ring_freq(dev);
5302 }
5303 dev_priv->rps.enabled = true;
5304 mutex_unlock(&dev_priv->rps.hw_lock);
5305
5306 intel_runtime_pm_put(dev_priv);
5307 }
5308
5309 void intel_enable_gt_powersave(struct drm_device *dev)
5310 {
5311 struct drm_i915_private *dev_priv = dev->dev_private;
5312
5313 if (IS_IRONLAKE_M(dev)) {
5314 mutex_lock(&dev->struct_mutex);
5315 ironlake_enable_drps(dev);
5316 ironlake_enable_rc6(dev);
5317 intel_init_emon(dev);
5318 mutex_unlock(&dev->struct_mutex);
5319 } else if (INTEL_INFO(dev)->gen >= 6) {
5320 /*
5321 * PCU communication is slow and this doesn't need to be
5322 * done at any specific time, so do this out of our fast path
5323 * to make resume and init faster.
5324 *
5325 * We depend on the HW RC6 power context save/restore
5326 * mechanism when entering D3 through runtime PM suspend. So
5327 * disable RPM until RPS/RC6 is properly setup. We can only
5328 * get here via the driver load/system resume/runtime resume
5329 * paths, so the _noresume version is enough (and in case of
5330 * runtime resume it's necessary).
5331 */
5332 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
5333 round_jiffies_up_relative(HZ)))
5334 intel_runtime_pm_get_noresume(dev_priv);
5335 }
5336 }
5337
5338 void intel_reset_gt_powersave(struct drm_device *dev)
5339 {
5340 struct drm_i915_private *dev_priv = dev->dev_private;
5341
5342 dev_priv->rps.enabled = false;
5343 intel_enable_gt_powersave(dev);
5344 }
5345
5346 static void ibx_init_clock_gating(struct drm_device *dev)
5347 {
5348 struct drm_i915_private *dev_priv = dev->dev_private;
5349
5350 /*
5351 * On Ibex Peak and Cougar Point, we need to disable clock
5352 * gating for the panel power sequencer or it will fail to
5353 * start up when no ports are active.
5354 */
5355 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
5356 }
5357
5358 static void g4x_disable_trickle_feed(struct drm_device *dev)
5359 {
5360 struct drm_i915_private *dev_priv = dev->dev_private;
5361 int pipe;
5362
5363 for_each_pipe(dev_priv, pipe) {
5364 I915_WRITE(DSPCNTR(pipe),
5365 I915_READ(DSPCNTR(pipe)) |
5366 DISPPLANE_TRICKLE_FEED_DISABLE);
5367 intel_flush_primary_plane(dev_priv, pipe);
5368 }
5369 }
5370
5371 static void ilk_init_lp_watermarks(struct drm_device *dev)
5372 {
5373 struct drm_i915_private *dev_priv = dev->dev_private;
5374
5375 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
5376 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
5377 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
5378
5379 /*
5380 * Don't touch WM1S_LP_EN here.
5381 * Doing so could cause underruns.
5382 */
5383 }
5384
5385 static void ironlake_init_clock_gating(struct drm_device *dev)
5386 {
5387 struct drm_i915_private *dev_priv = dev->dev_private;
5388 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
5389
5390 /*
5391 * Required for FBC
5392 * WaFbcDisableDpfcClockGating:ilk
5393 */
5394 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
5395 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
5396 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
5397
5398 I915_WRITE(PCH_3DCGDIS0,
5399 MARIUNIT_CLOCK_GATE_DISABLE |
5400 SVSMUNIT_CLOCK_GATE_DISABLE);
5401 I915_WRITE(PCH_3DCGDIS1,
5402 VFMUNIT_CLOCK_GATE_DISABLE);
5403
5404 /*
5405 * According to the spec the following bits should be set in
5406 * order to enable memory self-refresh
5407 * The bit 22/21 of 0x42004
5408 * The bit 5 of 0x42020
5409 * The bit 15 of 0x45000
5410 */
5411 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5412 (I915_READ(ILK_DISPLAY_CHICKEN2) |
5413 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
5414 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
5415 I915_WRITE(DISP_ARB_CTL,
5416 (I915_READ(DISP_ARB_CTL) |
5417 DISP_FBC_WM_DIS));
5418
5419 ilk_init_lp_watermarks(dev);
5420
5421 /*
5422 * Based on the document from hardware guys the following bits
5423 * should be set unconditionally in order to enable FBC.
5424 * The bit 22 of 0x42000
5425 * The bit 22 of 0x42004
5426 * The bit 7,8,9 of 0x42020.
5427 */
5428 if (IS_IRONLAKE_M(dev)) {
5429 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
5430 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5431 I915_READ(ILK_DISPLAY_CHICKEN1) |
5432 ILK_FBCQ_DIS);
5433 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5434 I915_READ(ILK_DISPLAY_CHICKEN2) |
5435 ILK_DPARB_GATE);
5436 }
5437
5438 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
5439
5440 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5441 I915_READ(ILK_DISPLAY_CHICKEN2) |
5442 ILK_ELPIN_409_SELECT);
5443 I915_WRITE(_3D_CHICKEN2,
5444 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
5445 _3D_CHICKEN2_WM_READ_PIPELINED);
5446
5447 /* WaDisableRenderCachePipelinedFlush:ilk */
5448 I915_WRITE(CACHE_MODE_0,
5449 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
5450
5451 /* WaDisable_RenderCache_OperationalFlush:ilk */
5452 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5453
5454 g4x_disable_trickle_feed(dev);
5455
5456 ibx_init_clock_gating(dev);
5457 }
5458
5459 static void cpt_init_clock_gating(struct drm_device *dev)
5460 {
5461 struct drm_i915_private *dev_priv = dev->dev_private;
5462 int pipe;
5463 uint32_t val;
5464
5465 /*
5466 * On Ibex Peak and Cougar Point, we need to disable clock
5467 * gating for the panel power sequencer or it will fail to
5468 * start up when no ports are active.
5469 */
5470 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
5471 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
5472 PCH_CPUNIT_CLOCK_GATE_DISABLE);
5473 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
5474 DPLS_EDP_PPS_FIX_DIS);
5475 /* The below fixes the weird display corruption, a few pixels shifted
5476 * downward, on (only) LVDS of some HP laptops with IVY.
5477 */
5478 for_each_pipe(dev_priv, pipe) {
5479 val = I915_READ(TRANS_CHICKEN2(pipe));
5480 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
5481 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
5482 if (dev_priv->vbt.fdi_rx_polarity_inverted)
5483 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
5484 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
5485 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
5486 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
5487 I915_WRITE(TRANS_CHICKEN2(pipe), val);
5488 }
5489 /* WADP0ClockGatingDisable */
5490 for_each_pipe(dev_priv, pipe) {
5491 I915_WRITE(TRANS_CHICKEN1(pipe),
5492 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
5493 }
5494 }
5495
5496 static void gen6_check_mch_setup(struct drm_device *dev)
5497 {
5498 struct drm_i915_private *dev_priv = dev->dev_private;
5499 uint32_t tmp;
5500
5501 tmp = I915_READ(MCH_SSKPD);
5502 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
5503 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
5504 tmp);
5505 }
5506
5507 static void gen6_init_clock_gating(struct drm_device *dev)
5508 {
5509 struct drm_i915_private *dev_priv = dev->dev_private;
5510 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
5511
5512 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
5513
5514 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5515 I915_READ(ILK_DISPLAY_CHICKEN2) |
5516 ILK_ELPIN_409_SELECT);
5517
5518 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
5519 I915_WRITE(_3D_CHICKEN,
5520 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
5521
5522 /* WaSetupGtModeTdRowDispatch:snb */
5523 if (IS_SNB_GT1(dev))
5524 I915_WRITE(GEN6_GT_MODE,
5525 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
5526
5527 /* WaDisable_RenderCache_OperationalFlush:snb */
5528 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5529
5530 /*
5531 * BSpec recoomends 8x4 when MSAA is used,
5532 * however in practice 16x4 seems fastest.
5533 *
5534 * Note that PS/WM thread counts depend on the WIZ hashing
5535 * disable bit, which we don't touch here, but it's good
5536 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5537 */
5538 I915_WRITE(GEN6_GT_MODE,
5539 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5540
5541 ilk_init_lp_watermarks(dev);
5542
5543 I915_WRITE(CACHE_MODE_0,
5544 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
5545
5546 I915_WRITE(GEN6_UCGCTL1,
5547 I915_READ(GEN6_UCGCTL1) |
5548 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
5549 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
5550
5551 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5552 * gating disable must be set. Failure to set it results in
5553 * flickering pixels due to Z write ordering failures after
5554 * some amount of runtime in the Mesa "fire" demo, and Unigine
5555 * Sanctuary and Tropics, and apparently anything else with
5556 * alpha test or pixel discard.
5557 *
5558 * According to the spec, bit 11 (RCCUNIT) must also be set,
5559 * but we didn't debug actual testcases to find it out.
5560 *
5561 * WaDisableRCCUnitClockGating:snb
5562 * WaDisableRCPBUnitClockGating:snb
5563 */
5564 I915_WRITE(GEN6_UCGCTL2,
5565 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
5566 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5567
5568 /* WaStripsFansDisableFastClipPerformanceFix:snb */
5569 I915_WRITE(_3D_CHICKEN3,
5570 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
5571
5572 /*
5573 * Bspec says:
5574 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
5575 * 3DSTATE_SF number of SF output attributes is more than 16."
5576 */
5577 I915_WRITE(_3D_CHICKEN3,
5578 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
5579
5580 /*
5581 * According to the spec the following bits should be
5582 * set in order to enable memory self-refresh and fbc:
5583 * The bit21 and bit22 of 0x42000
5584 * The bit21 and bit22 of 0x42004
5585 * The bit5 and bit7 of 0x42020
5586 * The bit14 of 0x70180
5587 * The bit14 of 0x71180
5588 *
5589 * WaFbcAsynchFlipDisableFbcQueue:snb
5590 */
5591 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5592 I915_READ(ILK_DISPLAY_CHICKEN1) |
5593 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
5594 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5595 I915_READ(ILK_DISPLAY_CHICKEN2) |
5596 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
5597 I915_WRITE(ILK_DSPCLK_GATE_D,
5598 I915_READ(ILK_DSPCLK_GATE_D) |
5599 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
5600 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
5601
5602 g4x_disable_trickle_feed(dev);
5603
5604 cpt_init_clock_gating(dev);
5605
5606 gen6_check_mch_setup(dev);
5607 }
5608
5609 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
5610 {
5611 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
5612
5613 /*
5614 * WaVSThreadDispatchOverride:ivb,vlv
5615 *
5616 * This actually overrides the dispatch
5617 * mode for all thread types.
5618 */
5619 reg &= ~GEN7_FF_SCHED_MASK;
5620 reg |= GEN7_FF_TS_SCHED_HW;
5621 reg |= GEN7_FF_VS_SCHED_HW;
5622 reg |= GEN7_FF_DS_SCHED_HW;
5623
5624 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
5625 }
5626
5627 static void lpt_init_clock_gating(struct drm_device *dev)
5628 {
5629 struct drm_i915_private *dev_priv = dev->dev_private;
5630
5631 /*
5632 * TODO: this bit should only be enabled when really needed, then
5633 * disabled when not needed anymore in order to save power.
5634 */
5635 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
5636 I915_WRITE(SOUTH_DSPCLK_GATE_D,
5637 I915_READ(SOUTH_DSPCLK_GATE_D) |
5638 PCH_LP_PARTITION_LEVEL_DISABLE);
5639
5640 /* WADPOClockGatingDisable:hsw */
5641 I915_WRITE(_TRANSA_CHICKEN1,
5642 I915_READ(_TRANSA_CHICKEN1) |
5643 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
5644 }
5645
5646 static void lpt_suspend_hw(struct drm_device *dev)
5647 {
5648 struct drm_i915_private *dev_priv = dev->dev_private;
5649
5650 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
5651 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
5652
5653 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
5654 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
5655 }
5656 }
5657
5658 static void broadwell_init_clock_gating(struct drm_device *dev)
5659 {
5660 struct drm_i915_private *dev_priv = dev->dev_private;
5661 enum pipe pipe;
5662
5663 I915_WRITE(WM3_LP_ILK, 0);
5664 I915_WRITE(WM2_LP_ILK, 0);
5665 I915_WRITE(WM1_LP_ILK, 0);
5666
5667 /* WaSwitchSolVfFArbitrationPriority:bdw */
5668 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
5669
5670 /* WaPsrDPAMaskVBlankInSRD:bdw */
5671 I915_WRITE(CHICKEN_PAR1_1,
5672 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
5673
5674 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
5675 for_each_pipe(dev_priv, pipe) {
5676 I915_WRITE(CHICKEN_PIPESL_1(pipe),
5677 I915_READ(CHICKEN_PIPESL_1(pipe)) |
5678 BDW_DPRS_MASK_VBLANK_SRD);
5679 }
5680
5681 /* WaVSRefCountFullforceMissDisable:bdw */
5682 /* WaDSRefCountFullforceMissDisable:bdw */
5683 I915_WRITE(GEN7_FF_THREAD_MODE,
5684 I915_READ(GEN7_FF_THREAD_MODE) &
5685 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
5686
5687 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
5688 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
5689
5690 /* WaDisableSDEUnitClockGating:bdw */
5691 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
5692 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5693
5694 lpt_init_clock_gating(dev);
5695 }
5696
5697 static void haswell_init_clock_gating(struct drm_device *dev)
5698 {
5699 struct drm_i915_private *dev_priv = dev->dev_private;
5700
5701 ilk_init_lp_watermarks(dev);
5702
5703 /* L3 caching of data atomics doesn't work -- disable it. */
5704 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
5705 I915_WRITE(HSW_ROW_CHICKEN3,
5706 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
5707
5708 /* This is required by WaCatErrorRejectionIssue:hsw */
5709 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5710 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5711 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5712
5713 /* WaVSRefCountFullforceMissDisable:hsw */
5714 I915_WRITE(GEN7_FF_THREAD_MODE,
5715 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
5716
5717 /* WaDisable_RenderCache_OperationalFlush:hsw */
5718 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5719
5720 /* enable HiZ Raw Stall Optimization */
5721 I915_WRITE(CACHE_MODE_0_GEN7,
5722 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
5723
5724 /* WaDisable4x2SubspanOptimization:hsw */
5725 I915_WRITE(CACHE_MODE_1,
5726 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5727
5728 /*
5729 * BSpec recommends 8x4 when MSAA is used,
5730 * however in practice 16x4 seems fastest.
5731 *
5732 * Note that PS/WM thread counts depend on the WIZ hashing
5733 * disable bit, which we don't touch here, but it's good
5734 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5735 */
5736 I915_WRITE(GEN7_GT_MODE,
5737 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5738
5739 /* WaSwitchSolVfFArbitrationPriority:hsw */
5740 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
5741
5742 /* WaRsPkgCStateDisplayPMReq:hsw */
5743 I915_WRITE(CHICKEN_PAR1_1,
5744 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
5745
5746 lpt_init_clock_gating(dev);
5747 }
5748
5749 static void ivybridge_init_clock_gating(struct drm_device *dev)
5750 {
5751 struct drm_i915_private *dev_priv = dev->dev_private;
5752 uint32_t snpcr;
5753
5754 ilk_init_lp_watermarks(dev);
5755
5756 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
5757
5758 /* WaDisableEarlyCull:ivb */
5759 I915_WRITE(_3D_CHICKEN3,
5760 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5761
5762 /* WaDisableBackToBackFlipFix:ivb */
5763 I915_WRITE(IVB_CHICKEN3,
5764 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5765 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5766
5767 /* WaDisablePSDDualDispatchEnable:ivb */
5768 if (IS_IVB_GT1(dev))
5769 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5770 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5771
5772 /* WaDisable_RenderCache_OperationalFlush:ivb */
5773 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5774
5775 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
5776 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5777 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5778
5779 /* WaApplyL3ControlAndL3ChickenMode:ivb */
5780 I915_WRITE(GEN7_L3CNTLREG1,
5781 GEN7_WA_FOR_GEN7_L3_CONTROL);
5782 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
5783 GEN7_WA_L3_CHICKEN_MODE);
5784 if (IS_IVB_GT1(dev))
5785 I915_WRITE(GEN7_ROW_CHICKEN2,
5786 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5787 else {
5788 /* must write both registers */
5789 I915_WRITE(GEN7_ROW_CHICKEN2,
5790 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5791 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
5792 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5793 }
5794
5795 /* WaForceL3Serialization:ivb */
5796 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5797 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5798
5799 /*
5800 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5801 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
5802 */
5803 I915_WRITE(GEN6_UCGCTL2,
5804 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
5805
5806 /* This is required by WaCatErrorRejectionIssue:ivb */
5807 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5808 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5809 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5810
5811 g4x_disable_trickle_feed(dev);
5812
5813 gen7_setup_fixed_func_scheduler(dev_priv);
5814
5815 if (0) { /* causes HiZ corruption on ivb:gt1 */
5816 /* enable HiZ Raw Stall Optimization */
5817 I915_WRITE(CACHE_MODE_0_GEN7,
5818 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
5819 }
5820
5821 /* WaDisable4x2SubspanOptimization:ivb */
5822 I915_WRITE(CACHE_MODE_1,
5823 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5824
5825 /*
5826 * BSpec recommends 8x4 when MSAA is used,
5827 * however in practice 16x4 seems fastest.
5828 *
5829 * Note that PS/WM thread counts depend on the WIZ hashing
5830 * disable bit, which we don't touch here, but it's good
5831 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5832 */
5833 I915_WRITE(GEN7_GT_MODE,
5834 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5835
5836 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5837 snpcr &= ~GEN6_MBC_SNPCR_MASK;
5838 snpcr |= GEN6_MBC_SNPCR_MED;
5839 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5840
5841 if (!HAS_PCH_NOP(dev))
5842 cpt_init_clock_gating(dev);
5843
5844 gen6_check_mch_setup(dev);
5845 }
5846
5847 static void valleyview_init_clock_gating(struct drm_device *dev)
5848 {
5849 struct drm_i915_private *dev_priv = dev->dev_private;
5850
5851 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
5852
5853 /* WaDisableEarlyCull:vlv */
5854 I915_WRITE(_3D_CHICKEN3,
5855 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5856
5857 /* WaDisableBackToBackFlipFix:vlv */
5858 I915_WRITE(IVB_CHICKEN3,
5859 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5860 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5861
5862 /* WaPsdDispatchEnable:vlv */
5863 /* WaDisablePSDDualDispatchEnable:vlv */
5864 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5865 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
5866 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5867
5868 /* WaDisable_RenderCache_OperationalFlush:vlv */
5869 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5870
5871 /* WaForceL3Serialization:vlv */
5872 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5873 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5874
5875 /* WaDisableDopClockGating:vlv */
5876 I915_WRITE(GEN7_ROW_CHICKEN2,
5877 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5878
5879 /* This is required by WaCatErrorRejectionIssue:vlv */
5880 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5881 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5882 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5883
5884 gen7_setup_fixed_func_scheduler(dev_priv);
5885
5886 /*
5887 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5888 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
5889 */
5890 I915_WRITE(GEN6_UCGCTL2,
5891 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
5892
5893 /* WaDisableL3Bank2xClockGate:vlv
5894 * Disabling L3 clock gating- MMIO 940c[25] = 1
5895 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
5896 I915_WRITE(GEN7_UCGCTL4,
5897 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
5898
5899 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
5900
5901 /*
5902 * BSpec says this must be set, even though
5903 * WaDisable4x2SubspanOptimization isn't listed for VLV.
5904 */
5905 I915_WRITE(CACHE_MODE_1,
5906 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5907
5908 /*
5909 * WaIncreaseL3CreditsForVLVB0:vlv
5910 * This is the hardware default actually.
5911 */
5912 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
5913
5914 /*
5915 * WaDisableVLVClockGating_VBIIssue:vlv
5916 * Disable clock gating on th GCFG unit to prevent a delay
5917 * in the reporting of vblank events.
5918 */
5919 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
5920 }
5921
5922 static void cherryview_init_clock_gating(struct drm_device *dev)
5923 {
5924 struct drm_i915_private *dev_priv = dev->dev_private;
5925
5926 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
5927
5928 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
5929
5930 /* WaVSRefCountFullforceMissDisable:chv */
5931 /* WaDSRefCountFullforceMissDisable:chv */
5932 I915_WRITE(GEN7_FF_THREAD_MODE,
5933 I915_READ(GEN7_FF_THREAD_MODE) &
5934 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
5935
5936 /* WaDisableSemaphoreAndSyncFlipWait:chv */
5937 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
5938 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
5939
5940 /* WaDisableCSUnitClockGating:chv */
5941 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
5942 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
5943
5944 /* WaDisableSDEUnitClockGating:chv */
5945 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
5946 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5947
5948 /* WaDisableGunitClockGating:chv (pre-production hw) */
5949 I915_WRITE(VLV_GUNIT_CLOCK_GATE, I915_READ(VLV_GUNIT_CLOCK_GATE) |
5950 GINT_DIS);
5951
5952 /* WaDisableFfDopClockGating:chv (pre-production hw) */
5953 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
5954 _MASKED_BIT_ENABLE(GEN8_FF_DOP_CLOCK_GATE_DISABLE));
5955
5956 /* WaDisableDopClockGating:chv (pre-production hw) */
5957 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
5958 GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
5959 }
5960
5961 static void g4x_init_clock_gating(struct drm_device *dev)
5962 {
5963 struct drm_i915_private *dev_priv = dev->dev_private;
5964 uint32_t dspclk_gate;
5965
5966 I915_WRITE(RENCLK_GATE_D1, 0);
5967 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5968 GS_UNIT_CLOCK_GATE_DISABLE |
5969 CL_UNIT_CLOCK_GATE_DISABLE);
5970 I915_WRITE(RAMCLK_GATE_D, 0);
5971 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5972 OVRUNIT_CLOCK_GATE_DISABLE |
5973 OVCUNIT_CLOCK_GATE_DISABLE;
5974 if (IS_GM45(dev))
5975 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5976 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5977
5978 /* WaDisableRenderCachePipelinedFlush */
5979 I915_WRITE(CACHE_MODE_0,
5980 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
5981
5982 /* WaDisable_RenderCache_OperationalFlush:g4x */
5983 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5984
5985 g4x_disable_trickle_feed(dev);
5986 }
5987
5988 static void crestline_init_clock_gating(struct drm_device *dev)
5989 {
5990 struct drm_i915_private *dev_priv = dev->dev_private;
5991
5992 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5993 I915_WRITE(RENCLK_GATE_D2, 0);
5994 I915_WRITE(DSPCLK_GATE_D, 0);
5995 I915_WRITE(RAMCLK_GATE_D, 0);
5996 I915_WRITE16(DEUC, 0);
5997 I915_WRITE(MI_ARB_STATE,
5998 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
5999
6000 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6001 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6002 }
6003
6004 static void broadwater_init_clock_gating(struct drm_device *dev)
6005 {
6006 struct drm_i915_private *dev_priv = dev->dev_private;
6007
6008 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
6009 I965_RCC_CLOCK_GATE_DISABLE |
6010 I965_RCPB_CLOCK_GATE_DISABLE |
6011 I965_ISC_CLOCK_GATE_DISABLE |
6012 I965_FBC_CLOCK_GATE_DISABLE);
6013 I915_WRITE(RENCLK_GATE_D2, 0);
6014 I915_WRITE(MI_ARB_STATE,
6015 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6016
6017 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6018 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6019 }
6020
6021 static void gen3_init_clock_gating(struct drm_device *dev)
6022 {
6023 struct drm_i915_private *dev_priv = dev->dev_private;
6024 u32 dstate = I915_READ(D_STATE);
6025
6026 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
6027 DSTATE_DOT_CLOCK_GATING;
6028 I915_WRITE(D_STATE, dstate);
6029
6030 if (IS_PINEVIEW(dev))
6031 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
6032
6033 /* IIR "flip pending" means done if this bit is set */
6034 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
6035
6036 /* interrupts should cause a wake up from C3 */
6037 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
6038
6039 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
6040 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
6041
6042 I915_WRITE(MI_ARB_STATE,
6043 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6044 }
6045
6046 static void i85x_init_clock_gating(struct drm_device *dev)
6047 {
6048 struct drm_i915_private *dev_priv = dev->dev_private;
6049
6050 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
6051
6052 /* interrupts should cause a wake up from C3 */
6053 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
6054 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
6055
6056 I915_WRITE(MEM_MODE,
6057 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
6058 }
6059
6060 static void i830_init_clock_gating(struct drm_device *dev)
6061 {
6062 struct drm_i915_private *dev_priv = dev->dev_private;
6063
6064 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
6065
6066 I915_WRITE(MEM_MODE,
6067 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
6068 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
6069 }
6070
6071 void intel_init_clock_gating(struct drm_device *dev)
6072 {
6073 struct drm_i915_private *dev_priv = dev->dev_private;
6074
6075 dev_priv->display.init_clock_gating(dev);
6076 }
6077
6078 void intel_suspend_hw(struct drm_device *dev)
6079 {
6080 if (HAS_PCH_LPT(dev))
6081 lpt_suspend_hw(dev);
6082 }
6083
6084 static void intel_init_fbc(struct drm_i915_private *dev_priv)
6085 {
6086 if (!HAS_FBC(dev_priv)) {
6087 dev_priv->fbc.enabled = false;
6088 return;
6089 }
6090
6091 if (INTEL_INFO(dev_priv)->gen >= 7) {
6092 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
6093 dev_priv->display.enable_fbc = gen7_enable_fbc;
6094 dev_priv->display.disable_fbc = ironlake_disable_fbc;
6095 } else if (INTEL_INFO(dev_priv)->gen >= 5) {
6096 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
6097 dev_priv->display.enable_fbc = ironlake_enable_fbc;
6098 dev_priv->display.disable_fbc = ironlake_disable_fbc;
6099 } else if (IS_GM45(dev_priv)) {
6100 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
6101 dev_priv->display.enable_fbc = g4x_enable_fbc;
6102 dev_priv->display.disable_fbc = g4x_disable_fbc;
6103 } else {
6104 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
6105 dev_priv->display.enable_fbc = i8xx_enable_fbc;
6106 dev_priv->display.disable_fbc = i8xx_disable_fbc;
6107
6108 /* This value was pulled out of someone's hat */
6109 I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);
6110 }
6111
6112 dev_priv->fbc.enabled = dev_priv->display.fbc_enabled(dev_priv->dev);
6113 }
6114
6115 /* Set up chip specific power management-related functions */
6116 void intel_init_pm(struct drm_device *dev)
6117 {
6118 struct drm_i915_private *dev_priv = dev->dev_private;
6119
6120 intel_init_fbc(dev_priv);
6121
6122 /* For cxsr */
6123 if (IS_PINEVIEW(dev))
6124 i915_pineview_get_mem_freq(dev);
6125 else if (IS_GEN5(dev))
6126 i915_ironlake_get_mem_freq(dev);
6127
6128 /* For FIFO watermark updates */
6129 if (IS_GEN9(dev)) {
6130 dev_priv->display.init_clock_gating = gen9_init_clock_gating;
6131 } else if (HAS_PCH_SPLIT(dev)) {
6132 ilk_setup_wm_latency(dev);
6133
6134 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
6135 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
6136 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
6137 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
6138 dev_priv->display.update_wm = ilk_update_wm;
6139 dev_priv->display.update_sprite_wm = ilk_update_sprite_wm;
6140 } else {
6141 DRM_DEBUG_KMS("Failed to read display plane latency. "
6142 "Disable CxSR\n");
6143 }
6144
6145 if (IS_GEN5(dev))
6146 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
6147 else if (IS_GEN6(dev))
6148 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
6149 else if (IS_IVYBRIDGE(dev))
6150 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
6151 else if (IS_HASWELL(dev))
6152 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
6153 else if (INTEL_INFO(dev)->gen == 8)
6154 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
6155 } else if (IS_CHERRYVIEW(dev)) {
6156 dev_priv->display.update_wm = cherryview_update_wm;
6157 dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;
6158 dev_priv->display.init_clock_gating =
6159 cherryview_init_clock_gating;
6160 } else if (IS_VALLEYVIEW(dev)) {
6161 dev_priv->display.update_wm = valleyview_update_wm;
6162 dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;
6163 dev_priv->display.init_clock_gating =
6164 valleyview_init_clock_gating;
6165 } else if (IS_PINEVIEW(dev)) {
6166 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
6167 dev_priv->is_ddr3,
6168 dev_priv->fsb_freq,
6169 dev_priv->mem_freq)) {
6170 DRM_INFO("failed to find known CxSR latency "
6171 "(found ddr%s fsb freq %d, mem freq %d), "
6172 "disabling CxSR\n",
6173 (dev_priv->is_ddr3 == 1) ? "3" : "2",
6174 dev_priv->fsb_freq, dev_priv->mem_freq);
6175 /* Disable CxSR and never update its watermark again */
6176 intel_set_memory_cxsr(dev_priv, false);
6177 dev_priv->display.update_wm = NULL;
6178 } else
6179 dev_priv->display.update_wm = pineview_update_wm;
6180 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6181 } else if (IS_G4X(dev)) {
6182 dev_priv->display.update_wm = g4x_update_wm;
6183 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
6184 } else if (IS_GEN4(dev)) {
6185 dev_priv->display.update_wm = i965_update_wm;
6186 if (IS_CRESTLINE(dev))
6187 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
6188 else if (IS_BROADWATER(dev))
6189 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
6190 } else if (IS_GEN3(dev)) {
6191 dev_priv->display.update_wm = i9xx_update_wm;
6192 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6193 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6194 } else if (IS_GEN2(dev)) {
6195 if (INTEL_INFO(dev)->num_pipes == 1) {
6196 dev_priv->display.update_wm = i845_update_wm;
6197 dev_priv->display.get_fifo_size = i845_get_fifo_size;
6198 } else {
6199 dev_priv->display.update_wm = i9xx_update_wm;
6200 dev_priv->display.get_fifo_size = i830_get_fifo_size;
6201 }
6202
6203 if (IS_I85X(dev) || IS_I865G(dev))
6204 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
6205 else
6206 dev_priv->display.init_clock_gating = i830_init_clock_gating;
6207 } else {
6208 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
6209 }
6210 }
6211
6212 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
6213 {
6214 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6215
6216 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6217 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
6218 return -EAGAIN;
6219 }
6220
6221 I915_WRITE(GEN6_PCODE_DATA, *val);
6222 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6223
6224 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6225 500)) {
6226 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
6227 return -ETIMEDOUT;
6228 }
6229
6230 *val = I915_READ(GEN6_PCODE_DATA);
6231 I915_WRITE(GEN6_PCODE_DATA, 0);
6232
6233 return 0;
6234 }
6235
6236 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
6237 {
6238 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6239
6240 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6241 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
6242 return -EAGAIN;
6243 }
6244
6245 I915_WRITE(GEN6_PCODE_DATA, val);
6246 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6247
6248 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6249 500)) {
6250 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
6251 return -ETIMEDOUT;
6252 }
6253
6254 I915_WRITE(GEN6_PCODE_DATA, 0);
6255
6256 return 0;
6257 }
6258
6259 static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
6260 {
6261 int div;
6262
6263 /* 4 x czclk */
6264 switch (dev_priv->mem_freq) {
6265 case 800:
6266 div = 10;
6267 break;
6268 case 1066:
6269 div = 12;
6270 break;
6271 case 1333:
6272 div = 16;
6273 break;
6274 default:
6275 return -1;
6276 }
6277
6278 return DIV_ROUND_CLOSEST(dev_priv->mem_freq * (val + 6 - 0xbd), 4 * div);
6279 }
6280
6281 static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
6282 {
6283 int mul;
6284
6285 /* 4 x czclk */
6286 switch (dev_priv->mem_freq) {
6287 case 800:
6288 mul = 10;
6289 break;
6290 case 1066:
6291 mul = 12;
6292 break;
6293 case 1333:
6294 mul = 16;
6295 break;
6296 default:
6297 return -1;
6298 }
6299
6300 return DIV_ROUND_CLOSEST(4 * mul * val, dev_priv->mem_freq) + 0xbd - 6;
6301 }
6302
6303 static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
6304 {
6305 int div, freq;
6306
6307 switch (dev_priv->rps.cz_freq) {
6308 case 200:
6309 div = 5;
6310 break;
6311 case 267:
6312 div = 6;
6313 break;
6314 case 320:
6315 case 333:
6316 case 400:
6317 div = 8;
6318 break;
6319 default:
6320 return -1;
6321 }
6322
6323 freq = (DIV_ROUND_CLOSEST((dev_priv->rps.cz_freq * val), 2 * div) / 2);
6324
6325 return freq;
6326 }
6327
6328 static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
6329 {
6330 int mul, opcode;
6331
6332 switch (dev_priv->rps.cz_freq) {
6333 case 200:
6334 mul = 5;
6335 break;
6336 case 267:
6337 mul = 6;
6338 break;
6339 case 320:
6340 case 333:
6341 case 400:
6342 mul = 8;
6343 break;
6344 default:
6345 return -1;
6346 }
6347
6348 /* CHV needs even values */
6349 opcode = (DIV_ROUND_CLOSEST((val * 2 * mul), dev_priv->rps.cz_freq) * 2);
6350
6351 return opcode;
6352 }
6353
6354 int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val)
6355 {
6356 int ret = -1;
6357
6358 if (IS_CHERRYVIEW(dev_priv->dev))
6359 ret = chv_gpu_freq(dev_priv, val);
6360 else if (IS_VALLEYVIEW(dev_priv->dev))
6361 ret = byt_gpu_freq(dev_priv, val);
6362
6363 return ret;
6364 }
6365
6366 int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val)
6367 {
6368 int ret = -1;
6369
6370 if (IS_CHERRYVIEW(dev_priv->dev))
6371 ret = chv_freq_opcode(dev_priv, val);
6372 else if (IS_VALLEYVIEW(dev_priv->dev))
6373 ret = byt_freq_opcode(dev_priv, val);
6374
6375 return ret;
6376 }
6377
6378 void intel_pm_setup(struct drm_device *dev)
6379 {
6380 struct drm_i915_private *dev_priv = dev->dev_private;
6381
6382 mutex_init(&dev_priv->rps.hw_lock);
6383
6384 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
6385 intel_gen6_powersave_work);
6386
6387 dev_priv->pm.suspended = false;
6388 }
Linux kernel - Deliverables
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