2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
28 #include <linux/cpufreq.h>
30 #include "intel_drv.h"
31 #include "../../../platform/x86/intel_ips.h"
32 #include <linux/module.h>
35 * RC6 is a special power stage which allows the GPU to enter an very
36 * low-voltage mode when idle, using down to 0V while at this stage. This
37 * stage is entered automatically when the GPU is idle when RC6 support is
38 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
40 * There are different RC6 modes available in Intel GPU, which differentiate
41 * among each other with the latency required to enter and leave RC6 and
42 * voltage consumed by the GPU in different states.
44 * The combination of the following flags define which states GPU is allowed
45 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
46 * RC6pp is deepest RC6. Their support by hardware varies according to the
47 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
48 * which brings the most power savings; deeper states save more power, but
49 * require higher latency to switch to and wake up.
51 #define INTEL_RC6_ENABLE (1<<0)
52 #define INTEL_RC6p_ENABLE (1<<1)
53 #define INTEL_RC6pp_ENABLE (1<<2)
55 static void gen9_init_clock_gating(struct drm_device
*dev
)
57 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
59 /* WaEnableLbsSlaRetryTimerDecrement:skl */
60 I915_WRITE(BDW_SCRATCH1
, I915_READ(BDW_SCRATCH1
) |
61 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE
);
64 static void skl_init_clock_gating(struct drm_device
*dev
)
66 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
68 gen9_init_clock_gating(dev
);
70 if (INTEL_REVID(dev
) == SKL_REVID_A0
) {
72 * WaDisableSDEUnitClockGating:skl
73 * WaSetGAPSunitClckGateDisable:skl
75 I915_WRITE(GEN8_UCGCTL6
, I915_READ(GEN8_UCGCTL6
) |
76 GEN8_GAPSUNIT_CLOCK_GATE_DISABLE
|
77 GEN8_SDEUNIT_CLOCK_GATE_DISABLE
);
80 if (INTEL_REVID(dev
) <= SKL_REVID_D0
) {
81 /* WaDisableHDCInvalidation:skl */
82 I915_WRITE(GAM_ECOCHK
, I915_READ(GAM_ECOCHK
) |
83 BDW_DISABLE_HDC_INVALIDATION
);
85 /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
86 I915_WRITE(FF_SLICE_CS_CHICKEN2
,
87 I915_READ(FF_SLICE_CS_CHICKEN2
) |
88 GEN9_TSG_BARRIER_ACK_DISABLE
);
91 if (INTEL_REVID(dev
) <= SKL_REVID_E0
)
92 /* WaDisableLSQCROPERFforOCL:skl */
93 I915_WRITE(GEN8_L3SQCREG4
, I915_READ(GEN8_L3SQCREG4
) |
94 GEN8_LQSC_RO_PERF_DIS
);
97 static void i915_pineview_get_mem_freq(struct drm_device
*dev
)
99 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
102 tmp
= I915_READ(CLKCFG
);
104 switch (tmp
& CLKCFG_FSB_MASK
) {
106 dev_priv
->fsb_freq
= 533; /* 133*4 */
109 dev_priv
->fsb_freq
= 800; /* 200*4 */
112 dev_priv
->fsb_freq
= 667; /* 167*4 */
115 dev_priv
->fsb_freq
= 400; /* 100*4 */
119 switch (tmp
& CLKCFG_MEM_MASK
) {
121 dev_priv
->mem_freq
= 533;
124 dev_priv
->mem_freq
= 667;
127 dev_priv
->mem_freq
= 800;
131 /* detect pineview DDR3 setting */
132 tmp
= I915_READ(CSHRDDR3CTL
);
133 dev_priv
->is_ddr3
= (tmp
& CSHRDDR3CTL_DDR3
) ? 1 : 0;
136 static void i915_ironlake_get_mem_freq(struct drm_device
*dev
)
138 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
141 ddrpll
= I915_READ16(DDRMPLL1
);
142 csipll
= I915_READ16(CSIPLL0
);
144 switch (ddrpll
& 0xff) {
146 dev_priv
->mem_freq
= 800;
149 dev_priv
->mem_freq
= 1066;
152 dev_priv
->mem_freq
= 1333;
155 dev_priv
->mem_freq
= 1600;
158 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
160 dev_priv
->mem_freq
= 0;
164 dev_priv
->ips
.r_t
= dev_priv
->mem_freq
;
166 switch (csipll
& 0x3ff) {
168 dev_priv
->fsb_freq
= 3200;
171 dev_priv
->fsb_freq
= 3733;
174 dev_priv
->fsb_freq
= 4266;
177 dev_priv
->fsb_freq
= 4800;
180 dev_priv
->fsb_freq
= 5333;
183 dev_priv
->fsb_freq
= 5866;
186 dev_priv
->fsb_freq
= 6400;
189 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
191 dev_priv
->fsb_freq
= 0;
195 if (dev_priv
->fsb_freq
== 3200) {
196 dev_priv
->ips
.c_m
= 0;
197 } else if (dev_priv
->fsb_freq
> 3200 && dev_priv
->fsb_freq
<= 4800) {
198 dev_priv
->ips
.c_m
= 1;
200 dev_priv
->ips
.c_m
= 2;
204 static const struct cxsr_latency cxsr_latency_table
[] = {
205 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
206 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
207 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
208 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
209 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
211 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
212 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
213 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
214 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
215 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
217 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
218 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
219 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
220 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
221 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
223 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
224 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
225 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
226 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
227 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
229 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
230 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
231 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
232 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
233 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
235 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
236 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
237 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
238 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
239 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
242 static const struct cxsr_latency
*intel_get_cxsr_latency(int is_desktop
,
247 const struct cxsr_latency
*latency
;
250 if (fsb
== 0 || mem
== 0)
253 for (i
= 0; i
< ARRAY_SIZE(cxsr_latency_table
); i
++) {
254 latency
= &cxsr_latency_table
[i
];
255 if (is_desktop
== latency
->is_desktop
&&
256 is_ddr3
== latency
->is_ddr3
&&
257 fsb
== latency
->fsb_freq
&& mem
== latency
->mem_freq
)
261 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
266 void intel_set_memory_cxsr(struct drm_i915_private
*dev_priv
, bool enable
)
268 struct drm_device
*dev
= dev_priv
->dev
;
271 if (IS_VALLEYVIEW(dev
)) {
272 I915_WRITE(FW_BLC_SELF_VLV
, enable
? FW_CSPWRDWNEN
: 0);
273 } else if (IS_G4X(dev
) || IS_CRESTLINE(dev
)) {
274 I915_WRITE(FW_BLC_SELF
, enable
? FW_BLC_SELF_EN
: 0);
275 } else if (IS_PINEVIEW(dev
)) {
276 val
= I915_READ(DSPFW3
) & ~PINEVIEW_SELF_REFRESH_EN
;
277 val
|= enable
? PINEVIEW_SELF_REFRESH_EN
: 0;
278 I915_WRITE(DSPFW3
, val
);
279 } else if (IS_I945G(dev
) || IS_I945GM(dev
)) {
280 val
= enable
? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN
) :
281 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN
);
282 I915_WRITE(FW_BLC_SELF
, val
);
283 } else if (IS_I915GM(dev
)) {
284 val
= enable
? _MASKED_BIT_ENABLE(INSTPM_SELF_EN
) :
285 _MASKED_BIT_DISABLE(INSTPM_SELF_EN
);
286 I915_WRITE(INSTPM
, val
);
291 DRM_DEBUG_KMS("memory self-refresh is %s\n",
292 enable
? "enabled" : "disabled");
296 * Latency for FIFO fetches is dependent on several factors:
297 * - memory configuration (speed, channels)
299 * - current MCH state
300 * It can be fairly high in some situations, so here we assume a fairly
301 * pessimal value. It's a tradeoff between extra memory fetches (if we
302 * set this value too high, the FIFO will fetch frequently to stay full)
303 * and power consumption (set it too low to save power and we might see
304 * FIFO underruns and display "flicker").
306 * A value of 5us seems to be a good balance; safe for very low end
307 * platforms but not overly aggressive on lower latency configs.
309 static const int pessimal_latency_ns
= 5000;
311 static int i9xx_get_fifo_size(struct drm_device
*dev
, int plane
)
313 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
314 uint32_t dsparb
= I915_READ(DSPARB
);
317 size
= dsparb
& 0x7f;
319 size
= ((dsparb
>> DSPARB_CSTART_SHIFT
) & 0x7f) - size
;
321 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
322 plane
? "B" : "A", size
);
327 static int i830_get_fifo_size(struct drm_device
*dev
, int plane
)
329 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
330 uint32_t dsparb
= I915_READ(DSPARB
);
333 size
= dsparb
& 0x1ff;
335 size
= ((dsparb
>> DSPARB_BEND_SHIFT
) & 0x1ff) - size
;
336 size
>>= 1; /* Convert to cachelines */
338 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
339 plane
? "B" : "A", size
);
344 static int i845_get_fifo_size(struct drm_device
*dev
, int plane
)
346 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
347 uint32_t dsparb
= I915_READ(DSPARB
);
350 size
= dsparb
& 0x7f;
351 size
>>= 2; /* Convert to cachelines */
353 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
360 /* Pineview has different values for various configs */
361 static const struct intel_watermark_params pineview_display_wm
= {
362 .fifo_size
= PINEVIEW_DISPLAY_FIFO
,
363 .max_wm
= PINEVIEW_MAX_WM
,
364 .default_wm
= PINEVIEW_DFT_WM
,
365 .guard_size
= PINEVIEW_GUARD_WM
,
366 .cacheline_size
= PINEVIEW_FIFO_LINE_SIZE
,
368 static const struct intel_watermark_params pineview_display_hplloff_wm
= {
369 .fifo_size
= PINEVIEW_DISPLAY_FIFO
,
370 .max_wm
= PINEVIEW_MAX_WM
,
371 .default_wm
= PINEVIEW_DFT_HPLLOFF_WM
,
372 .guard_size
= PINEVIEW_GUARD_WM
,
373 .cacheline_size
= PINEVIEW_FIFO_LINE_SIZE
,
375 static const struct intel_watermark_params pineview_cursor_wm
= {
376 .fifo_size
= PINEVIEW_CURSOR_FIFO
,
377 .max_wm
= PINEVIEW_CURSOR_MAX_WM
,
378 .default_wm
= PINEVIEW_CURSOR_DFT_WM
,
379 .guard_size
= PINEVIEW_CURSOR_GUARD_WM
,
380 .cacheline_size
= PINEVIEW_FIFO_LINE_SIZE
,
382 static const struct intel_watermark_params pineview_cursor_hplloff_wm
= {
383 .fifo_size
= PINEVIEW_CURSOR_FIFO
,
384 .max_wm
= PINEVIEW_CURSOR_MAX_WM
,
385 .default_wm
= PINEVIEW_CURSOR_DFT_WM
,
386 .guard_size
= PINEVIEW_CURSOR_GUARD_WM
,
387 .cacheline_size
= PINEVIEW_FIFO_LINE_SIZE
,
389 static const struct intel_watermark_params g4x_wm_info
= {
390 .fifo_size
= G4X_FIFO_SIZE
,
391 .max_wm
= G4X_MAX_WM
,
392 .default_wm
= G4X_MAX_WM
,
394 .cacheline_size
= G4X_FIFO_LINE_SIZE
,
396 static const struct intel_watermark_params g4x_cursor_wm_info
= {
397 .fifo_size
= I965_CURSOR_FIFO
,
398 .max_wm
= I965_CURSOR_MAX_WM
,
399 .default_wm
= I965_CURSOR_DFT_WM
,
401 .cacheline_size
= G4X_FIFO_LINE_SIZE
,
403 static const struct intel_watermark_params valleyview_wm_info
= {
404 .fifo_size
= VALLEYVIEW_FIFO_SIZE
,
405 .max_wm
= VALLEYVIEW_MAX_WM
,
406 .default_wm
= VALLEYVIEW_MAX_WM
,
408 .cacheline_size
= G4X_FIFO_LINE_SIZE
,
410 static const struct intel_watermark_params valleyview_cursor_wm_info
= {
411 .fifo_size
= I965_CURSOR_FIFO
,
412 .max_wm
= VALLEYVIEW_CURSOR_MAX_WM
,
413 .default_wm
= I965_CURSOR_DFT_WM
,
415 .cacheline_size
= G4X_FIFO_LINE_SIZE
,
417 static const struct intel_watermark_params i965_cursor_wm_info
= {
418 .fifo_size
= I965_CURSOR_FIFO
,
419 .max_wm
= I965_CURSOR_MAX_WM
,
420 .default_wm
= I965_CURSOR_DFT_WM
,
422 .cacheline_size
= I915_FIFO_LINE_SIZE
,
424 static const struct intel_watermark_params i945_wm_info
= {
425 .fifo_size
= I945_FIFO_SIZE
,
426 .max_wm
= I915_MAX_WM
,
429 .cacheline_size
= I915_FIFO_LINE_SIZE
,
431 static const struct intel_watermark_params i915_wm_info
= {
432 .fifo_size
= I915_FIFO_SIZE
,
433 .max_wm
= I915_MAX_WM
,
436 .cacheline_size
= I915_FIFO_LINE_SIZE
,
438 static const struct intel_watermark_params i830_a_wm_info
= {
439 .fifo_size
= I855GM_FIFO_SIZE
,
440 .max_wm
= I915_MAX_WM
,
443 .cacheline_size
= I830_FIFO_LINE_SIZE
,
445 static const struct intel_watermark_params i830_bc_wm_info
= {
446 .fifo_size
= I855GM_FIFO_SIZE
,
447 .max_wm
= I915_MAX_WM
/2,
450 .cacheline_size
= I830_FIFO_LINE_SIZE
,
452 static const struct intel_watermark_params i845_wm_info
= {
453 .fifo_size
= I830_FIFO_SIZE
,
454 .max_wm
= I915_MAX_WM
,
457 .cacheline_size
= I830_FIFO_LINE_SIZE
,
461 * intel_calculate_wm - calculate watermark level
462 * @clock_in_khz: pixel clock
463 * @wm: chip FIFO params
464 * @pixel_size: display pixel size
465 * @latency_ns: memory latency for the platform
467 * Calculate the watermark level (the level at which the display plane will
468 * start fetching from memory again). Each chip has a different display
469 * FIFO size and allocation, so the caller needs to figure that out and pass
470 * in the correct intel_watermark_params structure.
472 * As the pixel clock runs, the FIFO will be drained at a rate that depends
473 * on the pixel size. When it reaches the watermark level, it'll start
474 * fetching FIFO line sized based chunks from memory until the FIFO fills
475 * past the watermark point. If the FIFO drains completely, a FIFO underrun
476 * will occur, and a display engine hang could result.
478 static unsigned long intel_calculate_wm(unsigned long clock_in_khz
,
479 const struct intel_watermark_params
*wm
,
482 unsigned long latency_ns
)
484 long entries_required
, wm_size
;
487 * Note: we need to make sure we don't overflow for various clock &
489 * clocks go from a few thousand to several hundred thousand.
490 * latency is usually a few thousand
492 entries_required
= ((clock_in_khz
/ 1000) * pixel_size
* latency_ns
) /
494 entries_required
= DIV_ROUND_UP(entries_required
, wm
->cacheline_size
);
496 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required
);
498 wm_size
= fifo_size
- (entries_required
+ wm
->guard_size
);
500 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size
);
502 /* Don't promote wm_size to unsigned... */
503 if (wm_size
> (long)wm
->max_wm
)
504 wm_size
= wm
->max_wm
;
506 wm_size
= wm
->default_wm
;
509 * Bspec seems to indicate that the value shouldn't be lower than
510 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
511 * Lets go for 8 which is the burst size since certain platforms
512 * already use a hardcoded 8 (which is what the spec says should be
521 static struct drm_crtc
*single_enabled_crtc(struct drm_device
*dev
)
523 struct drm_crtc
*crtc
, *enabled
= NULL
;
525 for_each_crtc(dev
, crtc
) {
526 if (intel_crtc_active(crtc
)) {
536 static void pineview_update_wm(struct drm_crtc
*unused_crtc
)
538 struct drm_device
*dev
= unused_crtc
->dev
;
539 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
540 struct drm_crtc
*crtc
;
541 const struct cxsr_latency
*latency
;
545 latency
= intel_get_cxsr_latency(IS_PINEVIEW_G(dev
), dev_priv
->is_ddr3
,
546 dev_priv
->fsb_freq
, dev_priv
->mem_freq
);
548 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
549 intel_set_memory_cxsr(dev_priv
, false);
553 crtc
= single_enabled_crtc(dev
);
555 const struct drm_display_mode
*adjusted_mode
;
556 int pixel_size
= crtc
->primary
->state
->fb
->bits_per_pixel
/ 8;
559 adjusted_mode
= &to_intel_crtc(crtc
)->config
->base
.adjusted_mode
;
560 clock
= adjusted_mode
->crtc_clock
;
563 wm
= intel_calculate_wm(clock
, &pineview_display_wm
,
564 pineview_display_wm
.fifo_size
,
565 pixel_size
, latency
->display_sr
);
566 reg
= I915_READ(DSPFW1
);
567 reg
&= ~DSPFW_SR_MASK
;
568 reg
|= wm
<< DSPFW_SR_SHIFT
;
569 I915_WRITE(DSPFW1
, reg
);
570 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg
);
573 wm
= intel_calculate_wm(clock
, &pineview_cursor_wm
,
574 pineview_display_wm
.fifo_size
,
575 pixel_size
, latency
->cursor_sr
);
576 reg
= I915_READ(DSPFW3
);
577 reg
&= ~DSPFW_CURSOR_SR_MASK
;
578 reg
|= (wm
& 0x3f) << DSPFW_CURSOR_SR_SHIFT
;
579 I915_WRITE(DSPFW3
, reg
);
581 /* Display HPLL off SR */
582 wm
= intel_calculate_wm(clock
, &pineview_display_hplloff_wm
,
583 pineview_display_hplloff_wm
.fifo_size
,
584 pixel_size
, latency
->display_hpll_disable
);
585 reg
= I915_READ(DSPFW3
);
586 reg
&= ~DSPFW_HPLL_SR_MASK
;
587 reg
|= wm
& DSPFW_HPLL_SR_MASK
;
588 I915_WRITE(DSPFW3
, reg
);
590 /* cursor HPLL off SR */
591 wm
= intel_calculate_wm(clock
, &pineview_cursor_hplloff_wm
,
592 pineview_display_hplloff_wm
.fifo_size
,
593 pixel_size
, latency
->cursor_hpll_disable
);
594 reg
= I915_READ(DSPFW3
);
595 reg
&= ~DSPFW_HPLL_CURSOR_MASK
;
596 reg
|= (wm
& 0x3f) << DSPFW_HPLL_CURSOR_SHIFT
;
597 I915_WRITE(DSPFW3
, reg
);
598 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg
);
600 intel_set_memory_cxsr(dev_priv
, true);
602 intel_set_memory_cxsr(dev_priv
, false);
606 static bool g4x_compute_wm0(struct drm_device
*dev
,
608 const struct intel_watermark_params
*display
,
609 int display_latency_ns
,
610 const struct intel_watermark_params
*cursor
,
611 int cursor_latency_ns
,
615 struct drm_crtc
*crtc
;
616 const struct drm_display_mode
*adjusted_mode
;
617 int htotal
, hdisplay
, clock
, pixel_size
;
618 int line_time_us
, line_count
;
619 int entries
, tlb_miss
;
621 crtc
= intel_get_crtc_for_plane(dev
, plane
);
622 if (!intel_crtc_active(crtc
)) {
623 *cursor_wm
= cursor
->guard_size
;
624 *plane_wm
= display
->guard_size
;
628 adjusted_mode
= &to_intel_crtc(crtc
)->config
->base
.adjusted_mode
;
629 clock
= adjusted_mode
->crtc_clock
;
630 htotal
= adjusted_mode
->crtc_htotal
;
631 hdisplay
= to_intel_crtc(crtc
)->config
->pipe_src_w
;
632 pixel_size
= crtc
->primary
->state
->fb
->bits_per_pixel
/ 8;
634 /* Use the small buffer method to calculate plane watermark */
635 entries
= ((clock
* pixel_size
/ 1000) * display_latency_ns
) / 1000;
636 tlb_miss
= display
->fifo_size
*display
->cacheline_size
- hdisplay
* 8;
639 entries
= DIV_ROUND_UP(entries
, display
->cacheline_size
);
640 *plane_wm
= entries
+ display
->guard_size
;
641 if (*plane_wm
> (int)display
->max_wm
)
642 *plane_wm
= display
->max_wm
;
644 /* Use the large buffer method to calculate cursor watermark */
645 line_time_us
= max(htotal
* 1000 / clock
, 1);
646 line_count
= (cursor_latency_ns
/ line_time_us
+ 1000) / 1000;
647 entries
= line_count
* crtc
->cursor
->state
->crtc_w
* pixel_size
;
648 tlb_miss
= cursor
->fifo_size
*cursor
->cacheline_size
- hdisplay
* 8;
651 entries
= DIV_ROUND_UP(entries
, cursor
->cacheline_size
);
652 *cursor_wm
= entries
+ cursor
->guard_size
;
653 if (*cursor_wm
> (int)cursor
->max_wm
)
654 *cursor_wm
= (int)cursor
->max_wm
;
660 * Check the wm result.
662 * If any calculated watermark values is larger than the maximum value that
663 * can be programmed into the associated watermark register, that watermark
666 static bool g4x_check_srwm(struct drm_device
*dev
,
667 int display_wm
, int cursor_wm
,
668 const struct intel_watermark_params
*display
,
669 const struct intel_watermark_params
*cursor
)
671 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
672 display_wm
, cursor_wm
);
674 if (display_wm
> display
->max_wm
) {
675 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
676 display_wm
, display
->max_wm
);
680 if (cursor_wm
> cursor
->max_wm
) {
681 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
682 cursor_wm
, cursor
->max_wm
);
686 if (!(display_wm
|| cursor_wm
)) {
687 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
694 static bool g4x_compute_srwm(struct drm_device
*dev
,
697 const struct intel_watermark_params
*display
,
698 const struct intel_watermark_params
*cursor
,
699 int *display_wm
, int *cursor_wm
)
701 struct drm_crtc
*crtc
;
702 const struct drm_display_mode
*adjusted_mode
;
703 int hdisplay
, htotal
, pixel_size
, clock
;
704 unsigned long line_time_us
;
705 int line_count
, line_size
;
710 *display_wm
= *cursor_wm
= 0;
714 crtc
= intel_get_crtc_for_plane(dev
, plane
);
715 adjusted_mode
= &to_intel_crtc(crtc
)->config
->base
.adjusted_mode
;
716 clock
= adjusted_mode
->crtc_clock
;
717 htotal
= adjusted_mode
->crtc_htotal
;
718 hdisplay
= to_intel_crtc(crtc
)->config
->pipe_src_w
;
719 pixel_size
= crtc
->primary
->state
->fb
->bits_per_pixel
/ 8;
721 line_time_us
= max(htotal
* 1000 / clock
, 1);
722 line_count
= (latency_ns
/ line_time_us
+ 1000) / 1000;
723 line_size
= hdisplay
* pixel_size
;
725 /* Use the minimum of the small and large buffer method for primary */
726 small
= ((clock
* pixel_size
/ 1000) * latency_ns
) / 1000;
727 large
= line_count
* line_size
;
729 entries
= DIV_ROUND_UP(min(small
, large
), display
->cacheline_size
);
730 *display_wm
= entries
+ display
->guard_size
;
732 /* calculate the self-refresh watermark for display cursor */
733 entries
= line_count
* pixel_size
* crtc
->cursor
->state
->crtc_w
;
734 entries
= DIV_ROUND_UP(entries
, cursor
->cacheline_size
);
735 *cursor_wm
= entries
+ cursor
->guard_size
;
737 return g4x_check_srwm(dev
,
738 *display_wm
, *cursor_wm
,
742 static uint8_t vlv_compute_drain_latency(struct drm_crtc
*crtc
,
745 struct drm_device
*dev
= crtc
->dev
;
746 int entries
, prec_mult
, drain_latency
;
747 int clock
= to_intel_crtc(crtc
)->config
->base
.adjusted_mode
.crtc_clock
;
748 const int high_precision
= IS_CHERRYVIEW(dev
) ? 16 : 64;
750 if (WARN(clock
== 0, "Pixel clock is zero!\n"))
753 if (WARN(pixel_size
== 0, "Pixel size is zero!\n"))
756 entries
= DIV_ROUND_UP(clock
, 1000) * pixel_size
;
758 prec_mult
= high_precision
;
759 drain_latency
= 64 * prec_mult
* 4 / entries
;
761 if (drain_latency
> DRAIN_LATENCY_MASK
) {
763 drain_latency
= 64 * prec_mult
* 4 / entries
;
766 if (drain_latency
> DRAIN_LATENCY_MASK
)
767 drain_latency
= DRAIN_LATENCY_MASK
;
769 return drain_latency
| (prec_mult
== high_precision
?
770 DDL_PRECISION_HIGH
: DDL_PRECISION_LOW
);
774 * Update drain latency registers of memory arbiter
776 * Valleyview SoC has a new memory arbiter and needs drain latency registers
777 * to be programmed. Each plane has a drain latency multiplier and a drain
781 static void vlv_update_drain_latency(struct drm_crtc
*crtc
)
783 struct drm_device
*dev
= crtc
->dev
;
784 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
785 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
787 enum pipe pipe
= intel_crtc
->pipe
;
790 plane_dl
= I915_READ(VLV_DDL(pipe
)) &
791 ~(((DDL_PRECISION_HIGH
| DRAIN_LATENCY_MASK
) << DDL_CURSOR_SHIFT
) |
792 ((DDL_PRECISION_HIGH
| DRAIN_LATENCY_MASK
) << DDL_PLANE_SHIFT
));
794 if (!intel_crtc_active(crtc
)) {
795 I915_WRITE(VLV_DDL(pipe
), plane_dl
);
799 /* Primary plane Drain Latency */
800 pixel_size
= crtc
->primary
->state
->fb
->bits_per_pixel
/ 8; /* BPP */
801 plane_dl
= vlv_compute_drain_latency(crtc
, pixel_size
) << DDL_PLANE_SHIFT
;
803 /* Cursor Drain Latency
804 * BPP is always 4 for cursor
808 /* Program cursor DL only if it is enabled */
809 if (intel_crtc
->cursor_base
)
810 plane_dl
|= vlv_compute_drain_latency(crtc
, pixel_size
) << DDL_CURSOR_SHIFT
;
812 I915_WRITE(VLV_DDL(pipe
), plane_dl
);
815 #define single_plane_enabled(mask) is_power_of_2(mask)
817 static void valleyview_update_wm(struct drm_crtc
*crtc
)
819 struct drm_device
*dev
= crtc
->dev
;
820 static const int sr_latency_ns
= 12000;
821 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
822 int planea_wm
, planeb_wm
, cursora_wm
, cursorb_wm
;
823 int plane_sr
, cursor_sr
;
824 int ignore_plane_sr
, ignore_cursor_sr
;
825 unsigned int enabled
= 0;
828 vlv_update_drain_latency(crtc
);
830 if (g4x_compute_wm0(dev
, PIPE_A
,
831 &valleyview_wm_info
, pessimal_latency_ns
,
832 &valleyview_cursor_wm_info
, pessimal_latency_ns
,
833 &planea_wm
, &cursora_wm
))
834 enabled
|= 1 << PIPE_A
;
836 if (g4x_compute_wm0(dev
, PIPE_B
,
837 &valleyview_wm_info
, pessimal_latency_ns
,
838 &valleyview_cursor_wm_info
, pessimal_latency_ns
,
839 &planeb_wm
, &cursorb_wm
))
840 enabled
|= 1 << PIPE_B
;
842 if (single_plane_enabled(enabled
) &&
843 g4x_compute_srwm(dev
, ffs(enabled
) - 1,
846 &valleyview_cursor_wm_info
,
847 &plane_sr
, &ignore_cursor_sr
) &&
848 g4x_compute_srwm(dev
, ffs(enabled
) - 1,
851 &valleyview_cursor_wm_info
,
852 &ignore_plane_sr
, &cursor_sr
)) {
855 cxsr_enabled
= false;
856 intel_set_memory_cxsr(dev_priv
, false);
857 plane_sr
= cursor_sr
= 0;
860 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
861 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
862 planea_wm
, cursora_wm
,
863 planeb_wm
, cursorb_wm
,
864 plane_sr
, cursor_sr
);
867 (plane_sr
<< DSPFW_SR_SHIFT
) |
868 (cursorb_wm
<< DSPFW_CURSORB_SHIFT
) |
869 (planeb_wm
<< DSPFW_PLANEB_SHIFT
) |
870 (planea_wm
<< DSPFW_PLANEA_SHIFT
));
872 (I915_READ(DSPFW2
) & ~DSPFW_CURSORA_MASK
) |
873 (cursora_wm
<< DSPFW_CURSORA_SHIFT
));
875 (I915_READ(DSPFW3
) & ~DSPFW_CURSOR_SR_MASK
) |
876 (cursor_sr
<< DSPFW_CURSOR_SR_SHIFT
));
879 intel_set_memory_cxsr(dev_priv
, true);
882 static void cherryview_update_wm(struct drm_crtc
*crtc
)
884 struct drm_device
*dev
= crtc
->dev
;
885 static const int sr_latency_ns
= 12000;
886 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
887 int planea_wm
, planeb_wm
, planec_wm
;
888 int cursora_wm
, cursorb_wm
, cursorc_wm
;
889 int plane_sr
, cursor_sr
;
890 int ignore_plane_sr
, ignore_cursor_sr
;
891 unsigned int enabled
= 0;
894 vlv_update_drain_latency(crtc
);
896 if (g4x_compute_wm0(dev
, PIPE_A
,
897 &valleyview_wm_info
, pessimal_latency_ns
,
898 &valleyview_cursor_wm_info
, pessimal_latency_ns
,
899 &planea_wm
, &cursora_wm
))
900 enabled
|= 1 << PIPE_A
;
902 if (g4x_compute_wm0(dev
, PIPE_B
,
903 &valleyview_wm_info
, pessimal_latency_ns
,
904 &valleyview_cursor_wm_info
, pessimal_latency_ns
,
905 &planeb_wm
, &cursorb_wm
))
906 enabled
|= 1 << PIPE_B
;
908 if (g4x_compute_wm0(dev
, PIPE_C
,
909 &valleyview_wm_info
, pessimal_latency_ns
,
910 &valleyview_cursor_wm_info
, pessimal_latency_ns
,
911 &planec_wm
, &cursorc_wm
))
912 enabled
|= 1 << PIPE_C
;
914 if (single_plane_enabled(enabled
) &&
915 g4x_compute_srwm(dev
, ffs(enabled
) - 1,
918 &valleyview_cursor_wm_info
,
919 &plane_sr
, &ignore_cursor_sr
) &&
920 g4x_compute_srwm(dev
, ffs(enabled
) - 1,
923 &valleyview_cursor_wm_info
,
924 &ignore_plane_sr
, &cursor_sr
)) {
927 cxsr_enabled
= false;
928 intel_set_memory_cxsr(dev_priv
, false);
929 plane_sr
= cursor_sr
= 0;
932 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
933 "B: plane=%d, cursor=%d, C: plane=%d, cursor=%d, "
934 "SR: plane=%d, cursor=%d\n",
935 planea_wm
, cursora_wm
,
936 planeb_wm
, cursorb_wm
,
937 planec_wm
, cursorc_wm
,
938 plane_sr
, cursor_sr
);
941 (plane_sr
<< DSPFW_SR_SHIFT
) |
942 (cursorb_wm
<< DSPFW_CURSORB_SHIFT
) |
943 (planeb_wm
<< DSPFW_PLANEB_SHIFT
) |
944 (planea_wm
<< DSPFW_PLANEA_SHIFT
));
946 (I915_READ(DSPFW2
) & ~DSPFW_CURSORA_MASK
) |
947 (cursora_wm
<< DSPFW_CURSORA_SHIFT
));
949 (I915_READ(DSPFW3
) & ~DSPFW_CURSOR_SR_MASK
) |
950 (cursor_sr
<< DSPFW_CURSOR_SR_SHIFT
));
951 I915_WRITE(DSPFW9_CHV
,
952 (I915_READ(DSPFW9_CHV
) & ~(DSPFW_PLANEC_MASK
|
953 DSPFW_CURSORC_MASK
)) |
954 (planec_wm
<< DSPFW_PLANEC_SHIFT
) |
955 (cursorc_wm
<< DSPFW_CURSORC_SHIFT
));
958 intel_set_memory_cxsr(dev_priv
, true);
961 static void valleyview_update_sprite_wm(struct drm_plane
*plane
,
962 struct drm_crtc
*crtc
,
963 uint32_t sprite_width
,
964 uint32_t sprite_height
,
966 bool enabled
, bool scaled
)
968 struct drm_device
*dev
= crtc
->dev
;
969 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
970 int pipe
= to_intel_plane(plane
)->pipe
;
971 int sprite
= to_intel_plane(plane
)->plane
;
974 sprite_dl
= I915_READ(VLV_DDL(pipe
)) &
975 ~((DDL_PRECISION_HIGH
| DRAIN_LATENCY_MASK
) << DDL_SPRITE_SHIFT(sprite
));
978 sprite_dl
|= vlv_compute_drain_latency(crtc
, pixel_size
) << DDL_SPRITE_SHIFT(sprite
);
980 I915_WRITE(VLV_DDL(pipe
), sprite_dl
);
983 static void g4x_update_wm(struct drm_crtc
*crtc
)
985 struct drm_device
*dev
= crtc
->dev
;
986 static const int sr_latency_ns
= 12000;
987 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
988 int planea_wm
, planeb_wm
, cursora_wm
, cursorb_wm
;
989 int plane_sr
, cursor_sr
;
990 unsigned int enabled
= 0;
993 if (g4x_compute_wm0(dev
, PIPE_A
,
994 &g4x_wm_info
, pessimal_latency_ns
,
995 &g4x_cursor_wm_info
, pessimal_latency_ns
,
996 &planea_wm
, &cursora_wm
))
997 enabled
|= 1 << PIPE_A
;
999 if (g4x_compute_wm0(dev
, PIPE_B
,
1000 &g4x_wm_info
, pessimal_latency_ns
,
1001 &g4x_cursor_wm_info
, pessimal_latency_ns
,
1002 &planeb_wm
, &cursorb_wm
))
1003 enabled
|= 1 << PIPE_B
;
1005 if (single_plane_enabled(enabled
) &&
1006 g4x_compute_srwm(dev
, ffs(enabled
) - 1,
1009 &g4x_cursor_wm_info
,
1010 &plane_sr
, &cursor_sr
)) {
1011 cxsr_enabled
= true;
1013 cxsr_enabled
= false;
1014 intel_set_memory_cxsr(dev_priv
, false);
1015 plane_sr
= cursor_sr
= 0;
1018 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1019 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1020 planea_wm
, cursora_wm
,
1021 planeb_wm
, cursorb_wm
,
1022 plane_sr
, cursor_sr
);
1025 (plane_sr
<< DSPFW_SR_SHIFT
) |
1026 (cursorb_wm
<< DSPFW_CURSORB_SHIFT
) |
1027 (planeb_wm
<< DSPFW_PLANEB_SHIFT
) |
1028 (planea_wm
<< DSPFW_PLANEA_SHIFT
));
1030 (I915_READ(DSPFW2
) & ~DSPFW_CURSORA_MASK
) |
1031 (cursora_wm
<< DSPFW_CURSORA_SHIFT
));
1032 /* HPLL off in SR has some issues on G4x... disable it */
1034 (I915_READ(DSPFW3
) & ~(DSPFW_HPLL_SR_EN
| DSPFW_CURSOR_SR_MASK
)) |
1035 (cursor_sr
<< DSPFW_CURSOR_SR_SHIFT
));
1038 intel_set_memory_cxsr(dev_priv
, true);
1041 static void i965_update_wm(struct drm_crtc
*unused_crtc
)
1043 struct drm_device
*dev
= unused_crtc
->dev
;
1044 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1045 struct drm_crtc
*crtc
;
1050 /* Calc sr entries for one plane configs */
1051 crtc
= single_enabled_crtc(dev
);
1053 /* self-refresh has much higher latency */
1054 static const int sr_latency_ns
= 12000;
1055 const struct drm_display_mode
*adjusted_mode
=
1056 &to_intel_crtc(crtc
)->config
->base
.adjusted_mode
;
1057 int clock
= adjusted_mode
->crtc_clock
;
1058 int htotal
= adjusted_mode
->crtc_htotal
;
1059 int hdisplay
= to_intel_crtc(crtc
)->config
->pipe_src_w
;
1060 int pixel_size
= crtc
->primary
->state
->fb
->bits_per_pixel
/ 8;
1061 unsigned long line_time_us
;
1064 line_time_us
= max(htotal
* 1000 / clock
, 1);
1066 /* Use ns/us then divide to preserve precision */
1067 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
1068 pixel_size
* hdisplay
;
1069 entries
= DIV_ROUND_UP(entries
, I915_FIFO_LINE_SIZE
);
1070 srwm
= I965_FIFO_SIZE
- entries
;
1074 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1077 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
1078 pixel_size
* crtc
->cursor
->state
->crtc_w
;
1079 entries
= DIV_ROUND_UP(entries
,
1080 i965_cursor_wm_info
.cacheline_size
);
1081 cursor_sr
= i965_cursor_wm_info
.fifo_size
-
1082 (entries
+ i965_cursor_wm_info
.guard_size
);
1084 if (cursor_sr
> i965_cursor_wm_info
.max_wm
)
1085 cursor_sr
= i965_cursor_wm_info
.max_wm
;
1087 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1088 "cursor %d\n", srwm
, cursor_sr
);
1090 cxsr_enabled
= true;
1092 cxsr_enabled
= false;
1093 /* Turn off self refresh if both pipes are enabled */
1094 intel_set_memory_cxsr(dev_priv
, false);
1097 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1100 /* 965 has limitations... */
1101 I915_WRITE(DSPFW1
, (srwm
<< DSPFW_SR_SHIFT
) |
1102 (8 << DSPFW_CURSORB_SHIFT
) |
1103 (8 << DSPFW_PLANEB_SHIFT
) |
1104 (8 << DSPFW_PLANEA_SHIFT
));
1105 I915_WRITE(DSPFW2
, (8 << DSPFW_CURSORA_SHIFT
) |
1106 (8 << DSPFW_PLANEC_SHIFT_OLD
));
1107 /* update cursor SR watermark */
1108 I915_WRITE(DSPFW3
, (cursor_sr
<< DSPFW_CURSOR_SR_SHIFT
));
1111 intel_set_memory_cxsr(dev_priv
, true);
1114 static void i9xx_update_wm(struct drm_crtc
*unused_crtc
)
1116 struct drm_device
*dev
= unused_crtc
->dev
;
1117 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1118 const struct intel_watermark_params
*wm_info
;
1123 int planea_wm
, planeb_wm
;
1124 struct drm_crtc
*crtc
, *enabled
= NULL
;
1127 wm_info
= &i945_wm_info
;
1128 else if (!IS_GEN2(dev
))
1129 wm_info
= &i915_wm_info
;
1131 wm_info
= &i830_a_wm_info
;
1133 fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 0);
1134 crtc
= intel_get_crtc_for_plane(dev
, 0);
1135 if (intel_crtc_active(crtc
)) {
1136 const struct drm_display_mode
*adjusted_mode
;
1137 int cpp
= crtc
->primary
->state
->fb
->bits_per_pixel
/ 8;
1141 adjusted_mode
= &to_intel_crtc(crtc
)->config
->base
.adjusted_mode
;
1142 planea_wm
= intel_calculate_wm(adjusted_mode
->crtc_clock
,
1143 wm_info
, fifo_size
, cpp
,
1144 pessimal_latency_ns
);
1147 planea_wm
= fifo_size
- wm_info
->guard_size
;
1148 if (planea_wm
> (long)wm_info
->max_wm
)
1149 planea_wm
= wm_info
->max_wm
;
1153 wm_info
= &i830_bc_wm_info
;
1155 fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 1);
1156 crtc
= intel_get_crtc_for_plane(dev
, 1);
1157 if (intel_crtc_active(crtc
)) {
1158 const struct drm_display_mode
*adjusted_mode
;
1159 int cpp
= crtc
->primary
->state
->fb
->bits_per_pixel
/ 8;
1163 adjusted_mode
= &to_intel_crtc(crtc
)->config
->base
.adjusted_mode
;
1164 planeb_wm
= intel_calculate_wm(adjusted_mode
->crtc_clock
,
1165 wm_info
, fifo_size
, cpp
,
1166 pessimal_latency_ns
);
1167 if (enabled
== NULL
)
1172 planeb_wm
= fifo_size
- wm_info
->guard_size
;
1173 if (planeb_wm
> (long)wm_info
->max_wm
)
1174 planeb_wm
= wm_info
->max_wm
;
1177 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm
, planeb_wm
);
1179 if (IS_I915GM(dev
) && enabled
) {
1180 struct drm_i915_gem_object
*obj
;
1182 obj
= intel_fb_obj(enabled
->primary
->state
->fb
);
1184 /* self-refresh seems busted with untiled */
1185 if (obj
->tiling_mode
== I915_TILING_NONE
)
1190 * Overlay gets an aggressive default since video jitter is bad.
1194 /* Play safe and disable self-refresh before adjusting watermarks. */
1195 intel_set_memory_cxsr(dev_priv
, false);
1197 /* Calc sr entries for one plane configs */
1198 if (HAS_FW_BLC(dev
) && enabled
) {
1199 /* self-refresh has much higher latency */
1200 static const int sr_latency_ns
= 6000;
1201 const struct drm_display_mode
*adjusted_mode
=
1202 &to_intel_crtc(enabled
)->config
->base
.adjusted_mode
;
1203 int clock
= adjusted_mode
->crtc_clock
;
1204 int htotal
= adjusted_mode
->crtc_htotal
;
1205 int hdisplay
= to_intel_crtc(enabled
)->config
->pipe_src_w
;
1206 int pixel_size
= enabled
->primary
->state
->fb
->bits_per_pixel
/ 8;
1207 unsigned long line_time_us
;
1210 line_time_us
= max(htotal
* 1000 / clock
, 1);
1212 /* Use ns/us then divide to preserve precision */
1213 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
1214 pixel_size
* hdisplay
;
1215 entries
= DIV_ROUND_UP(entries
, wm_info
->cacheline_size
);
1216 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries
);
1217 srwm
= wm_info
->fifo_size
- entries
;
1221 if (IS_I945G(dev
) || IS_I945GM(dev
))
1222 I915_WRITE(FW_BLC_SELF
,
1223 FW_BLC_SELF_FIFO_MASK
| (srwm
& 0xff));
1224 else if (IS_I915GM(dev
))
1225 I915_WRITE(FW_BLC_SELF
, srwm
& 0x3f);
1228 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1229 planea_wm
, planeb_wm
, cwm
, srwm
);
1231 fwater_lo
= ((planeb_wm
& 0x3f) << 16) | (planea_wm
& 0x3f);
1232 fwater_hi
= (cwm
& 0x1f);
1234 /* Set request length to 8 cachelines per fetch */
1235 fwater_lo
= fwater_lo
| (1 << 24) | (1 << 8);
1236 fwater_hi
= fwater_hi
| (1 << 8);
1238 I915_WRITE(FW_BLC
, fwater_lo
);
1239 I915_WRITE(FW_BLC2
, fwater_hi
);
1242 intel_set_memory_cxsr(dev_priv
, true);
1245 static void i845_update_wm(struct drm_crtc
*unused_crtc
)
1247 struct drm_device
*dev
= unused_crtc
->dev
;
1248 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1249 struct drm_crtc
*crtc
;
1250 const struct drm_display_mode
*adjusted_mode
;
1254 crtc
= single_enabled_crtc(dev
);
1258 adjusted_mode
= &to_intel_crtc(crtc
)->config
->base
.adjusted_mode
;
1259 planea_wm
= intel_calculate_wm(adjusted_mode
->crtc_clock
,
1261 dev_priv
->display
.get_fifo_size(dev
, 0),
1262 4, pessimal_latency_ns
);
1263 fwater_lo
= I915_READ(FW_BLC
) & ~0xfff;
1264 fwater_lo
|= (3<<8) | planea_wm
;
1266 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm
);
1268 I915_WRITE(FW_BLC
, fwater_lo
);
1271 static uint32_t ilk_pipe_pixel_rate(struct drm_device
*dev
,
1272 struct drm_crtc
*crtc
)
1274 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1275 uint32_t pixel_rate
;
1277 pixel_rate
= intel_crtc
->config
->base
.adjusted_mode
.crtc_clock
;
1279 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1280 * adjust the pixel_rate here. */
1282 if (intel_crtc
->config
->pch_pfit
.enabled
) {
1283 uint64_t pipe_w
, pipe_h
, pfit_w
, pfit_h
;
1284 uint32_t pfit_size
= intel_crtc
->config
->pch_pfit
.size
;
1286 pipe_w
= intel_crtc
->config
->pipe_src_w
;
1287 pipe_h
= intel_crtc
->config
->pipe_src_h
;
1288 pfit_w
= (pfit_size
>> 16) & 0xFFFF;
1289 pfit_h
= pfit_size
& 0xFFFF;
1290 if (pipe_w
< pfit_w
)
1292 if (pipe_h
< pfit_h
)
1295 pixel_rate
= div_u64((uint64_t) pixel_rate
* pipe_w
* pipe_h
,
1302 /* latency must be in 0.1us units. */
1303 static uint32_t ilk_wm_method1(uint32_t pixel_rate
, uint8_t bytes_per_pixel
,
1308 if (WARN(latency
== 0, "Latency value missing\n"))
1311 ret
= (uint64_t) pixel_rate
* bytes_per_pixel
* latency
;
1312 ret
= DIV_ROUND_UP_ULL(ret
, 64 * 10000) + 2;
1317 /* latency must be in 0.1us units. */
1318 static uint32_t ilk_wm_method2(uint32_t pixel_rate
, uint32_t pipe_htotal
,
1319 uint32_t horiz_pixels
, uint8_t bytes_per_pixel
,
1324 if (WARN(latency
== 0, "Latency value missing\n"))
1327 ret
= (latency
* pixel_rate
) / (pipe_htotal
* 10000);
1328 ret
= (ret
+ 1) * horiz_pixels
* bytes_per_pixel
;
1329 ret
= DIV_ROUND_UP(ret
, 64) + 2;
1333 static uint32_t ilk_wm_fbc(uint32_t pri_val
, uint32_t horiz_pixels
,
1334 uint8_t bytes_per_pixel
)
1336 return DIV_ROUND_UP(pri_val
* 64, horiz_pixels
* bytes_per_pixel
) + 2;
1339 struct skl_pipe_wm_parameters
{
1341 uint32_t pipe_htotal
;
1342 uint32_t pixel_rate
; /* in KHz */
1343 struct intel_plane_wm_parameters plane
[I915_MAX_PLANES
];
1344 struct intel_plane_wm_parameters cursor
;
1347 struct ilk_pipe_wm_parameters
{
1349 uint32_t pipe_htotal
;
1350 uint32_t pixel_rate
;
1351 struct intel_plane_wm_parameters pri
;
1352 struct intel_plane_wm_parameters spr
;
1353 struct intel_plane_wm_parameters cur
;
1356 struct ilk_wm_maximums
{
1363 /* used in computing the new watermarks state */
1364 struct intel_wm_config
{
1365 unsigned int num_pipes_active
;
1366 bool sprites_enabled
;
1367 bool sprites_scaled
;
1371 * For both WM_PIPE and WM_LP.
1372 * mem_value must be in 0.1us units.
1374 static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters
*params
,
1378 uint32_t method1
, method2
;
1380 if (!params
->active
|| !params
->pri
.enabled
)
1383 method1
= ilk_wm_method1(params
->pixel_rate
,
1384 params
->pri
.bytes_per_pixel
,
1390 method2
= ilk_wm_method2(params
->pixel_rate
,
1391 params
->pipe_htotal
,
1392 params
->pri
.horiz_pixels
,
1393 params
->pri
.bytes_per_pixel
,
1396 return min(method1
, method2
);
1400 * For both WM_PIPE and WM_LP.
1401 * mem_value must be in 0.1us units.
1403 static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters
*params
,
1406 uint32_t method1
, method2
;
1408 if (!params
->active
|| !params
->spr
.enabled
)
1411 method1
= ilk_wm_method1(params
->pixel_rate
,
1412 params
->spr
.bytes_per_pixel
,
1414 method2
= ilk_wm_method2(params
->pixel_rate
,
1415 params
->pipe_htotal
,
1416 params
->spr
.horiz_pixels
,
1417 params
->spr
.bytes_per_pixel
,
1419 return min(method1
, method2
);
1423 * For both WM_PIPE and WM_LP.
1424 * mem_value must be in 0.1us units.
1426 static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters
*params
,
1429 if (!params
->active
|| !params
->cur
.enabled
)
1432 return ilk_wm_method2(params
->pixel_rate
,
1433 params
->pipe_htotal
,
1434 params
->cur
.horiz_pixels
,
1435 params
->cur
.bytes_per_pixel
,
1439 /* Only for WM_LP. */
1440 static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters
*params
,
1443 if (!params
->active
|| !params
->pri
.enabled
)
1446 return ilk_wm_fbc(pri_val
,
1447 params
->pri
.horiz_pixels
,
1448 params
->pri
.bytes_per_pixel
);
1451 static unsigned int ilk_display_fifo_size(const struct drm_device
*dev
)
1453 if (INTEL_INFO(dev
)->gen
>= 8)
1455 else if (INTEL_INFO(dev
)->gen
>= 7)
1461 static unsigned int ilk_plane_wm_reg_max(const struct drm_device
*dev
,
1462 int level
, bool is_sprite
)
1464 if (INTEL_INFO(dev
)->gen
>= 8)
1465 /* BDW primary/sprite plane watermarks */
1466 return level
== 0 ? 255 : 2047;
1467 else if (INTEL_INFO(dev
)->gen
>= 7)
1468 /* IVB/HSW primary/sprite plane watermarks */
1469 return level
== 0 ? 127 : 1023;
1470 else if (!is_sprite
)
1471 /* ILK/SNB primary plane watermarks */
1472 return level
== 0 ? 127 : 511;
1474 /* ILK/SNB sprite plane watermarks */
1475 return level
== 0 ? 63 : 255;
1478 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device
*dev
,
1481 if (INTEL_INFO(dev
)->gen
>= 7)
1482 return level
== 0 ? 63 : 255;
1484 return level
== 0 ? 31 : 63;
1487 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device
*dev
)
1489 if (INTEL_INFO(dev
)->gen
>= 8)
1495 /* Calculate the maximum primary/sprite plane watermark */
1496 static unsigned int ilk_plane_wm_max(const struct drm_device
*dev
,
1498 const struct intel_wm_config
*config
,
1499 enum intel_ddb_partitioning ddb_partitioning
,
1502 unsigned int fifo_size
= ilk_display_fifo_size(dev
);
1504 /* if sprites aren't enabled, sprites get nothing */
1505 if (is_sprite
&& !config
->sprites_enabled
)
1508 /* HSW allows LP1+ watermarks even with multiple pipes */
1509 if (level
== 0 || config
->num_pipes_active
> 1) {
1510 fifo_size
/= INTEL_INFO(dev
)->num_pipes
;
1513 * For some reason the non self refresh
1514 * FIFO size is only half of the self
1515 * refresh FIFO size on ILK/SNB.
1517 if (INTEL_INFO(dev
)->gen
<= 6)
1521 if (config
->sprites_enabled
) {
1522 /* level 0 is always calculated with 1:1 split */
1523 if (level
> 0 && ddb_partitioning
== INTEL_DDB_PART_5_6
) {
1532 /* clamp to max that the registers can hold */
1533 return min(fifo_size
, ilk_plane_wm_reg_max(dev
, level
, is_sprite
));
1536 /* Calculate the maximum cursor plane watermark */
1537 static unsigned int ilk_cursor_wm_max(const struct drm_device
*dev
,
1539 const struct intel_wm_config
*config
)
1541 /* HSW LP1+ watermarks w/ multiple pipes */
1542 if (level
> 0 && config
->num_pipes_active
> 1)
1545 /* otherwise just report max that registers can hold */
1546 return ilk_cursor_wm_reg_max(dev
, level
);
1549 static void ilk_compute_wm_maximums(const struct drm_device
*dev
,
1551 const struct intel_wm_config
*config
,
1552 enum intel_ddb_partitioning ddb_partitioning
,
1553 struct ilk_wm_maximums
*max
)
1555 max
->pri
= ilk_plane_wm_max(dev
, level
, config
, ddb_partitioning
, false);
1556 max
->spr
= ilk_plane_wm_max(dev
, level
, config
, ddb_partitioning
, true);
1557 max
->cur
= ilk_cursor_wm_max(dev
, level
, config
);
1558 max
->fbc
= ilk_fbc_wm_reg_max(dev
);
1561 static void ilk_compute_wm_reg_maximums(struct drm_device
*dev
,
1563 struct ilk_wm_maximums
*max
)
1565 max
->pri
= ilk_plane_wm_reg_max(dev
, level
, false);
1566 max
->spr
= ilk_plane_wm_reg_max(dev
, level
, true);
1567 max
->cur
= ilk_cursor_wm_reg_max(dev
, level
);
1568 max
->fbc
= ilk_fbc_wm_reg_max(dev
);
1571 static bool ilk_validate_wm_level(int level
,
1572 const struct ilk_wm_maximums
*max
,
1573 struct intel_wm_level
*result
)
1577 /* already determined to be invalid? */
1578 if (!result
->enable
)
1581 result
->enable
= result
->pri_val
<= max
->pri
&&
1582 result
->spr_val
<= max
->spr
&&
1583 result
->cur_val
<= max
->cur
;
1585 ret
= result
->enable
;
1588 * HACK until we can pre-compute everything,
1589 * and thus fail gracefully if LP0 watermarks
1592 if (level
== 0 && !result
->enable
) {
1593 if (result
->pri_val
> max
->pri
)
1594 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1595 level
, result
->pri_val
, max
->pri
);
1596 if (result
->spr_val
> max
->spr
)
1597 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1598 level
, result
->spr_val
, max
->spr
);
1599 if (result
->cur_val
> max
->cur
)
1600 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1601 level
, result
->cur_val
, max
->cur
);
1603 result
->pri_val
= min_t(uint32_t, result
->pri_val
, max
->pri
);
1604 result
->spr_val
= min_t(uint32_t, result
->spr_val
, max
->spr
);
1605 result
->cur_val
= min_t(uint32_t, result
->cur_val
, max
->cur
);
1606 result
->enable
= true;
1612 static void ilk_compute_wm_level(const struct drm_i915_private
*dev_priv
,
1614 const struct ilk_pipe_wm_parameters
*p
,
1615 struct intel_wm_level
*result
)
1617 uint16_t pri_latency
= dev_priv
->wm
.pri_latency
[level
];
1618 uint16_t spr_latency
= dev_priv
->wm
.spr_latency
[level
];
1619 uint16_t cur_latency
= dev_priv
->wm
.cur_latency
[level
];
1621 /* WM1+ latency values stored in 0.5us units */
1628 result
->pri_val
= ilk_compute_pri_wm(p
, pri_latency
, level
);
1629 result
->spr_val
= ilk_compute_spr_wm(p
, spr_latency
);
1630 result
->cur_val
= ilk_compute_cur_wm(p
, cur_latency
);
1631 result
->fbc_val
= ilk_compute_fbc_wm(p
, result
->pri_val
);
1632 result
->enable
= true;
1636 hsw_compute_linetime_wm(struct drm_device
*dev
, struct drm_crtc
*crtc
)
1638 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1639 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1640 struct drm_display_mode
*mode
= &intel_crtc
->config
->base
.adjusted_mode
;
1641 u32 linetime
, ips_linetime
;
1643 if (!intel_crtc_active(crtc
))
1646 /* The WM are computed with base on how long it takes to fill a single
1647 * row at the given clock rate, multiplied by 8.
1649 linetime
= DIV_ROUND_CLOSEST(mode
->crtc_htotal
* 1000 * 8,
1651 ips_linetime
= DIV_ROUND_CLOSEST(mode
->crtc_htotal
* 1000 * 8,
1652 intel_ddi_get_cdclk_freq(dev_priv
));
1654 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime
) |
1655 PIPE_WM_LINETIME_TIME(linetime
);
1658 static void intel_read_wm_latency(struct drm_device
*dev
, uint16_t wm
[8])
1660 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1665 int level
, max_level
= ilk_wm_max_level(dev
);
1667 /* read the first set of memory latencies[0:3] */
1668 val
= 0; /* data0 to be programmed to 0 for first set */
1669 mutex_lock(&dev_priv
->rps
.hw_lock
);
1670 ret
= sandybridge_pcode_read(dev_priv
,
1671 GEN9_PCODE_READ_MEM_LATENCY
,
1673 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1676 DRM_ERROR("SKL Mailbox read error = %d\n", ret
);
1680 wm
[0] = val
& GEN9_MEM_LATENCY_LEVEL_MASK
;
1681 wm
[1] = (val
>> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT
) &
1682 GEN9_MEM_LATENCY_LEVEL_MASK
;
1683 wm
[2] = (val
>> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT
) &
1684 GEN9_MEM_LATENCY_LEVEL_MASK
;
1685 wm
[3] = (val
>> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT
) &
1686 GEN9_MEM_LATENCY_LEVEL_MASK
;
1688 /* read the second set of memory latencies[4:7] */
1689 val
= 1; /* data0 to be programmed to 1 for second set */
1690 mutex_lock(&dev_priv
->rps
.hw_lock
);
1691 ret
= sandybridge_pcode_read(dev_priv
,
1692 GEN9_PCODE_READ_MEM_LATENCY
,
1694 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1696 DRM_ERROR("SKL Mailbox read error = %d\n", ret
);
1700 wm
[4] = val
& GEN9_MEM_LATENCY_LEVEL_MASK
;
1701 wm
[5] = (val
>> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT
) &
1702 GEN9_MEM_LATENCY_LEVEL_MASK
;
1703 wm
[6] = (val
>> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT
) &
1704 GEN9_MEM_LATENCY_LEVEL_MASK
;
1705 wm
[7] = (val
>> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT
) &
1706 GEN9_MEM_LATENCY_LEVEL_MASK
;
1709 * WaWmMemoryReadLatency:skl
1711 * punit doesn't take into account the read latency so we need
1712 * to add 2us to the various latency levels we retrieve from
1714 * - W0 is a bit special in that it's the only level that
1715 * can't be disabled if we want to have display working, so
1716 * we always add 2us there.
1717 * - For levels >=1, punit returns 0us latency when they are
1718 * disabled, so we respect that and don't add 2us then
1720 * Additionally, if a level n (n > 1) has a 0us latency, all
1721 * levels m (m >= n) need to be disabled. We make sure to
1722 * sanitize the values out of the punit to satisfy this
1726 for (level
= 1; level
<= max_level
; level
++)
1730 for (i
= level
+ 1; i
<= max_level
; i
++)
1735 } else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
1736 uint64_t sskpd
= I915_READ64(MCH_SSKPD
);
1738 wm
[0] = (sskpd
>> 56) & 0xFF;
1740 wm
[0] = sskpd
& 0xF;
1741 wm
[1] = (sskpd
>> 4) & 0xFF;
1742 wm
[2] = (sskpd
>> 12) & 0xFF;
1743 wm
[3] = (sskpd
>> 20) & 0x1FF;
1744 wm
[4] = (sskpd
>> 32) & 0x1FF;
1745 } else if (INTEL_INFO(dev
)->gen
>= 6) {
1746 uint32_t sskpd
= I915_READ(MCH_SSKPD
);
1748 wm
[0] = (sskpd
>> SSKPD_WM0_SHIFT
) & SSKPD_WM_MASK
;
1749 wm
[1] = (sskpd
>> SSKPD_WM1_SHIFT
) & SSKPD_WM_MASK
;
1750 wm
[2] = (sskpd
>> SSKPD_WM2_SHIFT
) & SSKPD_WM_MASK
;
1751 wm
[3] = (sskpd
>> SSKPD_WM3_SHIFT
) & SSKPD_WM_MASK
;
1752 } else if (INTEL_INFO(dev
)->gen
>= 5) {
1753 uint32_t mltr
= I915_READ(MLTR_ILK
);
1755 /* ILK primary LP0 latency is 700 ns */
1757 wm
[1] = (mltr
>> MLTR_WM1_SHIFT
) & ILK_SRLT_MASK
;
1758 wm
[2] = (mltr
>> MLTR_WM2_SHIFT
) & ILK_SRLT_MASK
;
1762 static void intel_fixup_spr_wm_latency(struct drm_device
*dev
, uint16_t wm
[5])
1764 /* ILK sprite LP0 latency is 1300 ns */
1765 if (INTEL_INFO(dev
)->gen
== 5)
1769 static void intel_fixup_cur_wm_latency(struct drm_device
*dev
, uint16_t wm
[5])
1771 /* ILK cursor LP0 latency is 1300 ns */
1772 if (INTEL_INFO(dev
)->gen
== 5)
1775 /* WaDoubleCursorLP3Latency:ivb */
1776 if (IS_IVYBRIDGE(dev
))
1780 int ilk_wm_max_level(const struct drm_device
*dev
)
1782 /* how many WM levels are we expecting */
1785 else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
1787 else if (INTEL_INFO(dev
)->gen
>= 6)
1793 static void intel_print_wm_latency(struct drm_device
*dev
,
1795 const uint16_t wm
[8])
1797 int level
, max_level
= ilk_wm_max_level(dev
);
1799 for (level
= 0; level
<= max_level
; level
++) {
1800 unsigned int latency
= wm
[level
];
1803 DRM_ERROR("%s WM%d latency not provided\n",
1809 * - latencies are in us on gen9.
1810 * - before then, WM1+ latency values are in 0.5us units
1817 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
1818 name
, level
, wm
[level
],
1819 latency
/ 10, latency
% 10);
1823 static bool ilk_increase_wm_latency(struct drm_i915_private
*dev_priv
,
1824 uint16_t wm
[5], uint16_t min
)
1826 int level
, max_level
= ilk_wm_max_level(dev_priv
->dev
);
1831 wm
[0] = max(wm
[0], min
);
1832 for (level
= 1; level
<= max_level
; level
++)
1833 wm
[level
] = max_t(uint16_t, wm
[level
], DIV_ROUND_UP(min
, 5));
1838 static void snb_wm_latency_quirk(struct drm_device
*dev
)
1840 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1844 * The BIOS provided WM memory latency values are often
1845 * inadequate for high resolution displays. Adjust them.
1847 changed
= ilk_increase_wm_latency(dev_priv
, dev_priv
->wm
.pri_latency
, 12) |
1848 ilk_increase_wm_latency(dev_priv
, dev_priv
->wm
.spr_latency
, 12) |
1849 ilk_increase_wm_latency(dev_priv
, dev_priv
->wm
.cur_latency
, 12);
1854 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
1855 intel_print_wm_latency(dev
, "Primary", dev_priv
->wm
.pri_latency
);
1856 intel_print_wm_latency(dev
, "Sprite", dev_priv
->wm
.spr_latency
);
1857 intel_print_wm_latency(dev
, "Cursor", dev_priv
->wm
.cur_latency
);
1860 static void ilk_setup_wm_latency(struct drm_device
*dev
)
1862 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1864 intel_read_wm_latency(dev
, dev_priv
->wm
.pri_latency
);
1866 memcpy(dev_priv
->wm
.spr_latency
, dev_priv
->wm
.pri_latency
,
1867 sizeof(dev_priv
->wm
.pri_latency
));
1868 memcpy(dev_priv
->wm
.cur_latency
, dev_priv
->wm
.pri_latency
,
1869 sizeof(dev_priv
->wm
.pri_latency
));
1871 intel_fixup_spr_wm_latency(dev
, dev_priv
->wm
.spr_latency
);
1872 intel_fixup_cur_wm_latency(dev
, dev_priv
->wm
.cur_latency
);
1874 intel_print_wm_latency(dev
, "Primary", dev_priv
->wm
.pri_latency
);
1875 intel_print_wm_latency(dev
, "Sprite", dev_priv
->wm
.spr_latency
);
1876 intel_print_wm_latency(dev
, "Cursor", dev_priv
->wm
.cur_latency
);
1879 snb_wm_latency_quirk(dev
);
1882 static void skl_setup_wm_latency(struct drm_device
*dev
)
1884 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1886 intel_read_wm_latency(dev
, dev_priv
->wm
.skl_latency
);
1887 intel_print_wm_latency(dev
, "Gen9 Plane", dev_priv
->wm
.skl_latency
);
1890 static void ilk_compute_wm_parameters(struct drm_crtc
*crtc
,
1891 struct ilk_pipe_wm_parameters
*p
)
1893 struct drm_device
*dev
= crtc
->dev
;
1894 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1895 enum pipe pipe
= intel_crtc
->pipe
;
1896 struct drm_plane
*plane
;
1898 if (!intel_crtc_active(crtc
))
1902 p
->pipe_htotal
= intel_crtc
->config
->base
.adjusted_mode
.crtc_htotal
;
1903 p
->pixel_rate
= ilk_pipe_pixel_rate(dev
, crtc
);
1904 p
->pri
.bytes_per_pixel
= crtc
->primary
->state
->fb
->bits_per_pixel
/ 8;
1905 p
->cur
.bytes_per_pixel
= 4;
1906 p
->pri
.horiz_pixels
= intel_crtc
->config
->pipe_src_w
;
1907 p
->cur
.horiz_pixels
= intel_crtc
->base
.cursor
->state
->crtc_w
;
1908 /* TODO: for now, assume primary and cursor planes are always enabled. */
1909 p
->pri
.enabled
= true;
1910 p
->cur
.enabled
= true;
1912 drm_for_each_legacy_plane(plane
, &dev
->mode_config
.plane_list
) {
1913 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
1915 if (intel_plane
->pipe
== pipe
) {
1916 p
->spr
= intel_plane
->wm
;
1922 static void ilk_compute_wm_config(struct drm_device
*dev
,
1923 struct intel_wm_config
*config
)
1925 struct intel_crtc
*intel_crtc
;
1927 /* Compute the currently _active_ config */
1928 for_each_intel_crtc(dev
, intel_crtc
) {
1929 const struct intel_pipe_wm
*wm
= &intel_crtc
->wm
.active
;
1931 if (!wm
->pipe_enabled
)
1934 config
->sprites_enabled
|= wm
->sprites_enabled
;
1935 config
->sprites_scaled
|= wm
->sprites_scaled
;
1936 config
->num_pipes_active
++;
1940 /* Compute new watermarks for the pipe */
1941 static bool intel_compute_pipe_wm(struct drm_crtc
*crtc
,
1942 const struct ilk_pipe_wm_parameters
*params
,
1943 struct intel_pipe_wm
*pipe_wm
)
1945 struct drm_device
*dev
= crtc
->dev
;
1946 const struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1947 int level
, max_level
= ilk_wm_max_level(dev
);
1948 /* LP0 watermark maximums depend on this pipe alone */
1949 struct intel_wm_config config
= {
1950 .num_pipes_active
= 1,
1951 .sprites_enabled
= params
->spr
.enabled
,
1952 .sprites_scaled
= params
->spr
.scaled
,
1954 struct ilk_wm_maximums max
;
1956 pipe_wm
->pipe_enabled
= params
->active
;
1957 pipe_wm
->sprites_enabled
= params
->spr
.enabled
;
1958 pipe_wm
->sprites_scaled
= params
->spr
.scaled
;
1960 /* ILK/SNB: LP2+ watermarks only w/o sprites */
1961 if (INTEL_INFO(dev
)->gen
<= 6 && params
->spr
.enabled
)
1964 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
1965 if (params
->spr
.scaled
)
1968 ilk_compute_wm_level(dev_priv
, 0, params
, &pipe_wm
->wm
[0]);
1970 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
1971 pipe_wm
->linetime
= hsw_compute_linetime_wm(dev
, crtc
);
1973 /* LP0 watermarks always use 1/2 DDB partitioning */
1974 ilk_compute_wm_maximums(dev
, 0, &config
, INTEL_DDB_PART_1_2
, &max
);
1976 /* At least LP0 must be valid */
1977 if (!ilk_validate_wm_level(0, &max
, &pipe_wm
->wm
[0]))
1980 ilk_compute_wm_reg_maximums(dev
, 1, &max
);
1982 for (level
= 1; level
<= max_level
; level
++) {
1983 struct intel_wm_level wm
= {};
1985 ilk_compute_wm_level(dev_priv
, level
, params
, &wm
);
1988 * Disable any watermark level that exceeds the
1989 * register maximums since such watermarks are
1992 if (!ilk_validate_wm_level(level
, &max
, &wm
))
1995 pipe_wm
->wm
[level
] = wm
;
2002 * Merge the watermarks from all active pipes for a specific level.
2004 static void ilk_merge_wm_level(struct drm_device
*dev
,
2006 struct intel_wm_level
*ret_wm
)
2008 const struct intel_crtc
*intel_crtc
;
2010 ret_wm
->enable
= true;
2012 for_each_intel_crtc(dev
, intel_crtc
) {
2013 const struct intel_pipe_wm
*active
= &intel_crtc
->wm
.active
;
2014 const struct intel_wm_level
*wm
= &active
->wm
[level
];
2016 if (!active
->pipe_enabled
)
2020 * The watermark values may have been used in the past,
2021 * so we must maintain them in the registers for some
2022 * time even if the level is now disabled.
2025 ret_wm
->enable
= false;
2027 ret_wm
->pri_val
= max(ret_wm
->pri_val
, wm
->pri_val
);
2028 ret_wm
->spr_val
= max(ret_wm
->spr_val
, wm
->spr_val
);
2029 ret_wm
->cur_val
= max(ret_wm
->cur_val
, wm
->cur_val
);
2030 ret_wm
->fbc_val
= max(ret_wm
->fbc_val
, wm
->fbc_val
);
2035 * Merge all low power watermarks for all active pipes.
2037 static void ilk_wm_merge(struct drm_device
*dev
,
2038 const struct intel_wm_config
*config
,
2039 const struct ilk_wm_maximums
*max
,
2040 struct intel_pipe_wm
*merged
)
2042 int level
, max_level
= ilk_wm_max_level(dev
);
2043 int last_enabled_level
= max_level
;
2045 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2046 if ((INTEL_INFO(dev
)->gen
<= 6 || IS_IVYBRIDGE(dev
)) &&
2047 config
->num_pipes_active
> 1)
2050 /* ILK: FBC WM must be disabled always */
2051 merged
->fbc_wm_enabled
= INTEL_INFO(dev
)->gen
>= 6;
2053 /* merge each WM1+ level */
2054 for (level
= 1; level
<= max_level
; level
++) {
2055 struct intel_wm_level
*wm
= &merged
->wm
[level
];
2057 ilk_merge_wm_level(dev
, level
, wm
);
2059 if (level
> last_enabled_level
)
2061 else if (!ilk_validate_wm_level(level
, max
, wm
))
2062 /* make sure all following levels get disabled */
2063 last_enabled_level
= level
- 1;
2066 * The spec says it is preferred to disable
2067 * FBC WMs instead of disabling a WM level.
2069 if (wm
->fbc_val
> max
->fbc
) {
2071 merged
->fbc_wm_enabled
= false;
2076 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2078 * FIXME this is racy. FBC might get enabled later.
2079 * What we should check here is whether FBC can be
2080 * enabled sometime later.
2082 if (IS_GEN5(dev
) && !merged
->fbc_wm_enabled
&& intel_fbc_enabled(dev
)) {
2083 for (level
= 2; level
<= max_level
; level
++) {
2084 struct intel_wm_level
*wm
= &merged
->wm
[level
];
2091 static int ilk_wm_lp_to_level(int wm_lp
, const struct intel_pipe_wm
*pipe_wm
)
2093 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2094 return wm_lp
+ (wm_lp
>= 2 && pipe_wm
->wm
[4].enable
);
2097 /* The value we need to program into the WM_LPx latency field */
2098 static unsigned int ilk_wm_lp_latency(struct drm_device
*dev
, int level
)
2100 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2102 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2105 return dev_priv
->wm
.pri_latency
[level
];
2108 static void ilk_compute_wm_results(struct drm_device
*dev
,
2109 const struct intel_pipe_wm
*merged
,
2110 enum intel_ddb_partitioning partitioning
,
2111 struct ilk_wm_values
*results
)
2113 struct intel_crtc
*intel_crtc
;
2116 results
->enable_fbc_wm
= merged
->fbc_wm_enabled
;
2117 results
->partitioning
= partitioning
;
2119 /* LP1+ register values */
2120 for (wm_lp
= 1; wm_lp
<= 3; wm_lp
++) {
2121 const struct intel_wm_level
*r
;
2123 level
= ilk_wm_lp_to_level(wm_lp
, merged
);
2125 r
= &merged
->wm
[level
];
2128 * Maintain the watermark values even if the level is
2129 * disabled. Doing otherwise could cause underruns.
2131 results
->wm_lp
[wm_lp
- 1] =
2132 (ilk_wm_lp_latency(dev
, level
) << WM1_LP_LATENCY_SHIFT
) |
2133 (r
->pri_val
<< WM1_LP_SR_SHIFT
) |
2137 results
->wm_lp
[wm_lp
- 1] |= WM1_LP_SR_EN
;
2139 if (INTEL_INFO(dev
)->gen
>= 8)
2140 results
->wm_lp
[wm_lp
- 1] |=
2141 r
->fbc_val
<< WM1_LP_FBC_SHIFT_BDW
;
2143 results
->wm_lp
[wm_lp
- 1] |=
2144 r
->fbc_val
<< WM1_LP_FBC_SHIFT
;
2147 * Always set WM1S_LP_EN when spr_val != 0, even if the
2148 * level is disabled. Doing otherwise could cause underruns.
2150 if (INTEL_INFO(dev
)->gen
<= 6 && r
->spr_val
) {
2151 WARN_ON(wm_lp
!= 1);
2152 results
->wm_lp_spr
[wm_lp
- 1] = WM1S_LP_EN
| r
->spr_val
;
2154 results
->wm_lp_spr
[wm_lp
- 1] = r
->spr_val
;
2157 /* LP0 register values */
2158 for_each_intel_crtc(dev
, intel_crtc
) {
2159 enum pipe pipe
= intel_crtc
->pipe
;
2160 const struct intel_wm_level
*r
=
2161 &intel_crtc
->wm
.active
.wm
[0];
2163 if (WARN_ON(!r
->enable
))
2166 results
->wm_linetime
[pipe
] = intel_crtc
->wm
.active
.linetime
;
2168 results
->wm_pipe
[pipe
] =
2169 (r
->pri_val
<< WM0_PIPE_PLANE_SHIFT
) |
2170 (r
->spr_val
<< WM0_PIPE_SPRITE_SHIFT
) |
2175 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2176 * case both are at the same level. Prefer r1 in case they're the same. */
2177 static struct intel_pipe_wm
*ilk_find_best_result(struct drm_device
*dev
,
2178 struct intel_pipe_wm
*r1
,
2179 struct intel_pipe_wm
*r2
)
2181 int level
, max_level
= ilk_wm_max_level(dev
);
2182 int level1
= 0, level2
= 0;
2184 for (level
= 1; level
<= max_level
; level
++) {
2185 if (r1
->wm
[level
].enable
)
2187 if (r2
->wm
[level
].enable
)
2191 if (level1
== level2
) {
2192 if (r2
->fbc_wm_enabled
&& !r1
->fbc_wm_enabled
)
2196 } else if (level1
> level2
) {
2203 /* dirty bits used to track which watermarks need changes */
2204 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2205 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2206 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2207 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2208 #define WM_DIRTY_FBC (1 << 24)
2209 #define WM_DIRTY_DDB (1 << 25)
2211 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private
*dev_priv
,
2212 const struct ilk_wm_values
*old
,
2213 const struct ilk_wm_values
*new)
2215 unsigned int dirty
= 0;
2219 for_each_pipe(dev_priv
, pipe
) {
2220 if (old
->wm_linetime
[pipe
] != new->wm_linetime
[pipe
]) {
2221 dirty
|= WM_DIRTY_LINETIME(pipe
);
2222 /* Must disable LP1+ watermarks too */
2223 dirty
|= WM_DIRTY_LP_ALL
;
2226 if (old
->wm_pipe
[pipe
] != new->wm_pipe
[pipe
]) {
2227 dirty
|= WM_DIRTY_PIPE(pipe
);
2228 /* Must disable LP1+ watermarks too */
2229 dirty
|= WM_DIRTY_LP_ALL
;
2233 if (old
->enable_fbc_wm
!= new->enable_fbc_wm
) {
2234 dirty
|= WM_DIRTY_FBC
;
2235 /* Must disable LP1+ watermarks too */
2236 dirty
|= WM_DIRTY_LP_ALL
;
2239 if (old
->partitioning
!= new->partitioning
) {
2240 dirty
|= WM_DIRTY_DDB
;
2241 /* Must disable LP1+ watermarks too */
2242 dirty
|= WM_DIRTY_LP_ALL
;
2245 /* LP1+ watermarks already deemed dirty, no need to continue */
2246 if (dirty
& WM_DIRTY_LP_ALL
)
2249 /* Find the lowest numbered LP1+ watermark in need of an update... */
2250 for (wm_lp
= 1; wm_lp
<= 3; wm_lp
++) {
2251 if (old
->wm_lp
[wm_lp
- 1] != new->wm_lp
[wm_lp
- 1] ||
2252 old
->wm_lp_spr
[wm_lp
- 1] != new->wm_lp_spr
[wm_lp
- 1])
2256 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2257 for (; wm_lp
<= 3; wm_lp
++)
2258 dirty
|= WM_DIRTY_LP(wm_lp
);
2263 static bool _ilk_disable_lp_wm(struct drm_i915_private
*dev_priv
,
2266 struct ilk_wm_values
*previous
= &dev_priv
->wm
.hw
;
2267 bool changed
= false;
2269 if (dirty
& WM_DIRTY_LP(3) && previous
->wm_lp
[2] & WM1_LP_SR_EN
) {
2270 previous
->wm_lp
[2] &= ~WM1_LP_SR_EN
;
2271 I915_WRITE(WM3_LP_ILK
, previous
->wm_lp
[2]);
2274 if (dirty
& WM_DIRTY_LP(2) && previous
->wm_lp
[1] & WM1_LP_SR_EN
) {
2275 previous
->wm_lp
[1] &= ~WM1_LP_SR_EN
;
2276 I915_WRITE(WM2_LP_ILK
, previous
->wm_lp
[1]);
2279 if (dirty
& WM_DIRTY_LP(1) && previous
->wm_lp
[0] & WM1_LP_SR_EN
) {
2280 previous
->wm_lp
[0] &= ~WM1_LP_SR_EN
;
2281 I915_WRITE(WM1_LP_ILK
, previous
->wm_lp
[0]);
2286 * Don't touch WM1S_LP_EN here.
2287 * Doing so could cause underruns.
2294 * The spec says we shouldn't write when we don't need, because every write
2295 * causes WMs to be re-evaluated, expending some power.
2297 static void ilk_write_wm_values(struct drm_i915_private
*dev_priv
,
2298 struct ilk_wm_values
*results
)
2300 struct drm_device
*dev
= dev_priv
->dev
;
2301 struct ilk_wm_values
*previous
= &dev_priv
->wm
.hw
;
2305 dirty
= ilk_compute_wm_dirty(dev_priv
, previous
, results
);
2309 _ilk_disable_lp_wm(dev_priv
, dirty
);
2311 if (dirty
& WM_DIRTY_PIPE(PIPE_A
))
2312 I915_WRITE(WM0_PIPEA_ILK
, results
->wm_pipe
[0]);
2313 if (dirty
& WM_DIRTY_PIPE(PIPE_B
))
2314 I915_WRITE(WM0_PIPEB_ILK
, results
->wm_pipe
[1]);
2315 if (dirty
& WM_DIRTY_PIPE(PIPE_C
))
2316 I915_WRITE(WM0_PIPEC_IVB
, results
->wm_pipe
[2]);
2318 if (dirty
& WM_DIRTY_LINETIME(PIPE_A
))
2319 I915_WRITE(PIPE_WM_LINETIME(PIPE_A
), results
->wm_linetime
[0]);
2320 if (dirty
& WM_DIRTY_LINETIME(PIPE_B
))
2321 I915_WRITE(PIPE_WM_LINETIME(PIPE_B
), results
->wm_linetime
[1]);
2322 if (dirty
& WM_DIRTY_LINETIME(PIPE_C
))
2323 I915_WRITE(PIPE_WM_LINETIME(PIPE_C
), results
->wm_linetime
[2]);
2325 if (dirty
& WM_DIRTY_DDB
) {
2326 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2327 val
= I915_READ(WM_MISC
);
2328 if (results
->partitioning
== INTEL_DDB_PART_1_2
)
2329 val
&= ~WM_MISC_DATA_PARTITION_5_6
;
2331 val
|= WM_MISC_DATA_PARTITION_5_6
;
2332 I915_WRITE(WM_MISC
, val
);
2334 val
= I915_READ(DISP_ARB_CTL2
);
2335 if (results
->partitioning
== INTEL_DDB_PART_1_2
)
2336 val
&= ~DISP_DATA_PARTITION_5_6
;
2338 val
|= DISP_DATA_PARTITION_5_6
;
2339 I915_WRITE(DISP_ARB_CTL2
, val
);
2343 if (dirty
& WM_DIRTY_FBC
) {
2344 val
= I915_READ(DISP_ARB_CTL
);
2345 if (results
->enable_fbc_wm
)
2346 val
&= ~DISP_FBC_WM_DIS
;
2348 val
|= DISP_FBC_WM_DIS
;
2349 I915_WRITE(DISP_ARB_CTL
, val
);
2352 if (dirty
& WM_DIRTY_LP(1) &&
2353 previous
->wm_lp_spr
[0] != results
->wm_lp_spr
[0])
2354 I915_WRITE(WM1S_LP_ILK
, results
->wm_lp_spr
[0]);
2356 if (INTEL_INFO(dev
)->gen
>= 7) {
2357 if (dirty
& WM_DIRTY_LP(2) && previous
->wm_lp_spr
[1] != results
->wm_lp_spr
[1])
2358 I915_WRITE(WM2S_LP_IVB
, results
->wm_lp_spr
[1]);
2359 if (dirty
& WM_DIRTY_LP(3) && previous
->wm_lp_spr
[2] != results
->wm_lp_spr
[2])
2360 I915_WRITE(WM3S_LP_IVB
, results
->wm_lp_spr
[2]);
2363 if (dirty
& WM_DIRTY_LP(1) && previous
->wm_lp
[0] != results
->wm_lp
[0])
2364 I915_WRITE(WM1_LP_ILK
, results
->wm_lp
[0]);
2365 if (dirty
& WM_DIRTY_LP(2) && previous
->wm_lp
[1] != results
->wm_lp
[1])
2366 I915_WRITE(WM2_LP_ILK
, results
->wm_lp
[1]);
2367 if (dirty
& WM_DIRTY_LP(3) && previous
->wm_lp
[2] != results
->wm_lp
[2])
2368 I915_WRITE(WM3_LP_ILK
, results
->wm_lp
[2]);
2370 dev_priv
->wm
.hw
= *results
;
2373 static bool ilk_disable_lp_wm(struct drm_device
*dev
)
2375 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2377 return _ilk_disable_lp_wm(dev_priv
, WM_DIRTY_LP_ALL
);
2381 * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2382 * different active planes.
2385 #define SKL_DDB_SIZE 896 /* in blocks */
2388 skl_ddb_get_pipe_allocation_limits(struct drm_device
*dev
,
2389 struct drm_crtc
*for_crtc
,
2390 const struct intel_wm_config
*config
,
2391 const struct skl_pipe_wm_parameters
*params
,
2392 struct skl_ddb_entry
*alloc
/* out */)
2394 struct drm_crtc
*crtc
;
2395 unsigned int pipe_size
, ddb_size
;
2396 int nth_active_pipe
;
2398 if (!params
->active
) {
2404 ddb_size
= SKL_DDB_SIZE
;
2406 ddb_size
-= 4; /* 4 blocks for bypass path allocation */
2408 nth_active_pipe
= 0;
2409 for_each_crtc(dev
, crtc
) {
2410 if (!intel_crtc_active(crtc
))
2413 if (crtc
== for_crtc
)
2419 pipe_size
= ddb_size
/ config
->num_pipes_active
;
2420 alloc
->start
= nth_active_pipe
* ddb_size
/ config
->num_pipes_active
;
2421 alloc
->end
= alloc
->start
+ pipe_size
;
2424 static unsigned int skl_cursor_allocation(const struct intel_wm_config
*config
)
2426 if (config
->num_pipes_active
== 1)
2432 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry
*entry
, u32 reg
)
2434 entry
->start
= reg
& 0x3ff;
2435 entry
->end
= (reg
>> 16) & 0x3ff;
2440 void skl_ddb_get_hw_state(struct drm_i915_private
*dev_priv
,
2441 struct skl_ddb_allocation
*ddb
/* out */)
2447 for_each_pipe(dev_priv
, pipe
) {
2448 for_each_plane(dev_priv
, pipe
, plane
) {
2449 val
= I915_READ(PLANE_BUF_CFG(pipe
, plane
));
2450 skl_ddb_entry_init_from_hw(&ddb
->plane
[pipe
][plane
],
2454 val
= I915_READ(CUR_BUF_CFG(pipe
));
2455 skl_ddb_entry_init_from_hw(&ddb
->cursor
[pipe
], val
);
2460 skl_plane_relative_data_rate(const struct intel_plane_wm_parameters
*p
)
2462 return p
->horiz_pixels
* p
->vert_pixels
* p
->bytes_per_pixel
;
2466 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
2467 * a 8192x4096@32bpp framebuffer:
2468 * 3 * 4096 * 8192 * 4 < 2^32
2471 skl_get_total_relative_data_rate(struct intel_crtc
*intel_crtc
,
2472 const struct skl_pipe_wm_parameters
*params
)
2474 unsigned int total_data_rate
= 0;
2477 for (plane
= 0; plane
< intel_num_planes(intel_crtc
); plane
++) {
2478 const struct intel_plane_wm_parameters
*p
;
2480 p
= ¶ms
->plane
[plane
];
2484 total_data_rate
+= skl_plane_relative_data_rate(p
);
2487 return total_data_rate
;
2491 skl_allocate_pipe_ddb(struct drm_crtc
*crtc
,
2492 const struct intel_wm_config
*config
,
2493 const struct skl_pipe_wm_parameters
*params
,
2494 struct skl_ddb_allocation
*ddb
/* out */)
2496 struct drm_device
*dev
= crtc
->dev
;
2497 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2498 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2499 enum pipe pipe
= intel_crtc
->pipe
;
2500 struct skl_ddb_entry
*alloc
= &ddb
->pipe
[pipe
];
2501 uint16_t alloc_size
, start
, cursor_blocks
;
2502 uint16_t minimum
[I915_MAX_PLANES
];
2503 unsigned int total_data_rate
;
2506 skl_ddb_get_pipe_allocation_limits(dev
, crtc
, config
, params
, alloc
);
2507 alloc_size
= skl_ddb_entry_size(alloc
);
2508 if (alloc_size
== 0) {
2509 memset(ddb
->plane
[pipe
], 0, sizeof(ddb
->plane
[pipe
]));
2510 memset(&ddb
->cursor
[pipe
], 0, sizeof(ddb
->cursor
[pipe
]));
2514 cursor_blocks
= skl_cursor_allocation(config
);
2515 ddb
->cursor
[pipe
].start
= alloc
->end
- cursor_blocks
;
2516 ddb
->cursor
[pipe
].end
= alloc
->end
;
2518 alloc_size
-= cursor_blocks
;
2519 alloc
->end
-= cursor_blocks
;
2521 /* 1. Allocate the mininum required blocks for each active plane */
2522 for_each_plane(dev_priv
, pipe
, plane
) {
2523 const struct intel_plane_wm_parameters
*p
;
2525 p
= ¶ms
->plane
[plane
];
2530 alloc_size
-= minimum
[plane
];
2534 * 2. Distribute the remaining space in proportion to the amount of
2535 * data each plane needs to fetch from memory.
2537 * FIXME: we may not allocate every single block here.
2539 total_data_rate
= skl_get_total_relative_data_rate(intel_crtc
, params
);
2541 start
= alloc
->start
;
2542 for (plane
= 0; plane
< intel_num_planes(intel_crtc
); plane
++) {
2543 const struct intel_plane_wm_parameters
*p
;
2544 unsigned int data_rate
;
2545 uint16_t plane_blocks
;
2547 p
= ¶ms
->plane
[plane
];
2551 data_rate
= skl_plane_relative_data_rate(p
);
2554 * promote the expression to 64 bits to avoid overflowing, the
2555 * result is < available as data_rate / total_data_rate < 1
2557 plane_blocks
= minimum
[plane
];
2558 plane_blocks
+= div_u64((uint64_t)alloc_size
* data_rate
,
2561 ddb
->plane
[pipe
][plane
].start
= start
;
2562 ddb
->plane
[pipe
][plane
].end
= start
+ plane_blocks
;
2564 start
+= plane_blocks
;
2569 static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state
*config
)
2571 /* TODO: Take into account the scalers once we support them */
2572 return config
->base
.adjusted_mode
.crtc_clock
;
2576 * The max latency should be 257 (max the punit can code is 255 and we add 2us
2577 * for the read latency) and bytes_per_pixel should always be <= 8, so that
2578 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
2579 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
2581 static uint32_t skl_wm_method1(uint32_t pixel_rate
, uint8_t bytes_per_pixel
,
2584 uint32_t wm_intermediate_val
, ret
;
2589 wm_intermediate_val
= latency
* pixel_rate
* bytes_per_pixel
/ 512;
2590 ret
= DIV_ROUND_UP(wm_intermediate_val
, 1000);
2595 static uint32_t skl_wm_method2(uint32_t pixel_rate
, uint32_t pipe_htotal
,
2596 uint32_t horiz_pixels
, uint8_t bytes_per_pixel
,
2597 uint64_t tiling
, uint32_t latency
)
2600 uint32_t plane_bytes_per_line
, plane_blocks_per_line
;
2601 uint32_t wm_intermediate_val
;
2606 plane_bytes_per_line
= horiz_pixels
* bytes_per_pixel
;
2608 if (tiling
== I915_FORMAT_MOD_Y_TILED
||
2609 tiling
== I915_FORMAT_MOD_Yf_TILED
) {
2610 plane_bytes_per_line
*= 4;
2611 plane_blocks_per_line
= DIV_ROUND_UP(plane_bytes_per_line
, 512);
2612 plane_blocks_per_line
/= 4;
2614 plane_blocks_per_line
= DIV_ROUND_UP(plane_bytes_per_line
, 512);
2617 wm_intermediate_val
= latency
* pixel_rate
;
2618 ret
= DIV_ROUND_UP(wm_intermediate_val
, pipe_htotal
* 1000) *
2619 plane_blocks_per_line
;
2624 static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation
*new_ddb
,
2625 const struct intel_crtc
*intel_crtc
)
2627 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2628 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2629 const struct skl_ddb_allocation
*cur_ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
2630 enum pipe pipe
= intel_crtc
->pipe
;
2632 if (memcmp(new_ddb
->plane
[pipe
], cur_ddb
->plane
[pipe
],
2633 sizeof(new_ddb
->plane
[pipe
])))
2636 if (memcmp(&new_ddb
->cursor
[pipe
], &cur_ddb
->cursor
[pipe
],
2637 sizeof(new_ddb
->cursor
[pipe
])))
2643 static void skl_compute_wm_global_parameters(struct drm_device
*dev
,
2644 struct intel_wm_config
*config
)
2646 struct drm_crtc
*crtc
;
2647 struct drm_plane
*plane
;
2649 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
)
2650 config
->num_pipes_active
+= intel_crtc_active(crtc
);
2652 /* FIXME: I don't think we need those two global parameters on SKL */
2653 list_for_each_entry(plane
, &dev
->mode_config
.plane_list
, head
) {
2654 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
2656 config
->sprites_enabled
|= intel_plane
->wm
.enabled
;
2657 config
->sprites_scaled
|= intel_plane
->wm
.scaled
;
2661 static void skl_compute_wm_pipe_parameters(struct drm_crtc
*crtc
,
2662 struct skl_pipe_wm_parameters
*p
)
2664 struct drm_device
*dev
= crtc
->dev
;
2665 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2666 enum pipe pipe
= intel_crtc
->pipe
;
2667 struct drm_plane
*plane
;
2668 struct drm_framebuffer
*fb
;
2669 int i
= 1; /* Index for sprite planes start */
2671 p
->active
= intel_crtc_active(crtc
);
2673 p
->pipe_htotal
= intel_crtc
->config
->base
.adjusted_mode
.crtc_htotal
;
2674 p
->pixel_rate
= skl_pipe_pixel_rate(intel_crtc
->config
);
2677 * For now, assume primary and cursor planes are always enabled.
2679 p
->plane
[0].enabled
= true;
2680 p
->plane
[0].bytes_per_pixel
=
2681 crtc
->primary
->state
->fb
->bits_per_pixel
/ 8;
2682 p
->plane
[0].horiz_pixels
= intel_crtc
->config
->pipe_src_w
;
2683 p
->plane
[0].vert_pixels
= intel_crtc
->config
->pipe_src_h
;
2684 p
->plane
[0].tiling
= DRM_FORMAT_MOD_NONE
;
2685 fb
= crtc
->primary
->state
->fb
;
2687 * Framebuffer can be NULL on plane disable, but it does not
2688 * matter for watermarks if we assume no tiling in that case.
2691 p
->plane
[0].tiling
= fb
->modifier
[0];
2693 p
->cursor
.enabled
= true;
2694 p
->cursor
.bytes_per_pixel
= 4;
2695 p
->cursor
.horiz_pixels
= intel_crtc
->base
.cursor
->state
->crtc_w
?
2696 intel_crtc
->base
.cursor
->state
->crtc_w
: 64;
2699 list_for_each_entry(plane
, &dev
->mode_config
.plane_list
, head
) {
2700 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
2702 if (intel_plane
->pipe
== pipe
&&
2703 plane
->type
== DRM_PLANE_TYPE_OVERLAY
)
2704 p
->plane
[i
++] = intel_plane
->wm
;
2708 static bool skl_compute_plane_wm(const struct drm_i915_private
*dev_priv
,
2709 struct skl_pipe_wm_parameters
*p
,
2710 struct intel_plane_wm_parameters
*p_params
,
2711 uint16_t ddb_allocation
,
2713 uint16_t *out_blocks
, /* out */
2714 uint8_t *out_lines
/* out */)
2716 uint32_t latency
= dev_priv
->wm
.skl_latency
[level
];
2717 uint32_t method1
, method2
;
2718 uint32_t plane_bytes_per_line
, plane_blocks_per_line
;
2719 uint32_t res_blocks
, res_lines
;
2720 uint32_t selected_result
;
2722 if (latency
== 0 || !p
->active
|| !p_params
->enabled
)
2725 method1
= skl_wm_method1(p
->pixel_rate
,
2726 p_params
->bytes_per_pixel
,
2728 method2
= skl_wm_method2(p
->pixel_rate
,
2730 p_params
->horiz_pixels
,
2731 p_params
->bytes_per_pixel
,
2735 plane_bytes_per_line
= p_params
->horiz_pixels
*
2736 p_params
->bytes_per_pixel
;
2737 plane_blocks_per_line
= DIV_ROUND_UP(plane_bytes_per_line
, 512);
2739 if (p_params
->tiling
== I915_FORMAT_MOD_Y_TILED
||
2740 p_params
->tiling
== I915_FORMAT_MOD_Yf_TILED
) {
2741 uint32_t y_tile_minimum
= plane_blocks_per_line
* 4;
2742 selected_result
= max(method2
, y_tile_minimum
);
2744 if ((ddb_allocation
/ plane_blocks_per_line
) >= 1)
2745 selected_result
= min(method1
, method2
);
2747 selected_result
= method1
;
2750 res_blocks
= selected_result
+ 1;
2751 res_lines
= DIV_ROUND_UP(selected_result
, plane_blocks_per_line
);
2753 if (level
>= 1 && level
<= 7) {
2754 if (p_params
->tiling
== I915_FORMAT_MOD_Y_TILED
||
2755 p_params
->tiling
== I915_FORMAT_MOD_Yf_TILED
)
2761 if (res_blocks
>= ddb_allocation
|| res_lines
> 31)
2764 *out_blocks
= res_blocks
;
2765 *out_lines
= res_lines
;
2770 static void skl_compute_wm_level(const struct drm_i915_private
*dev_priv
,
2771 struct skl_ddb_allocation
*ddb
,
2772 struct skl_pipe_wm_parameters
*p
,
2776 struct skl_wm_level
*result
)
2778 uint16_t ddb_blocks
;
2781 for (i
= 0; i
< num_planes
; i
++) {
2782 ddb_blocks
= skl_ddb_entry_size(&ddb
->plane
[pipe
][i
]);
2784 result
->plane_en
[i
] = skl_compute_plane_wm(dev_priv
,
2788 &result
->plane_res_b
[i
],
2789 &result
->plane_res_l
[i
]);
2792 ddb_blocks
= skl_ddb_entry_size(&ddb
->cursor
[pipe
]);
2793 result
->cursor_en
= skl_compute_plane_wm(dev_priv
, p
, &p
->cursor
,
2795 &result
->cursor_res_b
,
2796 &result
->cursor_res_l
);
2800 skl_compute_linetime_wm(struct drm_crtc
*crtc
, struct skl_pipe_wm_parameters
*p
)
2802 if (!intel_crtc_active(crtc
))
2805 return DIV_ROUND_UP(8 * p
->pipe_htotal
* 1000, p
->pixel_rate
);
2809 static void skl_compute_transition_wm(struct drm_crtc
*crtc
,
2810 struct skl_pipe_wm_parameters
*params
,
2811 struct skl_wm_level
*trans_wm
/* out */)
2813 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2816 if (!params
->active
)
2819 /* Until we know more, just disable transition WMs */
2820 for (i
= 0; i
< intel_num_planes(intel_crtc
); i
++)
2821 trans_wm
->plane_en
[i
] = false;
2822 trans_wm
->cursor_en
= false;
2825 static void skl_compute_pipe_wm(struct drm_crtc
*crtc
,
2826 struct skl_ddb_allocation
*ddb
,
2827 struct skl_pipe_wm_parameters
*params
,
2828 struct skl_pipe_wm
*pipe_wm
)
2830 struct drm_device
*dev
= crtc
->dev
;
2831 const struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2832 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2833 int level
, max_level
= ilk_wm_max_level(dev
);
2835 for (level
= 0; level
<= max_level
; level
++) {
2836 skl_compute_wm_level(dev_priv
, ddb
, params
, intel_crtc
->pipe
,
2837 level
, intel_num_planes(intel_crtc
),
2838 &pipe_wm
->wm
[level
]);
2840 pipe_wm
->linetime
= skl_compute_linetime_wm(crtc
, params
);
2842 skl_compute_transition_wm(crtc
, params
, &pipe_wm
->trans_wm
);
2845 static void skl_compute_wm_results(struct drm_device
*dev
,
2846 struct skl_pipe_wm_parameters
*p
,
2847 struct skl_pipe_wm
*p_wm
,
2848 struct skl_wm_values
*r
,
2849 struct intel_crtc
*intel_crtc
)
2851 int level
, max_level
= ilk_wm_max_level(dev
);
2852 enum pipe pipe
= intel_crtc
->pipe
;
2856 for (level
= 0; level
<= max_level
; level
++) {
2857 for (i
= 0; i
< intel_num_planes(intel_crtc
); i
++) {
2860 temp
|= p_wm
->wm
[level
].plane_res_l
[i
] <<
2861 PLANE_WM_LINES_SHIFT
;
2862 temp
|= p_wm
->wm
[level
].plane_res_b
[i
];
2863 if (p_wm
->wm
[level
].plane_en
[i
])
2864 temp
|= PLANE_WM_EN
;
2866 r
->plane
[pipe
][i
][level
] = temp
;
2871 temp
|= p_wm
->wm
[level
].cursor_res_l
<< PLANE_WM_LINES_SHIFT
;
2872 temp
|= p_wm
->wm
[level
].cursor_res_b
;
2874 if (p_wm
->wm
[level
].cursor_en
)
2875 temp
|= PLANE_WM_EN
;
2877 r
->cursor
[pipe
][level
] = temp
;
2881 /* transition WMs */
2882 for (i
= 0; i
< intel_num_planes(intel_crtc
); i
++) {
2884 temp
|= p_wm
->trans_wm
.plane_res_l
[i
] << PLANE_WM_LINES_SHIFT
;
2885 temp
|= p_wm
->trans_wm
.plane_res_b
[i
];
2886 if (p_wm
->trans_wm
.plane_en
[i
])
2887 temp
|= PLANE_WM_EN
;
2889 r
->plane_trans
[pipe
][i
] = temp
;
2893 temp
|= p_wm
->trans_wm
.cursor_res_l
<< PLANE_WM_LINES_SHIFT
;
2894 temp
|= p_wm
->trans_wm
.cursor_res_b
;
2895 if (p_wm
->trans_wm
.cursor_en
)
2896 temp
|= PLANE_WM_EN
;
2898 r
->cursor_trans
[pipe
] = temp
;
2900 r
->wm_linetime
[pipe
] = p_wm
->linetime
;
2903 static void skl_ddb_entry_write(struct drm_i915_private
*dev_priv
, uint32_t reg
,
2904 const struct skl_ddb_entry
*entry
)
2907 I915_WRITE(reg
, (entry
->end
- 1) << 16 | entry
->start
);
2912 static void skl_write_wm_values(struct drm_i915_private
*dev_priv
,
2913 const struct skl_wm_values
*new)
2915 struct drm_device
*dev
= dev_priv
->dev
;
2916 struct intel_crtc
*crtc
;
2918 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, base
.head
) {
2919 int i
, level
, max_level
= ilk_wm_max_level(dev
);
2920 enum pipe pipe
= crtc
->pipe
;
2922 if (!new->dirty
[pipe
])
2925 I915_WRITE(PIPE_WM_LINETIME(pipe
), new->wm_linetime
[pipe
]);
2927 for (level
= 0; level
<= max_level
; level
++) {
2928 for (i
= 0; i
< intel_num_planes(crtc
); i
++)
2929 I915_WRITE(PLANE_WM(pipe
, i
, level
),
2930 new->plane
[pipe
][i
][level
]);
2931 I915_WRITE(CUR_WM(pipe
, level
),
2932 new->cursor
[pipe
][level
]);
2934 for (i
= 0; i
< intel_num_planes(crtc
); i
++)
2935 I915_WRITE(PLANE_WM_TRANS(pipe
, i
),
2936 new->plane_trans
[pipe
][i
]);
2937 I915_WRITE(CUR_WM_TRANS(pipe
), new->cursor_trans
[pipe
]);
2939 for (i
= 0; i
< intel_num_planes(crtc
); i
++)
2940 skl_ddb_entry_write(dev_priv
,
2941 PLANE_BUF_CFG(pipe
, i
),
2942 &new->ddb
.plane
[pipe
][i
]);
2944 skl_ddb_entry_write(dev_priv
, CUR_BUF_CFG(pipe
),
2945 &new->ddb
.cursor
[pipe
]);
2950 * When setting up a new DDB allocation arrangement, we need to correctly
2951 * sequence the times at which the new allocations for the pipes are taken into
2952 * account or we'll have pipes fetching from space previously allocated to
2955 * Roughly the sequence looks like:
2956 * 1. re-allocate the pipe(s) with the allocation being reduced and not
2957 * overlapping with a previous light-up pipe (another way to put it is:
2958 * pipes with their new allocation strickly included into their old ones).
2959 * 2. re-allocate the other pipes that get their allocation reduced
2960 * 3. allocate the pipes having their allocation increased
2962 * Steps 1. and 2. are here to take care of the following case:
2963 * - Initially DDB looks like this:
2966 * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
2970 * We need to sequence the re-allocation: C, B, A (and not B, C, A).
2974 skl_wm_flush_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int pass
)
2978 DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe
), pass
);
2980 for_each_plane(dev_priv
, pipe
, plane
) {
2981 I915_WRITE(PLANE_SURF(pipe
, plane
),
2982 I915_READ(PLANE_SURF(pipe
, plane
)));
2984 I915_WRITE(CURBASE(pipe
), I915_READ(CURBASE(pipe
)));
2988 skl_ddb_allocation_included(const struct skl_ddb_allocation
*old
,
2989 const struct skl_ddb_allocation
*new,
2992 uint16_t old_size
, new_size
;
2994 old_size
= skl_ddb_entry_size(&old
->pipe
[pipe
]);
2995 new_size
= skl_ddb_entry_size(&new->pipe
[pipe
]);
2997 return old_size
!= new_size
&&
2998 new->pipe
[pipe
].start
>= old
->pipe
[pipe
].start
&&
2999 new->pipe
[pipe
].end
<= old
->pipe
[pipe
].end
;
3002 static void skl_flush_wm_values(struct drm_i915_private
*dev_priv
,
3003 struct skl_wm_values
*new_values
)
3005 struct drm_device
*dev
= dev_priv
->dev
;
3006 struct skl_ddb_allocation
*cur_ddb
, *new_ddb
;
3007 bool reallocated
[I915_MAX_PIPES
] = {false, false, false};
3008 struct intel_crtc
*crtc
;
3011 new_ddb
= &new_values
->ddb
;
3012 cur_ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
3015 * First pass: flush the pipes with the new allocation contained into
3018 * We'll wait for the vblank on those pipes to ensure we can safely
3019 * re-allocate the freed space without this pipe fetching from it.
3021 for_each_intel_crtc(dev
, crtc
) {
3027 if (!skl_ddb_allocation_included(cur_ddb
, new_ddb
, pipe
))
3030 skl_wm_flush_pipe(dev_priv
, pipe
, 1);
3031 intel_wait_for_vblank(dev
, pipe
);
3033 reallocated
[pipe
] = true;
3038 * Second pass: flush the pipes that are having their allocation
3039 * reduced, but overlapping with a previous allocation.
3041 * Here as well we need to wait for the vblank to make sure the freed
3042 * space is not used anymore.
3044 for_each_intel_crtc(dev
, crtc
) {
3050 if (reallocated
[pipe
])
3053 if (skl_ddb_entry_size(&new_ddb
->pipe
[pipe
]) <
3054 skl_ddb_entry_size(&cur_ddb
->pipe
[pipe
])) {
3055 skl_wm_flush_pipe(dev_priv
, pipe
, 2);
3056 intel_wait_for_vblank(dev
, pipe
);
3057 reallocated
[pipe
] = true;
3062 * Third pass: flush the pipes that got more space allocated.
3064 * We don't need to actively wait for the update here, next vblank
3065 * will just get more DDB space with the correct WM values.
3067 for_each_intel_crtc(dev
, crtc
) {
3074 * At this point, only the pipes more space than before are
3075 * left to re-allocate.
3077 if (reallocated
[pipe
])
3080 skl_wm_flush_pipe(dev_priv
, pipe
, 3);
3084 static bool skl_update_pipe_wm(struct drm_crtc
*crtc
,
3085 struct skl_pipe_wm_parameters
*params
,
3086 struct intel_wm_config
*config
,
3087 struct skl_ddb_allocation
*ddb
, /* out */
3088 struct skl_pipe_wm
*pipe_wm
/* out */)
3090 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3092 skl_compute_wm_pipe_parameters(crtc
, params
);
3093 skl_allocate_pipe_ddb(crtc
, config
, params
, ddb
);
3094 skl_compute_pipe_wm(crtc
, ddb
, params
, pipe_wm
);
3096 if (!memcmp(&intel_crtc
->wm
.skl_active
, pipe_wm
, sizeof(*pipe_wm
)))
3099 intel_crtc
->wm
.skl_active
= *pipe_wm
;
3103 static void skl_update_other_pipe_wm(struct drm_device
*dev
,
3104 struct drm_crtc
*crtc
,
3105 struct intel_wm_config
*config
,
3106 struct skl_wm_values
*r
)
3108 struct intel_crtc
*intel_crtc
;
3109 struct intel_crtc
*this_crtc
= to_intel_crtc(crtc
);
3112 * If the WM update hasn't changed the allocation for this_crtc (the
3113 * crtc we are currently computing the new WM values for), other
3114 * enabled crtcs will keep the same allocation and we don't need to
3115 * recompute anything for them.
3117 if (!skl_ddb_allocation_changed(&r
->ddb
, this_crtc
))
3121 * Otherwise, because of this_crtc being freshly enabled/disabled, the
3122 * other active pipes need new DDB allocation and WM values.
3124 list_for_each_entry(intel_crtc
, &dev
->mode_config
.crtc_list
,
3126 struct skl_pipe_wm_parameters params
= {};
3127 struct skl_pipe_wm pipe_wm
= {};
3130 if (this_crtc
->pipe
== intel_crtc
->pipe
)
3133 if (!intel_crtc
->active
)
3136 wm_changed
= skl_update_pipe_wm(&intel_crtc
->base
,
3141 * If we end up re-computing the other pipe WM values, it's
3142 * because it was really needed, so we expect the WM values to
3145 WARN_ON(!wm_changed
);
3147 skl_compute_wm_results(dev
, ¶ms
, &pipe_wm
, r
, intel_crtc
);
3148 r
->dirty
[intel_crtc
->pipe
] = true;
3152 static void skl_update_wm(struct drm_crtc
*crtc
)
3154 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3155 struct drm_device
*dev
= crtc
->dev
;
3156 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3157 struct skl_pipe_wm_parameters params
= {};
3158 struct skl_wm_values
*results
= &dev_priv
->wm
.skl_results
;
3159 struct skl_pipe_wm pipe_wm
= {};
3160 struct intel_wm_config config
= {};
3162 memset(results
, 0, sizeof(*results
));
3164 skl_compute_wm_global_parameters(dev
, &config
);
3166 if (!skl_update_pipe_wm(crtc
, ¶ms
, &config
,
3167 &results
->ddb
, &pipe_wm
))
3170 skl_compute_wm_results(dev
, ¶ms
, &pipe_wm
, results
, intel_crtc
);
3171 results
->dirty
[intel_crtc
->pipe
] = true;
3173 skl_update_other_pipe_wm(dev
, crtc
, &config
, results
);
3174 skl_write_wm_values(dev_priv
, results
);
3175 skl_flush_wm_values(dev_priv
, results
);
3177 /* store the new configuration */
3178 dev_priv
->wm
.skl_hw
= *results
;
3182 skl_update_sprite_wm(struct drm_plane
*plane
, struct drm_crtc
*crtc
,
3183 uint32_t sprite_width
, uint32_t sprite_height
,
3184 int pixel_size
, bool enabled
, bool scaled
)
3186 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
3187 struct drm_framebuffer
*fb
= plane
->state
->fb
;
3189 intel_plane
->wm
.enabled
= enabled
;
3190 intel_plane
->wm
.scaled
= scaled
;
3191 intel_plane
->wm
.horiz_pixels
= sprite_width
;
3192 intel_plane
->wm
.vert_pixels
= sprite_height
;
3193 intel_plane
->wm
.bytes_per_pixel
= pixel_size
;
3194 intel_plane
->wm
.tiling
= DRM_FORMAT_MOD_NONE
;
3196 * Framebuffer can be NULL on plane disable, but it does not
3197 * matter for watermarks if we assume no tiling in that case.
3200 intel_plane
->wm
.tiling
= fb
->modifier
[0];
3202 skl_update_wm(crtc
);
3205 static void ilk_update_wm(struct drm_crtc
*crtc
)
3207 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3208 struct drm_device
*dev
= crtc
->dev
;
3209 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3210 struct ilk_wm_maximums max
;
3211 struct ilk_pipe_wm_parameters params
= {};
3212 struct ilk_wm_values results
= {};
3213 enum intel_ddb_partitioning partitioning
;
3214 struct intel_pipe_wm pipe_wm
= {};
3215 struct intel_pipe_wm lp_wm_1_2
= {}, lp_wm_5_6
= {}, *best_lp_wm
;
3216 struct intel_wm_config config
= {};
3218 ilk_compute_wm_parameters(crtc
, ¶ms
);
3220 intel_compute_pipe_wm(crtc
, ¶ms
, &pipe_wm
);
3222 if (!memcmp(&intel_crtc
->wm
.active
, &pipe_wm
, sizeof(pipe_wm
)))
3225 intel_crtc
->wm
.active
= pipe_wm
;
3227 ilk_compute_wm_config(dev
, &config
);
3229 ilk_compute_wm_maximums(dev
, 1, &config
, INTEL_DDB_PART_1_2
, &max
);
3230 ilk_wm_merge(dev
, &config
, &max
, &lp_wm_1_2
);
3232 /* 5/6 split only in single pipe config on IVB+ */
3233 if (INTEL_INFO(dev
)->gen
>= 7 &&
3234 config
.num_pipes_active
== 1 && config
.sprites_enabled
) {
3235 ilk_compute_wm_maximums(dev
, 1, &config
, INTEL_DDB_PART_5_6
, &max
);
3236 ilk_wm_merge(dev
, &config
, &max
, &lp_wm_5_6
);
3238 best_lp_wm
= ilk_find_best_result(dev
, &lp_wm_1_2
, &lp_wm_5_6
);
3240 best_lp_wm
= &lp_wm_1_2
;
3243 partitioning
= (best_lp_wm
== &lp_wm_1_2
) ?
3244 INTEL_DDB_PART_1_2
: INTEL_DDB_PART_5_6
;
3246 ilk_compute_wm_results(dev
, best_lp_wm
, partitioning
, &results
);
3248 ilk_write_wm_values(dev_priv
, &results
);
3252 ilk_update_sprite_wm(struct drm_plane
*plane
,
3253 struct drm_crtc
*crtc
,
3254 uint32_t sprite_width
, uint32_t sprite_height
,
3255 int pixel_size
, bool enabled
, bool scaled
)
3257 struct drm_device
*dev
= plane
->dev
;
3258 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
3260 intel_plane
->wm
.enabled
= enabled
;
3261 intel_plane
->wm
.scaled
= scaled
;
3262 intel_plane
->wm
.horiz_pixels
= sprite_width
;
3263 intel_plane
->wm
.vert_pixels
= sprite_width
;
3264 intel_plane
->wm
.bytes_per_pixel
= pixel_size
;
3267 * IVB workaround: must disable low power watermarks for at least
3268 * one frame before enabling scaling. LP watermarks can be re-enabled
3269 * when scaling is disabled.
3271 * WaCxSRDisabledForSpriteScaling:ivb
3273 if (IS_IVYBRIDGE(dev
) && scaled
&& ilk_disable_lp_wm(dev
))
3274 intel_wait_for_vblank(dev
, intel_plane
->pipe
);
3276 ilk_update_wm(crtc
);
3279 static void skl_pipe_wm_active_state(uint32_t val
,
3280 struct skl_pipe_wm
*active
,
3286 bool is_enabled
= (val
& PLANE_WM_EN
) != 0;
3290 active
->wm
[level
].plane_en
[i
] = is_enabled
;
3291 active
->wm
[level
].plane_res_b
[i
] =
3292 val
& PLANE_WM_BLOCKS_MASK
;
3293 active
->wm
[level
].plane_res_l
[i
] =
3294 (val
>> PLANE_WM_LINES_SHIFT
) &
3295 PLANE_WM_LINES_MASK
;
3297 active
->wm
[level
].cursor_en
= is_enabled
;
3298 active
->wm
[level
].cursor_res_b
=
3299 val
& PLANE_WM_BLOCKS_MASK
;
3300 active
->wm
[level
].cursor_res_l
=
3301 (val
>> PLANE_WM_LINES_SHIFT
) &
3302 PLANE_WM_LINES_MASK
;
3306 active
->trans_wm
.plane_en
[i
] = is_enabled
;
3307 active
->trans_wm
.plane_res_b
[i
] =
3308 val
& PLANE_WM_BLOCKS_MASK
;
3309 active
->trans_wm
.plane_res_l
[i
] =
3310 (val
>> PLANE_WM_LINES_SHIFT
) &
3311 PLANE_WM_LINES_MASK
;
3313 active
->trans_wm
.cursor_en
= is_enabled
;
3314 active
->trans_wm
.cursor_res_b
=
3315 val
& PLANE_WM_BLOCKS_MASK
;
3316 active
->trans_wm
.cursor_res_l
=
3317 (val
>> PLANE_WM_LINES_SHIFT
) &
3318 PLANE_WM_LINES_MASK
;
3323 static void skl_pipe_wm_get_hw_state(struct drm_crtc
*crtc
)
3325 struct drm_device
*dev
= crtc
->dev
;
3326 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3327 struct skl_wm_values
*hw
= &dev_priv
->wm
.skl_hw
;
3328 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3329 struct skl_pipe_wm
*active
= &intel_crtc
->wm
.skl_active
;
3330 enum pipe pipe
= intel_crtc
->pipe
;
3331 int level
, i
, max_level
;
3334 max_level
= ilk_wm_max_level(dev
);
3336 hw
->wm_linetime
[pipe
] = I915_READ(PIPE_WM_LINETIME(pipe
));
3338 for (level
= 0; level
<= max_level
; level
++) {
3339 for (i
= 0; i
< intel_num_planes(intel_crtc
); i
++)
3340 hw
->plane
[pipe
][i
][level
] =
3341 I915_READ(PLANE_WM(pipe
, i
, level
));
3342 hw
->cursor
[pipe
][level
] = I915_READ(CUR_WM(pipe
, level
));
3345 for (i
= 0; i
< intel_num_planes(intel_crtc
); i
++)
3346 hw
->plane_trans
[pipe
][i
] = I915_READ(PLANE_WM_TRANS(pipe
, i
));
3347 hw
->cursor_trans
[pipe
] = I915_READ(CUR_WM_TRANS(pipe
));
3349 if (!intel_crtc_active(crtc
))
3352 hw
->dirty
[pipe
] = true;
3354 active
->linetime
= hw
->wm_linetime
[pipe
];
3356 for (level
= 0; level
<= max_level
; level
++) {
3357 for (i
= 0; i
< intel_num_planes(intel_crtc
); i
++) {
3358 temp
= hw
->plane
[pipe
][i
][level
];
3359 skl_pipe_wm_active_state(temp
, active
, false,
3362 temp
= hw
->cursor
[pipe
][level
];
3363 skl_pipe_wm_active_state(temp
, active
, false, true, i
, level
);
3366 for (i
= 0; i
< intel_num_planes(intel_crtc
); i
++) {
3367 temp
= hw
->plane_trans
[pipe
][i
];
3368 skl_pipe_wm_active_state(temp
, active
, true, false, i
, 0);
3371 temp
= hw
->cursor_trans
[pipe
];
3372 skl_pipe_wm_active_state(temp
, active
, true, true, i
, 0);
3375 void skl_wm_get_hw_state(struct drm_device
*dev
)
3377 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3378 struct skl_ddb_allocation
*ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
3379 struct drm_crtc
*crtc
;
3381 skl_ddb_get_hw_state(dev_priv
, ddb
);
3382 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
)
3383 skl_pipe_wm_get_hw_state(crtc
);
3386 static void ilk_pipe_wm_get_hw_state(struct drm_crtc
*crtc
)
3388 struct drm_device
*dev
= crtc
->dev
;
3389 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3390 struct ilk_wm_values
*hw
= &dev_priv
->wm
.hw
;
3391 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3392 struct intel_pipe_wm
*active
= &intel_crtc
->wm
.active
;
3393 enum pipe pipe
= intel_crtc
->pipe
;
3394 static const unsigned int wm0_pipe_reg
[] = {
3395 [PIPE_A
] = WM0_PIPEA_ILK
,
3396 [PIPE_B
] = WM0_PIPEB_ILK
,
3397 [PIPE_C
] = WM0_PIPEC_IVB
,
3400 hw
->wm_pipe
[pipe
] = I915_READ(wm0_pipe_reg
[pipe
]);
3401 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
3402 hw
->wm_linetime
[pipe
] = I915_READ(PIPE_WM_LINETIME(pipe
));
3404 active
->pipe_enabled
= intel_crtc_active(crtc
);
3406 if (active
->pipe_enabled
) {
3407 u32 tmp
= hw
->wm_pipe
[pipe
];
3410 * For active pipes LP0 watermark is marked as
3411 * enabled, and LP1+ watermaks as disabled since
3412 * we can't really reverse compute them in case
3413 * multiple pipes are active.
3415 active
->wm
[0].enable
= true;
3416 active
->wm
[0].pri_val
= (tmp
& WM0_PIPE_PLANE_MASK
) >> WM0_PIPE_PLANE_SHIFT
;
3417 active
->wm
[0].spr_val
= (tmp
& WM0_PIPE_SPRITE_MASK
) >> WM0_PIPE_SPRITE_SHIFT
;
3418 active
->wm
[0].cur_val
= tmp
& WM0_PIPE_CURSOR_MASK
;
3419 active
->linetime
= hw
->wm_linetime
[pipe
];
3421 int level
, max_level
= ilk_wm_max_level(dev
);
3424 * For inactive pipes, all watermark levels
3425 * should be marked as enabled but zeroed,
3426 * which is what we'd compute them to.
3428 for (level
= 0; level
<= max_level
; level
++)
3429 active
->wm
[level
].enable
= true;
3433 void ilk_wm_get_hw_state(struct drm_device
*dev
)
3435 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3436 struct ilk_wm_values
*hw
= &dev_priv
->wm
.hw
;
3437 struct drm_crtc
*crtc
;
3439 for_each_crtc(dev
, crtc
)
3440 ilk_pipe_wm_get_hw_state(crtc
);
3442 hw
->wm_lp
[0] = I915_READ(WM1_LP_ILK
);
3443 hw
->wm_lp
[1] = I915_READ(WM2_LP_ILK
);
3444 hw
->wm_lp
[2] = I915_READ(WM3_LP_ILK
);
3446 hw
->wm_lp_spr
[0] = I915_READ(WM1S_LP_ILK
);
3447 if (INTEL_INFO(dev
)->gen
>= 7) {
3448 hw
->wm_lp_spr
[1] = I915_READ(WM2S_LP_IVB
);
3449 hw
->wm_lp_spr
[2] = I915_READ(WM3S_LP_IVB
);
3452 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
3453 hw
->partitioning
= (I915_READ(WM_MISC
) & WM_MISC_DATA_PARTITION_5_6
) ?
3454 INTEL_DDB_PART_5_6
: INTEL_DDB_PART_1_2
;
3455 else if (IS_IVYBRIDGE(dev
))
3456 hw
->partitioning
= (I915_READ(DISP_ARB_CTL2
) & DISP_DATA_PARTITION_5_6
) ?
3457 INTEL_DDB_PART_5_6
: INTEL_DDB_PART_1_2
;
3460 !(I915_READ(DISP_ARB_CTL
) & DISP_FBC_WM_DIS
);
3464 * intel_update_watermarks - update FIFO watermark values based on current modes
3466 * Calculate watermark values for the various WM regs based on current mode
3467 * and plane configuration.
3469 * There are several cases to deal with here:
3470 * - normal (i.e. non-self-refresh)
3471 * - self-refresh (SR) mode
3472 * - lines are large relative to FIFO size (buffer can hold up to 2)
3473 * - lines are small relative to FIFO size (buffer can hold more than 2
3474 * lines), so need to account for TLB latency
3476 * The normal calculation is:
3477 * watermark = dotclock * bytes per pixel * latency
3478 * where latency is platform & configuration dependent (we assume pessimal
3481 * The SR calculation is:
3482 * watermark = (trunc(latency/line time)+1) * surface width *
3485 * line time = htotal / dotclock
3486 * surface width = hdisplay for normal plane and 64 for cursor
3487 * and latency is assumed to be high, as above.
3489 * The final value programmed to the register should always be rounded up,
3490 * and include an extra 2 entries to account for clock crossings.
3492 * We don't use the sprite, so we can ignore that. And on Crestline we have
3493 * to set the non-SR watermarks to 8.
3495 void intel_update_watermarks(struct drm_crtc
*crtc
)
3497 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
3499 if (dev_priv
->display
.update_wm
)
3500 dev_priv
->display
.update_wm(crtc
);
3503 void intel_update_sprite_watermarks(struct drm_plane
*plane
,
3504 struct drm_crtc
*crtc
,
3505 uint32_t sprite_width
,
3506 uint32_t sprite_height
,
3508 bool enabled
, bool scaled
)
3510 struct drm_i915_private
*dev_priv
= plane
->dev
->dev_private
;
3512 if (dev_priv
->display
.update_sprite_wm
)
3513 dev_priv
->display
.update_sprite_wm(plane
, crtc
,
3514 sprite_width
, sprite_height
,
3515 pixel_size
, enabled
, scaled
);
3519 * Lock protecting IPS related data structures
3521 DEFINE_SPINLOCK(mchdev_lock
);
3523 /* Global for IPS driver to get at the current i915 device. Protected by
3525 static struct drm_i915_private
*i915_mch_dev
;
3527 bool ironlake_set_drps(struct drm_device
*dev
, u8 val
)
3529 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3532 assert_spin_locked(&mchdev_lock
);
3534 rgvswctl
= I915_READ16(MEMSWCTL
);
3535 if (rgvswctl
& MEMCTL_CMD_STS
) {
3536 DRM_DEBUG("gpu busy, RCS change rejected\n");
3537 return false; /* still busy with another command */
3540 rgvswctl
= (MEMCTL_CMD_CHFREQ
<< MEMCTL_CMD_SHIFT
) |
3541 (val
<< MEMCTL_FREQ_SHIFT
) | MEMCTL_SFCAVM
;
3542 I915_WRITE16(MEMSWCTL
, rgvswctl
);
3543 POSTING_READ16(MEMSWCTL
);
3545 rgvswctl
|= MEMCTL_CMD_STS
;
3546 I915_WRITE16(MEMSWCTL
, rgvswctl
);
3551 static void ironlake_enable_drps(struct drm_device
*dev
)
3553 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3554 u32 rgvmodectl
= I915_READ(MEMMODECTL
);
3555 u8 fmax
, fmin
, fstart
, vstart
;
3557 spin_lock_irq(&mchdev_lock
);
3559 /* Enable temp reporting */
3560 I915_WRITE16(PMMISC
, I915_READ(PMMISC
) | MCPPCE_EN
);
3561 I915_WRITE16(TSC1
, I915_READ(TSC1
) | TSE
);
3563 /* 100ms RC evaluation intervals */
3564 I915_WRITE(RCUPEI
, 100000);
3565 I915_WRITE(RCDNEI
, 100000);
3567 /* Set max/min thresholds to 90ms and 80ms respectively */
3568 I915_WRITE(RCBMAXAVG
, 90000);
3569 I915_WRITE(RCBMINAVG
, 80000);
3571 I915_WRITE(MEMIHYST
, 1);
3573 /* Set up min, max, and cur for interrupt handling */
3574 fmax
= (rgvmodectl
& MEMMODE_FMAX_MASK
) >> MEMMODE_FMAX_SHIFT
;
3575 fmin
= (rgvmodectl
& MEMMODE_FMIN_MASK
);
3576 fstart
= (rgvmodectl
& MEMMODE_FSTART_MASK
) >>
3577 MEMMODE_FSTART_SHIFT
;
3579 vstart
= (I915_READ(PXVFREQ_BASE
+ (fstart
* 4)) & PXVFREQ_PX_MASK
) >>
3582 dev_priv
->ips
.fmax
= fmax
; /* IPS callback will increase this */
3583 dev_priv
->ips
.fstart
= fstart
;
3585 dev_priv
->ips
.max_delay
= fstart
;
3586 dev_priv
->ips
.min_delay
= fmin
;
3587 dev_priv
->ips
.cur_delay
= fstart
;
3589 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
3590 fmax
, fmin
, fstart
);
3592 I915_WRITE(MEMINTREN
, MEMINT_CX_SUPR_EN
| MEMINT_EVAL_CHG_EN
);
3595 * Interrupts will be enabled in ironlake_irq_postinstall
3598 I915_WRITE(VIDSTART
, vstart
);
3599 POSTING_READ(VIDSTART
);
3601 rgvmodectl
|= MEMMODE_SWMODE_EN
;
3602 I915_WRITE(MEMMODECTL
, rgvmodectl
);
3604 if (wait_for_atomic((I915_READ(MEMSWCTL
) & MEMCTL_CMD_STS
) == 0, 10))
3605 DRM_ERROR("stuck trying to change perf mode\n");
3608 ironlake_set_drps(dev
, fstart
);
3610 dev_priv
->ips
.last_count1
= I915_READ(0x112e4) + I915_READ(0x112e8) +
3612 dev_priv
->ips
.last_time1
= jiffies_to_msecs(jiffies
);
3613 dev_priv
->ips
.last_count2
= I915_READ(0x112f4);
3614 dev_priv
->ips
.last_time2
= ktime_get_raw_ns();
3616 spin_unlock_irq(&mchdev_lock
);
3619 static void ironlake_disable_drps(struct drm_device
*dev
)
3621 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3624 spin_lock_irq(&mchdev_lock
);
3626 rgvswctl
= I915_READ16(MEMSWCTL
);
3628 /* Ack interrupts, disable EFC interrupt */
3629 I915_WRITE(MEMINTREN
, I915_READ(MEMINTREN
) & ~MEMINT_EVAL_CHG_EN
);
3630 I915_WRITE(MEMINTRSTS
, MEMINT_EVAL_CHG
);
3631 I915_WRITE(DEIER
, I915_READ(DEIER
) & ~DE_PCU_EVENT
);
3632 I915_WRITE(DEIIR
, DE_PCU_EVENT
);
3633 I915_WRITE(DEIMR
, I915_READ(DEIMR
) | DE_PCU_EVENT
);
3635 /* Go back to the starting frequency */
3636 ironlake_set_drps(dev
, dev_priv
->ips
.fstart
);
3638 rgvswctl
|= MEMCTL_CMD_STS
;
3639 I915_WRITE(MEMSWCTL
, rgvswctl
);
3642 spin_unlock_irq(&mchdev_lock
);
3645 /* There's a funny hw issue where the hw returns all 0 when reading from
3646 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3647 * ourselves, instead of doing a rmw cycle (which might result in us clearing
3648 * all limits and the gpu stuck at whatever frequency it is at atm).
3650 static u32
gen6_rps_limits(struct drm_i915_private
*dev_priv
, u8 val
)
3654 /* Only set the down limit when we've reached the lowest level to avoid
3655 * getting more interrupts, otherwise leave this clear. This prevents a
3656 * race in the hw when coming out of rc6: There's a tiny window where
3657 * the hw runs at the minimal clock before selecting the desired
3658 * frequency, if the down threshold expires in that window we will not
3659 * receive a down interrupt. */
3660 limits
= dev_priv
->rps
.max_freq_softlimit
<< 24;
3661 if (val
<= dev_priv
->rps
.min_freq_softlimit
)
3662 limits
|= dev_priv
->rps
.min_freq_softlimit
<< 16;
3667 static void gen6_set_rps_thresholds(struct drm_i915_private
*dev_priv
, u8 val
)
3671 new_power
= dev_priv
->rps
.power
;
3672 switch (dev_priv
->rps
.power
) {
3674 if (val
> dev_priv
->rps
.efficient_freq
+ 1 && val
> dev_priv
->rps
.cur_freq
)
3675 new_power
= BETWEEN
;
3679 if (val
<= dev_priv
->rps
.efficient_freq
&& val
< dev_priv
->rps
.cur_freq
)
3680 new_power
= LOW_POWER
;
3681 else if (val
>= dev_priv
->rps
.rp0_freq
&& val
> dev_priv
->rps
.cur_freq
)
3682 new_power
= HIGH_POWER
;
3686 if (val
< (dev_priv
->rps
.rp1_freq
+ dev_priv
->rps
.rp0_freq
) >> 1 && val
< dev_priv
->rps
.cur_freq
)
3687 new_power
= BETWEEN
;
3690 /* Max/min bins are special */
3691 if (val
== dev_priv
->rps
.min_freq_softlimit
)
3692 new_power
= LOW_POWER
;
3693 if (val
== dev_priv
->rps
.max_freq_softlimit
)
3694 new_power
= HIGH_POWER
;
3695 if (new_power
== dev_priv
->rps
.power
)
3698 /* Note the units here are not exactly 1us, but 1280ns. */
3699 switch (new_power
) {
3701 /* Upclock if more than 95% busy over 16ms */
3702 I915_WRITE(GEN6_RP_UP_EI
, 12500);
3703 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 11800);
3705 /* Downclock if less than 85% busy over 32ms */
3706 I915_WRITE(GEN6_RP_DOWN_EI
, 25000);
3707 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 21250);
3709 I915_WRITE(GEN6_RP_CONTROL
,
3710 GEN6_RP_MEDIA_TURBO
|
3711 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
3712 GEN6_RP_MEDIA_IS_GFX
|
3714 GEN6_RP_UP_BUSY_AVG
|
3715 GEN6_RP_DOWN_IDLE_AVG
);
3719 /* Upclock if more than 90% busy over 13ms */
3720 I915_WRITE(GEN6_RP_UP_EI
, 10250);
3721 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 9225);
3723 /* Downclock if less than 75% busy over 32ms */
3724 I915_WRITE(GEN6_RP_DOWN_EI
, 25000);
3725 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 18750);
3727 I915_WRITE(GEN6_RP_CONTROL
,
3728 GEN6_RP_MEDIA_TURBO
|
3729 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
3730 GEN6_RP_MEDIA_IS_GFX
|
3732 GEN6_RP_UP_BUSY_AVG
|
3733 GEN6_RP_DOWN_IDLE_AVG
);
3737 /* Upclock if more than 85% busy over 10ms */
3738 I915_WRITE(GEN6_RP_UP_EI
, 8000);
3739 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 6800);
3741 /* Downclock if less than 60% busy over 32ms */
3742 I915_WRITE(GEN6_RP_DOWN_EI
, 25000);
3743 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 15000);
3745 I915_WRITE(GEN6_RP_CONTROL
,
3746 GEN6_RP_MEDIA_TURBO
|
3747 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
3748 GEN6_RP_MEDIA_IS_GFX
|
3750 GEN6_RP_UP_BUSY_AVG
|
3751 GEN6_RP_DOWN_IDLE_AVG
);
3755 dev_priv
->rps
.power
= new_power
;
3756 dev_priv
->rps
.last_adj
= 0;
3759 static u32
gen6_rps_pm_mask(struct drm_i915_private
*dev_priv
, u8 val
)
3763 if (val
> dev_priv
->rps
.min_freq_softlimit
)
3764 mask
|= GEN6_PM_RP_DOWN_THRESHOLD
| GEN6_PM_RP_DOWN_TIMEOUT
;
3765 if (val
< dev_priv
->rps
.max_freq_softlimit
)
3766 mask
|= GEN6_PM_RP_UP_THRESHOLD
;
3768 mask
|= dev_priv
->pm_rps_events
& (GEN6_PM_RP_DOWN_EI_EXPIRED
| GEN6_PM_RP_UP_EI_EXPIRED
);
3769 mask
&= dev_priv
->pm_rps_events
;
3771 return gen6_sanitize_rps_pm_mask(dev_priv
, ~mask
);
3774 /* gen6_set_rps is called to update the frequency request, but should also be
3775 * called when the range (min_delay and max_delay) is modified so that we can
3776 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
3777 static void gen6_set_rps(struct drm_device
*dev
, u8 val
)
3779 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3781 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
3782 WARN_ON(val
> dev_priv
->rps
.max_freq_softlimit
);
3783 WARN_ON(val
< dev_priv
->rps
.min_freq_softlimit
);
3785 /* min/max delay may still have been modified so be sure to
3786 * write the limits value.
3788 if (val
!= dev_priv
->rps
.cur_freq
) {
3789 gen6_set_rps_thresholds(dev_priv
, val
);
3791 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
3792 I915_WRITE(GEN6_RPNSWREQ
,
3793 HSW_FREQUENCY(val
));
3795 I915_WRITE(GEN6_RPNSWREQ
,
3796 GEN6_FREQUENCY(val
) |
3798 GEN6_AGGRESSIVE_TURBO
);
3801 /* Make sure we continue to get interrupts
3802 * until we hit the minimum or maximum frequencies.
3804 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS
, gen6_rps_limits(dev_priv
, val
));
3805 I915_WRITE(GEN6_PMINTRMSK
, gen6_rps_pm_mask(dev_priv
, val
));
3807 POSTING_READ(GEN6_RPNSWREQ
);
3809 dev_priv
->rps
.cur_freq
= val
;
3810 trace_intel_gpu_freq_change(val
* 50);
3813 static void valleyview_set_rps(struct drm_device
*dev
, u8 val
)
3815 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3817 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
3818 WARN_ON(val
> dev_priv
->rps
.max_freq_softlimit
);
3819 WARN_ON(val
< dev_priv
->rps
.min_freq_softlimit
);
3821 if (WARN_ONCE(IS_CHERRYVIEW(dev
) && (val
& 1),
3822 "Odd GPU freq value\n"))
3825 if (val
!= dev_priv
->rps
.cur_freq
)
3826 vlv_punit_write(dev_priv
, PUNIT_REG_GPU_FREQ_REQ
, val
);
3828 I915_WRITE(GEN6_PMINTRMSK
, gen6_rps_pm_mask(dev_priv
, val
));
3830 dev_priv
->rps
.cur_freq
= val
;
3831 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv
, val
));
3834 /* vlv_set_rps_idle: Set the frequency to Rpn if Gfx clocks are down
3836 * * If Gfx is Idle, then
3837 * 1. Mask Turbo interrupts
3838 * 2. Bring up Gfx clock
3839 * 3. Change the freq to Rpn and wait till P-Unit updates freq
3840 * 4. Clear the Force GFX CLK ON bit so that Gfx can down
3841 * 5. Unmask Turbo interrupts
3843 static void vlv_set_rps_idle(struct drm_i915_private
*dev_priv
)
3845 struct drm_device
*dev
= dev_priv
->dev
;
3847 /* CHV and latest VLV don't need to force the gfx clock */
3848 if (IS_CHERRYVIEW(dev
) || dev
->pdev
->revision
>= 0xd) {
3849 valleyview_set_rps(dev_priv
->dev
, dev_priv
->rps
.min_freq_softlimit
);
3854 * When we are idle. Drop to min voltage state.
3857 if (dev_priv
->rps
.cur_freq
<= dev_priv
->rps
.min_freq_softlimit
)
3860 /* Mask turbo interrupt so that they will not come in between */
3861 I915_WRITE(GEN6_PMINTRMSK
,
3862 gen6_sanitize_rps_pm_mask(dev_priv
, ~0));
3864 vlv_force_gfx_clock(dev_priv
, true);
3866 dev_priv
->rps
.cur_freq
= dev_priv
->rps
.min_freq_softlimit
;
3868 vlv_punit_write(dev_priv
, PUNIT_REG_GPU_FREQ_REQ
,
3869 dev_priv
->rps
.min_freq_softlimit
);
3871 if (wait_for(((vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
))
3872 & GENFREQSTATUS
) == 0, 100))
3873 DRM_ERROR("timed out waiting for Punit\n");
3875 vlv_force_gfx_clock(dev_priv
, false);
3877 I915_WRITE(GEN6_PMINTRMSK
,
3878 gen6_rps_pm_mask(dev_priv
, dev_priv
->rps
.cur_freq
));
3881 void gen6_rps_idle(struct drm_i915_private
*dev_priv
)
3883 struct drm_device
*dev
= dev_priv
->dev
;
3885 mutex_lock(&dev_priv
->rps
.hw_lock
);
3886 if (dev_priv
->rps
.enabled
) {
3887 if (IS_VALLEYVIEW(dev
))
3888 vlv_set_rps_idle(dev_priv
);
3890 gen6_set_rps(dev_priv
->dev
, dev_priv
->rps
.min_freq_softlimit
);
3891 dev_priv
->rps
.last_adj
= 0;
3893 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3896 void gen6_rps_boost(struct drm_i915_private
*dev_priv
)
3898 mutex_lock(&dev_priv
->rps
.hw_lock
);
3899 if (dev_priv
->rps
.enabled
) {
3900 intel_set_rps(dev_priv
->dev
, dev_priv
->rps
.max_freq_softlimit
);
3901 dev_priv
->rps
.last_adj
= 0;
3903 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3906 void intel_set_rps(struct drm_device
*dev
, u8 val
)
3908 if (IS_VALLEYVIEW(dev
))
3909 valleyview_set_rps(dev
, val
);
3911 gen6_set_rps(dev
, val
);
3914 static void gen9_disable_rps(struct drm_device
*dev
)
3916 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3918 I915_WRITE(GEN6_RC_CONTROL
, 0);
3919 I915_WRITE(GEN9_PG_ENABLE
, 0);
3922 static void gen6_disable_rps(struct drm_device
*dev
)
3924 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3926 I915_WRITE(GEN6_RC_CONTROL
, 0);
3927 I915_WRITE(GEN6_RPNSWREQ
, 1 << 31);
3930 static void cherryview_disable_rps(struct drm_device
*dev
)
3932 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3934 I915_WRITE(GEN6_RC_CONTROL
, 0);
3937 static void valleyview_disable_rps(struct drm_device
*dev
)
3939 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3941 /* we're doing forcewake before Disabling RC6,
3942 * This what the BIOS expects when going into suspend */
3943 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
3945 I915_WRITE(GEN6_RC_CONTROL
, 0);
3947 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
3950 static void intel_print_rc6_info(struct drm_device
*dev
, u32 mode
)
3952 if (IS_VALLEYVIEW(dev
)) {
3953 if (mode
& (GEN7_RC_CTL_TO_MODE
| GEN6_RC_CTL_EI_MODE(1)))
3954 mode
= GEN6_RC_CTL_RC6_ENABLE
;
3959 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
3960 (mode
& GEN6_RC_CTL_RC6_ENABLE
) ? "on" : "off",
3961 (mode
& GEN6_RC_CTL_RC6p_ENABLE
) ? "on" : "off",
3962 (mode
& GEN6_RC_CTL_RC6pp_ENABLE
) ? "on" : "off");
3965 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
3966 (mode
& GEN6_RC_CTL_RC6_ENABLE
) ? "on" : "off");
3969 static int sanitize_rc6_option(const struct drm_device
*dev
, int enable_rc6
)
3971 /* No RC6 before Ironlake */
3972 if (INTEL_INFO(dev
)->gen
< 5)
3975 /* RC6 is only on Ironlake mobile not on desktop */
3976 if (INTEL_INFO(dev
)->gen
== 5 && !IS_IRONLAKE_M(dev
))
3979 /* Respect the kernel parameter if it is set */
3980 if (enable_rc6
>= 0) {
3984 mask
= INTEL_RC6_ENABLE
| INTEL_RC6p_ENABLE
|
3987 mask
= INTEL_RC6_ENABLE
;
3989 if ((enable_rc6
& mask
) != enable_rc6
)
3990 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
3991 enable_rc6
& mask
, enable_rc6
, mask
);
3993 return enable_rc6
& mask
;
3996 /* Disable RC6 on Ironlake */
3997 if (INTEL_INFO(dev
)->gen
== 5)
4000 if (IS_IVYBRIDGE(dev
))
4001 return (INTEL_RC6_ENABLE
| INTEL_RC6p_ENABLE
);
4003 return INTEL_RC6_ENABLE
;
4006 int intel_enable_rc6(const struct drm_device
*dev
)
4008 return i915
.enable_rc6
;
4011 static void gen6_init_rps_frequencies(struct drm_device
*dev
)
4013 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4014 uint32_t rp_state_cap
;
4015 u32 ddcc_status
= 0;
4018 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
4019 /* All of these values are in units of 50MHz */
4020 dev_priv
->rps
.cur_freq
= 0;
4021 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
4022 dev_priv
->rps
.rp0_freq
= (rp_state_cap
>> 0) & 0xff;
4023 dev_priv
->rps
.rp1_freq
= (rp_state_cap
>> 8) & 0xff;
4024 dev_priv
->rps
.min_freq
= (rp_state_cap
>> 16) & 0xff;
4025 /* hw_max = RP0 until we check for overclocking */
4026 dev_priv
->rps
.max_freq
= dev_priv
->rps
.rp0_freq
;
4028 dev_priv
->rps
.efficient_freq
= dev_priv
->rps
.rp1_freq
;
4029 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
4030 ret
= sandybridge_pcode_read(dev_priv
,
4031 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL
,
4034 dev_priv
->rps
.efficient_freq
=
4036 ((ddcc_status
>> 8) & 0xff),
4037 dev_priv
->rps
.min_freq
,
4038 dev_priv
->rps
.max_freq
);
4041 /* Preserve min/max settings in case of re-init */
4042 if (dev_priv
->rps
.max_freq_softlimit
== 0)
4043 dev_priv
->rps
.max_freq_softlimit
= dev_priv
->rps
.max_freq
;
4045 if (dev_priv
->rps
.min_freq_softlimit
== 0) {
4046 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
4047 dev_priv
->rps
.min_freq_softlimit
=
4048 /* max(RPe, 450 MHz) */
4049 max(dev_priv
->rps
.efficient_freq
, (u8
) 9);
4051 dev_priv
->rps
.min_freq_softlimit
=
4052 dev_priv
->rps
.min_freq
;
4056 /* See the Gen9_GT_PM_Programming_Guide doc for the below */
4057 static void gen9_enable_rps(struct drm_device
*dev
)
4059 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4061 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
4063 gen6_init_rps_frequencies(dev
);
4065 I915_WRITE(GEN6_RPNSWREQ
, 0xc800000);
4066 I915_WRITE(GEN6_RC_VIDEO_FREQ
, 0xc800000);
4068 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 0xf4240);
4069 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS
, 0x12060000);
4070 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 0xe808);
4071 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 0x3bd08);
4072 I915_WRITE(GEN6_RP_UP_EI
, 0x101d0);
4073 I915_WRITE(GEN6_RP_DOWN_EI
, 0x55730);
4074 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 0xa);
4075 I915_WRITE(GEN6_PMINTRMSK
, 0x6);
4076 I915_WRITE(GEN6_RP_CONTROL
, GEN6_RP_MEDIA_TURBO
|
4077 GEN6_RP_MEDIA_HW_MODE
| GEN6_RP_MEDIA_IS_GFX
|
4078 GEN6_RP_ENABLE
| GEN6_RP_UP_BUSY_AVG
|
4079 GEN6_RP_DOWN_IDLE_AVG
);
4081 gen6_enable_rps_interrupts(dev
);
4083 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
4086 static void gen9_enable_rc6(struct drm_device
*dev
)
4088 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4089 struct intel_engine_cs
*ring
;
4090 uint32_t rc6_mask
= 0;
4093 /* 1a: Software RC state - RC0 */
4094 I915_WRITE(GEN6_RC_STATE
, 0);
4096 /* 1b: Get forcewake during program sequence. Although the driver
4097 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4098 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
4100 /* 2a: Disable RC states. */
4101 I915_WRITE(GEN6_RC_CONTROL
, 0);
4103 /* 2b: Program RC6 thresholds.*/
4104 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 54 << 16);
4105 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000); /* 12500 * 1280ns */
4106 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25); /* 25 * 1280ns */
4107 for_each_ring(ring
, dev_priv
, unused
)
4108 I915_WRITE(RING_MAX_IDLE(ring
->mmio_base
), 10);
4109 I915_WRITE(GEN6_RC_SLEEP
, 0);
4110 I915_WRITE(GEN6_RC6_THRESHOLD
, 37500); /* 37.5/125ms per EI */
4112 /* 2c: Program Coarse Power Gating Policies. */
4113 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS
, 25);
4114 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS
, 25);
4116 /* 3a: Enable RC6 */
4117 if (intel_enable_rc6(dev
) & INTEL_RC6_ENABLE
)
4118 rc6_mask
= GEN6_RC_CTL_RC6_ENABLE
;
4119 DRM_INFO("RC6 %s\n", (rc6_mask
& GEN6_RC_CTL_RC6_ENABLE
) ?
4121 I915_WRITE(GEN6_RC_CONTROL
, GEN6_RC_CTL_HW_ENABLE
|
4122 GEN6_RC_CTL_EI_MODE(1) |
4125 /* 3b: Enable Coarse Power Gating only when RC6 is enabled */
4126 I915_WRITE(GEN9_PG_ENABLE
, (rc6_mask
& GEN6_RC_CTL_RC6_ENABLE
) ? 3 : 0);
4128 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
4132 static void gen8_enable_rps(struct drm_device
*dev
)
4134 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4135 struct intel_engine_cs
*ring
;
4136 uint32_t rc6_mask
= 0;
4139 /* 1a: Software RC state - RC0 */
4140 I915_WRITE(GEN6_RC_STATE
, 0);
4142 /* 1c & 1d: Get forcewake during program sequence. Although the driver
4143 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4144 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
4146 /* 2a: Disable RC states. */
4147 I915_WRITE(GEN6_RC_CONTROL
, 0);
4149 /* Initialize rps frequencies */
4150 gen6_init_rps_frequencies(dev
);
4152 /* 2b: Program RC6 thresholds.*/
4153 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 40 << 16);
4154 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000); /* 12500 * 1280ns */
4155 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25); /* 25 * 1280ns */
4156 for_each_ring(ring
, dev_priv
, unused
)
4157 I915_WRITE(RING_MAX_IDLE(ring
->mmio_base
), 10);
4158 I915_WRITE(GEN6_RC_SLEEP
, 0);
4159 if (IS_BROADWELL(dev
))
4160 I915_WRITE(GEN6_RC6_THRESHOLD
, 625); /* 800us/1.28 for TO */
4162 I915_WRITE(GEN6_RC6_THRESHOLD
, 50000); /* 50/125ms per EI */
4165 if (intel_enable_rc6(dev
) & INTEL_RC6_ENABLE
)
4166 rc6_mask
= GEN6_RC_CTL_RC6_ENABLE
;
4167 intel_print_rc6_info(dev
, rc6_mask
);
4168 if (IS_BROADWELL(dev
))
4169 I915_WRITE(GEN6_RC_CONTROL
, GEN6_RC_CTL_HW_ENABLE
|
4170 GEN7_RC_CTL_TO_MODE
|
4173 I915_WRITE(GEN6_RC_CONTROL
, GEN6_RC_CTL_HW_ENABLE
|
4174 GEN6_RC_CTL_EI_MODE(1) |
4177 /* 4 Program defaults and thresholds for RPS*/
4178 I915_WRITE(GEN6_RPNSWREQ
,
4179 HSW_FREQUENCY(dev_priv
->rps
.rp1_freq
));
4180 I915_WRITE(GEN6_RC_VIDEO_FREQ
,
4181 HSW_FREQUENCY(dev_priv
->rps
.rp1_freq
));
4182 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
4183 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 100000000 / 128); /* 1 second timeout */
4185 /* Docs recommend 900MHz, and 300 MHz respectively */
4186 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS
,
4187 dev_priv
->rps
.max_freq_softlimit
<< 24 |
4188 dev_priv
->rps
.min_freq_softlimit
<< 16);
4190 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 7600000 / 128); /* 76ms busyness per EI, 90% */
4191 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 31300000 / 128); /* 313ms busyness per EI, 70%*/
4192 I915_WRITE(GEN6_RP_UP_EI
, 66000); /* 84.48ms, XXX: random? */
4193 I915_WRITE(GEN6_RP_DOWN_EI
, 350000); /* 448ms, XXX: random? */
4195 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
4198 I915_WRITE(GEN6_RP_CONTROL
,
4199 GEN6_RP_MEDIA_TURBO
|
4200 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
4201 GEN6_RP_MEDIA_IS_GFX
|
4203 GEN6_RP_UP_BUSY_AVG
|
4204 GEN6_RP_DOWN_IDLE_AVG
);
4206 /* 6: Ring frequency + overclocking (our driver does this later */
4208 dev_priv
->rps
.power
= HIGH_POWER
; /* force a reset */
4209 gen6_set_rps(dev_priv
->dev
, dev_priv
->rps
.min_freq_softlimit
);
4211 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
4214 static void gen6_enable_rps(struct drm_device
*dev
)
4216 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4217 struct intel_engine_cs
*ring
;
4218 u32 rc6vids
, pcu_mbox
= 0, rc6_mask
= 0;
4223 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
4225 /* Here begins a magic sequence of register writes to enable
4226 * auto-downclocking.
4228 * Perhaps there might be some value in exposing these to
4231 I915_WRITE(GEN6_RC_STATE
, 0);
4233 /* Clear the DBG now so we don't confuse earlier errors */
4234 if ((gtfifodbg
= I915_READ(GTFIFODBG
))) {
4235 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg
);
4236 I915_WRITE(GTFIFODBG
, gtfifodbg
);
4239 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
4241 /* Initialize rps frequencies */
4242 gen6_init_rps_frequencies(dev
);
4244 /* disable the counters and set deterministic thresholds */
4245 I915_WRITE(GEN6_RC_CONTROL
, 0);
4247 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT
, 1000 << 16);
4248 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 40 << 16 | 30);
4249 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT
, 30);
4250 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000);
4251 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25);
4253 for_each_ring(ring
, dev_priv
, i
)
4254 I915_WRITE(RING_MAX_IDLE(ring
->mmio_base
), 10);
4256 I915_WRITE(GEN6_RC_SLEEP
, 0);
4257 I915_WRITE(GEN6_RC1e_THRESHOLD
, 1000);
4258 if (IS_IVYBRIDGE(dev
))
4259 I915_WRITE(GEN6_RC6_THRESHOLD
, 125000);
4261 I915_WRITE(GEN6_RC6_THRESHOLD
, 50000);
4262 I915_WRITE(GEN6_RC6p_THRESHOLD
, 150000);
4263 I915_WRITE(GEN6_RC6pp_THRESHOLD
, 64000); /* unused */
4265 /* Check if we are enabling RC6 */
4266 rc6_mode
= intel_enable_rc6(dev_priv
->dev
);
4267 if (rc6_mode
& INTEL_RC6_ENABLE
)
4268 rc6_mask
|= GEN6_RC_CTL_RC6_ENABLE
;
4270 /* We don't use those on Haswell */
4271 if (!IS_HASWELL(dev
)) {
4272 if (rc6_mode
& INTEL_RC6p_ENABLE
)
4273 rc6_mask
|= GEN6_RC_CTL_RC6p_ENABLE
;
4275 if (rc6_mode
& INTEL_RC6pp_ENABLE
)
4276 rc6_mask
|= GEN6_RC_CTL_RC6pp_ENABLE
;
4279 intel_print_rc6_info(dev
, rc6_mask
);
4281 I915_WRITE(GEN6_RC_CONTROL
,
4283 GEN6_RC_CTL_EI_MODE(1) |
4284 GEN6_RC_CTL_HW_ENABLE
);
4286 /* Power down if completely idle for over 50ms */
4287 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 50000);
4288 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
4290 ret
= sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_MIN_FREQ_TABLE
, 0);
4292 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
4294 ret
= sandybridge_pcode_read(dev_priv
, GEN6_READ_OC_PARAMS
, &pcu_mbox
);
4295 if (!ret
&& (pcu_mbox
& (1<<31))) { /* OC supported */
4296 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
4297 (dev_priv
->rps
.max_freq_softlimit
& 0xff) * 50,
4298 (pcu_mbox
& 0xff) * 50);
4299 dev_priv
->rps
.max_freq
= pcu_mbox
& 0xff;
4302 dev_priv
->rps
.power
= HIGH_POWER
; /* force a reset */
4303 gen6_set_rps(dev_priv
->dev
, dev_priv
->rps
.min_freq_softlimit
);
4306 ret
= sandybridge_pcode_read(dev_priv
, GEN6_PCODE_READ_RC6VIDS
, &rc6vids
);
4307 if (IS_GEN6(dev
) && ret
) {
4308 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
4309 } else if (IS_GEN6(dev
) && (GEN6_DECODE_RC6_VID(rc6vids
& 0xff) < 450)) {
4310 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
4311 GEN6_DECODE_RC6_VID(rc6vids
& 0xff), 450);
4312 rc6vids
&= 0xffff00;
4313 rc6vids
|= GEN6_ENCODE_RC6_VID(450);
4314 ret
= sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_RC6VIDS
, rc6vids
);
4316 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
4319 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
4322 static void __gen6_update_ring_freq(struct drm_device
*dev
)
4324 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4326 unsigned int gpu_freq
;
4327 unsigned int max_ia_freq
, min_ring_freq
;
4328 int scaling_factor
= 180;
4329 struct cpufreq_policy
*policy
;
4331 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
4333 policy
= cpufreq_cpu_get(0);
4335 max_ia_freq
= policy
->cpuinfo
.max_freq
;
4336 cpufreq_cpu_put(policy
);
4339 * Default to measured freq if none found, PCU will ensure we
4342 max_ia_freq
= tsc_khz
;
4345 /* Convert from kHz to MHz */
4346 max_ia_freq
/= 1000;
4348 min_ring_freq
= I915_READ(DCLK
) & 0xf;
4349 /* convert DDR frequency from units of 266.6MHz to bandwidth */
4350 min_ring_freq
= mult_frac(min_ring_freq
, 8, 3);
4353 * For each potential GPU frequency, load a ring frequency we'd like
4354 * to use for memory access. We do this by specifying the IA frequency
4355 * the PCU should use as a reference to determine the ring frequency.
4357 for (gpu_freq
= dev_priv
->rps
.max_freq
; gpu_freq
>= dev_priv
->rps
.min_freq
;
4359 int diff
= dev_priv
->rps
.max_freq
- gpu_freq
;
4360 unsigned int ia_freq
= 0, ring_freq
= 0;
4362 if (INTEL_INFO(dev
)->gen
>= 8) {
4363 /* max(2 * GT, DDR). NB: GT is 50MHz units */
4364 ring_freq
= max(min_ring_freq
, gpu_freq
);
4365 } else if (IS_HASWELL(dev
)) {
4366 ring_freq
= mult_frac(gpu_freq
, 5, 4);
4367 ring_freq
= max(min_ring_freq
, ring_freq
);
4368 /* leave ia_freq as the default, chosen by cpufreq */
4370 /* On older processors, there is no separate ring
4371 * clock domain, so in order to boost the bandwidth
4372 * of the ring, we need to upclock the CPU (ia_freq).
4374 * For GPU frequencies less than 750MHz,
4375 * just use the lowest ring freq.
4377 if (gpu_freq
< min_freq
)
4380 ia_freq
= max_ia_freq
- ((diff
* scaling_factor
) / 2);
4381 ia_freq
= DIV_ROUND_CLOSEST(ia_freq
, 100);
4384 sandybridge_pcode_write(dev_priv
,
4385 GEN6_PCODE_WRITE_MIN_FREQ_TABLE
,
4386 ia_freq
<< GEN6_PCODE_FREQ_IA_RATIO_SHIFT
|
4387 ring_freq
<< GEN6_PCODE_FREQ_RING_RATIO_SHIFT
|
4392 void gen6_update_ring_freq(struct drm_device
*dev
)
4394 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4396 if (INTEL_INFO(dev
)->gen
< 6 || IS_VALLEYVIEW(dev
))
4399 mutex_lock(&dev_priv
->rps
.hw_lock
);
4400 __gen6_update_ring_freq(dev
);
4401 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4404 static int cherryview_rps_max_freq(struct drm_i915_private
*dev_priv
)
4406 struct drm_device
*dev
= dev_priv
->dev
;
4409 if (dev
->pdev
->revision
>= 0x20) {
4410 val
= vlv_punit_read(dev_priv
, FB_GFX_FMAX_AT_VMAX_FUSE
);
4412 switch (INTEL_INFO(dev
)->eu_total
) {
4414 /* (2 * 4) config */
4415 rp0
= (val
>> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT
);
4418 /* (2 * 6) config */
4419 rp0
= (val
>> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT
);
4422 /* (2 * 8) config */
4424 /* Setting (2 * 8) Min RP0 for any other combination */
4425 rp0
= (val
>> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT
);
4428 rp0
= (rp0
& FB_GFX_FREQ_FUSE_MASK
);
4430 /* For pre-production hardware */
4431 val
= vlv_punit_read(dev_priv
, PUNIT_GPU_STATUS_REG
);
4432 rp0
= (val
>> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT
) &
4433 PUNIT_GPU_STATUS_MAX_FREQ_MASK
;
4438 static int cherryview_rps_rpe_freq(struct drm_i915_private
*dev_priv
)
4442 val
= vlv_punit_read(dev_priv
, PUNIT_GPU_DUTYCYCLE_REG
);
4443 rpe
= (val
>> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT
) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK
;
4448 static int cherryview_rps_guar_freq(struct drm_i915_private
*dev_priv
)
4450 struct drm_device
*dev
= dev_priv
->dev
;
4453 if (dev
->pdev
->revision
>= 0x20) {
4454 val
= vlv_punit_read(dev_priv
, FB_GFX_FMAX_AT_VMAX_FUSE
);
4455 rp1
= (val
& FB_GFX_FREQ_FUSE_MASK
);
4457 /* For pre-production hardware */
4458 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
4459 rp1
= ((val
>> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT
) &
4460 PUNIT_GPU_STATUS_MAX_FREQ_MASK
);
4465 static int cherryview_rps_min_freq(struct drm_i915_private
*dev_priv
)
4467 struct drm_device
*dev
= dev_priv
->dev
;
4470 if (dev
->pdev
->revision
>= 0x20) {
4471 val
= vlv_punit_read(dev_priv
, FB_GFX_FMIN_AT_VMIN_FUSE
);
4472 rpn
= ((val
>> FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT
) &
4473 FB_GFX_FREQ_FUSE_MASK
);
4474 } else { /* For pre-production hardware */
4475 val
= vlv_punit_read(dev_priv
, PUNIT_GPU_STATUS_REG
);
4476 rpn
= ((val
>> PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT
) &
4477 PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK
);
4483 static int valleyview_rps_guar_freq(struct drm_i915_private
*dev_priv
)
4487 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FREQ_FUSE
);
4489 rp1
= (val
& FB_GFX_FGUARANTEED_FREQ_FUSE_MASK
) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT
;
4494 static int valleyview_rps_max_freq(struct drm_i915_private
*dev_priv
)
4498 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FREQ_FUSE
);
4500 rp0
= (val
& FB_GFX_MAX_FREQ_FUSE_MASK
) >> FB_GFX_MAX_FREQ_FUSE_SHIFT
;
4502 rp0
= min_t(u32
, rp0
, 0xea);
4507 static int valleyview_rps_rpe_freq(struct drm_i915_private
*dev_priv
)
4511 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FMAX_FUSE_LO
);
4512 rpe
= (val
& FB_FMAX_VMIN_FREQ_LO_MASK
) >> FB_FMAX_VMIN_FREQ_LO_SHIFT
;
4513 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FMAX_FUSE_HI
);
4514 rpe
|= (val
& FB_FMAX_VMIN_FREQ_HI_MASK
) << 5;
4519 static int valleyview_rps_min_freq(struct drm_i915_private
*dev_priv
)
4521 return vlv_punit_read(dev_priv
, PUNIT_REG_GPU_LFM
) & 0xff;
4524 /* Check that the pctx buffer wasn't move under us. */
4525 static void valleyview_check_pctx(struct drm_i915_private
*dev_priv
)
4527 unsigned long pctx_addr
= I915_READ(VLV_PCBR
) & ~4095;
4529 WARN_ON(pctx_addr
!= dev_priv
->mm
.stolen_base
+
4530 dev_priv
->vlv_pctx
->stolen
->start
);
4534 /* Check that the pcbr address is not empty. */
4535 static void cherryview_check_pctx(struct drm_i915_private
*dev_priv
)
4537 unsigned long pctx_addr
= I915_READ(VLV_PCBR
) & ~4095;
4539 WARN_ON((pctx_addr
>> VLV_PCBR_ADDR_SHIFT
) == 0);
4542 static void cherryview_setup_pctx(struct drm_device
*dev
)
4544 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4545 unsigned long pctx_paddr
, paddr
;
4546 struct i915_gtt
*gtt
= &dev_priv
->gtt
;
4548 int pctx_size
= 32*1024;
4550 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
4552 pcbr
= I915_READ(VLV_PCBR
);
4553 if ((pcbr
>> VLV_PCBR_ADDR_SHIFT
) == 0) {
4554 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
4555 paddr
= (dev_priv
->mm
.stolen_base
+
4556 (gtt
->stolen_size
- pctx_size
));
4558 pctx_paddr
= (paddr
& (~4095));
4559 I915_WRITE(VLV_PCBR
, pctx_paddr
);
4562 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR
));
4565 static void valleyview_setup_pctx(struct drm_device
*dev
)
4567 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4568 struct drm_i915_gem_object
*pctx
;
4569 unsigned long pctx_paddr
;
4571 int pctx_size
= 24*1024;
4573 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
4575 pcbr
= I915_READ(VLV_PCBR
);
4577 /* BIOS set it up already, grab the pre-alloc'd space */
4580 pcbr_offset
= (pcbr
& (~4095)) - dev_priv
->mm
.stolen_base
;
4581 pctx
= i915_gem_object_create_stolen_for_preallocated(dev_priv
->dev
,
4583 I915_GTT_OFFSET_NONE
,
4588 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
4591 * From the Gunit register HAS:
4592 * The Gfx driver is expected to program this register and ensure
4593 * proper allocation within Gfx stolen memory. For example, this
4594 * register should be programmed such than the PCBR range does not
4595 * overlap with other ranges, such as the frame buffer, protected
4596 * memory, or any other relevant ranges.
4598 pctx
= i915_gem_object_create_stolen(dev
, pctx_size
);
4600 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
4604 pctx_paddr
= dev_priv
->mm
.stolen_base
+ pctx
->stolen
->start
;
4605 I915_WRITE(VLV_PCBR
, pctx_paddr
);
4608 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR
));
4609 dev_priv
->vlv_pctx
= pctx
;
4612 static void valleyview_cleanup_pctx(struct drm_device
*dev
)
4614 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4616 if (WARN_ON(!dev_priv
->vlv_pctx
))
4619 drm_gem_object_unreference(&dev_priv
->vlv_pctx
->base
);
4620 dev_priv
->vlv_pctx
= NULL
;
4623 static void valleyview_init_gt_powersave(struct drm_device
*dev
)
4625 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4628 valleyview_setup_pctx(dev
);
4630 mutex_lock(&dev_priv
->rps
.hw_lock
);
4632 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
4633 switch ((val
>> 6) & 3) {
4636 dev_priv
->mem_freq
= 800;
4639 dev_priv
->mem_freq
= 1066;
4642 dev_priv
->mem_freq
= 1333;
4645 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv
->mem_freq
);
4647 dev_priv
->rps
.max_freq
= valleyview_rps_max_freq(dev_priv
);
4648 dev_priv
->rps
.rp0_freq
= dev_priv
->rps
.max_freq
;
4649 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
4650 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
),
4651 dev_priv
->rps
.max_freq
);
4653 dev_priv
->rps
.efficient_freq
= valleyview_rps_rpe_freq(dev_priv
);
4654 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
4655 intel_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
),
4656 dev_priv
->rps
.efficient_freq
);
4658 dev_priv
->rps
.rp1_freq
= valleyview_rps_guar_freq(dev_priv
);
4659 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
4660 intel_gpu_freq(dev_priv
, dev_priv
->rps
.rp1_freq
),
4661 dev_priv
->rps
.rp1_freq
);
4663 dev_priv
->rps
.min_freq
= valleyview_rps_min_freq(dev_priv
);
4664 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
4665 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
),
4666 dev_priv
->rps
.min_freq
);
4668 /* Preserve min/max settings in case of re-init */
4669 if (dev_priv
->rps
.max_freq_softlimit
== 0)
4670 dev_priv
->rps
.max_freq_softlimit
= dev_priv
->rps
.max_freq
;
4672 if (dev_priv
->rps
.min_freq_softlimit
== 0)
4673 dev_priv
->rps
.min_freq_softlimit
= dev_priv
->rps
.min_freq
;
4675 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4678 static void cherryview_init_gt_powersave(struct drm_device
*dev
)
4680 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4683 cherryview_setup_pctx(dev
);
4685 mutex_lock(&dev_priv
->rps
.hw_lock
);
4687 mutex_lock(&dev_priv
->dpio_lock
);
4688 val
= vlv_cck_read(dev_priv
, CCK_FUSE_REG
);
4689 mutex_unlock(&dev_priv
->dpio_lock
);
4691 switch ((val
>> 2) & 0x7) {
4694 dev_priv
->rps
.cz_freq
= 200;
4695 dev_priv
->mem_freq
= 1600;
4698 dev_priv
->rps
.cz_freq
= 267;
4699 dev_priv
->mem_freq
= 1600;
4702 dev_priv
->rps
.cz_freq
= 333;
4703 dev_priv
->mem_freq
= 2000;
4706 dev_priv
->rps
.cz_freq
= 320;
4707 dev_priv
->mem_freq
= 1600;
4710 dev_priv
->rps
.cz_freq
= 400;
4711 dev_priv
->mem_freq
= 1600;
4714 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv
->mem_freq
);
4716 dev_priv
->rps
.max_freq
= cherryview_rps_max_freq(dev_priv
);
4717 dev_priv
->rps
.rp0_freq
= dev_priv
->rps
.max_freq
;
4718 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
4719 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
),
4720 dev_priv
->rps
.max_freq
);
4722 dev_priv
->rps
.efficient_freq
= cherryview_rps_rpe_freq(dev_priv
);
4723 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
4724 intel_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
),
4725 dev_priv
->rps
.efficient_freq
);
4727 dev_priv
->rps
.rp1_freq
= cherryview_rps_guar_freq(dev_priv
);
4728 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
4729 intel_gpu_freq(dev_priv
, dev_priv
->rps
.rp1_freq
),
4730 dev_priv
->rps
.rp1_freq
);
4732 dev_priv
->rps
.min_freq
= cherryview_rps_min_freq(dev_priv
);
4733 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
4734 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
),
4735 dev_priv
->rps
.min_freq
);
4737 WARN_ONCE((dev_priv
->rps
.max_freq
|
4738 dev_priv
->rps
.efficient_freq
|
4739 dev_priv
->rps
.rp1_freq
|
4740 dev_priv
->rps
.min_freq
) & 1,
4741 "Odd GPU freq values\n");
4743 /* Preserve min/max settings in case of re-init */
4744 if (dev_priv
->rps
.max_freq_softlimit
== 0)
4745 dev_priv
->rps
.max_freq_softlimit
= dev_priv
->rps
.max_freq
;
4747 if (dev_priv
->rps
.min_freq_softlimit
== 0)
4748 dev_priv
->rps
.min_freq_softlimit
= dev_priv
->rps
.min_freq
;
4750 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4753 static void valleyview_cleanup_gt_powersave(struct drm_device
*dev
)
4755 valleyview_cleanup_pctx(dev
);
4758 static void cherryview_enable_rps(struct drm_device
*dev
)
4760 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4761 struct intel_engine_cs
*ring
;
4762 u32 gtfifodbg
, val
, rc6_mode
= 0, pcbr
;
4765 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
4767 gtfifodbg
= I915_READ(GTFIFODBG
);
4769 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4771 I915_WRITE(GTFIFODBG
, gtfifodbg
);
4774 cherryview_check_pctx(dev_priv
);
4776 /* 1a & 1b: Get forcewake during program sequence. Although the driver
4777 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4778 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
4780 /* Disable RC states. */
4781 I915_WRITE(GEN6_RC_CONTROL
, 0);
4783 /* 2a: Program RC6 thresholds.*/
4784 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 40 << 16);
4785 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000); /* 12500 * 1280ns */
4786 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25); /* 25 * 1280ns */
4788 for_each_ring(ring
, dev_priv
, i
)
4789 I915_WRITE(RING_MAX_IDLE(ring
->mmio_base
), 10);
4790 I915_WRITE(GEN6_RC_SLEEP
, 0);
4792 /* TO threshold set to 1750 us ( 0x557 * 1.28 us) */
4793 I915_WRITE(GEN6_RC6_THRESHOLD
, 0x557);
4795 /* allows RC6 residency counter to work */
4796 I915_WRITE(VLV_COUNTER_CONTROL
,
4797 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH
|
4798 VLV_MEDIA_RC6_COUNT_EN
|
4799 VLV_RENDER_RC6_COUNT_EN
));
4801 /* For now we assume BIOS is allocating and populating the PCBR */
4802 pcbr
= I915_READ(VLV_PCBR
);
4805 if ((intel_enable_rc6(dev
) & INTEL_RC6_ENABLE
) &&
4806 (pcbr
>> VLV_PCBR_ADDR_SHIFT
))
4807 rc6_mode
= GEN7_RC_CTL_TO_MODE
;
4809 I915_WRITE(GEN6_RC_CONTROL
, rc6_mode
);
4811 /* 4 Program defaults and thresholds for RPS*/
4812 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 1000000);
4813 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 59400);
4814 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 245000);
4815 I915_WRITE(GEN6_RP_UP_EI
, 66000);
4816 I915_WRITE(GEN6_RP_DOWN_EI
, 350000);
4818 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
4821 I915_WRITE(GEN6_RP_CONTROL
,
4822 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
4823 GEN6_RP_MEDIA_IS_GFX
|
4825 GEN6_RP_UP_BUSY_AVG
|
4826 GEN6_RP_DOWN_IDLE_AVG
);
4828 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
4830 /* RPS code assumes GPLL is used */
4831 WARN_ONCE((val
& GPLLENABLE
) == 0, "GPLL not enabled\n");
4833 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val
& GPLLENABLE
? "yes" : "no");
4834 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val
);
4836 dev_priv
->rps
.cur_freq
= (val
>> 8) & 0xff;
4837 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
4838 intel_gpu_freq(dev_priv
, dev_priv
->rps
.cur_freq
),
4839 dev_priv
->rps
.cur_freq
);
4841 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
4842 intel_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
),
4843 dev_priv
->rps
.efficient_freq
);
4845 valleyview_set_rps(dev_priv
->dev
, dev_priv
->rps
.efficient_freq
);
4847 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
4850 static void valleyview_enable_rps(struct drm_device
*dev
)
4852 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4853 struct intel_engine_cs
*ring
;
4854 u32 gtfifodbg
, val
, rc6_mode
= 0;
4857 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
4859 valleyview_check_pctx(dev_priv
);
4861 if ((gtfifodbg
= I915_READ(GTFIFODBG
))) {
4862 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4864 I915_WRITE(GTFIFODBG
, gtfifodbg
);
4867 /* If VLV, Forcewake all wells, else re-direct to regular path */
4868 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
4870 /* Disable RC states. */
4871 I915_WRITE(GEN6_RC_CONTROL
, 0);
4873 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 1000000);
4874 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 59400);
4875 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 245000);
4876 I915_WRITE(GEN6_RP_UP_EI
, 66000);
4877 I915_WRITE(GEN6_RP_DOWN_EI
, 350000);
4879 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
4881 I915_WRITE(GEN6_RP_CONTROL
,
4882 GEN6_RP_MEDIA_TURBO
|
4883 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
4884 GEN6_RP_MEDIA_IS_GFX
|
4886 GEN6_RP_UP_BUSY_AVG
|
4887 GEN6_RP_DOWN_IDLE_CONT
);
4889 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 0x00280000);
4890 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000);
4891 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25);
4893 for_each_ring(ring
, dev_priv
, i
)
4894 I915_WRITE(RING_MAX_IDLE(ring
->mmio_base
), 10);
4896 I915_WRITE(GEN6_RC6_THRESHOLD
, 0x557);
4898 /* allows RC6 residency counter to work */
4899 I915_WRITE(VLV_COUNTER_CONTROL
,
4900 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN
|
4901 VLV_RENDER_RC0_COUNT_EN
|
4902 VLV_MEDIA_RC6_COUNT_EN
|
4903 VLV_RENDER_RC6_COUNT_EN
));
4905 if (intel_enable_rc6(dev
) & INTEL_RC6_ENABLE
)
4906 rc6_mode
= GEN7_RC_CTL_TO_MODE
| VLV_RC_CTL_CTX_RST_PARALLEL
;
4908 intel_print_rc6_info(dev
, rc6_mode
);
4910 I915_WRITE(GEN6_RC_CONTROL
, rc6_mode
);
4912 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
4914 /* RPS code assumes GPLL is used */
4915 WARN_ONCE((val
& GPLLENABLE
) == 0, "GPLL not enabled\n");
4917 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val
& GPLLENABLE
? "yes" : "no");
4918 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val
);
4920 dev_priv
->rps
.cur_freq
= (val
>> 8) & 0xff;
4921 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
4922 intel_gpu_freq(dev_priv
, dev_priv
->rps
.cur_freq
),
4923 dev_priv
->rps
.cur_freq
);
4925 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
4926 intel_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
),
4927 dev_priv
->rps
.efficient_freq
);
4929 valleyview_set_rps(dev_priv
->dev
, dev_priv
->rps
.efficient_freq
);
4931 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
4934 static unsigned long intel_pxfreq(u32 vidfreq
)
4937 int div
= (vidfreq
& 0x3f0000) >> 16;
4938 int post
= (vidfreq
& 0x3000) >> 12;
4939 int pre
= (vidfreq
& 0x7);
4944 freq
= ((div
* 133333) / ((1<<post
) * pre
));
4949 static const struct cparams
{
4955 { 1, 1333, 301, 28664 },
4956 { 1, 1066, 294, 24460 },
4957 { 1, 800, 294, 25192 },
4958 { 0, 1333, 276, 27605 },
4959 { 0, 1066, 276, 27605 },
4960 { 0, 800, 231, 23784 },
4963 static unsigned long __i915_chipset_val(struct drm_i915_private
*dev_priv
)
4965 u64 total_count
, diff
, ret
;
4966 u32 count1
, count2
, count3
, m
= 0, c
= 0;
4967 unsigned long now
= jiffies_to_msecs(jiffies
), diff1
;
4970 assert_spin_locked(&mchdev_lock
);
4972 diff1
= now
- dev_priv
->ips
.last_time1
;
4974 /* Prevent division-by-zero if we are asking too fast.
4975 * Also, we don't get interesting results if we are polling
4976 * faster than once in 10ms, so just return the saved value
4980 return dev_priv
->ips
.chipset_power
;
4982 count1
= I915_READ(DMIEC
);
4983 count2
= I915_READ(DDREC
);
4984 count3
= I915_READ(CSIEC
);
4986 total_count
= count1
+ count2
+ count3
;
4988 /* FIXME: handle per-counter overflow */
4989 if (total_count
< dev_priv
->ips
.last_count1
) {
4990 diff
= ~0UL - dev_priv
->ips
.last_count1
;
4991 diff
+= total_count
;
4993 diff
= total_count
- dev_priv
->ips
.last_count1
;
4996 for (i
= 0; i
< ARRAY_SIZE(cparams
); i
++) {
4997 if (cparams
[i
].i
== dev_priv
->ips
.c_m
&&
4998 cparams
[i
].t
== dev_priv
->ips
.r_t
) {
5005 diff
= div_u64(diff
, diff1
);
5006 ret
= ((m
* diff
) + c
);
5007 ret
= div_u64(ret
, 10);
5009 dev_priv
->ips
.last_count1
= total_count
;
5010 dev_priv
->ips
.last_time1
= now
;
5012 dev_priv
->ips
.chipset_power
= ret
;
5017 unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
)
5019 struct drm_device
*dev
= dev_priv
->dev
;
5022 if (INTEL_INFO(dev
)->gen
!= 5)
5025 spin_lock_irq(&mchdev_lock
);
5027 val
= __i915_chipset_val(dev_priv
);
5029 spin_unlock_irq(&mchdev_lock
);
5034 unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
)
5036 unsigned long m
, x
, b
;
5039 tsfs
= I915_READ(TSFS
);
5041 m
= ((tsfs
& TSFS_SLOPE_MASK
) >> TSFS_SLOPE_SHIFT
);
5042 x
= I915_READ8(TR1
);
5044 b
= tsfs
& TSFS_INTR_MASK
;
5046 return ((m
* x
) / 127) - b
;
5049 static int _pxvid_to_vd(u8 pxvid
)
5054 if (pxvid
>= 8 && pxvid
< 31)
5057 return (pxvid
+ 2) * 125;
5060 static u32
pvid_to_extvid(struct drm_i915_private
*dev_priv
, u8 pxvid
)
5062 struct drm_device
*dev
= dev_priv
->dev
;
5063 const int vd
= _pxvid_to_vd(pxvid
);
5064 const int vm
= vd
- 1125;
5066 if (INTEL_INFO(dev
)->is_mobile
)
5067 return vm
> 0 ? vm
: 0;
5072 static void __i915_update_gfx_val(struct drm_i915_private
*dev_priv
)
5074 u64 now
, diff
, diffms
;
5077 assert_spin_locked(&mchdev_lock
);
5079 now
= ktime_get_raw_ns();
5080 diffms
= now
- dev_priv
->ips
.last_time2
;
5081 do_div(diffms
, NSEC_PER_MSEC
);
5083 /* Don't divide by 0 */
5087 count
= I915_READ(GFXEC
);
5089 if (count
< dev_priv
->ips
.last_count2
) {
5090 diff
= ~0UL - dev_priv
->ips
.last_count2
;
5093 diff
= count
- dev_priv
->ips
.last_count2
;
5096 dev_priv
->ips
.last_count2
= count
;
5097 dev_priv
->ips
.last_time2
= now
;
5099 /* More magic constants... */
5101 diff
= div_u64(diff
, diffms
* 10);
5102 dev_priv
->ips
.gfx_power
= diff
;
5105 void i915_update_gfx_val(struct drm_i915_private
*dev_priv
)
5107 struct drm_device
*dev
= dev_priv
->dev
;
5109 if (INTEL_INFO(dev
)->gen
!= 5)
5112 spin_lock_irq(&mchdev_lock
);
5114 __i915_update_gfx_val(dev_priv
);
5116 spin_unlock_irq(&mchdev_lock
);
5119 static unsigned long __i915_gfx_val(struct drm_i915_private
*dev_priv
)
5121 unsigned long t
, corr
, state1
, corr2
, state2
;
5124 assert_spin_locked(&mchdev_lock
);
5126 pxvid
= I915_READ(PXVFREQ_BASE
+ (dev_priv
->rps
.cur_freq
* 4));
5127 pxvid
= (pxvid
>> 24) & 0x7f;
5128 ext_v
= pvid_to_extvid(dev_priv
, pxvid
);
5132 t
= i915_mch_val(dev_priv
);
5134 /* Revel in the empirically derived constants */
5136 /* Correction factor in 1/100000 units */
5138 corr
= ((t
* 2349) + 135940);
5140 corr
= ((t
* 964) + 29317);
5142 corr
= ((t
* 301) + 1004);
5144 corr
= corr
* ((150142 * state1
) / 10000 - 78642);
5146 corr2
= (corr
* dev_priv
->ips
.corr
);
5148 state2
= (corr2
* state1
) / 10000;
5149 state2
/= 100; /* convert to mW */
5151 __i915_update_gfx_val(dev_priv
);
5153 return dev_priv
->ips
.gfx_power
+ state2
;
5156 unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
)
5158 struct drm_device
*dev
= dev_priv
->dev
;
5161 if (INTEL_INFO(dev
)->gen
!= 5)
5164 spin_lock_irq(&mchdev_lock
);
5166 val
= __i915_gfx_val(dev_priv
);
5168 spin_unlock_irq(&mchdev_lock
);
5174 * i915_read_mch_val - return value for IPS use
5176 * Calculate and return a value for the IPS driver to use when deciding whether
5177 * we have thermal and power headroom to increase CPU or GPU power budget.
5179 unsigned long i915_read_mch_val(void)
5181 struct drm_i915_private
*dev_priv
;
5182 unsigned long chipset_val
, graphics_val
, ret
= 0;
5184 spin_lock_irq(&mchdev_lock
);
5187 dev_priv
= i915_mch_dev
;
5189 chipset_val
= __i915_chipset_val(dev_priv
);
5190 graphics_val
= __i915_gfx_val(dev_priv
);
5192 ret
= chipset_val
+ graphics_val
;
5195 spin_unlock_irq(&mchdev_lock
);
5199 EXPORT_SYMBOL_GPL(i915_read_mch_val
);
5202 * i915_gpu_raise - raise GPU frequency limit
5204 * Raise the limit; IPS indicates we have thermal headroom.
5206 bool i915_gpu_raise(void)
5208 struct drm_i915_private
*dev_priv
;
5211 spin_lock_irq(&mchdev_lock
);
5212 if (!i915_mch_dev
) {
5216 dev_priv
= i915_mch_dev
;
5218 if (dev_priv
->ips
.max_delay
> dev_priv
->ips
.fmax
)
5219 dev_priv
->ips
.max_delay
--;
5222 spin_unlock_irq(&mchdev_lock
);
5226 EXPORT_SYMBOL_GPL(i915_gpu_raise
);
5229 * i915_gpu_lower - lower GPU frequency limit
5231 * IPS indicates we're close to a thermal limit, so throttle back the GPU
5232 * frequency maximum.
5234 bool i915_gpu_lower(void)
5236 struct drm_i915_private
*dev_priv
;
5239 spin_lock_irq(&mchdev_lock
);
5240 if (!i915_mch_dev
) {
5244 dev_priv
= i915_mch_dev
;
5246 if (dev_priv
->ips
.max_delay
< dev_priv
->ips
.min_delay
)
5247 dev_priv
->ips
.max_delay
++;
5250 spin_unlock_irq(&mchdev_lock
);
5254 EXPORT_SYMBOL_GPL(i915_gpu_lower
);
5257 * i915_gpu_busy - indicate GPU business to IPS
5259 * Tell the IPS driver whether or not the GPU is busy.
5261 bool i915_gpu_busy(void)
5263 struct drm_i915_private
*dev_priv
;
5264 struct intel_engine_cs
*ring
;
5268 spin_lock_irq(&mchdev_lock
);
5271 dev_priv
= i915_mch_dev
;
5273 for_each_ring(ring
, dev_priv
, i
)
5274 ret
|= !list_empty(&ring
->request_list
);
5277 spin_unlock_irq(&mchdev_lock
);
5281 EXPORT_SYMBOL_GPL(i915_gpu_busy
);
5284 * i915_gpu_turbo_disable - disable graphics turbo
5286 * Disable graphics turbo by resetting the max frequency and setting the
5287 * current frequency to the default.
5289 bool i915_gpu_turbo_disable(void)
5291 struct drm_i915_private
*dev_priv
;
5294 spin_lock_irq(&mchdev_lock
);
5295 if (!i915_mch_dev
) {
5299 dev_priv
= i915_mch_dev
;
5301 dev_priv
->ips
.max_delay
= dev_priv
->ips
.fstart
;
5303 if (!ironlake_set_drps(dev_priv
->dev
, dev_priv
->ips
.fstart
))
5307 spin_unlock_irq(&mchdev_lock
);
5311 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable
);
5314 * Tells the intel_ips driver that the i915 driver is now loaded, if
5315 * IPS got loaded first.
5317 * This awkward dance is so that neither module has to depend on the
5318 * other in order for IPS to do the appropriate communication of
5319 * GPU turbo limits to i915.
5322 ips_ping_for_i915_load(void)
5326 link
= symbol_get(ips_link_to_i915_driver
);
5329 symbol_put(ips_link_to_i915_driver
);
5333 void intel_gpu_ips_init(struct drm_i915_private
*dev_priv
)
5335 /* We only register the i915 ips part with intel-ips once everything is
5336 * set up, to avoid intel-ips sneaking in and reading bogus values. */
5337 spin_lock_irq(&mchdev_lock
);
5338 i915_mch_dev
= dev_priv
;
5339 spin_unlock_irq(&mchdev_lock
);
5341 ips_ping_for_i915_load();
5344 void intel_gpu_ips_teardown(void)
5346 spin_lock_irq(&mchdev_lock
);
5347 i915_mch_dev
= NULL
;
5348 spin_unlock_irq(&mchdev_lock
);
5351 static void intel_init_emon(struct drm_device
*dev
)
5353 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5358 /* Disable to program */
5362 /* Program energy weights for various events */
5363 I915_WRITE(SDEW
, 0x15040d00);
5364 I915_WRITE(CSIEW0
, 0x007f0000);
5365 I915_WRITE(CSIEW1
, 0x1e220004);
5366 I915_WRITE(CSIEW2
, 0x04000004);
5368 for (i
= 0; i
< 5; i
++)
5369 I915_WRITE(PEW
+ (i
* 4), 0);
5370 for (i
= 0; i
< 3; i
++)
5371 I915_WRITE(DEW
+ (i
* 4), 0);
5373 /* Program P-state weights to account for frequency power adjustment */
5374 for (i
= 0; i
< 16; i
++) {
5375 u32 pxvidfreq
= I915_READ(PXVFREQ_BASE
+ (i
* 4));
5376 unsigned long freq
= intel_pxfreq(pxvidfreq
);
5377 unsigned long vid
= (pxvidfreq
& PXVFREQ_PX_MASK
) >>
5382 val
*= (freq
/ 1000);
5384 val
/= (127*127*900);
5386 DRM_ERROR("bad pxval: %ld\n", val
);
5389 /* Render standby states get 0 weight */
5393 for (i
= 0; i
< 4; i
++) {
5394 u32 val
= (pxw
[i
*4] << 24) | (pxw
[(i
*4)+1] << 16) |
5395 (pxw
[(i
*4)+2] << 8) | (pxw
[(i
*4)+3]);
5396 I915_WRITE(PXW
+ (i
* 4), val
);
5399 /* Adjust magic regs to magic values (more experimental results) */
5400 I915_WRITE(OGW0
, 0);
5401 I915_WRITE(OGW1
, 0);
5402 I915_WRITE(EG0
, 0x00007f00);
5403 I915_WRITE(EG1
, 0x0000000e);
5404 I915_WRITE(EG2
, 0x000e0000);
5405 I915_WRITE(EG3
, 0x68000300);
5406 I915_WRITE(EG4
, 0x42000000);
5407 I915_WRITE(EG5
, 0x00140031);
5411 for (i
= 0; i
< 8; i
++)
5412 I915_WRITE(PXWL
+ (i
* 4), 0);
5414 /* Enable PMON + select events */
5415 I915_WRITE(ECR
, 0x80000019);
5417 lcfuse
= I915_READ(LCFUSE02
);
5419 dev_priv
->ips
.corr
= (lcfuse
& LCFUSE_HIV_MASK
);
5422 void intel_init_gt_powersave(struct drm_device
*dev
)
5424 i915
.enable_rc6
= sanitize_rc6_option(dev
, i915
.enable_rc6
);
5426 if (IS_CHERRYVIEW(dev
))
5427 cherryview_init_gt_powersave(dev
);
5428 else if (IS_VALLEYVIEW(dev
))
5429 valleyview_init_gt_powersave(dev
);
5432 void intel_cleanup_gt_powersave(struct drm_device
*dev
)
5434 if (IS_CHERRYVIEW(dev
))
5436 else if (IS_VALLEYVIEW(dev
))
5437 valleyview_cleanup_gt_powersave(dev
);
5440 static void gen6_suspend_rps(struct drm_device
*dev
)
5442 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5444 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
5447 * TODO: disable RPS interrupts on GEN9+ too once RPS support
5450 if (INTEL_INFO(dev
)->gen
< 9)
5451 gen6_disable_rps_interrupts(dev
);
5455 * intel_suspend_gt_powersave - suspend PM work and helper threads
5458 * We don't want to disable RC6 or other features here, we just want
5459 * to make sure any work we've queued has finished and won't bother
5460 * us while we're suspended.
5462 void intel_suspend_gt_powersave(struct drm_device
*dev
)
5464 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5466 if (INTEL_INFO(dev
)->gen
< 6)
5469 gen6_suspend_rps(dev
);
5471 /* Force GPU to min freq during suspend */
5472 gen6_rps_idle(dev_priv
);
5475 void intel_disable_gt_powersave(struct drm_device
*dev
)
5477 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5479 if (IS_IRONLAKE_M(dev
)) {
5480 ironlake_disable_drps(dev
);
5481 } else if (INTEL_INFO(dev
)->gen
>= 6) {
5482 intel_suspend_gt_powersave(dev
);
5484 mutex_lock(&dev_priv
->rps
.hw_lock
);
5485 if (INTEL_INFO(dev
)->gen
>= 9)
5486 gen9_disable_rps(dev
);
5487 else if (IS_CHERRYVIEW(dev
))
5488 cherryview_disable_rps(dev
);
5489 else if (IS_VALLEYVIEW(dev
))
5490 valleyview_disable_rps(dev
);
5492 gen6_disable_rps(dev
);
5494 dev_priv
->rps
.enabled
= false;
5495 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5499 static void intel_gen6_powersave_work(struct work_struct
*work
)
5501 struct drm_i915_private
*dev_priv
=
5502 container_of(work
, struct drm_i915_private
,
5503 rps
.delayed_resume_work
.work
);
5504 struct drm_device
*dev
= dev_priv
->dev
;
5506 mutex_lock(&dev_priv
->rps
.hw_lock
);
5509 * TODO: reset/enable RPS interrupts on GEN9+ too, once RPS support is
5512 if (INTEL_INFO(dev
)->gen
< 9)
5513 gen6_reset_rps_interrupts(dev
);
5515 if (IS_CHERRYVIEW(dev
)) {
5516 cherryview_enable_rps(dev
);
5517 } else if (IS_VALLEYVIEW(dev
)) {
5518 valleyview_enable_rps(dev
);
5519 } else if (INTEL_INFO(dev
)->gen
>= 9) {
5520 gen9_enable_rc6(dev
);
5521 gen9_enable_rps(dev
);
5522 __gen6_update_ring_freq(dev
);
5523 } else if (IS_BROADWELL(dev
)) {
5524 gen8_enable_rps(dev
);
5525 __gen6_update_ring_freq(dev
);
5527 gen6_enable_rps(dev
);
5528 __gen6_update_ring_freq(dev
);
5530 dev_priv
->rps
.enabled
= true;
5532 if (INTEL_INFO(dev
)->gen
< 9)
5533 gen6_enable_rps_interrupts(dev
);
5535 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5537 intel_runtime_pm_put(dev_priv
);
5540 void intel_enable_gt_powersave(struct drm_device
*dev
)
5542 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5544 /* Powersaving is controlled by the host when inside a VM */
5545 if (intel_vgpu_active(dev
))
5548 if (IS_IRONLAKE_M(dev
)) {
5549 mutex_lock(&dev
->struct_mutex
);
5550 ironlake_enable_drps(dev
);
5551 intel_init_emon(dev
);
5552 mutex_unlock(&dev
->struct_mutex
);
5553 } else if (INTEL_INFO(dev
)->gen
>= 6) {
5555 * PCU communication is slow and this doesn't need to be
5556 * done at any specific time, so do this out of our fast path
5557 * to make resume and init faster.
5559 * We depend on the HW RC6 power context save/restore
5560 * mechanism when entering D3 through runtime PM suspend. So
5561 * disable RPM until RPS/RC6 is properly setup. We can only
5562 * get here via the driver load/system resume/runtime resume
5563 * paths, so the _noresume version is enough (and in case of
5564 * runtime resume it's necessary).
5566 if (schedule_delayed_work(&dev_priv
->rps
.delayed_resume_work
,
5567 round_jiffies_up_relative(HZ
)))
5568 intel_runtime_pm_get_noresume(dev_priv
);
5572 void intel_reset_gt_powersave(struct drm_device
*dev
)
5574 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5576 if (INTEL_INFO(dev
)->gen
< 6)
5579 gen6_suspend_rps(dev
);
5580 dev_priv
->rps
.enabled
= false;
5583 static void ibx_init_clock_gating(struct drm_device
*dev
)
5585 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5588 * On Ibex Peak and Cougar Point, we need to disable clock
5589 * gating for the panel power sequencer or it will fail to
5590 * start up when no ports are active.
5592 I915_WRITE(SOUTH_DSPCLK_GATE_D
, PCH_DPLSUNIT_CLOCK_GATE_DISABLE
);
5595 static void g4x_disable_trickle_feed(struct drm_device
*dev
)
5597 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5600 for_each_pipe(dev_priv
, pipe
) {
5601 I915_WRITE(DSPCNTR(pipe
),
5602 I915_READ(DSPCNTR(pipe
)) |
5603 DISPPLANE_TRICKLE_FEED_DISABLE
);
5604 intel_flush_primary_plane(dev_priv
, pipe
);
5608 static void ilk_init_lp_watermarks(struct drm_device
*dev
)
5610 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5612 I915_WRITE(WM3_LP_ILK
, I915_READ(WM3_LP_ILK
) & ~WM1_LP_SR_EN
);
5613 I915_WRITE(WM2_LP_ILK
, I915_READ(WM2_LP_ILK
) & ~WM1_LP_SR_EN
);
5614 I915_WRITE(WM1_LP_ILK
, I915_READ(WM1_LP_ILK
) & ~WM1_LP_SR_EN
);
5617 * Don't touch WM1S_LP_EN here.
5618 * Doing so could cause underruns.
5622 static void ironlake_init_clock_gating(struct drm_device
*dev
)
5624 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5625 uint32_t dspclk_gate
= ILK_VRHUNIT_CLOCK_GATE_DISABLE
;
5629 * WaFbcDisableDpfcClockGating:ilk
5631 dspclk_gate
|= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE
|
5632 ILK_DPFCUNIT_CLOCK_GATE_DISABLE
|
5633 ILK_DPFDUNIT_CLOCK_GATE_ENABLE
;
5635 I915_WRITE(PCH_3DCGDIS0
,
5636 MARIUNIT_CLOCK_GATE_DISABLE
|
5637 SVSMUNIT_CLOCK_GATE_DISABLE
);
5638 I915_WRITE(PCH_3DCGDIS1
,
5639 VFMUNIT_CLOCK_GATE_DISABLE
);
5642 * According to the spec the following bits should be set in
5643 * order to enable memory self-refresh
5644 * The bit 22/21 of 0x42004
5645 * The bit 5 of 0x42020
5646 * The bit 15 of 0x45000
5648 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
5649 (I915_READ(ILK_DISPLAY_CHICKEN2
) |
5650 ILK_DPARB_GATE
| ILK_VSDPFD_FULL
));
5651 dspclk_gate
|= ILK_DPARBUNIT_CLOCK_GATE_ENABLE
;
5652 I915_WRITE(DISP_ARB_CTL
,
5653 (I915_READ(DISP_ARB_CTL
) |
5656 ilk_init_lp_watermarks(dev
);
5659 * Based on the document from hardware guys the following bits
5660 * should be set unconditionally in order to enable FBC.
5661 * The bit 22 of 0x42000
5662 * The bit 22 of 0x42004
5663 * The bit 7,8,9 of 0x42020.
5665 if (IS_IRONLAKE_M(dev
)) {
5666 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
5667 I915_WRITE(ILK_DISPLAY_CHICKEN1
,
5668 I915_READ(ILK_DISPLAY_CHICKEN1
) |
5670 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
5671 I915_READ(ILK_DISPLAY_CHICKEN2
) |
5675 I915_WRITE(ILK_DSPCLK_GATE_D
, dspclk_gate
);
5677 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
5678 I915_READ(ILK_DISPLAY_CHICKEN2
) |
5679 ILK_ELPIN_409_SELECT
);
5680 I915_WRITE(_3D_CHICKEN2
,
5681 _3D_CHICKEN2_WM_READ_PIPELINED
<< 16 |
5682 _3D_CHICKEN2_WM_READ_PIPELINED
);
5684 /* WaDisableRenderCachePipelinedFlush:ilk */
5685 I915_WRITE(CACHE_MODE_0
,
5686 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE
));
5688 /* WaDisable_RenderCache_OperationalFlush:ilk */
5689 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
5691 g4x_disable_trickle_feed(dev
);
5693 ibx_init_clock_gating(dev
);
5696 static void cpt_init_clock_gating(struct drm_device
*dev
)
5698 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5703 * On Ibex Peak and Cougar Point, we need to disable clock
5704 * gating for the panel power sequencer or it will fail to
5705 * start up when no ports are active.
5707 I915_WRITE(SOUTH_DSPCLK_GATE_D
, PCH_DPLSUNIT_CLOCK_GATE_DISABLE
|
5708 PCH_DPLUNIT_CLOCK_GATE_DISABLE
|
5709 PCH_CPUNIT_CLOCK_GATE_DISABLE
);
5710 I915_WRITE(SOUTH_CHICKEN2
, I915_READ(SOUTH_CHICKEN2
) |
5711 DPLS_EDP_PPS_FIX_DIS
);
5712 /* The below fixes the weird display corruption, a few pixels shifted
5713 * downward, on (only) LVDS of some HP laptops with IVY.
5715 for_each_pipe(dev_priv
, pipe
) {
5716 val
= I915_READ(TRANS_CHICKEN2(pipe
));
5717 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
5718 val
&= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED
;
5719 if (dev_priv
->vbt
.fdi_rx_polarity_inverted
)
5720 val
|= TRANS_CHICKEN2_FDI_POLARITY_REVERSED
;
5721 val
&= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK
;
5722 val
&= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER
;
5723 val
&= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH
;
5724 I915_WRITE(TRANS_CHICKEN2(pipe
), val
);
5726 /* WADP0ClockGatingDisable */
5727 for_each_pipe(dev_priv
, pipe
) {
5728 I915_WRITE(TRANS_CHICKEN1(pipe
),
5729 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE
);
5733 static void gen6_check_mch_setup(struct drm_device
*dev
)
5735 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5738 tmp
= I915_READ(MCH_SSKPD
);
5739 if ((tmp
& MCH_SSKPD_WM0_MASK
) != MCH_SSKPD_WM0_VAL
)
5740 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
5744 static void gen6_init_clock_gating(struct drm_device
*dev
)
5746 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5747 uint32_t dspclk_gate
= ILK_VRHUNIT_CLOCK_GATE_DISABLE
;
5749 I915_WRITE(ILK_DSPCLK_GATE_D
, dspclk_gate
);
5751 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
5752 I915_READ(ILK_DISPLAY_CHICKEN2
) |
5753 ILK_ELPIN_409_SELECT
);
5755 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
5756 I915_WRITE(_3D_CHICKEN
,
5757 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB
));
5759 /* WaDisable_RenderCache_OperationalFlush:snb */
5760 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
5763 * BSpec recoomends 8x4 when MSAA is used,
5764 * however in practice 16x4 seems fastest.
5766 * Note that PS/WM thread counts depend on the WIZ hashing
5767 * disable bit, which we don't touch here, but it's good
5768 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5770 I915_WRITE(GEN6_GT_MODE
,
5771 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK
, GEN6_WIZ_HASHING_16x4
));
5773 ilk_init_lp_watermarks(dev
);
5775 I915_WRITE(CACHE_MODE_0
,
5776 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB
));
5778 I915_WRITE(GEN6_UCGCTL1
,
5779 I915_READ(GEN6_UCGCTL1
) |
5780 GEN6_BLBUNIT_CLOCK_GATE_DISABLE
|
5781 GEN6_CSUNIT_CLOCK_GATE_DISABLE
);
5783 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5784 * gating disable must be set. Failure to set it results in
5785 * flickering pixels due to Z write ordering failures after
5786 * some amount of runtime in the Mesa "fire" demo, and Unigine
5787 * Sanctuary and Tropics, and apparently anything else with
5788 * alpha test or pixel discard.
5790 * According to the spec, bit 11 (RCCUNIT) must also be set,
5791 * but we didn't debug actual testcases to find it out.
5793 * WaDisableRCCUnitClockGating:snb
5794 * WaDisableRCPBUnitClockGating:snb
5796 I915_WRITE(GEN6_UCGCTL2
,
5797 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE
|
5798 GEN6_RCCUNIT_CLOCK_GATE_DISABLE
);
5800 /* WaStripsFansDisableFastClipPerformanceFix:snb */
5801 I915_WRITE(_3D_CHICKEN3
,
5802 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL
));
5806 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
5807 * 3DSTATE_SF number of SF output attributes is more than 16."
5809 I915_WRITE(_3D_CHICKEN3
,
5810 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH
));
5813 * According to the spec the following bits should be
5814 * set in order to enable memory self-refresh and fbc:
5815 * The bit21 and bit22 of 0x42000
5816 * The bit21 and bit22 of 0x42004
5817 * The bit5 and bit7 of 0x42020
5818 * The bit14 of 0x70180
5819 * The bit14 of 0x71180
5821 * WaFbcAsynchFlipDisableFbcQueue:snb
5823 I915_WRITE(ILK_DISPLAY_CHICKEN1
,
5824 I915_READ(ILK_DISPLAY_CHICKEN1
) |
5825 ILK_FBCQ_DIS
| ILK_PABSTRETCH_DIS
);
5826 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
5827 I915_READ(ILK_DISPLAY_CHICKEN2
) |
5828 ILK_DPARB_GATE
| ILK_VSDPFD_FULL
);
5829 I915_WRITE(ILK_DSPCLK_GATE_D
,
5830 I915_READ(ILK_DSPCLK_GATE_D
) |
5831 ILK_DPARBUNIT_CLOCK_GATE_ENABLE
|
5832 ILK_DPFDUNIT_CLOCK_GATE_ENABLE
);
5834 g4x_disable_trickle_feed(dev
);
5836 cpt_init_clock_gating(dev
);
5838 gen6_check_mch_setup(dev
);
5841 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private
*dev_priv
)
5843 uint32_t reg
= I915_READ(GEN7_FF_THREAD_MODE
);
5846 * WaVSThreadDispatchOverride:ivb,vlv
5848 * This actually overrides the dispatch
5849 * mode for all thread types.
5851 reg
&= ~GEN7_FF_SCHED_MASK
;
5852 reg
|= GEN7_FF_TS_SCHED_HW
;
5853 reg
|= GEN7_FF_VS_SCHED_HW
;
5854 reg
|= GEN7_FF_DS_SCHED_HW
;
5856 I915_WRITE(GEN7_FF_THREAD_MODE
, reg
);
5859 static void lpt_init_clock_gating(struct drm_device
*dev
)
5861 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5864 * TODO: this bit should only be enabled when really needed, then
5865 * disabled when not needed anymore in order to save power.
5867 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
)
5868 I915_WRITE(SOUTH_DSPCLK_GATE_D
,
5869 I915_READ(SOUTH_DSPCLK_GATE_D
) |
5870 PCH_LP_PARTITION_LEVEL_DISABLE
);
5872 /* WADPOClockGatingDisable:hsw */
5873 I915_WRITE(_TRANSA_CHICKEN1
,
5874 I915_READ(_TRANSA_CHICKEN1
) |
5875 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE
);
5878 static void lpt_suspend_hw(struct drm_device
*dev
)
5880 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5882 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
5883 uint32_t val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
5885 val
&= ~PCH_LP_PARTITION_LEVEL_DISABLE
;
5886 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
5890 static void broadwell_init_clock_gating(struct drm_device
*dev
)
5892 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5895 I915_WRITE(WM3_LP_ILK
, 0);
5896 I915_WRITE(WM2_LP_ILK
, 0);
5897 I915_WRITE(WM1_LP_ILK
, 0);
5899 /* WaSwitchSolVfFArbitrationPriority:bdw */
5900 I915_WRITE(GAM_ECOCHK
, I915_READ(GAM_ECOCHK
) | HSW_ECOCHK_ARB_PRIO_SOL
);
5902 /* WaPsrDPAMaskVBlankInSRD:bdw */
5903 I915_WRITE(CHICKEN_PAR1_1
,
5904 I915_READ(CHICKEN_PAR1_1
) | DPA_MASK_VBLANK_SRD
);
5906 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
5907 for_each_pipe(dev_priv
, pipe
) {
5908 I915_WRITE(CHICKEN_PIPESL_1(pipe
),
5909 I915_READ(CHICKEN_PIPESL_1(pipe
)) |
5910 BDW_DPRS_MASK_VBLANK_SRD
);
5913 /* WaVSRefCountFullforceMissDisable:bdw */
5914 /* WaDSRefCountFullforceMissDisable:bdw */
5915 I915_WRITE(GEN7_FF_THREAD_MODE
,
5916 I915_READ(GEN7_FF_THREAD_MODE
) &
5917 ~(GEN8_FF_DS_REF_CNT_FFME
| GEN7_FF_VS_REF_CNT_FFME
));
5919 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL
,
5920 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE
));
5922 /* WaDisableSDEUnitClockGating:bdw */
5923 I915_WRITE(GEN8_UCGCTL6
, I915_READ(GEN8_UCGCTL6
) |
5924 GEN8_SDEUNIT_CLOCK_GATE_DISABLE
);
5926 lpt_init_clock_gating(dev
);
5929 static void haswell_init_clock_gating(struct drm_device
*dev
)
5931 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5933 ilk_init_lp_watermarks(dev
);
5935 /* L3 caching of data atomics doesn't work -- disable it. */
5936 I915_WRITE(HSW_SCRATCH1
, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE
);
5937 I915_WRITE(HSW_ROW_CHICKEN3
,
5938 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE
));
5940 /* This is required by WaCatErrorRejectionIssue:hsw */
5941 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
5942 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
5943 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
5945 /* WaVSRefCountFullforceMissDisable:hsw */
5946 I915_WRITE(GEN7_FF_THREAD_MODE
,
5947 I915_READ(GEN7_FF_THREAD_MODE
) & ~GEN7_FF_VS_REF_CNT_FFME
);
5949 /* WaDisable_RenderCache_OperationalFlush:hsw */
5950 I915_WRITE(CACHE_MODE_0_GEN7
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
5952 /* enable HiZ Raw Stall Optimization */
5953 I915_WRITE(CACHE_MODE_0_GEN7
,
5954 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE
));
5956 /* WaDisable4x2SubspanOptimization:hsw */
5957 I915_WRITE(CACHE_MODE_1
,
5958 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
));
5961 * BSpec recommends 8x4 when MSAA is used,
5962 * however in practice 16x4 seems fastest.
5964 * Note that PS/WM thread counts depend on the WIZ hashing
5965 * disable bit, which we don't touch here, but it's good
5966 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5968 I915_WRITE(GEN7_GT_MODE
,
5969 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK
, GEN6_WIZ_HASHING_16x4
));
5971 /* WaSampleCChickenBitEnable:hsw */
5972 I915_WRITE(HALF_SLICE_CHICKEN3
,
5973 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE
));
5975 /* WaSwitchSolVfFArbitrationPriority:hsw */
5976 I915_WRITE(GAM_ECOCHK
, I915_READ(GAM_ECOCHK
) | HSW_ECOCHK_ARB_PRIO_SOL
);
5978 /* WaRsPkgCStateDisplayPMReq:hsw */
5979 I915_WRITE(CHICKEN_PAR1_1
,
5980 I915_READ(CHICKEN_PAR1_1
) | FORCE_ARB_IDLE_PLANES
);
5982 lpt_init_clock_gating(dev
);
5985 static void ivybridge_init_clock_gating(struct drm_device
*dev
)
5987 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5990 ilk_init_lp_watermarks(dev
);
5992 I915_WRITE(ILK_DSPCLK_GATE_D
, ILK_VRHUNIT_CLOCK_GATE_DISABLE
);
5994 /* WaDisableEarlyCull:ivb */
5995 I915_WRITE(_3D_CHICKEN3
,
5996 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL
));
5998 /* WaDisableBackToBackFlipFix:ivb */
5999 I915_WRITE(IVB_CHICKEN3
,
6000 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE
|
6001 CHICKEN3_DGMG_DONE_FIX_DISABLE
);
6003 /* WaDisablePSDDualDispatchEnable:ivb */
6004 if (IS_IVB_GT1(dev
))
6005 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1
,
6006 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE
));
6008 /* WaDisable_RenderCache_OperationalFlush:ivb */
6009 I915_WRITE(CACHE_MODE_0_GEN7
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
6011 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6012 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1
,
6013 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC
);
6015 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6016 I915_WRITE(GEN7_L3CNTLREG1
,
6017 GEN7_WA_FOR_GEN7_L3_CONTROL
);
6018 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER
,
6019 GEN7_WA_L3_CHICKEN_MODE
);
6020 if (IS_IVB_GT1(dev
))
6021 I915_WRITE(GEN7_ROW_CHICKEN2
,
6022 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
6024 /* must write both registers */
6025 I915_WRITE(GEN7_ROW_CHICKEN2
,
6026 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
6027 I915_WRITE(GEN7_ROW_CHICKEN2_GT2
,
6028 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
6031 /* WaForceL3Serialization:ivb */
6032 I915_WRITE(GEN7_L3SQCREG4
, I915_READ(GEN7_L3SQCREG4
) &
6033 ~L3SQ_URB_READ_CAM_MATCH_DISABLE
);
6036 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6037 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
6039 I915_WRITE(GEN6_UCGCTL2
,
6040 GEN6_RCZUNIT_CLOCK_GATE_DISABLE
);
6042 /* This is required by WaCatErrorRejectionIssue:ivb */
6043 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
6044 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
6045 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
6047 g4x_disable_trickle_feed(dev
);
6049 gen7_setup_fixed_func_scheduler(dev_priv
);
6051 if (0) { /* causes HiZ corruption on ivb:gt1 */
6052 /* enable HiZ Raw Stall Optimization */
6053 I915_WRITE(CACHE_MODE_0_GEN7
,
6054 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE
));
6057 /* WaDisable4x2SubspanOptimization:ivb */
6058 I915_WRITE(CACHE_MODE_1
,
6059 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
));
6062 * BSpec recommends 8x4 when MSAA is used,
6063 * however in practice 16x4 seems fastest.
6065 * Note that PS/WM thread counts depend on the WIZ hashing
6066 * disable bit, which we don't touch here, but it's good
6067 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6069 I915_WRITE(GEN7_GT_MODE
,
6070 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK
, GEN6_WIZ_HASHING_16x4
));
6072 snpcr
= I915_READ(GEN6_MBCUNIT_SNPCR
);
6073 snpcr
&= ~GEN6_MBC_SNPCR_MASK
;
6074 snpcr
|= GEN6_MBC_SNPCR_MED
;
6075 I915_WRITE(GEN6_MBCUNIT_SNPCR
, snpcr
);
6077 if (!HAS_PCH_NOP(dev
))
6078 cpt_init_clock_gating(dev
);
6080 gen6_check_mch_setup(dev
);
6083 static void valleyview_init_clock_gating(struct drm_device
*dev
)
6085 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6087 I915_WRITE(DSPCLK_GATE_D
, VRHUNIT_CLOCK_GATE_DISABLE
);
6089 /* WaDisableEarlyCull:vlv */
6090 I915_WRITE(_3D_CHICKEN3
,
6091 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL
));
6093 /* WaDisableBackToBackFlipFix:vlv */
6094 I915_WRITE(IVB_CHICKEN3
,
6095 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE
|
6096 CHICKEN3_DGMG_DONE_FIX_DISABLE
);
6098 /* WaPsdDispatchEnable:vlv */
6099 /* WaDisablePSDDualDispatchEnable:vlv */
6100 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1
,
6101 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP
|
6102 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE
));
6104 /* WaDisable_RenderCache_OperationalFlush:vlv */
6105 I915_WRITE(CACHE_MODE_0_GEN7
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
6107 /* WaForceL3Serialization:vlv */
6108 I915_WRITE(GEN7_L3SQCREG4
, I915_READ(GEN7_L3SQCREG4
) &
6109 ~L3SQ_URB_READ_CAM_MATCH_DISABLE
);
6111 /* WaDisableDopClockGating:vlv */
6112 I915_WRITE(GEN7_ROW_CHICKEN2
,
6113 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
6115 /* This is required by WaCatErrorRejectionIssue:vlv */
6116 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
6117 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
6118 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
6120 gen7_setup_fixed_func_scheduler(dev_priv
);
6123 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6124 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
6126 I915_WRITE(GEN6_UCGCTL2
,
6127 GEN6_RCZUNIT_CLOCK_GATE_DISABLE
);
6129 /* WaDisableL3Bank2xClockGate:vlv
6130 * Disabling L3 clock gating- MMIO 940c[25] = 1
6131 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
6132 I915_WRITE(GEN7_UCGCTL4
,
6133 I915_READ(GEN7_UCGCTL4
) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE
);
6135 I915_WRITE(MI_ARB_VLV
, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
);
6138 * BSpec says this must be set, even though
6139 * WaDisable4x2SubspanOptimization isn't listed for VLV.
6141 I915_WRITE(CACHE_MODE_1
,
6142 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
));
6145 * BSpec recommends 8x4 when MSAA is used,
6146 * however in practice 16x4 seems fastest.
6148 * Note that PS/WM thread counts depend on the WIZ hashing
6149 * disable bit, which we don't touch here, but it's good
6150 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6152 I915_WRITE(GEN7_GT_MODE
,
6153 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK
, GEN6_WIZ_HASHING_16x4
));
6156 * WaIncreaseL3CreditsForVLVB0:vlv
6157 * This is the hardware default actually.
6159 I915_WRITE(GEN7_L3SQCREG1
, VLV_B0_WA_L3SQCREG1_VALUE
);
6162 * WaDisableVLVClockGating_VBIIssue:vlv
6163 * Disable clock gating on th GCFG unit to prevent a delay
6164 * in the reporting of vblank events.
6166 I915_WRITE(VLV_GUNIT_CLOCK_GATE
, GCFG_DIS
);
6169 static void cherryview_init_clock_gating(struct drm_device
*dev
)
6171 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6173 I915_WRITE(DSPCLK_GATE_D
, VRHUNIT_CLOCK_GATE_DISABLE
);
6175 I915_WRITE(MI_ARB_VLV
, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
);
6177 /* WaVSRefCountFullforceMissDisable:chv */
6178 /* WaDSRefCountFullforceMissDisable:chv */
6179 I915_WRITE(GEN7_FF_THREAD_MODE
,
6180 I915_READ(GEN7_FF_THREAD_MODE
) &
6181 ~(GEN8_FF_DS_REF_CNT_FFME
| GEN7_FF_VS_REF_CNT_FFME
));
6183 /* WaDisableSemaphoreAndSyncFlipWait:chv */
6184 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL
,
6185 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE
));
6187 /* WaDisableCSUnitClockGating:chv */
6188 I915_WRITE(GEN6_UCGCTL1
, I915_READ(GEN6_UCGCTL1
) |
6189 GEN6_CSUNIT_CLOCK_GATE_DISABLE
);
6191 /* WaDisableSDEUnitClockGating:chv */
6192 I915_WRITE(GEN8_UCGCTL6
, I915_READ(GEN8_UCGCTL6
) |
6193 GEN8_SDEUNIT_CLOCK_GATE_DISABLE
);
6196 static void g4x_init_clock_gating(struct drm_device
*dev
)
6198 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6199 uint32_t dspclk_gate
;
6201 I915_WRITE(RENCLK_GATE_D1
, 0);
6202 I915_WRITE(RENCLK_GATE_D2
, VF_UNIT_CLOCK_GATE_DISABLE
|
6203 GS_UNIT_CLOCK_GATE_DISABLE
|
6204 CL_UNIT_CLOCK_GATE_DISABLE
);
6205 I915_WRITE(RAMCLK_GATE_D
, 0);
6206 dspclk_gate
= VRHUNIT_CLOCK_GATE_DISABLE
|
6207 OVRUNIT_CLOCK_GATE_DISABLE
|
6208 OVCUNIT_CLOCK_GATE_DISABLE
;
6210 dspclk_gate
|= DSSUNIT_CLOCK_GATE_DISABLE
;
6211 I915_WRITE(DSPCLK_GATE_D
, dspclk_gate
);
6213 /* WaDisableRenderCachePipelinedFlush */
6214 I915_WRITE(CACHE_MODE_0
,
6215 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE
));
6217 /* WaDisable_RenderCache_OperationalFlush:g4x */
6218 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
6220 g4x_disable_trickle_feed(dev
);
6223 static void crestline_init_clock_gating(struct drm_device
*dev
)
6225 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6227 I915_WRITE(RENCLK_GATE_D1
, I965_RCC_CLOCK_GATE_DISABLE
);
6228 I915_WRITE(RENCLK_GATE_D2
, 0);
6229 I915_WRITE(DSPCLK_GATE_D
, 0);
6230 I915_WRITE(RAMCLK_GATE_D
, 0);
6231 I915_WRITE16(DEUC
, 0);
6232 I915_WRITE(MI_ARB_STATE
,
6233 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
));
6235 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6236 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
6239 static void broadwater_init_clock_gating(struct drm_device
*dev
)
6241 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6243 I915_WRITE(RENCLK_GATE_D1
, I965_RCZ_CLOCK_GATE_DISABLE
|
6244 I965_RCC_CLOCK_GATE_DISABLE
|
6245 I965_RCPB_CLOCK_GATE_DISABLE
|
6246 I965_ISC_CLOCK_GATE_DISABLE
|
6247 I965_FBC_CLOCK_GATE_DISABLE
);
6248 I915_WRITE(RENCLK_GATE_D2
, 0);
6249 I915_WRITE(MI_ARB_STATE
,
6250 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
));
6252 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6253 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
6256 static void gen3_init_clock_gating(struct drm_device
*dev
)
6258 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6259 u32 dstate
= I915_READ(D_STATE
);
6261 dstate
|= DSTATE_PLL_D3_OFF
| DSTATE_GFX_CLOCK_GATING
|
6262 DSTATE_DOT_CLOCK_GATING
;
6263 I915_WRITE(D_STATE
, dstate
);
6265 if (IS_PINEVIEW(dev
))
6266 I915_WRITE(ECOSKPD
, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY
));
6268 /* IIR "flip pending" means done if this bit is set */
6269 I915_WRITE(ECOSKPD
, _MASKED_BIT_DISABLE(ECO_FLIP_DONE
));
6271 /* interrupts should cause a wake up from C3 */
6272 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN
));
6274 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
6275 I915_WRITE(MI_ARB_STATE
, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE
));
6277 I915_WRITE(MI_ARB_STATE
,
6278 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
));
6281 static void i85x_init_clock_gating(struct drm_device
*dev
)
6283 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6285 I915_WRITE(RENCLK_GATE_D1
, SV_CLOCK_GATE_DISABLE
);
6287 /* interrupts should cause a wake up from C3 */
6288 I915_WRITE(MI_STATE
, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN
) |
6289 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE
));
6291 I915_WRITE(MEM_MODE
,
6292 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE
));
6295 static void i830_init_clock_gating(struct drm_device
*dev
)
6297 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6299 I915_WRITE(DSPCLK_GATE_D
, OVRUNIT_CLOCK_GATE_DISABLE
);
6301 I915_WRITE(MEM_MODE
,
6302 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE
) |
6303 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE
));
6306 void intel_init_clock_gating(struct drm_device
*dev
)
6308 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6310 if (dev_priv
->display
.init_clock_gating
)
6311 dev_priv
->display
.init_clock_gating(dev
);
6314 void intel_suspend_hw(struct drm_device
*dev
)
6316 if (HAS_PCH_LPT(dev
))
6317 lpt_suspend_hw(dev
);
6320 /* Set up chip specific power management-related functions */
6321 void intel_init_pm(struct drm_device
*dev
)
6323 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6325 intel_fbc_init(dev_priv
);
6328 if (IS_PINEVIEW(dev
))
6329 i915_pineview_get_mem_freq(dev
);
6330 else if (IS_GEN5(dev
))
6331 i915_ironlake_get_mem_freq(dev
);
6333 /* For FIFO watermark updates */
6334 if (INTEL_INFO(dev
)->gen
>= 9) {
6335 skl_setup_wm_latency(dev
);
6337 dev_priv
->display
.init_clock_gating
= skl_init_clock_gating
;
6338 dev_priv
->display
.update_wm
= skl_update_wm
;
6339 dev_priv
->display
.update_sprite_wm
= skl_update_sprite_wm
;
6340 } else if (HAS_PCH_SPLIT(dev
)) {
6341 ilk_setup_wm_latency(dev
);
6343 if ((IS_GEN5(dev
) && dev_priv
->wm
.pri_latency
[1] &&
6344 dev_priv
->wm
.spr_latency
[1] && dev_priv
->wm
.cur_latency
[1]) ||
6345 (!IS_GEN5(dev
) && dev_priv
->wm
.pri_latency
[0] &&
6346 dev_priv
->wm
.spr_latency
[0] && dev_priv
->wm
.cur_latency
[0])) {
6347 dev_priv
->display
.update_wm
= ilk_update_wm
;
6348 dev_priv
->display
.update_sprite_wm
= ilk_update_sprite_wm
;
6350 DRM_DEBUG_KMS("Failed to read display plane latency. "
6355 dev_priv
->display
.init_clock_gating
= ironlake_init_clock_gating
;
6356 else if (IS_GEN6(dev
))
6357 dev_priv
->display
.init_clock_gating
= gen6_init_clock_gating
;
6358 else if (IS_IVYBRIDGE(dev
))
6359 dev_priv
->display
.init_clock_gating
= ivybridge_init_clock_gating
;
6360 else if (IS_HASWELL(dev
))
6361 dev_priv
->display
.init_clock_gating
= haswell_init_clock_gating
;
6362 else if (INTEL_INFO(dev
)->gen
== 8)
6363 dev_priv
->display
.init_clock_gating
= broadwell_init_clock_gating
;
6364 } else if (IS_CHERRYVIEW(dev
)) {
6365 dev_priv
->display
.update_wm
= cherryview_update_wm
;
6366 dev_priv
->display
.update_sprite_wm
= valleyview_update_sprite_wm
;
6367 dev_priv
->display
.init_clock_gating
=
6368 cherryview_init_clock_gating
;
6369 } else if (IS_VALLEYVIEW(dev
)) {
6370 dev_priv
->display
.update_wm
= valleyview_update_wm
;
6371 dev_priv
->display
.update_sprite_wm
= valleyview_update_sprite_wm
;
6372 dev_priv
->display
.init_clock_gating
=
6373 valleyview_init_clock_gating
;
6374 } else if (IS_PINEVIEW(dev
)) {
6375 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev
),
6378 dev_priv
->mem_freq
)) {
6379 DRM_INFO("failed to find known CxSR latency "
6380 "(found ddr%s fsb freq %d, mem freq %d), "
6382 (dev_priv
->is_ddr3
== 1) ? "3" : "2",
6383 dev_priv
->fsb_freq
, dev_priv
->mem_freq
);
6384 /* Disable CxSR and never update its watermark again */
6385 intel_set_memory_cxsr(dev_priv
, false);
6386 dev_priv
->display
.update_wm
= NULL
;
6388 dev_priv
->display
.update_wm
= pineview_update_wm
;
6389 dev_priv
->display
.init_clock_gating
= gen3_init_clock_gating
;
6390 } else if (IS_G4X(dev
)) {
6391 dev_priv
->display
.update_wm
= g4x_update_wm
;
6392 dev_priv
->display
.init_clock_gating
= g4x_init_clock_gating
;
6393 } else if (IS_GEN4(dev
)) {
6394 dev_priv
->display
.update_wm
= i965_update_wm
;
6395 if (IS_CRESTLINE(dev
))
6396 dev_priv
->display
.init_clock_gating
= crestline_init_clock_gating
;
6397 else if (IS_BROADWATER(dev
))
6398 dev_priv
->display
.init_clock_gating
= broadwater_init_clock_gating
;
6399 } else if (IS_GEN3(dev
)) {
6400 dev_priv
->display
.update_wm
= i9xx_update_wm
;
6401 dev_priv
->display
.get_fifo_size
= i9xx_get_fifo_size
;
6402 dev_priv
->display
.init_clock_gating
= gen3_init_clock_gating
;
6403 } else if (IS_GEN2(dev
)) {
6404 if (INTEL_INFO(dev
)->num_pipes
== 1) {
6405 dev_priv
->display
.update_wm
= i845_update_wm
;
6406 dev_priv
->display
.get_fifo_size
= i845_get_fifo_size
;
6408 dev_priv
->display
.update_wm
= i9xx_update_wm
;
6409 dev_priv
->display
.get_fifo_size
= i830_get_fifo_size
;
6412 if (IS_I85X(dev
) || IS_I865G(dev
))
6413 dev_priv
->display
.init_clock_gating
= i85x_init_clock_gating
;
6415 dev_priv
->display
.init_clock_gating
= i830_init_clock_gating
;
6417 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
6421 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u32 mbox
, u32
*val
)
6423 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
6425 if (I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) {
6426 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
6430 I915_WRITE(GEN6_PCODE_DATA
, *val
);
6431 I915_WRITE(GEN6_PCODE_DATA1
, 0);
6432 I915_WRITE(GEN6_PCODE_MAILBOX
, GEN6_PCODE_READY
| mbox
);
6434 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) == 0,
6436 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox
);
6440 *val
= I915_READ(GEN6_PCODE_DATA
);
6441 I915_WRITE(GEN6_PCODE_DATA
, 0);
6446 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
, u32 mbox
, u32 val
)
6448 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
6450 if (I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) {
6451 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
6455 I915_WRITE(GEN6_PCODE_DATA
, val
);
6456 I915_WRITE(GEN6_PCODE_MAILBOX
, GEN6_PCODE_READY
| mbox
);
6458 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) == 0,
6460 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox
);
6464 I915_WRITE(GEN6_PCODE_DATA
, 0);
6469 static int vlv_gpu_freq_div(unsigned int czclk_freq
)
6471 switch (czclk_freq
) {
6486 static int byt_gpu_freq(struct drm_i915_private
*dev_priv
, int val
)
6488 int div
, czclk_freq
= DIV_ROUND_CLOSEST(dev_priv
->mem_freq
, 4);
6490 div
= vlv_gpu_freq_div(czclk_freq
);
6494 return DIV_ROUND_CLOSEST(czclk_freq
* (val
+ 6 - 0xbd), div
);
6497 static int byt_freq_opcode(struct drm_i915_private
*dev_priv
, int val
)
6499 int mul
, czclk_freq
= DIV_ROUND_CLOSEST(dev_priv
->mem_freq
, 4);
6501 mul
= vlv_gpu_freq_div(czclk_freq
);
6505 return DIV_ROUND_CLOSEST(mul
* val
, czclk_freq
) + 0xbd - 6;
6508 static int chv_gpu_freq(struct drm_i915_private
*dev_priv
, int val
)
6510 int div
, czclk_freq
= dev_priv
->rps
.cz_freq
;
6512 div
= vlv_gpu_freq_div(czclk_freq
) / 2;
6516 return DIV_ROUND_CLOSEST(czclk_freq
* val
, 2 * div
) / 2;
6519 static int chv_freq_opcode(struct drm_i915_private
*dev_priv
, int val
)
6521 int mul
, czclk_freq
= dev_priv
->rps
.cz_freq
;
6523 mul
= vlv_gpu_freq_div(czclk_freq
) / 2;
6527 /* CHV needs even values */
6528 return DIV_ROUND_CLOSEST(val
* 2 * mul
, czclk_freq
) * 2;
6531 int intel_gpu_freq(struct drm_i915_private
*dev_priv
, int val
)
6533 if (IS_CHERRYVIEW(dev_priv
->dev
))
6534 return chv_gpu_freq(dev_priv
, val
);
6535 else if (IS_VALLEYVIEW(dev_priv
->dev
))
6536 return byt_gpu_freq(dev_priv
, val
);
6538 return val
* GT_FREQUENCY_MULTIPLIER
;
6541 int intel_freq_opcode(struct drm_i915_private
*dev_priv
, int val
)
6543 if (IS_CHERRYVIEW(dev_priv
->dev
))
6544 return chv_freq_opcode(dev_priv
, val
);
6545 else if (IS_VALLEYVIEW(dev_priv
->dev
))
6546 return byt_freq_opcode(dev_priv
, val
);
6548 return val
/ GT_FREQUENCY_MULTIPLIER
;
6551 void intel_pm_setup(struct drm_device
*dev
)
6553 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6555 mutex_init(&dev_priv
->rps
.hw_lock
);
6557 INIT_DELAYED_WORK(&dev_priv
->rps
.delayed_resume_work
,
6558 intel_gen6_powersave_work
);
6560 dev_priv
->pm
.suspended
= false;