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drm/i915: Read czclk from CCK on vlv/chv
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_pm.c
1 /*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28 #include <linux/cpufreq.h>
29 #include "i915_drv.h"
30 #include "intel_drv.h"
31 #include "../../../platform/x86/intel_ips.h"
32 #include <linux/module.h>
33
34 /**
35 * RC6 is a special power stage which allows the GPU to enter an very
36 * low-voltage mode when idle, using down to 0V while at this stage. This
37 * stage is entered automatically when the GPU is idle when RC6 support is
38 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
39 *
40 * There are different RC6 modes available in Intel GPU, which differentiate
41 * among each other with the latency required to enter and leave RC6 and
42 * voltage consumed by the GPU in different states.
43 *
44 * The combination of the following flags define which states GPU is allowed
45 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
46 * RC6pp is deepest RC6. Their support by hardware varies according to the
47 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
48 * which brings the most power savings; deeper states save more power, but
49 * require higher latency to switch to and wake up.
50 */
51 #define INTEL_RC6_ENABLE (1<<0)
52 #define INTEL_RC6p_ENABLE (1<<1)
53 #define INTEL_RC6pp_ENABLE (1<<2)
54
55 static void gen9_init_clock_gating(struct drm_device *dev)
56 {
57 struct drm_i915_private *dev_priv = dev->dev_private;
58
59 /* WaEnableLbsSlaRetryTimerDecrement:skl */
60 I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
61 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
62
63 /* WaDisableKillLogic:bxt,skl */
64 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
65 ECOCHK_DIS_TLB);
66 }
67
68 static void skl_init_clock_gating(struct drm_device *dev)
69 {
70 struct drm_i915_private *dev_priv = dev->dev_private;
71
72 gen9_init_clock_gating(dev);
73
74 if (INTEL_REVID(dev) <= SKL_REVID_D0) {
75 /* WaDisableHDCInvalidation:skl */
76 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
77 BDW_DISABLE_HDC_INVALIDATION);
78
79 /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
80 I915_WRITE(FF_SLICE_CS_CHICKEN2,
81 _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE));
82 }
83
84 /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
85 * involving this register should also be added to WA batch as required.
86 */
87 if (INTEL_REVID(dev) <= SKL_REVID_E0)
88 /* WaDisableLSQCROPERFforOCL:skl */
89 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
90 GEN8_LQSC_RO_PERF_DIS);
91
92 /* WaEnableGapsTsvCreditFix:skl */
93 if (IS_SKYLAKE(dev) && (INTEL_REVID(dev) >= SKL_REVID_C0)) {
94 I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
95 GEN9_GAPS_TSV_CREDIT_DISABLE));
96 }
97 }
98
99 static void bxt_init_clock_gating(struct drm_device *dev)
100 {
101 struct drm_i915_private *dev_priv = dev->dev_private;
102
103 gen9_init_clock_gating(dev);
104
105 /* WaDisableSDEUnitClockGating:bxt */
106 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
107 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
108
109 /*
110 * FIXME:
111 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
112 */
113 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
114 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
115
116 /* WaStoreMultiplePTEenable:bxt */
117 /* This is a requirement according to Hardware specification */
118 if (INTEL_REVID(dev) == BXT_REVID_A0)
119 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
120
121 /* WaSetClckGatingDisableMedia:bxt */
122 if (INTEL_REVID(dev) == BXT_REVID_A0) {
123 I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) &
124 ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE));
125 }
126 }
127
128 static void i915_pineview_get_mem_freq(struct drm_device *dev)
129 {
130 struct drm_i915_private *dev_priv = dev->dev_private;
131 u32 tmp;
132
133 tmp = I915_READ(CLKCFG);
134
135 switch (tmp & CLKCFG_FSB_MASK) {
136 case CLKCFG_FSB_533:
137 dev_priv->fsb_freq = 533; /* 133*4 */
138 break;
139 case CLKCFG_FSB_800:
140 dev_priv->fsb_freq = 800; /* 200*4 */
141 break;
142 case CLKCFG_FSB_667:
143 dev_priv->fsb_freq = 667; /* 167*4 */
144 break;
145 case CLKCFG_FSB_400:
146 dev_priv->fsb_freq = 400; /* 100*4 */
147 break;
148 }
149
150 switch (tmp & CLKCFG_MEM_MASK) {
151 case CLKCFG_MEM_533:
152 dev_priv->mem_freq = 533;
153 break;
154 case CLKCFG_MEM_667:
155 dev_priv->mem_freq = 667;
156 break;
157 case CLKCFG_MEM_800:
158 dev_priv->mem_freq = 800;
159 break;
160 }
161
162 /* detect pineview DDR3 setting */
163 tmp = I915_READ(CSHRDDR3CTL);
164 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
165 }
166
167 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
168 {
169 struct drm_i915_private *dev_priv = dev->dev_private;
170 u16 ddrpll, csipll;
171
172 ddrpll = I915_READ16(DDRMPLL1);
173 csipll = I915_READ16(CSIPLL0);
174
175 switch (ddrpll & 0xff) {
176 case 0xc:
177 dev_priv->mem_freq = 800;
178 break;
179 case 0x10:
180 dev_priv->mem_freq = 1066;
181 break;
182 case 0x14:
183 dev_priv->mem_freq = 1333;
184 break;
185 case 0x18:
186 dev_priv->mem_freq = 1600;
187 break;
188 default:
189 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
190 ddrpll & 0xff);
191 dev_priv->mem_freq = 0;
192 break;
193 }
194
195 dev_priv->ips.r_t = dev_priv->mem_freq;
196
197 switch (csipll & 0x3ff) {
198 case 0x00c:
199 dev_priv->fsb_freq = 3200;
200 break;
201 case 0x00e:
202 dev_priv->fsb_freq = 3733;
203 break;
204 case 0x010:
205 dev_priv->fsb_freq = 4266;
206 break;
207 case 0x012:
208 dev_priv->fsb_freq = 4800;
209 break;
210 case 0x014:
211 dev_priv->fsb_freq = 5333;
212 break;
213 case 0x016:
214 dev_priv->fsb_freq = 5866;
215 break;
216 case 0x018:
217 dev_priv->fsb_freq = 6400;
218 break;
219 default:
220 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
221 csipll & 0x3ff);
222 dev_priv->fsb_freq = 0;
223 break;
224 }
225
226 if (dev_priv->fsb_freq == 3200) {
227 dev_priv->ips.c_m = 0;
228 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
229 dev_priv->ips.c_m = 1;
230 } else {
231 dev_priv->ips.c_m = 2;
232 }
233 }
234
235 static const struct cxsr_latency cxsr_latency_table[] = {
236 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
237 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
238 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
239 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
240 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
241
242 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
243 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
244 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
245 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
246 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
247
248 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
249 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
250 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
251 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
252 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
253
254 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
255 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
256 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
257 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
258 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
259
260 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
261 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
262 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
263 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
264 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
265
266 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
267 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
268 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
269 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
270 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
271 };
272
273 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
274 int is_ddr3,
275 int fsb,
276 int mem)
277 {
278 const struct cxsr_latency *latency;
279 int i;
280
281 if (fsb == 0 || mem == 0)
282 return NULL;
283
284 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
285 latency = &cxsr_latency_table[i];
286 if (is_desktop == latency->is_desktop &&
287 is_ddr3 == latency->is_ddr3 &&
288 fsb == latency->fsb_freq && mem == latency->mem_freq)
289 return latency;
290 }
291
292 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
293
294 return NULL;
295 }
296
297 static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
298 {
299 u32 val;
300
301 mutex_lock(&dev_priv->rps.hw_lock);
302
303 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
304 if (enable)
305 val &= ~FORCE_DDR_HIGH_FREQ;
306 else
307 val |= FORCE_DDR_HIGH_FREQ;
308 val &= ~FORCE_DDR_LOW_FREQ;
309 val |= FORCE_DDR_FREQ_REQ_ACK;
310 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
311
312 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
313 FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
314 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
315
316 mutex_unlock(&dev_priv->rps.hw_lock);
317 }
318
319 static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
320 {
321 u32 val;
322
323 mutex_lock(&dev_priv->rps.hw_lock);
324
325 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
326 if (enable)
327 val |= DSP_MAXFIFO_PM5_ENABLE;
328 else
329 val &= ~DSP_MAXFIFO_PM5_ENABLE;
330 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
331
332 mutex_unlock(&dev_priv->rps.hw_lock);
333 }
334
335 #define FW_WM(value, plane) \
336 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
337
338 void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
339 {
340 struct drm_device *dev = dev_priv->dev;
341 u32 val;
342
343 if (IS_VALLEYVIEW(dev)) {
344 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
345 POSTING_READ(FW_BLC_SELF_VLV);
346 dev_priv->wm.vlv.cxsr = enable;
347 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
348 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
349 POSTING_READ(FW_BLC_SELF);
350 } else if (IS_PINEVIEW(dev)) {
351 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
352 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
353 I915_WRITE(DSPFW3, val);
354 POSTING_READ(DSPFW3);
355 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
356 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
357 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
358 I915_WRITE(FW_BLC_SELF, val);
359 POSTING_READ(FW_BLC_SELF);
360 } else if (IS_I915GM(dev)) {
361 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
362 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
363 I915_WRITE(INSTPM, val);
364 POSTING_READ(INSTPM);
365 } else {
366 return;
367 }
368
369 DRM_DEBUG_KMS("memory self-refresh is %s\n",
370 enable ? "enabled" : "disabled");
371 }
372
373
374 /*
375 * Latency for FIFO fetches is dependent on several factors:
376 * - memory configuration (speed, channels)
377 * - chipset
378 * - current MCH state
379 * It can be fairly high in some situations, so here we assume a fairly
380 * pessimal value. It's a tradeoff between extra memory fetches (if we
381 * set this value too high, the FIFO will fetch frequently to stay full)
382 * and power consumption (set it too low to save power and we might see
383 * FIFO underruns and display "flicker").
384 *
385 * A value of 5us seems to be a good balance; safe for very low end
386 * platforms but not overly aggressive on lower latency configs.
387 */
388 static const int pessimal_latency_ns = 5000;
389
390 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
391 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
392
393 static int vlv_get_fifo_size(struct drm_device *dev,
394 enum pipe pipe, int plane)
395 {
396 struct drm_i915_private *dev_priv = dev->dev_private;
397 int sprite0_start, sprite1_start, size;
398
399 switch (pipe) {
400 uint32_t dsparb, dsparb2, dsparb3;
401 case PIPE_A:
402 dsparb = I915_READ(DSPARB);
403 dsparb2 = I915_READ(DSPARB2);
404 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
405 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
406 break;
407 case PIPE_B:
408 dsparb = I915_READ(DSPARB);
409 dsparb2 = I915_READ(DSPARB2);
410 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
411 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
412 break;
413 case PIPE_C:
414 dsparb2 = I915_READ(DSPARB2);
415 dsparb3 = I915_READ(DSPARB3);
416 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
417 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
418 break;
419 default:
420 return 0;
421 }
422
423 switch (plane) {
424 case 0:
425 size = sprite0_start;
426 break;
427 case 1:
428 size = sprite1_start - sprite0_start;
429 break;
430 case 2:
431 size = 512 - 1 - sprite1_start;
432 break;
433 default:
434 return 0;
435 }
436
437 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
438 pipe_name(pipe), plane == 0 ? "primary" : "sprite",
439 plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
440 size);
441
442 return size;
443 }
444
445 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
446 {
447 struct drm_i915_private *dev_priv = dev->dev_private;
448 uint32_t dsparb = I915_READ(DSPARB);
449 int size;
450
451 size = dsparb & 0x7f;
452 if (plane)
453 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
454
455 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
456 plane ? "B" : "A", size);
457
458 return size;
459 }
460
461 static int i830_get_fifo_size(struct drm_device *dev, int plane)
462 {
463 struct drm_i915_private *dev_priv = dev->dev_private;
464 uint32_t dsparb = I915_READ(DSPARB);
465 int size;
466
467 size = dsparb & 0x1ff;
468 if (plane)
469 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
470 size >>= 1; /* Convert to cachelines */
471
472 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
473 plane ? "B" : "A", size);
474
475 return size;
476 }
477
478 static int i845_get_fifo_size(struct drm_device *dev, int plane)
479 {
480 struct drm_i915_private *dev_priv = dev->dev_private;
481 uint32_t dsparb = I915_READ(DSPARB);
482 int size;
483
484 size = dsparb & 0x7f;
485 size >>= 2; /* Convert to cachelines */
486
487 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
488 plane ? "B" : "A",
489 size);
490
491 return size;
492 }
493
494 /* Pineview has different values for various configs */
495 static const struct intel_watermark_params pineview_display_wm = {
496 .fifo_size = PINEVIEW_DISPLAY_FIFO,
497 .max_wm = PINEVIEW_MAX_WM,
498 .default_wm = PINEVIEW_DFT_WM,
499 .guard_size = PINEVIEW_GUARD_WM,
500 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
501 };
502 static const struct intel_watermark_params pineview_display_hplloff_wm = {
503 .fifo_size = PINEVIEW_DISPLAY_FIFO,
504 .max_wm = PINEVIEW_MAX_WM,
505 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
506 .guard_size = PINEVIEW_GUARD_WM,
507 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
508 };
509 static const struct intel_watermark_params pineview_cursor_wm = {
510 .fifo_size = PINEVIEW_CURSOR_FIFO,
511 .max_wm = PINEVIEW_CURSOR_MAX_WM,
512 .default_wm = PINEVIEW_CURSOR_DFT_WM,
513 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
514 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
515 };
516 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
517 .fifo_size = PINEVIEW_CURSOR_FIFO,
518 .max_wm = PINEVIEW_CURSOR_MAX_WM,
519 .default_wm = PINEVIEW_CURSOR_DFT_WM,
520 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
521 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
522 };
523 static const struct intel_watermark_params g4x_wm_info = {
524 .fifo_size = G4X_FIFO_SIZE,
525 .max_wm = G4X_MAX_WM,
526 .default_wm = G4X_MAX_WM,
527 .guard_size = 2,
528 .cacheline_size = G4X_FIFO_LINE_SIZE,
529 };
530 static const struct intel_watermark_params g4x_cursor_wm_info = {
531 .fifo_size = I965_CURSOR_FIFO,
532 .max_wm = I965_CURSOR_MAX_WM,
533 .default_wm = I965_CURSOR_DFT_WM,
534 .guard_size = 2,
535 .cacheline_size = G4X_FIFO_LINE_SIZE,
536 };
537 static const struct intel_watermark_params valleyview_wm_info = {
538 .fifo_size = VALLEYVIEW_FIFO_SIZE,
539 .max_wm = VALLEYVIEW_MAX_WM,
540 .default_wm = VALLEYVIEW_MAX_WM,
541 .guard_size = 2,
542 .cacheline_size = G4X_FIFO_LINE_SIZE,
543 };
544 static const struct intel_watermark_params valleyview_cursor_wm_info = {
545 .fifo_size = I965_CURSOR_FIFO,
546 .max_wm = VALLEYVIEW_CURSOR_MAX_WM,
547 .default_wm = I965_CURSOR_DFT_WM,
548 .guard_size = 2,
549 .cacheline_size = G4X_FIFO_LINE_SIZE,
550 };
551 static const struct intel_watermark_params i965_cursor_wm_info = {
552 .fifo_size = I965_CURSOR_FIFO,
553 .max_wm = I965_CURSOR_MAX_WM,
554 .default_wm = I965_CURSOR_DFT_WM,
555 .guard_size = 2,
556 .cacheline_size = I915_FIFO_LINE_SIZE,
557 };
558 static const struct intel_watermark_params i945_wm_info = {
559 .fifo_size = I945_FIFO_SIZE,
560 .max_wm = I915_MAX_WM,
561 .default_wm = 1,
562 .guard_size = 2,
563 .cacheline_size = I915_FIFO_LINE_SIZE,
564 };
565 static const struct intel_watermark_params i915_wm_info = {
566 .fifo_size = I915_FIFO_SIZE,
567 .max_wm = I915_MAX_WM,
568 .default_wm = 1,
569 .guard_size = 2,
570 .cacheline_size = I915_FIFO_LINE_SIZE,
571 };
572 static const struct intel_watermark_params i830_a_wm_info = {
573 .fifo_size = I855GM_FIFO_SIZE,
574 .max_wm = I915_MAX_WM,
575 .default_wm = 1,
576 .guard_size = 2,
577 .cacheline_size = I830_FIFO_LINE_SIZE,
578 };
579 static const struct intel_watermark_params i830_bc_wm_info = {
580 .fifo_size = I855GM_FIFO_SIZE,
581 .max_wm = I915_MAX_WM/2,
582 .default_wm = 1,
583 .guard_size = 2,
584 .cacheline_size = I830_FIFO_LINE_SIZE,
585 };
586 static const struct intel_watermark_params i845_wm_info = {
587 .fifo_size = I830_FIFO_SIZE,
588 .max_wm = I915_MAX_WM,
589 .default_wm = 1,
590 .guard_size = 2,
591 .cacheline_size = I830_FIFO_LINE_SIZE,
592 };
593
594 /**
595 * intel_calculate_wm - calculate watermark level
596 * @clock_in_khz: pixel clock
597 * @wm: chip FIFO params
598 * @pixel_size: display pixel size
599 * @latency_ns: memory latency for the platform
600 *
601 * Calculate the watermark level (the level at which the display plane will
602 * start fetching from memory again). Each chip has a different display
603 * FIFO size and allocation, so the caller needs to figure that out and pass
604 * in the correct intel_watermark_params structure.
605 *
606 * As the pixel clock runs, the FIFO will be drained at a rate that depends
607 * on the pixel size. When it reaches the watermark level, it'll start
608 * fetching FIFO line sized based chunks from memory until the FIFO fills
609 * past the watermark point. If the FIFO drains completely, a FIFO underrun
610 * will occur, and a display engine hang could result.
611 */
612 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
613 const struct intel_watermark_params *wm,
614 int fifo_size,
615 int pixel_size,
616 unsigned long latency_ns)
617 {
618 long entries_required, wm_size;
619
620 /*
621 * Note: we need to make sure we don't overflow for various clock &
622 * latency values.
623 * clocks go from a few thousand to several hundred thousand.
624 * latency is usually a few thousand
625 */
626 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
627 1000;
628 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
629
630 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
631
632 wm_size = fifo_size - (entries_required + wm->guard_size);
633
634 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
635
636 /* Don't promote wm_size to unsigned... */
637 if (wm_size > (long)wm->max_wm)
638 wm_size = wm->max_wm;
639 if (wm_size <= 0)
640 wm_size = wm->default_wm;
641
642 /*
643 * Bspec seems to indicate that the value shouldn't be lower than
644 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
645 * Lets go for 8 which is the burst size since certain platforms
646 * already use a hardcoded 8 (which is what the spec says should be
647 * done).
648 */
649 if (wm_size <= 8)
650 wm_size = 8;
651
652 return wm_size;
653 }
654
655 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
656 {
657 struct drm_crtc *crtc, *enabled = NULL;
658
659 for_each_crtc(dev, crtc) {
660 if (intel_crtc_active(crtc)) {
661 if (enabled)
662 return NULL;
663 enabled = crtc;
664 }
665 }
666
667 return enabled;
668 }
669
670 static void pineview_update_wm(struct drm_crtc *unused_crtc)
671 {
672 struct drm_device *dev = unused_crtc->dev;
673 struct drm_i915_private *dev_priv = dev->dev_private;
674 struct drm_crtc *crtc;
675 const struct cxsr_latency *latency;
676 u32 reg;
677 unsigned long wm;
678
679 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
680 dev_priv->fsb_freq, dev_priv->mem_freq);
681 if (!latency) {
682 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
683 intel_set_memory_cxsr(dev_priv, false);
684 return;
685 }
686
687 crtc = single_enabled_crtc(dev);
688 if (crtc) {
689 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
690 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
691 int clock = adjusted_mode->crtc_clock;
692
693 /* Display SR */
694 wm = intel_calculate_wm(clock, &pineview_display_wm,
695 pineview_display_wm.fifo_size,
696 pixel_size, latency->display_sr);
697 reg = I915_READ(DSPFW1);
698 reg &= ~DSPFW_SR_MASK;
699 reg |= FW_WM(wm, SR);
700 I915_WRITE(DSPFW1, reg);
701 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
702
703 /* cursor SR */
704 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
705 pineview_display_wm.fifo_size,
706 pixel_size, latency->cursor_sr);
707 reg = I915_READ(DSPFW3);
708 reg &= ~DSPFW_CURSOR_SR_MASK;
709 reg |= FW_WM(wm, CURSOR_SR);
710 I915_WRITE(DSPFW3, reg);
711
712 /* Display HPLL off SR */
713 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
714 pineview_display_hplloff_wm.fifo_size,
715 pixel_size, latency->display_hpll_disable);
716 reg = I915_READ(DSPFW3);
717 reg &= ~DSPFW_HPLL_SR_MASK;
718 reg |= FW_WM(wm, HPLL_SR);
719 I915_WRITE(DSPFW3, reg);
720
721 /* cursor HPLL off SR */
722 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
723 pineview_display_hplloff_wm.fifo_size,
724 pixel_size, latency->cursor_hpll_disable);
725 reg = I915_READ(DSPFW3);
726 reg &= ~DSPFW_HPLL_CURSOR_MASK;
727 reg |= FW_WM(wm, HPLL_CURSOR);
728 I915_WRITE(DSPFW3, reg);
729 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
730
731 intel_set_memory_cxsr(dev_priv, true);
732 } else {
733 intel_set_memory_cxsr(dev_priv, false);
734 }
735 }
736
737 static bool g4x_compute_wm0(struct drm_device *dev,
738 int plane,
739 const struct intel_watermark_params *display,
740 int display_latency_ns,
741 const struct intel_watermark_params *cursor,
742 int cursor_latency_ns,
743 int *plane_wm,
744 int *cursor_wm)
745 {
746 struct drm_crtc *crtc;
747 const struct drm_display_mode *adjusted_mode;
748 int htotal, hdisplay, clock, pixel_size;
749 int line_time_us, line_count;
750 int entries, tlb_miss;
751
752 crtc = intel_get_crtc_for_plane(dev, plane);
753 if (!intel_crtc_active(crtc)) {
754 *cursor_wm = cursor->guard_size;
755 *plane_wm = display->guard_size;
756 return false;
757 }
758
759 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
760 clock = adjusted_mode->crtc_clock;
761 htotal = adjusted_mode->crtc_htotal;
762 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
763 pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
764
765 /* Use the small buffer method to calculate plane watermark */
766 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
767 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
768 if (tlb_miss > 0)
769 entries += tlb_miss;
770 entries = DIV_ROUND_UP(entries, display->cacheline_size);
771 *plane_wm = entries + display->guard_size;
772 if (*plane_wm > (int)display->max_wm)
773 *plane_wm = display->max_wm;
774
775 /* Use the large buffer method to calculate cursor watermark */
776 line_time_us = max(htotal * 1000 / clock, 1);
777 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
778 entries = line_count * crtc->cursor->state->crtc_w * pixel_size;
779 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
780 if (tlb_miss > 0)
781 entries += tlb_miss;
782 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
783 *cursor_wm = entries + cursor->guard_size;
784 if (*cursor_wm > (int)cursor->max_wm)
785 *cursor_wm = (int)cursor->max_wm;
786
787 return true;
788 }
789
790 /*
791 * Check the wm result.
792 *
793 * If any calculated watermark values is larger than the maximum value that
794 * can be programmed into the associated watermark register, that watermark
795 * must be disabled.
796 */
797 static bool g4x_check_srwm(struct drm_device *dev,
798 int display_wm, int cursor_wm,
799 const struct intel_watermark_params *display,
800 const struct intel_watermark_params *cursor)
801 {
802 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
803 display_wm, cursor_wm);
804
805 if (display_wm > display->max_wm) {
806 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
807 display_wm, display->max_wm);
808 return false;
809 }
810
811 if (cursor_wm > cursor->max_wm) {
812 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
813 cursor_wm, cursor->max_wm);
814 return false;
815 }
816
817 if (!(display_wm || cursor_wm)) {
818 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
819 return false;
820 }
821
822 return true;
823 }
824
825 static bool g4x_compute_srwm(struct drm_device *dev,
826 int plane,
827 int latency_ns,
828 const struct intel_watermark_params *display,
829 const struct intel_watermark_params *cursor,
830 int *display_wm, int *cursor_wm)
831 {
832 struct drm_crtc *crtc;
833 const struct drm_display_mode *adjusted_mode;
834 int hdisplay, htotal, pixel_size, clock;
835 unsigned long line_time_us;
836 int line_count, line_size;
837 int small, large;
838 int entries;
839
840 if (!latency_ns) {
841 *display_wm = *cursor_wm = 0;
842 return false;
843 }
844
845 crtc = intel_get_crtc_for_plane(dev, plane);
846 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
847 clock = adjusted_mode->crtc_clock;
848 htotal = adjusted_mode->crtc_htotal;
849 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
850 pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
851
852 line_time_us = max(htotal * 1000 / clock, 1);
853 line_count = (latency_ns / line_time_us + 1000) / 1000;
854 line_size = hdisplay * pixel_size;
855
856 /* Use the minimum of the small and large buffer method for primary */
857 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
858 large = line_count * line_size;
859
860 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
861 *display_wm = entries + display->guard_size;
862
863 /* calculate the self-refresh watermark for display cursor */
864 entries = line_count * pixel_size * crtc->cursor->state->crtc_w;
865 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
866 *cursor_wm = entries + cursor->guard_size;
867
868 return g4x_check_srwm(dev,
869 *display_wm, *cursor_wm,
870 display, cursor);
871 }
872
873 #define FW_WM_VLV(value, plane) \
874 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
875
876 static void vlv_write_wm_values(struct intel_crtc *crtc,
877 const struct vlv_wm_values *wm)
878 {
879 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
880 enum pipe pipe = crtc->pipe;
881
882 I915_WRITE(VLV_DDL(pipe),
883 (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
884 (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
885 (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
886 (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
887
888 I915_WRITE(DSPFW1,
889 FW_WM(wm->sr.plane, SR) |
890 FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
891 FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
892 FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
893 I915_WRITE(DSPFW2,
894 FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
895 FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
896 FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
897 I915_WRITE(DSPFW3,
898 FW_WM(wm->sr.cursor, CURSOR_SR));
899
900 if (IS_CHERRYVIEW(dev_priv)) {
901 I915_WRITE(DSPFW7_CHV,
902 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
903 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
904 I915_WRITE(DSPFW8_CHV,
905 FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
906 FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
907 I915_WRITE(DSPFW9_CHV,
908 FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
909 FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
910 I915_WRITE(DSPHOWM,
911 FW_WM(wm->sr.plane >> 9, SR_HI) |
912 FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
913 FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
914 FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
915 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
916 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
917 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
918 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
919 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
920 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
921 } else {
922 I915_WRITE(DSPFW7,
923 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
924 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
925 I915_WRITE(DSPHOWM,
926 FW_WM(wm->sr.plane >> 9, SR_HI) |
927 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
928 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
929 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
930 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
931 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
932 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
933 }
934
935 /* zero (unused) WM1 watermarks */
936 I915_WRITE(DSPFW4, 0);
937 I915_WRITE(DSPFW5, 0);
938 I915_WRITE(DSPFW6, 0);
939 I915_WRITE(DSPHOWM1, 0);
940
941 POSTING_READ(DSPFW1);
942 }
943
944 #undef FW_WM_VLV
945
946 enum vlv_wm_level {
947 VLV_WM_LEVEL_PM2,
948 VLV_WM_LEVEL_PM5,
949 VLV_WM_LEVEL_DDR_DVFS,
950 };
951
952 /* latency must be in 0.1us units. */
953 static unsigned int vlv_wm_method2(unsigned int pixel_rate,
954 unsigned int pipe_htotal,
955 unsigned int horiz_pixels,
956 unsigned int bytes_per_pixel,
957 unsigned int latency)
958 {
959 unsigned int ret;
960
961 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
962 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
963 ret = DIV_ROUND_UP(ret, 64);
964
965 return ret;
966 }
967
968 static void vlv_setup_wm_latency(struct drm_device *dev)
969 {
970 struct drm_i915_private *dev_priv = dev->dev_private;
971
972 /* all latencies in usec */
973 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
974
975 dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
976
977 if (IS_CHERRYVIEW(dev_priv)) {
978 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
979 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
980
981 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
982 }
983 }
984
985 static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
986 struct intel_crtc *crtc,
987 const struct intel_plane_state *state,
988 int level)
989 {
990 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
991 int clock, htotal, pixel_size, width, wm;
992
993 if (dev_priv->wm.pri_latency[level] == 0)
994 return USHRT_MAX;
995
996 if (!state->visible)
997 return 0;
998
999 pixel_size = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1000 clock = crtc->config->base.adjusted_mode.crtc_clock;
1001 htotal = crtc->config->base.adjusted_mode.crtc_htotal;
1002 width = crtc->config->pipe_src_w;
1003 if (WARN_ON(htotal == 0))
1004 htotal = 1;
1005
1006 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1007 /*
1008 * FIXME the formula gives values that are
1009 * too big for the cursor FIFO, and hence we
1010 * would never be able to use cursors. For
1011 * now just hardcode the watermark.
1012 */
1013 wm = 63;
1014 } else {
1015 wm = vlv_wm_method2(clock, htotal, width, pixel_size,
1016 dev_priv->wm.pri_latency[level] * 10);
1017 }
1018
1019 return min_t(int, wm, USHRT_MAX);
1020 }
1021
1022 static void vlv_compute_fifo(struct intel_crtc *crtc)
1023 {
1024 struct drm_device *dev = crtc->base.dev;
1025 struct vlv_wm_state *wm_state = &crtc->wm_state;
1026 struct intel_plane *plane;
1027 unsigned int total_rate = 0;
1028 const int fifo_size = 512 - 1;
1029 int fifo_extra, fifo_left = fifo_size;
1030
1031 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1032 struct intel_plane_state *state =
1033 to_intel_plane_state(plane->base.state);
1034
1035 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1036 continue;
1037
1038 if (state->visible) {
1039 wm_state->num_active_planes++;
1040 total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1041 }
1042 }
1043
1044 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1045 struct intel_plane_state *state =
1046 to_intel_plane_state(plane->base.state);
1047 unsigned int rate;
1048
1049 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1050 plane->wm.fifo_size = 63;
1051 continue;
1052 }
1053
1054 if (!state->visible) {
1055 plane->wm.fifo_size = 0;
1056 continue;
1057 }
1058
1059 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1060 plane->wm.fifo_size = fifo_size * rate / total_rate;
1061 fifo_left -= plane->wm.fifo_size;
1062 }
1063
1064 fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1065
1066 /* spread the remainder evenly */
1067 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1068 int plane_extra;
1069
1070 if (fifo_left == 0)
1071 break;
1072
1073 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1074 continue;
1075
1076 /* give it all to the first plane if none are active */
1077 if (plane->wm.fifo_size == 0 &&
1078 wm_state->num_active_planes)
1079 continue;
1080
1081 plane_extra = min(fifo_extra, fifo_left);
1082 plane->wm.fifo_size += plane_extra;
1083 fifo_left -= plane_extra;
1084 }
1085
1086 WARN_ON(fifo_left != 0);
1087 }
1088
1089 static void vlv_invert_wms(struct intel_crtc *crtc)
1090 {
1091 struct vlv_wm_state *wm_state = &crtc->wm_state;
1092 int level;
1093
1094 for (level = 0; level < wm_state->num_levels; level++) {
1095 struct drm_device *dev = crtc->base.dev;
1096 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1097 struct intel_plane *plane;
1098
1099 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1100 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1101
1102 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1103 switch (plane->base.type) {
1104 int sprite;
1105 case DRM_PLANE_TYPE_CURSOR:
1106 wm_state->wm[level].cursor = plane->wm.fifo_size -
1107 wm_state->wm[level].cursor;
1108 break;
1109 case DRM_PLANE_TYPE_PRIMARY:
1110 wm_state->wm[level].primary = plane->wm.fifo_size -
1111 wm_state->wm[level].primary;
1112 break;
1113 case DRM_PLANE_TYPE_OVERLAY:
1114 sprite = plane->plane;
1115 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1116 wm_state->wm[level].sprite[sprite];
1117 break;
1118 }
1119 }
1120 }
1121 }
1122
1123 static void vlv_compute_wm(struct intel_crtc *crtc)
1124 {
1125 struct drm_device *dev = crtc->base.dev;
1126 struct vlv_wm_state *wm_state = &crtc->wm_state;
1127 struct intel_plane *plane;
1128 int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1129 int level;
1130
1131 memset(wm_state, 0, sizeof(*wm_state));
1132
1133 wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
1134 wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
1135
1136 wm_state->num_active_planes = 0;
1137
1138 vlv_compute_fifo(crtc);
1139
1140 if (wm_state->num_active_planes != 1)
1141 wm_state->cxsr = false;
1142
1143 if (wm_state->cxsr) {
1144 for (level = 0; level < wm_state->num_levels; level++) {
1145 wm_state->sr[level].plane = sr_fifo_size;
1146 wm_state->sr[level].cursor = 63;
1147 }
1148 }
1149
1150 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1151 struct intel_plane_state *state =
1152 to_intel_plane_state(plane->base.state);
1153
1154 if (!state->visible)
1155 continue;
1156
1157 /* normal watermarks */
1158 for (level = 0; level < wm_state->num_levels; level++) {
1159 int wm = vlv_compute_wm_level(plane, crtc, state, level);
1160 int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1161
1162 /* hack */
1163 if (WARN_ON(level == 0 && wm > max_wm))
1164 wm = max_wm;
1165
1166 if (wm > plane->wm.fifo_size)
1167 break;
1168
1169 switch (plane->base.type) {
1170 int sprite;
1171 case DRM_PLANE_TYPE_CURSOR:
1172 wm_state->wm[level].cursor = wm;
1173 break;
1174 case DRM_PLANE_TYPE_PRIMARY:
1175 wm_state->wm[level].primary = wm;
1176 break;
1177 case DRM_PLANE_TYPE_OVERLAY:
1178 sprite = plane->plane;
1179 wm_state->wm[level].sprite[sprite] = wm;
1180 break;
1181 }
1182 }
1183
1184 wm_state->num_levels = level;
1185
1186 if (!wm_state->cxsr)
1187 continue;
1188
1189 /* maxfifo watermarks */
1190 switch (plane->base.type) {
1191 int sprite, level;
1192 case DRM_PLANE_TYPE_CURSOR:
1193 for (level = 0; level < wm_state->num_levels; level++)
1194 wm_state->sr[level].cursor =
1195 wm_state->sr[level].cursor;
1196 break;
1197 case DRM_PLANE_TYPE_PRIMARY:
1198 for (level = 0; level < wm_state->num_levels; level++)
1199 wm_state->sr[level].plane =
1200 min(wm_state->sr[level].plane,
1201 wm_state->wm[level].primary);
1202 break;
1203 case DRM_PLANE_TYPE_OVERLAY:
1204 sprite = plane->plane;
1205 for (level = 0; level < wm_state->num_levels; level++)
1206 wm_state->sr[level].plane =
1207 min(wm_state->sr[level].plane,
1208 wm_state->wm[level].sprite[sprite]);
1209 break;
1210 }
1211 }
1212
1213 /* clear any (partially) filled invalid levels */
1214 for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
1215 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1216 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1217 }
1218
1219 vlv_invert_wms(crtc);
1220 }
1221
1222 #define VLV_FIFO(plane, value) \
1223 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1224
1225 static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1226 {
1227 struct drm_device *dev = crtc->base.dev;
1228 struct drm_i915_private *dev_priv = to_i915(dev);
1229 struct intel_plane *plane;
1230 int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1231
1232 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1233 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1234 WARN_ON(plane->wm.fifo_size != 63);
1235 continue;
1236 }
1237
1238 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1239 sprite0_start = plane->wm.fifo_size;
1240 else if (plane->plane == 0)
1241 sprite1_start = sprite0_start + plane->wm.fifo_size;
1242 else
1243 fifo_size = sprite1_start + plane->wm.fifo_size;
1244 }
1245
1246 WARN_ON(fifo_size != 512 - 1);
1247
1248 DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1249 pipe_name(crtc->pipe), sprite0_start,
1250 sprite1_start, fifo_size);
1251
1252 switch (crtc->pipe) {
1253 uint32_t dsparb, dsparb2, dsparb3;
1254 case PIPE_A:
1255 dsparb = I915_READ(DSPARB);
1256 dsparb2 = I915_READ(DSPARB2);
1257
1258 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1259 VLV_FIFO(SPRITEB, 0xff));
1260 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1261 VLV_FIFO(SPRITEB, sprite1_start));
1262
1263 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1264 VLV_FIFO(SPRITEB_HI, 0x1));
1265 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1266 VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1267
1268 I915_WRITE(DSPARB, dsparb);
1269 I915_WRITE(DSPARB2, dsparb2);
1270 break;
1271 case PIPE_B:
1272 dsparb = I915_READ(DSPARB);
1273 dsparb2 = I915_READ(DSPARB2);
1274
1275 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1276 VLV_FIFO(SPRITED, 0xff));
1277 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1278 VLV_FIFO(SPRITED, sprite1_start));
1279
1280 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1281 VLV_FIFO(SPRITED_HI, 0xff));
1282 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1283 VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1284
1285 I915_WRITE(DSPARB, dsparb);
1286 I915_WRITE(DSPARB2, dsparb2);
1287 break;
1288 case PIPE_C:
1289 dsparb3 = I915_READ(DSPARB3);
1290 dsparb2 = I915_READ(DSPARB2);
1291
1292 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1293 VLV_FIFO(SPRITEF, 0xff));
1294 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1295 VLV_FIFO(SPRITEF, sprite1_start));
1296
1297 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1298 VLV_FIFO(SPRITEF_HI, 0xff));
1299 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1300 VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1301
1302 I915_WRITE(DSPARB3, dsparb3);
1303 I915_WRITE(DSPARB2, dsparb2);
1304 break;
1305 default:
1306 break;
1307 }
1308 }
1309
1310 #undef VLV_FIFO
1311
1312 static void vlv_merge_wm(struct drm_device *dev,
1313 struct vlv_wm_values *wm)
1314 {
1315 struct intel_crtc *crtc;
1316 int num_active_crtcs = 0;
1317
1318 wm->level = to_i915(dev)->wm.max_level;
1319 wm->cxsr = true;
1320
1321 for_each_intel_crtc(dev, crtc) {
1322 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1323
1324 if (!crtc->active)
1325 continue;
1326
1327 if (!wm_state->cxsr)
1328 wm->cxsr = false;
1329
1330 num_active_crtcs++;
1331 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1332 }
1333
1334 if (num_active_crtcs != 1)
1335 wm->cxsr = false;
1336
1337 if (num_active_crtcs > 1)
1338 wm->level = VLV_WM_LEVEL_PM2;
1339
1340 for_each_intel_crtc(dev, crtc) {
1341 struct vlv_wm_state *wm_state = &crtc->wm_state;
1342 enum pipe pipe = crtc->pipe;
1343
1344 if (!crtc->active)
1345 continue;
1346
1347 wm->pipe[pipe] = wm_state->wm[wm->level];
1348 if (wm->cxsr)
1349 wm->sr = wm_state->sr[wm->level];
1350
1351 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1352 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1353 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1354 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1355 }
1356 }
1357
1358 static void vlv_update_wm(struct drm_crtc *crtc)
1359 {
1360 struct drm_device *dev = crtc->dev;
1361 struct drm_i915_private *dev_priv = dev->dev_private;
1362 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1363 enum pipe pipe = intel_crtc->pipe;
1364 struct vlv_wm_values wm = {};
1365
1366 vlv_compute_wm(intel_crtc);
1367 vlv_merge_wm(dev, &wm);
1368
1369 if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1370 /* FIXME should be part of crtc atomic commit */
1371 vlv_pipe_set_fifo_size(intel_crtc);
1372 return;
1373 }
1374
1375 if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1376 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1377 chv_set_memory_dvfs(dev_priv, false);
1378
1379 if (wm.level < VLV_WM_LEVEL_PM5 &&
1380 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1381 chv_set_memory_pm5(dev_priv, false);
1382
1383 if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
1384 intel_set_memory_cxsr(dev_priv, false);
1385
1386 /* FIXME should be part of crtc atomic commit */
1387 vlv_pipe_set_fifo_size(intel_crtc);
1388
1389 vlv_write_wm_values(intel_crtc, &wm);
1390
1391 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1392 "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1393 pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1394 wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1395 wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1396
1397 if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
1398 intel_set_memory_cxsr(dev_priv, true);
1399
1400 if (wm.level >= VLV_WM_LEVEL_PM5 &&
1401 dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1402 chv_set_memory_pm5(dev_priv, true);
1403
1404 if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1405 dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1406 chv_set_memory_dvfs(dev_priv, true);
1407
1408 dev_priv->wm.vlv = wm;
1409 }
1410
1411 #define single_plane_enabled(mask) is_power_of_2(mask)
1412
1413 static void g4x_update_wm(struct drm_crtc *crtc)
1414 {
1415 struct drm_device *dev = crtc->dev;
1416 static const int sr_latency_ns = 12000;
1417 struct drm_i915_private *dev_priv = dev->dev_private;
1418 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1419 int plane_sr, cursor_sr;
1420 unsigned int enabled = 0;
1421 bool cxsr_enabled;
1422
1423 if (g4x_compute_wm0(dev, PIPE_A,
1424 &g4x_wm_info, pessimal_latency_ns,
1425 &g4x_cursor_wm_info, pessimal_latency_ns,
1426 &planea_wm, &cursora_wm))
1427 enabled |= 1 << PIPE_A;
1428
1429 if (g4x_compute_wm0(dev, PIPE_B,
1430 &g4x_wm_info, pessimal_latency_ns,
1431 &g4x_cursor_wm_info, pessimal_latency_ns,
1432 &planeb_wm, &cursorb_wm))
1433 enabled |= 1 << PIPE_B;
1434
1435 if (single_plane_enabled(enabled) &&
1436 g4x_compute_srwm(dev, ffs(enabled) - 1,
1437 sr_latency_ns,
1438 &g4x_wm_info,
1439 &g4x_cursor_wm_info,
1440 &plane_sr, &cursor_sr)) {
1441 cxsr_enabled = true;
1442 } else {
1443 cxsr_enabled = false;
1444 intel_set_memory_cxsr(dev_priv, false);
1445 plane_sr = cursor_sr = 0;
1446 }
1447
1448 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1449 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1450 planea_wm, cursora_wm,
1451 planeb_wm, cursorb_wm,
1452 plane_sr, cursor_sr);
1453
1454 I915_WRITE(DSPFW1,
1455 FW_WM(plane_sr, SR) |
1456 FW_WM(cursorb_wm, CURSORB) |
1457 FW_WM(planeb_wm, PLANEB) |
1458 FW_WM(planea_wm, PLANEA));
1459 I915_WRITE(DSPFW2,
1460 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1461 FW_WM(cursora_wm, CURSORA));
1462 /* HPLL off in SR has some issues on G4x... disable it */
1463 I915_WRITE(DSPFW3,
1464 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1465 FW_WM(cursor_sr, CURSOR_SR));
1466
1467 if (cxsr_enabled)
1468 intel_set_memory_cxsr(dev_priv, true);
1469 }
1470
1471 static void i965_update_wm(struct drm_crtc *unused_crtc)
1472 {
1473 struct drm_device *dev = unused_crtc->dev;
1474 struct drm_i915_private *dev_priv = dev->dev_private;
1475 struct drm_crtc *crtc;
1476 int srwm = 1;
1477 int cursor_sr = 16;
1478 bool cxsr_enabled;
1479
1480 /* Calc sr entries for one plane configs */
1481 crtc = single_enabled_crtc(dev);
1482 if (crtc) {
1483 /* self-refresh has much higher latency */
1484 static const int sr_latency_ns = 12000;
1485 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1486 int clock = adjusted_mode->crtc_clock;
1487 int htotal = adjusted_mode->crtc_htotal;
1488 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
1489 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
1490 unsigned long line_time_us;
1491 int entries;
1492
1493 line_time_us = max(htotal * 1000 / clock, 1);
1494
1495 /* Use ns/us then divide to preserve precision */
1496 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1497 pixel_size * hdisplay;
1498 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1499 srwm = I965_FIFO_SIZE - entries;
1500 if (srwm < 0)
1501 srwm = 1;
1502 srwm &= 0x1ff;
1503 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1504 entries, srwm);
1505
1506 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1507 pixel_size * crtc->cursor->state->crtc_w;
1508 entries = DIV_ROUND_UP(entries,
1509 i965_cursor_wm_info.cacheline_size);
1510 cursor_sr = i965_cursor_wm_info.fifo_size -
1511 (entries + i965_cursor_wm_info.guard_size);
1512
1513 if (cursor_sr > i965_cursor_wm_info.max_wm)
1514 cursor_sr = i965_cursor_wm_info.max_wm;
1515
1516 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1517 "cursor %d\n", srwm, cursor_sr);
1518
1519 cxsr_enabled = true;
1520 } else {
1521 cxsr_enabled = false;
1522 /* Turn off self refresh if both pipes are enabled */
1523 intel_set_memory_cxsr(dev_priv, false);
1524 }
1525
1526 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1527 srwm);
1528
1529 /* 965 has limitations... */
1530 I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1531 FW_WM(8, CURSORB) |
1532 FW_WM(8, PLANEB) |
1533 FW_WM(8, PLANEA));
1534 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1535 FW_WM(8, PLANEC_OLD));
1536 /* update cursor SR watermark */
1537 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
1538
1539 if (cxsr_enabled)
1540 intel_set_memory_cxsr(dev_priv, true);
1541 }
1542
1543 #undef FW_WM
1544
1545 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1546 {
1547 struct drm_device *dev = unused_crtc->dev;
1548 struct drm_i915_private *dev_priv = dev->dev_private;
1549 const struct intel_watermark_params *wm_info;
1550 uint32_t fwater_lo;
1551 uint32_t fwater_hi;
1552 int cwm, srwm = 1;
1553 int fifo_size;
1554 int planea_wm, planeb_wm;
1555 struct drm_crtc *crtc, *enabled = NULL;
1556
1557 if (IS_I945GM(dev))
1558 wm_info = &i945_wm_info;
1559 else if (!IS_GEN2(dev))
1560 wm_info = &i915_wm_info;
1561 else
1562 wm_info = &i830_a_wm_info;
1563
1564 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1565 crtc = intel_get_crtc_for_plane(dev, 0);
1566 if (intel_crtc_active(crtc)) {
1567 const struct drm_display_mode *adjusted_mode;
1568 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
1569 if (IS_GEN2(dev))
1570 cpp = 4;
1571
1572 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1573 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1574 wm_info, fifo_size, cpp,
1575 pessimal_latency_ns);
1576 enabled = crtc;
1577 } else {
1578 planea_wm = fifo_size - wm_info->guard_size;
1579 if (planea_wm > (long)wm_info->max_wm)
1580 planea_wm = wm_info->max_wm;
1581 }
1582
1583 if (IS_GEN2(dev))
1584 wm_info = &i830_bc_wm_info;
1585
1586 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1587 crtc = intel_get_crtc_for_plane(dev, 1);
1588 if (intel_crtc_active(crtc)) {
1589 const struct drm_display_mode *adjusted_mode;
1590 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
1591 if (IS_GEN2(dev))
1592 cpp = 4;
1593
1594 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1595 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1596 wm_info, fifo_size, cpp,
1597 pessimal_latency_ns);
1598 if (enabled == NULL)
1599 enabled = crtc;
1600 else
1601 enabled = NULL;
1602 } else {
1603 planeb_wm = fifo_size - wm_info->guard_size;
1604 if (planeb_wm > (long)wm_info->max_wm)
1605 planeb_wm = wm_info->max_wm;
1606 }
1607
1608 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1609
1610 if (IS_I915GM(dev) && enabled) {
1611 struct drm_i915_gem_object *obj;
1612
1613 obj = intel_fb_obj(enabled->primary->state->fb);
1614
1615 /* self-refresh seems busted with untiled */
1616 if (obj->tiling_mode == I915_TILING_NONE)
1617 enabled = NULL;
1618 }
1619
1620 /*
1621 * Overlay gets an aggressive default since video jitter is bad.
1622 */
1623 cwm = 2;
1624
1625 /* Play safe and disable self-refresh before adjusting watermarks. */
1626 intel_set_memory_cxsr(dev_priv, false);
1627
1628 /* Calc sr entries for one plane configs */
1629 if (HAS_FW_BLC(dev) && enabled) {
1630 /* self-refresh has much higher latency */
1631 static const int sr_latency_ns = 6000;
1632 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode;
1633 int clock = adjusted_mode->crtc_clock;
1634 int htotal = adjusted_mode->crtc_htotal;
1635 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
1636 int pixel_size = enabled->primary->state->fb->bits_per_pixel / 8;
1637 unsigned long line_time_us;
1638 int entries;
1639
1640 line_time_us = max(htotal * 1000 / clock, 1);
1641
1642 /* Use ns/us then divide to preserve precision */
1643 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1644 pixel_size * hdisplay;
1645 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1646 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1647 srwm = wm_info->fifo_size - entries;
1648 if (srwm < 0)
1649 srwm = 1;
1650
1651 if (IS_I945G(dev) || IS_I945GM(dev))
1652 I915_WRITE(FW_BLC_SELF,
1653 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1654 else if (IS_I915GM(dev))
1655 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1656 }
1657
1658 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1659 planea_wm, planeb_wm, cwm, srwm);
1660
1661 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1662 fwater_hi = (cwm & 0x1f);
1663
1664 /* Set request length to 8 cachelines per fetch */
1665 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1666 fwater_hi = fwater_hi | (1 << 8);
1667
1668 I915_WRITE(FW_BLC, fwater_lo);
1669 I915_WRITE(FW_BLC2, fwater_hi);
1670
1671 if (enabled)
1672 intel_set_memory_cxsr(dev_priv, true);
1673 }
1674
1675 static void i845_update_wm(struct drm_crtc *unused_crtc)
1676 {
1677 struct drm_device *dev = unused_crtc->dev;
1678 struct drm_i915_private *dev_priv = dev->dev_private;
1679 struct drm_crtc *crtc;
1680 const struct drm_display_mode *adjusted_mode;
1681 uint32_t fwater_lo;
1682 int planea_wm;
1683
1684 crtc = single_enabled_crtc(dev);
1685 if (crtc == NULL)
1686 return;
1687
1688 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1689 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1690 &i845_wm_info,
1691 dev_priv->display.get_fifo_size(dev, 0),
1692 4, pessimal_latency_ns);
1693 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1694 fwater_lo |= (3<<8) | planea_wm;
1695
1696 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1697
1698 I915_WRITE(FW_BLC, fwater_lo);
1699 }
1700
1701 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
1702 {
1703 uint32_t pixel_rate;
1704
1705 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
1706
1707 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1708 * adjust the pixel_rate here. */
1709
1710 if (pipe_config->pch_pfit.enabled) {
1711 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1712 uint32_t pfit_size = pipe_config->pch_pfit.size;
1713
1714 pipe_w = pipe_config->pipe_src_w;
1715 pipe_h = pipe_config->pipe_src_h;
1716
1717 pfit_w = (pfit_size >> 16) & 0xFFFF;
1718 pfit_h = pfit_size & 0xFFFF;
1719 if (pipe_w < pfit_w)
1720 pipe_w = pfit_w;
1721 if (pipe_h < pfit_h)
1722 pipe_h = pfit_h;
1723
1724 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1725 pfit_w * pfit_h);
1726 }
1727
1728 return pixel_rate;
1729 }
1730
1731 /* latency must be in 0.1us units. */
1732 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
1733 uint32_t latency)
1734 {
1735 uint64_t ret;
1736
1737 if (WARN(latency == 0, "Latency value missing\n"))
1738 return UINT_MAX;
1739
1740 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1741 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1742
1743 return ret;
1744 }
1745
1746 /* latency must be in 0.1us units. */
1747 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1748 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1749 uint32_t latency)
1750 {
1751 uint32_t ret;
1752
1753 if (WARN(latency == 0, "Latency value missing\n"))
1754 return UINT_MAX;
1755
1756 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1757 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1758 ret = DIV_ROUND_UP(ret, 64) + 2;
1759 return ret;
1760 }
1761
1762 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1763 uint8_t bytes_per_pixel)
1764 {
1765 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1766 }
1767
1768 struct skl_pipe_wm_parameters {
1769 bool active;
1770 uint32_t pipe_htotal;
1771 uint32_t pixel_rate; /* in KHz */
1772 struct intel_plane_wm_parameters plane[I915_MAX_PLANES];
1773 struct intel_plane_wm_parameters cursor;
1774 };
1775
1776 struct ilk_pipe_wm_parameters {
1777 bool active;
1778 uint32_t pipe_htotal;
1779 uint32_t pixel_rate;
1780 struct intel_plane_wm_parameters pri;
1781 struct intel_plane_wm_parameters spr;
1782 struct intel_plane_wm_parameters cur;
1783 };
1784
1785 struct ilk_wm_maximums {
1786 uint16_t pri;
1787 uint16_t spr;
1788 uint16_t cur;
1789 uint16_t fbc;
1790 };
1791
1792 /* used in computing the new watermarks state */
1793 struct intel_wm_config {
1794 unsigned int num_pipes_active;
1795 bool sprites_enabled;
1796 bool sprites_scaled;
1797 };
1798
1799 /*
1800 * For both WM_PIPE and WM_LP.
1801 * mem_value must be in 0.1us units.
1802 */
1803 static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params,
1804 uint32_t mem_value,
1805 bool is_lp)
1806 {
1807 uint32_t method1, method2;
1808
1809 if (!params->active || !params->pri.enabled)
1810 return 0;
1811
1812 method1 = ilk_wm_method1(params->pixel_rate,
1813 params->pri.bytes_per_pixel,
1814 mem_value);
1815
1816 if (!is_lp)
1817 return method1;
1818
1819 method2 = ilk_wm_method2(params->pixel_rate,
1820 params->pipe_htotal,
1821 params->pri.horiz_pixels,
1822 params->pri.bytes_per_pixel,
1823 mem_value);
1824
1825 return min(method1, method2);
1826 }
1827
1828 /*
1829 * For both WM_PIPE and WM_LP.
1830 * mem_value must be in 0.1us units.
1831 */
1832 static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params,
1833 uint32_t mem_value)
1834 {
1835 uint32_t method1, method2;
1836
1837 if (!params->active || !params->spr.enabled)
1838 return 0;
1839
1840 method1 = ilk_wm_method1(params->pixel_rate,
1841 params->spr.bytes_per_pixel,
1842 mem_value);
1843 method2 = ilk_wm_method2(params->pixel_rate,
1844 params->pipe_htotal,
1845 params->spr.horiz_pixels,
1846 params->spr.bytes_per_pixel,
1847 mem_value);
1848 return min(method1, method2);
1849 }
1850
1851 /*
1852 * For both WM_PIPE and WM_LP.
1853 * mem_value must be in 0.1us units.
1854 */
1855 static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params,
1856 uint32_t mem_value)
1857 {
1858 if (!params->active || !params->cur.enabled)
1859 return 0;
1860
1861 return ilk_wm_method2(params->pixel_rate,
1862 params->pipe_htotal,
1863 params->cur.horiz_pixels,
1864 params->cur.bytes_per_pixel,
1865 mem_value);
1866 }
1867
1868 /* Only for WM_LP. */
1869 static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params,
1870 uint32_t pri_val)
1871 {
1872 if (!params->active || !params->pri.enabled)
1873 return 0;
1874
1875 return ilk_wm_fbc(pri_val,
1876 params->pri.horiz_pixels,
1877 params->pri.bytes_per_pixel);
1878 }
1879
1880 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1881 {
1882 if (INTEL_INFO(dev)->gen >= 8)
1883 return 3072;
1884 else if (INTEL_INFO(dev)->gen >= 7)
1885 return 768;
1886 else
1887 return 512;
1888 }
1889
1890 static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1891 int level, bool is_sprite)
1892 {
1893 if (INTEL_INFO(dev)->gen >= 8)
1894 /* BDW primary/sprite plane watermarks */
1895 return level == 0 ? 255 : 2047;
1896 else if (INTEL_INFO(dev)->gen >= 7)
1897 /* IVB/HSW primary/sprite plane watermarks */
1898 return level == 0 ? 127 : 1023;
1899 else if (!is_sprite)
1900 /* ILK/SNB primary plane watermarks */
1901 return level == 0 ? 127 : 511;
1902 else
1903 /* ILK/SNB sprite plane watermarks */
1904 return level == 0 ? 63 : 255;
1905 }
1906
1907 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1908 int level)
1909 {
1910 if (INTEL_INFO(dev)->gen >= 7)
1911 return level == 0 ? 63 : 255;
1912 else
1913 return level == 0 ? 31 : 63;
1914 }
1915
1916 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1917 {
1918 if (INTEL_INFO(dev)->gen >= 8)
1919 return 31;
1920 else
1921 return 15;
1922 }
1923
1924 /* Calculate the maximum primary/sprite plane watermark */
1925 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1926 int level,
1927 const struct intel_wm_config *config,
1928 enum intel_ddb_partitioning ddb_partitioning,
1929 bool is_sprite)
1930 {
1931 unsigned int fifo_size = ilk_display_fifo_size(dev);
1932
1933 /* if sprites aren't enabled, sprites get nothing */
1934 if (is_sprite && !config->sprites_enabled)
1935 return 0;
1936
1937 /* HSW allows LP1+ watermarks even with multiple pipes */
1938 if (level == 0 || config->num_pipes_active > 1) {
1939 fifo_size /= INTEL_INFO(dev)->num_pipes;
1940
1941 /*
1942 * For some reason the non self refresh
1943 * FIFO size is only half of the self
1944 * refresh FIFO size on ILK/SNB.
1945 */
1946 if (INTEL_INFO(dev)->gen <= 6)
1947 fifo_size /= 2;
1948 }
1949
1950 if (config->sprites_enabled) {
1951 /* level 0 is always calculated with 1:1 split */
1952 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1953 if (is_sprite)
1954 fifo_size *= 5;
1955 fifo_size /= 6;
1956 } else {
1957 fifo_size /= 2;
1958 }
1959 }
1960
1961 /* clamp to max that the registers can hold */
1962 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
1963 }
1964
1965 /* Calculate the maximum cursor plane watermark */
1966 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
1967 int level,
1968 const struct intel_wm_config *config)
1969 {
1970 /* HSW LP1+ watermarks w/ multiple pipes */
1971 if (level > 0 && config->num_pipes_active > 1)
1972 return 64;
1973
1974 /* otherwise just report max that registers can hold */
1975 return ilk_cursor_wm_reg_max(dev, level);
1976 }
1977
1978 static void ilk_compute_wm_maximums(const struct drm_device *dev,
1979 int level,
1980 const struct intel_wm_config *config,
1981 enum intel_ddb_partitioning ddb_partitioning,
1982 struct ilk_wm_maximums *max)
1983 {
1984 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1985 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1986 max->cur = ilk_cursor_wm_max(dev, level, config);
1987 max->fbc = ilk_fbc_wm_reg_max(dev);
1988 }
1989
1990 static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1991 int level,
1992 struct ilk_wm_maximums *max)
1993 {
1994 max->pri = ilk_plane_wm_reg_max(dev, level, false);
1995 max->spr = ilk_plane_wm_reg_max(dev, level, true);
1996 max->cur = ilk_cursor_wm_reg_max(dev, level);
1997 max->fbc = ilk_fbc_wm_reg_max(dev);
1998 }
1999
2000 static bool ilk_validate_wm_level(int level,
2001 const struct ilk_wm_maximums *max,
2002 struct intel_wm_level *result)
2003 {
2004 bool ret;
2005
2006 /* already determined to be invalid? */
2007 if (!result->enable)
2008 return false;
2009
2010 result->enable = result->pri_val <= max->pri &&
2011 result->spr_val <= max->spr &&
2012 result->cur_val <= max->cur;
2013
2014 ret = result->enable;
2015
2016 /*
2017 * HACK until we can pre-compute everything,
2018 * and thus fail gracefully if LP0 watermarks
2019 * are exceeded...
2020 */
2021 if (level == 0 && !result->enable) {
2022 if (result->pri_val > max->pri)
2023 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2024 level, result->pri_val, max->pri);
2025 if (result->spr_val > max->spr)
2026 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2027 level, result->spr_val, max->spr);
2028 if (result->cur_val > max->cur)
2029 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2030 level, result->cur_val, max->cur);
2031
2032 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2033 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2034 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2035 result->enable = true;
2036 }
2037
2038 return ret;
2039 }
2040
2041 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
2042 int level,
2043 const struct ilk_pipe_wm_parameters *p,
2044 struct intel_wm_level *result)
2045 {
2046 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2047 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2048 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2049
2050 /* WM1+ latency values stored in 0.5us units */
2051 if (level > 0) {
2052 pri_latency *= 5;
2053 spr_latency *= 5;
2054 cur_latency *= 5;
2055 }
2056
2057 result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
2058 result->spr_val = ilk_compute_spr_wm(p, spr_latency);
2059 result->cur_val = ilk_compute_cur_wm(p, cur_latency);
2060 result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
2061 result->enable = true;
2062 }
2063
2064 static uint32_t
2065 hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
2066 {
2067 struct drm_i915_private *dev_priv = dev->dev_private;
2068 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2069 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
2070 u32 linetime, ips_linetime;
2071
2072 if (!intel_crtc->active)
2073 return 0;
2074
2075 /* The WM are computed with base on how long it takes to fill a single
2076 * row at the given clock rate, multiplied by 8.
2077 * */
2078 linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2079 adjusted_mode->crtc_clock);
2080 ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2081 dev_priv->cdclk_freq);
2082
2083 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2084 PIPE_WM_LINETIME_TIME(linetime);
2085 }
2086
2087 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
2088 {
2089 struct drm_i915_private *dev_priv = dev->dev_private;
2090
2091 if (IS_GEN9(dev)) {
2092 uint32_t val;
2093 int ret, i;
2094 int level, max_level = ilk_wm_max_level(dev);
2095
2096 /* read the first set of memory latencies[0:3] */
2097 val = 0; /* data0 to be programmed to 0 for first set */
2098 mutex_lock(&dev_priv->rps.hw_lock);
2099 ret = sandybridge_pcode_read(dev_priv,
2100 GEN9_PCODE_READ_MEM_LATENCY,
2101 &val);
2102 mutex_unlock(&dev_priv->rps.hw_lock);
2103
2104 if (ret) {
2105 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2106 return;
2107 }
2108
2109 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2110 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2111 GEN9_MEM_LATENCY_LEVEL_MASK;
2112 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2113 GEN9_MEM_LATENCY_LEVEL_MASK;
2114 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2115 GEN9_MEM_LATENCY_LEVEL_MASK;
2116
2117 /* read the second set of memory latencies[4:7] */
2118 val = 1; /* data0 to be programmed to 1 for second set */
2119 mutex_lock(&dev_priv->rps.hw_lock);
2120 ret = sandybridge_pcode_read(dev_priv,
2121 GEN9_PCODE_READ_MEM_LATENCY,
2122 &val);
2123 mutex_unlock(&dev_priv->rps.hw_lock);
2124 if (ret) {
2125 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2126 return;
2127 }
2128
2129 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2130 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2131 GEN9_MEM_LATENCY_LEVEL_MASK;
2132 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2133 GEN9_MEM_LATENCY_LEVEL_MASK;
2134 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2135 GEN9_MEM_LATENCY_LEVEL_MASK;
2136
2137 /*
2138 * WaWmMemoryReadLatency:skl
2139 *
2140 * punit doesn't take into account the read latency so we need
2141 * to add 2us to the various latency levels we retrieve from
2142 * the punit.
2143 * - W0 is a bit special in that it's the only level that
2144 * can't be disabled if we want to have display working, so
2145 * we always add 2us there.
2146 * - For levels >=1, punit returns 0us latency when they are
2147 * disabled, so we respect that and don't add 2us then
2148 *
2149 * Additionally, if a level n (n > 1) has a 0us latency, all
2150 * levels m (m >= n) need to be disabled. We make sure to
2151 * sanitize the values out of the punit to satisfy this
2152 * requirement.
2153 */
2154 wm[0] += 2;
2155 for (level = 1; level <= max_level; level++)
2156 if (wm[level] != 0)
2157 wm[level] += 2;
2158 else {
2159 for (i = level + 1; i <= max_level; i++)
2160 wm[i] = 0;
2161
2162 break;
2163 }
2164 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2165 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2166
2167 wm[0] = (sskpd >> 56) & 0xFF;
2168 if (wm[0] == 0)
2169 wm[0] = sskpd & 0xF;
2170 wm[1] = (sskpd >> 4) & 0xFF;
2171 wm[2] = (sskpd >> 12) & 0xFF;
2172 wm[3] = (sskpd >> 20) & 0x1FF;
2173 wm[4] = (sskpd >> 32) & 0x1FF;
2174 } else if (INTEL_INFO(dev)->gen >= 6) {
2175 uint32_t sskpd = I915_READ(MCH_SSKPD);
2176
2177 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2178 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2179 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2180 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2181 } else if (INTEL_INFO(dev)->gen >= 5) {
2182 uint32_t mltr = I915_READ(MLTR_ILK);
2183
2184 /* ILK primary LP0 latency is 700 ns */
2185 wm[0] = 7;
2186 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2187 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2188 }
2189 }
2190
2191 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2192 {
2193 /* ILK sprite LP0 latency is 1300 ns */
2194 if (INTEL_INFO(dev)->gen == 5)
2195 wm[0] = 13;
2196 }
2197
2198 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2199 {
2200 /* ILK cursor LP0 latency is 1300 ns */
2201 if (INTEL_INFO(dev)->gen == 5)
2202 wm[0] = 13;
2203
2204 /* WaDoubleCursorLP3Latency:ivb */
2205 if (IS_IVYBRIDGE(dev))
2206 wm[3] *= 2;
2207 }
2208
2209 int ilk_wm_max_level(const struct drm_device *dev)
2210 {
2211 /* how many WM levels are we expecting */
2212 if (INTEL_INFO(dev)->gen >= 9)
2213 return 7;
2214 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2215 return 4;
2216 else if (INTEL_INFO(dev)->gen >= 6)
2217 return 3;
2218 else
2219 return 2;
2220 }
2221
2222 static void intel_print_wm_latency(struct drm_device *dev,
2223 const char *name,
2224 const uint16_t wm[8])
2225 {
2226 int level, max_level = ilk_wm_max_level(dev);
2227
2228 for (level = 0; level <= max_level; level++) {
2229 unsigned int latency = wm[level];
2230
2231 if (latency == 0) {
2232 DRM_ERROR("%s WM%d latency not provided\n",
2233 name, level);
2234 continue;
2235 }
2236
2237 /*
2238 * - latencies are in us on gen9.
2239 * - before then, WM1+ latency values are in 0.5us units
2240 */
2241 if (IS_GEN9(dev))
2242 latency *= 10;
2243 else if (level > 0)
2244 latency *= 5;
2245
2246 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2247 name, level, wm[level],
2248 latency / 10, latency % 10);
2249 }
2250 }
2251
2252 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2253 uint16_t wm[5], uint16_t min)
2254 {
2255 int level, max_level = ilk_wm_max_level(dev_priv->dev);
2256
2257 if (wm[0] >= min)
2258 return false;
2259
2260 wm[0] = max(wm[0], min);
2261 for (level = 1; level <= max_level; level++)
2262 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2263
2264 return true;
2265 }
2266
2267 static void snb_wm_latency_quirk(struct drm_device *dev)
2268 {
2269 struct drm_i915_private *dev_priv = dev->dev_private;
2270 bool changed;
2271
2272 /*
2273 * The BIOS provided WM memory latency values are often
2274 * inadequate for high resolution displays. Adjust them.
2275 */
2276 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2277 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2278 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2279
2280 if (!changed)
2281 return;
2282
2283 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2284 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2285 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2286 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2287 }
2288
2289 static void ilk_setup_wm_latency(struct drm_device *dev)
2290 {
2291 struct drm_i915_private *dev_priv = dev->dev_private;
2292
2293 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2294
2295 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2296 sizeof(dev_priv->wm.pri_latency));
2297 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2298 sizeof(dev_priv->wm.pri_latency));
2299
2300 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2301 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2302
2303 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2304 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2305 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2306
2307 if (IS_GEN6(dev))
2308 snb_wm_latency_quirk(dev);
2309 }
2310
2311 static void skl_setup_wm_latency(struct drm_device *dev)
2312 {
2313 struct drm_i915_private *dev_priv = dev->dev_private;
2314
2315 intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2316 intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2317 }
2318
2319 static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
2320 struct ilk_pipe_wm_parameters *p)
2321 {
2322 struct drm_device *dev = crtc->dev;
2323 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2324 enum pipe pipe = intel_crtc->pipe;
2325 struct drm_plane *plane;
2326
2327 if (!intel_crtc->active)
2328 return;
2329
2330 p->active = true;
2331 p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;
2332 p->pixel_rate = ilk_pipe_pixel_rate(intel_crtc->config);
2333
2334 if (crtc->primary->state->fb)
2335 p->pri.bytes_per_pixel =
2336 crtc->primary->state->fb->bits_per_pixel / 8;
2337 else
2338 p->pri.bytes_per_pixel = 4;
2339
2340 p->cur.bytes_per_pixel = 4;
2341 /*
2342 * TODO: for now, assume primary and cursor planes are always enabled.
2343 * Setting them to false makes the screen flicker.
2344 */
2345 p->pri.enabled = true;
2346 p->cur.enabled = true;
2347
2348 p->pri.horiz_pixels = intel_crtc->config->pipe_src_w;
2349 p->cur.horiz_pixels = intel_crtc->base.cursor->state->crtc_w;
2350
2351 drm_for_each_legacy_plane(plane, dev) {
2352 struct intel_plane *intel_plane = to_intel_plane(plane);
2353
2354 if (intel_plane->pipe == pipe) {
2355 p->spr = intel_plane->wm;
2356 break;
2357 }
2358 }
2359 }
2360
2361 static void ilk_compute_wm_config(struct drm_device *dev,
2362 struct intel_wm_config *config)
2363 {
2364 struct intel_crtc *intel_crtc;
2365
2366 /* Compute the currently _active_ config */
2367 for_each_intel_crtc(dev, intel_crtc) {
2368 const struct intel_pipe_wm *wm = &intel_crtc->wm.active;
2369
2370 if (!wm->pipe_enabled)
2371 continue;
2372
2373 config->sprites_enabled |= wm->sprites_enabled;
2374 config->sprites_scaled |= wm->sprites_scaled;
2375 config->num_pipes_active++;
2376 }
2377 }
2378
2379 /* Compute new watermarks for the pipe */
2380 static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
2381 const struct ilk_pipe_wm_parameters *params,
2382 struct intel_pipe_wm *pipe_wm)
2383 {
2384 struct drm_device *dev = crtc->dev;
2385 const struct drm_i915_private *dev_priv = dev->dev_private;
2386 int level, max_level = ilk_wm_max_level(dev);
2387 /* LP0 watermark maximums depend on this pipe alone */
2388 struct intel_wm_config config = {
2389 .num_pipes_active = 1,
2390 .sprites_enabled = params->spr.enabled,
2391 .sprites_scaled = params->spr.scaled,
2392 };
2393 struct ilk_wm_maximums max;
2394
2395 pipe_wm->pipe_enabled = params->active;
2396 pipe_wm->sprites_enabled = params->spr.enabled;
2397 pipe_wm->sprites_scaled = params->spr.scaled;
2398
2399 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2400 if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled)
2401 max_level = 1;
2402
2403 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2404 if (params->spr.scaled)
2405 max_level = 0;
2406
2407 ilk_compute_wm_level(dev_priv, 0, params, &pipe_wm->wm[0]);
2408
2409 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2410 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
2411
2412 /* LP0 watermarks always use 1/2 DDB partitioning */
2413 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2414
2415 /* At least LP0 must be valid */
2416 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
2417 return false;
2418
2419 ilk_compute_wm_reg_maximums(dev, 1, &max);
2420
2421 for (level = 1; level <= max_level; level++) {
2422 struct intel_wm_level wm = {};
2423
2424 ilk_compute_wm_level(dev_priv, level, params, &wm);
2425
2426 /*
2427 * Disable any watermark level that exceeds the
2428 * register maximums since such watermarks are
2429 * always invalid.
2430 */
2431 if (!ilk_validate_wm_level(level, &max, &wm))
2432 break;
2433
2434 pipe_wm->wm[level] = wm;
2435 }
2436
2437 return true;
2438 }
2439
2440 /*
2441 * Merge the watermarks from all active pipes for a specific level.
2442 */
2443 static void ilk_merge_wm_level(struct drm_device *dev,
2444 int level,
2445 struct intel_wm_level *ret_wm)
2446 {
2447 const struct intel_crtc *intel_crtc;
2448
2449 ret_wm->enable = true;
2450
2451 for_each_intel_crtc(dev, intel_crtc) {
2452 const struct intel_pipe_wm *active = &intel_crtc->wm.active;
2453 const struct intel_wm_level *wm = &active->wm[level];
2454
2455 if (!active->pipe_enabled)
2456 continue;
2457
2458 /*
2459 * The watermark values may have been used in the past,
2460 * so we must maintain them in the registers for some
2461 * time even if the level is now disabled.
2462 */
2463 if (!wm->enable)
2464 ret_wm->enable = false;
2465
2466 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2467 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2468 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2469 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2470 }
2471 }
2472
2473 /*
2474 * Merge all low power watermarks for all active pipes.
2475 */
2476 static void ilk_wm_merge(struct drm_device *dev,
2477 const struct intel_wm_config *config,
2478 const struct ilk_wm_maximums *max,
2479 struct intel_pipe_wm *merged)
2480 {
2481 struct drm_i915_private *dev_priv = dev->dev_private;
2482 int level, max_level = ilk_wm_max_level(dev);
2483 int last_enabled_level = max_level;
2484
2485 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2486 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2487 config->num_pipes_active > 1)
2488 return;
2489
2490 /* ILK: FBC WM must be disabled always */
2491 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
2492
2493 /* merge each WM1+ level */
2494 for (level = 1; level <= max_level; level++) {
2495 struct intel_wm_level *wm = &merged->wm[level];
2496
2497 ilk_merge_wm_level(dev, level, wm);
2498
2499 if (level > last_enabled_level)
2500 wm->enable = false;
2501 else if (!ilk_validate_wm_level(level, max, wm))
2502 /* make sure all following levels get disabled */
2503 last_enabled_level = level - 1;
2504
2505 /*
2506 * The spec says it is preferred to disable
2507 * FBC WMs instead of disabling a WM level.
2508 */
2509 if (wm->fbc_val > max->fbc) {
2510 if (wm->enable)
2511 merged->fbc_wm_enabled = false;
2512 wm->fbc_val = 0;
2513 }
2514 }
2515
2516 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2517 /*
2518 * FIXME this is racy. FBC might get enabled later.
2519 * What we should check here is whether FBC can be
2520 * enabled sometime later.
2521 */
2522 if (IS_GEN5(dev) && !merged->fbc_wm_enabled &&
2523 intel_fbc_enabled(dev_priv)) {
2524 for (level = 2; level <= max_level; level++) {
2525 struct intel_wm_level *wm = &merged->wm[level];
2526
2527 wm->enable = false;
2528 }
2529 }
2530 }
2531
2532 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2533 {
2534 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2535 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2536 }
2537
2538 /* The value we need to program into the WM_LPx latency field */
2539 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2540 {
2541 struct drm_i915_private *dev_priv = dev->dev_private;
2542
2543 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2544 return 2 * level;
2545 else
2546 return dev_priv->wm.pri_latency[level];
2547 }
2548
2549 static void ilk_compute_wm_results(struct drm_device *dev,
2550 const struct intel_pipe_wm *merged,
2551 enum intel_ddb_partitioning partitioning,
2552 struct ilk_wm_values *results)
2553 {
2554 struct intel_crtc *intel_crtc;
2555 int level, wm_lp;
2556
2557 results->enable_fbc_wm = merged->fbc_wm_enabled;
2558 results->partitioning = partitioning;
2559
2560 /* LP1+ register values */
2561 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2562 const struct intel_wm_level *r;
2563
2564 level = ilk_wm_lp_to_level(wm_lp, merged);
2565
2566 r = &merged->wm[level];
2567
2568 /*
2569 * Maintain the watermark values even if the level is
2570 * disabled. Doing otherwise could cause underruns.
2571 */
2572 results->wm_lp[wm_lp - 1] =
2573 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2574 (r->pri_val << WM1_LP_SR_SHIFT) |
2575 r->cur_val;
2576
2577 if (r->enable)
2578 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2579
2580 if (INTEL_INFO(dev)->gen >= 8)
2581 results->wm_lp[wm_lp - 1] |=
2582 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2583 else
2584 results->wm_lp[wm_lp - 1] |=
2585 r->fbc_val << WM1_LP_FBC_SHIFT;
2586
2587 /*
2588 * Always set WM1S_LP_EN when spr_val != 0, even if the
2589 * level is disabled. Doing otherwise could cause underruns.
2590 */
2591 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2592 WARN_ON(wm_lp != 1);
2593 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2594 } else
2595 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2596 }
2597
2598 /* LP0 register values */
2599 for_each_intel_crtc(dev, intel_crtc) {
2600 enum pipe pipe = intel_crtc->pipe;
2601 const struct intel_wm_level *r =
2602 &intel_crtc->wm.active.wm[0];
2603
2604 if (WARN_ON(!r->enable))
2605 continue;
2606
2607 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
2608
2609 results->wm_pipe[pipe] =
2610 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2611 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2612 r->cur_val;
2613 }
2614 }
2615
2616 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2617 * case both are at the same level. Prefer r1 in case they're the same. */
2618 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2619 struct intel_pipe_wm *r1,
2620 struct intel_pipe_wm *r2)
2621 {
2622 int level, max_level = ilk_wm_max_level(dev);
2623 int level1 = 0, level2 = 0;
2624
2625 for (level = 1; level <= max_level; level++) {
2626 if (r1->wm[level].enable)
2627 level1 = level;
2628 if (r2->wm[level].enable)
2629 level2 = level;
2630 }
2631
2632 if (level1 == level2) {
2633 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2634 return r2;
2635 else
2636 return r1;
2637 } else if (level1 > level2) {
2638 return r1;
2639 } else {
2640 return r2;
2641 }
2642 }
2643
2644 /* dirty bits used to track which watermarks need changes */
2645 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2646 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2647 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2648 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2649 #define WM_DIRTY_FBC (1 << 24)
2650 #define WM_DIRTY_DDB (1 << 25)
2651
2652 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
2653 const struct ilk_wm_values *old,
2654 const struct ilk_wm_values *new)
2655 {
2656 unsigned int dirty = 0;
2657 enum pipe pipe;
2658 int wm_lp;
2659
2660 for_each_pipe(dev_priv, pipe) {
2661 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2662 dirty |= WM_DIRTY_LINETIME(pipe);
2663 /* Must disable LP1+ watermarks too */
2664 dirty |= WM_DIRTY_LP_ALL;
2665 }
2666
2667 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2668 dirty |= WM_DIRTY_PIPE(pipe);
2669 /* Must disable LP1+ watermarks too */
2670 dirty |= WM_DIRTY_LP_ALL;
2671 }
2672 }
2673
2674 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2675 dirty |= WM_DIRTY_FBC;
2676 /* Must disable LP1+ watermarks too */
2677 dirty |= WM_DIRTY_LP_ALL;
2678 }
2679
2680 if (old->partitioning != new->partitioning) {
2681 dirty |= WM_DIRTY_DDB;
2682 /* Must disable LP1+ watermarks too */
2683 dirty |= WM_DIRTY_LP_ALL;
2684 }
2685
2686 /* LP1+ watermarks already deemed dirty, no need to continue */
2687 if (dirty & WM_DIRTY_LP_ALL)
2688 return dirty;
2689
2690 /* Find the lowest numbered LP1+ watermark in need of an update... */
2691 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2692 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2693 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2694 break;
2695 }
2696
2697 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2698 for (; wm_lp <= 3; wm_lp++)
2699 dirty |= WM_DIRTY_LP(wm_lp);
2700
2701 return dirty;
2702 }
2703
2704 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2705 unsigned int dirty)
2706 {
2707 struct ilk_wm_values *previous = &dev_priv->wm.hw;
2708 bool changed = false;
2709
2710 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2711 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2712 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2713 changed = true;
2714 }
2715 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2716 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2717 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2718 changed = true;
2719 }
2720 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2721 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2722 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2723 changed = true;
2724 }
2725
2726 /*
2727 * Don't touch WM1S_LP_EN here.
2728 * Doing so could cause underruns.
2729 */
2730
2731 return changed;
2732 }
2733
2734 /*
2735 * The spec says we shouldn't write when we don't need, because every write
2736 * causes WMs to be re-evaluated, expending some power.
2737 */
2738 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2739 struct ilk_wm_values *results)
2740 {
2741 struct drm_device *dev = dev_priv->dev;
2742 struct ilk_wm_values *previous = &dev_priv->wm.hw;
2743 unsigned int dirty;
2744 uint32_t val;
2745
2746 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
2747 if (!dirty)
2748 return;
2749
2750 _ilk_disable_lp_wm(dev_priv, dirty);
2751
2752 if (dirty & WM_DIRTY_PIPE(PIPE_A))
2753 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2754 if (dirty & WM_DIRTY_PIPE(PIPE_B))
2755 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2756 if (dirty & WM_DIRTY_PIPE(PIPE_C))
2757 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2758
2759 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2760 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2761 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2762 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2763 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2764 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2765
2766 if (dirty & WM_DIRTY_DDB) {
2767 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2768 val = I915_READ(WM_MISC);
2769 if (results->partitioning == INTEL_DDB_PART_1_2)
2770 val &= ~WM_MISC_DATA_PARTITION_5_6;
2771 else
2772 val |= WM_MISC_DATA_PARTITION_5_6;
2773 I915_WRITE(WM_MISC, val);
2774 } else {
2775 val = I915_READ(DISP_ARB_CTL2);
2776 if (results->partitioning == INTEL_DDB_PART_1_2)
2777 val &= ~DISP_DATA_PARTITION_5_6;
2778 else
2779 val |= DISP_DATA_PARTITION_5_6;
2780 I915_WRITE(DISP_ARB_CTL2, val);
2781 }
2782 }
2783
2784 if (dirty & WM_DIRTY_FBC) {
2785 val = I915_READ(DISP_ARB_CTL);
2786 if (results->enable_fbc_wm)
2787 val &= ~DISP_FBC_WM_DIS;
2788 else
2789 val |= DISP_FBC_WM_DIS;
2790 I915_WRITE(DISP_ARB_CTL, val);
2791 }
2792
2793 if (dirty & WM_DIRTY_LP(1) &&
2794 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2795 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2796
2797 if (INTEL_INFO(dev)->gen >= 7) {
2798 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2799 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2800 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2801 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2802 }
2803
2804 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2805 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2806 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2807 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2808 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2809 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2810
2811 dev_priv->wm.hw = *results;
2812 }
2813
2814 static bool ilk_disable_lp_wm(struct drm_device *dev)
2815 {
2816 struct drm_i915_private *dev_priv = dev->dev_private;
2817
2818 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2819 }
2820
2821 /*
2822 * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2823 * different active planes.
2824 */
2825
2826 #define SKL_DDB_SIZE 896 /* in blocks */
2827 #define BXT_DDB_SIZE 512
2828
2829 static void
2830 skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
2831 struct drm_crtc *for_crtc,
2832 const struct intel_wm_config *config,
2833 const struct skl_pipe_wm_parameters *params,
2834 struct skl_ddb_entry *alloc /* out */)
2835 {
2836 struct drm_crtc *crtc;
2837 unsigned int pipe_size, ddb_size;
2838 int nth_active_pipe;
2839
2840 if (!params->active) {
2841 alloc->start = 0;
2842 alloc->end = 0;
2843 return;
2844 }
2845
2846 if (IS_BROXTON(dev))
2847 ddb_size = BXT_DDB_SIZE;
2848 else
2849 ddb_size = SKL_DDB_SIZE;
2850
2851 ddb_size -= 4; /* 4 blocks for bypass path allocation */
2852
2853 nth_active_pipe = 0;
2854 for_each_crtc(dev, crtc) {
2855 if (!to_intel_crtc(crtc)->active)
2856 continue;
2857
2858 if (crtc == for_crtc)
2859 break;
2860
2861 nth_active_pipe++;
2862 }
2863
2864 pipe_size = ddb_size / config->num_pipes_active;
2865 alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active;
2866 alloc->end = alloc->start + pipe_size;
2867 }
2868
2869 static unsigned int skl_cursor_allocation(const struct intel_wm_config *config)
2870 {
2871 if (config->num_pipes_active == 1)
2872 return 32;
2873
2874 return 8;
2875 }
2876
2877 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
2878 {
2879 entry->start = reg & 0x3ff;
2880 entry->end = (reg >> 16) & 0x3ff;
2881 if (entry->end)
2882 entry->end += 1;
2883 }
2884
2885 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2886 struct skl_ddb_allocation *ddb /* out */)
2887 {
2888 enum pipe pipe;
2889 int plane;
2890 u32 val;
2891
2892 for_each_pipe(dev_priv, pipe) {
2893 for_each_plane(dev_priv, pipe, plane) {
2894 val = I915_READ(PLANE_BUF_CFG(pipe, plane));
2895 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
2896 val);
2897 }
2898
2899 val = I915_READ(CUR_BUF_CFG(pipe));
2900 skl_ddb_entry_init_from_hw(&ddb->cursor[pipe], val);
2901 }
2902 }
2903
2904 static unsigned int
2905 skl_plane_relative_data_rate(const struct intel_plane_wm_parameters *p, int y)
2906 {
2907
2908 /* for planar format */
2909 if (p->y_bytes_per_pixel) {
2910 if (y) /* y-plane data rate */
2911 return p->horiz_pixels * p->vert_pixels * p->y_bytes_per_pixel;
2912 else /* uv-plane data rate */
2913 return (p->horiz_pixels/2) * (p->vert_pixels/2) * p->bytes_per_pixel;
2914 }
2915
2916 /* for packed formats */
2917 return p->horiz_pixels * p->vert_pixels * p->bytes_per_pixel;
2918 }
2919
2920 /*
2921 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
2922 * a 8192x4096@32bpp framebuffer:
2923 * 3 * 4096 * 8192 * 4 < 2^32
2924 */
2925 static unsigned int
2926 skl_get_total_relative_data_rate(struct intel_crtc *intel_crtc,
2927 const struct skl_pipe_wm_parameters *params)
2928 {
2929 unsigned int total_data_rate = 0;
2930 int plane;
2931
2932 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
2933 const struct intel_plane_wm_parameters *p;
2934
2935 p = &params->plane[plane];
2936 if (!p->enabled)
2937 continue;
2938
2939 total_data_rate += skl_plane_relative_data_rate(p, 0); /* packed/uv */
2940 if (p->y_bytes_per_pixel) {
2941 total_data_rate += skl_plane_relative_data_rate(p, 1); /* y-plane */
2942 }
2943 }
2944
2945 return total_data_rate;
2946 }
2947
2948 static void
2949 skl_allocate_pipe_ddb(struct drm_crtc *crtc,
2950 const struct intel_wm_config *config,
2951 const struct skl_pipe_wm_parameters *params,
2952 struct skl_ddb_allocation *ddb /* out */)
2953 {
2954 struct drm_device *dev = crtc->dev;
2955 struct drm_i915_private *dev_priv = dev->dev_private;
2956 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2957 enum pipe pipe = intel_crtc->pipe;
2958 struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
2959 uint16_t alloc_size, start, cursor_blocks;
2960 uint16_t minimum[I915_MAX_PLANES];
2961 uint16_t y_minimum[I915_MAX_PLANES];
2962 unsigned int total_data_rate;
2963 int plane;
2964
2965 skl_ddb_get_pipe_allocation_limits(dev, crtc, config, params, alloc);
2966 alloc_size = skl_ddb_entry_size(alloc);
2967 if (alloc_size == 0) {
2968 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
2969 memset(&ddb->cursor[pipe], 0, sizeof(ddb->cursor[pipe]));
2970 return;
2971 }
2972
2973 cursor_blocks = skl_cursor_allocation(config);
2974 ddb->cursor[pipe].start = alloc->end - cursor_blocks;
2975 ddb->cursor[pipe].end = alloc->end;
2976
2977 alloc_size -= cursor_blocks;
2978 alloc->end -= cursor_blocks;
2979
2980 /* 1. Allocate the mininum required blocks for each active plane */
2981 for_each_plane(dev_priv, pipe, plane) {
2982 const struct intel_plane_wm_parameters *p;
2983
2984 p = &params->plane[plane];
2985 if (!p->enabled)
2986 continue;
2987
2988 minimum[plane] = 8;
2989 alloc_size -= minimum[plane];
2990 y_minimum[plane] = p->y_bytes_per_pixel ? 8 : 0;
2991 alloc_size -= y_minimum[plane];
2992 }
2993
2994 /*
2995 * 2. Distribute the remaining space in proportion to the amount of
2996 * data each plane needs to fetch from memory.
2997 *
2998 * FIXME: we may not allocate every single block here.
2999 */
3000 total_data_rate = skl_get_total_relative_data_rate(intel_crtc, params);
3001
3002 start = alloc->start;
3003 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
3004 const struct intel_plane_wm_parameters *p;
3005 unsigned int data_rate, y_data_rate;
3006 uint16_t plane_blocks, y_plane_blocks = 0;
3007
3008 p = &params->plane[plane];
3009 if (!p->enabled)
3010 continue;
3011
3012 data_rate = skl_plane_relative_data_rate(p, 0);
3013
3014 /*
3015 * allocation for (packed formats) or (uv-plane part of planar format):
3016 * promote the expression to 64 bits to avoid overflowing, the
3017 * result is < available as data_rate / total_data_rate < 1
3018 */
3019 plane_blocks = minimum[plane];
3020 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3021 total_data_rate);
3022
3023 ddb->plane[pipe][plane].start = start;
3024 ddb->plane[pipe][plane].end = start + plane_blocks;
3025
3026 start += plane_blocks;
3027
3028 /*
3029 * allocation for y_plane part of planar format:
3030 */
3031 if (p->y_bytes_per_pixel) {
3032 y_data_rate = skl_plane_relative_data_rate(p, 1);
3033 y_plane_blocks = y_minimum[plane];
3034 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3035 total_data_rate);
3036
3037 ddb->y_plane[pipe][plane].start = start;
3038 ddb->y_plane[pipe][plane].end = start + y_plane_blocks;
3039
3040 start += y_plane_blocks;
3041 }
3042
3043 }
3044
3045 }
3046
3047 static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
3048 {
3049 /* TODO: Take into account the scalers once we support them */
3050 return config->base.adjusted_mode.crtc_clock;
3051 }
3052
3053 /*
3054 * The max latency should be 257 (max the punit can code is 255 and we add 2us
3055 * for the read latency) and bytes_per_pixel should always be <= 8, so that
3056 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3057 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3058 */
3059 static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
3060 uint32_t latency)
3061 {
3062 uint32_t wm_intermediate_val, ret;
3063
3064 if (latency == 0)
3065 return UINT_MAX;
3066
3067 wm_intermediate_val = latency * pixel_rate * bytes_per_pixel / 512;
3068 ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3069
3070 return ret;
3071 }
3072
3073 static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
3074 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
3075 uint64_t tiling, uint32_t latency)
3076 {
3077 uint32_t ret;
3078 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3079 uint32_t wm_intermediate_val;
3080
3081 if (latency == 0)
3082 return UINT_MAX;
3083
3084 plane_bytes_per_line = horiz_pixels * bytes_per_pixel;
3085
3086 if (tiling == I915_FORMAT_MOD_Y_TILED ||
3087 tiling == I915_FORMAT_MOD_Yf_TILED) {
3088 plane_bytes_per_line *= 4;
3089 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3090 plane_blocks_per_line /= 4;
3091 } else {
3092 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3093 }
3094
3095 wm_intermediate_val = latency * pixel_rate;
3096 ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
3097 plane_blocks_per_line;
3098
3099 return ret;
3100 }
3101
3102 static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb,
3103 const struct intel_crtc *intel_crtc)
3104 {
3105 struct drm_device *dev = intel_crtc->base.dev;
3106 struct drm_i915_private *dev_priv = dev->dev_private;
3107 const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
3108 enum pipe pipe = intel_crtc->pipe;
3109
3110 if (memcmp(new_ddb->plane[pipe], cur_ddb->plane[pipe],
3111 sizeof(new_ddb->plane[pipe])))
3112 return true;
3113
3114 if (memcmp(&new_ddb->cursor[pipe], &cur_ddb->cursor[pipe],
3115 sizeof(new_ddb->cursor[pipe])))
3116 return true;
3117
3118 return false;
3119 }
3120
3121 static void skl_compute_wm_global_parameters(struct drm_device *dev,
3122 struct intel_wm_config *config)
3123 {
3124 struct drm_crtc *crtc;
3125 struct drm_plane *plane;
3126
3127 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3128 config->num_pipes_active += to_intel_crtc(crtc)->active;
3129
3130 /* FIXME: I don't think we need those two global parameters on SKL */
3131 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
3132 struct intel_plane *intel_plane = to_intel_plane(plane);
3133
3134 config->sprites_enabled |= intel_plane->wm.enabled;
3135 config->sprites_scaled |= intel_plane->wm.scaled;
3136 }
3137 }
3138
3139 static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,
3140 struct skl_pipe_wm_parameters *p)
3141 {
3142 struct drm_device *dev = crtc->dev;
3143 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3144 enum pipe pipe = intel_crtc->pipe;
3145 struct drm_plane *plane;
3146 struct drm_framebuffer *fb;
3147 int i = 1; /* Index for sprite planes start */
3148
3149 p->active = intel_crtc->active;
3150 if (p->active) {
3151 p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;
3152 p->pixel_rate = skl_pipe_pixel_rate(intel_crtc->config);
3153
3154 fb = crtc->primary->state->fb;
3155 /* For planar: Bpp is for uv plane, y_Bpp is for y plane */
3156 if (fb) {
3157 p->plane[0].enabled = true;
3158 p->plane[0].bytes_per_pixel = fb->pixel_format == DRM_FORMAT_NV12 ?
3159 drm_format_plane_cpp(fb->pixel_format, 1) :
3160 drm_format_plane_cpp(fb->pixel_format, 0);
3161 p->plane[0].y_bytes_per_pixel = fb->pixel_format == DRM_FORMAT_NV12 ?
3162 drm_format_plane_cpp(fb->pixel_format, 0) : 0;
3163 p->plane[0].tiling = fb->modifier[0];
3164 } else {
3165 p->plane[0].enabled = false;
3166 p->plane[0].bytes_per_pixel = 0;
3167 p->plane[0].y_bytes_per_pixel = 0;
3168 p->plane[0].tiling = DRM_FORMAT_MOD_NONE;
3169 }
3170 p->plane[0].horiz_pixels = intel_crtc->config->pipe_src_w;
3171 p->plane[0].vert_pixels = intel_crtc->config->pipe_src_h;
3172 p->plane[0].rotation = crtc->primary->state->rotation;
3173
3174 fb = crtc->cursor->state->fb;
3175 p->cursor.y_bytes_per_pixel = 0;
3176 if (fb) {
3177 p->cursor.enabled = true;
3178 p->cursor.bytes_per_pixel = fb->bits_per_pixel / 8;
3179 p->cursor.horiz_pixels = crtc->cursor->state->crtc_w;
3180 p->cursor.vert_pixels = crtc->cursor->state->crtc_h;
3181 } else {
3182 p->cursor.enabled = false;
3183 p->cursor.bytes_per_pixel = 0;
3184 p->cursor.horiz_pixels = 64;
3185 p->cursor.vert_pixels = 64;
3186 }
3187 }
3188
3189 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
3190 struct intel_plane *intel_plane = to_intel_plane(plane);
3191
3192 if (intel_plane->pipe == pipe &&
3193 plane->type == DRM_PLANE_TYPE_OVERLAY)
3194 p->plane[i++] = intel_plane->wm;
3195 }
3196 }
3197
3198 static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3199 struct skl_pipe_wm_parameters *p,
3200 struct intel_plane_wm_parameters *p_params,
3201 uint16_t ddb_allocation,
3202 int level,
3203 uint16_t *out_blocks, /* out */
3204 uint8_t *out_lines /* out */)
3205 {
3206 uint32_t latency = dev_priv->wm.skl_latency[level];
3207 uint32_t method1, method2;
3208 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3209 uint32_t res_blocks, res_lines;
3210 uint32_t selected_result;
3211 uint8_t bytes_per_pixel;
3212
3213 if (latency == 0 || !p->active || !p_params->enabled)
3214 return false;
3215
3216 bytes_per_pixel = p_params->y_bytes_per_pixel ?
3217 p_params->y_bytes_per_pixel :
3218 p_params->bytes_per_pixel;
3219 method1 = skl_wm_method1(p->pixel_rate,
3220 bytes_per_pixel,
3221 latency);
3222 method2 = skl_wm_method2(p->pixel_rate,
3223 p->pipe_htotal,
3224 p_params->horiz_pixels,
3225 bytes_per_pixel,
3226 p_params->tiling,
3227 latency);
3228
3229 plane_bytes_per_line = p_params->horiz_pixels * bytes_per_pixel;
3230 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3231
3232 if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
3233 p_params->tiling == I915_FORMAT_MOD_Yf_TILED) {
3234 uint32_t min_scanlines = 4;
3235 uint32_t y_tile_minimum;
3236 if (intel_rotation_90_or_270(p_params->rotation)) {
3237 switch (p_params->bytes_per_pixel) {
3238 case 1:
3239 min_scanlines = 16;
3240 break;
3241 case 2:
3242 min_scanlines = 8;
3243 break;
3244 case 8:
3245 WARN(1, "Unsupported pixel depth for rotation");
3246 }
3247 }
3248 y_tile_minimum = plane_blocks_per_line * min_scanlines;
3249 selected_result = max(method2, y_tile_minimum);
3250 } else {
3251 if ((ddb_allocation / plane_blocks_per_line) >= 1)
3252 selected_result = min(method1, method2);
3253 else
3254 selected_result = method1;
3255 }
3256
3257 res_blocks = selected_result + 1;
3258 res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
3259
3260 if (level >= 1 && level <= 7) {
3261 if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
3262 p_params->tiling == I915_FORMAT_MOD_Yf_TILED)
3263 res_lines += 4;
3264 else
3265 res_blocks++;
3266 }
3267
3268 if (res_blocks >= ddb_allocation || res_lines > 31)
3269 return false;
3270
3271 *out_blocks = res_blocks;
3272 *out_lines = res_lines;
3273
3274 return true;
3275 }
3276
3277 static void skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3278 struct skl_ddb_allocation *ddb,
3279 struct skl_pipe_wm_parameters *p,
3280 enum pipe pipe,
3281 int level,
3282 int num_planes,
3283 struct skl_wm_level *result)
3284 {
3285 uint16_t ddb_blocks;
3286 int i;
3287
3288 for (i = 0; i < num_planes; i++) {
3289 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3290
3291 result->plane_en[i] = skl_compute_plane_wm(dev_priv,
3292 p, &p->plane[i],
3293 ddb_blocks,
3294 level,
3295 &result->plane_res_b[i],
3296 &result->plane_res_l[i]);
3297 }
3298
3299 ddb_blocks = skl_ddb_entry_size(&ddb->cursor[pipe]);
3300 result->cursor_en = skl_compute_plane_wm(dev_priv, p, &p->cursor,
3301 ddb_blocks, level,
3302 &result->cursor_res_b,
3303 &result->cursor_res_l);
3304 }
3305
3306 static uint32_t
3307 skl_compute_linetime_wm(struct drm_crtc *crtc, struct skl_pipe_wm_parameters *p)
3308 {
3309 if (!to_intel_crtc(crtc)->active)
3310 return 0;
3311
3312 if (WARN_ON(p->pixel_rate == 0))
3313 return 0;
3314
3315 return DIV_ROUND_UP(8 * p->pipe_htotal * 1000, p->pixel_rate);
3316 }
3317
3318 static void skl_compute_transition_wm(struct drm_crtc *crtc,
3319 struct skl_pipe_wm_parameters *params,
3320 struct skl_wm_level *trans_wm /* out */)
3321 {
3322 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3323 int i;
3324
3325 if (!params->active)
3326 return;
3327
3328 /* Until we know more, just disable transition WMs */
3329 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3330 trans_wm->plane_en[i] = false;
3331 trans_wm->cursor_en = false;
3332 }
3333
3334 static void skl_compute_pipe_wm(struct drm_crtc *crtc,
3335 struct skl_ddb_allocation *ddb,
3336 struct skl_pipe_wm_parameters *params,
3337 struct skl_pipe_wm *pipe_wm)
3338 {
3339 struct drm_device *dev = crtc->dev;
3340 const struct drm_i915_private *dev_priv = dev->dev_private;
3341 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3342 int level, max_level = ilk_wm_max_level(dev);
3343
3344 for (level = 0; level <= max_level; level++) {
3345 skl_compute_wm_level(dev_priv, ddb, params, intel_crtc->pipe,
3346 level, intel_num_planes(intel_crtc),
3347 &pipe_wm->wm[level]);
3348 }
3349 pipe_wm->linetime = skl_compute_linetime_wm(crtc, params);
3350
3351 skl_compute_transition_wm(crtc, params, &pipe_wm->trans_wm);
3352 }
3353
3354 static void skl_compute_wm_results(struct drm_device *dev,
3355 struct skl_pipe_wm_parameters *p,
3356 struct skl_pipe_wm *p_wm,
3357 struct skl_wm_values *r,
3358 struct intel_crtc *intel_crtc)
3359 {
3360 int level, max_level = ilk_wm_max_level(dev);
3361 enum pipe pipe = intel_crtc->pipe;
3362 uint32_t temp;
3363 int i;
3364
3365 for (level = 0; level <= max_level; level++) {
3366 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3367 temp = 0;
3368
3369 temp |= p_wm->wm[level].plane_res_l[i] <<
3370 PLANE_WM_LINES_SHIFT;
3371 temp |= p_wm->wm[level].plane_res_b[i];
3372 if (p_wm->wm[level].plane_en[i])
3373 temp |= PLANE_WM_EN;
3374
3375 r->plane[pipe][i][level] = temp;
3376 }
3377
3378 temp = 0;
3379
3380 temp |= p_wm->wm[level].cursor_res_l << PLANE_WM_LINES_SHIFT;
3381 temp |= p_wm->wm[level].cursor_res_b;
3382
3383 if (p_wm->wm[level].cursor_en)
3384 temp |= PLANE_WM_EN;
3385
3386 r->cursor[pipe][level] = temp;
3387
3388 }
3389
3390 /* transition WMs */
3391 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3392 temp = 0;
3393 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3394 temp |= p_wm->trans_wm.plane_res_b[i];
3395 if (p_wm->trans_wm.plane_en[i])
3396 temp |= PLANE_WM_EN;
3397
3398 r->plane_trans[pipe][i] = temp;
3399 }
3400
3401 temp = 0;
3402 temp |= p_wm->trans_wm.cursor_res_l << PLANE_WM_LINES_SHIFT;
3403 temp |= p_wm->trans_wm.cursor_res_b;
3404 if (p_wm->trans_wm.cursor_en)
3405 temp |= PLANE_WM_EN;
3406
3407 r->cursor_trans[pipe] = temp;
3408
3409 r->wm_linetime[pipe] = p_wm->linetime;
3410 }
3411
3412 static void skl_ddb_entry_write(struct drm_i915_private *dev_priv, uint32_t reg,
3413 const struct skl_ddb_entry *entry)
3414 {
3415 if (entry->end)
3416 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3417 else
3418 I915_WRITE(reg, 0);
3419 }
3420
3421 static void skl_write_wm_values(struct drm_i915_private *dev_priv,
3422 const struct skl_wm_values *new)
3423 {
3424 struct drm_device *dev = dev_priv->dev;
3425 struct intel_crtc *crtc;
3426
3427 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
3428 int i, level, max_level = ilk_wm_max_level(dev);
3429 enum pipe pipe = crtc->pipe;
3430
3431 if (!new->dirty[pipe])
3432 continue;
3433
3434 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]);
3435
3436 for (level = 0; level <= max_level; level++) {
3437 for (i = 0; i < intel_num_planes(crtc); i++)
3438 I915_WRITE(PLANE_WM(pipe, i, level),
3439 new->plane[pipe][i][level]);
3440 I915_WRITE(CUR_WM(pipe, level),
3441 new->cursor[pipe][level]);
3442 }
3443 for (i = 0; i < intel_num_planes(crtc); i++)
3444 I915_WRITE(PLANE_WM_TRANS(pipe, i),
3445 new->plane_trans[pipe][i]);
3446 I915_WRITE(CUR_WM_TRANS(pipe), new->cursor_trans[pipe]);
3447
3448 for (i = 0; i < intel_num_planes(crtc); i++) {
3449 skl_ddb_entry_write(dev_priv,
3450 PLANE_BUF_CFG(pipe, i),
3451 &new->ddb.plane[pipe][i]);
3452 skl_ddb_entry_write(dev_priv,
3453 PLANE_NV12_BUF_CFG(pipe, i),
3454 &new->ddb.y_plane[pipe][i]);
3455 }
3456
3457 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3458 &new->ddb.cursor[pipe]);
3459 }
3460 }
3461
3462 /*
3463 * When setting up a new DDB allocation arrangement, we need to correctly
3464 * sequence the times at which the new allocations for the pipes are taken into
3465 * account or we'll have pipes fetching from space previously allocated to
3466 * another pipe.
3467 *
3468 * Roughly the sequence looks like:
3469 * 1. re-allocate the pipe(s) with the allocation being reduced and not
3470 * overlapping with a previous light-up pipe (another way to put it is:
3471 * pipes with their new allocation strickly included into their old ones).
3472 * 2. re-allocate the other pipes that get their allocation reduced
3473 * 3. allocate the pipes having their allocation increased
3474 *
3475 * Steps 1. and 2. are here to take care of the following case:
3476 * - Initially DDB looks like this:
3477 * | B | C |
3478 * - enable pipe A.
3479 * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
3480 * allocation
3481 * | A | B | C |
3482 *
3483 * We need to sequence the re-allocation: C, B, A (and not B, C, A).
3484 */
3485
3486 static void
3487 skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass)
3488 {
3489 int plane;
3490
3491 DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);
3492
3493 for_each_plane(dev_priv, pipe, plane) {
3494 I915_WRITE(PLANE_SURF(pipe, plane),
3495 I915_READ(PLANE_SURF(pipe, plane)));
3496 }
3497 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3498 }
3499
3500 static bool
3501 skl_ddb_allocation_included(const struct skl_ddb_allocation *old,
3502 const struct skl_ddb_allocation *new,
3503 enum pipe pipe)
3504 {
3505 uint16_t old_size, new_size;
3506
3507 old_size = skl_ddb_entry_size(&old->pipe[pipe]);
3508 new_size = skl_ddb_entry_size(&new->pipe[pipe]);
3509
3510 return old_size != new_size &&
3511 new->pipe[pipe].start >= old->pipe[pipe].start &&
3512 new->pipe[pipe].end <= old->pipe[pipe].end;
3513 }
3514
3515 static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
3516 struct skl_wm_values *new_values)
3517 {
3518 struct drm_device *dev = dev_priv->dev;
3519 struct skl_ddb_allocation *cur_ddb, *new_ddb;
3520 bool reallocated[I915_MAX_PIPES] = {};
3521 struct intel_crtc *crtc;
3522 enum pipe pipe;
3523
3524 new_ddb = &new_values->ddb;
3525 cur_ddb = &dev_priv->wm.skl_hw.ddb;
3526
3527 /*
3528 * First pass: flush the pipes with the new allocation contained into
3529 * the old space.
3530 *
3531 * We'll wait for the vblank on those pipes to ensure we can safely
3532 * re-allocate the freed space without this pipe fetching from it.
3533 */
3534 for_each_intel_crtc(dev, crtc) {
3535 if (!crtc->active)
3536 continue;
3537
3538 pipe = crtc->pipe;
3539
3540 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))
3541 continue;
3542
3543 skl_wm_flush_pipe(dev_priv, pipe, 1);
3544 intel_wait_for_vblank(dev, pipe);
3545
3546 reallocated[pipe] = true;
3547 }
3548
3549
3550 /*
3551 * Second pass: flush the pipes that are having their allocation
3552 * reduced, but overlapping with a previous allocation.
3553 *
3554 * Here as well we need to wait for the vblank to make sure the freed
3555 * space is not used anymore.
3556 */
3557 for_each_intel_crtc(dev, crtc) {
3558 if (!crtc->active)
3559 continue;
3560
3561 pipe = crtc->pipe;
3562
3563 if (reallocated[pipe])
3564 continue;
3565
3566 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <
3567 skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
3568 skl_wm_flush_pipe(dev_priv, pipe, 2);
3569 intel_wait_for_vblank(dev, pipe);
3570 reallocated[pipe] = true;
3571 }
3572 }
3573
3574 /*
3575 * Third pass: flush the pipes that got more space allocated.
3576 *
3577 * We don't need to actively wait for the update here, next vblank
3578 * will just get more DDB space with the correct WM values.
3579 */
3580 for_each_intel_crtc(dev, crtc) {
3581 if (!crtc->active)
3582 continue;
3583
3584 pipe = crtc->pipe;
3585
3586 /*
3587 * At this point, only the pipes more space than before are
3588 * left to re-allocate.
3589 */
3590 if (reallocated[pipe])
3591 continue;
3592
3593 skl_wm_flush_pipe(dev_priv, pipe, 3);
3594 }
3595 }
3596
3597 static bool skl_update_pipe_wm(struct drm_crtc *crtc,
3598 struct skl_pipe_wm_parameters *params,
3599 struct intel_wm_config *config,
3600 struct skl_ddb_allocation *ddb, /* out */
3601 struct skl_pipe_wm *pipe_wm /* out */)
3602 {
3603 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3604
3605 skl_compute_wm_pipe_parameters(crtc, params);
3606 skl_allocate_pipe_ddb(crtc, config, params, ddb);
3607 skl_compute_pipe_wm(crtc, ddb, params, pipe_wm);
3608
3609 if (!memcmp(&intel_crtc->wm.skl_active, pipe_wm, sizeof(*pipe_wm)))
3610 return false;
3611
3612 intel_crtc->wm.skl_active = *pipe_wm;
3613
3614 return true;
3615 }
3616
3617 static void skl_update_other_pipe_wm(struct drm_device *dev,
3618 struct drm_crtc *crtc,
3619 struct intel_wm_config *config,
3620 struct skl_wm_values *r)
3621 {
3622 struct intel_crtc *intel_crtc;
3623 struct intel_crtc *this_crtc = to_intel_crtc(crtc);
3624
3625 /*
3626 * If the WM update hasn't changed the allocation for this_crtc (the
3627 * crtc we are currently computing the new WM values for), other
3628 * enabled crtcs will keep the same allocation and we don't need to
3629 * recompute anything for them.
3630 */
3631 if (!skl_ddb_allocation_changed(&r->ddb, this_crtc))
3632 return;
3633
3634 /*
3635 * Otherwise, because of this_crtc being freshly enabled/disabled, the
3636 * other active pipes need new DDB allocation and WM values.
3637 */
3638 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
3639 base.head) {
3640 struct skl_pipe_wm_parameters params = {};
3641 struct skl_pipe_wm pipe_wm = {};
3642 bool wm_changed;
3643
3644 if (this_crtc->pipe == intel_crtc->pipe)
3645 continue;
3646
3647 if (!intel_crtc->active)
3648 continue;
3649
3650 wm_changed = skl_update_pipe_wm(&intel_crtc->base,
3651 &params, config,
3652 &r->ddb, &pipe_wm);
3653
3654 /*
3655 * If we end up re-computing the other pipe WM values, it's
3656 * because it was really needed, so we expect the WM values to
3657 * be different.
3658 */
3659 WARN_ON(!wm_changed);
3660
3661 skl_compute_wm_results(dev, &params, &pipe_wm, r, intel_crtc);
3662 r->dirty[intel_crtc->pipe] = true;
3663 }
3664 }
3665
3666 static void skl_clear_wm(struct skl_wm_values *watermarks, enum pipe pipe)
3667 {
3668 watermarks->wm_linetime[pipe] = 0;
3669 memset(watermarks->plane[pipe], 0,
3670 sizeof(uint32_t) * 8 * I915_MAX_PLANES);
3671 memset(watermarks->cursor[pipe], 0, sizeof(uint32_t) * 8);
3672 memset(watermarks->plane_trans[pipe],
3673 0, sizeof(uint32_t) * I915_MAX_PLANES);
3674 watermarks->cursor_trans[pipe] = 0;
3675
3676 /* Clear ddb entries for pipe */
3677 memset(&watermarks->ddb.pipe[pipe], 0, sizeof(struct skl_ddb_entry));
3678 memset(&watermarks->ddb.plane[pipe], 0,
3679 sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
3680 memset(&watermarks->ddb.y_plane[pipe], 0,
3681 sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
3682 memset(&watermarks->ddb.cursor[pipe], 0, sizeof(struct skl_ddb_entry));
3683
3684 }
3685
3686 static void skl_update_wm(struct drm_crtc *crtc)
3687 {
3688 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3689 struct drm_device *dev = crtc->dev;
3690 struct drm_i915_private *dev_priv = dev->dev_private;
3691 struct skl_pipe_wm_parameters params = {};
3692 struct skl_wm_values *results = &dev_priv->wm.skl_results;
3693 struct skl_pipe_wm pipe_wm = {};
3694 struct intel_wm_config config = {};
3695
3696
3697 /* Clear all dirty flags */
3698 memset(results->dirty, 0, sizeof(bool) * I915_MAX_PIPES);
3699
3700 skl_clear_wm(results, intel_crtc->pipe);
3701
3702 skl_compute_wm_global_parameters(dev, &config);
3703
3704 if (!skl_update_pipe_wm(crtc, &params, &config,
3705 &results->ddb, &pipe_wm))
3706 return;
3707
3708 skl_compute_wm_results(dev, &params, &pipe_wm, results, intel_crtc);
3709 results->dirty[intel_crtc->pipe] = true;
3710
3711 skl_update_other_pipe_wm(dev, crtc, &config, results);
3712 skl_write_wm_values(dev_priv, results);
3713 skl_flush_wm_values(dev_priv, results);
3714
3715 /* store the new configuration */
3716 dev_priv->wm.skl_hw = *results;
3717 }
3718
3719 static void
3720 skl_update_sprite_wm(struct drm_plane *plane, struct drm_crtc *crtc,
3721 uint32_t sprite_width, uint32_t sprite_height,
3722 int pixel_size, bool enabled, bool scaled)
3723 {
3724 struct intel_plane *intel_plane = to_intel_plane(plane);
3725 struct drm_framebuffer *fb = plane->state->fb;
3726
3727 intel_plane->wm.enabled = enabled;
3728 intel_plane->wm.scaled = scaled;
3729 intel_plane->wm.horiz_pixels = sprite_width;
3730 intel_plane->wm.vert_pixels = sprite_height;
3731 intel_plane->wm.tiling = DRM_FORMAT_MOD_NONE;
3732
3733 /* For planar: Bpp is for UV plane, y_Bpp is for Y plane */
3734 intel_plane->wm.bytes_per_pixel =
3735 (fb && fb->pixel_format == DRM_FORMAT_NV12) ?
3736 drm_format_plane_cpp(plane->state->fb->pixel_format, 1) : pixel_size;
3737 intel_plane->wm.y_bytes_per_pixel =
3738 (fb && fb->pixel_format == DRM_FORMAT_NV12) ?
3739 drm_format_plane_cpp(plane->state->fb->pixel_format, 0) : 0;
3740
3741 /*
3742 * Framebuffer can be NULL on plane disable, but it does not
3743 * matter for watermarks if we assume no tiling in that case.
3744 */
3745 if (fb)
3746 intel_plane->wm.tiling = fb->modifier[0];
3747 intel_plane->wm.rotation = plane->state->rotation;
3748
3749 skl_update_wm(crtc);
3750 }
3751
3752 static void ilk_update_wm(struct drm_crtc *crtc)
3753 {
3754 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3755 struct drm_device *dev = crtc->dev;
3756 struct drm_i915_private *dev_priv = dev->dev_private;
3757 struct ilk_wm_maximums max;
3758 struct ilk_pipe_wm_parameters params = {};
3759 struct ilk_wm_values results = {};
3760 enum intel_ddb_partitioning partitioning;
3761 struct intel_pipe_wm pipe_wm = {};
3762 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
3763 struct intel_wm_config config = {};
3764
3765 ilk_compute_wm_parameters(crtc, &params);
3766
3767 intel_compute_pipe_wm(crtc, &params, &pipe_wm);
3768
3769 if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
3770 return;
3771
3772 intel_crtc->wm.active = pipe_wm;
3773
3774 ilk_compute_wm_config(dev, &config);
3775
3776 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
3777 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
3778
3779 /* 5/6 split only in single pipe config on IVB+ */
3780 if (INTEL_INFO(dev)->gen >= 7 &&
3781 config.num_pipes_active == 1 && config.sprites_enabled) {
3782 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
3783 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
3784
3785 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
3786 } else {
3787 best_lp_wm = &lp_wm_1_2;
3788 }
3789
3790 partitioning = (best_lp_wm == &lp_wm_1_2) ?
3791 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
3792
3793 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
3794
3795 ilk_write_wm_values(dev_priv, &results);
3796 }
3797
3798 static void
3799 ilk_update_sprite_wm(struct drm_plane *plane,
3800 struct drm_crtc *crtc,
3801 uint32_t sprite_width, uint32_t sprite_height,
3802 int pixel_size, bool enabled, bool scaled)
3803 {
3804 struct drm_device *dev = plane->dev;
3805 struct intel_plane *intel_plane = to_intel_plane(plane);
3806
3807 intel_plane->wm.enabled = enabled;
3808 intel_plane->wm.scaled = scaled;
3809 intel_plane->wm.horiz_pixels = sprite_width;
3810 intel_plane->wm.vert_pixels = sprite_width;
3811 intel_plane->wm.bytes_per_pixel = pixel_size;
3812
3813 /*
3814 * IVB workaround: must disable low power watermarks for at least
3815 * one frame before enabling scaling. LP watermarks can be re-enabled
3816 * when scaling is disabled.
3817 *
3818 * WaCxSRDisabledForSpriteScaling:ivb
3819 */
3820 if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev))
3821 intel_wait_for_vblank(dev, intel_plane->pipe);
3822
3823 ilk_update_wm(crtc);
3824 }
3825
3826 static void skl_pipe_wm_active_state(uint32_t val,
3827 struct skl_pipe_wm *active,
3828 bool is_transwm,
3829 bool is_cursor,
3830 int i,
3831 int level)
3832 {
3833 bool is_enabled = (val & PLANE_WM_EN) != 0;
3834
3835 if (!is_transwm) {
3836 if (!is_cursor) {
3837 active->wm[level].plane_en[i] = is_enabled;
3838 active->wm[level].plane_res_b[i] =
3839 val & PLANE_WM_BLOCKS_MASK;
3840 active->wm[level].plane_res_l[i] =
3841 (val >> PLANE_WM_LINES_SHIFT) &
3842 PLANE_WM_LINES_MASK;
3843 } else {
3844 active->wm[level].cursor_en = is_enabled;
3845 active->wm[level].cursor_res_b =
3846 val & PLANE_WM_BLOCKS_MASK;
3847 active->wm[level].cursor_res_l =
3848 (val >> PLANE_WM_LINES_SHIFT) &
3849 PLANE_WM_LINES_MASK;
3850 }
3851 } else {
3852 if (!is_cursor) {
3853 active->trans_wm.plane_en[i] = is_enabled;
3854 active->trans_wm.plane_res_b[i] =
3855 val & PLANE_WM_BLOCKS_MASK;
3856 active->trans_wm.plane_res_l[i] =
3857 (val >> PLANE_WM_LINES_SHIFT) &
3858 PLANE_WM_LINES_MASK;
3859 } else {
3860 active->trans_wm.cursor_en = is_enabled;
3861 active->trans_wm.cursor_res_b =
3862 val & PLANE_WM_BLOCKS_MASK;
3863 active->trans_wm.cursor_res_l =
3864 (val >> PLANE_WM_LINES_SHIFT) &
3865 PLANE_WM_LINES_MASK;
3866 }
3867 }
3868 }
3869
3870 static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3871 {
3872 struct drm_device *dev = crtc->dev;
3873 struct drm_i915_private *dev_priv = dev->dev_private;
3874 struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
3875 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3876 struct skl_pipe_wm *active = &intel_crtc->wm.skl_active;
3877 enum pipe pipe = intel_crtc->pipe;
3878 int level, i, max_level;
3879 uint32_t temp;
3880
3881 max_level = ilk_wm_max_level(dev);
3882
3883 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3884
3885 for (level = 0; level <= max_level; level++) {
3886 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3887 hw->plane[pipe][i][level] =
3888 I915_READ(PLANE_WM(pipe, i, level));
3889 hw->cursor[pipe][level] = I915_READ(CUR_WM(pipe, level));
3890 }
3891
3892 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3893 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
3894 hw->cursor_trans[pipe] = I915_READ(CUR_WM_TRANS(pipe));
3895
3896 if (!intel_crtc->active)
3897 return;
3898
3899 hw->dirty[pipe] = true;
3900
3901 active->linetime = hw->wm_linetime[pipe];
3902
3903 for (level = 0; level <= max_level; level++) {
3904 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3905 temp = hw->plane[pipe][i][level];
3906 skl_pipe_wm_active_state(temp, active, false,
3907 false, i, level);
3908 }
3909 temp = hw->cursor[pipe][level];
3910 skl_pipe_wm_active_state(temp, active, false, true, i, level);
3911 }
3912
3913 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3914 temp = hw->plane_trans[pipe][i];
3915 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
3916 }
3917
3918 temp = hw->cursor_trans[pipe];
3919 skl_pipe_wm_active_state(temp, active, true, true, i, 0);
3920 }
3921
3922 void skl_wm_get_hw_state(struct drm_device *dev)
3923 {
3924 struct drm_i915_private *dev_priv = dev->dev_private;
3925 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3926 struct drm_crtc *crtc;
3927
3928 skl_ddb_get_hw_state(dev_priv, ddb);
3929 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3930 skl_pipe_wm_get_hw_state(crtc);
3931 }
3932
3933 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3934 {
3935 struct drm_device *dev = crtc->dev;
3936 struct drm_i915_private *dev_priv = dev->dev_private;
3937 struct ilk_wm_values *hw = &dev_priv->wm.hw;
3938 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3939 struct intel_pipe_wm *active = &intel_crtc->wm.active;
3940 enum pipe pipe = intel_crtc->pipe;
3941 static const unsigned int wm0_pipe_reg[] = {
3942 [PIPE_A] = WM0_PIPEA_ILK,
3943 [PIPE_B] = WM0_PIPEB_ILK,
3944 [PIPE_C] = WM0_PIPEC_IVB,
3945 };
3946
3947 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
3948 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3949 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3950
3951 active->pipe_enabled = intel_crtc->active;
3952
3953 if (active->pipe_enabled) {
3954 u32 tmp = hw->wm_pipe[pipe];
3955
3956 /*
3957 * For active pipes LP0 watermark is marked as
3958 * enabled, and LP1+ watermaks as disabled since
3959 * we can't really reverse compute them in case
3960 * multiple pipes are active.
3961 */
3962 active->wm[0].enable = true;
3963 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3964 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3965 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3966 active->linetime = hw->wm_linetime[pipe];
3967 } else {
3968 int level, max_level = ilk_wm_max_level(dev);
3969
3970 /*
3971 * For inactive pipes, all watermark levels
3972 * should be marked as enabled but zeroed,
3973 * which is what we'd compute them to.
3974 */
3975 for (level = 0; level <= max_level; level++)
3976 active->wm[level].enable = true;
3977 }
3978 }
3979
3980 #define _FW_WM(value, plane) \
3981 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
3982 #define _FW_WM_VLV(value, plane) \
3983 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
3984
3985 static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
3986 struct vlv_wm_values *wm)
3987 {
3988 enum pipe pipe;
3989 uint32_t tmp;
3990
3991 for_each_pipe(dev_priv, pipe) {
3992 tmp = I915_READ(VLV_DDL(pipe));
3993
3994 wm->ddl[pipe].primary =
3995 (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3996 wm->ddl[pipe].cursor =
3997 (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3998 wm->ddl[pipe].sprite[0] =
3999 (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4000 wm->ddl[pipe].sprite[1] =
4001 (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4002 }
4003
4004 tmp = I915_READ(DSPFW1);
4005 wm->sr.plane = _FW_WM(tmp, SR);
4006 wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
4007 wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
4008 wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
4009
4010 tmp = I915_READ(DSPFW2);
4011 wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
4012 wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
4013 wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
4014
4015 tmp = I915_READ(DSPFW3);
4016 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
4017
4018 if (IS_CHERRYVIEW(dev_priv)) {
4019 tmp = I915_READ(DSPFW7_CHV);
4020 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4021 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4022
4023 tmp = I915_READ(DSPFW8_CHV);
4024 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
4025 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
4026
4027 tmp = I915_READ(DSPFW9_CHV);
4028 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
4029 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
4030
4031 tmp = I915_READ(DSPHOWM);
4032 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4033 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
4034 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
4035 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
4036 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4037 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4038 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4039 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4040 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4041 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4042 } else {
4043 tmp = I915_READ(DSPFW7);
4044 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4045 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4046
4047 tmp = I915_READ(DSPHOWM);
4048 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4049 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4050 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4051 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4052 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4053 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4054 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4055 }
4056 }
4057
4058 #undef _FW_WM
4059 #undef _FW_WM_VLV
4060
4061 void vlv_wm_get_hw_state(struct drm_device *dev)
4062 {
4063 struct drm_i915_private *dev_priv = to_i915(dev);
4064 struct vlv_wm_values *wm = &dev_priv->wm.vlv;
4065 struct intel_plane *plane;
4066 enum pipe pipe;
4067 u32 val;
4068
4069 vlv_read_wm_values(dev_priv, wm);
4070
4071 for_each_intel_plane(dev, plane) {
4072 switch (plane->base.type) {
4073 int sprite;
4074 case DRM_PLANE_TYPE_CURSOR:
4075 plane->wm.fifo_size = 63;
4076 break;
4077 case DRM_PLANE_TYPE_PRIMARY:
4078 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
4079 break;
4080 case DRM_PLANE_TYPE_OVERLAY:
4081 sprite = plane->plane;
4082 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
4083 break;
4084 }
4085 }
4086
4087 wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4088 wm->level = VLV_WM_LEVEL_PM2;
4089
4090 if (IS_CHERRYVIEW(dev_priv)) {
4091 mutex_lock(&dev_priv->rps.hw_lock);
4092
4093 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4094 if (val & DSP_MAXFIFO_PM5_ENABLE)
4095 wm->level = VLV_WM_LEVEL_PM5;
4096
4097 /*
4098 * If DDR DVFS is disabled in the BIOS, Punit
4099 * will never ack the request. So if that happens
4100 * assume we don't have to enable/disable DDR DVFS
4101 * dynamically. To test that just set the REQ_ACK
4102 * bit to poke the Punit, but don't change the
4103 * HIGH/LOW bits so that we don't actually change
4104 * the current state.
4105 */
4106 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4107 val |= FORCE_DDR_FREQ_REQ_ACK;
4108 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
4109
4110 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
4111 FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
4112 DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4113 "assuming DDR DVFS is disabled\n");
4114 dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
4115 } else {
4116 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4117 if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4118 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4119 }
4120
4121 mutex_unlock(&dev_priv->rps.hw_lock);
4122 }
4123
4124 for_each_pipe(dev_priv, pipe)
4125 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4126 pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4127 wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4128
4129 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4130 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4131 }
4132
4133 void ilk_wm_get_hw_state(struct drm_device *dev)
4134 {
4135 struct drm_i915_private *dev_priv = dev->dev_private;
4136 struct ilk_wm_values *hw = &dev_priv->wm.hw;
4137 struct drm_crtc *crtc;
4138
4139 for_each_crtc(dev, crtc)
4140 ilk_pipe_wm_get_hw_state(crtc);
4141
4142 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4143 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4144 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4145
4146 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
4147 if (INTEL_INFO(dev)->gen >= 7) {
4148 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4149 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4150 }
4151
4152 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4153 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4154 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4155 else if (IS_IVYBRIDGE(dev))
4156 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4157 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4158
4159 hw->enable_fbc_wm =
4160 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4161 }
4162
4163 /**
4164 * intel_update_watermarks - update FIFO watermark values based on current modes
4165 *
4166 * Calculate watermark values for the various WM regs based on current mode
4167 * and plane configuration.
4168 *
4169 * There are several cases to deal with here:
4170 * - normal (i.e. non-self-refresh)
4171 * - self-refresh (SR) mode
4172 * - lines are large relative to FIFO size (buffer can hold up to 2)
4173 * - lines are small relative to FIFO size (buffer can hold more than 2
4174 * lines), so need to account for TLB latency
4175 *
4176 * The normal calculation is:
4177 * watermark = dotclock * bytes per pixel * latency
4178 * where latency is platform & configuration dependent (we assume pessimal
4179 * values here).
4180 *
4181 * The SR calculation is:
4182 * watermark = (trunc(latency/line time)+1) * surface width *
4183 * bytes per pixel
4184 * where
4185 * line time = htotal / dotclock
4186 * surface width = hdisplay for normal plane and 64 for cursor
4187 * and latency is assumed to be high, as above.
4188 *
4189 * The final value programmed to the register should always be rounded up,
4190 * and include an extra 2 entries to account for clock crossings.
4191 *
4192 * We don't use the sprite, so we can ignore that. And on Crestline we have
4193 * to set the non-SR watermarks to 8.
4194 */
4195 void intel_update_watermarks(struct drm_crtc *crtc)
4196 {
4197 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4198
4199 if (dev_priv->display.update_wm)
4200 dev_priv->display.update_wm(crtc);
4201 }
4202
4203 void intel_update_sprite_watermarks(struct drm_plane *plane,
4204 struct drm_crtc *crtc,
4205 uint32_t sprite_width,
4206 uint32_t sprite_height,
4207 int pixel_size,
4208 bool enabled, bool scaled)
4209 {
4210 struct drm_i915_private *dev_priv = plane->dev->dev_private;
4211
4212 if (dev_priv->display.update_sprite_wm)
4213 dev_priv->display.update_sprite_wm(plane, crtc,
4214 sprite_width, sprite_height,
4215 pixel_size, enabled, scaled);
4216 }
4217
4218 /**
4219 * Lock protecting IPS related data structures
4220 */
4221 DEFINE_SPINLOCK(mchdev_lock);
4222
4223 /* Global for IPS driver to get at the current i915 device. Protected by
4224 * mchdev_lock. */
4225 static struct drm_i915_private *i915_mch_dev;
4226
4227 bool ironlake_set_drps(struct drm_device *dev, u8 val)
4228 {
4229 struct drm_i915_private *dev_priv = dev->dev_private;
4230 u16 rgvswctl;
4231
4232 assert_spin_locked(&mchdev_lock);
4233
4234 rgvswctl = I915_READ16(MEMSWCTL);
4235 if (rgvswctl & MEMCTL_CMD_STS) {
4236 DRM_DEBUG("gpu busy, RCS change rejected\n");
4237 return false; /* still busy with another command */
4238 }
4239
4240 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4241 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4242 I915_WRITE16(MEMSWCTL, rgvswctl);
4243 POSTING_READ16(MEMSWCTL);
4244
4245 rgvswctl |= MEMCTL_CMD_STS;
4246 I915_WRITE16(MEMSWCTL, rgvswctl);
4247
4248 return true;
4249 }
4250
4251 static void ironlake_enable_drps(struct drm_device *dev)
4252 {
4253 struct drm_i915_private *dev_priv = dev->dev_private;
4254 u32 rgvmodectl = I915_READ(MEMMODECTL);
4255 u8 fmax, fmin, fstart, vstart;
4256
4257 spin_lock_irq(&mchdev_lock);
4258
4259 /* Enable temp reporting */
4260 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4261 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4262
4263 /* 100ms RC evaluation intervals */
4264 I915_WRITE(RCUPEI, 100000);
4265 I915_WRITE(RCDNEI, 100000);
4266
4267 /* Set max/min thresholds to 90ms and 80ms respectively */
4268 I915_WRITE(RCBMAXAVG, 90000);
4269 I915_WRITE(RCBMINAVG, 80000);
4270
4271 I915_WRITE(MEMIHYST, 1);
4272
4273 /* Set up min, max, and cur for interrupt handling */
4274 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4275 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4276 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4277 MEMMODE_FSTART_SHIFT;
4278
4279 vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
4280 PXVFREQ_PX_SHIFT;
4281
4282 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4283 dev_priv->ips.fstart = fstart;
4284
4285 dev_priv->ips.max_delay = fstart;
4286 dev_priv->ips.min_delay = fmin;
4287 dev_priv->ips.cur_delay = fstart;
4288
4289 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4290 fmax, fmin, fstart);
4291
4292 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4293
4294 /*
4295 * Interrupts will be enabled in ironlake_irq_postinstall
4296 */
4297
4298 I915_WRITE(VIDSTART, vstart);
4299 POSTING_READ(VIDSTART);
4300
4301 rgvmodectl |= MEMMODE_SWMODE_EN;
4302 I915_WRITE(MEMMODECTL, rgvmodectl);
4303
4304 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
4305 DRM_ERROR("stuck trying to change perf mode\n");
4306 mdelay(1);
4307
4308 ironlake_set_drps(dev, fstart);
4309
4310 dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4311 I915_READ(DDREC) + I915_READ(CSIEC);
4312 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
4313 dev_priv->ips.last_count2 = I915_READ(GFXEC);
4314 dev_priv->ips.last_time2 = ktime_get_raw_ns();
4315
4316 spin_unlock_irq(&mchdev_lock);
4317 }
4318
4319 static void ironlake_disable_drps(struct drm_device *dev)
4320 {
4321 struct drm_i915_private *dev_priv = dev->dev_private;
4322 u16 rgvswctl;
4323
4324 spin_lock_irq(&mchdev_lock);
4325
4326 rgvswctl = I915_READ16(MEMSWCTL);
4327
4328 /* Ack interrupts, disable EFC interrupt */
4329 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4330 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4331 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4332 I915_WRITE(DEIIR, DE_PCU_EVENT);
4333 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4334
4335 /* Go back to the starting frequency */
4336 ironlake_set_drps(dev, dev_priv->ips.fstart);
4337 mdelay(1);
4338 rgvswctl |= MEMCTL_CMD_STS;
4339 I915_WRITE(MEMSWCTL, rgvswctl);
4340 mdelay(1);
4341
4342 spin_unlock_irq(&mchdev_lock);
4343 }
4344
4345 /* There's a funny hw issue where the hw returns all 0 when reading from
4346 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4347 * ourselves, instead of doing a rmw cycle (which might result in us clearing
4348 * all limits and the gpu stuck at whatever frequency it is at atm).
4349 */
4350 static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
4351 {
4352 u32 limits;
4353
4354 /* Only set the down limit when we've reached the lowest level to avoid
4355 * getting more interrupts, otherwise leave this clear. This prevents a
4356 * race in the hw when coming out of rc6: There's a tiny window where
4357 * the hw runs at the minimal clock before selecting the desired
4358 * frequency, if the down threshold expires in that window we will not
4359 * receive a down interrupt. */
4360 if (IS_GEN9(dev_priv->dev)) {
4361 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4362 if (val <= dev_priv->rps.min_freq_softlimit)
4363 limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4364 } else {
4365 limits = dev_priv->rps.max_freq_softlimit << 24;
4366 if (val <= dev_priv->rps.min_freq_softlimit)
4367 limits |= dev_priv->rps.min_freq_softlimit << 16;
4368 }
4369
4370 return limits;
4371 }
4372
4373 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4374 {
4375 int new_power;
4376 u32 threshold_up = 0, threshold_down = 0; /* in % */
4377 u32 ei_up = 0, ei_down = 0;
4378
4379 new_power = dev_priv->rps.power;
4380 switch (dev_priv->rps.power) {
4381 case LOW_POWER:
4382 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
4383 new_power = BETWEEN;
4384 break;
4385
4386 case BETWEEN:
4387 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
4388 new_power = LOW_POWER;
4389 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
4390 new_power = HIGH_POWER;
4391 break;
4392
4393 case HIGH_POWER:
4394 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
4395 new_power = BETWEEN;
4396 break;
4397 }
4398 /* Max/min bins are special */
4399 if (val <= dev_priv->rps.min_freq_softlimit)
4400 new_power = LOW_POWER;
4401 if (val >= dev_priv->rps.max_freq_softlimit)
4402 new_power = HIGH_POWER;
4403 if (new_power == dev_priv->rps.power)
4404 return;
4405
4406 /* Note the units here are not exactly 1us, but 1280ns. */
4407 switch (new_power) {
4408 case LOW_POWER:
4409 /* Upclock if more than 95% busy over 16ms */
4410 ei_up = 16000;
4411 threshold_up = 95;
4412
4413 /* Downclock if less than 85% busy over 32ms */
4414 ei_down = 32000;
4415 threshold_down = 85;
4416 break;
4417
4418 case BETWEEN:
4419 /* Upclock if more than 90% busy over 13ms */
4420 ei_up = 13000;
4421 threshold_up = 90;
4422
4423 /* Downclock if less than 75% busy over 32ms */
4424 ei_down = 32000;
4425 threshold_down = 75;
4426 break;
4427
4428 case HIGH_POWER:
4429 /* Upclock if more than 85% busy over 10ms */
4430 ei_up = 10000;
4431 threshold_up = 85;
4432
4433 /* Downclock if less than 60% busy over 32ms */
4434 ei_down = 32000;
4435 threshold_down = 60;
4436 break;
4437 }
4438
4439 I915_WRITE(GEN6_RP_UP_EI,
4440 GT_INTERVAL_FROM_US(dev_priv, ei_up));
4441 I915_WRITE(GEN6_RP_UP_THRESHOLD,
4442 GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100)));
4443
4444 I915_WRITE(GEN6_RP_DOWN_EI,
4445 GT_INTERVAL_FROM_US(dev_priv, ei_down));
4446 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4447 GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100)));
4448
4449 I915_WRITE(GEN6_RP_CONTROL,
4450 GEN6_RP_MEDIA_TURBO |
4451 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4452 GEN6_RP_MEDIA_IS_GFX |
4453 GEN6_RP_ENABLE |
4454 GEN6_RP_UP_BUSY_AVG |
4455 GEN6_RP_DOWN_IDLE_AVG);
4456
4457 dev_priv->rps.power = new_power;
4458 dev_priv->rps.up_threshold = threshold_up;
4459 dev_priv->rps.down_threshold = threshold_down;
4460 dev_priv->rps.last_adj = 0;
4461 }
4462
4463 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4464 {
4465 u32 mask = 0;
4466
4467 if (val > dev_priv->rps.min_freq_softlimit)
4468 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
4469 if (val < dev_priv->rps.max_freq_softlimit)
4470 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
4471
4472 mask &= dev_priv->pm_rps_events;
4473
4474 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
4475 }
4476
4477 /* gen6_set_rps is called to update the frequency request, but should also be
4478 * called when the range (min_delay and max_delay) is modified so that we can
4479 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
4480 static void gen6_set_rps(struct drm_device *dev, u8 val)
4481 {
4482 struct drm_i915_private *dev_priv = dev->dev_private;
4483
4484 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4485 if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0))
4486 return;
4487
4488 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4489 WARN_ON(val > dev_priv->rps.max_freq);
4490 WARN_ON(val < dev_priv->rps.min_freq);
4491
4492 /* min/max delay may still have been modified so be sure to
4493 * write the limits value.
4494 */
4495 if (val != dev_priv->rps.cur_freq) {
4496 gen6_set_rps_thresholds(dev_priv, val);
4497
4498 if (IS_GEN9(dev))
4499 I915_WRITE(GEN6_RPNSWREQ,
4500 GEN9_FREQUENCY(val));
4501 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4502 I915_WRITE(GEN6_RPNSWREQ,
4503 HSW_FREQUENCY(val));
4504 else
4505 I915_WRITE(GEN6_RPNSWREQ,
4506 GEN6_FREQUENCY(val) |
4507 GEN6_OFFSET(0) |
4508 GEN6_AGGRESSIVE_TURBO);
4509 }
4510
4511 /* Make sure we continue to get interrupts
4512 * until we hit the minimum or maximum frequencies.
4513 */
4514 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
4515 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4516
4517 POSTING_READ(GEN6_RPNSWREQ);
4518
4519 dev_priv->rps.cur_freq = val;
4520 trace_intel_gpu_freq_change(val * 50);
4521 }
4522
4523 static void valleyview_set_rps(struct drm_device *dev, u8 val)
4524 {
4525 struct drm_i915_private *dev_priv = dev->dev_private;
4526
4527 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4528 WARN_ON(val > dev_priv->rps.max_freq);
4529 WARN_ON(val < dev_priv->rps.min_freq);
4530
4531 if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1),
4532 "Odd GPU freq value\n"))
4533 val &= ~1;
4534
4535 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4536
4537 if (val != dev_priv->rps.cur_freq) {
4538 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
4539 if (!IS_CHERRYVIEW(dev_priv))
4540 gen6_set_rps_thresholds(dev_priv, val);
4541 }
4542
4543 dev_priv->rps.cur_freq = val;
4544 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4545 }
4546
4547 /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
4548 *
4549 * * If Gfx is Idle, then
4550 * 1. Forcewake Media well.
4551 * 2. Request idle freq.
4552 * 3. Release Forcewake of Media well.
4553 */
4554 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4555 {
4556 u32 val = dev_priv->rps.idle_freq;
4557
4558 if (dev_priv->rps.cur_freq <= val)
4559 return;
4560
4561 /* Wake up the media well, as that takes a lot less
4562 * power than the Render well. */
4563 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
4564 valleyview_set_rps(dev_priv->dev, val);
4565 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
4566 }
4567
4568 void gen6_rps_busy(struct drm_i915_private *dev_priv)
4569 {
4570 mutex_lock(&dev_priv->rps.hw_lock);
4571 if (dev_priv->rps.enabled) {
4572 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
4573 gen6_rps_reset_ei(dev_priv);
4574 I915_WRITE(GEN6_PMINTRMSK,
4575 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
4576 }
4577 mutex_unlock(&dev_priv->rps.hw_lock);
4578 }
4579
4580 void gen6_rps_idle(struct drm_i915_private *dev_priv)
4581 {
4582 struct drm_device *dev = dev_priv->dev;
4583
4584 mutex_lock(&dev_priv->rps.hw_lock);
4585 if (dev_priv->rps.enabled) {
4586 if (IS_VALLEYVIEW(dev))
4587 vlv_set_rps_idle(dev_priv);
4588 else
4589 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
4590 dev_priv->rps.last_adj = 0;
4591 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
4592 }
4593 mutex_unlock(&dev_priv->rps.hw_lock);
4594
4595 spin_lock(&dev_priv->rps.client_lock);
4596 while (!list_empty(&dev_priv->rps.clients))
4597 list_del_init(dev_priv->rps.clients.next);
4598 spin_unlock(&dev_priv->rps.client_lock);
4599 }
4600
4601 void gen6_rps_boost(struct drm_i915_private *dev_priv,
4602 struct intel_rps_client *rps,
4603 unsigned long submitted)
4604 {
4605 /* This is intentionally racy! We peek at the state here, then
4606 * validate inside the RPS worker.
4607 */
4608 if (!(dev_priv->mm.busy &&
4609 dev_priv->rps.enabled &&
4610 dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit))
4611 return;
4612
4613 /* Force a RPS boost (and don't count it against the client) if
4614 * the GPU is severely congested.
4615 */
4616 if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
4617 rps = NULL;
4618
4619 spin_lock(&dev_priv->rps.client_lock);
4620 if (rps == NULL || list_empty(&rps->link)) {
4621 spin_lock_irq(&dev_priv->irq_lock);
4622 if (dev_priv->rps.interrupts_enabled) {
4623 dev_priv->rps.client_boost = true;
4624 queue_work(dev_priv->wq, &dev_priv->rps.work);
4625 }
4626 spin_unlock_irq(&dev_priv->irq_lock);
4627
4628 if (rps != NULL) {
4629 list_add(&rps->link, &dev_priv->rps.clients);
4630 rps->boosts++;
4631 } else
4632 dev_priv->rps.boosts++;
4633 }
4634 spin_unlock(&dev_priv->rps.client_lock);
4635 }
4636
4637 void intel_set_rps(struct drm_device *dev, u8 val)
4638 {
4639 if (IS_VALLEYVIEW(dev))
4640 valleyview_set_rps(dev, val);
4641 else
4642 gen6_set_rps(dev, val);
4643 }
4644
4645 static void gen9_disable_rps(struct drm_device *dev)
4646 {
4647 struct drm_i915_private *dev_priv = dev->dev_private;
4648
4649 I915_WRITE(GEN6_RC_CONTROL, 0);
4650 I915_WRITE(GEN9_PG_ENABLE, 0);
4651 }
4652
4653 static void gen6_disable_rps(struct drm_device *dev)
4654 {
4655 struct drm_i915_private *dev_priv = dev->dev_private;
4656
4657 I915_WRITE(GEN6_RC_CONTROL, 0);
4658 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
4659 }
4660
4661 static void cherryview_disable_rps(struct drm_device *dev)
4662 {
4663 struct drm_i915_private *dev_priv = dev->dev_private;
4664
4665 I915_WRITE(GEN6_RC_CONTROL, 0);
4666 }
4667
4668 static void valleyview_disable_rps(struct drm_device *dev)
4669 {
4670 struct drm_i915_private *dev_priv = dev->dev_private;
4671
4672 /* we're doing forcewake before Disabling RC6,
4673 * This what the BIOS expects when going into suspend */
4674 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4675
4676 I915_WRITE(GEN6_RC_CONTROL, 0);
4677
4678 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4679 }
4680
4681 static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
4682 {
4683 if (IS_VALLEYVIEW(dev)) {
4684 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
4685 mode = GEN6_RC_CTL_RC6_ENABLE;
4686 else
4687 mode = 0;
4688 }
4689 if (HAS_RC6p(dev))
4690 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
4691 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
4692 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
4693 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
4694
4695 else
4696 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
4697 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off");
4698 }
4699
4700 static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
4701 {
4702 /* No RC6 before Ironlake and code is gone for ilk. */
4703 if (INTEL_INFO(dev)->gen < 6)
4704 return 0;
4705
4706 /* Respect the kernel parameter if it is set */
4707 if (enable_rc6 >= 0) {
4708 int mask;
4709
4710 if (HAS_RC6p(dev))
4711 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
4712 INTEL_RC6pp_ENABLE;
4713 else
4714 mask = INTEL_RC6_ENABLE;
4715
4716 if ((enable_rc6 & mask) != enable_rc6)
4717 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
4718 enable_rc6 & mask, enable_rc6, mask);
4719
4720 return enable_rc6 & mask;
4721 }
4722
4723 if (IS_IVYBRIDGE(dev))
4724 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
4725
4726 return INTEL_RC6_ENABLE;
4727 }
4728
4729 int intel_enable_rc6(const struct drm_device *dev)
4730 {
4731 return i915.enable_rc6;
4732 }
4733
4734 static void gen6_init_rps_frequencies(struct drm_device *dev)
4735 {
4736 struct drm_i915_private *dev_priv = dev->dev_private;
4737 uint32_t rp_state_cap;
4738 u32 ddcc_status = 0;
4739 int ret;
4740
4741 /* All of these values are in units of 50MHz */
4742 dev_priv->rps.cur_freq = 0;
4743 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
4744 if (IS_BROXTON(dev)) {
4745 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
4746 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
4747 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
4748 dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff;
4749 } else {
4750 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
4751 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
4752 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
4753 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
4754 }
4755
4756 /* hw_max = RP0 until we check for overclocking */
4757 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
4758
4759 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
4760 if (IS_HASWELL(dev) || IS_BROADWELL(dev) || IS_SKYLAKE(dev)) {
4761 ret = sandybridge_pcode_read(dev_priv,
4762 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
4763 &ddcc_status);
4764 if (0 == ret)
4765 dev_priv->rps.efficient_freq =
4766 clamp_t(u8,
4767 ((ddcc_status >> 8) & 0xff),
4768 dev_priv->rps.min_freq,
4769 dev_priv->rps.max_freq);
4770 }
4771
4772 if (IS_SKYLAKE(dev)) {
4773 /* Store the frequency values in 16.66 MHZ units, which is
4774 the natural hardware unit for SKL */
4775 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
4776 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
4777 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
4778 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
4779 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
4780 }
4781
4782 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
4783
4784 /* Preserve min/max settings in case of re-init */
4785 if (dev_priv->rps.max_freq_softlimit == 0)
4786 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4787
4788 if (dev_priv->rps.min_freq_softlimit == 0) {
4789 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4790 dev_priv->rps.min_freq_softlimit =
4791 max_t(int, dev_priv->rps.efficient_freq,
4792 intel_freq_opcode(dev_priv, 450));
4793 else
4794 dev_priv->rps.min_freq_softlimit =
4795 dev_priv->rps.min_freq;
4796 }
4797 }
4798
4799 /* See the Gen9_GT_PM_Programming_Guide doc for the below */
4800 static void gen9_enable_rps(struct drm_device *dev)
4801 {
4802 struct drm_i915_private *dev_priv = dev->dev_private;
4803
4804 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4805
4806 gen6_init_rps_frequencies(dev);
4807
4808 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4809 if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) {
4810 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4811 return;
4812 }
4813
4814 /* Program defaults and thresholds for RPS*/
4815 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4816 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
4817
4818 /* 1 second timeout*/
4819 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
4820 GT_INTERVAL_FROM_US(dev_priv, 1000000));
4821
4822 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
4823
4824 /* Leaning on the below call to gen6_set_rps to program/setup the
4825 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
4826 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
4827 dev_priv->rps.power = HIGH_POWER; /* force a reset */
4828 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
4829
4830 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4831 }
4832
4833 static void gen9_enable_rc6(struct drm_device *dev)
4834 {
4835 struct drm_i915_private *dev_priv = dev->dev_private;
4836 struct intel_engine_cs *ring;
4837 uint32_t rc6_mask = 0;
4838 int unused;
4839
4840 /* 1a: Software RC state - RC0 */
4841 I915_WRITE(GEN6_RC_STATE, 0);
4842
4843 /* 1b: Get forcewake during program sequence. Although the driver
4844 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4845 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4846
4847 /* 2a: Disable RC states. */
4848 I915_WRITE(GEN6_RC_CONTROL, 0);
4849
4850 /* 2b: Program RC6 thresholds.*/
4851
4852 /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
4853 if (IS_SKYLAKE(dev) && !((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) &&
4854 (INTEL_REVID(dev) <= SKL_REVID_E0)))
4855 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
4856 else
4857 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
4858 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4859 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4860 for_each_ring(ring, dev_priv, unused)
4861 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4862
4863 if (HAS_GUC_UCODE(dev))
4864 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
4865
4866 I915_WRITE(GEN6_RC_SLEEP, 0);
4867 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
4868
4869 /* 2c: Program Coarse Power Gating Policies. */
4870 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
4871 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
4872
4873 /* 3a: Enable RC6 */
4874 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4875 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4876 DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4877 "on" : "off");
4878
4879 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_D0) ||
4880 (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A0))
4881 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4882 GEN7_RC_CTL_TO_MODE |
4883 rc6_mask);
4884 else
4885 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4886 GEN6_RC_CTL_EI_MODE(1) |
4887 rc6_mask);
4888
4889 /*
4890 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
4891 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
4892 */
4893 if ((IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) ||
4894 ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && (INTEL_REVID(dev) <= SKL_REVID_E0)))
4895 I915_WRITE(GEN9_PG_ENABLE, 0);
4896 else
4897 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4898 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
4899
4900 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4901
4902 }
4903
4904 static void gen8_enable_rps(struct drm_device *dev)
4905 {
4906 struct drm_i915_private *dev_priv = dev->dev_private;
4907 struct intel_engine_cs *ring;
4908 uint32_t rc6_mask = 0;
4909 int unused;
4910
4911 /* 1a: Software RC state - RC0 */
4912 I915_WRITE(GEN6_RC_STATE, 0);
4913
4914 /* 1c & 1d: Get forcewake during program sequence. Although the driver
4915 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4916 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4917
4918 /* 2a: Disable RC states. */
4919 I915_WRITE(GEN6_RC_CONTROL, 0);
4920
4921 /* Initialize rps frequencies */
4922 gen6_init_rps_frequencies(dev);
4923
4924 /* 2b: Program RC6 thresholds.*/
4925 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4926 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4927 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4928 for_each_ring(ring, dev_priv, unused)
4929 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4930 I915_WRITE(GEN6_RC_SLEEP, 0);
4931 if (IS_BROADWELL(dev))
4932 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
4933 else
4934 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
4935
4936 /* 3: Enable RC6 */
4937 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4938 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4939 intel_print_rc6_info(dev, rc6_mask);
4940 if (IS_BROADWELL(dev))
4941 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4942 GEN7_RC_CTL_TO_MODE |
4943 rc6_mask);
4944 else
4945 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4946 GEN6_RC_CTL_EI_MODE(1) |
4947 rc6_mask);
4948
4949 /* 4 Program defaults and thresholds for RPS*/
4950 I915_WRITE(GEN6_RPNSWREQ,
4951 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4952 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4953 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4954 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
4955 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
4956
4957 /* Docs recommend 900MHz, and 300 MHz respectively */
4958 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
4959 dev_priv->rps.max_freq_softlimit << 24 |
4960 dev_priv->rps.min_freq_softlimit << 16);
4961
4962 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
4963 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
4964 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
4965 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
4966
4967 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4968
4969 /* 5: Enable RPS */
4970 I915_WRITE(GEN6_RP_CONTROL,
4971 GEN6_RP_MEDIA_TURBO |
4972 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4973 GEN6_RP_MEDIA_IS_GFX |
4974 GEN6_RP_ENABLE |
4975 GEN6_RP_UP_BUSY_AVG |
4976 GEN6_RP_DOWN_IDLE_AVG);
4977
4978 /* 6: Ring frequency + overclocking (our driver does this later */
4979
4980 dev_priv->rps.power = HIGH_POWER; /* force a reset */
4981 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
4982
4983 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4984 }
4985
4986 static void gen6_enable_rps(struct drm_device *dev)
4987 {
4988 struct drm_i915_private *dev_priv = dev->dev_private;
4989 struct intel_engine_cs *ring;
4990 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
4991 u32 gtfifodbg;
4992 int rc6_mode;
4993 int i, ret;
4994
4995 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4996
4997 /* Here begins a magic sequence of register writes to enable
4998 * auto-downclocking.
4999 *
5000 * Perhaps there might be some value in exposing these to
5001 * userspace...
5002 */
5003 I915_WRITE(GEN6_RC_STATE, 0);
5004
5005 /* Clear the DBG now so we don't confuse earlier errors */
5006 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
5007 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
5008 I915_WRITE(GTFIFODBG, gtfifodbg);
5009 }
5010
5011 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5012
5013 /* Initialize rps frequencies */
5014 gen6_init_rps_frequencies(dev);
5015
5016 /* disable the counters and set deterministic thresholds */
5017 I915_WRITE(GEN6_RC_CONTROL, 0);
5018
5019 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
5020 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
5021 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
5022 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5023 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5024
5025 for_each_ring(ring, dev_priv, i)
5026 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5027
5028 I915_WRITE(GEN6_RC_SLEEP, 0);
5029 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
5030 if (IS_IVYBRIDGE(dev))
5031 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
5032 else
5033 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
5034 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
5035 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
5036
5037 /* Check if we are enabling RC6 */
5038 rc6_mode = intel_enable_rc6(dev_priv->dev);
5039 if (rc6_mode & INTEL_RC6_ENABLE)
5040 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
5041
5042 /* We don't use those on Haswell */
5043 if (!IS_HASWELL(dev)) {
5044 if (rc6_mode & INTEL_RC6p_ENABLE)
5045 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
5046
5047 if (rc6_mode & INTEL_RC6pp_ENABLE)
5048 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
5049 }
5050
5051 intel_print_rc6_info(dev, rc6_mask);
5052
5053 I915_WRITE(GEN6_RC_CONTROL,
5054 rc6_mask |
5055 GEN6_RC_CTL_EI_MODE(1) |
5056 GEN6_RC_CTL_HW_ENABLE);
5057
5058 /* Power down if completely idle for over 50ms */
5059 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
5060 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5061
5062 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
5063 if (ret)
5064 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
5065
5066 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
5067 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
5068 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
5069 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
5070 (pcu_mbox & 0xff) * 50);
5071 dev_priv->rps.max_freq = pcu_mbox & 0xff;
5072 }
5073
5074 dev_priv->rps.power = HIGH_POWER; /* force a reset */
5075 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
5076
5077 rc6vids = 0;
5078 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
5079 if (IS_GEN6(dev) && ret) {
5080 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
5081 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
5082 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5083 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5084 rc6vids &= 0xffff00;
5085 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5086 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5087 if (ret)
5088 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5089 }
5090
5091 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5092 }
5093
5094 static void __gen6_update_ring_freq(struct drm_device *dev)
5095 {
5096 struct drm_i915_private *dev_priv = dev->dev_private;
5097 int min_freq = 15;
5098 unsigned int gpu_freq;
5099 unsigned int max_ia_freq, min_ring_freq;
5100 unsigned int max_gpu_freq, min_gpu_freq;
5101 int scaling_factor = 180;
5102 struct cpufreq_policy *policy;
5103
5104 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5105
5106 policy = cpufreq_cpu_get(0);
5107 if (policy) {
5108 max_ia_freq = policy->cpuinfo.max_freq;
5109 cpufreq_cpu_put(policy);
5110 } else {
5111 /*
5112 * Default to measured freq if none found, PCU will ensure we
5113 * don't go over
5114 */
5115 max_ia_freq = tsc_khz;
5116 }
5117
5118 /* Convert from kHz to MHz */
5119 max_ia_freq /= 1000;
5120
5121 min_ring_freq = I915_READ(DCLK) & 0xf;
5122 /* convert DDR frequency from units of 266.6MHz to bandwidth */
5123 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
5124
5125 if (IS_SKYLAKE(dev)) {
5126 /* Convert GT frequency to 50 HZ units */
5127 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5128 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5129 } else {
5130 min_gpu_freq = dev_priv->rps.min_freq;
5131 max_gpu_freq = dev_priv->rps.max_freq;
5132 }
5133
5134 /*
5135 * For each potential GPU frequency, load a ring frequency we'd like
5136 * to use for memory access. We do this by specifying the IA frequency
5137 * the PCU should use as a reference to determine the ring frequency.
5138 */
5139 for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5140 int diff = max_gpu_freq - gpu_freq;
5141 unsigned int ia_freq = 0, ring_freq = 0;
5142
5143 if (IS_SKYLAKE(dev)) {
5144 /*
5145 * ring_freq = 2 * GT. ring_freq is in 100MHz units
5146 * No floor required for ring frequency on SKL.
5147 */
5148 ring_freq = gpu_freq;
5149 } else if (INTEL_INFO(dev)->gen >= 8) {
5150 /* max(2 * GT, DDR). NB: GT is 50MHz units */
5151 ring_freq = max(min_ring_freq, gpu_freq);
5152 } else if (IS_HASWELL(dev)) {
5153 ring_freq = mult_frac(gpu_freq, 5, 4);
5154 ring_freq = max(min_ring_freq, ring_freq);
5155 /* leave ia_freq as the default, chosen by cpufreq */
5156 } else {
5157 /* On older processors, there is no separate ring
5158 * clock domain, so in order to boost the bandwidth
5159 * of the ring, we need to upclock the CPU (ia_freq).
5160 *
5161 * For GPU frequencies less than 750MHz,
5162 * just use the lowest ring freq.
5163 */
5164 if (gpu_freq < min_freq)
5165 ia_freq = 800;
5166 else
5167 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5168 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5169 }
5170
5171 sandybridge_pcode_write(dev_priv,
5172 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
5173 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5174 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5175 gpu_freq);
5176 }
5177 }
5178
5179 void gen6_update_ring_freq(struct drm_device *dev)
5180 {
5181 struct drm_i915_private *dev_priv = dev->dev_private;
5182
5183 if (!HAS_CORE_RING_FREQ(dev))
5184 return;
5185
5186 mutex_lock(&dev_priv->rps.hw_lock);
5187 __gen6_update_ring_freq(dev);
5188 mutex_unlock(&dev_priv->rps.hw_lock);
5189 }
5190
5191 static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
5192 {
5193 struct drm_device *dev = dev_priv->dev;
5194 u32 val, rp0;
5195
5196 if (dev->pdev->revision >= 0x20) {
5197 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5198
5199 switch (INTEL_INFO(dev)->eu_total) {
5200 case 8:
5201 /* (2 * 4) config */
5202 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5203 break;
5204 case 12:
5205 /* (2 * 6) config */
5206 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5207 break;
5208 case 16:
5209 /* (2 * 8) config */
5210 default:
5211 /* Setting (2 * 8) Min RP0 for any other combination */
5212 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5213 break;
5214 }
5215 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5216 } else {
5217 /* For pre-production hardware */
5218 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
5219 rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
5220 PUNIT_GPU_STATUS_MAX_FREQ_MASK;
5221 }
5222 return rp0;
5223 }
5224
5225 static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5226 {
5227 u32 val, rpe;
5228
5229 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5230 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5231
5232 return rpe;
5233 }
5234
5235 static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5236 {
5237 struct drm_device *dev = dev_priv->dev;
5238 u32 val, rp1;
5239
5240 if (dev->pdev->revision >= 0x20) {
5241 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5242 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5243 } else {
5244 /* For pre-production hardware */
5245 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5246 rp1 = ((val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
5247 PUNIT_GPU_STATUS_MAX_FREQ_MASK);
5248 }
5249 return rp1;
5250 }
5251
5252 static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5253 {
5254 u32 val, rp1;
5255
5256 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5257
5258 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5259
5260 return rp1;
5261 }
5262
5263 static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
5264 {
5265 u32 val, rp0;
5266
5267 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5268
5269 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5270 /* Clamp to max */
5271 rp0 = min_t(u32, rp0, 0xea);
5272
5273 return rp0;
5274 }
5275
5276 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5277 {
5278 u32 val, rpe;
5279
5280 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
5281 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
5282 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
5283 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5284
5285 return rpe;
5286 }
5287
5288 static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
5289 {
5290 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5291 }
5292
5293 /* Check that the pctx buffer wasn't move under us. */
5294 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5295 {
5296 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5297
5298 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5299 dev_priv->vlv_pctx->stolen->start);
5300 }
5301
5302
5303 /* Check that the pcbr address is not empty. */
5304 static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5305 {
5306 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5307
5308 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5309 }
5310
5311 static void cherryview_setup_pctx(struct drm_device *dev)
5312 {
5313 struct drm_i915_private *dev_priv = dev->dev_private;
5314 unsigned long pctx_paddr, paddr;
5315 struct i915_gtt *gtt = &dev_priv->gtt;
5316 u32 pcbr;
5317 int pctx_size = 32*1024;
5318
5319 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
5320
5321 pcbr = I915_READ(VLV_PCBR);
5322 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
5323 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5324 paddr = (dev_priv->mm.stolen_base +
5325 (gtt->stolen_size - pctx_size));
5326
5327 pctx_paddr = (paddr & (~4095));
5328 I915_WRITE(VLV_PCBR, pctx_paddr);
5329 }
5330
5331 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5332 }
5333
5334 static void valleyview_setup_pctx(struct drm_device *dev)
5335 {
5336 struct drm_i915_private *dev_priv = dev->dev_private;
5337 struct drm_i915_gem_object *pctx;
5338 unsigned long pctx_paddr;
5339 u32 pcbr;
5340 int pctx_size = 24*1024;
5341
5342 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
5343
5344 pcbr = I915_READ(VLV_PCBR);
5345 if (pcbr) {
5346 /* BIOS set it up already, grab the pre-alloc'd space */
5347 int pcbr_offset;
5348
5349 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
5350 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
5351 pcbr_offset,
5352 I915_GTT_OFFSET_NONE,
5353 pctx_size);
5354 goto out;
5355 }
5356
5357 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5358
5359 /*
5360 * From the Gunit register HAS:
5361 * The Gfx driver is expected to program this register and ensure
5362 * proper allocation within Gfx stolen memory. For example, this
5363 * register should be programmed such than the PCBR range does not
5364 * overlap with other ranges, such as the frame buffer, protected
5365 * memory, or any other relevant ranges.
5366 */
5367 pctx = i915_gem_object_create_stolen(dev, pctx_size);
5368 if (!pctx) {
5369 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
5370 return;
5371 }
5372
5373 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5374 I915_WRITE(VLV_PCBR, pctx_paddr);
5375
5376 out:
5377 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5378 dev_priv->vlv_pctx = pctx;
5379 }
5380
5381 static void valleyview_cleanup_pctx(struct drm_device *dev)
5382 {
5383 struct drm_i915_private *dev_priv = dev->dev_private;
5384
5385 if (WARN_ON(!dev_priv->vlv_pctx))
5386 return;
5387
5388 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
5389 dev_priv->vlv_pctx = NULL;
5390 }
5391
5392 static void valleyview_init_gt_powersave(struct drm_device *dev)
5393 {
5394 struct drm_i915_private *dev_priv = dev->dev_private;
5395 u32 val;
5396
5397 valleyview_setup_pctx(dev);
5398
5399 mutex_lock(&dev_priv->rps.hw_lock);
5400
5401 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5402 switch ((val >> 6) & 3) {
5403 case 0:
5404 case 1:
5405 dev_priv->mem_freq = 800;
5406 break;
5407 case 2:
5408 dev_priv->mem_freq = 1066;
5409 break;
5410 case 3:
5411 dev_priv->mem_freq = 1333;
5412 break;
5413 }
5414 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5415
5416 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5417 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5418 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5419 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5420 dev_priv->rps.max_freq);
5421
5422 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5423 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5424 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5425 dev_priv->rps.efficient_freq);
5426
5427 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5428 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
5429 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5430 dev_priv->rps.rp1_freq);
5431
5432 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5433 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5434 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5435 dev_priv->rps.min_freq);
5436
5437 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5438
5439 /* Preserve min/max settings in case of re-init */
5440 if (dev_priv->rps.max_freq_softlimit == 0)
5441 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5442
5443 if (dev_priv->rps.min_freq_softlimit == 0)
5444 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5445
5446 mutex_unlock(&dev_priv->rps.hw_lock);
5447 }
5448
5449 static void cherryview_init_gt_powersave(struct drm_device *dev)
5450 {
5451 struct drm_i915_private *dev_priv = dev->dev_private;
5452 u32 val;
5453
5454 cherryview_setup_pctx(dev);
5455
5456 mutex_lock(&dev_priv->rps.hw_lock);
5457
5458 mutex_lock(&dev_priv->sb_lock);
5459 val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
5460 mutex_unlock(&dev_priv->sb_lock);
5461
5462 switch ((val >> 2) & 0x7) {
5463 case 3:
5464 dev_priv->mem_freq = 2000;
5465 break;
5466 default:
5467 dev_priv->mem_freq = 1600;
5468 break;
5469 }
5470 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5471
5472 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5473 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5474 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5475 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5476 dev_priv->rps.max_freq);
5477
5478 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5479 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5480 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5481 dev_priv->rps.efficient_freq);
5482
5483 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5484 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
5485 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5486 dev_priv->rps.rp1_freq);
5487
5488 /* PUnit validated range is only [RPe, RP0] */
5489 dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
5490 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5491 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5492 dev_priv->rps.min_freq);
5493
5494 WARN_ONCE((dev_priv->rps.max_freq |
5495 dev_priv->rps.efficient_freq |
5496 dev_priv->rps.rp1_freq |
5497 dev_priv->rps.min_freq) & 1,
5498 "Odd GPU freq values\n");
5499
5500 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5501
5502 /* Preserve min/max settings in case of re-init */
5503 if (dev_priv->rps.max_freq_softlimit == 0)
5504 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5505
5506 if (dev_priv->rps.min_freq_softlimit == 0)
5507 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5508
5509 mutex_unlock(&dev_priv->rps.hw_lock);
5510 }
5511
5512 static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
5513 {
5514 valleyview_cleanup_pctx(dev);
5515 }
5516
5517 static void cherryview_enable_rps(struct drm_device *dev)
5518 {
5519 struct drm_i915_private *dev_priv = dev->dev_private;
5520 struct intel_engine_cs *ring;
5521 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
5522 int i;
5523
5524 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5525
5526 gtfifodbg = I915_READ(GTFIFODBG);
5527 if (gtfifodbg) {
5528 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5529 gtfifodbg);
5530 I915_WRITE(GTFIFODBG, gtfifodbg);
5531 }
5532
5533 cherryview_check_pctx(dev_priv);
5534
5535 /* 1a & 1b: Get forcewake during program sequence. Although the driver
5536 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5537 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5538
5539 /* Disable RC states. */
5540 I915_WRITE(GEN6_RC_CONTROL, 0);
5541
5542 /* 2a: Program RC6 thresholds.*/
5543 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5544 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5545 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5546
5547 for_each_ring(ring, dev_priv, i)
5548 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5549 I915_WRITE(GEN6_RC_SLEEP, 0);
5550
5551 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
5552 I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
5553
5554 /* allows RC6 residency counter to work */
5555 I915_WRITE(VLV_COUNTER_CONTROL,
5556 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
5557 VLV_MEDIA_RC6_COUNT_EN |
5558 VLV_RENDER_RC6_COUNT_EN));
5559
5560 /* For now we assume BIOS is allocating and populating the PCBR */
5561 pcbr = I915_READ(VLV_PCBR);
5562
5563 /* 3: Enable RC6 */
5564 if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
5565 (pcbr >> VLV_PCBR_ADDR_SHIFT))
5566 rc6_mode = GEN7_RC_CTL_TO_MODE;
5567
5568 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5569
5570 /* 4 Program defaults and thresholds for RPS*/
5571 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
5572 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5573 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5574 I915_WRITE(GEN6_RP_UP_EI, 66000);
5575 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5576
5577 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5578
5579 /* 5: Enable RPS */
5580 I915_WRITE(GEN6_RP_CONTROL,
5581 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5582 GEN6_RP_MEDIA_IS_GFX |
5583 GEN6_RP_ENABLE |
5584 GEN6_RP_UP_BUSY_AVG |
5585 GEN6_RP_DOWN_IDLE_AVG);
5586
5587 /* Setting Fixed Bias */
5588 val = VLV_OVERRIDE_EN |
5589 VLV_SOC_TDP_EN |
5590 CHV_BIAS_CPU_50_SOC_50;
5591 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5592
5593 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5594
5595 /* RPS code assumes GPLL is used */
5596 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5597
5598 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
5599 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5600
5601 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5602 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5603 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
5604 dev_priv->rps.cur_freq);
5605
5606 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5607 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5608 dev_priv->rps.efficient_freq);
5609
5610 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5611
5612 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5613 }
5614
5615 static void valleyview_enable_rps(struct drm_device *dev)
5616 {
5617 struct drm_i915_private *dev_priv = dev->dev_private;
5618 struct intel_engine_cs *ring;
5619 u32 gtfifodbg, val, rc6_mode = 0;
5620 int i;
5621
5622 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5623
5624 valleyview_check_pctx(dev_priv);
5625
5626 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
5627 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5628 gtfifodbg);
5629 I915_WRITE(GTFIFODBG, gtfifodbg);
5630 }
5631
5632 /* If VLV, Forcewake all wells, else re-direct to regular path */
5633 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5634
5635 /* Disable RC states. */
5636 I915_WRITE(GEN6_RC_CONTROL, 0);
5637
5638 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
5639 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5640 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5641 I915_WRITE(GEN6_RP_UP_EI, 66000);
5642 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5643
5644 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5645
5646 I915_WRITE(GEN6_RP_CONTROL,
5647 GEN6_RP_MEDIA_TURBO |
5648 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5649 GEN6_RP_MEDIA_IS_GFX |
5650 GEN6_RP_ENABLE |
5651 GEN6_RP_UP_BUSY_AVG |
5652 GEN6_RP_DOWN_IDLE_CONT);
5653
5654 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
5655 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5656 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5657
5658 for_each_ring(ring, dev_priv, i)
5659 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5660
5661 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
5662
5663 /* allows RC6 residency counter to work */
5664 I915_WRITE(VLV_COUNTER_CONTROL,
5665 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
5666 VLV_RENDER_RC0_COUNT_EN |
5667 VLV_MEDIA_RC6_COUNT_EN |
5668 VLV_RENDER_RC6_COUNT_EN));
5669
5670 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
5671 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
5672
5673 intel_print_rc6_info(dev, rc6_mode);
5674
5675 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5676
5677 /* Setting Fixed Bias */
5678 val = VLV_OVERRIDE_EN |
5679 VLV_SOC_TDP_EN |
5680 VLV_BIAS_CPU_125_SOC_875;
5681 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5682
5683 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5684
5685 /* RPS code assumes GPLL is used */
5686 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5687
5688 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
5689 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5690
5691 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5692 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5693 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
5694 dev_priv->rps.cur_freq);
5695
5696 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5697 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5698 dev_priv->rps.efficient_freq);
5699
5700 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5701
5702 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5703 }
5704
5705 static unsigned long intel_pxfreq(u32 vidfreq)
5706 {
5707 unsigned long freq;
5708 int div = (vidfreq & 0x3f0000) >> 16;
5709 int post = (vidfreq & 0x3000) >> 12;
5710 int pre = (vidfreq & 0x7);
5711
5712 if (!pre)
5713 return 0;
5714
5715 freq = ((div * 133333) / ((1<<post) * pre));
5716
5717 return freq;
5718 }
5719
5720 static const struct cparams {
5721 u16 i;
5722 u16 t;
5723 u16 m;
5724 u16 c;
5725 } cparams[] = {
5726 { 1, 1333, 301, 28664 },
5727 { 1, 1066, 294, 24460 },
5728 { 1, 800, 294, 25192 },
5729 { 0, 1333, 276, 27605 },
5730 { 0, 1066, 276, 27605 },
5731 { 0, 800, 231, 23784 },
5732 };
5733
5734 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
5735 {
5736 u64 total_count, diff, ret;
5737 u32 count1, count2, count3, m = 0, c = 0;
5738 unsigned long now = jiffies_to_msecs(jiffies), diff1;
5739 int i;
5740
5741 assert_spin_locked(&mchdev_lock);
5742
5743 diff1 = now - dev_priv->ips.last_time1;
5744
5745 /* Prevent division-by-zero if we are asking too fast.
5746 * Also, we don't get interesting results if we are polling
5747 * faster than once in 10ms, so just return the saved value
5748 * in such cases.
5749 */
5750 if (diff1 <= 10)
5751 return dev_priv->ips.chipset_power;
5752
5753 count1 = I915_READ(DMIEC);
5754 count2 = I915_READ(DDREC);
5755 count3 = I915_READ(CSIEC);
5756
5757 total_count = count1 + count2 + count3;
5758
5759 /* FIXME: handle per-counter overflow */
5760 if (total_count < dev_priv->ips.last_count1) {
5761 diff = ~0UL - dev_priv->ips.last_count1;
5762 diff += total_count;
5763 } else {
5764 diff = total_count - dev_priv->ips.last_count1;
5765 }
5766
5767 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
5768 if (cparams[i].i == dev_priv->ips.c_m &&
5769 cparams[i].t == dev_priv->ips.r_t) {
5770 m = cparams[i].m;
5771 c = cparams[i].c;
5772 break;
5773 }
5774 }
5775
5776 diff = div_u64(diff, diff1);
5777 ret = ((m * diff) + c);
5778 ret = div_u64(ret, 10);
5779
5780 dev_priv->ips.last_count1 = total_count;
5781 dev_priv->ips.last_time1 = now;
5782
5783 dev_priv->ips.chipset_power = ret;
5784
5785 return ret;
5786 }
5787
5788 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
5789 {
5790 struct drm_device *dev = dev_priv->dev;
5791 unsigned long val;
5792
5793 if (INTEL_INFO(dev)->gen != 5)
5794 return 0;
5795
5796 spin_lock_irq(&mchdev_lock);
5797
5798 val = __i915_chipset_val(dev_priv);
5799
5800 spin_unlock_irq(&mchdev_lock);
5801
5802 return val;
5803 }
5804
5805 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
5806 {
5807 unsigned long m, x, b;
5808 u32 tsfs;
5809
5810 tsfs = I915_READ(TSFS);
5811
5812 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
5813 x = I915_READ8(TR1);
5814
5815 b = tsfs & TSFS_INTR_MASK;
5816
5817 return ((m * x) / 127) - b;
5818 }
5819
5820 static int _pxvid_to_vd(u8 pxvid)
5821 {
5822 if (pxvid == 0)
5823 return 0;
5824
5825 if (pxvid >= 8 && pxvid < 31)
5826 pxvid = 31;
5827
5828 return (pxvid + 2) * 125;
5829 }
5830
5831 static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
5832 {
5833 struct drm_device *dev = dev_priv->dev;
5834 const int vd = _pxvid_to_vd(pxvid);
5835 const int vm = vd - 1125;
5836
5837 if (INTEL_INFO(dev)->is_mobile)
5838 return vm > 0 ? vm : 0;
5839
5840 return vd;
5841 }
5842
5843 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
5844 {
5845 u64 now, diff, diffms;
5846 u32 count;
5847
5848 assert_spin_locked(&mchdev_lock);
5849
5850 now = ktime_get_raw_ns();
5851 diffms = now - dev_priv->ips.last_time2;
5852 do_div(diffms, NSEC_PER_MSEC);
5853
5854 /* Don't divide by 0 */
5855 if (!diffms)
5856 return;
5857
5858 count = I915_READ(GFXEC);
5859
5860 if (count < dev_priv->ips.last_count2) {
5861 diff = ~0UL - dev_priv->ips.last_count2;
5862 diff += count;
5863 } else {
5864 diff = count - dev_priv->ips.last_count2;
5865 }
5866
5867 dev_priv->ips.last_count2 = count;
5868 dev_priv->ips.last_time2 = now;
5869
5870 /* More magic constants... */
5871 diff = diff * 1181;
5872 diff = div_u64(diff, diffms * 10);
5873 dev_priv->ips.gfx_power = diff;
5874 }
5875
5876 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
5877 {
5878 struct drm_device *dev = dev_priv->dev;
5879
5880 if (INTEL_INFO(dev)->gen != 5)
5881 return;
5882
5883 spin_lock_irq(&mchdev_lock);
5884
5885 __i915_update_gfx_val(dev_priv);
5886
5887 spin_unlock_irq(&mchdev_lock);
5888 }
5889
5890 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
5891 {
5892 unsigned long t, corr, state1, corr2, state2;
5893 u32 pxvid, ext_v;
5894
5895 assert_spin_locked(&mchdev_lock);
5896
5897 pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
5898 pxvid = (pxvid >> 24) & 0x7f;
5899 ext_v = pvid_to_extvid(dev_priv, pxvid);
5900
5901 state1 = ext_v;
5902
5903 t = i915_mch_val(dev_priv);
5904
5905 /* Revel in the empirically derived constants */
5906
5907 /* Correction factor in 1/100000 units */
5908 if (t > 80)
5909 corr = ((t * 2349) + 135940);
5910 else if (t >= 50)
5911 corr = ((t * 964) + 29317);
5912 else /* < 50 */
5913 corr = ((t * 301) + 1004);
5914
5915 corr = corr * ((150142 * state1) / 10000 - 78642);
5916 corr /= 100000;
5917 corr2 = (corr * dev_priv->ips.corr);
5918
5919 state2 = (corr2 * state1) / 10000;
5920 state2 /= 100; /* convert to mW */
5921
5922 __i915_update_gfx_val(dev_priv);
5923
5924 return dev_priv->ips.gfx_power + state2;
5925 }
5926
5927 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
5928 {
5929 struct drm_device *dev = dev_priv->dev;
5930 unsigned long val;
5931
5932 if (INTEL_INFO(dev)->gen != 5)
5933 return 0;
5934
5935 spin_lock_irq(&mchdev_lock);
5936
5937 val = __i915_gfx_val(dev_priv);
5938
5939 spin_unlock_irq(&mchdev_lock);
5940
5941 return val;
5942 }
5943
5944 /**
5945 * i915_read_mch_val - return value for IPS use
5946 *
5947 * Calculate and return a value for the IPS driver to use when deciding whether
5948 * we have thermal and power headroom to increase CPU or GPU power budget.
5949 */
5950 unsigned long i915_read_mch_val(void)
5951 {
5952 struct drm_i915_private *dev_priv;
5953 unsigned long chipset_val, graphics_val, ret = 0;
5954
5955 spin_lock_irq(&mchdev_lock);
5956 if (!i915_mch_dev)
5957 goto out_unlock;
5958 dev_priv = i915_mch_dev;
5959
5960 chipset_val = __i915_chipset_val(dev_priv);
5961 graphics_val = __i915_gfx_val(dev_priv);
5962
5963 ret = chipset_val + graphics_val;
5964
5965 out_unlock:
5966 spin_unlock_irq(&mchdev_lock);
5967
5968 return ret;
5969 }
5970 EXPORT_SYMBOL_GPL(i915_read_mch_val);
5971
5972 /**
5973 * i915_gpu_raise - raise GPU frequency limit
5974 *
5975 * Raise the limit; IPS indicates we have thermal headroom.
5976 */
5977 bool i915_gpu_raise(void)
5978 {
5979 struct drm_i915_private *dev_priv;
5980 bool ret = true;
5981
5982 spin_lock_irq(&mchdev_lock);
5983 if (!i915_mch_dev) {
5984 ret = false;
5985 goto out_unlock;
5986 }
5987 dev_priv = i915_mch_dev;
5988
5989 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
5990 dev_priv->ips.max_delay--;
5991
5992 out_unlock:
5993 spin_unlock_irq(&mchdev_lock);
5994
5995 return ret;
5996 }
5997 EXPORT_SYMBOL_GPL(i915_gpu_raise);
5998
5999 /**
6000 * i915_gpu_lower - lower GPU frequency limit
6001 *
6002 * IPS indicates we're close to a thermal limit, so throttle back the GPU
6003 * frequency maximum.
6004 */
6005 bool i915_gpu_lower(void)
6006 {
6007 struct drm_i915_private *dev_priv;
6008 bool ret = true;
6009
6010 spin_lock_irq(&mchdev_lock);
6011 if (!i915_mch_dev) {
6012 ret = false;
6013 goto out_unlock;
6014 }
6015 dev_priv = i915_mch_dev;
6016
6017 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
6018 dev_priv->ips.max_delay++;
6019
6020 out_unlock:
6021 spin_unlock_irq(&mchdev_lock);
6022
6023 return ret;
6024 }
6025 EXPORT_SYMBOL_GPL(i915_gpu_lower);
6026
6027 /**
6028 * i915_gpu_busy - indicate GPU business to IPS
6029 *
6030 * Tell the IPS driver whether or not the GPU is busy.
6031 */
6032 bool i915_gpu_busy(void)
6033 {
6034 struct drm_i915_private *dev_priv;
6035 struct intel_engine_cs *ring;
6036 bool ret = false;
6037 int i;
6038
6039 spin_lock_irq(&mchdev_lock);
6040 if (!i915_mch_dev)
6041 goto out_unlock;
6042 dev_priv = i915_mch_dev;
6043
6044 for_each_ring(ring, dev_priv, i)
6045 ret |= !list_empty(&ring->request_list);
6046
6047 out_unlock:
6048 spin_unlock_irq(&mchdev_lock);
6049
6050 return ret;
6051 }
6052 EXPORT_SYMBOL_GPL(i915_gpu_busy);
6053
6054 /**
6055 * i915_gpu_turbo_disable - disable graphics turbo
6056 *
6057 * Disable graphics turbo by resetting the max frequency and setting the
6058 * current frequency to the default.
6059 */
6060 bool i915_gpu_turbo_disable(void)
6061 {
6062 struct drm_i915_private *dev_priv;
6063 bool ret = true;
6064
6065 spin_lock_irq(&mchdev_lock);
6066 if (!i915_mch_dev) {
6067 ret = false;
6068 goto out_unlock;
6069 }
6070 dev_priv = i915_mch_dev;
6071
6072 dev_priv->ips.max_delay = dev_priv->ips.fstart;
6073
6074 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
6075 ret = false;
6076
6077 out_unlock:
6078 spin_unlock_irq(&mchdev_lock);
6079
6080 return ret;
6081 }
6082 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6083
6084 /**
6085 * Tells the intel_ips driver that the i915 driver is now loaded, if
6086 * IPS got loaded first.
6087 *
6088 * This awkward dance is so that neither module has to depend on the
6089 * other in order for IPS to do the appropriate communication of
6090 * GPU turbo limits to i915.
6091 */
6092 static void
6093 ips_ping_for_i915_load(void)
6094 {
6095 void (*link)(void);
6096
6097 link = symbol_get(ips_link_to_i915_driver);
6098 if (link) {
6099 link();
6100 symbol_put(ips_link_to_i915_driver);
6101 }
6102 }
6103
6104 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6105 {
6106 /* We only register the i915 ips part with intel-ips once everything is
6107 * set up, to avoid intel-ips sneaking in and reading bogus values. */
6108 spin_lock_irq(&mchdev_lock);
6109 i915_mch_dev = dev_priv;
6110 spin_unlock_irq(&mchdev_lock);
6111
6112 ips_ping_for_i915_load();
6113 }
6114
6115 void intel_gpu_ips_teardown(void)
6116 {
6117 spin_lock_irq(&mchdev_lock);
6118 i915_mch_dev = NULL;
6119 spin_unlock_irq(&mchdev_lock);
6120 }
6121
6122 static void intel_init_emon(struct drm_device *dev)
6123 {
6124 struct drm_i915_private *dev_priv = dev->dev_private;
6125 u32 lcfuse;
6126 u8 pxw[16];
6127 int i;
6128
6129 /* Disable to program */
6130 I915_WRITE(ECR, 0);
6131 POSTING_READ(ECR);
6132
6133 /* Program energy weights for various events */
6134 I915_WRITE(SDEW, 0x15040d00);
6135 I915_WRITE(CSIEW0, 0x007f0000);
6136 I915_WRITE(CSIEW1, 0x1e220004);
6137 I915_WRITE(CSIEW2, 0x04000004);
6138
6139 for (i = 0; i < 5; i++)
6140 I915_WRITE(PEW(i), 0);
6141 for (i = 0; i < 3; i++)
6142 I915_WRITE(DEW(i), 0);
6143
6144 /* Program P-state weights to account for frequency power adjustment */
6145 for (i = 0; i < 16; i++) {
6146 u32 pxvidfreq = I915_READ(PXVFREQ(i));
6147 unsigned long freq = intel_pxfreq(pxvidfreq);
6148 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6149 PXVFREQ_PX_SHIFT;
6150 unsigned long val;
6151
6152 val = vid * vid;
6153 val *= (freq / 1000);
6154 val *= 255;
6155 val /= (127*127*900);
6156 if (val > 0xff)
6157 DRM_ERROR("bad pxval: %ld\n", val);
6158 pxw[i] = val;
6159 }
6160 /* Render standby states get 0 weight */
6161 pxw[14] = 0;
6162 pxw[15] = 0;
6163
6164 for (i = 0; i < 4; i++) {
6165 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6166 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
6167 I915_WRITE(PXW(i), val);
6168 }
6169
6170 /* Adjust magic regs to magic values (more experimental results) */
6171 I915_WRITE(OGW0, 0);
6172 I915_WRITE(OGW1, 0);
6173 I915_WRITE(EG0, 0x00007f00);
6174 I915_WRITE(EG1, 0x0000000e);
6175 I915_WRITE(EG2, 0x000e0000);
6176 I915_WRITE(EG3, 0x68000300);
6177 I915_WRITE(EG4, 0x42000000);
6178 I915_WRITE(EG5, 0x00140031);
6179 I915_WRITE(EG6, 0);
6180 I915_WRITE(EG7, 0);
6181
6182 for (i = 0; i < 8; i++)
6183 I915_WRITE(PXWL(i), 0);
6184
6185 /* Enable PMON + select events */
6186 I915_WRITE(ECR, 0x80000019);
6187
6188 lcfuse = I915_READ(LCFUSE02);
6189
6190 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
6191 }
6192
6193 void intel_init_gt_powersave(struct drm_device *dev)
6194 {
6195 i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
6196
6197 if (IS_CHERRYVIEW(dev))
6198 cherryview_init_gt_powersave(dev);
6199 else if (IS_VALLEYVIEW(dev))
6200 valleyview_init_gt_powersave(dev);
6201 }
6202
6203 void intel_cleanup_gt_powersave(struct drm_device *dev)
6204 {
6205 if (IS_CHERRYVIEW(dev))
6206 return;
6207 else if (IS_VALLEYVIEW(dev))
6208 valleyview_cleanup_gt_powersave(dev);
6209 }
6210
6211 static void gen6_suspend_rps(struct drm_device *dev)
6212 {
6213 struct drm_i915_private *dev_priv = dev->dev_private;
6214
6215 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
6216
6217 gen6_disable_rps_interrupts(dev);
6218 }
6219
6220 /**
6221 * intel_suspend_gt_powersave - suspend PM work and helper threads
6222 * @dev: drm device
6223 *
6224 * We don't want to disable RC6 or other features here, we just want
6225 * to make sure any work we've queued has finished and won't bother
6226 * us while we're suspended.
6227 */
6228 void intel_suspend_gt_powersave(struct drm_device *dev)
6229 {
6230 struct drm_i915_private *dev_priv = dev->dev_private;
6231
6232 if (INTEL_INFO(dev)->gen < 6)
6233 return;
6234
6235 gen6_suspend_rps(dev);
6236
6237 /* Force GPU to min freq during suspend */
6238 gen6_rps_idle(dev_priv);
6239 }
6240
6241 void intel_disable_gt_powersave(struct drm_device *dev)
6242 {
6243 struct drm_i915_private *dev_priv = dev->dev_private;
6244
6245 if (IS_IRONLAKE_M(dev)) {
6246 ironlake_disable_drps(dev);
6247 } else if (INTEL_INFO(dev)->gen >= 6) {
6248 intel_suspend_gt_powersave(dev);
6249
6250 mutex_lock(&dev_priv->rps.hw_lock);
6251 if (INTEL_INFO(dev)->gen >= 9)
6252 gen9_disable_rps(dev);
6253 else if (IS_CHERRYVIEW(dev))
6254 cherryview_disable_rps(dev);
6255 else if (IS_VALLEYVIEW(dev))
6256 valleyview_disable_rps(dev);
6257 else
6258 gen6_disable_rps(dev);
6259
6260 dev_priv->rps.enabled = false;
6261 mutex_unlock(&dev_priv->rps.hw_lock);
6262 }
6263 }
6264
6265 static void intel_gen6_powersave_work(struct work_struct *work)
6266 {
6267 struct drm_i915_private *dev_priv =
6268 container_of(work, struct drm_i915_private,
6269 rps.delayed_resume_work.work);
6270 struct drm_device *dev = dev_priv->dev;
6271
6272 mutex_lock(&dev_priv->rps.hw_lock);
6273
6274 gen6_reset_rps_interrupts(dev);
6275
6276 if (IS_CHERRYVIEW(dev)) {
6277 cherryview_enable_rps(dev);
6278 } else if (IS_VALLEYVIEW(dev)) {
6279 valleyview_enable_rps(dev);
6280 } else if (INTEL_INFO(dev)->gen >= 9) {
6281 gen9_enable_rc6(dev);
6282 gen9_enable_rps(dev);
6283 if (IS_SKYLAKE(dev))
6284 __gen6_update_ring_freq(dev);
6285 } else if (IS_BROADWELL(dev)) {
6286 gen8_enable_rps(dev);
6287 __gen6_update_ring_freq(dev);
6288 } else {
6289 gen6_enable_rps(dev);
6290 __gen6_update_ring_freq(dev);
6291 }
6292
6293 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6294 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6295
6296 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6297 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6298
6299 dev_priv->rps.enabled = true;
6300
6301 gen6_enable_rps_interrupts(dev);
6302
6303 mutex_unlock(&dev_priv->rps.hw_lock);
6304
6305 intel_runtime_pm_put(dev_priv);
6306 }
6307
6308 void intel_enable_gt_powersave(struct drm_device *dev)
6309 {
6310 struct drm_i915_private *dev_priv = dev->dev_private;
6311
6312 /* Powersaving is controlled by the host when inside a VM */
6313 if (intel_vgpu_active(dev))
6314 return;
6315
6316 if (IS_IRONLAKE_M(dev)) {
6317 mutex_lock(&dev->struct_mutex);
6318 ironlake_enable_drps(dev);
6319 intel_init_emon(dev);
6320 mutex_unlock(&dev->struct_mutex);
6321 } else if (INTEL_INFO(dev)->gen >= 6) {
6322 /*
6323 * PCU communication is slow and this doesn't need to be
6324 * done at any specific time, so do this out of our fast path
6325 * to make resume and init faster.
6326 *
6327 * We depend on the HW RC6 power context save/restore
6328 * mechanism when entering D3 through runtime PM suspend. So
6329 * disable RPM until RPS/RC6 is properly setup. We can only
6330 * get here via the driver load/system resume/runtime resume
6331 * paths, so the _noresume version is enough (and in case of
6332 * runtime resume it's necessary).
6333 */
6334 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
6335 round_jiffies_up_relative(HZ)))
6336 intel_runtime_pm_get_noresume(dev_priv);
6337 }
6338 }
6339
6340 void intel_reset_gt_powersave(struct drm_device *dev)
6341 {
6342 struct drm_i915_private *dev_priv = dev->dev_private;
6343
6344 if (INTEL_INFO(dev)->gen < 6)
6345 return;
6346
6347 gen6_suspend_rps(dev);
6348 dev_priv->rps.enabled = false;
6349 }
6350
6351 static void ibx_init_clock_gating(struct drm_device *dev)
6352 {
6353 struct drm_i915_private *dev_priv = dev->dev_private;
6354
6355 /*
6356 * On Ibex Peak and Cougar Point, we need to disable clock
6357 * gating for the panel power sequencer or it will fail to
6358 * start up when no ports are active.
6359 */
6360 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6361 }
6362
6363 static void g4x_disable_trickle_feed(struct drm_device *dev)
6364 {
6365 struct drm_i915_private *dev_priv = dev->dev_private;
6366 enum pipe pipe;
6367
6368 for_each_pipe(dev_priv, pipe) {
6369 I915_WRITE(DSPCNTR(pipe),
6370 I915_READ(DSPCNTR(pipe)) |
6371 DISPPLANE_TRICKLE_FEED_DISABLE);
6372
6373 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6374 POSTING_READ(DSPSURF(pipe));
6375 }
6376 }
6377
6378 static void ilk_init_lp_watermarks(struct drm_device *dev)
6379 {
6380 struct drm_i915_private *dev_priv = dev->dev_private;
6381
6382 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6383 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6384 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6385
6386 /*
6387 * Don't touch WM1S_LP_EN here.
6388 * Doing so could cause underruns.
6389 */
6390 }
6391
6392 static void ironlake_init_clock_gating(struct drm_device *dev)
6393 {
6394 struct drm_i915_private *dev_priv = dev->dev_private;
6395 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6396
6397 /*
6398 * Required for FBC
6399 * WaFbcDisableDpfcClockGating:ilk
6400 */
6401 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6402 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6403 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6404
6405 I915_WRITE(PCH_3DCGDIS0,
6406 MARIUNIT_CLOCK_GATE_DISABLE |
6407 SVSMUNIT_CLOCK_GATE_DISABLE);
6408 I915_WRITE(PCH_3DCGDIS1,
6409 VFMUNIT_CLOCK_GATE_DISABLE);
6410
6411 /*
6412 * According to the spec the following bits should be set in
6413 * order to enable memory self-refresh
6414 * The bit 22/21 of 0x42004
6415 * The bit 5 of 0x42020
6416 * The bit 15 of 0x45000
6417 */
6418 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6419 (I915_READ(ILK_DISPLAY_CHICKEN2) |
6420 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
6421 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6422 I915_WRITE(DISP_ARB_CTL,
6423 (I915_READ(DISP_ARB_CTL) |
6424 DISP_FBC_WM_DIS));
6425
6426 ilk_init_lp_watermarks(dev);
6427
6428 /*
6429 * Based on the document from hardware guys the following bits
6430 * should be set unconditionally in order to enable FBC.
6431 * The bit 22 of 0x42000
6432 * The bit 22 of 0x42004
6433 * The bit 7,8,9 of 0x42020.
6434 */
6435 if (IS_IRONLAKE_M(dev)) {
6436 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6437 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6438 I915_READ(ILK_DISPLAY_CHICKEN1) |
6439 ILK_FBCQ_DIS);
6440 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6441 I915_READ(ILK_DISPLAY_CHICKEN2) |
6442 ILK_DPARB_GATE);
6443 }
6444
6445 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6446
6447 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6448 I915_READ(ILK_DISPLAY_CHICKEN2) |
6449 ILK_ELPIN_409_SELECT);
6450 I915_WRITE(_3D_CHICKEN2,
6451 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6452 _3D_CHICKEN2_WM_READ_PIPELINED);
6453
6454 /* WaDisableRenderCachePipelinedFlush:ilk */
6455 I915_WRITE(CACHE_MODE_0,
6456 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6457
6458 /* WaDisable_RenderCache_OperationalFlush:ilk */
6459 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6460
6461 g4x_disable_trickle_feed(dev);
6462
6463 ibx_init_clock_gating(dev);
6464 }
6465
6466 static void cpt_init_clock_gating(struct drm_device *dev)
6467 {
6468 struct drm_i915_private *dev_priv = dev->dev_private;
6469 int pipe;
6470 uint32_t val;
6471
6472 /*
6473 * On Ibex Peak and Cougar Point, we need to disable clock
6474 * gating for the panel power sequencer or it will fail to
6475 * start up when no ports are active.
6476 */
6477 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6478 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6479 PCH_CPUNIT_CLOCK_GATE_DISABLE);
6480 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6481 DPLS_EDP_PPS_FIX_DIS);
6482 /* The below fixes the weird display corruption, a few pixels shifted
6483 * downward, on (only) LVDS of some HP laptops with IVY.
6484 */
6485 for_each_pipe(dev_priv, pipe) {
6486 val = I915_READ(TRANS_CHICKEN2(pipe));
6487 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6488 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6489 if (dev_priv->vbt.fdi_rx_polarity_inverted)
6490 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6491 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6492 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6493 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
6494 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6495 }
6496 /* WADP0ClockGatingDisable */
6497 for_each_pipe(dev_priv, pipe) {
6498 I915_WRITE(TRANS_CHICKEN1(pipe),
6499 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6500 }
6501 }
6502
6503 static void gen6_check_mch_setup(struct drm_device *dev)
6504 {
6505 struct drm_i915_private *dev_priv = dev->dev_private;
6506 uint32_t tmp;
6507
6508 tmp = I915_READ(MCH_SSKPD);
6509 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6510 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6511 tmp);
6512 }
6513
6514 static void gen6_init_clock_gating(struct drm_device *dev)
6515 {
6516 struct drm_i915_private *dev_priv = dev->dev_private;
6517 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6518
6519 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6520
6521 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6522 I915_READ(ILK_DISPLAY_CHICKEN2) |
6523 ILK_ELPIN_409_SELECT);
6524
6525 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
6526 I915_WRITE(_3D_CHICKEN,
6527 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
6528
6529 /* WaDisable_RenderCache_OperationalFlush:snb */
6530 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6531
6532 /*
6533 * BSpec recoomends 8x4 when MSAA is used,
6534 * however in practice 16x4 seems fastest.
6535 *
6536 * Note that PS/WM thread counts depend on the WIZ hashing
6537 * disable bit, which we don't touch here, but it's good
6538 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6539 */
6540 I915_WRITE(GEN6_GT_MODE,
6541 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6542
6543 ilk_init_lp_watermarks(dev);
6544
6545 I915_WRITE(CACHE_MODE_0,
6546 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6547
6548 I915_WRITE(GEN6_UCGCTL1,
6549 I915_READ(GEN6_UCGCTL1) |
6550 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
6551 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6552
6553 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
6554 * gating disable must be set. Failure to set it results in
6555 * flickering pixels due to Z write ordering failures after
6556 * some amount of runtime in the Mesa "fire" demo, and Unigine
6557 * Sanctuary and Tropics, and apparently anything else with
6558 * alpha test or pixel discard.
6559 *
6560 * According to the spec, bit 11 (RCCUNIT) must also be set,
6561 * but we didn't debug actual testcases to find it out.
6562 *
6563 * WaDisableRCCUnitClockGating:snb
6564 * WaDisableRCPBUnitClockGating:snb
6565 */
6566 I915_WRITE(GEN6_UCGCTL2,
6567 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
6568 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
6569
6570 /* WaStripsFansDisableFastClipPerformanceFix:snb */
6571 I915_WRITE(_3D_CHICKEN3,
6572 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6573
6574 /*
6575 * Bspec says:
6576 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
6577 * 3DSTATE_SF number of SF output attributes is more than 16."
6578 */
6579 I915_WRITE(_3D_CHICKEN3,
6580 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
6581
6582 /*
6583 * According to the spec the following bits should be
6584 * set in order to enable memory self-refresh and fbc:
6585 * The bit21 and bit22 of 0x42000
6586 * The bit21 and bit22 of 0x42004
6587 * The bit5 and bit7 of 0x42020
6588 * The bit14 of 0x70180
6589 * The bit14 of 0x71180
6590 *
6591 * WaFbcAsynchFlipDisableFbcQueue:snb
6592 */
6593 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6594 I915_READ(ILK_DISPLAY_CHICKEN1) |
6595 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6596 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6597 I915_READ(ILK_DISPLAY_CHICKEN2) |
6598 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
6599 I915_WRITE(ILK_DSPCLK_GATE_D,
6600 I915_READ(ILK_DSPCLK_GATE_D) |
6601 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
6602 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6603
6604 g4x_disable_trickle_feed(dev);
6605
6606 cpt_init_clock_gating(dev);
6607
6608 gen6_check_mch_setup(dev);
6609 }
6610
6611 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
6612 {
6613 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
6614
6615 /*
6616 * WaVSThreadDispatchOverride:ivb,vlv
6617 *
6618 * This actually overrides the dispatch
6619 * mode for all thread types.
6620 */
6621 reg &= ~GEN7_FF_SCHED_MASK;
6622 reg |= GEN7_FF_TS_SCHED_HW;
6623 reg |= GEN7_FF_VS_SCHED_HW;
6624 reg |= GEN7_FF_DS_SCHED_HW;
6625
6626 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
6627 }
6628
6629 static void lpt_init_clock_gating(struct drm_device *dev)
6630 {
6631 struct drm_i915_private *dev_priv = dev->dev_private;
6632
6633 /*
6634 * TODO: this bit should only be enabled when really needed, then
6635 * disabled when not needed anymore in order to save power.
6636 */
6637 if (HAS_PCH_LPT_LP(dev))
6638 I915_WRITE(SOUTH_DSPCLK_GATE_D,
6639 I915_READ(SOUTH_DSPCLK_GATE_D) |
6640 PCH_LP_PARTITION_LEVEL_DISABLE);
6641
6642 /* WADPOClockGatingDisable:hsw */
6643 I915_WRITE(_TRANSA_CHICKEN1,
6644 I915_READ(_TRANSA_CHICKEN1) |
6645 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6646 }
6647
6648 static void lpt_suspend_hw(struct drm_device *dev)
6649 {
6650 struct drm_i915_private *dev_priv = dev->dev_private;
6651
6652 if (HAS_PCH_LPT_LP(dev)) {
6653 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
6654
6655 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6656 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6657 }
6658 }
6659
6660 static void broadwell_init_clock_gating(struct drm_device *dev)
6661 {
6662 struct drm_i915_private *dev_priv = dev->dev_private;
6663 enum pipe pipe;
6664 uint32_t misccpctl;
6665
6666 ilk_init_lp_watermarks(dev);
6667
6668 /* WaSwitchSolVfFArbitrationPriority:bdw */
6669 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6670
6671 /* WaPsrDPAMaskVBlankInSRD:bdw */
6672 I915_WRITE(CHICKEN_PAR1_1,
6673 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
6674
6675 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
6676 for_each_pipe(dev_priv, pipe) {
6677 I915_WRITE(CHICKEN_PIPESL_1(pipe),
6678 I915_READ(CHICKEN_PIPESL_1(pipe)) |
6679 BDW_DPRS_MASK_VBLANK_SRD);
6680 }
6681
6682 /* WaVSRefCountFullforceMissDisable:bdw */
6683 /* WaDSRefCountFullforceMissDisable:bdw */
6684 I915_WRITE(GEN7_FF_THREAD_MODE,
6685 I915_READ(GEN7_FF_THREAD_MODE) &
6686 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
6687
6688 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6689 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
6690
6691 /* WaDisableSDEUnitClockGating:bdw */
6692 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6693 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6694
6695 /*
6696 * WaProgramL3SqcReg1Default:bdw
6697 * WaTempDisableDOPClkGating:bdw
6698 */
6699 misccpctl = I915_READ(GEN7_MISCCPCTL);
6700 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
6701 I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
6702 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
6703
6704 /*
6705 * WaGttCachingOffByDefault:bdw
6706 * GTT cache may not work with big pages, so if those
6707 * are ever enabled GTT cache may need to be disabled.
6708 */
6709 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
6710
6711 lpt_init_clock_gating(dev);
6712 }
6713
6714 static void haswell_init_clock_gating(struct drm_device *dev)
6715 {
6716 struct drm_i915_private *dev_priv = dev->dev_private;
6717
6718 ilk_init_lp_watermarks(dev);
6719
6720 /* L3 caching of data atomics doesn't work -- disable it. */
6721 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
6722 I915_WRITE(HSW_ROW_CHICKEN3,
6723 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
6724
6725 /* This is required by WaCatErrorRejectionIssue:hsw */
6726 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6727 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6728 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6729
6730 /* WaVSRefCountFullforceMissDisable:hsw */
6731 I915_WRITE(GEN7_FF_THREAD_MODE,
6732 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
6733
6734 /* WaDisable_RenderCache_OperationalFlush:hsw */
6735 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6736
6737 /* enable HiZ Raw Stall Optimization */
6738 I915_WRITE(CACHE_MODE_0_GEN7,
6739 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6740
6741 /* WaDisable4x2SubspanOptimization:hsw */
6742 I915_WRITE(CACHE_MODE_1,
6743 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6744
6745 /*
6746 * BSpec recommends 8x4 when MSAA is used,
6747 * however in practice 16x4 seems fastest.
6748 *
6749 * Note that PS/WM thread counts depend on the WIZ hashing
6750 * disable bit, which we don't touch here, but it's good
6751 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6752 */
6753 I915_WRITE(GEN7_GT_MODE,
6754 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6755
6756 /* WaSampleCChickenBitEnable:hsw */
6757 I915_WRITE(HALF_SLICE_CHICKEN3,
6758 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
6759
6760 /* WaSwitchSolVfFArbitrationPriority:hsw */
6761 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6762
6763 /* WaRsPkgCStateDisplayPMReq:hsw */
6764 I915_WRITE(CHICKEN_PAR1_1,
6765 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
6766
6767 lpt_init_clock_gating(dev);
6768 }
6769
6770 static void ivybridge_init_clock_gating(struct drm_device *dev)
6771 {
6772 struct drm_i915_private *dev_priv = dev->dev_private;
6773 uint32_t snpcr;
6774
6775 ilk_init_lp_watermarks(dev);
6776
6777 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6778
6779 /* WaDisableEarlyCull:ivb */
6780 I915_WRITE(_3D_CHICKEN3,
6781 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6782
6783 /* WaDisableBackToBackFlipFix:ivb */
6784 I915_WRITE(IVB_CHICKEN3,
6785 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6786 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6787
6788 /* WaDisablePSDDualDispatchEnable:ivb */
6789 if (IS_IVB_GT1(dev))
6790 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6791 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
6792
6793 /* WaDisable_RenderCache_OperationalFlush:ivb */
6794 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6795
6796 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6797 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
6798 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
6799
6800 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6801 I915_WRITE(GEN7_L3CNTLREG1,
6802 GEN7_WA_FOR_GEN7_L3_CONTROL);
6803 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
6804 GEN7_WA_L3_CHICKEN_MODE);
6805 if (IS_IVB_GT1(dev))
6806 I915_WRITE(GEN7_ROW_CHICKEN2,
6807 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6808 else {
6809 /* must write both registers */
6810 I915_WRITE(GEN7_ROW_CHICKEN2,
6811 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6812 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
6813 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6814 }
6815
6816 /* WaForceL3Serialization:ivb */
6817 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6818 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6819
6820 /*
6821 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6822 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
6823 */
6824 I915_WRITE(GEN6_UCGCTL2,
6825 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
6826
6827 /* This is required by WaCatErrorRejectionIssue:ivb */
6828 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6829 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6830 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6831
6832 g4x_disable_trickle_feed(dev);
6833
6834 gen7_setup_fixed_func_scheduler(dev_priv);
6835
6836 if (0) { /* causes HiZ corruption on ivb:gt1 */
6837 /* enable HiZ Raw Stall Optimization */
6838 I915_WRITE(CACHE_MODE_0_GEN7,
6839 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6840 }
6841
6842 /* WaDisable4x2SubspanOptimization:ivb */
6843 I915_WRITE(CACHE_MODE_1,
6844 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6845
6846 /*
6847 * BSpec recommends 8x4 when MSAA is used,
6848 * however in practice 16x4 seems fastest.
6849 *
6850 * Note that PS/WM thread counts depend on the WIZ hashing
6851 * disable bit, which we don't touch here, but it's good
6852 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6853 */
6854 I915_WRITE(GEN7_GT_MODE,
6855 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6856
6857 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
6858 snpcr &= ~GEN6_MBC_SNPCR_MASK;
6859 snpcr |= GEN6_MBC_SNPCR_MED;
6860 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
6861
6862 if (!HAS_PCH_NOP(dev))
6863 cpt_init_clock_gating(dev);
6864
6865 gen6_check_mch_setup(dev);
6866 }
6867
6868 static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
6869 {
6870 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6871
6872 /*
6873 * Disable trickle feed and enable pnd deadline calculation
6874 */
6875 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6876 I915_WRITE(CBR1_VLV, 0);
6877 }
6878
6879 static void valleyview_init_clock_gating(struct drm_device *dev)
6880 {
6881 struct drm_i915_private *dev_priv = dev->dev_private;
6882
6883 vlv_init_display_clock_gating(dev_priv);
6884
6885 /* WaDisableEarlyCull:vlv */
6886 I915_WRITE(_3D_CHICKEN3,
6887 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6888
6889 /* WaDisableBackToBackFlipFix:vlv */
6890 I915_WRITE(IVB_CHICKEN3,
6891 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6892 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6893
6894 /* WaPsdDispatchEnable:vlv */
6895 /* WaDisablePSDDualDispatchEnable:vlv */
6896 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6897 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
6898 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
6899
6900 /* WaDisable_RenderCache_OperationalFlush:vlv */
6901 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6902
6903 /* WaForceL3Serialization:vlv */
6904 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6905 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6906
6907 /* WaDisableDopClockGating:vlv */
6908 I915_WRITE(GEN7_ROW_CHICKEN2,
6909 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6910
6911 /* This is required by WaCatErrorRejectionIssue:vlv */
6912 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6913 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6914 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6915
6916 gen7_setup_fixed_func_scheduler(dev_priv);
6917
6918 /*
6919 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6920 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
6921 */
6922 I915_WRITE(GEN6_UCGCTL2,
6923 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
6924
6925 /* WaDisableL3Bank2xClockGate:vlv
6926 * Disabling L3 clock gating- MMIO 940c[25] = 1
6927 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
6928 I915_WRITE(GEN7_UCGCTL4,
6929 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
6930
6931 /*
6932 * BSpec says this must be set, even though
6933 * WaDisable4x2SubspanOptimization isn't listed for VLV.
6934 */
6935 I915_WRITE(CACHE_MODE_1,
6936 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6937
6938 /*
6939 * BSpec recommends 8x4 when MSAA is used,
6940 * however in practice 16x4 seems fastest.
6941 *
6942 * Note that PS/WM thread counts depend on the WIZ hashing
6943 * disable bit, which we don't touch here, but it's good
6944 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6945 */
6946 I915_WRITE(GEN7_GT_MODE,
6947 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6948
6949 /*
6950 * WaIncreaseL3CreditsForVLVB0:vlv
6951 * This is the hardware default actually.
6952 */
6953 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
6954
6955 /*
6956 * WaDisableVLVClockGating_VBIIssue:vlv
6957 * Disable clock gating on th GCFG unit to prevent a delay
6958 * in the reporting of vblank events.
6959 */
6960 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6961 }
6962
6963 static void cherryview_init_clock_gating(struct drm_device *dev)
6964 {
6965 struct drm_i915_private *dev_priv = dev->dev_private;
6966
6967 vlv_init_display_clock_gating(dev_priv);
6968
6969 /* WaVSRefCountFullforceMissDisable:chv */
6970 /* WaDSRefCountFullforceMissDisable:chv */
6971 I915_WRITE(GEN7_FF_THREAD_MODE,
6972 I915_READ(GEN7_FF_THREAD_MODE) &
6973 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
6974
6975 /* WaDisableSemaphoreAndSyncFlipWait:chv */
6976 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6977 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
6978
6979 /* WaDisableCSUnitClockGating:chv */
6980 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
6981 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6982
6983 /* WaDisableSDEUnitClockGating:chv */
6984 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6985 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6986
6987 /*
6988 * GTT cache may not work with big pages, so if those
6989 * are ever enabled GTT cache may need to be disabled.
6990 */
6991 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
6992 }
6993
6994 static void g4x_init_clock_gating(struct drm_device *dev)
6995 {
6996 struct drm_i915_private *dev_priv = dev->dev_private;
6997 uint32_t dspclk_gate;
6998
6999 I915_WRITE(RENCLK_GATE_D1, 0);
7000 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7001 GS_UNIT_CLOCK_GATE_DISABLE |
7002 CL_UNIT_CLOCK_GATE_DISABLE);
7003 I915_WRITE(RAMCLK_GATE_D, 0);
7004 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7005 OVRUNIT_CLOCK_GATE_DISABLE |
7006 OVCUNIT_CLOCK_GATE_DISABLE;
7007 if (IS_GM45(dev))
7008 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7009 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
7010
7011 /* WaDisableRenderCachePipelinedFlush */
7012 I915_WRITE(CACHE_MODE_0,
7013 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
7014
7015 /* WaDisable_RenderCache_OperationalFlush:g4x */
7016 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7017
7018 g4x_disable_trickle_feed(dev);
7019 }
7020
7021 static void crestline_init_clock_gating(struct drm_device *dev)
7022 {
7023 struct drm_i915_private *dev_priv = dev->dev_private;
7024
7025 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7026 I915_WRITE(RENCLK_GATE_D2, 0);
7027 I915_WRITE(DSPCLK_GATE_D, 0);
7028 I915_WRITE(RAMCLK_GATE_D, 0);
7029 I915_WRITE16(DEUC, 0);
7030 I915_WRITE(MI_ARB_STATE,
7031 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7032
7033 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7034 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7035 }
7036
7037 static void broadwater_init_clock_gating(struct drm_device *dev)
7038 {
7039 struct drm_i915_private *dev_priv = dev->dev_private;
7040
7041 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7042 I965_RCC_CLOCK_GATE_DISABLE |
7043 I965_RCPB_CLOCK_GATE_DISABLE |
7044 I965_ISC_CLOCK_GATE_DISABLE |
7045 I965_FBC_CLOCK_GATE_DISABLE);
7046 I915_WRITE(RENCLK_GATE_D2, 0);
7047 I915_WRITE(MI_ARB_STATE,
7048 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7049
7050 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7051 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7052 }
7053
7054 static void gen3_init_clock_gating(struct drm_device *dev)
7055 {
7056 struct drm_i915_private *dev_priv = dev->dev_private;
7057 u32 dstate = I915_READ(D_STATE);
7058
7059 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7060 DSTATE_DOT_CLOCK_GATING;
7061 I915_WRITE(D_STATE, dstate);
7062
7063 if (IS_PINEVIEW(dev))
7064 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
7065
7066 /* IIR "flip pending" means done if this bit is set */
7067 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
7068
7069 /* interrupts should cause a wake up from C3 */
7070 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
7071
7072 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7073 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
7074
7075 I915_WRITE(MI_ARB_STATE,
7076 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7077 }
7078
7079 static void i85x_init_clock_gating(struct drm_device *dev)
7080 {
7081 struct drm_i915_private *dev_priv = dev->dev_private;
7082
7083 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7084
7085 /* interrupts should cause a wake up from C3 */
7086 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7087 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
7088
7089 I915_WRITE(MEM_MODE,
7090 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
7091 }
7092
7093 static void i830_init_clock_gating(struct drm_device *dev)
7094 {
7095 struct drm_i915_private *dev_priv = dev->dev_private;
7096
7097 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
7098
7099 I915_WRITE(MEM_MODE,
7100 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7101 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
7102 }
7103
7104 void intel_init_clock_gating(struct drm_device *dev)
7105 {
7106 struct drm_i915_private *dev_priv = dev->dev_private;
7107
7108 if (dev_priv->display.init_clock_gating)
7109 dev_priv->display.init_clock_gating(dev);
7110 }
7111
7112 void intel_suspend_hw(struct drm_device *dev)
7113 {
7114 if (HAS_PCH_LPT(dev))
7115 lpt_suspend_hw(dev);
7116 }
7117
7118 /* Set up chip specific power management-related functions */
7119 void intel_init_pm(struct drm_device *dev)
7120 {
7121 struct drm_i915_private *dev_priv = dev->dev_private;
7122
7123 intel_fbc_init(dev_priv);
7124
7125 /* For cxsr */
7126 if (IS_PINEVIEW(dev))
7127 i915_pineview_get_mem_freq(dev);
7128 else if (IS_GEN5(dev))
7129 i915_ironlake_get_mem_freq(dev);
7130
7131 /* For FIFO watermark updates */
7132 if (INTEL_INFO(dev)->gen >= 9) {
7133 skl_setup_wm_latency(dev);
7134
7135 if (IS_BROXTON(dev))
7136 dev_priv->display.init_clock_gating =
7137 bxt_init_clock_gating;
7138 else if (IS_SKYLAKE(dev))
7139 dev_priv->display.init_clock_gating =
7140 skl_init_clock_gating;
7141 dev_priv->display.update_wm = skl_update_wm;
7142 dev_priv->display.update_sprite_wm = skl_update_sprite_wm;
7143 } else if (HAS_PCH_SPLIT(dev)) {
7144 ilk_setup_wm_latency(dev);
7145
7146 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
7147 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7148 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7149 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
7150 dev_priv->display.update_wm = ilk_update_wm;
7151 dev_priv->display.update_sprite_wm = ilk_update_sprite_wm;
7152 } else {
7153 DRM_DEBUG_KMS("Failed to read display plane latency. "
7154 "Disable CxSR\n");
7155 }
7156
7157 if (IS_GEN5(dev))
7158 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7159 else if (IS_GEN6(dev))
7160 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7161 else if (IS_IVYBRIDGE(dev))
7162 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7163 else if (IS_HASWELL(dev))
7164 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7165 else if (INTEL_INFO(dev)->gen == 8)
7166 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7167 } else if (IS_CHERRYVIEW(dev)) {
7168 vlv_setup_wm_latency(dev);
7169
7170 dev_priv->display.update_wm = vlv_update_wm;
7171 dev_priv->display.init_clock_gating =
7172 cherryview_init_clock_gating;
7173 } else if (IS_VALLEYVIEW(dev)) {
7174 vlv_setup_wm_latency(dev);
7175
7176 dev_priv->display.update_wm = vlv_update_wm;
7177 dev_priv->display.init_clock_gating =
7178 valleyview_init_clock_gating;
7179 } else if (IS_PINEVIEW(dev)) {
7180 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7181 dev_priv->is_ddr3,
7182 dev_priv->fsb_freq,
7183 dev_priv->mem_freq)) {
7184 DRM_INFO("failed to find known CxSR latency "
7185 "(found ddr%s fsb freq %d, mem freq %d), "
7186 "disabling CxSR\n",
7187 (dev_priv->is_ddr3 == 1) ? "3" : "2",
7188 dev_priv->fsb_freq, dev_priv->mem_freq);
7189 /* Disable CxSR and never update its watermark again */
7190 intel_set_memory_cxsr(dev_priv, false);
7191 dev_priv->display.update_wm = NULL;
7192 } else
7193 dev_priv->display.update_wm = pineview_update_wm;
7194 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7195 } else if (IS_G4X(dev)) {
7196 dev_priv->display.update_wm = g4x_update_wm;
7197 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7198 } else if (IS_GEN4(dev)) {
7199 dev_priv->display.update_wm = i965_update_wm;
7200 if (IS_CRESTLINE(dev))
7201 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7202 else if (IS_BROADWATER(dev))
7203 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7204 } else if (IS_GEN3(dev)) {
7205 dev_priv->display.update_wm = i9xx_update_wm;
7206 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7207 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7208 } else if (IS_GEN2(dev)) {
7209 if (INTEL_INFO(dev)->num_pipes == 1) {
7210 dev_priv->display.update_wm = i845_update_wm;
7211 dev_priv->display.get_fifo_size = i845_get_fifo_size;
7212 } else {
7213 dev_priv->display.update_wm = i9xx_update_wm;
7214 dev_priv->display.get_fifo_size = i830_get_fifo_size;
7215 }
7216
7217 if (IS_I85X(dev) || IS_I865G(dev))
7218 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7219 else
7220 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7221 } else {
7222 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
7223 }
7224 }
7225
7226 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
7227 {
7228 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7229
7230 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7231 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7232 return -EAGAIN;
7233 }
7234
7235 I915_WRITE(GEN6_PCODE_DATA, *val);
7236 I915_WRITE(GEN6_PCODE_DATA1, 0);
7237 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7238
7239 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7240 500)) {
7241 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7242 return -ETIMEDOUT;
7243 }
7244
7245 *val = I915_READ(GEN6_PCODE_DATA);
7246 I915_WRITE(GEN6_PCODE_DATA, 0);
7247
7248 return 0;
7249 }
7250
7251 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val)
7252 {
7253 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7254
7255 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7256 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7257 return -EAGAIN;
7258 }
7259
7260 I915_WRITE(GEN6_PCODE_DATA, val);
7261 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7262
7263 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7264 500)) {
7265 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7266 return -ETIMEDOUT;
7267 }
7268
7269 I915_WRITE(GEN6_PCODE_DATA, 0);
7270
7271 return 0;
7272 }
7273
7274 static int vlv_gpu_freq_div(unsigned int czclk_freq)
7275 {
7276 switch (czclk_freq) {
7277 case 200:
7278 return 10;
7279 case 267:
7280 return 12;
7281 case 320:
7282 case 333:
7283 return 16;
7284 case 400:
7285 return 20;
7286 default:
7287 return -1;
7288 }
7289 }
7290
7291 static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7292 {
7293 int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
7294
7295 div = vlv_gpu_freq_div(czclk_freq);
7296 if (div < 0)
7297 return div;
7298
7299 return DIV_ROUND_CLOSEST(czclk_freq * (val + 6 - 0xbd), div);
7300 }
7301
7302 static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
7303 {
7304 int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
7305
7306 mul = vlv_gpu_freq_div(czclk_freq);
7307 if (mul < 0)
7308 return mul;
7309
7310 return DIV_ROUND_CLOSEST(mul * val, czclk_freq) + 0xbd - 6;
7311 }
7312
7313 static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
7314 {
7315 int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
7316
7317 div = vlv_gpu_freq_div(czclk_freq) / 2;
7318 if (div < 0)
7319 return div;
7320
7321 return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2;
7322 }
7323
7324 static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
7325 {
7326 int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
7327
7328 mul = vlv_gpu_freq_div(czclk_freq) / 2;
7329 if (mul < 0)
7330 return mul;
7331
7332 /* CHV needs even values */
7333 return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2;
7334 }
7335
7336 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
7337 {
7338 if (IS_GEN9(dev_priv->dev))
7339 return (val * GT_FREQUENCY_MULTIPLIER) / GEN9_FREQ_SCALER;
7340 else if (IS_CHERRYVIEW(dev_priv->dev))
7341 return chv_gpu_freq(dev_priv, val);
7342 else if (IS_VALLEYVIEW(dev_priv->dev))
7343 return byt_gpu_freq(dev_priv, val);
7344 else
7345 return val * GT_FREQUENCY_MULTIPLIER;
7346 }
7347
7348 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7349 {
7350 if (IS_GEN9(dev_priv->dev))
7351 return (val * GEN9_FREQ_SCALER) / GT_FREQUENCY_MULTIPLIER;
7352 else if (IS_CHERRYVIEW(dev_priv->dev))
7353 return chv_freq_opcode(dev_priv, val);
7354 else if (IS_VALLEYVIEW(dev_priv->dev))
7355 return byt_freq_opcode(dev_priv, val);
7356 else
7357 return val / GT_FREQUENCY_MULTIPLIER;
7358 }
7359
7360 struct request_boost {
7361 struct work_struct work;
7362 struct drm_i915_gem_request *req;
7363 };
7364
7365 static void __intel_rps_boost_work(struct work_struct *work)
7366 {
7367 struct request_boost *boost = container_of(work, struct request_boost, work);
7368 struct drm_i915_gem_request *req = boost->req;
7369
7370 if (!i915_gem_request_completed(req, true))
7371 gen6_rps_boost(to_i915(req->ring->dev), NULL,
7372 req->emitted_jiffies);
7373
7374 i915_gem_request_unreference__unlocked(req);
7375 kfree(boost);
7376 }
7377
7378 void intel_queue_rps_boost_for_request(struct drm_device *dev,
7379 struct drm_i915_gem_request *req)
7380 {
7381 struct request_boost *boost;
7382
7383 if (req == NULL || INTEL_INFO(dev)->gen < 6)
7384 return;
7385
7386 if (i915_gem_request_completed(req, true))
7387 return;
7388
7389 boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
7390 if (boost == NULL)
7391 return;
7392
7393 i915_gem_request_reference(req);
7394 boost->req = req;
7395
7396 INIT_WORK(&boost->work, __intel_rps_boost_work);
7397 queue_work(to_i915(dev)->wq, &boost->work);
7398 }
7399
7400 void intel_pm_setup(struct drm_device *dev)
7401 {
7402 struct drm_i915_private *dev_priv = dev->dev_private;
7403
7404 mutex_init(&dev_priv->rps.hw_lock);
7405 spin_lock_init(&dev_priv->rps.client_lock);
7406
7407 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
7408 intel_gen6_powersave_work);
7409 INIT_LIST_HEAD(&dev_priv->rps.clients);
7410 INIT_LIST_HEAD(&dev_priv->rps.semaphores.link);
7411 INIT_LIST_HEAD(&dev_priv->rps.mmioflips.link);
7412
7413 dev_priv->pm.suspended = false;
7414 }
Linux kernel - Deliverables
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