2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
28 #include <linux/cpufreq.h>
29 #include <drm/drm_plane_helper.h>
31 #include "intel_drv.h"
32 #include "../../../platform/x86/intel_ips.h"
33 #include <linux/module.h>
38 * RC6 is a special power stage which allows the GPU to enter an very
39 * low-voltage mode when idle, using down to 0V while at this stage. This
40 * stage is entered automatically when the GPU is idle when RC6 support is
41 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
43 * There are different RC6 modes available in Intel GPU, which differentiate
44 * among each other with the latency required to enter and leave RC6 and
45 * voltage consumed by the GPU in different states.
47 * The combination of the following flags define which states GPU is allowed
48 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
49 * RC6pp is deepest RC6. Their support by hardware varies according to the
50 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
51 * which brings the most power savings; deeper states save more power, but
52 * require higher latency to switch to and wake up.
54 #define INTEL_RC6_ENABLE (1<<0)
55 #define INTEL_RC6p_ENABLE (1<<1)
56 #define INTEL_RC6pp_ENABLE (1<<2)
58 static void gen9_init_clock_gating(struct drm_device
*dev
)
60 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
62 /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl */
63 I915_WRITE(CHICKEN_PAR1_1
,
64 I915_READ(CHICKEN_PAR1_1
) | SKL_EDP_PSR_FIX_RDWRAP
);
66 I915_WRITE(GEN8_CONFIG0
,
67 I915_READ(GEN8_CONFIG0
) | GEN9_DEFAULT_FIXES
);
69 /* WaEnableChickenDCPR:skl,bxt,kbl */
70 I915_WRITE(GEN8_CHICKEN_DCPR_1
,
71 I915_READ(GEN8_CHICKEN_DCPR_1
) | MASK_WAKEMEM
);
73 /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */
74 /* WaFbcWakeMemOn:skl,bxt,kbl */
75 I915_WRITE(DISP_ARB_CTL
, I915_READ(DISP_ARB_CTL
) |
77 DISP_FBC_MEMORY_WAKE
);
79 /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl */
80 I915_WRITE(ILK_DPFC_CHICKEN
, I915_READ(ILK_DPFC_CHICKEN
) |
81 ILK_DPFC_DISABLE_DUMMY0
);
84 static void bxt_init_clock_gating(struct drm_device
*dev
)
86 struct drm_i915_private
*dev_priv
= to_i915(dev
);
88 gen9_init_clock_gating(dev
);
90 /* WaDisableSDEUnitClockGating:bxt */
91 I915_WRITE(GEN8_UCGCTL6
, I915_READ(GEN8_UCGCTL6
) |
92 GEN8_SDEUNIT_CLOCK_GATE_DISABLE
);
96 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
98 I915_WRITE(GEN8_UCGCTL6
, I915_READ(GEN8_UCGCTL6
) |
99 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ
);
102 * Wa: Backlight PWM may stop in the asserted state, causing backlight
105 if (IS_BXT_REVID(dev_priv
, BXT_REVID_B0
, REVID_FOREVER
))
106 I915_WRITE(GEN9_CLKGATE_DIS_0
, I915_READ(GEN9_CLKGATE_DIS_0
) |
107 PWM1_GATING_DIS
| PWM2_GATING_DIS
);
110 static void i915_pineview_get_mem_freq(struct drm_device
*dev
)
112 struct drm_i915_private
*dev_priv
= to_i915(dev
);
115 tmp
= I915_READ(CLKCFG
);
117 switch (tmp
& CLKCFG_FSB_MASK
) {
119 dev_priv
->fsb_freq
= 533; /* 133*4 */
122 dev_priv
->fsb_freq
= 800; /* 200*4 */
125 dev_priv
->fsb_freq
= 667; /* 167*4 */
128 dev_priv
->fsb_freq
= 400; /* 100*4 */
132 switch (tmp
& CLKCFG_MEM_MASK
) {
134 dev_priv
->mem_freq
= 533;
137 dev_priv
->mem_freq
= 667;
140 dev_priv
->mem_freq
= 800;
144 /* detect pineview DDR3 setting */
145 tmp
= I915_READ(CSHRDDR3CTL
);
146 dev_priv
->is_ddr3
= (tmp
& CSHRDDR3CTL_DDR3
) ? 1 : 0;
149 static void i915_ironlake_get_mem_freq(struct drm_device
*dev
)
151 struct drm_i915_private
*dev_priv
= to_i915(dev
);
154 ddrpll
= I915_READ16(DDRMPLL1
);
155 csipll
= I915_READ16(CSIPLL0
);
157 switch (ddrpll
& 0xff) {
159 dev_priv
->mem_freq
= 800;
162 dev_priv
->mem_freq
= 1066;
165 dev_priv
->mem_freq
= 1333;
168 dev_priv
->mem_freq
= 1600;
171 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
173 dev_priv
->mem_freq
= 0;
177 dev_priv
->ips
.r_t
= dev_priv
->mem_freq
;
179 switch (csipll
& 0x3ff) {
181 dev_priv
->fsb_freq
= 3200;
184 dev_priv
->fsb_freq
= 3733;
187 dev_priv
->fsb_freq
= 4266;
190 dev_priv
->fsb_freq
= 4800;
193 dev_priv
->fsb_freq
= 5333;
196 dev_priv
->fsb_freq
= 5866;
199 dev_priv
->fsb_freq
= 6400;
202 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
204 dev_priv
->fsb_freq
= 0;
208 if (dev_priv
->fsb_freq
== 3200) {
209 dev_priv
->ips
.c_m
= 0;
210 } else if (dev_priv
->fsb_freq
> 3200 && dev_priv
->fsb_freq
<= 4800) {
211 dev_priv
->ips
.c_m
= 1;
213 dev_priv
->ips
.c_m
= 2;
217 static const struct cxsr_latency cxsr_latency_table
[] = {
218 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
219 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
220 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
221 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
222 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
224 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
225 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
226 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
227 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
228 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
230 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
231 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
232 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
233 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
234 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
236 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
237 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
238 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
239 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
240 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
242 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
243 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
244 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
245 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
246 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
248 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
249 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
250 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
251 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
252 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
255 static const struct cxsr_latency
*intel_get_cxsr_latency(int is_desktop
,
260 const struct cxsr_latency
*latency
;
263 if (fsb
== 0 || mem
== 0)
266 for (i
= 0; i
< ARRAY_SIZE(cxsr_latency_table
); i
++) {
267 latency
= &cxsr_latency_table
[i
];
268 if (is_desktop
== latency
->is_desktop
&&
269 is_ddr3
== latency
->is_ddr3
&&
270 fsb
== latency
->fsb_freq
&& mem
== latency
->mem_freq
)
274 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
279 static void chv_set_memory_dvfs(struct drm_i915_private
*dev_priv
, bool enable
)
283 mutex_lock(&dev_priv
->rps
.hw_lock
);
285 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DDR_SETUP2
);
287 val
&= ~FORCE_DDR_HIGH_FREQ
;
289 val
|= FORCE_DDR_HIGH_FREQ
;
290 val
&= ~FORCE_DDR_LOW_FREQ
;
291 val
|= FORCE_DDR_FREQ_REQ_ACK
;
292 vlv_punit_write(dev_priv
, PUNIT_REG_DDR_SETUP2
, val
);
294 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DDR_SETUP2
) &
295 FORCE_DDR_FREQ_REQ_ACK
) == 0, 3))
296 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
298 mutex_unlock(&dev_priv
->rps
.hw_lock
);
301 static void chv_set_memory_pm5(struct drm_i915_private
*dev_priv
, bool enable
)
305 mutex_lock(&dev_priv
->rps
.hw_lock
);
307 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
309 val
|= DSP_MAXFIFO_PM5_ENABLE
;
311 val
&= ~DSP_MAXFIFO_PM5_ENABLE
;
312 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
314 mutex_unlock(&dev_priv
->rps
.hw_lock
);
317 #define FW_WM(value, plane) \
318 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
320 void intel_set_memory_cxsr(struct drm_i915_private
*dev_priv
, bool enable
)
322 struct drm_device
*dev
= &dev_priv
->drm
;
325 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
326 I915_WRITE(FW_BLC_SELF_VLV
, enable
? FW_CSPWRDWNEN
: 0);
327 POSTING_READ(FW_BLC_SELF_VLV
);
328 dev_priv
->wm
.vlv
.cxsr
= enable
;
329 } else if (IS_G4X(dev
) || IS_CRESTLINE(dev
)) {
330 I915_WRITE(FW_BLC_SELF
, enable
? FW_BLC_SELF_EN
: 0);
331 POSTING_READ(FW_BLC_SELF
);
332 } else if (IS_PINEVIEW(dev
)) {
333 val
= I915_READ(DSPFW3
) & ~PINEVIEW_SELF_REFRESH_EN
;
334 val
|= enable
? PINEVIEW_SELF_REFRESH_EN
: 0;
335 I915_WRITE(DSPFW3
, val
);
336 POSTING_READ(DSPFW3
);
337 } else if (IS_I945G(dev
) || IS_I945GM(dev
)) {
338 val
= enable
? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN
) :
339 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN
);
340 I915_WRITE(FW_BLC_SELF
, val
);
341 POSTING_READ(FW_BLC_SELF
);
342 } else if (IS_I915GM(dev
)) {
343 val
= enable
? _MASKED_BIT_ENABLE(INSTPM_SELF_EN
) :
344 _MASKED_BIT_DISABLE(INSTPM_SELF_EN
);
345 I915_WRITE(INSTPM
, val
);
346 POSTING_READ(INSTPM
);
351 DRM_DEBUG_KMS("memory self-refresh is %s\n",
352 enable
? "enabled" : "disabled");
357 * Latency for FIFO fetches is dependent on several factors:
358 * - memory configuration (speed, channels)
360 * - current MCH state
361 * It can be fairly high in some situations, so here we assume a fairly
362 * pessimal value. It's a tradeoff between extra memory fetches (if we
363 * set this value too high, the FIFO will fetch frequently to stay full)
364 * and power consumption (set it too low to save power and we might see
365 * FIFO underruns and display "flicker").
367 * A value of 5us seems to be a good balance; safe for very low end
368 * platforms but not overly aggressive on lower latency configs.
370 static const int pessimal_latency_ns
= 5000;
372 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
373 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
375 static int vlv_get_fifo_size(struct drm_device
*dev
,
376 enum pipe pipe
, int plane
)
378 struct drm_i915_private
*dev_priv
= to_i915(dev
);
379 int sprite0_start
, sprite1_start
, size
;
382 uint32_t dsparb
, dsparb2
, dsparb3
;
384 dsparb
= I915_READ(DSPARB
);
385 dsparb2
= I915_READ(DSPARB2
);
386 sprite0_start
= VLV_FIFO_START(dsparb
, dsparb2
, 0, 0);
387 sprite1_start
= VLV_FIFO_START(dsparb
, dsparb2
, 8, 4);
390 dsparb
= I915_READ(DSPARB
);
391 dsparb2
= I915_READ(DSPARB2
);
392 sprite0_start
= VLV_FIFO_START(dsparb
, dsparb2
, 16, 8);
393 sprite1_start
= VLV_FIFO_START(dsparb
, dsparb2
, 24, 12);
396 dsparb2
= I915_READ(DSPARB2
);
397 dsparb3
= I915_READ(DSPARB3
);
398 sprite0_start
= VLV_FIFO_START(dsparb3
, dsparb2
, 0, 16);
399 sprite1_start
= VLV_FIFO_START(dsparb3
, dsparb2
, 8, 20);
407 size
= sprite0_start
;
410 size
= sprite1_start
- sprite0_start
;
413 size
= 512 - 1 - sprite1_start
;
419 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
420 pipe_name(pipe
), plane
== 0 ? "primary" : "sprite",
421 plane
== 0 ? plane_name(pipe
) : sprite_name(pipe
, plane
- 1),
427 static int i9xx_get_fifo_size(struct drm_device
*dev
, int plane
)
429 struct drm_i915_private
*dev_priv
= to_i915(dev
);
430 uint32_t dsparb
= I915_READ(DSPARB
);
433 size
= dsparb
& 0x7f;
435 size
= ((dsparb
>> DSPARB_CSTART_SHIFT
) & 0x7f) - size
;
437 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
438 plane
? "B" : "A", size
);
443 static int i830_get_fifo_size(struct drm_device
*dev
, int plane
)
445 struct drm_i915_private
*dev_priv
= to_i915(dev
);
446 uint32_t dsparb
= I915_READ(DSPARB
);
449 size
= dsparb
& 0x1ff;
451 size
= ((dsparb
>> DSPARB_BEND_SHIFT
) & 0x1ff) - size
;
452 size
>>= 1; /* Convert to cachelines */
454 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
455 plane
? "B" : "A", size
);
460 static int i845_get_fifo_size(struct drm_device
*dev
, int plane
)
462 struct drm_i915_private
*dev_priv
= to_i915(dev
);
463 uint32_t dsparb
= I915_READ(DSPARB
);
466 size
= dsparb
& 0x7f;
467 size
>>= 2; /* Convert to cachelines */
469 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
476 /* Pineview has different values for various configs */
477 static const struct intel_watermark_params pineview_display_wm
= {
478 .fifo_size
= PINEVIEW_DISPLAY_FIFO
,
479 .max_wm
= PINEVIEW_MAX_WM
,
480 .default_wm
= PINEVIEW_DFT_WM
,
481 .guard_size
= PINEVIEW_GUARD_WM
,
482 .cacheline_size
= PINEVIEW_FIFO_LINE_SIZE
,
484 static const struct intel_watermark_params pineview_display_hplloff_wm
= {
485 .fifo_size
= PINEVIEW_DISPLAY_FIFO
,
486 .max_wm
= PINEVIEW_MAX_WM
,
487 .default_wm
= PINEVIEW_DFT_HPLLOFF_WM
,
488 .guard_size
= PINEVIEW_GUARD_WM
,
489 .cacheline_size
= PINEVIEW_FIFO_LINE_SIZE
,
491 static const struct intel_watermark_params pineview_cursor_wm
= {
492 .fifo_size
= PINEVIEW_CURSOR_FIFO
,
493 .max_wm
= PINEVIEW_CURSOR_MAX_WM
,
494 .default_wm
= PINEVIEW_CURSOR_DFT_WM
,
495 .guard_size
= PINEVIEW_CURSOR_GUARD_WM
,
496 .cacheline_size
= PINEVIEW_FIFO_LINE_SIZE
,
498 static const struct intel_watermark_params pineview_cursor_hplloff_wm
= {
499 .fifo_size
= PINEVIEW_CURSOR_FIFO
,
500 .max_wm
= PINEVIEW_CURSOR_MAX_WM
,
501 .default_wm
= PINEVIEW_CURSOR_DFT_WM
,
502 .guard_size
= PINEVIEW_CURSOR_GUARD_WM
,
503 .cacheline_size
= PINEVIEW_FIFO_LINE_SIZE
,
505 static const struct intel_watermark_params g4x_wm_info
= {
506 .fifo_size
= G4X_FIFO_SIZE
,
507 .max_wm
= G4X_MAX_WM
,
508 .default_wm
= G4X_MAX_WM
,
510 .cacheline_size
= G4X_FIFO_LINE_SIZE
,
512 static const struct intel_watermark_params g4x_cursor_wm_info
= {
513 .fifo_size
= I965_CURSOR_FIFO
,
514 .max_wm
= I965_CURSOR_MAX_WM
,
515 .default_wm
= I965_CURSOR_DFT_WM
,
517 .cacheline_size
= G4X_FIFO_LINE_SIZE
,
519 static const struct intel_watermark_params i965_cursor_wm_info
= {
520 .fifo_size
= I965_CURSOR_FIFO
,
521 .max_wm
= I965_CURSOR_MAX_WM
,
522 .default_wm
= I965_CURSOR_DFT_WM
,
524 .cacheline_size
= I915_FIFO_LINE_SIZE
,
526 static const struct intel_watermark_params i945_wm_info
= {
527 .fifo_size
= I945_FIFO_SIZE
,
528 .max_wm
= I915_MAX_WM
,
531 .cacheline_size
= I915_FIFO_LINE_SIZE
,
533 static const struct intel_watermark_params i915_wm_info
= {
534 .fifo_size
= I915_FIFO_SIZE
,
535 .max_wm
= I915_MAX_WM
,
538 .cacheline_size
= I915_FIFO_LINE_SIZE
,
540 static const struct intel_watermark_params i830_a_wm_info
= {
541 .fifo_size
= I855GM_FIFO_SIZE
,
542 .max_wm
= I915_MAX_WM
,
545 .cacheline_size
= I830_FIFO_LINE_SIZE
,
547 static const struct intel_watermark_params i830_bc_wm_info
= {
548 .fifo_size
= I855GM_FIFO_SIZE
,
549 .max_wm
= I915_MAX_WM
/2,
552 .cacheline_size
= I830_FIFO_LINE_SIZE
,
554 static const struct intel_watermark_params i845_wm_info
= {
555 .fifo_size
= I830_FIFO_SIZE
,
556 .max_wm
= I915_MAX_WM
,
559 .cacheline_size
= I830_FIFO_LINE_SIZE
,
563 * intel_calculate_wm - calculate watermark level
564 * @clock_in_khz: pixel clock
565 * @wm: chip FIFO params
566 * @cpp: bytes per pixel
567 * @latency_ns: memory latency for the platform
569 * Calculate the watermark level (the level at which the display plane will
570 * start fetching from memory again). Each chip has a different display
571 * FIFO size and allocation, so the caller needs to figure that out and pass
572 * in the correct intel_watermark_params structure.
574 * As the pixel clock runs, the FIFO will be drained at a rate that depends
575 * on the pixel size. When it reaches the watermark level, it'll start
576 * fetching FIFO line sized based chunks from memory until the FIFO fills
577 * past the watermark point. If the FIFO drains completely, a FIFO underrun
578 * will occur, and a display engine hang could result.
580 static unsigned long intel_calculate_wm(unsigned long clock_in_khz
,
581 const struct intel_watermark_params
*wm
,
582 int fifo_size
, int cpp
,
583 unsigned long latency_ns
)
585 long entries_required
, wm_size
;
588 * Note: we need to make sure we don't overflow for various clock &
590 * clocks go from a few thousand to several hundred thousand.
591 * latency is usually a few thousand
593 entries_required
= ((clock_in_khz
/ 1000) * cpp
* latency_ns
) /
595 entries_required
= DIV_ROUND_UP(entries_required
, wm
->cacheline_size
);
597 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required
);
599 wm_size
= fifo_size
- (entries_required
+ wm
->guard_size
);
601 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size
);
603 /* Don't promote wm_size to unsigned... */
604 if (wm_size
> (long)wm
->max_wm
)
605 wm_size
= wm
->max_wm
;
607 wm_size
= wm
->default_wm
;
610 * Bspec seems to indicate that the value shouldn't be lower than
611 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
612 * Lets go for 8 which is the burst size since certain platforms
613 * already use a hardcoded 8 (which is what the spec says should be
622 static struct drm_crtc
*single_enabled_crtc(struct drm_device
*dev
)
624 struct drm_crtc
*crtc
, *enabled
= NULL
;
626 for_each_crtc(dev
, crtc
) {
627 if (intel_crtc_active(crtc
)) {
637 static void pineview_update_wm(struct drm_crtc
*unused_crtc
)
639 struct drm_device
*dev
= unused_crtc
->dev
;
640 struct drm_i915_private
*dev_priv
= to_i915(dev
);
641 struct drm_crtc
*crtc
;
642 const struct cxsr_latency
*latency
;
646 latency
= intel_get_cxsr_latency(IS_PINEVIEW_G(dev
), dev_priv
->is_ddr3
,
647 dev_priv
->fsb_freq
, dev_priv
->mem_freq
);
649 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
650 intel_set_memory_cxsr(dev_priv
, false);
654 crtc
= single_enabled_crtc(dev
);
656 const struct drm_display_mode
*adjusted_mode
= &to_intel_crtc(crtc
)->config
->base
.adjusted_mode
;
657 int cpp
= drm_format_plane_cpp(crtc
->primary
->state
->fb
->pixel_format
, 0);
658 int clock
= adjusted_mode
->crtc_clock
;
661 wm
= intel_calculate_wm(clock
, &pineview_display_wm
,
662 pineview_display_wm
.fifo_size
,
663 cpp
, latency
->display_sr
);
664 reg
= I915_READ(DSPFW1
);
665 reg
&= ~DSPFW_SR_MASK
;
666 reg
|= FW_WM(wm
, SR
);
667 I915_WRITE(DSPFW1
, reg
);
668 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg
);
671 wm
= intel_calculate_wm(clock
, &pineview_cursor_wm
,
672 pineview_display_wm
.fifo_size
,
673 cpp
, latency
->cursor_sr
);
674 reg
= I915_READ(DSPFW3
);
675 reg
&= ~DSPFW_CURSOR_SR_MASK
;
676 reg
|= FW_WM(wm
, CURSOR_SR
);
677 I915_WRITE(DSPFW3
, reg
);
679 /* Display HPLL off SR */
680 wm
= intel_calculate_wm(clock
, &pineview_display_hplloff_wm
,
681 pineview_display_hplloff_wm
.fifo_size
,
682 cpp
, latency
->display_hpll_disable
);
683 reg
= I915_READ(DSPFW3
);
684 reg
&= ~DSPFW_HPLL_SR_MASK
;
685 reg
|= FW_WM(wm
, HPLL_SR
);
686 I915_WRITE(DSPFW3
, reg
);
688 /* cursor HPLL off SR */
689 wm
= intel_calculate_wm(clock
, &pineview_cursor_hplloff_wm
,
690 pineview_display_hplloff_wm
.fifo_size
,
691 cpp
, latency
->cursor_hpll_disable
);
692 reg
= I915_READ(DSPFW3
);
693 reg
&= ~DSPFW_HPLL_CURSOR_MASK
;
694 reg
|= FW_WM(wm
, HPLL_CURSOR
);
695 I915_WRITE(DSPFW3
, reg
);
696 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg
);
698 intel_set_memory_cxsr(dev_priv
, true);
700 intel_set_memory_cxsr(dev_priv
, false);
704 static bool g4x_compute_wm0(struct drm_device
*dev
,
706 const struct intel_watermark_params
*display
,
707 int display_latency_ns
,
708 const struct intel_watermark_params
*cursor
,
709 int cursor_latency_ns
,
713 struct drm_crtc
*crtc
;
714 const struct drm_display_mode
*adjusted_mode
;
715 int htotal
, hdisplay
, clock
, cpp
;
716 int line_time_us
, line_count
;
717 int entries
, tlb_miss
;
719 crtc
= intel_get_crtc_for_plane(dev
, plane
);
720 if (!intel_crtc_active(crtc
)) {
721 *cursor_wm
= cursor
->guard_size
;
722 *plane_wm
= display
->guard_size
;
726 adjusted_mode
= &to_intel_crtc(crtc
)->config
->base
.adjusted_mode
;
727 clock
= adjusted_mode
->crtc_clock
;
728 htotal
= adjusted_mode
->crtc_htotal
;
729 hdisplay
= to_intel_crtc(crtc
)->config
->pipe_src_w
;
730 cpp
= drm_format_plane_cpp(crtc
->primary
->state
->fb
->pixel_format
, 0);
732 /* Use the small buffer method to calculate plane watermark */
733 entries
= ((clock
* cpp
/ 1000) * display_latency_ns
) / 1000;
734 tlb_miss
= display
->fifo_size
*display
->cacheline_size
- hdisplay
* 8;
737 entries
= DIV_ROUND_UP(entries
, display
->cacheline_size
);
738 *plane_wm
= entries
+ display
->guard_size
;
739 if (*plane_wm
> (int)display
->max_wm
)
740 *plane_wm
= display
->max_wm
;
742 /* Use the large buffer method to calculate cursor watermark */
743 line_time_us
= max(htotal
* 1000 / clock
, 1);
744 line_count
= (cursor_latency_ns
/ line_time_us
+ 1000) / 1000;
745 entries
= line_count
* crtc
->cursor
->state
->crtc_w
* cpp
;
746 tlb_miss
= cursor
->fifo_size
*cursor
->cacheline_size
- hdisplay
* 8;
749 entries
= DIV_ROUND_UP(entries
, cursor
->cacheline_size
);
750 *cursor_wm
= entries
+ cursor
->guard_size
;
751 if (*cursor_wm
> (int)cursor
->max_wm
)
752 *cursor_wm
= (int)cursor
->max_wm
;
758 * Check the wm result.
760 * If any calculated watermark values is larger than the maximum value that
761 * can be programmed into the associated watermark register, that watermark
764 static bool g4x_check_srwm(struct drm_device
*dev
,
765 int display_wm
, int cursor_wm
,
766 const struct intel_watermark_params
*display
,
767 const struct intel_watermark_params
*cursor
)
769 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
770 display_wm
, cursor_wm
);
772 if (display_wm
> display
->max_wm
) {
773 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
774 display_wm
, display
->max_wm
);
778 if (cursor_wm
> cursor
->max_wm
) {
779 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
780 cursor_wm
, cursor
->max_wm
);
784 if (!(display_wm
|| cursor_wm
)) {
785 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
792 static bool g4x_compute_srwm(struct drm_device
*dev
,
795 const struct intel_watermark_params
*display
,
796 const struct intel_watermark_params
*cursor
,
797 int *display_wm
, int *cursor_wm
)
799 struct drm_crtc
*crtc
;
800 const struct drm_display_mode
*adjusted_mode
;
801 int hdisplay
, htotal
, cpp
, clock
;
802 unsigned long line_time_us
;
803 int line_count
, line_size
;
808 *display_wm
= *cursor_wm
= 0;
812 crtc
= intel_get_crtc_for_plane(dev
, plane
);
813 adjusted_mode
= &to_intel_crtc(crtc
)->config
->base
.adjusted_mode
;
814 clock
= adjusted_mode
->crtc_clock
;
815 htotal
= adjusted_mode
->crtc_htotal
;
816 hdisplay
= to_intel_crtc(crtc
)->config
->pipe_src_w
;
817 cpp
= drm_format_plane_cpp(crtc
->primary
->state
->fb
->pixel_format
, 0);
819 line_time_us
= max(htotal
* 1000 / clock
, 1);
820 line_count
= (latency_ns
/ line_time_us
+ 1000) / 1000;
821 line_size
= hdisplay
* cpp
;
823 /* Use the minimum of the small and large buffer method for primary */
824 small
= ((clock
* cpp
/ 1000) * latency_ns
) / 1000;
825 large
= line_count
* line_size
;
827 entries
= DIV_ROUND_UP(min(small
, large
), display
->cacheline_size
);
828 *display_wm
= entries
+ display
->guard_size
;
830 /* calculate the self-refresh watermark for display cursor */
831 entries
= line_count
* cpp
* crtc
->cursor
->state
->crtc_w
;
832 entries
= DIV_ROUND_UP(entries
, cursor
->cacheline_size
);
833 *cursor_wm
= entries
+ cursor
->guard_size
;
835 return g4x_check_srwm(dev
,
836 *display_wm
, *cursor_wm
,
840 #define FW_WM_VLV(value, plane) \
841 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
843 static void vlv_write_wm_values(struct intel_crtc
*crtc
,
844 const struct vlv_wm_values
*wm
)
846 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
847 enum pipe pipe
= crtc
->pipe
;
849 I915_WRITE(VLV_DDL(pipe
),
850 (wm
->ddl
[pipe
].cursor
<< DDL_CURSOR_SHIFT
) |
851 (wm
->ddl
[pipe
].sprite
[1] << DDL_SPRITE_SHIFT(1)) |
852 (wm
->ddl
[pipe
].sprite
[0] << DDL_SPRITE_SHIFT(0)) |
853 (wm
->ddl
[pipe
].primary
<< DDL_PLANE_SHIFT
));
856 FW_WM(wm
->sr
.plane
, SR
) |
857 FW_WM(wm
->pipe
[PIPE_B
].cursor
, CURSORB
) |
858 FW_WM_VLV(wm
->pipe
[PIPE_B
].primary
, PLANEB
) |
859 FW_WM_VLV(wm
->pipe
[PIPE_A
].primary
, PLANEA
));
861 FW_WM_VLV(wm
->pipe
[PIPE_A
].sprite
[1], SPRITEB
) |
862 FW_WM(wm
->pipe
[PIPE_A
].cursor
, CURSORA
) |
863 FW_WM_VLV(wm
->pipe
[PIPE_A
].sprite
[0], SPRITEA
));
865 FW_WM(wm
->sr
.cursor
, CURSOR_SR
));
867 if (IS_CHERRYVIEW(dev_priv
)) {
868 I915_WRITE(DSPFW7_CHV
,
869 FW_WM_VLV(wm
->pipe
[PIPE_B
].sprite
[1], SPRITED
) |
870 FW_WM_VLV(wm
->pipe
[PIPE_B
].sprite
[0], SPRITEC
));
871 I915_WRITE(DSPFW8_CHV
,
872 FW_WM_VLV(wm
->pipe
[PIPE_C
].sprite
[1], SPRITEF
) |
873 FW_WM_VLV(wm
->pipe
[PIPE_C
].sprite
[0], SPRITEE
));
874 I915_WRITE(DSPFW9_CHV
,
875 FW_WM_VLV(wm
->pipe
[PIPE_C
].primary
, PLANEC
) |
876 FW_WM(wm
->pipe
[PIPE_C
].cursor
, CURSORC
));
878 FW_WM(wm
->sr
.plane
>> 9, SR_HI
) |
879 FW_WM(wm
->pipe
[PIPE_C
].sprite
[1] >> 8, SPRITEF_HI
) |
880 FW_WM(wm
->pipe
[PIPE_C
].sprite
[0] >> 8, SPRITEE_HI
) |
881 FW_WM(wm
->pipe
[PIPE_C
].primary
>> 8, PLANEC_HI
) |
882 FW_WM(wm
->pipe
[PIPE_B
].sprite
[1] >> 8, SPRITED_HI
) |
883 FW_WM(wm
->pipe
[PIPE_B
].sprite
[0] >> 8, SPRITEC_HI
) |
884 FW_WM(wm
->pipe
[PIPE_B
].primary
>> 8, PLANEB_HI
) |
885 FW_WM(wm
->pipe
[PIPE_A
].sprite
[1] >> 8, SPRITEB_HI
) |
886 FW_WM(wm
->pipe
[PIPE_A
].sprite
[0] >> 8, SPRITEA_HI
) |
887 FW_WM(wm
->pipe
[PIPE_A
].primary
>> 8, PLANEA_HI
));
890 FW_WM_VLV(wm
->pipe
[PIPE_B
].sprite
[1], SPRITED
) |
891 FW_WM_VLV(wm
->pipe
[PIPE_B
].sprite
[0], SPRITEC
));
893 FW_WM(wm
->sr
.plane
>> 9, SR_HI
) |
894 FW_WM(wm
->pipe
[PIPE_B
].sprite
[1] >> 8, SPRITED_HI
) |
895 FW_WM(wm
->pipe
[PIPE_B
].sprite
[0] >> 8, SPRITEC_HI
) |
896 FW_WM(wm
->pipe
[PIPE_B
].primary
>> 8, PLANEB_HI
) |
897 FW_WM(wm
->pipe
[PIPE_A
].sprite
[1] >> 8, SPRITEB_HI
) |
898 FW_WM(wm
->pipe
[PIPE_A
].sprite
[0] >> 8, SPRITEA_HI
) |
899 FW_WM(wm
->pipe
[PIPE_A
].primary
>> 8, PLANEA_HI
));
902 /* zero (unused) WM1 watermarks */
903 I915_WRITE(DSPFW4
, 0);
904 I915_WRITE(DSPFW5
, 0);
905 I915_WRITE(DSPFW6
, 0);
906 I915_WRITE(DSPHOWM1
, 0);
908 POSTING_READ(DSPFW1
);
916 VLV_WM_LEVEL_DDR_DVFS
,
919 /* latency must be in 0.1us units. */
920 static unsigned int vlv_wm_method2(unsigned int pixel_rate
,
921 unsigned int pipe_htotal
,
922 unsigned int horiz_pixels
,
924 unsigned int latency
)
928 ret
= (latency
* pixel_rate
) / (pipe_htotal
* 10000);
929 ret
= (ret
+ 1) * horiz_pixels
* cpp
;
930 ret
= DIV_ROUND_UP(ret
, 64);
935 static void vlv_setup_wm_latency(struct drm_device
*dev
)
937 struct drm_i915_private
*dev_priv
= to_i915(dev
);
939 /* all latencies in usec */
940 dev_priv
->wm
.pri_latency
[VLV_WM_LEVEL_PM2
] = 3;
942 dev_priv
->wm
.max_level
= VLV_WM_LEVEL_PM2
;
944 if (IS_CHERRYVIEW(dev_priv
)) {
945 dev_priv
->wm
.pri_latency
[VLV_WM_LEVEL_PM5
] = 12;
946 dev_priv
->wm
.pri_latency
[VLV_WM_LEVEL_DDR_DVFS
] = 33;
948 dev_priv
->wm
.max_level
= VLV_WM_LEVEL_DDR_DVFS
;
952 static uint16_t vlv_compute_wm_level(struct intel_plane
*plane
,
953 struct intel_crtc
*crtc
,
954 const struct intel_plane_state
*state
,
957 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
958 int clock
, htotal
, cpp
, width
, wm
;
960 if (dev_priv
->wm
.pri_latency
[level
] == 0)
966 cpp
= drm_format_plane_cpp(state
->base
.fb
->pixel_format
, 0);
967 clock
= crtc
->config
->base
.adjusted_mode
.crtc_clock
;
968 htotal
= crtc
->config
->base
.adjusted_mode
.crtc_htotal
;
969 width
= crtc
->config
->pipe_src_w
;
970 if (WARN_ON(htotal
== 0))
973 if (plane
->base
.type
== DRM_PLANE_TYPE_CURSOR
) {
975 * FIXME the formula gives values that are
976 * too big for the cursor FIFO, and hence we
977 * would never be able to use cursors. For
978 * now just hardcode the watermark.
982 wm
= vlv_wm_method2(clock
, htotal
, width
, cpp
,
983 dev_priv
->wm
.pri_latency
[level
] * 10);
986 return min_t(int, wm
, USHRT_MAX
);
989 static void vlv_compute_fifo(struct intel_crtc
*crtc
)
991 struct drm_device
*dev
= crtc
->base
.dev
;
992 struct vlv_wm_state
*wm_state
= &crtc
->wm_state
;
993 struct intel_plane
*plane
;
994 unsigned int total_rate
= 0;
995 const int fifo_size
= 512 - 1;
996 int fifo_extra
, fifo_left
= fifo_size
;
998 for_each_intel_plane_on_crtc(dev
, crtc
, plane
) {
999 struct intel_plane_state
*state
=
1000 to_intel_plane_state(plane
->base
.state
);
1002 if (plane
->base
.type
== DRM_PLANE_TYPE_CURSOR
)
1005 if (state
->visible
) {
1006 wm_state
->num_active_planes
++;
1007 total_rate
+= drm_format_plane_cpp(state
->base
.fb
->pixel_format
, 0);
1011 for_each_intel_plane_on_crtc(dev
, crtc
, plane
) {
1012 struct intel_plane_state
*state
=
1013 to_intel_plane_state(plane
->base
.state
);
1016 if (plane
->base
.type
== DRM_PLANE_TYPE_CURSOR
) {
1017 plane
->wm
.fifo_size
= 63;
1021 if (!state
->visible
) {
1022 plane
->wm
.fifo_size
= 0;
1026 rate
= drm_format_plane_cpp(state
->base
.fb
->pixel_format
, 0);
1027 plane
->wm
.fifo_size
= fifo_size
* rate
/ total_rate
;
1028 fifo_left
-= plane
->wm
.fifo_size
;
1031 fifo_extra
= DIV_ROUND_UP(fifo_left
, wm_state
->num_active_planes
?: 1);
1033 /* spread the remainder evenly */
1034 for_each_intel_plane_on_crtc(dev
, crtc
, plane
) {
1040 if (plane
->base
.type
== DRM_PLANE_TYPE_CURSOR
)
1043 /* give it all to the first plane if none are active */
1044 if (plane
->wm
.fifo_size
== 0 &&
1045 wm_state
->num_active_planes
)
1048 plane_extra
= min(fifo_extra
, fifo_left
);
1049 plane
->wm
.fifo_size
+= plane_extra
;
1050 fifo_left
-= plane_extra
;
1053 WARN_ON(fifo_left
!= 0);
1056 static void vlv_invert_wms(struct intel_crtc
*crtc
)
1058 struct vlv_wm_state
*wm_state
= &crtc
->wm_state
;
1061 for (level
= 0; level
< wm_state
->num_levels
; level
++) {
1062 struct drm_device
*dev
= crtc
->base
.dev
;
1063 const int sr_fifo_size
= INTEL_INFO(dev
)->num_pipes
* 512 - 1;
1064 struct intel_plane
*plane
;
1066 wm_state
->sr
[level
].plane
= sr_fifo_size
- wm_state
->sr
[level
].plane
;
1067 wm_state
->sr
[level
].cursor
= 63 - wm_state
->sr
[level
].cursor
;
1069 for_each_intel_plane_on_crtc(dev
, crtc
, plane
) {
1070 switch (plane
->base
.type
) {
1072 case DRM_PLANE_TYPE_CURSOR
:
1073 wm_state
->wm
[level
].cursor
= plane
->wm
.fifo_size
-
1074 wm_state
->wm
[level
].cursor
;
1076 case DRM_PLANE_TYPE_PRIMARY
:
1077 wm_state
->wm
[level
].primary
= plane
->wm
.fifo_size
-
1078 wm_state
->wm
[level
].primary
;
1080 case DRM_PLANE_TYPE_OVERLAY
:
1081 sprite
= plane
->plane
;
1082 wm_state
->wm
[level
].sprite
[sprite
] = plane
->wm
.fifo_size
-
1083 wm_state
->wm
[level
].sprite
[sprite
];
1090 static void vlv_compute_wm(struct intel_crtc
*crtc
)
1092 struct drm_device
*dev
= crtc
->base
.dev
;
1093 struct vlv_wm_state
*wm_state
= &crtc
->wm_state
;
1094 struct intel_plane
*plane
;
1095 int sr_fifo_size
= INTEL_INFO(dev
)->num_pipes
* 512 - 1;
1098 memset(wm_state
, 0, sizeof(*wm_state
));
1100 wm_state
->cxsr
= crtc
->pipe
!= PIPE_C
&& crtc
->wm
.cxsr_allowed
;
1101 wm_state
->num_levels
= to_i915(dev
)->wm
.max_level
+ 1;
1103 wm_state
->num_active_planes
= 0;
1105 vlv_compute_fifo(crtc
);
1107 if (wm_state
->num_active_planes
!= 1)
1108 wm_state
->cxsr
= false;
1110 if (wm_state
->cxsr
) {
1111 for (level
= 0; level
< wm_state
->num_levels
; level
++) {
1112 wm_state
->sr
[level
].plane
= sr_fifo_size
;
1113 wm_state
->sr
[level
].cursor
= 63;
1117 for_each_intel_plane_on_crtc(dev
, crtc
, plane
) {
1118 struct intel_plane_state
*state
=
1119 to_intel_plane_state(plane
->base
.state
);
1121 if (!state
->visible
)
1124 /* normal watermarks */
1125 for (level
= 0; level
< wm_state
->num_levels
; level
++) {
1126 int wm
= vlv_compute_wm_level(plane
, crtc
, state
, level
);
1127 int max_wm
= plane
->base
.type
== DRM_PLANE_TYPE_CURSOR
? 63 : 511;
1130 if (WARN_ON(level
== 0 && wm
> max_wm
))
1133 if (wm
> plane
->wm
.fifo_size
)
1136 switch (plane
->base
.type
) {
1138 case DRM_PLANE_TYPE_CURSOR
:
1139 wm_state
->wm
[level
].cursor
= wm
;
1141 case DRM_PLANE_TYPE_PRIMARY
:
1142 wm_state
->wm
[level
].primary
= wm
;
1144 case DRM_PLANE_TYPE_OVERLAY
:
1145 sprite
= plane
->plane
;
1146 wm_state
->wm
[level
].sprite
[sprite
] = wm
;
1151 wm_state
->num_levels
= level
;
1153 if (!wm_state
->cxsr
)
1156 /* maxfifo watermarks */
1157 switch (plane
->base
.type
) {
1159 case DRM_PLANE_TYPE_CURSOR
:
1160 for (level
= 0; level
< wm_state
->num_levels
; level
++)
1161 wm_state
->sr
[level
].cursor
=
1162 wm_state
->wm
[level
].cursor
;
1164 case DRM_PLANE_TYPE_PRIMARY
:
1165 for (level
= 0; level
< wm_state
->num_levels
; level
++)
1166 wm_state
->sr
[level
].plane
=
1167 min(wm_state
->sr
[level
].plane
,
1168 wm_state
->wm
[level
].primary
);
1170 case DRM_PLANE_TYPE_OVERLAY
:
1171 sprite
= plane
->plane
;
1172 for (level
= 0; level
< wm_state
->num_levels
; level
++)
1173 wm_state
->sr
[level
].plane
=
1174 min(wm_state
->sr
[level
].plane
,
1175 wm_state
->wm
[level
].sprite
[sprite
]);
1180 /* clear any (partially) filled invalid levels */
1181 for (level
= wm_state
->num_levels
; level
< to_i915(dev
)->wm
.max_level
+ 1; level
++) {
1182 memset(&wm_state
->wm
[level
], 0, sizeof(wm_state
->wm
[level
]));
1183 memset(&wm_state
->sr
[level
], 0, sizeof(wm_state
->sr
[level
]));
1186 vlv_invert_wms(crtc
);
1189 #define VLV_FIFO(plane, value) \
1190 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1192 static void vlv_pipe_set_fifo_size(struct intel_crtc
*crtc
)
1194 struct drm_device
*dev
= crtc
->base
.dev
;
1195 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1196 struct intel_plane
*plane
;
1197 int sprite0_start
= 0, sprite1_start
= 0, fifo_size
= 0;
1199 for_each_intel_plane_on_crtc(dev
, crtc
, plane
) {
1200 if (plane
->base
.type
== DRM_PLANE_TYPE_CURSOR
) {
1201 WARN_ON(plane
->wm
.fifo_size
!= 63);
1205 if (plane
->base
.type
== DRM_PLANE_TYPE_PRIMARY
)
1206 sprite0_start
= plane
->wm
.fifo_size
;
1207 else if (plane
->plane
== 0)
1208 sprite1_start
= sprite0_start
+ plane
->wm
.fifo_size
;
1210 fifo_size
= sprite1_start
+ plane
->wm
.fifo_size
;
1213 WARN_ON(fifo_size
!= 512 - 1);
1215 DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1216 pipe_name(crtc
->pipe
), sprite0_start
,
1217 sprite1_start
, fifo_size
);
1219 switch (crtc
->pipe
) {
1220 uint32_t dsparb
, dsparb2
, dsparb3
;
1222 dsparb
= I915_READ(DSPARB
);
1223 dsparb2
= I915_READ(DSPARB2
);
1225 dsparb
&= ~(VLV_FIFO(SPRITEA
, 0xff) |
1226 VLV_FIFO(SPRITEB
, 0xff));
1227 dsparb
|= (VLV_FIFO(SPRITEA
, sprite0_start
) |
1228 VLV_FIFO(SPRITEB
, sprite1_start
));
1230 dsparb2
&= ~(VLV_FIFO(SPRITEA_HI
, 0x1) |
1231 VLV_FIFO(SPRITEB_HI
, 0x1));
1232 dsparb2
|= (VLV_FIFO(SPRITEA_HI
, sprite0_start
>> 8) |
1233 VLV_FIFO(SPRITEB_HI
, sprite1_start
>> 8));
1235 I915_WRITE(DSPARB
, dsparb
);
1236 I915_WRITE(DSPARB2
, dsparb2
);
1239 dsparb
= I915_READ(DSPARB
);
1240 dsparb2
= I915_READ(DSPARB2
);
1242 dsparb
&= ~(VLV_FIFO(SPRITEC
, 0xff) |
1243 VLV_FIFO(SPRITED
, 0xff));
1244 dsparb
|= (VLV_FIFO(SPRITEC
, sprite0_start
) |
1245 VLV_FIFO(SPRITED
, sprite1_start
));
1247 dsparb2
&= ~(VLV_FIFO(SPRITEC_HI
, 0xff) |
1248 VLV_FIFO(SPRITED_HI
, 0xff));
1249 dsparb2
|= (VLV_FIFO(SPRITEC_HI
, sprite0_start
>> 8) |
1250 VLV_FIFO(SPRITED_HI
, sprite1_start
>> 8));
1252 I915_WRITE(DSPARB
, dsparb
);
1253 I915_WRITE(DSPARB2
, dsparb2
);
1256 dsparb3
= I915_READ(DSPARB3
);
1257 dsparb2
= I915_READ(DSPARB2
);
1259 dsparb3
&= ~(VLV_FIFO(SPRITEE
, 0xff) |
1260 VLV_FIFO(SPRITEF
, 0xff));
1261 dsparb3
|= (VLV_FIFO(SPRITEE
, sprite0_start
) |
1262 VLV_FIFO(SPRITEF
, sprite1_start
));
1264 dsparb2
&= ~(VLV_FIFO(SPRITEE_HI
, 0xff) |
1265 VLV_FIFO(SPRITEF_HI
, 0xff));
1266 dsparb2
|= (VLV_FIFO(SPRITEE_HI
, sprite0_start
>> 8) |
1267 VLV_FIFO(SPRITEF_HI
, sprite1_start
>> 8));
1269 I915_WRITE(DSPARB3
, dsparb3
);
1270 I915_WRITE(DSPARB2
, dsparb2
);
1279 static void vlv_merge_wm(struct drm_device
*dev
,
1280 struct vlv_wm_values
*wm
)
1282 struct intel_crtc
*crtc
;
1283 int num_active_crtcs
= 0;
1285 wm
->level
= to_i915(dev
)->wm
.max_level
;
1288 for_each_intel_crtc(dev
, crtc
) {
1289 const struct vlv_wm_state
*wm_state
= &crtc
->wm_state
;
1294 if (!wm_state
->cxsr
)
1298 wm
->level
= min_t(int, wm
->level
, wm_state
->num_levels
- 1);
1301 if (num_active_crtcs
!= 1)
1304 if (num_active_crtcs
> 1)
1305 wm
->level
= VLV_WM_LEVEL_PM2
;
1307 for_each_intel_crtc(dev
, crtc
) {
1308 struct vlv_wm_state
*wm_state
= &crtc
->wm_state
;
1309 enum pipe pipe
= crtc
->pipe
;
1314 wm
->pipe
[pipe
] = wm_state
->wm
[wm
->level
];
1316 wm
->sr
= wm_state
->sr
[wm
->level
];
1318 wm
->ddl
[pipe
].primary
= DDL_PRECISION_HIGH
| 2;
1319 wm
->ddl
[pipe
].sprite
[0] = DDL_PRECISION_HIGH
| 2;
1320 wm
->ddl
[pipe
].sprite
[1] = DDL_PRECISION_HIGH
| 2;
1321 wm
->ddl
[pipe
].cursor
= DDL_PRECISION_HIGH
| 2;
1325 static void vlv_update_wm(struct drm_crtc
*crtc
)
1327 struct drm_device
*dev
= crtc
->dev
;
1328 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1329 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1330 enum pipe pipe
= intel_crtc
->pipe
;
1331 struct vlv_wm_values wm
= {};
1333 vlv_compute_wm(intel_crtc
);
1334 vlv_merge_wm(dev
, &wm
);
1336 if (memcmp(&dev_priv
->wm
.vlv
, &wm
, sizeof(wm
)) == 0) {
1337 /* FIXME should be part of crtc atomic commit */
1338 vlv_pipe_set_fifo_size(intel_crtc
);
1342 if (wm
.level
< VLV_WM_LEVEL_DDR_DVFS
&&
1343 dev_priv
->wm
.vlv
.level
>= VLV_WM_LEVEL_DDR_DVFS
)
1344 chv_set_memory_dvfs(dev_priv
, false);
1346 if (wm
.level
< VLV_WM_LEVEL_PM5
&&
1347 dev_priv
->wm
.vlv
.level
>= VLV_WM_LEVEL_PM5
)
1348 chv_set_memory_pm5(dev_priv
, false);
1350 if (!wm
.cxsr
&& dev_priv
->wm
.vlv
.cxsr
)
1351 intel_set_memory_cxsr(dev_priv
, false);
1353 /* FIXME should be part of crtc atomic commit */
1354 vlv_pipe_set_fifo_size(intel_crtc
);
1356 vlv_write_wm_values(intel_crtc
, &wm
);
1358 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1359 "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1360 pipe_name(pipe
), wm
.pipe
[pipe
].primary
, wm
.pipe
[pipe
].cursor
,
1361 wm
.pipe
[pipe
].sprite
[0], wm
.pipe
[pipe
].sprite
[1],
1362 wm
.sr
.plane
, wm
.sr
.cursor
, wm
.level
, wm
.cxsr
);
1364 if (wm
.cxsr
&& !dev_priv
->wm
.vlv
.cxsr
)
1365 intel_set_memory_cxsr(dev_priv
, true);
1367 if (wm
.level
>= VLV_WM_LEVEL_PM5
&&
1368 dev_priv
->wm
.vlv
.level
< VLV_WM_LEVEL_PM5
)
1369 chv_set_memory_pm5(dev_priv
, true);
1371 if (wm
.level
>= VLV_WM_LEVEL_DDR_DVFS
&&
1372 dev_priv
->wm
.vlv
.level
< VLV_WM_LEVEL_DDR_DVFS
)
1373 chv_set_memory_dvfs(dev_priv
, true);
1375 dev_priv
->wm
.vlv
= wm
;
1378 #define single_plane_enabled(mask) is_power_of_2(mask)
1380 static void g4x_update_wm(struct drm_crtc
*crtc
)
1382 struct drm_device
*dev
= crtc
->dev
;
1383 static const int sr_latency_ns
= 12000;
1384 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1385 int planea_wm
, planeb_wm
, cursora_wm
, cursorb_wm
;
1386 int plane_sr
, cursor_sr
;
1387 unsigned int enabled
= 0;
1390 if (g4x_compute_wm0(dev
, PIPE_A
,
1391 &g4x_wm_info
, pessimal_latency_ns
,
1392 &g4x_cursor_wm_info
, pessimal_latency_ns
,
1393 &planea_wm
, &cursora_wm
))
1394 enabled
|= 1 << PIPE_A
;
1396 if (g4x_compute_wm0(dev
, PIPE_B
,
1397 &g4x_wm_info
, pessimal_latency_ns
,
1398 &g4x_cursor_wm_info
, pessimal_latency_ns
,
1399 &planeb_wm
, &cursorb_wm
))
1400 enabled
|= 1 << PIPE_B
;
1402 if (single_plane_enabled(enabled
) &&
1403 g4x_compute_srwm(dev
, ffs(enabled
) - 1,
1406 &g4x_cursor_wm_info
,
1407 &plane_sr
, &cursor_sr
)) {
1408 cxsr_enabled
= true;
1410 cxsr_enabled
= false;
1411 intel_set_memory_cxsr(dev_priv
, false);
1412 plane_sr
= cursor_sr
= 0;
1415 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1416 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1417 planea_wm
, cursora_wm
,
1418 planeb_wm
, cursorb_wm
,
1419 plane_sr
, cursor_sr
);
1422 FW_WM(plane_sr
, SR
) |
1423 FW_WM(cursorb_wm
, CURSORB
) |
1424 FW_WM(planeb_wm
, PLANEB
) |
1425 FW_WM(planea_wm
, PLANEA
));
1427 (I915_READ(DSPFW2
) & ~DSPFW_CURSORA_MASK
) |
1428 FW_WM(cursora_wm
, CURSORA
));
1429 /* HPLL off in SR has some issues on G4x... disable it */
1431 (I915_READ(DSPFW3
) & ~(DSPFW_HPLL_SR_EN
| DSPFW_CURSOR_SR_MASK
)) |
1432 FW_WM(cursor_sr
, CURSOR_SR
));
1435 intel_set_memory_cxsr(dev_priv
, true);
1438 static void i965_update_wm(struct drm_crtc
*unused_crtc
)
1440 struct drm_device
*dev
= unused_crtc
->dev
;
1441 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1442 struct drm_crtc
*crtc
;
1447 /* Calc sr entries for one plane configs */
1448 crtc
= single_enabled_crtc(dev
);
1450 /* self-refresh has much higher latency */
1451 static const int sr_latency_ns
= 12000;
1452 const struct drm_display_mode
*adjusted_mode
= &to_intel_crtc(crtc
)->config
->base
.adjusted_mode
;
1453 int clock
= adjusted_mode
->crtc_clock
;
1454 int htotal
= adjusted_mode
->crtc_htotal
;
1455 int hdisplay
= to_intel_crtc(crtc
)->config
->pipe_src_w
;
1456 int cpp
= drm_format_plane_cpp(crtc
->primary
->state
->fb
->pixel_format
, 0);
1457 unsigned long line_time_us
;
1460 line_time_us
= max(htotal
* 1000 / clock
, 1);
1462 /* Use ns/us then divide to preserve precision */
1463 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
1465 entries
= DIV_ROUND_UP(entries
, I915_FIFO_LINE_SIZE
);
1466 srwm
= I965_FIFO_SIZE
- entries
;
1470 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1473 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
1474 cpp
* crtc
->cursor
->state
->crtc_w
;
1475 entries
= DIV_ROUND_UP(entries
,
1476 i965_cursor_wm_info
.cacheline_size
);
1477 cursor_sr
= i965_cursor_wm_info
.fifo_size
-
1478 (entries
+ i965_cursor_wm_info
.guard_size
);
1480 if (cursor_sr
> i965_cursor_wm_info
.max_wm
)
1481 cursor_sr
= i965_cursor_wm_info
.max_wm
;
1483 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1484 "cursor %d\n", srwm
, cursor_sr
);
1486 cxsr_enabled
= true;
1488 cxsr_enabled
= false;
1489 /* Turn off self refresh if both pipes are enabled */
1490 intel_set_memory_cxsr(dev_priv
, false);
1493 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1496 /* 965 has limitations... */
1497 I915_WRITE(DSPFW1
, FW_WM(srwm
, SR
) |
1501 I915_WRITE(DSPFW2
, FW_WM(8, CURSORA
) |
1502 FW_WM(8, PLANEC_OLD
));
1503 /* update cursor SR watermark */
1504 I915_WRITE(DSPFW3
, FW_WM(cursor_sr
, CURSOR_SR
));
1507 intel_set_memory_cxsr(dev_priv
, true);
1512 static void i9xx_update_wm(struct drm_crtc
*unused_crtc
)
1514 struct drm_device
*dev
= unused_crtc
->dev
;
1515 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1516 const struct intel_watermark_params
*wm_info
;
1521 int planea_wm
, planeb_wm
;
1522 struct drm_crtc
*crtc
, *enabled
= NULL
;
1525 wm_info
= &i945_wm_info
;
1526 else if (!IS_GEN2(dev
))
1527 wm_info
= &i915_wm_info
;
1529 wm_info
= &i830_a_wm_info
;
1531 fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 0);
1532 crtc
= intel_get_crtc_for_plane(dev
, 0);
1533 if (intel_crtc_active(crtc
)) {
1534 const struct drm_display_mode
*adjusted_mode
;
1535 int cpp
= drm_format_plane_cpp(crtc
->primary
->state
->fb
->pixel_format
, 0);
1539 adjusted_mode
= &to_intel_crtc(crtc
)->config
->base
.adjusted_mode
;
1540 planea_wm
= intel_calculate_wm(adjusted_mode
->crtc_clock
,
1541 wm_info
, fifo_size
, cpp
,
1542 pessimal_latency_ns
);
1545 planea_wm
= fifo_size
- wm_info
->guard_size
;
1546 if (planea_wm
> (long)wm_info
->max_wm
)
1547 planea_wm
= wm_info
->max_wm
;
1551 wm_info
= &i830_bc_wm_info
;
1553 fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 1);
1554 crtc
= intel_get_crtc_for_plane(dev
, 1);
1555 if (intel_crtc_active(crtc
)) {
1556 const struct drm_display_mode
*adjusted_mode
;
1557 int cpp
= drm_format_plane_cpp(crtc
->primary
->state
->fb
->pixel_format
, 0);
1561 adjusted_mode
= &to_intel_crtc(crtc
)->config
->base
.adjusted_mode
;
1562 planeb_wm
= intel_calculate_wm(adjusted_mode
->crtc_clock
,
1563 wm_info
, fifo_size
, cpp
,
1564 pessimal_latency_ns
);
1565 if (enabled
== NULL
)
1570 planeb_wm
= fifo_size
- wm_info
->guard_size
;
1571 if (planeb_wm
> (long)wm_info
->max_wm
)
1572 planeb_wm
= wm_info
->max_wm
;
1575 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm
, planeb_wm
);
1577 if (IS_I915GM(dev
) && enabled
) {
1578 struct drm_i915_gem_object
*obj
;
1580 obj
= intel_fb_obj(enabled
->primary
->state
->fb
);
1582 /* self-refresh seems busted with untiled */
1583 if (obj
->tiling_mode
== I915_TILING_NONE
)
1588 * Overlay gets an aggressive default since video jitter is bad.
1592 /* Play safe and disable self-refresh before adjusting watermarks. */
1593 intel_set_memory_cxsr(dev_priv
, false);
1595 /* Calc sr entries for one plane configs */
1596 if (HAS_FW_BLC(dev
) && enabled
) {
1597 /* self-refresh has much higher latency */
1598 static const int sr_latency_ns
= 6000;
1599 const struct drm_display_mode
*adjusted_mode
= &to_intel_crtc(enabled
)->config
->base
.adjusted_mode
;
1600 int clock
= adjusted_mode
->crtc_clock
;
1601 int htotal
= adjusted_mode
->crtc_htotal
;
1602 int hdisplay
= to_intel_crtc(enabled
)->config
->pipe_src_w
;
1603 int cpp
= drm_format_plane_cpp(enabled
->primary
->state
->fb
->pixel_format
, 0);
1604 unsigned long line_time_us
;
1607 line_time_us
= max(htotal
* 1000 / clock
, 1);
1609 /* Use ns/us then divide to preserve precision */
1610 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
1612 entries
= DIV_ROUND_UP(entries
, wm_info
->cacheline_size
);
1613 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries
);
1614 srwm
= wm_info
->fifo_size
- entries
;
1618 if (IS_I945G(dev
) || IS_I945GM(dev
))
1619 I915_WRITE(FW_BLC_SELF
,
1620 FW_BLC_SELF_FIFO_MASK
| (srwm
& 0xff));
1621 else if (IS_I915GM(dev
))
1622 I915_WRITE(FW_BLC_SELF
, srwm
& 0x3f);
1625 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1626 planea_wm
, planeb_wm
, cwm
, srwm
);
1628 fwater_lo
= ((planeb_wm
& 0x3f) << 16) | (planea_wm
& 0x3f);
1629 fwater_hi
= (cwm
& 0x1f);
1631 /* Set request length to 8 cachelines per fetch */
1632 fwater_lo
= fwater_lo
| (1 << 24) | (1 << 8);
1633 fwater_hi
= fwater_hi
| (1 << 8);
1635 I915_WRITE(FW_BLC
, fwater_lo
);
1636 I915_WRITE(FW_BLC2
, fwater_hi
);
1639 intel_set_memory_cxsr(dev_priv
, true);
1642 static void i845_update_wm(struct drm_crtc
*unused_crtc
)
1644 struct drm_device
*dev
= unused_crtc
->dev
;
1645 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1646 struct drm_crtc
*crtc
;
1647 const struct drm_display_mode
*adjusted_mode
;
1651 crtc
= single_enabled_crtc(dev
);
1655 adjusted_mode
= &to_intel_crtc(crtc
)->config
->base
.adjusted_mode
;
1656 planea_wm
= intel_calculate_wm(adjusted_mode
->crtc_clock
,
1658 dev_priv
->display
.get_fifo_size(dev
, 0),
1659 4, pessimal_latency_ns
);
1660 fwater_lo
= I915_READ(FW_BLC
) & ~0xfff;
1661 fwater_lo
|= (3<<8) | planea_wm
;
1663 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm
);
1665 I915_WRITE(FW_BLC
, fwater_lo
);
1668 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state
*pipe_config
)
1670 uint32_t pixel_rate
;
1672 pixel_rate
= pipe_config
->base
.adjusted_mode
.crtc_clock
;
1674 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1675 * adjust the pixel_rate here. */
1677 if (pipe_config
->pch_pfit
.enabled
) {
1678 uint64_t pipe_w
, pipe_h
, pfit_w
, pfit_h
;
1679 uint32_t pfit_size
= pipe_config
->pch_pfit
.size
;
1681 pipe_w
= pipe_config
->pipe_src_w
;
1682 pipe_h
= pipe_config
->pipe_src_h
;
1684 pfit_w
= (pfit_size
>> 16) & 0xFFFF;
1685 pfit_h
= pfit_size
& 0xFFFF;
1686 if (pipe_w
< pfit_w
)
1688 if (pipe_h
< pfit_h
)
1691 if (WARN_ON(!pfit_w
|| !pfit_h
))
1694 pixel_rate
= div_u64((uint64_t) pixel_rate
* pipe_w
* pipe_h
,
1701 /* latency must be in 0.1us units. */
1702 static uint32_t ilk_wm_method1(uint32_t pixel_rate
, uint8_t cpp
, uint32_t latency
)
1706 if (WARN(latency
== 0, "Latency value missing\n"))
1709 ret
= (uint64_t) pixel_rate
* cpp
* latency
;
1710 ret
= DIV_ROUND_UP_ULL(ret
, 64 * 10000) + 2;
1715 /* latency must be in 0.1us units. */
1716 static uint32_t ilk_wm_method2(uint32_t pixel_rate
, uint32_t pipe_htotal
,
1717 uint32_t horiz_pixels
, uint8_t cpp
,
1722 if (WARN(latency
== 0, "Latency value missing\n"))
1724 if (WARN_ON(!pipe_htotal
))
1727 ret
= (latency
* pixel_rate
) / (pipe_htotal
* 10000);
1728 ret
= (ret
+ 1) * horiz_pixels
* cpp
;
1729 ret
= DIV_ROUND_UP(ret
, 64) + 2;
1733 static uint32_t ilk_wm_fbc(uint32_t pri_val
, uint32_t horiz_pixels
,
1737 * Neither of these should be possible since this function shouldn't be
1738 * called if the CRTC is off or the plane is invisible. But let's be
1739 * extra paranoid to avoid a potential divide-by-zero if we screw up
1740 * elsewhere in the driver.
1744 if (WARN_ON(!horiz_pixels
))
1747 return DIV_ROUND_UP(pri_val
* 64, horiz_pixels
* cpp
) + 2;
1750 struct ilk_wm_maximums
{
1758 * For both WM_PIPE and WM_LP.
1759 * mem_value must be in 0.1us units.
1761 static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state
*cstate
,
1762 const struct intel_plane_state
*pstate
,
1766 int cpp
= pstate
->base
.fb
?
1767 drm_format_plane_cpp(pstate
->base
.fb
->pixel_format
, 0) : 0;
1768 uint32_t method1
, method2
;
1770 if (!cstate
->base
.active
|| !pstate
->visible
)
1773 method1
= ilk_wm_method1(ilk_pipe_pixel_rate(cstate
), cpp
, mem_value
);
1778 method2
= ilk_wm_method2(ilk_pipe_pixel_rate(cstate
),
1779 cstate
->base
.adjusted_mode
.crtc_htotal
,
1780 drm_rect_width(&pstate
->dst
),
1783 return min(method1
, method2
);
1787 * For both WM_PIPE and WM_LP.
1788 * mem_value must be in 0.1us units.
1790 static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state
*cstate
,
1791 const struct intel_plane_state
*pstate
,
1794 int cpp
= pstate
->base
.fb
?
1795 drm_format_plane_cpp(pstate
->base
.fb
->pixel_format
, 0) : 0;
1796 uint32_t method1
, method2
;
1798 if (!cstate
->base
.active
|| !pstate
->visible
)
1801 method1
= ilk_wm_method1(ilk_pipe_pixel_rate(cstate
), cpp
, mem_value
);
1802 method2
= ilk_wm_method2(ilk_pipe_pixel_rate(cstate
),
1803 cstate
->base
.adjusted_mode
.crtc_htotal
,
1804 drm_rect_width(&pstate
->dst
),
1806 return min(method1
, method2
);
1810 * For both WM_PIPE and WM_LP.
1811 * mem_value must be in 0.1us units.
1813 static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state
*cstate
,
1814 const struct intel_plane_state
*pstate
,
1818 * We treat the cursor plane as always-on for the purposes of watermark
1819 * calculation. Until we have two-stage watermark programming merged,
1820 * this is necessary to avoid flickering.
1823 int width
= pstate
->visible
? pstate
->base
.crtc_w
: 64;
1825 if (!cstate
->base
.active
)
1828 return ilk_wm_method2(ilk_pipe_pixel_rate(cstate
),
1829 cstate
->base
.adjusted_mode
.crtc_htotal
,
1830 width
, cpp
, mem_value
);
1833 /* Only for WM_LP. */
1834 static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state
*cstate
,
1835 const struct intel_plane_state
*pstate
,
1838 int cpp
= pstate
->base
.fb
?
1839 drm_format_plane_cpp(pstate
->base
.fb
->pixel_format
, 0) : 0;
1841 if (!cstate
->base
.active
|| !pstate
->visible
)
1844 return ilk_wm_fbc(pri_val
, drm_rect_width(&pstate
->dst
), cpp
);
1847 static unsigned int ilk_display_fifo_size(const struct drm_device
*dev
)
1849 if (INTEL_INFO(dev
)->gen
>= 8)
1851 else if (INTEL_INFO(dev
)->gen
>= 7)
1857 static unsigned int ilk_plane_wm_reg_max(const struct drm_device
*dev
,
1858 int level
, bool is_sprite
)
1860 if (INTEL_INFO(dev
)->gen
>= 8)
1861 /* BDW primary/sprite plane watermarks */
1862 return level
== 0 ? 255 : 2047;
1863 else if (INTEL_INFO(dev
)->gen
>= 7)
1864 /* IVB/HSW primary/sprite plane watermarks */
1865 return level
== 0 ? 127 : 1023;
1866 else if (!is_sprite
)
1867 /* ILK/SNB primary plane watermarks */
1868 return level
== 0 ? 127 : 511;
1870 /* ILK/SNB sprite plane watermarks */
1871 return level
== 0 ? 63 : 255;
1874 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device
*dev
,
1877 if (INTEL_INFO(dev
)->gen
>= 7)
1878 return level
== 0 ? 63 : 255;
1880 return level
== 0 ? 31 : 63;
1883 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device
*dev
)
1885 if (INTEL_INFO(dev
)->gen
>= 8)
1891 /* Calculate the maximum primary/sprite plane watermark */
1892 static unsigned int ilk_plane_wm_max(const struct drm_device
*dev
,
1894 const struct intel_wm_config
*config
,
1895 enum intel_ddb_partitioning ddb_partitioning
,
1898 unsigned int fifo_size
= ilk_display_fifo_size(dev
);
1900 /* if sprites aren't enabled, sprites get nothing */
1901 if (is_sprite
&& !config
->sprites_enabled
)
1904 /* HSW allows LP1+ watermarks even with multiple pipes */
1905 if (level
== 0 || config
->num_pipes_active
> 1) {
1906 fifo_size
/= INTEL_INFO(dev
)->num_pipes
;
1909 * For some reason the non self refresh
1910 * FIFO size is only half of the self
1911 * refresh FIFO size on ILK/SNB.
1913 if (INTEL_INFO(dev
)->gen
<= 6)
1917 if (config
->sprites_enabled
) {
1918 /* level 0 is always calculated with 1:1 split */
1919 if (level
> 0 && ddb_partitioning
== INTEL_DDB_PART_5_6
) {
1928 /* clamp to max that the registers can hold */
1929 return min(fifo_size
, ilk_plane_wm_reg_max(dev
, level
, is_sprite
));
1932 /* Calculate the maximum cursor plane watermark */
1933 static unsigned int ilk_cursor_wm_max(const struct drm_device
*dev
,
1935 const struct intel_wm_config
*config
)
1937 /* HSW LP1+ watermarks w/ multiple pipes */
1938 if (level
> 0 && config
->num_pipes_active
> 1)
1941 /* otherwise just report max that registers can hold */
1942 return ilk_cursor_wm_reg_max(dev
, level
);
1945 static void ilk_compute_wm_maximums(const struct drm_device
*dev
,
1947 const struct intel_wm_config
*config
,
1948 enum intel_ddb_partitioning ddb_partitioning
,
1949 struct ilk_wm_maximums
*max
)
1951 max
->pri
= ilk_plane_wm_max(dev
, level
, config
, ddb_partitioning
, false);
1952 max
->spr
= ilk_plane_wm_max(dev
, level
, config
, ddb_partitioning
, true);
1953 max
->cur
= ilk_cursor_wm_max(dev
, level
, config
);
1954 max
->fbc
= ilk_fbc_wm_reg_max(dev
);
1957 static void ilk_compute_wm_reg_maximums(struct drm_device
*dev
,
1959 struct ilk_wm_maximums
*max
)
1961 max
->pri
= ilk_plane_wm_reg_max(dev
, level
, false);
1962 max
->spr
= ilk_plane_wm_reg_max(dev
, level
, true);
1963 max
->cur
= ilk_cursor_wm_reg_max(dev
, level
);
1964 max
->fbc
= ilk_fbc_wm_reg_max(dev
);
1967 static bool ilk_validate_wm_level(int level
,
1968 const struct ilk_wm_maximums
*max
,
1969 struct intel_wm_level
*result
)
1973 /* already determined to be invalid? */
1974 if (!result
->enable
)
1977 result
->enable
= result
->pri_val
<= max
->pri
&&
1978 result
->spr_val
<= max
->spr
&&
1979 result
->cur_val
<= max
->cur
;
1981 ret
= result
->enable
;
1984 * HACK until we can pre-compute everything,
1985 * and thus fail gracefully if LP0 watermarks
1988 if (level
== 0 && !result
->enable
) {
1989 if (result
->pri_val
> max
->pri
)
1990 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1991 level
, result
->pri_val
, max
->pri
);
1992 if (result
->spr_val
> max
->spr
)
1993 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1994 level
, result
->spr_val
, max
->spr
);
1995 if (result
->cur_val
> max
->cur
)
1996 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1997 level
, result
->cur_val
, max
->cur
);
1999 result
->pri_val
= min_t(uint32_t, result
->pri_val
, max
->pri
);
2000 result
->spr_val
= min_t(uint32_t, result
->spr_val
, max
->spr
);
2001 result
->cur_val
= min_t(uint32_t, result
->cur_val
, max
->cur
);
2002 result
->enable
= true;
2008 static void ilk_compute_wm_level(const struct drm_i915_private
*dev_priv
,
2009 const struct intel_crtc
*intel_crtc
,
2011 struct intel_crtc_state
*cstate
,
2012 struct intel_plane_state
*pristate
,
2013 struct intel_plane_state
*sprstate
,
2014 struct intel_plane_state
*curstate
,
2015 struct intel_wm_level
*result
)
2017 uint16_t pri_latency
= dev_priv
->wm
.pri_latency
[level
];
2018 uint16_t spr_latency
= dev_priv
->wm
.spr_latency
[level
];
2019 uint16_t cur_latency
= dev_priv
->wm
.cur_latency
[level
];
2021 /* WM1+ latency values stored in 0.5us units */
2029 result
->pri_val
= ilk_compute_pri_wm(cstate
, pristate
,
2030 pri_latency
, level
);
2031 result
->fbc_val
= ilk_compute_fbc_wm(cstate
, pristate
, result
->pri_val
);
2035 result
->spr_val
= ilk_compute_spr_wm(cstate
, sprstate
, spr_latency
);
2038 result
->cur_val
= ilk_compute_cur_wm(cstate
, curstate
, cur_latency
);
2040 result
->enable
= true;
2044 hsw_compute_linetime_wm(const struct intel_crtc_state
*cstate
)
2046 const struct intel_atomic_state
*intel_state
=
2047 to_intel_atomic_state(cstate
->base
.state
);
2048 const struct drm_display_mode
*adjusted_mode
=
2049 &cstate
->base
.adjusted_mode
;
2050 u32 linetime
, ips_linetime
;
2052 if (!cstate
->base
.active
)
2054 if (WARN_ON(adjusted_mode
->crtc_clock
== 0))
2056 if (WARN_ON(intel_state
->cdclk
== 0))
2059 /* The WM are computed with base on how long it takes to fill a single
2060 * row at the given clock rate, multiplied by 8.
2062 linetime
= DIV_ROUND_CLOSEST(adjusted_mode
->crtc_htotal
* 1000 * 8,
2063 adjusted_mode
->crtc_clock
);
2064 ips_linetime
= DIV_ROUND_CLOSEST(adjusted_mode
->crtc_htotal
* 1000 * 8,
2065 intel_state
->cdclk
);
2067 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime
) |
2068 PIPE_WM_LINETIME_TIME(linetime
);
2071 static void intel_read_wm_latency(struct drm_device
*dev
, uint16_t wm
[8])
2073 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2078 int level
, max_level
= ilk_wm_max_level(dev
);
2080 /* read the first set of memory latencies[0:3] */
2081 val
= 0; /* data0 to be programmed to 0 for first set */
2082 mutex_lock(&dev_priv
->rps
.hw_lock
);
2083 ret
= sandybridge_pcode_read(dev_priv
,
2084 GEN9_PCODE_READ_MEM_LATENCY
,
2086 mutex_unlock(&dev_priv
->rps
.hw_lock
);
2089 DRM_ERROR("SKL Mailbox read error = %d\n", ret
);
2093 wm
[0] = val
& GEN9_MEM_LATENCY_LEVEL_MASK
;
2094 wm
[1] = (val
>> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT
) &
2095 GEN9_MEM_LATENCY_LEVEL_MASK
;
2096 wm
[2] = (val
>> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT
) &
2097 GEN9_MEM_LATENCY_LEVEL_MASK
;
2098 wm
[3] = (val
>> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT
) &
2099 GEN9_MEM_LATENCY_LEVEL_MASK
;
2101 /* read the second set of memory latencies[4:7] */
2102 val
= 1; /* data0 to be programmed to 1 for second set */
2103 mutex_lock(&dev_priv
->rps
.hw_lock
);
2104 ret
= sandybridge_pcode_read(dev_priv
,
2105 GEN9_PCODE_READ_MEM_LATENCY
,
2107 mutex_unlock(&dev_priv
->rps
.hw_lock
);
2109 DRM_ERROR("SKL Mailbox read error = %d\n", ret
);
2113 wm
[4] = val
& GEN9_MEM_LATENCY_LEVEL_MASK
;
2114 wm
[5] = (val
>> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT
) &
2115 GEN9_MEM_LATENCY_LEVEL_MASK
;
2116 wm
[6] = (val
>> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT
) &
2117 GEN9_MEM_LATENCY_LEVEL_MASK
;
2118 wm
[7] = (val
>> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT
) &
2119 GEN9_MEM_LATENCY_LEVEL_MASK
;
2122 * WaWmMemoryReadLatency:skl
2124 * punit doesn't take into account the read latency so we need
2125 * to add 2us to the various latency levels we retrieve from
2127 * - W0 is a bit special in that it's the only level that
2128 * can't be disabled if we want to have display working, so
2129 * we always add 2us there.
2130 * - For levels >=1, punit returns 0us latency when they are
2131 * disabled, so we respect that and don't add 2us then
2133 * Additionally, if a level n (n > 1) has a 0us latency, all
2134 * levels m (m >= n) need to be disabled. We make sure to
2135 * sanitize the values out of the punit to satisfy this
2139 for (level
= 1; level
<= max_level
; level
++)
2143 for (i
= level
+ 1; i
<= max_level
; i
++)
2148 } else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2149 uint64_t sskpd
= I915_READ64(MCH_SSKPD
);
2151 wm
[0] = (sskpd
>> 56) & 0xFF;
2153 wm
[0] = sskpd
& 0xF;
2154 wm
[1] = (sskpd
>> 4) & 0xFF;
2155 wm
[2] = (sskpd
>> 12) & 0xFF;
2156 wm
[3] = (sskpd
>> 20) & 0x1FF;
2157 wm
[4] = (sskpd
>> 32) & 0x1FF;
2158 } else if (INTEL_INFO(dev
)->gen
>= 6) {
2159 uint32_t sskpd
= I915_READ(MCH_SSKPD
);
2161 wm
[0] = (sskpd
>> SSKPD_WM0_SHIFT
) & SSKPD_WM_MASK
;
2162 wm
[1] = (sskpd
>> SSKPD_WM1_SHIFT
) & SSKPD_WM_MASK
;
2163 wm
[2] = (sskpd
>> SSKPD_WM2_SHIFT
) & SSKPD_WM_MASK
;
2164 wm
[3] = (sskpd
>> SSKPD_WM3_SHIFT
) & SSKPD_WM_MASK
;
2165 } else if (INTEL_INFO(dev
)->gen
>= 5) {
2166 uint32_t mltr
= I915_READ(MLTR_ILK
);
2168 /* ILK primary LP0 latency is 700 ns */
2170 wm
[1] = (mltr
>> MLTR_WM1_SHIFT
) & ILK_SRLT_MASK
;
2171 wm
[2] = (mltr
>> MLTR_WM2_SHIFT
) & ILK_SRLT_MASK
;
2175 static void intel_fixup_spr_wm_latency(struct drm_device
*dev
, uint16_t wm
[5])
2177 /* ILK sprite LP0 latency is 1300 ns */
2182 static void intel_fixup_cur_wm_latency(struct drm_device
*dev
, uint16_t wm
[5])
2184 /* ILK cursor LP0 latency is 1300 ns */
2188 /* WaDoubleCursorLP3Latency:ivb */
2189 if (IS_IVYBRIDGE(dev
))
2193 int ilk_wm_max_level(const struct drm_device
*dev
)
2195 /* how many WM levels are we expecting */
2196 if (INTEL_INFO(dev
)->gen
>= 9)
2198 else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2200 else if (INTEL_INFO(dev
)->gen
>= 6)
2206 static void intel_print_wm_latency(struct drm_device
*dev
,
2208 const uint16_t wm
[8])
2210 int level
, max_level
= ilk_wm_max_level(dev
);
2212 for (level
= 0; level
<= max_level
; level
++) {
2213 unsigned int latency
= wm
[level
];
2216 DRM_ERROR("%s WM%d latency not provided\n",
2222 * - latencies are in us on gen9.
2223 * - before then, WM1+ latency values are in 0.5us units
2230 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2231 name
, level
, wm
[level
],
2232 latency
/ 10, latency
% 10);
2236 static bool ilk_increase_wm_latency(struct drm_i915_private
*dev_priv
,
2237 uint16_t wm
[5], uint16_t min
)
2239 int level
, max_level
= ilk_wm_max_level(&dev_priv
->drm
);
2244 wm
[0] = max(wm
[0], min
);
2245 for (level
= 1; level
<= max_level
; level
++)
2246 wm
[level
] = max_t(uint16_t, wm
[level
], DIV_ROUND_UP(min
, 5));
2251 static void snb_wm_latency_quirk(struct drm_device
*dev
)
2253 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2257 * The BIOS provided WM memory latency values are often
2258 * inadequate for high resolution displays. Adjust them.
2260 changed
= ilk_increase_wm_latency(dev_priv
, dev_priv
->wm
.pri_latency
, 12) |
2261 ilk_increase_wm_latency(dev_priv
, dev_priv
->wm
.spr_latency
, 12) |
2262 ilk_increase_wm_latency(dev_priv
, dev_priv
->wm
.cur_latency
, 12);
2267 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2268 intel_print_wm_latency(dev
, "Primary", dev_priv
->wm
.pri_latency
);
2269 intel_print_wm_latency(dev
, "Sprite", dev_priv
->wm
.spr_latency
);
2270 intel_print_wm_latency(dev
, "Cursor", dev_priv
->wm
.cur_latency
);
2273 static void ilk_setup_wm_latency(struct drm_device
*dev
)
2275 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2277 intel_read_wm_latency(dev
, dev_priv
->wm
.pri_latency
);
2279 memcpy(dev_priv
->wm
.spr_latency
, dev_priv
->wm
.pri_latency
,
2280 sizeof(dev_priv
->wm
.pri_latency
));
2281 memcpy(dev_priv
->wm
.cur_latency
, dev_priv
->wm
.pri_latency
,
2282 sizeof(dev_priv
->wm
.pri_latency
));
2284 intel_fixup_spr_wm_latency(dev
, dev_priv
->wm
.spr_latency
);
2285 intel_fixup_cur_wm_latency(dev
, dev_priv
->wm
.cur_latency
);
2287 intel_print_wm_latency(dev
, "Primary", dev_priv
->wm
.pri_latency
);
2288 intel_print_wm_latency(dev
, "Sprite", dev_priv
->wm
.spr_latency
);
2289 intel_print_wm_latency(dev
, "Cursor", dev_priv
->wm
.cur_latency
);
2292 snb_wm_latency_quirk(dev
);
2295 static void skl_setup_wm_latency(struct drm_device
*dev
)
2297 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2299 intel_read_wm_latency(dev
, dev_priv
->wm
.skl_latency
);
2300 intel_print_wm_latency(dev
, "Gen9 Plane", dev_priv
->wm
.skl_latency
);
2303 static bool ilk_validate_pipe_wm(struct drm_device
*dev
,
2304 struct intel_pipe_wm
*pipe_wm
)
2306 /* LP0 watermark maximums depend on this pipe alone */
2307 const struct intel_wm_config config
= {
2308 .num_pipes_active
= 1,
2309 .sprites_enabled
= pipe_wm
->sprites_enabled
,
2310 .sprites_scaled
= pipe_wm
->sprites_scaled
,
2312 struct ilk_wm_maximums max
;
2314 /* LP0 watermarks always use 1/2 DDB partitioning */
2315 ilk_compute_wm_maximums(dev
, 0, &config
, INTEL_DDB_PART_1_2
, &max
);
2317 /* At least LP0 must be valid */
2318 if (!ilk_validate_wm_level(0, &max
, &pipe_wm
->wm
[0])) {
2319 DRM_DEBUG_KMS("LP0 watermark invalid\n");
2326 /* Compute new watermarks for the pipe */
2327 static int ilk_compute_pipe_wm(struct intel_crtc_state
*cstate
)
2329 struct drm_atomic_state
*state
= cstate
->base
.state
;
2330 struct intel_crtc
*intel_crtc
= to_intel_crtc(cstate
->base
.crtc
);
2331 struct intel_pipe_wm
*pipe_wm
;
2332 struct drm_device
*dev
= state
->dev
;
2333 const struct drm_i915_private
*dev_priv
= to_i915(dev
);
2334 struct intel_plane
*intel_plane
;
2335 struct intel_plane_state
*pristate
= NULL
;
2336 struct intel_plane_state
*sprstate
= NULL
;
2337 struct intel_plane_state
*curstate
= NULL
;
2338 int level
, max_level
= ilk_wm_max_level(dev
), usable_level
;
2339 struct ilk_wm_maximums max
;
2341 pipe_wm
= &cstate
->wm
.ilk
.optimal
;
2343 for_each_intel_plane_on_crtc(dev
, intel_crtc
, intel_plane
) {
2344 struct intel_plane_state
*ps
;
2346 ps
= intel_atomic_get_existing_plane_state(state
,
2351 if (intel_plane
->base
.type
== DRM_PLANE_TYPE_PRIMARY
)
2353 else if (intel_plane
->base
.type
== DRM_PLANE_TYPE_OVERLAY
)
2355 else if (intel_plane
->base
.type
== DRM_PLANE_TYPE_CURSOR
)
2359 pipe_wm
->pipe_enabled
= cstate
->base
.active
;
2361 pipe_wm
->sprites_enabled
= sprstate
->visible
;
2362 pipe_wm
->sprites_scaled
= sprstate
->visible
&&
2363 (drm_rect_width(&sprstate
->dst
) != drm_rect_width(&sprstate
->src
) >> 16 ||
2364 drm_rect_height(&sprstate
->dst
) != drm_rect_height(&sprstate
->src
) >> 16);
2367 usable_level
= max_level
;
2369 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2370 if (INTEL_INFO(dev
)->gen
<= 6 && pipe_wm
->sprites_enabled
)
2373 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2374 if (pipe_wm
->sprites_scaled
)
2377 ilk_compute_wm_level(dev_priv
, intel_crtc
, 0, cstate
,
2378 pristate
, sprstate
, curstate
, &pipe_wm
->raw_wm
[0]);
2380 memset(&pipe_wm
->wm
, 0, sizeof(pipe_wm
->wm
));
2381 pipe_wm
->wm
[0] = pipe_wm
->raw_wm
[0];
2383 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2384 pipe_wm
->linetime
= hsw_compute_linetime_wm(cstate
);
2386 if (!ilk_validate_pipe_wm(dev
, pipe_wm
))
2389 ilk_compute_wm_reg_maximums(dev
, 1, &max
);
2391 for (level
= 1; level
<= max_level
; level
++) {
2392 struct intel_wm_level
*wm
= &pipe_wm
->raw_wm
[level
];
2394 ilk_compute_wm_level(dev_priv
, intel_crtc
, level
, cstate
,
2395 pristate
, sprstate
, curstate
, wm
);
2398 * Disable any watermark level that exceeds the
2399 * register maximums since such watermarks are
2402 if (level
> usable_level
)
2405 if (ilk_validate_wm_level(level
, &max
, wm
))
2406 pipe_wm
->wm
[level
] = *wm
;
2408 usable_level
= level
;
2415 * Build a set of 'intermediate' watermark values that satisfy both the old
2416 * state and the new state. These can be programmed to the hardware
2419 static int ilk_compute_intermediate_wm(struct drm_device
*dev
,
2420 struct intel_crtc
*intel_crtc
,
2421 struct intel_crtc_state
*newstate
)
2423 struct intel_pipe_wm
*a
= &newstate
->wm
.ilk
.intermediate
;
2424 struct intel_pipe_wm
*b
= &intel_crtc
->wm
.active
.ilk
;
2425 int level
, max_level
= ilk_wm_max_level(dev
);
2428 * Start with the final, target watermarks, then combine with the
2429 * currently active watermarks to get values that are safe both before
2430 * and after the vblank.
2432 *a
= newstate
->wm
.ilk
.optimal
;
2433 a
->pipe_enabled
|= b
->pipe_enabled
;
2434 a
->sprites_enabled
|= b
->sprites_enabled
;
2435 a
->sprites_scaled
|= b
->sprites_scaled
;
2437 for (level
= 0; level
<= max_level
; level
++) {
2438 struct intel_wm_level
*a_wm
= &a
->wm
[level
];
2439 const struct intel_wm_level
*b_wm
= &b
->wm
[level
];
2441 a_wm
->enable
&= b_wm
->enable
;
2442 a_wm
->pri_val
= max(a_wm
->pri_val
, b_wm
->pri_val
);
2443 a_wm
->spr_val
= max(a_wm
->spr_val
, b_wm
->spr_val
);
2444 a_wm
->cur_val
= max(a_wm
->cur_val
, b_wm
->cur_val
);
2445 a_wm
->fbc_val
= max(a_wm
->fbc_val
, b_wm
->fbc_val
);
2449 * We need to make sure that these merged watermark values are
2450 * actually a valid configuration themselves. If they're not,
2451 * there's no safe way to transition from the old state to
2452 * the new state, so we need to fail the atomic transaction.
2454 if (!ilk_validate_pipe_wm(dev
, a
))
2458 * If our intermediate WM are identical to the final WM, then we can
2459 * omit the post-vblank programming; only update if it's different.
2461 if (memcmp(a
, &newstate
->wm
.ilk
.optimal
, sizeof(*a
)) == 0)
2462 newstate
->wm
.need_postvbl_update
= false;
2468 * Merge the watermarks from all active pipes for a specific level.
2470 static void ilk_merge_wm_level(struct drm_device
*dev
,
2472 struct intel_wm_level
*ret_wm
)
2474 const struct intel_crtc
*intel_crtc
;
2476 ret_wm
->enable
= true;
2478 for_each_intel_crtc(dev
, intel_crtc
) {
2479 const struct intel_pipe_wm
*active
= &intel_crtc
->wm
.active
.ilk
;
2480 const struct intel_wm_level
*wm
= &active
->wm
[level
];
2482 if (!active
->pipe_enabled
)
2486 * The watermark values may have been used in the past,
2487 * so we must maintain them in the registers for some
2488 * time even if the level is now disabled.
2491 ret_wm
->enable
= false;
2493 ret_wm
->pri_val
= max(ret_wm
->pri_val
, wm
->pri_val
);
2494 ret_wm
->spr_val
= max(ret_wm
->spr_val
, wm
->spr_val
);
2495 ret_wm
->cur_val
= max(ret_wm
->cur_val
, wm
->cur_val
);
2496 ret_wm
->fbc_val
= max(ret_wm
->fbc_val
, wm
->fbc_val
);
2501 * Merge all low power watermarks for all active pipes.
2503 static void ilk_wm_merge(struct drm_device
*dev
,
2504 const struct intel_wm_config
*config
,
2505 const struct ilk_wm_maximums
*max
,
2506 struct intel_pipe_wm
*merged
)
2508 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2509 int level
, max_level
= ilk_wm_max_level(dev
);
2510 int last_enabled_level
= max_level
;
2512 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2513 if ((INTEL_INFO(dev
)->gen
<= 6 || IS_IVYBRIDGE(dev
)) &&
2514 config
->num_pipes_active
> 1)
2515 last_enabled_level
= 0;
2517 /* ILK: FBC WM must be disabled always */
2518 merged
->fbc_wm_enabled
= INTEL_INFO(dev
)->gen
>= 6;
2520 /* merge each WM1+ level */
2521 for (level
= 1; level
<= max_level
; level
++) {
2522 struct intel_wm_level
*wm
= &merged
->wm
[level
];
2524 ilk_merge_wm_level(dev
, level
, wm
);
2526 if (level
> last_enabled_level
)
2528 else if (!ilk_validate_wm_level(level
, max
, wm
))
2529 /* make sure all following levels get disabled */
2530 last_enabled_level
= level
- 1;
2533 * The spec says it is preferred to disable
2534 * FBC WMs instead of disabling a WM level.
2536 if (wm
->fbc_val
> max
->fbc
) {
2538 merged
->fbc_wm_enabled
= false;
2543 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2545 * FIXME this is racy. FBC might get enabled later.
2546 * What we should check here is whether FBC can be
2547 * enabled sometime later.
2549 if (IS_GEN5(dev
) && !merged
->fbc_wm_enabled
&&
2550 intel_fbc_is_active(dev_priv
)) {
2551 for (level
= 2; level
<= max_level
; level
++) {
2552 struct intel_wm_level
*wm
= &merged
->wm
[level
];
2559 static int ilk_wm_lp_to_level(int wm_lp
, const struct intel_pipe_wm
*pipe_wm
)
2561 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2562 return wm_lp
+ (wm_lp
>= 2 && pipe_wm
->wm
[4].enable
);
2565 /* The value we need to program into the WM_LPx latency field */
2566 static unsigned int ilk_wm_lp_latency(struct drm_device
*dev
, int level
)
2568 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2570 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2573 return dev_priv
->wm
.pri_latency
[level
];
2576 static void ilk_compute_wm_results(struct drm_device
*dev
,
2577 const struct intel_pipe_wm
*merged
,
2578 enum intel_ddb_partitioning partitioning
,
2579 struct ilk_wm_values
*results
)
2581 struct intel_crtc
*intel_crtc
;
2584 results
->enable_fbc_wm
= merged
->fbc_wm_enabled
;
2585 results
->partitioning
= partitioning
;
2587 /* LP1+ register values */
2588 for (wm_lp
= 1; wm_lp
<= 3; wm_lp
++) {
2589 const struct intel_wm_level
*r
;
2591 level
= ilk_wm_lp_to_level(wm_lp
, merged
);
2593 r
= &merged
->wm
[level
];
2596 * Maintain the watermark values even if the level is
2597 * disabled. Doing otherwise could cause underruns.
2599 results
->wm_lp
[wm_lp
- 1] =
2600 (ilk_wm_lp_latency(dev
, level
) << WM1_LP_LATENCY_SHIFT
) |
2601 (r
->pri_val
<< WM1_LP_SR_SHIFT
) |
2605 results
->wm_lp
[wm_lp
- 1] |= WM1_LP_SR_EN
;
2607 if (INTEL_INFO(dev
)->gen
>= 8)
2608 results
->wm_lp
[wm_lp
- 1] |=
2609 r
->fbc_val
<< WM1_LP_FBC_SHIFT_BDW
;
2611 results
->wm_lp
[wm_lp
- 1] |=
2612 r
->fbc_val
<< WM1_LP_FBC_SHIFT
;
2615 * Always set WM1S_LP_EN when spr_val != 0, even if the
2616 * level is disabled. Doing otherwise could cause underruns.
2618 if (INTEL_INFO(dev
)->gen
<= 6 && r
->spr_val
) {
2619 WARN_ON(wm_lp
!= 1);
2620 results
->wm_lp_spr
[wm_lp
- 1] = WM1S_LP_EN
| r
->spr_val
;
2622 results
->wm_lp_spr
[wm_lp
- 1] = r
->spr_val
;
2625 /* LP0 register values */
2626 for_each_intel_crtc(dev
, intel_crtc
) {
2627 enum pipe pipe
= intel_crtc
->pipe
;
2628 const struct intel_wm_level
*r
=
2629 &intel_crtc
->wm
.active
.ilk
.wm
[0];
2631 if (WARN_ON(!r
->enable
))
2634 results
->wm_linetime
[pipe
] = intel_crtc
->wm
.active
.ilk
.linetime
;
2636 results
->wm_pipe
[pipe
] =
2637 (r
->pri_val
<< WM0_PIPE_PLANE_SHIFT
) |
2638 (r
->spr_val
<< WM0_PIPE_SPRITE_SHIFT
) |
2643 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2644 * case both are at the same level. Prefer r1 in case they're the same. */
2645 static struct intel_pipe_wm
*ilk_find_best_result(struct drm_device
*dev
,
2646 struct intel_pipe_wm
*r1
,
2647 struct intel_pipe_wm
*r2
)
2649 int level
, max_level
= ilk_wm_max_level(dev
);
2650 int level1
= 0, level2
= 0;
2652 for (level
= 1; level
<= max_level
; level
++) {
2653 if (r1
->wm
[level
].enable
)
2655 if (r2
->wm
[level
].enable
)
2659 if (level1
== level2
) {
2660 if (r2
->fbc_wm_enabled
&& !r1
->fbc_wm_enabled
)
2664 } else if (level1
> level2
) {
2671 /* dirty bits used to track which watermarks need changes */
2672 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2673 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2674 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2675 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2676 #define WM_DIRTY_FBC (1 << 24)
2677 #define WM_DIRTY_DDB (1 << 25)
2679 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private
*dev_priv
,
2680 const struct ilk_wm_values
*old
,
2681 const struct ilk_wm_values
*new)
2683 unsigned int dirty
= 0;
2687 for_each_pipe(dev_priv
, pipe
) {
2688 if (old
->wm_linetime
[pipe
] != new->wm_linetime
[pipe
]) {
2689 dirty
|= WM_DIRTY_LINETIME(pipe
);
2690 /* Must disable LP1+ watermarks too */
2691 dirty
|= WM_DIRTY_LP_ALL
;
2694 if (old
->wm_pipe
[pipe
] != new->wm_pipe
[pipe
]) {
2695 dirty
|= WM_DIRTY_PIPE(pipe
);
2696 /* Must disable LP1+ watermarks too */
2697 dirty
|= WM_DIRTY_LP_ALL
;
2701 if (old
->enable_fbc_wm
!= new->enable_fbc_wm
) {
2702 dirty
|= WM_DIRTY_FBC
;
2703 /* Must disable LP1+ watermarks too */
2704 dirty
|= WM_DIRTY_LP_ALL
;
2707 if (old
->partitioning
!= new->partitioning
) {
2708 dirty
|= WM_DIRTY_DDB
;
2709 /* Must disable LP1+ watermarks too */
2710 dirty
|= WM_DIRTY_LP_ALL
;
2713 /* LP1+ watermarks already deemed dirty, no need to continue */
2714 if (dirty
& WM_DIRTY_LP_ALL
)
2717 /* Find the lowest numbered LP1+ watermark in need of an update... */
2718 for (wm_lp
= 1; wm_lp
<= 3; wm_lp
++) {
2719 if (old
->wm_lp
[wm_lp
- 1] != new->wm_lp
[wm_lp
- 1] ||
2720 old
->wm_lp_spr
[wm_lp
- 1] != new->wm_lp_spr
[wm_lp
- 1])
2724 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2725 for (; wm_lp
<= 3; wm_lp
++)
2726 dirty
|= WM_DIRTY_LP(wm_lp
);
2731 static bool _ilk_disable_lp_wm(struct drm_i915_private
*dev_priv
,
2734 struct ilk_wm_values
*previous
= &dev_priv
->wm
.hw
;
2735 bool changed
= false;
2737 if (dirty
& WM_DIRTY_LP(3) && previous
->wm_lp
[2] & WM1_LP_SR_EN
) {
2738 previous
->wm_lp
[2] &= ~WM1_LP_SR_EN
;
2739 I915_WRITE(WM3_LP_ILK
, previous
->wm_lp
[2]);
2742 if (dirty
& WM_DIRTY_LP(2) && previous
->wm_lp
[1] & WM1_LP_SR_EN
) {
2743 previous
->wm_lp
[1] &= ~WM1_LP_SR_EN
;
2744 I915_WRITE(WM2_LP_ILK
, previous
->wm_lp
[1]);
2747 if (dirty
& WM_DIRTY_LP(1) && previous
->wm_lp
[0] & WM1_LP_SR_EN
) {
2748 previous
->wm_lp
[0] &= ~WM1_LP_SR_EN
;
2749 I915_WRITE(WM1_LP_ILK
, previous
->wm_lp
[0]);
2754 * Don't touch WM1S_LP_EN here.
2755 * Doing so could cause underruns.
2762 * The spec says we shouldn't write when we don't need, because every write
2763 * causes WMs to be re-evaluated, expending some power.
2765 static void ilk_write_wm_values(struct drm_i915_private
*dev_priv
,
2766 struct ilk_wm_values
*results
)
2768 struct drm_device
*dev
= &dev_priv
->drm
;
2769 struct ilk_wm_values
*previous
= &dev_priv
->wm
.hw
;
2773 dirty
= ilk_compute_wm_dirty(dev_priv
, previous
, results
);
2777 _ilk_disable_lp_wm(dev_priv
, dirty
);
2779 if (dirty
& WM_DIRTY_PIPE(PIPE_A
))
2780 I915_WRITE(WM0_PIPEA_ILK
, results
->wm_pipe
[0]);
2781 if (dirty
& WM_DIRTY_PIPE(PIPE_B
))
2782 I915_WRITE(WM0_PIPEB_ILK
, results
->wm_pipe
[1]);
2783 if (dirty
& WM_DIRTY_PIPE(PIPE_C
))
2784 I915_WRITE(WM0_PIPEC_IVB
, results
->wm_pipe
[2]);
2786 if (dirty
& WM_DIRTY_LINETIME(PIPE_A
))
2787 I915_WRITE(PIPE_WM_LINETIME(PIPE_A
), results
->wm_linetime
[0]);
2788 if (dirty
& WM_DIRTY_LINETIME(PIPE_B
))
2789 I915_WRITE(PIPE_WM_LINETIME(PIPE_B
), results
->wm_linetime
[1]);
2790 if (dirty
& WM_DIRTY_LINETIME(PIPE_C
))
2791 I915_WRITE(PIPE_WM_LINETIME(PIPE_C
), results
->wm_linetime
[2]);
2793 if (dirty
& WM_DIRTY_DDB
) {
2794 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2795 val
= I915_READ(WM_MISC
);
2796 if (results
->partitioning
== INTEL_DDB_PART_1_2
)
2797 val
&= ~WM_MISC_DATA_PARTITION_5_6
;
2799 val
|= WM_MISC_DATA_PARTITION_5_6
;
2800 I915_WRITE(WM_MISC
, val
);
2802 val
= I915_READ(DISP_ARB_CTL2
);
2803 if (results
->partitioning
== INTEL_DDB_PART_1_2
)
2804 val
&= ~DISP_DATA_PARTITION_5_6
;
2806 val
|= DISP_DATA_PARTITION_5_6
;
2807 I915_WRITE(DISP_ARB_CTL2
, val
);
2811 if (dirty
& WM_DIRTY_FBC
) {
2812 val
= I915_READ(DISP_ARB_CTL
);
2813 if (results
->enable_fbc_wm
)
2814 val
&= ~DISP_FBC_WM_DIS
;
2816 val
|= DISP_FBC_WM_DIS
;
2817 I915_WRITE(DISP_ARB_CTL
, val
);
2820 if (dirty
& WM_DIRTY_LP(1) &&
2821 previous
->wm_lp_spr
[0] != results
->wm_lp_spr
[0])
2822 I915_WRITE(WM1S_LP_ILK
, results
->wm_lp_spr
[0]);
2824 if (INTEL_INFO(dev
)->gen
>= 7) {
2825 if (dirty
& WM_DIRTY_LP(2) && previous
->wm_lp_spr
[1] != results
->wm_lp_spr
[1])
2826 I915_WRITE(WM2S_LP_IVB
, results
->wm_lp_spr
[1]);
2827 if (dirty
& WM_DIRTY_LP(3) && previous
->wm_lp_spr
[2] != results
->wm_lp_spr
[2])
2828 I915_WRITE(WM3S_LP_IVB
, results
->wm_lp_spr
[2]);
2831 if (dirty
& WM_DIRTY_LP(1) && previous
->wm_lp
[0] != results
->wm_lp
[0])
2832 I915_WRITE(WM1_LP_ILK
, results
->wm_lp
[0]);
2833 if (dirty
& WM_DIRTY_LP(2) && previous
->wm_lp
[1] != results
->wm_lp
[1])
2834 I915_WRITE(WM2_LP_ILK
, results
->wm_lp
[1]);
2835 if (dirty
& WM_DIRTY_LP(3) && previous
->wm_lp
[2] != results
->wm_lp
[2])
2836 I915_WRITE(WM3_LP_ILK
, results
->wm_lp
[2]);
2838 dev_priv
->wm
.hw
= *results
;
2841 bool ilk_disable_lp_wm(struct drm_device
*dev
)
2843 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2845 return _ilk_disable_lp_wm(dev_priv
, WM_DIRTY_LP_ALL
);
2849 * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2850 * different active planes.
2853 #define SKL_DDB_SIZE 896 /* in blocks */
2854 #define BXT_DDB_SIZE 512
2857 * Return the index of a plane in the SKL DDB and wm result arrays. Primary
2858 * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
2859 * other universal planes are in indices 1..n. Note that this may leave unused
2860 * indices between the top "sprite" plane and the cursor.
2863 skl_wm_plane_id(const struct intel_plane
*plane
)
2865 switch (plane
->base
.type
) {
2866 case DRM_PLANE_TYPE_PRIMARY
:
2868 case DRM_PLANE_TYPE_CURSOR
:
2869 return PLANE_CURSOR
;
2870 case DRM_PLANE_TYPE_OVERLAY
:
2871 return plane
->plane
+ 1;
2873 MISSING_CASE(plane
->base
.type
);
2874 return plane
->plane
;
2879 skl_ddb_get_pipe_allocation_limits(struct drm_device
*dev
,
2880 const struct intel_crtc_state
*cstate
,
2881 struct skl_ddb_entry
*alloc
, /* out */
2882 int *num_active
/* out */)
2884 struct drm_atomic_state
*state
= cstate
->base
.state
;
2885 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
2886 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2887 struct drm_crtc
*for_crtc
= cstate
->base
.crtc
;
2888 unsigned int pipe_size
, ddb_size
;
2889 int nth_active_pipe
;
2890 int pipe
= to_intel_crtc(for_crtc
)->pipe
;
2892 if (WARN_ON(!state
) || !cstate
->base
.active
) {
2895 *num_active
= hweight32(dev_priv
->active_crtcs
);
2899 if (intel_state
->active_pipe_changes
)
2900 *num_active
= hweight32(intel_state
->active_crtcs
);
2902 *num_active
= hweight32(dev_priv
->active_crtcs
);
2904 if (IS_BROXTON(dev
))
2905 ddb_size
= BXT_DDB_SIZE
;
2907 ddb_size
= SKL_DDB_SIZE
;
2909 ddb_size
-= 4; /* 4 blocks for bypass path allocation */
2912 * If the state doesn't change the active CRTC's, then there's
2913 * no need to recalculate; the existing pipe allocation limits
2914 * should remain unchanged. Note that we're safe from racing
2915 * commits since any racing commit that changes the active CRTC
2916 * list would need to grab _all_ crtc locks, including the one
2917 * we currently hold.
2919 if (!intel_state
->active_pipe_changes
) {
2920 *alloc
= dev_priv
->wm
.skl_hw
.ddb
.pipe
[pipe
];
2924 nth_active_pipe
= hweight32(intel_state
->active_crtcs
&
2925 (drm_crtc_mask(for_crtc
) - 1));
2926 pipe_size
= ddb_size
/ hweight32(intel_state
->active_crtcs
);
2927 alloc
->start
= nth_active_pipe
* ddb_size
/ *num_active
;
2928 alloc
->end
= alloc
->start
+ pipe_size
;
2931 static unsigned int skl_cursor_allocation(int num_active
)
2933 if (num_active
== 1)
2939 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry
*entry
, u32 reg
)
2941 entry
->start
= reg
& 0x3ff;
2942 entry
->end
= (reg
>> 16) & 0x3ff;
2947 void skl_ddb_get_hw_state(struct drm_i915_private
*dev_priv
,
2948 struct skl_ddb_allocation
*ddb
/* out */)
2954 memset(ddb
, 0, sizeof(*ddb
));
2956 for_each_pipe(dev_priv
, pipe
) {
2957 enum intel_display_power_domain power_domain
;
2959 power_domain
= POWER_DOMAIN_PIPE(pipe
);
2960 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
))
2963 for_each_plane(dev_priv
, pipe
, plane
) {
2964 val
= I915_READ(PLANE_BUF_CFG(pipe
, plane
));
2965 skl_ddb_entry_init_from_hw(&ddb
->plane
[pipe
][plane
],
2969 val
= I915_READ(CUR_BUF_CFG(pipe
));
2970 skl_ddb_entry_init_from_hw(&ddb
->plane
[pipe
][PLANE_CURSOR
],
2973 intel_display_power_put(dev_priv
, power_domain
);
2978 * Determines the downscale amount of a plane for the purposes of watermark calculations.
2979 * The bspec defines downscale amount as:
2982 * Horizontal down scale amount = maximum[1, Horizontal source size /
2983 * Horizontal destination size]
2984 * Vertical down scale amount = maximum[1, Vertical source size /
2985 * Vertical destination size]
2986 * Total down scale amount = Horizontal down scale amount *
2987 * Vertical down scale amount
2990 * Return value is provided in 16.16 fixed point form to retain fractional part.
2991 * Caller should take care of dividing & rounding off the value.
2994 skl_plane_downscale_amount(const struct intel_plane_state
*pstate
)
2996 uint32_t downscale_h
, downscale_w
;
2997 uint32_t src_w
, src_h
, dst_w
, dst_h
;
2999 if (WARN_ON(!pstate
->visible
))
3000 return DRM_PLANE_HELPER_NO_SCALING
;
3002 /* n.b., src is 16.16 fixed point, dst is whole integer */
3003 src_w
= drm_rect_width(&pstate
->src
);
3004 src_h
= drm_rect_height(&pstate
->src
);
3005 dst_w
= drm_rect_width(&pstate
->dst
);
3006 dst_h
= drm_rect_height(&pstate
->dst
);
3007 if (intel_rotation_90_or_270(pstate
->base
.rotation
))
3010 downscale_h
= max(src_h
/ dst_h
, (uint32_t)DRM_PLANE_HELPER_NO_SCALING
);
3011 downscale_w
= max(src_w
/ dst_w
, (uint32_t)DRM_PLANE_HELPER_NO_SCALING
);
3013 /* Provide result in 16.16 fixed point */
3014 return (uint64_t)downscale_w
* downscale_h
>> 16;
3018 skl_plane_relative_data_rate(const struct intel_crtc_state
*cstate
,
3019 const struct drm_plane_state
*pstate
,
3022 struct intel_plane_state
*intel_pstate
= to_intel_plane_state(pstate
);
3023 struct drm_framebuffer
*fb
= pstate
->fb
;
3024 uint32_t down_scale_amount
, data_rate
;
3025 uint32_t width
= 0, height
= 0;
3026 unsigned format
= fb
? fb
->pixel_format
: DRM_FORMAT_XRGB8888
;
3028 if (!intel_pstate
->visible
)
3030 if (pstate
->plane
->type
== DRM_PLANE_TYPE_CURSOR
)
3032 if (y
&& format
!= DRM_FORMAT_NV12
)
3035 width
= drm_rect_width(&intel_pstate
->src
) >> 16;
3036 height
= drm_rect_height(&intel_pstate
->src
) >> 16;
3038 if (intel_rotation_90_or_270(pstate
->rotation
))
3039 swap(width
, height
);
3041 /* for planar format */
3042 if (format
== DRM_FORMAT_NV12
) {
3043 if (y
) /* y-plane data rate */
3044 data_rate
= width
* height
*
3045 drm_format_plane_cpp(format
, 0);
3046 else /* uv-plane data rate */
3047 data_rate
= (width
/ 2) * (height
/ 2) *
3048 drm_format_plane_cpp(format
, 1);
3050 /* for packed formats */
3051 data_rate
= width
* height
* drm_format_plane_cpp(format
, 0);
3054 down_scale_amount
= skl_plane_downscale_amount(intel_pstate
);
3056 return (uint64_t)data_rate
* down_scale_amount
>> 16;
3060 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
3061 * a 8192x4096@32bpp framebuffer:
3062 * 3 * 4096 * 8192 * 4 < 2^32
3065 skl_get_total_relative_data_rate(struct intel_crtc_state
*intel_cstate
)
3067 struct drm_crtc_state
*cstate
= &intel_cstate
->base
;
3068 struct drm_atomic_state
*state
= cstate
->state
;
3069 struct drm_crtc
*crtc
= cstate
->crtc
;
3070 struct drm_device
*dev
= crtc
->dev
;
3071 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3072 const struct drm_plane
*plane
;
3073 const struct intel_plane
*intel_plane
;
3074 struct drm_plane_state
*pstate
;
3075 unsigned int rate
, total_data_rate
= 0;
3079 if (WARN_ON(!state
))
3082 /* Calculate and cache data rate for each plane */
3083 for_each_plane_in_state(state
, plane
, pstate
, i
) {
3084 id
= skl_wm_plane_id(to_intel_plane(plane
));
3085 intel_plane
= to_intel_plane(plane
);
3087 if (intel_plane
->pipe
!= intel_crtc
->pipe
)
3091 rate
= skl_plane_relative_data_rate(intel_cstate
,
3093 intel_cstate
->wm
.skl
.plane_data_rate
[id
] = rate
;
3096 rate
= skl_plane_relative_data_rate(intel_cstate
,
3098 intel_cstate
->wm
.skl
.plane_y_data_rate
[id
] = rate
;
3101 /* Calculate CRTC's total data rate from cached values */
3102 for_each_intel_plane_on_crtc(dev
, intel_crtc
, intel_plane
) {
3103 int id
= skl_wm_plane_id(intel_plane
);
3106 total_data_rate
+= intel_cstate
->wm
.skl
.plane_data_rate
[id
];
3107 total_data_rate
+= intel_cstate
->wm
.skl
.plane_y_data_rate
[id
];
3110 WARN_ON(cstate
->plane_mask
&& total_data_rate
== 0);
3112 return total_data_rate
;
3116 skl_ddb_min_alloc(const struct drm_plane_state
*pstate
,
3119 struct drm_framebuffer
*fb
= pstate
->fb
;
3120 struct intel_plane_state
*intel_pstate
= to_intel_plane_state(pstate
);
3121 uint32_t src_w
, src_h
;
3122 uint32_t min_scanlines
= 8;
3128 /* For packed formats, no y-plane, return 0 */
3129 if (y
&& fb
->pixel_format
!= DRM_FORMAT_NV12
)
3132 /* For Non Y-tile return 8-blocks */
3133 if (fb
->modifier
[0] != I915_FORMAT_MOD_Y_TILED
&&
3134 fb
->modifier
[0] != I915_FORMAT_MOD_Yf_TILED
)
3137 src_w
= drm_rect_width(&intel_pstate
->src
) >> 16;
3138 src_h
= drm_rect_height(&intel_pstate
->src
) >> 16;
3140 if (intel_rotation_90_or_270(pstate
->rotation
))
3143 /* Halve UV plane width and height for NV12 */
3144 if (fb
->pixel_format
== DRM_FORMAT_NV12
&& !y
) {
3149 if (fb
->pixel_format
== DRM_FORMAT_NV12
&& !y
)
3150 plane_bpp
= drm_format_plane_cpp(fb
->pixel_format
, 1);
3152 plane_bpp
= drm_format_plane_cpp(fb
->pixel_format
, 0);
3154 if (intel_rotation_90_or_270(pstate
->rotation
)) {
3155 switch (plane_bpp
) {
3169 WARN(1, "Unsupported pixel depth %u for rotation",
3175 return DIV_ROUND_UP((4 * src_w
* plane_bpp
), 512) * min_scanlines
/4 + 3;
3179 skl_allocate_pipe_ddb(struct intel_crtc_state
*cstate
,
3180 struct skl_ddb_allocation
*ddb
/* out */)
3182 struct drm_atomic_state
*state
= cstate
->base
.state
;
3183 struct drm_crtc
*crtc
= cstate
->base
.crtc
;
3184 struct drm_device
*dev
= crtc
->dev
;
3185 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3186 struct intel_plane
*intel_plane
;
3187 struct drm_plane
*plane
;
3188 struct drm_plane_state
*pstate
;
3189 enum pipe pipe
= intel_crtc
->pipe
;
3190 struct skl_ddb_entry
*alloc
= &ddb
->pipe
[pipe
];
3191 uint16_t alloc_size
, start
, cursor_blocks
;
3192 uint16_t *minimum
= cstate
->wm
.skl
.minimum_blocks
;
3193 uint16_t *y_minimum
= cstate
->wm
.skl
.minimum_y_blocks
;
3194 unsigned int total_data_rate
;
3198 if (WARN_ON(!state
))
3201 if (!cstate
->base
.active
) {
3202 ddb
->pipe
[pipe
].start
= ddb
->pipe
[pipe
].end
= 0;
3203 memset(ddb
->plane
[pipe
], 0, sizeof(ddb
->plane
[pipe
]));
3204 memset(ddb
->y_plane
[pipe
], 0, sizeof(ddb
->y_plane
[pipe
]));
3208 skl_ddb_get_pipe_allocation_limits(dev
, cstate
, alloc
, &num_active
);
3209 alloc_size
= skl_ddb_entry_size(alloc
);
3210 if (alloc_size
== 0) {
3211 memset(ddb
->plane
[pipe
], 0, sizeof(ddb
->plane
[pipe
]));
3215 cursor_blocks
= skl_cursor_allocation(num_active
);
3216 ddb
->plane
[pipe
][PLANE_CURSOR
].start
= alloc
->end
- cursor_blocks
;
3217 ddb
->plane
[pipe
][PLANE_CURSOR
].end
= alloc
->end
;
3219 alloc_size
-= cursor_blocks
;
3221 /* 1. Allocate the mininum required blocks for each active plane */
3222 for_each_plane_in_state(state
, plane
, pstate
, i
) {
3223 intel_plane
= to_intel_plane(plane
);
3224 id
= skl_wm_plane_id(intel_plane
);
3226 if (intel_plane
->pipe
!= pipe
)
3229 if (!to_intel_plane_state(pstate
)->visible
) {
3234 if (plane
->type
== DRM_PLANE_TYPE_CURSOR
) {
3240 minimum
[id
] = skl_ddb_min_alloc(pstate
, 0);
3241 y_minimum
[id
] = skl_ddb_min_alloc(pstate
, 1);
3244 for (i
= 0; i
< PLANE_CURSOR
; i
++) {
3245 alloc_size
-= minimum
[i
];
3246 alloc_size
-= y_minimum
[i
];
3250 * 2. Distribute the remaining space in proportion to the amount of
3251 * data each plane needs to fetch from memory.
3253 * FIXME: we may not allocate every single block here.
3255 total_data_rate
= skl_get_total_relative_data_rate(cstate
);
3256 if (total_data_rate
== 0)
3259 start
= alloc
->start
;
3260 for_each_intel_plane_on_crtc(dev
, intel_crtc
, intel_plane
) {
3261 unsigned int data_rate
, y_data_rate
;
3262 uint16_t plane_blocks
, y_plane_blocks
= 0;
3263 int id
= skl_wm_plane_id(intel_plane
);
3265 data_rate
= cstate
->wm
.skl
.plane_data_rate
[id
];
3268 * allocation for (packed formats) or (uv-plane part of planar format):
3269 * promote the expression to 64 bits to avoid overflowing, the
3270 * result is < available as data_rate / total_data_rate < 1
3272 plane_blocks
= minimum
[id
];
3273 plane_blocks
+= div_u64((uint64_t)alloc_size
* data_rate
,
3276 /* Leave disabled planes at (0,0) */
3278 ddb
->plane
[pipe
][id
].start
= start
;
3279 ddb
->plane
[pipe
][id
].end
= start
+ plane_blocks
;
3282 start
+= plane_blocks
;
3285 * allocation for y_plane part of planar format:
3287 y_data_rate
= cstate
->wm
.skl
.plane_y_data_rate
[id
];
3289 y_plane_blocks
= y_minimum
[id
];
3290 y_plane_blocks
+= div_u64((uint64_t)alloc_size
* y_data_rate
,
3294 ddb
->y_plane
[pipe
][id
].start
= start
;
3295 ddb
->y_plane
[pipe
][id
].end
= start
+ y_plane_blocks
;
3298 start
+= y_plane_blocks
;
3304 static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state
*config
)
3306 /* TODO: Take into account the scalers once we support them */
3307 return config
->base
.adjusted_mode
.crtc_clock
;
3311 * The max latency should be 257 (max the punit can code is 255 and we add 2us
3312 * for the read latency) and cpp should always be <= 8, so that
3313 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3314 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3316 static uint32_t skl_wm_method1(uint32_t pixel_rate
, uint8_t cpp
, uint32_t latency
)
3318 uint32_t wm_intermediate_val
, ret
;
3323 wm_intermediate_val
= latency
* pixel_rate
* cpp
/ 512;
3324 ret
= DIV_ROUND_UP(wm_intermediate_val
, 1000);
3329 static uint32_t skl_wm_method2(uint32_t pixel_rate
, uint32_t pipe_htotal
,
3330 uint32_t horiz_pixels
, uint8_t cpp
,
3331 uint64_t tiling
, uint32_t latency
)
3334 uint32_t plane_bytes_per_line
, plane_blocks_per_line
;
3335 uint32_t wm_intermediate_val
;
3340 plane_bytes_per_line
= horiz_pixels
* cpp
;
3342 if (tiling
== I915_FORMAT_MOD_Y_TILED
||
3343 tiling
== I915_FORMAT_MOD_Yf_TILED
) {
3344 plane_bytes_per_line
*= 4;
3345 plane_blocks_per_line
= DIV_ROUND_UP(plane_bytes_per_line
, 512);
3346 plane_blocks_per_line
/= 4;
3348 plane_blocks_per_line
= DIV_ROUND_UP(plane_bytes_per_line
, 512);
3351 wm_intermediate_val
= latency
* pixel_rate
;
3352 ret
= DIV_ROUND_UP(wm_intermediate_val
, pipe_htotal
* 1000) *
3353 plane_blocks_per_line
;
3358 static uint32_t skl_adjusted_plane_pixel_rate(const struct intel_crtc_state
*cstate
,
3359 struct intel_plane_state
*pstate
)
3361 uint64_t adjusted_pixel_rate
;
3362 uint64_t downscale_amount
;
3363 uint64_t pixel_rate
;
3365 /* Shouldn't reach here on disabled planes... */
3366 if (WARN_ON(!pstate
->visible
))
3370 * Adjusted plane pixel rate is just the pipe's adjusted pixel rate
3371 * with additional adjustments for plane-specific scaling.
3373 adjusted_pixel_rate
= skl_pipe_pixel_rate(cstate
);
3374 downscale_amount
= skl_plane_downscale_amount(pstate
);
3376 pixel_rate
= adjusted_pixel_rate
* downscale_amount
>> 16;
3377 WARN_ON(pixel_rate
!= clamp_t(uint32_t, pixel_rate
, 0, ~0));
3382 static int skl_compute_plane_wm(const struct drm_i915_private
*dev_priv
,
3383 struct intel_crtc_state
*cstate
,
3384 struct intel_plane_state
*intel_pstate
,
3385 uint16_t ddb_allocation
,
3387 uint16_t *out_blocks
, /* out */
3388 uint8_t *out_lines
, /* out */
3389 bool *enabled
/* out */)
3391 struct drm_plane_state
*pstate
= &intel_pstate
->base
;
3392 struct drm_framebuffer
*fb
= pstate
->fb
;
3393 uint32_t latency
= dev_priv
->wm
.skl_latency
[level
];
3394 uint32_t method1
, method2
;
3395 uint32_t plane_bytes_per_line
, plane_blocks_per_line
;
3396 uint32_t res_blocks
, res_lines
;
3397 uint32_t selected_result
;
3399 uint32_t width
= 0, height
= 0;
3400 uint32_t plane_pixel_rate
;
3402 if (latency
== 0 || !cstate
->base
.active
|| !intel_pstate
->visible
) {
3407 width
= drm_rect_width(&intel_pstate
->src
) >> 16;
3408 height
= drm_rect_height(&intel_pstate
->src
) >> 16;
3410 if (intel_rotation_90_or_270(pstate
->rotation
))
3411 swap(width
, height
);
3413 cpp
= drm_format_plane_cpp(fb
->pixel_format
, 0);
3414 plane_pixel_rate
= skl_adjusted_plane_pixel_rate(cstate
, intel_pstate
);
3416 method1
= skl_wm_method1(plane_pixel_rate
, cpp
, latency
);
3417 method2
= skl_wm_method2(plane_pixel_rate
,
3418 cstate
->base
.adjusted_mode
.crtc_htotal
,
3424 plane_bytes_per_line
= width
* cpp
;
3425 plane_blocks_per_line
= DIV_ROUND_UP(plane_bytes_per_line
, 512);
3427 if (fb
->modifier
[0] == I915_FORMAT_MOD_Y_TILED
||
3428 fb
->modifier
[0] == I915_FORMAT_MOD_Yf_TILED
) {
3429 uint32_t min_scanlines
= 4;
3430 uint32_t y_tile_minimum
;
3431 if (intel_rotation_90_or_270(pstate
->rotation
)) {
3432 int cpp
= (fb
->pixel_format
== DRM_FORMAT_NV12
) ?
3433 drm_format_plane_cpp(fb
->pixel_format
, 1) :
3434 drm_format_plane_cpp(fb
->pixel_format
, 0);
3444 WARN(1, "Unsupported pixel depth for rotation");
3447 y_tile_minimum
= plane_blocks_per_line
* min_scanlines
;
3448 selected_result
= max(method2
, y_tile_minimum
);
3450 if ((ddb_allocation
/ plane_blocks_per_line
) >= 1)
3451 selected_result
= min(method1
, method2
);
3453 selected_result
= method1
;
3456 res_blocks
= selected_result
+ 1;
3457 res_lines
= DIV_ROUND_UP(selected_result
, plane_blocks_per_line
);
3459 if (level
>= 1 && level
<= 7) {
3460 if (fb
->modifier
[0] == I915_FORMAT_MOD_Y_TILED
||
3461 fb
->modifier
[0] == I915_FORMAT_MOD_Yf_TILED
)
3467 if (res_blocks
>= ddb_allocation
|| res_lines
> 31) {
3471 * If there are no valid level 0 watermarks, then we can't
3472 * support this display configuration.
3477 DRM_DEBUG_KMS("Requested display configuration exceeds system watermark limitations\n");
3478 DRM_DEBUG_KMS("Plane %d.%d: blocks required = %u/%u, lines required = %u/31\n",
3479 to_intel_crtc(cstate
->base
.crtc
)->pipe
,
3480 skl_wm_plane_id(to_intel_plane(pstate
->plane
)),
3481 res_blocks
, ddb_allocation
, res_lines
);
3487 *out_blocks
= res_blocks
;
3488 *out_lines
= res_lines
;
3495 skl_compute_wm_level(const struct drm_i915_private
*dev_priv
,
3496 struct skl_ddb_allocation
*ddb
,
3497 struct intel_crtc_state
*cstate
,
3499 struct skl_wm_level
*result
)
3501 struct drm_atomic_state
*state
= cstate
->base
.state
;
3502 struct intel_crtc
*intel_crtc
= to_intel_crtc(cstate
->base
.crtc
);
3503 struct drm_plane
*plane
;
3504 struct intel_plane
*intel_plane
;
3505 struct intel_plane_state
*intel_pstate
;
3506 uint16_t ddb_blocks
;
3507 enum pipe pipe
= intel_crtc
->pipe
;
3511 * We'll only calculate watermarks for planes that are actually
3512 * enabled, so make sure all other planes are set as disabled.
3514 memset(result
, 0, sizeof(*result
));
3516 for_each_intel_plane_mask(&dev_priv
->drm
,
3518 cstate
->base
.plane_mask
) {
3519 int i
= skl_wm_plane_id(intel_plane
);
3521 plane
= &intel_plane
->base
;
3522 intel_pstate
= NULL
;
3525 intel_atomic_get_existing_plane_state(state
,
3529 * Note: If we start supporting multiple pending atomic commits
3530 * against the same planes/CRTC's in the future, plane->state
3531 * will no longer be the correct pre-state to use for the
3532 * calculations here and we'll need to change where we get the
3533 * 'unchanged' plane data from.
3535 * For now this is fine because we only allow one queued commit
3536 * against a CRTC. Even if the plane isn't modified by this
3537 * transaction and we don't have a plane lock, we still have
3538 * the CRTC's lock, so we know that no other transactions are
3539 * racing with us to update it.
3542 intel_pstate
= to_intel_plane_state(plane
->state
);
3544 WARN_ON(!intel_pstate
->base
.fb
);
3546 ddb_blocks
= skl_ddb_entry_size(&ddb
->plane
[pipe
][i
]);
3548 ret
= skl_compute_plane_wm(dev_priv
,
3553 &result
->plane_res_b
[i
],
3554 &result
->plane_res_l
[i
],
3555 &result
->plane_en
[i
]);
3564 skl_compute_linetime_wm(struct intel_crtc_state
*cstate
)
3566 if (!cstate
->base
.active
)
3569 if (WARN_ON(skl_pipe_pixel_rate(cstate
) == 0))
3572 return DIV_ROUND_UP(8 * cstate
->base
.adjusted_mode
.crtc_htotal
* 1000,
3573 skl_pipe_pixel_rate(cstate
));
3576 static void skl_compute_transition_wm(struct intel_crtc_state
*cstate
,
3577 struct skl_wm_level
*trans_wm
/* out */)
3579 struct drm_crtc
*crtc
= cstate
->base
.crtc
;
3580 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3581 struct intel_plane
*intel_plane
;
3583 if (!cstate
->base
.active
)
3586 /* Until we know more, just disable transition WMs */
3587 for_each_intel_plane_on_crtc(crtc
->dev
, intel_crtc
, intel_plane
) {
3588 int i
= skl_wm_plane_id(intel_plane
);
3590 trans_wm
->plane_en
[i
] = false;
3594 static int skl_build_pipe_wm(struct intel_crtc_state
*cstate
,
3595 struct skl_ddb_allocation
*ddb
,
3596 struct skl_pipe_wm
*pipe_wm
)
3598 struct drm_device
*dev
= cstate
->base
.crtc
->dev
;
3599 const struct drm_i915_private
*dev_priv
= to_i915(dev
);
3600 int level
, max_level
= ilk_wm_max_level(dev
);
3603 for (level
= 0; level
<= max_level
; level
++) {
3604 ret
= skl_compute_wm_level(dev_priv
, ddb
, cstate
,
3605 level
, &pipe_wm
->wm
[level
]);
3609 pipe_wm
->linetime
= skl_compute_linetime_wm(cstate
);
3611 skl_compute_transition_wm(cstate
, &pipe_wm
->trans_wm
);
3616 static void skl_compute_wm_results(struct drm_device
*dev
,
3617 struct skl_pipe_wm
*p_wm
,
3618 struct skl_wm_values
*r
,
3619 struct intel_crtc
*intel_crtc
)
3621 int level
, max_level
= ilk_wm_max_level(dev
);
3622 enum pipe pipe
= intel_crtc
->pipe
;
3626 for (level
= 0; level
<= max_level
; level
++) {
3627 for (i
= 0; i
< intel_num_planes(intel_crtc
); i
++) {
3630 temp
|= p_wm
->wm
[level
].plane_res_l
[i
] <<
3631 PLANE_WM_LINES_SHIFT
;
3632 temp
|= p_wm
->wm
[level
].plane_res_b
[i
];
3633 if (p_wm
->wm
[level
].plane_en
[i
])
3634 temp
|= PLANE_WM_EN
;
3636 r
->plane
[pipe
][i
][level
] = temp
;
3641 temp
|= p_wm
->wm
[level
].plane_res_l
[PLANE_CURSOR
] << PLANE_WM_LINES_SHIFT
;
3642 temp
|= p_wm
->wm
[level
].plane_res_b
[PLANE_CURSOR
];
3644 if (p_wm
->wm
[level
].plane_en
[PLANE_CURSOR
])
3645 temp
|= PLANE_WM_EN
;
3647 r
->plane
[pipe
][PLANE_CURSOR
][level
] = temp
;
3651 /* transition WMs */
3652 for (i
= 0; i
< intel_num_planes(intel_crtc
); i
++) {
3654 temp
|= p_wm
->trans_wm
.plane_res_l
[i
] << PLANE_WM_LINES_SHIFT
;
3655 temp
|= p_wm
->trans_wm
.plane_res_b
[i
];
3656 if (p_wm
->trans_wm
.plane_en
[i
])
3657 temp
|= PLANE_WM_EN
;
3659 r
->plane_trans
[pipe
][i
] = temp
;
3663 temp
|= p_wm
->trans_wm
.plane_res_l
[PLANE_CURSOR
] << PLANE_WM_LINES_SHIFT
;
3664 temp
|= p_wm
->trans_wm
.plane_res_b
[PLANE_CURSOR
];
3665 if (p_wm
->trans_wm
.plane_en
[PLANE_CURSOR
])
3666 temp
|= PLANE_WM_EN
;
3668 r
->plane_trans
[pipe
][PLANE_CURSOR
] = temp
;
3670 r
->wm_linetime
[pipe
] = p_wm
->linetime
;
3673 static void skl_ddb_entry_write(struct drm_i915_private
*dev_priv
,
3675 const struct skl_ddb_entry
*entry
)
3678 I915_WRITE(reg
, (entry
->end
- 1) << 16 | entry
->start
);
3683 static void skl_write_wm_values(struct drm_i915_private
*dev_priv
,
3684 const struct skl_wm_values
*new)
3686 struct drm_device
*dev
= &dev_priv
->drm
;
3687 struct intel_crtc
*crtc
;
3689 for_each_intel_crtc(dev
, crtc
) {
3690 int i
, level
, max_level
= ilk_wm_max_level(dev
);
3691 enum pipe pipe
= crtc
->pipe
;
3693 if ((new->dirty_pipes
& drm_crtc_mask(&crtc
->base
)) == 0)
3698 I915_WRITE(PIPE_WM_LINETIME(pipe
), new->wm_linetime
[pipe
]);
3700 for (level
= 0; level
<= max_level
; level
++) {
3701 for (i
= 0; i
< intel_num_planes(crtc
); i
++)
3702 I915_WRITE(PLANE_WM(pipe
, i
, level
),
3703 new->plane
[pipe
][i
][level
]);
3704 I915_WRITE(CUR_WM(pipe
, level
),
3705 new->plane
[pipe
][PLANE_CURSOR
][level
]);
3707 for (i
= 0; i
< intel_num_planes(crtc
); i
++)
3708 I915_WRITE(PLANE_WM_TRANS(pipe
, i
),
3709 new->plane_trans
[pipe
][i
]);
3710 I915_WRITE(CUR_WM_TRANS(pipe
),
3711 new->plane_trans
[pipe
][PLANE_CURSOR
]);
3713 for (i
= 0; i
< intel_num_planes(crtc
); i
++) {
3714 skl_ddb_entry_write(dev_priv
,
3715 PLANE_BUF_CFG(pipe
, i
),
3716 &new->ddb
.plane
[pipe
][i
]);
3717 skl_ddb_entry_write(dev_priv
,
3718 PLANE_NV12_BUF_CFG(pipe
, i
),
3719 &new->ddb
.y_plane
[pipe
][i
]);
3722 skl_ddb_entry_write(dev_priv
, CUR_BUF_CFG(pipe
),
3723 &new->ddb
.plane
[pipe
][PLANE_CURSOR
]);
3728 * When setting up a new DDB allocation arrangement, we need to correctly
3729 * sequence the times at which the new allocations for the pipes are taken into
3730 * account or we'll have pipes fetching from space previously allocated to
3733 * Roughly the sequence looks like:
3734 * 1. re-allocate the pipe(s) with the allocation being reduced and not
3735 * overlapping with a previous light-up pipe (another way to put it is:
3736 * pipes with their new allocation strickly included into their old ones).
3737 * 2. re-allocate the other pipes that get their allocation reduced
3738 * 3. allocate the pipes having their allocation increased
3740 * Steps 1. and 2. are here to take care of the following case:
3741 * - Initially DDB looks like this:
3744 * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
3748 * We need to sequence the re-allocation: C, B, A (and not B, C, A).
3752 skl_wm_flush_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int pass
)
3756 DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe
), pass
);
3758 for_each_plane(dev_priv
, pipe
, plane
) {
3759 I915_WRITE(PLANE_SURF(pipe
, plane
),
3760 I915_READ(PLANE_SURF(pipe
, plane
)));
3762 I915_WRITE(CURBASE(pipe
), I915_READ(CURBASE(pipe
)));
3766 skl_ddb_allocation_included(const struct skl_ddb_allocation
*old
,
3767 const struct skl_ddb_allocation
*new,
3770 uint16_t old_size
, new_size
;
3772 old_size
= skl_ddb_entry_size(&old
->pipe
[pipe
]);
3773 new_size
= skl_ddb_entry_size(&new->pipe
[pipe
]);
3775 return old_size
!= new_size
&&
3776 new->pipe
[pipe
].start
>= old
->pipe
[pipe
].start
&&
3777 new->pipe
[pipe
].end
<= old
->pipe
[pipe
].end
;
3780 static void skl_flush_wm_values(struct drm_i915_private
*dev_priv
,
3781 struct skl_wm_values
*new_values
)
3783 struct drm_device
*dev
= &dev_priv
->drm
;
3784 struct skl_ddb_allocation
*cur_ddb
, *new_ddb
;
3785 bool reallocated
[I915_MAX_PIPES
] = {};
3786 struct intel_crtc
*crtc
;
3789 new_ddb
= &new_values
->ddb
;
3790 cur_ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
3793 * First pass: flush the pipes with the new allocation contained into
3796 * We'll wait for the vblank on those pipes to ensure we can safely
3797 * re-allocate the freed space without this pipe fetching from it.
3799 for_each_intel_crtc(dev
, crtc
) {
3805 if (!skl_ddb_allocation_included(cur_ddb
, new_ddb
, pipe
))
3808 skl_wm_flush_pipe(dev_priv
, pipe
, 1);
3809 intel_wait_for_vblank(dev
, pipe
);
3811 reallocated
[pipe
] = true;
3816 * Second pass: flush the pipes that are having their allocation
3817 * reduced, but overlapping with a previous allocation.
3819 * Here as well we need to wait for the vblank to make sure the freed
3820 * space is not used anymore.
3822 for_each_intel_crtc(dev
, crtc
) {
3828 if (reallocated
[pipe
])
3831 if (skl_ddb_entry_size(&new_ddb
->pipe
[pipe
]) <
3832 skl_ddb_entry_size(&cur_ddb
->pipe
[pipe
])) {
3833 skl_wm_flush_pipe(dev_priv
, pipe
, 2);
3834 intel_wait_for_vblank(dev
, pipe
);
3835 reallocated
[pipe
] = true;
3840 * Third pass: flush the pipes that got more space allocated.
3842 * We don't need to actively wait for the update here, next vblank
3843 * will just get more DDB space with the correct WM values.
3845 for_each_intel_crtc(dev
, crtc
) {
3852 * At this point, only the pipes more space than before are
3853 * left to re-allocate.
3855 if (reallocated
[pipe
])
3858 skl_wm_flush_pipe(dev_priv
, pipe
, 3);
3862 static int skl_update_pipe_wm(struct drm_crtc_state
*cstate
,
3863 struct skl_ddb_allocation
*ddb
, /* out */
3864 struct skl_pipe_wm
*pipe_wm
, /* out */
3865 bool *changed
/* out */)
3867 struct intel_crtc
*intel_crtc
= to_intel_crtc(cstate
->crtc
);
3868 struct intel_crtc_state
*intel_cstate
= to_intel_crtc_state(cstate
);
3871 ret
= skl_build_pipe_wm(intel_cstate
, ddb
, pipe_wm
);
3875 if (!memcmp(&intel_crtc
->wm
.active
.skl
, pipe_wm
, sizeof(*pipe_wm
)))
3884 pipes_modified(struct drm_atomic_state
*state
)
3886 struct drm_crtc
*crtc
;
3887 struct drm_crtc_state
*cstate
;
3888 uint32_t i
, ret
= 0;
3890 for_each_crtc_in_state(state
, crtc
, cstate
, i
)
3891 ret
|= drm_crtc_mask(crtc
);
3897 skl_compute_ddb(struct drm_atomic_state
*state
)
3899 struct drm_device
*dev
= state
->dev
;
3900 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3901 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
3902 struct intel_crtc
*intel_crtc
;
3903 struct skl_ddb_allocation
*ddb
= &intel_state
->wm_results
.ddb
;
3904 uint32_t realloc_pipes
= pipes_modified(state
);
3908 * If this is our first atomic update following hardware readout,
3909 * we can't trust the DDB that the BIOS programmed for us. Let's
3910 * pretend that all pipes switched active status so that we'll
3911 * ensure a full DDB recompute.
3913 if (dev_priv
->wm
.distrust_bios_wm
)
3914 intel_state
->active_pipe_changes
= ~0;
3917 * If the modeset changes which CRTC's are active, we need to
3918 * recompute the DDB allocation for *all* active pipes, even
3919 * those that weren't otherwise being modified in any way by this
3920 * atomic commit. Due to the shrinking of the per-pipe allocations
3921 * when new active CRTC's are added, it's possible for a pipe that
3922 * we were already using and aren't changing at all here to suddenly
3923 * become invalid if its DDB needs exceeds its new allocation.
3925 * Note that if we wind up doing a full DDB recompute, we can't let
3926 * any other display updates race with this transaction, so we need
3927 * to grab the lock on *all* CRTC's.
3929 if (intel_state
->active_pipe_changes
) {
3931 intel_state
->wm_results
.dirty_pipes
= ~0;
3934 for_each_intel_crtc_mask(dev
, intel_crtc
, realloc_pipes
) {
3935 struct intel_crtc_state
*cstate
;
3937 cstate
= intel_atomic_get_crtc_state(state
, intel_crtc
);
3939 return PTR_ERR(cstate
);
3941 ret
= skl_allocate_pipe_ddb(cstate
, ddb
);
3950 skl_compute_wm(struct drm_atomic_state
*state
)
3952 struct drm_crtc
*crtc
;
3953 struct drm_crtc_state
*cstate
;
3954 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
3955 struct skl_wm_values
*results
= &intel_state
->wm_results
;
3956 struct skl_pipe_wm
*pipe_wm
;
3957 bool changed
= false;
3961 * If this transaction isn't actually touching any CRTC's, don't
3962 * bother with watermark calculation. Note that if we pass this
3963 * test, we're guaranteed to hold at least one CRTC state mutex,
3964 * which means we can safely use values like dev_priv->active_crtcs
3965 * since any racing commits that want to update them would need to
3966 * hold _all_ CRTC state mutexes.
3968 for_each_crtc_in_state(state
, crtc
, cstate
, i
)
3973 /* Clear all dirty flags */
3974 results
->dirty_pipes
= 0;
3976 ret
= skl_compute_ddb(state
);
3981 * Calculate WM's for all pipes that are part of this transaction.
3982 * Note that the DDB allocation above may have added more CRTC's that
3983 * weren't otherwise being modified (and set bits in dirty_pipes) if
3984 * pipe allocations had to change.
3986 * FIXME: Now that we're doing this in the atomic check phase, we
3987 * should allow skl_update_pipe_wm() to return failure in cases where
3988 * no suitable watermark values can be found.
3990 for_each_crtc_in_state(state
, crtc
, cstate
, i
) {
3991 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3992 struct intel_crtc_state
*intel_cstate
=
3993 to_intel_crtc_state(cstate
);
3995 pipe_wm
= &intel_cstate
->wm
.skl
.optimal
;
3996 ret
= skl_update_pipe_wm(cstate
, &results
->ddb
, pipe_wm
,
4002 results
->dirty_pipes
|= drm_crtc_mask(crtc
);
4004 if ((results
->dirty_pipes
& drm_crtc_mask(crtc
)) == 0)
4005 /* This pipe's WM's did not change */
4008 intel_cstate
->update_wm_pre
= true;
4009 skl_compute_wm_results(crtc
->dev
, pipe_wm
, results
, intel_crtc
);
4015 static void skl_update_wm(struct drm_crtc
*crtc
)
4017 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4018 struct drm_device
*dev
= crtc
->dev
;
4019 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4020 struct skl_wm_values
*results
= &dev_priv
->wm
.skl_results
;
4021 struct intel_crtc_state
*cstate
= to_intel_crtc_state(crtc
->state
);
4022 struct skl_pipe_wm
*pipe_wm
= &cstate
->wm
.skl
.optimal
;
4024 if ((results
->dirty_pipes
& drm_crtc_mask(crtc
)) == 0)
4027 intel_crtc
->wm
.active
.skl
= *pipe_wm
;
4029 mutex_lock(&dev_priv
->wm
.wm_mutex
);
4031 skl_write_wm_values(dev_priv
, results
);
4032 skl_flush_wm_values(dev_priv
, results
);
4034 /* store the new configuration */
4035 dev_priv
->wm
.skl_hw
= *results
;
4037 mutex_unlock(&dev_priv
->wm
.wm_mutex
);
4040 static void ilk_compute_wm_config(struct drm_device
*dev
,
4041 struct intel_wm_config
*config
)
4043 struct intel_crtc
*crtc
;
4045 /* Compute the currently _active_ config */
4046 for_each_intel_crtc(dev
, crtc
) {
4047 const struct intel_pipe_wm
*wm
= &crtc
->wm
.active
.ilk
;
4049 if (!wm
->pipe_enabled
)
4052 config
->sprites_enabled
|= wm
->sprites_enabled
;
4053 config
->sprites_scaled
|= wm
->sprites_scaled
;
4054 config
->num_pipes_active
++;
4058 static void ilk_program_watermarks(struct drm_i915_private
*dev_priv
)
4060 struct drm_device
*dev
= &dev_priv
->drm
;
4061 struct intel_pipe_wm lp_wm_1_2
= {}, lp_wm_5_6
= {}, *best_lp_wm
;
4062 struct ilk_wm_maximums max
;
4063 struct intel_wm_config config
= {};
4064 struct ilk_wm_values results
= {};
4065 enum intel_ddb_partitioning partitioning
;
4067 ilk_compute_wm_config(dev
, &config
);
4069 ilk_compute_wm_maximums(dev
, 1, &config
, INTEL_DDB_PART_1_2
, &max
);
4070 ilk_wm_merge(dev
, &config
, &max
, &lp_wm_1_2
);
4072 /* 5/6 split only in single pipe config on IVB+ */
4073 if (INTEL_INFO(dev
)->gen
>= 7 &&
4074 config
.num_pipes_active
== 1 && config
.sprites_enabled
) {
4075 ilk_compute_wm_maximums(dev
, 1, &config
, INTEL_DDB_PART_5_6
, &max
);
4076 ilk_wm_merge(dev
, &config
, &max
, &lp_wm_5_6
);
4078 best_lp_wm
= ilk_find_best_result(dev
, &lp_wm_1_2
, &lp_wm_5_6
);
4080 best_lp_wm
= &lp_wm_1_2
;
4083 partitioning
= (best_lp_wm
== &lp_wm_1_2
) ?
4084 INTEL_DDB_PART_1_2
: INTEL_DDB_PART_5_6
;
4086 ilk_compute_wm_results(dev
, best_lp_wm
, partitioning
, &results
);
4088 ilk_write_wm_values(dev_priv
, &results
);
4091 static void ilk_initial_watermarks(struct intel_crtc_state
*cstate
)
4093 struct drm_i915_private
*dev_priv
= to_i915(cstate
->base
.crtc
->dev
);
4094 struct intel_crtc
*intel_crtc
= to_intel_crtc(cstate
->base
.crtc
);
4096 mutex_lock(&dev_priv
->wm
.wm_mutex
);
4097 intel_crtc
->wm
.active
.ilk
= cstate
->wm
.ilk
.intermediate
;
4098 ilk_program_watermarks(dev_priv
);
4099 mutex_unlock(&dev_priv
->wm
.wm_mutex
);
4102 static void ilk_optimize_watermarks(struct intel_crtc_state
*cstate
)
4104 struct drm_i915_private
*dev_priv
= to_i915(cstate
->base
.crtc
->dev
);
4105 struct intel_crtc
*intel_crtc
= to_intel_crtc(cstate
->base
.crtc
);
4107 mutex_lock(&dev_priv
->wm
.wm_mutex
);
4108 if (cstate
->wm
.need_postvbl_update
) {
4109 intel_crtc
->wm
.active
.ilk
= cstate
->wm
.ilk
.optimal
;
4110 ilk_program_watermarks(dev_priv
);
4112 mutex_unlock(&dev_priv
->wm
.wm_mutex
);
4115 static void skl_pipe_wm_active_state(uint32_t val
,
4116 struct skl_pipe_wm
*active
,
4122 bool is_enabled
= (val
& PLANE_WM_EN
) != 0;
4126 active
->wm
[level
].plane_en
[i
] = is_enabled
;
4127 active
->wm
[level
].plane_res_b
[i
] =
4128 val
& PLANE_WM_BLOCKS_MASK
;
4129 active
->wm
[level
].plane_res_l
[i
] =
4130 (val
>> PLANE_WM_LINES_SHIFT
) &
4131 PLANE_WM_LINES_MASK
;
4133 active
->wm
[level
].plane_en
[PLANE_CURSOR
] = is_enabled
;
4134 active
->wm
[level
].plane_res_b
[PLANE_CURSOR
] =
4135 val
& PLANE_WM_BLOCKS_MASK
;
4136 active
->wm
[level
].plane_res_l
[PLANE_CURSOR
] =
4137 (val
>> PLANE_WM_LINES_SHIFT
) &
4138 PLANE_WM_LINES_MASK
;
4142 active
->trans_wm
.plane_en
[i
] = is_enabled
;
4143 active
->trans_wm
.plane_res_b
[i
] =
4144 val
& PLANE_WM_BLOCKS_MASK
;
4145 active
->trans_wm
.plane_res_l
[i
] =
4146 (val
>> PLANE_WM_LINES_SHIFT
) &
4147 PLANE_WM_LINES_MASK
;
4149 active
->trans_wm
.plane_en
[PLANE_CURSOR
] = is_enabled
;
4150 active
->trans_wm
.plane_res_b
[PLANE_CURSOR
] =
4151 val
& PLANE_WM_BLOCKS_MASK
;
4152 active
->trans_wm
.plane_res_l
[PLANE_CURSOR
] =
4153 (val
>> PLANE_WM_LINES_SHIFT
) &
4154 PLANE_WM_LINES_MASK
;
4159 static void skl_pipe_wm_get_hw_state(struct drm_crtc
*crtc
)
4161 struct drm_device
*dev
= crtc
->dev
;
4162 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4163 struct skl_wm_values
*hw
= &dev_priv
->wm
.skl_hw
;
4164 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4165 struct intel_crtc_state
*cstate
= to_intel_crtc_state(crtc
->state
);
4166 struct skl_pipe_wm
*active
= &cstate
->wm
.skl
.optimal
;
4167 enum pipe pipe
= intel_crtc
->pipe
;
4168 int level
, i
, max_level
;
4171 max_level
= ilk_wm_max_level(dev
);
4173 hw
->wm_linetime
[pipe
] = I915_READ(PIPE_WM_LINETIME(pipe
));
4175 for (level
= 0; level
<= max_level
; level
++) {
4176 for (i
= 0; i
< intel_num_planes(intel_crtc
); i
++)
4177 hw
->plane
[pipe
][i
][level
] =
4178 I915_READ(PLANE_WM(pipe
, i
, level
));
4179 hw
->plane
[pipe
][PLANE_CURSOR
][level
] = I915_READ(CUR_WM(pipe
, level
));
4182 for (i
= 0; i
< intel_num_planes(intel_crtc
); i
++)
4183 hw
->plane_trans
[pipe
][i
] = I915_READ(PLANE_WM_TRANS(pipe
, i
));
4184 hw
->plane_trans
[pipe
][PLANE_CURSOR
] = I915_READ(CUR_WM_TRANS(pipe
));
4186 if (!intel_crtc
->active
)
4189 hw
->dirty_pipes
|= drm_crtc_mask(crtc
);
4191 active
->linetime
= hw
->wm_linetime
[pipe
];
4193 for (level
= 0; level
<= max_level
; level
++) {
4194 for (i
= 0; i
< intel_num_planes(intel_crtc
); i
++) {
4195 temp
= hw
->plane
[pipe
][i
][level
];
4196 skl_pipe_wm_active_state(temp
, active
, false,
4199 temp
= hw
->plane
[pipe
][PLANE_CURSOR
][level
];
4200 skl_pipe_wm_active_state(temp
, active
, false, true, i
, level
);
4203 for (i
= 0; i
< intel_num_planes(intel_crtc
); i
++) {
4204 temp
= hw
->plane_trans
[pipe
][i
];
4205 skl_pipe_wm_active_state(temp
, active
, true, false, i
, 0);
4208 temp
= hw
->plane_trans
[pipe
][PLANE_CURSOR
];
4209 skl_pipe_wm_active_state(temp
, active
, true, true, i
, 0);
4211 intel_crtc
->wm
.active
.skl
= *active
;
4214 void skl_wm_get_hw_state(struct drm_device
*dev
)
4216 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4217 struct skl_ddb_allocation
*ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
4218 struct drm_crtc
*crtc
;
4220 skl_ddb_get_hw_state(dev_priv
, ddb
);
4221 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
)
4222 skl_pipe_wm_get_hw_state(crtc
);
4224 if (dev_priv
->active_crtcs
) {
4225 /* Fully recompute DDB on first atomic commit */
4226 dev_priv
->wm
.distrust_bios_wm
= true;
4228 /* Easy/common case; just sanitize DDB now if everything off */
4229 memset(ddb
, 0, sizeof(*ddb
));
4233 static void ilk_pipe_wm_get_hw_state(struct drm_crtc
*crtc
)
4235 struct drm_device
*dev
= crtc
->dev
;
4236 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4237 struct ilk_wm_values
*hw
= &dev_priv
->wm
.hw
;
4238 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4239 struct intel_crtc_state
*cstate
= to_intel_crtc_state(crtc
->state
);
4240 struct intel_pipe_wm
*active
= &cstate
->wm
.ilk
.optimal
;
4241 enum pipe pipe
= intel_crtc
->pipe
;
4242 static const i915_reg_t wm0_pipe_reg
[] = {
4243 [PIPE_A
] = WM0_PIPEA_ILK
,
4244 [PIPE_B
] = WM0_PIPEB_ILK
,
4245 [PIPE_C
] = WM0_PIPEC_IVB
,
4248 hw
->wm_pipe
[pipe
] = I915_READ(wm0_pipe_reg
[pipe
]);
4249 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
4250 hw
->wm_linetime
[pipe
] = I915_READ(PIPE_WM_LINETIME(pipe
));
4252 memset(active
, 0, sizeof(*active
));
4254 active
->pipe_enabled
= intel_crtc
->active
;
4256 if (active
->pipe_enabled
) {
4257 u32 tmp
= hw
->wm_pipe
[pipe
];
4260 * For active pipes LP0 watermark is marked as
4261 * enabled, and LP1+ watermaks as disabled since
4262 * we can't really reverse compute them in case
4263 * multiple pipes are active.
4265 active
->wm
[0].enable
= true;
4266 active
->wm
[0].pri_val
= (tmp
& WM0_PIPE_PLANE_MASK
) >> WM0_PIPE_PLANE_SHIFT
;
4267 active
->wm
[0].spr_val
= (tmp
& WM0_PIPE_SPRITE_MASK
) >> WM0_PIPE_SPRITE_SHIFT
;
4268 active
->wm
[0].cur_val
= tmp
& WM0_PIPE_CURSOR_MASK
;
4269 active
->linetime
= hw
->wm_linetime
[pipe
];
4271 int level
, max_level
= ilk_wm_max_level(dev
);
4274 * For inactive pipes, all watermark levels
4275 * should be marked as enabled but zeroed,
4276 * which is what we'd compute them to.
4278 for (level
= 0; level
<= max_level
; level
++)
4279 active
->wm
[level
].enable
= true;
4282 intel_crtc
->wm
.active
.ilk
= *active
;
4285 #define _FW_WM(value, plane) \
4286 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
4287 #define _FW_WM_VLV(value, plane) \
4288 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
4290 static void vlv_read_wm_values(struct drm_i915_private
*dev_priv
,
4291 struct vlv_wm_values
*wm
)
4296 for_each_pipe(dev_priv
, pipe
) {
4297 tmp
= I915_READ(VLV_DDL(pipe
));
4299 wm
->ddl
[pipe
].primary
=
4300 (tmp
>> DDL_PLANE_SHIFT
) & (DDL_PRECISION_HIGH
| DRAIN_LATENCY_MASK
);
4301 wm
->ddl
[pipe
].cursor
=
4302 (tmp
>> DDL_CURSOR_SHIFT
) & (DDL_PRECISION_HIGH
| DRAIN_LATENCY_MASK
);
4303 wm
->ddl
[pipe
].sprite
[0] =
4304 (tmp
>> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH
| DRAIN_LATENCY_MASK
);
4305 wm
->ddl
[pipe
].sprite
[1] =
4306 (tmp
>> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH
| DRAIN_LATENCY_MASK
);
4309 tmp
= I915_READ(DSPFW1
);
4310 wm
->sr
.plane
= _FW_WM(tmp
, SR
);
4311 wm
->pipe
[PIPE_B
].cursor
= _FW_WM(tmp
, CURSORB
);
4312 wm
->pipe
[PIPE_B
].primary
= _FW_WM_VLV(tmp
, PLANEB
);
4313 wm
->pipe
[PIPE_A
].primary
= _FW_WM_VLV(tmp
, PLANEA
);
4315 tmp
= I915_READ(DSPFW2
);
4316 wm
->pipe
[PIPE_A
].sprite
[1] = _FW_WM_VLV(tmp
, SPRITEB
);
4317 wm
->pipe
[PIPE_A
].cursor
= _FW_WM(tmp
, CURSORA
);
4318 wm
->pipe
[PIPE_A
].sprite
[0] = _FW_WM_VLV(tmp
, SPRITEA
);
4320 tmp
= I915_READ(DSPFW3
);
4321 wm
->sr
.cursor
= _FW_WM(tmp
, CURSOR_SR
);
4323 if (IS_CHERRYVIEW(dev_priv
)) {
4324 tmp
= I915_READ(DSPFW7_CHV
);
4325 wm
->pipe
[PIPE_B
].sprite
[1] = _FW_WM_VLV(tmp
, SPRITED
);
4326 wm
->pipe
[PIPE_B
].sprite
[0] = _FW_WM_VLV(tmp
, SPRITEC
);
4328 tmp
= I915_READ(DSPFW8_CHV
);
4329 wm
->pipe
[PIPE_C
].sprite
[1] = _FW_WM_VLV(tmp
, SPRITEF
);
4330 wm
->pipe
[PIPE_C
].sprite
[0] = _FW_WM_VLV(tmp
, SPRITEE
);
4332 tmp
= I915_READ(DSPFW9_CHV
);
4333 wm
->pipe
[PIPE_C
].primary
= _FW_WM_VLV(tmp
, PLANEC
);
4334 wm
->pipe
[PIPE_C
].cursor
= _FW_WM(tmp
, CURSORC
);
4336 tmp
= I915_READ(DSPHOWM
);
4337 wm
->sr
.plane
|= _FW_WM(tmp
, SR_HI
) << 9;
4338 wm
->pipe
[PIPE_C
].sprite
[1] |= _FW_WM(tmp
, SPRITEF_HI
) << 8;
4339 wm
->pipe
[PIPE_C
].sprite
[0] |= _FW_WM(tmp
, SPRITEE_HI
) << 8;
4340 wm
->pipe
[PIPE_C
].primary
|= _FW_WM(tmp
, PLANEC_HI
) << 8;
4341 wm
->pipe
[PIPE_B
].sprite
[1] |= _FW_WM(tmp
, SPRITED_HI
) << 8;
4342 wm
->pipe
[PIPE_B
].sprite
[0] |= _FW_WM(tmp
, SPRITEC_HI
) << 8;
4343 wm
->pipe
[PIPE_B
].primary
|= _FW_WM(tmp
, PLANEB_HI
) << 8;
4344 wm
->pipe
[PIPE_A
].sprite
[1] |= _FW_WM(tmp
, SPRITEB_HI
) << 8;
4345 wm
->pipe
[PIPE_A
].sprite
[0] |= _FW_WM(tmp
, SPRITEA_HI
) << 8;
4346 wm
->pipe
[PIPE_A
].primary
|= _FW_WM(tmp
, PLANEA_HI
) << 8;
4348 tmp
= I915_READ(DSPFW7
);
4349 wm
->pipe
[PIPE_B
].sprite
[1] = _FW_WM_VLV(tmp
, SPRITED
);
4350 wm
->pipe
[PIPE_B
].sprite
[0] = _FW_WM_VLV(tmp
, SPRITEC
);
4352 tmp
= I915_READ(DSPHOWM
);
4353 wm
->sr
.plane
|= _FW_WM(tmp
, SR_HI
) << 9;
4354 wm
->pipe
[PIPE_B
].sprite
[1] |= _FW_WM(tmp
, SPRITED_HI
) << 8;
4355 wm
->pipe
[PIPE_B
].sprite
[0] |= _FW_WM(tmp
, SPRITEC_HI
) << 8;
4356 wm
->pipe
[PIPE_B
].primary
|= _FW_WM(tmp
, PLANEB_HI
) << 8;
4357 wm
->pipe
[PIPE_A
].sprite
[1] |= _FW_WM(tmp
, SPRITEB_HI
) << 8;
4358 wm
->pipe
[PIPE_A
].sprite
[0] |= _FW_WM(tmp
, SPRITEA_HI
) << 8;
4359 wm
->pipe
[PIPE_A
].primary
|= _FW_WM(tmp
, PLANEA_HI
) << 8;
4366 void vlv_wm_get_hw_state(struct drm_device
*dev
)
4368 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4369 struct vlv_wm_values
*wm
= &dev_priv
->wm
.vlv
;
4370 struct intel_plane
*plane
;
4374 vlv_read_wm_values(dev_priv
, wm
);
4376 for_each_intel_plane(dev
, plane
) {
4377 switch (plane
->base
.type
) {
4379 case DRM_PLANE_TYPE_CURSOR
:
4380 plane
->wm
.fifo_size
= 63;
4382 case DRM_PLANE_TYPE_PRIMARY
:
4383 plane
->wm
.fifo_size
= vlv_get_fifo_size(dev
, plane
->pipe
, 0);
4385 case DRM_PLANE_TYPE_OVERLAY
:
4386 sprite
= plane
->plane
;
4387 plane
->wm
.fifo_size
= vlv_get_fifo_size(dev
, plane
->pipe
, sprite
+ 1);
4392 wm
->cxsr
= I915_READ(FW_BLC_SELF_VLV
) & FW_CSPWRDWNEN
;
4393 wm
->level
= VLV_WM_LEVEL_PM2
;
4395 if (IS_CHERRYVIEW(dev_priv
)) {
4396 mutex_lock(&dev_priv
->rps
.hw_lock
);
4398 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
4399 if (val
& DSP_MAXFIFO_PM5_ENABLE
)
4400 wm
->level
= VLV_WM_LEVEL_PM5
;
4403 * If DDR DVFS is disabled in the BIOS, Punit
4404 * will never ack the request. So if that happens
4405 * assume we don't have to enable/disable DDR DVFS
4406 * dynamically. To test that just set the REQ_ACK
4407 * bit to poke the Punit, but don't change the
4408 * HIGH/LOW bits so that we don't actually change
4409 * the current state.
4411 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DDR_SETUP2
);
4412 val
|= FORCE_DDR_FREQ_REQ_ACK
;
4413 vlv_punit_write(dev_priv
, PUNIT_REG_DDR_SETUP2
, val
);
4415 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DDR_SETUP2
) &
4416 FORCE_DDR_FREQ_REQ_ACK
) == 0, 3)) {
4417 DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4418 "assuming DDR DVFS is disabled\n");
4419 dev_priv
->wm
.max_level
= VLV_WM_LEVEL_PM5
;
4421 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DDR_SETUP2
);
4422 if ((val
& FORCE_DDR_HIGH_FREQ
) == 0)
4423 wm
->level
= VLV_WM_LEVEL_DDR_DVFS
;
4426 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4429 for_each_pipe(dev_priv
, pipe
)
4430 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4431 pipe_name(pipe
), wm
->pipe
[pipe
].primary
, wm
->pipe
[pipe
].cursor
,
4432 wm
->pipe
[pipe
].sprite
[0], wm
->pipe
[pipe
].sprite
[1]);
4434 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4435 wm
->sr
.plane
, wm
->sr
.cursor
, wm
->level
, wm
->cxsr
);
4438 void ilk_wm_get_hw_state(struct drm_device
*dev
)
4440 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4441 struct ilk_wm_values
*hw
= &dev_priv
->wm
.hw
;
4442 struct drm_crtc
*crtc
;
4444 for_each_crtc(dev
, crtc
)
4445 ilk_pipe_wm_get_hw_state(crtc
);
4447 hw
->wm_lp
[0] = I915_READ(WM1_LP_ILK
);
4448 hw
->wm_lp
[1] = I915_READ(WM2_LP_ILK
);
4449 hw
->wm_lp
[2] = I915_READ(WM3_LP_ILK
);
4451 hw
->wm_lp_spr
[0] = I915_READ(WM1S_LP_ILK
);
4452 if (INTEL_INFO(dev
)->gen
>= 7) {
4453 hw
->wm_lp_spr
[1] = I915_READ(WM2S_LP_IVB
);
4454 hw
->wm_lp_spr
[2] = I915_READ(WM3S_LP_IVB
);
4457 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
4458 hw
->partitioning
= (I915_READ(WM_MISC
) & WM_MISC_DATA_PARTITION_5_6
) ?
4459 INTEL_DDB_PART_5_6
: INTEL_DDB_PART_1_2
;
4460 else if (IS_IVYBRIDGE(dev
))
4461 hw
->partitioning
= (I915_READ(DISP_ARB_CTL2
) & DISP_DATA_PARTITION_5_6
) ?
4462 INTEL_DDB_PART_5_6
: INTEL_DDB_PART_1_2
;
4465 !(I915_READ(DISP_ARB_CTL
) & DISP_FBC_WM_DIS
);
4469 * intel_update_watermarks - update FIFO watermark values based on current modes
4471 * Calculate watermark values for the various WM regs based on current mode
4472 * and plane configuration.
4474 * There are several cases to deal with here:
4475 * - normal (i.e. non-self-refresh)
4476 * - self-refresh (SR) mode
4477 * - lines are large relative to FIFO size (buffer can hold up to 2)
4478 * - lines are small relative to FIFO size (buffer can hold more than 2
4479 * lines), so need to account for TLB latency
4481 * The normal calculation is:
4482 * watermark = dotclock * bytes per pixel * latency
4483 * where latency is platform & configuration dependent (we assume pessimal
4486 * The SR calculation is:
4487 * watermark = (trunc(latency/line time)+1) * surface width *
4490 * line time = htotal / dotclock
4491 * surface width = hdisplay for normal plane and 64 for cursor
4492 * and latency is assumed to be high, as above.
4494 * The final value programmed to the register should always be rounded up,
4495 * and include an extra 2 entries to account for clock crossings.
4497 * We don't use the sprite, so we can ignore that. And on Crestline we have
4498 * to set the non-SR watermarks to 8.
4500 void intel_update_watermarks(struct drm_crtc
*crtc
)
4502 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
4504 if (dev_priv
->display
.update_wm
)
4505 dev_priv
->display
.update_wm(crtc
);
4509 * Lock protecting IPS related data structures
4511 DEFINE_SPINLOCK(mchdev_lock
);
4513 /* Global for IPS driver to get at the current i915 device. Protected by
4515 static struct drm_i915_private
*i915_mch_dev
;
4517 bool ironlake_set_drps(struct drm_i915_private
*dev_priv
, u8 val
)
4521 assert_spin_locked(&mchdev_lock
);
4523 rgvswctl
= I915_READ16(MEMSWCTL
);
4524 if (rgvswctl
& MEMCTL_CMD_STS
) {
4525 DRM_DEBUG("gpu busy, RCS change rejected\n");
4526 return false; /* still busy with another command */
4529 rgvswctl
= (MEMCTL_CMD_CHFREQ
<< MEMCTL_CMD_SHIFT
) |
4530 (val
<< MEMCTL_FREQ_SHIFT
) | MEMCTL_SFCAVM
;
4531 I915_WRITE16(MEMSWCTL
, rgvswctl
);
4532 POSTING_READ16(MEMSWCTL
);
4534 rgvswctl
|= MEMCTL_CMD_STS
;
4535 I915_WRITE16(MEMSWCTL
, rgvswctl
);
4540 static void ironlake_enable_drps(struct drm_i915_private
*dev_priv
)
4543 u8 fmax
, fmin
, fstart
, vstart
;
4545 spin_lock_irq(&mchdev_lock
);
4547 rgvmodectl
= I915_READ(MEMMODECTL
);
4549 /* Enable temp reporting */
4550 I915_WRITE16(PMMISC
, I915_READ(PMMISC
) | MCPPCE_EN
);
4551 I915_WRITE16(TSC1
, I915_READ(TSC1
) | TSE
);
4553 /* 100ms RC evaluation intervals */
4554 I915_WRITE(RCUPEI
, 100000);
4555 I915_WRITE(RCDNEI
, 100000);
4557 /* Set max/min thresholds to 90ms and 80ms respectively */
4558 I915_WRITE(RCBMAXAVG
, 90000);
4559 I915_WRITE(RCBMINAVG
, 80000);
4561 I915_WRITE(MEMIHYST
, 1);
4563 /* Set up min, max, and cur for interrupt handling */
4564 fmax
= (rgvmodectl
& MEMMODE_FMAX_MASK
) >> MEMMODE_FMAX_SHIFT
;
4565 fmin
= (rgvmodectl
& MEMMODE_FMIN_MASK
);
4566 fstart
= (rgvmodectl
& MEMMODE_FSTART_MASK
) >>
4567 MEMMODE_FSTART_SHIFT
;
4569 vstart
= (I915_READ(PXVFREQ(fstart
)) & PXVFREQ_PX_MASK
) >>
4572 dev_priv
->ips
.fmax
= fmax
; /* IPS callback will increase this */
4573 dev_priv
->ips
.fstart
= fstart
;
4575 dev_priv
->ips
.max_delay
= fstart
;
4576 dev_priv
->ips
.min_delay
= fmin
;
4577 dev_priv
->ips
.cur_delay
= fstart
;
4579 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4580 fmax
, fmin
, fstart
);
4582 I915_WRITE(MEMINTREN
, MEMINT_CX_SUPR_EN
| MEMINT_EVAL_CHG_EN
);
4585 * Interrupts will be enabled in ironlake_irq_postinstall
4588 I915_WRITE(VIDSTART
, vstart
);
4589 POSTING_READ(VIDSTART
);
4591 rgvmodectl
|= MEMMODE_SWMODE_EN
;
4592 I915_WRITE(MEMMODECTL
, rgvmodectl
);
4594 if (wait_for_atomic((I915_READ(MEMSWCTL
) & MEMCTL_CMD_STS
) == 0, 10))
4595 DRM_ERROR("stuck trying to change perf mode\n");
4598 ironlake_set_drps(dev_priv
, fstart
);
4600 dev_priv
->ips
.last_count1
= I915_READ(DMIEC
) +
4601 I915_READ(DDREC
) + I915_READ(CSIEC
);
4602 dev_priv
->ips
.last_time1
= jiffies_to_msecs(jiffies
);
4603 dev_priv
->ips
.last_count2
= I915_READ(GFXEC
);
4604 dev_priv
->ips
.last_time2
= ktime_get_raw_ns();
4606 spin_unlock_irq(&mchdev_lock
);
4609 static void ironlake_disable_drps(struct drm_i915_private
*dev_priv
)
4613 spin_lock_irq(&mchdev_lock
);
4615 rgvswctl
= I915_READ16(MEMSWCTL
);
4617 /* Ack interrupts, disable EFC interrupt */
4618 I915_WRITE(MEMINTREN
, I915_READ(MEMINTREN
) & ~MEMINT_EVAL_CHG_EN
);
4619 I915_WRITE(MEMINTRSTS
, MEMINT_EVAL_CHG
);
4620 I915_WRITE(DEIER
, I915_READ(DEIER
) & ~DE_PCU_EVENT
);
4621 I915_WRITE(DEIIR
, DE_PCU_EVENT
);
4622 I915_WRITE(DEIMR
, I915_READ(DEIMR
) | DE_PCU_EVENT
);
4624 /* Go back to the starting frequency */
4625 ironlake_set_drps(dev_priv
, dev_priv
->ips
.fstart
);
4627 rgvswctl
|= MEMCTL_CMD_STS
;
4628 I915_WRITE(MEMSWCTL
, rgvswctl
);
4631 spin_unlock_irq(&mchdev_lock
);
4634 /* There's a funny hw issue where the hw returns all 0 when reading from
4635 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4636 * ourselves, instead of doing a rmw cycle (which might result in us clearing
4637 * all limits and the gpu stuck at whatever frequency it is at atm).
4639 static u32
intel_rps_limits(struct drm_i915_private
*dev_priv
, u8 val
)
4643 /* Only set the down limit when we've reached the lowest level to avoid
4644 * getting more interrupts, otherwise leave this clear. This prevents a
4645 * race in the hw when coming out of rc6: There's a tiny window where
4646 * the hw runs at the minimal clock before selecting the desired
4647 * frequency, if the down threshold expires in that window we will not
4648 * receive a down interrupt. */
4649 if (IS_GEN9(dev_priv
)) {
4650 limits
= (dev_priv
->rps
.max_freq_softlimit
) << 23;
4651 if (val
<= dev_priv
->rps
.min_freq_softlimit
)
4652 limits
|= (dev_priv
->rps
.min_freq_softlimit
) << 14;
4654 limits
= dev_priv
->rps
.max_freq_softlimit
<< 24;
4655 if (val
<= dev_priv
->rps
.min_freq_softlimit
)
4656 limits
|= dev_priv
->rps
.min_freq_softlimit
<< 16;
4662 static void gen6_set_rps_thresholds(struct drm_i915_private
*dev_priv
, u8 val
)
4665 u32 threshold_up
= 0, threshold_down
= 0; /* in % */
4666 u32 ei_up
= 0, ei_down
= 0;
4668 new_power
= dev_priv
->rps
.power
;
4669 switch (dev_priv
->rps
.power
) {
4671 if (val
> dev_priv
->rps
.efficient_freq
+ 1 &&
4672 val
> dev_priv
->rps
.cur_freq
)
4673 new_power
= BETWEEN
;
4677 if (val
<= dev_priv
->rps
.efficient_freq
&&
4678 val
< dev_priv
->rps
.cur_freq
)
4679 new_power
= LOW_POWER
;
4680 else if (val
>= dev_priv
->rps
.rp0_freq
&&
4681 val
> dev_priv
->rps
.cur_freq
)
4682 new_power
= HIGH_POWER
;
4686 if (val
< (dev_priv
->rps
.rp1_freq
+ dev_priv
->rps
.rp0_freq
) >> 1 &&
4687 val
< dev_priv
->rps
.cur_freq
)
4688 new_power
= BETWEEN
;
4691 /* Max/min bins are special */
4692 if (val
<= dev_priv
->rps
.min_freq_softlimit
)
4693 new_power
= LOW_POWER
;
4694 if (val
>= dev_priv
->rps
.max_freq_softlimit
)
4695 new_power
= HIGH_POWER
;
4696 if (new_power
== dev_priv
->rps
.power
)
4699 /* Note the units here are not exactly 1us, but 1280ns. */
4700 switch (new_power
) {
4702 /* Upclock if more than 95% busy over 16ms */
4706 /* Downclock if less than 85% busy over 32ms */
4708 threshold_down
= 85;
4712 /* Upclock if more than 90% busy over 13ms */
4716 /* Downclock if less than 75% busy over 32ms */
4718 threshold_down
= 75;
4722 /* Upclock if more than 85% busy over 10ms */
4726 /* Downclock if less than 60% busy over 32ms */
4728 threshold_down
= 60;
4732 I915_WRITE(GEN6_RP_UP_EI
,
4733 GT_INTERVAL_FROM_US(dev_priv
, ei_up
));
4734 I915_WRITE(GEN6_RP_UP_THRESHOLD
,
4735 GT_INTERVAL_FROM_US(dev_priv
,
4736 ei_up
* threshold_up
/ 100));
4738 I915_WRITE(GEN6_RP_DOWN_EI
,
4739 GT_INTERVAL_FROM_US(dev_priv
, ei_down
));
4740 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
,
4741 GT_INTERVAL_FROM_US(dev_priv
,
4742 ei_down
* threshold_down
/ 100));
4744 I915_WRITE(GEN6_RP_CONTROL
,
4745 GEN6_RP_MEDIA_TURBO
|
4746 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
4747 GEN6_RP_MEDIA_IS_GFX
|
4749 GEN6_RP_UP_BUSY_AVG
|
4750 GEN6_RP_DOWN_IDLE_AVG
);
4752 dev_priv
->rps
.power
= new_power
;
4753 dev_priv
->rps
.up_threshold
= threshold_up
;
4754 dev_priv
->rps
.down_threshold
= threshold_down
;
4755 dev_priv
->rps
.last_adj
= 0;
4758 static u32
gen6_rps_pm_mask(struct drm_i915_private
*dev_priv
, u8 val
)
4762 if (val
> dev_priv
->rps
.min_freq_softlimit
)
4763 mask
|= GEN6_PM_RP_DOWN_EI_EXPIRED
| GEN6_PM_RP_DOWN_THRESHOLD
| GEN6_PM_RP_DOWN_TIMEOUT
;
4764 if (val
< dev_priv
->rps
.max_freq_softlimit
)
4765 mask
|= GEN6_PM_RP_UP_EI_EXPIRED
| GEN6_PM_RP_UP_THRESHOLD
;
4767 mask
&= dev_priv
->pm_rps_events
;
4769 return gen6_sanitize_rps_pm_mask(dev_priv
, ~mask
);
4772 /* gen6_set_rps is called to update the frequency request, but should also be
4773 * called when the range (min_delay and max_delay) is modified so that we can
4774 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
4775 static void gen6_set_rps(struct drm_i915_private
*dev_priv
, u8 val
)
4777 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4778 if (IS_BXT_REVID(dev_priv
, 0, BXT_REVID_A1
))
4781 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
4782 WARN_ON(val
> dev_priv
->rps
.max_freq
);
4783 WARN_ON(val
< dev_priv
->rps
.min_freq
);
4785 /* min/max delay may still have been modified so be sure to
4786 * write the limits value.
4788 if (val
!= dev_priv
->rps
.cur_freq
) {
4789 gen6_set_rps_thresholds(dev_priv
, val
);
4791 if (IS_GEN9(dev_priv
))
4792 I915_WRITE(GEN6_RPNSWREQ
,
4793 GEN9_FREQUENCY(val
));
4794 else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
4795 I915_WRITE(GEN6_RPNSWREQ
,
4796 HSW_FREQUENCY(val
));
4798 I915_WRITE(GEN6_RPNSWREQ
,
4799 GEN6_FREQUENCY(val
) |
4801 GEN6_AGGRESSIVE_TURBO
);
4804 /* Make sure we continue to get interrupts
4805 * until we hit the minimum or maximum frequencies.
4807 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS
, intel_rps_limits(dev_priv
, val
));
4808 I915_WRITE(GEN6_PMINTRMSK
, gen6_rps_pm_mask(dev_priv
, val
));
4810 POSTING_READ(GEN6_RPNSWREQ
);
4812 dev_priv
->rps
.cur_freq
= val
;
4813 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv
, val
));
4816 static void valleyview_set_rps(struct drm_i915_private
*dev_priv
, u8 val
)
4818 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
4819 WARN_ON(val
> dev_priv
->rps
.max_freq
);
4820 WARN_ON(val
< dev_priv
->rps
.min_freq
);
4822 if (WARN_ONCE(IS_CHERRYVIEW(dev_priv
) && (val
& 1),
4823 "Odd GPU freq value\n"))
4826 I915_WRITE(GEN6_PMINTRMSK
, gen6_rps_pm_mask(dev_priv
, val
));
4828 if (val
!= dev_priv
->rps
.cur_freq
) {
4829 vlv_punit_write(dev_priv
, PUNIT_REG_GPU_FREQ_REQ
, val
);
4830 if (!IS_CHERRYVIEW(dev_priv
))
4831 gen6_set_rps_thresholds(dev_priv
, val
);
4834 dev_priv
->rps
.cur_freq
= val
;
4835 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv
, val
));
4838 /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
4840 * * If Gfx is Idle, then
4841 * 1. Forcewake Media well.
4842 * 2. Request idle freq.
4843 * 3. Release Forcewake of Media well.
4845 static void vlv_set_rps_idle(struct drm_i915_private
*dev_priv
)
4847 u32 val
= dev_priv
->rps
.idle_freq
;
4849 if (dev_priv
->rps
.cur_freq
<= val
)
4852 /* Wake up the media well, as that takes a lot less
4853 * power than the Render well. */
4854 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_MEDIA
);
4855 valleyview_set_rps(dev_priv
, val
);
4856 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_MEDIA
);
4859 void gen6_rps_busy(struct drm_i915_private
*dev_priv
)
4861 mutex_lock(&dev_priv
->rps
.hw_lock
);
4862 if (dev_priv
->rps
.enabled
) {
4863 if (dev_priv
->pm_rps_events
& (GEN6_PM_RP_DOWN_EI_EXPIRED
| GEN6_PM_RP_UP_EI_EXPIRED
))
4864 gen6_rps_reset_ei(dev_priv
);
4865 I915_WRITE(GEN6_PMINTRMSK
,
4866 gen6_rps_pm_mask(dev_priv
, dev_priv
->rps
.cur_freq
));
4868 gen6_enable_rps_interrupts(dev_priv
);
4870 /* Ensure we start at the user's desired frequency */
4871 intel_set_rps(dev_priv
,
4872 clamp(dev_priv
->rps
.cur_freq
,
4873 dev_priv
->rps
.min_freq_softlimit
,
4874 dev_priv
->rps
.max_freq_softlimit
));
4876 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4879 void gen6_rps_idle(struct drm_i915_private
*dev_priv
)
4881 /* Flush our bottom-half so that it does not race with us
4882 * setting the idle frequency and so that it is bounded by
4883 * our rpm wakeref. And then disable the interrupts to stop any
4884 * futher RPS reclocking whilst we are asleep.
4886 gen6_disable_rps_interrupts(dev_priv
);
4888 mutex_lock(&dev_priv
->rps
.hw_lock
);
4889 if (dev_priv
->rps
.enabled
) {
4890 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
4891 vlv_set_rps_idle(dev_priv
);
4893 gen6_set_rps(dev_priv
, dev_priv
->rps
.idle_freq
);
4894 dev_priv
->rps
.last_adj
= 0;
4895 I915_WRITE(GEN6_PMINTRMSK
,
4896 gen6_sanitize_rps_pm_mask(dev_priv
, ~0));
4898 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4900 spin_lock(&dev_priv
->rps
.client_lock
);
4901 while (!list_empty(&dev_priv
->rps
.clients
))
4902 list_del_init(dev_priv
->rps
.clients
.next
);
4903 spin_unlock(&dev_priv
->rps
.client_lock
);
4906 void gen6_rps_boost(struct drm_i915_private
*dev_priv
,
4907 struct intel_rps_client
*rps
,
4908 unsigned long submitted
)
4910 /* This is intentionally racy! We peek at the state here, then
4911 * validate inside the RPS worker.
4913 if (!(dev_priv
->gt
.awake
&&
4914 dev_priv
->rps
.enabled
&&
4915 dev_priv
->rps
.cur_freq
< dev_priv
->rps
.max_freq_softlimit
))
4918 /* Force a RPS boost (and don't count it against the client) if
4919 * the GPU is severely congested.
4921 if (rps
&& time_after(jiffies
, submitted
+ DRM_I915_THROTTLE_JIFFIES
))
4924 spin_lock(&dev_priv
->rps
.client_lock
);
4925 if (rps
== NULL
|| list_empty(&rps
->link
)) {
4926 spin_lock_irq(&dev_priv
->irq_lock
);
4927 if (dev_priv
->rps
.interrupts_enabled
) {
4928 dev_priv
->rps
.client_boost
= true;
4929 schedule_work(&dev_priv
->rps
.work
);
4931 spin_unlock_irq(&dev_priv
->irq_lock
);
4934 list_add(&rps
->link
, &dev_priv
->rps
.clients
);
4937 dev_priv
->rps
.boosts
++;
4939 spin_unlock(&dev_priv
->rps
.client_lock
);
4942 void intel_set_rps(struct drm_i915_private
*dev_priv
, u8 val
)
4944 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
4945 valleyview_set_rps(dev_priv
, val
);
4947 gen6_set_rps(dev_priv
, val
);
4950 static void gen9_disable_rc6(struct drm_i915_private
*dev_priv
)
4952 I915_WRITE(GEN6_RC_CONTROL
, 0);
4953 I915_WRITE(GEN9_PG_ENABLE
, 0);
4956 static void gen9_disable_rps(struct drm_i915_private
*dev_priv
)
4958 I915_WRITE(GEN6_RP_CONTROL
, 0);
4961 static void gen6_disable_rps(struct drm_i915_private
*dev_priv
)
4963 I915_WRITE(GEN6_RC_CONTROL
, 0);
4964 I915_WRITE(GEN6_RPNSWREQ
, 1 << 31);
4965 I915_WRITE(GEN6_RP_CONTROL
, 0);
4968 static void cherryview_disable_rps(struct drm_i915_private
*dev_priv
)
4970 I915_WRITE(GEN6_RC_CONTROL
, 0);
4973 static void valleyview_disable_rps(struct drm_i915_private
*dev_priv
)
4975 /* we're doing forcewake before Disabling RC6,
4976 * This what the BIOS expects when going into suspend */
4977 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
4979 I915_WRITE(GEN6_RC_CONTROL
, 0);
4981 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
4984 static void intel_print_rc6_info(struct drm_i915_private
*dev_priv
, u32 mode
)
4986 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
4987 if (mode
& (GEN7_RC_CTL_TO_MODE
| GEN6_RC_CTL_EI_MODE(1)))
4988 mode
= GEN6_RC_CTL_RC6_ENABLE
;
4992 if (HAS_RC6p(dev_priv
))
4993 DRM_DEBUG_DRIVER("Enabling RC6 states: "
4994 "RC6 %s RC6p %s RC6pp %s\n",
4995 onoff(mode
& GEN6_RC_CTL_RC6_ENABLE
),
4996 onoff(mode
& GEN6_RC_CTL_RC6p_ENABLE
),
4997 onoff(mode
& GEN6_RC_CTL_RC6pp_ENABLE
));
5000 DRM_DEBUG_DRIVER("Enabling RC6 states: RC6 %s\n",
5001 onoff(mode
& GEN6_RC_CTL_RC6_ENABLE
));
5004 static bool bxt_check_bios_rc6_setup(struct drm_i915_private
*dev_priv
)
5006 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
5007 bool enable_rc6
= true;
5008 unsigned long rc6_ctx_base
;
5012 rc_ctl
= I915_READ(GEN6_RC_CONTROL
);
5013 rc_sw_target
= (I915_READ(GEN6_RC_STATE
) & RC_SW_TARGET_STATE_MASK
) >>
5014 RC_SW_TARGET_STATE_SHIFT
;
5015 DRM_DEBUG_DRIVER("BIOS enabled RC states: "
5016 "HW_CTRL %s HW_RC6 %s SW_TARGET_STATE %x\n",
5017 onoff(rc_ctl
& GEN6_RC_CTL_HW_ENABLE
),
5018 onoff(rc_ctl
& GEN6_RC_CTL_RC6_ENABLE
),
5021 if (!(I915_READ(RC6_LOCATION
) & RC6_CTX_IN_DRAM
)) {
5022 DRM_DEBUG_DRIVER("RC6 Base location not set properly.\n");
5027 * The exact context size is not known for BXT, so assume a page size
5030 rc6_ctx_base
= I915_READ(RC6_CTX_BASE
) & RC6_CTX_BASE_MASK
;
5031 if (!((rc6_ctx_base
>= ggtt
->stolen_reserved_base
) &&
5032 (rc6_ctx_base
+ PAGE_SIZE
<= ggtt
->stolen_reserved_base
+
5033 ggtt
->stolen_reserved_size
))) {
5034 DRM_DEBUG_DRIVER("RC6 Base address not as expected.\n");
5038 if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT
) & IDLE_TIME_MASK
) > 1) &&
5039 ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0
) & IDLE_TIME_MASK
) > 1) &&
5040 ((I915_READ(PWRCTX_MAXCNT_BCSUNIT
) & IDLE_TIME_MASK
) > 1) &&
5041 ((I915_READ(PWRCTX_MAXCNT_VECSUNIT
) & IDLE_TIME_MASK
) > 1))) {
5042 DRM_DEBUG_DRIVER("Engine Idle wait time not set properly.\n");
5046 if (!I915_READ(GEN8_PUSHBUS_CONTROL
) ||
5047 !I915_READ(GEN8_PUSHBUS_ENABLE
) ||
5048 !I915_READ(GEN8_PUSHBUS_SHIFT
)) {
5049 DRM_DEBUG_DRIVER("Pushbus not setup properly.\n");
5053 if (!I915_READ(GEN6_GFXPAUSE
)) {
5054 DRM_DEBUG_DRIVER("GFX pause not setup properly.\n");
5058 if (!I915_READ(GEN8_MISC_CTRL0
)) {
5059 DRM_DEBUG_DRIVER("GPM control not setup properly.\n");
5066 int sanitize_rc6_option(struct drm_i915_private
*dev_priv
, int enable_rc6
)
5068 /* No RC6 before Ironlake and code is gone for ilk. */
5069 if (INTEL_INFO(dev_priv
)->gen
< 6)
5075 if (IS_BROXTON(dev_priv
) && !bxt_check_bios_rc6_setup(dev_priv
)) {
5076 DRM_INFO("RC6 disabled by BIOS\n");
5080 /* Respect the kernel parameter if it is set */
5081 if (enable_rc6
>= 0) {
5084 if (HAS_RC6p(dev_priv
))
5085 mask
= INTEL_RC6_ENABLE
| INTEL_RC6p_ENABLE
|
5088 mask
= INTEL_RC6_ENABLE
;
5090 if ((enable_rc6
& mask
) != enable_rc6
)
5091 DRM_DEBUG_DRIVER("Adjusting RC6 mask to %d "
5092 "(requested %d, valid %d)\n",
5093 enable_rc6
& mask
, enable_rc6
, mask
);
5095 return enable_rc6
& mask
;
5098 if (IS_IVYBRIDGE(dev_priv
))
5099 return (INTEL_RC6_ENABLE
| INTEL_RC6p_ENABLE
);
5101 return INTEL_RC6_ENABLE
;
5104 static void gen6_init_rps_frequencies(struct drm_i915_private
*dev_priv
)
5106 uint32_t rp_state_cap
;
5107 u32 ddcc_status
= 0;
5110 /* All of these values are in units of 50MHz */
5111 dev_priv
->rps
.cur_freq
= 0;
5112 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
5113 if (IS_BROXTON(dev_priv
)) {
5114 rp_state_cap
= I915_READ(BXT_RP_STATE_CAP
);
5115 dev_priv
->rps
.rp0_freq
= (rp_state_cap
>> 16) & 0xff;
5116 dev_priv
->rps
.rp1_freq
= (rp_state_cap
>> 8) & 0xff;
5117 dev_priv
->rps
.min_freq
= (rp_state_cap
>> 0) & 0xff;
5119 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
5120 dev_priv
->rps
.rp0_freq
= (rp_state_cap
>> 0) & 0xff;
5121 dev_priv
->rps
.rp1_freq
= (rp_state_cap
>> 8) & 0xff;
5122 dev_priv
->rps
.min_freq
= (rp_state_cap
>> 16) & 0xff;
5125 /* hw_max = RP0 until we check for overclocking */
5126 dev_priv
->rps
.max_freq
= dev_priv
->rps
.rp0_freq
;
5128 dev_priv
->rps
.efficient_freq
= dev_priv
->rps
.rp1_freq
;
5129 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
) ||
5130 IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
)) {
5131 ret
= sandybridge_pcode_read(dev_priv
,
5132 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL
,
5135 dev_priv
->rps
.efficient_freq
=
5137 ((ddcc_status
>> 8) & 0xff),
5138 dev_priv
->rps
.min_freq
,
5139 dev_priv
->rps
.max_freq
);
5142 if (IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
)) {
5143 /* Store the frequency values in 16.66 MHZ units, which is
5144 the natural hardware unit for SKL */
5145 dev_priv
->rps
.rp0_freq
*= GEN9_FREQ_SCALER
;
5146 dev_priv
->rps
.rp1_freq
*= GEN9_FREQ_SCALER
;
5147 dev_priv
->rps
.min_freq
*= GEN9_FREQ_SCALER
;
5148 dev_priv
->rps
.max_freq
*= GEN9_FREQ_SCALER
;
5149 dev_priv
->rps
.efficient_freq
*= GEN9_FREQ_SCALER
;
5152 dev_priv
->rps
.idle_freq
= dev_priv
->rps
.min_freq
;
5154 /* Preserve min/max settings in case of re-init */
5155 if (dev_priv
->rps
.max_freq_softlimit
== 0)
5156 dev_priv
->rps
.max_freq_softlimit
= dev_priv
->rps
.max_freq
;
5158 if (dev_priv
->rps
.min_freq_softlimit
== 0) {
5159 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
5160 dev_priv
->rps
.min_freq_softlimit
=
5161 max_t(int, dev_priv
->rps
.efficient_freq
,
5162 intel_freq_opcode(dev_priv
, 450));
5164 dev_priv
->rps
.min_freq_softlimit
=
5165 dev_priv
->rps
.min_freq
;
5169 /* See the Gen9_GT_PM_Programming_Guide doc for the below */
5170 static void gen9_enable_rps(struct drm_i915_private
*dev_priv
)
5172 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
5174 gen6_init_rps_frequencies(dev_priv
);
5176 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
5177 if (IS_BXT_REVID(dev_priv
, 0, BXT_REVID_A1
)) {
5179 * BIOS could leave the Hw Turbo enabled, so need to explicitly
5180 * clear out the Control register just to avoid inconsitency
5181 * with debugfs interface, which will show Turbo as enabled
5182 * only and that is not expected by the User after adding the
5183 * WaGsvDisableTurbo. Apart from this there is no problem even
5184 * if the Turbo is left enabled in the Control register, as the
5185 * Up/Down interrupts would remain masked.
5187 gen9_disable_rps(dev_priv
);
5188 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
5192 /* Program defaults and thresholds for RPS*/
5193 I915_WRITE(GEN6_RC_VIDEO_FREQ
,
5194 GEN9_FREQUENCY(dev_priv
->rps
.rp1_freq
));
5196 /* 1 second timeout*/
5197 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
,
5198 GT_INTERVAL_FROM_US(dev_priv
, 1000000));
5200 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 0xa);
5202 /* Leaning on the below call to gen6_set_rps to program/setup the
5203 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
5204 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
5205 dev_priv
->rps
.power
= HIGH_POWER
; /* force a reset */
5206 gen6_set_rps(dev_priv
, dev_priv
->rps
.idle_freq
);
5208 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
5211 static void gen9_enable_rc6(struct drm_i915_private
*dev_priv
)
5213 struct intel_engine_cs
*engine
;
5214 uint32_t rc6_mask
= 0;
5216 /* 1a: Software RC state - RC0 */
5217 I915_WRITE(GEN6_RC_STATE
, 0);
5219 /* 1b: Get forcewake during program sequence. Although the driver
5220 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5221 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
5223 /* 2a: Disable RC states. */
5224 I915_WRITE(GEN6_RC_CONTROL
, 0);
5226 /* 2b: Program RC6 thresholds.*/
5228 /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
5229 if (IS_SKYLAKE(dev_priv
))
5230 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 108 << 16);
5232 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 54 << 16);
5233 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000); /* 12500 * 1280ns */
5234 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25); /* 25 * 1280ns */
5235 for_each_engine(engine
, dev_priv
)
5236 I915_WRITE(RING_MAX_IDLE(engine
->mmio_base
), 10);
5238 if (HAS_GUC(dev_priv
))
5239 I915_WRITE(GUC_MAX_IDLE_COUNT
, 0xA);
5241 I915_WRITE(GEN6_RC_SLEEP
, 0);
5243 /* 2c: Program Coarse Power Gating Policies. */
5244 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS
, 25);
5245 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS
, 25);
5247 /* 3a: Enable RC6 */
5248 if (intel_enable_rc6() & INTEL_RC6_ENABLE
)
5249 rc6_mask
= GEN6_RC_CTL_RC6_ENABLE
;
5250 DRM_INFO("RC6 %s\n", onoff(rc6_mask
& GEN6_RC_CTL_RC6_ENABLE
));
5251 /* WaRsUseTimeoutMode */
5252 if (IS_SKL_REVID(dev_priv
, 0, SKL_REVID_D0
) ||
5253 IS_BXT_REVID(dev_priv
, 0, BXT_REVID_A1
)) {
5254 I915_WRITE(GEN6_RC6_THRESHOLD
, 625); /* 800us */
5255 I915_WRITE(GEN6_RC_CONTROL
, GEN6_RC_CTL_HW_ENABLE
|
5256 GEN7_RC_CTL_TO_MODE
|
5259 I915_WRITE(GEN6_RC6_THRESHOLD
, 37500); /* 37.5/125ms per EI */
5260 I915_WRITE(GEN6_RC_CONTROL
, GEN6_RC_CTL_HW_ENABLE
|
5261 GEN6_RC_CTL_EI_MODE(1) |
5266 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
5267 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
5269 if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv
))
5270 I915_WRITE(GEN9_PG_ENABLE
, 0);
5272 I915_WRITE(GEN9_PG_ENABLE
, (rc6_mask
& GEN6_RC_CTL_RC6_ENABLE
) ?
5273 (GEN9_RENDER_PG_ENABLE
| GEN9_MEDIA_PG_ENABLE
) : 0);
5275 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
5278 static void gen8_enable_rps(struct drm_i915_private
*dev_priv
)
5280 struct intel_engine_cs
*engine
;
5281 uint32_t rc6_mask
= 0;
5283 /* 1a: Software RC state - RC0 */
5284 I915_WRITE(GEN6_RC_STATE
, 0);
5286 /* 1c & 1d: Get forcewake during program sequence. Although the driver
5287 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5288 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
5290 /* 2a: Disable RC states. */
5291 I915_WRITE(GEN6_RC_CONTROL
, 0);
5293 /* Initialize rps frequencies */
5294 gen6_init_rps_frequencies(dev_priv
);
5296 /* 2b: Program RC6 thresholds.*/
5297 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 40 << 16);
5298 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000); /* 12500 * 1280ns */
5299 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25); /* 25 * 1280ns */
5300 for_each_engine(engine
, dev_priv
)
5301 I915_WRITE(RING_MAX_IDLE(engine
->mmio_base
), 10);
5302 I915_WRITE(GEN6_RC_SLEEP
, 0);
5303 if (IS_BROADWELL(dev_priv
))
5304 I915_WRITE(GEN6_RC6_THRESHOLD
, 625); /* 800us/1.28 for TO */
5306 I915_WRITE(GEN6_RC6_THRESHOLD
, 50000); /* 50/125ms per EI */
5309 if (intel_enable_rc6() & INTEL_RC6_ENABLE
)
5310 rc6_mask
= GEN6_RC_CTL_RC6_ENABLE
;
5311 intel_print_rc6_info(dev_priv
, rc6_mask
);
5312 if (IS_BROADWELL(dev_priv
))
5313 I915_WRITE(GEN6_RC_CONTROL
, GEN6_RC_CTL_HW_ENABLE
|
5314 GEN7_RC_CTL_TO_MODE
|
5317 I915_WRITE(GEN6_RC_CONTROL
, GEN6_RC_CTL_HW_ENABLE
|
5318 GEN6_RC_CTL_EI_MODE(1) |
5321 /* 4 Program defaults and thresholds for RPS*/
5322 I915_WRITE(GEN6_RPNSWREQ
,
5323 HSW_FREQUENCY(dev_priv
->rps
.rp1_freq
));
5324 I915_WRITE(GEN6_RC_VIDEO_FREQ
,
5325 HSW_FREQUENCY(dev_priv
->rps
.rp1_freq
));
5326 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
5327 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 100000000 / 128); /* 1 second timeout */
5329 /* Docs recommend 900MHz, and 300 MHz respectively */
5330 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS
,
5331 dev_priv
->rps
.max_freq_softlimit
<< 24 |
5332 dev_priv
->rps
.min_freq_softlimit
<< 16);
5334 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 7600000 / 128); /* 76ms busyness per EI, 90% */
5335 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 31300000 / 128); /* 313ms busyness per EI, 70%*/
5336 I915_WRITE(GEN6_RP_UP_EI
, 66000); /* 84.48ms, XXX: random? */
5337 I915_WRITE(GEN6_RP_DOWN_EI
, 350000); /* 448ms, XXX: random? */
5339 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
5342 I915_WRITE(GEN6_RP_CONTROL
,
5343 GEN6_RP_MEDIA_TURBO
|
5344 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
5345 GEN6_RP_MEDIA_IS_GFX
|
5347 GEN6_RP_UP_BUSY_AVG
|
5348 GEN6_RP_DOWN_IDLE_AVG
);
5350 /* 6: Ring frequency + overclocking (our driver does this later */
5352 dev_priv
->rps
.power
= HIGH_POWER
; /* force a reset */
5353 gen6_set_rps(dev_priv
, dev_priv
->rps
.idle_freq
);
5355 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
5358 static void gen6_enable_rps(struct drm_i915_private
*dev_priv
)
5360 struct intel_engine_cs
*engine
;
5361 u32 rc6vids
, pcu_mbox
= 0, rc6_mask
= 0;
5366 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
5368 /* Here begins a magic sequence of register writes to enable
5369 * auto-downclocking.
5371 * Perhaps there might be some value in exposing these to
5374 I915_WRITE(GEN6_RC_STATE
, 0);
5376 /* Clear the DBG now so we don't confuse earlier errors */
5377 gtfifodbg
= I915_READ(GTFIFODBG
);
5379 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg
);
5380 I915_WRITE(GTFIFODBG
, gtfifodbg
);
5383 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
5385 /* Initialize rps frequencies */
5386 gen6_init_rps_frequencies(dev_priv
);
5388 /* disable the counters and set deterministic thresholds */
5389 I915_WRITE(GEN6_RC_CONTROL
, 0);
5391 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT
, 1000 << 16);
5392 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 40 << 16 | 30);
5393 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT
, 30);
5394 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000);
5395 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25);
5397 for_each_engine(engine
, dev_priv
)
5398 I915_WRITE(RING_MAX_IDLE(engine
->mmio_base
), 10);
5400 I915_WRITE(GEN6_RC_SLEEP
, 0);
5401 I915_WRITE(GEN6_RC1e_THRESHOLD
, 1000);
5402 if (IS_IVYBRIDGE(dev_priv
))
5403 I915_WRITE(GEN6_RC6_THRESHOLD
, 125000);
5405 I915_WRITE(GEN6_RC6_THRESHOLD
, 50000);
5406 I915_WRITE(GEN6_RC6p_THRESHOLD
, 150000);
5407 I915_WRITE(GEN6_RC6pp_THRESHOLD
, 64000); /* unused */
5409 /* Check if we are enabling RC6 */
5410 rc6_mode
= intel_enable_rc6();
5411 if (rc6_mode
& INTEL_RC6_ENABLE
)
5412 rc6_mask
|= GEN6_RC_CTL_RC6_ENABLE
;
5414 /* We don't use those on Haswell */
5415 if (!IS_HASWELL(dev_priv
)) {
5416 if (rc6_mode
& INTEL_RC6p_ENABLE
)
5417 rc6_mask
|= GEN6_RC_CTL_RC6p_ENABLE
;
5419 if (rc6_mode
& INTEL_RC6pp_ENABLE
)
5420 rc6_mask
|= GEN6_RC_CTL_RC6pp_ENABLE
;
5423 intel_print_rc6_info(dev_priv
, rc6_mask
);
5425 I915_WRITE(GEN6_RC_CONTROL
,
5427 GEN6_RC_CTL_EI_MODE(1) |
5428 GEN6_RC_CTL_HW_ENABLE
);
5430 /* Power down if completely idle for over 50ms */
5431 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 50000);
5432 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
5434 ret
= sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_MIN_FREQ_TABLE
, 0);
5436 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
5438 ret
= sandybridge_pcode_read(dev_priv
, GEN6_READ_OC_PARAMS
, &pcu_mbox
);
5439 if (!ret
&& (pcu_mbox
& (1<<31))) { /* OC supported */
5440 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
5441 (dev_priv
->rps
.max_freq_softlimit
& 0xff) * 50,
5442 (pcu_mbox
& 0xff) * 50);
5443 dev_priv
->rps
.max_freq
= pcu_mbox
& 0xff;
5446 dev_priv
->rps
.power
= HIGH_POWER
; /* force a reset */
5447 gen6_set_rps(dev_priv
, dev_priv
->rps
.idle_freq
);
5450 ret
= sandybridge_pcode_read(dev_priv
, GEN6_PCODE_READ_RC6VIDS
, &rc6vids
);
5451 if (IS_GEN6(dev_priv
) && ret
) {
5452 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
5453 } else if (IS_GEN6(dev_priv
) && (GEN6_DECODE_RC6_VID(rc6vids
& 0xff) < 450)) {
5454 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5455 GEN6_DECODE_RC6_VID(rc6vids
& 0xff), 450);
5456 rc6vids
&= 0xffff00;
5457 rc6vids
|= GEN6_ENCODE_RC6_VID(450);
5458 ret
= sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_RC6VIDS
, rc6vids
);
5460 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5463 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
5466 static void __gen6_update_ring_freq(struct drm_i915_private
*dev_priv
)
5469 unsigned int gpu_freq
;
5470 unsigned int max_ia_freq
, min_ring_freq
;
5471 unsigned int max_gpu_freq
, min_gpu_freq
;
5472 int scaling_factor
= 180;
5473 struct cpufreq_policy
*policy
;
5475 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
5477 policy
= cpufreq_cpu_get(0);
5479 max_ia_freq
= policy
->cpuinfo
.max_freq
;
5480 cpufreq_cpu_put(policy
);
5483 * Default to measured freq if none found, PCU will ensure we
5486 max_ia_freq
= tsc_khz
;
5489 /* Convert from kHz to MHz */
5490 max_ia_freq
/= 1000;
5492 min_ring_freq
= I915_READ(DCLK
) & 0xf;
5493 /* convert DDR frequency from units of 266.6MHz to bandwidth */
5494 min_ring_freq
= mult_frac(min_ring_freq
, 8, 3);
5496 if (IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
)) {
5497 /* Convert GT frequency to 50 HZ units */
5498 min_gpu_freq
= dev_priv
->rps
.min_freq
/ GEN9_FREQ_SCALER
;
5499 max_gpu_freq
= dev_priv
->rps
.max_freq
/ GEN9_FREQ_SCALER
;
5501 min_gpu_freq
= dev_priv
->rps
.min_freq
;
5502 max_gpu_freq
= dev_priv
->rps
.max_freq
;
5506 * For each potential GPU frequency, load a ring frequency we'd like
5507 * to use for memory access. We do this by specifying the IA frequency
5508 * the PCU should use as a reference to determine the ring frequency.
5510 for (gpu_freq
= max_gpu_freq
; gpu_freq
>= min_gpu_freq
; gpu_freq
--) {
5511 int diff
= max_gpu_freq
- gpu_freq
;
5512 unsigned int ia_freq
= 0, ring_freq
= 0;
5514 if (IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
)) {
5516 * ring_freq = 2 * GT. ring_freq is in 100MHz units
5517 * No floor required for ring frequency on SKL.
5519 ring_freq
= gpu_freq
;
5520 } else if (INTEL_INFO(dev_priv
)->gen
>= 8) {
5521 /* max(2 * GT, DDR). NB: GT is 50MHz units */
5522 ring_freq
= max(min_ring_freq
, gpu_freq
);
5523 } else if (IS_HASWELL(dev_priv
)) {
5524 ring_freq
= mult_frac(gpu_freq
, 5, 4);
5525 ring_freq
= max(min_ring_freq
, ring_freq
);
5526 /* leave ia_freq as the default, chosen by cpufreq */
5528 /* On older processors, there is no separate ring
5529 * clock domain, so in order to boost the bandwidth
5530 * of the ring, we need to upclock the CPU (ia_freq).
5532 * For GPU frequencies less than 750MHz,
5533 * just use the lowest ring freq.
5535 if (gpu_freq
< min_freq
)
5538 ia_freq
= max_ia_freq
- ((diff
* scaling_factor
) / 2);
5539 ia_freq
= DIV_ROUND_CLOSEST(ia_freq
, 100);
5542 sandybridge_pcode_write(dev_priv
,
5543 GEN6_PCODE_WRITE_MIN_FREQ_TABLE
,
5544 ia_freq
<< GEN6_PCODE_FREQ_IA_RATIO_SHIFT
|
5545 ring_freq
<< GEN6_PCODE_FREQ_RING_RATIO_SHIFT
|
5550 void gen6_update_ring_freq(struct drm_i915_private
*dev_priv
)
5552 if (!HAS_CORE_RING_FREQ(dev_priv
))
5555 mutex_lock(&dev_priv
->rps
.hw_lock
);
5556 __gen6_update_ring_freq(dev_priv
);
5557 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5560 static int cherryview_rps_max_freq(struct drm_i915_private
*dev_priv
)
5564 val
= vlv_punit_read(dev_priv
, FB_GFX_FMAX_AT_VMAX_FUSE
);
5566 switch (INTEL_INFO(dev_priv
)->eu_total
) {
5568 /* (2 * 4) config */
5569 rp0
= (val
>> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT
);
5572 /* (2 * 6) config */
5573 rp0
= (val
>> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT
);
5576 /* (2 * 8) config */
5578 /* Setting (2 * 8) Min RP0 for any other combination */
5579 rp0
= (val
>> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT
);
5583 rp0
= (rp0
& FB_GFX_FREQ_FUSE_MASK
);
5588 static int cherryview_rps_rpe_freq(struct drm_i915_private
*dev_priv
)
5592 val
= vlv_punit_read(dev_priv
, PUNIT_GPU_DUTYCYCLE_REG
);
5593 rpe
= (val
>> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT
) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK
;
5598 static int cherryview_rps_guar_freq(struct drm_i915_private
*dev_priv
)
5602 val
= vlv_punit_read(dev_priv
, FB_GFX_FMAX_AT_VMAX_FUSE
);
5603 rp1
= (val
& FB_GFX_FREQ_FUSE_MASK
);
5608 static int valleyview_rps_guar_freq(struct drm_i915_private
*dev_priv
)
5612 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FREQ_FUSE
);
5614 rp1
= (val
& FB_GFX_FGUARANTEED_FREQ_FUSE_MASK
) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT
;
5619 static int valleyview_rps_max_freq(struct drm_i915_private
*dev_priv
)
5623 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FREQ_FUSE
);
5625 rp0
= (val
& FB_GFX_MAX_FREQ_FUSE_MASK
) >> FB_GFX_MAX_FREQ_FUSE_SHIFT
;
5627 rp0
= min_t(u32
, rp0
, 0xea);
5632 static int valleyview_rps_rpe_freq(struct drm_i915_private
*dev_priv
)
5636 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FMAX_FUSE_LO
);
5637 rpe
= (val
& FB_FMAX_VMIN_FREQ_LO_MASK
) >> FB_FMAX_VMIN_FREQ_LO_SHIFT
;
5638 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FMAX_FUSE_HI
);
5639 rpe
|= (val
& FB_FMAX_VMIN_FREQ_HI_MASK
) << 5;
5644 static int valleyview_rps_min_freq(struct drm_i915_private
*dev_priv
)
5648 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_LFM
) & 0xff;
5650 * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
5651 * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
5652 * a BYT-M B0 the above register contains 0xbf. Moreover when setting
5653 * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
5654 * to make sure it matches what Punit accepts.
5656 return max_t(u32
, val
, 0xc0);
5659 /* Check that the pctx buffer wasn't move under us. */
5660 static void valleyview_check_pctx(struct drm_i915_private
*dev_priv
)
5662 unsigned long pctx_addr
= I915_READ(VLV_PCBR
) & ~4095;
5664 WARN_ON(pctx_addr
!= dev_priv
->mm
.stolen_base
+
5665 dev_priv
->vlv_pctx
->stolen
->start
);
5669 /* Check that the pcbr address is not empty. */
5670 static void cherryview_check_pctx(struct drm_i915_private
*dev_priv
)
5672 unsigned long pctx_addr
= I915_READ(VLV_PCBR
) & ~4095;
5674 WARN_ON((pctx_addr
>> VLV_PCBR_ADDR_SHIFT
) == 0);
5677 static void cherryview_setup_pctx(struct drm_i915_private
*dev_priv
)
5679 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
5680 unsigned long pctx_paddr
, paddr
;
5682 int pctx_size
= 32*1024;
5684 pcbr
= I915_READ(VLV_PCBR
);
5685 if ((pcbr
>> VLV_PCBR_ADDR_SHIFT
) == 0) {
5686 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5687 paddr
= (dev_priv
->mm
.stolen_base
+
5688 (ggtt
->stolen_size
- pctx_size
));
5690 pctx_paddr
= (paddr
& (~4095));
5691 I915_WRITE(VLV_PCBR
, pctx_paddr
);
5694 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR
));
5697 static void valleyview_setup_pctx(struct drm_i915_private
*dev_priv
)
5699 struct drm_i915_gem_object
*pctx
;
5700 unsigned long pctx_paddr
;
5702 int pctx_size
= 24*1024;
5704 mutex_lock(&dev_priv
->drm
.struct_mutex
);
5706 pcbr
= I915_READ(VLV_PCBR
);
5708 /* BIOS set it up already, grab the pre-alloc'd space */
5711 pcbr_offset
= (pcbr
& (~4095)) - dev_priv
->mm
.stolen_base
;
5712 pctx
= i915_gem_object_create_stolen_for_preallocated(&dev_priv
->drm
,
5714 I915_GTT_OFFSET_NONE
,
5719 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5722 * From the Gunit register HAS:
5723 * The Gfx driver is expected to program this register and ensure
5724 * proper allocation within Gfx stolen memory. For example, this
5725 * register should be programmed such than the PCBR range does not
5726 * overlap with other ranges, such as the frame buffer, protected
5727 * memory, or any other relevant ranges.
5729 pctx
= i915_gem_object_create_stolen(&dev_priv
->drm
, pctx_size
);
5731 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
5735 pctx_paddr
= dev_priv
->mm
.stolen_base
+ pctx
->stolen
->start
;
5736 I915_WRITE(VLV_PCBR
, pctx_paddr
);
5739 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR
));
5740 dev_priv
->vlv_pctx
= pctx
;
5741 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
5744 static void valleyview_cleanup_pctx(struct drm_i915_private
*dev_priv
)
5746 if (WARN_ON(!dev_priv
->vlv_pctx
))
5749 drm_gem_object_unreference_unlocked(&dev_priv
->vlv_pctx
->base
);
5750 dev_priv
->vlv_pctx
= NULL
;
5753 static void vlv_init_gpll_ref_freq(struct drm_i915_private
*dev_priv
)
5755 dev_priv
->rps
.gpll_ref_freq
=
5756 vlv_get_cck_clock(dev_priv
, "GPLL ref",
5757 CCK_GPLL_CLOCK_CONTROL
,
5758 dev_priv
->czclk_freq
);
5760 DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n",
5761 dev_priv
->rps
.gpll_ref_freq
);
5764 static void valleyview_init_gt_powersave(struct drm_i915_private
*dev_priv
)
5768 valleyview_setup_pctx(dev_priv
);
5770 vlv_init_gpll_ref_freq(dev_priv
);
5772 mutex_lock(&dev_priv
->rps
.hw_lock
);
5774 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
5775 switch ((val
>> 6) & 3) {
5778 dev_priv
->mem_freq
= 800;
5781 dev_priv
->mem_freq
= 1066;
5784 dev_priv
->mem_freq
= 1333;
5787 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv
->mem_freq
);
5789 dev_priv
->rps
.max_freq
= valleyview_rps_max_freq(dev_priv
);
5790 dev_priv
->rps
.rp0_freq
= dev_priv
->rps
.max_freq
;
5791 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5792 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
),
5793 dev_priv
->rps
.max_freq
);
5795 dev_priv
->rps
.efficient_freq
= valleyview_rps_rpe_freq(dev_priv
);
5796 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5797 intel_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
),
5798 dev_priv
->rps
.efficient_freq
);
5800 dev_priv
->rps
.rp1_freq
= valleyview_rps_guar_freq(dev_priv
);
5801 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
5802 intel_gpu_freq(dev_priv
, dev_priv
->rps
.rp1_freq
),
5803 dev_priv
->rps
.rp1_freq
);
5805 dev_priv
->rps
.min_freq
= valleyview_rps_min_freq(dev_priv
);
5806 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5807 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
),
5808 dev_priv
->rps
.min_freq
);
5810 dev_priv
->rps
.idle_freq
= dev_priv
->rps
.min_freq
;
5812 /* Preserve min/max settings in case of re-init */
5813 if (dev_priv
->rps
.max_freq_softlimit
== 0)
5814 dev_priv
->rps
.max_freq_softlimit
= dev_priv
->rps
.max_freq
;
5816 if (dev_priv
->rps
.min_freq_softlimit
== 0)
5817 dev_priv
->rps
.min_freq_softlimit
= dev_priv
->rps
.min_freq
;
5819 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5822 static void cherryview_init_gt_powersave(struct drm_i915_private
*dev_priv
)
5826 cherryview_setup_pctx(dev_priv
);
5828 vlv_init_gpll_ref_freq(dev_priv
);
5830 mutex_lock(&dev_priv
->rps
.hw_lock
);
5832 mutex_lock(&dev_priv
->sb_lock
);
5833 val
= vlv_cck_read(dev_priv
, CCK_FUSE_REG
);
5834 mutex_unlock(&dev_priv
->sb_lock
);
5836 switch ((val
>> 2) & 0x7) {
5838 dev_priv
->mem_freq
= 2000;
5841 dev_priv
->mem_freq
= 1600;
5844 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv
->mem_freq
);
5846 dev_priv
->rps
.max_freq
= cherryview_rps_max_freq(dev_priv
);
5847 dev_priv
->rps
.rp0_freq
= dev_priv
->rps
.max_freq
;
5848 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5849 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
),
5850 dev_priv
->rps
.max_freq
);
5852 dev_priv
->rps
.efficient_freq
= cherryview_rps_rpe_freq(dev_priv
);
5853 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5854 intel_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
),
5855 dev_priv
->rps
.efficient_freq
);
5857 dev_priv
->rps
.rp1_freq
= cherryview_rps_guar_freq(dev_priv
);
5858 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
5859 intel_gpu_freq(dev_priv
, dev_priv
->rps
.rp1_freq
),
5860 dev_priv
->rps
.rp1_freq
);
5862 /* PUnit validated range is only [RPe, RP0] */
5863 dev_priv
->rps
.min_freq
= dev_priv
->rps
.efficient_freq
;
5864 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5865 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
),
5866 dev_priv
->rps
.min_freq
);
5868 WARN_ONCE((dev_priv
->rps
.max_freq
|
5869 dev_priv
->rps
.efficient_freq
|
5870 dev_priv
->rps
.rp1_freq
|
5871 dev_priv
->rps
.min_freq
) & 1,
5872 "Odd GPU freq values\n");
5874 dev_priv
->rps
.idle_freq
= dev_priv
->rps
.min_freq
;
5876 /* Preserve min/max settings in case of re-init */
5877 if (dev_priv
->rps
.max_freq_softlimit
== 0)
5878 dev_priv
->rps
.max_freq_softlimit
= dev_priv
->rps
.max_freq
;
5880 if (dev_priv
->rps
.min_freq_softlimit
== 0)
5881 dev_priv
->rps
.min_freq_softlimit
= dev_priv
->rps
.min_freq
;
5883 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5886 static void valleyview_cleanup_gt_powersave(struct drm_i915_private
*dev_priv
)
5888 valleyview_cleanup_pctx(dev_priv
);
5891 static void cherryview_enable_rps(struct drm_i915_private
*dev_priv
)
5893 struct intel_engine_cs
*engine
;
5894 u32 gtfifodbg
, val
, rc6_mode
= 0, pcbr
;
5896 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
5898 gtfifodbg
= I915_READ(GTFIFODBG
) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV
|
5899 GT_FIFO_FREE_ENTRIES_CHV
);
5901 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5903 I915_WRITE(GTFIFODBG
, gtfifodbg
);
5906 cherryview_check_pctx(dev_priv
);
5908 /* 1a & 1b: Get forcewake during program sequence. Although the driver
5909 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5910 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
5912 /* Disable RC states. */
5913 I915_WRITE(GEN6_RC_CONTROL
, 0);
5915 /* 2a: Program RC6 thresholds.*/
5916 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 40 << 16);
5917 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000); /* 12500 * 1280ns */
5918 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25); /* 25 * 1280ns */
5920 for_each_engine(engine
, dev_priv
)
5921 I915_WRITE(RING_MAX_IDLE(engine
->mmio_base
), 10);
5922 I915_WRITE(GEN6_RC_SLEEP
, 0);
5924 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
5925 I915_WRITE(GEN6_RC6_THRESHOLD
, 0x186);
5927 /* allows RC6 residency counter to work */
5928 I915_WRITE(VLV_COUNTER_CONTROL
,
5929 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH
|
5930 VLV_MEDIA_RC6_COUNT_EN
|
5931 VLV_RENDER_RC6_COUNT_EN
));
5933 /* For now we assume BIOS is allocating and populating the PCBR */
5934 pcbr
= I915_READ(VLV_PCBR
);
5937 if ((intel_enable_rc6() & INTEL_RC6_ENABLE
) &&
5938 (pcbr
>> VLV_PCBR_ADDR_SHIFT
))
5939 rc6_mode
= GEN7_RC_CTL_TO_MODE
;
5941 I915_WRITE(GEN6_RC_CONTROL
, rc6_mode
);
5943 /* 4 Program defaults and thresholds for RPS*/
5944 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 1000000);
5945 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 59400);
5946 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 245000);
5947 I915_WRITE(GEN6_RP_UP_EI
, 66000);
5948 I915_WRITE(GEN6_RP_DOWN_EI
, 350000);
5950 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
5953 I915_WRITE(GEN6_RP_CONTROL
,
5954 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
5955 GEN6_RP_MEDIA_IS_GFX
|
5957 GEN6_RP_UP_BUSY_AVG
|
5958 GEN6_RP_DOWN_IDLE_AVG
);
5960 /* Setting Fixed Bias */
5961 val
= VLV_OVERRIDE_EN
|
5963 CHV_BIAS_CPU_50_SOC_50
;
5964 vlv_punit_write(dev_priv
, VLV_TURBO_SOC_OVERRIDE
, val
);
5966 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
5968 /* RPS code assumes GPLL is used */
5969 WARN_ONCE((val
& GPLLENABLE
) == 0, "GPLL not enabled\n");
5971 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val
& GPLLENABLE
));
5972 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val
);
5974 dev_priv
->rps
.cur_freq
= (val
>> 8) & 0xff;
5975 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5976 intel_gpu_freq(dev_priv
, dev_priv
->rps
.cur_freq
),
5977 dev_priv
->rps
.cur_freq
);
5979 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5980 intel_gpu_freq(dev_priv
, dev_priv
->rps
.idle_freq
),
5981 dev_priv
->rps
.idle_freq
);
5983 valleyview_set_rps(dev_priv
, dev_priv
->rps
.idle_freq
);
5985 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
5988 static void valleyview_enable_rps(struct drm_i915_private
*dev_priv
)
5990 struct intel_engine_cs
*engine
;
5991 u32 gtfifodbg
, val
, rc6_mode
= 0;
5993 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
5995 valleyview_check_pctx(dev_priv
);
5997 gtfifodbg
= I915_READ(GTFIFODBG
);
5999 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
6001 I915_WRITE(GTFIFODBG
, gtfifodbg
);
6004 /* If VLV, Forcewake all wells, else re-direct to regular path */
6005 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
6007 /* Disable RC states. */
6008 I915_WRITE(GEN6_RC_CONTROL
, 0);
6010 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 1000000);
6011 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 59400);
6012 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 245000);
6013 I915_WRITE(GEN6_RP_UP_EI
, 66000);
6014 I915_WRITE(GEN6_RP_DOWN_EI
, 350000);
6016 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
6018 I915_WRITE(GEN6_RP_CONTROL
,
6019 GEN6_RP_MEDIA_TURBO
|
6020 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
6021 GEN6_RP_MEDIA_IS_GFX
|
6023 GEN6_RP_UP_BUSY_AVG
|
6024 GEN6_RP_DOWN_IDLE_CONT
);
6026 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 0x00280000);
6027 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000);
6028 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25);
6030 for_each_engine(engine
, dev_priv
)
6031 I915_WRITE(RING_MAX_IDLE(engine
->mmio_base
), 10);
6033 I915_WRITE(GEN6_RC6_THRESHOLD
, 0x557);
6035 /* allows RC6 residency counter to work */
6036 I915_WRITE(VLV_COUNTER_CONTROL
,
6037 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN
|
6038 VLV_RENDER_RC0_COUNT_EN
|
6039 VLV_MEDIA_RC6_COUNT_EN
|
6040 VLV_RENDER_RC6_COUNT_EN
));
6042 if (intel_enable_rc6() & INTEL_RC6_ENABLE
)
6043 rc6_mode
= GEN7_RC_CTL_TO_MODE
| VLV_RC_CTL_CTX_RST_PARALLEL
;
6045 intel_print_rc6_info(dev_priv
, rc6_mode
);
6047 I915_WRITE(GEN6_RC_CONTROL
, rc6_mode
);
6049 /* Setting Fixed Bias */
6050 val
= VLV_OVERRIDE_EN
|
6052 VLV_BIAS_CPU_125_SOC_875
;
6053 vlv_punit_write(dev_priv
, VLV_TURBO_SOC_OVERRIDE
, val
);
6055 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
6057 /* RPS code assumes GPLL is used */
6058 WARN_ONCE((val
& GPLLENABLE
) == 0, "GPLL not enabled\n");
6060 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val
& GPLLENABLE
));
6061 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val
);
6063 dev_priv
->rps
.cur_freq
= (val
>> 8) & 0xff;
6064 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
6065 intel_gpu_freq(dev_priv
, dev_priv
->rps
.cur_freq
),
6066 dev_priv
->rps
.cur_freq
);
6068 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
6069 intel_gpu_freq(dev_priv
, dev_priv
->rps
.idle_freq
),
6070 dev_priv
->rps
.idle_freq
);
6072 valleyview_set_rps(dev_priv
, dev_priv
->rps
.idle_freq
);
6074 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
6077 static unsigned long intel_pxfreq(u32 vidfreq
)
6080 int div
= (vidfreq
& 0x3f0000) >> 16;
6081 int post
= (vidfreq
& 0x3000) >> 12;
6082 int pre
= (vidfreq
& 0x7);
6087 freq
= ((div
* 133333) / ((1<<post
) * pre
));
6092 static const struct cparams
{
6098 { 1, 1333, 301, 28664 },
6099 { 1, 1066, 294, 24460 },
6100 { 1, 800, 294, 25192 },
6101 { 0, 1333, 276, 27605 },
6102 { 0, 1066, 276, 27605 },
6103 { 0, 800, 231, 23784 },
6106 static unsigned long __i915_chipset_val(struct drm_i915_private
*dev_priv
)
6108 u64 total_count
, diff
, ret
;
6109 u32 count1
, count2
, count3
, m
= 0, c
= 0;
6110 unsigned long now
= jiffies_to_msecs(jiffies
), diff1
;
6113 assert_spin_locked(&mchdev_lock
);
6115 diff1
= now
- dev_priv
->ips
.last_time1
;
6117 /* Prevent division-by-zero if we are asking too fast.
6118 * Also, we don't get interesting results if we are polling
6119 * faster than once in 10ms, so just return the saved value
6123 return dev_priv
->ips
.chipset_power
;
6125 count1
= I915_READ(DMIEC
);
6126 count2
= I915_READ(DDREC
);
6127 count3
= I915_READ(CSIEC
);
6129 total_count
= count1
+ count2
+ count3
;
6131 /* FIXME: handle per-counter overflow */
6132 if (total_count
< dev_priv
->ips
.last_count1
) {
6133 diff
= ~0UL - dev_priv
->ips
.last_count1
;
6134 diff
+= total_count
;
6136 diff
= total_count
- dev_priv
->ips
.last_count1
;
6139 for (i
= 0; i
< ARRAY_SIZE(cparams
); i
++) {
6140 if (cparams
[i
].i
== dev_priv
->ips
.c_m
&&
6141 cparams
[i
].t
== dev_priv
->ips
.r_t
) {
6148 diff
= div_u64(diff
, diff1
);
6149 ret
= ((m
* diff
) + c
);
6150 ret
= div_u64(ret
, 10);
6152 dev_priv
->ips
.last_count1
= total_count
;
6153 dev_priv
->ips
.last_time1
= now
;
6155 dev_priv
->ips
.chipset_power
= ret
;
6160 unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
)
6164 if (INTEL_INFO(dev_priv
)->gen
!= 5)
6167 spin_lock_irq(&mchdev_lock
);
6169 val
= __i915_chipset_val(dev_priv
);
6171 spin_unlock_irq(&mchdev_lock
);
6176 unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
)
6178 unsigned long m
, x
, b
;
6181 tsfs
= I915_READ(TSFS
);
6183 m
= ((tsfs
& TSFS_SLOPE_MASK
) >> TSFS_SLOPE_SHIFT
);
6184 x
= I915_READ8(TR1
);
6186 b
= tsfs
& TSFS_INTR_MASK
;
6188 return ((m
* x
) / 127) - b
;
6191 static int _pxvid_to_vd(u8 pxvid
)
6196 if (pxvid
>= 8 && pxvid
< 31)
6199 return (pxvid
+ 2) * 125;
6202 static u32
pvid_to_extvid(struct drm_i915_private
*dev_priv
, u8 pxvid
)
6204 const int vd
= _pxvid_to_vd(pxvid
);
6205 const int vm
= vd
- 1125;
6207 if (INTEL_INFO(dev_priv
)->is_mobile
)
6208 return vm
> 0 ? vm
: 0;
6213 static void __i915_update_gfx_val(struct drm_i915_private
*dev_priv
)
6215 u64 now
, diff
, diffms
;
6218 assert_spin_locked(&mchdev_lock
);
6220 now
= ktime_get_raw_ns();
6221 diffms
= now
- dev_priv
->ips
.last_time2
;
6222 do_div(diffms
, NSEC_PER_MSEC
);
6224 /* Don't divide by 0 */
6228 count
= I915_READ(GFXEC
);
6230 if (count
< dev_priv
->ips
.last_count2
) {
6231 diff
= ~0UL - dev_priv
->ips
.last_count2
;
6234 diff
= count
- dev_priv
->ips
.last_count2
;
6237 dev_priv
->ips
.last_count2
= count
;
6238 dev_priv
->ips
.last_time2
= now
;
6240 /* More magic constants... */
6242 diff
= div_u64(diff
, diffms
* 10);
6243 dev_priv
->ips
.gfx_power
= diff
;
6246 void i915_update_gfx_val(struct drm_i915_private
*dev_priv
)
6248 if (INTEL_INFO(dev_priv
)->gen
!= 5)
6251 spin_lock_irq(&mchdev_lock
);
6253 __i915_update_gfx_val(dev_priv
);
6255 spin_unlock_irq(&mchdev_lock
);
6258 static unsigned long __i915_gfx_val(struct drm_i915_private
*dev_priv
)
6260 unsigned long t
, corr
, state1
, corr2
, state2
;
6263 assert_spin_locked(&mchdev_lock
);
6265 pxvid
= I915_READ(PXVFREQ(dev_priv
->rps
.cur_freq
));
6266 pxvid
= (pxvid
>> 24) & 0x7f;
6267 ext_v
= pvid_to_extvid(dev_priv
, pxvid
);
6271 t
= i915_mch_val(dev_priv
);
6273 /* Revel in the empirically derived constants */
6275 /* Correction factor in 1/100000 units */
6277 corr
= ((t
* 2349) + 135940);
6279 corr
= ((t
* 964) + 29317);
6281 corr
= ((t
* 301) + 1004);
6283 corr
= corr
* ((150142 * state1
) / 10000 - 78642);
6285 corr2
= (corr
* dev_priv
->ips
.corr
);
6287 state2
= (corr2
* state1
) / 10000;
6288 state2
/= 100; /* convert to mW */
6290 __i915_update_gfx_val(dev_priv
);
6292 return dev_priv
->ips
.gfx_power
+ state2
;
6295 unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
)
6299 if (INTEL_INFO(dev_priv
)->gen
!= 5)
6302 spin_lock_irq(&mchdev_lock
);
6304 val
= __i915_gfx_val(dev_priv
);
6306 spin_unlock_irq(&mchdev_lock
);
6312 * i915_read_mch_val - return value for IPS use
6314 * Calculate and return a value for the IPS driver to use when deciding whether
6315 * we have thermal and power headroom to increase CPU or GPU power budget.
6317 unsigned long i915_read_mch_val(void)
6319 struct drm_i915_private
*dev_priv
;
6320 unsigned long chipset_val
, graphics_val
, ret
= 0;
6322 spin_lock_irq(&mchdev_lock
);
6325 dev_priv
= i915_mch_dev
;
6327 chipset_val
= __i915_chipset_val(dev_priv
);
6328 graphics_val
= __i915_gfx_val(dev_priv
);
6330 ret
= chipset_val
+ graphics_val
;
6333 spin_unlock_irq(&mchdev_lock
);
6337 EXPORT_SYMBOL_GPL(i915_read_mch_val
);
6340 * i915_gpu_raise - raise GPU frequency limit
6342 * Raise the limit; IPS indicates we have thermal headroom.
6344 bool i915_gpu_raise(void)
6346 struct drm_i915_private
*dev_priv
;
6349 spin_lock_irq(&mchdev_lock
);
6350 if (!i915_mch_dev
) {
6354 dev_priv
= i915_mch_dev
;
6356 if (dev_priv
->ips
.max_delay
> dev_priv
->ips
.fmax
)
6357 dev_priv
->ips
.max_delay
--;
6360 spin_unlock_irq(&mchdev_lock
);
6364 EXPORT_SYMBOL_GPL(i915_gpu_raise
);
6367 * i915_gpu_lower - lower GPU frequency limit
6369 * IPS indicates we're close to a thermal limit, so throttle back the GPU
6370 * frequency maximum.
6372 bool i915_gpu_lower(void)
6374 struct drm_i915_private
*dev_priv
;
6377 spin_lock_irq(&mchdev_lock
);
6378 if (!i915_mch_dev
) {
6382 dev_priv
= i915_mch_dev
;
6384 if (dev_priv
->ips
.max_delay
< dev_priv
->ips
.min_delay
)
6385 dev_priv
->ips
.max_delay
++;
6388 spin_unlock_irq(&mchdev_lock
);
6392 EXPORT_SYMBOL_GPL(i915_gpu_lower
);
6395 * i915_gpu_busy - indicate GPU business to IPS
6397 * Tell the IPS driver whether or not the GPU is busy.
6399 bool i915_gpu_busy(void)
6401 struct drm_i915_private
*dev_priv
;
6402 struct intel_engine_cs
*engine
;
6405 spin_lock_irq(&mchdev_lock
);
6408 dev_priv
= i915_mch_dev
;
6410 for_each_engine(engine
, dev_priv
)
6411 ret
|= !list_empty(&engine
->request_list
);
6414 spin_unlock_irq(&mchdev_lock
);
6418 EXPORT_SYMBOL_GPL(i915_gpu_busy
);
6421 * i915_gpu_turbo_disable - disable graphics turbo
6423 * Disable graphics turbo by resetting the max frequency and setting the
6424 * current frequency to the default.
6426 bool i915_gpu_turbo_disable(void)
6428 struct drm_i915_private
*dev_priv
;
6431 spin_lock_irq(&mchdev_lock
);
6432 if (!i915_mch_dev
) {
6436 dev_priv
= i915_mch_dev
;
6438 dev_priv
->ips
.max_delay
= dev_priv
->ips
.fstart
;
6440 if (!ironlake_set_drps(dev_priv
, dev_priv
->ips
.fstart
))
6444 spin_unlock_irq(&mchdev_lock
);
6448 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable
);
6451 * Tells the intel_ips driver that the i915 driver is now loaded, if
6452 * IPS got loaded first.
6454 * This awkward dance is so that neither module has to depend on the
6455 * other in order for IPS to do the appropriate communication of
6456 * GPU turbo limits to i915.
6459 ips_ping_for_i915_load(void)
6463 link
= symbol_get(ips_link_to_i915_driver
);
6466 symbol_put(ips_link_to_i915_driver
);
6470 void intel_gpu_ips_init(struct drm_i915_private
*dev_priv
)
6472 /* We only register the i915 ips part with intel-ips once everything is
6473 * set up, to avoid intel-ips sneaking in and reading bogus values. */
6474 spin_lock_irq(&mchdev_lock
);
6475 i915_mch_dev
= dev_priv
;
6476 spin_unlock_irq(&mchdev_lock
);
6478 ips_ping_for_i915_load();
6481 void intel_gpu_ips_teardown(void)
6483 spin_lock_irq(&mchdev_lock
);
6484 i915_mch_dev
= NULL
;
6485 spin_unlock_irq(&mchdev_lock
);
6488 static void intel_init_emon(struct drm_i915_private
*dev_priv
)
6494 /* Disable to program */
6498 /* Program energy weights for various events */
6499 I915_WRITE(SDEW
, 0x15040d00);
6500 I915_WRITE(CSIEW0
, 0x007f0000);
6501 I915_WRITE(CSIEW1
, 0x1e220004);
6502 I915_WRITE(CSIEW2
, 0x04000004);
6504 for (i
= 0; i
< 5; i
++)
6505 I915_WRITE(PEW(i
), 0);
6506 for (i
= 0; i
< 3; i
++)
6507 I915_WRITE(DEW(i
), 0);
6509 /* Program P-state weights to account for frequency power adjustment */
6510 for (i
= 0; i
< 16; i
++) {
6511 u32 pxvidfreq
= I915_READ(PXVFREQ(i
));
6512 unsigned long freq
= intel_pxfreq(pxvidfreq
);
6513 unsigned long vid
= (pxvidfreq
& PXVFREQ_PX_MASK
) >>
6518 val
*= (freq
/ 1000);
6520 val
/= (127*127*900);
6522 DRM_ERROR("bad pxval: %ld\n", val
);
6525 /* Render standby states get 0 weight */
6529 for (i
= 0; i
< 4; i
++) {
6530 u32 val
= (pxw
[i
*4] << 24) | (pxw
[(i
*4)+1] << 16) |
6531 (pxw
[(i
*4)+2] << 8) | (pxw
[(i
*4)+3]);
6532 I915_WRITE(PXW(i
), val
);
6535 /* Adjust magic regs to magic values (more experimental results) */
6536 I915_WRITE(OGW0
, 0);
6537 I915_WRITE(OGW1
, 0);
6538 I915_WRITE(EG0
, 0x00007f00);
6539 I915_WRITE(EG1
, 0x0000000e);
6540 I915_WRITE(EG2
, 0x000e0000);
6541 I915_WRITE(EG3
, 0x68000300);
6542 I915_WRITE(EG4
, 0x42000000);
6543 I915_WRITE(EG5
, 0x00140031);
6547 for (i
= 0; i
< 8; i
++)
6548 I915_WRITE(PXWL(i
), 0);
6550 /* Enable PMON + select events */
6551 I915_WRITE(ECR
, 0x80000019);
6553 lcfuse
= I915_READ(LCFUSE02
);
6555 dev_priv
->ips
.corr
= (lcfuse
& LCFUSE_HIV_MASK
);
6558 void intel_init_gt_powersave(struct drm_i915_private
*dev_priv
)
6561 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6564 if (!i915
.enable_rc6
) {
6565 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6566 intel_runtime_pm_get(dev_priv
);
6569 if (IS_CHERRYVIEW(dev_priv
))
6570 cherryview_init_gt_powersave(dev_priv
);
6571 else if (IS_VALLEYVIEW(dev_priv
))
6572 valleyview_init_gt_powersave(dev_priv
);
6575 void intel_cleanup_gt_powersave(struct drm_i915_private
*dev_priv
)
6577 if (IS_CHERRYVIEW(dev_priv
))
6579 else if (IS_VALLEYVIEW(dev_priv
))
6580 valleyview_cleanup_gt_powersave(dev_priv
);
6582 if (!i915
.enable_rc6
)
6583 intel_runtime_pm_put(dev_priv
);
6586 static void gen6_suspend_rps(struct drm_i915_private
*dev_priv
)
6588 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
6590 gen6_disable_rps_interrupts(dev_priv
);
6594 * intel_suspend_gt_powersave - suspend PM work and helper threads
6595 * @dev_priv: i915 device
6597 * We don't want to disable RC6 or other features here, we just want
6598 * to make sure any work we've queued has finished and won't bother
6599 * us while we're suspended.
6601 void intel_suspend_gt_powersave(struct drm_i915_private
*dev_priv
)
6603 if (INTEL_GEN(dev_priv
) < 6)
6606 gen6_suspend_rps(dev_priv
);
6608 /* Force GPU to min freq during suspend */
6609 gen6_rps_idle(dev_priv
);
6612 void intel_disable_gt_powersave(struct drm_i915_private
*dev_priv
)
6614 if (IS_IRONLAKE_M(dev_priv
)) {
6615 ironlake_disable_drps(dev_priv
);
6616 } else if (INTEL_INFO(dev_priv
)->gen
>= 6) {
6617 intel_suspend_gt_powersave(dev_priv
);
6619 mutex_lock(&dev_priv
->rps
.hw_lock
);
6620 if (INTEL_INFO(dev_priv
)->gen
>= 9) {
6621 gen9_disable_rc6(dev_priv
);
6622 gen9_disable_rps(dev_priv
);
6623 } else if (IS_CHERRYVIEW(dev_priv
))
6624 cherryview_disable_rps(dev_priv
);
6625 else if (IS_VALLEYVIEW(dev_priv
))
6626 valleyview_disable_rps(dev_priv
);
6628 gen6_disable_rps(dev_priv
);
6630 dev_priv
->rps
.enabled
= false;
6631 mutex_unlock(&dev_priv
->rps
.hw_lock
);
6635 static void intel_gen6_powersave_work(struct work_struct
*work
)
6637 struct drm_i915_private
*dev_priv
=
6638 container_of(work
, struct drm_i915_private
,
6639 rps
.delayed_resume_work
.work
);
6641 mutex_lock(&dev_priv
->rps
.hw_lock
);
6643 gen6_reset_rps_interrupts(dev_priv
);
6645 if (IS_CHERRYVIEW(dev_priv
)) {
6646 cherryview_enable_rps(dev_priv
);
6647 } else if (IS_VALLEYVIEW(dev_priv
)) {
6648 valleyview_enable_rps(dev_priv
);
6649 } else if (INTEL_INFO(dev_priv
)->gen
>= 9) {
6650 gen9_enable_rc6(dev_priv
);
6651 gen9_enable_rps(dev_priv
);
6652 if (IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
))
6653 __gen6_update_ring_freq(dev_priv
);
6654 } else if (IS_BROADWELL(dev_priv
)) {
6655 gen8_enable_rps(dev_priv
);
6656 __gen6_update_ring_freq(dev_priv
);
6658 gen6_enable_rps(dev_priv
);
6659 __gen6_update_ring_freq(dev_priv
);
6662 WARN_ON(dev_priv
->rps
.max_freq
< dev_priv
->rps
.min_freq
);
6663 WARN_ON(dev_priv
->rps
.idle_freq
> dev_priv
->rps
.max_freq
);
6665 WARN_ON(dev_priv
->rps
.efficient_freq
< dev_priv
->rps
.min_freq
);
6666 WARN_ON(dev_priv
->rps
.efficient_freq
> dev_priv
->rps
.max_freq
);
6668 dev_priv
->rps
.enabled
= true;
6670 gen6_enable_rps_interrupts(dev_priv
);
6672 mutex_unlock(&dev_priv
->rps
.hw_lock
);
6674 intel_runtime_pm_put(dev_priv
);
6677 void intel_enable_gt_powersave(struct drm_i915_private
*dev_priv
)
6679 /* Powersaving is controlled by the host when inside a VM */
6680 if (intel_vgpu_active(dev_priv
))
6683 if (IS_IRONLAKE_M(dev_priv
)) {
6684 ironlake_enable_drps(dev_priv
);
6685 mutex_lock(&dev_priv
->drm
.struct_mutex
);
6686 intel_init_emon(dev_priv
);
6687 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
6688 } else if (INTEL_INFO(dev_priv
)->gen
>= 6) {
6690 * PCU communication is slow and this doesn't need to be
6691 * done at any specific time, so do this out of our fast path
6692 * to make resume and init faster.
6694 * We depend on the HW RC6 power context save/restore
6695 * mechanism when entering D3 through runtime PM suspend. So
6696 * disable RPM until RPS/RC6 is properly setup. We can only
6697 * get here via the driver load/system resume/runtime resume
6698 * paths, so the _noresume version is enough (and in case of
6699 * runtime resume it's necessary).
6701 if (schedule_delayed_work(&dev_priv
->rps
.delayed_resume_work
,
6702 round_jiffies_up_relative(HZ
)))
6703 intel_runtime_pm_get_noresume(dev_priv
);
6707 void intel_reset_gt_powersave(struct drm_i915_private
*dev_priv
)
6709 if (INTEL_INFO(dev_priv
)->gen
< 6)
6712 gen6_suspend_rps(dev_priv
);
6713 dev_priv
->rps
.enabled
= false;
6716 static void ibx_init_clock_gating(struct drm_device
*dev
)
6718 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6721 * On Ibex Peak and Cougar Point, we need to disable clock
6722 * gating for the panel power sequencer or it will fail to
6723 * start up when no ports are active.
6725 I915_WRITE(SOUTH_DSPCLK_GATE_D
, PCH_DPLSUNIT_CLOCK_GATE_DISABLE
);
6728 static void g4x_disable_trickle_feed(struct drm_device
*dev
)
6730 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6733 for_each_pipe(dev_priv
, pipe
) {
6734 I915_WRITE(DSPCNTR(pipe
),
6735 I915_READ(DSPCNTR(pipe
)) |
6736 DISPPLANE_TRICKLE_FEED_DISABLE
);
6738 I915_WRITE(DSPSURF(pipe
), I915_READ(DSPSURF(pipe
)));
6739 POSTING_READ(DSPSURF(pipe
));
6743 static void ilk_init_lp_watermarks(struct drm_device
*dev
)
6745 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6747 I915_WRITE(WM3_LP_ILK
, I915_READ(WM3_LP_ILK
) & ~WM1_LP_SR_EN
);
6748 I915_WRITE(WM2_LP_ILK
, I915_READ(WM2_LP_ILK
) & ~WM1_LP_SR_EN
);
6749 I915_WRITE(WM1_LP_ILK
, I915_READ(WM1_LP_ILK
) & ~WM1_LP_SR_EN
);
6752 * Don't touch WM1S_LP_EN here.
6753 * Doing so could cause underruns.
6757 static void ironlake_init_clock_gating(struct drm_device
*dev
)
6759 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6760 uint32_t dspclk_gate
= ILK_VRHUNIT_CLOCK_GATE_DISABLE
;
6764 * WaFbcDisableDpfcClockGating:ilk
6766 dspclk_gate
|= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE
|
6767 ILK_DPFCUNIT_CLOCK_GATE_DISABLE
|
6768 ILK_DPFDUNIT_CLOCK_GATE_ENABLE
;
6770 I915_WRITE(PCH_3DCGDIS0
,
6771 MARIUNIT_CLOCK_GATE_DISABLE
|
6772 SVSMUNIT_CLOCK_GATE_DISABLE
);
6773 I915_WRITE(PCH_3DCGDIS1
,
6774 VFMUNIT_CLOCK_GATE_DISABLE
);
6777 * According to the spec the following bits should be set in
6778 * order to enable memory self-refresh
6779 * The bit 22/21 of 0x42004
6780 * The bit 5 of 0x42020
6781 * The bit 15 of 0x45000
6783 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
6784 (I915_READ(ILK_DISPLAY_CHICKEN2
) |
6785 ILK_DPARB_GATE
| ILK_VSDPFD_FULL
));
6786 dspclk_gate
|= ILK_DPARBUNIT_CLOCK_GATE_ENABLE
;
6787 I915_WRITE(DISP_ARB_CTL
,
6788 (I915_READ(DISP_ARB_CTL
) |
6791 ilk_init_lp_watermarks(dev
);
6794 * Based on the document from hardware guys the following bits
6795 * should be set unconditionally in order to enable FBC.
6796 * The bit 22 of 0x42000
6797 * The bit 22 of 0x42004
6798 * The bit 7,8,9 of 0x42020.
6800 if (IS_IRONLAKE_M(dev
)) {
6801 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6802 I915_WRITE(ILK_DISPLAY_CHICKEN1
,
6803 I915_READ(ILK_DISPLAY_CHICKEN1
) |
6805 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
6806 I915_READ(ILK_DISPLAY_CHICKEN2
) |
6810 I915_WRITE(ILK_DSPCLK_GATE_D
, dspclk_gate
);
6812 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
6813 I915_READ(ILK_DISPLAY_CHICKEN2
) |
6814 ILK_ELPIN_409_SELECT
);
6815 I915_WRITE(_3D_CHICKEN2
,
6816 _3D_CHICKEN2_WM_READ_PIPELINED
<< 16 |
6817 _3D_CHICKEN2_WM_READ_PIPELINED
);
6819 /* WaDisableRenderCachePipelinedFlush:ilk */
6820 I915_WRITE(CACHE_MODE_0
,
6821 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE
));
6823 /* WaDisable_RenderCache_OperationalFlush:ilk */
6824 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
6826 g4x_disable_trickle_feed(dev
);
6828 ibx_init_clock_gating(dev
);
6831 static void cpt_init_clock_gating(struct drm_device
*dev
)
6833 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6838 * On Ibex Peak and Cougar Point, we need to disable clock
6839 * gating for the panel power sequencer or it will fail to
6840 * start up when no ports are active.
6842 I915_WRITE(SOUTH_DSPCLK_GATE_D
, PCH_DPLSUNIT_CLOCK_GATE_DISABLE
|
6843 PCH_DPLUNIT_CLOCK_GATE_DISABLE
|
6844 PCH_CPUNIT_CLOCK_GATE_DISABLE
);
6845 I915_WRITE(SOUTH_CHICKEN2
, I915_READ(SOUTH_CHICKEN2
) |
6846 DPLS_EDP_PPS_FIX_DIS
);
6847 /* The below fixes the weird display corruption, a few pixels shifted
6848 * downward, on (only) LVDS of some HP laptops with IVY.
6850 for_each_pipe(dev_priv
, pipe
) {
6851 val
= I915_READ(TRANS_CHICKEN2(pipe
));
6852 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
6853 val
&= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED
;
6854 if (dev_priv
->vbt
.fdi_rx_polarity_inverted
)
6855 val
|= TRANS_CHICKEN2_FDI_POLARITY_REVERSED
;
6856 val
&= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK
;
6857 val
&= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER
;
6858 val
&= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH
;
6859 I915_WRITE(TRANS_CHICKEN2(pipe
), val
);
6861 /* WADP0ClockGatingDisable */
6862 for_each_pipe(dev_priv
, pipe
) {
6863 I915_WRITE(TRANS_CHICKEN1(pipe
),
6864 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE
);
6868 static void gen6_check_mch_setup(struct drm_device
*dev
)
6870 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6873 tmp
= I915_READ(MCH_SSKPD
);
6874 if ((tmp
& MCH_SSKPD_WM0_MASK
) != MCH_SSKPD_WM0_VAL
)
6875 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6879 static void gen6_init_clock_gating(struct drm_device
*dev
)
6881 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6882 uint32_t dspclk_gate
= ILK_VRHUNIT_CLOCK_GATE_DISABLE
;
6884 I915_WRITE(ILK_DSPCLK_GATE_D
, dspclk_gate
);
6886 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
6887 I915_READ(ILK_DISPLAY_CHICKEN2
) |
6888 ILK_ELPIN_409_SELECT
);
6890 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
6891 I915_WRITE(_3D_CHICKEN
,
6892 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB
));
6894 /* WaDisable_RenderCache_OperationalFlush:snb */
6895 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
6898 * BSpec recoomends 8x4 when MSAA is used,
6899 * however in practice 16x4 seems fastest.
6901 * Note that PS/WM thread counts depend on the WIZ hashing
6902 * disable bit, which we don't touch here, but it's good
6903 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6905 I915_WRITE(GEN6_GT_MODE
,
6906 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK
, GEN6_WIZ_HASHING_16x4
));
6908 ilk_init_lp_watermarks(dev
);
6910 I915_WRITE(CACHE_MODE_0
,
6911 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB
));
6913 I915_WRITE(GEN6_UCGCTL1
,
6914 I915_READ(GEN6_UCGCTL1
) |
6915 GEN6_BLBUNIT_CLOCK_GATE_DISABLE
|
6916 GEN6_CSUNIT_CLOCK_GATE_DISABLE
);
6918 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
6919 * gating disable must be set. Failure to set it results in
6920 * flickering pixels due to Z write ordering failures after
6921 * some amount of runtime in the Mesa "fire" demo, and Unigine
6922 * Sanctuary and Tropics, and apparently anything else with
6923 * alpha test or pixel discard.
6925 * According to the spec, bit 11 (RCCUNIT) must also be set,
6926 * but we didn't debug actual testcases to find it out.
6928 * WaDisableRCCUnitClockGating:snb
6929 * WaDisableRCPBUnitClockGating:snb
6931 I915_WRITE(GEN6_UCGCTL2
,
6932 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE
|
6933 GEN6_RCCUNIT_CLOCK_GATE_DISABLE
);
6935 /* WaStripsFansDisableFastClipPerformanceFix:snb */
6936 I915_WRITE(_3D_CHICKEN3
,
6937 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL
));
6941 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
6942 * 3DSTATE_SF number of SF output attributes is more than 16."
6944 I915_WRITE(_3D_CHICKEN3
,
6945 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH
));
6948 * According to the spec the following bits should be
6949 * set in order to enable memory self-refresh and fbc:
6950 * The bit21 and bit22 of 0x42000
6951 * The bit21 and bit22 of 0x42004
6952 * The bit5 and bit7 of 0x42020
6953 * The bit14 of 0x70180
6954 * The bit14 of 0x71180
6956 * WaFbcAsynchFlipDisableFbcQueue:snb
6958 I915_WRITE(ILK_DISPLAY_CHICKEN1
,
6959 I915_READ(ILK_DISPLAY_CHICKEN1
) |
6960 ILK_FBCQ_DIS
| ILK_PABSTRETCH_DIS
);
6961 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
6962 I915_READ(ILK_DISPLAY_CHICKEN2
) |
6963 ILK_DPARB_GATE
| ILK_VSDPFD_FULL
);
6964 I915_WRITE(ILK_DSPCLK_GATE_D
,
6965 I915_READ(ILK_DSPCLK_GATE_D
) |
6966 ILK_DPARBUNIT_CLOCK_GATE_ENABLE
|
6967 ILK_DPFDUNIT_CLOCK_GATE_ENABLE
);
6969 g4x_disable_trickle_feed(dev
);
6971 cpt_init_clock_gating(dev
);
6973 gen6_check_mch_setup(dev
);
6976 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private
*dev_priv
)
6978 uint32_t reg
= I915_READ(GEN7_FF_THREAD_MODE
);
6981 * WaVSThreadDispatchOverride:ivb,vlv
6983 * This actually overrides the dispatch
6984 * mode for all thread types.
6986 reg
&= ~GEN7_FF_SCHED_MASK
;
6987 reg
|= GEN7_FF_TS_SCHED_HW
;
6988 reg
|= GEN7_FF_VS_SCHED_HW
;
6989 reg
|= GEN7_FF_DS_SCHED_HW
;
6991 I915_WRITE(GEN7_FF_THREAD_MODE
, reg
);
6994 static void lpt_init_clock_gating(struct drm_device
*dev
)
6996 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6999 * TODO: this bit should only be enabled when really needed, then
7000 * disabled when not needed anymore in order to save power.
7002 if (HAS_PCH_LPT_LP(dev
))
7003 I915_WRITE(SOUTH_DSPCLK_GATE_D
,
7004 I915_READ(SOUTH_DSPCLK_GATE_D
) |
7005 PCH_LP_PARTITION_LEVEL_DISABLE
);
7007 /* WADPOClockGatingDisable:hsw */
7008 I915_WRITE(TRANS_CHICKEN1(PIPE_A
),
7009 I915_READ(TRANS_CHICKEN1(PIPE_A
)) |
7010 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE
);
7013 static void lpt_suspend_hw(struct drm_device
*dev
)
7015 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7017 if (HAS_PCH_LPT_LP(dev
)) {
7018 uint32_t val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
7020 val
&= ~PCH_LP_PARTITION_LEVEL_DISABLE
;
7021 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
7025 static void gen8_set_l3sqc_credits(struct drm_i915_private
*dev_priv
,
7026 int general_prio_credits
,
7027 int high_prio_credits
)
7031 /* WaTempDisableDOPClkGating:bdw */
7032 misccpctl
= I915_READ(GEN7_MISCCPCTL
);
7033 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
& ~GEN7_DOP_CLOCK_GATE_ENABLE
);
7035 I915_WRITE(GEN8_L3SQCREG1
,
7036 L3_GENERAL_PRIO_CREDITS(general_prio_credits
) |
7037 L3_HIGH_PRIO_CREDITS(high_prio_credits
));
7040 * Wait at least 100 clocks before re-enabling clock gating.
7041 * See the definition of L3SQCREG1 in BSpec.
7043 POSTING_READ(GEN8_L3SQCREG1
);
7045 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
);
7048 static void kabylake_init_clock_gating(struct drm_device
*dev
)
7050 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7052 gen9_init_clock_gating(dev
);
7054 /* WaDisableSDEUnitClockGating:kbl */
7055 if (IS_KBL_REVID(dev_priv
, 0, KBL_REVID_B0
))
7056 I915_WRITE(GEN8_UCGCTL6
, I915_READ(GEN8_UCGCTL6
) |
7057 GEN8_SDEUNIT_CLOCK_GATE_DISABLE
);
7059 /* WaDisableGamClockGating:kbl */
7060 if (IS_KBL_REVID(dev_priv
, 0, KBL_REVID_B0
))
7061 I915_WRITE(GEN6_UCGCTL1
, I915_READ(GEN6_UCGCTL1
) |
7062 GEN6_GAMUNIT_CLOCK_GATE_DISABLE
);
7064 /* WaFbcNukeOnHostModify:kbl */
7065 I915_WRITE(ILK_DPFC_CHICKEN
, I915_READ(ILK_DPFC_CHICKEN
) |
7066 ILK_DPFC_NUKE_ON_ANY_MODIFICATION
);
7069 static void skylake_init_clock_gating(struct drm_device
*dev
)
7071 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7073 gen9_init_clock_gating(dev
);
7075 /* WAC6entrylatency:skl */
7076 I915_WRITE(FBC_LLC_READ_CTRL
, I915_READ(FBC_LLC_READ_CTRL
) |
7077 FBC_LLC_FULLY_OPEN
);
7079 /* WaFbcNukeOnHostModify:skl */
7080 I915_WRITE(ILK_DPFC_CHICKEN
, I915_READ(ILK_DPFC_CHICKEN
) |
7081 ILK_DPFC_NUKE_ON_ANY_MODIFICATION
);
7084 static void broadwell_init_clock_gating(struct drm_device
*dev
)
7086 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7089 ilk_init_lp_watermarks(dev
);
7091 /* WaSwitchSolVfFArbitrationPriority:bdw */
7092 I915_WRITE(GAM_ECOCHK
, I915_READ(GAM_ECOCHK
) | HSW_ECOCHK_ARB_PRIO_SOL
);
7094 /* WaPsrDPAMaskVBlankInSRD:bdw */
7095 I915_WRITE(CHICKEN_PAR1_1
,
7096 I915_READ(CHICKEN_PAR1_1
) | DPA_MASK_VBLANK_SRD
);
7098 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
7099 for_each_pipe(dev_priv
, pipe
) {
7100 I915_WRITE(CHICKEN_PIPESL_1(pipe
),
7101 I915_READ(CHICKEN_PIPESL_1(pipe
)) |
7102 BDW_DPRS_MASK_VBLANK_SRD
);
7105 /* WaVSRefCountFullforceMissDisable:bdw */
7106 /* WaDSRefCountFullforceMissDisable:bdw */
7107 I915_WRITE(GEN7_FF_THREAD_MODE
,
7108 I915_READ(GEN7_FF_THREAD_MODE
) &
7109 ~(GEN8_FF_DS_REF_CNT_FFME
| GEN7_FF_VS_REF_CNT_FFME
));
7111 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL
,
7112 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE
));
7114 /* WaDisableSDEUnitClockGating:bdw */
7115 I915_WRITE(GEN8_UCGCTL6
, I915_READ(GEN8_UCGCTL6
) |
7116 GEN8_SDEUNIT_CLOCK_GATE_DISABLE
);
7118 /* WaProgramL3SqcReg1Default:bdw */
7119 gen8_set_l3sqc_credits(dev_priv
, 30, 2);
7122 * WaGttCachingOffByDefault:bdw
7123 * GTT cache may not work with big pages, so if those
7124 * are ever enabled GTT cache may need to be disabled.
7126 I915_WRITE(HSW_GTT_CACHE_EN
, GTT_CACHE_EN_ALL
);
7128 /* WaKVMNotificationOnConfigChange:bdw */
7129 I915_WRITE(CHICKEN_PAR2_1
, I915_READ(CHICKEN_PAR2_1
)
7130 | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT
);
7132 lpt_init_clock_gating(dev
);
7135 static void haswell_init_clock_gating(struct drm_device
*dev
)
7137 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7139 ilk_init_lp_watermarks(dev
);
7141 /* L3 caching of data atomics doesn't work -- disable it. */
7142 I915_WRITE(HSW_SCRATCH1
, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE
);
7143 I915_WRITE(HSW_ROW_CHICKEN3
,
7144 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE
));
7146 /* This is required by WaCatErrorRejectionIssue:hsw */
7147 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
7148 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
7149 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
7151 /* WaVSRefCountFullforceMissDisable:hsw */
7152 I915_WRITE(GEN7_FF_THREAD_MODE
,
7153 I915_READ(GEN7_FF_THREAD_MODE
) & ~GEN7_FF_VS_REF_CNT_FFME
);
7155 /* WaDisable_RenderCache_OperationalFlush:hsw */
7156 I915_WRITE(CACHE_MODE_0_GEN7
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
7158 /* enable HiZ Raw Stall Optimization */
7159 I915_WRITE(CACHE_MODE_0_GEN7
,
7160 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE
));
7162 /* WaDisable4x2SubspanOptimization:hsw */
7163 I915_WRITE(CACHE_MODE_1
,
7164 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
));
7167 * BSpec recommends 8x4 when MSAA is used,
7168 * however in practice 16x4 seems fastest.
7170 * Note that PS/WM thread counts depend on the WIZ hashing
7171 * disable bit, which we don't touch here, but it's good
7172 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7174 I915_WRITE(GEN7_GT_MODE
,
7175 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK
, GEN6_WIZ_HASHING_16x4
));
7177 /* WaSampleCChickenBitEnable:hsw */
7178 I915_WRITE(HALF_SLICE_CHICKEN3
,
7179 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE
));
7181 /* WaSwitchSolVfFArbitrationPriority:hsw */
7182 I915_WRITE(GAM_ECOCHK
, I915_READ(GAM_ECOCHK
) | HSW_ECOCHK_ARB_PRIO_SOL
);
7184 /* WaRsPkgCStateDisplayPMReq:hsw */
7185 I915_WRITE(CHICKEN_PAR1_1
,
7186 I915_READ(CHICKEN_PAR1_1
) | FORCE_ARB_IDLE_PLANES
);
7188 lpt_init_clock_gating(dev
);
7191 static void ivybridge_init_clock_gating(struct drm_device
*dev
)
7193 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7196 ilk_init_lp_watermarks(dev
);
7198 I915_WRITE(ILK_DSPCLK_GATE_D
, ILK_VRHUNIT_CLOCK_GATE_DISABLE
);
7200 /* WaDisableEarlyCull:ivb */
7201 I915_WRITE(_3D_CHICKEN3
,
7202 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL
));
7204 /* WaDisableBackToBackFlipFix:ivb */
7205 I915_WRITE(IVB_CHICKEN3
,
7206 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE
|
7207 CHICKEN3_DGMG_DONE_FIX_DISABLE
);
7209 /* WaDisablePSDDualDispatchEnable:ivb */
7210 if (IS_IVB_GT1(dev
))
7211 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1
,
7212 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE
));
7214 /* WaDisable_RenderCache_OperationalFlush:ivb */
7215 I915_WRITE(CACHE_MODE_0_GEN7
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
7217 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
7218 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1
,
7219 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC
);
7221 /* WaApplyL3ControlAndL3ChickenMode:ivb */
7222 I915_WRITE(GEN7_L3CNTLREG1
,
7223 GEN7_WA_FOR_GEN7_L3_CONTROL
);
7224 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER
,
7225 GEN7_WA_L3_CHICKEN_MODE
);
7226 if (IS_IVB_GT1(dev
))
7227 I915_WRITE(GEN7_ROW_CHICKEN2
,
7228 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
7230 /* must write both registers */
7231 I915_WRITE(GEN7_ROW_CHICKEN2
,
7232 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
7233 I915_WRITE(GEN7_ROW_CHICKEN2_GT2
,
7234 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
7237 /* WaForceL3Serialization:ivb */
7238 I915_WRITE(GEN7_L3SQCREG4
, I915_READ(GEN7_L3SQCREG4
) &
7239 ~L3SQ_URB_READ_CAM_MATCH_DISABLE
);
7242 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
7243 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
7245 I915_WRITE(GEN6_UCGCTL2
,
7246 GEN6_RCZUNIT_CLOCK_GATE_DISABLE
);
7248 /* This is required by WaCatErrorRejectionIssue:ivb */
7249 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
7250 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
7251 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
7253 g4x_disable_trickle_feed(dev
);
7255 gen7_setup_fixed_func_scheduler(dev_priv
);
7257 if (0) { /* causes HiZ corruption on ivb:gt1 */
7258 /* enable HiZ Raw Stall Optimization */
7259 I915_WRITE(CACHE_MODE_0_GEN7
,
7260 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE
));
7263 /* WaDisable4x2SubspanOptimization:ivb */
7264 I915_WRITE(CACHE_MODE_1
,
7265 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
));
7268 * BSpec recommends 8x4 when MSAA is used,
7269 * however in practice 16x4 seems fastest.
7271 * Note that PS/WM thread counts depend on the WIZ hashing
7272 * disable bit, which we don't touch here, but it's good
7273 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7275 I915_WRITE(GEN7_GT_MODE
,
7276 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK
, GEN6_WIZ_HASHING_16x4
));
7278 snpcr
= I915_READ(GEN6_MBCUNIT_SNPCR
);
7279 snpcr
&= ~GEN6_MBC_SNPCR_MASK
;
7280 snpcr
|= GEN6_MBC_SNPCR_MED
;
7281 I915_WRITE(GEN6_MBCUNIT_SNPCR
, snpcr
);
7283 if (!HAS_PCH_NOP(dev
))
7284 cpt_init_clock_gating(dev
);
7286 gen6_check_mch_setup(dev
);
7289 static void valleyview_init_clock_gating(struct drm_device
*dev
)
7291 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7293 /* WaDisableEarlyCull:vlv */
7294 I915_WRITE(_3D_CHICKEN3
,
7295 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL
));
7297 /* WaDisableBackToBackFlipFix:vlv */
7298 I915_WRITE(IVB_CHICKEN3
,
7299 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE
|
7300 CHICKEN3_DGMG_DONE_FIX_DISABLE
);
7302 /* WaPsdDispatchEnable:vlv */
7303 /* WaDisablePSDDualDispatchEnable:vlv */
7304 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1
,
7305 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP
|
7306 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE
));
7308 /* WaDisable_RenderCache_OperationalFlush:vlv */
7309 I915_WRITE(CACHE_MODE_0_GEN7
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
7311 /* WaForceL3Serialization:vlv */
7312 I915_WRITE(GEN7_L3SQCREG4
, I915_READ(GEN7_L3SQCREG4
) &
7313 ~L3SQ_URB_READ_CAM_MATCH_DISABLE
);
7315 /* WaDisableDopClockGating:vlv */
7316 I915_WRITE(GEN7_ROW_CHICKEN2
,
7317 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
7319 /* This is required by WaCatErrorRejectionIssue:vlv */
7320 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
7321 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
7322 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
7324 gen7_setup_fixed_func_scheduler(dev_priv
);
7327 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
7328 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
7330 I915_WRITE(GEN6_UCGCTL2
,
7331 GEN6_RCZUNIT_CLOCK_GATE_DISABLE
);
7333 /* WaDisableL3Bank2xClockGate:vlv
7334 * Disabling L3 clock gating- MMIO 940c[25] = 1
7335 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
7336 I915_WRITE(GEN7_UCGCTL4
,
7337 I915_READ(GEN7_UCGCTL4
) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE
);
7340 * BSpec says this must be set, even though
7341 * WaDisable4x2SubspanOptimization isn't listed for VLV.
7343 I915_WRITE(CACHE_MODE_1
,
7344 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
));
7347 * BSpec recommends 8x4 when MSAA is used,
7348 * however in practice 16x4 seems fastest.
7350 * Note that PS/WM thread counts depend on the WIZ hashing
7351 * disable bit, which we don't touch here, but it's good
7352 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7354 I915_WRITE(GEN7_GT_MODE
,
7355 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK
, GEN6_WIZ_HASHING_16x4
));
7358 * WaIncreaseL3CreditsForVLVB0:vlv
7359 * This is the hardware default actually.
7361 I915_WRITE(GEN7_L3SQCREG1
, VLV_B0_WA_L3SQCREG1_VALUE
);
7364 * WaDisableVLVClockGating_VBIIssue:vlv
7365 * Disable clock gating on th GCFG unit to prevent a delay
7366 * in the reporting of vblank events.
7368 I915_WRITE(VLV_GUNIT_CLOCK_GATE
, GCFG_DIS
);
7371 static void cherryview_init_clock_gating(struct drm_device
*dev
)
7373 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7375 /* WaVSRefCountFullforceMissDisable:chv */
7376 /* WaDSRefCountFullforceMissDisable:chv */
7377 I915_WRITE(GEN7_FF_THREAD_MODE
,
7378 I915_READ(GEN7_FF_THREAD_MODE
) &
7379 ~(GEN8_FF_DS_REF_CNT_FFME
| GEN7_FF_VS_REF_CNT_FFME
));
7381 /* WaDisableSemaphoreAndSyncFlipWait:chv */
7382 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL
,
7383 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE
));
7385 /* WaDisableCSUnitClockGating:chv */
7386 I915_WRITE(GEN6_UCGCTL1
, I915_READ(GEN6_UCGCTL1
) |
7387 GEN6_CSUNIT_CLOCK_GATE_DISABLE
);
7389 /* WaDisableSDEUnitClockGating:chv */
7390 I915_WRITE(GEN8_UCGCTL6
, I915_READ(GEN8_UCGCTL6
) |
7391 GEN8_SDEUNIT_CLOCK_GATE_DISABLE
);
7394 * WaProgramL3SqcReg1Default:chv
7395 * See gfxspecs/Related Documents/Performance Guide/
7396 * LSQC Setting Recommendations.
7398 gen8_set_l3sqc_credits(dev_priv
, 38, 2);
7401 * GTT cache may not work with big pages, so if those
7402 * are ever enabled GTT cache may need to be disabled.
7404 I915_WRITE(HSW_GTT_CACHE_EN
, GTT_CACHE_EN_ALL
);
7407 static void g4x_init_clock_gating(struct drm_device
*dev
)
7409 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7410 uint32_t dspclk_gate
;
7412 I915_WRITE(RENCLK_GATE_D1
, 0);
7413 I915_WRITE(RENCLK_GATE_D2
, VF_UNIT_CLOCK_GATE_DISABLE
|
7414 GS_UNIT_CLOCK_GATE_DISABLE
|
7415 CL_UNIT_CLOCK_GATE_DISABLE
);
7416 I915_WRITE(RAMCLK_GATE_D
, 0);
7417 dspclk_gate
= VRHUNIT_CLOCK_GATE_DISABLE
|
7418 OVRUNIT_CLOCK_GATE_DISABLE
|
7419 OVCUNIT_CLOCK_GATE_DISABLE
;
7421 dspclk_gate
|= DSSUNIT_CLOCK_GATE_DISABLE
;
7422 I915_WRITE(DSPCLK_GATE_D
, dspclk_gate
);
7424 /* WaDisableRenderCachePipelinedFlush */
7425 I915_WRITE(CACHE_MODE_0
,
7426 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE
));
7428 /* WaDisable_RenderCache_OperationalFlush:g4x */
7429 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
7431 g4x_disable_trickle_feed(dev
);
7434 static void crestline_init_clock_gating(struct drm_device
*dev
)
7436 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7438 I915_WRITE(RENCLK_GATE_D1
, I965_RCC_CLOCK_GATE_DISABLE
);
7439 I915_WRITE(RENCLK_GATE_D2
, 0);
7440 I915_WRITE(DSPCLK_GATE_D
, 0);
7441 I915_WRITE(RAMCLK_GATE_D
, 0);
7442 I915_WRITE16(DEUC
, 0);
7443 I915_WRITE(MI_ARB_STATE
,
7444 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
));
7446 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7447 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
7450 static void broadwater_init_clock_gating(struct drm_device
*dev
)
7452 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7454 I915_WRITE(RENCLK_GATE_D1
, I965_RCZ_CLOCK_GATE_DISABLE
|
7455 I965_RCC_CLOCK_GATE_DISABLE
|
7456 I965_RCPB_CLOCK_GATE_DISABLE
|
7457 I965_ISC_CLOCK_GATE_DISABLE
|
7458 I965_FBC_CLOCK_GATE_DISABLE
);
7459 I915_WRITE(RENCLK_GATE_D2
, 0);
7460 I915_WRITE(MI_ARB_STATE
,
7461 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
));
7463 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7464 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
7467 static void gen3_init_clock_gating(struct drm_device
*dev
)
7469 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7470 u32 dstate
= I915_READ(D_STATE
);
7472 dstate
|= DSTATE_PLL_D3_OFF
| DSTATE_GFX_CLOCK_GATING
|
7473 DSTATE_DOT_CLOCK_GATING
;
7474 I915_WRITE(D_STATE
, dstate
);
7476 if (IS_PINEVIEW(dev
))
7477 I915_WRITE(ECOSKPD
, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY
));
7479 /* IIR "flip pending" means done if this bit is set */
7480 I915_WRITE(ECOSKPD
, _MASKED_BIT_DISABLE(ECO_FLIP_DONE
));
7482 /* interrupts should cause a wake up from C3 */
7483 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN
));
7485 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7486 I915_WRITE(MI_ARB_STATE
, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE
));
7488 I915_WRITE(MI_ARB_STATE
,
7489 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
));
7492 static void i85x_init_clock_gating(struct drm_device
*dev
)
7494 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7496 I915_WRITE(RENCLK_GATE_D1
, SV_CLOCK_GATE_DISABLE
);
7498 /* interrupts should cause a wake up from C3 */
7499 I915_WRITE(MI_STATE
, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN
) |
7500 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE
));
7502 I915_WRITE(MEM_MODE
,
7503 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE
));
7506 static void i830_init_clock_gating(struct drm_device
*dev
)
7508 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7510 I915_WRITE(DSPCLK_GATE_D
, OVRUNIT_CLOCK_GATE_DISABLE
);
7512 I915_WRITE(MEM_MODE
,
7513 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE
) |
7514 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE
));
7517 void intel_init_clock_gating(struct drm_device
*dev
)
7519 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7521 dev_priv
->display
.init_clock_gating(dev
);
7524 void intel_suspend_hw(struct drm_device
*dev
)
7526 if (HAS_PCH_LPT(dev
))
7527 lpt_suspend_hw(dev
);
7530 static void nop_init_clock_gating(struct drm_device
*dev
)
7532 DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n");
7536 * intel_init_clock_gating_hooks - setup the clock gating hooks
7537 * @dev_priv: device private
7539 * Setup the hooks that configure which clocks of a given platform can be
7540 * gated and also apply various GT and display specific workarounds for these
7541 * platforms. Note that some GT specific workarounds are applied separately
7542 * when GPU contexts or batchbuffers start their execution.
7544 void intel_init_clock_gating_hooks(struct drm_i915_private
*dev_priv
)
7546 if (IS_SKYLAKE(dev_priv
))
7547 dev_priv
->display
.init_clock_gating
= skylake_init_clock_gating
;
7548 else if (IS_KABYLAKE(dev_priv
))
7549 dev_priv
->display
.init_clock_gating
= kabylake_init_clock_gating
;
7550 else if (IS_BROXTON(dev_priv
))
7551 dev_priv
->display
.init_clock_gating
= bxt_init_clock_gating
;
7552 else if (IS_BROADWELL(dev_priv
))
7553 dev_priv
->display
.init_clock_gating
= broadwell_init_clock_gating
;
7554 else if (IS_CHERRYVIEW(dev_priv
))
7555 dev_priv
->display
.init_clock_gating
= cherryview_init_clock_gating
;
7556 else if (IS_HASWELL(dev_priv
))
7557 dev_priv
->display
.init_clock_gating
= haswell_init_clock_gating
;
7558 else if (IS_IVYBRIDGE(dev_priv
))
7559 dev_priv
->display
.init_clock_gating
= ivybridge_init_clock_gating
;
7560 else if (IS_VALLEYVIEW(dev_priv
))
7561 dev_priv
->display
.init_clock_gating
= valleyview_init_clock_gating
;
7562 else if (IS_GEN6(dev_priv
))
7563 dev_priv
->display
.init_clock_gating
= gen6_init_clock_gating
;
7564 else if (IS_GEN5(dev_priv
))
7565 dev_priv
->display
.init_clock_gating
= ironlake_init_clock_gating
;
7566 else if (IS_G4X(dev_priv
))
7567 dev_priv
->display
.init_clock_gating
= g4x_init_clock_gating
;
7568 else if (IS_CRESTLINE(dev_priv
))
7569 dev_priv
->display
.init_clock_gating
= crestline_init_clock_gating
;
7570 else if (IS_BROADWATER(dev_priv
))
7571 dev_priv
->display
.init_clock_gating
= broadwater_init_clock_gating
;
7572 else if (IS_GEN3(dev_priv
))
7573 dev_priv
->display
.init_clock_gating
= gen3_init_clock_gating
;
7574 else if (IS_I85X(dev_priv
) || IS_I865G(dev_priv
))
7575 dev_priv
->display
.init_clock_gating
= i85x_init_clock_gating
;
7576 else if (IS_GEN2(dev_priv
))
7577 dev_priv
->display
.init_clock_gating
= i830_init_clock_gating
;
7579 MISSING_CASE(INTEL_DEVID(dev_priv
));
7580 dev_priv
->display
.init_clock_gating
= nop_init_clock_gating
;
7584 /* Set up chip specific power management-related functions */
7585 void intel_init_pm(struct drm_device
*dev
)
7587 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7589 intel_fbc_init(dev_priv
);
7592 if (IS_PINEVIEW(dev
))
7593 i915_pineview_get_mem_freq(dev
);
7594 else if (IS_GEN5(dev
))
7595 i915_ironlake_get_mem_freq(dev
);
7597 /* For FIFO watermark updates */
7598 if (INTEL_INFO(dev
)->gen
>= 9) {
7599 skl_setup_wm_latency(dev
);
7600 dev_priv
->display
.update_wm
= skl_update_wm
;
7601 dev_priv
->display
.compute_global_watermarks
= skl_compute_wm
;
7602 } else if (HAS_PCH_SPLIT(dev
)) {
7603 ilk_setup_wm_latency(dev
);
7605 if ((IS_GEN5(dev
) && dev_priv
->wm
.pri_latency
[1] &&
7606 dev_priv
->wm
.spr_latency
[1] && dev_priv
->wm
.cur_latency
[1]) ||
7607 (!IS_GEN5(dev
) && dev_priv
->wm
.pri_latency
[0] &&
7608 dev_priv
->wm
.spr_latency
[0] && dev_priv
->wm
.cur_latency
[0])) {
7609 dev_priv
->display
.compute_pipe_wm
= ilk_compute_pipe_wm
;
7610 dev_priv
->display
.compute_intermediate_wm
=
7611 ilk_compute_intermediate_wm
;
7612 dev_priv
->display
.initial_watermarks
=
7613 ilk_initial_watermarks
;
7614 dev_priv
->display
.optimize_watermarks
=
7615 ilk_optimize_watermarks
;
7617 DRM_DEBUG_KMS("Failed to read display plane latency. "
7620 } else if (IS_CHERRYVIEW(dev
)) {
7621 vlv_setup_wm_latency(dev
);
7622 dev_priv
->display
.update_wm
= vlv_update_wm
;
7623 } else if (IS_VALLEYVIEW(dev
)) {
7624 vlv_setup_wm_latency(dev
);
7625 dev_priv
->display
.update_wm
= vlv_update_wm
;
7626 } else if (IS_PINEVIEW(dev
)) {
7627 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev
),
7630 dev_priv
->mem_freq
)) {
7631 DRM_INFO("failed to find known CxSR latency "
7632 "(found ddr%s fsb freq %d, mem freq %d), "
7634 (dev_priv
->is_ddr3
== 1) ? "3" : "2",
7635 dev_priv
->fsb_freq
, dev_priv
->mem_freq
);
7636 /* Disable CxSR and never update its watermark again */
7637 intel_set_memory_cxsr(dev_priv
, false);
7638 dev_priv
->display
.update_wm
= NULL
;
7640 dev_priv
->display
.update_wm
= pineview_update_wm
;
7641 } else if (IS_G4X(dev
)) {
7642 dev_priv
->display
.update_wm
= g4x_update_wm
;
7643 } else if (IS_GEN4(dev
)) {
7644 dev_priv
->display
.update_wm
= i965_update_wm
;
7645 } else if (IS_GEN3(dev
)) {
7646 dev_priv
->display
.update_wm
= i9xx_update_wm
;
7647 dev_priv
->display
.get_fifo_size
= i9xx_get_fifo_size
;
7648 } else if (IS_GEN2(dev
)) {
7649 if (INTEL_INFO(dev
)->num_pipes
== 1) {
7650 dev_priv
->display
.update_wm
= i845_update_wm
;
7651 dev_priv
->display
.get_fifo_size
= i845_get_fifo_size
;
7653 dev_priv
->display
.update_wm
= i9xx_update_wm
;
7654 dev_priv
->display
.get_fifo_size
= i830_get_fifo_size
;
7657 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
7661 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u32 mbox
, u32
*val
)
7663 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
7665 /* GEN6_PCODE_* are outside of the forcewake domain, we can
7666 * use te fw I915_READ variants to reduce the amount of work
7667 * required when reading/writing.
7670 if (I915_READ_FW(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) {
7671 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7675 I915_WRITE_FW(GEN6_PCODE_DATA
, *val
);
7676 I915_WRITE_FW(GEN6_PCODE_DATA1
, 0);
7677 I915_WRITE_FW(GEN6_PCODE_MAILBOX
, GEN6_PCODE_READY
| mbox
);
7679 if (intel_wait_for_register_fw(dev_priv
,
7680 GEN6_PCODE_MAILBOX
, GEN6_PCODE_READY
, 0,
7682 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox
);
7686 *val
= I915_READ_FW(GEN6_PCODE_DATA
);
7687 I915_WRITE_FW(GEN6_PCODE_DATA
, 0);
7692 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
,
7695 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
7697 /* GEN6_PCODE_* are outside of the forcewake domain, we can
7698 * use te fw I915_READ variants to reduce the amount of work
7699 * required when reading/writing.
7702 if (I915_READ_FW(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) {
7703 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7707 I915_WRITE_FW(GEN6_PCODE_DATA
, val
);
7708 I915_WRITE_FW(GEN6_PCODE_MAILBOX
, GEN6_PCODE_READY
| mbox
);
7710 if (intel_wait_for_register_fw(dev_priv
,
7711 GEN6_PCODE_MAILBOX
, GEN6_PCODE_READY
, 0,
7713 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox
);
7717 I915_WRITE_FW(GEN6_PCODE_DATA
, 0);
7722 static int byt_gpu_freq(struct drm_i915_private
*dev_priv
, int val
)
7726 * Slow = Fast = GPLL ref * N
7728 return DIV_ROUND_CLOSEST(dev_priv
->rps
.gpll_ref_freq
* (val
- 0xb7), 1000);
7731 static int byt_freq_opcode(struct drm_i915_private
*dev_priv
, int val
)
7733 return DIV_ROUND_CLOSEST(1000 * val
, dev_priv
->rps
.gpll_ref_freq
) + 0xb7;
7736 static int chv_gpu_freq(struct drm_i915_private
*dev_priv
, int val
)
7740 * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2
7742 return DIV_ROUND_CLOSEST(dev_priv
->rps
.gpll_ref_freq
* val
, 2 * 2 * 1000);
7745 static int chv_freq_opcode(struct drm_i915_private
*dev_priv
, int val
)
7747 /* CHV needs even values */
7748 return DIV_ROUND_CLOSEST(2 * 1000 * val
, dev_priv
->rps
.gpll_ref_freq
) * 2;
7751 int intel_gpu_freq(struct drm_i915_private
*dev_priv
, int val
)
7753 if (IS_GEN9(dev_priv
))
7754 return DIV_ROUND_CLOSEST(val
* GT_FREQUENCY_MULTIPLIER
,
7756 else if (IS_CHERRYVIEW(dev_priv
))
7757 return chv_gpu_freq(dev_priv
, val
);
7758 else if (IS_VALLEYVIEW(dev_priv
))
7759 return byt_gpu_freq(dev_priv
, val
);
7761 return val
* GT_FREQUENCY_MULTIPLIER
;
7764 int intel_freq_opcode(struct drm_i915_private
*dev_priv
, int val
)
7766 if (IS_GEN9(dev_priv
))
7767 return DIV_ROUND_CLOSEST(val
* GEN9_FREQ_SCALER
,
7768 GT_FREQUENCY_MULTIPLIER
);
7769 else if (IS_CHERRYVIEW(dev_priv
))
7770 return chv_freq_opcode(dev_priv
, val
);
7771 else if (IS_VALLEYVIEW(dev_priv
))
7772 return byt_freq_opcode(dev_priv
, val
);
7774 return DIV_ROUND_CLOSEST(val
, GT_FREQUENCY_MULTIPLIER
);
7777 struct request_boost
{
7778 struct work_struct work
;
7779 struct drm_i915_gem_request
*req
;
7782 static void __intel_rps_boost_work(struct work_struct
*work
)
7784 struct request_boost
*boost
= container_of(work
, struct request_boost
, work
);
7785 struct drm_i915_gem_request
*req
= boost
->req
;
7787 if (!i915_gem_request_completed(req
))
7788 gen6_rps_boost(req
->i915
, NULL
, req
->emitted_jiffies
);
7790 i915_gem_request_unreference(req
);
7794 void intel_queue_rps_boost_for_request(struct drm_i915_gem_request
*req
)
7796 struct request_boost
*boost
;
7798 if (req
== NULL
|| INTEL_GEN(req
->i915
) < 6)
7801 if (i915_gem_request_completed(req
))
7804 boost
= kmalloc(sizeof(*boost
), GFP_ATOMIC
);
7808 i915_gem_request_reference(req
);
7811 INIT_WORK(&boost
->work
, __intel_rps_boost_work
);
7812 queue_work(req
->i915
->wq
, &boost
->work
);
7815 void intel_pm_setup(struct drm_device
*dev
)
7817 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7819 mutex_init(&dev_priv
->rps
.hw_lock
);
7820 spin_lock_init(&dev_priv
->rps
.client_lock
);
7822 INIT_DELAYED_WORK(&dev_priv
->rps
.delayed_resume_work
,
7823 intel_gen6_powersave_work
);
7824 INIT_LIST_HEAD(&dev_priv
->rps
.clients
);
7825 INIT_LIST_HEAD(&dev_priv
->rps
.semaphores
.link
);
7826 INIT_LIST_HEAD(&dev_priv
->rps
.mmioflips
.link
);
7828 dev_priv
->pm
.suspended
= false;
7829 atomic_set(&dev_priv
->pm
.wakeref_count
, 0);
7830 atomic_set(&dev_priv
->pm
.atomic_seq
, 0);