2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
28 #include <linux/cpufreq.h>
29 #include <drm/drm_plane_helper.h>
31 #include "intel_drv.h"
32 #include "../../../platform/x86/intel_ips.h"
33 #include <linux/module.h>
38 * RC6 is a special power stage which allows the GPU to enter an very
39 * low-voltage mode when idle, using down to 0V while at this stage. This
40 * stage is entered automatically when the GPU is idle when RC6 support is
41 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
43 * There are different RC6 modes available in Intel GPU, which differentiate
44 * among each other with the latency required to enter and leave RC6 and
45 * voltage consumed by the GPU in different states.
47 * The combination of the following flags define which states GPU is allowed
48 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
49 * RC6pp is deepest RC6. Their support by hardware varies according to the
50 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
51 * which brings the most power savings; deeper states save more power, but
52 * require higher latency to switch to and wake up.
54 #define INTEL_RC6_ENABLE (1<<0)
55 #define INTEL_RC6p_ENABLE (1<<1)
56 #define INTEL_RC6pp_ENABLE (1<<2)
58 static void gen9_init_clock_gating(struct drm_device
*dev
)
60 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
62 /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl */
63 I915_WRITE(CHICKEN_PAR1_1
,
64 I915_READ(CHICKEN_PAR1_1
) | SKL_EDP_PSR_FIX_RDWRAP
);
66 I915_WRITE(GEN8_CONFIG0
,
67 I915_READ(GEN8_CONFIG0
) | GEN9_DEFAULT_FIXES
);
70 static void bxt_init_clock_gating(struct drm_device
*dev
)
72 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
74 gen9_init_clock_gating(dev
);
76 /* WaDisableSDEUnitClockGating:bxt */
77 I915_WRITE(GEN8_UCGCTL6
, I915_READ(GEN8_UCGCTL6
) |
78 GEN8_SDEUNIT_CLOCK_GATE_DISABLE
);
82 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
84 I915_WRITE(GEN8_UCGCTL6
, I915_READ(GEN8_UCGCTL6
) |
85 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ
);
88 * Wa: Backlight PWM may stop in the asserted state, causing backlight
91 if (IS_BXT_REVID(dev_priv
, BXT_REVID_B0
, REVID_FOREVER
))
92 I915_WRITE(GEN9_CLKGATE_DIS_0
, I915_READ(GEN9_CLKGATE_DIS_0
) |
93 PWM1_GATING_DIS
| PWM2_GATING_DIS
);
96 static void i915_pineview_get_mem_freq(struct drm_device
*dev
)
98 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
101 tmp
= I915_READ(CLKCFG
);
103 switch (tmp
& CLKCFG_FSB_MASK
) {
105 dev_priv
->fsb_freq
= 533; /* 133*4 */
108 dev_priv
->fsb_freq
= 800; /* 200*4 */
111 dev_priv
->fsb_freq
= 667; /* 167*4 */
114 dev_priv
->fsb_freq
= 400; /* 100*4 */
118 switch (tmp
& CLKCFG_MEM_MASK
) {
120 dev_priv
->mem_freq
= 533;
123 dev_priv
->mem_freq
= 667;
126 dev_priv
->mem_freq
= 800;
130 /* detect pineview DDR3 setting */
131 tmp
= I915_READ(CSHRDDR3CTL
);
132 dev_priv
->is_ddr3
= (tmp
& CSHRDDR3CTL_DDR3
) ? 1 : 0;
135 static void i915_ironlake_get_mem_freq(struct drm_device
*dev
)
137 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
140 ddrpll
= I915_READ16(DDRMPLL1
);
141 csipll
= I915_READ16(CSIPLL0
);
143 switch (ddrpll
& 0xff) {
145 dev_priv
->mem_freq
= 800;
148 dev_priv
->mem_freq
= 1066;
151 dev_priv
->mem_freq
= 1333;
154 dev_priv
->mem_freq
= 1600;
157 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
159 dev_priv
->mem_freq
= 0;
163 dev_priv
->ips
.r_t
= dev_priv
->mem_freq
;
165 switch (csipll
& 0x3ff) {
167 dev_priv
->fsb_freq
= 3200;
170 dev_priv
->fsb_freq
= 3733;
173 dev_priv
->fsb_freq
= 4266;
176 dev_priv
->fsb_freq
= 4800;
179 dev_priv
->fsb_freq
= 5333;
182 dev_priv
->fsb_freq
= 5866;
185 dev_priv
->fsb_freq
= 6400;
188 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
190 dev_priv
->fsb_freq
= 0;
194 if (dev_priv
->fsb_freq
== 3200) {
195 dev_priv
->ips
.c_m
= 0;
196 } else if (dev_priv
->fsb_freq
> 3200 && dev_priv
->fsb_freq
<= 4800) {
197 dev_priv
->ips
.c_m
= 1;
199 dev_priv
->ips
.c_m
= 2;
203 static const struct cxsr_latency cxsr_latency_table
[] = {
204 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
205 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
206 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
207 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
208 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
210 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
211 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
212 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
213 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
214 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
216 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
217 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
218 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
219 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
220 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
222 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
223 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
224 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
225 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
226 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
228 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
229 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
230 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
231 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
232 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
234 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
235 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
236 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
237 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
238 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
241 static const struct cxsr_latency
*intel_get_cxsr_latency(int is_desktop
,
246 const struct cxsr_latency
*latency
;
249 if (fsb
== 0 || mem
== 0)
252 for (i
= 0; i
< ARRAY_SIZE(cxsr_latency_table
); i
++) {
253 latency
= &cxsr_latency_table
[i
];
254 if (is_desktop
== latency
->is_desktop
&&
255 is_ddr3
== latency
->is_ddr3
&&
256 fsb
== latency
->fsb_freq
&& mem
== latency
->mem_freq
)
260 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
265 static void chv_set_memory_dvfs(struct drm_i915_private
*dev_priv
, bool enable
)
269 mutex_lock(&dev_priv
->rps
.hw_lock
);
271 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DDR_SETUP2
);
273 val
&= ~FORCE_DDR_HIGH_FREQ
;
275 val
|= FORCE_DDR_HIGH_FREQ
;
276 val
&= ~FORCE_DDR_LOW_FREQ
;
277 val
|= FORCE_DDR_FREQ_REQ_ACK
;
278 vlv_punit_write(dev_priv
, PUNIT_REG_DDR_SETUP2
, val
);
280 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DDR_SETUP2
) &
281 FORCE_DDR_FREQ_REQ_ACK
) == 0, 3))
282 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
284 mutex_unlock(&dev_priv
->rps
.hw_lock
);
287 static void chv_set_memory_pm5(struct drm_i915_private
*dev_priv
, bool enable
)
291 mutex_lock(&dev_priv
->rps
.hw_lock
);
293 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
295 val
|= DSP_MAXFIFO_PM5_ENABLE
;
297 val
&= ~DSP_MAXFIFO_PM5_ENABLE
;
298 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
300 mutex_unlock(&dev_priv
->rps
.hw_lock
);
303 #define FW_WM(value, plane) \
304 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
306 void intel_set_memory_cxsr(struct drm_i915_private
*dev_priv
, bool enable
)
308 struct drm_device
*dev
= dev_priv
->dev
;
311 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
312 I915_WRITE(FW_BLC_SELF_VLV
, enable
? FW_CSPWRDWNEN
: 0);
313 POSTING_READ(FW_BLC_SELF_VLV
);
314 dev_priv
->wm
.vlv
.cxsr
= enable
;
315 } else if (IS_G4X(dev
) || IS_CRESTLINE(dev
)) {
316 I915_WRITE(FW_BLC_SELF
, enable
? FW_BLC_SELF_EN
: 0);
317 POSTING_READ(FW_BLC_SELF
);
318 } else if (IS_PINEVIEW(dev
)) {
319 val
= I915_READ(DSPFW3
) & ~PINEVIEW_SELF_REFRESH_EN
;
320 val
|= enable
? PINEVIEW_SELF_REFRESH_EN
: 0;
321 I915_WRITE(DSPFW3
, val
);
322 POSTING_READ(DSPFW3
);
323 } else if (IS_I945G(dev
) || IS_I945GM(dev
)) {
324 val
= enable
? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN
) :
325 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN
);
326 I915_WRITE(FW_BLC_SELF
, val
);
327 POSTING_READ(FW_BLC_SELF
);
328 } else if (IS_I915GM(dev
)) {
329 val
= enable
? _MASKED_BIT_ENABLE(INSTPM_SELF_EN
) :
330 _MASKED_BIT_DISABLE(INSTPM_SELF_EN
);
331 I915_WRITE(INSTPM
, val
);
332 POSTING_READ(INSTPM
);
337 DRM_DEBUG_KMS("memory self-refresh is %s\n",
338 enable
? "enabled" : "disabled");
343 * Latency for FIFO fetches is dependent on several factors:
344 * - memory configuration (speed, channels)
346 * - current MCH state
347 * It can be fairly high in some situations, so here we assume a fairly
348 * pessimal value. It's a tradeoff between extra memory fetches (if we
349 * set this value too high, the FIFO will fetch frequently to stay full)
350 * and power consumption (set it too low to save power and we might see
351 * FIFO underruns and display "flicker").
353 * A value of 5us seems to be a good balance; safe for very low end
354 * platforms but not overly aggressive on lower latency configs.
356 static const int pessimal_latency_ns
= 5000;
358 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
359 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
361 static int vlv_get_fifo_size(struct drm_device
*dev
,
362 enum pipe pipe
, int plane
)
364 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
365 int sprite0_start
, sprite1_start
, size
;
368 uint32_t dsparb
, dsparb2
, dsparb3
;
370 dsparb
= I915_READ(DSPARB
);
371 dsparb2
= I915_READ(DSPARB2
);
372 sprite0_start
= VLV_FIFO_START(dsparb
, dsparb2
, 0, 0);
373 sprite1_start
= VLV_FIFO_START(dsparb
, dsparb2
, 8, 4);
376 dsparb
= I915_READ(DSPARB
);
377 dsparb2
= I915_READ(DSPARB2
);
378 sprite0_start
= VLV_FIFO_START(dsparb
, dsparb2
, 16, 8);
379 sprite1_start
= VLV_FIFO_START(dsparb
, dsparb2
, 24, 12);
382 dsparb2
= I915_READ(DSPARB2
);
383 dsparb3
= I915_READ(DSPARB3
);
384 sprite0_start
= VLV_FIFO_START(dsparb3
, dsparb2
, 0, 16);
385 sprite1_start
= VLV_FIFO_START(dsparb3
, dsparb2
, 8, 20);
393 size
= sprite0_start
;
396 size
= sprite1_start
- sprite0_start
;
399 size
= 512 - 1 - sprite1_start
;
405 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
406 pipe_name(pipe
), plane
== 0 ? "primary" : "sprite",
407 plane
== 0 ? plane_name(pipe
) : sprite_name(pipe
, plane
- 1),
413 static int i9xx_get_fifo_size(struct drm_device
*dev
, int plane
)
415 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
416 uint32_t dsparb
= I915_READ(DSPARB
);
419 size
= dsparb
& 0x7f;
421 size
= ((dsparb
>> DSPARB_CSTART_SHIFT
) & 0x7f) - size
;
423 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
424 plane
? "B" : "A", size
);
429 static int i830_get_fifo_size(struct drm_device
*dev
, int plane
)
431 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
432 uint32_t dsparb
= I915_READ(DSPARB
);
435 size
= dsparb
& 0x1ff;
437 size
= ((dsparb
>> DSPARB_BEND_SHIFT
) & 0x1ff) - size
;
438 size
>>= 1; /* Convert to cachelines */
440 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
441 plane
? "B" : "A", size
);
446 static int i845_get_fifo_size(struct drm_device
*dev
, int plane
)
448 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
449 uint32_t dsparb
= I915_READ(DSPARB
);
452 size
= dsparb
& 0x7f;
453 size
>>= 2; /* Convert to cachelines */
455 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
462 /* Pineview has different values for various configs */
463 static const struct intel_watermark_params pineview_display_wm
= {
464 .fifo_size
= PINEVIEW_DISPLAY_FIFO
,
465 .max_wm
= PINEVIEW_MAX_WM
,
466 .default_wm
= PINEVIEW_DFT_WM
,
467 .guard_size
= PINEVIEW_GUARD_WM
,
468 .cacheline_size
= PINEVIEW_FIFO_LINE_SIZE
,
470 static const struct intel_watermark_params pineview_display_hplloff_wm
= {
471 .fifo_size
= PINEVIEW_DISPLAY_FIFO
,
472 .max_wm
= PINEVIEW_MAX_WM
,
473 .default_wm
= PINEVIEW_DFT_HPLLOFF_WM
,
474 .guard_size
= PINEVIEW_GUARD_WM
,
475 .cacheline_size
= PINEVIEW_FIFO_LINE_SIZE
,
477 static const struct intel_watermark_params pineview_cursor_wm
= {
478 .fifo_size
= PINEVIEW_CURSOR_FIFO
,
479 .max_wm
= PINEVIEW_CURSOR_MAX_WM
,
480 .default_wm
= PINEVIEW_CURSOR_DFT_WM
,
481 .guard_size
= PINEVIEW_CURSOR_GUARD_WM
,
482 .cacheline_size
= PINEVIEW_FIFO_LINE_SIZE
,
484 static const struct intel_watermark_params pineview_cursor_hplloff_wm
= {
485 .fifo_size
= PINEVIEW_CURSOR_FIFO
,
486 .max_wm
= PINEVIEW_CURSOR_MAX_WM
,
487 .default_wm
= PINEVIEW_CURSOR_DFT_WM
,
488 .guard_size
= PINEVIEW_CURSOR_GUARD_WM
,
489 .cacheline_size
= PINEVIEW_FIFO_LINE_SIZE
,
491 static const struct intel_watermark_params g4x_wm_info
= {
492 .fifo_size
= G4X_FIFO_SIZE
,
493 .max_wm
= G4X_MAX_WM
,
494 .default_wm
= G4X_MAX_WM
,
496 .cacheline_size
= G4X_FIFO_LINE_SIZE
,
498 static const struct intel_watermark_params g4x_cursor_wm_info
= {
499 .fifo_size
= I965_CURSOR_FIFO
,
500 .max_wm
= I965_CURSOR_MAX_WM
,
501 .default_wm
= I965_CURSOR_DFT_WM
,
503 .cacheline_size
= G4X_FIFO_LINE_SIZE
,
505 static const struct intel_watermark_params i965_cursor_wm_info
= {
506 .fifo_size
= I965_CURSOR_FIFO
,
507 .max_wm
= I965_CURSOR_MAX_WM
,
508 .default_wm
= I965_CURSOR_DFT_WM
,
510 .cacheline_size
= I915_FIFO_LINE_SIZE
,
512 static const struct intel_watermark_params i945_wm_info
= {
513 .fifo_size
= I945_FIFO_SIZE
,
514 .max_wm
= I915_MAX_WM
,
517 .cacheline_size
= I915_FIFO_LINE_SIZE
,
519 static const struct intel_watermark_params i915_wm_info
= {
520 .fifo_size
= I915_FIFO_SIZE
,
521 .max_wm
= I915_MAX_WM
,
524 .cacheline_size
= I915_FIFO_LINE_SIZE
,
526 static const struct intel_watermark_params i830_a_wm_info
= {
527 .fifo_size
= I855GM_FIFO_SIZE
,
528 .max_wm
= I915_MAX_WM
,
531 .cacheline_size
= I830_FIFO_LINE_SIZE
,
533 static const struct intel_watermark_params i830_bc_wm_info
= {
534 .fifo_size
= I855GM_FIFO_SIZE
,
535 .max_wm
= I915_MAX_WM
/2,
538 .cacheline_size
= I830_FIFO_LINE_SIZE
,
540 static const struct intel_watermark_params i845_wm_info
= {
541 .fifo_size
= I830_FIFO_SIZE
,
542 .max_wm
= I915_MAX_WM
,
545 .cacheline_size
= I830_FIFO_LINE_SIZE
,
549 * intel_calculate_wm - calculate watermark level
550 * @clock_in_khz: pixel clock
551 * @wm: chip FIFO params
552 * @cpp: bytes per pixel
553 * @latency_ns: memory latency for the platform
555 * Calculate the watermark level (the level at which the display plane will
556 * start fetching from memory again). Each chip has a different display
557 * FIFO size and allocation, so the caller needs to figure that out and pass
558 * in the correct intel_watermark_params structure.
560 * As the pixel clock runs, the FIFO will be drained at a rate that depends
561 * on the pixel size. When it reaches the watermark level, it'll start
562 * fetching FIFO line sized based chunks from memory until the FIFO fills
563 * past the watermark point. If the FIFO drains completely, a FIFO underrun
564 * will occur, and a display engine hang could result.
566 static unsigned long intel_calculate_wm(unsigned long clock_in_khz
,
567 const struct intel_watermark_params
*wm
,
568 int fifo_size
, int cpp
,
569 unsigned long latency_ns
)
571 long entries_required
, wm_size
;
574 * Note: we need to make sure we don't overflow for various clock &
576 * clocks go from a few thousand to several hundred thousand.
577 * latency is usually a few thousand
579 entries_required
= ((clock_in_khz
/ 1000) * cpp
* latency_ns
) /
581 entries_required
= DIV_ROUND_UP(entries_required
, wm
->cacheline_size
);
583 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required
);
585 wm_size
= fifo_size
- (entries_required
+ wm
->guard_size
);
587 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size
);
589 /* Don't promote wm_size to unsigned... */
590 if (wm_size
> (long)wm
->max_wm
)
591 wm_size
= wm
->max_wm
;
593 wm_size
= wm
->default_wm
;
596 * Bspec seems to indicate that the value shouldn't be lower than
597 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
598 * Lets go for 8 which is the burst size since certain platforms
599 * already use a hardcoded 8 (which is what the spec says should be
608 static struct drm_crtc
*single_enabled_crtc(struct drm_device
*dev
)
610 struct drm_crtc
*crtc
, *enabled
= NULL
;
612 for_each_crtc(dev
, crtc
) {
613 if (intel_crtc_active(crtc
)) {
623 static void pineview_update_wm(struct drm_crtc
*unused_crtc
)
625 struct drm_device
*dev
= unused_crtc
->dev
;
626 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
627 struct drm_crtc
*crtc
;
628 const struct cxsr_latency
*latency
;
632 latency
= intel_get_cxsr_latency(IS_PINEVIEW_G(dev
), dev_priv
->is_ddr3
,
633 dev_priv
->fsb_freq
, dev_priv
->mem_freq
);
635 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
636 intel_set_memory_cxsr(dev_priv
, false);
640 crtc
= single_enabled_crtc(dev
);
642 const struct drm_display_mode
*adjusted_mode
= &to_intel_crtc(crtc
)->config
->base
.adjusted_mode
;
643 int cpp
= drm_format_plane_cpp(crtc
->primary
->state
->fb
->pixel_format
, 0);
644 int clock
= adjusted_mode
->crtc_clock
;
647 wm
= intel_calculate_wm(clock
, &pineview_display_wm
,
648 pineview_display_wm
.fifo_size
,
649 cpp
, latency
->display_sr
);
650 reg
= I915_READ(DSPFW1
);
651 reg
&= ~DSPFW_SR_MASK
;
652 reg
|= FW_WM(wm
, SR
);
653 I915_WRITE(DSPFW1
, reg
);
654 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg
);
657 wm
= intel_calculate_wm(clock
, &pineview_cursor_wm
,
658 pineview_display_wm
.fifo_size
,
659 cpp
, latency
->cursor_sr
);
660 reg
= I915_READ(DSPFW3
);
661 reg
&= ~DSPFW_CURSOR_SR_MASK
;
662 reg
|= FW_WM(wm
, CURSOR_SR
);
663 I915_WRITE(DSPFW3
, reg
);
665 /* Display HPLL off SR */
666 wm
= intel_calculate_wm(clock
, &pineview_display_hplloff_wm
,
667 pineview_display_hplloff_wm
.fifo_size
,
668 cpp
, latency
->display_hpll_disable
);
669 reg
= I915_READ(DSPFW3
);
670 reg
&= ~DSPFW_HPLL_SR_MASK
;
671 reg
|= FW_WM(wm
, HPLL_SR
);
672 I915_WRITE(DSPFW3
, reg
);
674 /* cursor HPLL off SR */
675 wm
= intel_calculate_wm(clock
, &pineview_cursor_hplloff_wm
,
676 pineview_display_hplloff_wm
.fifo_size
,
677 cpp
, latency
->cursor_hpll_disable
);
678 reg
= I915_READ(DSPFW3
);
679 reg
&= ~DSPFW_HPLL_CURSOR_MASK
;
680 reg
|= FW_WM(wm
, HPLL_CURSOR
);
681 I915_WRITE(DSPFW3
, reg
);
682 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg
);
684 intel_set_memory_cxsr(dev_priv
, true);
686 intel_set_memory_cxsr(dev_priv
, false);
690 static bool g4x_compute_wm0(struct drm_device
*dev
,
692 const struct intel_watermark_params
*display
,
693 int display_latency_ns
,
694 const struct intel_watermark_params
*cursor
,
695 int cursor_latency_ns
,
699 struct drm_crtc
*crtc
;
700 const struct drm_display_mode
*adjusted_mode
;
701 int htotal
, hdisplay
, clock
, cpp
;
702 int line_time_us
, line_count
;
703 int entries
, tlb_miss
;
705 crtc
= intel_get_crtc_for_plane(dev
, plane
);
706 if (!intel_crtc_active(crtc
)) {
707 *cursor_wm
= cursor
->guard_size
;
708 *plane_wm
= display
->guard_size
;
712 adjusted_mode
= &to_intel_crtc(crtc
)->config
->base
.adjusted_mode
;
713 clock
= adjusted_mode
->crtc_clock
;
714 htotal
= adjusted_mode
->crtc_htotal
;
715 hdisplay
= to_intel_crtc(crtc
)->config
->pipe_src_w
;
716 cpp
= drm_format_plane_cpp(crtc
->primary
->state
->fb
->pixel_format
, 0);
718 /* Use the small buffer method to calculate plane watermark */
719 entries
= ((clock
* cpp
/ 1000) * display_latency_ns
) / 1000;
720 tlb_miss
= display
->fifo_size
*display
->cacheline_size
- hdisplay
* 8;
723 entries
= DIV_ROUND_UP(entries
, display
->cacheline_size
);
724 *plane_wm
= entries
+ display
->guard_size
;
725 if (*plane_wm
> (int)display
->max_wm
)
726 *plane_wm
= display
->max_wm
;
728 /* Use the large buffer method to calculate cursor watermark */
729 line_time_us
= max(htotal
* 1000 / clock
, 1);
730 line_count
= (cursor_latency_ns
/ line_time_us
+ 1000) / 1000;
731 entries
= line_count
* crtc
->cursor
->state
->crtc_w
* cpp
;
732 tlb_miss
= cursor
->fifo_size
*cursor
->cacheline_size
- hdisplay
* 8;
735 entries
= DIV_ROUND_UP(entries
, cursor
->cacheline_size
);
736 *cursor_wm
= entries
+ cursor
->guard_size
;
737 if (*cursor_wm
> (int)cursor
->max_wm
)
738 *cursor_wm
= (int)cursor
->max_wm
;
744 * Check the wm result.
746 * If any calculated watermark values is larger than the maximum value that
747 * can be programmed into the associated watermark register, that watermark
750 static bool g4x_check_srwm(struct drm_device
*dev
,
751 int display_wm
, int cursor_wm
,
752 const struct intel_watermark_params
*display
,
753 const struct intel_watermark_params
*cursor
)
755 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
756 display_wm
, cursor_wm
);
758 if (display_wm
> display
->max_wm
) {
759 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
760 display_wm
, display
->max_wm
);
764 if (cursor_wm
> cursor
->max_wm
) {
765 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
766 cursor_wm
, cursor
->max_wm
);
770 if (!(display_wm
|| cursor_wm
)) {
771 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
778 static bool g4x_compute_srwm(struct drm_device
*dev
,
781 const struct intel_watermark_params
*display
,
782 const struct intel_watermark_params
*cursor
,
783 int *display_wm
, int *cursor_wm
)
785 struct drm_crtc
*crtc
;
786 const struct drm_display_mode
*adjusted_mode
;
787 int hdisplay
, htotal
, cpp
, clock
;
788 unsigned long line_time_us
;
789 int line_count
, line_size
;
794 *display_wm
= *cursor_wm
= 0;
798 crtc
= intel_get_crtc_for_plane(dev
, plane
);
799 adjusted_mode
= &to_intel_crtc(crtc
)->config
->base
.adjusted_mode
;
800 clock
= adjusted_mode
->crtc_clock
;
801 htotal
= adjusted_mode
->crtc_htotal
;
802 hdisplay
= to_intel_crtc(crtc
)->config
->pipe_src_w
;
803 cpp
= drm_format_plane_cpp(crtc
->primary
->state
->fb
->pixel_format
, 0);
805 line_time_us
= max(htotal
* 1000 / clock
, 1);
806 line_count
= (latency_ns
/ line_time_us
+ 1000) / 1000;
807 line_size
= hdisplay
* cpp
;
809 /* Use the minimum of the small and large buffer method for primary */
810 small
= ((clock
* cpp
/ 1000) * latency_ns
) / 1000;
811 large
= line_count
* line_size
;
813 entries
= DIV_ROUND_UP(min(small
, large
), display
->cacheline_size
);
814 *display_wm
= entries
+ display
->guard_size
;
816 /* calculate the self-refresh watermark for display cursor */
817 entries
= line_count
* cpp
* crtc
->cursor
->state
->crtc_w
;
818 entries
= DIV_ROUND_UP(entries
, cursor
->cacheline_size
);
819 *cursor_wm
= entries
+ cursor
->guard_size
;
821 return g4x_check_srwm(dev
,
822 *display_wm
, *cursor_wm
,
826 #define FW_WM_VLV(value, plane) \
827 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
829 static void vlv_write_wm_values(struct intel_crtc
*crtc
,
830 const struct vlv_wm_values
*wm
)
832 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
833 enum pipe pipe
= crtc
->pipe
;
835 I915_WRITE(VLV_DDL(pipe
),
836 (wm
->ddl
[pipe
].cursor
<< DDL_CURSOR_SHIFT
) |
837 (wm
->ddl
[pipe
].sprite
[1] << DDL_SPRITE_SHIFT(1)) |
838 (wm
->ddl
[pipe
].sprite
[0] << DDL_SPRITE_SHIFT(0)) |
839 (wm
->ddl
[pipe
].primary
<< DDL_PLANE_SHIFT
));
842 FW_WM(wm
->sr
.plane
, SR
) |
843 FW_WM(wm
->pipe
[PIPE_B
].cursor
, CURSORB
) |
844 FW_WM_VLV(wm
->pipe
[PIPE_B
].primary
, PLANEB
) |
845 FW_WM_VLV(wm
->pipe
[PIPE_A
].primary
, PLANEA
));
847 FW_WM_VLV(wm
->pipe
[PIPE_A
].sprite
[1], SPRITEB
) |
848 FW_WM(wm
->pipe
[PIPE_A
].cursor
, CURSORA
) |
849 FW_WM_VLV(wm
->pipe
[PIPE_A
].sprite
[0], SPRITEA
));
851 FW_WM(wm
->sr
.cursor
, CURSOR_SR
));
853 if (IS_CHERRYVIEW(dev_priv
)) {
854 I915_WRITE(DSPFW7_CHV
,
855 FW_WM_VLV(wm
->pipe
[PIPE_B
].sprite
[1], SPRITED
) |
856 FW_WM_VLV(wm
->pipe
[PIPE_B
].sprite
[0], SPRITEC
));
857 I915_WRITE(DSPFW8_CHV
,
858 FW_WM_VLV(wm
->pipe
[PIPE_C
].sprite
[1], SPRITEF
) |
859 FW_WM_VLV(wm
->pipe
[PIPE_C
].sprite
[0], SPRITEE
));
860 I915_WRITE(DSPFW9_CHV
,
861 FW_WM_VLV(wm
->pipe
[PIPE_C
].primary
, PLANEC
) |
862 FW_WM(wm
->pipe
[PIPE_C
].cursor
, CURSORC
));
864 FW_WM(wm
->sr
.plane
>> 9, SR_HI
) |
865 FW_WM(wm
->pipe
[PIPE_C
].sprite
[1] >> 8, SPRITEF_HI
) |
866 FW_WM(wm
->pipe
[PIPE_C
].sprite
[0] >> 8, SPRITEE_HI
) |
867 FW_WM(wm
->pipe
[PIPE_C
].primary
>> 8, PLANEC_HI
) |
868 FW_WM(wm
->pipe
[PIPE_B
].sprite
[1] >> 8, SPRITED_HI
) |
869 FW_WM(wm
->pipe
[PIPE_B
].sprite
[0] >> 8, SPRITEC_HI
) |
870 FW_WM(wm
->pipe
[PIPE_B
].primary
>> 8, PLANEB_HI
) |
871 FW_WM(wm
->pipe
[PIPE_A
].sprite
[1] >> 8, SPRITEB_HI
) |
872 FW_WM(wm
->pipe
[PIPE_A
].sprite
[0] >> 8, SPRITEA_HI
) |
873 FW_WM(wm
->pipe
[PIPE_A
].primary
>> 8, PLANEA_HI
));
876 FW_WM_VLV(wm
->pipe
[PIPE_B
].sprite
[1], SPRITED
) |
877 FW_WM_VLV(wm
->pipe
[PIPE_B
].sprite
[0], SPRITEC
));
879 FW_WM(wm
->sr
.plane
>> 9, SR_HI
) |
880 FW_WM(wm
->pipe
[PIPE_B
].sprite
[1] >> 8, SPRITED_HI
) |
881 FW_WM(wm
->pipe
[PIPE_B
].sprite
[0] >> 8, SPRITEC_HI
) |
882 FW_WM(wm
->pipe
[PIPE_B
].primary
>> 8, PLANEB_HI
) |
883 FW_WM(wm
->pipe
[PIPE_A
].sprite
[1] >> 8, SPRITEB_HI
) |
884 FW_WM(wm
->pipe
[PIPE_A
].sprite
[0] >> 8, SPRITEA_HI
) |
885 FW_WM(wm
->pipe
[PIPE_A
].primary
>> 8, PLANEA_HI
));
888 /* zero (unused) WM1 watermarks */
889 I915_WRITE(DSPFW4
, 0);
890 I915_WRITE(DSPFW5
, 0);
891 I915_WRITE(DSPFW6
, 0);
892 I915_WRITE(DSPHOWM1
, 0);
894 POSTING_READ(DSPFW1
);
902 VLV_WM_LEVEL_DDR_DVFS
,
905 /* latency must be in 0.1us units. */
906 static unsigned int vlv_wm_method2(unsigned int pixel_rate
,
907 unsigned int pipe_htotal
,
908 unsigned int horiz_pixels
,
910 unsigned int latency
)
914 ret
= (latency
* pixel_rate
) / (pipe_htotal
* 10000);
915 ret
= (ret
+ 1) * horiz_pixels
* cpp
;
916 ret
= DIV_ROUND_UP(ret
, 64);
921 static void vlv_setup_wm_latency(struct drm_device
*dev
)
923 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
925 /* all latencies in usec */
926 dev_priv
->wm
.pri_latency
[VLV_WM_LEVEL_PM2
] = 3;
928 dev_priv
->wm
.max_level
= VLV_WM_LEVEL_PM2
;
930 if (IS_CHERRYVIEW(dev_priv
)) {
931 dev_priv
->wm
.pri_latency
[VLV_WM_LEVEL_PM5
] = 12;
932 dev_priv
->wm
.pri_latency
[VLV_WM_LEVEL_DDR_DVFS
] = 33;
934 dev_priv
->wm
.max_level
= VLV_WM_LEVEL_DDR_DVFS
;
938 static uint16_t vlv_compute_wm_level(struct intel_plane
*plane
,
939 struct intel_crtc
*crtc
,
940 const struct intel_plane_state
*state
,
943 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
944 int clock
, htotal
, cpp
, width
, wm
;
946 if (dev_priv
->wm
.pri_latency
[level
] == 0)
952 cpp
= drm_format_plane_cpp(state
->base
.fb
->pixel_format
, 0);
953 clock
= crtc
->config
->base
.adjusted_mode
.crtc_clock
;
954 htotal
= crtc
->config
->base
.adjusted_mode
.crtc_htotal
;
955 width
= crtc
->config
->pipe_src_w
;
956 if (WARN_ON(htotal
== 0))
959 if (plane
->base
.type
== DRM_PLANE_TYPE_CURSOR
) {
961 * FIXME the formula gives values that are
962 * too big for the cursor FIFO, and hence we
963 * would never be able to use cursors. For
964 * now just hardcode the watermark.
968 wm
= vlv_wm_method2(clock
, htotal
, width
, cpp
,
969 dev_priv
->wm
.pri_latency
[level
] * 10);
972 return min_t(int, wm
, USHRT_MAX
);
975 static void vlv_compute_fifo(struct intel_crtc
*crtc
)
977 struct drm_device
*dev
= crtc
->base
.dev
;
978 struct vlv_wm_state
*wm_state
= &crtc
->wm_state
;
979 struct intel_plane
*plane
;
980 unsigned int total_rate
= 0;
981 const int fifo_size
= 512 - 1;
982 int fifo_extra
, fifo_left
= fifo_size
;
984 for_each_intel_plane_on_crtc(dev
, crtc
, plane
) {
985 struct intel_plane_state
*state
=
986 to_intel_plane_state(plane
->base
.state
);
988 if (plane
->base
.type
== DRM_PLANE_TYPE_CURSOR
)
991 if (state
->visible
) {
992 wm_state
->num_active_planes
++;
993 total_rate
+= drm_format_plane_cpp(state
->base
.fb
->pixel_format
, 0);
997 for_each_intel_plane_on_crtc(dev
, crtc
, plane
) {
998 struct intel_plane_state
*state
=
999 to_intel_plane_state(plane
->base
.state
);
1002 if (plane
->base
.type
== DRM_PLANE_TYPE_CURSOR
) {
1003 plane
->wm
.fifo_size
= 63;
1007 if (!state
->visible
) {
1008 plane
->wm
.fifo_size
= 0;
1012 rate
= drm_format_plane_cpp(state
->base
.fb
->pixel_format
, 0);
1013 plane
->wm
.fifo_size
= fifo_size
* rate
/ total_rate
;
1014 fifo_left
-= plane
->wm
.fifo_size
;
1017 fifo_extra
= DIV_ROUND_UP(fifo_left
, wm_state
->num_active_planes
?: 1);
1019 /* spread the remainder evenly */
1020 for_each_intel_plane_on_crtc(dev
, crtc
, plane
) {
1026 if (plane
->base
.type
== DRM_PLANE_TYPE_CURSOR
)
1029 /* give it all to the first plane if none are active */
1030 if (plane
->wm
.fifo_size
== 0 &&
1031 wm_state
->num_active_planes
)
1034 plane_extra
= min(fifo_extra
, fifo_left
);
1035 plane
->wm
.fifo_size
+= plane_extra
;
1036 fifo_left
-= plane_extra
;
1039 WARN_ON(fifo_left
!= 0);
1042 static void vlv_invert_wms(struct intel_crtc
*crtc
)
1044 struct vlv_wm_state
*wm_state
= &crtc
->wm_state
;
1047 for (level
= 0; level
< wm_state
->num_levels
; level
++) {
1048 struct drm_device
*dev
= crtc
->base
.dev
;
1049 const int sr_fifo_size
= INTEL_INFO(dev
)->num_pipes
* 512 - 1;
1050 struct intel_plane
*plane
;
1052 wm_state
->sr
[level
].plane
= sr_fifo_size
- wm_state
->sr
[level
].plane
;
1053 wm_state
->sr
[level
].cursor
= 63 - wm_state
->sr
[level
].cursor
;
1055 for_each_intel_plane_on_crtc(dev
, crtc
, plane
) {
1056 switch (plane
->base
.type
) {
1058 case DRM_PLANE_TYPE_CURSOR
:
1059 wm_state
->wm
[level
].cursor
= plane
->wm
.fifo_size
-
1060 wm_state
->wm
[level
].cursor
;
1062 case DRM_PLANE_TYPE_PRIMARY
:
1063 wm_state
->wm
[level
].primary
= plane
->wm
.fifo_size
-
1064 wm_state
->wm
[level
].primary
;
1066 case DRM_PLANE_TYPE_OVERLAY
:
1067 sprite
= plane
->plane
;
1068 wm_state
->wm
[level
].sprite
[sprite
] = plane
->wm
.fifo_size
-
1069 wm_state
->wm
[level
].sprite
[sprite
];
1076 static void vlv_compute_wm(struct intel_crtc
*crtc
)
1078 struct drm_device
*dev
= crtc
->base
.dev
;
1079 struct vlv_wm_state
*wm_state
= &crtc
->wm_state
;
1080 struct intel_plane
*plane
;
1081 int sr_fifo_size
= INTEL_INFO(dev
)->num_pipes
* 512 - 1;
1084 memset(wm_state
, 0, sizeof(*wm_state
));
1086 wm_state
->cxsr
= crtc
->pipe
!= PIPE_C
&& crtc
->wm
.cxsr_allowed
;
1087 wm_state
->num_levels
= to_i915(dev
)->wm
.max_level
+ 1;
1089 wm_state
->num_active_planes
= 0;
1091 vlv_compute_fifo(crtc
);
1093 if (wm_state
->num_active_planes
!= 1)
1094 wm_state
->cxsr
= false;
1096 if (wm_state
->cxsr
) {
1097 for (level
= 0; level
< wm_state
->num_levels
; level
++) {
1098 wm_state
->sr
[level
].plane
= sr_fifo_size
;
1099 wm_state
->sr
[level
].cursor
= 63;
1103 for_each_intel_plane_on_crtc(dev
, crtc
, plane
) {
1104 struct intel_plane_state
*state
=
1105 to_intel_plane_state(plane
->base
.state
);
1107 if (!state
->visible
)
1110 /* normal watermarks */
1111 for (level
= 0; level
< wm_state
->num_levels
; level
++) {
1112 int wm
= vlv_compute_wm_level(plane
, crtc
, state
, level
);
1113 int max_wm
= plane
->base
.type
== DRM_PLANE_TYPE_CURSOR
? 63 : 511;
1116 if (WARN_ON(level
== 0 && wm
> max_wm
))
1119 if (wm
> plane
->wm
.fifo_size
)
1122 switch (plane
->base
.type
) {
1124 case DRM_PLANE_TYPE_CURSOR
:
1125 wm_state
->wm
[level
].cursor
= wm
;
1127 case DRM_PLANE_TYPE_PRIMARY
:
1128 wm_state
->wm
[level
].primary
= wm
;
1130 case DRM_PLANE_TYPE_OVERLAY
:
1131 sprite
= plane
->plane
;
1132 wm_state
->wm
[level
].sprite
[sprite
] = wm
;
1137 wm_state
->num_levels
= level
;
1139 if (!wm_state
->cxsr
)
1142 /* maxfifo watermarks */
1143 switch (plane
->base
.type
) {
1145 case DRM_PLANE_TYPE_CURSOR
:
1146 for (level
= 0; level
< wm_state
->num_levels
; level
++)
1147 wm_state
->sr
[level
].cursor
=
1148 wm_state
->wm
[level
].cursor
;
1150 case DRM_PLANE_TYPE_PRIMARY
:
1151 for (level
= 0; level
< wm_state
->num_levels
; level
++)
1152 wm_state
->sr
[level
].plane
=
1153 min(wm_state
->sr
[level
].plane
,
1154 wm_state
->wm
[level
].primary
);
1156 case DRM_PLANE_TYPE_OVERLAY
:
1157 sprite
= plane
->plane
;
1158 for (level
= 0; level
< wm_state
->num_levels
; level
++)
1159 wm_state
->sr
[level
].plane
=
1160 min(wm_state
->sr
[level
].plane
,
1161 wm_state
->wm
[level
].sprite
[sprite
]);
1166 /* clear any (partially) filled invalid levels */
1167 for (level
= wm_state
->num_levels
; level
< to_i915(dev
)->wm
.max_level
+ 1; level
++) {
1168 memset(&wm_state
->wm
[level
], 0, sizeof(wm_state
->wm
[level
]));
1169 memset(&wm_state
->sr
[level
], 0, sizeof(wm_state
->sr
[level
]));
1172 vlv_invert_wms(crtc
);
1175 #define VLV_FIFO(plane, value) \
1176 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1178 static void vlv_pipe_set_fifo_size(struct intel_crtc
*crtc
)
1180 struct drm_device
*dev
= crtc
->base
.dev
;
1181 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1182 struct intel_plane
*plane
;
1183 int sprite0_start
= 0, sprite1_start
= 0, fifo_size
= 0;
1185 for_each_intel_plane_on_crtc(dev
, crtc
, plane
) {
1186 if (plane
->base
.type
== DRM_PLANE_TYPE_CURSOR
) {
1187 WARN_ON(plane
->wm
.fifo_size
!= 63);
1191 if (plane
->base
.type
== DRM_PLANE_TYPE_PRIMARY
)
1192 sprite0_start
= plane
->wm
.fifo_size
;
1193 else if (plane
->plane
== 0)
1194 sprite1_start
= sprite0_start
+ plane
->wm
.fifo_size
;
1196 fifo_size
= sprite1_start
+ plane
->wm
.fifo_size
;
1199 WARN_ON(fifo_size
!= 512 - 1);
1201 DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1202 pipe_name(crtc
->pipe
), sprite0_start
,
1203 sprite1_start
, fifo_size
);
1205 switch (crtc
->pipe
) {
1206 uint32_t dsparb
, dsparb2
, dsparb3
;
1208 dsparb
= I915_READ(DSPARB
);
1209 dsparb2
= I915_READ(DSPARB2
);
1211 dsparb
&= ~(VLV_FIFO(SPRITEA
, 0xff) |
1212 VLV_FIFO(SPRITEB
, 0xff));
1213 dsparb
|= (VLV_FIFO(SPRITEA
, sprite0_start
) |
1214 VLV_FIFO(SPRITEB
, sprite1_start
));
1216 dsparb2
&= ~(VLV_FIFO(SPRITEA_HI
, 0x1) |
1217 VLV_FIFO(SPRITEB_HI
, 0x1));
1218 dsparb2
|= (VLV_FIFO(SPRITEA_HI
, sprite0_start
>> 8) |
1219 VLV_FIFO(SPRITEB_HI
, sprite1_start
>> 8));
1221 I915_WRITE(DSPARB
, dsparb
);
1222 I915_WRITE(DSPARB2
, dsparb2
);
1225 dsparb
= I915_READ(DSPARB
);
1226 dsparb2
= I915_READ(DSPARB2
);
1228 dsparb
&= ~(VLV_FIFO(SPRITEC
, 0xff) |
1229 VLV_FIFO(SPRITED
, 0xff));
1230 dsparb
|= (VLV_FIFO(SPRITEC
, sprite0_start
) |
1231 VLV_FIFO(SPRITED
, sprite1_start
));
1233 dsparb2
&= ~(VLV_FIFO(SPRITEC_HI
, 0xff) |
1234 VLV_FIFO(SPRITED_HI
, 0xff));
1235 dsparb2
|= (VLV_FIFO(SPRITEC_HI
, sprite0_start
>> 8) |
1236 VLV_FIFO(SPRITED_HI
, sprite1_start
>> 8));
1238 I915_WRITE(DSPARB
, dsparb
);
1239 I915_WRITE(DSPARB2
, dsparb2
);
1242 dsparb3
= I915_READ(DSPARB3
);
1243 dsparb2
= I915_READ(DSPARB2
);
1245 dsparb3
&= ~(VLV_FIFO(SPRITEE
, 0xff) |
1246 VLV_FIFO(SPRITEF
, 0xff));
1247 dsparb3
|= (VLV_FIFO(SPRITEE
, sprite0_start
) |
1248 VLV_FIFO(SPRITEF
, sprite1_start
));
1250 dsparb2
&= ~(VLV_FIFO(SPRITEE_HI
, 0xff) |
1251 VLV_FIFO(SPRITEF_HI
, 0xff));
1252 dsparb2
|= (VLV_FIFO(SPRITEE_HI
, sprite0_start
>> 8) |
1253 VLV_FIFO(SPRITEF_HI
, sprite1_start
>> 8));
1255 I915_WRITE(DSPARB3
, dsparb3
);
1256 I915_WRITE(DSPARB2
, dsparb2
);
1265 static void vlv_merge_wm(struct drm_device
*dev
,
1266 struct vlv_wm_values
*wm
)
1268 struct intel_crtc
*crtc
;
1269 int num_active_crtcs
= 0;
1271 wm
->level
= to_i915(dev
)->wm
.max_level
;
1274 for_each_intel_crtc(dev
, crtc
) {
1275 const struct vlv_wm_state
*wm_state
= &crtc
->wm_state
;
1280 if (!wm_state
->cxsr
)
1284 wm
->level
= min_t(int, wm
->level
, wm_state
->num_levels
- 1);
1287 if (num_active_crtcs
!= 1)
1290 if (num_active_crtcs
> 1)
1291 wm
->level
= VLV_WM_LEVEL_PM2
;
1293 for_each_intel_crtc(dev
, crtc
) {
1294 struct vlv_wm_state
*wm_state
= &crtc
->wm_state
;
1295 enum pipe pipe
= crtc
->pipe
;
1300 wm
->pipe
[pipe
] = wm_state
->wm
[wm
->level
];
1302 wm
->sr
= wm_state
->sr
[wm
->level
];
1304 wm
->ddl
[pipe
].primary
= DDL_PRECISION_HIGH
| 2;
1305 wm
->ddl
[pipe
].sprite
[0] = DDL_PRECISION_HIGH
| 2;
1306 wm
->ddl
[pipe
].sprite
[1] = DDL_PRECISION_HIGH
| 2;
1307 wm
->ddl
[pipe
].cursor
= DDL_PRECISION_HIGH
| 2;
1311 static void vlv_update_wm(struct drm_crtc
*crtc
)
1313 struct drm_device
*dev
= crtc
->dev
;
1314 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1315 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1316 enum pipe pipe
= intel_crtc
->pipe
;
1317 struct vlv_wm_values wm
= {};
1319 vlv_compute_wm(intel_crtc
);
1320 vlv_merge_wm(dev
, &wm
);
1322 if (memcmp(&dev_priv
->wm
.vlv
, &wm
, sizeof(wm
)) == 0) {
1323 /* FIXME should be part of crtc atomic commit */
1324 vlv_pipe_set_fifo_size(intel_crtc
);
1328 if (wm
.level
< VLV_WM_LEVEL_DDR_DVFS
&&
1329 dev_priv
->wm
.vlv
.level
>= VLV_WM_LEVEL_DDR_DVFS
)
1330 chv_set_memory_dvfs(dev_priv
, false);
1332 if (wm
.level
< VLV_WM_LEVEL_PM5
&&
1333 dev_priv
->wm
.vlv
.level
>= VLV_WM_LEVEL_PM5
)
1334 chv_set_memory_pm5(dev_priv
, false);
1336 if (!wm
.cxsr
&& dev_priv
->wm
.vlv
.cxsr
)
1337 intel_set_memory_cxsr(dev_priv
, false);
1339 /* FIXME should be part of crtc atomic commit */
1340 vlv_pipe_set_fifo_size(intel_crtc
);
1342 vlv_write_wm_values(intel_crtc
, &wm
);
1344 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1345 "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1346 pipe_name(pipe
), wm
.pipe
[pipe
].primary
, wm
.pipe
[pipe
].cursor
,
1347 wm
.pipe
[pipe
].sprite
[0], wm
.pipe
[pipe
].sprite
[1],
1348 wm
.sr
.plane
, wm
.sr
.cursor
, wm
.level
, wm
.cxsr
);
1350 if (wm
.cxsr
&& !dev_priv
->wm
.vlv
.cxsr
)
1351 intel_set_memory_cxsr(dev_priv
, true);
1353 if (wm
.level
>= VLV_WM_LEVEL_PM5
&&
1354 dev_priv
->wm
.vlv
.level
< VLV_WM_LEVEL_PM5
)
1355 chv_set_memory_pm5(dev_priv
, true);
1357 if (wm
.level
>= VLV_WM_LEVEL_DDR_DVFS
&&
1358 dev_priv
->wm
.vlv
.level
< VLV_WM_LEVEL_DDR_DVFS
)
1359 chv_set_memory_dvfs(dev_priv
, true);
1361 dev_priv
->wm
.vlv
= wm
;
1364 #define single_plane_enabled(mask) is_power_of_2(mask)
1366 static void g4x_update_wm(struct drm_crtc
*crtc
)
1368 struct drm_device
*dev
= crtc
->dev
;
1369 static const int sr_latency_ns
= 12000;
1370 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1371 int planea_wm
, planeb_wm
, cursora_wm
, cursorb_wm
;
1372 int plane_sr
, cursor_sr
;
1373 unsigned int enabled
= 0;
1376 if (g4x_compute_wm0(dev
, PIPE_A
,
1377 &g4x_wm_info
, pessimal_latency_ns
,
1378 &g4x_cursor_wm_info
, pessimal_latency_ns
,
1379 &planea_wm
, &cursora_wm
))
1380 enabled
|= 1 << PIPE_A
;
1382 if (g4x_compute_wm0(dev
, PIPE_B
,
1383 &g4x_wm_info
, pessimal_latency_ns
,
1384 &g4x_cursor_wm_info
, pessimal_latency_ns
,
1385 &planeb_wm
, &cursorb_wm
))
1386 enabled
|= 1 << PIPE_B
;
1388 if (single_plane_enabled(enabled
) &&
1389 g4x_compute_srwm(dev
, ffs(enabled
) - 1,
1392 &g4x_cursor_wm_info
,
1393 &plane_sr
, &cursor_sr
)) {
1394 cxsr_enabled
= true;
1396 cxsr_enabled
= false;
1397 intel_set_memory_cxsr(dev_priv
, false);
1398 plane_sr
= cursor_sr
= 0;
1401 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1402 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1403 planea_wm
, cursora_wm
,
1404 planeb_wm
, cursorb_wm
,
1405 plane_sr
, cursor_sr
);
1408 FW_WM(plane_sr
, SR
) |
1409 FW_WM(cursorb_wm
, CURSORB
) |
1410 FW_WM(planeb_wm
, PLANEB
) |
1411 FW_WM(planea_wm
, PLANEA
));
1413 (I915_READ(DSPFW2
) & ~DSPFW_CURSORA_MASK
) |
1414 FW_WM(cursora_wm
, CURSORA
));
1415 /* HPLL off in SR has some issues on G4x... disable it */
1417 (I915_READ(DSPFW3
) & ~(DSPFW_HPLL_SR_EN
| DSPFW_CURSOR_SR_MASK
)) |
1418 FW_WM(cursor_sr
, CURSOR_SR
));
1421 intel_set_memory_cxsr(dev_priv
, true);
1424 static void i965_update_wm(struct drm_crtc
*unused_crtc
)
1426 struct drm_device
*dev
= unused_crtc
->dev
;
1427 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1428 struct drm_crtc
*crtc
;
1433 /* Calc sr entries for one plane configs */
1434 crtc
= single_enabled_crtc(dev
);
1436 /* self-refresh has much higher latency */
1437 static const int sr_latency_ns
= 12000;
1438 const struct drm_display_mode
*adjusted_mode
= &to_intel_crtc(crtc
)->config
->base
.adjusted_mode
;
1439 int clock
= adjusted_mode
->crtc_clock
;
1440 int htotal
= adjusted_mode
->crtc_htotal
;
1441 int hdisplay
= to_intel_crtc(crtc
)->config
->pipe_src_w
;
1442 int cpp
= drm_format_plane_cpp(crtc
->primary
->state
->fb
->pixel_format
, 0);
1443 unsigned long line_time_us
;
1446 line_time_us
= max(htotal
* 1000 / clock
, 1);
1448 /* Use ns/us then divide to preserve precision */
1449 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
1451 entries
= DIV_ROUND_UP(entries
, I915_FIFO_LINE_SIZE
);
1452 srwm
= I965_FIFO_SIZE
- entries
;
1456 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1459 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
1460 cpp
* crtc
->cursor
->state
->crtc_w
;
1461 entries
= DIV_ROUND_UP(entries
,
1462 i965_cursor_wm_info
.cacheline_size
);
1463 cursor_sr
= i965_cursor_wm_info
.fifo_size
-
1464 (entries
+ i965_cursor_wm_info
.guard_size
);
1466 if (cursor_sr
> i965_cursor_wm_info
.max_wm
)
1467 cursor_sr
= i965_cursor_wm_info
.max_wm
;
1469 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1470 "cursor %d\n", srwm
, cursor_sr
);
1472 cxsr_enabled
= true;
1474 cxsr_enabled
= false;
1475 /* Turn off self refresh if both pipes are enabled */
1476 intel_set_memory_cxsr(dev_priv
, false);
1479 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1482 /* 965 has limitations... */
1483 I915_WRITE(DSPFW1
, FW_WM(srwm
, SR
) |
1487 I915_WRITE(DSPFW2
, FW_WM(8, CURSORA
) |
1488 FW_WM(8, PLANEC_OLD
));
1489 /* update cursor SR watermark */
1490 I915_WRITE(DSPFW3
, FW_WM(cursor_sr
, CURSOR_SR
));
1493 intel_set_memory_cxsr(dev_priv
, true);
1498 static void i9xx_update_wm(struct drm_crtc
*unused_crtc
)
1500 struct drm_device
*dev
= unused_crtc
->dev
;
1501 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1502 const struct intel_watermark_params
*wm_info
;
1507 int planea_wm
, planeb_wm
;
1508 struct drm_crtc
*crtc
, *enabled
= NULL
;
1511 wm_info
= &i945_wm_info
;
1512 else if (!IS_GEN2(dev
))
1513 wm_info
= &i915_wm_info
;
1515 wm_info
= &i830_a_wm_info
;
1517 fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 0);
1518 crtc
= intel_get_crtc_for_plane(dev
, 0);
1519 if (intel_crtc_active(crtc
)) {
1520 const struct drm_display_mode
*adjusted_mode
;
1521 int cpp
= drm_format_plane_cpp(crtc
->primary
->state
->fb
->pixel_format
, 0);
1525 adjusted_mode
= &to_intel_crtc(crtc
)->config
->base
.adjusted_mode
;
1526 planea_wm
= intel_calculate_wm(adjusted_mode
->crtc_clock
,
1527 wm_info
, fifo_size
, cpp
,
1528 pessimal_latency_ns
);
1531 planea_wm
= fifo_size
- wm_info
->guard_size
;
1532 if (planea_wm
> (long)wm_info
->max_wm
)
1533 planea_wm
= wm_info
->max_wm
;
1537 wm_info
= &i830_bc_wm_info
;
1539 fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 1);
1540 crtc
= intel_get_crtc_for_plane(dev
, 1);
1541 if (intel_crtc_active(crtc
)) {
1542 const struct drm_display_mode
*adjusted_mode
;
1543 int cpp
= drm_format_plane_cpp(crtc
->primary
->state
->fb
->pixel_format
, 0);
1547 adjusted_mode
= &to_intel_crtc(crtc
)->config
->base
.adjusted_mode
;
1548 planeb_wm
= intel_calculate_wm(adjusted_mode
->crtc_clock
,
1549 wm_info
, fifo_size
, cpp
,
1550 pessimal_latency_ns
);
1551 if (enabled
== NULL
)
1556 planeb_wm
= fifo_size
- wm_info
->guard_size
;
1557 if (planeb_wm
> (long)wm_info
->max_wm
)
1558 planeb_wm
= wm_info
->max_wm
;
1561 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm
, planeb_wm
);
1563 if (IS_I915GM(dev
) && enabled
) {
1564 struct drm_i915_gem_object
*obj
;
1566 obj
= intel_fb_obj(enabled
->primary
->state
->fb
);
1568 /* self-refresh seems busted with untiled */
1569 if (obj
->tiling_mode
== I915_TILING_NONE
)
1574 * Overlay gets an aggressive default since video jitter is bad.
1578 /* Play safe and disable self-refresh before adjusting watermarks. */
1579 intel_set_memory_cxsr(dev_priv
, false);
1581 /* Calc sr entries for one plane configs */
1582 if (HAS_FW_BLC(dev
) && enabled
) {
1583 /* self-refresh has much higher latency */
1584 static const int sr_latency_ns
= 6000;
1585 const struct drm_display_mode
*adjusted_mode
= &to_intel_crtc(enabled
)->config
->base
.adjusted_mode
;
1586 int clock
= adjusted_mode
->crtc_clock
;
1587 int htotal
= adjusted_mode
->crtc_htotal
;
1588 int hdisplay
= to_intel_crtc(enabled
)->config
->pipe_src_w
;
1589 int cpp
= drm_format_plane_cpp(enabled
->primary
->state
->fb
->pixel_format
, 0);
1590 unsigned long line_time_us
;
1593 line_time_us
= max(htotal
* 1000 / clock
, 1);
1595 /* Use ns/us then divide to preserve precision */
1596 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
1598 entries
= DIV_ROUND_UP(entries
, wm_info
->cacheline_size
);
1599 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries
);
1600 srwm
= wm_info
->fifo_size
- entries
;
1604 if (IS_I945G(dev
) || IS_I945GM(dev
))
1605 I915_WRITE(FW_BLC_SELF
,
1606 FW_BLC_SELF_FIFO_MASK
| (srwm
& 0xff));
1607 else if (IS_I915GM(dev
))
1608 I915_WRITE(FW_BLC_SELF
, srwm
& 0x3f);
1611 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1612 planea_wm
, planeb_wm
, cwm
, srwm
);
1614 fwater_lo
= ((planeb_wm
& 0x3f) << 16) | (planea_wm
& 0x3f);
1615 fwater_hi
= (cwm
& 0x1f);
1617 /* Set request length to 8 cachelines per fetch */
1618 fwater_lo
= fwater_lo
| (1 << 24) | (1 << 8);
1619 fwater_hi
= fwater_hi
| (1 << 8);
1621 I915_WRITE(FW_BLC
, fwater_lo
);
1622 I915_WRITE(FW_BLC2
, fwater_hi
);
1625 intel_set_memory_cxsr(dev_priv
, true);
1628 static void i845_update_wm(struct drm_crtc
*unused_crtc
)
1630 struct drm_device
*dev
= unused_crtc
->dev
;
1631 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1632 struct drm_crtc
*crtc
;
1633 const struct drm_display_mode
*adjusted_mode
;
1637 crtc
= single_enabled_crtc(dev
);
1641 adjusted_mode
= &to_intel_crtc(crtc
)->config
->base
.adjusted_mode
;
1642 planea_wm
= intel_calculate_wm(adjusted_mode
->crtc_clock
,
1644 dev_priv
->display
.get_fifo_size(dev
, 0),
1645 4, pessimal_latency_ns
);
1646 fwater_lo
= I915_READ(FW_BLC
) & ~0xfff;
1647 fwater_lo
|= (3<<8) | planea_wm
;
1649 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm
);
1651 I915_WRITE(FW_BLC
, fwater_lo
);
1654 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state
*pipe_config
)
1656 uint32_t pixel_rate
;
1658 pixel_rate
= pipe_config
->base
.adjusted_mode
.crtc_clock
;
1660 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1661 * adjust the pixel_rate here. */
1663 if (pipe_config
->pch_pfit
.enabled
) {
1664 uint64_t pipe_w
, pipe_h
, pfit_w
, pfit_h
;
1665 uint32_t pfit_size
= pipe_config
->pch_pfit
.size
;
1667 pipe_w
= pipe_config
->pipe_src_w
;
1668 pipe_h
= pipe_config
->pipe_src_h
;
1670 pfit_w
= (pfit_size
>> 16) & 0xFFFF;
1671 pfit_h
= pfit_size
& 0xFFFF;
1672 if (pipe_w
< pfit_w
)
1674 if (pipe_h
< pfit_h
)
1677 if (WARN_ON(!pfit_w
|| !pfit_h
))
1680 pixel_rate
= div_u64((uint64_t) pixel_rate
* pipe_w
* pipe_h
,
1687 /* latency must be in 0.1us units. */
1688 static uint32_t ilk_wm_method1(uint32_t pixel_rate
, uint8_t cpp
, uint32_t latency
)
1692 if (WARN(latency
== 0, "Latency value missing\n"))
1695 ret
= (uint64_t) pixel_rate
* cpp
* latency
;
1696 ret
= DIV_ROUND_UP_ULL(ret
, 64 * 10000) + 2;
1701 /* latency must be in 0.1us units. */
1702 static uint32_t ilk_wm_method2(uint32_t pixel_rate
, uint32_t pipe_htotal
,
1703 uint32_t horiz_pixels
, uint8_t cpp
,
1708 if (WARN(latency
== 0, "Latency value missing\n"))
1710 if (WARN_ON(!pipe_htotal
))
1713 ret
= (latency
* pixel_rate
) / (pipe_htotal
* 10000);
1714 ret
= (ret
+ 1) * horiz_pixels
* cpp
;
1715 ret
= DIV_ROUND_UP(ret
, 64) + 2;
1719 static uint32_t ilk_wm_fbc(uint32_t pri_val
, uint32_t horiz_pixels
,
1723 * Neither of these should be possible since this function shouldn't be
1724 * called if the CRTC is off or the plane is invisible. But let's be
1725 * extra paranoid to avoid a potential divide-by-zero if we screw up
1726 * elsewhere in the driver.
1730 if (WARN_ON(!horiz_pixels
))
1733 return DIV_ROUND_UP(pri_val
* 64, horiz_pixels
* cpp
) + 2;
1736 struct ilk_wm_maximums
{
1744 * For both WM_PIPE and WM_LP.
1745 * mem_value must be in 0.1us units.
1747 static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state
*cstate
,
1748 const struct intel_plane_state
*pstate
,
1752 int cpp
= pstate
->base
.fb
?
1753 drm_format_plane_cpp(pstate
->base
.fb
->pixel_format
, 0) : 0;
1754 uint32_t method1
, method2
;
1756 if (!cstate
->base
.active
|| !pstate
->visible
)
1759 method1
= ilk_wm_method1(ilk_pipe_pixel_rate(cstate
), cpp
, mem_value
);
1764 method2
= ilk_wm_method2(ilk_pipe_pixel_rate(cstate
),
1765 cstate
->base
.adjusted_mode
.crtc_htotal
,
1766 drm_rect_width(&pstate
->dst
),
1769 return min(method1
, method2
);
1773 * For both WM_PIPE and WM_LP.
1774 * mem_value must be in 0.1us units.
1776 static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state
*cstate
,
1777 const struct intel_plane_state
*pstate
,
1780 int cpp
= pstate
->base
.fb
?
1781 drm_format_plane_cpp(pstate
->base
.fb
->pixel_format
, 0) : 0;
1782 uint32_t method1
, method2
;
1784 if (!cstate
->base
.active
|| !pstate
->visible
)
1787 method1
= ilk_wm_method1(ilk_pipe_pixel_rate(cstate
), cpp
, mem_value
);
1788 method2
= ilk_wm_method2(ilk_pipe_pixel_rate(cstate
),
1789 cstate
->base
.adjusted_mode
.crtc_htotal
,
1790 drm_rect_width(&pstate
->dst
),
1792 return min(method1
, method2
);
1796 * For both WM_PIPE and WM_LP.
1797 * mem_value must be in 0.1us units.
1799 static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state
*cstate
,
1800 const struct intel_plane_state
*pstate
,
1804 * We treat the cursor plane as always-on for the purposes of watermark
1805 * calculation. Until we have two-stage watermark programming merged,
1806 * this is necessary to avoid flickering.
1809 int width
= pstate
->visible
? pstate
->base
.crtc_w
: 64;
1811 if (!cstate
->base
.active
)
1814 return ilk_wm_method2(ilk_pipe_pixel_rate(cstate
),
1815 cstate
->base
.adjusted_mode
.crtc_htotal
,
1816 width
, cpp
, mem_value
);
1819 /* Only for WM_LP. */
1820 static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state
*cstate
,
1821 const struct intel_plane_state
*pstate
,
1824 int cpp
= pstate
->base
.fb
?
1825 drm_format_plane_cpp(pstate
->base
.fb
->pixel_format
, 0) : 0;
1827 if (!cstate
->base
.active
|| !pstate
->visible
)
1830 return ilk_wm_fbc(pri_val
, drm_rect_width(&pstate
->dst
), cpp
);
1833 static unsigned int ilk_display_fifo_size(const struct drm_device
*dev
)
1835 if (INTEL_INFO(dev
)->gen
>= 8)
1837 else if (INTEL_INFO(dev
)->gen
>= 7)
1843 static unsigned int ilk_plane_wm_reg_max(const struct drm_device
*dev
,
1844 int level
, bool is_sprite
)
1846 if (INTEL_INFO(dev
)->gen
>= 8)
1847 /* BDW primary/sprite plane watermarks */
1848 return level
== 0 ? 255 : 2047;
1849 else if (INTEL_INFO(dev
)->gen
>= 7)
1850 /* IVB/HSW primary/sprite plane watermarks */
1851 return level
== 0 ? 127 : 1023;
1852 else if (!is_sprite
)
1853 /* ILK/SNB primary plane watermarks */
1854 return level
== 0 ? 127 : 511;
1856 /* ILK/SNB sprite plane watermarks */
1857 return level
== 0 ? 63 : 255;
1860 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device
*dev
,
1863 if (INTEL_INFO(dev
)->gen
>= 7)
1864 return level
== 0 ? 63 : 255;
1866 return level
== 0 ? 31 : 63;
1869 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device
*dev
)
1871 if (INTEL_INFO(dev
)->gen
>= 8)
1877 /* Calculate the maximum primary/sprite plane watermark */
1878 static unsigned int ilk_plane_wm_max(const struct drm_device
*dev
,
1880 const struct intel_wm_config
*config
,
1881 enum intel_ddb_partitioning ddb_partitioning
,
1884 unsigned int fifo_size
= ilk_display_fifo_size(dev
);
1886 /* if sprites aren't enabled, sprites get nothing */
1887 if (is_sprite
&& !config
->sprites_enabled
)
1890 /* HSW allows LP1+ watermarks even with multiple pipes */
1891 if (level
== 0 || config
->num_pipes_active
> 1) {
1892 fifo_size
/= INTEL_INFO(dev
)->num_pipes
;
1895 * For some reason the non self refresh
1896 * FIFO size is only half of the self
1897 * refresh FIFO size on ILK/SNB.
1899 if (INTEL_INFO(dev
)->gen
<= 6)
1903 if (config
->sprites_enabled
) {
1904 /* level 0 is always calculated with 1:1 split */
1905 if (level
> 0 && ddb_partitioning
== INTEL_DDB_PART_5_6
) {
1914 /* clamp to max that the registers can hold */
1915 return min(fifo_size
, ilk_plane_wm_reg_max(dev
, level
, is_sprite
));
1918 /* Calculate the maximum cursor plane watermark */
1919 static unsigned int ilk_cursor_wm_max(const struct drm_device
*dev
,
1921 const struct intel_wm_config
*config
)
1923 /* HSW LP1+ watermarks w/ multiple pipes */
1924 if (level
> 0 && config
->num_pipes_active
> 1)
1927 /* otherwise just report max that registers can hold */
1928 return ilk_cursor_wm_reg_max(dev
, level
);
1931 static void ilk_compute_wm_maximums(const struct drm_device
*dev
,
1933 const struct intel_wm_config
*config
,
1934 enum intel_ddb_partitioning ddb_partitioning
,
1935 struct ilk_wm_maximums
*max
)
1937 max
->pri
= ilk_plane_wm_max(dev
, level
, config
, ddb_partitioning
, false);
1938 max
->spr
= ilk_plane_wm_max(dev
, level
, config
, ddb_partitioning
, true);
1939 max
->cur
= ilk_cursor_wm_max(dev
, level
, config
);
1940 max
->fbc
= ilk_fbc_wm_reg_max(dev
);
1943 static void ilk_compute_wm_reg_maximums(struct drm_device
*dev
,
1945 struct ilk_wm_maximums
*max
)
1947 max
->pri
= ilk_plane_wm_reg_max(dev
, level
, false);
1948 max
->spr
= ilk_plane_wm_reg_max(dev
, level
, true);
1949 max
->cur
= ilk_cursor_wm_reg_max(dev
, level
);
1950 max
->fbc
= ilk_fbc_wm_reg_max(dev
);
1953 static bool ilk_validate_wm_level(int level
,
1954 const struct ilk_wm_maximums
*max
,
1955 struct intel_wm_level
*result
)
1959 /* already determined to be invalid? */
1960 if (!result
->enable
)
1963 result
->enable
= result
->pri_val
<= max
->pri
&&
1964 result
->spr_val
<= max
->spr
&&
1965 result
->cur_val
<= max
->cur
;
1967 ret
= result
->enable
;
1970 * HACK until we can pre-compute everything,
1971 * and thus fail gracefully if LP0 watermarks
1974 if (level
== 0 && !result
->enable
) {
1975 if (result
->pri_val
> max
->pri
)
1976 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1977 level
, result
->pri_val
, max
->pri
);
1978 if (result
->spr_val
> max
->spr
)
1979 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1980 level
, result
->spr_val
, max
->spr
);
1981 if (result
->cur_val
> max
->cur
)
1982 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1983 level
, result
->cur_val
, max
->cur
);
1985 result
->pri_val
= min_t(uint32_t, result
->pri_val
, max
->pri
);
1986 result
->spr_val
= min_t(uint32_t, result
->spr_val
, max
->spr
);
1987 result
->cur_val
= min_t(uint32_t, result
->cur_val
, max
->cur
);
1988 result
->enable
= true;
1994 static void ilk_compute_wm_level(const struct drm_i915_private
*dev_priv
,
1995 const struct intel_crtc
*intel_crtc
,
1997 struct intel_crtc_state
*cstate
,
1998 struct intel_plane_state
*pristate
,
1999 struct intel_plane_state
*sprstate
,
2000 struct intel_plane_state
*curstate
,
2001 struct intel_wm_level
*result
)
2003 uint16_t pri_latency
= dev_priv
->wm
.pri_latency
[level
];
2004 uint16_t spr_latency
= dev_priv
->wm
.spr_latency
[level
];
2005 uint16_t cur_latency
= dev_priv
->wm
.cur_latency
[level
];
2007 /* WM1+ latency values stored in 0.5us units */
2015 result
->pri_val
= ilk_compute_pri_wm(cstate
, pristate
,
2016 pri_latency
, level
);
2017 result
->fbc_val
= ilk_compute_fbc_wm(cstate
, pristate
, result
->pri_val
);
2021 result
->spr_val
= ilk_compute_spr_wm(cstate
, sprstate
, spr_latency
);
2024 result
->cur_val
= ilk_compute_cur_wm(cstate
, curstate
, cur_latency
);
2026 result
->enable
= true;
2030 hsw_compute_linetime_wm(const struct intel_crtc_state
*cstate
)
2032 const struct intel_atomic_state
*intel_state
=
2033 to_intel_atomic_state(cstate
->base
.state
);
2034 const struct drm_display_mode
*adjusted_mode
=
2035 &cstate
->base
.adjusted_mode
;
2036 u32 linetime
, ips_linetime
;
2038 if (!cstate
->base
.active
)
2040 if (WARN_ON(adjusted_mode
->crtc_clock
== 0))
2042 if (WARN_ON(intel_state
->cdclk
== 0))
2045 /* The WM are computed with base on how long it takes to fill a single
2046 * row at the given clock rate, multiplied by 8.
2048 linetime
= DIV_ROUND_CLOSEST(adjusted_mode
->crtc_htotal
* 1000 * 8,
2049 adjusted_mode
->crtc_clock
);
2050 ips_linetime
= DIV_ROUND_CLOSEST(adjusted_mode
->crtc_htotal
* 1000 * 8,
2051 intel_state
->cdclk
);
2053 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime
) |
2054 PIPE_WM_LINETIME_TIME(linetime
);
2057 static void intel_read_wm_latency(struct drm_device
*dev
, uint16_t wm
[8])
2059 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2064 int level
, max_level
= ilk_wm_max_level(dev
);
2066 /* read the first set of memory latencies[0:3] */
2067 val
= 0; /* data0 to be programmed to 0 for first set */
2068 mutex_lock(&dev_priv
->rps
.hw_lock
);
2069 ret
= sandybridge_pcode_read(dev_priv
,
2070 GEN9_PCODE_READ_MEM_LATENCY
,
2072 mutex_unlock(&dev_priv
->rps
.hw_lock
);
2075 DRM_ERROR("SKL Mailbox read error = %d\n", ret
);
2079 wm
[0] = val
& GEN9_MEM_LATENCY_LEVEL_MASK
;
2080 wm
[1] = (val
>> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT
) &
2081 GEN9_MEM_LATENCY_LEVEL_MASK
;
2082 wm
[2] = (val
>> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT
) &
2083 GEN9_MEM_LATENCY_LEVEL_MASK
;
2084 wm
[3] = (val
>> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT
) &
2085 GEN9_MEM_LATENCY_LEVEL_MASK
;
2087 /* read the second set of memory latencies[4:7] */
2088 val
= 1; /* data0 to be programmed to 1 for second set */
2089 mutex_lock(&dev_priv
->rps
.hw_lock
);
2090 ret
= sandybridge_pcode_read(dev_priv
,
2091 GEN9_PCODE_READ_MEM_LATENCY
,
2093 mutex_unlock(&dev_priv
->rps
.hw_lock
);
2095 DRM_ERROR("SKL Mailbox read error = %d\n", ret
);
2099 wm
[4] = val
& GEN9_MEM_LATENCY_LEVEL_MASK
;
2100 wm
[5] = (val
>> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT
) &
2101 GEN9_MEM_LATENCY_LEVEL_MASK
;
2102 wm
[6] = (val
>> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT
) &
2103 GEN9_MEM_LATENCY_LEVEL_MASK
;
2104 wm
[7] = (val
>> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT
) &
2105 GEN9_MEM_LATENCY_LEVEL_MASK
;
2108 * WaWmMemoryReadLatency:skl
2110 * punit doesn't take into account the read latency so we need
2111 * to add 2us to the various latency levels we retrieve from
2113 * - W0 is a bit special in that it's the only level that
2114 * can't be disabled if we want to have display working, so
2115 * we always add 2us there.
2116 * - For levels >=1, punit returns 0us latency when they are
2117 * disabled, so we respect that and don't add 2us then
2119 * Additionally, if a level n (n > 1) has a 0us latency, all
2120 * levels m (m >= n) need to be disabled. We make sure to
2121 * sanitize the values out of the punit to satisfy this
2125 for (level
= 1; level
<= max_level
; level
++)
2129 for (i
= level
+ 1; i
<= max_level
; i
++)
2134 } else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2135 uint64_t sskpd
= I915_READ64(MCH_SSKPD
);
2137 wm
[0] = (sskpd
>> 56) & 0xFF;
2139 wm
[0] = sskpd
& 0xF;
2140 wm
[1] = (sskpd
>> 4) & 0xFF;
2141 wm
[2] = (sskpd
>> 12) & 0xFF;
2142 wm
[3] = (sskpd
>> 20) & 0x1FF;
2143 wm
[4] = (sskpd
>> 32) & 0x1FF;
2144 } else if (INTEL_INFO(dev
)->gen
>= 6) {
2145 uint32_t sskpd
= I915_READ(MCH_SSKPD
);
2147 wm
[0] = (sskpd
>> SSKPD_WM0_SHIFT
) & SSKPD_WM_MASK
;
2148 wm
[1] = (sskpd
>> SSKPD_WM1_SHIFT
) & SSKPD_WM_MASK
;
2149 wm
[2] = (sskpd
>> SSKPD_WM2_SHIFT
) & SSKPD_WM_MASK
;
2150 wm
[3] = (sskpd
>> SSKPD_WM3_SHIFT
) & SSKPD_WM_MASK
;
2151 } else if (INTEL_INFO(dev
)->gen
>= 5) {
2152 uint32_t mltr
= I915_READ(MLTR_ILK
);
2154 /* ILK primary LP0 latency is 700 ns */
2156 wm
[1] = (mltr
>> MLTR_WM1_SHIFT
) & ILK_SRLT_MASK
;
2157 wm
[2] = (mltr
>> MLTR_WM2_SHIFT
) & ILK_SRLT_MASK
;
2161 static void intel_fixup_spr_wm_latency(struct drm_device
*dev
, uint16_t wm
[5])
2163 /* ILK sprite LP0 latency is 1300 ns */
2168 static void intel_fixup_cur_wm_latency(struct drm_device
*dev
, uint16_t wm
[5])
2170 /* ILK cursor LP0 latency is 1300 ns */
2174 /* WaDoubleCursorLP3Latency:ivb */
2175 if (IS_IVYBRIDGE(dev
))
2179 int ilk_wm_max_level(const struct drm_device
*dev
)
2181 /* how many WM levels are we expecting */
2182 if (INTEL_INFO(dev
)->gen
>= 9)
2184 else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2186 else if (INTEL_INFO(dev
)->gen
>= 6)
2192 static void intel_print_wm_latency(struct drm_device
*dev
,
2194 const uint16_t wm
[8])
2196 int level
, max_level
= ilk_wm_max_level(dev
);
2198 for (level
= 0; level
<= max_level
; level
++) {
2199 unsigned int latency
= wm
[level
];
2202 DRM_ERROR("%s WM%d latency not provided\n",
2208 * - latencies are in us on gen9.
2209 * - before then, WM1+ latency values are in 0.5us units
2216 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2217 name
, level
, wm
[level
],
2218 latency
/ 10, latency
% 10);
2222 static bool ilk_increase_wm_latency(struct drm_i915_private
*dev_priv
,
2223 uint16_t wm
[5], uint16_t min
)
2225 int level
, max_level
= ilk_wm_max_level(dev_priv
->dev
);
2230 wm
[0] = max(wm
[0], min
);
2231 for (level
= 1; level
<= max_level
; level
++)
2232 wm
[level
] = max_t(uint16_t, wm
[level
], DIV_ROUND_UP(min
, 5));
2237 static void snb_wm_latency_quirk(struct drm_device
*dev
)
2239 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2243 * The BIOS provided WM memory latency values are often
2244 * inadequate for high resolution displays. Adjust them.
2246 changed
= ilk_increase_wm_latency(dev_priv
, dev_priv
->wm
.pri_latency
, 12) |
2247 ilk_increase_wm_latency(dev_priv
, dev_priv
->wm
.spr_latency
, 12) |
2248 ilk_increase_wm_latency(dev_priv
, dev_priv
->wm
.cur_latency
, 12);
2253 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2254 intel_print_wm_latency(dev
, "Primary", dev_priv
->wm
.pri_latency
);
2255 intel_print_wm_latency(dev
, "Sprite", dev_priv
->wm
.spr_latency
);
2256 intel_print_wm_latency(dev
, "Cursor", dev_priv
->wm
.cur_latency
);
2259 static void ilk_setup_wm_latency(struct drm_device
*dev
)
2261 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2263 intel_read_wm_latency(dev
, dev_priv
->wm
.pri_latency
);
2265 memcpy(dev_priv
->wm
.spr_latency
, dev_priv
->wm
.pri_latency
,
2266 sizeof(dev_priv
->wm
.pri_latency
));
2267 memcpy(dev_priv
->wm
.cur_latency
, dev_priv
->wm
.pri_latency
,
2268 sizeof(dev_priv
->wm
.pri_latency
));
2270 intel_fixup_spr_wm_latency(dev
, dev_priv
->wm
.spr_latency
);
2271 intel_fixup_cur_wm_latency(dev
, dev_priv
->wm
.cur_latency
);
2273 intel_print_wm_latency(dev
, "Primary", dev_priv
->wm
.pri_latency
);
2274 intel_print_wm_latency(dev
, "Sprite", dev_priv
->wm
.spr_latency
);
2275 intel_print_wm_latency(dev
, "Cursor", dev_priv
->wm
.cur_latency
);
2278 snb_wm_latency_quirk(dev
);
2281 static void skl_setup_wm_latency(struct drm_device
*dev
)
2283 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2285 intel_read_wm_latency(dev
, dev_priv
->wm
.skl_latency
);
2286 intel_print_wm_latency(dev
, "Gen9 Plane", dev_priv
->wm
.skl_latency
);
2289 static bool ilk_validate_pipe_wm(struct drm_device
*dev
,
2290 struct intel_pipe_wm
*pipe_wm
)
2292 /* LP0 watermark maximums depend on this pipe alone */
2293 const struct intel_wm_config config
= {
2294 .num_pipes_active
= 1,
2295 .sprites_enabled
= pipe_wm
->sprites_enabled
,
2296 .sprites_scaled
= pipe_wm
->sprites_scaled
,
2298 struct ilk_wm_maximums max
;
2300 /* LP0 watermarks always use 1/2 DDB partitioning */
2301 ilk_compute_wm_maximums(dev
, 0, &config
, INTEL_DDB_PART_1_2
, &max
);
2303 /* At least LP0 must be valid */
2304 if (!ilk_validate_wm_level(0, &max
, &pipe_wm
->wm
[0])) {
2305 DRM_DEBUG_KMS("LP0 watermark invalid\n");
2312 /* Compute new watermarks for the pipe */
2313 static int ilk_compute_pipe_wm(struct intel_crtc_state
*cstate
)
2315 struct drm_atomic_state
*state
= cstate
->base
.state
;
2316 struct intel_crtc
*intel_crtc
= to_intel_crtc(cstate
->base
.crtc
);
2317 struct intel_pipe_wm
*pipe_wm
;
2318 struct drm_device
*dev
= state
->dev
;
2319 const struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2320 struct intel_plane
*intel_plane
;
2321 struct intel_plane_state
*pristate
= NULL
;
2322 struct intel_plane_state
*sprstate
= NULL
;
2323 struct intel_plane_state
*curstate
= NULL
;
2324 int level
, max_level
= ilk_wm_max_level(dev
), usable_level
;
2325 struct ilk_wm_maximums max
;
2327 pipe_wm
= &cstate
->wm
.ilk
.optimal
;
2329 for_each_intel_plane_on_crtc(dev
, intel_crtc
, intel_plane
) {
2330 struct intel_plane_state
*ps
;
2332 ps
= intel_atomic_get_existing_plane_state(state
,
2337 if (intel_plane
->base
.type
== DRM_PLANE_TYPE_PRIMARY
)
2339 else if (intel_plane
->base
.type
== DRM_PLANE_TYPE_OVERLAY
)
2341 else if (intel_plane
->base
.type
== DRM_PLANE_TYPE_CURSOR
)
2345 pipe_wm
->pipe_enabled
= cstate
->base
.active
;
2347 pipe_wm
->sprites_enabled
= sprstate
->visible
;
2348 pipe_wm
->sprites_scaled
= sprstate
->visible
&&
2349 (drm_rect_width(&sprstate
->dst
) != drm_rect_width(&sprstate
->src
) >> 16 ||
2350 drm_rect_height(&sprstate
->dst
) != drm_rect_height(&sprstate
->src
) >> 16);
2353 usable_level
= max_level
;
2355 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2356 if (INTEL_INFO(dev
)->gen
<= 6 && pipe_wm
->sprites_enabled
)
2359 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2360 if (pipe_wm
->sprites_scaled
)
2363 ilk_compute_wm_level(dev_priv
, intel_crtc
, 0, cstate
,
2364 pristate
, sprstate
, curstate
, &pipe_wm
->raw_wm
[0]);
2366 memset(&pipe_wm
->wm
, 0, sizeof(pipe_wm
->wm
));
2367 pipe_wm
->wm
[0] = pipe_wm
->raw_wm
[0];
2369 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2370 pipe_wm
->linetime
= hsw_compute_linetime_wm(cstate
);
2372 if (!ilk_validate_pipe_wm(dev
, pipe_wm
))
2375 ilk_compute_wm_reg_maximums(dev
, 1, &max
);
2377 for (level
= 1; level
<= max_level
; level
++) {
2378 struct intel_wm_level
*wm
= &pipe_wm
->raw_wm
[level
];
2380 ilk_compute_wm_level(dev_priv
, intel_crtc
, level
, cstate
,
2381 pristate
, sprstate
, curstate
, wm
);
2384 * Disable any watermark level that exceeds the
2385 * register maximums since such watermarks are
2388 if (level
> usable_level
)
2391 if (ilk_validate_wm_level(level
, &max
, wm
))
2392 pipe_wm
->wm
[level
] = *wm
;
2394 usable_level
= level
;
2401 * Build a set of 'intermediate' watermark values that satisfy both the old
2402 * state and the new state. These can be programmed to the hardware
2405 static int ilk_compute_intermediate_wm(struct drm_device
*dev
,
2406 struct intel_crtc
*intel_crtc
,
2407 struct intel_crtc_state
*newstate
)
2409 struct intel_pipe_wm
*a
= &newstate
->wm
.ilk
.intermediate
;
2410 struct intel_pipe_wm
*b
= &intel_crtc
->wm
.active
.ilk
;
2411 int level
, max_level
= ilk_wm_max_level(dev
);
2414 * Start with the final, target watermarks, then combine with the
2415 * currently active watermarks to get values that are safe both before
2416 * and after the vblank.
2418 *a
= newstate
->wm
.ilk
.optimal
;
2419 a
->pipe_enabled
|= b
->pipe_enabled
;
2420 a
->sprites_enabled
|= b
->sprites_enabled
;
2421 a
->sprites_scaled
|= b
->sprites_scaled
;
2423 for (level
= 0; level
<= max_level
; level
++) {
2424 struct intel_wm_level
*a_wm
= &a
->wm
[level
];
2425 const struct intel_wm_level
*b_wm
= &b
->wm
[level
];
2427 a_wm
->enable
&= b_wm
->enable
;
2428 a_wm
->pri_val
= max(a_wm
->pri_val
, b_wm
->pri_val
);
2429 a_wm
->spr_val
= max(a_wm
->spr_val
, b_wm
->spr_val
);
2430 a_wm
->cur_val
= max(a_wm
->cur_val
, b_wm
->cur_val
);
2431 a_wm
->fbc_val
= max(a_wm
->fbc_val
, b_wm
->fbc_val
);
2435 * We need to make sure that these merged watermark values are
2436 * actually a valid configuration themselves. If they're not,
2437 * there's no safe way to transition from the old state to
2438 * the new state, so we need to fail the atomic transaction.
2440 if (!ilk_validate_pipe_wm(dev
, a
))
2444 * If our intermediate WM are identical to the final WM, then we can
2445 * omit the post-vblank programming; only update if it's different.
2447 if (memcmp(a
, &newstate
->wm
.ilk
.optimal
, sizeof(*a
)) == 0)
2448 newstate
->wm
.need_postvbl_update
= false;
2454 * Merge the watermarks from all active pipes for a specific level.
2456 static void ilk_merge_wm_level(struct drm_device
*dev
,
2458 struct intel_wm_level
*ret_wm
)
2460 const struct intel_crtc
*intel_crtc
;
2462 ret_wm
->enable
= true;
2464 for_each_intel_crtc(dev
, intel_crtc
) {
2465 const struct intel_pipe_wm
*active
= &intel_crtc
->wm
.active
.ilk
;
2466 const struct intel_wm_level
*wm
= &active
->wm
[level
];
2468 if (!active
->pipe_enabled
)
2472 * The watermark values may have been used in the past,
2473 * so we must maintain them in the registers for some
2474 * time even if the level is now disabled.
2477 ret_wm
->enable
= false;
2479 ret_wm
->pri_val
= max(ret_wm
->pri_val
, wm
->pri_val
);
2480 ret_wm
->spr_val
= max(ret_wm
->spr_val
, wm
->spr_val
);
2481 ret_wm
->cur_val
= max(ret_wm
->cur_val
, wm
->cur_val
);
2482 ret_wm
->fbc_val
= max(ret_wm
->fbc_val
, wm
->fbc_val
);
2487 * Merge all low power watermarks for all active pipes.
2489 static void ilk_wm_merge(struct drm_device
*dev
,
2490 const struct intel_wm_config
*config
,
2491 const struct ilk_wm_maximums
*max
,
2492 struct intel_pipe_wm
*merged
)
2494 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2495 int level
, max_level
= ilk_wm_max_level(dev
);
2496 int last_enabled_level
= max_level
;
2498 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2499 if ((INTEL_INFO(dev
)->gen
<= 6 || IS_IVYBRIDGE(dev
)) &&
2500 config
->num_pipes_active
> 1)
2501 last_enabled_level
= 0;
2503 /* ILK: FBC WM must be disabled always */
2504 merged
->fbc_wm_enabled
= INTEL_INFO(dev
)->gen
>= 6;
2506 /* merge each WM1+ level */
2507 for (level
= 1; level
<= max_level
; level
++) {
2508 struct intel_wm_level
*wm
= &merged
->wm
[level
];
2510 ilk_merge_wm_level(dev
, level
, wm
);
2512 if (level
> last_enabled_level
)
2514 else if (!ilk_validate_wm_level(level
, max
, wm
))
2515 /* make sure all following levels get disabled */
2516 last_enabled_level
= level
- 1;
2519 * The spec says it is preferred to disable
2520 * FBC WMs instead of disabling a WM level.
2522 if (wm
->fbc_val
> max
->fbc
) {
2524 merged
->fbc_wm_enabled
= false;
2529 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2531 * FIXME this is racy. FBC might get enabled later.
2532 * What we should check here is whether FBC can be
2533 * enabled sometime later.
2535 if (IS_GEN5(dev
) && !merged
->fbc_wm_enabled
&&
2536 intel_fbc_is_active(dev_priv
)) {
2537 for (level
= 2; level
<= max_level
; level
++) {
2538 struct intel_wm_level
*wm
= &merged
->wm
[level
];
2545 static int ilk_wm_lp_to_level(int wm_lp
, const struct intel_pipe_wm
*pipe_wm
)
2547 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2548 return wm_lp
+ (wm_lp
>= 2 && pipe_wm
->wm
[4].enable
);
2551 /* The value we need to program into the WM_LPx latency field */
2552 static unsigned int ilk_wm_lp_latency(struct drm_device
*dev
, int level
)
2554 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2556 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2559 return dev_priv
->wm
.pri_latency
[level
];
2562 static void ilk_compute_wm_results(struct drm_device
*dev
,
2563 const struct intel_pipe_wm
*merged
,
2564 enum intel_ddb_partitioning partitioning
,
2565 struct ilk_wm_values
*results
)
2567 struct intel_crtc
*intel_crtc
;
2570 results
->enable_fbc_wm
= merged
->fbc_wm_enabled
;
2571 results
->partitioning
= partitioning
;
2573 /* LP1+ register values */
2574 for (wm_lp
= 1; wm_lp
<= 3; wm_lp
++) {
2575 const struct intel_wm_level
*r
;
2577 level
= ilk_wm_lp_to_level(wm_lp
, merged
);
2579 r
= &merged
->wm
[level
];
2582 * Maintain the watermark values even if the level is
2583 * disabled. Doing otherwise could cause underruns.
2585 results
->wm_lp
[wm_lp
- 1] =
2586 (ilk_wm_lp_latency(dev
, level
) << WM1_LP_LATENCY_SHIFT
) |
2587 (r
->pri_val
<< WM1_LP_SR_SHIFT
) |
2591 results
->wm_lp
[wm_lp
- 1] |= WM1_LP_SR_EN
;
2593 if (INTEL_INFO(dev
)->gen
>= 8)
2594 results
->wm_lp
[wm_lp
- 1] |=
2595 r
->fbc_val
<< WM1_LP_FBC_SHIFT_BDW
;
2597 results
->wm_lp
[wm_lp
- 1] |=
2598 r
->fbc_val
<< WM1_LP_FBC_SHIFT
;
2601 * Always set WM1S_LP_EN when spr_val != 0, even if the
2602 * level is disabled. Doing otherwise could cause underruns.
2604 if (INTEL_INFO(dev
)->gen
<= 6 && r
->spr_val
) {
2605 WARN_ON(wm_lp
!= 1);
2606 results
->wm_lp_spr
[wm_lp
- 1] = WM1S_LP_EN
| r
->spr_val
;
2608 results
->wm_lp_spr
[wm_lp
- 1] = r
->spr_val
;
2611 /* LP0 register values */
2612 for_each_intel_crtc(dev
, intel_crtc
) {
2613 enum pipe pipe
= intel_crtc
->pipe
;
2614 const struct intel_wm_level
*r
=
2615 &intel_crtc
->wm
.active
.ilk
.wm
[0];
2617 if (WARN_ON(!r
->enable
))
2620 results
->wm_linetime
[pipe
] = intel_crtc
->wm
.active
.ilk
.linetime
;
2622 results
->wm_pipe
[pipe
] =
2623 (r
->pri_val
<< WM0_PIPE_PLANE_SHIFT
) |
2624 (r
->spr_val
<< WM0_PIPE_SPRITE_SHIFT
) |
2629 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2630 * case both are at the same level. Prefer r1 in case they're the same. */
2631 static struct intel_pipe_wm
*ilk_find_best_result(struct drm_device
*dev
,
2632 struct intel_pipe_wm
*r1
,
2633 struct intel_pipe_wm
*r2
)
2635 int level
, max_level
= ilk_wm_max_level(dev
);
2636 int level1
= 0, level2
= 0;
2638 for (level
= 1; level
<= max_level
; level
++) {
2639 if (r1
->wm
[level
].enable
)
2641 if (r2
->wm
[level
].enable
)
2645 if (level1
== level2
) {
2646 if (r2
->fbc_wm_enabled
&& !r1
->fbc_wm_enabled
)
2650 } else if (level1
> level2
) {
2657 /* dirty bits used to track which watermarks need changes */
2658 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2659 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2660 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2661 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2662 #define WM_DIRTY_FBC (1 << 24)
2663 #define WM_DIRTY_DDB (1 << 25)
2665 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private
*dev_priv
,
2666 const struct ilk_wm_values
*old
,
2667 const struct ilk_wm_values
*new)
2669 unsigned int dirty
= 0;
2673 for_each_pipe(dev_priv
, pipe
) {
2674 if (old
->wm_linetime
[pipe
] != new->wm_linetime
[pipe
]) {
2675 dirty
|= WM_DIRTY_LINETIME(pipe
);
2676 /* Must disable LP1+ watermarks too */
2677 dirty
|= WM_DIRTY_LP_ALL
;
2680 if (old
->wm_pipe
[pipe
] != new->wm_pipe
[pipe
]) {
2681 dirty
|= WM_DIRTY_PIPE(pipe
);
2682 /* Must disable LP1+ watermarks too */
2683 dirty
|= WM_DIRTY_LP_ALL
;
2687 if (old
->enable_fbc_wm
!= new->enable_fbc_wm
) {
2688 dirty
|= WM_DIRTY_FBC
;
2689 /* Must disable LP1+ watermarks too */
2690 dirty
|= WM_DIRTY_LP_ALL
;
2693 if (old
->partitioning
!= new->partitioning
) {
2694 dirty
|= WM_DIRTY_DDB
;
2695 /* Must disable LP1+ watermarks too */
2696 dirty
|= WM_DIRTY_LP_ALL
;
2699 /* LP1+ watermarks already deemed dirty, no need to continue */
2700 if (dirty
& WM_DIRTY_LP_ALL
)
2703 /* Find the lowest numbered LP1+ watermark in need of an update... */
2704 for (wm_lp
= 1; wm_lp
<= 3; wm_lp
++) {
2705 if (old
->wm_lp
[wm_lp
- 1] != new->wm_lp
[wm_lp
- 1] ||
2706 old
->wm_lp_spr
[wm_lp
- 1] != new->wm_lp_spr
[wm_lp
- 1])
2710 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2711 for (; wm_lp
<= 3; wm_lp
++)
2712 dirty
|= WM_DIRTY_LP(wm_lp
);
2717 static bool _ilk_disable_lp_wm(struct drm_i915_private
*dev_priv
,
2720 struct ilk_wm_values
*previous
= &dev_priv
->wm
.hw
;
2721 bool changed
= false;
2723 if (dirty
& WM_DIRTY_LP(3) && previous
->wm_lp
[2] & WM1_LP_SR_EN
) {
2724 previous
->wm_lp
[2] &= ~WM1_LP_SR_EN
;
2725 I915_WRITE(WM3_LP_ILK
, previous
->wm_lp
[2]);
2728 if (dirty
& WM_DIRTY_LP(2) && previous
->wm_lp
[1] & WM1_LP_SR_EN
) {
2729 previous
->wm_lp
[1] &= ~WM1_LP_SR_EN
;
2730 I915_WRITE(WM2_LP_ILK
, previous
->wm_lp
[1]);
2733 if (dirty
& WM_DIRTY_LP(1) && previous
->wm_lp
[0] & WM1_LP_SR_EN
) {
2734 previous
->wm_lp
[0] &= ~WM1_LP_SR_EN
;
2735 I915_WRITE(WM1_LP_ILK
, previous
->wm_lp
[0]);
2740 * Don't touch WM1S_LP_EN here.
2741 * Doing so could cause underruns.
2748 * The spec says we shouldn't write when we don't need, because every write
2749 * causes WMs to be re-evaluated, expending some power.
2751 static void ilk_write_wm_values(struct drm_i915_private
*dev_priv
,
2752 struct ilk_wm_values
*results
)
2754 struct drm_device
*dev
= dev_priv
->dev
;
2755 struct ilk_wm_values
*previous
= &dev_priv
->wm
.hw
;
2759 dirty
= ilk_compute_wm_dirty(dev_priv
, previous
, results
);
2763 _ilk_disable_lp_wm(dev_priv
, dirty
);
2765 if (dirty
& WM_DIRTY_PIPE(PIPE_A
))
2766 I915_WRITE(WM0_PIPEA_ILK
, results
->wm_pipe
[0]);
2767 if (dirty
& WM_DIRTY_PIPE(PIPE_B
))
2768 I915_WRITE(WM0_PIPEB_ILK
, results
->wm_pipe
[1]);
2769 if (dirty
& WM_DIRTY_PIPE(PIPE_C
))
2770 I915_WRITE(WM0_PIPEC_IVB
, results
->wm_pipe
[2]);
2772 if (dirty
& WM_DIRTY_LINETIME(PIPE_A
))
2773 I915_WRITE(PIPE_WM_LINETIME(PIPE_A
), results
->wm_linetime
[0]);
2774 if (dirty
& WM_DIRTY_LINETIME(PIPE_B
))
2775 I915_WRITE(PIPE_WM_LINETIME(PIPE_B
), results
->wm_linetime
[1]);
2776 if (dirty
& WM_DIRTY_LINETIME(PIPE_C
))
2777 I915_WRITE(PIPE_WM_LINETIME(PIPE_C
), results
->wm_linetime
[2]);
2779 if (dirty
& WM_DIRTY_DDB
) {
2780 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2781 val
= I915_READ(WM_MISC
);
2782 if (results
->partitioning
== INTEL_DDB_PART_1_2
)
2783 val
&= ~WM_MISC_DATA_PARTITION_5_6
;
2785 val
|= WM_MISC_DATA_PARTITION_5_6
;
2786 I915_WRITE(WM_MISC
, val
);
2788 val
= I915_READ(DISP_ARB_CTL2
);
2789 if (results
->partitioning
== INTEL_DDB_PART_1_2
)
2790 val
&= ~DISP_DATA_PARTITION_5_6
;
2792 val
|= DISP_DATA_PARTITION_5_6
;
2793 I915_WRITE(DISP_ARB_CTL2
, val
);
2797 if (dirty
& WM_DIRTY_FBC
) {
2798 val
= I915_READ(DISP_ARB_CTL
);
2799 if (results
->enable_fbc_wm
)
2800 val
&= ~DISP_FBC_WM_DIS
;
2802 val
|= DISP_FBC_WM_DIS
;
2803 I915_WRITE(DISP_ARB_CTL
, val
);
2806 if (dirty
& WM_DIRTY_LP(1) &&
2807 previous
->wm_lp_spr
[0] != results
->wm_lp_spr
[0])
2808 I915_WRITE(WM1S_LP_ILK
, results
->wm_lp_spr
[0]);
2810 if (INTEL_INFO(dev
)->gen
>= 7) {
2811 if (dirty
& WM_DIRTY_LP(2) && previous
->wm_lp_spr
[1] != results
->wm_lp_spr
[1])
2812 I915_WRITE(WM2S_LP_IVB
, results
->wm_lp_spr
[1]);
2813 if (dirty
& WM_DIRTY_LP(3) && previous
->wm_lp_spr
[2] != results
->wm_lp_spr
[2])
2814 I915_WRITE(WM3S_LP_IVB
, results
->wm_lp_spr
[2]);
2817 if (dirty
& WM_DIRTY_LP(1) && previous
->wm_lp
[0] != results
->wm_lp
[0])
2818 I915_WRITE(WM1_LP_ILK
, results
->wm_lp
[0]);
2819 if (dirty
& WM_DIRTY_LP(2) && previous
->wm_lp
[1] != results
->wm_lp
[1])
2820 I915_WRITE(WM2_LP_ILK
, results
->wm_lp
[1]);
2821 if (dirty
& WM_DIRTY_LP(3) && previous
->wm_lp
[2] != results
->wm_lp
[2])
2822 I915_WRITE(WM3_LP_ILK
, results
->wm_lp
[2]);
2824 dev_priv
->wm
.hw
= *results
;
2827 bool ilk_disable_lp_wm(struct drm_device
*dev
)
2829 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2831 return _ilk_disable_lp_wm(dev_priv
, WM_DIRTY_LP_ALL
);
2835 * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2836 * different active planes.
2839 #define SKL_DDB_SIZE 896 /* in blocks */
2840 #define BXT_DDB_SIZE 512
2843 * Return the index of a plane in the SKL DDB and wm result arrays. Primary
2844 * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
2845 * other universal planes are in indices 1..n. Note that this may leave unused
2846 * indices between the top "sprite" plane and the cursor.
2849 skl_wm_plane_id(const struct intel_plane
*plane
)
2851 switch (plane
->base
.type
) {
2852 case DRM_PLANE_TYPE_PRIMARY
:
2854 case DRM_PLANE_TYPE_CURSOR
:
2855 return PLANE_CURSOR
;
2856 case DRM_PLANE_TYPE_OVERLAY
:
2857 return plane
->plane
+ 1;
2859 MISSING_CASE(plane
->base
.type
);
2860 return plane
->plane
;
2865 skl_ddb_get_pipe_allocation_limits(struct drm_device
*dev
,
2866 const struct intel_crtc_state
*cstate
,
2867 struct skl_ddb_entry
*alloc
, /* out */
2868 int *num_active
/* out */)
2870 struct drm_atomic_state
*state
= cstate
->base
.state
;
2871 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
2872 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2873 struct drm_crtc
*for_crtc
= cstate
->base
.crtc
;
2874 unsigned int pipe_size
, ddb_size
;
2875 int nth_active_pipe
;
2876 int pipe
= to_intel_crtc(for_crtc
)->pipe
;
2878 if (WARN_ON(!state
) || !cstate
->base
.active
) {
2881 *num_active
= hweight32(dev_priv
->active_crtcs
);
2885 if (intel_state
->active_pipe_changes
)
2886 *num_active
= hweight32(intel_state
->active_crtcs
);
2888 *num_active
= hweight32(dev_priv
->active_crtcs
);
2890 if (IS_BROXTON(dev
))
2891 ddb_size
= BXT_DDB_SIZE
;
2893 ddb_size
= SKL_DDB_SIZE
;
2895 ddb_size
-= 4; /* 4 blocks for bypass path allocation */
2898 * If the state doesn't change the active CRTC's, then there's
2899 * no need to recalculate; the existing pipe allocation limits
2900 * should remain unchanged. Note that we're safe from racing
2901 * commits since any racing commit that changes the active CRTC
2902 * list would need to grab _all_ crtc locks, including the one
2903 * we currently hold.
2905 if (!intel_state
->active_pipe_changes
) {
2906 *alloc
= dev_priv
->wm
.skl_hw
.ddb
.pipe
[pipe
];
2910 nth_active_pipe
= hweight32(intel_state
->active_crtcs
&
2911 (drm_crtc_mask(for_crtc
) - 1));
2912 pipe_size
= ddb_size
/ hweight32(intel_state
->active_crtcs
);
2913 alloc
->start
= nth_active_pipe
* ddb_size
/ *num_active
;
2914 alloc
->end
= alloc
->start
+ pipe_size
;
2917 static unsigned int skl_cursor_allocation(int num_active
)
2919 if (num_active
== 1)
2925 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry
*entry
, u32 reg
)
2927 entry
->start
= reg
& 0x3ff;
2928 entry
->end
= (reg
>> 16) & 0x3ff;
2933 void skl_ddb_get_hw_state(struct drm_i915_private
*dev_priv
,
2934 struct skl_ddb_allocation
*ddb
/* out */)
2940 memset(ddb
, 0, sizeof(*ddb
));
2942 for_each_pipe(dev_priv
, pipe
) {
2943 enum intel_display_power_domain power_domain
;
2945 power_domain
= POWER_DOMAIN_PIPE(pipe
);
2946 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
))
2949 for_each_plane(dev_priv
, pipe
, plane
) {
2950 val
= I915_READ(PLANE_BUF_CFG(pipe
, plane
));
2951 skl_ddb_entry_init_from_hw(&ddb
->plane
[pipe
][plane
],
2955 val
= I915_READ(CUR_BUF_CFG(pipe
));
2956 skl_ddb_entry_init_from_hw(&ddb
->plane
[pipe
][PLANE_CURSOR
],
2959 intel_display_power_put(dev_priv
, power_domain
);
2964 * Determines the downscale amount of a plane for the purposes of watermark calculations.
2965 * The bspec defines downscale amount as:
2968 * Horizontal down scale amount = maximum[1, Horizontal source size /
2969 * Horizontal destination size]
2970 * Vertical down scale amount = maximum[1, Vertical source size /
2971 * Vertical destination size]
2972 * Total down scale amount = Horizontal down scale amount *
2973 * Vertical down scale amount
2976 * Return value is provided in 16.16 fixed point form to retain fractional part.
2977 * Caller should take care of dividing & rounding off the value.
2980 skl_plane_downscale_amount(const struct intel_plane_state
*pstate
)
2982 uint32_t downscale_h
, downscale_w
;
2983 uint32_t src_w
, src_h
, dst_w
, dst_h
;
2985 if (WARN_ON(!pstate
->visible
))
2986 return DRM_PLANE_HELPER_NO_SCALING
;
2988 /* n.b., src is 16.16 fixed point, dst is whole integer */
2989 src_w
= drm_rect_width(&pstate
->src
);
2990 src_h
= drm_rect_height(&pstate
->src
);
2991 dst_w
= drm_rect_width(&pstate
->dst
);
2992 dst_h
= drm_rect_height(&pstate
->dst
);
2993 if (intel_rotation_90_or_270(pstate
->base
.rotation
))
2996 downscale_h
= max(src_h
/ dst_h
, (uint32_t)DRM_PLANE_HELPER_NO_SCALING
);
2997 downscale_w
= max(src_w
/ dst_w
, (uint32_t)DRM_PLANE_HELPER_NO_SCALING
);
2999 /* Provide result in 16.16 fixed point */
3000 return (uint64_t)downscale_w
* downscale_h
>> 16;
3004 skl_plane_relative_data_rate(const struct intel_crtc_state
*cstate
,
3005 const struct drm_plane_state
*pstate
,
3008 struct intel_plane_state
*intel_pstate
= to_intel_plane_state(pstate
);
3009 struct drm_framebuffer
*fb
= pstate
->fb
;
3010 uint32_t down_scale_amount
, data_rate
;
3011 uint32_t width
= 0, height
= 0;
3012 unsigned format
= fb
? fb
->pixel_format
: DRM_FORMAT_XRGB8888
;
3014 if (!intel_pstate
->visible
)
3016 if (pstate
->plane
->type
== DRM_PLANE_TYPE_CURSOR
)
3018 if (y
&& format
!= DRM_FORMAT_NV12
)
3021 width
= drm_rect_width(&intel_pstate
->src
) >> 16;
3022 height
= drm_rect_height(&intel_pstate
->src
) >> 16;
3024 if (intel_rotation_90_or_270(pstate
->rotation
))
3025 swap(width
, height
);
3027 /* for planar format */
3028 if (format
== DRM_FORMAT_NV12
) {
3029 if (y
) /* y-plane data rate */
3030 data_rate
= width
* height
*
3031 drm_format_plane_cpp(format
, 0);
3032 else /* uv-plane data rate */
3033 data_rate
= (width
/ 2) * (height
/ 2) *
3034 drm_format_plane_cpp(format
, 1);
3036 /* for packed formats */
3037 data_rate
= width
* height
* drm_format_plane_cpp(format
, 0);
3040 down_scale_amount
= skl_plane_downscale_amount(intel_pstate
);
3042 return (uint64_t)data_rate
* down_scale_amount
>> 16;
3046 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
3047 * a 8192x4096@32bpp framebuffer:
3048 * 3 * 4096 * 8192 * 4 < 2^32
3051 skl_get_total_relative_data_rate(struct intel_crtc_state
*intel_cstate
)
3053 struct drm_crtc_state
*cstate
= &intel_cstate
->base
;
3054 struct drm_atomic_state
*state
= cstate
->state
;
3055 struct drm_crtc
*crtc
= cstate
->crtc
;
3056 struct drm_device
*dev
= crtc
->dev
;
3057 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3058 const struct drm_plane
*plane
;
3059 const struct intel_plane
*intel_plane
;
3060 struct drm_plane_state
*pstate
;
3061 unsigned int rate
, total_data_rate
= 0;
3065 if (WARN_ON(!state
))
3068 /* Calculate and cache data rate for each plane */
3069 for_each_plane_in_state(state
, plane
, pstate
, i
) {
3070 id
= skl_wm_plane_id(to_intel_plane(plane
));
3071 intel_plane
= to_intel_plane(plane
);
3073 if (intel_plane
->pipe
!= intel_crtc
->pipe
)
3077 rate
= skl_plane_relative_data_rate(intel_cstate
,
3079 intel_cstate
->wm
.skl
.plane_data_rate
[id
] = rate
;
3082 rate
= skl_plane_relative_data_rate(intel_cstate
,
3084 intel_cstate
->wm
.skl
.plane_y_data_rate
[id
] = rate
;
3087 /* Calculate CRTC's total data rate from cached values */
3088 for_each_intel_plane_on_crtc(dev
, intel_crtc
, intel_plane
) {
3089 int id
= skl_wm_plane_id(intel_plane
);
3092 total_data_rate
+= intel_cstate
->wm
.skl
.plane_data_rate
[id
];
3093 total_data_rate
+= intel_cstate
->wm
.skl
.plane_y_data_rate
[id
];
3096 WARN_ON(cstate
->plane_mask
&& total_data_rate
== 0);
3098 return total_data_rate
;
3102 skl_ddb_min_alloc(const struct drm_plane_state
*pstate
,
3105 struct drm_framebuffer
*fb
= pstate
->fb
;
3106 struct intel_plane_state
*intel_pstate
= to_intel_plane_state(pstate
);
3107 uint32_t src_w
, src_h
;
3108 uint32_t min_scanlines
= 8;
3114 /* For packed formats, no y-plane, return 0 */
3115 if (y
&& fb
->pixel_format
!= DRM_FORMAT_NV12
)
3118 /* For Non Y-tile return 8-blocks */
3119 if (fb
->modifier
[0] != I915_FORMAT_MOD_Y_TILED
&&
3120 fb
->modifier
[0] != I915_FORMAT_MOD_Yf_TILED
)
3123 src_w
= drm_rect_width(&intel_pstate
->src
) >> 16;
3124 src_h
= drm_rect_height(&intel_pstate
->src
) >> 16;
3126 if (intel_rotation_90_or_270(pstate
->rotation
))
3129 /* Halve UV plane width and height for NV12 */
3130 if (fb
->pixel_format
== DRM_FORMAT_NV12
&& !y
) {
3135 if (fb
->pixel_format
== DRM_FORMAT_NV12
&& !y
)
3136 plane_bpp
= drm_format_plane_cpp(fb
->pixel_format
, 1);
3138 plane_bpp
= drm_format_plane_cpp(fb
->pixel_format
, 0);
3140 if (intel_rotation_90_or_270(pstate
->rotation
)) {
3141 switch (plane_bpp
) {
3155 WARN(1, "Unsupported pixel depth %u for rotation",
3161 return DIV_ROUND_UP((4 * src_w
* plane_bpp
), 512) * min_scanlines
/4 + 3;
3165 skl_allocate_pipe_ddb(struct intel_crtc_state
*cstate
,
3166 struct skl_ddb_allocation
*ddb
/* out */)
3168 struct drm_atomic_state
*state
= cstate
->base
.state
;
3169 struct drm_crtc
*crtc
= cstate
->base
.crtc
;
3170 struct drm_device
*dev
= crtc
->dev
;
3171 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3172 struct intel_plane
*intel_plane
;
3173 struct drm_plane
*plane
;
3174 struct drm_plane_state
*pstate
;
3175 enum pipe pipe
= intel_crtc
->pipe
;
3176 struct skl_ddb_entry
*alloc
= &ddb
->pipe
[pipe
];
3177 uint16_t alloc_size
, start
, cursor_blocks
;
3178 uint16_t *minimum
= cstate
->wm
.skl
.minimum_blocks
;
3179 uint16_t *y_minimum
= cstate
->wm
.skl
.minimum_y_blocks
;
3180 unsigned int total_data_rate
;
3184 if (WARN_ON(!state
))
3187 if (!cstate
->base
.active
) {
3188 ddb
->pipe
[pipe
].start
= ddb
->pipe
[pipe
].end
= 0;
3189 memset(ddb
->plane
[pipe
], 0, sizeof(ddb
->plane
[pipe
]));
3190 memset(ddb
->y_plane
[pipe
], 0, sizeof(ddb
->y_plane
[pipe
]));
3194 skl_ddb_get_pipe_allocation_limits(dev
, cstate
, alloc
, &num_active
);
3195 alloc_size
= skl_ddb_entry_size(alloc
);
3196 if (alloc_size
== 0) {
3197 memset(ddb
->plane
[pipe
], 0, sizeof(ddb
->plane
[pipe
]));
3201 cursor_blocks
= skl_cursor_allocation(num_active
);
3202 ddb
->plane
[pipe
][PLANE_CURSOR
].start
= alloc
->end
- cursor_blocks
;
3203 ddb
->plane
[pipe
][PLANE_CURSOR
].end
= alloc
->end
;
3205 alloc_size
-= cursor_blocks
;
3207 /* 1. Allocate the mininum required blocks for each active plane */
3208 for_each_plane_in_state(state
, plane
, pstate
, i
) {
3209 intel_plane
= to_intel_plane(plane
);
3210 id
= skl_wm_plane_id(intel_plane
);
3212 if (intel_plane
->pipe
!= pipe
)
3215 if (!to_intel_plane_state(pstate
)->visible
) {
3220 if (plane
->type
== DRM_PLANE_TYPE_CURSOR
) {
3226 minimum
[id
] = skl_ddb_min_alloc(pstate
, 0);
3227 y_minimum
[id
] = skl_ddb_min_alloc(pstate
, 1);
3230 for (i
= 0; i
< PLANE_CURSOR
; i
++) {
3231 alloc_size
-= minimum
[i
];
3232 alloc_size
-= y_minimum
[i
];
3236 * 2. Distribute the remaining space in proportion to the amount of
3237 * data each plane needs to fetch from memory.
3239 * FIXME: we may not allocate every single block here.
3241 total_data_rate
= skl_get_total_relative_data_rate(cstate
);
3242 if (total_data_rate
== 0)
3245 start
= alloc
->start
;
3246 for_each_intel_plane_on_crtc(dev
, intel_crtc
, intel_plane
) {
3247 unsigned int data_rate
, y_data_rate
;
3248 uint16_t plane_blocks
, y_plane_blocks
= 0;
3249 int id
= skl_wm_plane_id(intel_plane
);
3251 data_rate
= cstate
->wm
.skl
.plane_data_rate
[id
];
3254 * allocation for (packed formats) or (uv-plane part of planar format):
3255 * promote the expression to 64 bits to avoid overflowing, the
3256 * result is < available as data_rate / total_data_rate < 1
3258 plane_blocks
= minimum
[id
];
3259 plane_blocks
+= div_u64((uint64_t)alloc_size
* data_rate
,
3262 /* Leave disabled planes at (0,0) */
3264 ddb
->plane
[pipe
][id
].start
= start
;
3265 ddb
->plane
[pipe
][id
].end
= start
+ plane_blocks
;
3268 start
+= plane_blocks
;
3271 * allocation for y_plane part of planar format:
3273 y_data_rate
= cstate
->wm
.skl
.plane_y_data_rate
[id
];
3275 y_plane_blocks
= y_minimum
[id
];
3276 y_plane_blocks
+= div_u64((uint64_t)alloc_size
* y_data_rate
,
3280 ddb
->y_plane
[pipe
][id
].start
= start
;
3281 ddb
->y_plane
[pipe
][id
].end
= start
+ y_plane_blocks
;
3284 start
+= y_plane_blocks
;
3290 static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state
*config
)
3292 /* TODO: Take into account the scalers once we support them */
3293 return config
->base
.adjusted_mode
.crtc_clock
;
3297 * The max latency should be 257 (max the punit can code is 255 and we add 2us
3298 * for the read latency) and cpp should always be <= 8, so that
3299 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3300 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3302 static uint32_t skl_wm_method1(uint32_t pixel_rate
, uint8_t cpp
, uint32_t latency
)
3304 uint32_t wm_intermediate_val
, ret
;
3309 wm_intermediate_val
= latency
* pixel_rate
* cpp
/ 512;
3310 ret
= DIV_ROUND_UP(wm_intermediate_val
, 1000);
3315 static uint32_t skl_wm_method2(uint32_t pixel_rate
, uint32_t pipe_htotal
,
3316 uint32_t horiz_pixels
, uint8_t cpp
,
3317 uint64_t tiling
, uint32_t latency
)
3320 uint32_t plane_bytes_per_line
, plane_blocks_per_line
;
3321 uint32_t wm_intermediate_val
;
3326 plane_bytes_per_line
= horiz_pixels
* cpp
;
3328 if (tiling
== I915_FORMAT_MOD_Y_TILED
||
3329 tiling
== I915_FORMAT_MOD_Yf_TILED
) {
3330 plane_bytes_per_line
*= 4;
3331 plane_blocks_per_line
= DIV_ROUND_UP(plane_bytes_per_line
, 512);
3332 plane_blocks_per_line
/= 4;
3334 plane_blocks_per_line
= DIV_ROUND_UP(plane_bytes_per_line
, 512);
3337 wm_intermediate_val
= latency
* pixel_rate
;
3338 ret
= DIV_ROUND_UP(wm_intermediate_val
, pipe_htotal
* 1000) *
3339 plane_blocks_per_line
;
3344 static uint32_t skl_adjusted_plane_pixel_rate(const struct intel_crtc_state
*cstate
,
3345 struct intel_plane_state
*pstate
)
3347 uint64_t adjusted_pixel_rate
;
3348 uint64_t downscale_amount
;
3349 uint64_t pixel_rate
;
3351 /* Shouldn't reach here on disabled planes... */
3352 if (WARN_ON(!pstate
->visible
))
3356 * Adjusted plane pixel rate is just the pipe's adjusted pixel rate
3357 * with additional adjustments for plane-specific scaling.
3359 adjusted_pixel_rate
= skl_pipe_pixel_rate(cstate
);
3360 downscale_amount
= skl_plane_downscale_amount(pstate
);
3362 pixel_rate
= adjusted_pixel_rate
* downscale_amount
>> 16;
3363 WARN_ON(pixel_rate
!= clamp_t(uint32_t, pixel_rate
, 0, ~0));
3368 static int skl_compute_plane_wm(const struct drm_i915_private
*dev_priv
,
3369 struct intel_crtc_state
*cstate
,
3370 struct intel_plane_state
*intel_pstate
,
3371 uint16_t ddb_allocation
,
3373 uint16_t *out_blocks
, /* out */
3374 uint8_t *out_lines
, /* out */
3375 bool *enabled
/* out */)
3377 struct drm_plane_state
*pstate
= &intel_pstate
->base
;
3378 struct drm_framebuffer
*fb
= pstate
->fb
;
3379 uint32_t latency
= dev_priv
->wm
.skl_latency
[level
];
3380 uint32_t method1
, method2
;
3381 uint32_t plane_bytes_per_line
, plane_blocks_per_line
;
3382 uint32_t res_blocks
, res_lines
;
3383 uint32_t selected_result
;
3385 uint32_t width
= 0, height
= 0;
3386 uint32_t plane_pixel_rate
;
3388 if (latency
== 0 || !cstate
->base
.active
|| !intel_pstate
->visible
) {
3393 width
= drm_rect_width(&intel_pstate
->src
) >> 16;
3394 height
= drm_rect_height(&intel_pstate
->src
) >> 16;
3396 if (intel_rotation_90_or_270(pstate
->rotation
))
3397 swap(width
, height
);
3399 cpp
= drm_format_plane_cpp(fb
->pixel_format
, 0);
3400 plane_pixel_rate
= skl_adjusted_plane_pixel_rate(cstate
, intel_pstate
);
3402 method1
= skl_wm_method1(plane_pixel_rate
, cpp
, latency
);
3403 method2
= skl_wm_method2(plane_pixel_rate
,
3404 cstate
->base
.adjusted_mode
.crtc_htotal
,
3410 plane_bytes_per_line
= width
* cpp
;
3411 plane_blocks_per_line
= DIV_ROUND_UP(plane_bytes_per_line
, 512);
3413 if (fb
->modifier
[0] == I915_FORMAT_MOD_Y_TILED
||
3414 fb
->modifier
[0] == I915_FORMAT_MOD_Yf_TILED
) {
3415 uint32_t min_scanlines
= 4;
3416 uint32_t y_tile_minimum
;
3417 if (intel_rotation_90_or_270(pstate
->rotation
)) {
3418 int cpp
= (fb
->pixel_format
== DRM_FORMAT_NV12
) ?
3419 drm_format_plane_cpp(fb
->pixel_format
, 1) :
3420 drm_format_plane_cpp(fb
->pixel_format
, 0);
3430 WARN(1, "Unsupported pixel depth for rotation");
3433 y_tile_minimum
= plane_blocks_per_line
* min_scanlines
;
3434 selected_result
= max(method2
, y_tile_minimum
);
3436 if ((ddb_allocation
/ plane_blocks_per_line
) >= 1)
3437 selected_result
= min(method1
, method2
);
3439 selected_result
= method1
;
3442 res_blocks
= selected_result
+ 1;
3443 res_lines
= DIV_ROUND_UP(selected_result
, plane_blocks_per_line
);
3445 if (level
>= 1 && level
<= 7) {
3446 if (fb
->modifier
[0] == I915_FORMAT_MOD_Y_TILED
||
3447 fb
->modifier
[0] == I915_FORMAT_MOD_Yf_TILED
)
3453 if (res_blocks
>= ddb_allocation
|| res_lines
> 31) {
3457 * If there are no valid level 0 watermarks, then we can't
3458 * support this display configuration.
3463 DRM_DEBUG_KMS("Requested display configuration exceeds system watermark limitations\n");
3464 DRM_DEBUG_KMS("Plane %d.%d: blocks required = %u/%u, lines required = %u/31\n",
3465 to_intel_crtc(cstate
->base
.crtc
)->pipe
,
3466 skl_wm_plane_id(to_intel_plane(pstate
->plane
)),
3467 res_blocks
, ddb_allocation
, res_lines
);
3473 *out_blocks
= res_blocks
;
3474 *out_lines
= res_lines
;
3481 skl_compute_wm_level(const struct drm_i915_private
*dev_priv
,
3482 struct skl_ddb_allocation
*ddb
,
3483 struct intel_crtc_state
*cstate
,
3485 struct skl_wm_level
*result
)
3487 struct drm_device
*dev
= dev_priv
->dev
;
3488 struct drm_atomic_state
*state
= cstate
->base
.state
;
3489 struct intel_crtc
*intel_crtc
= to_intel_crtc(cstate
->base
.crtc
);
3490 struct drm_plane
*plane
;
3491 struct intel_plane
*intel_plane
;
3492 struct intel_plane_state
*intel_pstate
;
3493 uint16_t ddb_blocks
;
3494 enum pipe pipe
= intel_crtc
->pipe
;
3498 * We'll only calculate watermarks for planes that are actually
3499 * enabled, so make sure all other planes are set as disabled.
3501 memset(result
, 0, sizeof(*result
));
3503 for_each_intel_plane_mask(dev
, intel_plane
, cstate
->base
.plane_mask
) {
3504 int i
= skl_wm_plane_id(intel_plane
);
3506 plane
= &intel_plane
->base
;
3507 intel_pstate
= NULL
;
3510 intel_atomic_get_existing_plane_state(state
,
3514 * Note: If we start supporting multiple pending atomic commits
3515 * against the same planes/CRTC's in the future, plane->state
3516 * will no longer be the correct pre-state to use for the
3517 * calculations here and we'll need to change where we get the
3518 * 'unchanged' plane data from.
3520 * For now this is fine because we only allow one queued commit
3521 * against a CRTC. Even if the plane isn't modified by this
3522 * transaction and we don't have a plane lock, we still have
3523 * the CRTC's lock, so we know that no other transactions are
3524 * racing with us to update it.
3527 intel_pstate
= to_intel_plane_state(plane
->state
);
3529 WARN_ON(!intel_pstate
->base
.fb
);
3531 ddb_blocks
= skl_ddb_entry_size(&ddb
->plane
[pipe
][i
]);
3533 ret
= skl_compute_plane_wm(dev_priv
,
3538 &result
->plane_res_b
[i
],
3539 &result
->plane_res_l
[i
],
3540 &result
->plane_en
[i
]);
3549 skl_compute_linetime_wm(struct intel_crtc_state
*cstate
)
3551 if (!cstate
->base
.active
)
3554 if (WARN_ON(skl_pipe_pixel_rate(cstate
) == 0))
3557 return DIV_ROUND_UP(8 * cstate
->base
.adjusted_mode
.crtc_htotal
* 1000,
3558 skl_pipe_pixel_rate(cstate
));
3561 static void skl_compute_transition_wm(struct intel_crtc_state
*cstate
,
3562 struct skl_wm_level
*trans_wm
/* out */)
3564 struct drm_crtc
*crtc
= cstate
->base
.crtc
;
3565 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3566 struct intel_plane
*intel_plane
;
3568 if (!cstate
->base
.active
)
3571 /* Until we know more, just disable transition WMs */
3572 for_each_intel_plane_on_crtc(crtc
->dev
, intel_crtc
, intel_plane
) {
3573 int i
= skl_wm_plane_id(intel_plane
);
3575 trans_wm
->plane_en
[i
] = false;
3579 static int skl_build_pipe_wm(struct intel_crtc_state
*cstate
,
3580 struct skl_ddb_allocation
*ddb
,
3581 struct skl_pipe_wm
*pipe_wm
)
3583 struct drm_device
*dev
= cstate
->base
.crtc
->dev
;
3584 const struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3585 int level
, max_level
= ilk_wm_max_level(dev
);
3588 for (level
= 0; level
<= max_level
; level
++) {
3589 ret
= skl_compute_wm_level(dev_priv
, ddb
, cstate
,
3590 level
, &pipe_wm
->wm
[level
]);
3594 pipe_wm
->linetime
= skl_compute_linetime_wm(cstate
);
3596 skl_compute_transition_wm(cstate
, &pipe_wm
->trans_wm
);
3601 static void skl_compute_wm_results(struct drm_device
*dev
,
3602 struct skl_pipe_wm
*p_wm
,
3603 struct skl_wm_values
*r
,
3604 struct intel_crtc
*intel_crtc
)
3606 int level
, max_level
= ilk_wm_max_level(dev
);
3607 enum pipe pipe
= intel_crtc
->pipe
;
3611 for (level
= 0; level
<= max_level
; level
++) {
3612 for (i
= 0; i
< intel_num_planes(intel_crtc
); i
++) {
3615 temp
|= p_wm
->wm
[level
].plane_res_l
[i
] <<
3616 PLANE_WM_LINES_SHIFT
;
3617 temp
|= p_wm
->wm
[level
].plane_res_b
[i
];
3618 if (p_wm
->wm
[level
].plane_en
[i
])
3619 temp
|= PLANE_WM_EN
;
3621 r
->plane
[pipe
][i
][level
] = temp
;
3626 temp
|= p_wm
->wm
[level
].plane_res_l
[PLANE_CURSOR
] << PLANE_WM_LINES_SHIFT
;
3627 temp
|= p_wm
->wm
[level
].plane_res_b
[PLANE_CURSOR
];
3629 if (p_wm
->wm
[level
].plane_en
[PLANE_CURSOR
])
3630 temp
|= PLANE_WM_EN
;
3632 r
->plane
[pipe
][PLANE_CURSOR
][level
] = temp
;
3636 /* transition WMs */
3637 for (i
= 0; i
< intel_num_planes(intel_crtc
); i
++) {
3639 temp
|= p_wm
->trans_wm
.plane_res_l
[i
] << PLANE_WM_LINES_SHIFT
;
3640 temp
|= p_wm
->trans_wm
.plane_res_b
[i
];
3641 if (p_wm
->trans_wm
.plane_en
[i
])
3642 temp
|= PLANE_WM_EN
;
3644 r
->plane_trans
[pipe
][i
] = temp
;
3648 temp
|= p_wm
->trans_wm
.plane_res_l
[PLANE_CURSOR
] << PLANE_WM_LINES_SHIFT
;
3649 temp
|= p_wm
->trans_wm
.plane_res_b
[PLANE_CURSOR
];
3650 if (p_wm
->trans_wm
.plane_en
[PLANE_CURSOR
])
3651 temp
|= PLANE_WM_EN
;
3653 r
->plane_trans
[pipe
][PLANE_CURSOR
] = temp
;
3655 r
->wm_linetime
[pipe
] = p_wm
->linetime
;
3658 static void skl_ddb_entry_write(struct drm_i915_private
*dev_priv
,
3660 const struct skl_ddb_entry
*entry
)
3663 I915_WRITE(reg
, (entry
->end
- 1) << 16 | entry
->start
);
3668 static void skl_write_wm_values(struct drm_i915_private
*dev_priv
,
3669 const struct skl_wm_values
*new)
3671 struct drm_device
*dev
= dev_priv
->dev
;
3672 struct intel_crtc
*crtc
;
3674 for_each_intel_crtc(dev
, crtc
) {
3675 int i
, level
, max_level
= ilk_wm_max_level(dev
);
3676 enum pipe pipe
= crtc
->pipe
;
3678 if ((new->dirty_pipes
& drm_crtc_mask(&crtc
->base
)) == 0)
3683 I915_WRITE(PIPE_WM_LINETIME(pipe
), new->wm_linetime
[pipe
]);
3685 for (level
= 0; level
<= max_level
; level
++) {
3686 for (i
= 0; i
< intel_num_planes(crtc
); i
++)
3687 I915_WRITE(PLANE_WM(pipe
, i
, level
),
3688 new->plane
[pipe
][i
][level
]);
3689 I915_WRITE(CUR_WM(pipe
, level
),
3690 new->plane
[pipe
][PLANE_CURSOR
][level
]);
3692 for (i
= 0; i
< intel_num_planes(crtc
); i
++)
3693 I915_WRITE(PLANE_WM_TRANS(pipe
, i
),
3694 new->plane_trans
[pipe
][i
]);
3695 I915_WRITE(CUR_WM_TRANS(pipe
),
3696 new->plane_trans
[pipe
][PLANE_CURSOR
]);
3698 for (i
= 0; i
< intel_num_planes(crtc
); i
++) {
3699 skl_ddb_entry_write(dev_priv
,
3700 PLANE_BUF_CFG(pipe
, i
),
3701 &new->ddb
.plane
[pipe
][i
]);
3702 skl_ddb_entry_write(dev_priv
,
3703 PLANE_NV12_BUF_CFG(pipe
, i
),
3704 &new->ddb
.y_plane
[pipe
][i
]);
3707 skl_ddb_entry_write(dev_priv
, CUR_BUF_CFG(pipe
),
3708 &new->ddb
.plane
[pipe
][PLANE_CURSOR
]);
3713 * When setting up a new DDB allocation arrangement, we need to correctly
3714 * sequence the times at which the new allocations for the pipes are taken into
3715 * account or we'll have pipes fetching from space previously allocated to
3718 * Roughly the sequence looks like:
3719 * 1. re-allocate the pipe(s) with the allocation being reduced and not
3720 * overlapping with a previous light-up pipe (another way to put it is:
3721 * pipes with their new allocation strickly included into their old ones).
3722 * 2. re-allocate the other pipes that get their allocation reduced
3723 * 3. allocate the pipes having their allocation increased
3725 * Steps 1. and 2. are here to take care of the following case:
3726 * - Initially DDB looks like this:
3729 * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
3733 * We need to sequence the re-allocation: C, B, A (and not B, C, A).
3737 skl_wm_flush_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int pass
)
3741 DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe
), pass
);
3743 for_each_plane(dev_priv
, pipe
, plane
) {
3744 I915_WRITE(PLANE_SURF(pipe
, plane
),
3745 I915_READ(PLANE_SURF(pipe
, plane
)));
3747 I915_WRITE(CURBASE(pipe
), I915_READ(CURBASE(pipe
)));
3751 skl_ddb_allocation_included(const struct skl_ddb_allocation
*old
,
3752 const struct skl_ddb_allocation
*new,
3755 uint16_t old_size
, new_size
;
3757 old_size
= skl_ddb_entry_size(&old
->pipe
[pipe
]);
3758 new_size
= skl_ddb_entry_size(&new->pipe
[pipe
]);
3760 return old_size
!= new_size
&&
3761 new->pipe
[pipe
].start
>= old
->pipe
[pipe
].start
&&
3762 new->pipe
[pipe
].end
<= old
->pipe
[pipe
].end
;
3765 static void skl_flush_wm_values(struct drm_i915_private
*dev_priv
,
3766 struct skl_wm_values
*new_values
)
3768 struct drm_device
*dev
= dev_priv
->dev
;
3769 struct skl_ddb_allocation
*cur_ddb
, *new_ddb
;
3770 bool reallocated
[I915_MAX_PIPES
] = {};
3771 struct intel_crtc
*crtc
;
3774 new_ddb
= &new_values
->ddb
;
3775 cur_ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
3778 * First pass: flush the pipes with the new allocation contained into
3781 * We'll wait for the vblank on those pipes to ensure we can safely
3782 * re-allocate the freed space without this pipe fetching from it.
3784 for_each_intel_crtc(dev
, crtc
) {
3790 if (!skl_ddb_allocation_included(cur_ddb
, new_ddb
, pipe
))
3793 skl_wm_flush_pipe(dev_priv
, pipe
, 1);
3794 intel_wait_for_vblank(dev
, pipe
);
3796 reallocated
[pipe
] = true;
3801 * Second pass: flush the pipes that are having their allocation
3802 * reduced, but overlapping with a previous allocation.
3804 * Here as well we need to wait for the vblank to make sure the freed
3805 * space is not used anymore.
3807 for_each_intel_crtc(dev
, crtc
) {
3813 if (reallocated
[pipe
])
3816 if (skl_ddb_entry_size(&new_ddb
->pipe
[pipe
]) <
3817 skl_ddb_entry_size(&cur_ddb
->pipe
[pipe
])) {
3818 skl_wm_flush_pipe(dev_priv
, pipe
, 2);
3819 intel_wait_for_vblank(dev
, pipe
);
3820 reallocated
[pipe
] = true;
3825 * Third pass: flush the pipes that got more space allocated.
3827 * We don't need to actively wait for the update here, next vblank
3828 * will just get more DDB space with the correct WM values.
3830 for_each_intel_crtc(dev
, crtc
) {
3837 * At this point, only the pipes more space than before are
3838 * left to re-allocate.
3840 if (reallocated
[pipe
])
3843 skl_wm_flush_pipe(dev_priv
, pipe
, 3);
3847 static int skl_update_pipe_wm(struct drm_crtc_state
*cstate
,
3848 struct skl_ddb_allocation
*ddb
, /* out */
3849 struct skl_pipe_wm
*pipe_wm
, /* out */
3850 bool *changed
/* out */)
3852 struct intel_crtc
*intel_crtc
= to_intel_crtc(cstate
->crtc
);
3853 struct intel_crtc_state
*intel_cstate
= to_intel_crtc_state(cstate
);
3856 ret
= skl_build_pipe_wm(intel_cstate
, ddb
, pipe_wm
);
3860 if (!memcmp(&intel_crtc
->wm
.active
.skl
, pipe_wm
, sizeof(*pipe_wm
)))
3869 skl_compute_ddb(struct drm_atomic_state
*state
)
3871 struct drm_device
*dev
= state
->dev
;
3872 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3873 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
3874 struct intel_crtc
*intel_crtc
;
3875 struct skl_ddb_allocation
*ddb
= &intel_state
->wm_results
.ddb
;
3876 unsigned realloc_pipes
= dev_priv
->active_crtcs
;
3880 * If this is our first atomic update following hardware readout,
3881 * we can't trust the DDB that the BIOS programmed for us. Let's
3882 * pretend that all pipes switched active status so that we'll
3883 * ensure a full DDB recompute.
3885 if (dev_priv
->wm
.distrust_bios_wm
)
3886 intel_state
->active_pipe_changes
= ~0;
3889 * If the modeset changes which CRTC's are active, we need to
3890 * recompute the DDB allocation for *all* active pipes, even
3891 * those that weren't otherwise being modified in any way by this
3892 * atomic commit. Due to the shrinking of the per-pipe allocations
3893 * when new active CRTC's are added, it's possible for a pipe that
3894 * we were already using and aren't changing at all here to suddenly
3895 * become invalid if its DDB needs exceeds its new allocation.
3897 * Note that if we wind up doing a full DDB recompute, we can't let
3898 * any other display updates race with this transaction, so we need
3899 * to grab the lock on *all* CRTC's.
3901 if (intel_state
->active_pipe_changes
) {
3903 intel_state
->wm_results
.dirty_pipes
= ~0;
3906 for_each_intel_crtc_mask(dev
, intel_crtc
, realloc_pipes
) {
3907 struct intel_crtc_state
*cstate
;
3909 cstate
= intel_atomic_get_crtc_state(state
, intel_crtc
);
3911 return PTR_ERR(cstate
);
3913 ret
= skl_allocate_pipe_ddb(cstate
, ddb
);
3922 skl_compute_wm(struct drm_atomic_state
*state
)
3924 struct drm_crtc
*crtc
;
3925 struct drm_crtc_state
*cstate
;
3926 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
3927 struct skl_wm_values
*results
= &intel_state
->wm_results
;
3928 struct skl_pipe_wm
*pipe_wm
;
3929 bool changed
= false;
3933 * If this transaction isn't actually touching any CRTC's, don't
3934 * bother with watermark calculation. Note that if we pass this
3935 * test, we're guaranteed to hold at least one CRTC state mutex,
3936 * which means we can safely use values like dev_priv->active_crtcs
3937 * since any racing commits that want to update them would need to
3938 * hold _all_ CRTC state mutexes.
3940 for_each_crtc_in_state(state
, crtc
, cstate
, i
)
3945 /* Clear all dirty flags */
3946 results
->dirty_pipes
= 0;
3948 ret
= skl_compute_ddb(state
);
3953 * Calculate WM's for all pipes that are part of this transaction.
3954 * Note that the DDB allocation above may have added more CRTC's that
3955 * weren't otherwise being modified (and set bits in dirty_pipes) if
3956 * pipe allocations had to change.
3958 * FIXME: Now that we're doing this in the atomic check phase, we
3959 * should allow skl_update_pipe_wm() to return failure in cases where
3960 * no suitable watermark values can be found.
3962 for_each_crtc_in_state(state
, crtc
, cstate
, i
) {
3963 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3964 struct intel_crtc_state
*intel_cstate
=
3965 to_intel_crtc_state(cstate
);
3967 pipe_wm
= &intel_cstate
->wm
.skl
.optimal
;
3968 ret
= skl_update_pipe_wm(cstate
, &results
->ddb
, pipe_wm
,
3974 results
->dirty_pipes
|= drm_crtc_mask(crtc
);
3976 if ((results
->dirty_pipes
& drm_crtc_mask(crtc
)) == 0)
3977 /* This pipe's WM's did not change */
3980 intel_cstate
->update_wm_pre
= true;
3981 skl_compute_wm_results(crtc
->dev
, pipe_wm
, results
, intel_crtc
);
3987 static void skl_update_wm(struct drm_crtc
*crtc
)
3989 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3990 struct drm_device
*dev
= crtc
->dev
;
3991 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3992 struct skl_wm_values
*results
= &dev_priv
->wm
.skl_results
;
3993 struct intel_crtc_state
*cstate
= to_intel_crtc_state(crtc
->state
);
3994 struct skl_pipe_wm
*pipe_wm
= &cstate
->wm
.skl
.optimal
;
3996 if ((results
->dirty_pipes
& drm_crtc_mask(crtc
)) == 0)
3999 intel_crtc
->wm
.active
.skl
= *pipe_wm
;
4001 mutex_lock(&dev_priv
->wm
.wm_mutex
);
4003 skl_write_wm_values(dev_priv
, results
);
4004 skl_flush_wm_values(dev_priv
, results
);
4006 /* store the new configuration */
4007 dev_priv
->wm
.skl_hw
= *results
;
4009 mutex_unlock(&dev_priv
->wm
.wm_mutex
);
4012 static void ilk_compute_wm_config(struct drm_device
*dev
,
4013 struct intel_wm_config
*config
)
4015 struct intel_crtc
*crtc
;
4017 /* Compute the currently _active_ config */
4018 for_each_intel_crtc(dev
, crtc
) {
4019 const struct intel_pipe_wm
*wm
= &crtc
->wm
.active
.ilk
;
4021 if (!wm
->pipe_enabled
)
4024 config
->sprites_enabled
|= wm
->sprites_enabled
;
4025 config
->sprites_scaled
|= wm
->sprites_scaled
;
4026 config
->num_pipes_active
++;
4030 static void ilk_program_watermarks(struct drm_i915_private
*dev_priv
)
4032 struct drm_device
*dev
= dev_priv
->dev
;
4033 struct intel_pipe_wm lp_wm_1_2
= {}, lp_wm_5_6
= {}, *best_lp_wm
;
4034 struct ilk_wm_maximums max
;
4035 struct intel_wm_config config
= {};
4036 struct ilk_wm_values results
= {};
4037 enum intel_ddb_partitioning partitioning
;
4039 ilk_compute_wm_config(dev
, &config
);
4041 ilk_compute_wm_maximums(dev
, 1, &config
, INTEL_DDB_PART_1_2
, &max
);
4042 ilk_wm_merge(dev
, &config
, &max
, &lp_wm_1_2
);
4044 /* 5/6 split only in single pipe config on IVB+ */
4045 if (INTEL_INFO(dev
)->gen
>= 7 &&
4046 config
.num_pipes_active
== 1 && config
.sprites_enabled
) {
4047 ilk_compute_wm_maximums(dev
, 1, &config
, INTEL_DDB_PART_5_6
, &max
);
4048 ilk_wm_merge(dev
, &config
, &max
, &lp_wm_5_6
);
4050 best_lp_wm
= ilk_find_best_result(dev
, &lp_wm_1_2
, &lp_wm_5_6
);
4052 best_lp_wm
= &lp_wm_1_2
;
4055 partitioning
= (best_lp_wm
== &lp_wm_1_2
) ?
4056 INTEL_DDB_PART_1_2
: INTEL_DDB_PART_5_6
;
4058 ilk_compute_wm_results(dev
, best_lp_wm
, partitioning
, &results
);
4060 ilk_write_wm_values(dev_priv
, &results
);
4063 static void ilk_initial_watermarks(struct intel_crtc_state
*cstate
)
4065 struct drm_i915_private
*dev_priv
= to_i915(cstate
->base
.crtc
->dev
);
4066 struct intel_crtc
*intel_crtc
= to_intel_crtc(cstate
->base
.crtc
);
4068 mutex_lock(&dev_priv
->wm
.wm_mutex
);
4069 intel_crtc
->wm
.active
.ilk
= cstate
->wm
.ilk
.intermediate
;
4070 ilk_program_watermarks(dev_priv
);
4071 mutex_unlock(&dev_priv
->wm
.wm_mutex
);
4074 static void ilk_optimize_watermarks(struct intel_crtc_state
*cstate
)
4076 struct drm_i915_private
*dev_priv
= to_i915(cstate
->base
.crtc
->dev
);
4077 struct intel_crtc
*intel_crtc
= to_intel_crtc(cstate
->base
.crtc
);
4079 mutex_lock(&dev_priv
->wm
.wm_mutex
);
4080 if (cstate
->wm
.need_postvbl_update
) {
4081 intel_crtc
->wm
.active
.ilk
= cstate
->wm
.ilk
.optimal
;
4082 ilk_program_watermarks(dev_priv
);
4084 mutex_unlock(&dev_priv
->wm
.wm_mutex
);
4087 static void skl_pipe_wm_active_state(uint32_t val
,
4088 struct skl_pipe_wm
*active
,
4094 bool is_enabled
= (val
& PLANE_WM_EN
) != 0;
4098 active
->wm
[level
].plane_en
[i
] = is_enabled
;
4099 active
->wm
[level
].plane_res_b
[i
] =
4100 val
& PLANE_WM_BLOCKS_MASK
;
4101 active
->wm
[level
].plane_res_l
[i
] =
4102 (val
>> PLANE_WM_LINES_SHIFT
) &
4103 PLANE_WM_LINES_MASK
;
4105 active
->wm
[level
].plane_en
[PLANE_CURSOR
] = is_enabled
;
4106 active
->wm
[level
].plane_res_b
[PLANE_CURSOR
] =
4107 val
& PLANE_WM_BLOCKS_MASK
;
4108 active
->wm
[level
].plane_res_l
[PLANE_CURSOR
] =
4109 (val
>> PLANE_WM_LINES_SHIFT
) &
4110 PLANE_WM_LINES_MASK
;
4114 active
->trans_wm
.plane_en
[i
] = is_enabled
;
4115 active
->trans_wm
.plane_res_b
[i
] =
4116 val
& PLANE_WM_BLOCKS_MASK
;
4117 active
->trans_wm
.plane_res_l
[i
] =
4118 (val
>> PLANE_WM_LINES_SHIFT
) &
4119 PLANE_WM_LINES_MASK
;
4121 active
->trans_wm
.plane_en
[PLANE_CURSOR
] = is_enabled
;
4122 active
->trans_wm
.plane_res_b
[PLANE_CURSOR
] =
4123 val
& PLANE_WM_BLOCKS_MASK
;
4124 active
->trans_wm
.plane_res_l
[PLANE_CURSOR
] =
4125 (val
>> PLANE_WM_LINES_SHIFT
) &
4126 PLANE_WM_LINES_MASK
;
4131 static void skl_pipe_wm_get_hw_state(struct drm_crtc
*crtc
)
4133 struct drm_device
*dev
= crtc
->dev
;
4134 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4135 struct skl_wm_values
*hw
= &dev_priv
->wm
.skl_hw
;
4136 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4137 struct intel_crtc_state
*cstate
= to_intel_crtc_state(crtc
->state
);
4138 struct skl_pipe_wm
*active
= &cstate
->wm
.skl
.optimal
;
4139 enum pipe pipe
= intel_crtc
->pipe
;
4140 int level
, i
, max_level
;
4143 max_level
= ilk_wm_max_level(dev
);
4145 hw
->wm_linetime
[pipe
] = I915_READ(PIPE_WM_LINETIME(pipe
));
4147 for (level
= 0; level
<= max_level
; level
++) {
4148 for (i
= 0; i
< intel_num_planes(intel_crtc
); i
++)
4149 hw
->plane
[pipe
][i
][level
] =
4150 I915_READ(PLANE_WM(pipe
, i
, level
));
4151 hw
->plane
[pipe
][PLANE_CURSOR
][level
] = I915_READ(CUR_WM(pipe
, level
));
4154 for (i
= 0; i
< intel_num_planes(intel_crtc
); i
++)
4155 hw
->plane_trans
[pipe
][i
] = I915_READ(PLANE_WM_TRANS(pipe
, i
));
4156 hw
->plane_trans
[pipe
][PLANE_CURSOR
] = I915_READ(CUR_WM_TRANS(pipe
));
4158 if (!intel_crtc
->active
)
4161 hw
->dirty_pipes
|= drm_crtc_mask(crtc
);
4163 active
->linetime
= hw
->wm_linetime
[pipe
];
4165 for (level
= 0; level
<= max_level
; level
++) {
4166 for (i
= 0; i
< intel_num_planes(intel_crtc
); i
++) {
4167 temp
= hw
->plane
[pipe
][i
][level
];
4168 skl_pipe_wm_active_state(temp
, active
, false,
4171 temp
= hw
->plane
[pipe
][PLANE_CURSOR
][level
];
4172 skl_pipe_wm_active_state(temp
, active
, false, true, i
, level
);
4175 for (i
= 0; i
< intel_num_planes(intel_crtc
); i
++) {
4176 temp
= hw
->plane_trans
[pipe
][i
];
4177 skl_pipe_wm_active_state(temp
, active
, true, false, i
, 0);
4180 temp
= hw
->plane_trans
[pipe
][PLANE_CURSOR
];
4181 skl_pipe_wm_active_state(temp
, active
, true, true, i
, 0);
4183 intel_crtc
->wm
.active
.skl
= *active
;
4186 void skl_wm_get_hw_state(struct drm_device
*dev
)
4188 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4189 struct skl_ddb_allocation
*ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
4190 struct drm_crtc
*crtc
;
4192 skl_ddb_get_hw_state(dev_priv
, ddb
);
4193 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
)
4194 skl_pipe_wm_get_hw_state(crtc
);
4196 if (dev_priv
->active_crtcs
) {
4197 /* Fully recompute DDB on first atomic commit */
4198 dev_priv
->wm
.distrust_bios_wm
= true;
4200 /* Easy/common case; just sanitize DDB now if everything off */
4201 memset(ddb
, 0, sizeof(*ddb
));
4205 static void ilk_pipe_wm_get_hw_state(struct drm_crtc
*crtc
)
4207 struct drm_device
*dev
= crtc
->dev
;
4208 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4209 struct ilk_wm_values
*hw
= &dev_priv
->wm
.hw
;
4210 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4211 struct intel_crtc_state
*cstate
= to_intel_crtc_state(crtc
->state
);
4212 struct intel_pipe_wm
*active
= &cstate
->wm
.ilk
.optimal
;
4213 enum pipe pipe
= intel_crtc
->pipe
;
4214 static const i915_reg_t wm0_pipe_reg
[] = {
4215 [PIPE_A
] = WM0_PIPEA_ILK
,
4216 [PIPE_B
] = WM0_PIPEB_ILK
,
4217 [PIPE_C
] = WM0_PIPEC_IVB
,
4220 hw
->wm_pipe
[pipe
] = I915_READ(wm0_pipe_reg
[pipe
]);
4221 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
4222 hw
->wm_linetime
[pipe
] = I915_READ(PIPE_WM_LINETIME(pipe
));
4224 memset(active
, 0, sizeof(*active
));
4226 active
->pipe_enabled
= intel_crtc
->active
;
4228 if (active
->pipe_enabled
) {
4229 u32 tmp
= hw
->wm_pipe
[pipe
];
4232 * For active pipes LP0 watermark is marked as
4233 * enabled, and LP1+ watermaks as disabled since
4234 * we can't really reverse compute them in case
4235 * multiple pipes are active.
4237 active
->wm
[0].enable
= true;
4238 active
->wm
[0].pri_val
= (tmp
& WM0_PIPE_PLANE_MASK
) >> WM0_PIPE_PLANE_SHIFT
;
4239 active
->wm
[0].spr_val
= (tmp
& WM0_PIPE_SPRITE_MASK
) >> WM0_PIPE_SPRITE_SHIFT
;
4240 active
->wm
[0].cur_val
= tmp
& WM0_PIPE_CURSOR_MASK
;
4241 active
->linetime
= hw
->wm_linetime
[pipe
];
4243 int level
, max_level
= ilk_wm_max_level(dev
);
4246 * For inactive pipes, all watermark levels
4247 * should be marked as enabled but zeroed,
4248 * which is what we'd compute them to.
4250 for (level
= 0; level
<= max_level
; level
++)
4251 active
->wm
[level
].enable
= true;
4254 intel_crtc
->wm
.active
.ilk
= *active
;
4257 #define _FW_WM(value, plane) \
4258 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
4259 #define _FW_WM_VLV(value, plane) \
4260 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
4262 static void vlv_read_wm_values(struct drm_i915_private
*dev_priv
,
4263 struct vlv_wm_values
*wm
)
4268 for_each_pipe(dev_priv
, pipe
) {
4269 tmp
= I915_READ(VLV_DDL(pipe
));
4271 wm
->ddl
[pipe
].primary
=
4272 (tmp
>> DDL_PLANE_SHIFT
) & (DDL_PRECISION_HIGH
| DRAIN_LATENCY_MASK
);
4273 wm
->ddl
[pipe
].cursor
=
4274 (tmp
>> DDL_CURSOR_SHIFT
) & (DDL_PRECISION_HIGH
| DRAIN_LATENCY_MASK
);
4275 wm
->ddl
[pipe
].sprite
[0] =
4276 (tmp
>> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH
| DRAIN_LATENCY_MASK
);
4277 wm
->ddl
[pipe
].sprite
[1] =
4278 (tmp
>> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH
| DRAIN_LATENCY_MASK
);
4281 tmp
= I915_READ(DSPFW1
);
4282 wm
->sr
.plane
= _FW_WM(tmp
, SR
);
4283 wm
->pipe
[PIPE_B
].cursor
= _FW_WM(tmp
, CURSORB
);
4284 wm
->pipe
[PIPE_B
].primary
= _FW_WM_VLV(tmp
, PLANEB
);
4285 wm
->pipe
[PIPE_A
].primary
= _FW_WM_VLV(tmp
, PLANEA
);
4287 tmp
= I915_READ(DSPFW2
);
4288 wm
->pipe
[PIPE_A
].sprite
[1] = _FW_WM_VLV(tmp
, SPRITEB
);
4289 wm
->pipe
[PIPE_A
].cursor
= _FW_WM(tmp
, CURSORA
);
4290 wm
->pipe
[PIPE_A
].sprite
[0] = _FW_WM_VLV(tmp
, SPRITEA
);
4292 tmp
= I915_READ(DSPFW3
);
4293 wm
->sr
.cursor
= _FW_WM(tmp
, CURSOR_SR
);
4295 if (IS_CHERRYVIEW(dev_priv
)) {
4296 tmp
= I915_READ(DSPFW7_CHV
);
4297 wm
->pipe
[PIPE_B
].sprite
[1] = _FW_WM_VLV(tmp
, SPRITED
);
4298 wm
->pipe
[PIPE_B
].sprite
[0] = _FW_WM_VLV(tmp
, SPRITEC
);
4300 tmp
= I915_READ(DSPFW8_CHV
);
4301 wm
->pipe
[PIPE_C
].sprite
[1] = _FW_WM_VLV(tmp
, SPRITEF
);
4302 wm
->pipe
[PIPE_C
].sprite
[0] = _FW_WM_VLV(tmp
, SPRITEE
);
4304 tmp
= I915_READ(DSPFW9_CHV
);
4305 wm
->pipe
[PIPE_C
].primary
= _FW_WM_VLV(tmp
, PLANEC
);
4306 wm
->pipe
[PIPE_C
].cursor
= _FW_WM(tmp
, CURSORC
);
4308 tmp
= I915_READ(DSPHOWM
);
4309 wm
->sr
.plane
|= _FW_WM(tmp
, SR_HI
) << 9;
4310 wm
->pipe
[PIPE_C
].sprite
[1] |= _FW_WM(tmp
, SPRITEF_HI
) << 8;
4311 wm
->pipe
[PIPE_C
].sprite
[0] |= _FW_WM(tmp
, SPRITEE_HI
) << 8;
4312 wm
->pipe
[PIPE_C
].primary
|= _FW_WM(tmp
, PLANEC_HI
) << 8;
4313 wm
->pipe
[PIPE_B
].sprite
[1] |= _FW_WM(tmp
, SPRITED_HI
) << 8;
4314 wm
->pipe
[PIPE_B
].sprite
[0] |= _FW_WM(tmp
, SPRITEC_HI
) << 8;
4315 wm
->pipe
[PIPE_B
].primary
|= _FW_WM(tmp
, PLANEB_HI
) << 8;
4316 wm
->pipe
[PIPE_A
].sprite
[1] |= _FW_WM(tmp
, SPRITEB_HI
) << 8;
4317 wm
->pipe
[PIPE_A
].sprite
[0] |= _FW_WM(tmp
, SPRITEA_HI
) << 8;
4318 wm
->pipe
[PIPE_A
].primary
|= _FW_WM(tmp
, PLANEA_HI
) << 8;
4320 tmp
= I915_READ(DSPFW7
);
4321 wm
->pipe
[PIPE_B
].sprite
[1] = _FW_WM_VLV(tmp
, SPRITED
);
4322 wm
->pipe
[PIPE_B
].sprite
[0] = _FW_WM_VLV(tmp
, SPRITEC
);
4324 tmp
= I915_READ(DSPHOWM
);
4325 wm
->sr
.plane
|= _FW_WM(tmp
, SR_HI
) << 9;
4326 wm
->pipe
[PIPE_B
].sprite
[1] |= _FW_WM(tmp
, SPRITED_HI
) << 8;
4327 wm
->pipe
[PIPE_B
].sprite
[0] |= _FW_WM(tmp
, SPRITEC_HI
) << 8;
4328 wm
->pipe
[PIPE_B
].primary
|= _FW_WM(tmp
, PLANEB_HI
) << 8;
4329 wm
->pipe
[PIPE_A
].sprite
[1] |= _FW_WM(tmp
, SPRITEB_HI
) << 8;
4330 wm
->pipe
[PIPE_A
].sprite
[0] |= _FW_WM(tmp
, SPRITEA_HI
) << 8;
4331 wm
->pipe
[PIPE_A
].primary
|= _FW_WM(tmp
, PLANEA_HI
) << 8;
4338 void vlv_wm_get_hw_state(struct drm_device
*dev
)
4340 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4341 struct vlv_wm_values
*wm
= &dev_priv
->wm
.vlv
;
4342 struct intel_plane
*plane
;
4346 vlv_read_wm_values(dev_priv
, wm
);
4348 for_each_intel_plane(dev
, plane
) {
4349 switch (plane
->base
.type
) {
4351 case DRM_PLANE_TYPE_CURSOR
:
4352 plane
->wm
.fifo_size
= 63;
4354 case DRM_PLANE_TYPE_PRIMARY
:
4355 plane
->wm
.fifo_size
= vlv_get_fifo_size(dev
, plane
->pipe
, 0);
4357 case DRM_PLANE_TYPE_OVERLAY
:
4358 sprite
= plane
->plane
;
4359 plane
->wm
.fifo_size
= vlv_get_fifo_size(dev
, plane
->pipe
, sprite
+ 1);
4364 wm
->cxsr
= I915_READ(FW_BLC_SELF_VLV
) & FW_CSPWRDWNEN
;
4365 wm
->level
= VLV_WM_LEVEL_PM2
;
4367 if (IS_CHERRYVIEW(dev_priv
)) {
4368 mutex_lock(&dev_priv
->rps
.hw_lock
);
4370 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
4371 if (val
& DSP_MAXFIFO_PM5_ENABLE
)
4372 wm
->level
= VLV_WM_LEVEL_PM5
;
4375 * If DDR DVFS is disabled in the BIOS, Punit
4376 * will never ack the request. So if that happens
4377 * assume we don't have to enable/disable DDR DVFS
4378 * dynamically. To test that just set the REQ_ACK
4379 * bit to poke the Punit, but don't change the
4380 * HIGH/LOW bits so that we don't actually change
4381 * the current state.
4383 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DDR_SETUP2
);
4384 val
|= FORCE_DDR_FREQ_REQ_ACK
;
4385 vlv_punit_write(dev_priv
, PUNIT_REG_DDR_SETUP2
, val
);
4387 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DDR_SETUP2
) &
4388 FORCE_DDR_FREQ_REQ_ACK
) == 0, 3)) {
4389 DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4390 "assuming DDR DVFS is disabled\n");
4391 dev_priv
->wm
.max_level
= VLV_WM_LEVEL_PM5
;
4393 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DDR_SETUP2
);
4394 if ((val
& FORCE_DDR_HIGH_FREQ
) == 0)
4395 wm
->level
= VLV_WM_LEVEL_DDR_DVFS
;
4398 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4401 for_each_pipe(dev_priv
, pipe
)
4402 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4403 pipe_name(pipe
), wm
->pipe
[pipe
].primary
, wm
->pipe
[pipe
].cursor
,
4404 wm
->pipe
[pipe
].sprite
[0], wm
->pipe
[pipe
].sprite
[1]);
4406 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4407 wm
->sr
.plane
, wm
->sr
.cursor
, wm
->level
, wm
->cxsr
);
4410 void ilk_wm_get_hw_state(struct drm_device
*dev
)
4412 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4413 struct ilk_wm_values
*hw
= &dev_priv
->wm
.hw
;
4414 struct drm_crtc
*crtc
;
4416 for_each_crtc(dev
, crtc
)
4417 ilk_pipe_wm_get_hw_state(crtc
);
4419 hw
->wm_lp
[0] = I915_READ(WM1_LP_ILK
);
4420 hw
->wm_lp
[1] = I915_READ(WM2_LP_ILK
);
4421 hw
->wm_lp
[2] = I915_READ(WM3_LP_ILK
);
4423 hw
->wm_lp_spr
[0] = I915_READ(WM1S_LP_ILK
);
4424 if (INTEL_INFO(dev
)->gen
>= 7) {
4425 hw
->wm_lp_spr
[1] = I915_READ(WM2S_LP_IVB
);
4426 hw
->wm_lp_spr
[2] = I915_READ(WM3S_LP_IVB
);
4429 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
4430 hw
->partitioning
= (I915_READ(WM_MISC
) & WM_MISC_DATA_PARTITION_5_6
) ?
4431 INTEL_DDB_PART_5_6
: INTEL_DDB_PART_1_2
;
4432 else if (IS_IVYBRIDGE(dev
))
4433 hw
->partitioning
= (I915_READ(DISP_ARB_CTL2
) & DISP_DATA_PARTITION_5_6
) ?
4434 INTEL_DDB_PART_5_6
: INTEL_DDB_PART_1_2
;
4437 !(I915_READ(DISP_ARB_CTL
) & DISP_FBC_WM_DIS
);
4441 * intel_update_watermarks - update FIFO watermark values based on current modes
4443 * Calculate watermark values for the various WM regs based on current mode
4444 * and plane configuration.
4446 * There are several cases to deal with here:
4447 * - normal (i.e. non-self-refresh)
4448 * - self-refresh (SR) mode
4449 * - lines are large relative to FIFO size (buffer can hold up to 2)
4450 * - lines are small relative to FIFO size (buffer can hold more than 2
4451 * lines), so need to account for TLB latency
4453 * The normal calculation is:
4454 * watermark = dotclock * bytes per pixel * latency
4455 * where latency is platform & configuration dependent (we assume pessimal
4458 * The SR calculation is:
4459 * watermark = (trunc(latency/line time)+1) * surface width *
4462 * line time = htotal / dotclock
4463 * surface width = hdisplay for normal plane and 64 for cursor
4464 * and latency is assumed to be high, as above.
4466 * The final value programmed to the register should always be rounded up,
4467 * and include an extra 2 entries to account for clock crossings.
4469 * We don't use the sprite, so we can ignore that. And on Crestline we have
4470 * to set the non-SR watermarks to 8.
4472 void intel_update_watermarks(struct drm_crtc
*crtc
)
4474 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
4476 if (dev_priv
->display
.update_wm
)
4477 dev_priv
->display
.update_wm(crtc
);
4481 * Lock protecting IPS related data structures
4483 DEFINE_SPINLOCK(mchdev_lock
);
4485 /* Global for IPS driver to get at the current i915 device. Protected by
4487 static struct drm_i915_private
*i915_mch_dev
;
4489 bool ironlake_set_drps(struct drm_i915_private
*dev_priv
, u8 val
)
4493 assert_spin_locked(&mchdev_lock
);
4495 rgvswctl
= I915_READ16(MEMSWCTL
);
4496 if (rgvswctl
& MEMCTL_CMD_STS
) {
4497 DRM_DEBUG("gpu busy, RCS change rejected\n");
4498 return false; /* still busy with another command */
4501 rgvswctl
= (MEMCTL_CMD_CHFREQ
<< MEMCTL_CMD_SHIFT
) |
4502 (val
<< MEMCTL_FREQ_SHIFT
) | MEMCTL_SFCAVM
;
4503 I915_WRITE16(MEMSWCTL
, rgvswctl
);
4504 POSTING_READ16(MEMSWCTL
);
4506 rgvswctl
|= MEMCTL_CMD_STS
;
4507 I915_WRITE16(MEMSWCTL
, rgvswctl
);
4512 static void ironlake_enable_drps(struct drm_i915_private
*dev_priv
)
4515 u8 fmax
, fmin
, fstart
, vstart
;
4517 spin_lock_irq(&mchdev_lock
);
4519 rgvmodectl
= I915_READ(MEMMODECTL
);
4521 /* Enable temp reporting */
4522 I915_WRITE16(PMMISC
, I915_READ(PMMISC
) | MCPPCE_EN
);
4523 I915_WRITE16(TSC1
, I915_READ(TSC1
) | TSE
);
4525 /* 100ms RC evaluation intervals */
4526 I915_WRITE(RCUPEI
, 100000);
4527 I915_WRITE(RCDNEI
, 100000);
4529 /* Set max/min thresholds to 90ms and 80ms respectively */
4530 I915_WRITE(RCBMAXAVG
, 90000);
4531 I915_WRITE(RCBMINAVG
, 80000);
4533 I915_WRITE(MEMIHYST
, 1);
4535 /* Set up min, max, and cur for interrupt handling */
4536 fmax
= (rgvmodectl
& MEMMODE_FMAX_MASK
) >> MEMMODE_FMAX_SHIFT
;
4537 fmin
= (rgvmodectl
& MEMMODE_FMIN_MASK
);
4538 fstart
= (rgvmodectl
& MEMMODE_FSTART_MASK
) >>
4539 MEMMODE_FSTART_SHIFT
;
4541 vstart
= (I915_READ(PXVFREQ(fstart
)) & PXVFREQ_PX_MASK
) >>
4544 dev_priv
->ips
.fmax
= fmax
; /* IPS callback will increase this */
4545 dev_priv
->ips
.fstart
= fstart
;
4547 dev_priv
->ips
.max_delay
= fstart
;
4548 dev_priv
->ips
.min_delay
= fmin
;
4549 dev_priv
->ips
.cur_delay
= fstart
;
4551 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4552 fmax
, fmin
, fstart
);
4554 I915_WRITE(MEMINTREN
, MEMINT_CX_SUPR_EN
| MEMINT_EVAL_CHG_EN
);
4557 * Interrupts will be enabled in ironlake_irq_postinstall
4560 I915_WRITE(VIDSTART
, vstart
);
4561 POSTING_READ(VIDSTART
);
4563 rgvmodectl
|= MEMMODE_SWMODE_EN
;
4564 I915_WRITE(MEMMODECTL
, rgvmodectl
);
4566 if (wait_for_atomic((I915_READ(MEMSWCTL
) & MEMCTL_CMD_STS
) == 0, 10))
4567 DRM_ERROR("stuck trying to change perf mode\n");
4570 ironlake_set_drps(dev_priv
, fstart
);
4572 dev_priv
->ips
.last_count1
= I915_READ(DMIEC
) +
4573 I915_READ(DDREC
) + I915_READ(CSIEC
);
4574 dev_priv
->ips
.last_time1
= jiffies_to_msecs(jiffies
);
4575 dev_priv
->ips
.last_count2
= I915_READ(GFXEC
);
4576 dev_priv
->ips
.last_time2
= ktime_get_raw_ns();
4578 spin_unlock_irq(&mchdev_lock
);
4581 static void ironlake_disable_drps(struct drm_i915_private
*dev_priv
)
4585 spin_lock_irq(&mchdev_lock
);
4587 rgvswctl
= I915_READ16(MEMSWCTL
);
4589 /* Ack interrupts, disable EFC interrupt */
4590 I915_WRITE(MEMINTREN
, I915_READ(MEMINTREN
) & ~MEMINT_EVAL_CHG_EN
);
4591 I915_WRITE(MEMINTRSTS
, MEMINT_EVAL_CHG
);
4592 I915_WRITE(DEIER
, I915_READ(DEIER
) & ~DE_PCU_EVENT
);
4593 I915_WRITE(DEIIR
, DE_PCU_EVENT
);
4594 I915_WRITE(DEIMR
, I915_READ(DEIMR
) | DE_PCU_EVENT
);
4596 /* Go back to the starting frequency */
4597 ironlake_set_drps(dev_priv
, dev_priv
->ips
.fstart
);
4599 rgvswctl
|= MEMCTL_CMD_STS
;
4600 I915_WRITE(MEMSWCTL
, rgvswctl
);
4603 spin_unlock_irq(&mchdev_lock
);
4606 /* There's a funny hw issue where the hw returns all 0 when reading from
4607 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4608 * ourselves, instead of doing a rmw cycle (which might result in us clearing
4609 * all limits and the gpu stuck at whatever frequency it is at atm).
4611 static u32
intel_rps_limits(struct drm_i915_private
*dev_priv
, u8 val
)
4615 /* Only set the down limit when we've reached the lowest level to avoid
4616 * getting more interrupts, otherwise leave this clear. This prevents a
4617 * race in the hw when coming out of rc6: There's a tiny window where
4618 * the hw runs at the minimal clock before selecting the desired
4619 * frequency, if the down threshold expires in that window we will not
4620 * receive a down interrupt. */
4621 if (IS_GEN9(dev_priv
)) {
4622 limits
= (dev_priv
->rps
.max_freq_softlimit
) << 23;
4623 if (val
<= dev_priv
->rps
.min_freq_softlimit
)
4624 limits
|= (dev_priv
->rps
.min_freq_softlimit
) << 14;
4626 limits
= dev_priv
->rps
.max_freq_softlimit
<< 24;
4627 if (val
<= dev_priv
->rps
.min_freq_softlimit
)
4628 limits
|= dev_priv
->rps
.min_freq_softlimit
<< 16;
4634 static void gen6_set_rps_thresholds(struct drm_i915_private
*dev_priv
, u8 val
)
4637 u32 threshold_up
= 0, threshold_down
= 0; /* in % */
4638 u32 ei_up
= 0, ei_down
= 0;
4640 new_power
= dev_priv
->rps
.power
;
4641 switch (dev_priv
->rps
.power
) {
4643 if (val
> dev_priv
->rps
.efficient_freq
+ 1 && val
> dev_priv
->rps
.cur_freq
)
4644 new_power
= BETWEEN
;
4648 if (val
<= dev_priv
->rps
.efficient_freq
&& val
< dev_priv
->rps
.cur_freq
)
4649 new_power
= LOW_POWER
;
4650 else if (val
>= dev_priv
->rps
.rp0_freq
&& val
> dev_priv
->rps
.cur_freq
)
4651 new_power
= HIGH_POWER
;
4655 if (val
< (dev_priv
->rps
.rp1_freq
+ dev_priv
->rps
.rp0_freq
) >> 1 && val
< dev_priv
->rps
.cur_freq
)
4656 new_power
= BETWEEN
;
4659 /* Max/min bins are special */
4660 if (val
<= dev_priv
->rps
.min_freq_softlimit
)
4661 new_power
= LOW_POWER
;
4662 if (val
>= dev_priv
->rps
.max_freq_softlimit
)
4663 new_power
= HIGH_POWER
;
4664 if (new_power
== dev_priv
->rps
.power
)
4667 /* Note the units here are not exactly 1us, but 1280ns. */
4668 switch (new_power
) {
4670 /* Upclock if more than 95% busy over 16ms */
4674 /* Downclock if less than 85% busy over 32ms */
4676 threshold_down
= 85;
4680 /* Upclock if more than 90% busy over 13ms */
4684 /* Downclock if less than 75% busy over 32ms */
4686 threshold_down
= 75;
4690 /* Upclock if more than 85% busy over 10ms */
4694 /* Downclock if less than 60% busy over 32ms */
4696 threshold_down
= 60;
4700 I915_WRITE(GEN6_RP_UP_EI
,
4701 GT_INTERVAL_FROM_US(dev_priv
, ei_up
));
4702 I915_WRITE(GEN6_RP_UP_THRESHOLD
,
4703 GT_INTERVAL_FROM_US(dev_priv
, (ei_up
* threshold_up
/ 100)));
4705 I915_WRITE(GEN6_RP_DOWN_EI
,
4706 GT_INTERVAL_FROM_US(dev_priv
, ei_down
));
4707 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
,
4708 GT_INTERVAL_FROM_US(dev_priv
, (ei_down
* threshold_down
/ 100)));
4710 I915_WRITE(GEN6_RP_CONTROL
,
4711 GEN6_RP_MEDIA_TURBO
|
4712 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
4713 GEN6_RP_MEDIA_IS_GFX
|
4715 GEN6_RP_UP_BUSY_AVG
|
4716 GEN6_RP_DOWN_IDLE_AVG
);
4718 dev_priv
->rps
.power
= new_power
;
4719 dev_priv
->rps
.up_threshold
= threshold_up
;
4720 dev_priv
->rps
.down_threshold
= threshold_down
;
4721 dev_priv
->rps
.last_adj
= 0;
4724 static u32
gen6_rps_pm_mask(struct drm_i915_private
*dev_priv
, u8 val
)
4728 if (val
> dev_priv
->rps
.min_freq_softlimit
)
4729 mask
|= GEN6_PM_RP_DOWN_EI_EXPIRED
| GEN6_PM_RP_DOWN_THRESHOLD
| GEN6_PM_RP_DOWN_TIMEOUT
;
4730 if (val
< dev_priv
->rps
.max_freq_softlimit
)
4731 mask
|= GEN6_PM_RP_UP_EI_EXPIRED
| GEN6_PM_RP_UP_THRESHOLD
;
4733 mask
&= dev_priv
->pm_rps_events
;
4735 return gen6_sanitize_rps_pm_mask(dev_priv
, ~mask
);
4738 /* gen6_set_rps is called to update the frequency request, but should also be
4739 * called when the range (min_delay and max_delay) is modified so that we can
4740 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
4741 static void gen6_set_rps(struct drm_i915_private
*dev_priv
, u8 val
)
4743 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4744 if (IS_BXT_REVID(dev_priv
, 0, BXT_REVID_A1
))
4747 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
4748 WARN_ON(val
> dev_priv
->rps
.max_freq
);
4749 WARN_ON(val
< dev_priv
->rps
.min_freq
);
4751 /* min/max delay may still have been modified so be sure to
4752 * write the limits value.
4754 if (val
!= dev_priv
->rps
.cur_freq
) {
4755 gen6_set_rps_thresholds(dev_priv
, val
);
4757 if (IS_GEN9(dev_priv
))
4758 I915_WRITE(GEN6_RPNSWREQ
,
4759 GEN9_FREQUENCY(val
));
4760 else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
4761 I915_WRITE(GEN6_RPNSWREQ
,
4762 HSW_FREQUENCY(val
));
4764 I915_WRITE(GEN6_RPNSWREQ
,
4765 GEN6_FREQUENCY(val
) |
4767 GEN6_AGGRESSIVE_TURBO
);
4770 /* Make sure we continue to get interrupts
4771 * until we hit the minimum or maximum frequencies.
4773 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS
, intel_rps_limits(dev_priv
, val
));
4774 I915_WRITE(GEN6_PMINTRMSK
, gen6_rps_pm_mask(dev_priv
, val
));
4776 POSTING_READ(GEN6_RPNSWREQ
);
4778 dev_priv
->rps
.cur_freq
= val
;
4779 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv
, val
));
4782 static void valleyview_set_rps(struct drm_i915_private
*dev_priv
, u8 val
)
4784 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
4785 WARN_ON(val
> dev_priv
->rps
.max_freq
);
4786 WARN_ON(val
< dev_priv
->rps
.min_freq
);
4788 if (WARN_ONCE(IS_CHERRYVIEW(dev_priv
) && (val
& 1),
4789 "Odd GPU freq value\n"))
4792 I915_WRITE(GEN6_PMINTRMSK
, gen6_rps_pm_mask(dev_priv
, val
));
4794 if (val
!= dev_priv
->rps
.cur_freq
) {
4795 vlv_punit_write(dev_priv
, PUNIT_REG_GPU_FREQ_REQ
, val
);
4796 if (!IS_CHERRYVIEW(dev_priv
))
4797 gen6_set_rps_thresholds(dev_priv
, val
);
4800 dev_priv
->rps
.cur_freq
= val
;
4801 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv
, val
));
4804 /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
4806 * * If Gfx is Idle, then
4807 * 1. Forcewake Media well.
4808 * 2. Request idle freq.
4809 * 3. Release Forcewake of Media well.
4811 static void vlv_set_rps_idle(struct drm_i915_private
*dev_priv
)
4813 u32 val
= dev_priv
->rps
.idle_freq
;
4815 if (dev_priv
->rps
.cur_freq
<= val
)
4818 /* Wake up the media well, as that takes a lot less
4819 * power than the Render well. */
4820 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_MEDIA
);
4821 valleyview_set_rps(dev_priv
, val
);
4822 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_MEDIA
);
4825 void gen6_rps_busy(struct drm_i915_private
*dev_priv
)
4827 mutex_lock(&dev_priv
->rps
.hw_lock
);
4828 if (dev_priv
->rps
.enabled
) {
4829 if (dev_priv
->pm_rps_events
& (GEN6_PM_RP_DOWN_EI_EXPIRED
| GEN6_PM_RP_UP_EI_EXPIRED
))
4830 gen6_rps_reset_ei(dev_priv
);
4831 I915_WRITE(GEN6_PMINTRMSK
,
4832 gen6_rps_pm_mask(dev_priv
, dev_priv
->rps
.cur_freq
));
4834 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4837 void gen6_rps_idle(struct drm_i915_private
*dev_priv
)
4839 mutex_lock(&dev_priv
->rps
.hw_lock
);
4840 if (dev_priv
->rps
.enabled
) {
4841 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
4842 vlv_set_rps_idle(dev_priv
);
4844 gen6_set_rps(dev_priv
, dev_priv
->rps
.idle_freq
);
4845 dev_priv
->rps
.last_adj
= 0;
4846 I915_WRITE(GEN6_PMINTRMSK
, 0xffffffff);
4848 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4850 spin_lock(&dev_priv
->rps
.client_lock
);
4851 while (!list_empty(&dev_priv
->rps
.clients
))
4852 list_del_init(dev_priv
->rps
.clients
.next
);
4853 spin_unlock(&dev_priv
->rps
.client_lock
);
4856 void gen6_rps_boost(struct drm_i915_private
*dev_priv
,
4857 struct intel_rps_client
*rps
,
4858 unsigned long submitted
)
4860 /* This is intentionally racy! We peek at the state here, then
4861 * validate inside the RPS worker.
4863 if (!(dev_priv
->mm
.busy
&&
4864 dev_priv
->rps
.enabled
&&
4865 dev_priv
->rps
.cur_freq
< dev_priv
->rps
.max_freq_softlimit
))
4868 /* Force a RPS boost (and don't count it against the client) if
4869 * the GPU is severely congested.
4871 if (rps
&& time_after(jiffies
, submitted
+ DRM_I915_THROTTLE_JIFFIES
))
4874 spin_lock(&dev_priv
->rps
.client_lock
);
4875 if (rps
== NULL
|| list_empty(&rps
->link
)) {
4876 spin_lock_irq(&dev_priv
->irq_lock
);
4877 if (dev_priv
->rps
.interrupts_enabled
) {
4878 dev_priv
->rps
.client_boost
= true;
4879 queue_work(dev_priv
->wq
, &dev_priv
->rps
.work
);
4881 spin_unlock_irq(&dev_priv
->irq_lock
);
4884 list_add(&rps
->link
, &dev_priv
->rps
.clients
);
4887 dev_priv
->rps
.boosts
++;
4889 spin_unlock(&dev_priv
->rps
.client_lock
);
4892 void intel_set_rps(struct drm_i915_private
*dev_priv
, u8 val
)
4894 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
4895 valleyview_set_rps(dev_priv
, val
);
4897 gen6_set_rps(dev_priv
, val
);
4900 static void gen9_disable_rc6(struct drm_i915_private
*dev_priv
)
4902 I915_WRITE(GEN6_RC_CONTROL
, 0);
4903 I915_WRITE(GEN9_PG_ENABLE
, 0);
4906 static void gen9_disable_rps(struct drm_i915_private
*dev_priv
)
4908 I915_WRITE(GEN6_RP_CONTROL
, 0);
4911 static void gen6_disable_rps(struct drm_i915_private
*dev_priv
)
4913 I915_WRITE(GEN6_RC_CONTROL
, 0);
4914 I915_WRITE(GEN6_RPNSWREQ
, 1 << 31);
4915 I915_WRITE(GEN6_RP_CONTROL
, 0);
4918 static void cherryview_disable_rps(struct drm_i915_private
*dev_priv
)
4920 I915_WRITE(GEN6_RC_CONTROL
, 0);
4923 static void valleyview_disable_rps(struct drm_i915_private
*dev_priv
)
4925 /* we're doing forcewake before Disabling RC6,
4926 * This what the BIOS expects when going into suspend */
4927 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
4929 I915_WRITE(GEN6_RC_CONTROL
, 0);
4931 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
4934 static void intel_print_rc6_info(struct drm_i915_private
*dev_priv
, u32 mode
)
4936 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
4937 if (mode
& (GEN7_RC_CTL_TO_MODE
| GEN6_RC_CTL_EI_MODE(1)))
4938 mode
= GEN6_RC_CTL_RC6_ENABLE
;
4942 if (HAS_RC6p(dev_priv
))
4943 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
4944 onoff(mode
& GEN6_RC_CTL_RC6_ENABLE
),
4945 onoff(mode
& GEN6_RC_CTL_RC6p_ENABLE
),
4946 onoff(mode
& GEN6_RC_CTL_RC6pp_ENABLE
));
4949 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
4950 onoff(mode
& GEN6_RC_CTL_RC6_ENABLE
));
4953 static bool bxt_check_bios_rc6_setup(struct drm_i915_private
*dev_priv
)
4955 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
4956 bool enable_rc6
= true;
4957 unsigned long rc6_ctx_base
;
4959 if (!(I915_READ(RC6_LOCATION
) & RC6_CTX_IN_DRAM
)) {
4960 DRM_DEBUG_KMS("RC6 Base location not set properly.\n");
4965 * The exact context size is not known for BXT, so assume a page size
4968 rc6_ctx_base
= I915_READ(RC6_CTX_BASE
) & RC6_CTX_BASE_MASK
;
4969 if (!((rc6_ctx_base
>= ggtt
->stolen_reserved_base
) &&
4970 (rc6_ctx_base
+ PAGE_SIZE
<= ggtt
->stolen_reserved_base
+
4971 ggtt
->stolen_reserved_size
))) {
4972 DRM_DEBUG_KMS("RC6 Base address not as expected.\n");
4976 if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT
) & IDLE_TIME_MASK
) > 1) &&
4977 ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0
) & IDLE_TIME_MASK
) > 1) &&
4978 ((I915_READ(PWRCTX_MAXCNT_BCSUNIT
) & IDLE_TIME_MASK
) > 1) &&
4979 ((I915_READ(PWRCTX_MAXCNT_VECSUNIT
) & IDLE_TIME_MASK
) > 1))) {
4980 DRM_DEBUG_KMS("Engine Idle wait time not set properly.\n");
4984 if (!(I915_READ(GEN6_RC_CONTROL
) & (GEN6_RC_CTL_RC6_ENABLE
|
4985 GEN6_RC_CTL_HW_ENABLE
)) &&
4986 ((I915_READ(GEN6_RC_CONTROL
) & GEN6_RC_CTL_HW_ENABLE
) ||
4987 !(I915_READ(GEN6_RC_STATE
) & RC6_STATE
))) {
4988 DRM_DEBUG_KMS("HW/SW RC6 is not enabled by BIOS.\n");
4995 int sanitize_rc6_option(struct drm_i915_private
*dev_priv
, int enable_rc6
)
4997 /* No RC6 before Ironlake and code is gone for ilk. */
4998 if (INTEL_INFO(dev_priv
)->gen
< 6)
5004 if (IS_BROXTON(dev_priv
) && !bxt_check_bios_rc6_setup(dev_priv
)) {
5005 DRM_INFO("RC6 disabled by BIOS\n");
5009 /* Respect the kernel parameter if it is set */
5010 if (enable_rc6
>= 0) {
5013 if (HAS_RC6p(dev_priv
))
5014 mask
= INTEL_RC6_ENABLE
| INTEL_RC6p_ENABLE
|
5017 mask
= INTEL_RC6_ENABLE
;
5019 if ((enable_rc6
& mask
) != enable_rc6
)
5020 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
5021 enable_rc6
& mask
, enable_rc6
, mask
);
5023 return enable_rc6
& mask
;
5026 if (IS_IVYBRIDGE(dev_priv
))
5027 return (INTEL_RC6_ENABLE
| INTEL_RC6p_ENABLE
);
5029 return INTEL_RC6_ENABLE
;
5032 static void gen6_init_rps_frequencies(struct drm_i915_private
*dev_priv
)
5034 uint32_t rp_state_cap
;
5035 u32 ddcc_status
= 0;
5038 /* All of these values are in units of 50MHz */
5039 dev_priv
->rps
.cur_freq
= 0;
5040 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
5041 if (IS_BROXTON(dev_priv
)) {
5042 rp_state_cap
= I915_READ(BXT_RP_STATE_CAP
);
5043 dev_priv
->rps
.rp0_freq
= (rp_state_cap
>> 16) & 0xff;
5044 dev_priv
->rps
.rp1_freq
= (rp_state_cap
>> 8) & 0xff;
5045 dev_priv
->rps
.min_freq
= (rp_state_cap
>> 0) & 0xff;
5047 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
5048 dev_priv
->rps
.rp0_freq
= (rp_state_cap
>> 0) & 0xff;
5049 dev_priv
->rps
.rp1_freq
= (rp_state_cap
>> 8) & 0xff;
5050 dev_priv
->rps
.min_freq
= (rp_state_cap
>> 16) & 0xff;
5053 /* hw_max = RP0 until we check for overclocking */
5054 dev_priv
->rps
.max_freq
= dev_priv
->rps
.rp0_freq
;
5056 dev_priv
->rps
.efficient_freq
= dev_priv
->rps
.rp1_freq
;
5057 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
) ||
5058 IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
)) {
5059 ret
= sandybridge_pcode_read(dev_priv
,
5060 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL
,
5063 dev_priv
->rps
.efficient_freq
=
5065 ((ddcc_status
>> 8) & 0xff),
5066 dev_priv
->rps
.min_freq
,
5067 dev_priv
->rps
.max_freq
);
5070 if (IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
)) {
5071 /* Store the frequency values in 16.66 MHZ units, which is
5072 the natural hardware unit for SKL */
5073 dev_priv
->rps
.rp0_freq
*= GEN9_FREQ_SCALER
;
5074 dev_priv
->rps
.rp1_freq
*= GEN9_FREQ_SCALER
;
5075 dev_priv
->rps
.min_freq
*= GEN9_FREQ_SCALER
;
5076 dev_priv
->rps
.max_freq
*= GEN9_FREQ_SCALER
;
5077 dev_priv
->rps
.efficient_freq
*= GEN9_FREQ_SCALER
;
5080 dev_priv
->rps
.idle_freq
= dev_priv
->rps
.min_freq
;
5082 /* Preserve min/max settings in case of re-init */
5083 if (dev_priv
->rps
.max_freq_softlimit
== 0)
5084 dev_priv
->rps
.max_freq_softlimit
= dev_priv
->rps
.max_freq
;
5086 if (dev_priv
->rps
.min_freq_softlimit
== 0) {
5087 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
5088 dev_priv
->rps
.min_freq_softlimit
=
5089 max_t(int, dev_priv
->rps
.efficient_freq
,
5090 intel_freq_opcode(dev_priv
, 450));
5092 dev_priv
->rps
.min_freq_softlimit
=
5093 dev_priv
->rps
.min_freq
;
5097 /* See the Gen9_GT_PM_Programming_Guide doc for the below */
5098 static void gen9_enable_rps(struct drm_i915_private
*dev_priv
)
5100 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
5102 gen6_init_rps_frequencies(dev_priv
);
5104 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
5105 if (IS_BXT_REVID(dev_priv
, 0, BXT_REVID_A1
)) {
5107 * BIOS could leave the Hw Turbo enabled, so need to explicitly
5108 * clear out the Control register just to avoid inconsitency
5109 * with debugfs interface, which will show Turbo as enabled
5110 * only and that is not expected by the User after adding the
5111 * WaGsvDisableTurbo. Apart from this there is no problem even
5112 * if the Turbo is left enabled in the Control register, as the
5113 * Up/Down interrupts would remain masked.
5115 gen9_disable_rps(dev_priv
);
5116 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
5120 /* Program defaults and thresholds for RPS*/
5121 I915_WRITE(GEN6_RC_VIDEO_FREQ
,
5122 GEN9_FREQUENCY(dev_priv
->rps
.rp1_freq
));
5124 /* 1 second timeout*/
5125 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
,
5126 GT_INTERVAL_FROM_US(dev_priv
, 1000000));
5128 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 0xa);
5130 /* Leaning on the below call to gen6_set_rps to program/setup the
5131 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
5132 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
5133 dev_priv
->rps
.power
= HIGH_POWER
; /* force a reset */
5134 gen6_set_rps(dev_priv
, dev_priv
->rps
.idle_freq
);
5136 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
5139 static void gen9_enable_rc6(struct drm_i915_private
*dev_priv
)
5141 struct intel_engine_cs
*engine
;
5142 uint32_t rc6_mask
= 0;
5144 /* 1a: Software RC state - RC0 */
5145 I915_WRITE(GEN6_RC_STATE
, 0);
5147 /* 1b: Get forcewake during program sequence. Although the driver
5148 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5149 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
5151 /* 2a: Disable RC states. */
5152 I915_WRITE(GEN6_RC_CONTROL
, 0);
5154 /* 2b: Program RC6 thresholds.*/
5156 /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
5157 if (IS_SKYLAKE(dev_priv
))
5158 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 108 << 16);
5160 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 54 << 16);
5161 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000); /* 12500 * 1280ns */
5162 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25); /* 25 * 1280ns */
5163 for_each_engine(engine
, dev_priv
)
5164 I915_WRITE(RING_MAX_IDLE(engine
->mmio_base
), 10);
5166 if (HAS_GUC(dev_priv
))
5167 I915_WRITE(GUC_MAX_IDLE_COUNT
, 0xA);
5169 I915_WRITE(GEN6_RC_SLEEP
, 0);
5171 /* 2c: Program Coarse Power Gating Policies. */
5172 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS
, 25);
5173 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS
, 25);
5175 /* 3a: Enable RC6 */
5176 if (intel_enable_rc6() & INTEL_RC6_ENABLE
)
5177 rc6_mask
= GEN6_RC_CTL_RC6_ENABLE
;
5178 DRM_INFO("RC6 %s\n", onoff(rc6_mask
& GEN6_RC_CTL_RC6_ENABLE
));
5179 /* WaRsUseTimeoutMode */
5180 if (IS_SKL_REVID(dev_priv
, 0, SKL_REVID_D0
) ||
5181 IS_BXT_REVID(dev_priv
, 0, BXT_REVID_A1
)) {
5182 I915_WRITE(GEN6_RC6_THRESHOLD
, 625); /* 800us */
5183 I915_WRITE(GEN6_RC_CONTROL
, GEN6_RC_CTL_HW_ENABLE
|
5184 GEN7_RC_CTL_TO_MODE
|
5187 I915_WRITE(GEN6_RC6_THRESHOLD
, 37500); /* 37.5/125ms per EI */
5188 I915_WRITE(GEN6_RC_CONTROL
, GEN6_RC_CTL_HW_ENABLE
|
5189 GEN6_RC_CTL_EI_MODE(1) |
5194 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
5195 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
5197 if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv
))
5198 I915_WRITE(GEN9_PG_ENABLE
, 0);
5200 I915_WRITE(GEN9_PG_ENABLE
, (rc6_mask
& GEN6_RC_CTL_RC6_ENABLE
) ?
5201 (GEN9_RENDER_PG_ENABLE
| GEN9_MEDIA_PG_ENABLE
) : 0);
5203 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
5206 static void gen8_enable_rps(struct drm_i915_private
*dev_priv
)
5208 struct intel_engine_cs
*engine
;
5209 uint32_t rc6_mask
= 0;
5211 /* 1a: Software RC state - RC0 */
5212 I915_WRITE(GEN6_RC_STATE
, 0);
5214 /* 1c & 1d: Get forcewake during program sequence. Although the driver
5215 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5216 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
5218 /* 2a: Disable RC states. */
5219 I915_WRITE(GEN6_RC_CONTROL
, 0);
5221 /* Initialize rps frequencies */
5222 gen6_init_rps_frequencies(dev_priv
);
5224 /* 2b: Program RC6 thresholds.*/
5225 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 40 << 16);
5226 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000); /* 12500 * 1280ns */
5227 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25); /* 25 * 1280ns */
5228 for_each_engine(engine
, dev_priv
)
5229 I915_WRITE(RING_MAX_IDLE(engine
->mmio_base
), 10);
5230 I915_WRITE(GEN6_RC_SLEEP
, 0);
5231 if (IS_BROADWELL(dev_priv
))
5232 I915_WRITE(GEN6_RC6_THRESHOLD
, 625); /* 800us/1.28 for TO */
5234 I915_WRITE(GEN6_RC6_THRESHOLD
, 50000); /* 50/125ms per EI */
5237 if (intel_enable_rc6() & INTEL_RC6_ENABLE
)
5238 rc6_mask
= GEN6_RC_CTL_RC6_ENABLE
;
5239 intel_print_rc6_info(dev_priv
, rc6_mask
);
5240 if (IS_BROADWELL(dev_priv
))
5241 I915_WRITE(GEN6_RC_CONTROL
, GEN6_RC_CTL_HW_ENABLE
|
5242 GEN7_RC_CTL_TO_MODE
|
5245 I915_WRITE(GEN6_RC_CONTROL
, GEN6_RC_CTL_HW_ENABLE
|
5246 GEN6_RC_CTL_EI_MODE(1) |
5249 /* 4 Program defaults and thresholds for RPS*/
5250 I915_WRITE(GEN6_RPNSWREQ
,
5251 HSW_FREQUENCY(dev_priv
->rps
.rp1_freq
));
5252 I915_WRITE(GEN6_RC_VIDEO_FREQ
,
5253 HSW_FREQUENCY(dev_priv
->rps
.rp1_freq
));
5254 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
5255 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 100000000 / 128); /* 1 second timeout */
5257 /* Docs recommend 900MHz, and 300 MHz respectively */
5258 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS
,
5259 dev_priv
->rps
.max_freq_softlimit
<< 24 |
5260 dev_priv
->rps
.min_freq_softlimit
<< 16);
5262 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 7600000 / 128); /* 76ms busyness per EI, 90% */
5263 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 31300000 / 128); /* 313ms busyness per EI, 70%*/
5264 I915_WRITE(GEN6_RP_UP_EI
, 66000); /* 84.48ms, XXX: random? */
5265 I915_WRITE(GEN6_RP_DOWN_EI
, 350000); /* 448ms, XXX: random? */
5267 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
5270 I915_WRITE(GEN6_RP_CONTROL
,
5271 GEN6_RP_MEDIA_TURBO
|
5272 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
5273 GEN6_RP_MEDIA_IS_GFX
|
5275 GEN6_RP_UP_BUSY_AVG
|
5276 GEN6_RP_DOWN_IDLE_AVG
);
5278 /* 6: Ring frequency + overclocking (our driver does this later */
5280 dev_priv
->rps
.power
= HIGH_POWER
; /* force a reset */
5281 gen6_set_rps(dev_priv
, dev_priv
->rps
.idle_freq
);
5283 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
5286 static void gen6_enable_rps(struct drm_i915_private
*dev_priv
)
5288 struct intel_engine_cs
*engine
;
5289 u32 rc6vids
, pcu_mbox
= 0, rc6_mask
= 0;
5294 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
5296 /* Here begins a magic sequence of register writes to enable
5297 * auto-downclocking.
5299 * Perhaps there might be some value in exposing these to
5302 I915_WRITE(GEN6_RC_STATE
, 0);
5304 /* Clear the DBG now so we don't confuse earlier errors */
5305 gtfifodbg
= I915_READ(GTFIFODBG
);
5307 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg
);
5308 I915_WRITE(GTFIFODBG
, gtfifodbg
);
5311 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
5313 /* Initialize rps frequencies */
5314 gen6_init_rps_frequencies(dev_priv
);
5316 /* disable the counters and set deterministic thresholds */
5317 I915_WRITE(GEN6_RC_CONTROL
, 0);
5319 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT
, 1000 << 16);
5320 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 40 << 16 | 30);
5321 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT
, 30);
5322 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000);
5323 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25);
5325 for_each_engine(engine
, dev_priv
)
5326 I915_WRITE(RING_MAX_IDLE(engine
->mmio_base
), 10);
5328 I915_WRITE(GEN6_RC_SLEEP
, 0);
5329 I915_WRITE(GEN6_RC1e_THRESHOLD
, 1000);
5330 if (IS_IVYBRIDGE(dev_priv
))
5331 I915_WRITE(GEN6_RC6_THRESHOLD
, 125000);
5333 I915_WRITE(GEN6_RC6_THRESHOLD
, 50000);
5334 I915_WRITE(GEN6_RC6p_THRESHOLD
, 150000);
5335 I915_WRITE(GEN6_RC6pp_THRESHOLD
, 64000); /* unused */
5337 /* Check if we are enabling RC6 */
5338 rc6_mode
= intel_enable_rc6();
5339 if (rc6_mode
& INTEL_RC6_ENABLE
)
5340 rc6_mask
|= GEN6_RC_CTL_RC6_ENABLE
;
5342 /* We don't use those on Haswell */
5343 if (!IS_HASWELL(dev_priv
)) {
5344 if (rc6_mode
& INTEL_RC6p_ENABLE
)
5345 rc6_mask
|= GEN6_RC_CTL_RC6p_ENABLE
;
5347 if (rc6_mode
& INTEL_RC6pp_ENABLE
)
5348 rc6_mask
|= GEN6_RC_CTL_RC6pp_ENABLE
;
5351 intel_print_rc6_info(dev_priv
, rc6_mask
);
5353 I915_WRITE(GEN6_RC_CONTROL
,
5355 GEN6_RC_CTL_EI_MODE(1) |
5356 GEN6_RC_CTL_HW_ENABLE
);
5358 /* Power down if completely idle for over 50ms */
5359 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 50000);
5360 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
5362 ret
= sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_MIN_FREQ_TABLE
, 0);
5364 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
5366 ret
= sandybridge_pcode_read(dev_priv
, GEN6_READ_OC_PARAMS
, &pcu_mbox
);
5367 if (!ret
&& (pcu_mbox
& (1<<31))) { /* OC supported */
5368 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
5369 (dev_priv
->rps
.max_freq_softlimit
& 0xff) * 50,
5370 (pcu_mbox
& 0xff) * 50);
5371 dev_priv
->rps
.max_freq
= pcu_mbox
& 0xff;
5374 dev_priv
->rps
.power
= HIGH_POWER
; /* force a reset */
5375 gen6_set_rps(dev_priv
, dev_priv
->rps
.idle_freq
);
5378 ret
= sandybridge_pcode_read(dev_priv
, GEN6_PCODE_READ_RC6VIDS
, &rc6vids
);
5379 if (IS_GEN6(dev_priv
) && ret
) {
5380 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
5381 } else if (IS_GEN6(dev_priv
) && (GEN6_DECODE_RC6_VID(rc6vids
& 0xff) < 450)) {
5382 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5383 GEN6_DECODE_RC6_VID(rc6vids
& 0xff), 450);
5384 rc6vids
&= 0xffff00;
5385 rc6vids
|= GEN6_ENCODE_RC6_VID(450);
5386 ret
= sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_RC6VIDS
, rc6vids
);
5388 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5391 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
5394 static void __gen6_update_ring_freq(struct drm_i915_private
*dev_priv
)
5397 unsigned int gpu_freq
;
5398 unsigned int max_ia_freq
, min_ring_freq
;
5399 unsigned int max_gpu_freq
, min_gpu_freq
;
5400 int scaling_factor
= 180;
5401 struct cpufreq_policy
*policy
;
5403 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
5405 policy
= cpufreq_cpu_get(0);
5407 max_ia_freq
= policy
->cpuinfo
.max_freq
;
5408 cpufreq_cpu_put(policy
);
5411 * Default to measured freq if none found, PCU will ensure we
5414 max_ia_freq
= tsc_khz
;
5417 /* Convert from kHz to MHz */
5418 max_ia_freq
/= 1000;
5420 min_ring_freq
= I915_READ(DCLK
) & 0xf;
5421 /* convert DDR frequency from units of 266.6MHz to bandwidth */
5422 min_ring_freq
= mult_frac(min_ring_freq
, 8, 3);
5424 if (IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
)) {
5425 /* Convert GT frequency to 50 HZ units */
5426 min_gpu_freq
= dev_priv
->rps
.min_freq
/ GEN9_FREQ_SCALER
;
5427 max_gpu_freq
= dev_priv
->rps
.max_freq
/ GEN9_FREQ_SCALER
;
5429 min_gpu_freq
= dev_priv
->rps
.min_freq
;
5430 max_gpu_freq
= dev_priv
->rps
.max_freq
;
5434 * For each potential GPU frequency, load a ring frequency we'd like
5435 * to use for memory access. We do this by specifying the IA frequency
5436 * the PCU should use as a reference to determine the ring frequency.
5438 for (gpu_freq
= max_gpu_freq
; gpu_freq
>= min_gpu_freq
; gpu_freq
--) {
5439 int diff
= max_gpu_freq
- gpu_freq
;
5440 unsigned int ia_freq
= 0, ring_freq
= 0;
5442 if (IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
)) {
5444 * ring_freq = 2 * GT. ring_freq is in 100MHz units
5445 * No floor required for ring frequency on SKL.
5447 ring_freq
= gpu_freq
;
5448 } else if (INTEL_INFO(dev_priv
)->gen
>= 8) {
5449 /* max(2 * GT, DDR). NB: GT is 50MHz units */
5450 ring_freq
= max(min_ring_freq
, gpu_freq
);
5451 } else if (IS_HASWELL(dev_priv
)) {
5452 ring_freq
= mult_frac(gpu_freq
, 5, 4);
5453 ring_freq
= max(min_ring_freq
, ring_freq
);
5454 /* leave ia_freq as the default, chosen by cpufreq */
5456 /* On older processors, there is no separate ring
5457 * clock domain, so in order to boost the bandwidth
5458 * of the ring, we need to upclock the CPU (ia_freq).
5460 * For GPU frequencies less than 750MHz,
5461 * just use the lowest ring freq.
5463 if (gpu_freq
< min_freq
)
5466 ia_freq
= max_ia_freq
- ((diff
* scaling_factor
) / 2);
5467 ia_freq
= DIV_ROUND_CLOSEST(ia_freq
, 100);
5470 sandybridge_pcode_write(dev_priv
,
5471 GEN6_PCODE_WRITE_MIN_FREQ_TABLE
,
5472 ia_freq
<< GEN6_PCODE_FREQ_IA_RATIO_SHIFT
|
5473 ring_freq
<< GEN6_PCODE_FREQ_RING_RATIO_SHIFT
|
5478 void gen6_update_ring_freq(struct drm_i915_private
*dev_priv
)
5480 if (!HAS_CORE_RING_FREQ(dev_priv
))
5483 mutex_lock(&dev_priv
->rps
.hw_lock
);
5484 __gen6_update_ring_freq(dev_priv
);
5485 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5488 static int cherryview_rps_max_freq(struct drm_i915_private
*dev_priv
)
5492 val
= vlv_punit_read(dev_priv
, FB_GFX_FMAX_AT_VMAX_FUSE
);
5494 switch (INTEL_INFO(dev_priv
)->eu_total
) {
5496 /* (2 * 4) config */
5497 rp0
= (val
>> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT
);
5500 /* (2 * 6) config */
5501 rp0
= (val
>> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT
);
5504 /* (2 * 8) config */
5506 /* Setting (2 * 8) Min RP0 for any other combination */
5507 rp0
= (val
>> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT
);
5511 rp0
= (rp0
& FB_GFX_FREQ_FUSE_MASK
);
5516 static int cherryview_rps_rpe_freq(struct drm_i915_private
*dev_priv
)
5520 val
= vlv_punit_read(dev_priv
, PUNIT_GPU_DUTYCYCLE_REG
);
5521 rpe
= (val
>> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT
) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK
;
5526 static int cherryview_rps_guar_freq(struct drm_i915_private
*dev_priv
)
5530 val
= vlv_punit_read(dev_priv
, FB_GFX_FMAX_AT_VMAX_FUSE
);
5531 rp1
= (val
& FB_GFX_FREQ_FUSE_MASK
);
5536 static int valleyview_rps_guar_freq(struct drm_i915_private
*dev_priv
)
5540 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FREQ_FUSE
);
5542 rp1
= (val
& FB_GFX_FGUARANTEED_FREQ_FUSE_MASK
) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT
;
5547 static int valleyview_rps_max_freq(struct drm_i915_private
*dev_priv
)
5551 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FREQ_FUSE
);
5553 rp0
= (val
& FB_GFX_MAX_FREQ_FUSE_MASK
) >> FB_GFX_MAX_FREQ_FUSE_SHIFT
;
5555 rp0
= min_t(u32
, rp0
, 0xea);
5560 static int valleyview_rps_rpe_freq(struct drm_i915_private
*dev_priv
)
5564 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FMAX_FUSE_LO
);
5565 rpe
= (val
& FB_FMAX_VMIN_FREQ_LO_MASK
) >> FB_FMAX_VMIN_FREQ_LO_SHIFT
;
5566 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FMAX_FUSE_HI
);
5567 rpe
|= (val
& FB_FMAX_VMIN_FREQ_HI_MASK
) << 5;
5572 static int valleyview_rps_min_freq(struct drm_i915_private
*dev_priv
)
5576 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_LFM
) & 0xff;
5578 * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
5579 * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
5580 * a BYT-M B0 the above register contains 0xbf. Moreover when setting
5581 * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
5582 * to make sure it matches what Punit accepts.
5584 return max_t(u32
, val
, 0xc0);
5587 /* Check that the pctx buffer wasn't move under us. */
5588 static void valleyview_check_pctx(struct drm_i915_private
*dev_priv
)
5590 unsigned long pctx_addr
= I915_READ(VLV_PCBR
) & ~4095;
5592 WARN_ON(pctx_addr
!= dev_priv
->mm
.stolen_base
+
5593 dev_priv
->vlv_pctx
->stolen
->start
);
5597 /* Check that the pcbr address is not empty. */
5598 static void cherryview_check_pctx(struct drm_i915_private
*dev_priv
)
5600 unsigned long pctx_addr
= I915_READ(VLV_PCBR
) & ~4095;
5602 WARN_ON((pctx_addr
>> VLV_PCBR_ADDR_SHIFT
) == 0);
5605 static void cherryview_setup_pctx(struct drm_i915_private
*dev_priv
)
5607 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
5608 unsigned long pctx_paddr
, paddr
;
5610 int pctx_size
= 32*1024;
5612 pcbr
= I915_READ(VLV_PCBR
);
5613 if ((pcbr
>> VLV_PCBR_ADDR_SHIFT
) == 0) {
5614 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5615 paddr
= (dev_priv
->mm
.stolen_base
+
5616 (ggtt
->stolen_size
- pctx_size
));
5618 pctx_paddr
= (paddr
& (~4095));
5619 I915_WRITE(VLV_PCBR
, pctx_paddr
);
5622 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR
));
5625 static void valleyview_setup_pctx(struct drm_i915_private
*dev_priv
)
5627 struct drm_i915_gem_object
*pctx
;
5628 unsigned long pctx_paddr
;
5630 int pctx_size
= 24*1024;
5632 mutex_lock(&dev_priv
->dev
->struct_mutex
);
5634 pcbr
= I915_READ(VLV_PCBR
);
5636 /* BIOS set it up already, grab the pre-alloc'd space */
5639 pcbr_offset
= (pcbr
& (~4095)) - dev_priv
->mm
.stolen_base
;
5640 pctx
= i915_gem_object_create_stolen_for_preallocated(dev_priv
->dev
,
5642 I915_GTT_OFFSET_NONE
,
5647 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5650 * From the Gunit register HAS:
5651 * The Gfx driver is expected to program this register and ensure
5652 * proper allocation within Gfx stolen memory. For example, this
5653 * register should be programmed such than the PCBR range does not
5654 * overlap with other ranges, such as the frame buffer, protected
5655 * memory, or any other relevant ranges.
5657 pctx
= i915_gem_object_create_stolen(dev_priv
->dev
, pctx_size
);
5659 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
5663 pctx_paddr
= dev_priv
->mm
.stolen_base
+ pctx
->stolen
->start
;
5664 I915_WRITE(VLV_PCBR
, pctx_paddr
);
5667 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR
));
5668 dev_priv
->vlv_pctx
= pctx
;
5669 mutex_unlock(&dev_priv
->dev
->struct_mutex
);
5672 static void valleyview_cleanup_pctx(struct drm_i915_private
*dev_priv
)
5674 if (WARN_ON(!dev_priv
->vlv_pctx
))
5677 drm_gem_object_unreference_unlocked(&dev_priv
->vlv_pctx
->base
);
5678 dev_priv
->vlv_pctx
= NULL
;
5681 static void vlv_init_gpll_ref_freq(struct drm_i915_private
*dev_priv
)
5683 dev_priv
->rps
.gpll_ref_freq
=
5684 vlv_get_cck_clock(dev_priv
, "GPLL ref",
5685 CCK_GPLL_CLOCK_CONTROL
,
5686 dev_priv
->czclk_freq
);
5688 DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n",
5689 dev_priv
->rps
.gpll_ref_freq
);
5692 static void valleyview_init_gt_powersave(struct drm_i915_private
*dev_priv
)
5696 valleyview_setup_pctx(dev_priv
);
5698 vlv_init_gpll_ref_freq(dev_priv
);
5700 mutex_lock(&dev_priv
->rps
.hw_lock
);
5702 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
5703 switch ((val
>> 6) & 3) {
5706 dev_priv
->mem_freq
= 800;
5709 dev_priv
->mem_freq
= 1066;
5712 dev_priv
->mem_freq
= 1333;
5715 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv
->mem_freq
);
5717 dev_priv
->rps
.max_freq
= valleyview_rps_max_freq(dev_priv
);
5718 dev_priv
->rps
.rp0_freq
= dev_priv
->rps
.max_freq
;
5719 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5720 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
),
5721 dev_priv
->rps
.max_freq
);
5723 dev_priv
->rps
.efficient_freq
= valleyview_rps_rpe_freq(dev_priv
);
5724 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5725 intel_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
),
5726 dev_priv
->rps
.efficient_freq
);
5728 dev_priv
->rps
.rp1_freq
= valleyview_rps_guar_freq(dev_priv
);
5729 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
5730 intel_gpu_freq(dev_priv
, dev_priv
->rps
.rp1_freq
),
5731 dev_priv
->rps
.rp1_freq
);
5733 dev_priv
->rps
.min_freq
= valleyview_rps_min_freq(dev_priv
);
5734 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5735 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
),
5736 dev_priv
->rps
.min_freq
);
5738 dev_priv
->rps
.idle_freq
= dev_priv
->rps
.min_freq
;
5740 /* Preserve min/max settings in case of re-init */
5741 if (dev_priv
->rps
.max_freq_softlimit
== 0)
5742 dev_priv
->rps
.max_freq_softlimit
= dev_priv
->rps
.max_freq
;
5744 if (dev_priv
->rps
.min_freq_softlimit
== 0)
5745 dev_priv
->rps
.min_freq_softlimit
= dev_priv
->rps
.min_freq
;
5747 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5750 static void cherryview_init_gt_powersave(struct drm_i915_private
*dev_priv
)
5754 cherryview_setup_pctx(dev_priv
);
5756 vlv_init_gpll_ref_freq(dev_priv
);
5758 mutex_lock(&dev_priv
->rps
.hw_lock
);
5760 mutex_lock(&dev_priv
->sb_lock
);
5761 val
= vlv_cck_read(dev_priv
, CCK_FUSE_REG
);
5762 mutex_unlock(&dev_priv
->sb_lock
);
5764 switch ((val
>> 2) & 0x7) {
5766 dev_priv
->mem_freq
= 2000;
5769 dev_priv
->mem_freq
= 1600;
5772 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv
->mem_freq
);
5774 dev_priv
->rps
.max_freq
= cherryview_rps_max_freq(dev_priv
);
5775 dev_priv
->rps
.rp0_freq
= dev_priv
->rps
.max_freq
;
5776 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5777 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
),
5778 dev_priv
->rps
.max_freq
);
5780 dev_priv
->rps
.efficient_freq
= cherryview_rps_rpe_freq(dev_priv
);
5781 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5782 intel_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
),
5783 dev_priv
->rps
.efficient_freq
);
5785 dev_priv
->rps
.rp1_freq
= cherryview_rps_guar_freq(dev_priv
);
5786 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
5787 intel_gpu_freq(dev_priv
, dev_priv
->rps
.rp1_freq
),
5788 dev_priv
->rps
.rp1_freq
);
5790 /* PUnit validated range is only [RPe, RP0] */
5791 dev_priv
->rps
.min_freq
= dev_priv
->rps
.efficient_freq
;
5792 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5793 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
),
5794 dev_priv
->rps
.min_freq
);
5796 WARN_ONCE((dev_priv
->rps
.max_freq
|
5797 dev_priv
->rps
.efficient_freq
|
5798 dev_priv
->rps
.rp1_freq
|
5799 dev_priv
->rps
.min_freq
) & 1,
5800 "Odd GPU freq values\n");
5802 dev_priv
->rps
.idle_freq
= dev_priv
->rps
.min_freq
;
5804 /* Preserve min/max settings in case of re-init */
5805 if (dev_priv
->rps
.max_freq_softlimit
== 0)
5806 dev_priv
->rps
.max_freq_softlimit
= dev_priv
->rps
.max_freq
;
5808 if (dev_priv
->rps
.min_freq_softlimit
== 0)
5809 dev_priv
->rps
.min_freq_softlimit
= dev_priv
->rps
.min_freq
;
5811 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5814 static void valleyview_cleanup_gt_powersave(struct drm_i915_private
*dev_priv
)
5816 valleyview_cleanup_pctx(dev_priv
);
5819 static void cherryview_enable_rps(struct drm_i915_private
*dev_priv
)
5821 struct intel_engine_cs
*engine
;
5822 u32 gtfifodbg
, val
, rc6_mode
= 0, pcbr
;
5824 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
5826 gtfifodbg
= I915_READ(GTFIFODBG
) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV
|
5827 GT_FIFO_FREE_ENTRIES_CHV
);
5829 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5831 I915_WRITE(GTFIFODBG
, gtfifodbg
);
5834 cherryview_check_pctx(dev_priv
);
5836 /* 1a & 1b: Get forcewake during program sequence. Although the driver
5837 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5838 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
5840 /* Disable RC states. */
5841 I915_WRITE(GEN6_RC_CONTROL
, 0);
5843 /* 2a: Program RC6 thresholds.*/
5844 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 40 << 16);
5845 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000); /* 12500 * 1280ns */
5846 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25); /* 25 * 1280ns */
5848 for_each_engine(engine
, dev_priv
)
5849 I915_WRITE(RING_MAX_IDLE(engine
->mmio_base
), 10);
5850 I915_WRITE(GEN6_RC_SLEEP
, 0);
5852 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
5853 I915_WRITE(GEN6_RC6_THRESHOLD
, 0x186);
5855 /* allows RC6 residency counter to work */
5856 I915_WRITE(VLV_COUNTER_CONTROL
,
5857 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH
|
5858 VLV_MEDIA_RC6_COUNT_EN
|
5859 VLV_RENDER_RC6_COUNT_EN
));
5861 /* For now we assume BIOS is allocating and populating the PCBR */
5862 pcbr
= I915_READ(VLV_PCBR
);
5865 if ((intel_enable_rc6() & INTEL_RC6_ENABLE
) &&
5866 (pcbr
>> VLV_PCBR_ADDR_SHIFT
))
5867 rc6_mode
= GEN7_RC_CTL_TO_MODE
;
5869 I915_WRITE(GEN6_RC_CONTROL
, rc6_mode
);
5871 /* 4 Program defaults and thresholds for RPS*/
5872 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 1000000);
5873 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 59400);
5874 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 245000);
5875 I915_WRITE(GEN6_RP_UP_EI
, 66000);
5876 I915_WRITE(GEN6_RP_DOWN_EI
, 350000);
5878 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
5881 I915_WRITE(GEN6_RP_CONTROL
,
5882 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
5883 GEN6_RP_MEDIA_IS_GFX
|
5885 GEN6_RP_UP_BUSY_AVG
|
5886 GEN6_RP_DOWN_IDLE_AVG
);
5888 /* Setting Fixed Bias */
5889 val
= VLV_OVERRIDE_EN
|
5891 CHV_BIAS_CPU_50_SOC_50
;
5892 vlv_punit_write(dev_priv
, VLV_TURBO_SOC_OVERRIDE
, val
);
5894 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
5896 /* RPS code assumes GPLL is used */
5897 WARN_ONCE((val
& GPLLENABLE
) == 0, "GPLL not enabled\n");
5899 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val
& GPLLENABLE
));
5900 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val
);
5902 dev_priv
->rps
.cur_freq
= (val
>> 8) & 0xff;
5903 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5904 intel_gpu_freq(dev_priv
, dev_priv
->rps
.cur_freq
),
5905 dev_priv
->rps
.cur_freq
);
5907 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5908 intel_gpu_freq(dev_priv
, dev_priv
->rps
.idle_freq
),
5909 dev_priv
->rps
.idle_freq
);
5911 valleyview_set_rps(dev_priv
, dev_priv
->rps
.idle_freq
);
5913 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
5916 static void valleyview_enable_rps(struct drm_i915_private
*dev_priv
)
5918 struct intel_engine_cs
*engine
;
5919 u32 gtfifodbg
, val
, rc6_mode
= 0;
5921 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
5923 valleyview_check_pctx(dev_priv
);
5925 gtfifodbg
= I915_READ(GTFIFODBG
);
5927 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5929 I915_WRITE(GTFIFODBG
, gtfifodbg
);
5932 /* If VLV, Forcewake all wells, else re-direct to regular path */
5933 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
5935 /* Disable RC states. */
5936 I915_WRITE(GEN6_RC_CONTROL
, 0);
5938 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 1000000);
5939 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 59400);
5940 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 245000);
5941 I915_WRITE(GEN6_RP_UP_EI
, 66000);
5942 I915_WRITE(GEN6_RP_DOWN_EI
, 350000);
5944 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
5946 I915_WRITE(GEN6_RP_CONTROL
,
5947 GEN6_RP_MEDIA_TURBO
|
5948 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
5949 GEN6_RP_MEDIA_IS_GFX
|
5951 GEN6_RP_UP_BUSY_AVG
|
5952 GEN6_RP_DOWN_IDLE_CONT
);
5954 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 0x00280000);
5955 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000);
5956 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25);
5958 for_each_engine(engine
, dev_priv
)
5959 I915_WRITE(RING_MAX_IDLE(engine
->mmio_base
), 10);
5961 I915_WRITE(GEN6_RC6_THRESHOLD
, 0x557);
5963 /* allows RC6 residency counter to work */
5964 I915_WRITE(VLV_COUNTER_CONTROL
,
5965 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN
|
5966 VLV_RENDER_RC0_COUNT_EN
|
5967 VLV_MEDIA_RC6_COUNT_EN
|
5968 VLV_RENDER_RC6_COUNT_EN
));
5970 if (intel_enable_rc6() & INTEL_RC6_ENABLE
)
5971 rc6_mode
= GEN7_RC_CTL_TO_MODE
| VLV_RC_CTL_CTX_RST_PARALLEL
;
5973 intel_print_rc6_info(dev_priv
, rc6_mode
);
5975 I915_WRITE(GEN6_RC_CONTROL
, rc6_mode
);
5977 /* Setting Fixed Bias */
5978 val
= VLV_OVERRIDE_EN
|
5980 VLV_BIAS_CPU_125_SOC_875
;
5981 vlv_punit_write(dev_priv
, VLV_TURBO_SOC_OVERRIDE
, val
);
5983 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
5985 /* RPS code assumes GPLL is used */
5986 WARN_ONCE((val
& GPLLENABLE
) == 0, "GPLL not enabled\n");
5988 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val
& GPLLENABLE
));
5989 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val
);
5991 dev_priv
->rps
.cur_freq
= (val
>> 8) & 0xff;
5992 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5993 intel_gpu_freq(dev_priv
, dev_priv
->rps
.cur_freq
),
5994 dev_priv
->rps
.cur_freq
);
5996 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5997 intel_gpu_freq(dev_priv
, dev_priv
->rps
.idle_freq
),
5998 dev_priv
->rps
.idle_freq
);
6000 valleyview_set_rps(dev_priv
, dev_priv
->rps
.idle_freq
);
6002 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
6005 static unsigned long intel_pxfreq(u32 vidfreq
)
6008 int div
= (vidfreq
& 0x3f0000) >> 16;
6009 int post
= (vidfreq
& 0x3000) >> 12;
6010 int pre
= (vidfreq
& 0x7);
6015 freq
= ((div
* 133333) / ((1<<post
) * pre
));
6020 static const struct cparams
{
6026 { 1, 1333, 301, 28664 },
6027 { 1, 1066, 294, 24460 },
6028 { 1, 800, 294, 25192 },
6029 { 0, 1333, 276, 27605 },
6030 { 0, 1066, 276, 27605 },
6031 { 0, 800, 231, 23784 },
6034 static unsigned long __i915_chipset_val(struct drm_i915_private
*dev_priv
)
6036 u64 total_count
, diff
, ret
;
6037 u32 count1
, count2
, count3
, m
= 0, c
= 0;
6038 unsigned long now
= jiffies_to_msecs(jiffies
), diff1
;
6041 assert_spin_locked(&mchdev_lock
);
6043 diff1
= now
- dev_priv
->ips
.last_time1
;
6045 /* Prevent division-by-zero if we are asking too fast.
6046 * Also, we don't get interesting results if we are polling
6047 * faster than once in 10ms, so just return the saved value
6051 return dev_priv
->ips
.chipset_power
;
6053 count1
= I915_READ(DMIEC
);
6054 count2
= I915_READ(DDREC
);
6055 count3
= I915_READ(CSIEC
);
6057 total_count
= count1
+ count2
+ count3
;
6059 /* FIXME: handle per-counter overflow */
6060 if (total_count
< dev_priv
->ips
.last_count1
) {
6061 diff
= ~0UL - dev_priv
->ips
.last_count1
;
6062 diff
+= total_count
;
6064 diff
= total_count
- dev_priv
->ips
.last_count1
;
6067 for (i
= 0; i
< ARRAY_SIZE(cparams
); i
++) {
6068 if (cparams
[i
].i
== dev_priv
->ips
.c_m
&&
6069 cparams
[i
].t
== dev_priv
->ips
.r_t
) {
6076 diff
= div_u64(diff
, diff1
);
6077 ret
= ((m
* diff
) + c
);
6078 ret
= div_u64(ret
, 10);
6080 dev_priv
->ips
.last_count1
= total_count
;
6081 dev_priv
->ips
.last_time1
= now
;
6083 dev_priv
->ips
.chipset_power
= ret
;
6088 unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
)
6092 if (INTEL_INFO(dev_priv
)->gen
!= 5)
6095 spin_lock_irq(&mchdev_lock
);
6097 val
= __i915_chipset_val(dev_priv
);
6099 spin_unlock_irq(&mchdev_lock
);
6104 unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
)
6106 unsigned long m
, x
, b
;
6109 tsfs
= I915_READ(TSFS
);
6111 m
= ((tsfs
& TSFS_SLOPE_MASK
) >> TSFS_SLOPE_SHIFT
);
6112 x
= I915_READ8(TR1
);
6114 b
= tsfs
& TSFS_INTR_MASK
;
6116 return ((m
* x
) / 127) - b
;
6119 static int _pxvid_to_vd(u8 pxvid
)
6124 if (pxvid
>= 8 && pxvid
< 31)
6127 return (pxvid
+ 2) * 125;
6130 static u32
pvid_to_extvid(struct drm_i915_private
*dev_priv
, u8 pxvid
)
6132 const int vd
= _pxvid_to_vd(pxvid
);
6133 const int vm
= vd
- 1125;
6135 if (INTEL_INFO(dev_priv
)->is_mobile
)
6136 return vm
> 0 ? vm
: 0;
6141 static void __i915_update_gfx_val(struct drm_i915_private
*dev_priv
)
6143 u64 now
, diff
, diffms
;
6146 assert_spin_locked(&mchdev_lock
);
6148 now
= ktime_get_raw_ns();
6149 diffms
= now
- dev_priv
->ips
.last_time2
;
6150 do_div(diffms
, NSEC_PER_MSEC
);
6152 /* Don't divide by 0 */
6156 count
= I915_READ(GFXEC
);
6158 if (count
< dev_priv
->ips
.last_count2
) {
6159 diff
= ~0UL - dev_priv
->ips
.last_count2
;
6162 diff
= count
- dev_priv
->ips
.last_count2
;
6165 dev_priv
->ips
.last_count2
= count
;
6166 dev_priv
->ips
.last_time2
= now
;
6168 /* More magic constants... */
6170 diff
= div_u64(diff
, diffms
* 10);
6171 dev_priv
->ips
.gfx_power
= diff
;
6174 void i915_update_gfx_val(struct drm_i915_private
*dev_priv
)
6176 if (INTEL_INFO(dev_priv
)->gen
!= 5)
6179 spin_lock_irq(&mchdev_lock
);
6181 __i915_update_gfx_val(dev_priv
);
6183 spin_unlock_irq(&mchdev_lock
);
6186 static unsigned long __i915_gfx_val(struct drm_i915_private
*dev_priv
)
6188 unsigned long t
, corr
, state1
, corr2
, state2
;
6191 assert_spin_locked(&mchdev_lock
);
6193 pxvid
= I915_READ(PXVFREQ(dev_priv
->rps
.cur_freq
));
6194 pxvid
= (pxvid
>> 24) & 0x7f;
6195 ext_v
= pvid_to_extvid(dev_priv
, pxvid
);
6199 t
= i915_mch_val(dev_priv
);
6201 /* Revel in the empirically derived constants */
6203 /* Correction factor in 1/100000 units */
6205 corr
= ((t
* 2349) + 135940);
6207 corr
= ((t
* 964) + 29317);
6209 corr
= ((t
* 301) + 1004);
6211 corr
= corr
* ((150142 * state1
) / 10000 - 78642);
6213 corr2
= (corr
* dev_priv
->ips
.corr
);
6215 state2
= (corr2
* state1
) / 10000;
6216 state2
/= 100; /* convert to mW */
6218 __i915_update_gfx_val(dev_priv
);
6220 return dev_priv
->ips
.gfx_power
+ state2
;
6223 unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
)
6227 if (INTEL_INFO(dev_priv
)->gen
!= 5)
6230 spin_lock_irq(&mchdev_lock
);
6232 val
= __i915_gfx_val(dev_priv
);
6234 spin_unlock_irq(&mchdev_lock
);
6240 * i915_read_mch_val - return value for IPS use
6242 * Calculate and return a value for the IPS driver to use when deciding whether
6243 * we have thermal and power headroom to increase CPU or GPU power budget.
6245 unsigned long i915_read_mch_val(void)
6247 struct drm_i915_private
*dev_priv
;
6248 unsigned long chipset_val
, graphics_val
, ret
= 0;
6250 spin_lock_irq(&mchdev_lock
);
6253 dev_priv
= i915_mch_dev
;
6255 chipset_val
= __i915_chipset_val(dev_priv
);
6256 graphics_val
= __i915_gfx_val(dev_priv
);
6258 ret
= chipset_val
+ graphics_val
;
6261 spin_unlock_irq(&mchdev_lock
);
6265 EXPORT_SYMBOL_GPL(i915_read_mch_val
);
6268 * i915_gpu_raise - raise GPU frequency limit
6270 * Raise the limit; IPS indicates we have thermal headroom.
6272 bool i915_gpu_raise(void)
6274 struct drm_i915_private
*dev_priv
;
6277 spin_lock_irq(&mchdev_lock
);
6278 if (!i915_mch_dev
) {
6282 dev_priv
= i915_mch_dev
;
6284 if (dev_priv
->ips
.max_delay
> dev_priv
->ips
.fmax
)
6285 dev_priv
->ips
.max_delay
--;
6288 spin_unlock_irq(&mchdev_lock
);
6292 EXPORT_SYMBOL_GPL(i915_gpu_raise
);
6295 * i915_gpu_lower - lower GPU frequency limit
6297 * IPS indicates we're close to a thermal limit, so throttle back the GPU
6298 * frequency maximum.
6300 bool i915_gpu_lower(void)
6302 struct drm_i915_private
*dev_priv
;
6305 spin_lock_irq(&mchdev_lock
);
6306 if (!i915_mch_dev
) {
6310 dev_priv
= i915_mch_dev
;
6312 if (dev_priv
->ips
.max_delay
< dev_priv
->ips
.min_delay
)
6313 dev_priv
->ips
.max_delay
++;
6316 spin_unlock_irq(&mchdev_lock
);
6320 EXPORT_SYMBOL_GPL(i915_gpu_lower
);
6323 * i915_gpu_busy - indicate GPU business to IPS
6325 * Tell the IPS driver whether or not the GPU is busy.
6327 bool i915_gpu_busy(void)
6329 struct drm_i915_private
*dev_priv
;
6330 struct intel_engine_cs
*engine
;
6333 spin_lock_irq(&mchdev_lock
);
6336 dev_priv
= i915_mch_dev
;
6338 for_each_engine(engine
, dev_priv
)
6339 ret
|= !list_empty(&engine
->request_list
);
6342 spin_unlock_irq(&mchdev_lock
);
6346 EXPORT_SYMBOL_GPL(i915_gpu_busy
);
6349 * i915_gpu_turbo_disable - disable graphics turbo
6351 * Disable graphics turbo by resetting the max frequency and setting the
6352 * current frequency to the default.
6354 bool i915_gpu_turbo_disable(void)
6356 struct drm_i915_private
*dev_priv
;
6359 spin_lock_irq(&mchdev_lock
);
6360 if (!i915_mch_dev
) {
6364 dev_priv
= i915_mch_dev
;
6366 dev_priv
->ips
.max_delay
= dev_priv
->ips
.fstart
;
6368 if (!ironlake_set_drps(dev_priv
, dev_priv
->ips
.fstart
))
6372 spin_unlock_irq(&mchdev_lock
);
6376 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable
);
6379 * Tells the intel_ips driver that the i915 driver is now loaded, if
6380 * IPS got loaded first.
6382 * This awkward dance is so that neither module has to depend on the
6383 * other in order for IPS to do the appropriate communication of
6384 * GPU turbo limits to i915.
6387 ips_ping_for_i915_load(void)
6391 link
= symbol_get(ips_link_to_i915_driver
);
6394 symbol_put(ips_link_to_i915_driver
);
6398 void intel_gpu_ips_init(struct drm_i915_private
*dev_priv
)
6400 /* We only register the i915 ips part with intel-ips once everything is
6401 * set up, to avoid intel-ips sneaking in and reading bogus values. */
6402 spin_lock_irq(&mchdev_lock
);
6403 i915_mch_dev
= dev_priv
;
6404 spin_unlock_irq(&mchdev_lock
);
6406 ips_ping_for_i915_load();
6409 void intel_gpu_ips_teardown(void)
6411 spin_lock_irq(&mchdev_lock
);
6412 i915_mch_dev
= NULL
;
6413 spin_unlock_irq(&mchdev_lock
);
6416 static void intel_init_emon(struct drm_i915_private
*dev_priv
)
6422 /* Disable to program */
6426 /* Program energy weights for various events */
6427 I915_WRITE(SDEW
, 0x15040d00);
6428 I915_WRITE(CSIEW0
, 0x007f0000);
6429 I915_WRITE(CSIEW1
, 0x1e220004);
6430 I915_WRITE(CSIEW2
, 0x04000004);
6432 for (i
= 0; i
< 5; i
++)
6433 I915_WRITE(PEW(i
), 0);
6434 for (i
= 0; i
< 3; i
++)
6435 I915_WRITE(DEW(i
), 0);
6437 /* Program P-state weights to account for frequency power adjustment */
6438 for (i
= 0; i
< 16; i
++) {
6439 u32 pxvidfreq
= I915_READ(PXVFREQ(i
));
6440 unsigned long freq
= intel_pxfreq(pxvidfreq
);
6441 unsigned long vid
= (pxvidfreq
& PXVFREQ_PX_MASK
) >>
6446 val
*= (freq
/ 1000);
6448 val
/= (127*127*900);
6450 DRM_ERROR("bad pxval: %ld\n", val
);
6453 /* Render standby states get 0 weight */
6457 for (i
= 0; i
< 4; i
++) {
6458 u32 val
= (pxw
[i
*4] << 24) | (pxw
[(i
*4)+1] << 16) |
6459 (pxw
[(i
*4)+2] << 8) | (pxw
[(i
*4)+3]);
6460 I915_WRITE(PXW(i
), val
);
6463 /* Adjust magic regs to magic values (more experimental results) */
6464 I915_WRITE(OGW0
, 0);
6465 I915_WRITE(OGW1
, 0);
6466 I915_WRITE(EG0
, 0x00007f00);
6467 I915_WRITE(EG1
, 0x0000000e);
6468 I915_WRITE(EG2
, 0x000e0000);
6469 I915_WRITE(EG3
, 0x68000300);
6470 I915_WRITE(EG4
, 0x42000000);
6471 I915_WRITE(EG5
, 0x00140031);
6475 for (i
= 0; i
< 8; i
++)
6476 I915_WRITE(PXWL(i
), 0);
6478 /* Enable PMON + select events */
6479 I915_WRITE(ECR
, 0x80000019);
6481 lcfuse
= I915_READ(LCFUSE02
);
6483 dev_priv
->ips
.corr
= (lcfuse
& LCFUSE_HIV_MASK
);
6486 void intel_init_gt_powersave(struct drm_i915_private
*dev_priv
)
6489 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6492 if (!i915
.enable_rc6
) {
6493 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6494 intel_runtime_pm_get(dev_priv
);
6497 if (IS_CHERRYVIEW(dev_priv
))
6498 cherryview_init_gt_powersave(dev_priv
);
6499 else if (IS_VALLEYVIEW(dev_priv
))
6500 valleyview_init_gt_powersave(dev_priv
);
6503 void intel_cleanup_gt_powersave(struct drm_i915_private
*dev_priv
)
6505 if (IS_CHERRYVIEW(dev_priv
))
6507 else if (IS_VALLEYVIEW(dev_priv
))
6508 valleyview_cleanup_gt_powersave(dev_priv
);
6510 if (!i915
.enable_rc6
)
6511 intel_runtime_pm_put(dev_priv
);
6514 static void gen6_suspend_rps(struct drm_i915_private
*dev_priv
)
6516 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
6518 gen6_disable_rps_interrupts(dev_priv
);
6522 * intel_suspend_gt_powersave - suspend PM work and helper threads
6523 * @dev_priv: i915 device
6525 * We don't want to disable RC6 or other features here, we just want
6526 * to make sure any work we've queued has finished and won't bother
6527 * us while we're suspended.
6529 void intel_suspend_gt_powersave(struct drm_i915_private
*dev_priv
)
6531 if (INTEL_GEN(dev_priv
) < 6)
6534 gen6_suspend_rps(dev_priv
);
6536 /* Force GPU to min freq during suspend */
6537 gen6_rps_idle(dev_priv
);
6540 void intel_disable_gt_powersave(struct drm_i915_private
*dev_priv
)
6542 if (IS_IRONLAKE_M(dev_priv
)) {
6543 ironlake_disable_drps(dev_priv
);
6544 } else if (INTEL_INFO(dev_priv
)->gen
>= 6) {
6545 intel_suspend_gt_powersave(dev_priv
);
6547 mutex_lock(&dev_priv
->rps
.hw_lock
);
6548 if (INTEL_INFO(dev_priv
)->gen
>= 9) {
6549 gen9_disable_rc6(dev_priv
);
6550 gen9_disable_rps(dev_priv
);
6551 } else if (IS_CHERRYVIEW(dev_priv
))
6552 cherryview_disable_rps(dev_priv
);
6553 else if (IS_VALLEYVIEW(dev_priv
))
6554 valleyview_disable_rps(dev_priv
);
6556 gen6_disable_rps(dev_priv
);
6558 dev_priv
->rps
.enabled
= false;
6559 mutex_unlock(&dev_priv
->rps
.hw_lock
);
6563 static void intel_gen6_powersave_work(struct work_struct
*work
)
6565 struct drm_i915_private
*dev_priv
=
6566 container_of(work
, struct drm_i915_private
,
6567 rps
.delayed_resume_work
.work
);
6569 mutex_lock(&dev_priv
->rps
.hw_lock
);
6571 gen6_reset_rps_interrupts(dev_priv
);
6573 if (IS_CHERRYVIEW(dev_priv
)) {
6574 cherryview_enable_rps(dev_priv
);
6575 } else if (IS_VALLEYVIEW(dev_priv
)) {
6576 valleyview_enable_rps(dev_priv
);
6577 } else if (INTEL_INFO(dev_priv
)->gen
>= 9) {
6578 gen9_enable_rc6(dev_priv
);
6579 gen9_enable_rps(dev_priv
);
6580 if (IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
))
6581 __gen6_update_ring_freq(dev_priv
);
6582 } else if (IS_BROADWELL(dev_priv
)) {
6583 gen8_enable_rps(dev_priv
);
6584 __gen6_update_ring_freq(dev_priv
);
6586 gen6_enable_rps(dev_priv
);
6587 __gen6_update_ring_freq(dev_priv
);
6590 WARN_ON(dev_priv
->rps
.max_freq
< dev_priv
->rps
.min_freq
);
6591 WARN_ON(dev_priv
->rps
.idle_freq
> dev_priv
->rps
.max_freq
);
6593 WARN_ON(dev_priv
->rps
.efficient_freq
< dev_priv
->rps
.min_freq
);
6594 WARN_ON(dev_priv
->rps
.efficient_freq
> dev_priv
->rps
.max_freq
);
6596 dev_priv
->rps
.enabled
= true;
6598 gen6_enable_rps_interrupts(dev_priv
);
6600 mutex_unlock(&dev_priv
->rps
.hw_lock
);
6602 intel_runtime_pm_put(dev_priv
);
6605 void intel_enable_gt_powersave(struct drm_i915_private
*dev_priv
)
6607 /* Powersaving is controlled by the host when inside a VM */
6608 if (intel_vgpu_active(dev_priv
))
6611 if (IS_IRONLAKE_M(dev_priv
)) {
6612 ironlake_enable_drps(dev_priv
);
6613 mutex_lock(&dev_priv
->dev
->struct_mutex
);
6614 intel_init_emon(dev_priv
);
6615 mutex_unlock(&dev_priv
->dev
->struct_mutex
);
6616 } else if (INTEL_INFO(dev_priv
)->gen
>= 6) {
6618 * PCU communication is slow and this doesn't need to be
6619 * done at any specific time, so do this out of our fast path
6620 * to make resume and init faster.
6622 * We depend on the HW RC6 power context save/restore
6623 * mechanism when entering D3 through runtime PM suspend. So
6624 * disable RPM until RPS/RC6 is properly setup. We can only
6625 * get here via the driver load/system resume/runtime resume
6626 * paths, so the _noresume version is enough (and in case of
6627 * runtime resume it's necessary).
6629 if (schedule_delayed_work(&dev_priv
->rps
.delayed_resume_work
,
6630 round_jiffies_up_relative(HZ
)))
6631 intel_runtime_pm_get_noresume(dev_priv
);
6635 void intel_reset_gt_powersave(struct drm_i915_private
*dev_priv
)
6637 if (INTEL_INFO(dev_priv
)->gen
< 6)
6640 gen6_suspend_rps(dev_priv
);
6641 dev_priv
->rps
.enabled
= false;
6644 static void ibx_init_clock_gating(struct drm_device
*dev
)
6646 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6649 * On Ibex Peak and Cougar Point, we need to disable clock
6650 * gating for the panel power sequencer or it will fail to
6651 * start up when no ports are active.
6653 I915_WRITE(SOUTH_DSPCLK_GATE_D
, PCH_DPLSUNIT_CLOCK_GATE_DISABLE
);
6656 static void g4x_disable_trickle_feed(struct drm_device
*dev
)
6658 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6661 for_each_pipe(dev_priv
, pipe
) {
6662 I915_WRITE(DSPCNTR(pipe
),
6663 I915_READ(DSPCNTR(pipe
)) |
6664 DISPPLANE_TRICKLE_FEED_DISABLE
);
6666 I915_WRITE(DSPSURF(pipe
), I915_READ(DSPSURF(pipe
)));
6667 POSTING_READ(DSPSURF(pipe
));
6671 static void ilk_init_lp_watermarks(struct drm_device
*dev
)
6673 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6675 I915_WRITE(WM3_LP_ILK
, I915_READ(WM3_LP_ILK
) & ~WM1_LP_SR_EN
);
6676 I915_WRITE(WM2_LP_ILK
, I915_READ(WM2_LP_ILK
) & ~WM1_LP_SR_EN
);
6677 I915_WRITE(WM1_LP_ILK
, I915_READ(WM1_LP_ILK
) & ~WM1_LP_SR_EN
);
6680 * Don't touch WM1S_LP_EN here.
6681 * Doing so could cause underruns.
6685 static void ironlake_init_clock_gating(struct drm_device
*dev
)
6687 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6688 uint32_t dspclk_gate
= ILK_VRHUNIT_CLOCK_GATE_DISABLE
;
6692 * WaFbcDisableDpfcClockGating:ilk
6694 dspclk_gate
|= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE
|
6695 ILK_DPFCUNIT_CLOCK_GATE_DISABLE
|
6696 ILK_DPFDUNIT_CLOCK_GATE_ENABLE
;
6698 I915_WRITE(PCH_3DCGDIS0
,
6699 MARIUNIT_CLOCK_GATE_DISABLE
|
6700 SVSMUNIT_CLOCK_GATE_DISABLE
);
6701 I915_WRITE(PCH_3DCGDIS1
,
6702 VFMUNIT_CLOCK_GATE_DISABLE
);
6705 * According to the spec the following bits should be set in
6706 * order to enable memory self-refresh
6707 * The bit 22/21 of 0x42004
6708 * The bit 5 of 0x42020
6709 * The bit 15 of 0x45000
6711 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
6712 (I915_READ(ILK_DISPLAY_CHICKEN2
) |
6713 ILK_DPARB_GATE
| ILK_VSDPFD_FULL
));
6714 dspclk_gate
|= ILK_DPARBUNIT_CLOCK_GATE_ENABLE
;
6715 I915_WRITE(DISP_ARB_CTL
,
6716 (I915_READ(DISP_ARB_CTL
) |
6719 ilk_init_lp_watermarks(dev
);
6722 * Based on the document from hardware guys the following bits
6723 * should be set unconditionally in order to enable FBC.
6724 * The bit 22 of 0x42000
6725 * The bit 22 of 0x42004
6726 * The bit 7,8,9 of 0x42020.
6728 if (IS_IRONLAKE_M(dev
)) {
6729 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6730 I915_WRITE(ILK_DISPLAY_CHICKEN1
,
6731 I915_READ(ILK_DISPLAY_CHICKEN1
) |
6733 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
6734 I915_READ(ILK_DISPLAY_CHICKEN2
) |
6738 I915_WRITE(ILK_DSPCLK_GATE_D
, dspclk_gate
);
6740 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
6741 I915_READ(ILK_DISPLAY_CHICKEN2
) |
6742 ILK_ELPIN_409_SELECT
);
6743 I915_WRITE(_3D_CHICKEN2
,
6744 _3D_CHICKEN2_WM_READ_PIPELINED
<< 16 |
6745 _3D_CHICKEN2_WM_READ_PIPELINED
);
6747 /* WaDisableRenderCachePipelinedFlush:ilk */
6748 I915_WRITE(CACHE_MODE_0
,
6749 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE
));
6751 /* WaDisable_RenderCache_OperationalFlush:ilk */
6752 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
6754 g4x_disable_trickle_feed(dev
);
6756 ibx_init_clock_gating(dev
);
6759 static void cpt_init_clock_gating(struct drm_device
*dev
)
6761 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6766 * On Ibex Peak and Cougar Point, we need to disable clock
6767 * gating for the panel power sequencer or it will fail to
6768 * start up when no ports are active.
6770 I915_WRITE(SOUTH_DSPCLK_GATE_D
, PCH_DPLSUNIT_CLOCK_GATE_DISABLE
|
6771 PCH_DPLUNIT_CLOCK_GATE_DISABLE
|
6772 PCH_CPUNIT_CLOCK_GATE_DISABLE
);
6773 I915_WRITE(SOUTH_CHICKEN2
, I915_READ(SOUTH_CHICKEN2
) |
6774 DPLS_EDP_PPS_FIX_DIS
);
6775 /* The below fixes the weird display corruption, a few pixels shifted
6776 * downward, on (only) LVDS of some HP laptops with IVY.
6778 for_each_pipe(dev_priv
, pipe
) {
6779 val
= I915_READ(TRANS_CHICKEN2(pipe
));
6780 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
6781 val
&= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED
;
6782 if (dev_priv
->vbt
.fdi_rx_polarity_inverted
)
6783 val
|= TRANS_CHICKEN2_FDI_POLARITY_REVERSED
;
6784 val
&= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK
;
6785 val
&= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER
;
6786 val
&= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH
;
6787 I915_WRITE(TRANS_CHICKEN2(pipe
), val
);
6789 /* WADP0ClockGatingDisable */
6790 for_each_pipe(dev_priv
, pipe
) {
6791 I915_WRITE(TRANS_CHICKEN1(pipe
),
6792 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE
);
6796 static void gen6_check_mch_setup(struct drm_device
*dev
)
6798 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6801 tmp
= I915_READ(MCH_SSKPD
);
6802 if ((tmp
& MCH_SSKPD_WM0_MASK
) != MCH_SSKPD_WM0_VAL
)
6803 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6807 static void gen6_init_clock_gating(struct drm_device
*dev
)
6809 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6810 uint32_t dspclk_gate
= ILK_VRHUNIT_CLOCK_GATE_DISABLE
;
6812 I915_WRITE(ILK_DSPCLK_GATE_D
, dspclk_gate
);
6814 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
6815 I915_READ(ILK_DISPLAY_CHICKEN2
) |
6816 ILK_ELPIN_409_SELECT
);
6818 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
6819 I915_WRITE(_3D_CHICKEN
,
6820 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB
));
6822 /* WaDisable_RenderCache_OperationalFlush:snb */
6823 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
6826 * BSpec recoomends 8x4 when MSAA is used,
6827 * however in practice 16x4 seems fastest.
6829 * Note that PS/WM thread counts depend on the WIZ hashing
6830 * disable bit, which we don't touch here, but it's good
6831 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6833 I915_WRITE(GEN6_GT_MODE
,
6834 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK
, GEN6_WIZ_HASHING_16x4
));
6836 ilk_init_lp_watermarks(dev
);
6838 I915_WRITE(CACHE_MODE_0
,
6839 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB
));
6841 I915_WRITE(GEN6_UCGCTL1
,
6842 I915_READ(GEN6_UCGCTL1
) |
6843 GEN6_BLBUNIT_CLOCK_GATE_DISABLE
|
6844 GEN6_CSUNIT_CLOCK_GATE_DISABLE
);
6846 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
6847 * gating disable must be set. Failure to set it results in
6848 * flickering pixels due to Z write ordering failures after
6849 * some amount of runtime in the Mesa "fire" demo, and Unigine
6850 * Sanctuary and Tropics, and apparently anything else with
6851 * alpha test or pixel discard.
6853 * According to the spec, bit 11 (RCCUNIT) must also be set,
6854 * but we didn't debug actual testcases to find it out.
6856 * WaDisableRCCUnitClockGating:snb
6857 * WaDisableRCPBUnitClockGating:snb
6859 I915_WRITE(GEN6_UCGCTL2
,
6860 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE
|
6861 GEN6_RCCUNIT_CLOCK_GATE_DISABLE
);
6863 /* WaStripsFansDisableFastClipPerformanceFix:snb */
6864 I915_WRITE(_3D_CHICKEN3
,
6865 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL
));
6869 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
6870 * 3DSTATE_SF number of SF output attributes is more than 16."
6872 I915_WRITE(_3D_CHICKEN3
,
6873 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH
));
6876 * According to the spec the following bits should be
6877 * set in order to enable memory self-refresh and fbc:
6878 * The bit21 and bit22 of 0x42000
6879 * The bit21 and bit22 of 0x42004
6880 * The bit5 and bit7 of 0x42020
6881 * The bit14 of 0x70180
6882 * The bit14 of 0x71180
6884 * WaFbcAsynchFlipDisableFbcQueue:snb
6886 I915_WRITE(ILK_DISPLAY_CHICKEN1
,
6887 I915_READ(ILK_DISPLAY_CHICKEN1
) |
6888 ILK_FBCQ_DIS
| ILK_PABSTRETCH_DIS
);
6889 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
6890 I915_READ(ILK_DISPLAY_CHICKEN2
) |
6891 ILK_DPARB_GATE
| ILK_VSDPFD_FULL
);
6892 I915_WRITE(ILK_DSPCLK_GATE_D
,
6893 I915_READ(ILK_DSPCLK_GATE_D
) |
6894 ILK_DPARBUNIT_CLOCK_GATE_ENABLE
|
6895 ILK_DPFDUNIT_CLOCK_GATE_ENABLE
);
6897 g4x_disable_trickle_feed(dev
);
6899 cpt_init_clock_gating(dev
);
6901 gen6_check_mch_setup(dev
);
6904 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private
*dev_priv
)
6906 uint32_t reg
= I915_READ(GEN7_FF_THREAD_MODE
);
6909 * WaVSThreadDispatchOverride:ivb,vlv
6911 * This actually overrides the dispatch
6912 * mode for all thread types.
6914 reg
&= ~GEN7_FF_SCHED_MASK
;
6915 reg
|= GEN7_FF_TS_SCHED_HW
;
6916 reg
|= GEN7_FF_VS_SCHED_HW
;
6917 reg
|= GEN7_FF_DS_SCHED_HW
;
6919 I915_WRITE(GEN7_FF_THREAD_MODE
, reg
);
6922 static void lpt_init_clock_gating(struct drm_device
*dev
)
6924 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6927 * TODO: this bit should only be enabled when really needed, then
6928 * disabled when not needed anymore in order to save power.
6930 if (HAS_PCH_LPT_LP(dev
))
6931 I915_WRITE(SOUTH_DSPCLK_GATE_D
,
6932 I915_READ(SOUTH_DSPCLK_GATE_D
) |
6933 PCH_LP_PARTITION_LEVEL_DISABLE
);
6935 /* WADPOClockGatingDisable:hsw */
6936 I915_WRITE(TRANS_CHICKEN1(PIPE_A
),
6937 I915_READ(TRANS_CHICKEN1(PIPE_A
)) |
6938 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE
);
6941 static void lpt_suspend_hw(struct drm_device
*dev
)
6943 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6945 if (HAS_PCH_LPT_LP(dev
)) {
6946 uint32_t val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
6948 val
&= ~PCH_LP_PARTITION_LEVEL_DISABLE
;
6949 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
6953 static void gen8_set_l3sqc_credits(struct drm_i915_private
*dev_priv
,
6954 int general_prio_credits
,
6955 int high_prio_credits
)
6959 /* WaTempDisableDOPClkGating:bdw */
6960 misccpctl
= I915_READ(GEN7_MISCCPCTL
);
6961 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
& ~GEN7_DOP_CLOCK_GATE_ENABLE
);
6963 I915_WRITE(GEN8_L3SQCREG1
,
6964 L3_GENERAL_PRIO_CREDITS(general_prio_credits
) |
6965 L3_HIGH_PRIO_CREDITS(high_prio_credits
));
6968 * Wait at least 100 clocks before re-enabling clock gating.
6969 * See the definition of L3SQCREG1 in BSpec.
6971 POSTING_READ(GEN8_L3SQCREG1
);
6973 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
);
6976 static void kabylake_init_clock_gating(struct drm_device
*dev
)
6978 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6980 gen9_init_clock_gating(dev
);
6982 /* WaDisableSDEUnitClockGating:kbl */
6983 if (IS_KBL_REVID(dev_priv
, 0, KBL_REVID_B0
))
6984 I915_WRITE(GEN8_UCGCTL6
, I915_READ(GEN8_UCGCTL6
) |
6985 GEN8_SDEUNIT_CLOCK_GATE_DISABLE
);
6987 /* WaDisableGamClockGating:kbl */
6988 if (IS_KBL_REVID(dev_priv
, 0, KBL_REVID_B0
))
6989 I915_WRITE(GEN6_UCGCTL1
, I915_READ(GEN6_UCGCTL1
) |
6990 GEN6_GAMUNIT_CLOCK_GATE_DISABLE
);
6993 static void skylake_init_clock_gating(struct drm_device
*dev
)
6995 gen9_init_clock_gating(dev
);
6998 static void broadwell_init_clock_gating(struct drm_device
*dev
)
7000 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7003 ilk_init_lp_watermarks(dev
);
7005 /* WaSwitchSolVfFArbitrationPriority:bdw */
7006 I915_WRITE(GAM_ECOCHK
, I915_READ(GAM_ECOCHK
) | HSW_ECOCHK_ARB_PRIO_SOL
);
7008 /* WaPsrDPAMaskVBlankInSRD:bdw */
7009 I915_WRITE(CHICKEN_PAR1_1
,
7010 I915_READ(CHICKEN_PAR1_1
) | DPA_MASK_VBLANK_SRD
);
7012 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
7013 for_each_pipe(dev_priv
, pipe
) {
7014 I915_WRITE(CHICKEN_PIPESL_1(pipe
),
7015 I915_READ(CHICKEN_PIPESL_1(pipe
)) |
7016 BDW_DPRS_MASK_VBLANK_SRD
);
7019 /* WaVSRefCountFullforceMissDisable:bdw */
7020 /* WaDSRefCountFullforceMissDisable:bdw */
7021 I915_WRITE(GEN7_FF_THREAD_MODE
,
7022 I915_READ(GEN7_FF_THREAD_MODE
) &
7023 ~(GEN8_FF_DS_REF_CNT_FFME
| GEN7_FF_VS_REF_CNT_FFME
));
7025 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL
,
7026 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE
));
7028 /* WaDisableSDEUnitClockGating:bdw */
7029 I915_WRITE(GEN8_UCGCTL6
, I915_READ(GEN8_UCGCTL6
) |
7030 GEN8_SDEUNIT_CLOCK_GATE_DISABLE
);
7032 /* WaProgramL3SqcReg1Default:bdw */
7033 gen8_set_l3sqc_credits(dev_priv
, 30, 2);
7036 * WaGttCachingOffByDefault:bdw
7037 * GTT cache may not work with big pages, so if those
7038 * are ever enabled GTT cache may need to be disabled.
7040 I915_WRITE(HSW_GTT_CACHE_EN
, GTT_CACHE_EN_ALL
);
7042 /* WaKVMNotificationOnConfigChange:bdw */
7043 I915_WRITE(CHICKEN_PAR2_1
, I915_READ(CHICKEN_PAR2_1
)
7044 | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT
);
7046 lpt_init_clock_gating(dev
);
7049 static void haswell_init_clock_gating(struct drm_device
*dev
)
7051 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7053 ilk_init_lp_watermarks(dev
);
7055 /* L3 caching of data atomics doesn't work -- disable it. */
7056 I915_WRITE(HSW_SCRATCH1
, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE
);
7057 I915_WRITE(HSW_ROW_CHICKEN3
,
7058 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE
));
7060 /* This is required by WaCatErrorRejectionIssue:hsw */
7061 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
7062 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
7063 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
7065 /* WaVSRefCountFullforceMissDisable:hsw */
7066 I915_WRITE(GEN7_FF_THREAD_MODE
,
7067 I915_READ(GEN7_FF_THREAD_MODE
) & ~GEN7_FF_VS_REF_CNT_FFME
);
7069 /* WaDisable_RenderCache_OperationalFlush:hsw */
7070 I915_WRITE(CACHE_MODE_0_GEN7
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
7072 /* enable HiZ Raw Stall Optimization */
7073 I915_WRITE(CACHE_MODE_0_GEN7
,
7074 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE
));
7076 /* WaDisable4x2SubspanOptimization:hsw */
7077 I915_WRITE(CACHE_MODE_1
,
7078 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
));
7081 * BSpec recommends 8x4 when MSAA is used,
7082 * however in practice 16x4 seems fastest.
7084 * Note that PS/WM thread counts depend on the WIZ hashing
7085 * disable bit, which we don't touch here, but it's good
7086 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7088 I915_WRITE(GEN7_GT_MODE
,
7089 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK
, GEN6_WIZ_HASHING_16x4
));
7091 /* WaSampleCChickenBitEnable:hsw */
7092 I915_WRITE(HALF_SLICE_CHICKEN3
,
7093 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE
));
7095 /* WaSwitchSolVfFArbitrationPriority:hsw */
7096 I915_WRITE(GAM_ECOCHK
, I915_READ(GAM_ECOCHK
) | HSW_ECOCHK_ARB_PRIO_SOL
);
7098 /* WaRsPkgCStateDisplayPMReq:hsw */
7099 I915_WRITE(CHICKEN_PAR1_1
,
7100 I915_READ(CHICKEN_PAR1_1
) | FORCE_ARB_IDLE_PLANES
);
7102 lpt_init_clock_gating(dev
);
7105 static void ivybridge_init_clock_gating(struct drm_device
*dev
)
7107 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7110 ilk_init_lp_watermarks(dev
);
7112 I915_WRITE(ILK_DSPCLK_GATE_D
, ILK_VRHUNIT_CLOCK_GATE_DISABLE
);
7114 /* WaDisableEarlyCull:ivb */
7115 I915_WRITE(_3D_CHICKEN3
,
7116 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL
));
7118 /* WaDisableBackToBackFlipFix:ivb */
7119 I915_WRITE(IVB_CHICKEN3
,
7120 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE
|
7121 CHICKEN3_DGMG_DONE_FIX_DISABLE
);
7123 /* WaDisablePSDDualDispatchEnable:ivb */
7124 if (IS_IVB_GT1(dev
))
7125 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1
,
7126 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE
));
7128 /* WaDisable_RenderCache_OperationalFlush:ivb */
7129 I915_WRITE(CACHE_MODE_0_GEN7
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
7131 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
7132 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1
,
7133 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC
);
7135 /* WaApplyL3ControlAndL3ChickenMode:ivb */
7136 I915_WRITE(GEN7_L3CNTLREG1
,
7137 GEN7_WA_FOR_GEN7_L3_CONTROL
);
7138 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER
,
7139 GEN7_WA_L3_CHICKEN_MODE
);
7140 if (IS_IVB_GT1(dev
))
7141 I915_WRITE(GEN7_ROW_CHICKEN2
,
7142 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
7144 /* must write both registers */
7145 I915_WRITE(GEN7_ROW_CHICKEN2
,
7146 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
7147 I915_WRITE(GEN7_ROW_CHICKEN2_GT2
,
7148 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
7151 /* WaForceL3Serialization:ivb */
7152 I915_WRITE(GEN7_L3SQCREG4
, I915_READ(GEN7_L3SQCREG4
) &
7153 ~L3SQ_URB_READ_CAM_MATCH_DISABLE
);
7156 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
7157 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
7159 I915_WRITE(GEN6_UCGCTL2
,
7160 GEN6_RCZUNIT_CLOCK_GATE_DISABLE
);
7162 /* This is required by WaCatErrorRejectionIssue:ivb */
7163 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
7164 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
7165 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
7167 g4x_disable_trickle_feed(dev
);
7169 gen7_setup_fixed_func_scheduler(dev_priv
);
7171 if (0) { /* causes HiZ corruption on ivb:gt1 */
7172 /* enable HiZ Raw Stall Optimization */
7173 I915_WRITE(CACHE_MODE_0_GEN7
,
7174 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE
));
7177 /* WaDisable4x2SubspanOptimization:ivb */
7178 I915_WRITE(CACHE_MODE_1
,
7179 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
));
7182 * BSpec recommends 8x4 when MSAA is used,
7183 * however in practice 16x4 seems fastest.
7185 * Note that PS/WM thread counts depend on the WIZ hashing
7186 * disable bit, which we don't touch here, but it's good
7187 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7189 I915_WRITE(GEN7_GT_MODE
,
7190 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK
, GEN6_WIZ_HASHING_16x4
));
7192 snpcr
= I915_READ(GEN6_MBCUNIT_SNPCR
);
7193 snpcr
&= ~GEN6_MBC_SNPCR_MASK
;
7194 snpcr
|= GEN6_MBC_SNPCR_MED
;
7195 I915_WRITE(GEN6_MBCUNIT_SNPCR
, snpcr
);
7197 if (!HAS_PCH_NOP(dev
))
7198 cpt_init_clock_gating(dev
);
7200 gen6_check_mch_setup(dev
);
7203 static void valleyview_init_clock_gating(struct drm_device
*dev
)
7205 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7207 /* WaDisableEarlyCull:vlv */
7208 I915_WRITE(_3D_CHICKEN3
,
7209 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL
));
7211 /* WaDisableBackToBackFlipFix:vlv */
7212 I915_WRITE(IVB_CHICKEN3
,
7213 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE
|
7214 CHICKEN3_DGMG_DONE_FIX_DISABLE
);
7216 /* WaPsdDispatchEnable:vlv */
7217 /* WaDisablePSDDualDispatchEnable:vlv */
7218 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1
,
7219 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP
|
7220 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE
));
7222 /* WaDisable_RenderCache_OperationalFlush:vlv */
7223 I915_WRITE(CACHE_MODE_0_GEN7
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
7225 /* WaForceL3Serialization:vlv */
7226 I915_WRITE(GEN7_L3SQCREG4
, I915_READ(GEN7_L3SQCREG4
) &
7227 ~L3SQ_URB_READ_CAM_MATCH_DISABLE
);
7229 /* WaDisableDopClockGating:vlv */
7230 I915_WRITE(GEN7_ROW_CHICKEN2
,
7231 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
7233 /* This is required by WaCatErrorRejectionIssue:vlv */
7234 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
7235 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
7236 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
7238 gen7_setup_fixed_func_scheduler(dev_priv
);
7241 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
7242 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
7244 I915_WRITE(GEN6_UCGCTL2
,
7245 GEN6_RCZUNIT_CLOCK_GATE_DISABLE
);
7247 /* WaDisableL3Bank2xClockGate:vlv
7248 * Disabling L3 clock gating- MMIO 940c[25] = 1
7249 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
7250 I915_WRITE(GEN7_UCGCTL4
,
7251 I915_READ(GEN7_UCGCTL4
) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE
);
7254 * BSpec says this must be set, even though
7255 * WaDisable4x2SubspanOptimization isn't listed for VLV.
7257 I915_WRITE(CACHE_MODE_1
,
7258 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
));
7261 * BSpec recommends 8x4 when MSAA is used,
7262 * however in practice 16x4 seems fastest.
7264 * Note that PS/WM thread counts depend on the WIZ hashing
7265 * disable bit, which we don't touch here, but it's good
7266 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7268 I915_WRITE(GEN7_GT_MODE
,
7269 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK
, GEN6_WIZ_HASHING_16x4
));
7272 * WaIncreaseL3CreditsForVLVB0:vlv
7273 * This is the hardware default actually.
7275 I915_WRITE(GEN7_L3SQCREG1
, VLV_B0_WA_L3SQCREG1_VALUE
);
7278 * WaDisableVLVClockGating_VBIIssue:vlv
7279 * Disable clock gating on th GCFG unit to prevent a delay
7280 * in the reporting of vblank events.
7282 I915_WRITE(VLV_GUNIT_CLOCK_GATE
, GCFG_DIS
);
7285 static void cherryview_init_clock_gating(struct drm_device
*dev
)
7287 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7289 /* WaVSRefCountFullforceMissDisable:chv */
7290 /* WaDSRefCountFullforceMissDisable:chv */
7291 I915_WRITE(GEN7_FF_THREAD_MODE
,
7292 I915_READ(GEN7_FF_THREAD_MODE
) &
7293 ~(GEN8_FF_DS_REF_CNT_FFME
| GEN7_FF_VS_REF_CNT_FFME
));
7295 /* WaDisableSemaphoreAndSyncFlipWait:chv */
7296 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL
,
7297 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE
));
7299 /* WaDisableCSUnitClockGating:chv */
7300 I915_WRITE(GEN6_UCGCTL1
, I915_READ(GEN6_UCGCTL1
) |
7301 GEN6_CSUNIT_CLOCK_GATE_DISABLE
);
7303 /* WaDisableSDEUnitClockGating:chv */
7304 I915_WRITE(GEN8_UCGCTL6
, I915_READ(GEN8_UCGCTL6
) |
7305 GEN8_SDEUNIT_CLOCK_GATE_DISABLE
);
7308 * WaProgramL3SqcReg1Default:chv
7309 * See gfxspecs/Related Documents/Performance Guide/
7310 * LSQC Setting Recommendations.
7312 gen8_set_l3sqc_credits(dev_priv
, 38, 2);
7315 * GTT cache may not work with big pages, so if those
7316 * are ever enabled GTT cache may need to be disabled.
7318 I915_WRITE(HSW_GTT_CACHE_EN
, GTT_CACHE_EN_ALL
);
7321 static void g4x_init_clock_gating(struct drm_device
*dev
)
7323 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7324 uint32_t dspclk_gate
;
7326 I915_WRITE(RENCLK_GATE_D1
, 0);
7327 I915_WRITE(RENCLK_GATE_D2
, VF_UNIT_CLOCK_GATE_DISABLE
|
7328 GS_UNIT_CLOCK_GATE_DISABLE
|
7329 CL_UNIT_CLOCK_GATE_DISABLE
);
7330 I915_WRITE(RAMCLK_GATE_D
, 0);
7331 dspclk_gate
= VRHUNIT_CLOCK_GATE_DISABLE
|
7332 OVRUNIT_CLOCK_GATE_DISABLE
|
7333 OVCUNIT_CLOCK_GATE_DISABLE
;
7335 dspclk_gate
|= DSSUNIT_CLOCK_GATE_DISABLE
;
7336 I915_WRITE(DSPCLK_GATE_D
, dspclk_gate
);
7338 /* WaDisableRenderCachePipelinedFlush */
7339 I915_WRITE(CACHE_MODE_0
,
7340 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE
));
7342 /* WaDisable_RenderCache_OperationalFlush:g4x */
7343 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
7345 g4x_disable_trickle_feed(dev
);
7348 static void crestline_init_clock_gating(struct drm_device
*dev
)
7350 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7352 I915_WRITE(RENCLK_GATE_D1
, I965_RCC_CLOCK_GATE_DISABLE
);
7353 I915_WRITE(RENCLK_GATE_D2
, 0);
7354 I915_WRITE(DSPCLK_GATE_D
, 0);
7355 I915_WRITE(RAMCLK_GATE_D
, 0);
7356 I915_WRITE16(DEUC
, 0);
7357 I915_WRITE(MI_ARB_STATE
,
7358 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
));
7360 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7361 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
7364 static void broadwater_init_clock_gating(struct drm_device
*dev
)
7366 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7368 I915_WRITE(RENCLK_GATE_D1
, I965_RCZ_CLOCK_GATE_DISABLE
|
7369 I965_RCC_CLOCK_GATE_DISABLE
|
7370 I965_RCPB_CLOCK_GATE_DISABLE
|
7371 I965_ISC_CLOCK_GATE_DISABLE
|
7372 I965_FBC_CLOCK_GATE_DISABLE
);
7373 I915_WRITE(RENCLK_GATE_D2
, 0);
7374 I915_WRITE(MI_ARB_STATE
,
7375 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
));
7377 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7378 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
7381 static void gen3_init_clock_gating(struct drm_device
*dev
)
7383 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7384 u32 dstate
= I915_READ(D_STATE
);
7386 dstate
|= DSTATE_PLL_D3_OFF
| DSTATE_GFX_CLOCK_GATING
|
7387 DSTATE_DOT_CLOCK_GATING
;
7388 I915_WRITE(D_STATE
, dstate
);
7390 if (IS_PINEVIEW(dev
))
7391 I915_WRITE(ECOSKPD
, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY
));
7393 /* IIR "flip pending" means done if this bit is set */
7394 I915_WRITE(ECOSKPD
, _MASKED_BIT_DISABLE(ECO_FLIP_DONE
));
7396 /* interrupts should cause a wake up from C3 */
7397 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN
));
7399 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7400 I915_WRITE(MI_ARB_STATE
, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE
));
7402 I915_WRITE(MI_ARB_STATE
,
7403 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
));
7406 static void i85x_init_clock_gating(struct drm_device
*dev
)
7408 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7410 I915_WRITE(RENCLK_GATE_D1
, SV_CLOCK_GATE_DISABLE
);
7412 /* interrupts should cause a wake up from C3 */
7413 I915_WRITE(MI_STATE
, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN
) |
7414 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE
));
7416 I915_WRITE(MEM_MODE
,
7417 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE
));
7420 static void i830_init_clock_gating(struct drm_device
*dev
)
7422 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7424 I915_WRITE(DSPCLK_GATE_D
, OVRUNIT_CLOCK_GATE_DISABLE
);
7426 I915_WRITE(MEM_MODE
,
7427 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE
) |
7428 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE
));
7431 void intel_init_clock_gating(struct drm_device
*dev
)
7433 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7435 dev_priv
->display
.init_clock_gating(dev
);
7438 void intel_suspend_hw(struct drm_device
*dev
)
7440 if (HAS_PCH_LPT(dev
))
7441 lpt_suspend_hw(dev
);
7444 static void nop_init_clock_gating(struct drm_device
*dev
)
7446 DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n");
7450 * intel_init_clock_gating_hooks - setup the clock gating hooks
7451 * @dev_priv: device private
7453 * Setup the hooks that configure which clocks of a given platform can be
7454 * gated and also apply various GT and display specific workarounds for these
7455 * platforms. Note that some GT specific workarounds are applied separately
7456 * when GPU contexts or batchbuffers start their execution.
7458 void intel_init_clock_gating_hooks(struct drm_i915_private
*dev_priv
)
7460 if (IS_SKYLAKE(dev_priv
))
7461 dev_priv
->display
.init_clock_gating
= skylake_init_clock_gating
;
7462 else if (IS_KABYLAKE(dev_priv
))
7463 dev_priv
->display
.init_clock_gating
= kabylake_init_clock_gating
;
7464 else if (IS_BROXTON(dev_priv
))
7465 dev_priv
->display
.init_clock_gating
= bxt_init_clock_gating
;
7466 else if (IS_BROADWELL(dev_priv
))
7467 dev_priv
->display
.init_clock_gating
= broadwell_init_clock_gating
;
7468 else if (IS_CHERRYVIEW(dev_priv
))
7469 dev_priv
->display
.init_clock_gating
= cherryview_init_clock_gating
;
7470 else if (IS_HASWELL(dev_priv
))
7471 dev_priv
->display
.init_clock_gating
= haswell_init_clock_gating
;
7472 else if (IS_IVYBRIDGE(dev_priv
))
7473 dev_priv
->display
.init_clock_gating
= ivybridge_init_clock_gating
;
7474 else if (IS_VALLEYVIEW(dev_priv
))
7475 dev_priv
->display
.init_clock_gating
= valleyview_init_clock_gating
;
7476 else if (IS_GEN6(dev_priv
))
7477 dev_priv
->display
.init_clock_gating
= gen6_init_clock_gating
;
7478 else if (IS_GEN5(dev_priv
))
7479 dev_priv
->display
.init_clock_gating
= ironlake_init_clock_gating
;
7480 else if (IS_G4X(dev_priv
))
7481 dev_priv
->display
.init_clock_gating
= g4x_init_clock_gating
;
7482 else if (IS_CRESTLINE(dev_priv
))
7483 dev_priv
->display
.init_clock_gating
= crestline_init_clock_gating
;
7484 else if (IS_BROADWATER(dev_priv
))
7485 dev_priv
->display
.init_clock_gating
= broadwater_init_clock_gating
;
7486 else if (IS_GEN3(dev_priv
))
7487 dev_priv
->display
.init_clock_gating
= gen3_init_clock_gating
;
7488 else if (IS_I85X(dev_priv
) || IS_I865G(dev_priv
))
7489 dev_priv
->display
.init_clock_gating
= i85x_init_clock_gating
;
7490 else if (IS_GEN2(dev_priv
))
7491 dev_priv
->display
.init_clock_gating
= i830_init_clock_gating
;
7493 MISSING_CASE(INTEL_DEVID(dev_priv
));
7494 dev_priv
->display
.init_clock_gating
= nop_init_clock_gating
;
7498 /* Set up chip specific power management-related functions */
7499 void intel_init_pm(struct drm_device
*dev
)
7501 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7503 intel_fbc_init(dev_priv
);
7506 if (IS_PINEVIEW(dev
))
7507 i915_pineview_get_mem_freq(dev
);
7508 else if (IS_GEN5(dev
))
7509 i915_ironlake_get_mem_freq(dev
);
7511 /* For FIFO watermark updates */
7512 if (INTEL_INFO(dev
)->gen
>= 9) {
7513 skl_setup_wm_latency(dev
);
7514 dev_priv
->display
.update_wm
= skl_update_wm
;
7515 dev_priv
->display
.compute_global_watermarks
= skl_compute_wm
;
7516 } else if (HAS_PCH_SPLIT(dev
)) {
7517 ilk_setup_wm_latency(dev
);
7519 if ((IS_GEN5(dev
) && dev_priv
->wm
.pri_latency
[1] &&
7520 dev_priv
->wm
.spr_latency
[1] && dev_priv
->wm
.cur_latency
[1]) ||
7521 (!IS_GEN5(dev
) && dev_priv
->wm
.pri_latency
[0] &&
7522 dev_priv
->wm
.spr_latency
[0] && dev_priv
->wm
.cur_latency
[0])) {
7523 dev_priv
->display
.compute_pipe_wm
= ilk_compute_pipe_wm
;
7524 dev_priv
->display
.compute_intermediate_wm
=
7525 ilk_compute_intermediate_wm
;
7526 dev_priv
->display
.initial_watermarks
=
7527 ilk_initial_watermarks
;
7528 dev_priv
->display
.optimize_watermarks
=
7529 ilk_optimize_watermarks
;
7531 DRM_DEBUG_KMS("Failed to read display plane latency. "
7534 } else if (IS_CHERRYVIEW(dev
)) {
7535 vlv_setup_wm_latency(dev
);
7536 dev_priv
->display
.update_wm
= vlv_update_wm
;
7537 } else if (IS_VALLEYVIEW(dev
)) {
7538 vlv_setup_wm_latency(dev
);
7539 dev_priv
->display
.update_wm
= vlv_update_wm
;
7540 } else if (IS_PINEVIEW(dev
)) {
7541 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev
),
7544 dev_priv
->mem_freq
)) {
7545 DRM_INFO("failed to find known CxSR latency "
7546 "(found ddr%s fsb freq %d, mem freq %d), "
7548 (dev_priv
->is_ddr3
== 1) ? "3" : "2",
7549 dev_priv
->fsb_freq
, dev_priv
->mem_freq
);
7550 /* Disable CxSR and never update its watermark again */
7551 intel_set_memory_cxsr(dev_priv
, false);
7552 dev_priv
->display
.update_wm
= NULL
;
7554 dev_priv
->display
.update_wm
= pineview_update_wm
;
7555 } else if (IS_G4X(dev
)) {
7556 dev_priv
->display
.update_wm
= g4x_update_wm
;
7557 } else if (IS_GEN4(dev
)) {
7558 dev_priv
->display
.update_wm
= i965_update_wm
;
7559 } else if (IS_GEN3(dev
)) {
7560 dev_priv
->display
.update_wm
= i9xx_update_wm
;
7561 dev_priv
->display
.get_fifo_size
= i9xx_get_fifo_size
;
7562 } else if (IS_GEN2(dev
)) {
7563 if (INTEL_INFO(dev
)->num_pipes
== 1) {
7564 dev_priv
->display
.update_wm
= i845_update_wm
;
7565 dev_priv
->display
.get_fifo_size
= i845_get_fifo_size
;
7567 dev_priv
->display
.update_wm
= i9xx_update_wm
;
7568 dev_priv
->display
.get_fifo_size
= i830_get_fifo_size
;
7571 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
7575 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u32 mbox
, u32
*val
)
7577 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
7579 if (I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) {
7580 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7584 I915_WRITE(GEN6_PCODE_DATA
, *val
);
7585 I915_WRITE(GEN6_PCODE_DATA1
, 0);
7586 I915_WRITE(GEN6_PCODE_MAILBOX
, GEN6_PCODE_READY
| mbox
);
7588 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) == 0,
7590 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox
);
7594 *val
= I915_READ(GEN6_PCODE_DATA
);
7595 I915_WRITE(GEN6_PCODE_DATA
, 0);
7600 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
, u32 mbox
, u32 val
)
7602 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
7604 if (I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) {
7605 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7609 I915_WRITE(GEN6_PCODE_DATA
, val
);
7610 I915_WRITE(GEN6_PCODE_MAILBOX
, GEN6_PCODE_READY
| mbox
);
7612 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) == 0,
7614 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox
);
7618 I915_WRITE(GEN6_PCODE_DATA
, 0);
7623 static int byt_gpu_freq(struct drm_i915_private
*dev_priv
, int val
)
7627 * Slow = Fast = GPLL ref * N
7629 return DIV_ROUND_CLOSEST(dev_priv
->rps
.gpll_ref_freq
* (val
- 0xb7), 1000);
7632 static int byt_freq_opcode(struct drm_i915_private
*dev_priv
, int val
)
7634 return DIV_ROUND_CLOSEST(1000 * val
, dev_priv
->rps
.gpll_ref_freq
) + 0xb7;
7637 static int chv_gpu_freq(struct drm_i915_private
*dev_priv
, int val
)
7641 * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2
7643 return DIV_ROUND_CLOSEST(dev_priv
->rps
.gpll_ref_freq
* val
, 2 * 2 * 1000);
7646 static int chv_freq_opcode(struct drm_i915_private
*dev_priv
, int val
)
7648 /* CHV needs even values */
7649 return DIV_ROUND_CLOSEST(2 * 1000 * val
, dev_priv
->rps
.gpll_ref_freq
) * 2;
7652 int intel_gpu_freq(struct drm_i915_private
*dev_priv
, int val
)
7654 if (IS_GEN9(dev_priv
))
7655 return DIV_ROUND_CLOSEST(val
* GT_FREQUENCY_MULTIPLIER
,
7657 else if (IS_CHERRYVIEW(dev_priv
))
7658 return chv_gpu_freq(dev_priv
, val
);
7659 else if (IS_VALLEYVIEW(dev_priv
))
7660 return byt_gpu_freq(dev_priv
, val
);
7662 return val
* GT_FREQUENCY_MULTIPLIER
;
7665 int intel_freq_opcode(struct drm_i915_private
*dev_priv
, int val
)
7667 if (IS_GEN9(dev_priv
))
7668 return DIV_ROUND_CLOSEST(val
* GEN9_FREQ_SCALER
,
7669 GT_FREQUENCY_MULTIPLIER
);
7670 else if (IS_CHERRYVIEW(dev_priv
))
7671 return chv_freq_opcode(dev_priv
, val
);
7672 else if (IS_VALLEYVIEW(dev_priv
))
7673 return byt_freq_opcode(dev_priv
, val
);
7675 return DIV_ROUND_CLOSEST(val
, GT_FREQUENCY_MULTIPLIER
);
7678 struct request_boost
{
7679 struct work_struct work
;
7680 struct drm_i915_gem_request
*req
;
7683 static void __intel_rps_boost_work(struct work_struct
*work
)
7685 struct request_boost
*boost
= container_of(work
, struct request_boost
, work
);
7686 struct drm_i915_gem_request
*req
= boost
->req
;
7688 if (!i915_gem_request_completed(req
, true))
7689 gen6_rps_boost(req
->i915
, NULL
, req
->emitted_jiffies
);
7691 i915_gem_request_unreference(req
);
7695 void intel_queue_rps_boost_for_request(struct drm_i915_gem_request
*req
)
7697 struct request_boost
*boost
;
7699 if (req
== NULL
|| INTEL_GEN(req
->i915
) < 6)
7702 if (i915_gem_request_completed(req
, true))
7705 boost
= kmalloc(sizeof(*boost
), GFP_ATOMIC
);
7709 i915_gem_request_reference(req
);
7712 INIT_WORK(&boost
->work
, __intel_rps_boost_work
);
7713 queue_work(req
->i915
->wq
, &boost
->work
);
7716 void intel_pm_setup(struct drm_device
*dev
)
7718 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7720 mutex_init(&dev_priv
->rps
.hw_lock
);
7721 spin_lock_init(&dev_priv
->rps
.client_lock
);
7723 INIT_DELAYED_WORK(&dev_priv
->rps
.delayed_resume_work
,
7724 intel_gen6_powersave_work
);
7725 INIT_LIST_HEAD(&dev_priv
->rps
.clients
);
7726 INIT_LIST_HEAD(&dev_priv
->rps
.semaphores
.link
);
7727 INIT_LIST_HEAD(&dev_priv
->rps
.mmioflips
.link
);
7729 dev_priv
->pm
.suspended
= false;
7730 atomic_set(&dev_priv
->pm
.wakeref_count
, 0);
7731 atomic_set(&dev_priv
->pm
.atomic_seq
, 0);