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drm/i915: Tweak RPS thresholds to more aggressively downclock
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_pm.c
1 /*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28 #include <linux/cpufreq.h>
29 #include "i915_drv.h"
30 #include "intel_drv.h"
31 #include "../../../platform/x86/intel_ips.h"
32 #include <linux/module.h>
33 #include <drm/i915_powerwell.h>
34
35 /* FBC, or Frame Buffer Compression, is a technique employed to compress the
36 * framebuffer contents in-memory, aiming at reducing the required bandwidth
37 * during in-memory transfers and, therefore, reduce the power packet.
38 *
39 * The benefits of FBC are mostly visible with solid backgrounds and
40 * variation-less patterns.
41 *
42 * FBC-related functionality can be enabled by the means of the
43 * i915.i915_enable_fbc parameter
44 */
45
46 static void i8xx_disable_fbc(struct drm_device *dev)
47 {
48 struct drm_i915_private *dev_priv = dev->dev_private;
49 u32 fbc_ctl;
50
51 /* Disable compression */
52 fbc_ctl = I915_READ(FBC_CONTROL);
53 if ((fbc_ctl & FBC_CTL_EN) == 0)
54 return;
55
56 fbc_ctl &= ~FBC_CTL_EN;
57 I915_WRITE(FBC_CONTROL, fbc_ctl);
58
59 /* Wait for compressing bit to clear */
60 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
61 DRM_DEBUG_KMS("FBC idle timed out\n");
62 return;
63 }
64
65 DRM_DEBUG_KMS("disabled FBC\n");
66 }
67
68 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
69 {
70 struct drm_device *dev = crtc->dev;
71 struct drm_i915_private *dev_priv = dev->dev_private;
72 struct drm_framebuffer *fb = crtc->fb;
73 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
74 struct drm_i915_gem_object *obj = intel_fb->obj;
75 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
76 int cfb_pitch;
77 int plane, i;
78 u32 fbc_ctl, fbc_ctl2;
79
80 cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
81 if (fb->pitches[0] < cfb_pitch)
82 cfb_pitch = fb->pitches[0];
83
84 /* FBC_CTL wants 64B units */
85 cfb_pitch = (cfb_pitch / 64) - 1;
86 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
87
88 /* Clear old tags */
89 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
90 I915_WRITE(FBC_TAG + (i * 4), 0);
91
92 /* Set it up... */
93 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
94 fbc_ctl2 |= plane;
95 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
96 I915_WRITE(FBC_FENCE_OFF, crtc->y);
97
98 /* enable it... */
99 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
100 if (IS_I945GM(dev))
101 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
102 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
103 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
104 fbc_ctl |= obj->fence_reg;
105 I915_WRITE(FBC_CONTROL, fbc_ctl);
106
107 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c, ",
108 cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
109 }
110
111 static bool i8xx_fbc_enabled(struct drm_device *dev)
112 {
113 struct drm_i915_private *dev_priv = dev->dev_private;
114
115 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
116 }
117
118 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
119 {
120 struct drm_device *dev = crtc->dev;
121 struct drm_i915_private *dev_priv = dev->dev_private;
122 struct drm_framebuffer *fb = crtc->fb;
123 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
124 struct drm_i915_gem_object *obj = intel_fb->obj;
125 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
126 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
127 unsigned long stall_watermark = 200;
128 u32 dpfc_ctl;
129
130 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
131 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
132 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
133
134 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
135 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
136 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
137 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
138
139 /* enable it... */
140 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
141
142 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
143 }
144
145 static void g4x_disable_fbc(struct drm_device *dev)
146 {
147 struct drm_i915_private *dev_priv = dev->dev_private;
148 u32 dpfc_ctl;
149
150 /* Disable compression */
151 dpfc_ctl = I915_READ(DPFC_CONTROL);
152 if (dpfc_ctl & DPFC_CTL_EN) {
153 dpfc_ctl &= ~DPFC_CTL_EN;
154 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
155
156 DRM_DEBUG_KMS("disabled FBC\n");
157 }
158 }
159
160 static bool g4x_fbc_enabled(struct drm_device *dev)
161 {
162 struct drm_i915_private *dev_priv = dev->dev_private;
163
164 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
165 }
166
167 static void sandybridge_blit_fbc_update(struct drm_device *dev)
168 {
169 struct drm_i915_private *dev_priv = dev->dev_private;
170 u32 blt_ecoskpd;
171
172 /* Make sure blitter notifies FBC of writes */
173 gen6_gt_force_wake_get(dev_priv);
174 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
175 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
176 GEN6_BLITTER_LOCK_SHIFT;
177 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
178 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
179 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
180 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
181 GEN6_BLITTER_LOCK_SHIFT);
182 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
183 POSTING_READ(GEN6_BLITTER_ECOSKPD);
184 gen6_gt_force_wake_put(dev_priv);
185 }
186
187 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
188 {
189 struct drm_device *dev = crtc->dev;
190 struct drm_i915_private *dev_priv = dev->dev_private;
191 struct drm_framebuffer *fb = crtc->fb;
192 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
193 struct drm_i915_gem_object *obj = intel_fb->obj;
194 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
195 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
196 unsigned long stall_watermark = 200;
197 u32 dpfc_ctl;
198
199 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
200 dpfc_ctl &= DPFC_RESERVED;
201 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
202 /* Set persistent mode for front-buffer rendering, ala X. */
203 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
204 dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
205 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
206
207 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
208 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
209 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
210 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
211 I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
212 /* enable it... */
213 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
214
215 if (IS_GEN6(dev)) {
216 I915_WRITE(SNB_DPFC_CTL_SA,
217 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
218 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
219 sandybridge_blit_fbc_update(dev);
220 }
221
222 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
223 }
224
225 static void ironlake_disable_fbc(struct drm_device *dev)
226 {
227 struct drm_i915_private *dev_priv = dev->dev_private;
228 u32 dpfc_ctl;
229
230 /* Disable compression */
231 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
232 if (dpfc_ctl & DPFC_CTL_EN) {
233 dpfc_ctl &= ~DPFC_CTL_EN;
234 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
235
236 if (IS_IVYBRIDGE(dev))
237 /* WaFbcDisableDpfcClockGating:ivb */
238 I915_WRITE(ILK_DSPCLK_GATE_D,
239 I915_READ(ILK_DSPCLK_GATE_D) &
240 ~ILK_DPFCUNIT_CLOCK_GATE_DISABLE);
241
242 if (IS_HASWELL(dev))
243 /* WaFbcDisableDpfcClockGating:hsw */
244 I915_WRITE(HSW_CLKGATE_DISABLE_PART_1,
245 I915_READ(HSW_CLKGATE_DISABLE_PART_1) &
246 ~HSW_DPFC_GATING_DISABLE);
247
248 DRM_DEBUG_KMS("disabled FBC\n");
249 }
250 }
251
252 static bool ironlake_fbc_enabled(struct drm_device *dev)
253 {
254 struct drm_i915_private *dev_priv = dev->dev_private;
255
256 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
257 }
258
259 static void gen7_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
260 {
261 struct drm_device *dev = crtc->dev;
262 struct drm_i915_private *dev_priv = dev->dev_private;
263 struct drm_framebuffer *fb = crtc->fb;
264 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
265 struct drm_i915_gem_object *obj = intel_fb->obj;
266 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
267
268 I915_WRITE(IVB_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj));
269
270 I915_WRITE(ILK_DPFC_CONTROL, DPFC_CTL_EN | DPFC_CTL_LIMIT_1X |
271 IVB_DPFC_CTL_FENCE_EN |
272 intel_crtc->plane << IVB_DPFC_CTL_PLANE_SHIFT);
273
274 if (IS_IVYBRIDGE(dev)) {
275 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
276 I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS);
277 /* WaFbcDisableDpfcClockGating:ivb */
278 I915_WRITE(ILK_DSPCLK_GATE_D,
279 I915_READ(ILK_DSPCLK_GATE_D) |
280 ILK_DPFCUNIT_CLOCK_GATE_DISABLE);
281 } else {
282 /* WaFbcAsynchFlipDisableFbcQueue:hsw */
283 I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe),
284 HSW_BYPASS_FBC_QUEUE);
285 /* WaFbcDisableDpfcClockGating:hsw */
286 I915_WRITE(HSW_CLKGATE_DISABLE_PART_1,
287 I915_READ(HSW_CLKGATE_DISABLE_PART_1) |
288 HSW_DPFC_GATING_DISABLE);
289 }
290
291 I915_WRITE(SNB_DPFC_CTL_SA,
292 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
293 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
294
295 sandybridge_blit_fbc_update(dev);
296
297 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
298 }
299
300 bool intel_fbc_enabled(struct drm_device *dev)
301 {
302 struct drm_i915_private *dev_priv = dev->dev_private;
303
304 if (!dev_priv->display.fbc_enabled)
305 return false;
306
307 return dev_priv->display.fbc_enabled(dev);
308 }
309
310 static void intel_fbc_work_fn(struct work_struct *__work)
311 {
312 struct intel_fbc_work *work =
313 container_of(to_delayed_work(__work),
314 struct intel_fbc_work, work);
315 struct drm_device *dev = work->crtc->dev;
316 struct drm_i915_private *dev_priv = dev->dev_private;
317
318 mutex_lock(&dev->struct_mutex);
319 if (work == dev_priv->fbc.fbc_work) {
320 /* Double check that we haven't switched fb without cancelling
321 * the prior work.
322 */
323 if (work->crtc->fb == work->fb) {
324 dev_priv->display.enable_fbc(work->crtc,
325 work->interval);
326
327 dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;
328 dev_priv->fbc.fb_id = work->crtc->fb->base.id;
329 dev_priv->fbc.y = work->crtc->y;
330 }
331
332 dev_priv->fbc.fbc_work = NULL;
333 }
334 mutex_unlock(&dev->struct_mutex);
335
336 kfree(work);
337 }
338
339 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
340 {
341 if (dev_priv->fbc.fbc_work == NULL)
342 return;
343
344 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
345
346 /* Synchronisation is provided by struct_mutex and checking of
347 * dev_priv->fbc.fbc_work, so we can perform the cancellation
348 * entirely asynchronously.
349 */
350 if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
351 /* tasklet was killed before being run, clean up */
352 kfree(dev_priv->fbc.fbc_work);
353
354 /* Mark the work as no longer wanted so that if it does
355 * wake-up (because the work was already running and waiting
356 * for our mutex), it will discover that is no longer
357 * necessary to run.
358 */
359 dev_priv->fbc.fbc_work = NULL;
360 }
361
362 static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
363 {
364 struct intel_fbc_work *work;
365 struct drm_device *dev = crtc->dev;
366 struct drm_i915_private *dev_priv = dev->dev_private;
367
368 if (!dev_priv->display.enable_fbc)
369 return;
370
371 intel_cancel_fbc_work(dev_priv);
372
373 work = kzalloc(sizeof(*work), GFP_KERNEL);
374 if (work == NULL) {
375 DRM_ERROR("Failed to allocate FBC work structure\n");
376 dev_priv->display.enable_fbc(crtc, interval);
377 return;
378 }
379
380 work->crtc = crtc;
381 work->fb = crtc->fb;
382 work->interval = interval;
383 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
384
385 dev_priv->fbc.fbc_work = work;
386
387 /* Delay the actual enabling to let pageflipping cease and the
388 * display to settle before starting the compression. Note that
389 * this delay also serves a second purpose: it allows for a
390 * vblank to pass after disabling the FBC before we attempt
391 * to modify the control registers.
392 *
393 * A more complicated solution would involve tracking vblanks
394 * following the termination of the page-flipping sequence
395 * and indeed performing the enable as a co-routine and not
396 * waiting synchronously upon the vblank.
397 *
398 * WaFbcWaitForVBlankBeforeEnable:ilk,snb
399 */
400 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
401 }
402
403 void intel_disable_fbc(struct drm_device *dev)
404 {
405 struct drm_i915_private *dev_priv = dev->dev_private;
406
407 intel_cancel_fbc_work(dev_priv);
408
409 if (!dev_priv->display.disable_fbc)
410 return;
411
412 dev_priv->display.disable_fbc(dev);
413 dev_priv->fbc.plane = -1;
414 }
415
416 static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
417 enum no_fbc_reason reason)
418 {
419 if (dev_priv->fbc.no_fbc_reason == reason)
420 return false;
421
422 dev_priv->fbc.no_fbc_reason = reason;
423 return true;
424 }
425
426 /**
427 * intel_update_fbc - enable/disable FBC as needed
428 * @dev: the drm_device
429 *
430 * Set up the framebuffer compression hardware at mode set time. We
431 * enable it if possible:
432 * - plane A only (on pre-965)
433 * - no pixel mulitply/line duplication
434 * - no alpha buffer discard
435 * - no dual wide
436 * - framebuffer <= max_hdisplay in width, max_vdisplay in height
437 *
438 * We can't assume that any compression will take place (worst case),
439 * so the compressed buffer has to be the same size as the uncompressed
440 * one. It also must reside (along with the line length buffer) in
441 * stolen memory.
442 *
443 * We need to enable/disable FBC on a global basis.
444 */
445 void intel_update_fbc(struct drm_device *dev)
446 {
447 struct drm_i915_private *dev_priv = dev->dev_private;
448 struct drm_crtc *crtc = NULL, *tmp_crtc;
449 struct intel_crtc *intel_crtc;
450 struct drm_framebuffer *fb;
451 struct intel_framebuffer *intel_fb;
452 struct drm_i915_gem_object *obj;
453 const struct drm_display_mode *adjusted_mode;
454 unsigned int max_width, max_height;
455
456 if (!I915_HAS_FBC(dev)) {
457 set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED);
458 return;
459 }
460
461 if (!i915_powersave) {
462 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
463 DRM_DEBUG_KMS("fbc disabled per module param\n");
464 return;
465 }
466
467 /*
468 * If FBC is already on, we just have to verify that we can
469 * keep it that way...
470 * Need to disable if:
471 * - more than one pipe is active
472 * - changing FBC params (stride, fence, mode)
473 * - new fb is too large to fit in compressed buffer
474 * - going to an unsupported config (interlace, pixel multiply, etc.)
475 */
476 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
477 if (intel_crtc_active(tmp_crtc) &&
478 !to_intel_crtc(tmp_crtc)->primary_disabled) {
479 if (crtc) {
480 if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
481 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
482 goto out_disable;
483 }
484 crtc = tmp_crtc;
485 }
486 }
487
488 if (!crtc || crtc->fb == NULL) {
489 if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
490 DRM_DEBUG_KMS("no output, disabling\n");
491 goto out_disable;
492 }
493
494 intel_crtc = to_intel_crtc(crtc);
495 fb = crtc->fb;
496 intel_fb = to_intel_framebuffer(fb);
497 obj = intel_fb->obj;
498 adjusted_mode = &intel_crtc->config.adjusted_mode;
499
500 if (i915_enable_fbc < 0 &&
501 INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) {
502 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
503 DRM_DEBUG_KMS("disabled per chip default\n");
504 goto out_disable;
505 }
506 if (!i915_enable_fbc) {
507 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
508 DRM_DEBUG_KMS("fbc disabled per module param\n");
509 goto out_disable;
510 }
511 if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ||
512 (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
513 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
514 DRM_DEBUG_KMS("mode incompatible with compression, "
515 "disabling\n");
516 goto out_disable;
517 }
518
519 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
520 max_width = 4096;
521 max_height = 2048;
522 } else {
523 max_width = 2048;
524 max_height = 1536;
525 }
526 if (intel_crtc->config.pipe_src_w > max_width ||
527 intel_crtc->config.pipe_src_h > max_height) {
528 if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
529 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
530 goto out_disable;
531 }
532 if ((IS_I915GM(dev) || IS_I945GM(dev) || IS_HASWELL(dev)) &&
533 intel_crtc->plane != 0) {
534 if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
535 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
536 goto out_disable;
537 }
538
539 /* The use of a CPU fence is mandatory in order to detect writes
540 * by the CPU to the scanout and trigger updates to the FBC.
541 */
542 if (obj->tiling_mode != I915_TILING_X ||
543 obj->fence_reg == I915_FENCE_REG_NONE) {
544 if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED))
545 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
546 goto out_disable;
547 }
548
549 /* If the kernel debugger is active, always disable compression */
550 if (in_dbg_master())
551 goto out_disable;
552
553 if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) {
554 if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL))
555 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
556 goto out_disable;
557 }
558
559 /* If the scanout has not changed, don't modify the FBC settings.
560 * Note that we make the fundamental assumption that the fb->obj
561 * cannot be unpinned (and have its GTT offset and fence revoked)
562 * without first being decoupled from the scanout and FBC disabled.
563 */
564 if (dev_priv->fbc.plane == intel_crtc->plane &&
565 dev_priv->fbc.fb_id == fb->base.id &&
566 dev_priv->fbc.y == crtc->y)
567 return;
568
569 if (intel_fbc_enabled(dev)) {
570 /* We update FBC along two paths, after changing fb/crtc
571 * configuration (modeswitching) and after page-flipping
572 * finishes. For the latter, we know that not only did
573 * we disable the FBC at the start of the page-flip
574 * sequence, but also more than one vblank has passed.
575 *
576 * For the former case of modeswitching, it is possible
577 * to switch between two FBC valid configurations
578 * instantaneously so we do need to disable the FBC
579 * before we can modify its control registers. We also
580 * have to wait for the next vblank for that to take
581 * effect. However, since we delay enabling FBC we can
582 * assume that a vblank has passed since disabling and
583 * that we can safely alter the registers in the deferred
584 * callback.
585 *
586 * In the scenario that we go from a valid to invalid
587 * and then back to valid FBC configuration we have
588 * no strict enforcement that a vblank occurred since
589 * disabling the FBC. However, along all current pipe
590 * disabling paths we do need to wait for a vblank at
591 * some point. And we wait before enabling FBC anyway.
592 */
593 DRM_DEBUG_KMS("disabling active FBC for update\n");
594 intel_disable_fbc(dev);
595 }
596
597 intel_enable_fbc(crtc, 500);
598 dev_priv->fbc.no_fbc_reason = FBC_OK;
599 return;
600
601 out_disable:
602 /* Multiple disables should be harmless */
603 if (intel_fbc_enabled(dev)) {
604 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
605 intel_disable_fbc(dev);
606 }
607 i915_gem_stolen_cleanup_compression(dev);
608 }
609
610 static void i915_pineview_get_mem_freq(struct drm_device *dev)
611 {
612 drm_i915_private_t *dev_priv = dev->dev_private;
613 u32 tmp;
614
615 tmp = I915_READ(CLKCFG);
616
617 switch (tmp & CLKCFG_FSB_MASK) {
618 case CLKCFG_FSB_533:
619 dev_priv->fsb_freq = 533; /* 133*4 */
620 break;
621 case CLKCFG_FSB_800:
622 dev_priv->fsb_freq = 800; /* 200*4 */
623 break;
624 case CLKCFG_FSB_667:
625 dev_priv->fsb_freq = 667; /* 167*4 */
626 break;
627 case CLKCFG_FSB_400:
628 dev_priv->fsb_freq = 400; /* 100*4 */
629 break;
630 }
631
632 switch (tmp & CLKCFG_MEM_MASK) {
633 case CLKCFG_MEM_533:
634 dev_priv->mem_freq = 533;
635 break;
636 case CLKCFG_MEM_667:
637 dev_priv->mem_freq = 667;
638 break;
639 case CLKCFG_MEM_800:
640 dev_priv->mem_freq = 800;
641 break;
642 }
643
644 /* detect pineview DDR3 setting */
645 tmp = I915_READ(CSHRDDR3CTL);
646 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
647 }
648
649 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
650 {
651 drm_i915_private_t *dev_priv = dev->dev_private;
652 u16 ddrpll, csipll;
653
654 ddrpll = I915_READ16(DDRMPLL1);
655 csipll = I915_READ16(CSIPLL0);
656
657 switch (ddrpll & 0xff) {
658 case 0xc:
659 dev_priv->mem_freq = 800;
660 break;
661 case 0x10:
662 dev_priv->mem_freq = 1066;
663 break;
664 case 0x14:
665 dev_priv->mem_freq = 1333;
666 break;
667 case 0x18:
668 dev_priv->mem_freq = 1600;
669 break;
670 default:
671 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
672 ddrpll & 0xff);
673 dev_priv->mem_freq = 0;
674 break;
675 }
676
677 dev_priv->ips.r_t = dev_priv->mem_freq;
678
679 switch (csipll & 0x3ff) {
680 case 0x00c:
681 dev_priv->fsb_freq = 3200;
682 break;
683 case 0x00e:
684 dev_priv->fsb_freq = 3733;
685 break;
686 case 0x010:
687 dev_priv->fsb_freq = 4266;
688 break;
689 case 0x012:
690 dev_priv->fsb_freq = 4800;
691 break;
692 case 0x014:
693 dev_priv->fsb_freq = 5333;
694 break;
695 case 0x016:
696 dev_priv->fsb_freq = 5866;
697 break;
698 case 0x018:
699 dev_priv->fsb_freq = 6400;
700 break;
701 default:
702 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
703 csipll & 0x3ff);
704 dev_priv->fsb_freq = 0;
705 break;
706 }
707
708 if (dev_priv->fsb_freq == 3200) {
709 dev_priv->ips.c_m = 0;
710 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
711 dev_priv->ips.c_m = 1;
712 } else {
713 dev_priv->ips.c_m = 2;
714 }
715 }
716
717 static const struct cxsr_latency cxsr_latency_table[] = {
718 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
719 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
720 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
721 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
722 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
723
724 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
725 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
726 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
727 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
728 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
729
730 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
731 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
732 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
733 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
734 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
735
736 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
737 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
738 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
739 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
740 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
741
742 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
743 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
744 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
745 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
746 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
747
748 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
749 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
750 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
751 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
752 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
753 };
754
755 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
756 int is_ddr3,
757 int fsb,
758 int mem)
759 {
760 const struct cxsr_latency *latency;
761 int i;
762
763 if (fsb == 0 || mem == 0)
764 return NULL;
765
766 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
767 latency = &cxsr_latency_table[i];
768 if (is_desktop == latency->is_desktop &&
769 is_ddr3 == latency->is_ddr3 &&
770 fsb == latency->fsb_freq && mem == latency->mem_freq)
771 return latency;
772 }
773
774 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
775
776 return NULL;
777 }
778
779 static void pineview_disable_cxsr(struct drm_device *dev)
780 {
781 struct drm_i915_private *dev_priv = dev->dev_private;
782
783 /* deactivate cxsr */
784 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
785 }
786
787 /*
788 * Latency for FIFO fetches is dependent on several factors:
789 * - memory configuration (speed, channels)
790 * - chipset
791 * - current MCH state
792 * It can be fairly high in some situations, so here we assume a fairly
793 * pessimal value. It's a tradeoff between extra memory fetches (if we
794 * set this value too high, the FIFO will fetch frequently to stay full)
795 * and power consumption (set it too low to save power and we might see
796 * FIFO underruns and display "flicker").
797 *
798 * A value of 5us seems to be a good balance; safe for very low end
799 * platforms but not overly aggressive on lower latency configs.
800 */
801 static const int latency_ns = 5000;
802
803 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
804 {
805 struct drm_i915_private *dev_priv = dev->dev_private;
806 uint32_t dsparb = I915_READ(DSPARB);
807 int size;
808
809 size = dsparb & 0x7f;
810 if (plane)
811 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
812
813 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
814 plane ? "B" : "A", size);
815
816 return size;
817 }
818
819 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
820 {
821 struct drm_i915_private *dev_priv = dev->dev_private;
822 uint32_t dsparb = I915_READ(DSPARB);
823 int size;
824
825 size = dsparb & 0x1ff;
826 if (plane)
827 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
828 size >>= 1; /* Convert to cachelines */
829
830 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
831 plane ? "B" : "A", size);
832
833 return size;
834 }
835
836 static int i845_get_fifo_size(struct drm_device *dev, int plane)
837 {
838 struct drm_i915_private *dev_priv = dev->dev_private;
839 uint32_t dsparb = I915_READ(DSPARB);
840 int size;
841
842 size = dsparb & 0x7f;
843 size >>= 2; /* Convert to cachelines */
844
845 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
846 plane ? "B" : "A",
847 size);
848
849 return size;
850 }
851
852 static int i830_get_fifo_size(struct drm_device *dev, int plane)
853 {
854 struct drm_i915_private *dev_priv = dev->dev_private;
855 uint32_t dsparb = I915_READ(DSPARB);
856 int size;
857
858 size = dsparb & 0x7f;
859 size >>= 1; /* Convert to cachelines */
860
861 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
862 plane ? "B" : "A", size);
863
864 return size;
865 }
866
867 /* Pineview has different values for various configs */
868 static const struct intel_watermark_params pineview_display_wm = {
869 PINEVIEW_DISPLAY_FIFO,
870 PINEVIEW_MAX_WM,
871 PINEVIEW_DFT_WM,
872 PINEVIEW_GUARD_WM,
873 PINEVIEW_FIFO_LINE_SIZE
874 };
875 static const struct intel_watermark_params pineview_display_hplloff_wm = {
876 PINEVIEW_DISPLAY_FIFO,
877 PINEVIEW_MAX_WM,
878 PINEVIEW_DFT_HPLLOFF_WM,
879 PINEVIEW_GUARD_WM,
880 PINEVIEW_FIFO_LINE_SIZE
881 };
882 static const struct intel_watermark_params pineview_cursor_wm = {
883 PINEVIEW_CURSOR_FIFO,
884 PINEVIEW_CURSOR_MAX_WM,
885 PINEVIEW_CURSOR_DFT_WM,
886 PINEVIEW_CURSOR_GUARD_WM,
887 PINEVIEW_FIFO_LINE_SIZE,
888 };
889 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
890 PINEVIEW_CURSOR_FIFO,
891 PINEVIEW_CURSOR_MAX_WM,
892 PINEVIEW_CURSOR_DFT_WM,
893 PINEVIEW_CURSOR_GUARD_WM,
894 PINEVIEW_FIFO_LINE_SIZE
895 };
896 static const struct intel_watermark_params g4x_wm_info = {
897 G4X_FIFO_SIZE,
898 G4X_MAX_WM,
899 G4X_MAX_WM,
900 2,
901 G4X_FIFO_LINE_SIZE,
902 };
903 static const struct intel_watermark_params g4x_cursor_wm_info = {
904 I965_CURSOR_FIFO,
905 I965_CURSOR_MAX_WM,
906 I965_CURSOR_DFT_WM,
907 2,
908 G4X_FIFO_LINE_SIZE,
909 };
910 static const struct intel_watermark_params valleyview_wm_info = {
911 VALLEYVIEW_FIFO_SIZE,
912 VALLEYVIEW_MAX_WM,
913 VALLEYVIEW_MAX_WM,
914 2,
915 G4X_FIFO_LINE_SIZE,
916 };
917 static const struct intel_watermark_params valleyview_cursor_wm_info = {
918 I965_CURSOR_FIFO,
919 VALLEYVIEW_CURSOR_MAX_WM,
920 I965_CURSOR_DFT_WM,
921 2,
922 G4X_FIFO_LINE_SIZE,
923 };
924 static const struct intel_watermark_params i965_cursor_wm_info = {
925 I965_CURSOR_FIFO,
926 I965_CURSOR_MAX_WM,
927 I965_CURSOR_DFT_WM,
928 2,
929 I915_FIFO_LINE_SIZE,
930 };
931 static const struct intel_watermark_params i945_wm_info = {
932 I945_FIFO_SIZE,
933 I915_MAX_WM,
934 1,
935 2,
936 I915_FIFO_LINE_SIZE
937 };
938 static const struct intel_watermark_params i915_wm_info = {
939 I915_FIFO_SIZE,
940 I915_MAX_WM,
941 1,
942 2,
943 I915_FIFO_LINE_SIZE
944 };
945 static const struct intel_watermark_params i855_wm_info = {
946 I855GM_FIFO_SIZE,
947 I915_MAX_WM,
948 1,
949 2,
950 I830_FIFO_LINE_SIZE
951 };
952 static const struct intel_watermark_params i830_wm_info = {
953 I830_FIFO_SIZE,
954 I915_MAX_WM,
955 1,
956 2,
957 I830_FIFO_LINE_SIZE
958 };
959
960 static const struct intel_watermark_params ironlake_display_wm_info = {
961 ILK_DISPLAY_FIFO,
962 ILK_DISPLAY_MAXWM,
963 ILK_DISPLAY_DFTWM,
964 2,
965 ILK_FIFO_LINE_SIZE
966 };
967 static const struct intel_watermark_params ironlake_cursor_wm_info = {
968 ILK_CURSOR_FIFO,
969 ILK_CURSOR_MAXWM,
970 ILK_CURSOR_DFTWM,
971 2,
972 ILK_FIFO_LINE_SIZE
973 };
974 static const struct intel_watermark_params ironlake_display_srwm_info = {
975 ILK_DISPLAY_SR_FIFO,
976 ILK_DISPLAY_MAX_SRWM,
977 ILK_DISPLAY_DFT_SRWM,
978 2,
979 ILK_FIFO_LINE_SIZE
980 };
981 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
982 ILK_CURSOR_SR_FIFO,
983 ILK_CURSOR_MAX_SRWM,
984 ILK_CURSOR_DFT_SRWM,
985 2,
986 ILK_FIFO_LINE_SIZE
987 };
988
989 static const struct intel_watermark_params sandybridge_display_wm_info = {
990 SNB_DISPLAY_FIFO,
991 SNB_DISPLAY_MAXWM,
992 SNB_DISPLAY_DFTWM,
993 2,
994 SNB_FIFO_LINE_SIZE
995 };
996 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
997 SNB_CURSOR_FIFO,
998 SNB_CURSOR_MAXWM,
999 SNB_CURSOR_DFTWM,
1000 2,
1001 SNB_FIFO_LINE_SIZE
1002 };
1003 static const struct intel_watermark_params sandybridge_display_srwm_info = {
1004 SNB_DISPLAY_SR_FIFO,
1005 SNB_DISPLAY_MAX_SRWM,
1006 SNB_DISPLAY_DFT_SRWM,
1007 2,
1008 SNB_FIFO_LINE_SIZE
1009 };
1010 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
1011 SNB_CURSOR_SR_FIFO,
1012 SNB_CURSOR_MAX_SRWM,
1013 SNB_CURSOR_DFT_SRWM,
1014 2,
1015 SNB_FIFO_LINE_SIZE
1016 };
1017
1018
1019 /**
1020 * intel_calculate_wm - calculate watermark level
1021 * @clock_in_khz: pixel clock
1022 * @wm: chip FIFO params
1023 * @pixel_size: display pixel size
1024 * @latency_ns: memory latency for the platform
1025 *
1026 * Calculate the watermark level (the level at which the display plane will
1027 * start fetching from memory again). Each chip has a different display
1028 * FIFO size and allocation, so the caller needs to figure that out and pass
1029 * in the correct intel_watermark_params structure.
1030 *
1031 * As the pixel clock runs, the FIFO will be drained at a rate that depends
1032 * on the pixel size. When it reaches the watermark level, it'll start
1033 * fetching FIFO line sized based chunks from memory until the FIFO fills
1034 * past the watermark point. If the FIFO drains completely, a FIFO underrun
1035 * will occur, and a display engine hang could result.
1036 */
1037 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
1038 const struct intel_watermark_params *wm,
1039 int fifo_size,
1040 int pixel_size,
1041 unsigned long latency_ns)
1042 {
1043 long entries_required, wm_size;
1044
1045 /*
1046 * Note: we need to make sure we don't overflow for various clock &
1047 * latency values.
1048 * clocks go from a few thousand to several hundred thousand.
1049 * latency is usually a few thousand
1050 */
1051 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
1052 1000;
1053 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
1054
1055 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
1056
1057 wm_size = fifo_size - (entries_required + wm->guard_size);
1058
1059 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
1060
1061 /* Don't promote wm_size to unsigned... */
1062 if (wm_size > (long)wm->max_wm)
1063 wm_size = wm->max_wm;
1064 if (wm_size <= 0)
1065 wm_size = wm->default_wm;
1066 return wm_size;
1067 }
1068
1069 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1070 {
1071 struct drm_crtc *crtc, *enabled = NULL;
1072
1073 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1074 if (intel_crtc_active(crtc)) {
1075 if (enabled)
1076 return NULL;
1077 enabled = crtc;
1078 }
1079 }
1080
1081 return enabled;
1082 }
1083
1084 static void pineview_update_wm(struct drm_crtc *unused_crtc)
1085 {
1086 struct drm_device *dev = unused_crtc->dev;
1087 struct drm_i915_private *dev_priv = dev->dev_private;
1088 struct drm_crtc *crtc;
1089 const struct cxsr_latency *latency;
1090 u32 reg;
1091 unsigned long wm;
1092
1093 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1094 dev_priv->fsb_freq, dev_priv->mem_freq);
1095 if (!latency) {
1096 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1097 pineview_disable_cxsr(dev);
1098 return;
1099 }
1100
1101 crtc = single_enabled_crtc(dev);
1102 if (crtc) {
1103 const struct drm_display_mode *adjusted_mode;
1104 int pixel_size = crtc->fb->bits_per_pixel / 8;
1105 int clock;
1106
1107 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1108 clock = adjusted_mode->crtc_clock;
1109
1110 /* Display SR */
1111 wm = intel_calculate_wm(clock, &pineview_display_wm,
1112 pineview_display_wm.fifo_size,
1113 pixel_size, latency->display_sr);
1114 reg = I915_READ(DSPFW1);
1115 reg &= ~DSPFW_SR_MASK;
1116 reg |= wm << DSPFW_SR_SHIFT;
1117 I915_WRITE(DSPFW1, reg);
1118 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1119
1120 /* cursor SR */
1121 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1122 pineview_display_wm.fifo_size,
1123 pixel_size, latency->cursor_sr);
1124 reg = I915_READ(DSPFW3);
1125 reg &= ~DSPFW_CURSOR_SR_MASK;
1126 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1127 I915_WRITE(DSPFW3, reg);
1128
1129 /* Display HPLL off SR */
1130 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1131 pineview_display_hplloff_wm.fifo_size,
1132 pixel_size, latency->display_hpll_disable);
1133 reg = I915_READ(DSPFW3);
1134 reg &= ~DSPFW_HPLL_SR_MASK;
1135 reg |= wm & DSPFW_HPLL_SR_MASK;
1136 I915_WRITE(DSPFW3, reg);
1137
1138 /* cursor HPLL off SR */
1139 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1140 pineview_display_hplloff_wm.fifo_size,
1141 pixel_size, latency->cursor_hpll_disable);
1142 reg = I915_READ(DSPFW3);
1143 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1144 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1145 I915_WRITE(DSPFW3, reg);
1146 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1147
1148 /* activate cxsr */
1149 I915_WRITE(DSPFW3,
1150 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1151 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1152 } else {
1153 pineview_disable_cxsr(dev);
1154 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1155 }
1156 }
1157
1158 static bool g4x_compute_wm0(struct drm_device *dev,
1159 int plane,
1160 const struct intel_watermark_params *display,
1161 int display_latency_ns,
1162 const struct intel_watermark_params *cursor,
1163 int cursor_latency_ns,
1164 int *plane_wm,
1165 int *cursor_wm)
1166 {
1167 struct drm_crtc *crtc;
1168 const struct drm_display_mode *adjusted_mode;
1169 int htotal, hdisplay, clock, pixel_size;
1170 int line_time_us, line_count;
1171 int entries, tlb_miss;
1172
1173 crtc = intel_get_crtc_for_plane(dev, plane);
1174 if (!intel_crtc_active(crtc)) {
1175 *cursor_wm = cursor->guard_size;
1176 *plane_wm = display->guard_size;
1177 return false;
1178 }
1179
1180 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1181 clock = adjusted_mode->crtc_clock;
1182 htotal = adjusted_mode->htotal;
1183 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1184 pixel_size = crtc->fb->bits_per_pixel / 8;
1185
1186 /* Use the small buffer method to calculate plane watermark */
1187 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1188 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1189 if (tlb_miss > 0)
1190 entries += tlb_miss;
1191 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1192 *plane_wm = entries + display->guard_size;
1193 if (*plane_wm > (int)display->max_wm)
1194 *plane_wm = display->max_wm;
1195
1196 /* Use the large buffer method to calculate cursor watermark */
1197 line_time_us = ((htotal * 1000) / clock);
1198 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1199 entries = line_count * 64 * pixel_size;
1200 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1201 if (tlb_miss > 0)
1202 entries += tlb_miss;
1203 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1204 *cursor_wm = entries + cursor->guard_size;
1205 if (*cursor_wm > (int)cursor->max_wm)
1206 *cursor_wm = (int)cursor->max_wm;
1207
1208 return true;
1209 }
1210
1211 /*
1212 * Check the wm result.
1213 *
1214 * If any calculated watermark values is larger than the maximum value that
1215 * can be programmed into the associated watermark register, that watermark
1216 * must be disabled.
1217 */
1218 static bool g4x_check_srwm(struct drm_device *dev,
1219 int display_wm, int cursor_wm,
1220 const struct intel_watermark_params *display,
1221 const struct intel_watermark_params *cursor)
1222 {
1223 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1224 display_wm, cursor_wm);
1225
1226 if (display_wm > display->max_wm) {
1227 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1228 display_wm, display->max_wm);
1229 return false;
1230 }
1231
1232 if (cursor_wm > cursor->max_wm) {
1233 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1234 cursor_wm, cursor->max_wm);
1235 return false;
1236 }
1237
1238 if (!(display_wm || cursor_wm)) {
1239 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1240 return false;
1241 }
1242
1243 return true;
1244 }
1245
1246 static bool g4x_compute_srwm(struct drm_device *dev,
1247 int plane,
1248 int latency_ns,
1249 const struct intel_watermark_params *display,
1250 const struct intel_watermark_params *cursor,
1251 int *display_wm, int *cursor_wm)
1252 {
1253 struct drm_crtc *crtc;
1254 const struct drm_display_mode *adjusted_mode;
1255 int hdisplay, htotal, pixel_size, clock;
1256 unsigned long line_time_us;
1257 int line_count, line_size;
1258 int small, large;
1259 int entries;
1260
1261 if (!latency_ns) {
1262 *display_wm = *cursor_wm = 0;
1263 return false;
1264 }
1265
1266 crtc = intel_get_crtc_for_plane(dev, plane);
1267 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1268 clock = adjusted_mode->crtc_clock;
1269 htotal = adjusted_mode->htotal;
1270 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1271 pixel_size = crtc->fb->bits_per_pixel / 8;
1272
1273 line_time_us = (htotal * 1000) / clock;
1274 line_count = (latency_ns / line_time_us + 1000) / 1000;
1275 line_size = hdisplay * pixel_size;
1276
1277 /* Use the minimum of the small and large buffer method for primary */
1278 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1279 large = line_count * line_size;
1280
1281 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1282 *display_wm = entries + display->guard_size;
1283
1284 /* calculate the self-refresh watermark for display cursor */
1285 entries = line_count * pixel_size * 64;
1286 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1287 *cursor_wm = entries + cursor->guard_size;
1288
1289 return g4x_check_srwm(dev,
1290 *display_wm, *cursor_wm,
1291 display, cursor);
1292 }
1293
1294 static bool vlv_compute_drain_latency(struct drm_device *dev,
1295 int plane,
1296 int *plane_prec_mult,
1297 int *plane_dl,
1298 int *cursor_prec_mult,
1299 int *cursor_dl)
1300 {
1301 struct drm_crtc *crtc;
1302 int clock, pixel_size;
1303 int entries;
1304
1305 crtc = intel_get_crtc_for_plane(dev, plane);
1306 if (!intel_crtc_active(crtc))
1307 return false;
1308
1309 clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
1310 pixel_size = crtc->fb->bits_per_pixel / 8; /* BPP */
1311
1312 entries = (clock / 1000) * pixel_size;
1313 *plane_prec_mult = (entries > 256) ?
1314 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1315 *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1316 pixel_size);
1317
1318 entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */
1319 *cursor_prec_mult = (entries > 256) ?
1320 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1321 *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1322
1323 return true;
1324 }
1325
1326 /*
1327 * Update drain latency registers of memory arbiter
1328 *
1329 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1330 * to be programmed. Each plane has a drain latency multiplier and a drain
1331 * latency value.
1332 */
1333
1334 static void vlv_update_drain_latency(struct drm_device *dev)
1335 {
1336 struct drm_i915_private *dev_priv = dev->dev_private;
1337 int planea_prec, planea_dl, planeb_prec, planeb_dl;
1338 int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1339 int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1340 either 16 or 32 */
1341
1342 /* For plane A, Cursor A */
1343 if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1344 &cursor_prec_mult, &cursora_dl)) {
1345 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1346 DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1347 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1348 DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1349
1350 I915_WRITE(VLV_DDL1, cursora_prec |
1351 (cursora_dl << DDL_CURSORA_SHIFT) |
1352 planea_prec | planea_dl);
1353 }
1354
1355 /* For plane B, Cursor B */
1356 if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1357 &cursor_prec_mult, &cursorb_dl)) {
1358 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1359 DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1360 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1361 DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1362
1363 I915_WRITE(VLV_DDL2, cursorb_prec |
1364 (cursorb_dl << DDL_CURSORB_SHIFT) |
1365 planeb_prec | planeb_dl);
1366 }
1367 }
1368
1369 #define single_plane_enabled(mask) is_power_of_2(mask)
1370
1371 static void valleyview_update_wm(struct drm_crtc *crtc)
1372 {
1373 struct drm_device *dev = crtc->dev;
1374 static const int sr_latency_ns = 12000;
1375 struct drm_i915_private *dev_priv = dev->dev_private;
1376 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1377 int plane_sr, cursor_sr;
1378 int ignore_plane_sr, ignore_cursor_sr;
1379 unsigned int enabled = 0;
1380
1381 vlv_update_drain_latency(dev);
1382
1383 if (g4x_compute_wm0(dev, PIPE_A,
1384 &valleyview_wm_info, latency_ns,
1385 &valleyview_cursor_wm_info, latency_ns,
1386 &planea_wm, &cursora_wm))
1387 enabled |= 1 << PIPE_A;
1388
1389 if (g4x_compute_wm0(dev, PIPE_B,
1390 &valleyview_wm_info, latency_ns,
1391 &valleyview_cursor_wm_info, latency_ns,
1392 &planeb_wm, &cursorb_wm))
1393 enabled |= 1 << PIPE_B;
1394
1395 if (single_plane_enabled(enabled) &&
1396 g4x_compute_srwm(dev, ffs(enabled) - 1,
1397 sr_latency_ns,
1398 &valleyview_wm_info,
1399 &valleyview_cursor_wm_info,
1400 &plane_sr, &ignore_cursor_sr) &&
1401 g4x_compute_srwm(dev, ffs(enabled) - 1,
1402 2*sr_latency_ns,
1403 &valleyview_wm_info,
1404 &valleyview_cursor_wm_info,
1405 &ignore_plane_sr, &cursor_sr)) {
1406 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
1407 } else {
1408 I915_WRITE(FW_BLC_SELF_VLV,
1409 I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
1410 plane_sr = cursor_sr = 0;
1411 }
1412
1413 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1414 planea_wm, cursora_wm,
1415 planeb_wm, cursorb_wm,
1416 plane_sr, cursor_sr);
1417
1418 I915_WRITE(DSPFW1,
1419 (plane_sr << DSPFW_SR_SHIFT) |
1420 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1421 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1422 planea_wm);
1423 I915_WRITE(DSPFW2,
1424 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1425 (cursora_wm << DSPFW_CURSORA_SHIFT));
1426 I915_WRITE(DSPFW3,
1427 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1428 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1429 }
1430
1431 static void g4x_update_wm(struct drm_crtc *crtc)
1432 {
1433 struct drm_device *dev = crtc->dev;
1434 static const int sr_latency_ns = 12000;
1435 struct drm_i915_private *dev_priv = dev->dev_private;
1436 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1437 int plane_sr, cursor_sr;
1438 unsigned int enabled = 0;
1439
1440 if (g4x_compute_wm0(dev, PIPE_A,
1441 &g4x_wm_info, latency_ns,
1442 &g4x_cursor_wm_info, latency_ns,
1443 &planea_wm, &cursora_wm))
1444 enabled |= 1 << PIPE_A;
1445
1446 if (g4x_compute_wm0(dev, PIPE_B,
1447 &g4x_wm_info, latency_ns,
1448 &g4x_cursor_wm_info, latency_ns,
1449 &planeb_wm, &cursorb_wm))
1450 enabled |= 1 << PIPE_B;
1451
1452 if (single_plane_enabled(enabled) &&
1453 g4x_compute_srwm(dev, ffs(enabled) - 1,
1454 sr_latency_ns,
1455 &g4x_wm_info,
1456 &g4x_cursor_wm_info,
1457 &plane_sr, &cursor_sr)) {
1458 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1459 } else {
1460 I915_WRITE(FW_BLC_SELF,
1461 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
1462 plane_sr = cursor_sr = 0;
1463 }
1464
1465 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1466 planea_wm, cursora_wm,
1467 planeb_wm, cursorb_wm,
1468 plane_sr, cursor_sr);
1469
1470 I915_WRITE(DSPFW1,
1471 (plane_sr << DSPFW_SR_SHIFT) |
1472 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1473 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1474 planea_wm);
1475 I915_WRITE(DSPFW2,
1476 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1477 (cursora_wm << DSPFW_CURSORA_SHIFT));
1478 /* HPLL off in SR has some issues on G4x... disable it */
1479 I915_WRITE(DSPFW3,
1480 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1481 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1482 }
1483
1484 static void i965_update_wm(struct drm_crtc *unused_crtc)
1485 {
1486 struct drm_device *dev = unused_crtc->dev;
1487 struct drm_i915_private *dev_priv = dev->dev_private;
1488 struct drm_crtc *crtc;
1489 int srwm = 1;
1490 int cursor_sr = 16;
1491
1492 /* Calc sr entries for one plane configs */
1493 crtc = single_enabled_crtc(dev);
1494 if (crtc) {
1495 /* self-refresh has much higher latency */
1496 static const int sr_latency_ns = 12000;
1497 const struct drm_display_mode *adjusted_mode =
1498 &to_intel_crtc(crtc)->config.adjusted_mode;
1499 int clock = adjusted_mode->crtc_clock;
1500 int htotal = adjusted_mode->htotal;
1501 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1502 int pixel_size = crtc->fb->bits_per_pixel / 8;
1503 unsigned long line_time_us;
1504 int entries;
1505
1506 line_time_us = ((htotal * 1000) / clock);
1507
1508 /* Use ns/us then divide to preserve precision */
1509 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1510 pixel_size * hdisplay;
1511 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1512 srwm = I965_FIFO_SIZE - entries;
1513 if (srwm < 0)
1514 srwm = 1;
1515 srwm &= 0x1ff;
1516 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1517 entries, srwm);
1518
1519 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1520 pixel_size * 64;
1521 entries = DIV_ROUND_UP(entries,
1522 i965_cursor_wm_info.cacheline_size);
1523 cursor_sr = i965_cursor_wm_info.fifo_size -
1524 (entries + i965_cursor_wm_info.guard_size);
1525
1526 if (cursor_sr > i965_cursor_wm_info.max_wm)
1527 cursor_sr = i965_cursor_wm_info.max_wm;
1528
1529 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1530 "cursor %d\n", srwm, cursor_sr);
1531
1532 if (IS_CRESTLINE(dev))
1533 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1534 } else {
1535 /* Turn off self refresh if both pipes are enabled */
1536 if (IS_CRESTLINE(dev))
1537 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1538 & ~FW_BLC_SELF_EN);
1539 }
1540
1541 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1542 srwm);
1543
1544 /* 965 has limitations... */
1545 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1546 (8 << 16) | (8 << 8) | (8 << 0));
1547 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1548 /* update cursor SR watermark */
1549 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1550 }
1551
1552 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1553 {
1554 struct drm_device *dev = unused_crtc->dev;
1555 struct drm_i915_private *dev_priv = dev->dev_private;
1556 const struct intel_watermark_params *wm_info;
1557 uint32_t fwater_lo;
1558 uint32_t fwater_hi;
1559 int cwm, srwm = 1;
1560 int fifo_size;
1561 int planea_wm, planeb_wm;
1562 struct drm_crtc *crtc, *enabled = NULL;
1563
1564 if (IS_I945GM(dev))
1565 wm_info = &i945_wm_info;
1566 else if (!IS_GEN2(dev))
1567 wm_info = &i915_wm_info;
1568 else
1569 wm_info = &i855_wm_info;
1570
1571 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1572 crtc = intel_get_crtc_for_plane(dev, 0);
1573 if (intel_crtc_active(crtc)) {
1574 const struct drm_display_mode *adjusted_mode;
1575 int cpp = crtc->fb->bits_per_pixel / 8;
1576 if (IS_GEN2(dev))
1577 cpp = 4;
1578
1579 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1580 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1581 wm_info, fifo_size, cpp,
1582 latency_ns);
1583 enabled = crtc;
1584 } else
1585 planea_wm = fifo_size - wm_info->guard_size;
1586
1587 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1588 crtc = intel_get_crtc_for_plane(dev, 1);
1589 if (intel_crtc_active(crtc)) {
1590 const struct drm_display_mode *adjusted_mode;
1591 int cpp = crtc->fb->bits_per_pixel / 8;
1592 if (IS_GEN2(dev))
1593 cpp = 4;
1594
1595 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1596 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1597 wm_info, fifo_size, cpp,
1598 latency_ns);
1599 if (enabled == NULL)
1600 enabled = crtc;
1601 else
1602 enabled = NULL;
1603 } else
1604 planeb_wm = fifo_size - wm_info->guard_size;
1605
1606 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1607
1608 /*
1609 * Overlay gets an aggressive default since video jitter is bad.
1610 */
1611 cwm = 2;
1612
1613 /* Play safe and disable self-refresh before adjusting watermarks. */
1614 if (IS_I945G(dev) || IS_I945GM(dev))
1615 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1616 else if (IS_I915GM(dev))
1617 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
1618
1619 /* Calc sr entries for one plane configs */
1620 if (HAS_FW_BLC(dev) && enabled) {
1621 /* self-refresh has much higher latency */
1622 static const int sr_latency_ns = 6000;
1623 const struct drm_display_mode *adjusted_mode =
1624 &to_intel_crtc(enabled)->config.adjusted_mode;
1625 int clock = adjusted_mode->crtc_clock;
1626 int htotal = adjusted_mode->htotal;
1627 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1628 int pixel_size = enabled->fb->bits_per_pixel / 8;
1629 unsigned long line_time_us;
1630 int entries;
1631
1632 line_time_us = (htotal * 1000) / clock;
1633
1634 /* Use ns/us then divide to preserve precision */
1635 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1636 pixel_size * hdisplay;
1637 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1638 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1639 srwm = wm_info->fifo_size - entries;
1640 if (srwm < 0)
1641 srwm = 1;
1642
1643 if (IS_I945G(dev) || IS_I945GM(dev))
1644 I915_WRITE(FW_BLC_SELF,
1645 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1646 else if (IS_I915GM(dev))
1647 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1648 }
1649
1650 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1651 planea_wm, planeb_wm, cwm, srwm);
1652
1653 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1654 fwater_hi = (cwm & 0x1f);
1655
1656 /* Set request length to 8 cachelines per fetch */
1657 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1658 fwater_hi = fwater_hi | (1 << 8);
1659
1660 I915_WRITE(FW_BLC, fwater_lo);
1661 I915_WRITE(FW_BLC2, fwater_hi);
1662
1663 if (HAS_FW_BLC(dev)) {
1664 if (enabled) {
1665 if (IS_I945G(dev) || IS_I945GM(dev))
1666 I915_WRITE(FW_BLC_SELF,
1667 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1668 else if (IS_I915GM(dev))
1669 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
1670 DRM_DEBUG_KMS("memory self refresh enabled\n");
1671 } else
1672 DRM_DEBUG_KMS("memory self refresh disabled\n");
1673 }
1674 }
1675
1676 static void i830_update_wm(struct drm_crtc *unused_crtc)
1677 {
1678 struct drm_device *dev = unused_crtc->dev;
1679 struct drm_i915_private *dev_priv = dev->dev_private;
1680 struct drm_crtc *crtc;
1681 const struct drm_display_mode *adjusted_mode;
1682 uint32_t fwater_lo;
1683 int planea_wm;
1684
1685 crtc = single_enabled_crtc(dev);
1686 if (crtc == NULL)
1687 return;
1688
1689 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1690 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1691 &i830_wm_info,
1692 dev_priv->display.get_fifo_size(dev, 0),
1693 4, latency_ns);
1694 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1695 fwater_lo |= (3<<8) | planea_wm;
1696
1697 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1698
1699 I915_WRITE(FW_BLC, fwater_lo);
1700 }
1701
1702 /*
1703 * Check the wm result.
1704 *
1705 * If any calculated watermark values is larger than the maximum value that
1706 * can be programmed into the associated watermark register, that watermark
1707 * must be disabled.
1708 */
1709 static bool ironlake_check_srwm(struct drm_device *dev, int level,
1710 int fbc_wm, int display_wm, int cursor_wm,
1711 const struct intel_watermark_params *display,
1712 const struct intel_watermark_params *cursor)
1713 {
1714 struct drm_i915_private *dev_priv = dev->dev_private;
1715
1716 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
1717 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
1718
1719 if (fbc_wm > SNB_FBC_MAX_SRWM) {
1720 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
1721 fbc_wm, SNB_FBC_MAX_SRWM, level);
1722
1723 /* fbc has it's own way to disable FBC WM */
1724 I915_WRITE(DISP_ARB_CTL,
1725 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
1726 return false;
1727 } else if (INTEL_INFO(dev)->gen >= 6) {
1728 /* enable FBC WM (except on ILK, where it must remain off) */
1729 I915_WRITE(DISP_ARB_CTL,
1730 I915_READ(DISP_ARB_CTL) & ~DISP_FBC_WM_DIS);
1731 }
1732
1733 if (display_wm > display->max_wm) {
1734 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
1735 display_wm, SNB_DISPLAY_MAX_SRWM, level);
1736 return false;
1737 }
1738
1739 if (cursor_wm > cursor->max_wm) {
1740 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
1741 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1742 return false;
1743 }
1744
1745 if (!(fbc_wm || display_wm || cursor_wm)) {
1746 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
1747 return false;
1748 }
1749
1750 return true;
1751 }
1752
1753 /*
1754 * Compute watermark values of WM[1-3],
1755 */
1756 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
1757 int latency_ns,
1758 const struct intel_watermark_params *display,
1759 const struct intel_watermark_params *cursor,
1760 int *fbc_wm, int *display_wm, int *cursor_wm)
1761 {
1762 struct drm_crtc *crtc;
1763 const struct drm_display_mode *adjusted_mode;
1764 unsigned long line_time_us;
1765 int hdisplay, htotal, pixel_size, clock;
1766 int line_count, line_size;
1767 int small, large;
1768 int entries;
1769
1770 if (!latency_ns) {
1771 *fbc_wm = *display_wm = *cursor_wm = 0;
1772 return false;
1773 }
1774
1775 crtc = intel_get_crtc_for_plane(dev, plane);
1776 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1777 clock = adjusted_mode->crtc_clock;
1778 htotal = adjusted_mode->htotal;
1779 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1780 pixel_size = crtc->fb->bits_per_pixel / 8;
1781
1782 line_time_us = (htotal * 1000) / clock;
1783 line_count = (latency_ns / line_time_us + 1000) / 1000;
1784 line_size = hdisplay * pixel_size;
1785
1786 /* Use the minimum of the small and large buffer method for primary */
1787 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1788 large = line_count * line_size;
1789
1790 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1791 *display_wm = entries + display->guard_size;
1792
1793 /*
1794 * Spec says:
1795 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
1796 */
1797 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
1798
1799 /* calculate the self-refresh watermark for display cursor */
1800 entries = line_count * pixel_size * 64;
1801 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1802 *cursor_wm = entries + cursor->guard_size;
1803
1804 return ironlake_check_srwm(dev, level,
1805 *fbc_wm, *display_wm, *cursor_wm,
1806 display, cursor);
1807 }
1808
1809 static void ironlake_update_wm(struct drm_crtc *crtc)
1810 {
1811 struct drm_device *dev = crtc->dev;
1812 struct drm_i915_private *dev_priv = dev->dev_private;
1813 int fbc_wm, plane_wm, cursor_wm;
1814 unsigned int enabled;
1815
1816 enabled = 0;
1817 if (g4x_compute_wm0(dev, PIPE_A,
1818 &ironlake_display_wm_info,
1819 dev_priv->wm.pri_latency[0] * 100,
1820 &ironlake_cursor_wm_info,
1821 dev_priv->wm.cur_latency[0] * 100,
1822 &plane_wm, &cursor_wm)) {
1823 I915_WRITE(WM0_PIPEA_ILK,
1824 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1825 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1826 " plane %d, " "cursor: %d\n",
1827 plane_wm, cursor_wm);
1828 enabled |= 1 << PIPE_A;
1829 }
1830
1831 if (g4x_compute_wm0(dev, PIPE_B,
1832 &ironlake_display_wm_info,
1833 dev_priv->wm.pri_latency[0] * 100,
1834 &ironlake_cursor_wm_info,
1835 dev_priv->wm.cur_latency[0] * 100,
1836 &plane_wm, &cursor_wm)) {
1837 I915_WRITE(WM0_PIPEB_ILK,
1838 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1839 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1840 " plane %d, cursor: %d\n",
1841 plane_wm, cursor_wm);
1842 enabled |= 1 << PIPE_B;
1843 }
1844
1845 /*
1846 * Calculate and update the self-refresh watermark only when one
1847 * display plane is used.
1848 */
1849 I915_WRITE(WM3_LP_ILK, 0);
1850 I915_WRITE(WM2_LP_ILK, 0);
1851 I915_WRITE(WM1_LP_ILK, 0);
1852
1853 if (!single_plane_enabled(enabled))
1854 return;
1855 enabled = ffs(enabled) - 1;
1856
1857 /* WM1 */
1858 if (!ironlake_compute_srwm(dev, 1, enabled,
1859 dev_priv->wm.pri_latency[1] * 500,
1860 &ironlake_display_srwm_info,
1861 &ironlake_cursor_srwm_info,
1862 &fbc_wm, &plane_wm, &cursor_wm))
1863 return;
1864
1865 I915_WRITE(WM1_LP_ILK,
1866 WM1_LP_SR_EN |
1867 (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
1868 (fbc_wm << WM1_LP_FBC_SHIFT) |
1869 (plane_wm << WM1_LP_SR_SHIFT) |
1870 cursor_wm);
1871
1872 /* WM2 */
1873 if (!ironlake_compute_srwm(dev, 2, enabled,
1874 dev_priv->wm.pri_latency[2] * 500,
1875 &ironlake_display_srwm_info,
1876 &ironlake_cursor_srwm_info,
1877 &fbc_wm, &plane_wm, &cursor_wm))
1878 return;
1879
1880 I915_WRITE(WM2_LP_ILK,
1881 WM2_LP_EN |
1882 (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
1883 (fbc_wm << WM1_LP_FBC_SHIFT) |
1884 (plane_wm << WM1_LP_SR_SHIFT) |
1885 cursor_wm);
1886
1887 /*
1888 * WM3 is unsupported on ILK, probably because we don't have latency
1889 * data for that power state
1890 */
1891 }
1892
1893 static void sandybridge_update_wm(struct drm_crtc *crtc)
1894 {
1895 struct drm_device *dev = crtc->dev;
1896 struct drm_i915_private *dev_priv = dev->dev_private;
1897 int latency = dev_priv->wm.pri_latency[0] * 100; /* In unit 0.1us */
1898 u32 val;
1899 int fbc_wm, plane_wm, cursor_wm;
1900 unsigned int enabled;
1901
1902 enabled = 0;
1903 if (g4x_compute_wm0(dev, PIPE_A,
1904 &sandybridge_display_wm_info, latency,
1905 &sandybridge_cursor_wm_info, latency,
1906 &plane_wm, &cursor_wm)) {
1907 val = I915_READ(WM0_PIPEA_ILK);
1908 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1909 I915_WRITE(WM0_PIPEA_ILK, val |
1910 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1911 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1912 " plane %d, " "cursor: %d\n",
1913 plane_wm, cursor_wm);
1914 enabled |= 1 << PIPE_A;
1915 }
1916
1917 if (g4x_compute_wm0(dev, PIPE_B,
1918 &sandybridge_display_wm_info, latency,
1919 &sandybridge_cursor_wm_info, latency,
1920 &plane_wm, &cursor_wm)) {
1921 val = I915_READ(WM0_PIPEB_ILK);
1922 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1923 I915_WRITE(WM0_PIPEB_ILK, val |
1924 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1925 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1926 " plane %d, cursor: %d\n",
1927 plane_wm, cursor_wm);
1928 enabled |= 1 << PIPE_B;
1929 }
1930
1931 /*
1932 * Calculate and update the self-refresh watermark only when one
1933 * display plane is used.
1934 *
1935 * SNB support 3 levels of watermark.
1936 *
1937 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1938 * and disabled in the descending order
1939 *
1940 */
1941 I915_WRITE(WM3_LP_ILK, 0);
1942 I915_WRITE(WM2_LP_ILK, 0);
1943 I915_WRITE(WM1_LP_ILK, 0);
1944
1945 if (!single_plane_enabled(enabled) ||
1946 dev_priv->sprite_scaling_enabled)
1947 return;
1948 enabled = ffs(enabled) - 1;
1949
1950 /* WM1 */
1951 if (!ironlake_compute_srwm(dev, 1, enabled,
1952 dev_priv->wm.pri_latency[1] * 500,
1953 &sandybridge_display_srwm_info,
1954 &sandybridge_cursor_srwm_info,
1955 &fbc_wm, &plane_wm, &cursor_wm))
1956 return;
1957
1958 I915_WRITE(WM1_LP_ILK,
1959 WM1_LP_SR_EN |
1960 (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
1961 (fbc_wm << WM1_LP_FBC_SHIFT) |
1962 (plane_wm << WM1_LP_SR_SHIFT) |
1963 cursor_wm);
1964
1965 /* WM2 */
1966 if (!ironlake_compute_srwm(dev, 2, enabled,
1967 dev_priv->wm.pri_latency[2] * 500,
1968 &sandybridge_display_srwm_info,
1969 &sandybridge_cursor_srwm_info,
1970 &fbc_wm, &plane_wm, &cursor_wm))
1971 return;
1972
1973 I915_WRITE(WM2_LP_ILK,
1974 WM2_LP_EN |
1975 (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
1976 (fbc_wm << WM1_LP_FBC_SHIFT) |
1977 (plane_wm << WM1_LP_SR_SHIFT) |
1978 cursor_wm);
1979
1980 /* WM3 */
1981 if (!ironlake_compute_srwm(dev, 3, enabled,
1982 dev_priv->wm.pri_latency[3] * 500,
1983 &sandybridge_display_srwm_info,
1984 &sandybridge_cursor_srwm_info,
1985 &fbc_wm, &plane_wm, &cursor_wm))
1986 return;
1987
1988 I915_WRITE(WM3_LP_ILK,
1989 WM3_LP_EN |
1990 (dev_priv->wm.pri_latency[3] << WM1_LP_LATENCY_SHIFT) |
1991 (fbc_wm << WM1_LP_FBC_SHIFT) |
1992 (plane_wm << WM1_LP_SR_SHIFT) |
1993 cursor_wm);
1994 }
1995
1996 static void ivybridge_update_wm(struct drm_crtc *crtc)
1997 {
1998 struct drm_device *dev = crtc->dev;
1999 struct drm_i915_private *dev_priv = dev->dev_private;
2000 int latency = dev_priv->wm.pri_latency[0] * 100; /* In unit 0.1us */
2001 u32 val;
2002 int fbc_wm, plane_wm, cursor_wm;
2003 int ignore_fbc_wm, ignore_plane_wm, ignore_cursor_wm;
2004 unsigned int enabled;
2005
2006 enabled = 0;
2007 if (g4x_compute_wm0(dev, PIPE_A,
2008 &sandybridge_display_wm_info, latency,
2009 &sandybridge_cursor_wm_info, latency,
2010 &plane_wm, &cursor_wm)) {
2011 val = I915_READ(WM0_PIPEA_ILK);
2012 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2013 I915_WRITE(WM0_PIPEA_ILK, val |
2014 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2015 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
2016 " plane %d, " "cursor: %d\n",
2017 plane_wm, cursor_wm);
2018 enabled |= 1 << PIPE_A;
2019 }
2020
2021 if (g4x_compute_wm0(dev, PIPE_B,
2022 &sandybridge_display_wm_info, latency,
2023 &sandybridge_cursor_wm_info, latency,
2024 &plane_wm, &cursor_wm)) {
2025 val = I915_READ(WM0_PIPEB_ILK);
2026 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2027 I915_WRITE(WM0_PIPEB_ILK, val |
2028 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2029 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
2030 " plane %d, cursor: %d\n",
2031 plane_wm, cursor_wm);
2032 enabled |= 1 << PIPE_B;
2033 }
2034
2035 if (g4x_compute_wm0(dev, PIPE_C,
2036 &sandybridge_display_wm_info, latency,
2037 &sandybridge_cursor_wm_info, latency,
2038 &plane_wm, &cursor_wm)) {
2039 val = I915_READ(WM0_PIPEC_IVB);
2040 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2041 I915_WRITE(WM0_PIPEC_IVB, val |
2042 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2043 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
2044 " plane %d, cursor: %d\n",
2045 plane_wm, cursor_wm);
2046 enabled |= 1 << PIPE_C;
2047 }
2048
2049 /*
2050 * Calculate and update the self-refresh watermark only when one
2051 * display plane is used.
2052 *
2053 * SNB support 3 levels of watermark.
2054 *
2055 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
2056 * and disabled in the descending order
2057 *
2058 */
2059 I915_WRITE(WM3_LP_ILK, 0);
2060 I915_WRITE(WM2_LP_ILK, 0);
2061 I915_WRITE(WM1_LP_ILK, 0);
2062
2063 if (!single_plane_enabled(enabled) ||
2064 dev_priv->sprite_scaling_enabled)
2065 return;
2066 enabled = ffs(enabled) - 1;
2067
2068 /* WM1 */
2069 if (!ironlake_compute_srwm(dev, 1, enabled,
2070 dev_priv->wm.pri_latency[1] * 500,
2071 &sandybridge_display_srwm_info,
2072 &sandybridge_cursor_srwm_info,
2073 &fbc_wm, &plane_wm, &cursor_wm))
2074 return;
2075
2076 I915_WRITE(WM1_LP_ILK,
2077 WM1_LP_SR_EN |
2078 (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
2079 (fbc_wm << WM1_LP_FBC_SHIFT) |
2080 (plane_wm << WM1_LP_SR_SHIFT) |
2081 cursor_wm);
2082
2083 /* WM2 */
2084 if (!ironlake_compute_srwm(dev, 2, enabled,
2085 dev_priv->wm.pri_latency[2] * 500,
2086 &sandybridge_display_srwm_info,
2087 &sandybridge_cursor_srwm_info,
2088 &fbc_wm, &plane_wm, &cursor_wm))
2089 return;
2090
2091 I915_WRITE(WM2_LP_ILK,
2092 WM2_LP_EN |
2093 (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
2094 (fbc_wm << WM1_LP_FBC_SHIFT) |
2095 (plane_wm << WM1_LP_SR_SHIFT) |
2096 cursor_wm);
2097
2098 /* WM3, note we have to correct the cursor latency */
2099 if (!ironlake_compute_srwm(dev, 3, enabled,
2100 dev_priv->wm.pri_latency[3] * 500,
2101 &sandybridge_display_srwm_info,
2102 &sandybridge_cursor_srwm_info,
2103 &fbc_wm, &plane_wm, &ignore_cursor_wm) ||
2104 !ironlake_compute_srwm(dev, 3, enabled,
2105 dev_priv->wm.cur_latency[3] * 500,
2106 &sandybridge_display_srwm_info,
2107 &sandybridge_cursor_srwm_info,
2108 &ignore_fbc_wm, &ignore_plane_wm, &cursor_wm))
2109 return;
2110
2111 I915_WRITE(WM3_LP_ILK,
2112 WM3_LP_EN |
2113 (dev_priv->wm.pri_latency[3] << WM1_LP_LATENCY_SHIFT) |
2114 (fbc_wm << WM1_LP_FBC_SHIFT) |
2115 (plane_wm << WM1_LP_SR_SHIFT) |
2116 cursor_wm);
2117 }
2118
2119 static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
2120 struct drm_crtc *crtc)
2121 {
2122 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2123 uint32_t pixel_rate;
2124
2125 pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock;
2126
2127 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
2128 * adjust the pixel_rate here. */
2129
2130 if (intel_crtc->config.pch_pfit.enabled) {
2131 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
2132 uint32_t pfit_size = intel_crtc->config.pch_pfit.size;
2133
2134 pipe_w = intel_crtc->config.pipe_src_w;
2135 pipe_h = intel_crtc->config.pipe_src_h;
2136 pfit_w = (pfit_size >> 16) & 0xFFFF;
2137 pfit_h = pfit_size & 0xFFFF;
2138 if (pipe_w < pfit_w)
2139 pipe_w = pfit_w;
2140 if (pipe_h < pfit_h)
2141 pipe_h = pfit_h;
2142
2143 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
2144 pfit_w * pfit_h);
2145 }
2146
2147 return pixel_rate;
2148 }
2149
2150 /* latency must be in 0.1us units. */
2151 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
2152 uint32_t latency)
2153 {
2154 uint64_t ret;
2155
2156 if (WARN(latency == 0, "Latency value missing\n"))
2157 return UINT_MAX;
2158
2159 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
2160 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
2161
2162 return ret;
2163 }
2164
2165 /* latency must be in 0.1us units. */
2166 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
2167 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
2168 uint32_t latency)
2169 {
2170 uint32_t ret;
2171
2172 if (WARN(latency == 0, "Latency value missing\n"))
2173 return UINT_MAX;
2174
2175 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
2176 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
2177 ret = DIV_ROUND_UP(ret, 64) + 2;
2178 return ret;
2179 }
2180
2181 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
2182 uint8_t bytes_per_pixel)
2183 {
2184 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
2185 }
2186
2187 struct hsw_pipe_wm_parameters {
2188 bool active;
2189 uint32_t pipe_htotal;
2190 uint32_t pixel_rate;
2191 struct intel_plane_wm_parameters pri;
2192 struct intel_plane_wm_parameters spr;
2193 struct intel_plane_wm_parameters cur;
2194 };
2195
2196 struct hsw_wm_maximums {
2197 uint16_t pri;
2198 uint16_t spr;
2199 uint16_t cur;
2200 uint16_t fbc;
2201 };
2202
2203 struct hsw_wm_values {
2204 uint32_t wm_pipe[3];
2205 uint32_t wm_lp[3];
2206 uint32_t wm_lp_spr[3];
2207 uint32_t wm_linetime[3];
2208 bool enable_fbc_wm;
2209 };
2210
2211 /* used in computing the new watermarks state */
2212 struct intel_wm_config {
2213 unsigned int num_pipes_active;
2214 bool sprites_enabled;
2215 bool sprites_scaled;
2216 bool fbc_wm_enabled;
2217 };
2218
2219 /*
2220 * For both WM_PIPE and WM_LP.
2221 * mem_value must be in 0.1us units.
2222 */
2223 static uint32_t ilk_compute_pri_wm(const struct hsw_pipe_wm_parameters *params,
2224 uint32_t mem_value,
2225 bool is_lp)
2226 {
2227 uint32_t method1, method2;
2228
2229 if (!params->active || !params->pri.enabled)
2230 return 0;
2231
2232 method1 = ilk_wm_method1(params->pixel_rate,
2233 params->pri.bytes_per_pixel,
2234 mem_value);
2235
2236 if (!is_lp)
2237 return method1;
2238
2239 method2 = ilk_wm_method2(params->pixel_rate,
2240 params->pipe_htotal,
2241 params->pri.horiz_pixels,
2242 params->pri.bytes_per_pixel,
2243 mem_value);
2244
2245 return min(method1, method2);
2246 }
2247
2248 /*
2249 * For both WM_PIPE and WM_LP.
2250 * mem_value must be in 0.1us units.
2251 */
2252 static uint32_t ilk_compute_spr_wm(const struct hsw_pipe_wm_parameters *params,
2253 uint32_t mem_value)
2254 {
2255 uint32_t method1, method2;
2256
2257 if (!params->active || !params->spr.enabled)
2258 return 0;
2259
2260 method1 = ilk_wm_method1(params->pixel_rate,
2261 params->spr.bytes_per_pixel,
2262 mem_value);
2263 method2 = ilk_wm_method2(params->pixel_rate,
2264 params->pipe_htotal,
2265 params->spr.horiz_pixels,
2266 params->spr.bytes_per_pixel,
2267 mem_value);
2268 return min(method1, method2);
2269 }
2270
2271 /*
2272 * For both WM_PIPE and WM_LP.
2273 * mem_value must be in 0.1us units.
2274 */
2275 static uint32_t ilk_compute_cur_wm(const struct hsw_pipe_wm_parameters *params,
2276 uint32_t mem_value)
2277 {
2278 if (!params->active || !params->cur.enabled)
2279 return 0;
2280
2281 return ilk_wm_method2(params->pixel_rate,
2282 params->pipe_htotal,
2283 params->cur.horiz_pixels,
2284 params->cur.bytes_per_pixel,
2285 mem_value);
2286 }
2287
2288 /* Only for WM_LP. */
2289 static uint32_t ilk_compute_fbc_wm(const struct hsw_pipe_wm_parameters *params,
2290 uint32_t pri_val)
2291 {
2292 if (!params->active || !params->pri.enabled)
2293 return 0;
2294
2295 return ilk_wm_fbc(pri_val,
2296 params->pri.horiz_pixels,
2297 params->pri.bytes_per_pixel);
2298 }
2299
2300 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
2301 {
2302 if (INTEL_INFO(dev)->gen >= 7)
2303 return 768;
2304 else
2305 return 512;
2306 }
2307
2308 /* Calculate the maximum primary/sprite plane watermark */
2309 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
2310 int level,
2311 const struct intel_wm_config *config,
2312 enum intel_ddb_partitioning ddb_partitioning,
2313 bool is_sprite)
2314 {
2315 unsigned int fifo_size = ilk_display_fifo_size(dev);
2316 unsigned int max;
2317
2318 /* if sprites aren't enabled, sprites get nothing */
2319 if (is_sprite && !config->sprites_enabled)
2320 return 0;
2321
2322 /* HSW allows LP1+ watermarks even with multiple pipes */
2323 if (level == 0 || config->num_pipes_active > 1) {
2324 fifo_size /= INTEL_INFO(dev)->num_pipes;
2325
2326 /*
2327 * For some reason the non self refresh
2328 * FIFO size is only half of the self
2329 * refresh FIFO size on ILK/SNB.
2330 */
2331 if (INTEL_INFO(dev)->gen <= 6)
2332 fifo_size /= 2;
2333 }
2334
2335 if (config->sprites_enabled) {
2336 /* level 0 is always calculated with 1:1 split */
2337 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
2338 if (is_sprite)
2339 fifo_size *= 5;
2340 fifo_size /= 6;
2341 } else {
2342 fifo_size /= 2;
2343 }
2344 }
2345
2346 /* clamp to max that the registers can hold */
2347 if (INTEL_INFO(dev)->gen >= 7)
2348 /* IVB/HSW primary/sprite plane watermarks */
2349 max = level == 0 ? 127 : 1023;
2350 else if (!is_sprite)
2351 /* ILK/SNB primary plane watermarks */
2352 max = level == 0 ? 127 : 511;
2353 else
2354 /* ILK/SNB sprite plane watermarks */
2355 max = level == 0 ? 63 : 255;
2356
2357 return min(fifo_size, max);
2358 }
2359
2360 /* Calculate the maximum cursor plane watermark */
2361 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
2362 int level,
2363 const struct intel_wm_config *config)
2364 {
2365 /* HSW LP1+ watermarks w/ multiple pipes */
2366 if (level > 0 && config->num_pipes_active > 1)
2367 return 64;
2368
2369 /* otherwise just report max that registers can hold */
2370 if (INTEL_INFO(dev)->gen >= 7)
2371 return level == 0 ? 63 : 255;
2372 else
2373 return level == 0 ? 31 : 63;
2374 }
2375
2376 /* Calculate the maximum FBC watermark */
2377 static unsigned int ilk_fbc_wm_max(void)
2378 {
2379 /* max that registers can hold */
2380 return 15;
2381 }
2382
2383 static void ilk_wm_max(struct drm_device *dev,
2384 int level,
2385 const struct intel_wm_config *config,
2386 enum intel_ddb_partitioning ddb_partitioning,
2387 struct hsw_wm_maximums *max)
2388 {
2389 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
2390 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
2391 max->cur = ilk_cursor_wm_max(dev, level, config);
2392 max->fbc = ilk_fbc_wm_max();
2393 }
2394
2395 static bool ilk_check_wm(int level,
2396 const struct hsw_wm_maximums *max,
2397 struct intel_wm_level *result)
2398 {
2399 bool ret;
2400
2401 /* already determined to be invalid? */
2402 if (!result->enable)
2403 return false;
2404
2405 result->enable = result->pri_val <= max->pri &&
2406 result->spr_val <= max->spr &&
2407 result->cur_val <= max->cur;
2408
2409 ret = result->enable;
2410
2411 /*
2412 * HACK until we can pre-compute everything,
2413 * and thus fail gracefully if LP0 watermarks
2414 * are exceeded...
2415 */
2416 if (level == 0 && !result->enable) {
2417 if (result->pri_val > max->pri)
2418 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2419 level, result->pri_val, max->pri);
2420 if (result->spr_val > max->spr)
2421 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2422 level, result->spr_val, max->spr);
2423 if (result->cur_val > max->cur)
2424 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2425 level, result->cur_val, max->cur);
2426
2427 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2428 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2429 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2430 result->enable = true;
2431 }
2432
2433 DRM_DEBUG_KMS("WM%d: %sabled\n", level, result->enable ? "en" : "dis");
2434
2435 return ret;
2436 }
2437
2438 static void ilk_compute_wm_level(struct drm_i915_private *dev_priv,
2439 int level,
2440 const struct hsw_pipe_wm_parameters *p,
2441 struct intel_wm_level *result)
2442 {
2443 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2444 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2445 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2446
2447 /* WM1+ latency values stored in 0.5us units */
2448 if (level > 0) {
2449 pri_latency *= 5;
2450 spr_latency *= 5;
2451 cur_latency *= 5;
2452 }
2453
2454 result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
2455 result->spr_val = ilk_compute_spr_wm(p, spr_latency);
2456 result->cur_val = ilk_compute_cur_wm(p, cur_latency);
2457 result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
2458 result->enable = true;
2459 }
2460
2461 static bool hsw_compute_lp_wm(struct drm_i915_private *dev_priv,
2462 int level, const struct hsw_wm_maximums *max,
2463 const struct hsw_pipe_wm_parameters *params,
2464 struct intel_wm_level *result)
2465 {
2466 enum pipe pipe;
2467 struct intel_wm_level res[3];
2468
2469 for (pipe = PIPE_A; pipe <= PIPE_C; pipe++)
2470 ilk_compute_wm_level(dev_priv, level, &params[pipe], &res[pipe]);
2471
2472 result->pri_val = max3(res[0].pri_val, res[1].pri_val, res[2].pri_val);
2473 result->spr_val = max3(res[0].spr_val, res[1].spr_val, res[2].spr_val);
2474 result->cur_val = max3(res[0].cur_val, res[1].cur_val, res[2].cur_val);
2475 result->fbc_val = max3(res[0].fbc_val, res[1].fbc_val, res[2].fbc_val);
2476 result->enable = true;
2477
2478 return ilk_check_wm(level, max, result);
2479 }
2480
2481
2482 static uint32_t hsw_compute_wm_pipe(struct drm_device *dev,
2483 const struct hsw_pipe_wm_parameters *params)
2484 {
2485 struct drm_i915_private *dev_priv = dev->dev_private;
2486 struct intel_wm_config config = {
2487 .num_pipes_active = 1,
2488 .sprites_enabled = params->spr.enabled,
2489 .sprites_scaled = params->spr.scaled,
2490 };
2491 struct hsw_wm_maximums max;
2492 struct intel_wm_level res;
2493
2494 if (!params->active)
2495 return 0;
2496
2497 ilk_wm_max(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2498
2499 ilk_compute_wm_level(dev_priv, 0, params, &res);
2500
2501 ilk_check_wm(0, &max, &res);
2502
2503 return (res.pri_val << WM0_PIPE_PLANE_SHIFT) |
2504 (res.spr_val << WM0_PIPE_SPRITE_SHIFT) |
2505 res.cur_val;
2506 }
2507
2508 static uint32_t
2509 hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
2510 {
2511 struct drm_i915_private *dev_priv = dev->dev_private;
2512 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2513 struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
2514 u32 linetime, ips_linetime;
2515
2516 if (!intel_crtc_active(crtc))
2517 return 0;
2518
2519 /* The WM are computed with base on how long it takes to fill a single
2520 * row at the given clock rate, multiplied by 8.
2521 * */
2522 linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8, mode->clock);
2523 ips_linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8,
2524 intel_ddi_get_cdclk_freq(dev_priv));
2525
2526 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2527 PIPE_WM_LINETIME_TIME(linetime);
2528 }
2529
2530 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5])
2531 {
2532 struct drm_i915_private *dev_priv = dev->dev_private;
2533
2534 if (IS_HASWELL(dev)) {
2535 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2536
2537 wm[0] = (sskpd >> 56) & 0xFF;
2538 if (wm[0] == 0)
2539 wm[0] = sskpd & 0xF;
2540 wm[1] = (sskpd >> 4) & 0xFF;
2541 wm[2] = (sskpd >> 12) & 0xFF;
2542 wm[3] = (sskpd >> 20) & 0x1FF;
2543 wm[4] = (sskpd >> 32) & 0x1FF;
2544 } else if (INTEL_INFO(dev)->gen >= 6) {
2545 uint32_t sskpd = I915_READ(MCH_SSKPD);
2546
2547 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2548 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2549 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2550 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2551 } else if (INTEL_INFO(dev)->gen >= 5) {
2552 uint32_t mltr = I915_READ(MLTR_ILK);
2553
2554 /* ILK primary LP0 latency is 700 ns */
2555 wm[0] = 7;
2556 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2557 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2558 }
2559 }
2560
2561 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2562 {
2563 /* ILK sprite LP0 latency is 1300 ns */
2564 if (INTEL_INFO(dev)->gen == 5)
2565 wm[0] = 13;
2566 }
2567
2568 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2569 {
2570 /* ILK cursor LP0 latency is 1300 ns */
2571 if (INTEL_INFO(dev)->gen == 5)
2572 wm[0] = 13;
2573
2574 /* WaDoubleCursorLP3Latency:ivb */
2575 if (IS_IVYBRIDGE(dev))
2576 wm[3] *= 2;
2577 }
2578
2579 static int ilk_wm_max_level(const struct drm_device *dev)
2580 {
2581 /* how many WM levels are we expecting */
2582 if (IS_HASWELL(dev))
2583 return 4;
2584 else if (INTEL_INFO(dev)->gen >= 6)
2585 return 3;
2586 else
2587 return 2;
2588 }
2589
2590 static void intel_print_wm_latency(struct drm_device *dev,
2591 const char *name,
2592 const uint16_t wm[5])
2593 {
2594 int level, max_level = ilk_wm_max_level(dev);
2595
2596 for (level = 0; level <= max_level; level++) {
2597 unsigned int latency = wm[level];
2598
2599 if (latency == 0) {
2600 DRM_ERROR("%s WM%d latency not provided\n",
2601 name, level);
2602 continue;
2603 }
2604
2605 /* WM1+ latency values in 0.5us units */
2606 if (level > 0)
2607 latency *= 5;
2608
2609 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2610 name, level, wm[level],
2611 latency / 10, latency % 10);
2612 }
2613 }
2614
2615 static void intel_setup_wm_latency(struct drm_device *dev)
2616 {
2617 struct drm_i915_private *dev_priv = dev->dev_private;
2618
2619 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2620
2621 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2622 sizeof(dev_priv->wm.pri_latency));
2623 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2624 sizeof(dev_priv->wm.pri_latency));
2625
2626 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2627 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2628
2629 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2630 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2631 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2632 }
2633
2634 static void hsw_compute_wm_parameters(struct drm_device *dev,
2635 struct hsw_pipe_wm_parameters *params,
2636 struct hsw_wm_maximums *lp_max_1_2,
2637 struct hsw_wm_maximums *lp_max_5_6)
2638 {
2639 struct drm_crtc *crtc;
2640 struct drm_plane *plane;
2641 enum pipe pipe;
2642 struct intel_wm_config config = {};
2643
2644 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2645 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2646 struct hsw_pipe_wm_parameters *p;
2647
2648 pipe = intel_crtc->pipe;
2649 p = &params[pipe];
2650
2651 p->active = intel_crtc_active(crtc);
2652 if (!p->active)
2653 continue;
2654
2655 config.num_pipes_active++;
2656
2657 p->pipe_htotal = intel_crtc->config.adjusted_mode.htotal;
2658 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
2659 p->pri.bytes_per_pixel = crtc->fb->bits_per_pixel / 8;
2660 p->cur.bytes_per_pixel = 4;
2661 p->pri.horiz_pixels = intel_crtc->config.pipe_src_w;
2662 p->cur.horiz_pixels = 64;
2663 /* TODO: for now, assume primary and cursor planes are always enabled. */
2664 p->pri.enabled = true;
2665 p->cur.enabled = true;
2666 }
2667
2668 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2669 struct intel_plane *intel_plane = to_intel_plane(plane);
2670 struct hsw_pipe_wm_parameters *p;
2671
2672 pipe = intel_plane->pipe;
2673 p = &params[pipe];
2674
2675 p->spr = intel_plane->wm;
2676
2677 config.sprites_enabled |= p->spr.enabled;
2678 config.sprites_scaled |= p->spr.scaled;
2679 }
2680
2681 ilk_wm_max(dev, 1, &config, INTEL_DDB_PART_1_2, lp_max_1_2);
2682
2683 /* 5/6 split only in single pipe config on IVB+ */
2684 if (INTEL_INFO(dev)->gen >= 7 && config.num_pipes_active <= 1)
2685 ilk_wm_max(dev, 1, &config, INTEL_DDB_PART_5_6, lp_max_5_6);
2686 else
2687 *lp_max_5_6 = *lp_max_1_2;
2688 }
2689
2690 static void hsw_compute_wm_results(struct drm_device *dev,
2691 const struct hsw_pipe_wm_parameters *params,
2692 const struct hsw_wm_maximums *lp_maximums,
2693 struct hsw_wm_values *results)
2694 {
2695 struct drm_i915_private *dev_priv = dev->dev_private;
2696 struct drm_crtc *crtc;
2697 struct intel_wm_level lp_results[4] = {};
2698 enum pipe pipe;
2699 int level, max_level, wm_lp;
2700
2701 for (level = 1; level <= 4; level++)
2702 if (!hsw_compute_lp_wm(dev_priv, level,
2703 lp_maximums, params,
2704 &lp_results[level - 1]))
2705 break;
2706 max_level = level - 1;
2707
2708 memset(results, 0, sizeof(*results));
2709
2710 /* The spec says it is preferred to disable FBC WMs instead of disabling
2711 * a WM level. */
2712 results->enable_fbc_wm = true;
2713 for (level = 1; level <= max_level; level++) {
2714 if (lp_results[level - 1].fbc_val > lp_maximums->fbc) {
2715 results->enable_fbc_wm = false;
2716 lp_results[level - 1].fbc_val = 0;
2717 }
2718 }
2719
2720 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2721 const struct intel_wm_level *r;
2722
2723 level = (max_level == 4 && wm_lp > 1) ? wm_lp + 1 : wm_lp;
2724 if (level > max_level)
2725 break;
2726
2727 r = &lp_results[level - 1];
2728 results->wm_lp[wm_lp - 1] = HSW_WM_LP_VAL(level * 2,
2729 r->fbc_val,
2730 r->pri_val,
2731 r->cur_val);
2732 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2733 }
2734
2735 for_each_pipe(pipe)
2736 results->wm_pipe[pipe] = hsw_compute_wm_pipe(dev,
2737 &params[pipe]);
2738
2739 for_each_pipe(pipe) {
2740 crtc = dev_priv->pipe_to_crtc_mapping[pipe];
2741 results->wm_linetime[pipe] = hsw_compute_linetime_wm(dev, crtc);
2742 }
2743 }
2744
2745 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2746 * case both are at the same level. Prefer r1 in case they're the same. */
2747 static struct hsw_wm_values *hsw_find_best_result(struct hsw_wm_values *r1,
2748 struct hsw_wm_values *r2)
2749 {
2750 int i, val_r1 = 0, val_r2 = 0;
2751
2752 for (i = 0; i < 3; i++) {
2753 if (r1->wm_lp[i] & WM3_LP_EN)
2754 val_r1 = r1->wm_lp[i] & WM1_LP_LATENCY_MASK;
2755 if (r2->wm_lp[i] & WM3_LP_EN)
2756 val_r2 = r2->wm_lp[i] & WM1_LP_LATENCY_MASK;
2757 }
2758
2759 if (val_r1 == val_r2) {
2760 if (r2->enable_fbc_wm && !r1->enable_fbc_wm)
2761 return r2;
2762 else
2763 return r1;
2764 } else if (val_r1 > val_r2) {
2765 return r1;
2766 } else {
2767 return r2;
2768 }
2769 }
2770
2771 /*
2772 * The spec says we shouldn't write when we don't need, because every write
2773 * causes WMs to be re-evaluated, expending some power.
2774 */
2775 static void hsw_write_wm_values(struct drm_i915_private *dev_priv,
2776 struct hsw_wm_values *results,
2777 enum intel_ddb_partitioning partitioning)
2778 {
2779 struct hsw_wm_values previous;
2780 uint32_t val;
2781 enum intel_ddb_partitioning prev_partitioning;
2782 bool prev_enable_fbc_wm;
2783
2784 previous.wm_pipe[0] = I915_READ(WM0_PIPEA_ILK);
2785 previous.wm_pipe[1] = I915_READ(WM0_PIPEB_ILK);
2786 previous.wm_pipe[2] = I915_READ(WM0_PIPEC_IVB);
2787 previous.wm_lp[0] = I915_READ(WM1_LP_ILK);
2788 previous.wm_lp[1] = I915_READ(WM2_LP_ILK);
2789 previous.wm_lp[2] = I915_READ(WM3_LP_ILK);
2790 previous.wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
2791 previous.wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
2792 previous.wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
2793 previous.wm_linetime[0] = I915_READ(PIPE_WM_LINETIME(PIPE_A));
2794 previous.wm_linetime[1] = I915_READ(PIPE_WM_LINETIME(PIPE_B));
2795 previous.wm_linetime[2] = I915_READ(PIPE_WM_LINETIME(PIPE_C));
2796
2797 prev_partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
2798 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
2799
2800 prev_enable_fbc_wm = !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
2801
2802 if (memcmp(results->wm_pipe, previous.wm_pipe,
2803 sizeof(results->wm_pipe)) == 0 &&
2804 memcmp(results->wm_lp, previous.wm_lp,
2805 sizeof(results->wm_lp)) == 0 &&
2806 memcmp(results->wm_lp_spr, previous.wm_lp_spr,
2807 sizeof(results->wm_lp_spr)) == 0 &&
2808 memcmp(results->wm_linetime, previous.wm_linetime,
2809 sizeof(results->wm_linetime)) == 0 &&
2810 partitioning == prev_partitioning &&
2811 results->enable_fbc_wm == prev_enable_fbc_wm)
2812 return;
2813
2814 if (previous.wm_lp[2] != 0)
2815 I915_WRITE(WM3_LP_ILK, 0);
2816 if (previous.wm_lp[1] != 0)
2817 I915_WRITE(WM2_LP_ILK, 0);
2818 if (previous.wm_lp[0] != 0)
2819 I915_WRITE(WM1_LP_ILK, 0);
2820
2821 if (previous.wm_pipe[0] != results->wm_pipe[0])
2822 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2823 if (previous.wm_pipe[1] != results->wm_pipe[1])
2824 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2825 if (previous.wm_pipe[2] != results->wm_pipe[2])
2826 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2827
2828 if (previous.wm_linetime[0] != results->wm_linetime[0])
2829 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2830 if (previous.wm_linetime[1] != results->wm_linetime[1])
2831 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2832 if (previous.wm_linetime[2] != results->wm_linetime[2])
2833 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2834
2835 if (prev_partitioning != partitioning) {
2836 val = I915_READ(WM_MISC);
2837 if (partitioning == INTEL_DDB_PART_1_2)
2838 val &= ~WM_MISC_DATA_PARTITION_5_6;
2839 else
2840 val |= WM_MISC_DATA_PARTITION_5_6;
2841 I915_WRITE(WM_MISC, val);
2842 }
2843
2844 if (prev_enable_fbc_wm != results->enable_fbc_wm) {
2845 val = I915_READ(DISP_ARB_CTL);
2846 if (results->enable_fbc_wm)
2847 val &= ~DISP_FBC_WM_DIS;
2848 else
2849 val |= DISP_FBC_WM_DIS;
2850 I915_WRITE(DISP_ARB_CTL, val);
2851 }
2852
2853 if (previous.wm_lp_spr[0] != results->wm_lp_spr[0])
2854 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2855 if (previous.wm_lp_spr[1] != results->wm_lp_spr[1])
2856 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2857 if (previous.wm_lp_spr[2] != results->wm_lp_spr[2])
2858 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2859
2860 if (results->wm_lp[0] != 0)
2861 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2862 if (results->wm_lp[1] != 0)
2863 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2864 if (results->wm_lp[2] != 0)
2865 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2866 }
2867
2868 static void haswell_update_wm(struct drm_crtc *crtc)
2869 {
2870 struct drm_device *dev = crtc->dev;
2871 struct drm_i915_private *dev_priv = dev->dev_private;
2872 struct hsw_wm_maximums lp_max_1_2, lp_max_5_6;
2873 struct hsw_pipe_wm_parameters params[3];
2874 struct hsw_wm_values results_1_2, results_5_6, *best_results;
2875 enum intel_ddb_partitioning partitioning;
2876
2877 hsw_compute_wm_parameters(dev, params, &lp_max_1_2, &lp_max_5_6);
2878
2879 hsw_compute_wm_results(dev, params,
2880 &lp_max_1_2, &results_1_2);
2881 if (lp_max_1_2.pri != lp_max_5_6.pri) {
2882 hsw_compute_wm_results(dev, params,
2883 &lp_max_5_6, &results_5_6);
2884 best_results = hsw_find_best_result(&results_1_2, &results_5_6);
2885 } else {
2886 best_results = &results_1_2;
2887 }
2888
2889 partitioning = (best_results == &results_1_2) ?
2890 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
2891
2892 hsw_write_wm_values(dev_priv, best_results, partitioning);
2893 }
2894
2895 static void haswell_update_sprite_wm(struct drm_plane *plane,
2896 struct drm_crtc *crtc,
2897 uint32_t sprite_width, int pixel_size,
2898 bool enabled, bool scaled)
2899 {
2900 struct intel_plane *intel_plane = to_intel_plane(plane);
2901
2902 intel_plane->wm.enabled = enabled;
2903 intel_plane->wm.scaled = scaled;
2904 intel_plane->wm.horiz_pixels = sprite_width;
2905 intel_plane->wm.bytes_per_pixel = pixel_size;
2906
2907 haswell_update_wm(crtc);
2908 }
2909
2910 static bool
2911 sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
2912 uint32_t sprite_width, int pixel_size,
2913 const struct intel_watermark_params *display,
2914 int display_latency_ns, int *sprite_wm)
2915 {
2916 struct drm_crtc *crtc;
2917 int clock;
2918 int entries, tlb_miss;
2919
2920 crtc = intel_get_crtc_for_plane(dev, plane);
2921 if (!intel_crtc_active(crtc)) {
2922 *sprite_wm = display->guard_size;
2923 return false;
2924 }
2925
2926 clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
2927
2928 /* Use the small buffer method to calculate the sprite watermark */
2929 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
2930 tlb_miss = display->fifo_size*display->cacheline_size -
2931 sprite_width * 8;
2932 if (tlb_miss > 0)
2933 entries += tlb_miss;
2934 entries = DIV_ROUND_UP(entries, display->cacheline_size);
2935 *sprite_wm = entries + display->guard_size;
2936 if (*sprite_wm > (int)display->max_wm)
2937 *sprite_wm = display->max_wm;
2938
2939 return true;
2940 }
2941
2942 static bool
2943 sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
2944 uint32_t sprite_width, int pixel_size,
2945 const struct intel_watermark_params *display,
2946 int latency_ns, int *sprite_wm)
2947 {
2948 struct drm_crtc *crtc;
2949 unsigned long line_time_us;
2950 int clock;
2951 int line_count, line_size;
2952 int small, large;
2953 int entries;
2954
2955 if (!latency_ns) {
2956 *sprite_wm = 0;
2957 return false;
2958 }
2959
2960 crtc = intel_get_crtc_for_plane(dev, plane);
2961 clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
2962 if (!clock) {
2963 *sprite_wm = 0;
2964 return false;
2965 }
2966
2967 line_time_us = (sprite_width * 1000) / clock;
2968 if (!line_time_us) {
2969 *sprite_wm = 0;
2970 return false;
2971 }
2972
2973 line_count = (latency_ns / line_time_us + 1000) / 1000;
2974 line_size = sprite_width * pixel_size;
2975
2976 /* Use the minimum of the small and large buffer method for primary */
2977 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
2978 large = line_count * line_size;
2979
2980 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
2981 *sprite_wm = entries + display->guard_size;
2982
2983 return *sprite_wm > 0x3ff ? false : true;
2984 }
2985
2986 static void sandybridge_update_sprite_wm(struct drm_plane *plane,
2987 struct drm_crtc *crtc,
2988 uint32_t sprite_width, int pixel_size,
2989 bool enabled, bool scaled)
2990 {
2991 struct drm_device *dev = plane->dev;
2992 struct drm_i915_private *dev_priv = dev->dev_private;
2993 int pipe = to_intel_plane(plane)->pipe;
2994 int latency = dev_priv->wm.spr_latency[0] * 100; /* In unit 0.1us */
2995 u32 val;
2996 int sprite_wm, reg;
2997 int ret;
2998
2999 if (!enabled)
3000 return;
3001
3002 switch (pipe) {
3003 case 0:
3004 reg = WM0_PIPEA_ILK;
3005 break;
3006 case 1:
3007 reg = WM0_PIPEB_ILK;
3008 break;
3009 case 2:
3010 reg = WM0_PIPEC_IVB;
3011 break;
3012 default:
3013 return; /* bad pipe */
3014 }
3015
3016 ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
3017 &sandybridge_display_wm_info,
3018 latency, &sprite_wm);
3019 if (!ret) {
3020 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %c\n",
3021 pipe_name(pipe));
3022 return;
3023 }
3024
3025 val = I915_READ(reg);
3026 val &= ~WM0_PIPE_SPRITE_MASK;
3027 I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
3028 DRM_DEBUG_KMS("sprite watermarks For pipe %c - %d\n", pipe_name(pipe), sprite_wm);
3029
3030
3031 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
3032 pixel_size,
3033 &sandybridge_display_srwm_info,
3034 dev_priv->wm.spr_latency[1] * 500,
3035 &sprite_wm);
3036 if (!ret) {
3037 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %c\n",
3038 pipe_name(pipe));
3039 return;
3040 }
3041 I915_WRITE(WM1S_LP_ILK, sprite_wm);
3042
3043 /* Only IVB has two more LP watermarks for sprite */
3044 if (!IS_IVYBRIDGE(dev))
3045 return;
3046
3047 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
3048 pixel_size,
3049 &sandybridge_display_srwm_info,
3050 dev_priv->wm.spr_latency[2] * 500,
3051 &sprite_wm);
3052 if (!ret) {
3053 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %c\n",
3054 pipe_name(pipe));
3055 return;
3056 }
3057 I915_WRITE(WM2S_LP_IVB, sprite_wm);
3058
3059 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
3060 pixel_size,
3061 &sandybridge_display_srwm_info,
3062 dev_priv->wm.spr_latency[3] * 500,
3063 &sprite_wm);
3064 if (!ret) {
3065 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %c\n",
3066 pipe_name(pipe));
3067 return;
3068 }
3069 I915_WRITE(WM3S_LP_IVB, sprite_wm);
3070 }
3071
3072 /**
3073 * intel_update_watermarks - update FIFO watermark values based on current modes
3074 *
3075 * Calculate watermark values for the various WM regs based on current mode
3076 * and plane configuration.
3077 *
3078 * There are several cases to deal with here:
3079 * - normal (i.e. non-self-refresh)
3080 * - self-refresh (SR) mode
3081 * - lines are large relative to FIFO size (buffer can hold up to 2)
3082 * - lines are small relative to FIFO size (buffer can hold more than 2
3083 * lines), so need to account for TLB latency
3084 *
3085 * The normal calculation is:
3086 * watermark = dotclock * bytes per pixel * latency
3087 * where latency is platform & configuration dependent (we assume pessimal
3088 * values here).
3089 *
3090 * The SR calculation is:
3091 * watermark = (trunc(latency/line time)+1) * surface width *
3092 * bytes per pixel
3093 * where
3094 * line time = htotal / dotclock
3095 * surface width = hdisplay for normal plane and 64 for cursor
3096 * and latency is assumed to be high, as above.
3097 *
3098 * The final value programmed to the register should always be rounded up,
3099 * and include an extra 2 entries to account for clock crossings.
3100 *
3101 * We don't use the sprite, so we can ignore that. And on Crestline we have
3102 * to set the non-SR watermarks to 8.
3103 */
3104 void intel_update_watermarks(struct drm_crtc *crtc)
3105 {
3106 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
3107
3108 if (dev_priv->display.update_wm)
3109 dev_priv->display.update_wm(crtc);
3110 }
3111
3112 void intel_update_sprite_watermarks(struct drm_plane *plane,
3113 struct drm_crtc *crtc,
3114 uint32_t sprite_width, int pixel_size,
3115 bool enabled, bool scaled)
3116 {
3117 struct drm_i915_private *dev_priv = plane->dev->dev_private;
3118
3119 if (dev_priv->display.update_sprite_wm)
3120 dev_priv->display.update_sprite_wm(plane, crtc, sprite_width,
3121 pixel_size, enabled, scaled);
3122 }
3123
3124 static struct drm_i915_gem_object *
3125 intel_alloc_context_page(struct drm_device *dev)
3126 {
3127 struct drm_i915_gem_object *ctx;
3128 int ret;
3129
3130 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3131
3132 ctx = i915_gem_alloc_object(dev, 4096);
3133 if (!ctx) {
3134 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
3135 return NULL;
3136 }
3137
3138 ret = i915_gem_obj_ggtt_pin(ctx, 4096, true, false);
3139 if (ret) {
3140 DRM_ERROR("failed to pin power context: %d\n", ret);
3141 goto err_unref;
3142 }
3143
3144 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
3145 if (ret) {
3146 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
3147 goto err_unpin;
3148 }
3149
3150 return ctx;
3151
3152 err_unpin:
3153 i915_gem_object_unpin(ctx);
3154 err_unref:
3155 drm_gem_object_unreference(&ctx->base);
3156 return NULL;
3157 }
3158
3159 /**
3160 * Lock protecting IPS related data structures
3161 */
3162 DEFINE_SPINLOCK(mchdev_lock);
3163
3164 /* Global for IPS driver to get at the current i915 device. Protected by
3165 * mchdev_lock. */
3166 static struct drm_i915_private *i915_mch_dev;
3167
3168 bool ironlake_set_drps(struct drm_device *dev, u8 val)
3169 {
3170 struct drm_i915_private *dev_priv = dev->dev_private;
3171 u16 rgvswctl;
3172
3173 assert_spin_locked(&mchdev_lock);
3174
3175 rgvswctl = I915_READ16(MEMSWCTL);
3176 if (rgvswctl & MEMCTL_CMD_STS) {
3177 DRM_DEBUG("gpu busy, RCS change rejected\n");
3178 return false; /* still busy with another command */
3179 }
3180
3181 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
3182 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
3183 I915_WRITE16(MEMSWCTL, rgvswctl);
3184 POSTING_READ16(MEMSWCTL);
3185
3186 rgvswctl |= MEMCTL_CMD_STS;
3187 I915_WRITE16(MEMSWCTL, rgvswctl);
3188
3189 return true;
3190 }
3191
3192 static void ironlake_enable_drps(struct drm_device *dev)
3193 {
3194 struct drm_i915_private *dev_priv = dev->dev_private;
3195 u32 rgvmodectl = I915_READ(MEMMODECTL);
3196 u8 fmax, fmin, fstart, vstart;
3197
3198 spin_lock_irq(&mchdev_lock);
3199
3200 /* Enable temp reporting */
3201 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
3202 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
3203
3204 /* 100ms RC evaluation intervals */
3205 I915_WRITE(RCUPEI, 100000);
3206 I915_WRITE(RCDNEI, 100000);
3207
3208 /* Set max/min thresholds to 90ms and 80ms respectively */
3209 I915_WRITE(RCBMAXAVG, 90000);
3210 I915_WRITE(RCBMINAVG, 80000);
3211
3212 I915_WRITE(MEMIHYST, 1);
3213
3214 /* Set up min, max, and cur for interrupt handling */
3215 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
3216 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
3217 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
3218 MEMMODE_FSTART_SHIFT;
3219
3220 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
3221 PXVFREQ_PX_SHIFT;
3222
3223 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
3224 dev_priv->ips.fstart = fstart;
3225
3226 dev_priv->ips.max_delay = fstart;
3227 dev_priv->ips.min_delay = fmin;
3228 dev_priv->ips.cur_delay = fstart;
3229
3230 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
3231 fmax, fmin, fstart);
3232
3233 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
3234
3235 /*
3236 * Interrupts will be enabled in ironlake_irq_postinstall
3237 */
3238
3239 I915_WRITE(VIDSTART, vstart);
3240 POSTING_READ(VIDSTART);
3241
3242 rgvmodectl |= MEMMODE_SWMODE_EN;
3243 I915_WRITE(MEMMODECTL, rgvmodectl);
3244
3245 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
3246 DRM_ERROR("stuck trying to change perf mode\n");
3247 mdelay(1);
3248
3249 ironlake_set_drps(dev, fstart);
3250
3251 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
3252 I915_READ(0x112e0);
3253 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
3254 dev_priv->ips.last_count2 = I915_READ(0x112f4);
3255 getrawmonotonic(&dev_priv->ips.last_time2);
3256
3257 spin_unlock_irq(&mchdev_lock);
3258 }
3259
3260 static void ironlake_disable_drps(struct drm_device *dev)
3261 {
3262 struct drm_i915_private *dev_priv = dev->dev_private;
3263 u16 rgvswctl;
3264
3265 spin_lock_irq(&mchdev_lock);
3266
3267 rgvswctl = I915_READ16(MEMSWCTL);
3268
3269 /* Ack interrupts, disable EFC interrupt */
3270 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
3271 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
3272 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
3273 I915_WRITE(DEIIR, DE_PCU_EVENT);
3274 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
3275
3276 /* Go back to the starting frequency */
3277 ironlake_set_drps(dev, dev_priv->ips.fstart);
3278 mdelay(1);
3279 rgvswctl |= MEMCTL_CMD_STS;
3280 I915_WRITE(MEMSWCTL, rgvswctl);
3281 mdelay(1);
3282
3283 spin_unlock_irq(&mchdev_lock);
3284 }
3285
3286 /* There's a funny hw issue where the hw returns all 0 when reading from
3287 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3288 * ourselves, instead of doing a rmw cycle (which might result in us clearing
3289 * all limits and the gpu stuck at whatever frequency it is at atm).
3290 */
3291 static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 *val)
3292 {
3293 u32 limits;
3294
3295 limits = 0;
3296
3297 if (*val >= dev_priv->rps.max_delay)
3298 *val = dev_priv->rps.max_delay;
3299 limits |= dev_priv->rps.max_delay << 24;
3300
3301 /* Only set the down limit when we've reached the lowest level to avoid
3302 * getting more interrupts, otherwise leave this clear. This prevents a
3303 * race in the hw when coming out of rc6: There's a tiny window where
3304 * the hw runs at the minimal clock before selecting the desired
3305 * frequency, if the down threshold expires in that window we will not
3306 * receive a down interrupt. */
3307 if (*val <= dev_priv->rps.min_delay) {
3308 *val = dev_priv->rps.min_delay;
3309 limits |= dev_priv->rps.min_delay << 16;
3310 }
3311
3312 return limits;
3313 }
3314
3315 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
3316 {
3317 int new_power;
3318
3319 new_power = dev_priv->rps.power;
3320 switch (dev_priv->rps.power) {
3321 case LOW_POWER:
3322 if (val > dev_priv->rps.rpe_delay + 1 && val > dev_priv->rps.cur_delay)
3323 new_power = BETWEEN;
3324 break;
3325
3326 case BETWEEN:
3327 if (val <= dev_priv->rps.rpe_delay && val < dev_priv->rps.cur_delay)
3328 new_power = LOW_POWER;
3329 else if (val >= dev_priv->rps.rp0_delay && val > dev_priv->rps.cur_delay)
3330 new_power = HIGH_POWER;
3331 break;
3332
3333 case HIGH_POWER:
3334 if (val < (dev_priv->rps.rp1_delay + dev_priv->rps.rp0_delay) >> 1 && val < dev_priv->rps.cur_delay)
3335 new_power = BETWEEN;
3336 break;
3337 }
3338 /* Max/min bins are special */
3339 if (val == dev_priv->rps.min_delay)
3340 new_power = LOW_POWER;
3341 if (val == dev_priv->rps.max_delay)
3342 new_power = HIGH_POWER;
3343 if (new_power == dev_priv->rps.power)
3344 return;
3345
3346 /* Note the units here are not exactly 1us, but 1280ns. */
3347 switch (new_power) {
3348 case LOW_POWER:
3349 /* Upclock if more than 95% busy over 16ms */
3350 I915_WRITE(GEN6_RP_UP_EI, 12500);
3351 I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800);
3352
3353 /* Downclock if less than 85% busy over 32ms */
3354 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3355 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250);
3356
3357 I915_WRITE(GEN6_RP_CONTROL,
3358 GEN6_RP_MEDIA_TURBO |
3359 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3360 GEN6_RP_MEDIA_IS_GFX |
3361 GEN6_RP_ENABLE |
3362 GEN6_RP_UP_BUSY_AVG |
3363 GEN6_RP_DOWN_IDLE_AVG);
3364 break;
3365
3366 case BETWEEN:
3367 /* Upclock if more than 90% busy over 13ms */
3368 I915_WRITE(GEN6_RP_UP_EI, 10250);
3369 I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225);
3370
3371 /* Downclock if less than 75% busy over 32ms */
3372 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3373 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750);
3374
3375 I915_WRITE(GEN6_RP_CONTROL,
3376 GEN6_RP_MEDIA_TURBO |
3377 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3378 GEN6_RP_MEDIA_IS_GFX |
3379 GEN6_RP_ENABLE |
3380 GEN6_RP_UP_BUSY_AVG |
3381 GEN6_RP_DOWN_IDLE_AVG);
3382 break;
3383
3384 case HIGH_POWER:
3385 /* Upclock if more than 85% busy over 10ms */
3386 I915_WRITE(GEN6_RP_UP_EI, 8000);
3387 I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800);
3388
3389 /* Downclock if less than 60% busy over 32ms */
3390 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3391 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000);
3392
3393 I915_WRITE(GEN6_RP_CONTROL,
3394 GEN6_RP_MEDIA_TURBO |
3395 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3396 GEN6_RP_MEDIA_IS_GFX |
3397 GEN6_RP_ENABLE |
3398 GEN6_RP_UP_BUSY_AVG |
3399 GEN6_RP_DOWN_IDLE_AVG);
3400 break;
3401 }
3402
3403 dev_priv->rps.power = new_power;
3404 dev_priv->rps.last_adj = 0;
3405 }
3406
3407 void gen6_set_rps(struct drm_device *dev, u8 val)
3408 {
3409 struct drm_i915_private *dev_priv = dev->dev_private;
3410 u32 limits = gen6_rps_limits(dev_priv, &val);
3411
3412 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3413 WARN_ON(val > dev_priv->rps.max_delay);
3414 WARN_ON(val < dev_priv->rps.min_delay);
3415
3416 if (val == dev_priv->rps.cur_delay)
3417 return;
3418
3419 gen6_set_rps_thresholds(dev_priv, val);
3420
3421 if (IS_HASWELL(dev))
3422 I915_WRITE(GEN6_RPNSWREQ,
3423 HSW_FREQUENCY(val));
3424 else
3425 I915_WRITE(GEN6_RPNSWREQ,
3426 GEN6_FREQUENCY(val) |
3427 GEN6_OFFSET(0) |
3428 GEN6_AGGRESSIVE_TURBO);
3429
3430 /* Make sure we continue to get interrupts
3431 * until we hit the minimum or maximum frequencies.
3432 */
3433 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
3434
3435 POSTING_READ(GEN6_RPNSWREQ);
3436
3437 dev_priv->rps.cur_delay = val;
3438
3439 trace_intel_gpu_freq_change(val * 50);
3440 }
3441
3442 void gen6_rps_idle(struct drm_i915_private *dev_priv)
3443 {
3444 mutex_lock(&dev_priv->rps.hw_lock);
3445 if (dev_priv->info->is_valleyview)
3446 valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
3447 else
3448 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
3449 dev_priv->rps.last_adj = 0;
3450 mutex_unlock(&dev_priv->rps.hw_lock);
3451 }
3452
3453 void gen6_rps_boost(struct drm_i915_private *dev_priv)
3454 {
3455 mutex_lock(&dev_priv->rps.hw_lock);
3456 if (dev_priv->info->is_valleyview)
3457 valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_delay);
3458 else
3459 gen6_set_rps(dev_priv->dev, dev_priv->rps.max_delay);
3460 dev_priv->rps.last_adj = 0;
3461 mutex_unlock(&dev_priv->rps.hw_lock);
3462 }
3463
3464 /*
3465 * Wait until the previous freq change has completed,
3466 * or the timeout elapsed, and then update our notion
3467 * of the current GPU frequency.
3468 */
3469 static void vlv_update_rps_cur_delay(struct drm_i915_private *dev_priv)
3470 {
3471 u32 pval;
3472
3473 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3474
3475 if (wait_for(((pval = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS)) & GENFREQSTATUS) == 0, 10))
3476 DRM_DEBUG_DRIVER("timed out waiting for Punit\n");
3477
3478 pval >>= 8;
3479
3480 if (pval != dev_priv->rps.cur_delay)
3481 DRM_DEBUG_DRIVER("Punit overrode GPU freq: %d MHz (%u) requested, but got %d Mhz (%u)\n",
3482 vlv_gpu_freq(dev_priv->mem_freq, dev_priv->rps.cur_delay),
3483 dev_priv->rps.cur_delay,
3484 vlv_gpu_freq(dev_priv->mem_freq, pval), pval);
3485
3486 dev_priv->rps.cur_delay = pval;
3487 }
3488
3489 void valleyview_set_rps(struct drm_device *dev, u8 val)
3490 {
3491 struct drm_i915_private *dev_priv = dev->dev_private;
3492
3493 gen6_rps_limits(dev_priv, &val);
3494
3495 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3496 WARN_ON(val > dev_priv->rps.max_delay);
3497 WARN_ON(val < dev_priv->rps.min_delay);
3498
3499 vlv_update_rps_cur_delay(dev_priv);
3500
3501 DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
3502 vlv_gpu_freq(dev_priv->mem_freq,
3503 dev_priv->rps.cur_delay),
3504 dev_priv->rps.cur_delay,
3505 vlv_gpu_freq(dev_priv->mem_freq, val), val);
3506
3507 if (val == dev_priv->rps.cur_delay)
3508 return;
3509
3510 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
3511
3512 dev_priv->rps.cur_delay = val;
3513
3514 trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv->mem_freq, val));
3515 }
3516
3517 static void gen6_disable_rps_interrupts(struct drm_device *dev)
3518 {
3519 struct drm_i915_private *dev_priv = dev->dev_private;
3520
3521 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3522 I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) & ~GEN6_PM_RPS_EVENTS);
3523 /* Complete PM interrupt masking here doesn't race with the rps work
3524 * item again unmasking PM interrupts because that is using a different
3525 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3526 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3527
3528 spin_lock_irq(&dev_priv->irq_lock);
3529 dev_priv->rps.pm_iir = 0;
3530 spin_unlock_irq(&dev_priv->irq_lock);
3531
3532 I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
3533 }
3534
3535 static void gen6_disable_rps(struct drm_device *dev)
3536 {
3537 struct drm_i915_private *dev_priv = dev->dev_private;
3538
3539 I915_WRITE(GEN6_RC_CONTROL, 0);
3540 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
3541
3542 gen6_disable_rps_interrupts(dev);
3543 }
3544
3545 static void valleyview_disable_rps(struct drm_device *dev)
3546 {
3547 struct drm_i915_private *dev_priv = dev->dev_private;
3548
3549 I915_WRITE(GEN6_RC_CONTROL, 0);
3550
3551 gen6_disable_rps_interrupts(dev);
3552
3553 if (dev_priv->vlv_pctx) {
3554 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
3555 dev_priv->vlv_pctx = NULL;
3556 }
3557 }
3558
3559 int intel_enable_rc6(const struct drm_device *dev)
3560 {
3561 /* No RC6 before Ironlake */
3562 if (INTEL_INFO(dev)->gen < 5)
3563 return 0;
3564
3565 /* Respect the kernel parameter if it is set */
3566 if (i915_enable_rc6 >= 0)
3567 return i915_enable_rc6;
3568
3569 /* Disable RC6 on Ironlake */
3570 if (INTEL_INFO(dev)->gen == 5)
3571 return 0;
3572
3573 if (IS_HASWELL(dev)) {
3574 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
3575 return INTEL_RC6_ENABLE;
3576 }
3577
3578 /* snb/ivb have more than one rc6 state. */
3579 if (INTEL_INFO(dev)->gen == 6) {
3580 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
3581 return INTEL_RC6_ENABLE;
3582 }
3583
3584 DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n");
3585 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
3586 }
3587
3588 static void gen6_enable_rps_interrupts(struct drm_device *dev)
3589 {
3590 struct drm_i915_private *dev_priv = dev->dev_private;
3591 u32 enabled_intrs;
3592
3593 spin_lock_irq(&dev_priv->irq_lock);
3594 WARN_ON(dev_priv->rps.pm_iir);
3595 snb_enable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS);
3596 I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
3597 spin_unlock_irq(&dev_priv->irq_lock);
3598
3599 /* only unmask PM interrupts we need. Mask all others. */
3600 enabled_intrs = GEN6_PM_RPS_EVENTS;
3601
3602 /* IVB and SNB hard hangs on looping batchbuffer
3603 * if GEN6_PM_UP_EI_EXPIRED is masked.
3604 */
3605 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
3606 enabled_intrs |= GEN6_PM_RP_UP_EI_EXPIRED;
3607
3608 I915_WRITE(GEN6_PMINTRMSK, ~enabled_intrs);
3609 }
3610
3611 static void gen6_enable_rps(struct drm_device *dev)
3612 {
3613 struct drm_i915_private *dev_priv = dev->dev_private;
3614 struct intel_ring_buffer *ring;
3615 u32 rp_state_cap;
3616 u32 gt_perf_status;
3617 u32 rc6vids, pcu_mbox, rc6_mask = 0;
3618 u32 gtfifodbg;
3619 int rc6_mode;
3620 int i, ret;
3621
3622 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3623
3624 /* Here begins a magic sequence of register writes to enable
3625 * auto-downclocking.
3626 *
3627 * Perhaps there might be some value in exposing these to
3628 * userspace...
3629 */
3630 I915_WRITE(GEN6_RC_STATE, 0);
3631
3632 /* Clear the DBG now so we don't confuse earlier errors */
3633 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3634 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3635 I915_WRITE(GTFIFODBG, gtfifodbg);
3636 }
3637
3638 gen6_gt_force_wake_get(dev_priv);
3639
3640 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3641 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
3642
3643 /* In units of 50MHz */
3644 dev_priv->rps.hw_max = dev_priv->rps.max_delay = rp_state_cap & 0xff;
3645 dev_priv->rps.min_delay = (rp_state_cap >> 16) & 0xff;
3646 dev_priv->rps.rp1_delay = (rp_state_cap >> 8) & 0xff;
3647 dev_priv->rps.rp0_delay = (rp_state_cap >> 0) & 0xff;
3648 dev_priv->rps.rpe_delay = dev_priv->rps.rp1_delay;
3649 dev_priv->rps.cur_delay = 0;
3650
3651 /* disable the counters and set deterministic thresholds */
3652 I915_WRITE(GEN6_RC_CONTROL, 0);
3653
3654 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
3655 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
3656 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
3657 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3658 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3659
3660 for_each_ring(ring, dev_priv, i)
3661 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3662
3663 I915_WRITE(GEN6_RC_SLEEP, 0);
3664 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
3665 if (INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev))
3666 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
3667 else
3668 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
3669 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
3670 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
3671
3672 /* Check if we are enabling RC6 */
3673 rc6_mode = intel_enable_rc6(dev_priv->dev);
3674 if (rc6_mode & INTEL_RC6_ENABLE)
3675 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
3676
3677 /* We don't use those on Haswell */
3678 if (!IS_HASWELL(dev)) {
3679 if (rc6_mode & INTEL_RC6p_ENABLE)
3680 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
3681
3682 if (rc6_mode & INTEL_RC6pp_ENABLE)
3683 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
3684 }
3685
3686 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
3687 (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3688 (rc6_mask & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3689 (rc6_mask & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
3690
3691 I915_WRITE(GEN6_RC_CONTROL,
3692 rc6_mask |
3693 GEN6_RC_CTL_EI_MODE(1) |
3694 GEN6_RC_CTL_HW_ENABLE);
3695
3696 /* Power down if completely idle for over 50ms */
3697 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
3698 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3699
3700 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
3701 if (!ret) {
3702 pcu_mbox = 0;
3703 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
3704 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
3705 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
3706 (dev_priv->rps.max_delay & 0xff) * 50,
3707 (pcu_mbox & 0xff) * 50);
3708 dev_priv->rps.hw_max = pcu_mbox & 0xff;
3709 }
3710 } else {
3711 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
3712 }
3713
3714 dev_priv->rps.power = HIGH_POWER; /* force a reset */
3715 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
3716
3717 gen6_enable_rps_interrupts(dev);
3718
3719 rc6vids = 0;
3720 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
3721 if (IS_GEN6(dev) && ret) {
3722 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
3723 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
3724 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
3725 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
3726 rc6vids &= 0xffff00;
3727 rc6vids |= GEN6_ENCODE_RC6_VID(450);
3728 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
3729 if (ret)
3730 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
3731 }
3732
3733 gen6_gt_force_wake_put(dev_priv);
3734 }
3735
3736 void gen6_update_ring_freq(struct drm_device *dev)
3737 {
3738 struct drm_i915_private *dev_priv = dev->dev_private;
3739 int min_freq = 15;
3740 unsigned int gpu_freq;
3741 unsigned int max_ia_freq, min_ring_freq;
3742 int scaling_factor = 180;
3743
3744 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3745
3746 max_ia_freq = cpufreq_quick_get_max(0);
3747 /*
3748 * Default to measured freq if none found, PCU will ensure we don't go
3749 * over
3750 */
3751 if (!max_ia_freq)
3752 max_ia_freq = tsc_khz;
3753
3754 /* Convert from kHz to MHz */
3755 max_ia_freq /= 1000;
3756
3757 min_ring_freq = I915_READ(MCHBAR_MIRROR_BASE_SNB + DCLK) & 0xf;
3758 /* convert DDR frequency from units of 266.6MHz to bandwidth */
3759 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3760
3761 /*
3762 * For each potential GPU frequency, load a ring frequency we'd like
3763 * to use for memory access. We do this by specifying the IA frequency
3764 * the PCU should use as a reference to determine the ring frequency.
3765 */
3766 for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay;
3767 gpu_freq--) {
3768 int diff = dev_priv->rps.max_delay - gpu_freq;
3769 unsigned int ia_freq = 0, ring_freq = 0;
3770
3771 if (IS_HASWELL(dev)) {
3772 ring_freq = mult_frac(gpu_freq, 5, 4);
3773 ring_freq = max(min_ring_freq, ring_freq);
3774 /* leave ia_freq as the default, chosen by cpufreq */
3775 } else {
3776 /* On older processors, there is no separate ring
3777 * clock domain, so in order to boost the bandwidth
3778 * of the ring, we need to upclock the CPU (ia_freq).
3779 *
3780 * For GPU frequencies less than 750MHz,
3781 * just use the lowest ring freq.
3782 */
3783 if (gpu_freq < min_freq)
3784 ia_freq = 800;
3785 else
3786 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
3787 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
3788 }
3789
3790 sandybridge_pcode_write(dev_priv,
3791 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3792 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
3793 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
3794 gpu_freq);
3795 }
3796 }
3797
3798 int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
3799 {
3800 u32 val, rp0;
3801
3802 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
3803
3804 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
3805 /* Clamp to max */
3806 rp0 = min_t(u32, rp0, 0xea);
3807
3808 return rp0;
3809 }
3810
3811 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
3812 {
3813 u32 val, rpe;
3814
3815 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
3816 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
3817 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
3818 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
3819
3820 return rpe;
3821 }
3822
3823 int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
3824 {
3825 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
3826 }
3827
3828 static void valleyview_setup_pctx(struct drm_device *dev)
3829 {
3830 struct drm_i915_private *dev_priv = dev->dev_private;
3831 struct drm_i915_gem_object *pctx;
3832 unsigned long pctx_paddr;
3833 u32 pcbr;
3834 int pctx_size = 24*1024;
3835
3836 pcbr = I915_READ(VLV_PCBR);
3837 if (pcbr) {
3838 /* BIOS set it up already, grab the pre-alloc'd space */
3839 int pcbr_offset;
3840
3841 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
3842 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
3843 pcbr_offset,
3844 I915_GTT_OFFSET_NONE,
3845 pctx_size);
3846 goto out;
3847 }
3848
3849 /*
3850 * From the Gunit register HAS:
3851 * The Gfx driver is expected to program this register and ensure
3852 * proper allocation within Gfx stolen memory. For example, this
3853 * register should be programmed such than the PCBR range does not
3854 * overlap with other ranges, such as the frame buffer, protected
3855 * memory, or any other relevant ranges.
3856 */
3857 pctx = i915_gem_object_create_stolen(dev, pctx_size);
3858 if (!pctx) {
3859 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
3860 return;
3861 }
3862
3863 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
3864 I915_WRITE(VLV_PCBR, pctx_paddr);
3865
3866 out:
3867 dev_priv->vlv_pctx = pctx;
3868 }
3869
3870 static void valleyview_enable_rps(struct drm_device *dev)
3871 {
3872 struct drm_i915_private *dev_priv = dev->dev_private;
3873 struct intel_ring_buffer *ring;
3874 u32 gtfifodbg, val, rc6_mode = 0;
3875 int i;
3876
3877 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3878
3879 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3880 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
3881 gtfifodbg);
3882 I915_WRITE(GTFIFODBG, gtfifodbg);
3883 }
3884
3885 valleyview_setup_pctx(dev);
3886
3887 gen6_gt_force_wake_get(dev_priv);
3888
3889 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
3890 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
3891 I915_WRITE(GEN6_RP_UP_EI, 66000);
3892 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
3893
3894 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3895
3896 I915_WRITE(GEN6_RP_CONTROL,
3897 GEN6_RP_MEDIA_TURBO |
3898 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3899 GEN6_RP_MEDIA_IS_GFX |
3900 GEN6_RP_ENABLE |
3901 GEN6_RP_UP_BUSY_AVG |
3902 GEN6_RP_DOWN_IDLE_CONT);
3903
3904 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
3905 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3906 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3907
3908 for_each_ring(ring, dev_priv, i)
3909 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3910
3911 I915_WRITE(GEN6_RC6_THRESHOLD, 0xc350);
3912
3913 /* allows RC6 residency counter to work */
3914 I915_WRITE(VLV_COUNTER_CONTROL,
3915 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
3916 VLV_MEDIA_RC6_COUNT_EN |
3917 VLV_RENDER_RC6_COUNT_EN));
3918 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
3919 rc6_mode = GEN7_RC_CTL_TO_MODE;
3920 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
3921
3922 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
3923 switch ((val >> 6) & 3) {
3924 case 0:
3925 case 1:
3926 dev_priv->mem_freq = 800;
3927 break;
3928 case 2:
3929 dev_priv->mem_freq = 1066;
3930 break;
3931 case 3:
3932 dev_priv->mem_freq = 1333;
3933 break;
3934 }
3935 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
3936
3937 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
3938 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
3939
3940 dev_priv->rps.cur_delay = (val >> 8) & 0xff;
3941 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
3942 vlv_gpu_freq(dev_priv->mem_freq,
3943 dev_priv->rps.cur_delay),
3944 dev_priv->rps.cur_delay);
3945
3946 dev_priv->rps.max_delay = valleyview_rps_max_freq(dev_priv);
3947 dev_priv->rps.hw_max = dev_priv->rps.max_delay;
3948 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
3949 vlv_gpu_freq(dev_priv->mem_freq,
3950 dev_priv->rps.max_delay),
3951 dev_priv->rps.max_delay);
3952
3953 dev_priv->rps.rpe_delay = valleyview_rps_rpe_freq(dev_priv);
3954 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
3955 vlv_gpu_freq(dev_priv->mem_freq,
3956 dev_priv->rps.rpe_delay),
3957 dev_priv->rps.rpe_delay);
3958
3959 dev_priv->rps.min_delay = valleyview_rps_min_freq(dev_priv);
3960 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
3961 vlv_gpu_freq(dev_priv->mem_freq,
3962 dev_priv->rps.min_delay),
3963 dev_priv->rps.min_delay);
3964
3965 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
3966 vlv_gpu_freq(dev_priv->mem_freq,
3967 dev_priv->rps.rpe_delay),
3968 dev_priv->rps.rpe_delay);
3969
3970 valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
3971
3972 gen6_enable_rps_interrupts(dev);
3973
3974 gen6_gt_force_wake_put(dev_priv);
3975 }
3976
3977 void ironlake_teardown_rc6(struct drm_device *dev)
3978 {
3979 struct drm_i915_private *dev_priv = dev->dev_private;
3980
3981 if (dev_priv->ips.renderctx) {
3982 i915_gem_object_unpin(dev_priv->ips.renderctx);
3983 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
3984 dev_priv->ips.renderctx = NULL;
3985 }
3986
3987 if (dev_priv->ips.pwrctx) {
3988 i915_gem_object_unpin(dev_priv->ips.pwrctx);
3989 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
3990 dev_priv->ips.pwrctx = NULL;
3991 }
3992 }
3993
3994 static void ironlake_disable_rc6(struct drm_device *dev)
3995 {
3996 struct drm_i915_private *dev_priv = dev->dev_private;
3997
3998 if (I915_READ(PWRCTXA)) {
3999 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
4000 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
4001 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
4002 50);
4003
4004 I915_WRITE(PWRCTXA, 0);
4005 POSTING_READ(PWRCTXA);
4006
4007 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
4008 POSTING_READ(RSTDBYCTL);
4009 }
4010 }
4011
4012 static int ironlake_setup_rc6(struct drm_device *dev)
4013 {
4014 struct drm_i915_private *dev_priv = dev->dev_private;
4015
4016 if (dev_priv->ips.renderctx == NULL)
4017 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
4018 if (!dev_priv->ips.renderctx)
4019 return -ENOMEM;
4020
4021 if (dev_priv->ips.pwrctx == NULL)
4022 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
4023 if (!dev_priv->ips.pwrctx) {
4024 ironlake_teardown_rc6(dev);
4025 return -ENOMEM;
4026 }
4027
4028 return 0;
4029 }
4030
4031 static void ironlake_enable_rc6(struct drm_device *dev)
4032 {
4033 struct drm_i915_private *dev_priv = dev->dev_private;
4034 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
4035 bool was_interruptible;
4036 int ret;
4037
4038 /* rc6 disabled by default due to repeated reports of hanging during
4039 * boot and resume.
4040 */
4041 if (!intel_enable_rc6(dev))
4042 return;
4043
4044 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4045
4046 ret = ironlake_setup_rc6(dev);
4047 if (ret)
4048 return;
4049
4050 was_interruptible = dev_priv->mm.interruptible;
4051 dev_priv->mm.interruptible = false;
4052
4053 /*
4054 * GPU can automatically power down the render unit if given a page
4055 * to save state.
4056 */
4057 ret = intel_ring_begin(ring, 6);
4058 if (ret) {
4059 ironlake_teardown_rc6(dev);
4060 dev_priv->mm.interruptible = was_interruptible;
4061 return;
4062 }
4063
4064 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
4065 intel_ring_emit(ring, MI_SET_CONTEXT);
4066 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) |
4067 MI_MM_SPACE_GTT |
4068 MI_SAVE_EXT_STATE_EN |
4069 MI_RESTORE_EXT_STATE_EN |
4070 MI_RESTORE_INHIBIT);
4071 intel_ring_emit(ring, MI_SUSPEND_FLUSH);
4072 intel_ring_emit(ring, MI_NOOP);
4073 intel_ring_emit(ring, MI_FLUSH);
4074 intel_ring_advance(ring);
4075
4076 /*
4077 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
4078 * does an implicit flush, combined with MI_FLUSH above, it should be
4079 * safe to assume that renderctx is valid
4080 */
4081 ret = intel_ring_idle(ring);
4082 dev_priv->mm.interruptible = was_interruptible;
4083 if (ret) {
4084 DRM_ERROR("failed to enable ironlake power savings\n");
4085 ironlake_teardown_rc6(dev);
4086 return;
4087 }
4088
4089 I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN);
4090 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
4091 }
4092
4093 static unsigned long intel_pxfreq(u32 vidfreq)
4094 {
4095 unsigned long freq;
4096 int div = (vidfreq & 0x3f0000) >> 16;
4097 int post = (vidfreq & 0x3000) >> 12;
4098 int pre = (vidfreq & 0x7);
4099
4100 if (!pre)
4101 return 0;
4102
4103 freq = ((div * 133333) / ((1<<post) * pre));
4104
4105 return freq;
4106 }
4107
4108 static const struct cparams {
4109 u16 i;
4110 u16 t;
4111 u16 m;
4112 u16 c;
4113 } cparams[] = {
4114 { 1, 1333, 301, 28664 },
4115 { 1, 1066, 294, 24460 },
4116 { 1, 800, 294, 25192 },
4117 { 0, 1333, 276, 27605 },
4118 { 0, 1066, 276, 27605 },
4119 { 0, 800, 231, 23784 },
4120 };
4121
4122 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
4123 {
4124 u64 total_count, diff, ret;
4125 u32 count1, count2, count3, m = 0, c = 0;
4126 unsigned long now = jiffies_to_msecs(jiffies), diff1;
4127 int i;
4128
4129 assert_spin_locked(&mchdev_lock);
4130
4131 diff1 = now - dev_priv->ips.last_time1;
4132
4133 /* Prevent division-by-zero if we are asking too fast.
4134 * Also, we don't get interesting results if we are polling
4135 * faster than once in 10ms, so just return the saved value
4136 * in such cases.
4137 */
4138 if (diff1 <= 10)
4139 return dev_priv->ips.chipset_power;
4140
4141 count1 = I915_READ(DMIEC);
4142 count2 = I915_READ(DDREC);
4143 count3 = I915_READ(CSIEC);
4144
4145 total_count = count1 + count2 + count3;
4146
4147 /* FIXME: handle per-counter overflow */
4148 if (total_count < dev_priv->ips.last_count1) {
4149 diff = ~0UL - dev_priv->ips.last_count1;
4150 diff += total_count;
4151 } else {
4152 diff = total_count - dev_priv->ips.last_count1;
4153 }
4154
4155 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
4156 if (cparams[i].i == dev_priv->ips.c_m &&
4157 cparams[i].t == dev_priv->ips.r_t) {
4158 m = cparams[i].m;
4159 c = cparams[i].c;
4160 break;
4161 }
4162 }
4163
4164 diff = div_u64(diff, diff1);
4165 ret = ((m * diff) + c);
4166 ret = div_u64(ret, 10);
4167
4168 dev_priv->ips.last_count1 = total_count;
4169 dev_priv->ips.last_time1 = now;
4170
4171 dev_priv->ips.chipset_power = ret;
4172
4173 return ret;
4174 }
4175
4176 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
4177 {
4178 unsigned long val;
4179
4180 if (dev_priv->info->gen != 5)
4181 return 0;
4182
4183 spin_lock_irq(&mchdev_lock);
4184
4185 val = __i915_chipset_val(dev_priv);
4186
4187 spin_unlock_irq(&mchdev_lock);
4188
4189 return val;
4190 }
4191
4192 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
4193 {
4194 unsigned long m, x, b;
4195 u32 tsfs;
4196
4197 tsfs = I915_READ(TSFS);
4198
4199 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
4200 x = I915_READ8(TR1);
4201
4202 b = tsfs & TSFS_INTR_MASK;
4203
4204 return ((m * x) / 127) - b;
4205 }
4206
4207 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
4208 {
4209 static const struct v_table {
4210 u16 vd; /* in .1 mil */
4211 u16 vm; /* in .1 mil */
4212 } v_table[] = {
4213 { 0, 0, },
4214 { 375, 0, },
4215 { 500, 0, },
4216 { 625, 0, },
4217 { 750, 0, },
4218 { 875, 0, },
4219 { 1000, 0, },
4220 { 1125, 0, },
4221 { 4125, 3000, },
4222 { 4125, 3000, },
4223 { 4125, 3000, },
4224 { 4125, 3000, },
4225 { 4125, 3000, },
4226 { 4125, 3000, },
4227 { 4125, 3000, },
4228 { 4125, 3000, },
4229 { 4125, 3000, },
4230 { 4125, 3000, },
4231 { 4125, 3000, },
4232 { 4125, 3000, },
4233 { 4125, 3000, },
4234 { 4125, 3000, },
4235 { 4125, 3000, },
4236 { 4125, 3000, },
4237 { 4125, 3000, },
4238 { 4125, 3000, },
4239 { 4125, 3000, },
4240 { 4125, 3000, },
4241 { 4125, 3000, },
4242 { 4125, 3000, },
4243 { 4125, 3000, },
4244 { 4125, 3000, },
4245 { 4250, 3125, },
4246 { 4375, 3250, },
4247 { 4500, 3375, },
4248 { 4625, 3500, },
4249 { 4750, 3625, },
4250 { 4875, 3750, },
4251 { 5000, 3875, },
4252 { 5125, 4000, },
4253 { 5250, 4125, },
4254 { 5375, 4250, },
4255 { 5500, 4375, },
4256 { 5625, 4500, },
4257 { 5750, 4625, },
4258 { 5875, 4750, },
4259 { 6000, 4875, },
4260 { 6125, 5000, },
4261 { 6250, 5125, },
4262 { 6375, 5250, },
4263 { 6500, 5375, },
4264 { 6625, 5500, },
4265 { 6750, 5625, },
4266 { 6875, 5750, },
4267 { 7000, 5875, },
4268 { 7125, 6000, },
4269 { 7250, 6125, },
4270 { 7375, 6250, },
4271 { 7500, 6375, },
4272 { 7625, 6500, },
4273 { 7750, 6625, },
4274 { 7875, 6750, },
4275 { 8000, 6875, },
4276 { 8125, 7000, },
4277 { 8250, 7125, },
4278 { 8375, 7250, },
4279 { 8500, 7375, },
4280 { 8625, 7500, },
4281 { 8750, 7625, },
4282 { 8875, 7750, },
4283 { 9000, 7875, },
4284 { 9125, 8000, },
4285 { 9250, 8125, },
4286 { 9375, 8250, },
4287 { 9500, 8375, },
4288 { 9625, 8500, },
4289 { 9750, 8625, },
4290 { 9875, 8750, },
4291 { 10000, 8875, },
4292 { 10125, 9000, },
4293 { 10250, 9125, },
4294 { 10375, 9250, },
4295 { 10500, 9375, },
4296 { 10625, 9500, },
4297 { 10750, 9625, },
4298 { 10875, 9750, },
4299 { 11000, 9875, },
4300 { 11125, 10000, },
4301 { 11250, 10125, },
4302 { 11375, 10250, },
4303 { 11500, 10375, },
4304 { 11625, 10500, },
4305 { 11750, 10625, },
4306 { 11875, 10750, },
4307 { 12000, 10875, },
4308 { 12125, 11000, },
4309 { 12250, 11125, },
4310 { 12375, 11250, },
4311 { 12500, 11375, },
4312 { 12625, 11500, },
4313 { 12750, 11625, },
4314 { 12875, 11750, },
4315 { 13000, 11875, },
4316 { 13125, 12000, },
4317 { 13250, 12125, },
4318 { 13375, 12250, },
4319 { 13500, 12375, },
4320 { 13625, 12500, },
4321 { 13750, 12625, },
4322 { 13875, 12750, },
4323 { 14000, 12875, },
4324 { 14125, 13000, },
4325 { 14250, 13125, },
4326 { 14375, 13250, },
4327 { 14500, 13375, },
4328 { 14625, 13500, },
4329 { 14750, 13625, },
4330 { 14875, 13750, },
4331 { 15000, 13875, },
4332 { 15125, 14000, },
4333 { 15250, 14125, },
4334 { 15375, 14250, },
4335 { 15500, 14375, },
4336 { 15625, 14500, },
4337 { 15750, 14625, },
4338 { 15875, 14750, },
4339 { 16000, 14875, },
4340 { 16125, 15000, },
4341 };
4342 if (dev_priv->info->is_mobile)
4343 return v_table[pxvid].vm;
4344 else
4345 return v_table[pxvid].vd;
4346 }
4347
4348 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
4349 {
4350 struct timespec now, diff1;
4351 u64 diff;
4352 unsigned long diffms;
4353 u32 count;
4354
4355 assert_spin_locked(&mchdev_lock);
4356
4357 getrawmonotonic(&now);
4358 diff1 = timespec_sub(now, dev_priv->ips.last_time2);
4359
4360 /* Don't divide by 0 */
4361 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
4362 if (!diffms)
4363 return;
4364
4365 count = I915_READ(GFXEC);
4366
4367 if (count < dev_priv->ips.last_count2) {
4368 diff = ~0UL - dev_priv->ips.last_count2;
4369 diff += count;
4370 } else {
4371 diff = count - dev_priv->ips.last_count2;
4372 }
4373
4374 dev_priv->ips.last_count2 = count;
4375 dev_priv->ips.last_time2 = now;
4376
4377 /* More magic constants... */
4378 diff = diff * 1181;
4379 diff = div_u64(diff, diffms * 10);
4380 dev_priv->ips.gfx_power = diff;
4381 }
4382
4383 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
4384 {
4385 if (dev_priv->info->gen != 5)
4386 return;
4387
4388 spin_lock_irq(&mchdev_lock);
4389
4390 __i915_update_gfx_val(dev_priv);
4391
4392 spin_unlock_irq(&mchdev_lock);
4393 }
4394
4395 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
4396 {
4397 unsigned long t, corr, state1, corr2, state2;
4398 u32 pxvid, ext_v;
4399
4400 assert_spin_locked(&mchdev_lock);
4401
4402 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4));
4403 pxvid = (pxvid >> 24) & 0x7f;
4404 ext_v = pvid_to_extvid(dev_priv, pxvid);
4405
4406 state1 = ext_v;
4407
4408 t = i915_mch_val(dev_priv);
4409
4410 /* Revel in the empirically derived constants */
4411
4412 /* Correction factor in 1/100000 units */
4413 if (t > 80)
4414 corr = ((t * 2349) + 135940);
4415 else if (t >= 50)
4416 corr = ((t * 964) + 29317);
4417 else /* < 50 */
4418 corr = ((t * 301) + 1004);
4419
4420 corr = corr * ((150142 * state1) / 10000 - 78642);
4421 corr /= 100000;
4422 corr2 = (corr * dev_priv->ips.corr);
4423
4424 state2 = (corr2 * state1) / 10000;
4425 state2 /= 100; /* convert to mW */
4426
4427 __i915_update_gfx_val(dev_priv);
4428
4429 return dev_priv->ips.gfx_power + state2;
4430 }
4431
4432 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
4433 {
4434 unsigned long val;
4435
4436 if (dev_priv->info->gen != 5)
4437 return 0;
4438
4439 spin_lock_irq(&mchdev_lock);
4440
4441 val = __i915_gfx_val(dev_priv);
4442
4443 spin_unlock_irq(&mchdev_lock);
4444
4445 return val;
4446 }
4447
4448 /**
4449 * i915_read_mch_val - return value for IPS use
4450 *
4451 * Calculate and return a value for the IPS driver to use when deciding whether
4452 * we have thermal and power headroom to increase CPU or GPU power budget.
4453 */
4454 unsigned long i915_read_mch_val(void)
4455 {
4456 struct drm_i915_private *dev_priv;
4457 unsigned long chipset_val, graphics_val, ret = 0;
4458
4459 spin_lock_irq(&mchdev_lock);
4460 if (!i915_mch_dev)
4461 goto out_unlock;
4462 dev_priv = i915_mch_dev;
4463
4464 chipset_val = __i915_chipset_val(dev_priv);
4465 graphics_val = __i915_gfx_val(dev_priv);
4466
4467 ret = chipset_val + graphics_val;
4468
4469 out_unlock:
4470 spin_unlock_irq(&mchdev_lock);
4471
4472 return ret;
4473 }
4474 EXPORT_SYMBOL_GPL(i915_read_mch_val);
4475
4476 /**
4477 * i915_gpu_raise - raise GPU frequency limit
4478 *
4479 * Raise the limit; IPS indicates we have thermal headroom.
4480 */
4481 bool i915_gpu_raise(void)
4482 {
4483 struct drm_i915_private *dev_priv;
4484 bool ret = true;
4485
4486 spin_lock_irq(&mchdev_lock);
4487 if (!i915_mch_dev) {
4488 ret = false;
4489 goto out_unlock;
4490 }
4491 dev_priv = i915_mch_dev;
4492
4493 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
4494 dev_priv->ips.max_delay--;
4495
4496 out_unlock:
4497 spin_unlock_irq(&mchdev_lock);
4498
4499 return ret;
4500 }
4501 EXPORT_SYMBOL_GPL(i915_gpu_raise);
4502
4503 /**
4504 * i915_gpu_lower - lower GPU frequency limit
4505 *
4506 * IPS indicates we're close to a thermal limit, so throttle back the GPU
4507 * frequency maximum.
4508 */
4509 bool i915_gpu_lower(void)
4510 {
4511 struct drm_i915_private *dev_priv;
4512 bool ret = true;
4513
4514 spin_lock_irq(&mchdev_lock);
4515 if (!i915_mch_dev) {
4516 ret = false;
4517 goto out_unlock;
4518 }
4519 dev_priv = i915_mch_dev;
4520
4521 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
4522 dev_priv->ips.max_delay++;
4523
4524 out_unlock:
4525 spin_unlock_irq(&mchdev_lock);
4526
4527 return ret;
4528 }
4529 EXPORT_SYMBOL_GPL(i915_gpu_lower);
4530
4531 /**
4532 * i915_gpu_busy - indicate GPU business to IPS
4533 *
4534 * Tell the IPS driver whether or not the GPU is busy.
4535 */
4536 bool i915_gpu_busy(void)
4537 {
4538 struct drm_i915_private *dev_priv;
4539 struct intel_ring_buffer *ring;
4540 bool ret = false;
4541 int i;
4542
4543 spin_lock_irq(&mchdev_lock);
4544 if (!i915_mch_dev)
4545 goto out_unlock;
4546 dev_priv = i915_mch_dev;
4547
4548 for_each_ring(ring, dev_priv, i)
4549 ret |= !list_empty(&ring->request_list);
4550
4551 out_unlock:
4552 spin_unlock_irq(&mchdev_lock);
4553
4554 return ret;
4555 }
4556 EXPORT_SYMBOL_GPL(i915_gpu_busy);
4557
4558 /**
4559 * i915_gpu_turbo_disable - disable graphics turbo
4560 *
4561 * Disable graphics turbo by resetting the max frequency and setting the
4562 * current frequency to the default.
4563 */
4564 bool i915_gpu_turbo_disable(void)
4565 {
4566 struct drm_i915_private *dev_priv;
4567 bool ret = true;
4568
4569 spin_lock_irq(&mchdev_lock);
4570 if (!i915_mch_dev) {
4571 ret = false;
4572 goto out_unlock;
4573 }
4574 dev_priv = i915_mch_dev;
4575
4576 dev_priv->ips.max_delay = dev_priv->ips.fstart;
4577
4578 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
4579 ret = false;
4580
4581 out_unlock:
4582 spin_unlock_irq(&mchdev_lock);
4583
4584 return ret;
4585 }
4586 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
4587
4588 /**
4589 * Tells the intel_ips driver that the i915 driver is now loaded, if
4590 * IPS got loaded first.
4591 *
4592 * This awkward dance is so that neither module has to depend on the
4593 * other in order for IPS to do the appropriate communication of
4594 * GPU turbo limits to i915.
4595 */
4596 static void
4597 ips_ping_for_i915_load(void)
4598 {
4599 void (*link)(void);
4600
4601 link = symbol_get(ips_link_to_i915_driver);
4602 if (link) {
4603 link();
4604 symbol_put(ips_link_to_i915_driver);
4605 }
4606 }
4607
4608 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
4609 {
4610 /* We only register the i915 ips part with intel-ips once everything is
4611 * set up, to avoid intel-ips sneaking in and reading bogus values. */
4612 spin_lock_irq(&mchdev_lock);
4613 i915_mch_dev = dev_priv;
4614 spin_unlock_irq(&mchdev_lock);
4615
4616 ips_ping_for_i915_load();
4617 }
4618
4619 void intel_gpu_ips_teardown(void)
4620 {
4621 spin_lock_irq(&mchdev_lock);
4622 i915_mch_dev = NULL;
4623 spin_unlock_irq(&mchdev_lock);
4624 }
4625 static void intel_init_emon(struct drm_device *dev)
4626 {
4627 struct drm_i915_private *dev_priv = dev->dev_private;
4628 u32 lcfuse;
4629 u8 pxw[16];
4630 int i;
4631
4632 /* Disable to program */
4633 I915_WRITE(ECR, 0);
4634 POSTING_READ(ECR);
4635
4636 /* Program energy weights for various events */
4637 I915_WRITE(SDEW, 0x15040d00);
4638 I915_WRITE(CSIEW0, 0x007f0000);
4639 I915_WRITE(CSIEW1, 0x1e220004);
4640 I915_WRITE(CSIEW2, 0x04000004);
4641
4642 for (i = 0; i < 5; i++)
4643 I915_WRITE(PEW + (i * 4), 0);
4644 for (i = 0; i < 3; i++)
4645 I915_WRITE(DEW + (i * 4), 0);
4646
4647 /* Program P-state weights to account for frequency power adjustment */
4648 for (i = 0; i < 16; i++) {
4649 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
4650 unsigned long freq = intel_pxfreq(pxvidfreq);
4651 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
4652 PXVFREQ_PX_SHIFT;
4653 unsigned long val;
4654
4655 val = vid * vid;
4656 val *= (freq / 1000);
4657 val *= 255;
4658 val /= (127*127*900);
4659 if (val > 0xff)
4660 DRM_ERROR("bad pxval: %ld\n", val);
4661 pxw[i] = val;
4662 }
4663 /* Render standby states get 0 weight */
4664 pxw[14] = 0;
4665 pxw[15] = 0;
4666
4667 for (i = 0; i < 4; i++) {
4668 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
4669 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
4670 I915_WRITE(PXW + (i * 4), val);
4671 }
4672
4673 /* Adjust magic regs to magic values (more experimental results) */
4674 I915_WRITE(OGW0, 0);
4675 I915_WRITE(OGW1, 0);
4676 I915_WRITE(EG0, 0x00007f00);
4677 I915_WRITE(EG1, 0x0000000e);
4678 I915_WRITE(EG2, 0x000e0000);
4679 I915_WRITE(EG3, 0x68000300);
4680 I915_WRITE(EG4, 0x42000000);
4681 I915_WRITE(EG5, 0x00140031);
4682 I915_WRITE(EG6, 0);
4683 I915_WRITE(EG7, 0);
4684
4685 for (i = 0; i < 8; i++)
4686 I915_WRITE(PXWL + (i * 4), 0);
4687
4688 /* Enable PMON + select events */
4689 I915_WRITE(ECR, 0x80000019);
4690
4691 lcfuse = I915_READ(LCFUSE02);
4692
4693 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
4694 }
4695
4696 void intel_disable_gt_powersave(struct drm_device *dev)
4697 {
4698 struct drm_i915_private *dev_priv = dev->dev_private;
4699
4700 /* Interrupts should be disabled already to avoid re-arming. */
4701 WARN_ON(dev->irq_enabled);
4702
4703 if (IS_IRONLAKE_M(dev)) {
4704 ironlake_disable_drps(dev);
4705 ironlake_disable_rc6(dev);
4706 } else if (INTEL_INFO(dev)->gen >= 6) {
4707 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
4708 cancel_work_sync(&dev_priv->rps.work);
4709 mutex_lock(&dev_priv->rps.hw_lock);
4710 if (IS_VALLEYVIEW(dev))
4711 valleyview_disable_rps(dev);
4712 else
4713 gen6_disable_rps(dev);
4714 mutex_unlock(&dev_priv->rps.hw_lock);
4715 }
4716 }
4717
4718 static void intel_gen6_powersave_work(struct work_struct *work)
4719 {
4720 struct drm_i915_private *dev_priv =
4721 container_of(work, struct drm_i915_private,
4722 rps.delayed_resume_work.work);
4723 struct drm_device *dev = dev_priv->dev;
4724
4725 mutex_lock(&dev_priv->rps.hw_lock);
4726
4727 if (IS_VALLEYVIEW(dev)) {
4728 valleyview_enable_rps(dev);
4729 } else {
4730 gen6_enable_rps(dev);
4731 gen6_update_ring_freq(dev);
4732 }
4733 mutex_unlock(&dev_priv->rps.hw_lock);
4734 }
4735
4736 void intel_enable_gt_powersave(struct drm_device *dev)
4737 {
4738 struct drm_i915_private *dev_priv = dev->dev_private;
4739
4740 if (IS_IRONLAKE_M(dev)) {
4741 ironlake_enable_drps(dev);
4742 ironlake_enable_rc6(dev);
4743 intel_init_emon(dev);
4744 } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
4745 /*
4746 * PCU communication is slow and this doesn't need to be
4747 * done at any specific time, so do this out of our fast path
4748 * to make resume and init faster.
4749 */
4750 schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
4751 round_jiffies_up_relative(HZ));
4752 }
4753 }
4754
4755 static void ibx_init_clock_gating(struct drm_device *dev)
4756 {
4757 struct drm_i915_private *dev_priv = dev->dev_private;
4758
4759 /*
4760 * On Ibex Peak and Cougar Point, we need to disable clock
4761 * gating for the panel power sequencer or it will fail to
4762 * start up when no ports are active.
4763 */
4764 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
4765 }
4766
4767 static void g4x_disable_trickle_feed(struct drm_device *dev)
4768 {
4769 struct drm_i915_private *dev_priv = dev->dev_private;
4770 int pipe;
4771
4772 for_each_pipe(pipe) {
4773 I915_WRITE(DSPCNTR(pipe),
4774 I915_READ(DSPCNTR(pipe)) |
4775 DISPPLANE_TRICKLE_FEED_DISABLE);
4776 intel_flush_display_plane(dev_priv, pipe);
4777 }
4778 }
4779
4780 static void ironlake_init_clock_gating(struct drm_device *dev)
4781 {
4782 struct drm_i915_private *dev_priv = dev->dev_private;
4783 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
4784
4785 /*
4786 * Required for FBC
4787 * WaFbcDisableDpfcClockGating:ilk
4788 */
4789 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
4790 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
4791 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
4792
4793 I915_WRITE(PCH_3DCGDIS0,
4794 MARIUNIT_CLOCK_GATE_DISABLE |
4795 SVSMUNIT_CLOCK_GATE_DISABLE);
4796 I915_WRITE(PCH_3DCGDIS1,
4797 VFMUNIT_CLOCK_GATE_DISABLE);
4798
4799 /*
4800 * According to the spec the following bits should be set in
4801 * order to enable memory self-refresh
4802 * The bit 22/21 of 0x42004
4803 * The bit 5 of 0x42020
4804 * The bit 15 of 0x45000
4805 */
4806 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4807 (I915_READ(ILK_DISPLAY_CHICKEN2) |
4808 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4809 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
4810 I915_WRITE(DISP_ARB_CTL,
4811 (I915_READ(DISP_ARB_CTL) |
4812 DISP_FBC_WM_DIS));
4813 I915_WRITE(WM3_LP_ILK, 0);
4814 I915_WRITE(WM2_LP_ILK, 0);
4815 I915_WRITE(WM1_LP_ILK, 0);
4816
4817 /*
4818 * Based on the document from hardware guys the following bits
4819 * should be set unconditionally in order to enable FBC.
4820 * The bit 22 of 0x42000
4821 * The bit 22 of 0x42004
4822 * The bit 7,8,9 of 0x42020.
4823 */
4824 if (IS_IRONLAKE_M(dev)) {
4825 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
4826 I915_WRITE(ILK_DISPLAY_CHICKEN1,
4827 I915_READ(ILK_DISPLAY_CHICKEN1) |
4828 ILK_FBCQ_DIS);
4829 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4830 I915_READ(ILK_DISPLAY_CHICKEN2) |
4831 ILK_DPARB_GATE);
4832 }
4833
4834 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
4835
4836 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4837 I915_READ(ILK_DISPLAY_CHICKEN2) |
4838 ILK_ELPIN_409_SELECT);
4839 I915_WRITE(_3D_CHICKEN2,
4840 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
4841 _3D_CHICKEN2_WM_READ_PIPELINED);
4842
4843 /* WaDisableRenderCachePipelinedFlush:ilk */
4844 I915_WRITE(CACHE_MODE_0,
4845 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
4846
4847 g4x_disable_trickle_feed(dev);
4848
4849 ibx_init_clock_gating(dev);
4850 }
4851
4852 static void cpt_init_clock_gating(struct drm_device *dev)
4853 {
4854 struct drm_i915_private *dev_priv = dev->dev_private;
4855 int pipe;
4856 uint32_t val;
4857
4858 /*
4859 * On Ibex Peak and Cougar Point, we need to disable clock
4860 * gating for the panel power sequencer or it will fail to
4861 * start up when no ports are active.
4862 */
4863 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
4864 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
4865 DPLS_EDP_PPS_FIX_DIS);
4866 /* The below fixes the weird display corruption, a few pixels shifted
4867 * downward, on (only) LVDS of some HP laptops with IVY.
4868 */
4869 for_each_pipe(pipe) {
4870 val = I915_READ(TRANS_CHICKEN2(pipe));
4871 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
4872 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
4873 if (dev_priv->vbt.fdi_rx_polarity_inverted)
4874 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
4875 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
4876 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
4877 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
4878 I915_WRITE(TRANS_CHICKEN2(pipe), val);
4879 }
4880 /* WADP0ClockGatingDisable */
4881 for_each_pipe(pipe) {
4882 I915_WRITE(TRANS_CHICKEN1(pipe),
4883 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
4884 }
4885 }
4886
4887 static void gen6_check_mch_setup(struct drm_device *dev)
4888 {
4889 struct drm_i915_private *dev_priv = dev->dev_private;
4890 uint32_t tmp;
4891
4892 tmp = I915_READ(MCH_SSKPD);
4893 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) {
4894 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp);
4895 DRM_INFO("This can cause pipe underruns and display issues.\n");
4896 DRM_INFO("Please upgrade your BIOS to fix this.\n");
4897 }
4898 }
4899
4900 static void gen6_init_clock_gating(struct drm_device *dev)
4901 {
4902 struct drm_i915_private *dev_priv = dev->dev_private;
4903 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
4904
4905 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
4906
4907 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4908 I915_READ(ILK_DISPLAY_CHICKEN2) |
4909 ILK_ELPIN_409_SELECT);
4910
4911 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4912 I915_WRITE(_3D_CHICKEN,
4913 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
4914
4915 /* WaSetupGtModeTdRowDispatch:snb */
4916 if (IS_SNB_GT1(dev))
4917 I915_WRITE(GEN6_GT_MODE,
4918 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
4919
4920 I915_WRITE(WM3_LP_ILK, 0);
4921 I915_WRITE(WM2_LP_ILK, 0);
4922 I915_WRITE(WM1_LP_ILK, 0);
4923
4924 I915_WRITE(CACHE_MODE_0,
4925 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
4926
4927 I915_WRITE(GEN6_UCGCTL1,
4928 I915_READ(GEN6_UCGCTL1) |
4929 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
4930 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
4931
4932 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4933 * gating disable must be set. Failure to set it results in
4934 * flickering pixels due to Z write ordering failures after
4935 * some amount of runtime in the Mesa "fire" demo, and Unigine
4936 * Sanctuary and Tropics, and apparently anything else with
4937 * alpha test or pixel discard.
4938 *
4939 * According to the spec, bit 11 (RCCUNIT) must also be set,
4940 * but we didn't debug actual testcases to find it out.
4941 *
4942 * Also apply WaDisableVDSUnitClockGating:snb and
4943 * WaDisableRCPBUnitClockGating:snb.
4944 */
4945 I915_WRITE(GEN6_UCGCTL2,
4946 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
4947 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
4948 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4949
4950 /* Bspec says we need to always set all mask bits. */
4951 I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) |
4952 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL);
4953
4954 /*
4955 * According to the spec the following bits should be
4956 * set in order to enable memory self-refresh and fbc:
4957 * The bit21 and bit22 of 0x42000
4958 * The bit21 and bit22 of 0x42004
4959 * The bit5 and bit7 of 0x42020
4960 * The bit14 of 0x70180
4961 * The bit14 of 0x71180
4962 *
4963 * WaFbcAsynchFlipDisableFbcQueue:snb
4964 */
4965 I915_WRITE(ILK_DISPLAY_CHICKEN1,
4966 I915_READ(ILK_DISPLAY_CHICKEN1) |
4967 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
4968 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4969 I915_READ(ILK_DISPLAY_CHICKEN2) |
4970 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
4971 I915_WRITE(ILK_DSPCLK_GATE_D,
4972 I915_READ(ILK_DSPCLK_GATE_D) |
4973 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
4974 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
4975
4976 g4x_disable_trickle_feed(dev);
4977
4978 /* The default value should be 0x200 according to docs, but the two
4979 * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
4980 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff));
4981 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
4982
4983 cpt_init_clock_gating(dev);
4984
4985 gen6_check_mch_setup(dev);
4986 }
4987
4988 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
4989 {
4990 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
4991
4992 reg &= ~GEN7_FF_SCHED_MASK;
4993 reg |= GEN7_FF_TS_SCHED_HW;
4994 reg |= GEN7_FF_VS_SCHED_HW;
4995 reg |= GEN7_FF_DS_SCHED_HW;
4996
4997 if (IS_HASWELL(dev_priv->dev))
4998 reg &= ~GEN7_FF_VS_REF_CNT_FFME;
4999
5000 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
5001 }
5002
5003 static void lpt_init_clock_gating(struct drm_device *dev)
5004 {
5005 struct drm_i915_private *dev_priv = dev->dev_private;
5006
5007 /*
5008 * TODO: this bit should only be enabled when really needed, then
5009 * disabled when not needed anymore in order to save power.
5010 */
5011 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
5012 I915_WRITE(SOUTH_DSPCLK_GATE_D,
5013 I915_READ(SOUTH_DSPCLK_GATE_D) |
5014 PCH_LP_PARTITION_LEVEL_DISABLE);
5015
5016 /* WADPOClockGatingDisable:hsw */
5017 I915_WRITE(_TRANSA_CHICKEN1,
5018 I915_READ(_TRANSA_CHICKEN1) |
5019 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
5020 }
5021
5022 static void lpt_suspend_hw(struct drm_device *dev)
5023 {
5024 struct drm_i915_private *dev_priv = dev->dev_private;
5025
5026 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
5027 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
5028
5029 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
5030 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
5031 }
5032 }
5033
5034 static void haswell_init_clock_gating(struct drm_device *dev)
5035 {
5036 struct drm_i915_private *dev_priv = dev->dev_private;
5037
5038 I915_WRITE(WM3_LP_ILK, 0);
5039 I915_WRITE(WM2_LP_ILK, 0);
5040 I915_WRITE(WM1_LP_ILK, 0);
5041
5042 /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5043 * This implements the WaDisableRCZUnitClockGating:hsw workaround.
5044 */
5045 I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
5046
5047 /* Apply the WaDisableRHWOOptimizationForRenderHang:hsw workaround. */
5048 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5049 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5050
5051 /* WaApplyL3ControlAndL3ChickenMode:hsw */
5052 I915_WRITE(GEN7_L3CNTLREG1,
5053 GEN7_WA_FOR_GEN7_L3_CONTROL);
5054 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
5055 GEN7_WA_L3_CHICKEN_MODE);
5056
5057 /* This is required by WaCatErrorRejectionIssue:hsw */
5058 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5059 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5060 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5061
5062 /* WaVSRefCountFullforceMissDisable:hsw */
5063 gen7_setup_fixed_func_scheduler(dev_priv);
5064
5065 /* WaDisable4x2SubspanOptimization:hsw */
5066 I915_WRITE(CACHE_MODE_1,
5067 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5068
5069 /* WaSwitchSolVfFArbitrationPriority:hsw */
5070 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
5071
5072 /* WaRsPkgCStateDisplayPMReq:hsw */
5073 I915_WRITE(CHICKEN_PAR1_1,
5074 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
5075
5076 lpt_init_clock_gating(dev);
5077 }
5078
5079 static void ivybridge_init_clock_gating(struct drm_device *dev)
5080 {
5081 struct drm_i915_private *dev_priv = dev->dev_private;
5082 uint32_t snpcr;
5083
5084 I915_WRITE(WM3_LP_ILK, 0);
5085 I915_WRITE(WM2_LP_ILK, 0);
5086 I915_WRITE(WM1_LP_ILK, 0);
5087
5088 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
5089
5090 /* WaDisableEarlyCull:ivb */
5091 I915_WRITE(_3D_CHICKEN3,
5092 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5093
5094 /* WaDisableBackToBackFlipFix:ivb */
5095 I915_WRITE(IVB_CHICKEN3,
5096 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5097 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5098
5099 /* WaDisablePSDDualDispatchEnable:ivb */
5100 if (IS_IVB_GT1(dev))
5101 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5102 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5103 else
5104 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
5105 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5106
5107 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
5108 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5109 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5110
5111 /* WaApplyL3ControlAndL3ChickenMode:ivb */
5112 I915_WRITE(GEN7_L3CNTLREG1,
5113 GEN7_WA_FOR_GEN7_L3_CONTROL);
5114 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
5115 GEN7_WA_L3_CHICKEN_MODE);
5116 if (IS_IVB_GT1(dev))
5117 I915_WRITE(GEN7_ROW_CHICKEN2,
5118 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5119 else
5120 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
5121 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5122
5123
5124 /* WaForceL3Serialization:ivb */
5125 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5126 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5127
5128 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5129 * gating disable must be set. Failure to set it results in
5130 * flickering pixels due to Z write ordering failures after
5131 * some amount of runtime in the Mesa "fire" demo, and Unigine
5132 * Sanctuary and Tropics, and apparently anything else with
5133 * alpha test or pixel discard.
5134 *
5135 * According to the spec, bit 11 (RCCUNIT) must also be set,
5136 * but we didn't debug actual testcases to find it out.
5137 *
5138 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5139 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
5140 */
5141 I915_WRITE(GEN6_UCGCTL2,
5142 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
5143 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5144
5145 /* This is required by WaCatErrorRejectionIssue:ivb */
5146 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5147 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5148 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5149
5150 g4x_disable_trickle_feed(dev);
5151
5152 /* WaVSRefCountFullforceMissDisable:ivb */
5153 gen7_setup_fixed_func_scheduler(dev_priv);
5154
5155 /* WaDisable4x2SubspanOptimization:ivb */
5156 I915_WRITE(CACHE_MODE_1,
5157 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5158
5159 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5160 snpcr &= ~GEN6_MBC_SNPCR_MASK;
5161 snpcr |= GEN6_MBC_SNPCR_MED;
5162 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5163
5164 if (!HAS_PCH_NOP(dev))
5165 cpt_init_clock_gating(dev);
5166
5167 gen6_check_mch_setup(dev);
5168 }
5169
5170 static void valleyview_init_clock_gating(struct drm_device *dev)
5171 {
5172 struct drm_i915_private *dev_priv = dev->dev_private;
5173
5174 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
5175
5176 /* WaDisableEarlyCull:vlv */
5177 I915_WRITE(_3D_CHICKEN3,
5178 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5179
5180 /* WaDisableBackToBackFlipFix:vlv */
5181 I915_WRITE(IVB_CHICKEN3,
5182 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5183 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5184
5185 /* WaDisablePSDDualDispatchEnable:vlv */
5186 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5187 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
5188 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5189
5190 /* Apply the WaDisableRHWOOptimizationForRenderHang:vlv workaround. */
5191 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5192 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5193
5194 /* WaApplyL3ControlAndL3ChickenMode:vlv */
5195 I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
5196 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
5197
5198 /* WaForceL3Serialization:vlv */
5199 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5200 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5201
5202 /* WaDisableDopClockGating:vlv */
5203 I915_WRITE(GEN7_ROW_CHICKEN2,
5204 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5205
5206 /* This is required by WaCatErrorRejectionIssue:vlv */
5207 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5208 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5209 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5210
5211 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5212 * gating disable must be set. Failure to set it results in
5213 * flickering pixels due to Z write ordering failures after
5214 * some amount of runtime in the Mesa "fire" demo, and Unigine
5215 * Sanctuary and Tropics, and apparently anything else with
5216 * alpha test or pixel discard.
5217 *
5218 * According to the spec, bit 11 (RCCUNIT) must also be set,
5219 * but we didn't debug actual testcases to find it out.
5220 *
5221 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5222 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
5223 *
5224 * Also apply WaDisableVDSUnitClockGating:vlv and
5225 * WaDisableRCPBUnitClockGating:vlv.
5226 */
5227 I915_WRITE(GEN6_UCGCTL2,
5228 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
5229 GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
5230 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
5231 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
5232 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5233
5234 I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
5235
5236 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
5237
5238 I915_WRITE(CACHE_MODE_1,
5239 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5240
5241 /*
5242 * WaDisableVLVClockGating_VBIIssue:vlv
5243 * Disable clock gating on th GCFG unit to prevent a delay
5244 * in the reporting of vblank events.
5245 */
5246 I915_WRITE(VLV_GUNIT_CLOCK_GATE, 0xffffffff);
5247
5248 /* Conservative clock gating settings for now */
5249 I915_WRITE(0x9400, 0xffffffff);
5250 I915_WRITE(0x9404, 0xffffffff);
5251 I915_WRITE(0x9408, 0xffffffff);
5252 I915_WRITE(0x940c, 0xffffffff);
5253 I915_WRITE(0x9410, 0xffffffff);
5254 I915_WRITE(0x9414, 0xffffffff);
5255 I915_WRITE(0x9418, 0xffffffff);
5256 }
5257
5258 static void g4x_init_clock_gating(struct drm_device *dev)
5259 {
5260 struct drm_i915_private *dev_priv = dev->dev_private;
5261 uint32_t dspclk_gate;
5262
5263 I915_WRITE(RENCLK_GATE_D1, 0);
5264 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5265 GS_UNIT_CLOCK_GATE_DISABLE |
5266 CL_UNIT_CLOCK_GATE_DISABLE);
5267 I915_WRITE(RAMCLK_GATE_D, 0);
5268 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5269 OVRUNIT_CLOCK_GATE_DISABLE |
5270 OVCUNIT_CLOCK_GATE_DISABLE;
5271 if (IS_GM45(dev))
5272 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5273 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5274
5275 /* WaDisableRenderCachePipelinedFlush */
5276 I915_WRITE(CACHE_MODE_0,
5277 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
5278
5279 g4x_disable_trickle_feed(dev);
5280 }
5281
5282 static void crestline_init_clock_gating(struct drm_device *dev)
5283 {
5284 struct drm_i915_private *dev_priv = dev->dev_private;
5285
5286 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5287 I915_WRITE(RENCLK_GATE_D2, 0);
5288 I915_WRITE(DSPCLK_GATE_D, 0);
5289 I915_WRITE(RAMCLK_GATE_D, 0);
5290 I915_WRITE16(DEUC, 0);
5291 I915_WRITE(MI_ARB_STATE,
5292 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
5293 }
5294
5295 static void broadwater_init_clock_gating(struct drm_device *dev)
5296 {
5297 struct drm_i915_private *dev_priv = dev->dev_private;
5298
5299 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5300 I965_RCC_CLOCK_GATE_DISABLE |
5301 I965_RCPB_CLOCK_GATE_DISABLE |
5302 I965_ISC_CLOCK_GATE_DISABLE |
5303 I965_FBC_CLOCK_GATE_DISABLE);
5304 I915_WRITE(RENCLK_GATE_D2, 0);
5305 I915_WRITE(MI_ARB_STATE,
5306 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
5307 }
5308
5309 static void gen3_init_clock_gating(struct drm_device *dev)
5310 {
5311 struct drm_i915_private *dev_priv = dev->dev_private;
5312 u32 dstate = I915_READ(D_STATE);
5313
5314 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5315 DSTATE_DOT_CLOCK_GATING;
5316 I915_WRITE(D_STATE, dstate);
5317
5318 if (IS_PINEVIEW(dev))
5319 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
5320
5321 /* IIR "flip pending" means done if this bit is set */
5322 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
5323 }
5324
5325 static void i85x_init_clock_gating(struct drm_device *dev)
5326 {
5327 struct drm_i915_private *dev_priv = dev->dev_private;
5328
5329 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5330 }
5331
5332 static void i830_init_clock_gating(struct drm_device *dev)
5333 {
5334 struct drm_i915_private *dev_priv = dev->dev_private;
5335
5336 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5337 }
5338
5339 void intel_init_clock_gating(struct drm_device *dev)
5340 {
5341 struct drm_i915_private *dev_priv = dev->dev_private;
5342
5343 dev_priv->display.init_clock_gating(dev);
5344 }
5345
5346 void intel_suspend_hw(struct drm_device *dev)
5347 {
5348 if (HAS_PCH_LPT(dev))
5349 lpt_suspend_hw(dev);
5350 }
5351
5352 /**
5353 * We should only use the power well if we explicitly asked the hardware to
5354 * enable it, so check if it's enabled and also check if we've requested it to
5355 * be enabled.
5356 */
5357 bool intel_display_power_enabled(struct drm_device *dev,
5358 enum intel_display_power_domain domain)
5359 {
5360 struct drm_i915_private *dev_priv = dev->dev_private;
5361
5362 if (!HAS_POWER_WELL(dev))
5363 return true;
5364
5365 switch (domain) {
5366 case POWER_DOMAIN_PIPE_A:
5367 case POWER_DOMAIN_TRANSCODER_EDP:
5368 return true;
5369 case POWER_DOMAIN_VGA:
5370 case POWER_DOMAIN_PIPE_B:
5371 case POWER_DOMAIN_PIPE_C:
5372 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
5373 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
5374 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
5375 case POWER_DOMAIN_TRANSCODER_A:
5376 case POWER_DOMAIN_TRANSCODER_B:
5377 case POWER_DOMAIN_TRANSCODER_C:
5378 return I915_READ(HSW_PWR_WELL_DRIVER) ==
5379 (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
5380 default:
5381 BUG();
5382 }
5383 }
5384
5385 static void __intel_set_power_well(struct drm_device *dev, bool enable)
5386 {
5387 struct drm_i915_private *dev_priv = dev->dev_private;
5388 bool is_enabled, enable_requested;
5389 uint32_t tmp;
5390
5391 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
5392 is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
5393 enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
5394
5395 if (enable) {
5396 if (!enable_requested)
5397 I915_WRITE(HSW_PWR_WELL_DRIVER,
5398 HSW_PWR_WELL_ENABLE_REQUEST);
5399
5400 if (!is_enabled) {
5401 DRM_DEBUG_KMS("Enabling power well\n");
5402 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
5403 HSW_PWR_WELL_STATE_ENABLED), 20))
5404 DRM_ERROR("Timeout enabling power well\n");
5405 }
5406 } else {
5407 if (enable_requested) {
5408 unsigned long irqflags;
5409 enum pipe p;
5410
5411 I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
5412 POSTING_READ(HSW_PWR_WELL_DRIVER);
5413 DRM_DEBUG_KMS("Requesting to disable the power well\n");
5414
5415 /*
5416 * After this, the registers on the pipes that are part
5417 * of the power well will become zero, so we have to
5418 * adjust our counters according to that.
5419 *
5420 * FIXME: Should we do this in general in
5421 * drm_vblank_post_modeset?
5422 */
5423 spin_lock_irqsave(&dev->vbl_lock, irqflags);
5424 for_each_pipe(p)
5425 if (p != PIPE_A)
5426 dev->last_vblank[p] = 0;
5427 spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
5428 }
5429 }
5430 }
5431
5432 static void __intel_power_well_get(struct i915_power_well *power_well)
5433 {
5434 if (!power_well->count++)
5435 __intel_set_power_well(power_well->device, true);
5436 }
5437
5438 static void __intel_power_well_put(struct i915_power_well *power_well)
5439 {
5440 WARN_ON(!power_well->count);
5441 if (!--power_well->count)
5442 __intel_set_power_well(power_well->device, false);
5443 }
5444
5445 void intel_display_power_get(struct drm_device *dev,
5446 enum intel_display_power_domain domain)
5447 {
5448 struct drm_i915_private *dev_priv = dev->dev_private;
5449 struct i915_power_well *power_well = &dev_priv->power_well;
5450
5451 if (!HAS_POWER_WELL(dev))
5452 return;
5453
5454 switch (domain) {
5455 case POWER_DOMAIN_PIPE_A:
5456 case POWER_DOMAIN_TRANSCODER_EDP:
5457 return;
5458 case POWER_DOMAIN_VGA:
5459 case POWER_DOMAIN_PIPE_B:
5460 case POWER_DOMAIN_PIPE_C:
5461 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
5462 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
5463 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
5464 case POWER_DOMAIN_TRANSCODER_A:
5465 case POWER_DOMAIN_TRANSCODER_B:
5466 case POWER_DOMAIN_TRANSCODER_C:
5467 spin_lock_irq(&power_well->lock);
5468 __intel_power_well_get(power_well);
5469 spin_unlock_irq(&power_well->lock);
5470 return;
5471 default:
5472 BUG();
5473 }
5474 }
5475
5476 void intel_display_power_put(struct drm_device *dev,
5477 enum intel_display_power_domain domain)
5478 {
5479 struct drm_i915_private *dev_priv = dev->dev_private;
5480 struct i915_power_well *power_well = &dev_priv->power_well;
5481
5482 if (!HAS_POWER_WELL(dev))
5483 return;
5484
5485 switch (domain) {
5486 case POWER_DOMAIN_PIPE_A:
5487 case POWER_DOMAIN_TRANSCODER_EDP:
5488 return;
5489 case POWER_DOMAIN_VGA:
5490 case POWER_DOMAIN_PIPE_B:
5491 case POWER_DOMAIN_PIPE_C:
5492 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
5493 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
5494 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
5495 case POWER_DOMAIN_TRANSCODER_A:
5496 case POWER_DOMAIN_TRANSCODER_B:
5497 case POWER_DOMAIN_TRANSCODER_C:
5498 spin_lock_irq(&power_well->lock);
5499 __intel_power_well_put(power_well);
5500 spin_unlock_irq(&power_well->lock);
5501 return;
5502 default:
5503 BUG();
5504 }
5505 }
5506
5507 static struct i915_power_well *hsw_pwr;
5508
5509 /* Display audio driver power well request */
5510 void i915_request_power_well(void)
5511 {
5512 if (WARN_ON(!hsw_pwr))
5513 return;
5514
5515 spin_lock_irq(&hsw_pwr->lock);
5516 __intel_power_well_get(hsw_pwr);
5517 spin_unlock_irq(&hsw_pwr->lock);
5518 }
5519 EXPORT_SYMBOL_GPL(i915_request_power_well);
5520
5521 /* Display audio driver power well release */
5522 void i915_release_power_well(void)
5523 {
5524 if (WARN_ON(!hsw_pwr))
5525 return;
5526
5527 spin_lock_irq(&hsw_pwr->lock);
5528 __intel_power_well_put(hsw_pwr);
5529 spin_unlock_irq(&hsw_pwr->lock);
5530 }
5531 EXPORT_SYMBOL_GPL(i915_release_power_well);
5532
5533 int i915_init_power_well(struct drm_device *dev)
5534 {
5535 struct drm_i915_private *dev_priv = dev->dev_private;
5536
5537 hsw_pwr = &dev_priv->power_well;
5538
5539 hsw_pwr->device = dev;
5540 spin_lock_init(&hsw_pwr->lock);
5541 hsw_pwr->count = 0;
5542
5543 return 0;
5544 }
5545
5546 void i915_remove_power_well(struct drm_device *dev)
5547 {
5548 hsw_pwr = NULL;
5549 }
5550
5551 void intel_set_power_well(struct drm_device *dev, bool enable)
5552 {
5553 struct drm_i915_private *dev_priv = dev->dev_private;
5554 struct i915_power_well *power_well = &dev_priv->power_well;
5555
5556 if (!HAS_POWER_WELL(dev))
5557 return;
5558
5559 if (!i915_disable_power_well && !enable)
5560 return;
5561
5562 spin_lock_irq(&power_well->lock);
5563
5564 /*
5565 * This function will only ever contribute one
5566 * to the power well reference count. i915_request
5567 * is what tracks whether we have or have not
5568 * added the one to the reference count.
5569 */
5570 if (power_well->i915_request == enable)
5571 goto out;
5572
5573 power_well->i915_request = enable;
5574
5575 if (enable)
5576 __intel_power_well_get(power_well);
5577 else
5578 __intel_power_well_put(power_well);
5579
5580 out:
5581 spin_unlock_irq(&power_well->lock);
5582 }
5583
5584 static void intel_resume_power_well(struct drm_device *dev)
5585 {
5586 struct drm_i915_private *dev_priv = dev->dev_private;
5587 struct i915_power_well *power_well = &dev_priv->power_well;
5588
5589 if (!HAS_POWER_WELL(dev))
5590 return;
5591
5592 spin_lock_irq(&power_well->lock);
5593 __intel_set_power_well(dev, power_well->count > 0);
5594 spin_unlock_irq(&power_well->lock);
5595 }
5596
5597 /*
5598 * Starting with Haswell, we have a "Power Down Well" that can be turned off
5599 * when not needed anymore. We have 4 registers that can request the power well
5600 * to be enabled, and it will only be disabled if none of the registers is
5601 * requesting it to be enabled.
5602 */
5603 void intel_init_power_well(struct drm_device *dev)
5604 {
5605 struct drm_i915_private *dev_priv = dev->dev_private;
5606
5607 if (!HAS_POWER_WELL(dev))
5608 return;
5609
5610 /* For now, we need the power well to be always enabled. */
5611 intel_set_power_well(dev, true);
5612 intel_resume_power_well(dev);
5613
5614 /* We're taking over the BIOS, so clear any requests made by it since
5615 * the driver is in charge now. */
5616 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
5617 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
5618 }
5619
5620 /* Disables PC8 so we can use the GMBUS and DP AUX interrupts. */
5621 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)
5622 {
5623 hsw_disable_package_c8(dev_priv);
5624 }
5625
5626 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)
5627 {
5628 hsw_enable_package_c8(dev_priv);
5629 }
5630
5631 /* Set up chip specific power management-related functions */
5632 void intel_init_pm(struct drm_device *dev)
5633 {
5634 struct drm_i915_private *dev_priv = dev->dev_private;
5635
5636 if (I915_HAS_FBC(dev)) {
5637 if (HAS_PCH_SPLIT(dev)) {
5638 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
5639 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
5640 dev_priv->display.enable_fbc =
5641 gen7_enable_fbc;
5642 else
5643 dev_priv->display.enable_fbc =
5644 ironlake_enable_fbc;
5645 dev_priv->display.disable_fbc = ironlake_disable_fbc;
5646 } else if (IS_GM45(dev)) {
5647 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5648 dev_priv->display.enable_fbc = g4x_enable_fbc;
5649 dev_priv->display.disable_fbc = g4x_disable_fbc;
5650 } else if (IS_CRESTLINE(dev)) {
5651 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5652 dev_priv->display.enable_fbc = i8xx_enable_fbc;
5653 dev_priv->display.disable_fbc = i8xx_disable_fbc;
5654 }
5655 /* 855GM needs testing */
5656 }
5657
5658 /* For cxsr */
5659 if (IS_PINEVIEW(dev))
5660 i915_pineview_get_mem_freq(dev);
5661 else if (IS_GEN5(dev))
5662 i915_ironlake_get_mem_freq(dev);
5663
5664 /* For FIFO watermark updates */
5665 if (HAS_PCH_SPLIT(dev)) {
5666 intel_setup_wm_latency(dev);
5667
5668 if (IS_GEN5(dev)) {
5669 if (dev_priv->wm.pri_latency[1] &&
5670 dev_priv->wm.spr_latency[1] &&
5671 dev_priv->wm.cur_latency[1])
5672 dev_priv->display.update_wm = ironlake_update_wm;
5673 else {
5674 DRM_DEBUG_KMS("Failed to get proper latency. "
5675 "Disable CxSR\n");
5676 dev_priv->display.update_wm = NULL;
5677 }
5678 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
5679 } else if (IS_GEN6(dev)) {
5680 if (dev_priv->wm.pri_latency[0] &&
5681 dev_priv->wm.spr_latency[0] &&
5682 dev_priv->wm.cur_latency[0]) {
5683 dev_priv->display.update_wm = sandybridge_update_wm;
5684 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
5685 } else {
5686 DRM_DEBUG_KMS("Failed to read display plane latency. "
5687 "Disable CxSR\n");
5688 dev_priv->display.update_wm = NULL;
5689 }
5690 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
5691 } else if (IS_IVYBRIDGE(dev)) {
5692 if (dev_priv->wm.pri_latency[0] &&
5693 dev_priv->wm.spr_latency[0] &&
5694 dev_priv->wm.cur_latency[0]) {
5695 dev_priv->display.update_wm = ivybridge_update_wm;
5696 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
5697 } else {
5698 DRM_DEBUG_KMS("Failed to read display plane latency. "
5699 "Disable CxSR\n");
5700 dev_priv->display.update_wm = NULL;
5701 }
5702 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
5703 } else if (IS_HASWELL(dev)) {
5704 if (dev_priv->wm.pri_latency[0] &&
5705 dev_priv->wm.spr_latency[0] &&
5706 dev_priv->wm.cur_latency[0]) {
5707 dev_priv->display.update_wm = haswell_update_wm;
5708 dev_priv->display.update_sprite_wm =
5709 haswell_update_sprite_wm;
5710 } else {
5711 DRM_DEBUG_KMS("Failed to read display plane latency. "
5712 "Disable CxSR\n");
5713 dev_priv->display.update_wm = NULL;
5714 }
5715 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
5716 } else
5717 dev_priv->display.update_wm = NULL;
5718 } else if (IS_VALLEYVIEW(dev)) {
5719 dev_priv->display.update_wm = valleyview_update_wm;
5720 dev_priv->display.init_clock_gating =
5721 valleyview_init_clock_gating;
5722 } else if (IS_PINEVIEW(dev)) {
5723 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5724 dev_priv->is_ddr3,
5725 dev_priv->fsb_freq,
5726 dev_priv->mem_freq)) {
5727 DRM_INFO("failed to find known CxSR latency "
5728 "(found ddr%s fsb freq %d, mem freq %d), "
5729 "disabling CxSR\n",
5730 (dev_priv->is_ddr3 == 1) ? "3" : "2",
5731 dev_priv->fsb_freq, dev_priv->mem_freq);
5732 /* Disable CxSR and never update its watermark again */
5733 pineview_disable_cxsr(dev);
5734 dev_priv->display.update_wm = NULL;
5735 } else
5736 dev_priv->display.update_wm = pineview_update_wm;
5737 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
5738 } else if (IS_G4X(dev)) {
5739 dev_priv->display.update_wm = g4x_update_wm;
5740 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
5741 } else if (IS_GEN4(dev)) {
5742 dev_priv->display.update_wm = i965_update_wm;
5743 if (IS_CRESTLINE(dev))
5744 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
5745 else if (IS_BROADWATER(dev))
5746 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
5747 } else if (IS_GEN3(dev)) {
5748 dev_priv->display.update_wm = i9xx_update_wm;
5749 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5750 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
5751 } else if (IS_I865G(dev)) {
5752 dev_priv->display.update_wm = i830_update_wm;
5753 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
5754 dev_priv->display.get_fifo_size = i830_get_fifo_size;
5755 } else if (IS_I85X(dev)) {
5756 dev_priv->display.update_wm = i9xx_update_wm;
5757 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
5758 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
5759 } else {
5760 dev_priv->display.update_wm = i830_update_wm;
5761 dev_priv->display.init_clock_gating = i830_init_clock_gating;
5762 if (IS_845G(dev))
5763 dev_priv->display.get_fifo_size = i845_get_fifo_size;
5764 else
5765 dev_priv->display.get_fifo_size = i830_get_fifo_size;
5766 }
5767 }
5768
5769 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
5770 {
5771 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5772
5773 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
5774 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
5775 return -EAGAIN;
5776 }
5777
5778 I915_WRITE(GEN6_PCODE_DATA, *val);
5779 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
5780
5781 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
5782 500)) {
5783 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
5784 return -ETIMEDOUT;
5785 }
5786
5787 *val = I915_READ(GEN6_PCODE_DATA);
5788 I915_WRITE(GEN6_PCODE_DATA, 0);
5789
5790 return 0;
5791 }
5792
5793 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
5794 {
5795 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5796
5797 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
5798 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
5799 return -EAGAIN;
5800 }
5801
5802 I915_WRITE(GEN6_PCODE_DATA, val);
5803 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
5804
5805 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
5806 500)) {
5807 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
5808 return -ETIMEDOUT;
5809 }
5810
5811 I915_WRITE(GEN6_PCODE_DATA, 0);
5812
5813 return 0;
5814 }
5815
5816 int vlv_gpu_freq(int ddr_freq, int val)
5817 {
5818 int mult, base;
5819
5820 switch (ddr_freq) {
5821 case 800:
5822 mult = 20;
5823 base = 120;
5824 break;
5825 case 1066:
5826 mult = 22;
5827 base = 133;
5828 break;
5829 case 1333:
5830 mult = 21;
5831 base = 125;
5832 break;
5833 default:
5834 return -1;
5835 }
5836
5837 return ((val - 0xbd) * mult) + base;
5838 }
5839
5840 int vlv_freq_opcode(int ddr_freq, int val)
5841 {
5842 int mult, base;
5843
5844 switch (ddr_freq) {
5845 case 800:
5846 mult = 20;
5847 base = 120;
5848 break;
5849 case 1066:
5850 mult = 22;
5851 base = 133;
5852 break;
5853 case 1333:
5854 mult = 21;
5855 base = 125;
5856 break;
5857 default:
5858 return -1;
5859 }
5860
5861 val /= mult;
5862 val -= base / mult;
5863 val += 0xbd;
5864
5865 if (val > 0xea)
5866 val = 0xea;
5867
5868 return val;
5869 }
5870
5871 void intel_pm_init(struct drm_device *dev)
5872 {
5873 struct drm_i915_private *dev_priv = dev->dev_private;
5874
5875 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
5876 intel_gen6_powersave_work);
5877 }
5878
Linux kernel - Deliverables
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