2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
28 #include <linux/cpufreq.h>
30 #include "intel_drv.h"
31 #include "../../../platform/x86/intel_ips.h"
32 #include <linux/module.h>
35 * RC6 is a special power stage which allows the GPU to enter an very
36 * low-voltage mode when idle, using down to 0V while at this stage. This
37 * stage is entered automatically when the GPU is idle when RC6 support is
38 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
40 * There are different RC6 modes available in Intel GPU, which differentiate
41 * among each other with the latency required to enter and leave RC6 and
42 * voltage consumed by the GPU in different states.
44 * The combination of the following flags define which states GPU is allowed
45 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
46 * RC6pp is deepest RC6. Their support by hardware varies according to the
47 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
48 * which brings the most power savings; deeper states save more power, but
49 * require higher latency to switch to and wake up.
51 #define INTEL_RC6_ENABLE (1<<0)
52 #define INTEL_RC6p_ENABLE (1<<1)
53 #define INTEL_RC6pp_ENABLE (1<<2)
55 static void bxt_init_clock_gating(struct drm_device
*dev
)
57 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
59 /* WaDisableSDEUnitClockGating:bxt */
60 I915_WRITE(GEN8_UCGCTL6
, I915_READ(GEN8_UCGCTL6
) |
61 GEN8_SDEUNIT_CLOCK_GATE_DISABLE
);
65 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
67 I915_WRITE(GEN8_UCGCTL6
, I915_READ(GEN8_UCGCTL6
) |
68 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ
);
71 static void i915_pineview_get_mem_freq(struct drm_device
*dev
)
73 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
76 tmp
= I915_READ(CLKCFG
);
78 switch (tmp
& CLKCFG_FSB_MASK
) {
80 dev_priv
->fsb_freq
= 533; /* 133*4 */
83 dev_priv
->fsb_freq
= 800; /* 200*4 */
86 dev_priv
->fsb_freq
= 667; /* 167*4 */
89 dev_priv
->fsb_freq
= 400; /* 100*4 */
93 switch (tmp
& CLKCFG_MEM_MASK
) {
95 dev_priv
->mem_freq
= 533;
98 dev_priv
->mem_freq
= 667;
101 dev_priv
->mem_freq
= 800;
105 /* detect pineview DDR3 setting */
106 tmp
= I915_READ(CSHRDDR3CTL
);
107 dev_priv
->is_ddr3
= (tmp
& CSHRDDR3CTL_DDR3
) ? 1 : 0;
110 static void i915_ironlake_get_mem_freq(struct drm_device
*dev
)
112 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
115 ddrpll
= I915_READ16(DDRMPLL1
);
116 csipll
= I915_READ16(CSIPLL0
);
118 switch (ddrpll
& 0xff) {
120 dev_priv
->mem_freq
= 800;
123 dev_priv
->mem_freq
= 1066;
126 dev_priv
->mem_freq
= 1333;
129 dev_priv
->mem_freq
= 1600;
132 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
134 dev_priv
->mem_freq
= 0;
138 dev_priv
->ips
.r_t
= dev_priv
->mem_freq
;
140 switch (csipll
& 0x3ff) {
142 dev_priv
->fsb_freq
= 3200;
145 dev_priv
->fsb_freq
= 3733;
148 dev_priv
->fsb_freq
= 4266;
151 dev_priv
->fsb_freq
= 4800;
154 dev_priv
->fsb_freq
= 5333;
157 dev_priv
->fsb_freq
= 5866;
160 dev_priv
->fsb_freq
= 6400;
163 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
165 dev_priv
->fsb_freq
= 0;
169 if (dev_priv
->fsb_freq
== 3200) {
170 dev_priv
->ips
.c_m
= 0;
171 } else if (dev_priv
->fsb_freq
> 3200 && dev_priv
->fsb_freq
<= 4800) {
172 dev_priv
->ips
.c_m
= 1;
174 dev_priv
->ips
.c_m
= 2;
178 static const struct cxsr_latency cxsr_latency_table
[] = {
179 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
180 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
181 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
182 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
183 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
185 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
186 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
187 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
188 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
189 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
191 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
192 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
193 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
194 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
195 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
197 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
198 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
199 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
200 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
201 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
203 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
204 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
205 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
206 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
207 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
209 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
210 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
211 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
212 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
213 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
216 static const struct cxsr_latency
*intel_get_cxsr_latency(int is_desktop
,
221 const struct cxsr_latency
*latency
;
224 if (fsb
== 0 || mem
== 0)
227 for (i
= 0; i
< ARRAY_SIZE(cxsr_latency_table
); i
++) {
228 latency
= &cxsr_latency_table
[i
];
229 if (is_desktop
== latency
->is_desktop
&&
230 is_ddr3
== latency
->is_ddr3
&&
231 fsb
== latency
->fsb_freq
&& mem
== latency
->mem_freq
)
235 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
240 static void chv_set_memory_dvfs(struct drm_i915_private
*dev_priv
, bool enable
)
244 mutex_lock(&dev_priv
->rps
.hw_lock
);
246 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DDR_SETUP2
);
248 val
&= ~FORCE_DDR_HIGH_FREQ
;
250 val
|= FORCE_DDR_HIGH_FREQ
;
251 val
&= ~FORCE_DDR_LOW_FREQ
;
252 val
|= FORCE_DDR_FREQ_REQ_ACK
;
253 vlv_punit_write(dev_priv
, PUNIT_REG_DDR_SETUP2
, val
);
255 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DDR_SETUP2
) &
256 FORCE_DDR_FREQ_REQ_ACK
) == 0, 3))
257 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
259 mutex_unlock(&dev_priv
->rps
.hw_lock
);
262 static void chv_set_memory_pm5(struct drm_i915_private
*dev_priv
, bool enable
)
266 mutex_lock(&dev_priv
->rps
.hw_lock
);
268 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
270 val
|= DSP_MAXFIFO_PM5_ENABLE
;
272 val
&= ~DSP_MAXFIFO_PM5_ENABLE
;
273 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
275 mutex_unlock(&dev_priv
->rps
.hw_lock
);
278 #define FW_WM(value, plane) \
279 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
281 void intel_set_memory_cxsr(struct drm_i915_private
*dev_priv
, bool enable
)
283 struct drm_device
*dev
= dev_priv
->dev
;
286 if (IS_VALLEYVIEW(dev
)) {
287 I915_WRITE(FW_BLC_SELF_VLV
, enable
? FW_CSPWRDWNEN
: 0);
288 POSTING_READ(FW_BLC_SELF_VLV
);
289 dev_priv
->wm
.vlv
.cxsr
= enable
;
290 } else if (IS_G4X(dev
) || IS_CRESTLINE(dev
)) {
291 I915_WRITE(FW_BLC_SELF
, enable
? FW_BLC_SELF_EN
: 0);
292 POSTING_READ(FW_BLC_SELF
);
293 } else if (IS_PINEVIEW(dev
)) {
294 val
= I915_READ(DSPFW3
) & ~PINEVIEW_SELF_REFRESH_EN
;
295 val
|= enable
? PINEVIEW_SELF_REFRESH_EN
: 0;
296 I915_WRITE(DSPFW3
, val
);
297 POSTING_READ(DSPFW3
);
298 } else if (IS_I945G(dev
) || IS_I945GM(dev
)) {
299 val
= enable
? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN
) :
300 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN
);
301 I915_WRITE(FW_BLC_SELF
, val
);
302 POSTING_READ(FW_BLC_SELF
);
303 } else if (IS_I915GM(dev
)) {
304 val
= enable
? _MASKED_BIT_ENABLE(INSTPM_SELF_EN
) :
305 _MASKED_BIT_DISABLE(INSTPM_SELF_EN
);
306 I915_WRITE(INSTPM
, val
);
307 POSTING_READ(INSTPM
);
312 DRM_DEBUG_KMS("memory self-refresh is %s\n",
313 enable
? "enabled" : "disabled");
318 * Latency for FIFO fetches is dependent on several factors:
319 * - memory configuration (speed, channels)
321 * - current MCH state
322 * It can be fairly high in some situations, so here we assume a fairly
323 * pessimal value. It's a tradeoff between extra memory fetches (if we
324 * set this value too high, the FIFO will fetch frequently to stay full)
325 * and power consumption (set it too low to save power and we might see
326 * FIFO underruns and display "flicker").
328 * A value of 5us seems to be a good balance; safe for very low end
329 * platforms but not overly aggressive on lower latency configs.
331 static const int pessimal_latency_ns
= 5000;
333 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
334 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
336 static int vlv_get_fifo_size(struct drm_device
*dev
,
337 enum pipe pipe
, int plane
)
339 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
340 int sprite0_start
, sprite1_start
, size
;
343 uint32_t dsparb
, dsparb2
, dsparb3
;
345 dsparb
= I915_READ(DSPARB
);
346 dsparb2
= I915_READ(DSPARB2
);
347 sprite0_start
= VLV_FIFO_START(dsparb
, dsparb2
, 0, 0);
348 sprite1_start
= VLV_FIFO_START(dsparb
, dsparb2
, 8, 4);
351 dsparb
= I915_READ(DSPARB
);
352 dsparb2
= I915_READ(DSPARB2
);
353 sprite0_start
= VLV_FIFO_START(dsparb
, dsparb2
, 16, 8);
354 sprite1_start
= VLV_FIFO_START(dsparb
, dsparb2
, 24, 12);
357 dsparb2
= I915_READ(DSPARB2
);
358 dsparb3
= I915_READ(DSPARB3
);
359 sprite0_start
= VLV_FIFO_START(dsparb3
, dsparb2
, 0, 16);
360 sprite1_start
= VLV_FIFO_START(dsparb3
, dsparb2
, 8, 20);
368 size
= sprite0_start
;
371 size
= sprite1_start
- sprite0_start
;
374 size
= 512 - 1 - sprite1_start
;
380 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
381 pipe_name(pipe
), plane
== 0 ? "primary" : "sprite",
382 plane
== 0 ? plane_name(pipe
) : sprite_name(pipe
, plane
- 1),
388 static int i9xx_get_fifo_size(struct drm_device
*dev
, int plane
)
390 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
391 uint32_t dsparb
= I915_READ(DSPARB
);
394 size
= dsparb
& 0x7f;
396 size
= ((dsparb
>> DSPARB_CSTART_SHIFT
) & 0x7f) - size
;
398 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
399 plane
? "B" : "A", size
);
404 static int i830_get_fifo_size(struct drm_device
*dev
, int plane
)
406 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
407 uint32_t dsparb
= I915_READ(DSPARB
);
410 size
= dsparb
& 0x1ff;
412 size
= ((dsparb
>> DSPARB_BEND_SHIFT
) & 0x1ff) - size
;
413 size
>>= 1; /* Convert to cachelines */
415 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
416 plane
? "B" : "A", size
);
421 static int i845_get_fifo_size(struct drm_device
*dev
, int plane
)
423 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
424 uint32_t dsparb
= I915_READ(DSPARB
);
427 size
= dsparb
& 0x7f;
428 size
>>= 2; /* Convert to cachelines */
430 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
437 /* Pineview has different values for various configs */
438 static const struct intel_watermark_params pineview_display_wm
= {
439 .fifo_size
= PINEVIEW_DISPLAY_FIFO
,
440 .max_wm
= PINEVIEW_MAX_WM
,
441 .default_wm
= PINEVIEW_DFT_WM
,
442 .guard_size
= PINEVIEW_GUARD_WM
,
443 .cacheline_size
= PINEVIEW_FIFO_LINE_SIZE
,
445 static const struct intel_watermark_params pineview_display_hplloff_wm
= {
446 .fifo_size
= PINEVIEW_DISPLAY_FIFO
,
447 .max_wm
= PINEVIEW_MAX_WM
,
448 .default_wm
= PINEVIEW_DFT_HPLLOFF_WM
,
449 .guard_size
= PINEVIEW_GUARD_WM
,
450 .cacheline_size
= PINEVIEW_FIFO_LINE_SIZE
,
452 static const struct intel_watermark_params pineview_cursor_wm
= {
453 .fifo_size
= PINEVIEW_CURSOR_FIFO
,
454 .max_wm
= PINEVIEW_CURSOR_MAX_WM
,
455 .default_wm
= PINEVIEW_CURSOR_DFT_WM
,
456 .guard_size
= PINEVIEW_CURSOR_GUARD_WM
,
457 .cacheline_size
= PINEVIEW_FIFO_LINE_SIZE
,
459 static const struct intel_watermark_params pineview_cursor_hplloff_wm
= {
460 .fifo_size
= PINEVIEW_CURSOR_FIFO
,
461 .max_wm
= PINEVIEW_CURSOR_MAX_WM
,
462 .default_wm
= PINEVIEW_CURSOR_DFT_WM
,
463 .guard_size
= PINEVIEW_CURSOR_GUARD_WM
,
464 .cacheline_size
= PINEVIEW_FIFO_LINE_SIZE
,
466 static const struct intel_watermark_params g4x_wm_info
= {
467 .fifo_size
= G4X_FIFO_SIZE
,
468 .max_wm
= G4X_MAX_WM
,
469 .default_wm
= G4X_MAX_WM
,
471 .cacheline_size
= G4X_FIFO_LINE_SIZE
,
473 static const struct intel_watermark_params g4x_cursor_wm_info
= {
474 .fifo_size
= I965_CURSOR_FIFO
,
475 .max_wm
= I965_CURSOR_MAX_WM
,
476 .default_wm
= I965_CURSOR_DFT_WM
,
478 .cacheline_size
= G4X_FIFO_LINE_SIZE
,
480 static const struct intel_watermark_params valleyview_wm_info
= {
481 .fifo_size
= VALLEYVIEW_FIFO_SIZE
,
482 .max_wm
= VALLEYVIEW_MAX_WM
,
483 .default_wm
= VALLEYVIEW_MAX_WM
,
485 .cacheline_size
= G4X_FIFO_LINE_SIZE
,
487 static const struct intel_watermark_params valleyview_cursor_wm_info
= {
488 .fifo_size
= I965_CURSOR_FIFO
,
489 .max_wm
= VALLEYVIEW_CURSOR_MAX_WM
,
490 .default_wm
= I965_CURSOR_DFT_WM
,
492 .cacheline_size
= G4X_FIFO_LINE_SIZE
,
494 static const struct intel_watermark_params i965_cursor_wm_info
= {
495 .fifo_size
= I965_CURSOR_FIFO
,
496 .max_wm
= I965_CURSOR_MAX_WM
,
497 .default_wm
= I965_CURSOR_DFT_WM
,
499 .cacheline_size
= I915_FIFO_LINE_SIZE
,
501 static const struct intel_watermark_params i945_wm_info
= {
502 .fifo_size
= I945_FIFO_SIZE
,
503 .max_wm
= I915_MAX_WM
,
506 .cacheline_size
= I915_FIFO_LINE_SIZE
,
508 static const struct intel_watermark_params i915_wm_info
= {
509 .fifo_size
= I915_FIFO_SIZE
,
510 .max_wm
= I915_MAX_WM
,
513 .cacheline_size
= I915_FIFO_LINE_SIZE
,
515 static const struct intel_watermark_params i830_a_wm_info
= {
516 .fifo_size
= I855GM_FIFO_SIZE
,
517 .max_wm
= I915_MAX_WM
,
520 .cacheline_size
= I830_FIFO_LINE_SIZE
,
522 static const struct intel_watermark_params i830_bc_wm_info
= {
523 .fifo_size
= I855GM_FIFO_SIZE
,
524 .max_wm
= I915_MAX_WM
/2,
527 .cacheline_size
= I830_FIFO_LINE_SIZE
,
529 static const struct intel_watermark_params i845_wm_info
= {
530 .fifo_size
= I830_FIFO_SIZE
,
531 .max_wm
= I915_MAX_WM
,
534 .cacheline_size
= I830_FIFO_LINE_SIZE
,
538 * intel_calculate_wm - calculate watermark level
539 * @clock_in_khz: pixel clock
540 * @wm: chip FIFO params
541 * @pixel_size: display pixel size
542 * @latency_ns: memory latency for the platform
544 * Calculate the watermark level (the level at which the display plane will
545 * start fetching from memory again). Each chip has a different display
546 * FIFO size and allocation, so the caller needs to figure that out and pass
547 * in the correct intel_watermark_params structure.
549 * As the pixel clock runs, the FIFO will be drained at a rate that depends
550 * on the pixel size. When it reaches the watermark level, it'll start
551 * fetching FIFO line sized based chunks from memory until the FIFO fills
552 * past the watermark point. If the FIFO drains completely, a FIFO underrun
553 * will occur, and a display engine hang could result.
555 static unsigned long intel_calculate_wm(unsigned long clock_in_khz
,
556 const struct intel_watermark_params
*wm
,
559 unsigned long latency_ns
)
561 long entries_required
, wm_size
;
564 * Note: we need to make sure we don't overflow for various clock &
566 * clocks go from a few thousand to several hundred thousand.
567 * latency is usually a few thousand
569 entries_required
= ((clock_in_khz
/ 1000) * pixel_size
* latency_ns
) /
571 entries_required
= DIV_ROUND_UP(entries_required
, wm
->cacheline_size
);
573 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required
);
575 wm_size
= fifo_size
- (entries_required
+ wm
->guard_size
);
577 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size
);
579 /* Don't promote wm_size to unsigned... */
580 if (wm_size
> (long)wm
->max_wm
)
581 wm_size
= wm
->max_wm
;
583 wm_size
= wm
->default_wm
;
586 * Bspec seems to indicate that the value shouldn't be lower than
587 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
588 * Lets go for 8 which is the burst size since certain platforms
589 * already use a hardcoded 8 (which is what the spec says should be
598 static struct drm_crtc
*single_enabled_crtc(struct drm_device
*dev
)
600 struct drm_crtc
*crtc
, *enabled
= NULL
;
602 for_each_crtc(dev
, crtc
) {
603 if (intel_crtc_active(crtc
)) {
613 static void pineview_update_wm(struct drm_crtc
*unused_crtc
)
615 struct drm_device
*dev
= unused_crtc
->dev
;
616 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
617 struct drm_crtc
*crtc
;
618 const struct cxsr_latency
*latency
;
622 latency
= intel_get_cxsr_latency(IS_PINEVIEW_G(dev
), dev_priv
->is_ddr3
,
623 dev_priv
->fsb_freq
, dev_priv
->mem_freq
);
625 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
626 intel_set_memory_cxsr(dev_priv
, false);
630 crtc
= single_enabled_crtc(dev
);
632 const struct drm_display_mode
*adjusted_mode
= &to_intel_crtc(crtc
)->config
->base
.adjusted_mode
;
633 int pixel_size
= crtc
->primary
->state
->fb
->bits_per_pixel
/ 8;
634 int clock
= adjusted_mode
->crtc_clock
;
637 wm
= intel_calculate_wm(clock
, &pineview_display_wm
,
638 pineview_display_wm
.fifo_size
,
639 pixel_size
, latency
->display_sr
);
640 reg
= I915_READ(DSPFW1
);
641 reg
&= ~DSPFW_SR_MASK
;
642 reg
|= FW_WM(wm
, SR
);
643 I915_WRITE(DSPFW1
, reg
);
644 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg
);
647 wm
= intel_calculate_wm(clock
, &pineview_cursor_wm
,
648 pineview_display_wm
.fifo_size
,
649 pixel_size
, latency
->cursor_sr
);
650 reg
= I915_READ(DSPFW3
);
651 reg
&= ~DSPFW_CURSOR_SR_MASK
;
652 reg
|= FW_WM(wm
, CURSOR_SR
);
653 I915_WRITE(DSPFW3
, reg
);
655 /* Display HPLL off SR */
656 wm
= intel_calculate_wm(clock
, &pineview_display_hplloff_wm
,
657 pineview_display_hplloff_wm
.fifo_size
,
658 pixel_size
, latency
->display_hpll_disable
);
659 reg
= I915_READ(DSPFW3
);
660 reg
&= ~DSPFW_HPLL_SR_MASK
;
661 reg
|= FW_WM(wm
, HPLL_SR
);
662 I915_WRITE(DSPFW3
, reg
);
664 /* cursor HPLL off SR */
665 wm
= intel_calculate_wm(clock
, &pineview_cursor_hplloff_wm
,
666 pineview_display_hplloff_wm
.fifo_size
,
667 pixel_size
, latency
->cursor_hpll_disable
);
668 reg
= I915_READ(DSPFW3
);
669 reg
&= ~DSPFW_HPLL_CURSOR_MASK
;
670 reg
|= FW_WM(wm
, HPLL_CURSOR
);
671 I915_WRITE(DSPFW3
, reg
);
672 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg
);
674 intel_set_memory_cxsr(dev_priv
, true);
676 intel_set_memory_cxsr(dev_priv
, false);
680 static bool g4x_compute_wm0(struct drm_device
*dev
,
682 const struct intel_watermark_params
*display
,
683 int display_latency_ns
,
684 const struct intel_watermark_params
*cursor
,
685 int cursor_latency_ns
,
689 struct drm_crtc
*crtc
;
690 const struct drm_display_mode
*adjusted_mode
;
691 int htotal
, hdisplay
, clock
, pixel_size
;
692 int line_time_us
, line_count
;
693 int entries
, tlb_miss
;
695 crtc
= intel_get_crtc_for_plane(dev
, plane
);
696 if (!intel_crtc_active(crtc
)) {
697 *cursor_wm
= cursor
->guard_size
;
698 *plane_wm
= display
->guard_size
;
702 adjusted_mode
= &to_intel_crtc(crtc
)->config
->base
.adjusted_mode
;
703 clock
= adjusted_mode
->crtc_clock
;
704 htotal
= adjusted_mode
->crtc_htotal
;
705 hdisplay
= to_intel_crtc(crtc
)->config
->pipe_src_w
;
706 pixel_size
= crtc
->primary
->state
->fb
->bits_per_pixel
/ 8;
708 /* Use the small buffer method to calculate plane watermark */
709 entries
= ((clock
* pixel_size
/ 1000) * display_latency_ns
) / 1000;
710 tlb_miss
= display
->fifo_size
*display
->cacheline_size
- hdisplay
* 8;
713 entries
= DIV_ROUND_UP(entries
, display
->cacheline_size
);
714 *plane_wm
= entries
+ display
->guard_size
;
715 if (*plane_wm
> (int)display
->max_wm
)
716 *plane_wm
= display
->max_wm
;
718 /* Use the large buffer method to calculate cursor watermark */
719 line_time_us
= max(htotal
* 1000 / clock
, 1);
720 line_count
= (cursor_latency_ns
/ line_time_us
+ 1000) / 1000;
721 entries
= line_count
* crtc
->cursor
->state
->crtc_w
* pixel_size
;
722 tlb_miss
= cursor
->fifo_size
*cursor
->cacheline_size
- hdisplay
* 8;
725 entries
= DIV_ROUND_UP(entries
, cursor
->cacheline_size
);
726 *cursor_wm
= entries
+ cursor
->guard_size
;
727 if (*cursor_wm
> (int)cursor
->max_wm
)
728 *cursor_wm
= (int)cursor
->max_wm
;
734 * Check the wm result.
736 * If any calculated watermark values is larger than the maximum value that
737 * can be programmed into the associated watermark register, that watermark
740 static bool g4x_check_srwm(struct drm_device
*dev
,
741 int display_wm
, int cursor_wm
,
742 const struct intel_watermark_params
*display
,
743 const struct intel_watermark_params
*cursor
)
745 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
746 display_wm
, cursor_wm
);
748 if (display_wm
> display
->max_wm
) {
749 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
750 display_wm
, display
->max_wm
);
754 if (cursor_wm
> cursor
->max_wm
) {
755 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
756 cursor_wm
, cursor
->max_wm
);
760 if (!(display_wm
|| cursor_wm
)) {
761 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
768 static bool g4x_compute_srwm(struct drm_device
*dev
,
771 const struct intel_watermark_params
*display
,
772 const struct intel_watermark_params
*cursor
,
773 int *display_wm
, int *cursor_wm
)
775 struct drm_crtc
*crtc
;
776 const struct drm_display_mode
*adjusted_mode
;
777 int hdisplay
, htotal
, pixel_size
, clock
;
778 unsigned long line_time_us
;
779 int line_count
, line_size
;
784 *display_wm
= *cursor_wm
= 0;
788 crtc
= intel_get_crtc_for_plane(dev
, plane
);
789 adjusted_mode
= &to_intel_crtc(crtc
)->config
->base
.adjusted_mode
;
790 clock
= adjusted_mode
->crtc_clock
;
791 htotal
= adjusted_mode
->crtc_htotal
;
792 hdisplay
= to_intel_crtc(crtc
)->config
->pipe_src_w
;
793 pixel_size
= crtc
->primary
->state
->fb
->bits_per_pixel
/ 8;
795 line_time_us
= max(htotal
* 1000 / clock
, 1);
796 line_count
= (latency_ns
/ line_time_us
+ 1000) / 1000;
797 line_size
= hdisplay
* pixel_size
;
799 /* Use the minimum of the small and large buffer method for primary */
800 small
= ((clock
* pixel_size
/ 1000) * latency_ns
) / 1000;
801 large
= line_count
* line_size
;
803 entries
= DIV_ROUND_UP(min(small
, large
), display
->cacheline_size
);
804 *display_wm
= entries
+ display
->guard_size
;
806 /* calculate the self-refresh watermark for display cursor */
807 entries
= line_count
* pixel_size
* crtc
->cursor
->state
->crtc_w
;
808 entries
= DIV_ROUND_UP(entries
, cursor
->cacheline_size
);
809 *cursor_wm
= entries
+ cursor
->guard_size
;
811 return g4x_check_srwm(dev
,
812 *display_wm
, *cursor_wm
,
816 #define FW_WM_VLV(value, plane) \
817 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
819 static void vlv_write_wm_values(struct intel_crtc
*crtc
,
820 const struct vlv_wm_values
*wm
)
822 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
823 enum pipe pipe
= crtc
->pipe
;
825 I915_WRITE(VLV_DDL(pipe
),
826 (wm
->ddl
[pipe
].cursor
<< DDL_CURSOR_SHIFT
) |
827 (wm
->ddl
[pipe
].sprite
[1] << DDL_SPRITE_SHIFT(1)) |
828 (wm
->ddl
[pipe
].sprite
[0] << DDL_SPRITE_SHIFT(0)) |
829 (wm
->ddl
[pipe
].primary
<< DDL_PLANE_SHIFT
));
832 FW_WM(wm
->sr
.plane
, SR
) |
833 FW_WM(wm
->pipe
[PIPE_B
].cursor
, CURSORB
) |
834 FW_WM_VLV(wm
->pipe
[PIPE_B
].primary
, PLANEB
) |
835 FW_WM_VLV(wm
->pipe
[PIPE_A
].primary
, PLANEA
));
837 FW_WM_VLV(wm
->pipe
[PIPE_A
].sprite
[1], SPRITEB
) |
838 FW_WM(wm
->pipe
[PIPE_A
].cursor
, CURSORA
) |
839 FW_WM_VLV(wm
->pipe
[PIPE_A
].sprite
[0], SPRITEA
));
841 FW_WM(wm
->sr
.cursor
, CURSOR_SR
));
843 if (IS_CHERRYVIEW(dev_priv
)) {
844 I915_WRITE(DSPFW7_CHV
,
845 FW_WM_VLV(wm
->pipe
[PIPE_B
].sprite
[1], SPRITED
) |
846 FW_WM_VLV(wm
->pipe
[PIPE_B
].sprite
[0], SPRITEC
));
847 I915_WRITE(DSPFW8_CHV
,
848 FW_WM_VLV(wm
->pipe
[PIPE_C
].sprite
[1], SPRITEF
) |
849 FW_WM_VLV(wm
->pipe
[PIPE_C
].sprite
[0], SPRITEE
));
850 I915_WRITE(DSPFW9_CHV
,
851 FW_WM_VLV(wm
->pipe
[PIPE_C
].primary
, PLANEC
) |
852 FW_WM(wm
->pipe
[PIPE_C
].cursor
, CURSORC
));
854 FW_WM(wm
->sr
.plane
>> 9, SR_HI
) |
855 FW_WM(wm
->pipe
[PIPE_C
].sprite
[1] >> 8, SPRITEF_HI
) |
856 FW_WM(wm
->pipe
[PIPE_C
].sprite
[0] >> 8, SPRITEE_HI
) |
857 FW_WM(wm
->pipe
[PIPE_C
].primary
>> 8, PLANEC_HI
) |
858 FW_WM(wm
->pipe
[PIPE_B
].sprite
[1] >> 8, SPRITED_HI
) |
859 FW_WM(wm
->pipe
[PIPE_B
].sprite
[0] >> 8, SPRITEC_HI
) |
860 FW_WM(wm
->pipe
[PIPE_B
].primary
>> 8, PLANEB_HI
) |
861 FW_WM(wm
->pipe
[PIPE_A
].sprite
[1] >> 8, SPRITEB_HI
) |
862 FW_WM(wm
->pipe
[PIPE_A
].sprite
[0] >> 8, SPRITEA_HI
) |
863 FW_WM(wm
->pipe
[PIPE_A
].primary
>> 8, PLANEA_HI
));
866 FW_WM_VLV(wm
->pipe
[PIPE_B
].sprite
[1], SPRITED
) |
867 FW_WM_VLV(wm
->pipe
[PIPE_B
].sprite
[0], SPRITEC
));
869 FW_WM(wm
->sr
.plane
>> 9, SR_HI
) |
870 FW_WM(wm
->pipe
[PIPE_B
].sprite
[1] >> 8, SPRITED_HI
) |
871 FW_WM(wm
->pipe
[PIPE_B
].sprite
[0] >> 8, SPRITEC_HI
) |
872 FW_WM(wm
->pipe
[PIPE_B
].primary
>> 8, PLANEB_HI
) |
873 FW_WM(wm
->pipe
[PIPE_A
].sprite
[1] >> 8, SPRITEB_HI
) |
874 FW_WM(wm
->pipe
[PIPE_A
].sprite
[0] >> 8, SPRITEA_HI
) |
875 FW_WM(wm
->pipe
[PIPE_A
].primary
>> 8, PLANEA_HI
));
878 /* zero (unused) WM1 watermarks */
879 I915_WRITE(DSPFW4
, 0);
880 I915_WRITE(DSPFW5
, 0);
881 I915_WRITE(DSPFW6
, 0);
882 I915_WRITE(DSPHOWM1
, 0);
884 POSTING_READ(DSPFW1
);
892 VLV_WM_LEVEL_DDR_DVFS
,
895 /* latency must be in 0.1us units. */
896 static unsigned int vlv_wm_method2(unsigned int pixel_rate
,
897 unsigned int pipe_htotal
,
898 unsigned int horiz_pixels
,
899 unsigned int bytes_per_pixel
,
900 unsigned int latency
)
904 ret
= (latency
* pixel_rate
) / (pipe_htotal
* 10000);
905 ret
= (ret
+ 1) * horiz_pixels
* bytes_per_pixel
;
906 ret
= DIV_ROUND_UP(ret
, 64);
911 static void vlv_setup_wm_latency(struct drm_device
*dev
)
913 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
915 /* all latencies in usec */
916 dev_priv
->wm
.pri_latency
[VLV_WM_LEVEL_PM2
] = 3;
918 dev_priv
->wm
.max_level
= VLV_WM_LEVEL_PM2
;
920 if (IS_CHERRYVIEW(dev_priv
)) {
921 dev_priv
->wm
.pri_latency
[VLV_WM_LEVEL_PM5
] = 12;
922 dev_priv
->wm
.pri_latency
[VLV_WM_LEVEL_DDR_DVFS
] = 33;
924 dev_priv
->wm
.max_level
= VLV_WM_LEVEL_DDR_DVFS
;
928 static uint16_t vlv_compute_wm_level(struct intel_plane
*plane
,
929 struct intel_crtc
*crtc
,
930 const struct intel_plane_state
*state
,
933 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
934 int clock
, htotal
, pixel_size
, width
, wm
;
936 if (dev_priv
->wm
.pri_latency
[level
] == 0)
942 pixel_size
= drm_format_plane_cpp(state
->base
.fb
->pixel_format
, 0);
943 clock
= crtc
->config
->base
.adjusted_mode
.crtc_clock
;
944 htotal
= crtc
->config
->base
.adjusted_mode
.crtc_htotal
;
945 width
= crtc
->config
->pipe_src_w
;
946 if (WARN_ON(htotal
== 0))
949 if (plane
->base
.type
== DRM_PLANE_TYPE_CURSOR
) {
951 * FIXME the formula gives values that are
952 * too big for the cursor FIFO, and hence we
953 * would never be able to use cursors. For
954 * now just hardcode the watermark.
958 wm
= vlv_wm_method2(clock
, htotal
, width
, pixel_size
,
959 dev_priv
->wm
.pri_latency
[level
] * 10);
962 return min_t(int, wm
, USHRT_MAX
);
965 static void vlv_compute_fifo(struct intel_crtc
*crtc
)
967 struct drm_device
*dev
= crtc
->base
.dev
;
968 struct vlv_wm_state
*wm_state
= &crtc
->wm_state
;
969 struct intel_plane
*plane
;
970 unsigned int total_rate
= 0;
971 const int fifo_size
= 512 - 1;
972 int fifo_extra
, fifo_left
= fifo_size
;
974 for_each_intel_plane_on_crtc(dev
, crtc
, plane
) {
975 struct intel_plane_state
*state
=
976 to_intel_plane_state(plane
->base
.state
);
978 if (plane
->base
.type
== DRM_PLANE_TYPE_CURSOR
)
981 if (state
->visible
) {
982 wm_state
->num_active_planes
++;
983 total_rate
+= drm_format_plane_cpp(state
->base
.fb
->pixel_format
, 0);
987 for_each_intel_plane_on_crtc(dev
, crtc
, plane
) {
988 struct intel_plane_state
*state
=
989 to_intel_plane_state(plane
->base
.state
);
992 if (plane
->base
.type
== DRM_PLANE_TYPE_CURSOR
) {
993 plane
->wm
.fifo_size
= 63;
997 if (!state
->visible
) {
998 plane
->wm
.fifo_size
= 0;
1002 rate
= drm_format_plane_cpp(state
->base
.fb
->pixel_format
, 0);
1003 plane
->wm
.fifo_size
= fifo_size
* rate
/ total_rate
;
1004 fifo_left
-= plane
->wm
.fifo_size
;
1007 fifo_extra
= DIV_ROUND_UP(fifo_left
, wm_state
->num_active_planes
?: 1);
1009 /* spread the remainder evenly */
1010 for_each_intel_plane_on_crtc(dev
, crtc
, plane
) {
1016 if (plane
->base
.type
== DRM_PLANE_TYPE_CURSOR
)
1019 /* give it all to the first plane if none are active */
1020 if (plane
->wm
.fifo_size
== 0 &&
1021 wm_state
->num_active_planes
)
1024 plane_extra
= min(fifo_extra
, fifo_left
);
1025 plane
->wm
.fifo_size
+= plane_extra
;
1026 fifo_left
-= plane_extra
;
1029 WARN_ON(fifo_left
!= 0);
1032 static void vlv_invert_wms(struct intel_crtc
*crtc
)
1034 struct vlv_wm_state
*wm_state
= &crtc
->wm_state
;
1037 for (level
= 0; level
< wm_state
->num_levels
; level
++) {
1038 struct drm_device
*dev
= crtc
->base
.dev
;
1039 const int sr_fifo_size
= INTEL_INFO(dev
)->num_pipes
* 512 - 1;
1040 struct intel_plane
*plane
;
1042 wm_state
->sr
[level
].plane
= sr_fifo_size
- wm_state
->sr
[level
].plane
;
1043 wm_state
->sr
[level
].cursor
= 63 - wm_state
->sr
[level
].cursor
;
1045 for_each_intel_plane_on_crtc(dev
, crtc
, plane
) {
1046 switch (plane
->base
.type
) {
1048 case DRM_PLANE_TYPE_CURSOR
:
1049 wm_state
->wm
[level
].cursor
= plane
->wm
.fifo_size
-
1050 wm_state
->wm
[level
].cursor
;
1052 case DRM_PLANE_TYPE_PRIMARY
:
1053 wm_state
->wm
[level
].primary
= plane
->wm
.fifo_size
-
1054 wm_state
->wm
[level
].primary
;
1056 case DRM_PLANE_TYPE_OVERLAY
:
1057 sprite
= plane
->plane
;
1058 wm_state
->wm
[level
].sprite
[sprite
] = plane
->wm
.fifo_size
-
1059 wm_state
->wm
[level
].sprite
[sprite
];
1066 static void vlv_compute_wm(struct intel_crtc
*crtc
)
1068 struct drm_device
*dev
= crtc
->base
.dev
;
1069 struct vlv_wm_state
*wm_state
= &crtc
->wm_state
;
1070 struct intel_plane
*plane
;
1071 int sr_fifo_size
= INTEL_INFO(dev
)->num_pipes
* 512 - 1;
1074 memset(wm_state
, 0, sizeof(*wm_state
));
1076 wm_state
->cxsr
= crtc
->pipe
!= PIPE_C
&& crtc
->wm
.cxsr_allowed
;
1077 wm_state
->num_levels
= to_i915(dev
)->wm
.max_level
+ 1;
1079 wm_state
->num_active_planes
= 0;
1081 vlv_compute_fifo(crtc
);
1083 if (wm_state
->num_active_planes
!= 1)
1084 wm_state
->cxsr
= false;
1086 if (wm_state
->cxsr
) {
1087 for (level
= 0; level
< wm_state
->num_levels
; level
++) {
1088 wm_state
->sr
[level
].plane
= sr_fifo_size
;
1089 wm_state
->sr
[level
].cursor
= 63;
1093 for_each_intel_plane_on_crtc(dev
, crtc
, plane
) {
1094 struct intel_plane_state
*state
=
1095 to_intel_plane_state(plane
->base
.state
);
1097 if (!state
->visible
)
1100 /* normal watermarks */
1101 for (level
= 0; level
< wm_state
->num_levels
; level
++) {
1102 int wm
= vlv_compute_wm_level(plane
, crtc
, state
, level
);
1103 int max_wm
= plane
->base
.type
== DRM_PLANE_TYPE_CURSOR
? 63 : 511;
1106 if (WARN_ON(level
== 0 && wm
> max_wm
))
1109 if (wm
> plane
->wm
.fifo_size
)
1112 switch (plane
->base
.type
) {
1114 case DRM_PLANE_TYPE_CURSOR
:
1115 wm_state
->wm
[level
].cursor
= wm
;
1117 case DRM_PLANE_TYPE_PRIMARY
:
1118 wm_state
->wm
[level
].primary
= wm
;
1120 case DRM_PLANE_TYPE_OVERLAY
:
1121 sprite
= plane
->plane
;
1122 wm_state
->wm
[level
].sprite
[sprite
] = wm
;
1127 wm_state
->num_levels
= level
;
1129 if (!wm_state
->cxsr
)
1132 /* maxfifo watermarks */
1133 switch (plane
->base
.type
) {
1135 case DRM_PLANE_TYPE_CURSOR
:
1136 for (level
= 0; level
< wm_state
->num_levels
; level
++)
1137 wm_state
->sr
[level
].cursor
=
1138 wm_state
->sr
[level
].cursor
;
1140 case DRM_PLANE_TYPE_PRIMARY
:
1141 for (level
= 0; level
< wm_state
->num_levels
; level
++)
1142 wm_state
->sr
[level
].plane
=
1143 min(wm_state
->sr
[level
].plane
,
1144 wm_state
->wm
[level
].primary
);
1146 case DRM_PLANE_TYPE_OVERLAY
:
1147 sprite
= plane
->plane
;
1148 for (level
= 0; level
< wm_state
->num_levels
; level
++)
1149 wm_state
->sr
[level
].plane
=
1150 min(wm_state
->sr
[level
].plane
,
1151 wm_state
->wm
[level
].sprite
[sprite
]);
1156 /* clear any (partially) filled invalid levels */
1157 for (level
= wm_state
->num_levels
; level
< to_i915(dev
)->wm
.max_level
+ 1; level
++) {
1158 memset(&wm_state
->wm
[level
], 0, sizeof(wm_state
->wm
[level
]));
1159 memset(&wm_state
->sr
[level
], 0, sizeof(wm_state
->sr
[level
]));
1162 vlv_invert_wms(crtc
);
1165 #define VLV_FIFO(plane, value) \
1166 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1168 static void vlv_pipe_set_fifo_size(struct intel_crtc
*crtc
)
1170 struct drm_device
*dev
= crtc
->base
.dev
;
1171 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1172 struct intel_plane
*plane
;
1173 int sprite0_start
= 0, sprite1_start
= 0, fifo_size
= 0;
1175 for_each_intel_plane_on_crtc(dev
, crtc
, plane
) {
1176 if (plane
->base
.type
== DRM_PLANE_TYPE_CURSOR
) {
1177 WARN_ON(plane
->wm
.fifo_size
!= 63);
1181 if (plane
->base
.type
== DRM_PLANE_TYPE_PRIMARY
)
1182 sprite0_start
= plane
->wm
.fifo_size
;
1183 else if (plane
->plane
== 0)
1184 sprite1_start
= sprite0_start
+ plane
->wm
.fifo_size
;
1186 fifo_size
= sprite1_start
+ plane
->wm
.fifo_size
;
1189 WARN_ON(fifo_size
!= 512 - 1);
1191 DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1192 pipe_name(crtc
->pipe
), sprite0_start
,
1193 sprite1_start
, fifo_size
);
1195 switch (crtc
->pipe
) {
1196 uint32_t dsparb
, dsparb2
, dsparb3
;
1198 dsparb
= I915_READ(DSPARB
);
1199 dsparb2
= I915_READ(DSPARB2
);
1201 dsparb
&= ~(VLV_FIFO(SPRITEA
, 0xff) |
1202 VLV_FIFO(SPRITEB
, 0xff));
1203 dsparb
|= (VLV_FIFO(SPRITEA
, sprite0_start
) |
1204 VLV_FIFO(SPRITEB
, sprite1_start
));
1206 dsparb2
&= ~(VLV_FIFO(SPRITEA_HI
, 0x1) |
1207 VLV_FIFO(SPRITEB_HI
, 0x1));
1208 dsparb2
|= (VLV_FIFO(SPRITEA_HI
, sprite0_start
>> 8) |
1209 VLV_FIFO(SPRITEB_HI
, sprite1_start
>> 8));
1211 I915_WRITE(DSPARB
, dsparb
);
1212 I915_WRITE(DSPARB2
, dsparb2
);
1215 dsparb
= I915_READ(DSPARB
);
1216 dsparb2
= I915_READ(DSPARB2
);
1218 dsparb
&= ~(VLV_FIFO(SPRITEC
, 0xff) |
1219 VLV_FIFO(SPRITED
, 0xff));
1220 dsparb
|= (VLV_FIFO(SPRITEC
, sprite0_start
) |
1221 VLV_FIFO(SPRITED
, sprite1_start
));
1223 dsparb2
&= ~(VLV_FIFO(SPRITEC_HI
, 0xff) |
1224 VLV_FIFO(SPRITED_HI
, 0xff));
1225 dsparb2
|= (VLV_FIFO(SPRITEC_HI
, sprite0_start
>> 8) |
1226 VLV_FIFO(SPRITED_HI
, sprite1_start
>> 8));
1228 I915_WRITE(DSPARB
, dsparb
);
1229 I915_WRITE(DSPARB2
, dsparb2
);
1232 dsparb3
= I915_READ(DSPARB3
);
1233 dsparb2
= I915_READ(DSPARB2
);
1235 dsparb3
&= ~(VLV_FIFO(SPRITEE
, 0xff) |
1236 VLV_FIFO(SPRITEF
, 0xff));
1237 dsparb3
|= (VLV_FIFO(SPRITEE
, sprite0_start
) |
1238 VLV_FIFO(SPRITEF
, sprite1_start
));
1240 dsparb2
&= ~(VLV_FIFO(SPRITEE_HI
, 0xff) |
1241 VLV_FIFO(SPRITEF_HI
, 0xff));
1242 dsparb2
|= (VLV_FIFO(SPRITEE_HI
, sprite0_start
>> 8) |
1243 VLV_FIFO(SPRITEF_HI
, sprite1_start
>> 8));
1245 I915_WRITE(DSPARB3
, dsparb3
);
1246 I915_WRITE(DSPARB2
, dsparb2
);
1255 static void vlv_merge_wm(struct drm_device
*dev
,
1256 struct vlv_wm_values
*wm
)
1258 struct intel_crtc
*crtc
;
1259 int num_active_crtcs
= 0;
1261 wm
->level
= to_i915(dev
)->wm
.max_level
;
1264 for_each_intel_crtc(dev
, crtc
) {
1265 const struct vlv_wm_state
*wm_state
= &crtc
->wm_state
;
1270 if (!wm_state
->cxsr
)
1274 wm
->level
= min_t(int, wm
->level
, wm_state
->num_levels
- 1);
1277 if (num_active_crtcs
!= 1)
1280 if (num_active_crtcs
> 1)
1281 wm
->level
= VLV_WM_LEVEL_PM2
;
1283 for_each_intel_crtc(dev
, crtc
) {
1284 struct vlv_wm_state
*wm_state
= &crtc
->wm_state
;
1285 enum pipe pipe
= crtc
->pipe
;
1290 wm
->pipe
[pipe
] = wm_state
->wm
[wm
->level
];
1292 wm
->sr
= wm_state
->sr
[wm
->level
];
1294 wm
->ddl
[pipe
].primary
= DDL_PRECISION_HIGH
| 2;
1295 wm
->ddl
[pipe
].sprite
[0] = DDL_PRECISION_HIGH
| 2;
1296 wm
->ddl
[pipe
].sprite
[1] = DDL_PRECISION_HIGH
| 2;
1297 wm
->ddl
[pipe
].cursor
= DDL_PRECISION_HIGH
| 2;
1301 static void vlv_update_wm(struct drm_crtc
*crtc
)
1303 struct drm_device
*dev
= crtc
->dev
;
1304 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1305 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1306 enum pipe pipe
= intel_crtc
->pipe
;
1307 struct vlv_wm_values wm
= {};
1309 vlv_compute_wm(intel_crtc
);
1310 vlv_merge_wm(dev
, &wm
);
1312 if (memcmp(&dev_priv
->wm
.vlv
, &wm
, sizeof(wm
)) == 0) {
1313 /* FIXME should be part of crtc atomic commit */
1314 vlv_pipe_set_fifo_size(intel_crtc
);
1318 if (wm
.level
< VLV_WM_LEVEL_DDR_DVFS
&&
1319 dev_priv
->wm
.vlv
.level
>= VLV_WM_LEVEL_DDR_DVFS
)
1320 chv_set_memory_dvfs(dev_priv
, false);
1322 if (wm
.level
< VLV_WM_LEVEL_PM5
&&
1323 dev_priv
->wm
.vlv
.level
>= VLV_WM_LEVEL_PM5
)
1324 chv_set_memory_pm5(dev_priv
, false);
1326 if (!wm
.cxsr
&& dev_priv
->wm
.vlv
.cxsr
)
1327 intel_set_memory_cxsr(dev_priv
, false);
1329 /* FIXME should be part of crtc atomic commit */
1330 vlv_pipe_set_fifo_size(intel_crtc
);
1332 vlv_write_wm_values(intel_crtc
, &wm
);
1334 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1335 "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1336 pipe_name(pipe
), wm
.pipe
[pipe
].primary
, wm
.pipe
[pipe
].cursor
,
1337 wm
.pipe
[pipe
].sprite
[0], wm
.pipe
[pipe
].sprite
[1],
1338 wm
.sr
.plane
, wm
.sr
.cursor
, wm
.level
, wm
.cxsr
);
1340 if (wm
.cxsr
&& !dev_priv
->wm
.vlv
.cxsr
)
1341 intel_set_memory_cxsr(dev_priv
, true);
1343 if (wm
.level
>= VLV_WM_LEVEL_PM5
&&
1344 dev_priv
->wm
.vlv
.level
< VLV_WM_LEVEL_PM5
)
1345 chv_set_memory_pm5(dev_priv
, true);
1347 if (wm
.level
>= VLV_WM_LEVEL_DDR_DVFS
&&
1348 dev_priv
->wm
.vlv
.level
< VLV_WM_LEVEL_DDR_DVFS
)
1349 chv_set_memory_dvfs(dev_priv
, true);
1351 dev_priv
->wm
.vlv
= wm
;
1354 #define single_plane_enabled(mask) is_power_of_2(mask)
1356 static void g4x_update_wm(struct drm_crtc
*crtc
)
1358 struct drm_device
*dev
= crtc
->dev
;
1359 static const int sr_latency_ns
= 12000;
1360 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1361 int planea_wm
, planeb_wm
, cursora_wm
, cursorb_wm
;
1362 int plane_sr
, cursor_sr
;
1363 unsigned int enabled
= 0;
1366 if (g4x_compute_wm0(dev
, PIPE_A
,
1367 &g4x_wm_info
, pessimal_latency_ns
,
1368 &g4x_cursor_wm_info
, pessimal_latency_ns
,
1369 &planea_wm
, &cursora_wm
))
1370 enabled
|= 1 << PIPE_A
;
1372 if (g4x_compute_wm0(dev
, PIPE_B
,
1373 &g4x_wm_info
, pessimal_latency_ns
,
1374 &g4x_cursor_wm_info
, pessimal_latency_ns
,
1375 &planeb_wm
, &cursorb_wm
))
1376 enabled
|= 1 << PIPE_B
;
1378 if (single_plane_enabled(enabled
) &&
1379 g4x_compute_srwm(dev
, ffs(enabled
) - 1,
1382 &g4x_cursor_wm_info
,
1383 &plane_sr
, &cursor_sr
)) {
1384 cxsr_enabled
= true;
1386 cxsr_enabled
= false;
1387 intel_set_memory_cxsr(dev_priv
, false);
1388 plane_sr
= cursor_sr
= 0;
1391 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1392 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1393 planea_wm
, cursora_wm
,
1394 planeb_wm
, cursorb_wm
,
1395 plane_sr
, cursor_sr
);
1398 FW_WM(plane_sr
, SR
) |
1399 FW_WM(cursorb_wm
, CURSORB
) |
1400 FW_WM(planeb_wm
, PLANEB
) |
1401 FW_WM(planea_wm
, PLANEA
));
1403 (I915_READ(DSPFW2
) & ~DSPFW_CURSORA_MASK
) |
1404 FW_WM(cursora_wm
, CURSORA
));
1405 /* HPLL off in SR has some issues on G4x... disable it */
1407 (I915_READ(DSPFW3
) & ~(DSPFW_HPLL_SR_EN
| DSPFW_CURSOR_SR_MASK
)) |
1408 FW_WM(cursor_sr
, CURSOR_SR
));
1411 intel_set_memory_cxsr(dev_priv
, true);
1414 static void i965_update_wm(struct drm_crtc
*unused_crtc
)
1416 struct drm_device
*dev
= unused_crtc
->dev
;
1417 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1418 struct drm_crtc
*crtc
;
1423 /* Calc sr entries for one plane configs */
1424 crtc
= single_enabled_crtc(dev
);
1426 /* self-refresh has much higher latency */
1427 static const int sr_latency_ns
= 12000;
1428 const struct drm_display_mode
*adjusted_mode
= &to_intel_crtc(crtc
)->config
->base
.adjusted_mode
;
1429 int clock
= adjusted_mode
->crtc_clock
;
1430 int htotal
= adjusted_mode
->crtc_htotal
;
1431 int hdisplay
= to_intel_crtc(crtc
)->config
->pipe_src_w
;
1432 int pixel_size
= crtc
->primary
->state
->fb
->bits_per_pixel
/ 8;
1433 unsigned long line_time_us
;
1436 line_time_us
= max(htotal
* 1000 / clock
, 1);
1438 /* Use ns/us then divide to preserve precision */
1439 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
1440 pixel_size
* hdisplay
;
1441 entries
= DIV_ROUND_UP(entries
, I915_FIFO_LINE_SIZE
);
1442 srwm
= I965_FIFO_SIZE
- entries
;
1446 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1449 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
1450 pixel_size
* crtc
->cursor
->state
->crtc_w
;
1451 entries
= DIV_ROUND_UP(entries
,
1452 i965_cursor_wm_info
.cacheline_size
);
1453 cursor_sr
= i965_cursor_wm_info
.fifo_size
-
1454 (entries
+ i965_cursor_wm_info
.guard_size
);
1456 if (cursor_sr
> i965_cursor_wm_info
.max_wm
)
1457 cursor_sr
= i965_cursor_wm_info
.max_wm
;
1459 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1460 "cursor %d\n", srwm
, cursor_sr
);
1462 cxsr_enabled
= true;
1464 cxsr_enabled
= false;
1465 /* Turn off self refresh if both pipes are enabled */
1466 intel_set_memory_cxsr(dev_priv
, false);
1469 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1472 /* 965 has limitations... */
1473 I915_WRITE(DSPFW1
, FW_WM(srwm
, SR
) |
1477 I915_WRITE(DSPFW2
, FW_WM(8, CURSORA
) |
1478 FW_WM(8, PLANEC_OLD
));
1479 /* update cursor SR watermark */
1480 I915_WRITE(DSPFW3
, FW_WM(cursor_sr
, CURSOR_SR
));
1483 intel_set_memory_cxsr(dev_priv
, true);
1488 static void i9xx_update_wm(struct drm_crtc
*unused_crtc
)
1490 struct drm_device
*dev
= unused_crtc
->dev
;
1491 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1492 const struct intel_watermark_params
*wm_info
;
1497 int planea_wm
, planeb_wm
;
1498 struct drm_crtc
*crtc
, *enabled
= NULL
;
1501 wm_info
= &i945_wm_info
;
1502 else if (!IS_GEN2(dev
))
1503 wm_info
= &i915_wm_info
;
1505 wm_info
= &i830_a_wm_info
;
1507 fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 0);
1508 crtc
= intel_get_crtc_for_plane(dev
, 0);
1509 if (intel_crtc_active(crtc
)) {
1510 const struct drm_display_mode
*adjusted_mode
;
1511 int cpp
= crtc
->primary
->state
->fb
->bits_per_pixel
/ 8;
1515 adjusted_mode
= &to_intel_crtc(crtc
)->config
->base
.adjusted_mode
;
1516 planea_wm
= intel_calculate_wm(adjusted_mode
->crtc_clock
,
1517 wm_info
, fifo_size
, cpp
,
1518 pessimal_latency_ns
);
1521 planea_wm
= fifo_size
- wm_info
->guard_size
;
1522 if (planea_wm
> (long)wm_info
->max_wm
)
1523 planea_wm
= wm_info
->max_wm
;
1527 wm_info
= &i830_bc_wm_info
;
1529 fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 1);
1530 crtc
= intel_get_crtc_for_plane(dev
, 1);
1531 if (intel_crtc_active(crtc
)) {
1532 const struct drm_display_mode
*adjusted_mode
;
1533 int cpp
= crtc
->primary
->state
->fb
->bits_per_pixel
/ 8;
1537 adjusted_mode
= &to_intel_crtc(crtc
)->config
->base
.adjusted_mode
;
1538 planeb_wm
= intel_calculate_wm(adjusted_mode
->crtc_clock
,
1539 wm_info
, fifo_size
, cpp
,
1540 pessimal_latency_ns
);
1541 if (enabled
== NULL
)
1546 planeb_wm
= fifo_size
- wm_info
->guard_size
;
1547 if (planeb_wm
> (long)wm_info
->max_wm
)
1548 planeb_wm
= wm_info
->max_wm
;
1551 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm
, planeb_wm
);
1553 if (IS_I915GM(dev
) && enabled
) {
1554 struct drm_i915_gem_object
*obj
;
1556 obj
= intel_fb_obj(enabled
->primary
->state
->fb
);
1558 /* self-refresh seems busted with untiled */
1559 if (obj
->tiling_mode
== I915_TILING_NONE
)
1564 * Overlay gets an aggressive default since video jitter is bad.
1568 /* Play safe and disable self-refresh before adjusting watermarks. */
1569 intel_set_memory_cxsr(dev_priv
, false);
1571 /* Calc sr entries for one plane configs */
1572 if (HAS_FW_BLC(dev
) && enabled
) {
1573 /* self-refresh has much higher latency */
1574 static const int sr_latency_ns
= 6000;
1575 const struct drm_display_mode
*adjusted_mode
= &to_intel_crtc(enabled
)->config
->base
.adjusted_mode
;
1576 int clock
= adjusted_mode
->crtc_clock
;
1577 int htotal
= adjusted_mode
->crtc_htotal
;
1578 int hdisplay
= to_intel_crtc(enabled
)->config
->pipe_src_w
;
1579 int pixel_size
= enabled
->primary
->state
->fb
->bits_per_pixel
/ 8;
1580 unsigned long line_time_us
;
1583 line_time_us
= max(htotal
* 1000 / clock
, 1);
1585 /* Use ns/us then divide to preserve precision */
1586 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
1587 pixel_size
* hdisplay
;
1588 entries
= DIV_ROUND_UP(entries
, wm_info
->cacheline_size
);
1589 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries
);
1590 srwm
= wm_info
->fifo_size
- entries
;
1594 if (IS_I945G(dev
) || IS_I945GM(dev
))
1595 I915_WRITE(FW_BLC_SELF
,
1596 FW_BLC_SELF_FIFO_MASK
| (srwm
& 0xff));
1597 else if (IS_I915GM(dev
))
1598 I915_WRITE(FW_BLC_SELF
, srwm
& 0x3f);
1601 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1602 planea_wm
, planeb_wm
, cwm
, srwm
);
1604 fwater_lo
= ((planeb_wm
& 0x3f) << 16) | (planea_wm
& 0x3f);
1605 fwater_hi
= (cwm
& 0x1f);
1607 /* Set request length to 8 cachelines per fetch */
1608 fwater_lo
= fwater_lo
| (1 << 24) | (1 << 8);
1609 fwater_hi
= fwater_hi
| (1 << 8);
1611 I915_WRITE(FW_BLC
, fwater_lo
);
1612 I915_WRITE(FW_BLC2
, fwater_hi
);
1615 intel_set_memory_cxsr(dev_priv
, true);
1618 static void i845_update_wm(struct drm_crtc
*unused_crtc
)
1620 struct drm_device
*dev
= unused_crtc
->dev
;
1621 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1622 struct drm_crtc
*crtc
;
1623 const struct drm_display_mode
*adjusted_mode
;
1627 crtc
= single_enabled_crtc(dev
);
1631 adjusted_mode
= &to_intel_crtc(crtc
)->config
->base
.adjusted_mode
;
1632 planea_wm
= intel_calculate_wm(adjusted_mode
->crtc_clock
,
1634 dev_priv
->display
.get_fifo_size(dev
, 0),
1635 4, pessimal_latency_ns
);
1636 fwater_lo
= I915_READ(FW_BLC
) & ~0xfff;
1637 fwater_lo
|= (3<<8) | planea_wm
;
1639 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm
);
1641 I915_WRITE(FW_BLC
, fwater_lo
);
1644 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state
*pipe_config
)
1646 uint32_t pixel_rate
;
1648 pixel_rate
= pipe_config
->base
.adjusted_mode
.crtc_clock
;
1650 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1651 * adjust the pixel_rate here. */
1653 if (pipe_config
->pch_pfit
.enabled
) {
1654 uint64_t pipe_w
, pipe_h
, pfit_w
, pfit_h
;
1655 uint32_t pfit_size
= pipe_config
->pch_pfit
.size
;
1657 pipe_w
= pipe_config
->pipe_src_w
;
1658 pipe_h
= pipe_config
->pipe_src_h
;
1660 pfit_w
= (pfit_size
>> 16) & 0xFFFF;
1661 pfit_h
= pfit_size
& 0xFFFF;
1662 if (pipe_w
< pfit_w
)
1664 if (pipe_h
< pfit_h
)
1667 pixel_rate
= div_u64((uint64_t) pixel_rate
* pipe_w
* pipe_h
,
1674 /* latency must be in 0.1us units. */
1675 static uint32_t ilk_wm_method1(uint32_t pixel_rate
, uint8_t bytes_per_pixel
,
1680 if (WARN(latency
== 0, "Latency value missing\n"))
1683 ret
= (uint64_t) pixel_rate
* bytes_per_pixel
* latency
;
1684 ret
= DIV_ROUND_UP_ULL(ret
, 64 * 10000) + 2;
1689 /* latency must be in 0.1us units. */
1690 static uint32_t ilk_wm_method2(uint32_t pixel_rate
, uint32_t pipe_htotal
,
1691 uint32_t horiz_pixels
, uint8_t bytes_per_pixel
,
1696 if (WARN(latency
== 0, "Latency value missing\n"))
1699 ret
= (latency
* pixel_rate
) / (pipe_htotal
* 10000);
1700 ret
= (ret
+ 1) * horiz_pixels
* bytes_per_pixel
;
1701 ret
= DIV_ROUND_UP(ret
, 64) + 2;
1705 static uint32_t ilk_wm_fbc(uint32_t pri_val
, uint32_t horiz_pixels
,
1706 uint8_t bytes_per_pixel
)
1708 return DIV_ROUND_UP(pri_val
* 64, horiz_pixels
* bytes_per_pixel
) + 2;
1711 struct ilk_wm_maximums
{
1719 * For both WM_PIPE and WM_LP.
1720 * mem_value must be in 0.1us units.
1722 static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state
*cstate
,
1723 const struct intel_plane_state
*pstate
,
1727 int bpp
= pstate
->base
.fb
? pstate
->base
.fb
->bits_per_pixel
/ 8 : 0;
1728 uint32_t method1
, method2
;
1730 if (!cstate
->base
.active
|| !pstate
->visible
)
1733 method1
= ilk_wm_method1(ilk_pipe_pixel_rate(cstate
), bpp
, mem_value
);
1738 method2
= ilk_wm_method2(ilk_pipe_pixel_rate(cstate
),
1739 cstate
->base
.adjusted_mode
.crtc_htotal
,
1740 drm_rect_width(&pstate
->dst
),
1744 return min(method1
, method2
);
1748 * For both WM_PIPE and WM_LP.
1749 * mem_value must be in 0.1us units.
1751 static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state
*cstate
,
1752 const struct intel_plane_state
*pstate
,
1755 int bpp
= pstate
->base
.fb
? pstate
->base
.fb
->bits_per_pixel
/ 8 : 0;
1756 uint32_t method1
, method2
;
1758 if (!cstate
->base
.active
|| !pstate
->visible
)
1761 method1
= ilk_wm_method1(ilk_pipe_pixel_rate(cstate
), bpp
, mem_value
);
1762 method2
= ilk_wm_method2(ilk_pipe_pixel_rate(cstate
),
1763 cstate
->base
.adjusted_mode
.crtc_htotal
,
1764 drm_rect_width(&pstate
->dst
),
1767 return min(method1
, method2
);
1771 * For both WM_PIPE and WM_LP.
1772 * mem_value must be in 0.1us units.
1774 static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state
*cstate
,
1775 const struct intel_plane_state
*pstate
,
1778 int bpp
= pstate
->base
.fb
? pstate
->base
.fb
->bits_per_pixel
/ 8 : 0;
1780 if (!cstate
->base
.active
|| !pstate
->visible
)
1783 return ilk_wm_method2(ilk_pipe_pixel_rate(cstate
),
1784 cstate
->base
.adjusted_mode
.crtc_htotal
,
1785 drm_rect_width(&pstate
->dst
),
1790 /* Only for WM_LP. */
1791 static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state
*cstate
,
1792 const struct intel_plane_state
*pstate
,
1795 int bpp
= pstate
->base
.fb
? pstate
->base
.fb
->bits_per_pixel
/ 8 : 0;
1797 if (!cstate
->base
.active
|| !pstate
->visible
)
1800 return ilk_wm_fbc(pri_val
, drm_rect_width(&pstate
->dst
), bpp
);
1803 static unsigned int ilk_display_fifo_size(const struct drm_device
*dev
)
1805 if (INTEL_INFO(dev
)->gen
>= 8)
1807 else if (INTEL_INFO(dev
)->gen
>= 7)
1813 static unsigned int ilk_plane_wm_reg_max(const struct drm_device
*dev
,
1814 int level
, bool is_sprite
)
1816 if (INTEL_INFO(dev
)->gen
>= 8)
1817 /* BDW primary/sprite plane watermarks */
1818 return level
== 0 ? 255 : 2047;
1819 else if (INTEL_INFO(dev
)->gen
>= 7)
1820 /* IVB/HSW primary/sprite plane watermarks */
1821 return level
== 0 ? 127 : 1023;
1822 else if (!is_sprite
)
1823 /* ILK/SNB primary plane watermarks */
1824 return level
== 0 ? 127 : 511;
1826 /* ILK/SNB sprite plane watermarks */
1827 return level
== 0 ? 63 : 255;
1830 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device
*dev
,
1833 if (INTEL_INFO(dev
)->gen
>= 7)
1834 return level
== 0 ? 63 : 255;
1836 return level
== 0 ? 31 : 63;
1839 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device
*dev
)
1841 if (INTEL_INFO(dev
)->gen
>= 8)
1847 /* Calculate the maximum primary/sprite plane watermark */
1848 static unsigned int ilk_plane_wm_max(const struct drm_device
*dev
,
1850 const struct intel_wm_config
*config
,
1851 enum intel_ddb_partitioning ddb_partitioning
,
1854 unsigned int fifo_size
= ilk_display_fifo_size(dev
);
1856 /* if sprites aren't enabled, sprites get nothing */
1857 if (is_sprite
&& !config
->sprites_enabled
)
1860 /* HSW allows LP1+ watermarks even with multiple pipes */
1861 if (level
== 0 || config
->num_pipes_active
> 1) {
1862 fifo_size
/= INTEL_INFO(dev
)->num_pipes
;
1865 * For some reason the non self refresh
1866 * FIFO size is only half of the self
1867 * refresh FIFO size on ILK/SNB.
1869 if (INTEL_INFO(dev
)->gen
<= 6)
1873 if (config
->sprites_enabled
) {
1874 /* level 0 is always calculated with 1:1 split */
1875 if (level
> 0 && ddb_partitioning
== INTEL_DDB_PART_5_6
) {
1884 /* clamp to max that the registers can hold */
1885 return min(fifo_size
, ilk_plane_wm_reg_max(dev
, level
, is_sprite
));
1888 /* Calculate the maximum cursor plane watermark */
1889 static unsigned int ilk_cursor_wm_max(const struct drm_device
*dev
,
1891 const struct intel_wm_config
*config
)
1893 /* HSW LP1+ watermarks w/ multiple pipes */
1894 if (level
> 0 && config
->num_pipes_active
> 1)
1897 /* otherwise just report max that registers can hold */
1898 return ilk_cursor_wm_reg_max(dev
, level
);
1901 static void ilk_compute_wm_maximums(const struct drm_device
*dev
,
1903 const struct intel_wm_config
*config
,
1904 enum intel_ddb_partitioning ddb_partitioning
,
1905 struct ilk_wm_maximums
*max
)
1907 max
->pri
= ilk_plane_wm_max(dev
, level
, config
, ddb_partitioning
, false);
1908 max
->spr
= ilk_plane_wm_max(dev
, level
, config
, ddb_partitioning
, true);
1909 max
->cur
= ilk_cursor_wm_max(dev
, level
, config
);
1910 max
->fbc
= ilk_fbc_wm_reg_max(dev
);
1913 static void ilk_compute_wm_reg_maximums(struct drm_device
*dev
,
1915 struct ilk_wm_maximums
*max
)
1917 max
->pri
= ilk_plane_wm_reg_max(dev
, level
, false);
1918 max
->spr
= ilk_plane_wm_reg_max(dev
, level
, true);
1919 max
->cur
= ilk_cursor_wm_reg_max(dev
, level
);
1920 max
->fbc
= ilk_fbc_wm_reg_max(dev
);
1923 static bool ilk_validate_wm_level(int level
,
1924 const struct ilk_wm_maximums
*max
,
1925 struct intel_wm_level
*result
)
1929 /* already determined to be invalid? */
1930 if (!result
->enable
)
1933 result
->enable
= result
->pri_val
<= max
->pri
&&
1934 result
->spr_val
<= max
->spr
&&
1935 result
->cur_val
<= max
->cur
;
1937 ret
= result
->enable
;
1940 * HACK until we can pre-compute everything,
1941 * and thus fail gracefully if LP0 watermarks
1944 if (level
== 0 && !result
->enable
) {
1945 if (result
->pri_val
> max
->pri
)
1946 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1947 level
, result
->pri_val
, max
->pri
);
1948 if (result
->spr_val
> max
->spr
)
1949 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1950 level
, result
->spr_val
, max
->spr
);
1951 if (result
->cur_val
> max
->cur
)
1952 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1953 level
, result
->cur_val
, max
->cur
);
1955 result
->pri_val
= min_t(uint32_t, result
->pri_val
, max
->pri
);
1956 result
->spr_val
= min_t(uint32_t, result
->spr_val
, max
->spr
);
1957 result
->cur_val
= min_t(uint32_t, result
->cur_val
, max
->cur
);
1958 result
->enable
= true;
1964 static void ilk_compute_wm_level(const struct drm_i915_private
*dev_priv
,
1965 const struct intel_crtc
*intel_crtc
,
1967 struct intel_crtc_state
*cstate
,
1968 struct intel_plane_state
*pristate
,
1969 struct intel_plane_state
*sprstate
,
1970 struct intel_plane_state
*curstate
,
1971 struct intel_wm_level
*result
)
1973 uint16_t pri_latency
= dev_priv
->wm
.pri_latency
[level
];
1974 uint16_t spr_latency
= dev_priv
->wm
.spr_latency
[level
];
1975 uint16_t cur_latency
= dev_priv
->wm
.cur_latency
[level
];
1977 /* WM1+ latency values stored in 0.5us units */
1984 result
->pri_val
= ilk_compute_pri_wm(cstate
, pristate
,
1985 pri_latency
, level
);
1986 result
->spr_val
= ilk_compute_spr_wm(cstate
, sprstate
, spr_latency
);
1987 result
->cur_val
= ilk_compute_cur_wm(cstate
, curstate
, cur_latency
);
1988 result
->fbc_val
= ilk_compute_fbc_wm(cstate
, pristate
, result
->pri_val
);
1989 result
->enable
= true;
1993 hsw_compute_linetime_wm(struct drm_device
*dev
, struct drm_crtc
*crtc
)
1995 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1996 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1997 const struct drm_display_mode
*adjusted_mode
= &intel_crtc
->config
->base
.adjusted_mode
;
1998 u32 linetime
, ips_linetime
;
2000 if (!intel_crtc
->active
)
2003 /* The WM are computed with base on how long it takes to fill a single
2004 * row at the given clock rate, multiplied by 8.
2006 linetime
= DIV_ROUND_CLOSEST(adjusted_mode
->crtc_htotal
* 1000 * 8,
2007 adjusted_mode
->crtc_clock
);
2008 ips_linetime
= DIV_ROUND_CLOSEST(adjusted_mode
->crtc_htotal
* 1000 * 8,
2009 dev_priv
->cdclk_freq
);
2011 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime
) |
2012 PIPE_WM_LINETIME_TIME(linetime
);
2015 static void intel_read_wm_latency(struct drm_device
*dev
, uint16_t wm
[8])
2017 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2022 int level
, max_level
= ilk_wm_max_level(dev
);
2024 /* read the first set of memory latencies[0:3] */
2025 val
= 0; /* data0 to be programmed to 0 for first set */
2026 mutex_lock(&dev_priv
->rps
.hw_lock
);
2027 ret
= sandybridge_pcode_read(dev_priv
,
2028 GEN9_PCODE_READ_MEM_LATENCY
,
2030 mutex_unlock(&dev_priv
->rps
.hw_lock
);
2033 DRM_ERROR("SKL Mailbox read error = %d\n", ret
);
2037 wm
[0] = val
& GEN9_MEM_LATENCY_LEVEL_MASK
;
2038 wm
[1] = (val
>> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT
) &
2039 GEN9_MEM_LATENCY_LEVEL_MASK
;
2040 wm
[2] = (val
>> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT
) &
2041 GEN9_MEM_LATENCY_LEVEL_MASK
;
2042 wm
[3] = (val
>> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT
) &
2043 GEN9_MEM_LATENCY_LEVEL_MASK
;
2045 /* read the second set of memory latencies[4:7] */
2046 val
= 1; /* data0 to be programmed to 1 for second set */
2047 mutex_lock(&dev_priv
->rps
.hw_lock
);
2048 ret
= sandybridge_pcode_read(dev_priv
,
2049 GEN9_PCODE_READ_MEM_LATENCY
,
2051 mutex_unlock(&dev_priv
->rps
.hw_lock
);
2053 DRM_ERROR("SKL Mailbox read error = %d\n", ret
);
2057 wm
[4] = val
& GEN9_MEM_LATENCY_LEVEL_MASK
;
2058 wm
[5] = (val
>> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT
) &
2059 GEN9_MEM_LATENCY_LEVEL_MASK
;
2060 wm
[6] = (val
>> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT
) &
2061 GEN9_MEM_LATENCY_LEVEL_MASK
;
2062 wm
[7] = (val
>> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT
) &
2063 GEN9_MEM_LATENCY_LEVEL_MASK
;
2066 * WaWmMemoryReadLatency:skl
2068 * punit doesn't take into account the read latency so we need
2069 * to add 2us to the various latency levels we retrieve from
2071 * - W0 is a bit special in that it's the only level that
2072 * can't be disabled if we want to have display working, so
2073 * we always add 2us there.
2074 * - For levels >=1, punit returns 0us latency when they are
2075 * disabled, so we respect that and don't add 2us then
2077 * Additionally, if a level n (n > 1) has a 0us latency, all
2078 * levels m (m >= n) need to be disabled. We make sure to
2079 * sanitize the values out of the punit to satisfy this
2083 for (level
= 1; level
<= max_level
; level
++)
2087 for (i
= level
+ 1; i
<= max_level
; i
++)
2092 } else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2093 uint64_t sskpd
= I915_READ64(MCH_SSKPD
);
2095 wm
[0] = (sskpd
>> 56) & 0xFF;
2097 wm
[0] = sskpd
& 0xF;
2098 wm
[1] = (sskpd
>> 4) & 0xFF;
2099 wm
[2] = (sskpd
>> 12) & 0xFF;
2100 wm
[3] = (sskpd
>> 20) & 0x1FF;
2101 wm
[4] = (sskpd
>> 32) & 0x1FF;
2102 } else if (INTEL_INFO(dev
)->gen
>= 6) {
2103 uint32_t sskpd
= I915_READ(MCH_SSKPD
);
2105 wm
[0] = (sskpd
>> SSKPD_WM0_SHIFT
) & SSKPD_WM_MASK
;
2106 wm
[1] = (sskpd
>> SSKPD_WM1_SHIFT
) & SSKPD_WM_MASK
;
2107 wm
[2] = (sskpd
>> SSKPD_WM2_SHIFT
) & SSKPD_WM_MASK
;
2108 wm
[3] = (sskpd
>> SSKPD_WM3_SHIFT
) & SSKPD_WM_MASK
;
2109 } else if (INTEL_INFO(dev
)->gen
>= 5) {
2110 uint32_t mltr
= I915_READ(MLTR_ILK
);
2112 /* ILK primary LP0 latency is 700 ns */
2114 wm
[1] = (mltr
>> MLTR_WM1_SHIFT
) & ILK_SRLT_MASK
;
2115 wm
[2] = (mltr
>> MLTR_WM2_SHIFT
) & ILK_SRLT_MASK
;
2119 static void intel_fixup_spr_wm_latency(struct drm_device
*dev
, uint16_t wm
[5])
2121 /* ILK sprite LP0 latency is 1300 ns */
2122 if (INTEL_INFO(dev
)->gen
== 5)
2126 static void intel_fixup_cur_wm_latency(struct drm_device
*dev
, uint16_t wm
[5])
2128 /* ILK cursor LP0 latency is 1300 ns */
2129 if (INTEL_INFO(dev
)->gen
== 5)
2132 /* WaDoubleCursorLP3Latency:ivb */
2133 if (IS_IVYBRIDGE(dev
))
2137 int ilk_wm_max_level(const struct drm_device
*dev
)
2139 /* how many WM levels are we expecting */
2140 if (INTEL_INFO(dev
)->gen
>= 9)
2142 else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2144 else if (INTEL_INFO(dev
)->gen
>= 6)
2150 static void intel_print_wm_latency(struct drm_device
*dev
,
2152 const uint16_t wm
[8])
2154 int level
, max_level
= ilk_wm_max_level(dev
);
2156 for (level
= 0; level
<= max_level
; level
++) {
2157 unsigned int latency
= wm
[level
];
2160 DRM_ERROR("%s WM%d latency not provided\n",
2166 * - latencies are in us on gen9.
2167 * - before then, WM1+ latency values are in 0.5us units
2174 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2175 name
, level
, wm
[level
],
2176 latency
/ 10, latency
% 10);
2180 static bool ilk_increase_wm_latency(struct drm_i915_private
*dev_priv
,
2181 uint16_t wm
[5], uint16_t min
)
2183 int level
, max_level
= ilk_wm_max_level(dev_priv
->dev
);
2188 wm
[0] = max(wm
[0], min
);
2189 for (level
= 1; level
<= max_level
; level
++)
2190 wm
[level
] = max_t(uint16_t, wm
[level
], DIV_ROUND_UP(min
, 5));
2195 static void snb_wm_latency_quirk(struct drm_device
*dev
)
2197 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2201 * The BIOS provided WM memory latency values are often
2202 * inadequate for high resolution displays. Adjust them.
2204 changed
= ilk_increase_wm_latency(dev_priv
, dev_priv
->wm
.pri_latency
, 12) |
2205 ilk_increase_wm_latency(dev_priv
, dev_priv
->wm
.spr_latency
, 12) |
2206 ilk_increase_wm_latency(dev_priv
, dev_priv
->wm
.cur_latency
, 12);
2211 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2212 intel_print_wm_latency(dev
, "Primary", dev_priv
->wm
.pri_latency
);
2213 intel_print_wm_latency(dev
, "Sprite", dev_priv
->wm
.spr_latency
);
2214 intel_print_wm_latency(dev
, "Cursor", dev_priv
->wm
.cur_latency
);
2217 static void ilk_setup_wm_latency(struct drm_device
*dev
)
2219 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2221 intel_read_wm_latency(dev
, dev_priv
->wm
.pri_latency
);
2223 memcpy(dev_priv
->wm
.spr_latency
, dev_priv
->wm
.pri_latency
,
2224 sizeof(dev_priv
->wm
.pri_latency
));
2225 memcpy(dev_priv
->wm
.cur_latency
, dev_priv
->wm
.pri_latency
,
2226 sizeof(dev_priv
->wm
.pri_latency
));
2228 intel_fixup_spr_wm_latency(dev
, dev_priv
->wm
.spr_latency
);
2229 intel_fixup_cur_wm_latency(dev
, dev_priv
->wm
.cur_latency
);
2231 intel_print_wm_latency(dev
, "Primary", dev_priv
->wm
.pri_latency
);
2232 intel_print_wm_latency(dev
, "Sprite", dev_priv
->wm
.spr_latency
);
2233 intel_print_wm_latency(dev
, "Cursor", dev_priv
->wm
.cur_latency
);
2236 snb_wm_latency_quirk(dev
);
2239 static void skl_setup_wm_latency(struct drm_device
*dev
)
2241 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2243 intel_read_wm_latency(dev
, dev_priv
->wm
.skl_latency
);
2244 intel_print_wm_latency(dev
, "Gen9 Plane", dev_priv
->wm
.skl_latency
);
2247 /* Compute new watermarks for the pipe */
2248 static int ilk_compute_pipe_wm(struct intel_crtc
*intel_crtc
,
2249 struct drm_atomic_state
*state
)
2251 struct intel_pipe_wm
*pipe_wm
;
2252 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2253 const struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2254 struct intel_crtc_state
*cstate
= NULL
;
2255 struct intel_plane
*intel_plane
;
2256 struct drm_plane_state
*ps
;
2257 struct intel_plane_state
*pristate
= NULL
;
2258 struct intel_plane_state
*sprstate
= NULL
;
2259 struct intel_plane_state
*curstate
= NULL
;
2260 int level
, max_level
= ilk_wm_max_level(dev
);
2261 /* LP0 watermark maximums depend on this pipe alone */
2262 struct intel_wm_config config
= {
2263 .num_pipes_active
= 1,
2265 struct ilk_wm_maximums max
;
2267 cstate
= intel_atomic_get_crtc_state(state
, intel_crtc
);
2269 return PTR_ERR(cstate
);
2271 pipe_wm
= &cstate
->wm
.optimal
.ilk
;
2273 for_each_intel_plane_on_crtc(dev
, intel_crtc
, intel_plane
) {
2274 ps
= drm_atomic_get_plane_state(state
,
2275 &intel_plane
->base
);
2279 if (intel_plane
->base
.type
== DRM_PLANE_TYPE_PRIMARY
)
2280 pristate
= to_intel_plane_state(ps
);
2281 else if (intel_plane
->base
.type
== DRM_PLANE_TYPE_OVERLAY
)
2282 sprstate
= to_intel_plane_state(ps
);
2283 else if (intel_plane
->base
.type
== DRM_PLANE_TYPE_CURSOR
)
2284 curstate
= to_intel_plane_state(ps
);
2287 config
.sprites_enabled
= sprstate
->visible
;
2288 config
.sprites_scaled
= sprstate
->visible
&&
2289 (drm_rect_width(&sprstate
->dst
) != drm_rect_width(&sprstate
->src
) >> 16 ||
2290 drm_rect_height(&sprstate
->dst
) != drm_rect_height(&sprstate
->src
) >> 16);
2292 pipe_wm
->pipe_enabled
= cstate
->base
.active
;
2293 pipe_wm
->sprites_enabled
= config
.sprites_enabled
;
2294 pipe_wm
->sprites_scaled
= config
.sprites_scaled
;
2296 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2297 if (INTEL_INFO(dev
)->gen
<= 6 && sprstate
->visible
)
2300 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2301 if (config
.sprites_scaled
)
2304 ilk_compute_wm_level(dev_priv
, intel_crtc
, 0, cstate
,
2305 pristate
, sprstate
, curstate
, &pipe_wm
->wm
[0]);
2307 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2308 pipe_wm
->linetime
= hsw_compute_linetime_wm(dev
,
2311 /* LP0 watermarks always use 1/2 DDB partitioning */
2312 ilk_compute_wm_maximums(dev
, 0, &config
, INTEL_DDB_PART_1_2
, &max
);
2314 /* At least LP0 must be valid */
2315 if (!ilk_validate_wm_level(0, &max
, &pipe_wm
->wm
[0]))
2318 ilk_compute_wm_reg_maximums(dev
, 1, &max
);
2320 for (level
= 1; level
<= max_level
; level
++) {
2321 struct intel_wm_level wm
= {};
2323 ilk_compute_wm_level(dev_priv
, intel_crtc
, level
, cstate
,
2324 pristate
, sprstate
, curstate
, &wm
);
2327 * Disable any watermark level that exceeds the
2328 * register maximums since such watermarks are
2331 if (!ilk_validate_wm_level(level
, &max
, &wm
))
2334 pipe_wm
->wm
[level
] = wm
;
2341 * Merge the watermarks from all active pipes for a specific level.
2343 static void ilk_merge_wm_level(struct drm_device
*dev
,
2345 struct intel_wm_level
*ret_wm
)
2347 const struct intel_crtc
*intel_crtc
;
2349 ret_wm
->enable
= true;
2351 for_each_intel_crtc(dev
, intel_crtc
) {
2352 const struct intel_crtc_state
*cstate
=
2353 to_intel_crtc_state(intel_crtc
->base
.state
);
2354 const struct intel_pipe_wm
*active
= &cstate
->wm
.optimal
.ilk
;
2355 const struct intel_wm_level
*wm
= &active
->wm
[level
];
2357 if (!active
->pipe_enabled
)
2361 * The watermark values may have been used in the past,
2362 * so we must maintain them in the registers for some
2363 * time even if the level is now disabled.
2366 ret_wm
->enable
= false;
2368 ret_wm
->pri_val
= max(ret_wm
->pri_val
, wm
->pri_val
);
2369 ret_wm
->spr_val
= max(ret_wm
->spr_val
, wm
->spr_val
);
2370 ret_wm
->cur_val
= max(ret_wm
->cur_val
, wm
->cur_val
);
2371 ret_wm
->fbc_val
= max(ret_wm
->fbc_val
, wm
->fbc_val
);
2376 * Merge all low power watermarks for all active pipes.
2378 static void ilk_wm_merge(struct drm_device
*dev
,
2379 const struct intel_wm_config
*config
,
2380 const struct ilk_wm_maximums
*max
,
2381 struct intel_pipe_wm
*merged
)
2383 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2384 int level
, max_level
= ilk_wm_max_level(dev
);
2385 int last_enabled_level
= max_level
;
2387 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2388 if ((INTEL_INFO(dev
)->gen
<= 6 || IS_IVYBRIDGE(dev
)) &&
2389 config
->num_pipes_active
> 1)
2392 /* ILK: FBC WM must be disabled always */
2393 merged
->fbc_wm_enabled
= INTEL_INFO(dev
)->gen
>= 6;
2395 /* merge each WM1+ level */
2396 for (level
= 1; level
<= max_level
; level
++) {
2397 struct intel_wm_level
*wm
= &merged
->wm
[level
];
2399 ilk_merge_wm_level(dev
, level
, wm
);
2401 if (level
> last_enabled_level
)
2403 else if (!ilk_validate_wm_level(level
, max
, wm
))
2404 /* make sure all following levels get disabled */
2405 last_enabled_level
= level
- 1;
2408 * The spec says it is preferred to disable
2409 * FBC WMs instead of disabling a WM level.
2411 if (wm
->fbc_val
> max
->fbc
) {
2413 merged
->fbc_wm_enabled
= false;
2418 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2420 * FIXME this is racy. FBC might get enabled later.
2421 * What we should check here is whether FBC can be
2422 * enabled sometime later.
2424 if (IS_GEN5(dev
) && !merged
->fbc_wm_enabled
&&
2425 intel_fbc_enabled(dev_priv
)) {
2426 for (level
= 2; level
<= max_level
; level
++) {
2427 struct intel_wm_level
*wm
= &merged
->wm
[level
];
2434 static int ilk_wm_lp_to_level(int wm_lp
, const struct intel_pipe_wm
*pipe_wm
)
2436 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2437 return wm_lp
+ (wm_lp
>= 2 && pipe_wm
->wm
[4].enable
);
2440 /* The value we need to program into the WM_LPx latency field */
2441 static unsigned int ilk_wm_lp_latency(struct drm_device
*dev
, int level
)
2443 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2445 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2448 return dev_priv
->wm
.pri_latency
[level
];
2451 static void ilk_compute_wm_results(struct drm_device
*dev
,
2452 const struct intel_pipe_wm
*merged
,
2453 enum intel_ddb_partitioning partitioning
,
2454 struct ilk_wm_values
*results
)
2456 struct intel_crtc
*intel_crtc
;
2459 results
->enable_fbc_wm
= merged
->fbc_wm_enabled
;
2460 results
->partitioning
= partitioning
;
2462 /* LP1+ register values */
2463 for (wm_lp
= 1; wm_lp
<= 3; wm_lp
++) {
2464 const struct intel_wm_level
*r
;
2466 level
= ilk_wm_lp_to_level(wm_lp
, merged
);
2468 r
= &merged
->wm
[level
];
2471 * Maintain the watermark values even if the level is
2472 * disabled. Doing otherwise could cause underruns.
2474 results
->wm_lp
[wm_lp
- 1] =
2475 (ilk_wm_lp_latency(dev
, level
) << WM1_LP_LATENCY_SHIFT
) |
2476 (r
->pri_val
<< WM1_LP_SR_SHIFT
) |
2480 results
->wm_lp
[wm_lp
- 1] |= WM1_LP_SR_EN
;
2482 if (INTEL_INFO(dev
)->gen
>= 8)
2483 results
->wm_lp
[wm_lp
- 1] |=
2484 r
->fbc_val
<< WM1_LP_FBC_SHIFT_BDW
;
2486 results
->wm_lp
[wm_lp
- 1] |=
2487 r
->fbc_val
<< WM1_LP_FBC_SHIFT
;
2490 * Always set WM1S_LP_EN when spr_val != 0, even if the
2491 * level is disabled. Doing otherwise could cause underruns.
2493 if (INTEL_INFO(dev
)->gen
<= 6 && r
->spr_val
) {
2494 WARN_ON(wm_lp
!= 1);
2495 results
->wm_lp_spr
[wm_lp
- 1] = WM1S_LP_EN
| r
->spr_val
;
2497 results
->wm_lp_spr
[wm_lp
- 1] = r
->spr_val
;
2500 /* LP0 register values */
2501 for_each_intel_crtc(dev
, intel_crtc
) {
2502 const struct intel_crtc_state
*cstate
=
2503 to_intel_crtc_state(intel_crtc
->base
.state
);
2504 enum pipe pipe
= intel_crtc
->pipe
;
2505 const struct intel_wm_level
*r
= &cstate
->wm
.optimal
.ilk
.wm
[0];
2507 if (WARN_ON(!r
->enable
))
2510 results
->wm_linetime
[pipe
] = cstate
->wm
.optimal
.ilk
.linetime
;
2512 results
->wm_pipe
[pipe
] =
2513 (r
->pri_val
<< WM0_PIPE_PLANE_SHIFT
) |
2514 (r
->spr_val
<< WM0_PIPE_SPRITE_SHIFT
) |
2519 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2520 * case both are at the same level. Prefer r1 in case they're the same. */
2521 static struct intel_pipe_wm
*ilk_find_best_result(struct drm_device
*dev
,
2522 struct intel_pipe_wm
*r1
,
2523 struct intel_pipe_wm
*r2
)
2525 int level
, max_level
= ilk_wm_max_level(dev
);
2526 int level1
= 0, level2
= 0;
2528 for (level
= 1; level
<= max_level
; level
++) {
2529 if (r1
->wm
[level
].enable
)
2531 if (r2
->wm
[level
].enable
)
2535 if (level1
== level2
) {
2536 if (r2
->fbc_wm_enabled
&& !r1
->fbc_wm_enabled
)
2540 } else if (level1
> level2
) {
2547 /* dirty bits used to track which watermarks need changes */
2548 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2549 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2550 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2551 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2552 #define WM_DIRTY_FBC (1 << 24)
2553 #define WM_DIRTY_DDB (1 << 25)
2555 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private
*dev_priv
,
2556 const struct ilk_wm_values
*old
,
2557 const struct ilk_wm_values
*new)
2559 unsigned int dirty
= 0;
2563 for_each_pipe(dev_priv
, pipe
) {
2564 if (old
->wm_linetime
[pipe
] != new->wm_linetime
[pipe
]) {
2565 dirty
|= WM_DIRTY_LINETIME(pipe
);
2566 /* Must disable LP1+ watermarks too */
2567 dirty
|= WM_DIRTY_LP_ALL
;
2570 if (old
->wm_pipe
[pipe
] != new->wm_pipe
[pipe
]) {
2571 dirty
|= WM_DIRTY_PIPE(pipe
);
2572 /* Must disable LP1+ watermarks too */
2573 dirty
|= WM_DIRTY_LP_ALL
;
2577 if (old
->enable_fbc_wm
!= new->enable_fbc_wm
) {
2578 dirty
|= WM_DIRTY_FBC
;
2579 /* Must disable LP1+ watermarks too */
2580 dirty
|= WM_DIRTY_LP_ALL
;
2583 if (old
->partitioning
!= new->partitioning
) {
2584 dirty
|= WM_DIRTY_DDB
;
2585 /* Must disable LP1+ watermarks too */
2586 dirty
|= WM_DIRTY_LP_ALL
;
2589 /* LP1+ watermarks already deemed dirty, no need to continue */
2590 if (dirty
& WM_DIRTY_LP_ALL
)
2593 /* Find the lowest numbered LP1+ watermark in need of an update... */
2594 for (wm_lp
= 1; wm_lp
<= 3; wm_lp
++) {
2595 if (old
->wm_lp
[wm_lp
- 1] != new->wm_lp
[wm_lp
- 1] ||
2596 old
->wm_lp_spr
[wm_lp
- 1] != new->wm_lp_spr
[wm_lp
- 1])
2600 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2601 for (; wm_lp
<= 3; wm_lp
++)
2602 dirty
|= WM_DIRTY_LP(wm_lp
);
2607 static bool _ilk_disable_lp_wm(struct drm_i915_private
*dev_priv
,
2610 struct ilk_wm_values
*previous
= &dev_priv
->wm
.hw
;
2611 bool changed
= false;
2613 if (dirty
& WM_DIRTY_LP(3) && previous
->wm_lp
[2] & WM1_LP_SR_EN
) {
2614 previous
->wm_lp
[2] &= ~WM1_LP_SR_EN
;
2615 I915_WRITE(WM3_LP_ILK
, previous
->wm_lp
[2]);
2618 if (dirty
& WM_DIRTY_LP(2) && previous
->wm_lp
[1] & WM1_LP_SR_EN
) {
2619 previous
->wm_lp
[1] &= ~WM1_LP_SR_EN
;
2620 I915_WRITE(WM2_LP_ILK
, previous
->wm_lp
[1]);
2623 if (dirty
& WM_DIRTY_LP(1) && previous
->wm_lp
[0] & WM1_LP_SR_EN
) {
2624 previous
->wm_lp
[0] &= ~WM1_LP_SR_EN
;
2625 I915_WRITE(WM1_LP_ILK
, previous
->wm_lp
[0]);
2630 * Don't touch WM1S_LP_EN here.
2631 * Doing so could cause underruns.
2638 * The spec says we shouldn't write when we don't need, because every write
2639 * causes WMs to be re-evaluated, expending some power.
2641 static void ilk_write_wm_values(struct drm_i915_private
*dev_priv
,
2642 struct ilk_wm_values
*results
)
2644 struct drm_device
*dev
= dev_priv
->dev
;
2645 struct ilk_wm_values
*previous
= &dev_priv
->wm
.hw
;
2649 dirty
= ilk_compute_wm_dirty(dev_priv
, previous
, results
);
2653 _ilk_disable_lp_wm(dev_priv
, dirty
);
2655 if (dirty
& WM_DIRTY_PIPE(PIPE_A
))
2656 I915_WRITE(WM0_PIPEA_ILK
, results
->wm_pipe
[0]);
2657 if (dirty
& WM_DIRTY_PIPE(PIPE_B
))
2658 I915_WRITE(WM0_PIPEB_ILK
, results
->wm_pipe
[1]);
2659 if (dirty
& WM_DIRTY_PIPE(PIPE_C
))
2660 I915_WRITE(WM0_PIPEC_IVB
, results
->wm_pipe
[2]);
2662 if (dirty
& WM_DIRTY_LINETIME(PIPE_A
))
2663 I915_WRITE(PIPE_WM_LINETIME(PIPE_A
), results
->wm_linetime
[0]);
2664 if (dirty
& WM_DIRTY_LINETIME(PIPE_B
))
2665 I915_WRITE(PIPE_WM_LINETIME(PIPE_B
), results
->wm_linetime
[1]);
2666 if (dirty
& WM_DIRTY_LINETIME(PIPE_C
))
2667 I915_WRITE(PIPE_WM_LINETIME(PIPE_C
), results
->wm_linetime
[2]);
2669 if (dirty
& WM_DIRTY_DDB
) {
2670 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2671 val
= I915_READ(WM_MISC
);
2672 if (results
->partitioning
== INTEL_DDB_PART_1_2
)
2673 val
&= ~WM_MISC_DATA_PARTITION_5_6
;
2675 val
|= WM_MISC_DATA_PARTITION_5_6
;
2676 I915_WRITE(WM_MISC
, val
);
2678 val
= I915_READ(DISP_ARB_CTL2
);
2679 if (results
->partitioning
== INTEL_DDB_PART_1_2
)
2680 val
&= ~DISP_DATA_PARTITION_5_6
;
2682 val
|= DISP_DATA_PARTITION_5_6
;
2683 I915_WRITE(DISP_ARB_CTL2
, val
);
2687 if (dirty
& WM_DIRTY_FBC
) {
2688 val
= I915_READ(DISP_ARB_CTL
);
2689 if (results
->enable_fbc_wm
)
2690 val
&= ~DISP_FBC_WM_DIS
;
2692 val
|= DISP_FBC_WM_DIS
;
2693 I915_WRITE(DISP_ARB_CTL
, val
);
2696 if (dirty
& WM_DIRTY_LP(1) &&
2697 previous
->wm_lp_spr
[0] != results
->wm_lp_spr
[0])
2698 I915_WRITE(WM1S_LP_ILK
, results
->wm_lp_spr
[0]);
2700 if (INTEL_INFO(dev
)->gen
>= 7) {
2701 if (dirty
& WM_DIRTY_LP(2) && previous
->wm_lp_spr
[1] != results
->wm_lp_spr
[1])
2702 I915_WRITE(WM2S_LP_IVB
, results
->wm_lp_spr
[1]);
2703 if (dirty
& WM_DIRTY_LP(3) && previous
->wm_lp_spr
[2] != results
->wm_lp_spr
[2])
2704 I915_WRITE(WM3S_LP_IVB
, results
->wm_lp_spr
[2]);
2707 if (dirty
& WM_DIRTY_LP(1) && previous
->wm_lp
[0] != results
->wm_lp
[0])
2708 I915_WRITE(WM1_LP_ILK
, results
->wm_lp
[0]);
2709 if (dirty
& WM_DIRTY_LP(2) && previous
->wm_lp
[1] != results
->wm_lp
[1])
2710 I915_WRITE(WM2_LP_ILK
, results
->wm_lp
[1]);
2711 if (dirty
& WM_DIRTY_LP(3) && previous
->wm_lp
[2] != results
->wm_lp
[2])
2712 I915_WRITE(WM3_LP_ILK
, results
->wm_lp
[2]);
2714 dev_priv
->wm
.hw
= *results
;
2717 static bool ilk_disable_lp_wm(struct drm_device
*dev
)
2719 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2721 return _ilk_disable_lp_wm(dev_priv
, WM_DIRTY_LP_ALL
);
2725 * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2726 * different active planes.
2729 #define SKL_DDB_SIZE 896 /* in blocks */
2730 #define BXT_DDB_SIZE 512
2733 * Return the index of a plane in the SKL DDB and wm result arrays. Primary
2734 * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
2735 * other universal planes are in indices 1..n. Note that this may leave unused
2736 * indices between the top "sprite" plane and the cursor.
2739 skl_wm_plane_id(const struct intel_plane
*plane
)
2741 switch (plane
->base
.type
) {
2742 case DRM_PLANE_TYPE_PRIMARY
:
2744 case DRM_PLANE_TYPE_CURSOR
:
2745 return PLANE_CURSOR
;
2746 case DRM_PLANE_TYPE_OVERLAY
:
2747 return plane
->plane
+ 1;
2749 MISSING_CASE(plane
->base
.type
);
2750 return plane
->plane
;
2755 skl_ddb_get_pipe_allocation_limits(struct drm_device
*dev
,
2756 const struct intel_crtc_state
*cstate
,
2757 const struct intel_wm_config
*config
,
2758 struct skl_ddb_entry
*alloc
/* out */)
2760 struct drm_crtc
*for_crtc
= cstate
->base
.crtc
;
2761 struct drm_crtc
*crtc
;
2762 unsigned int pipe_size
, ddb_size
;
2763 int nth_active_pipe
;
2765 if (!cstate
->base
.active
) {
2771 if (IS_BROXTON(dev
))
2772 ddb_size
= BXT_DDB_SIZE
;
2774 ddb_size
= SKL_DDB_SIZE
;
2776 ddb_size
-= 4; /* 4 blocks for bypass path allocation */
2778 nth_active_pipe
= 0;
2779 for_each_crtc(dev
, crtc
) {
2780 if (!to_intel_crtc(crtc
)->active
)
2783 if (crtc
== for_crtc
)
2789 pipe_size
= ddb_size
/ config
->num_pipes_active
;
2790 alloc
->start
= nth_active_pipe
* ddb_size
/ config
->num_pipes_active
;
2791 alloc
->end
= alloc
->start
+ pipe_size
;
2794 static unsigned int skl_cursor_allocation(const struct intel_wm_config
*config
)
2796 if (config
->num_pipes_active
== 1)
2802 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry
*entry
, u32 reg
)
2804 entry
->start
= reg
& 0x3ff;
2805 entry
->end
= (reg
>> 16) & 0x3ff;
2810 void skl_ddb_get_hw_state(struct drm_i915_private
*dev_priv
,
2811 struct skl_ddb_allocation
*ddb
/* out */)
2817 for_each_pipe(dev_priv
, pipe
) {
2818 for_each_plane(dev_priv
, pipe
, plane
) {
2819 val
= I915_READ(PLANE_BUF_CFG(pipe
, plane
));
2820 skl_ddb_entry_init_from_hw(&ddb
->plane
[pipe
][plane
],
2824 val
= I915_READ(CUR_BUF_CFG(pipe
));
2825 skl_ddb_entry_init_from_hw(&ddb
->plane
[pipe
][PLANE_CURSOR
],
2831 skl_plane_relative_data_rate(const struct intel_crtc_state
*cstate
,
2832 const struct drm_plane_state
*pstate
,
2835 struct intel_crtc
*intel_crtc
= to_intel_crtc(cstate
->base
.crtc
);
2836 struct drm_framebuffer
*fb
= pstate
->fb
;
2838 /* for planar format */
2839 if (fb
->pixel_format
== DRM_FORMAT_NV12
) {
2840 if (y
) /* y-plane data rate */
2841 return intel_crtc
->config
->pipe_src_w
*
2842 intel_crtc
->config
->pipe_src_h
*
2843 drm_format_plane_cpp(fb
->pixel_format
, 0);
2844 else /* uv-plane data rate */
2845 return (intel_crtc
->config
->pipe_src_w
/2) *
2846 (intel_crtc
->config
->pipe_src_h
/2) *
2847 drm_format_plane_cpp(fb
->pixel_format
, 1);
2850 /* for packed formats */
2851 return intel_crtc
->config
->pipe_src_w
*
2852 intel_crtc
->config
->pipe_src_h
*
2853 drm_format_plane_cpp(fb
->pixel_format
, 0);
2857 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
2858 * a 8192x4096@32bpp framebuffer:
2859 * 3 * 4096 * 8192 * 4 < 2^32
2862 skl_get_total_relative_data_rate(const struct intel_crtc_state
*cstate
)
2864 struct intel_crtc
*intel_crtc
= to_intel_crtc(cstate
->base
.crtc
);
2865 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2866 const struct intel_plane
*intel_plane
;
2867 unsigned int total_data_rate
= 0;
2869 for_each_intel_plane_on_crtc(dev
, intel_crtc
, intel_plane
) {
2870 const struct drm_plane_state
*pstate
= intel_plane
->base
.state
;
2872 if (pstate
->fb
== NULL
)
2875 if (intel_plane
->base
.type
== DRM_PLANE_TYPE_CURSOR
)
2879 total_data_rate
+= skl_plane_relative_data_rate(cstate
,
2883 if (pstate
->fb
->pixel_format
== DRM_FORMAT_NV12
)
2885 total_data_rate
+= skl_plane_relative_data_rate(cstate
,
2890 return total_data_rate
;
2894 skl_allocate_pipe_ddb(struct intel_crtc_state
*cstate
,
2895 struct skl_ddb_allocation
*ddb
/* out */)
2897 struct drm_crtc
*crtc
= cstate
->base
.crtc
;
2898 struct drm_device
*dev
= crtc
->dev
;
2899 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2900 struct intel_wm_config
*config
= &dev_priv
->wm
.config
;
2901 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2902 struct intel_plane
*intel_plane
;
2903 enum pipe pipe
= intel_crtc
->pipe
;
2904 struct skl_ddb_entry
*alloc
= &ddb
->pipe
[pipe
];
2905 uint16_t alloc_size
, start
, cursor_blocks
;
2906 uint16_t minimum
[I915_MAX_PLANES
];
2907 uint16_t y_minimum
[I915_MAX_PLANES
];
2908 unsigned int total_data_rate
;
2910 skl_ddb_get_pipe_allocation_limits(dev
, cstate
, config
, alloc
);
2911 alloc_size
= skl_ddb_entry_size(alloc
);
2912 if (alloc_size
== 0) {
2913 memset(ddb
->plane
[pipe
], 0, sizeof(ddb
->plane
[pipe
]));
2914 memset(&ddb
->plane
[pipe
][PLANE_CURSOR
], 0,
2915 sizeof(ddb
->plane
[pipe
][PLANE_CURSOR
]));
2919 cursor_blocks
= skl_cursor_allocation(config
);
2920 ddb
->plane
[pipe
][PLANE_CURSOR
].start
= alloc
->end
- cursor_blocks
;
2921 ddb
->plane
[pipe
][PLANE_CURSOR
].end
= alloc
->end
;
2923 alloc_size
-= cursor_blocks
;
2924 alloc
->end
-= cursor_blocks
;
2926 /* 1. Allocate the mininum required blocks for each active plane */
2927 for_each_intel_plane_on_crtc(dev
, intel_crtc
, intel_plane
) {
2928 struct drm_plane
*plane
= &intel_plane
->base
;
2929 struct drm_framebuffer
*fb
= plane
->state
->fb
;
2930 int id
= skl_wm_plane_id(intel_plane
);
2934 if (plane
->type
== DRM_PLANE_TYPE_CURSOR
)
2938 alloc_size
-= minimum
[id
];
2939 y_minimum
[id
] = (fb
->pixel_format
== DRM_FORMAT_NV12
) ? 8 : 0;
2940 alloc_size
-= y_minimum
[id
];
2944 * 2. Distribute the remaining space in proportion to the amount of
2945 * data each plane needs to fetch from memory.
2947 * FIXME: we may not allocate every single block here.
2949 total_data_rate
= skl_get_total_relative_data_rate(cstate
);
2951 start
= alloc
->start
;
2952 for_each_intel_plane_on_crtc(dev
, intel_crtc
, intel_plane
) {
2953 struct drm_plane
*plane
= &intel_plane
->base
;
2954 struct drm_plane_state
*pstate
= intel_plane
->base
.state
;
2955 unsigned int data_rate
, y_data_rate
;
2956 uint16_t plane_blocks
, y_plane_blocks
= 0;
2957 int id
= skl_wm_plane_id(intel_plane
);
2959 if (pstate
->fb
== NULL
)
2961 if (plane
->type
== DRM_PLANE_TYPE_CURSOR
)
2964 data_rate
= skl_plane_relative_data_rate(cstate
, pstate
, 0);
2967 * allocation for (packed formats) or (uv-plane part of planar format):
2968 * promote the expression to 64 bits to avoid overflowing, the
2969 * result is < available as data_rate / total_data_rate < 1
2971 plane_blocks
= minimum
[id
];
2972 plane_blocks
+= div_u64((uint64_t)alloc_size
* data_rate
,
2975 ddb
->plane
[pipe
][id
].start
= start
;
2976 ddb
->plane
[pipe
][id
].end
= start
+ plane_blocks
;
2978 start
+= plane_blocks
;
2981 * allocation for y_plane part of planar format:
2983 if (pstate
->fb
->pixel_format
== DRM_FORMAT_NV12
) {
2984 y_data_rate
= skl_plane_relative_data_rate(cstate
,
2987 y_plane_blocks
= y_minimum
[id
];
2988 y_plane_blocks
+= div_u64((uint64_t)alloc_size
* y_data_rate
,
2991 ddb
->y_plane
[pipe
][id
].start
= start
;
2992 ddb
->y_plane
[pipe
][id
].end
= start
+ y_plane_blocks
;
2994 start
+= y_plane_blocks
;
3001 static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state
*config
)
3003 /* TODO: Take into account the scalers once we support them */
3004 return config
->base
.adjusted_mode
.crtc_clock
;
3008 * The max latency should be 257 (max the punit can code is 255 and we add 2us
3009 * for the read latency) and bytes_per_pixel should always be <= 8, so that
3010 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3011 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3013 static uint32_t skl_wm_method1(uint32_t pixel_rate
, uint8_t bytes_per_pixel
,
3016 uint32_t wm_intermediate_val
, ret
;
3021 wm_intermediate_val
= latency
* pixel_rate
* bytes_per_pixel
/ 512;
3022 ret
= DIV_ROUND_UP(wm_intermediate_val
, 1000);
3027 static uint32_t skl_wm_method2(uint32_t pixel_rate
, uint32_t pipe_htotal
,
3028 uint32_t horiz_pixels
, uint8_t bytes_per_pixel
,
3029 uint64_t tiling
, uint32_t latency
)
3032 uint32_t plane_bytes_per_line
, plane_blocks_per_line
;
3033 uint32_t wm_intermediate_val
;
3038 plane_bytes_per_line
= horiz_pixels
* bytes_per_pixel
;
3040 if (tiling
== I915_FORMAT_MOD_Y_TILED
||
3041 tiling
== I915_FORMAT_MOD_Yf_TILED
) {
3042 plane_bytes_per_line
*= 4;
3043 plane_blocks_per_line
= DIV_ROUND_UP(plane_bytes_per_line
, 512);
3044 plane_blocks_per_line
/= 4;
3046 plane_blocks_per_line
= DIV_ROUND_UP(plane_bytes_per_line
, 512);
3049 wm_intermediate_val
= latency
* pixel_rate
;
3050 ret
= DIV_ROUND_UP(wm_intermediate_val
, pipe_htotal
* 1000) *
3051 plane_blocks_per_line
;
3056 static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation
*new_ddb
,
3057 const struct intel_crtc
*intel_crtc
)
3059 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3060 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3061 const struct skl_ddb_allocation
*cur_ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
3062 enum pipe pipe
= intel_crtc
->pipe
;
3064 if (memcmp(new_ddb
->plane
[pipe
], cur_ddb
->plane
[pipe
],
3065 sizeof(new_ddb
->plane
[pipe
])))
3068 if (memcmp(&new_ddb
->plane
[pipe
][PLANE_CURSOR
], &cur_ddb
->plane
[pipe
][PLANE_CURSOR
],
3069 sizeof(new_ddb
->plane
[pipe
][PLANE_CURSOR
])))
3075 static bool skl_compute_plane_wm(const struct drm_i915_private
*dev_priv
,
3076 struct intel_crtc_state
*cstate
,
3077 struct intel_plane
*intel_plane
,
3078 uint16_t ddb_allocation
,
3080 uint16_t *out_blocks
, /* out */
3081 uint8_t *out_lines
/* out */)
3083 struct drm_plane
*plane
= &intel_plane
->base
;
3084 struct drm_framebuffer
*fb
= plane
->state
->fb
;
3085 uint32_t latency
= dev_priv
->wm
.skl_latency
[level
];
3086 uint32_t method1
, method2
;
3087 uint32_t plane_bytes_per_line
, plane_blocks_per_line
;
3088 uint32_t res_blocks
, res_lines
;
3089 uint32_t selected_result
;
3090 uint8_t bytes_per_pixel
;
3092 if (latency
== 0 || !cstate
->base
.active
|| !fb
)
3095 bytes_per_pixel
= drm_format_plane_cpp(fb
->pixel_format
, 0);
3096 method1
= skl_wm_method1(skl_pipe_pixel_rate(cstate
),
3099 method2
= skl_wm_method2(skl_pipe_pixel_rate(cstate
),
3100 cstate
->base
.adjusted_mode
.crtc_htotal
,
3106 plane_bytes_per_line
= cstate
->pipe_src_w
* bytes_per_pixel
;
3107 plane_blocks_per_line
= DIV_ROUND_UP(plane_bytes_per_line
, 512);
3109 if (fb
->modifier
[0] == I915_FORMAT_MOD_Y_TILED
||
3110 fb
->modifier
[0] == I915_FORMAT_MOD_Yf_TILED
) {
3111 uint32_t min_scanlines
= 4;
3112 uint32_t y_tile_minimum
;
3113 if (intel_rotation_90_or_270(plane
->state
->rotation
)) {
3114 int bpp
= (fb
->pixel_format
== DRM_FORMAT_NV12
) ?
3115 drm_format_plane_cpp(fb
->pixel_format
, 1) :
3116 drm_format_plane_cpp(fb
->pixel_format
, 0);
3126 WARN(1, "Unsupported pixel depth for rotation");
3129 y_tile_minimum
= plane_blocks_per_line
* min_scanlines
;
3130 selected_result
= max(method2
, y_tile_minimum
);
3132 if ((ddb_allocation
/ plane_blocks_per_line
) >= 1)
3133 selected_result
= min(method1
, method2
);
3135 selected_result
= method1
;
3138 res_blocks
= selected_result
+ 1;
3139 res_lines
= DIV_ROUND_UP(selected_result
, plane_blocks_per_line
);
3141 if (level
>= 1 && level
<= 7) {
3142 if (fb
->modifier
[0] == I915_FORMAT_MOD_Y_TILED
||
3143 fb
->modifier
[0] == I915_FORMAT_MOD_Yf_TILED
)
3149 if (res_blocks
>= ddb_allocation
|| res_lines
> 31)
3152 *out_blocks
= res_blocks
;
3153 *out_lines
= res_lines
;
3158 static void skl_compute_wm_level(const struct drm_i915_private
*dev_priv
,
3159 struct skl_ddb_allocation
*ddb
,
3160 struct intel_crtc_state
*cstate
,
3162 struct skl_wm_level
*result
)
3164 struct drm_device
*dev
= dev_priv
->dev
;
3165 struct intel_crtc
*intel_crtc
= to_intel_crtc(cstate
->base
.crtc
);
3166 struct intel_plane
*intel_plane
;
3167 uint16_t ddb_blocks
;
3168 enum pipe pipe
= intel_crtc
->pipe
;
3170 for_each_intel_plane_on_crtc(dev
, intel_crtc
, intel_plane
) {
3171 int i
= skl_wm_plane_id(intel_plane
);
3173 ddb_blocks
= skl_ddb_entry_size(&ddb
->plane
[pipe
][i
]);
3175 result
->plane_en
[i
] = skl_compute_plane_wm(dev_priv
,
3180 &result
->plane_res_b
[i
],
3181 &result
->plane_res_l
[i
]);
3186 skl_compute_linetime_wm(struct intel_crtc_state
*cstate
)
3188 if (!cstate
->base
.active
)
3191 if (WARN_ON(skl_pipe_pixel_rate(cstate
) == 0))
3194 return DIV_ROUND_UP(8 * cstate
->base
.adjusted_mode
.crtc_htotal
* 1000,
3195 skl_pipe_pixel_rate(cstate
));
3198 static void skl_compute_transition_wm(struct intel_crtc_state
*cstate
,
3199 struct skl_wm_level
*trans_wm
/* out */)
3201 struct drm_crtc
*crtc
= cstate
->base
.crtc
;
3202 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3203 struct intel_plane
*intel_plane
;
3205 if (!cstate
->base
.active
)
3208 /* Until we know more, just disable transition WMs */
3209 for_each_intel_plane_on_crtc(crtc
->dev
, intel_crtc
, intel_plane
) {
3210 int i
= skl_wm_plane_id(intel_plane
);
3212 trans_wm
->plane_en
[i
] = false;
3216 static void skl_compute_pipe_wm(struct intel_crtc_state
*cstate
,
3217 struct skl_ddb_allocation
*ddb
,
3218 struct skl_pipe_wm
*pipe_wm
)
3220 struct drm_device
*dev
= cstate
->base
.crtc
->dev
;
3221 const struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3222 int level
, max_level
= ilk_wm_max_level(dev
);
3224 for (level
= 0; level
<= max_level
; level
++) {
3225 skl_compute_wm_level(dev_priv
, ddb
, cstate
,
3226 level
, &pipe_wm
->wm
[level
]);
3228 pipe_wm
->linetime
= skl_compute_linetime_wm(cstate
);
3230 skl_compute_transition_wm(cstate
, &pipe_wm
->trans_wm
);
3233 static void skl_compute_wm_results(struct drm_device
*dev
,
3234 struct skl_pipe_wm
*p_wm
,
3235 struct skl_wm_values
*r
,
3236 struct intel_crtc
*intel_crtc
)
3238 int level
, max_level
= ilk_wm_max_level(dev
);
3239 enum pipe pipe
= intel_crtc
->pipe
;
3243 for (level
= 0; level
<= max_level
; level
++) {
3244 for (i
= 0; i
< intel_num_planes(intel_crtc
); i
++) {
3247 temp
|= p_wm
->wm
[level
].plane_res_l
[i
] <<
3248 PLANE_WM_LINES_SHIFT
;
3249 temp
|= p_wm
->wm
[level
].plane_res_b
[i
];
3250 if (p_wm
->wm
[level
].plane_en
[i
])
3251 temp
|= PLANE_WM_EN
;
3253 r
->plane
[pipe
][i
][level
] = temp
;
3258 temp
|= p_wm
->wm
[level
].plane_res_l
[PLANE_CURSOR
] << PLANE_WM_LINES_SHIFT
;
3259 temp
|= p_wm
->wm
[level
].plane_res_b
[PLANE_CURSOR
];
3261 if (p_wm
->wm
[level
].plane_en
[PLANE_CURSOR
])
3262 temp
|= PLANE_WM_EN
;
3264 r
->plane
[pipe
][PLANE_CURSOR
][level
] = temp
;
3268 /* transition WMs */
3269 for (i
= 0; i
< intel_num_planes(intel_crtc
); i
++) {
3271 temp
|= p_wm
->trans_wm
.plane_res_l
[i
] << PLANE_WM_LINES_SHIFT
;
3272 temp
|= p_wm
->trans_wm
.plane_res_b
[i
];
3273 if (p_wm
->trans_wm
.plane_en
[i
])
3274 temp
|= PLANE_WM_EN
;
3276 r
->plane_trans
[pipe
][i
] = temp
;
3280 temp
|= p_wm
->trans_wm
.plane_res_l
[PLANE_CURSOR
] << PLANE_WM_LINES_SHIFT
;
3281 temp
|= p_wm
->trans_wm
.plane_res_b
[PLANE_CURSOR
];
3282 if (p_wm
->trans_wm
.plane_en
[PLANE_CURSOR
])
3283 temp
|= PLANE_WM_EN
;
3285 r
->plane_trans
[pipe
][PLANE_CURSOR
] = temp
;
3287 r
->wm_linetime
[pipe
] = p_wm
->linetime
;
3290 static void skl_ddb_entry_write(struct drm_i915_private
*dev_priv
, uint32_t reg
,
3291 const struct skl_ddb_entry
*entry
)
3294 I915_WRITE(reg
, (entry
->end
- 1) << 16 | entry
->start
);
3299 static void skl_write_wm_values(struct drm_i915_private
*dev_priv
,
3300 const struct skl_wm_values
*new)
3302 struct drm_device
*dev
= dev_priv
->dev
;
3303 struct intel_crtc
*crtc
;
3305 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, base
.head
) {
3306 int i
, level
, max_level
= ilk_wm_max_level(dev
);
3307 enum pipe pipe
= crtc
->pipe
;
3309 if (!new->dirty
[pipe
])
3312 I915_WRITE(PIPE_WM_LINETIME(pipe
), new->wm_linetime
[pipe
]);
3314 for (level
= 0; level
<= max_level
; level
++) {
3315 for (i
= 0; i
< intel_num_planes(crtc
); i
++)
3316 I915_WRITE(PLANE_WM(pipe
, i
, level
),
3317 new->plane
[pipe
][i
][level
]);
3318 I915_WRITE(CUR_WM(pipe
, level
),
3319 new->plane
[pipe
][PLANE_CURSOR
][level
]);
3321 for (i
= 0; i
< intel_num_planes(crtc
); i
++)
3322 I915_WRITE(PLANE_WM_TRANS(pipe
, i
),
3323 new->plane_trans
[pipe
][i
]);
3324 I915_WRITE(CUR_WM_TRANS(pipe
),
3325 new->plane_trans
[pipe
][PLANE_CURSOR
]);
3327 for (i
= 0; i
< intel_num_planes(crtc
); i
++) {
3328 skl_ddb_entry_write(dev_priv
,
3329 PLANE_BUF_CFG(pipe
, i
),
3330 &new->ddb
.plane
[pipe
][i
]);
3331 skl_ddb_entry_write(dev_priv
,
3332 PLANE_NV12_BUF_CFG(pipe
, i
),
3333 &new->ddb
.y_plane
[pipe
][i
]);
3336 skl_ddb_entry_write(dev_priv
, CUR_BUF_CFG(pipe
),
3337 &new->ddb
.plane
[pipe
][PLANE_CURSOR
]);
3342 * When setting up a new DDB allocation arrangement, we need to correctly
3343 * sequence the times at which the new allocations for the pipes are taken into
3344 * account or we'll have pipes fetching from space previously allocated to
3347 * Roughly the sequence looks like:
3348 * 1. re-allocate the pipe(s) with the allocation being reduced and not
3349 * overlapping with a previous light-up pipe (another way to put it is:
3350 * pipes with their new allocation strickly included into their old ones).
3351 * 2. re-allocate the other pipes that get their allocation reduced
3352 * 3. allocate the pipes having their allocation increased
3354 * Steps 1. and 2. are here to take care of the following case:
3355 * - Initially DDB looks like this:
3358 * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
3362 * We need to sequence the re-allocation: C, B, A (and not B, C, A).
3366 skl_wm_flush_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int pass
)
3370 DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe
), pass
);
3372 for_each_plane(dev_priv
, pipe
, plane
) {
3373 I915_WRITE(PLANE_SURF(pipe
, plane
),
3374 I915_READ(PLANE_SURF(pipe
, plane
)));
3376 I915_WRITE(CURBASE(pipe
), I915_READ(CURBASE(pipe
)));
3380 skl_ddb_allocation_included(const struct skl_ddb_allocation
*old
,
3381 const struct skl_ddb_allocation
*new,
3384 uint16_t old_size
, new_size
;
3386 old_size
= skl_ddb_entry_size(&old
->pipe
[pipe
]);
3387 new_size
= skl_ddb_entry_size(&new->pipe
[pipe
]);
3389 return old_size
!= new_size
&&
3390 new->pipe
[pipe
].start
>= old
->pipe
[pipe
].start
&&
3391 new->pipe
[pipe
].end
<= old
->pipe
[pipe
].end
;
3394 static void skl_flush_wm_values(struct drm_i915_private
*dev_priv
,
3395 struct skl_wm_values
*new_values
)
3397 struct drm_device
*dev
= dev_priv
->dev
;
3398 struct skl_ddb_allocation
*cur_ddb
, *new_ddb
;
3399 bool reallocated
[I915_MAX_PIPES
] = {};
3400 struct intel_crtc
*crtc
;
3403 new_ddb
= &new_values
->ddb
;
3404 cur_ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
3407 * First pass: flush the pipes with the new allocation contained into
3410 * We'll wait for the vblank on those pipes to ensure we can safely
3411 * re-allocate the freed space without this pipe fetching from it.
3413 for_each_intel_crtc(dev
, crtc
) {
3419 if (!skl_ddb_allocation_included(cur_ddb
, new_ddb
, pipe
))
3422 skl_wm_flush_pipe(dev_priv
, pipe
, 1);
3423 intel_wait_for_vblank(dev
, pipe
);
3425 reallocated
[pipe
] = true;
3430 * Second pass: flush the pipes that are having their allocation
3431 * reduced, but overlapping with a previous allocation.
3433 * Here as well we need to wait for the vblank to make sure the freed
3434 * space is not used anymore.
3436 for_each_intel_crtc(dev
, crtc
) {
3442 if (reallocated
[pipe
])
3445 if (skl_ddb_entry_size(&new_ddb
->pipe
[pipe
]) <
3446 skl_ddb_entry_size(&cur_ddb
->pipe
[pipe
])) {
3447 skl_wm_flush_pipe(dev_priv
, pipe
, 2);
3448 intel_wait_for_vblank(dev
, pipe
);
3449 reallocated
[pipe
] = true;
3454 * Third pass: flush the pipes that got more space allocated.
3456 * We don't need to actively wait for the update here, next vblank
3457 * will just get more DDB space with the correct WM values.
3459 for_each_intel_crtc(dev
, crtc
) {
3466 * At this point, only the pipes more space than before are
3467 * left to re-allocate.
3469 if (reallocated
[pipe
])
3472 skl_wm_flush_pipe(dev_priv
, pipe
, 3);
3476 static bool skl_update_pipe_wm(struct drm_crtc
*crtc
,
3477 struct skl_ddb_allocation
*ddb
, /* out */
3478 struct skl_pipe_wm
*pipe_wm
/* out */)
3480 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3481 struct intel_crtc_state
*cstate
= to_intel_crtc_state(crtc
->state
);
3483 skl_allocate_pipe_ddb(cstate
, ddb
);
3484 skl_compute_pipe_wm(cstate
, ddb
, pipe_wm
);
3486 if (!memcmp(&intel_crtc
->wm
.active
.skl
, pipe_wm
, sizeof(*pipe_wm
)))
3489 intel_crtc
->wm
.active
.skl
= *pipe_wm
;
3494 static void skl_update_other_pipe_wm(struct drm_device
*dev
,
3495 struct drm_crtc
*crtc
,
3496 struct skl_wm_values
*r
)
3498 struct intel_crtc
*intel_crtc
;
3499 struct intel_crtc
*this_crtc
= to_intel_crtc(crtc
);
3502 * If the WM update hasn't changed the allocation for this_crtc (the
3503 * crtc we are currently computing the new WM values for), other
3504 * enabled crtcs will keep the same allocation and we don't need to
3505 * recompute anything for them.
3507 if (!skl_ddb_allocation_changed(&r
->ddb
, this_crtc
))
3511 * Otherwise, because of this_crtc being freshly enabled/disabled, the
3512 * other active pipes need new DDB allocation and WM values.
3514 list_for_each_entry(intel_crtc
, &dev
->mode_config
.crtc_list
,
3516 struct skl_pipe_wm pipe_wm
= {};
3519 if (this_crtc
->pipe
== intel_crtc
->pipe
)
3522 if (!intel_crtc
->active
)
3525 wm_changed
= skl_update_pipe_wm(&intel_crtc
->base
,
3529 * If we end up re-computing the other pipe WM values, it's
3530 * because it was really needed, so we expect the WM values to
3533 WARN_ON(!wm_changed
);
3535 skl_compute_wm_results(dev
, &pipe_wm
, r
, intel_crtc
);
3536 r
->dirty
[intel_crtc
->pipe
] = true;
3540 static void skl_clear_wm(struct skl_wm_values
*watermarks
, enum pipe pipe
)
3542 watermarks
->wm_linetime
[pipe
] = 0;
3543 memset(watermarks
->plane
[pipe
], 0,
3544 sizeof(uint32_t) * 8 * I915_MAX_PLANES
);
3545 memset(watermarks
->plane_trans
[pipe
],
3546 0, sizeof(uint32_t) * I915_MAX_PLANES
);
3547 watermarks
->plane_trans
[pipe
][PLANE_CURSOR
] = 0;
3549 /* Clear ddb entries for pipe */
3550 memset(&watermarks
->ddb
.pipe
[pipe
], 0, sizeof(struct skl_ddb_entry
));
3551 memset(&watermarks
->ddb
.plane
[pipe
], 0,
3552 sizeof(struct skl_ddb_entry
) * I915_MAX_PLANES
);
3553 memset(&watermarks
->ddb
.y_plane
[pipe
], 0,
3554 sizeof(struct skl_ddb_entry
) * I915_MAX_PLANES
);
3555 memset(&watermarks
->ddb
.plane
[pipe
][PLANE_CURSOR
], 0,
3556 sizeof(struct skl_ddb_entry
));
3560 static void skl_update_wm(struct drm_crtc
*crtc
)
3562 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3563 struct drm_device
*dev
= crtc
->dev
;
3564 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3565 struct skl_wm_values
*results
= &dev_priv
->wm
.skl_results
;
3566 struct intel_crtc_state
*cstate
= to_intel_crtc_state(crtc
->state
);
3567 struct skl_pipe_wm
*pipe_wm
= &cstate
->wm
.optimal
.skl
;
3570 /* Clear all dirty flags */
3571 memset(results
->dirty
, 0, sizeof(bool) * I915_MAX_PIPES
);
3573 skl_clear_wm(results
, intel_crtc
->pipe
);
3575 if (!skl_update_pipe_wm(crtc
, &results
->ddb
, pipe_wm
))
3578 skl_compute_wm_results(dev
, pipe_wm
, results
, intel_crtc
);
3579 results
->dirty
[intel_crtc
->pipe
] = true;
3581 skl_update_other_pipe_wm(dev
, crtc
, results
);
3582 skl_write_wm_values(dev_priv
, results
);
3583 skl_flush_wm_values(dev_priv
, results
);
3585 /* store the new configuration */
3586 dev_priv
->wm
.skl_hw
= *results
;
3589 static void ilk_program_watermarks(struct drm_i915_private
*dev_priv
)
3591 struct drm_device
*dev
= dev_priv
->dev
;
3592 struct intel_pipe_wm lp_wm_1_2
= {}, lp_wm_5_6
= {}, *best_lp_wm
;
3593 struct ilk_wm_maximums max
;
3594 struct intel_wm_config
*config
= &dev_priv
->wm
.config
;
3595 struct ilk_wm_values results
= {};
3596 enum intel_ddb_partitioning partitioning
;
3598 ilk_compute_wm_maximums(dev
, 1, config
, INTEL_DDB_PART_1_2
, &max
);
3599 ilk_wm_merge(dev
, config
, &max
, &lp_wm_1_2
);
3601 /* 5/6 split only in single pipe config on IVB+ */
3602 if (INTEL_INFO(dev
)->gen
>= 7 &&
3603 config
->num_pipes_active
== 1 && config
->sprites_enabled
) {
3604 ilk_compute_wm_maximums(dev
, 1, config
, INTEL_DDB_PART_5_6
, &max
);
3605 ilk_wm_merge(dev
, config
, &max
, &lp_wm_5_6
);
3607 best_lp_wm
= ilk_find_best_result(dev
, &lp_wm_1_2
, &lp_wm_5_6
);
3609 best_lp_wm
= &lp_wm_1_2
;
3612 partitioning
= (best_lp_wm
== &lp_wm_1_2
) ?
3613 INTEL_DDB_PART_1_2
: INTEL_DDB_PART_5_6
;
3615 ilk_compute_wm_results(dev
, best_lp_wm
, partitioning
, &results
);
3617 ilk_write_wm_values(dev_priv
, &results
);
3620 static void ilk_update_wm(struct drm_crtc
*crtc
)
3622 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
3623 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3624 struct intel_crtc_state
*cstate
= to_intel_crtc_state(crtc
->state
);
3626 WARN_ON(cstate
->base
.active
!= intel_crtc
->active
);
3629 * IVB workaround: must disable low power watermarks for at least
3630 * one frame before enabling scaling. LP watermarks can be re-enabled
3631 * when scaling is disabled.
3633 * WaCxSRDisabledForSpriteScaling:ivb
3635 if (cstate
->disable_lp_wm
) {
3636 ilk_disable_lp_wm(crtc
->dev
);
3637 intel_wait_for_vblank(crtc
->dev
, intel_crtc
->pipe
);
3640 intel_crtc
->wm
.active
.ilk
= cstate
->wm
.optimal
.ilk
;
3642 ilk_program_watermarks(dev_priv
);
3645 static void skl_pipe_wm_active_state(uint32_t val
,
3646 struct skl_pipe_wm
*active
,
3652 bool is_enabled
= (val
& PLANE_WM_EN
) != 0;
3656 active
->wm
[level
].plane_en
[i
] = is_enabled
;
3657 active
->wm
[level
].plane_res_b
[i
] =
3658 val
& PLANE_WM_BLOCKS_MASK
;
3659 active
->wm
[level
].plane_res_l
[i
] =
3660 (val
>> PLANE_WM_LINES_SHIFT
) &
3661 PLANE_WM_LINES_MASK
;
3663 active
->wm
[level
].plane_en
[PLANE_CURSOR
] = is_enabled
;
3664 active
->wm
[level
].plane_res_b
[PLANE_CURSOR
] =
3665 val
& PLANE_WM_BLOCKS_MASK
;
3666 active
->wm
[level
].plane_res_l
[PLANE_CURSOR
] =
3667 (val
>> PLANE_WM_LINES_SHIFT
) &
3668 PLANE_WM_LINES_MASK
;
3672 active
->trans_wm
.plane_en
[i
] = is_enabled
;
3673 active
->trans_wm
.plane_res_b
[i
] =
3674 val
& PLANE_WM_BLOCKS_MASK
;
3675 active
->trans_wm
.plane_res_l
[i
] =
3676 (val
>> PLANE_WM_LINES_SHIFT
) &
3677 PLANE_WM_LINES_MASK
;
3679 active
->trans_wm
.plane_en
[PLANE_CURSOR
] = is_enabled
;
3680 active
->trans_wm
.plane_res_b
[PLANE_CURSOR
] =
3681 val
& PLANE_WM_BLOCKS_MASK
;
3682 active
->trans_wm
.plane_res_l
[PLANE_CURSOR
] =
3683 (val
>> PLANE_WM_LINES_SHIFT
) &
3684 PLANE_WM_LINES_MASK
;
3689 static void skl_pipe_wm_get_hw_state(struct drm_crtc
*crtc
)
3691 struct drm_device
*dev
= crtc
->dev
;
3692 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3693 struct skl_wm_values
*hw
= &dev_priv
->wm
.skl_hw
;
3694 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3695 struct intel_crtc_state
*cstate
= to_intel_crtc_state(crtc
->state
);
3696 struct skl_pipe_wm
*active
= &cstate
->wm
.optimal
.skl
;
3697 enum pipe pipe
= intel_crtc
->pipe
;
3698 int level
, i
, max_level
;
3701 max_level
= ilk_wm_max_level(dev
);
3703 hw
->wm_linetime
[pipe
] = I915_READ(PIPE_WM_LINETIME(pipe
));
3705 for (level
= 0; level
<= max_level
; level
++) {
3706 for (i
= 0; i
< intel_num_planes(intel_crtc
); i
++)
3707 hw
->plane
[pipe
][i
][level
] =
3708 I915_READ(PLANE_WM(pipe
, i
, level
));
3709 hw
->plane
[pipe
][PLANE_CURSOR
][level
] = I915_READ(CUR_WM(pipe
, level
));
3712 for (i
= 0; i
< intel_num_planes(intel_crtc
); i
++)
3713 hw
->plane_trans
[pipe
][i
] = I915_READ(PLANE_WM_TRANS(pipe
, i
));
3714 hw
->plane_trans
[pipe
][PLANE_CURSOR
] = I915_READ(CUR_WM_TRANS(pipe
));
3716 if (!intel_crtc
->active
)
3719 hw
->dirty
[pipe
] = true;
3721 active
->linetime
= hw
->wm_linetime
[pipe
];
3723 for (level
= 0; level
<= max_level
; level
++) {
3724 for (i
= 0; i
< intel_num_planes(intel_crtc
); i
++) {
3725 temp
= hw
->plane
[pipe
][i
][level
];
3726 skl_pipe_wm_active_state(temp
, active
, false,
3729 temp
= hw
->plane
[pipe
][PLANE_CURSOR
][level
];
3730 skl_pipe_wm_active_state(temp
, active
, false, true, i
, level
);
3733 for (i
= 0; i
< intel_num_planes(intel_crtc
); i
++) {
3734 temp
= hw
->plane_trans
[pipe
][i
];
3735 skl_pipe_wm_active_state(temp
, active
, true, false, i
, 0);
3738 temp
= hw
->plane_trans
[pipe
][PLANE_CURSOR
];
3739 skl_pipe_wm_active_state(temp
, active
, true, true, i
, 0);
3741 intel_crtc
->wm
.active
.skl
= *active
;
3744 void skl_wm_get_hw_state(struct drm_device
*dev
)
3746 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3747 struct skl_ddb_allocation
*ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
3748 struct drm_crtc
*crtc
;
3750 skl_ddb_get_hw_state(dev_priv
, ddb
);
3751 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
)
3752 skl_pipe_wm_get_hw_state(crtc
);
3755 static void ilk_pipe_wm_get_hw_state(struct drm_crtc
*crtc
)
3757 struct drm_device
*dev
= crtc
->dev
;
3758 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3759 struct ilk_wm_values
*hw
= &dev_priv
->wm
.hw
;
3760 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3761 struct intel_crtc_state
*cstate
= to_intel_crtc_state(crtc
->state
);
3762 struct intel_pipe_wm
*active
= &cstate
->wm
.optimal
.ilk
;
3763 enum pipe pipe
= intel_crtc
->pipe
;
3764 static const unsigned int wm0_pipe_reg
[] = {
3765 [PIPE_A
] = WM0_PIPEA_ILK
,
3766 [PIPE_B
] = WM0_PIPEB_ILK
,
3767 [PIPE_C
] = WM0_PIPEC_IVB
,
3770 hw
->wm_pipe
[pipe
] = I915_READ(wm0_pipe_reg
[pipe
]);
3771 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
3772 hw
->wm_linetime
[pipe
] = I915_READ(PIPE_WM_LINETIME(pipe
));
3774 active
->pipe_enabled
= intel_crtc
->active
;
3776 if (active
->pipe_enabled
) {
3777 u32 tmp
= hw
->wm_pipe
[pipe
];
3780 * For active pipes LP0 watermark is marked as
3781 * enabled, and LP1+ watermaks as disabled since
3782 * we can't really reverse compute them in case
3783 * multiple pipes are active.
3785 active
->wm
[0].enable
= true;
3786 active
->wm
[0].pri_val
= (tmp
& WM0_PIPE_PLANE_MASK
) >> WM0_PIPE_PLANE_SHIFT
;
3787 active
->wm
[0].spr_val
= (tmp
& WM0_PIPE_SPRITE_MASK
) >> WM0_PIPE_SPRITE_SHIFT
;
3788 active
->wm
[0].cur_val
= tmp
& WM0_PIPE_CURSOR_MASK
;
3789 active
->linetime
= hw
->wm_linetime
[pipe
];
3791 int level
, max_level
= ilk_wm_max_level(dev
);
3794 * For inactive pipes, all watermark levels
3795 * should be marked as enabled but zeroed,
3796 * which is what we'd compute them to.
3798 for (level
= 0; level
<= max_level
; level
++)
3799 active
->wm
[level
].enable
= true;
3802 intel_crtc
->wm
.active
.ilk
= *active
;
3805 #define _FW_WM(value, plane) \
3806 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
3807 #define _FW_WM_VLV(value, plane) \
3808 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
3810 static void vlv_read_wm_values(struct drm_i915_private
*dev_priv
,
3811 struct vlv_wm_values
*wm
)
3816 for_each_pipe(dev_priv
, pipe
) {
3817 tmp
= I915_READ(VLV_DDL(pipe
));
3819 wm
->ddl
[pipe
].primary
=
3820 (tmp
>> DDL_PLANE_SHIFT
) & (DDL_PRECISION_HIGH
| DRAIN_LATENCY_MASK
);
3821 wm
->ddl
[pipe
].cursor
=
3822 (tmp
>> DDL_CURSOR_SHIFT
) & (DDL_PRECISION_HIGH
| DRAIN_LATENCY_MASK
);
3823 wm
->ddl
[pipe
].sprite
[0] =
3824 (tmp
>> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH
| DRAIN_LATENCY_MASK
);
3825 wm
->ddl
[pipe
].sprite
[1] =
3826 (tmp
>> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH
| DRAIN_LATENCY_MASK
);
3829 tmp
= I915_READ(DSPFW1
);
3830 wm
->sr
.plane
= _FW_WM(tmp
, SR
);
3831 wm
->pipe
[PIPE_B
].cursor
= _FW_WM(tmp
, CURSORB
);
3832 wm
->pipe
[PIPE_B
].primary
= _FW_WM_VLV(tmp
, PLANEB
);
3833 wm
->pipe
[PIPE_A
].primary
= _FW_WM_VLV(tmp
, PLANEA
);
3835 tmp
= I915_READ(DSPFW2
);
3836 wm
->pipe
[PIPE_A
].sprite
[1] = _FW_WM_VLV(tmp
, SPRITEB
);
3837 wm
->pipe
[PIPE_A
].cursor
= _FW_WM(tmp
, CURSORA
);
3838 wm
->pipe
[PIPE_A
].sprite
[0] = _FW_WM_VLV(tmp
, SPRITEA
);
3840 tmp
= I915_READ(DSPFW3
);
3841 wm
->sr
.cursor
= _FW_WM(tmp
, CURSOR_SR
);
3843 if (IS_CHERRYVIEW(dev_priv
)) {
3844 tmp
= I915_READ(DSPFW7_CHV
);
3845 wm
->pipe
[PIPE_B
].sprite
[1] = _FW_WM_VLV(tmp
, SPRITED
);
3846 wm
->pipe
[PIPE_B
].sprite
[0] = _FW_WM_VLV(tmp
, SPRITEC
);
3848 tmp
= I915_READ(DSPFW8_CHV
);
3849 wm
->pipe
[PIPE_C
].sprite
[1] = _FW_WM_VLV(tmp
, SPRITEF
);
3850 wm
->pipe
[PIPE_C
].sprite
[0] = _FW_WM_VLV(tmp
, SPRITEE
);
3852 tmp
= I915_READ(DSPFW9_CHV
);
3853 wm
->pipe
[PIPE_C
].primary
= _FW_WM_VLV(tmp
, PLANEC
);
3854 wm
->pipe
[PIPE_C
].cursor
= _FW_WM(tmp
, CURSORC
);
3856 tmp
= I915_READ(DSPHOWM
);
3857 wm
->sr
.plane
|= _FW_WM(tmp
, SR_HI
) << 9;
3858 wm
->pipe
[PIPE_C
].sprite
[1] |= _FW_WM(tmp
, SPRITEF_HI
) << 8;
3859 wm
->pipe
[PIPE_C
].sprite
[0] |= _FW_WM(tmp
, SPRITEE_HI
) << 8;
3860 wm
->pipe
[PIPE_C
].primary
|= _FW_WM(tmp
, PLANEC_HI
) << 8;
3861 wm
->pipe
[PIPE_B
].sprite
[1] |= _FW_WM(tmp
, SPRITED_HI
) << 8;
3862 wm
->pipe
[PIPE_B
].sprite
[0] |= _FW_WM(tmp
, SPRITEC_HI
) << 8;
3863 wm
->pipe
[PIPE_B
].primary
|= _FW_WM(tmp
, PLANEB_HI
) << 8;
3864 wm
->pipe
[PIPE_A
].sprite
[1] |= _FW_WM(tmp
, SPRITEB_HI
) << 8;
3865 wm
->pipe
[PIPE_A
].sprite
[0] |= _FW_WM(tmp
, SPRITEA_HI
) << 8;
3866 wm
->pipe
[PIPE_A
].primary
|= _FW_WM(tmp
, PLANEA_HI
) << 8;
3868 tmp
= I915_READ(DSPFW7
);
3869 wm
->pipe
[PIPE_B
].sprite
[1] = _FW_WM_VLV(tmp
, SPRITED
);
3870 wm
->pipe
[PIPE_B
].sprite
[0] = _FW_WM_VLV(tmp
, SPRITEC
);
3872 tmp
= I915_READ(DSPHOWM
);
3873 wm
->sr
.plane
|= _FW_WM(tmp
, SR_HI
) << 9;
3874 wm
->pipe
[PIPE_B
].sprite
[1] |= _FW_WM(tmp
, SPRITED_HI
) << 8;
3875 wm
->pipe
[PIPE_B
].sprite
[0] |= _FW_WM(tmp
, SPRITEC_HI
) << 8;
3876 wm
->pipe
[PIPE_B
].primary
|= _FW_WM(tmp
, PLANEB_HI
) << 8;
3877 wm
->pipe
[PIPE_A
].sprite
[1] |= _FW_WM(tmp
, SPRITEB_HI
) << 8;
3878 wm
->pipe
[PIPE_A
].sprite
[0] |= _FW_WM(tmp
, SPRITEA_HI
) << 8;
3879 wm
->pipe
[PIPE_A
].primary
|= _FW_WM(tmp
, PLANEA_HI
) << 8;
3886 void vlv_wm_get_hw_state(struct drm_device
*dev
)
3888 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3889 struct vlv_wm_values
*wm
= &dev_priv
->wm
.vlv
;
3890 struct intel_plane
*plane
;
3894 vlv_read_wm_values(dev_priv
, wm
);
3896 for_each_intel_plane(dev
, plane
) {
3897 switch (plane
->base
.type
) {
3899 case DRM_PLANE_TYPE_CURSOR
:
3900 plane
->wm
.fifo_size
= 63;
3902 case DRM_PLANE_TYPE_PRIMARY
:
3903 plane
->wm
.fifo_size
= vlv_get_fifo_size(dev
, plane
->pipe
, 0);
3905 case DRM_PLANE_TYPE_OVERLAY
:
3906 sprite
= plane
->plane
;
3907 plane
->wm
.fifo_size
= vlv_get_fifo_size(dev
, plane
->pipe
, sprite
+ 1);
3912 wm
->cxsr
= I915_READ(FW_BLC_SELF_VLV
) & FW_CSPWRDWNEN
;
3913 wm
->level
= VLV_WM_LEVEL_PM2
;
3915 if (IS_CHERRYVIEW(dev_priv
)) {
3916 mutex_lock(&dev_priv
->rps
.hw_lock
);
3918 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
3919 if (val
& DSP_MAXFIFO_PM5_ENABLE
)
3920 wm
->level
= VLV_WM_LEVEL_PM5
;
3923 * If DDR DVFS is disabled in the BIOS, Punit
3924 * will never ack the request. So if that happens
3925 * assume we don't have to enable/disable DDR DVFS
3926 * dynamically. To test that just set the REQ_ACK
3927 * bit to poke the Punit, but don't change the
3928 * HIGH/LOW bits so that we don't actually change
3929 * the current state.
3931 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DDR_SETUP2
);
3932 val
|= FORCE_DDR_FREQ_REQ_ACK
;
3933 vlv_punit_write(dev_priv
, PUNIT_REG_DDR_SETUP2
, val
);
3935 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DDR_SETUP2
) &
3936 FORCE_DDR_FREQ_REQ_ACK
) == 0, 3)) {
3937 DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
3938 "assuming DDR DVFS is disabled\n");
3939 dev_priv
->wm
.max_level
= VLV_WM_LEVEL_PM5
;
3941 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DDR_SETUP2
);
3942 if ((val
& FORCE_DDR_HIGH_FREQ
) == 0)
3943 wm
->level
= VLV_WM_LEVEL_DDR_DVFS
;
3946 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3949 for_each_pipe(dev_priv
, pipe
)
3950 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
3951 pipe_name(pipe
), wm
->pipe
[pipe
].primary
, wm
->pipe
[pipe
].cursor
,
3952 wm
->pipe
[pipe
].sprite
[0], wm
->pipe
[pipe
].sprite
[1]);
3954 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
3955 wm
->sr
.plane
, wm
->sr
.cursor
, wm
->level
, wm
->cxsr
);
3958 void ilk_wm_get_hw_state(struct drm_device
*dev
)
3960 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3961 struct ilk_wm_values
*hw
= &dev_priv
->wm
.hw
;
3962 struct drm_crtc
*crtc
;
3964 for_each_crtc(dev
, crtc
)
3965 ilk_pipe_wm_get_hw_state(crtc
);
3967 hw
->wm_lp
[0] = I915_READ(WM1_LP_ILK
);
3968 hw
->wm_lp
[1] = I915_READ(WM2_LP_ILK
);
3969 hw
->wm_lp
[2] = I915_READ(WM3_LP_ILK
);
3971 hw
->wm_lp_spr
[0] = I915_READ(WM1S_LP_ILK
);
3972 if (INTEL_INFO(dev
)->gen
>= 7) {
3973 hw
->wm_lp_spr
[1] = I915_READ(WM2S_LP_IVB
);
3974 hw
->wm_lp_spr
[2] = I915_READ(WM3S_LP_IVB
);
3977 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
3978 hw
->partitioning
= (I915_READ(WM_MISC
) & WM_MISC_DATA_PARTITION_5_6
) ?
3979 INTEL_DDB_PART_5_6
: INTEL_DDB_PART_1_2
;
3980 else if (IS_IVYBRIDGE(dev
))
3981 hw
->partitioning
= (I915_READ(DISP_ARB_CTL2
) & DISP_DATA_PARTITION_5_6
) ?
3982 INTEL_DDB_PART_5_6
: INTEL_DDB_PART_1_2
;
3985 !(I915_READ(DISP_ARB_CTL
) & DISP_FBC_WM_DIS
);
3989 * intel_update_watermarks - update FIFO watermark values based on current modes
3991 * Calculate watermark values for the various WM regs based on current mode
3992 * and plane configuration.
3994 * There are several cases to deal with here:
3995 * - normal (i.e. non-self-refresh)
3996 * - self-refresh (SR) mode
3997 * - lines are large relative to FIFO size (buffer can hold up to 2)
3998 * - lines are small relative to FIFO size (buffer can hold more than 2
3999 * lines), so need to account for TLB latency
4001 * The normal calculation is:
4002 * watermark = dotclock * bytes per pixel * latency
4003 * where latency is platform & configuration dependent (we assume pessimal
4006 * The SR calculation is:
4007 * watermark = (trunc(latency/line time)+1) * surface width *
4010 * line time = htotal / dotclock
4011 * surface width = hdisplay for normal plane and 64 for cursor
4012 * and latency is assumed to be high, as above.
4014 * The final value programmed to the register should always be rounded up,
4015 * and include an extra 2 entries to account for clock crossings.
4017 * We don't use the sprite, so we can ignore that. And on Crestline we have
4018 * to set the non-SR watermarks to 8.
4020 void intel_update_watermarks(struct drm_crtc
*crtc
)
4022 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
4024 if (dev_priv
->display
.update_wm
)
4025 dev_priv
->display
.update_wm(crtc
);
4029 * Lock protecting IPS related data structures
4031 DEFINE_SPINLOCK(mchdev_lock
);
4033 /* Global for IPS driver to get at the current i915 device. Protected by
4035 static struct drm_i915_private
*i915_mch_dev
;
4037 bool ironlake_set_drps(struct drm_device
*dev
, u8 val
)
4039 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4042 assert_spin_locked(&mchdev_lock
);
4044 rgvswctl
= I915_READ16(MEMSWCTL
);
4045 if (rgvswctl
& MEMCTL_CMD_STS
) {
4046 DRM_DEBUG("gpu busy, RCS change rejected\n");
4047 return false; /* still busy with another command */
4050 rgvswctl
= (MEMCTL_CMD_CHFREQ
<< MEMCTL_CMD_SHIFT
) |
4051 (val
<< MEMCTL_FREQ_SHIFT
) | MEMCTL_SFCAVM
;
4052 I915_WRITE16(MEMSWCTL
, rgvswctl
);
4053 POSTING_READ16(MEMSWCTL
);
4055 rgvswctl
|= MEMCTL_CMD_STS
;
4056 I915_WRITE16(MEMSWCTL
, rgvswctl
);
4061 static void ironlake_enable_drps(struct drm_device
*dev
)
4063 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4064 u32 rgvmodectl
= I915_READ(MEMMODECTL
);
4065 u8 fmax
, fmin
, fstart
, vstart
;
4067 spin_lock_irq(&mchdev_lock
);
4069 /* Enable temp reporting */
4070 I915_WRITE16(PMMISC
, I915_READ(PMMISC
) | MCPPCE_EN
);
4071 I915_WRITE16(TSC1
, I915_READ(TSC1
) | TSE
);
4073 /* 100ms RC evaluation intervals */
4074 I915_WRITE(RCUPEI
, 100000);
4075 I915_WRITE(RCDNEI
, 100000);
4077 /* Set max/min thresholds to 90ms and 80ms respectively */
4078 I915_WRITE(RCBMAXAVG
, 90000);
4079 I915_WRITE(RCBMINAVG
, 80000);
4081 I915_WRITE(MEMIHYST
, 1);
4083 /* Set up min, max, and cur for interrupt handling */
4084 fmax
= (rgvmodectl
& MEMMODE_FMAX_MASK
) >> MEMMODE_FMAX_SHIFT
;
4085 fmin
= (rgvmodectl
& MEMMODE_FMIN_MASK
);
4086 fstart
= (rgvmodectl
& MEMMODE_FSTART_MASK
) >>
4087 MEMMODE_FSTART_SHIFT
;
4089 vstart
= (I915_READ(PXVFREQ(fstart
)) & PXVFREQ_PX_MASK
) >>
4092 dev_priv
->ips
.fmax
= fmax
; /* IPS callback will increase this */
4093 dev_priv
->ips
.fstart
= fstart
;
4095 dev_priv
->ips
.max_delay
= fstart
;
4096 dev_priv
->ips
.min_delay
= fmin
;
4097 dev_priv
->ips
.cur_delay
= fstart
;
4099 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4100 fmax
, fmin
, fstart
);
4102 I915_WRITE(MEMINTREN
, MEMINT_CX_SUPR_EN
| MEMINT_EVAL_CHG_EN
);
4105 * Interrupts will be enabled in ironlake_irq_postinstall
4108 I915_WRITE(VIDSTART
, vstart
);
4109 POSTING_READ(VIDSTART
);
4111 rgvmodectl
|= MEMMODE_SWMODE_EN
;
4112 I915_WRITE(MEMMODECTL
, rgvmodectl
);
4114 if (wait_for_atomic((I915_READ(MEMSWCTL
) & MEMCTL_CMD_STS
) == 0, 10))
4115 DRM_ERROR("stuck trying to change perf mode\n");
4118 ironlake_set_drps(dev
, fstart
);
4120 dev_priv
->ips
.last_count1
= I915_READ(DMIEC
) +
4121 I915_READ(DDREC
) + I915_READ(CSIEC
);
4122 dev_priv
->ips
.last_time1
= jiffies_to_msecs(jiffies
);
4123 dev_priv
->ips
.last_count2
= I915_READ(GFXEC
);
4124 dev_priv
->ips
.last_time2
= ktime_get_raw_ns();
4126 spin_unlock_irq(&mchdev_lock
);
4129 static void ironlake_disable_drps(struct drm_device
*dev
)
4131 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4134 spin_lock_irq(&mchdev_lock
);
4136 rgvswctl
= I915_READ16(MEMSWCTL
);
4138 /* Ack interrupts, disable EFC interrupt */
4139 I915_WRITE(MEMINTREN
, I915_READ(MEMINTREN
) & ~MEMINT_EVAL_CHG_EN
);
4140 I915_WRITE(MEMINTRSTS
, MEMINT_EVAL_CHG
);
4141 I915_WRITE(DEIER
, I915_READ(DEIER
) & ~DE_PCU_EVENT
);
4142 I915_WRITE(DEIIR
, DE_PCU_EVENT
);
4143 I915_WRITE(DEIMR
, I915_READ(DEIMR
) | DE_PCU_EVENT
);
4145 /* Go back to the starting frequency */
4146 ironlake_set_drps(dev
, dev_priv
->ips
.fstart
);
4148 rgvswctl
|= MEMCTL_CMD_STS
;
4149 I915_WRITE(MEMSWCTL
, rgvswctl
);
4152 spin_unlock_irq(&mchdev_lock
);
4155 /* There's a funny hw issue where the hw returns all 0 when reading from
4156 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4157 * ourselves, instead of doing a rmw cycle (which might result in us clearing
4158 * all limits and the gpu stuck at whatever frequency it is at atm).
4160 static u32
intel_rps_limits(struct drm_i915_private
*dev_priv
, u8 val
)
4164 /* Only set the down limit when we've reached the lowest level to avoid
4165 * getting more interrupts, otherwise leave this clear. This prevents a
4166 * race in the hw when coming out of rc6: There's a tiny window where
4167 * the hw runs at the minimal clock before selecting the desired
4168 * frequency, if the down threshold expires in that window we will not
4169 * receive a down interrupt. */
4170 if (IS_GEN9(dev_priv
->dev
)) {
4171 limits
= (dev_priv
->rps
.max_freq_softlimit
) << 23;
4172 if (val
<= dev_priv
->rps
.min_freq_softlimit
)
4173 limits
|= (dev_priv
->rps
.min_freq_softlimit
) << 14;
4175 limits
= dev_priv
->rps
.max_freq_softlimit
<< 24;
4176 if (val
<= dev_priv
->rps
.min_freq_softlimit
)
4177 limits
|= dev_priv
->rps
.min_freq_softlimit
<< 16;
4183 static void gen6_set_rps_thresholds(struct drm_i915_private
*dev_priv
, u8 val
)
4186 u32 threshold_up
= 0, threshold_down
= 0; /* in % */
4187 u32 ei_up
= 0, ei_down
= 0;
4189 new_power
= dev_priv
->rps
.power
;
4190 switch (dev_priv
->rps
.power
) {
4192 if (val
> dev_priv
->rps
.efficient_freq
+ 1 && val
> dev_priv
->rps
.cur_freq
)
4193 new_power
= BETWEEN
;
4197 if (val
<= dev_priv
->rps
.efficient_freq
&& val
< dev_priv
->rps
.cur_freq
)
4198 new_power
= LOW_POWER
;
4199 else if (val
>= dev_priv
->rps
.rp0_freq
&& val
> dev_priv
->rps
.cur_freq
)
4200 new_power
= HIGH_POWER
;
4204 if (val
< (dev_priv
->rps
.rp1_freq
+ dev_priv
->rps
.rp0_freq
) >> 1 && val
< dev_priv
->rps
.cur_freq
)
4205 new_power
= BETWEEN
;
4208 /* Max/min bins are special */
4209 if (val
<= dev_priv
->rps
.min_freq_softlimit
)
4210 new_power
= LOW_POWER
;
4211 if (val
>= dev_priv
->rps
.max_freq_softlimit
)
4212 new_power
= HIGH_POWER
;
4213 if (new_power
== dev_priv
->rps
.power
)
4216 /* Note the units here are not exactly 1us, but 1280ns. */
4217 switch (new_power
) {
4219 /* Upclock if more than 95% busy over 16ms */
4223 /* Downclock if less than 85% busy over 32ms */
4225 threshold_down
= 85;
4229 /* Upclock if more than 90% busy over 13ms */
4233 /* Downclock if less than 75% busy over 32ms */
4235 threshold_down
= 75;
4239 /* Upclock if more than 85% busy over 10ms */
4243 /* Downclock if less than 60% busy over 32ms */
4245 threshold_down
= 60;
4249 I915_WRITE(GEN6_RP_UP_EI
,
4250 GT_INTERVAL_FROM_US(dev_priv
, ei_up
));
4251 I915_WRITE(GEN6_RP_UP_THRESHOLD
,
4252 GT_INTERVAL_FROM_US(dev_priv
, (ei_up
* threshold_up
/ 100)));
4254 I915_WRITE(GEN6_RP_DOWN_EI
,
4255 GT_INTERVAL_FROM_US(dev_priv
, ei_down
));
4256 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
,
4257 GT_INTERVAL_FROM_US(dev_priv
, (ei_down
* threshold_down
/ 100)));
4259 I915_WRITE(GEN6_RP_CONTROL
,
4260 GEN6_RP_MEDIA_TURBO
|
4261 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
4262 GEN6_RP_MEDIA_IS_GFX
|
4264 GEN6_RP_UP_BUSY_AVG
|
4265 GEN6_RP_DOWN_IDLE_AVG
);
4267 dev_priv
->rps
.power
= new_power
;
4268 dev_priv
->rps
.up_threshold
= threshold_up
;
4269 dev_priv
->rps
.down_threshold
= threshold_down
;
4270 dev_priv
->rps
.last_adj
= 0;
4273 static u32
gen6_rps_pm_mask(struct drm_i915_private
*dev_priv
, u8 val
)
4277 if (val
> dev_priv
->rps
.min_freq_softlimit
)
4278 mask
|= GEN6_PM_RP_DOWN_EI_EXPIRED
| GEN6_PM_RP_DOWN_THRESHOLD
| GEN6_PM_RP_DOWN_TIMEOUT
;
4279 if (val
< dev_priv
->rps
.max_freq_softlimit
)
4280 mask
|= GEN6_PM_RP_UP_EI_EXPIRED
| GEN6_PM_RP_UP_THRESHOLD
;
4282 mask
&= dev_priv
->pm_rps_events
;
4284 return gen6_sanitize_rps_pm_mask(dev_priv
, ~mask
);
4287 /* gen6_set_rps is called to update the frequency request, but should also be
4288 * called when the range (min_delay and max_delay) is modified so that we can
4289 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
4290 static void gen6_set_rps(struct drm_device
*dev
, u8 val
)
4292 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4294 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4295 if (IS_BXT_REVID(dev
, 0, BXT_REVID_A1
))
4298 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
4299 WARN_ON(val
> dev_priv
->rps
.max_freq
);
4300 WARN_ON(val
< dev_priv
->rps
.min_freq
);
4302 /* min/max delay may still have been modified so be sure to
4303 * write the limits value.
4305 if (val
!= dev_priv
->rps
.cur_freq
) {
4306 gen6_set_rps_thresholds(dev_priv
, val
);
4309 I915_WRITE(GEN6_RPNSWREQ
,
4310 GEN9_FREQUENCY(val
));
4311 else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
4312 I915_WRITE(GEN6_RPNSWREQ
,
4313 HSW_FREQUENCY(val
));
4315 I915_WRITE(GEN6_RPNSWREQ
,
4316 GEN6_FREQUENCY(val
) |
4318 GEN6_AGGRESSIVE_TURBO
);
4321 /* Make sure we continue to get interrupts
4322 * until we hit the minimum or maximum frequencies.
4324 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS
, intel_rps_limits(dev_priv
, val
));
4325 I915_WRITE(GEN6_PMINTRMSK
, gen6_rps_pm_mask(dev_priv
, val
));
4327 POSTING_READ(GEN6_RPNSWREQ
);
4329 dev_priv
->rps
.cur_freq
= val
;
4330 trace_intel_gpu_freq_change(val
* 50);
4333 static void valleyview_set_rps(struct drm_device
*dev
, u8 val
)
4335 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4337 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
4338 WARN_ON(val
> dev_priv
->rps
.max_freq
);
4339 WARN_ON(val
< dev_priv
->rps
.min_freq
);
4341 if (WARN_ONCE(IS_CHERRYVIEW(dev
) && (val
& 1),
4342 "Odd GPU freq value\n"))
4345 I915_WRITE(GEN6_PMINTRMSK
, gen6_rps_pm_mask(dev_priv
, val
));
4347 if (val
!= dev_priv
->rps
.cur_freq
) {
4348 vlv_punit_write(dev_priv
, PUNIT_REG_GPU_FREQ_REQ
, val
);
4349 if (!IS_CHERRYVIEW(dev_priv
))
4350 gen6_set_rps_thresholds(dev_priv
, val
);
4353 dev_priv
->rps
.cur_freq
= val
;
4354 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv
, val
));
4357 /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
4359 * * If Gfx is Idle, then
4360 * 1. Forcewake Media well.
4361 * 2. Request idle freq.
4362 * 3. Release Forcewake of Media well.
4364 static void vlv_set_rps_idle(struct drm_i915_private
*dev_priv
)
4366 u32 val
= dev_priv
->rps
.idle_freq
;
4368 if (dev_priv
->rps
.cur_freq
<= val
)
4371 /* Wake up the media well, as that takes a lot less
4372 * power than the Render well. */
4373 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_MEDIA
);
4374 valleyview_set_rps(dev_priv
->dev
, val
);
4375 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_MEDIA
);
4378 void gen6_rps_busy(struct drm_i915_private
*dev_priv
)
4380 mutex_lock(&dev_priv
->rps
.hw_lock
);
4381 if (dev_priv
->rps
.enabled
) {
4382 if (dev_priv
->pm_rps_events
& (GEN6_PM_RP_DOWN_EI_EXPIRED
| GEN6_PM_RP_UP_EI_EXPIRED
))
4383 gen6_rps_reset_ei(dev_priv
);
4384 I915_WRITE(GEN6_PMINTRMSK
,
4385 gen6_rps_pm_mask(dev_priv
, dev_priv
->rps
.cur_freq
));
4387 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4390 void gen6_rps_idle(struct drm_i915_private
*dev_priv
)
4392 struct drm_device
*dev
= dev_priv
->dev
;
4394 mutex_lock(&dev_priv
->rps
.hw_lock
);
4395 if (dev_priv
->rps
.enabled
) {
4396 if (IS_VALLEYVIEW(dev
))
4397 vlv_set_rps_idle(dev_priv
);
4399 gen6_set_rps(dev_priv
->dev
, dev_priv
->rps
.idle_freq
);
4400 dev_priv
->rps
.last_adj
= 0;
4401 I915_WRITE(GEN6_PMINTRMSK
, 0xffffffff);
4403 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4405 spin_lock(&dev_priv
->rps
.client_lock
);
4406 while (!list_empty(&dev_priv
->rps
.clients
))
4407 list_del_init(dev_priv
->rps
.clients
.next
);
4408 spin_unlock(&dev_priv
->rps
.client_lock
);
4411 void gen6_rps_boost(struct drm_i915_private
*dev_priv
,
4412 struct intel_rps_client
*rps
,
4413 unsigned long submitted
)
4415 /* This is intentionally racy! We peek at the state here, then
4416 * validate inside the RPS worker.
4418 if (!(dev_priv
->mm
.busy
&&
4419 dev_priv
->rps
.enabled
&&
4420 dev_priv
->rps
.cur_freq
< dev_priv
->rps
.max_freq_softlimit
))
4423 /* Force a RPS boost (and don't count it against the client) if
4424 * the GPU is severely congested.
4426 if (rps
&& time_after(jiffies
, submitted
+ DRM_I915_THROTTLE_JIFFIES
))
4429 spin_lock(&dev_priv
->rps
.client_lock
);
4430 if (rps
== NULL
|| list_empty(&rps
->link
)) {
4431 spin_lock_irq(&dev_priv
->irq_lock
);
4432 if (dev_priv
->rps
.interrupts_enabled
) {
4433 dev_priv
->rps
.client_boost
= true;
4434 queue_work(dev_priv
->wq
, &dev_priv
->rps
.work
);
4436 spin_unlock_irq(&dev_priv
->irq_lock
);
4439 list_add(&rps
->link
, &dev_priv
->rps
.clients
);
4442 dev_priv
->rps
.boosts
++;
4444 spin_unlock(&dev_priv
->rps
.client_lock
);
4447 void intel_set_rps(struct drm_device
*dev
, u8 val
)
4449 if (IS_VALLEYVIEW(dev
))
4450 valleyview_set_rps(dev
, val
);
4452 gen6_set_rps(dev
, val
);
4455 static void gen9_disable_rps(struct drm_device
*dev
)
4457 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4459 I915_WRITE(GEN6_RC_CONTROL
, 0);
4460 I915_WRITE(GEN9_PG_ENABLE
, 0);
4463 static void gen6_disable_rps(struct drm_device
*dev
)
4465 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4467 I915_WRITE(GEN6_RC_CONTROL
, 0);
4468 I915_WRITE(GEN6_RPNSWREQ
, 1 << 31);
4471 static void cherryview_disable_rps(struct drm_device
*dev
)
4473 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4475 I915_WRITE(GEN6_RC_CONTROL
, 0);
4478 static void valleyview_disable_rps(struct drm_device
*dev
)
4480 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4482 /* we're doing forcewake before Disabling RC6,
4483 * This what the BIOS expects when going into suspend */
4484 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
4486 I915_WRITE(GEN6_RC_CONTROL
, 0);
4488 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
4491 static void intel_print_rc6_info(struct drm_device
*dev
, u32 mode
)
4493 if (IS_VALLEYVIEW(dev
)) {
4494 if (mode
& (GEN7_RC_CTL_TO_MODE
| GEN6_RC_CTL_EI_MODE(1)))
4495 mode
= GEN6_RC_CTL_RC6_ENABLE
;
4500 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
4501 (mode
& GEN6_RC_CTL_RC6_ENABLE
) ? "on" : "off",
4502 (mode
& GEN6_RC_CTL_RC6p_ENABLE
) ? "on" : "off",
4503 (mode
& GEN6_RC_CTL_RC6pp_ENABLE
) ? "on" : "off");
4506 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
4507 (mode
& GEN6_RC_CTL_RC6_ENABLE
) ? "on" : "off");
4510 static int sanitize_rc6_option(const struct drm_device
*dev
, int enable_rc6
)
4512 /* No RC6 before Ironlake and code is gone for ilk. */
4513 if (INTEL_INFO(dev
)->gen
< 6)
4516 /* Respect the kernel parameter if it is set */
4517 if (enable_rc6
>= 0) {
4521 mask
= INTEL_RC6_ENABLE
| INTEL_RC6p_ENABLE
|
4524 mask
= INTEL_RC6_ENABLE
;
4526 if ((enable_rc6
& mask
) != enable_rc6
)
4527 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
4528 enable_rc6
& mask
, enable_rc6
, mask
);
4530 return enable_rc6
& mask
;
4533 if (IS_IVYBRIDGE(dev
))
4534 return (INTEL_RC6_ENABLE
| INTEL_RC6p_ENABLE
);
4536 return INTEL_RC6_ENABLE
;
4539 int intel_enable_rc6(const struct drm_device
*dev
)
4541 return i915
.enable_rc6
;
4544 static void gen6_init_rps_frequencies(struct drm_device
*dev
)
4546 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4547 uint32_t rp_state_cap
;
4548 u32 ddcc_status
= 0;
4551 /* All of these values are in units of 50MHz */
4552 dev_priv
->rps
.cur_freq
= 0;
4553 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
4554 if (IS_BROXTON(dev
)) {
4555 rp_state_cap
= I915_READ(BXT_RP_STATE_CAP
);
4556 dev_priv
->rps
.rp0_freq
= (rp_state_cap
>> 16) & 0xff;
4557 dev_priv
->rps
.rp1_freq
= (rp_state_cap
>> 8) & 0xff;
4558 dev_priv
->rps
.min_freq
= (rp_state_cap
>> 0) & 0xff;
4560 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
4561 dev_priv
->rps
.rp0_freq
= (rp_state_cap
>> 0) & 0xff;
4562 dev_priv
->rps
.rp1_freq
= (rp_state_cap
>> 8) & 0xff;
4563 dev_priv
->rps
.min_freq
= (rp_state_cap
>> 16) & 0xff;
4566 /* hw_max = RP0 until we check for overclocking */
4567 dev_priv
->rps
.max_freq
= dev_priv
->rps
.rp0_freq
;
4569 dev_priv
->rps
.efficient_freq
= dev_priv
->rps
.rp1_freq
;
4570 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
) ||
4571 IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
)) {
4572 ret
= sandybridge_pcode_read(dev_priv
,
4573 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL
,
4576 dev_priv
->rps
.efficient_freq
=
4578 ((ddcc_status
>> 8) & 0xff),
4579 dev_priv
->rps
.min_freq
,
4580 dev_priv
->rps
.max_freq
);
4583 if (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
)) {
4584 /* Store the frequency values in 16.66 MHZ units, which is
4585 the natural hardware unit for SKL */
4586 dev_priv
->rps
.rp0_freq
*= GEN9_FREQ_SCALER
;
4587 dev_priv
->rps
.rp1_freq
*= GEN9_FREQ_SCALER
;
4588 dev_priv
->rps
.min_freq
*= GEN9_FREQ_SCALER
;
4589 dev_priv
->rps
.max_freq
*= GEN9_FREQ_SCALER
;
4590 dev_priv
->rps
.efficient_freq
*= GEN9_FREQ_SCALER
;
4593 dev_priv
->rps
.idle_freq
= dev_priv
->rps
.min_freq
;
4595 /* Preserve min/max settings in case of re-init */
4596 if (dev_priv
->rps
.max_freq_softlimit
== 0)
4597 dev_priv
->rps
.max_freq_softlimit
= dev_priv
->rps
.max_freq
;
4599 if (dev_priv
->rps
.min_freq_softlimit
== 0) {
4600 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
4601 dev_priv
->rps
.min_freq_softlimit
=
4602 max_t(int, dev_priv
->rps
.efficient_freq
,
4603 intel_freq_opcode(dev_priv
, 450));
4605 dev_priv
->rps
.min_freq_softlimit
=
4606 dev_priv
->rps
.min_freq
;
4610 /* See the Gen9_GT_PM_Programming_Guide doc for the below */
4611 static void gen9_enable_rps(struct drm_device
*dev
)
4613 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4615 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
4617 gen6_init_rps_frequencies(dev
);
4619 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4620 if (IS_BXT_REVID(dev
, 0, BXT_REVID_A1
)) {
4621 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
4625 /* Program defaults and thresholds for RPS*/
4626 I915_WRITE(GEN6_RC_VIDEO_FREQ
,
4627 GEN9_FREQUENCY(dev_priv
->rps
.rp1_freq
));
4629 /* 1 second timeout*/
4630 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
,
4631 GT_INTERVAL_FROM_US(dev_priv
, 1000000));
4633 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 0xa);
4635 /* Leaning on the below call to gen6_set_rps to program/setup the
4636 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
4637 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
4638 dev_priv
->rps
.power
= HIGH_POWER
; /* force a reset */
4639 gen6_set_rps(dev_priv
->dev
, dev_priv
->rps
.min_freq_softlimit
);
4641 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
4644 static void gen9_enable_rc6(struct drm_device
*dev
)
4646 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4647 struct intel_engine_cs
*ring
;
4648 uint32_t rc6_mask
= 0;
4651 /* 1a: Software RC state - RC0 */
4652 I915_WRITE(GEN6_RC_STATE
, 0);
4654 /* 1b: Get forcewake during program sequence. Although the driver
4655 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4656 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
4658 /* 2a: Disable RC states. */
4659 I915_WRITE(GEN6_RC_CONTROL
, 0);
4661 /* 2b: Program RC6 thresholds.*/
4663 /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
4664 if (IS_SKYLAKE(dev
) && !((IS_SKL_GT3(dev
) || IS_SKL_GT4(dev
)) &&
4665 IS_SKL_REVID(dev
, 0, SKL_REVID_E0
)))
4666 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 108 << 16);
4668 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 54 << 16);
4669 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000); /* 12500 * 1280ns */
4670 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25); /* 25 * 1280ns */
4671 for_each_ring(ring
, dev_priv
, unused
)
4672 I915_WRITE(RING_MAX_IDLE(ring
->mmio_base
), 10);
4674 if (HAS_GUC_UCODE(dev
))
4675 I915_WRITE(GUC_MAX_IDLE_COUNT
, 0xA);
4677 I915_WRITE(GEN6_RC_SLEEP
, 0);
4679 /* 2c: Program Coarse Power Gating Policies. */
4680 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS
, 25);
4681 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS
, 25);
4683 /* 3a: Enable RC6 */
4684 if (intel_enable_rc6(dev
) & INTEL_RC6_ENABLE
)
4685 rc6_mask
= GEN6_RC_CTL_RC6_ENABLE
;
4686 DRM_INFO("RC6 %s\n", (rc6_mask
& GEN6_RC_CTL_RC6_ENABLE
) ?
4688 /* WaRsUseTimeoutMode */
4689 if (IS_SKL_REVID(dev
, 0, SKL_REVID_D0
) ||
4690 IS_BXT_REVID(dev
, 0, BXT_REVID_A0
)) {
4691 I915_WRITE(GEN6_RC6_THRESHOLD
, 625); /* 800us */
4692 I915_WRITE(GEN6_RC_CONTROL
, GEN6_RC_CTL_HW_ENABLE
|
4693 GEN7_RC_CTL_TO_MODE
|
4696 I915_WRITE(GEN6_RC6_THRESHOLD
, 37500); /* 37.5/125ms per EI */
4697 I915_WRITE(GEN6_RC_CONTROL
, GEN6_RC_CTL_HW_ENABLE
|
4698 GEN6_RC_CTL_EI_MODE(1) |
4703 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
4704 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
4706 if (IS_BXT_REVID(dev
, 0, BXT_REVID_A1
) ||
4707 ((IS_SKL_GT3(dev
) || IS_SKL_GT4(dev
)) &&
4708 IS_SKL_REVID(dev
, 0, SKL_REVID_E0
)))
4709 I915_WRITE(GEN9_PG_ENABLE
, 0);
4711 I915_WRITE(GEN9_PG_ENABLE
, (rc6_mask
& GEN6_RC_CTL_RC6_ENABLE
) ?
4712 (GEN9_RENDER_PG_ENABLE
| GEN9_MEDIA_PG_ENABLE
) : 0);
4714 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
4718 static void gen8_enable_rps(struct drm_device
*dev
)
4720 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4721 struct intel_engine_cs
*ring
;
4722 uint32_t rc6_mask
= 0;
4725 /* 1a: Software RC state - RC0 */
4726 I915_WRITE(GEN6_RC_STATE
, 0);
4728 /* 1c & 1d: Get forcewake during program sequence. Although the driver
4729 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4730 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
4732 /* 2a: Disable RC states. */
4733 I915_WRITE(GEN6_RC_CONTROL
, 0);
4735 /* Initialize rps frequencies */
4736 gen6_init_rps_frequencies(dev
);
4738 /* 2b: Program RC6 thresholds.*/
4739 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 40 << 16);
4740 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000); /* 12500 * 1280ns */
4741 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25); /* 25 * 1280ns */
4742 for_each_ring(ring
, dev_priv
, unused
)
4743 I915_WRITE(RING_MAX_IDLE(ring
->mmio_base
), 10);
4744 I915_WRITE(GEN6_RC_SLEEP
, 0);
4745 if (IS_BROADWELL(dev
))
4746 I915_WRITE(GEN6_RC6_THRESHOLD
, 625); /* 800us/1.28 for TO */
4748 I915_WRITE(GEN6_RC6_THRESHOLD
, 50000); /* 50/125ms per EI */
4751 if (intel_enable_rc6(dev
) & INTEL_RC6_ENABLE
)
4752 rc6_mask
= GEN6_RC_CTL_RC6_ENABLE
;
4753 intel_print_rc6_info(dev
, rc6_mask
);
4754 if (IS_BROADWELL(dev
))
4755 I915_WRITE(GEN6_RC_CONTROL
, GEN6_RC_CTL_HW_ENABLE
|
4756 GEN7_RC_CTL_TO_MODE
|
4759 I915_WRITE(GEN6_RC_CONTROL
, GEN6_RC_CTL_HW_ENABLE
|
4760 GEN6_RC_CTL_EI_MODE(1) |
4763 /* 4 Program defaults and thresholds for RPS*/
4764 I915_WRITE(GEN6_RPNSWREQ
,
4765 HSW_FREQUENCY(dev_priv
->rps
.rp1_freq
));
4766 I915_WRITE(GEN6_RC_VIDEO_FREQ
,
4767 HSW_FREQUENCY(dev_priv
->rps
.rp1_freq
));
4768 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
4769 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 100000000 / 128); /* 1 second timeout */
4771 /* Docs recommend 900MHz, and 300 MHz respectively */
4772 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS
,
4773 dev_priv
->rps
.max_freq_softlimit
<< 24 |
4774 dev_priv
->rps
.min_freq_softlimit
<< 16);
4776 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 7600000 / 128); /* 76ms busyness per EI, 90% */
4777 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 31300000 / 128); /* 313ms busyness per EI, 70%*/
4778 I915_WRITE(GEN6_RP_UP_EI
, 66000); /* 84.48ms, XXX: random? */
4779 I915_WRITE(GEN6_RP_DOWN_EI
, 350000); /* 448ms, XXX: random? */
4781 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
4784 I915_WRITE(GEN6_RP_CONTROL
,
4785 GEN6_RP_MEDIA_TURBO
|
4786 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
4787 GEN6_RP_MEDIA_IS_GFX
|
4789 GEN6_RP_UP_BUSY_AVG
|
4790 GEN6_RP_DOWN_IDLE_AVG
);
4792 /* 6: Ring frequency + overclocking (our driver does this later */
4794 dev_priv
->rps
.power
= HIGH_POWER
; /* force a reset */
4795 gen6_set_rps(dev_priv
->dev
, dev_priv
->rps
.idle_freq
);
4797 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
4800 static void gen6_enable_rps(struct drm_device
*dev
)
4802 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4803 struct intel_engine_cs
*ring
;
4804 u32 rc6vids
, pcu_mbox
= 0, rc6_mask
= 0;
4809 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
4811 /* Here begins a magic sequence of register writes to enable
4812 * auto-downclocking.
4814 * Perhaps there might be some value in exposing these to
4817 I915_WRITE(GEN6_RC_STATE
, 0);
4819 /* Clear the DBG now so we don't confuse earlier errors */
4820 if ((gtfifodbg
= I915_READ(GTFIFODBG
))) {
4821 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg
);
4822 I915_WRITE(GTFIFODBG
, gtfifodbg
);
4825 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
4827 /* Initialize rps frequencies */
4828 gen6_init_rps_frequencies(dev
);
4830 /* disable the counters and set deterministic thresholds */
4831 I915_WRITE(GEN6_RC_CONTROL
, 0);
4833 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT
, 1000 << 16);
4834 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 40 << 16 | 30);
4835 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT
, 30);
4836 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000);
4837 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25);
4839 for_each_ring(ring
, dev_priv
, i
)
4840 I915_WRITE(RING_MAX_IDLE(ring
->mmio_base
), 10);
4842 I915_WRITE(GEN6_RC_SLEEP
, 0);
4843 I915_WRITE(GEN6_RC1e_THRESHOLD
, 1000);
4844 if (IS_IVYBRIDGE(dev
))
4845 I915_WRITE(GEN6_RC6_THRESHOLD
, 125000);
4847 I915_WRITE(GEN6_RC6_THRESHOLD
, 50000);
4848 I915_WRITE(GEN6_RC6p_THRESHOLD
, 150000);
4849 I915_WRITE(GEN6_RC6pp_THRESHOLD
, 64000); /* unused */
4851 /* Check if we are enabling RC6 */
4852 rc6_mode
= intel_enable_rc6(dev_priv
->dev
);
4853 if (rc6_mode
& INTEL_RC6_ENABLE
)
4854 rc6_mask
|= GEN6_RC_CTL_RC6_ENABLE
;
4856 /* We don't use those on Haswell */
4857 if (!IS_HASWELL(dev
)) {
4858 if (rc6_mode
& INTEL_RC6p_ENABLE
)
4859 rc6_mask
|= GEN6_RC_CTL_RC6p_ENABLE
;
4861 if (rc6_mode
& INTEL_RC6pp_ENABLE
)
4862 rc6_mask
|= GEN6_RC_CTL_RC6pp_ENABLE
;
4865 intel_print_rc6_info(dev
, rc6_mask
);
4867 I915_WRITE(GEN6_RC_CONTROL
,
4869 GEN6_RC_CTL_EI_MODE(1) |
4870 GEN6_RC_CTL_HW_ENABLE
);
4872 /* Power down if completely idle for over 50ms */
4873 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 50000);
4874 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
4876 ret
= sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_MIN_FREQ_TABLE
, 0);
4878 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
4880 ret
= sandybridge_pcode_read(dev_priv
, GEN6_READ_OC_PARAMS
, &pcu_mbox
);
4881 if (!ret
&& (pcu_mbox
& (1<<31))) { /* OC supported */
4882 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
4883 (dev_priv
->rps
.max_freq_softlimit
& 0xff) * 50,
4884 (pcu_mbox
& 0xff) * 50);
4885 dev_priv
->rps
.max_freq
= pcu_mbox
& 0xff;
4888 dev_priv
->rps
.power
= HIGH_POWER
; /* force a reset */
4889 gen6_set_rps(dev_priv
->dev
, dev_priv
->rps
.idle_freq
);
4892 ret
= sandybridge_pcode_read(dev_priv
, GEN6_PCODE_READ_RC6VIDS
, &rc6vids
);
4893 if (IS_GEN6(dev
) && ret
) {
4894 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
4895 } else if (IS_GEN6(dev
) && (GEN6_DECODE_RC6_VID(rc6vids
& 0xff) < 450)) {
4896 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
4897 GEN6_DECODE_RC6_VID(rc6vids
& 0xff), 450);
4898 rc6vids
&= 0xffff00;
4899 rc6vids
|= GEN6_ENCODE_RC6_VID(450);
4900 ret
= sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_RC6VIDS
, rc6vids
);
4902 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
4905 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
4908 static void __gen6_update_ring_freq(struct drm_device
*dev
)
4910 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4912 unsigned int gpu_freq
;
4913 unsigned int max_ia_freq
, min_ring_freq
;
4914 unsigned int max_gpu_freq
, min_gpu_freq
;
4915 int scaling_factor
= 180;
4916 struct cpufreq_policy
*policy
;
4918 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
4920 policy
= cpufreq_cpu_get(0);
4922 max_ia_freq
= policy
->cpuinfo
.max_freq
;
4923 cpufreq_cpu_put(policy
);
4926 * Default to measured freq if none found, PCU will ensure we
4929 max_ia_freq
= tsc_khz
;
4932 /* Convert from kHz to MHz */
4933 max_ia_freq
/= 1000;
4935 min_ring_freq
= I915_READ(DCLK
) & 0xf;
4936 /* convert DDR frequency from units of 266.6MHz to bandwidth */
4937 min_ring_freq
= mult_frac(min_ring_freq
, 8, 3);
4939 if (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
)) {
4940 /* Convert GT frequency to 50 HZ units */
4941 min_gpu_freq
= dev_priv
->rps
.min_freq
/ GEN9_FREQ_SCALER
;
4942 max_gpu_freq
= dev_priv
->rps
.max_freq
/ GEN9_FREQ_SCALER
;
4944 min_gpu_freq
= dev_priv
->rps
.min_freq
;
4945 max_gpu_freq
= dev_priv
->rps
.max_freq
;
4949 * For each potential GPU frequency, load a ring frequency we'd like
4950 * to use for memory access. We do this by specifying the IA frequency
4951 * the PCU should use as a reference to determine the ring frequency.
4953 for (gpu_freq
= max_gpu_freq
; gpu_freq
>= min_gpu_freq
; gpu_freq
--) {
4954 int diff
= max_gpu_freq
- gpu_freq
;
4955 unsigned int ia_freq
= 0, ring_freq
= 0;
4957 if (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
)) {
4959 * ring_freq = 2 * GT. ring_freq is in 100MHz units
4960 * No floor required for ring frequency on SKL.
4962 ring_freq
= gpu_freq
;
4963 } else if (INTEL_INFO(dev
)->gen
>= 8) {
4964 /* max(2 * GT, DDR). NB: GT is 50MHz units */
4965 ring_freq
= max(min_ring_freq
, gpu_freq
);
4966 } else if (IS_HASWELL(dev
)) {
4967 ring_freq
= mult_frac(gpu_freq
, 5, 4);
4968 ring_freq
= max(min_ring_freq
, ring_freq
);
4969 /* leave ia_freq as the default, chosen by cpufreq */
4971 /* On older processors, there is no separate ring
4972 * clock domain, so in order to boost the bandwidth
4973 * of the ring, we need to upclock the CPU (ia_freq).
4975 * For GPU frequencies less than 750MHz,
4976 * just use the lowest ring freq.
4978 if (gpu_freq
< min_freq
)
4981 ia_freq
= max_ia_freq
- ((diff
* scaling_factor
) / 2);
4982 ia_freq
= DIV_ROUND_CLOSEST(ia_freq
, 100);
4985 sandybridge_pcode_write(dev_priv
,
4986 GEN6_PCODE_WRITE_MIN_FREQ_TABLE
,
4987 ia_freq
<< GEN6_PCODE_FREQ_IA_RATIO_SHIFT
|
4988 ring_freq
<< GEN6_PCODE_FREQ_RING_RATIO_SHIFT
|
4993 void gen6_update_ring_freq(struct drm_device
*dev
)
4995 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4997 if (!HAS_CORE_RING_FREQ(dev
))
5000 mutex_lock(&dev_priv
->rps
.hw_lock
);
5001 __gen6_update_ring_freq(dev
);
5002 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5005 static int cherryview_rps_max_freq(struct drm_i915_private
*dev_priv
)
5007 struct drm_device
*dev
= dev_priv
->dev
;
5010 val
= vlv_punit_read(dev_priv
, FB_GFX_FMAX_AT_VMAX_FUSE
);
5012 switch (INTEL_INFO(dev
)->eu_total
) {
5014 /* (2 * 4) config */
5015 rp0
= (val
>> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT
);
5018 /* (2 * 6) config */
5019 rp0
= (val
>> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT
);
5022 /* (2 * 8) config */
5024 /* Setting (2 * 8) Min RP0 for any other combination */
5025 rp0
= (val
>> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT
);
5029 rp0
= (rp0
& FB_GFX_FREQ_FUSE_MASK
);
5034 static int cherryview_rps_rpe_freq(struct drm_i915_private
*dev_priv
)
5038 val
= vlv_punit_read(dev_priv
, PUNIT_GPU_DUTYCYCLE_REG
);
5039 rpe
= (val
>> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT
) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK
;
5044 static int cherryview_rps_guar_freq(struct drm_i915_private
*dev_priv
)
5048 val
= vlv_punit_read(dev_priv
, FB_GFX_FMAX_AT_VMAX_FUSE
);
5049 rp1
= (val
& FB_GFX_FREQ_FUSE_MASK
);
5054 static int valleyview_rps_guar_freq(struct drm_i915_private
*dev_priv
)
5058 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FREQ_FUSE
);
5060 rp1
= (val
& FB_GFX_FGUARANTEED_FREQ_FUSE_MASK
) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT
;
5065 static int valleyview_rps_max_freq(struct drm_i915_private
*dev_priv
)
5069 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FREQ_FUSE
);
5071 rp0
= (val
& FB_GFX_MAX_FREQ_FUSE_MASK
) >> FB_GFX_MAX_FREQ_FUSE_SHIFT
;
5073 rp0
= min_t(u32
, rp0
, 0xea);
5078 static int valleyview_rps_rpe_freq(struct drm_i915_private
*dev_priv
)
5082 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FMAX_FUSE_LO
);
5083 rpe
= (val
& FB_FMAX_VMIN_FREQ_LO_MASK
) >> FB_FMAX_VMIN_FREQ_LO_SHIFT
;
5084 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FMAX_FUSE_HI
);
5085 rpe
|= (val
& FB_FMAX_VMIN_FREQ_HI_MASK
) << 5;
5090 static int valleyview_rps_min_freq(struct drm_i915_private
*dev_priv
)
5092 return vlv_punit_read(dev_priv
, PUNIT_REG_GPU_LFM
) & 0xff;
5095 /* Check that the pctx buffer wasn't move under us. */
5096 static void valleyview_check_pctx(struct drm_i915_private
*dev_priv
)
5098 unsigned long pctx_addr
= I915_READ(VLV_PCBR
) & ~4095;
5100 WARN_ON(pctx_addr
!= dev_priv
->mm
.stolen_base
+
5101 dev_priv
->vlv_pctx
->stolen
->start
);
5105 /* Check that the pcbr address is not empty. */
5106 static void cherryview_check_pctx(struct drm_i915_private
*dev_priv
)
5108 unsigned long pctx_addr
= I915_READ(VLV_PCBR
) & ~4095;
5110 WARN_ON((pctx_addr
>> VLV_PCBR_ADDR_SHIFT
) == 0);
5113 static void cherryview_setup_pctx(struct drm_device
*dev
)
5115 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5116 unsigned long pctx_paddr
, paddr
;
5117 struct i915_gtt
*gtt
= &dev_priv
->gtt
;
5119 int pctx_size
= 32*1024;
5121 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
5123 pcbr
= I915_READ(VLV_PCBR
);
5124 if ((pcbr
>> VLV_PCBR_ADDR_SHIFT
) == 0) {
5125 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5126 paddr
= (dev_priv
->mm
.stolen_base
+
5127 (gtt
->stolen_size
- pctx_size
));
5129 pctx_paddr
= (paddr
& (~4095));
5130 I915_WRITE(VLV_PCBR
, pctx_paddr
);
5133 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR
));
5136 static void valleyview_setup_pctx(struct drm_device
*dev
)
5138 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5139 struct drm_i915_gem_object
*pctx
;
5140 unsigned long pctx_paddr
;
5142 int pctx_size
= 24*1024;
5144 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
5146 pcbr
= I915_READ(VLV_PCBR
);
5148 /* BIOS set it up already, grab the pre-alloc'd space */
5151 pcbr_offset
= (pcbr
& (~4095)) - dev_priv
->mm
.stolen_base
;
5152 pctx
= i915_gem_object_create_stolen_for_preallocated(dev_priv
->dev
,
5154 I915_GTT_OFFSET_NONE
,
5159 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5162 * From the Gunit register HAS:
5163 * The Gfx driver is expected to program this register and ensure
5164 * proper allocation within Gfx stolen memory. For example, this
5165 * register should be programmed such than the PCBR range does not
5166 * overlap with other ranges, such as the frame buffer, protected
5167 * memory, or any other relevant ranges.
5169 pctx
= i915_gem_object_create_stolen(dev
, pctx_size
);
5171 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
5175 pctx_paddr
= dev_priv
->mm
.stolen_base
+ pctx
->stolen
->start
;
5176 I915_WRITE(VLV_PCBR
, pctx_paddr
);
5179 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR
));
5180 dev_priv
->vlv_pctx
= pctx
;
5183 static void valleyview_cleanup_pctx(struct drm_device
*dev
)
5185 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5187 if (WARN_ON(!dev_priv
->vlv_pctx
))
5190 drm_gem_object_unreference(&dev_priv
->vlv_pctx
->base
);
5191 dev_priv
->vlv_pctx
= NULL
;
5194 static void valleyview_init_gt_powersave(struct drm_device
*dev
)
5196 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5199 valleyview_setup_pctx(dev
);
5201 mutex_lock(&dev_priv
->rps
.hw_lock
);
5203 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
5204 switch ((val
>> 6) & 3) {
5207 dev_priv
->mem_freq
= 800;
5210 dev_priv
->mem_freq
= 1066;
5213 dev_priv
->mem_freq
= 1333;
5216 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv
->mem_freq
);
5218 dev_priv
->rps
.max_freq
= valleyview_rps_max_freq(dev_priv
);
5219 dev_priv
->rps
.rp0_freq
= dev_priv
->rps
.max_freq
;
5220 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5221 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
),
5222 dev_priv
->rps
.max_freq
);
5224 dev_priv
->rps
.efficient_freq
= valleyview_rps_rpe_freq(dev_priv
);
5225 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5226 intel_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
),
5227 dev_priv
->rps
.efficient_freq
);
5229 dev_priv
->rps
.rp1_freq
= valleyview_rps_guar_freq(dev_priv
);
5230 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
5231 intel_gpu_freq(dev_priv
, dev_priv
->rps
.rp1_freq
),
5232 dev_priv
->rps
.rp1_freq
);
5234 dev_priv
->rps
.min_freq
= valleyview_rps_min_freq(dev_priv
);
5235 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5236 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
),
5237 dev_priv
->rps
.min_freq
);
5239 dev_priv
->rps
.idle_freq
= dev_priv
->rps
.min_freq
;
5241 /* Preserve min/max settings in case of re-init */
5242 if (dev_priv
->rps
.max_freq_softlimit
== 0)
5243 dev_priv
->rps
.max_freq_softlimit
= dev_priv
->rps
.max_freq
;
5245 if (dev_priv
->rps
.min_freq_softlimit
== 0)
5246 dev_priv
->rps
.min_freq_softlimit
= dev_priv
->rps
.min_freq
;
5248 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5251 static void cherryview_init_gt_powersave(struct drm_device
*dev
)
5253 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5256 cherryview_setup_pctx(dev
);
5258 mutex_lock(&dev_priv
->rps
.hw_lock
);
5260 mutex_lock(&dev_priv
->sb_lock
);
5261 val
= vlv_cck_read(dev_priv
, CCK_FUSE_REG
);
5262 mutex_unlock(&dev_priv
->sb_lock
);
5264 switch ((val
>> 2) & 0x7) {
5266 dev_priv
->mem_freq
= 2000;
5269 dev_priv
->mem_freq
= 1600;
5272 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv
->mem_freq
);
5274 dev_priv
->rps
.max_freq
= cherryview_rps_max_freq(dev_priv
);
5275 dev_priv
->rps
.rp0_freq
= dev_priv
->rps
.max_freq
;
5276 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5277 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
),
5278 dev_priv
->rps
.max_freq
);
5280 dev_priv
->rps
.efficient_freq
= cherryview_rps_rpe_freq(dev_priv
);
5281 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5282 intel_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
),
5283 dev_priv
->rps
.efficient_freq
);
5285 dev_priv
->rps
.rp1_freq
= cherryview_rps_guar_freq(dev_priv
);
5286 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
5287 intel_gpu_freq(dev_priv
, dev_priv
->rps
.rp1_freq
),
5288 dev_priv
->rps
.rp1_freq
);
5290 /* PUnit validated range is only [RPe, RP0] */
5291 dev_priv
->rps
.min_freq
= dev_priv
->rps
.efficient_freq
;
5292 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5293 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
),
5294 dev_priv
->rps
.min_freq
);
5296 WARN_ONCE((dev_priv
->rps
.max_freq
|
5297 dev_priv
->rps
.efficient_freq
|
5298 dev_priv
->rps
.rp1_freq
|
5299 dev_priv
->rps
.min_freq
) & 1,
5300 "Odd GPU freq values\n");
5302 dev_priv
->rps
.idle_freq
= dev_priv
->rps
.min_freq
;
5304 /* Preserve min/max settings in case of re-init */
5305 if (dev_priv
->rps
.max_freq_softlimit
== 0)
5306 dev_priv
->rps
.max_freq_softlimit
= dev_priv
->rps
.max_freq
;
5308 if (dev_priv
->rps
.min_freq_softlimit
== 0)
5309 dev_priv
->rps
.min_freq_softlimit
= dev_priv
->rps
.min_freq
;
5311 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5314 static void valleyview_cleanup_gt_powersave(struct drm_device
*dev
)
5316 valleyview_cleanup_pctx(dev
);
5319 static void cherryview_enable_rps(struct drm_device
*dev
)
5321 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5322 struct intel_engine_cs
*ring
;
5323 u32 gtfifodbg
, val
, rc6_mode
= 0, pcbr
;
5326 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
5328 gtfifodbg
= I915_READ(GTFIFODBG
);
5330 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5332 I915_WRITE(GTFIFODBG
, gtfifodbg
);
5335 cherryview_check_pctx(dev_priv
);
5337 /* 1a & 1b: Get forcewake during program sequence. Although the driver
5338 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5339 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
5341 /* Disable RC states. */
5342 I915_WRITE(GEN6_RC_CONTROL
, 0);
5344 /* 2a: Program RC6 thresholds.*/
5345 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 40 << 16);
5346 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000); /* 12500 * 1280ns */
5347 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25); /* 25 * 1280ns */
5349 for_each_ring(ring
, dev_priv
, i
)
5350 I915_WRITE(RING_MAX_IDLE(ring
->mmio_base
), 10);
5351 I915_WRITE(GEN6_RC_SLEEP
, 0);
5353 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
5354 I915_WRITE(GEN6_RC6_THRESHOLD
, 0x186);
5356 /* allows RC6 residency counter to work */
5357 I915_WRITE(VLV_COUNTER_CONTROL
,
5358 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH
|
5359 VLV_MEDIA_RC6_COUNT_EN
|
5360 VLV_RENDER_RC6_COUNT_EN
));
5362 /* For now we assume BIOS is allocating and populating the PCBR */
5363 pcbr
= I915_READ(VLV_PCBR
);
5366 if ((intel_enable_rc6(dev
) & INTEL_RC6_ENABLE
) &&
5367 (pcbr
>> VLV_PCBR_ADDR_SHIFT
))
5368 rc6_mode
= GEN7_RC_CTL_TO_MODE
;
5370 I915_WRITE(GEN6_RC_CONTROL
, rc6_mode
);
5372 /* 4 Program defaults and thresholds for RPS*/
5373 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 1000000);
5374 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 59400);
5375 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 245000);
5376 I915_WRITE(GEN6_RP_UP_EI
, 66000);
5377 I915_WRITE(GEN6_RP_DOWN_EI
, 350000);
5379 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
5382 I915_WRITE(GEN6_RP_CONTROL
,
5383 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
5384 GEN6_RP_MEDIA_IS_GFX
|
5386 GEN6_RP_UP_BUSY_AVG
|
5387 GEN6_RP_DOWN_IDLE_AVG
);
5389 /* Setting Fixed Bias */
5390 val
= VLV_OVERRIDE_EN
|
5392 CHV_BIAS_CPU_50_SOC_50
;
5393 vlv_punit_write(dev_priv
, VLV_TURBO_SOC_OVERRIDE
, val
);
5395 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
5397 /* RPS code assumes GPLL is used */
5398 WARN_ONCE((val
& GPLLENABLE
) == 0, "GPLL not enabled\n");
5400 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val
& GPLLENABLE
));
5401 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val
);
5403 dev_priv
->rps
.cur_freq
= (val
>> 8) & 0xff;
5404 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5405 intel_gpu_freq(dev_priv
, dev_priv
->rps
.cur_freq
),
5406 dev_priv
->rps
.cur_freq
);
5408 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5409 intel_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
),
5410 dev_priv
->rps
.efficient_freq
);
5412 valleyview_set_rps(dev_priv
->dev
, dev_priv
->rps
.efficient_freq
);
5414 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
5417 static void valleyview_enable_rps(struct drm_device
*dev
)
5419 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5420 struct intel_engine_cs
*ring
;
5421 u32 gtfifodbg
, val
, rc6_mode
= 0;
5424 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
5426 valleyview_check_pctx(dev_priv
);
5428 if ((gtfifodbg
= I915_READ(GTFIFODBG
))) {
5429 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5431 I915_WRITE(GTFIFODBG
, gtfifodbg
);
5434 /* If VLV, Forcewake all wells, else re-direct to regular path */
5435 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
5437 /* Disable RC states. */
5438 I915_WRITE(GEN6_RC_CONTROL
, 0);
5440 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 1000000);
5441 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 59400);
5442 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 245000);
5443 I915_WRITE(GEN6_RP_UP_EI
, 66000);
5444 I915_WRITE(GEN6_RP_DOWN_EI
, 350000);
5446 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
5448 I915_WRITE(GEN6_RP_CONTROL
,
5449 GEN6_RP_MEDIA_TURBO
|
5450 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
5451 GEN6_RP_MEDIA_IS_GFX
|
5453 GEN6_RP_UP_BUSY_AVG
|
5454 GEN6_RP_DOWN_IDLE_CONT
);
5456 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 0x00280000);
5457 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000);
5458 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25);
5460 for_each_ring(ring
, dev_priv
, i
)
5461 I915_WRITE(RING_MAX_IDLE(ring
->mmio_base
), 10);
5463 I915_WRITE(GEN6_RC6_THRESHOLD
, 0x557);
5465 /* allows RC6 residency counter to work */
5466 I915_WRITE(VLV_COUNTER_CONTROL
,
5467 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN
|
5468 VLV_RENDER_RC0_COUNT_EN
|
5469 VLV_MEDIA_RC6_COUNT_EN
|
5470 VLV_RENDER_RC6_COUNT_EN
));
5472 if (intel_enable_rc6(dev
) & INTEL_RC6_ENABLE
)
5473 rc6_mode
= GEN7_RC_CTL_TO_MODE
| VLV_RC_CTL_CTX_RST_PARALLEL
;
5475 intel_print_rc6_info(dev
, rc6_mode
);
5477 I915_WRITE(GEN6_RC_CONTROL
, rc6_mode
);
5479 /* Setting Fixed Bias */
5480 val
= VLV_OVERRIDE_EN
|
5482 VLV_BIAS_CPU_125_SOC_875
;
5483 vlv_punit_write(dev_priv
, VLV_TURBO_SOC_OVERRIDE
, val
);
5485 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
5487 /* RPS code assumes GPLL is used */
5488 WARN_ONCE((val
& GPLLENABLE
) == 0, "GPLL not enabled\n");
5490 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val
& GPLLENABLE
));
5491 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val
);
5493 dev_priv
->rps
.cur_freq
= (val
>> 8) & 0xff;
5494 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5495 intel_gpu_freq(dev_priv
, dev_priv
->rps
.cur_freq
),
5496 dev_priv
->rps
.cur_freq
);
5498 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5499 intel_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
),
5500 dev_priv
->rps
.efficient_freq
);
5502 valleyview_set_rps(dev_priv
->dev
, dev_priv
->rps
.efficient_freq
);
5504 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
5507 static unsigned long intel_pxfreq(u32 vidfreq
)
5510 int div
= (vidfreq
& 0x3f0000) >> 16;
5511 int post
= (vidfreq
& 0x3000) >> 12;
5512 int pre
= (vidfreq
& 0x7);
5517 freq
= ((div
* 133333) / ((1<<post
) * pre
));
5522 static const struct cparams
{
5528 { 1, 1333, 301, 28664 },
5529 { 1, 1066, 294, 24460 },
5530 { 1, 800, 294, 25192 },
5531 { 0, 1333, 276, 27605 },
5532 { 0, 1066, 276, 27605 },
5533 { 0, 800, 231, 23784 },
5536 static unsigned long __i915_chipset_val(struct drm_i915_private
*dev_priv
)
5538 u64 total_count
, diff
, ret
;
5539 u32 count1
, count2
, count3
, m
= 0, c
= 0;
5540 unsigned long now
= jiffies_to_msecs(jiffies
), diff1
;
5543 assert_spin_locked(&mchdev_lock
);
5545 diff1
= now
- dev_priv
->ips
.last_time1
;
5547 /* Prevent division-by-zero if we are asking too fast.
5548 * Also, we don't get interesting results if we are polling
5549 * faster than once in 10ms, so just return the saved value
5553 return dev_priv
->ips
.chipset_power
;
5555 count1
= I915_READ(DMIEC
);
5556 count2
= I915_READ(DDREC
);
5557 count3
= I915_READ(CSIEC
);
5559 total_count
= count1
+ count2
+ count3
;
5561 /* FIXME: handle per-counter overflow */
5562 if (total_count
< dev_priv
->ips
.last_count1
) {
5563 diff
= ~0UL - dev_priv
->ips
.last_count1
;
5564 diff
+= total_count
;
5566 diff
= total_count
- dev_priv
->ips
.last_count1
;
5569 for (i
= 0; i
< ARRAY_SIZE(cparams
); i
++) {
5570 if (cparams
[i
].i
== dev_priv
->ips
.c_m
&&
5571 cparams
[i
].t
== dev_priv
->ips
.r_t
) {
5578 diff
= div_u64(diff
, diff1
);
5579 ret
= ((m
* diff
) + c
);
5580 ret
= div_u64(ret
, 10);
5582 dev_priv
->ips
.last_count1
= total_count
;
5583 dev_priv
->ips
.last_time1
= now
;
5585 dev_priv
->ips
.chipset_power
= ret
;
5590 unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
)
5592 struct drm_device
*dev
= dev_priv
->dev
;
5595 if (INTEL_INFO(dev
)->gen
!= 5)
5598 spin_lock_irq(&mchdev_lock
);
5600 val
= __i915_chipset_val(dev_priv
);
5602 spin_unlock_irq(&mchdev_lock
);
5607 unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
)
5609 unsigned long m
, x
, b
;
5612 tsfs
= I915_READ(TSFS
);
5614 m
= ((tsfs
& TSFS_SLOPE_MASK
) >> TSFS_SLOPE_SHIFT
);
5615 x
= I915_READ8(TR1
);
5617 b
= tsfs
& TSFS_INTR_MASK
;
5619 return ((m
* x
) / 127) - b
;
5622 static int _pxvid_to_vd(u8 pxvid
)
5627 if (pxvid
>= 8 && pxvid
< 31)
5630 return (pxvid
+ 2) * 125;
5633 static u32
pvid_to_extvid(struct drm_i915_private
*dev_priv
, u8 pxvid
)
5635 struct drm_device
*dev
= dev_priv
->dev
;
5636 const int vd
= _pxvid_to_vd(pxvid
);
5637 const int vm
= vd
- 1125;
5639 if (INTEL_INFO(dev
)->is_mobile
)
5640 return vm
> 0 ? vm
: 0;
5645 static void __i915_update_gfx_val(struct drm_i915_private
*dev_priv
)
5647 u64 now
, diff
, diffms
;
5650 assert_spin_locked(&mchdev_lock
);
5652 now
= ktime_get_raw_ns();
5653 diffms
= now
- dev_priv
->ips
.last_time2
;
5654 do_div(diffms
, NSEC_PER_MSEC
);
5656 /* Don't divide by 0 */
5660 count
= I915_READ(GFXEC
);
5662 if (count
< dev_priv
->ips
.last_count2
) {
5663 diff
= ~0UL - dev_priv
->ips
.last_count2
;
5666 diff
= count
- dev_priv
->ips
.last_count2
;
5669 dev_priv
->ips
.last_count2
= count
;
5670 dev_priv
->ips
.last_time2
= now
;
5672 /* More magic constants... */
5674 diff
= div_u64(diff
, diffms
* 10);
5675 dev_priv
->ips
.gfx_power
= diff
;
5678 void i915_update_gfx_val(struct drm_i915_private
*dev_priv
)
5680 struct drm_device
*dev
= dev_priv
->dev
;
5682 if (INTEL_INFO(dev
)->gen
!= 5)
5685 spin_lock_irq(&mchdev_lock
);
5687 __i915_update_gfx_val(dev_priv
);
5689 spin_unlock_irq(&mchdev_lock
);
5692 static unsigned long __i915_gfx_val(struct drm_i915_private
*dev_priv
)
5694 unsigned long t
, corr
, state1
, corr2
, state2
;
5697 assert_spin_locked(&mchdev_lock
);
5699 pxvid
= I915_READ(PXVFREQ(dev_priv
->rps
.cur_freq
));
5700 pxvid
= (pxvid
>> 24) & 0x7f;
5701 ext_v
= pvid_to_extvid(dev_priv
, pxvid
);
5705 t
= i915_mch_val(dev_priv
);
5707 /* Revel in the empirically derived constants */
5709 /* Correction factor in 1/100000 units */
5711 corr
= ((t
* 2349) + 135940);
5713 corr
= ((t
* 964) + 29317);
5715 corr
= ((t
* 301) + 1004);
5717 corr
= corr
* ((150142 * state1
) / 10000 - 78642);
5719 corr2
= (corr
* dev_priv
->ips
.corr
);
5721 state2
= (corr2
* state1
) / 10000;
5722 state2
/= 100; /* convert to mW */
5724 __i915_update_gfx_val(dev_priv
);
5726 return dev_priv
->ips
.gfx_power
+ state2
;
5729 unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
)
5731 struct drm_device
*dev
= dev_priv
->dev
;
5734 if (INTEL_INFO(dev
)->gen
!= 5)
5737 spin_lock_irq(&mchdev_lock
);
5739 val
= __i915_gfx_val(dev_priv
);
5741 spin_unlock_irq(&mchdev_lock
);
5747 * i915_read_mch_val - return value for IPS use
5749 * Calculate and return a value for the IPS driver to use when deciding whether
5750 * we have thermal and power headroom to increase CPU or GPU power budget.
5752 unsigned long i915_read_mch_val(void)
5754 struct drm_i915_private
*dev_priv
;
5755 unsigned long chipset_val
, graphics_val
, ret
= 0;
5757 spin_lock_irq(&mchdev_lock
);
5760 dev_priv
= i915_mch_dev
;
5762 chipset_val
= __i915_chipset_val(dev_priv
);
5763 graphics_val
= __i915_gfx_val(dev_priv
);
5765 ret
= chipset_val
+ graphics_val
;
5768 spin_unlock_irq(&mchdev_lock
);
5772 EXPORT_SYMBOL_GPL(i915_read_mch_val
);
5775 * i915_gpu_raise - raise GPU frequency limit
5777 * Raise the limit; IPS indicates we have thermal headroom.
5779 bool i915_gpu_raise(void)
5781 struct drm_i915_private
*dev_priv
;
5784 spin_lock_irq(&mchdev_lock
);
5785 if (!i915_mch_dev
) {
5789 dev_priv
= i915_mch_dev
;
5791 if (dev_priv
->ips
.max_delay
> dev_priv
->ips
.fmax
)
5792 dev_priv
->ips
.max_delay
--;
5795 spin_unlock_irq(&mchdev_lock
);
5799 EXPORT_SYMBOL_GPL(i915_gpu_raise
);
5802 * i915_gpu_lower - lower GPU frequency limit
5804 * IPS indicates we're close to a thermal limit, so throttle back the GPU
5805 * frequency maximum.
5807 bool i915_gpu_lower(void)
5809 struct drm_i915_private
*dev_priv
;
5812 spin_lock_irq(&mchdev_lock
);
5813 if (!i915_mch_dev
) {
5817 dev_priv
= i915_mch_dev
;
5819 if (dev_priv
->ips
.max_delay
< dev_priv
->ips
.min_delay
)
5820 dev_priv
->ips
.max_delay
++;
5823 spin_unlock_irq(&mchdev_lock
);
5827 EXPORT_SYMBOL_GPL(i915_gpu_lower
);
5830 * i915_gpu_busy - indicate GPU business to IPS
5832 * Tell the IPS driver whether or not the GPU is busy.
5834 bool i915_gpu_busy(void)
5836 struct drm_i915_private
*dev_priv
;
5837 struct intel_engine_cs
*ring
;
5841 spin_lock_irq(&mchdev_lock
);
5844 dev_priv
= i915_mch_dev
;
5846 for_each_ring(ring
, dev_priv
, i
)
5847 ret
|= !list_empty(&ring
->request_list
);
5850 spin_unlock_irq(&mchdev_lock
);
5854 EXPORT_SYMBOL_GPL(i915_gpu_busy
);
5857 * i915_gpu_turbo_disable - disable graphics turbo
5859 * Disable graphics turbo by resetting the max frequency and setting the
5860 * current frequency to the default.
5862 bool i915_gpu_turbo_disable(void)
5864 struct drm_i915_private
*dev_priv
;
5867 spin_lock_irq(&mchdev_lock
);
5868 if (!i915_mch_dev
) {
5872 dev_priv
= i915_mch_dev
;
5874 dev_priv
->ips
.max_delay
= dev_priv
->ips
.fstart
;
5876 if (!ironlake_set_drps(dev_priv
->dev
, dev_priv
->ips
.fstart
))
5880 spin_unlock_irq(&mchdev_lock
);
5884 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable
);
5887 * Tells the intel_ips driver that the i915 driver is now loaded, if
5888 * IPS got loaded first.
5890 * This awkward dance is so that neither module has to depend on the
5891 * other in order for IPS to do the appropriate communication of
5892 * GPU turbo limits to i915.
5895 ips_ping_for_i915_load(void)
5899 link
= symbol_get(ips_link_to_i915_driver
);
5902 symbol_put(ips_link_to_i915_driver
);
5906 void intel_gpu_ips_init(struct drm_i915_private
*dev_priv
)
5908 /* We only register the i915 ips part with intel-ips once everything is
5909 * set up, to avoid intel-ips sneaking in and reading bogus values. */
5910 spin_lock_irq(&mchdev_lock
);
5911 i915_mch_dev
= dev_priv
;
5912 spin_unlock_irq(&mchdev_lock
);
5914 ips_ping_for_i915_load();
5917 void intel_gpu_ips_teardown(void)
5919 spin_lock_irq(&mchdev_lock
);
5920 i915_mch_dev
= NULL
;
5921 spin_unlock_irq(&mchdev_lock
);
5924 static void intel_init_emon(struct drm_device
*dev
)
5926 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5931 /* Disable to program */
5935 /* Program energy weights for various events */
5936 I915_WRITE(SDEW
, 0x15040d00);
5937 I915_WRITE(CSIEW0
, 0x007f0000);
5938 I915_WRITE(CSIEW1
, 0x1e220004);
5939 I915_WRITE(CSIEW2
, 0x04000004);
5941 for (i
= 0; i
< 5; i
++)
5942 I915_WRITE(PEW(i
), 0);
5943 for (i
= 0; i
< 3; i
++)
5944 I915_WRITE(DEW(i
), 0);
5946 /* Program P-state weights to account for frequency power adjustment */
5947 for (i
= 0; i
< 16; i
++) {
5948 u32 pxvidfreq
= I915_READ(PXVFREQ(i
));
5949 unsigned long freq
= intel_pxfreq(pxvidfreq
);
5950 unsigned long vid
= (pxvidfreq
& PXVFREQ_PX_MASK
) >>
5955 val
*= (freq
/ 1000);
5957 val
/= (127*127*900);
5959 DRM_ERROR("bad pxval: %ld\n", val
);
5962 /* Render standby states get 0 weight */
5966 for (i
= 0; i
< 4; i
++) {
5967 u32 val
= (pxw
[i
*4] << 24) | (pxw
[(i
*4)+1] << 16) |
5968 (pxw
[(i
*4)+2] << 8) | (pxw
[(i
*4)+3]);
5969 I915_WRITE(PXW(i
), val
);
5972 /* Adjust magic regs to magic values (more experimental results) */
5973 I915_WRITE(OGW0
, 0);
5974 I915_WRITE(OGW1
, 0);
5975 I915_WRITE(EG0
, 0x00007f00);
5976 I915_WRITE(EG1
, 0x0000000e);
5977 I915_WRITE(EG2
, 0x000e0000);
5978 I915_WRITE(EG3
, 0x68000300);
5979 I915_WRITE(EG4
, 0x42000000);
5980 I915_WRITE(EG5
, 0x00140031);
5984 for (i
= 0; i
< 8; i
++)
5985 I915_WRITE(PXWL(i
), 0);
5987 /* Enable PMON + select events */
5988 I915_WRITE(ECR
, 0x80000019);
5990 lcfuse
= I915_READ(LCFUSE02
);
5992 dev_priv
->ips
.corr
= (lcfuse
& LCFUSE_HIV_MASK
);
5995 void intel_init_gt_powersave(struct drm_device
*dev
)
5997 i915
.enable_rc6
= sanitize_rc6_option(dev
, i915
.enable_rc6
);
5999 if (IS_CHERRYVIEW(dev
))
6000 cherryview_init_gt_powersave(dev
);
6001 else if (IS_VALLEYVIEW(dev
))
6002 valleyview_init_gt_powersave(dev
);
6005 void intel_cleanup_gt_powersave(struct drm_device
*dev
)
6007 if (IS_CHERRYVIEW(dev
))
6009 else if (IS_VALLEYVIEW(dev
))
6010 valleyview_cleanup_gt_powersave(dev
);
6013 static void gen6_suspend_rps(struct drm_device
*dev
)
6015 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6017 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
6019 gen6_disable_rps_interrupts(dev
);
6023 * intel_suspend_gt_powersave - suspend PM work and helper threads
6026 * We don't want to disable RC6 or other features here, we just want
6027 * to make sure any work we've queued has finished and won't bother
6028 * us while we're suspended.
6030 void intel_suspend_gt_powersave(struct drm_device
*dev
)
6032 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6034 if (INTEL_INFO(dev
)->gen
< 6)
6037 gen6_suspend_rps(dev
);
6039 /* Force GPU to min freq during suspend */
6040 gen6_rps_idle(dev_priv
);
6043 void intel_disable_gt_powersave(struct drm_device
*dev
)
6045 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6047 if (IS_IRONLAKE_M(dev
)) {
6048 ironlake_disable_drps(dev
);
6049 } else if (INTEL_INFO(dev
)->gen
>= 6) {
6050 intel_suspend_gt_powersave(dev
);
6052 mutex_lock(&dev_priv
->rps
.hw_lock
);
6053 if (INTEL_INFO(dev
)->gen
>= 9)
6054 gen9_disable_rps(dev
);
6055 else if (IS_CHERRYVIEW(dev
))
6056 cherryview_disable_rps(dev
);
6057 else if (IS_VALLEYVIEW(dev
))
6058 valleyview_disable_rps(dev
);
6060 gen6_disable_rps(dev
);
6062 dev_priv
->rps
.enabled
= false;
6063 mutex_unlock(&dev_priv
->rps
.hw_lock
);
6067 static void intel_gen6_powersave_work(struct work_struct
*work
)
6069 struct drm_i915_private
*dev_priv
=
6070 container_of(work
, struct drm_i915_private
,
6071 rps
.delayed_resume_work
.work
);
6072 struct drm_device
*dev
= dev_priv
->dev
;
6074 mutex_lock(&dev_priv
->rps
.hw_lock
);
6076 gen6_reset_rps_interrupts(dev
);
6078 if (IS_CHERRYVIEW(dev
)) {
6079 cherryview_enable_rps(dev
);
6080 } else if (IS_VALLEYVIEW(dev
)) {
6081 valleyview_enable_rps(dev
);
6082 } else if (INTEL_INFO(dev
)->gen
>= 9) {
6083 gen9_enable_rc6(dev
);
6084 gen9_enable_rps(dev
);
6085 if (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
))
6086 __gen6_update_ring_freq(dev
);
6087 } else if (IS_BROADWELL(dev
)) {
6088 gen8_enable_rps(dev
);
6089 __gen6_update_ring_freq(dev
);
6091 gen6_enable_rps(dev
);
6092 __gen6_update_ring_freq(dev
);
6095 WARN_ON(dev_priv
->rps
.max_freq
< dev_priv
->rps
.min_freq
);
6096 WARN_ON(dev_priv
->rps
.idle_freq
> dev_priv
->rps
.max_freq
);
6098 WARN_ON(dev_priv
->rps
.efficient_freq
< dev_priv
->rps
.min_freq
);
6099 WARN_ON(dev_priv
->rps
.efficient_freq
> dev_priv
->rps
.max_freq
);
6101 dev_priv
->rps
.enabled
= true;
6103 gen6_enable_rps_interrupts(dev
);
6105 mutex_unlock(&dev_priv
->rps
.hw_lock
);
6107 intel_runtime_pm_put(dev_priv
);
6110 void intel_enable_gt_powersave(struct drm_device
*dev
)
6112 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6114 /* Powersaving is controlled by the host when inside a VM */
6115 if (intel_vgpu_active(dev
))
6118 if (IS_IRONLAKE_M(dev
)) {
6119 mutex_lock(&dev
->struct_mutex
);
6120 ironlake_enable_drps(dev
);
6121 intel_init_emon(dev
);
6122 mutex_unlock(&dev
->struct_mutex
);
6123 } else if (INTEL_INFO(dev
)->gen
>= 6) {
6125 * PCU communication is slow and this doesn't need to be
6126 * done at any specific time, so do this out of our fast path
6127 * to make resume and init faster.
6129 * We depend on the HW RC6 power context save/restore
6130 * mechanism when entering D3 through runtime PM suspend. So
6131 * disable RPM until RPS/RC6 is properly setup. We can only
6132 * get here via the driver load/system resume/runtime resume
6133 * paths, so the _noresume version is enough (and in case of
6134 * runtime resume it's necessary).
6136 if (schedule_delayed_work(&dev_priv
->rps
.delayed_resume_work
,
6137 round_jiffies_up_relative(HZ
)))
6138 intel_runtime_pm_get_noresume(dev_priv
);
6142 void intel_reset_gt_powersave(struct drm_device
*dev
)
6144 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6146 if (INTEL_INFO(dev
)->gen
< 6)
6149 gen6_suspend_rps(dev
);
6150 dev_priv
->rps
.enabled
= false;
6153 static void ibx_init_clock_gating(struct drm_device
*dev
)
6155 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6158 * On Ibex Peak and Cougar Point, we need to disable clock
6159 * gating for the panel power sequencer or it will fail to
6160 * start up when no ports are active.
6162 I915_WRITE(SOUTH_DSPCLK_GATE_D
, PCH_DPLSUNIT_CLOCK_GATE_DISABLE
);
6165 static void g4x_disable_trickle_feed(struct drm_device
*dev
)
6167 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6170 for_each_pipe(dev_priv
, pipe
) {
6171 I915_WRITE(DSPCNTR(pipe
),
6172 I915_READ(DSPCNTR(pipe
)) |
6173 DISPPLANE_TRICKLE_FEED_DISABLE
);
6175 I915_WRITE(DSPSURF(pipe
), I915_READ(DSPSURF(pipe
)));
6176 POSTING_READ(DSPSURF(pipe
));
6180 static void ilk_init_lp_watermarks(struct drm_device
*dev
)
6182 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6184 I915_WRITE(WM3_LP_ILK
, I915_READ(WM3_LP_ILK
) & ~WM1_LP_SR_EN
);
6185 I915_WRITE(WM2_LP_ILK
, I915_READ(WM2_LP_ILK
) & ~WM1_LP_SR_EN
);
6186 I915_WRITE(WM1_LP_ILK
, I915_READ(WM1_LP_ILK
) & ~WM1_LP_SR_EN
);
6189 * Don't touch WM1S_LP_EN here.
6190 * Doing so could cause underruns.
6194 static void ironlake_init_clock_gating(struct drm_device
*dev
)
6196 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6197 uint32_t dspclk_gate
= ILK_VRHUNIT_CLOCK_GATE_DISABLE
;
6201 * WaFbcDisableDpfcClockGating:ilk
6203 dspclk_gate
|= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE
|
6204 ILK_DPFCUNIT_CLOCK_GATE_DISABLE
|
6205 ILK_DPFDUNIT_CLOCK_GATE_ENABLE
;
6207 I915_WRITE(PCH_3DCGDIS0
,
6208 MARIUNIT_CLOCK_GATE_DISABLE
|
6209 SVSMUNIT_CLOCK_GATE_DISABLE
);
6210 I915_WRITE(PCH_3DCGDIS1
,
6211 VFMUNIT_CLOCK_GATE_DISABLE
);
6214 * According to the spec the following bits should be set in
6215 * order to enable memory self-refresh
6216 * The bit 22/21 of 0x42004
6217 * The bit 5 of 0x42020
6218 * The bit 15 of 0x45000
6220 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
6221 (I915_READ(ILK_DISPLAY_CHICKEN2
) |
6222 ILK_DPARB_GATE
| ILK_VSDPFD_FULL
));
6223 dspclk_gate
|= ILK_DPARBUNIT_CLOCK_GATE_ENABLE
;
6224 I915_WRITE(DISP_ARB_CTL
,
6225 (I915_READ(DISP_ARB_CTL
) |
6228 ilk_init_lp_watermarks(dev
);
6231 * Based on the document from hardware guys the following bits
6232 * should be set unconditionally in order to enable FBC.
6233 * The bit 22 of 0x42000
6234 * The bit 22 of 0x42004
6235 * The bit 7,8,9 of 0x42020.
6237 if (IS_IRONLAKE_M(dev
)) {
6238 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6239 I915_WRITE(ILK_DISPLAY_CHICKEN1
,
6240 I915_READ(ILK_DISPLAY_CHICKEN1
) |
6242 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
6243 I915_READ(ILK_DISPLAY_CHICKEN2
) |
6247 I915_WRITE(ILK_DSPCLK_GATE_D
, dspclk_gate
);
6249 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
6250 I915_READ(ILK_DISPLAY_CHICKEN2
) |
6251 ILK_ELPIN_409_SELECT
);
6252 I915_WRITE(_3D_CHICKEN2
,
6253 _3D_CHICKEN2_WM_READ_PIPELINED
<< 16 |
6254 _3D_CHICKEN2_WM_READ_PIPELINED
);
6256 /* WaDisableRenderCachePipelinedFlush:ilk */
6257 I915_WRITE(CACHE_MODE_0
,
6258 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE
));
6260 /* WaDisable_RenderCache_OperationalFlush:ilk */
6261 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
6263 g4x_disable_trickle_feed(dev
);
6265 ibx_init_clock_gating(dev
);
6268 static void cpt_init_clock_gating(struct drm_device
*dev
)
6270 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6275 * On Ibex Peak and Cougar Point, we need to disable clock
6276 * gating for the panel power sequencer or it will fail to
6277 * start up when no ports are active.
6279 I915_WRITE(SOUTH_DSPCLK_GATE_D
, PCH_DPLSUNIT_CLOCK_GATE_DISABLE
|
6280 PCH_DPLUNIT_CLOCK_GATE_DISABLE
|
6281 PCH_CPUNIT_CLOCK_GATE_DISABLE
);
6282 I915_WRITE(SOUTH_CHICKEN2
, I915_READ(SOUTH_CHICKEN2
) |
6283 DPLS_EDP_PPS_FIX_DIS
);
6284 /* The below fixes the weird display corruption, a few pixels shifted
6285 * downward, on (only) LVDS of some HP laptops with IVY.
6287 for_each_pipe(dev_priv
, pipe
) {
6288 val
= I915_READ(TRANS_CHICKEN2(pipe
));
6289 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
6290 val
&= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED
;
6291 if (dev_priv
->vbt
.fdi_rx_polarity_inverted
)
6292 val
|= TRANS_CHICKEN2_FDI_POLARITY_REVERSED
;
6293 val
&= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK
;
6294 val
&= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER
;
6295 val
&= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH
;
6296 I915_WRITE(TRANS_CHICKEN2(pipe
), val
);
6298 /* WADP0ClockGatingDisable */
6299 for_each_pipe(dev_priv
, pipe
) {
6300 I915_WRITE(TRANS_CHICKEN1(pipe
),
6301 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE
);
6305 static void gen6_check_mch_setup(struct drm_device
*dev
)
6307 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6310 tmp
= I915_READ(MCH_SSKPD
);
6311 if ((tmp
& MCH_SSKPD_WM0_MASK
) != MCH_SSKPD_WM0_VAL
)
6312 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6316 static void gen6_init_clock_gating(struct drm_device
*dev
)
6318 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6319 uint32_t dspclk_gate
= ILK_VRHUNIT_CLOCK_GATE_DISABLE
;
6321 I915_WRITE(ILK_DSPCLK_GATE_D
, dspclk_gate
);
6323 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
6324 I915_READ(ILK_DISPLAY_CHICKEN2
) |
6325 ILK_ELPIN_409_SELECT
);
6327 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
6328 I915_WRITE(_3D_CHICKEN
,
6329 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB
));
6331 /* WaDisable_RenderCache_OperationalFlush:snb */
6332 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
6335 * BSpec recoomends 8x4 when MSAA is used,
6336 * however in practice 16x4 seems fastest.
6338 * Note that PS/WM thread counts depend on the WIZ hashing
6339 * disable bit, which we don't touch here, but it's good
6340 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6342 I915_WRITE(GEN6_GT_MODE
,
6343 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK
, GEN6_WIZ_HASHING_16x4
));
6345 ilk_init_lp_watermarks(dev
);
6347 I915_WRITE(CACHE_MODE_0
,
6348 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB
));
6350 I915_WRITE(GEN6_UCGCTL1
,
6351 I915_READ(GEN6_UCGCTL1
) |
6352 GEN6_BLBUNIT_CLOCK_GATE_DISABLE
|
6353 GEN6_CSUNIT_CLOCK_GATE_DISABLE
);
6355 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
6356 * gating disable must be set. Failure to set it results in
6357 * flickering pixels due to Z write ordering failures after
6358 * some amount of runtime in the Mesa "fire" demo, and Unigine
6359 * Sanctuary and Tropics, and apparently anything else with
6360 * alpha test or pixel discard.
6362 * According to the spec, bit 11 (RCCUNIT) must also be set,
6363 * but we didn't debug actual testcases to find it out.
6365 * WaDisableRCCUnitClockGating:snb
6366 * WaDisableRCPBUnitClockGating:snb
6368 I915_WRITE(GEN6_UCGCTL2
,
6369 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE
|
6370 GEN6_RCCUNIT_CLOCK_GATE_DISABLE
);
6372 /* WaStripsFansDisableFastClipPerformanceFix:snb */
6373 I915_WRITE(_3D_CHICKEN3
,
6374 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL
));
6378 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
6379 * 3DSTATE_SF number of SF output attributes is more than 16."
6381 I915_WRITE(_3D_CHICKEN3
,
6382 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH
));
6385 * According to the spec the following bits should be
6386 * set in order to enable memory self-refresh and fbc:
6387 * The bit21 and bit22 of 0x42000
6388 * The bit21 and bit22 of 0x42004
6389 * The bit5 and bit7 of 0x42020
6390 * The bit14 of 0x70180
6391 * The bit14 of 0x71180
6393 * WaFbcAsynchFlipDisableFbcQueue:snb
6395 I915_WRITE(ILK_DISPLAY_CHICKEN1
,
6396 I915_READ(ILK_DISPLAY_CHICKEN1
) |
6397 ILK_FBCQ_DIS
| ILK_PABSTRETCH_DIS
);
6398 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
6399 I915_READ(ILK_DISPLAY_CHICKEN2
) |
6400 ILK_DPARB_GATE
| ILK_VSDPFD_FULL
);
6401 I915_WRITE(ILK_DSPCLK_GATE_D
,
6402 I915_READ(ILK_DSPCLK_GATE_D
) |
6403 ILK_DPARBUNIT_CLOCK_GATE_ENABLE
|
6404 ILK_DPFDUNIT_CLOCK_GATE_ENABLE
);
6406 g4x_disable_trickle_feed(dev
);
6408 cpt_init_clock_gating(dev
);
6410 gen6_check_mch_setup(dev
);
6413 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private
*dev_priv
)
6415 uint32_t reg
= I915_READ(GEN7_FF_THREAD_MODE
);
6418 * WaVSThreadDispatchOverride:ivb,vlv
6420 * This actually overrides the dispatch
6421 * mode for all thread types.
6423 reg
&= ~GEN7_FF_SCHED_MASK
;
6424 reg
|= GEN7_FF_TS_SCHED_HW
;
6425 reg
|= GEN7_FF_VS_SCHED_HW
;
6426 reg
|= GEN7_FF_DS_SCHED_HW
;
6428 I915_WRITE(GEN7_FF_THREAD_MODE
, reg
);
6431 static void lpt_init_clock_gating(struct drm_device
*dev
)
6433 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6436 * TODO: this bit should only be enabled when really needed, then
6437 * disabled when not needed anymore in order to save power.
6439 if (HAS_PCH_LPT_LP(dev
))
6440 I915_WRITE(SOUTH_DSPCLK_GATE_D
,
6441 I915_READ(SOUTH_DSPCLK_GATE_D
) |
6442 PCH_LP_PARTITION_LEVEL_DISABLE
);
6444 /* WADPOClockGatingDisable:hsw */
6445 I915_WRITE(TRANS_CHICKEN1(PIPE_A
),
6446 I915_READ(TRANS_CHICKEN1(PIPE_A
)) |
6447 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE
);
6450 static void lpt_suspend_hw(struct drm_device
*dev
)
6452 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6454 if (HAS_PCH_LPT_LP(dev
)) {
6455 uint32_t val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
6457 val
&= ~PCH_LP_PARTITION_LEVEL_DISABLE
;
6458 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
6462 static void broadwell_init_clock_gating(struct drm_device
*dev
)
6464 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6468 ilk_init_lp_watermarks(dev
);
6470 /* WaSwitchSolVfFArbitrationPriority:bdw */
6471 I915_WRITE(GAM_ECOCHK
, I915_READ(GAM_ECOCHK
) | HSW_ECOCHK_ARB_PRIO_SOL
);
6473 /* WaPsrDPAMaskVBlankInSRD:bdw */
6474 I915_WRITE(CHICKEN_PAR1_1
,
6475 I915_READ(CHICKEN_PAR1_1
) | DPA_MASK_VBLANK_SRD
);
6477 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
6478 for_each_pipe(dev_priv
, pipe
) {
6479 I915_WRITE(CHICKEN_PIPESL_1(pipe
),
6480 I915_READ(CHICKEN_PIPESL_1(pipe
)) |
6481 BDW_DPRS_MASK_VBLANK_SRD
);
6484 /* WaVSRefCountFullforceMissDisable:bdw */
6485 /* WaDSRefCountFullforceMissDisable:bdw */
6486 I915_WRITE(GEN7_FF_THREAD_MODE
,
6487 I915_READ(GEN7_FF_THREAD_MODE
) &
6488 ~(GEN8_FF_DS_REF_CNT_FFME
| GEN7_FF_VS_REF_CNT_FFME
));
6490 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL
,
6491 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE
));
6493 /* WaDisableSDEUnitClockGating:bdw */
6494 I915_WRITE(GEN8_UCGCTL6
, I915_READ(GEN8_UCGCTL6
) |
6495 GEN8_SDEUNIT_CLOCK_GATE_DISABLE
);
6498 * WaProgramL3SqcReg1Default:bdw
6499 * WaTempDisableDOPClkGating:bdw
6501 misccpctl
= I915_READ(GEN7_MISCCPCTL
);
6502 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
& ~GEN7_DOP_CLOCK_GATE_ENABLE
);
6503 I915_WRITE(GEN8_L3SQCREG1
, BDW_WA_L3SQCREG1_DEFAULT
);
6504 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
);
6507 * WaGttCachingOffByDefault:bdw
6508 * GTT cache may not work with big pages, so if those
6509 * are ever enabled GTT cache may need to be disabled.
6511 I915_WRITE(HSW_GTT_CACHE_EN
, GTT_CACHE_EN_ALL
);
6513 lpt_init_clock_gating(dev
);
6516 static void haswell_init_clock_gating(struct drm_device
*dev
)
6518 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6520 ilk_init_lp_watermarks(dev
);
6522 /* L3 caching of data atomics doesn't work -- disable it. */
6523 I915_WRITE(HSW_SCRATCH1
, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE
);
6524 I915_WRITE(HSW_ROW_CHICKEN3
,
6525 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE
));
6527 /* This is required by WaCatErrorRejectionIssue:hsw */
6528 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
6529 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
6530 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
6532 /* WaVSRefCountFullforceMissDisable:hsw */
6533 I915_WRITE(GEN7_FF_THREAD_MODE
,
6534 I915_READ(GEN7_FF_THREAD_MODE
) & ~GEN7_FF_VS_REF_CNT_FFME
);
6536 /* WaDisable_RenderCache_OperationalFlush:hsw */
6537 I915_WRITE(CACHE_MODE_0_GEN7
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
6539 /* enable HiZ Raw Stall Optimization */
6540 I915_WRITE(CACHE_MODE_0_GEN7
,
6541 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE
));
6543 /* WaDisable4x2SubspanOptimization:hsw */
6544 I915_WRITE(CACHE_MODE_1
,
6545 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
));
6548 * BSpec recommends 8x4 when MSAA is used,
6549 * however in practice 16x4 seems fastest.
6551 * Note that PS/WM thread counts depend on the WIZ hashing
6552 * disable bit, which we don't touch here, but it's good
6553 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6555 I915_WRITE(GEN7_GT_MODE
,
6556 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK
, GEN6_WIZ_HASHING_16x4
));
6558 /* WaSampleCChickenBitEnable:hsw */
6559 I915_WRITE(HALF_SLICE_CHICKEN3
,
6560 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE
));
6562 /* WaSwitchSolVfFArbitrationPriority:hsw */
6563 I915_WRITE(GAM_ECOCHK
, I915_READ(GAM_ECOCHK
) | HSW_ECOCHK_ARB_PRIO_SOL
);
6565 /* WaRsPkgCStateDisplayPMReq:hsw */
6566 I915_WRITE(CHICKEN_PAR1_1
,
6567 I915_READ(CHICKEN_PAR1_1
) | FORCE_ARB_IDLE_PLANES
);
6569 lpt_init_clock_gating(dev
);
6572 static void ivybridge_init_clock_gating(struct drm_device
*dev
)
6574 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6577 ilk_init_lp_watermarks(dev
);
6579 I915_WRITE(ILK_DSPCLK_GATE_D
, ILK_VRHUNIT_CLOCK_GATE_DISABLE
);
6581 /* WaDisableEarlyCull:ivb */
6582 I915_WRITE(_3D_CHICKEN3
,
6583 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL
));
6585 /* WaDisableBackToBackFlipFix:ivb */
6586 I915_WRITE(IVB_CHICKEN3
,
6587 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE
|
6588 CHICKEN3_DGMG_DONE_FIX_DISABLE
);
6590 /* WaDisablePSDDualDispatchEnable:ivb */
6591 if (IS_IVB_GT1(dev
))
6592 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1
,
6593 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE
));
6595 /* WaDisable_RenderCache_OperationalFlush:ivb */
6596 I915_WRITE(CACHE_MODE_0_GEN7
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
6598 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6599 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1
,
6600 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC
);
6602 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6603 I915_WRITE(GEN7_L3CNTLREG1
,
6604 GEN7_WA_FOR_GEN7_L3_CONTROL
);
6605 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER
,
6606 GEN7_WA_L3_CHICKEN_MODE
);
6607 if (IS_IVB_GT1(dev
))
6608 I915_WRITE(GEN7_ROW_CHICKEN2
,
6609 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
6611 /* must write both registers */
6612 I915_WRITE(GEN7_ROW_CHICKEN2
,
6613 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
6614 I915_WRITE(GEN7_ROW_CHICKEN2_GT2
,
6615 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
6618 /* WaForceL3Serialization:ivb */
6619 I915_WRITE(GEN7_L3SQCREG4
, I915_READ(GEN7_L3SQCREG4
) &
6620 ~L3SQ_URB_READ_CAM_MATCH_DISABLE
);
6623 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6624 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
6626 I915_WRITE(GEN6_UCGCTL2
,
6627 GEN6_RCZUNIT_CLOCK_GATE_DISABLE
);
6629 /* This is required by WaCatErrorRejectionIssue:ivb */
6630 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
6631 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
6632 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
6634 g4x_disable_trickle_feed(dev
);
6636 gen7_setup_fixed_func_scheduler(dev_priv
);
6638 if (0) { /* causes HiZ corruption on ivb:gt1 */
6639 /* enable HiZ Raw Stall Optimization */
6640 I915_WRITE(CACHE_MODE_0_GEN7
,
6641 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE
));
6644 /* WaDisable4x2SubspanOptimization:ivb */
6645 I915_WRITE(CACHE_MODE_1
,
6646 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
));
6649 * BSpec recommends 8x4 when MSAA is used,
6650 * however in practice 16x4 seems fastest.
6652 * Note that PS/WM thread counts depend on the WIZ hashing
6653 * disable bit, which we don't touch here, but it's good
6654 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6656 I915_WRITE(GEN7_GT_MODE
,
6657 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK
, GEN6_WIZ_HASHING_16x4
));
6659 snpcr
= I915_READ(GEN6_MBCUNIT_SNPCR
);
6660 snpcr
&= ~GEN6_MBC_SNPCR_MASK
;
6661 snpcr
|= GEN6_MBC_SNPCR_MED
;
6662 I915_WRITE(GEN6_MBCUNIT_SNPCR
, snpcr
);
6664 if (!HAS_PCH_NOP(dev
))
6665 cpt_init_clock_gating(dev
);
6667 gen6_check_mch_setup(dev
);
6670 static void vlv_init_display_clock_gating(struct drm_i915_private
*dev_priv
)
6672 I915_WRITE(DSPCLK_GATE_D
, VRHUNIT_CLOCK_GATE_DISABLE
);
6675 * Disable trickle feed and enable pnd deadline calculation
6677 I915_WRITE(MI_ARB_VLV
, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
);
6678 I915_WRITE(CBR1_VLV
, 0);
6681 static void valleyview_init_clock_gating(struct drm_device
*dev
)
6683 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6685 vlv_init_display_clock_gating(dev_priv
);
6687 /* WaDisableEarlyCull:vlv */
6688 I915_WRITE(_3D_CHICKEN3
,
6689 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL
));
6691 /* WaDisableBackToBackFlipFix:vlv */
6692 I915_WRITE(IVB_CHICKEN3
,
6693 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE
|
6694 CHICKEN3_DGMG_DONE_FIX_DISABLE
);
6696 /* WaPsdDispatchEnable:vlv */
6697 /* WaDisablePSDDualDispatchEnable:vlv */
6698 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1
,
6699 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP
|
6700 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE
));
6702 /* WaDisable_RenderCache_OperationalFlush:vlv */
6703 I915_WRITE(CACHE_MODE_0_GEN7
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
6705 /* WaForceL3Serialization:vlv */
6706 I915_WRITE(GEN7_L3SQCREG4
, I915_READ(GEN7_L3SQCREG4
) &
6707 ~L3SQ_URB_READ_CAM_MATCH_DISABLE
);
6709 /* WaDisableDopClockGating:vlv */
6710 I915_WRITE(GEN7_ROW_CHICKEN2
,
6711 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
6713 /* This is required by WaCatErrorRejectionIssue:vlv */
6714 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
6715 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
6716 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
6718 gen7_setup_fixed_func_scheduler(dev_priv
);
6721 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6722 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
6724 I915_WRITE(GEN6_UCGCTL2
,
6725 GEN6_RCZUNIT_CLOCK_GATE_DISABLE
);
6727 /* WaDisableL3Bank2xClockGate:vlv
6728 * Disabling L3 clock gating- MMIO 940c[25] = 1
6729 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
6730 I915_WRITE(GEN7_UCGCTL4
,
6731 I915_READ(GEN7_UCGCTL4
) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE
);
6734 * BSpec says this must be set, even though
6735 * WaDisable4x2SubspanOptimization isn't listed for VLV.
6737 I915_WRITE(CACHE_MODE_1
,
6738 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
));
6741 * BSpec recommends 8x4 when MSAA is used,
6742 * however in practice 16x4 seems fastest.
6744 * Note that PS/WM thread counts depend on the WIZ hashing
6745 * disable bit, which we don't touch here, but it's good
6746 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6748 I915_WRITE(GEN7_GT_MODE
,
6749 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK
, GEN6_WIZ_HASHING_16x4
));
6752 * WaIncreaseL3CreditsForVLVB0:vlv
6753 * This is the hardware default actually.
6755 I915_WRITE(GEN7_L3SQCREG1
, VLV_B0_WA_L3SQCREG1_VALUE
);
6758 * WaDisableVLVClockGating_VBIIssue:vlv
6759 * Disable clock gating on th GCFG unit to prevent a delay
6760 * in the reporting of vblank events.
6762 I915_WRITE(VLV_GUNIT_CLOCK_GATE
, GCFG_DIS
);
6765 static void cherryview_init_clock_gating(struct drm_device
*dev
)
6767 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6769 vlv_init_display_clock_gating(dev_priv
);
6771 /* WaVSRefCountFullforceMissDisable:chv */
6772 /* WaDSRefCountFullforceMissDisable:chv */
6773 I915_WRITE(GEN7_FF_THREAD_MODE
,
6774 I915_READ(GEN7_FF_THREAD_MODE
) &
6775 ~(GEN8_FF_DS_REF_CNT_FFME
| GEN7_FF_VS_REF_CNT_FFME
));
6777 /* WaDisableSemaphoreAndSyncFlipWait:chv */
6778 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL
,
6779 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE
));
6781 /* WaDisableCSUnitClockGating:chv */
6782 I915_WRITE(GEN6_UCGCTL1
, I915_READ(GEN6_UCGCTL1
) |
6783 GEN6_CSUNIT_CLOCK_GATE_DISABLE
);
6785 /* WaDisableSDEUnitClockGating:chv */
6786 I915_WRITE(GEN8_UCGCTL6
, I915_READ(GEN8_UCGCTL6
) |
6787 GEN8_SDEUNIT_CLOCK_GATE_DISABLE
);
6790 * GTT cache may not work with big pages, so if those
6791 * are ever enabled GTT cache may need to be disabled.
6793 I915_WRITE(HSW_GTT_CACHE_EN
, GTT_CACHE_EN_ALL
);
6796 static void g4x_init_clock_gating(struct drm_device
*dev
)
6798 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6799 uint32_t dspclk_gate
;
6801 I915_WRITE(RENCLK_GATE_D1
, 0);
6802 I915_WRITE(RENCLK_GATE_D2
, VF_UNIT_CLOCK_GATE_DISABLE
|
6803 GS_UNIT_CLOCK_GATE_DISABLE
|
6804 CL_UNIT_CLOCK_GATE_DISABLE
);
6805 I915_WRITE(RAMCLK_GATE_D
, 0);
6806 dspclk_gate
= VRHUNIT_CLOCK_GATE_DISABLE
|
6807 OVRUNIT_CLOCK_GATE_DISABLE
|
6808 OVCUNIT_CLOCK_GATE_DISABLE
;
6810 dspclk_gate
|= DSSUNIT_CLOCK_GATE_DISABLE
;
6811 I915_WRITE(DSPCLK_GATE_D
, dspclk_gate
);
6813 /* WaDisableRenderCachePipelinedFlush */
6814 I915_WRITE(CACHE_MODE_0
,
6815 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE
));
6817 /* WaDisable_RenderCache_OperationalFlush:g4x */
6818 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
6820 g4x_disable_trickle_feed(dev
);
6823 static void crestline_init_clock_gating(struct drm_device
*dev
)
6825 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6827 I915_WRITE(RENCLK_GATE_D1
, I965_RCC_CLOCK_GATE_DISABLE
);
6828 I915_WRITE(RENCLK_GATE_D2
, 0);
6829 I915_WRITE(DSPCLK_GATE_D
, 0);
6830 I915_WRITE(RAMCLK_GATE_D
, 0);
6831 I915_WRITE16(DEUC
, 0);
6832 I915_WRITE(MI_ARB_STATE
,
6833 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
));
6835 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6836 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
6839 static void broadwater_init_clock_gating(struct drm_device
*dev
)
6841 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6843 I915_WRITE(RENCLK_GATE_D1
, I965_RCZ_CLOCK_GATE_DISABLE
|
6844 I965_RCC_CLOCK_GATE_DISABLE
|
6845 I965_RCPB_CLOCK_GATE_DISABLE
|
6846 I965_ISC_CLOCK_GATE_DISABLE
|
6847 I965_FBC_CLOCK_GATE_DISABLE
);
6848 I915_WRITE(RENCLK_GATE_D2
, 0);
6849 I915_WRITE(MI_ARB_STATE
,
6850 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
));
6852 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6853 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
6856 static void gen3_init_clock_gating(struct drm_device
*dev
)
6858 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6859 u32 dstate
= I915_READ(D_STATE
);
6861 dstate
|= DSTATE_PLL_D3_OFF
| DSTATE_GFX_CLOCK_GATING
|
6862 DSTATE_DOT_CLOCK_GATING
;
6863 I915_WRITE(D_STATE
, dstate
);
6865 if (IS_PINEVIEW(dev
))
6866 I915_WRITE(ECOSKPD
, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY
));
6868 /* IIR "flip pending" means done if this bit is set */
6869 I915_WRITE(ECOSKPD
, _MASKED_BIT_DISABLE(ECO_FLIP_DONE
));
6871 /* interrupts should cause a wake up from C3 */
6872 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN
));
6874 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
6875 I915_WRITE(MI_ARB_STATE
, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE
));
6877 I915_WRITE(MI_ARB_STATE
,
6878 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
));
6881 static void i85x_init_clock_gating(struct drm_device
*dev
)
6883 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6885 I915_WRITE(RENCLK_GATE_D1
, SV_CLOCK_GATE_DISABLE
);
6887 /* interrupts should cause a wake up from C3 */
6888 I915_WRITE(MI_STATE
, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN
) |
6889 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE
));
6891 I915_WRITE(MEM_MODE
,
6892 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE
));
6895 static void i830_init_clock_gating(struct drm_device
*dev
)
6897 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6899 I915_WRITE(DSPCLK_GATE_D
, OVRUNIT_CLOCK_GATE_DISABLE
);
6901 I915_WRITE(MEM_MODE
,
6902 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE
) |
6903 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE
));
6906 void intel_init_clock_gating(struct drm_device
*dev
)
6908 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6910 if (dev_priv
->display
.init_clock_gating
)
6911 dev_priv
->display
.init_clock_gating(dev
);
6914 void intel_suspend_hw(struct drm_device
*dev
)
6916 if (HAS_PCH_LPT(dev
))
6917 lpt_suspend_hw(dev
);
6920 /* Set up chip specific power management-related functions */
6921 void intel_init_pm(struct drm_device
*dev
)
6923 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6925 intel_fbc_init(dev_priv
);
6928 if (IS_PINEVIEW(dev
))
6929 i915_pineview_get_mem_freq(dev
);
6930 else if (IS_GEN5(dev
))
6931 i915_ironlake_get_mem_freq(dev
);
6933 /* For FIFO watermark updates */
6934 if (INTEL_INFO(dev
)->gen
>= 9) {
6935 skl_setup_wm_latency(dev
);
6937 if (IS_BROXTON(dev
))
6938 dev_priv
->display
.init_clock_gating
=
6939 bxt_init_clock_gating
;
6940 dev_priv
->display
.update_wm
= skl_update_wm
;
6941 } else if (HAS_PCH_SPLIT(dev
)) {
6942 ilk_setup_wm_latency(dev
);
6944 if ((IS_GEN5(dev
) && dev_priv
->wm
.pri_latency
[1] &&
6945 dev_priv
->wm
.spr_latency
[1] && dev_priv
->wm
.cur_latency
[1]) ||
6946 (!IS_GEN5(dev
) && dev_priv
->wm
.pri_latency
[0] &&
6947 dev_priv
->wm
.spr_latency
[0] && dev_priv
->wm
.cur_latency
[0])) {
6948 dev_priv
->display
.update_wm
= ilk_update_wm
;
6949 dev_priv
->display
.compute_pipe_wm
= ilk_compute_pipe_wm
;
6951 DRM_DEBUG_KMS("Failed to read display plane latency. "
6956 dev_priv
->display
.init_clock_gating
= ironlake_init_clock_gating
;
6957 else if (IS_GEN6(dev
))
6958 dev_priv
->display
.init_clock_gating
= gen6_init_clock_gating
;
6959 else if (IS_IVYBRIDGE(dev
))
6960 dev_priv
->display
.init_clock_gating
= ivybridge_init_clock_gating
;
6961 else if (IS_HASWELL(dev
))
6962 dev_priv
->display
.init_clock_gating
= haswell_init_clock_gating
;
6963 else if (INTEL_INFO(dev
)->gen
== 8)
6964 dev_priv
->display
.init_clock_gating
= broadwell_init_clock_gating
;
6965 } else if (IS_CHERRYVIEW(dev
)) {
6966 vlv_setup_wm_latency(dev
);
6968 dev_priv
->display
.update_wm
= vlv_update_wm
;
6969 dev_priv
->display
.init_clock_gating
=
6970 cherryview_init_clock_gating
;
6971 } else if (IS_VALLEYVIEW(dev
)) {
6972 vlv_setup_wm_latency(dev
);
6974 dev_priv
->display
.update_wm
= vlv_update_wm
;
6975 dev_priv
->display
.init_clock_gating
=
6976 valleyview_init_clock_gating
;
6977 } else if (IS_PINEVIEW(dev
)) {
6978 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev
),
6981 dev_priv
->mem_freq
)) {
6982 DRM_INFO("failed to find known CxSR latency "
6983 "(found ddr%s fsb freq %d, mem freq %d), "
6985 (dev_priv
->is_ddr3
== 1) ? "3" : "2",
6986 dev_priv
->fsb_freq
, dev_priv
->mem_freq
);
6987 /* Disable CxSR and never update its watermark again */
6988 intel_set_memory_cxsr(dev_priv
, false);
6989 dev_priv
->display
.update_wm
= NULL
;
6991 dev_priv
->display
.update_wm
= pineview_update_wm
;
6992 dev_priv
->display
.init_clock_gating
= gen3_init_clock_gating
;
6993 } else if (IS_G4X(dev
)) {
6994 dev_priv
->display
.update_wm
= g4x_update_wm
;
6995 dev_priv
->display
.init_clock_gating
= g4x_init_clock_gating
;
6996 } else if (IS_GEN4(dev
)) {
6997 dev_priv
->display
.update_wm
= i965_update_wm
;
6998 if (IS_CRESTLINE(dev
))
6999 dev_priv
->display
.init_clock_gating
= crestline_init_clock_gating
;
7000 else if (IS_BROADWATER(dev
))
7001 dev_priv
->display
.init_clock_gating
= broadwater_init_clock_gating
;
7002 } else if (IS_GEN3(dev
)) {
7003 dev_priv
->display
.update_wm
= i9xx_update_wm
;
7004 dev_priv
->display
.get_fifo_size
= i9xx_get_fifo_size
;
7005 dev_priv
->display
.init_clock_gating
= gen3_init_clock_gating
;
7006 } else if (IS_GEN2(dev
)) {
7007 if (INTEL_INFO(dev
)->num_pipes
== 1) {
7008 dev_priv
->display
.update_wm
= i845_update_wm
;
7009 dev_priv
->display
.get_fifo_size
= i845_get_fifo_size
;
7011 dev_priv
->display
.update_wm
= i9xx_update_wm
;
7012 dev_priv
->display
.get_fifo_size
= i830_get_fifo_size
;
7015 if (IS_I85X(dev
) || IS_I865G(dev
))
7016 dev_priv
->display
.init_clock_gating
= i85x_init_clock_gating
;
7018 dev_priv
->display
.init_clock_gating
= i830_init_clock_gating
;
7020 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
7024 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u32 mbox
, u32
*val
)
7026 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
7028 if (I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) {
7029 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7033 I915_WRITE(GEN6_PCODE_DATA
, *val
);
7034 I915_WRITE(GEN6_PCODE_DATA1
, 0);
7035 I915_WRITE(GEN6_PCODE_MAILBOX
, GEN6_PCODE_READY
| mbox
);
7037 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) == 0,
7039 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox
);
7043 *val
= I915_READ(GEN6_PCODE_DATA
);
7044 I915_WRITE(GEN6_PCODE_DATA
, 0);
7049 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
, u32 mbox
, u32 val
)
7051 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
7053 if (I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) {
7054 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7058 I915_WRITE(GEN6_PCODE_DATA
, val
);
7059 I915_WRITE(GEN6_PCODE_MAILBOX
, GEN6_PCODE_READY
| mbox
);
7061 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) == 0,
7063 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox
);
7067 I915_WRITE(GEN6_PCODE_DATA
, 0);
7072 static int vlv_gpu_freq_div(unsigned int czclk_freq
)
7074 switch (czclk_freq
) {
7089 static int byt_gpu_freq(struct drm_i915_private
*dev_priv
, int val
)
7091 int div
, czclk_freq
= DIV_ROUND_CLOSEST(dev_priv
->czclk_freq
, 1000);
7093 div
= vlv_gpu_freq_div(czclk_freq
);
7097 return DIV_ROUND_CLOSEST(czclk_freq
* (val
+ 6 - 0xbd), div
);
7100 static int byt_freq_opcode(struct drm_i915_private
*dev_priv
, int val
)
7102 int mul
, czclk_freq
= DIV_ROUND_CLOSEST(dev_priv
->czclk_freq
, 1000);
7104 mul
= vlv_gpu_freq_div(czclk_freq
);
7108 return DIV_ROUND_CLOSEST(mul
* val
, czclk_freq
) + 0xbd - 6;
7111 static int chv_gpu_freq(struct drm_i915_private
*dev_priv
, int val
)
7113 int div
, czclk_freq
= DIV_ROUND_CLOSEST(dev_priv
->czclk_freq
, 1000);
7115 div
= vlv_gpu_freq_div(czclk_freq
) / 2;
7119 return DIV_ROUND_CLOSEST(czclk_freq
* val
, 2 * div
) / 2;
7122 static int chv_freq_opcode(struct drm_i915_private
*dev_priv
, int val
)
7124 int mul
, czclk_freq
= DIV_ROUND_CLOSEST(dev_priv
->czclk_freq
, 1000);
7126 mul
= vlv_gpu_freq_div(czclk_freq
) / 2;
7130 /* CHV needs even values */
7131 return DIV_ROUND_CLOSEST(val
* 2 * mul
, czclk_freq
) * 2;
7134 int intel_gpu_freq(struct drm_i915_private
*dev_priv
, int val
)
7136 if (IS_GEN9(dev_priv
->dev
))
7137 return (val
* GT_FREQUENCY_MULTIPLIER
) / GEN9_FREQ_SCALER
;
7138 else if (IS_CHERRYVIEW(dev_priv
->dev
))
7139 return chv_gpu_freq(dev_priv
, val
);
7140 else if (IS_VALLEYVIEW(dev_priv
->dev
))
7141 return byt_gpu_freq(dev_priv
, val
);
7143 return val
* GT_FREQUENCY_MULTIPLIER
;
7146 int intel_freq_opcode(struct drm_i915_private
*dev_priv
, int val
)
7148 if (IS_GEN9(dev_priv
->dev
))
7149 return (val
* GEN9_FREQ_SCALER
) / GT_FREQUENCY_MULTIPLIER
;
7150 else if (IS_CHERRYVIEW(dev_priv
->dev
))
7151 return chv_freq_opcode(dev_priv
, val
);
7152 else if (IS_VALLEYVIEW(dev_priv
->dev
))
7153 return byt_freq_opcode(dev_priv
, val
);
7155 return val
/ GT_FREQUENCY_MULTIPLIER
;
7158 struct request_boost
{
7159 struct work_struct work
;
7160 struct drm_i915_gem_request
*req
;
7163 static void __intel_rps_boost_work(struct work_struct
*work
)
7165 struct request_boost
*boost
= container_of(work
, struct request_boost
, work
);
7166 struct drm_i915_gem_request
*req
= boost
->req
;
7168 if (!i915_gem_request_completed(req
, true))
7169 gen6_rps_boost(to_i915(req
->ring
->dev
), NULL
,
7170 req
->emitted_jiffies
);
7172 i915_gem_request_unreference__unlocked(req
);
7176 void intel_queue_rps_boost_for_request(struct drm_device
*dev
,
7177 struct drm_i915_gem_request
*req
)
7179 struct request_boost
*boost
;
7181 if (req
== NULL
|| INTEL_INFO(dev
)->gen
< 6)
7184 if (i915_gem_request_completed(req
, true))
7187 boost
= kmalloc(sizeof(*boost
), GFP_ATOMIC
);
7191 i915_gem_request_reference(req
);
7194 INIT_WORK(&boost
->work
, __intel_rps_boost_work
);
7195 queue_work(to_i915(dev
)->wq
, &boost
->work
);
7198 void intel_pm_setup(struct drm_device
*dev
)
7200 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7202 mutex_init(&dev_priv
->rps
.hw_lock
);
7203 spin_lock_init(&dev_priv
->rps
.client_lock
);
7205 INIT_DELAYED_WORK(&dev_priv
->rps
.delayed_resume_work
,
7206 intel_gen6_powersave_work
);
7207 INIT_LIST_HEAD(&dev_priv
->rps
.clients
);
7208 INIT_LIST_HEAD(&dev_priv
->rps
.semaphores
.link
);
7209 INIT_LIST_HEAD(&dev_priv
->rps
.mmioflips
.link
);
7211 dev_priv
->pm
.suspended
= false;