projects / deliverable / linux.git / blob
? search:


e398963797a60b77fb65e636bceddd63648ef0a0
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_pm.c
1 /*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28 #include <linux/cpufreq.h>
29 #include "i915_drv.h"
30 #include "intel_drv.h"
31 #include "../../../platform/x86/intel_ips.h"
32 #include <linux/module.h>
33
34 #define FORCEWAKE_ACK_TIMEOUT_MS 2
35
36 /* FBC, or Frame Buffer Compression, is a technique employed to compress the
37 * framebuffer contents in-memory, aiming at reducing the required bandwidth
38 * during in-memory transfers and, therefore, reduce the power packet.
39 *
40 * The benefits of FBC are mostly visible with solid backgrounds and
41 * variation-less patterns.
42 *
43 * FBC-related functionality can be enabled by the means of the
44 * i915.i915_enable_fbc parameter
45 */
46
47 static bool intel_crtc_active(struct drm_crtc *crtc)
48 {
49 /* Be paranoid as we can arrive here with only partial
50 * state retrieved from the hardware during setup.
51 */
52 return to_intel_crtc(crtc)->active && crtc->fb && crtc->mode.clock;
53 }
54
55 static void i8xx_disable_fbc(struct drm_device *dev)
56 {
57 struct drm_i915_private *dev_priv = dev->dev_private;
58 u32 fbc_ctl;
59
60 /* Disable compression */
61 fbc_ctl = I915_READ(FBC_CONTROL);
62 if ((fbc_ctl & FBC_CTL_EN) == 0)
63 return;
64
65 fbc_ctl &= ~FBC_CTL_EN;
66 I915_WRITE(FBC_CONTROL, fbc_ctl);
67
68 /* Wait for compressing bit to clear */
69 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
70 DRM_DEBUG_KMS("FBC idle timed out\n");
71 return;
72 }
73
74 DRM_DEBUG_KMS("disabled FBC\n");
75 }
76
77 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
78 {
79 struct drm_device *dev = crtc->dev;
80 struct drm_i915_private *dev_priv = dev->dev_private;
81 struct drm_framebuffer *fb = crtc->fb;
82 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
83 struct drm_i915_gem_object *obj = intel_fb->obj;
84 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
85 int cfb_pitch;
86 int plane, i;
87 u32 fbc_ctl, fbc_ctl2;
88
89 cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
90 if (fb->pitches[0] < cfb_pitch)
91 cfb_pitch = fb->pitches[0];
92
93 /* FBC_CTL wants 64B units */
94 cfb_pitch = (cfb_pitch / 64) - 1;
95 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
96
97 /* Clear old tags */
98 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
99 I915_WRITE(FBC_TAG + (i * 4), 0);
100
101 /* Set it up... */
102 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
103 fbc_ctl2 |= plane;
104 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
105 I915_WRITE(FBC_FENCE_OFF, crtc->y);
106
107 /* enable it... */
108 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
109 if (IS_I945GM(dev))
110 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
111 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
112 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
113 fbc_ctl |= obj->fence_reg;
114 I915_WRITE(FBC_CONTROL, fbc_ctl);
115
116 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c, ",
117 cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
118 }
119
120 static bool i8xx_fbc_enabled(struct drm_device *dev)
121 {
122 struct drm_i915_private *dev_priv = dev->dev_private;
123
124 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
125 }
126
127 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
128 {
129 struct drm_device *dev = crtc->dev;
130 struct drm_i915_private *dev_priv = dev->dev_private;
131 struct drm_framebuffer *fb = crtc->fb;
132 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
133 struct drm_i915_gem_object *obj = intel_fb->obj;
134 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
135 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
136 unsigned long stall_watermark = 200;
137 u32 dpfc_ctl;
138
139 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
140 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
141 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
142
143 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
144 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
145 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
146 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
147
148 /* enable it... */
149 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
150
151 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
152 }
153
154 static void g4x_disable_fbc(struct drm_device *dev)
155 {
156 struct drm_i915_private *dev_priv = dev->dev_private;
157 u32 dpfc_ctl;
158
159 /* Disable compression */
160 dpfc_ctl = I915_READ(DPFC_CONTROL);
161 if (dpfc_ctl & DPFC_CTL_EN) {
162 dpfc_ctl &= ~DPFC_CTL_EN;
163 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
164
165 DRM_DEBUG_KMS("disabled FBC\n");
166 }
167 }
168
169 static bool g4x_fbc_enabled(struct drm_device *dev)
170 {
171 struct drm_i915_private *dev_priv = dev->dev_private;
172
173 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
174 }
175
176 static void sandybridge_blit_fbc_update(struct drm_device *dev)
177 {
178 struct drm_i915_private *dev_priv = dev->dev_private;
179 u32 blt_ecoskpd;
180
181 /* Make sure blitter notifies FBC of writes */
182 gen6_gt_force_wake_get(dev_priv);
183 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
184 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
185 GEN6_BLITTER_LOCK_SHIFT;
186 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
187 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
188 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
189 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
190 GEN6_BLITTER_LOCK_SHIFT);
191 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
192 POSTING_READ(GEN6_BLITTER_ECOSKPD);
193 gen6_gt_force_wake_put(dev_priv);
194 }
195
196 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
197 {
198 struct drm_device *dev = crtc->dev;
199 struct drm_i915_private *dev_priv = dev->dev_private;
200 struct drm_framebuffer *fb = crtc->fb;
201 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
202 struct drm_i915_gem_object *obj = intel_fb->obj;
203 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
204 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
205 unsigned long stall_watermark = 200;
206 u32 dpfc_ctl;
207
208 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
209 dpfc_ctl &= DPFC_RESERVED;
210 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
211 /* Set persistent mode for front-buffer rendering, ala X. */
212 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
213 dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
214 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
215
216 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
217 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
218 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
219 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
220 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
221 /* enable it... */
222 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
223
224 if (IS_GEN6(dev)) {
225 I915_WRITE(SNB_DPFC_CTL_SA,
226 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
227 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
228 sandybridge_blit_fbc_update(dev);
229 }
230
231 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
232 }
233
234 static void ironlake_disable_fbc(struct drm_device *dev)
235 {
236 struct drm_i915_private *dev_priv = dev->dev_private;
237 u32 dpfc_ctl;
238
239 /* Disable compression */
240 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
241 if (dpfc_ctl & DPFC_CTL_EN) {
242 dpfc_ctl &= ~DPFC_CTL_EN;
243 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
244
245 DRM_DEBUG_KMS("disabled FBC\n");
246 }
247 }
248
249 static bool ironlake_fbc_enabled(struct drm_device *dev)
250 {
251 struct drm_i915_private *dev_priv = dev->dev_private;
252
253 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
254 }
255
256 static void gen7_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
257 {
258 struct drm_device *dev = crtc->dev;
259 struct drm_i915_private *dev_priv = dev->dev_private;
260 struct drm_framebuffer *fb = crtc->fb;
261 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
262 struct drm_i915_gem_object *obj = intel_fb->obj;
263 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
264
265 I915_WRITE(IVB_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
266
267 I915_WRITE(ILK_DPFC_CONTROL, DPFC_CTL_EN | DPFC_CTL_LIMIT_1X |
268 IVB_DPFC_CTL_FENCE_EN |
269 intel_crtc->plane << IVB_DPFC_CTL_PLANE_SHIFT);
270
271 I915_WRITE(SNB_DPFC_CTL_SA,
272 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
273 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
274
275 sandybridge_blit_fbc_update(dev);
276
277 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
278 }
279
280 bool intel_fbc_enabled(struct drm_device *dev)
281 {
282 struct drm_i915_private *dev_priv = dev->dev_private;
283
284 if (!dev_priv->display.fbc_enabled)
285 return false;
286
287 return dev_priv->display.fbc_enabled(dev);
288 }
289
290 static void intel_fbc_work_fn(struct work_struct *__work)
291 {
292 struct intel_fbc_work *work =
293 container_of(to_delayed_work(__work),
294 struct intel_fbc_work, work);
295 struct drm_device *dev = work->crtc->dev;
296 struct drm_i915_private *dev_priv = dev->dev_private;
297
298 mutex_lock(&dev->struct_mutex);
299 if (work == dev_priv->fbc_work) {
300 /* Double check that we haven't switched fb without cancelling
301 * the prior work.
302 */
303 if (work->crtc->fb == work->fb) {
304 dev_priv->display.enable_fbc(work->crtc,
305 work->interval);
306
307 dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
308 dev_priv->cfb_fb = work->crtc->fb->base.id;
309 dev_priv->cfb_y = work->crtc->y;
310 }
311
312 dev_priv->fbc_work = NULL;
313 }
314 mutex_unlock(&dev->struct_mutex);
315
316 kfree(work);
317 }
318
319 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
320 {
321 if (dev_priv->fbc_work == NULL)
322 return;
323
324 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
325
326 /* Synchronisation is provided by struct_mutex and checking of
327 * dev_priv->fbc_work, so we can perform the cancellation
328 * entirely asynchronously.
329 */
330 if (cancel_delayed_work(&dev_priv->fbc_work->work))
331 /* tasklet was killed before being run, clean up */
332 kfree(dev_priv->fbc_work);
333
334 /* Mark the work as no longer wanted so that if it does
335 * wake-up (because the work was already running and waiting
336 * for our mutex), it will discover that is no longer
337 * necessary to run.
338 */
339 dev_priv->fbc_work = NULL;
340 }
341
342 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
343 {
344 struct intel_fbc_work *work;
345 struct drm_device *dev = crtc->dev;
346 struct drm_i915_private *dev_priv = dev->dev_private;
347
348 if (!dev_priv->display.enable_fbc)
349 return;
350
351 intel_cancel_fbc_work(dev_priv);
352
353 work = kzalloc(sizeof *work, GFP_KERNEL);
354 if (work == NULL) {
355 dev_priv->display.enable_fbc(crtc, interval);
356 return;
357 }
358
359 work->crtc = crtc;
360 work->fb = crtc->fb;
361 work->interval = interval;
362 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
363
364 dev_priv->fbc_work = work;
365
366 DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
367
368 /* Delay the actual enabling to let pageflipping cease and the
369 * display to settle before starting the compression. Note that
370 * this delay also serves a second purpose: it allows for a
371 * vblank to pass after disabling the FBC before we attempt
372 * to modify the control registers.
373 *
374 * A more complicated solution would involve tracking vblanks
375 * following the termination of the page-flipping sequence
376 * and indeed performing the enable as a co-routine and not
377 * waiting synchronously upon the vblank.
378 */
379 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
380 }
381
382 void intel_disable_fbc(struct drm_device *dev)
383 {
384 struct drm_i915_private *dev_priv = dev->dev_private;
385
386 intel_cancel_fbc_work(dev_priv);
387
388 if (!dev_priv->display.disable_fbc)
389 return;
390
391 dev_priv->display.disable_fbc(dev);
392 dev_priv->cfb_plane = -1;
393 }
394
395 /**
396 * intel_update_fbc - enable/disable FBC as needed
397 * @dev: the drm_device
398 *
399 * Set up the framebuffer compression hardware at mode set time. We
400 * enable it if possible:
401 * - plane A only (on pre-965)
402 * - no pixel mulitply/line duplication
403 * - no alpha buffer discard
404 * - no dual wide
405 * - framebuffer <= 2048 in width, 1536 in height
406 *
407 * We can't assume that any compression will take place (worst case),
408 * so the compressed buffer has to be the same size as the uncompressed
409 * one. It also must reside (along with the line length buffer) in
410 * stolen memory.
411 *
412 * We need to enable/disable FBC on a global basis.
413 */
414 void intel_update_fbc(struct drm_device *dev)
415 {
416 struct drm_i915_private *dev_priv = dev->dev_private;
417 struct drm_crtc *crtc = NULL, *tmp_crtc;
418 struct intel_crtc *intel_crtc;
419 struct drm_framebuffer *fb;
420 struct intel_framebuffer *intel_fb;
421 struct drm_i915_gem_object *obj;
422 int enable_fbc;
423
424 if (!i915_powersave)
425 return;
426
427 if (!I915_HAS_FBC(dev))
428 return;
429
430 /*
431 * If FBC is already on, we just have to verify that we can
432 * keep it that way...
433 * Need to disable if:
434 * - more than one pipe is active
435 * - changing FBC params (stride, fence, mode)
436 * - new fb is too large to fit in compressed buffer
437 * - going to an unsupported config (interlace, pixel multiply, etc.)
438 */
439 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
440 if (intel_crtc_active(tmp_crtc) &&
441 !to_intel_crtc(tmp_crtc)->primary_disabled) {
442 if (crtc) {
443 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
444 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
445 goto out_disable;
446 }
447 crtc = tmp_crtc;
448 }
449 }
450
451 if (!crtc || crtc->fb == NULL) {
452 DRM_DEBUG_KMS("no output, disabling\n");
453 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
454 goto out_disable;
455 }
456
457 intel_crtc = to_intel_crtc(crtc);
458 fb = crtc->fb;
459 intel_fb = to_intel_framebuffer(fb);
460 obj = intel_fb->obj;
461
462 enable_fbc = i915_enable_fbc;
463 if (enable_fbc < 0) {
464 DRM_DEBUG_KMS("fbc set to per-chip default\n");
465 enable_fbc = 1;
466 if (INTEL_INFO(dev)->gen <= 7)
467 enable_fbc = 0;
468 }
469 if (!enable_fbc) {
470 DRM_DEBUG_KMS("fbc disabled per module param\n");
471 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
472 goto out_disable;
473 }
474 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
475 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
476 DRM_DEBUG_KMS("mode incompatible with compression, "
477 "disabling\n");
478 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
479 goto out_disable;
480 }
481 if ((crtc->mode.hdisplay > 2048) ||
482 (crtc->mode.vdisplay > 1536)) {
483 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
484 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
485 goto out_disable;
486 }
487 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
488 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
489 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
490 goto out_disable;
491 }
492
493 /* The use of a CPU fence is mandatory in order to detect writes
494 * by the CPU to the scanout and trigger updates to the FBC.
495 */
496 if (obj->tiling_mode != I915_TILING_X ||
497 obj->fence_reg == I915_FENCE_REG_NONE) {
498 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
499 dev_priv->no_fbc_reason = FBC_NOT_TILED;
500 goto out_disable;
501 }
502
503 /* If the kernel debugger is active, always disable compression */
504 if (in_dbg_master())
505 goto out_disable;
506
507 if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) {
508 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
509 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
510 goto out_disable;
511 }
512
513 /* If the scanout has not changed, don't modify the FBC settings.
514 * Note that we make the fundamental assumption that the fb->obj
515 * cannot be unpinned (and have its GTT offset and fence revoked)
516 * without first being decoupled from the scanout and FBC disabled.
517 */
518 if (dev_priv->cfb_plane == intel_crtc->plane &&
519 dev_priv->cfb_fb == fb->base.id &&
520 dev_priv->cfb_y == crtc->y)
521 return;
522
523 if (intel_fbc_enabled(dev)) {
524 /* We update FBC along two paths, after changing fb/crtc
525 * configuration (modeswitching) and after page-flipping
526 * finishes. For the latter, we know that not only did
527 * we disable the FBC at the start of the page-flip
528 * sequence, but also more than one vblank has passed.
529 *
530 * For the former case of modeswitching, it is possible
531 * to switch between two FBC valid configurations
532 * instantaneously so we do need to disable the FBC
533 * before we can modify its control registers. We also
534 * have to wait for the next vblank for that to take
535 * effect. However, since we delay enabling FBC we can
536 * assume that a vblank has passed since disabling and
537 * that we can safely alter the registers in the deferred
538 * callback.
539 *
540 * In the scenario that we go from a valid to invalid
541 * and then back to valid FBC configuration we have
542 * no strict enforcement that a vblank occurred since
543 * disabling the FBC. However, along all current pipe
544 * disabling paths we do need to wait for a vblank at
545 * some point. And we wait before enabling FBC anyway.
546 */
547 DRM_DEBUG_KMS("disabling active FBC for update\n");
548 intel_disable_fbc(dev);
549 }
550
551 intel_enable_fbc(crtc, 500);
552 return;
553
554 out_disable:
555 /* Multiple disables should be harmless */
556 if (intel_fbc_enabled(dev)) {
557 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
558 intel_disable_fbc(dev);
559 }
560 i915_gem_stolen_cleanup_compression(dev);
561 }
562
563 static void i915_pineview_get_mem_freq(struct drm_device *dev)
564 {
565 drm_i915_private_t *dev_priv = dev->dev_private;
566 u32 tmp;
567
568 tmp = I915_READ(CLKCFG);
569
570 switch (tmp & CLKCFG_FSB_MASK) {
571 case CLKCFG_FSB_533:
572 dev_priv->fsb_freq = 533; /* 133*4 */
573 break;
574 case CLKCFG_FSB_800:
575 dev_priv->fsb_freq = 800; /* 200*4 */
576 break;
577 case CLKCFG_FSB_667:
578 dev_priv->fsb_freq = 667; /* 167*4 */
579 break;
580 case CLKCFG_FSB_400:
581 dev_priv->fsb_freq = 400; /* 100*4 */
582 break;
583 }
584
585 switch (tmp & CLKCFG_MEM_MASK) {
586 case CLKCFG_MEM_533:
587 dev_priv->mem_freq = 533;
588 break;
589 case CLKCFG_MEM_667:
590 dev_priv->mem_freq = 667;
591 break;
592 case CLKCFG_MEM_800:
593 dev_priv->mem_freq = 800;
594 break;
595 }
596
597 /* detect pineview DDR3 setting */
598 tmp = I915_READ(CSHRDDR3CTL);
599 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
600 }
601
602 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
603 {
604 drm_i915_private_t *dev_priv = dev->dev_private;
605 u16 ddrpll, csipll;
606
607 ddrpll = I915_READ16(DDRMPLL1);
608 csipll = I915_READ16(CSIPLL0);
609
610 switch (ddrpll & 0xff) {
611 case 0xc:
612 dev_priv->mem_freq = 800;
613 break;
614 case 0x10:
615 dev_priv->mem_freq = 1066;
616 break;
617 case 0x14:
618 dev_priv->mem_freq = 1333;
619 break;
620 case 0x18:
621 dev_priv->mem_freq = 1600;
622 break;
623 default:
624 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
625 ddrpll & 0xff);
626 dev_priv->mem_freq = 0;
627 break;
628 }
629
630 dev_priv->ips.r_t = dev_priv->mem_freq;
631
632 switch (csipll & 0x3ff) {
633 case 0x00c:
634 dev_priv->fsb_freq = 3200;
635 break;
636 case 0x00e:
637 dev_priv->fsb_freq = 3733;
638 break;
639 case 0x010:
640 dev_priv->fsb_freq = 4266;
641 break;
642 case 0x012:
643 dev_priv->fsb_freq = 4800;
644 break;
645 case 0x014:
646 dev_priv->fsb_freq = 5333;
647 break;
648 case 0x016:
649 dev_priv->fsb_freq = 5866;
650 break;
651 case 0x018:
652 dev_priv->fsb_freq = 6400;
653 break;
654 default:
655 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
656 csipll & 0x3ff);
657 dev_priv->fsb_freq = 0;
658 break;
659 }
660
661 if (dev_priv->fsb_freq == 3200) {
662 dev_priv->ips.c_m = 0;
663 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
664 dev_priv->ips.c_m = 1;
665 } else {
666 dev_priv->ips.c_m = 2;
667 }
668 }
669
670 static const struct cxsr_latency cxsr_latency_table[] = {
671 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
672 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
673 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
674 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
675 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
676
677 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
678 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
679 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
680 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
681 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
682
683 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
684 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
685 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
686 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
687 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
688
689 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
690 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
691 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
692 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
693 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
694
695 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
696 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
697 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
698 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
699 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
700
701 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
702 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
703 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
704 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
705 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
706 };
707
708 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
709 int is_ddr3,
710 int fsb,
711 int mem)
712 {
713 const struct cxsr_latency *latency;
714 int i;
715
716 if (fsb == 0 || mem == 0)
717 return NULL;
718
719 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
720 latency = &cxsr_latency_table[i];
721 if (is_desktop == latency->is_desktop &&
722 is_ddr3 == latency->is_ddr3 &&
723 fsb == latency->fsb_freq && mem == latency->mem_freq)
724 return latency;
725 }
726
727 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
728
729 return NULL;
730 }
731
732 static void pineview_disable_cxsr(struct drm_device *dev)
733 {
734 struct drm_i915_private *dev_priv = dev->dev_private;
735
736 /* deactivate cxsr */
737 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
738 }
739
740 /*
741 * Latency for FIFO fetches is dependent on several factors:
742 * - memory configuration (speed, channels)
743 * - chipset
744 * - current MCH state
745 * It can be fairly high in some situations, so here we assume a fairly
746 * pessimal value. It's a tradeoff between extra memory fetches (if we
747 * set this value too high, the FIFO will fetch frequently to stay full)
748 * and power consumption (set it too low to save power and we might see
749 * FIFO underruns and display "flicker").
750 *
751 * A value of 5us seems to be a good balance; safe for very low end
752 * platforms but not overly aggressive on lower latency configs.
753 */
754 static const int latency_ns = 5000;
755
756 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
757 {
758 struct drm_i915_private *dev_priv = dev->dev_private;
759 uint32_t dsparb = I915_READ(DSPARB);
760 int size;
761
762 size = dsparb & 0x7f;
763 if (plane)
764 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
765
766 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
767 plane ? "B" : "A", size);
768
769 return size;
770 }
771
772 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
773 {
774 struct drm_i915_private *dev_priv = dev->dev_private;
775 uint32_t dsparb = I915_READ(DSPARB);
776 int size;
777
778 size = dsparb & 0x1ff;
779 if (plane)
780 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
781 size >>= 1; /* Convert to cachelines */
782
783 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
784 plane ? "B" : "A", size);
785
786 return size;
787 }
788
789 static int i845_get_fifo_size(struct drm_device *dev, int plane)
790 {
791 struct drm_i915_private *dev_priv = dev->dev_private;
792 uint32_t dsparb = I915_READ(DSPARB);
793 int size;
794
795 size = dsparb & 0x7f;
796 size >>= 2; /* Convert to cachelines */
797
798 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
799 plane ? "B" : "A",
800 size);
801
802 return size;
803 }
804
805 static int i830_get_fifo_size(struct drm_device *dev, int plane)
806 {
807 struct drm_i915_private *dev_priv = dev->dev_private;
808 uint32_t dsparb = I915_READ(DSPARB);
809 int size;
810
811 size = dsparb & 0x7f;
812 size >>= 1; /* Convert to cachelines */
813
814 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
815 plane ? "B" : "A", size);
816
817 return size;
818 }
819
820 /* Pineview has different values for various configs */
821 static const struct intel_watermark_params pineview_display_wm = {
822 PINEVIEW_DISPLAY_FIFO,
823 PINEVIEW_MAX_WM,
824 PINEVIEW_DFT_WM,
825 PINEVIEW_GUARD_WM,
826 PINEVIEW_FIFO_LINE_SIZE
827 };
828 static const struct intel_watermark_params pineview_display_hplloff_wm = {
829 PINEVIEW_DISPLAY_FIFO,
830 PINEVIEW_MAX_WM,
831 PINEVIEW_DFT_HPLLOFF_WM,
832 PINEVIEW_GUARD_WM,
833 PINEVIEW_FIFO_LINE_SIZE
834 };
835 static const struct intel_watermark_params pineview_cursor_wm = {
836 PINEVIEW_CURSOR_FIFO,
837 PINEVIEW_CURSOR_MAX_WM,
838 PINEVIEW_CURSOR_DFT_WM,
839 PINEVIEW_CURSOR_GUARD_WM,
840 PINEVIEW_FIFO_LINE_SIZE,
841 };
842 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
843 PINEVIEW_CURSOR_FIFO,
844 PINEVIEW_CURSOR_MAX_WM,
845 PINEVIEW_CURSOR_DFT_WM,
846 PINEVIEW_CURSOR_GUARD_WM,
847 PINEVIEW_FIFO_LINE_SIZE
848 };
849 static const struct intel_watermark_params g4x_wm_info = {
850 G4X_FIFO_SIZE,
851 G4X_MAX_WM,
852 G4X_MAX_WM,
853 2,
854 G4X_FIFO_LINE_SIZE,
855 };
856 static const struct intel_watermark_params g4x_cursor_wm_info = {
857 I965_CURSOR_FIFO,
858 I965_CURSOR_MAX_WM,
859 I965_CURSOR_DFT_WM,
860 2,
861 G4X_FIFO_LINE_SIZE,
862 };
863 static const struct intel_watermark_params valleyview_wm_info = {
864 VALLEYVIEW_FIFO_SIZE,
865 VALLEYVIEW_MAX_WM,
866 VALLEYVIEW_MAX_WM,
867 2,
868 G4X_FIFO_LINE_SIZE,
869 };
870 static const struct intel_watermark_params valleyview_cursor_wm_info = {
871 I965_CURSOR_FIFO,
872 VALLEYVIEW_CURSOR_MAX_WM,
873 I965_CURSOR_DFT_WM,
874 2,
875 G4X_FIFO_LINE_SIZE,
876 };
877 static const struct intel_watermark_params i965_cursor_wm_info = {
878 I965_CURSOR_FIFO,
879 I965_CURSOR_MAX_WM,
880 I965_CURSOR_DFT_WM,
881 2,
882 I915_FIFO_LINE_SIZE,
883 };
884 static const struct intel_watermark_params i945_wm_info = {
885 I945_FIFO_SIZE,
886 I915_MAX_WM,
887 1,
888 2,
889 I915_FIFO_LINE_SIZE
890 };
891 static const struct intel_watermark_params i915_wm_info = {
892 I915_FIFO_SIZE,
893 I915_MAX_WM,
894 1,
895 2,
896 I915_FIFO_LINE_SIZE
897 };
898 static const struct intel_watermark_params i855_wm_info = {
899 I855GM_FIFO_SIZE,
900 I915_MAX_WM,
901 1,
902 2,
903 I830_FIFO_LINE_SIZE
904 };
905 static const struct intel_watermark_params i830_wm_info = {
906 I830_FIFO_SIZE,
907 I915_MAX_WM,
908 1,
909 2,
910 I830_FIFO_LINE_SIZE
911 };
912
913 static const struct intel_watermark_params ironlake_display_wm_info = {
914 ILK_DISPLAY_FIFO,
915 ILK_DISPLAY_MAXWM,
916 ILK_DISPLAY_DFTWM,
917 2,
918 ILK_FIFO_LINE_SIZE
919 };
920 static const struct intel_watermark_params ironlake_cursor_wm_info = {
921 ILK_CURSOR_FIFO,
922 ILK_CURSOR_MAXWM,
923 ILK_CURSOR_DFTWM,
924 2,
925 ILK_FIFO_LINE_SIZE
926 };
927 static const struct intel_watermark_params ironlake_display_srwm_info = {
928 ILK_DISPLAY_SR_FIFO,
929 ILK_DISPLAY_MAX_SRWM,
930 ILK_DISPLAY_DFT_SRWM,
931 2,
932 ILK_FIFO_LINE_SIZE
933 };
934 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
935 ILK_CURSOR_SR_FIFO,
936 ILK_CURSOR_MAX_SRWM,
937 ILK_CURSOR_DFT_SRWM,
938 2,
939 ILK_FIFO_LINE_SIZE
940 };
941
942 static const struct intel_watermark_params sandybridge_display_wm_info = {
943 SNB_DISPLAY_FIFO,
944 SNB_DISPLAY_MAXWM,
945 SNB_DISPLAY_DFTWM,
946 2,
947 SNB_FIFO_LINE_SIZE
948 };
949 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
950 SNB_CURSOR_FIFO,
951 SNB_CURSOR_MAXWM,
952 SNB_CURSOR_DFTWM,
953 2,
954 SNB_FIFO_LINE_SIZE
955 };
956 static const struct intel_watermark_params sandybridge_display_srwm_info = {
957 SNB_DISPLAY_SR_FIFO,
958 SNB_DISPLAY_MAX_SRWM,
959 SNB_DISPLAY_DFT_SRWM,
960 2,
961 SNB_FIFO_LINE_SIZE
962 };
963 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
964 SNB_CURSOR_SR_FIFO,
965 SNB_CURSOR_MAX_SRWM,
966 SNB_CURSOR_DFT_SRWM,
967 2,
968 SNB_FIFO_LINE_SIZE
969 };
970
971
972 /**
973 * intel_calculate_wm - calculate watermark level
974 * @clock_in_khz: pixel clock
975 * @wm: chip FIFO params
976 * @pixel_size: display pixel size
977 * @latency_ns: memory latency for the platform
978 *
979 * Calculate the watermark level (the level at which the display plane will
980 * start fetching from memory again). Each chip has a different display
981 * FIFO size and allocation, so the caller needs to figure that out and pass
982 * in the correct intel_watermark_params structure.
983 *
984 * As the pixel clock runs, the FIFO will be drained at a rate that depends
985 * on the pixel size. When it reaches the watermark level, it'll start
986 * fetching FIFO line sized based chunks from memory until the FIFO fills
987 * past the watermark point. If the FIFO drains completely, a FIFO underrun
988 * will occur, and a display engine hang could result.
989 */
990 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
991 const struct intel_watermark_params *wm,
992 int fifo_size,
993 int pixel_size,
994 unsigned long latency_ns)
995 {
996 long entries_required, wm_size;
997
998 /*
999 * Note: we need to make sure we don't overflow for various clock &
1000 * latency values.
1001 * clocks go from a few thousand to several hundred thousand.
1002 * latency is usually a few thousand
1003 */
1004 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
1005 1000;
1006 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
1007
1008 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
1009
1010 wm_size = fifo_size - (entries_required + wm->guard_size);
1011
1012 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
1013
1014 /* Don't promote wm_size to unsigned... */
1015 if (wm_size > (long)wm->max_wm)
1016 wm_size = wm->max_wm;
1017 if (wm_size <= 0)
1018 wm_size = wm->default_wm;
1019 return wm_size;
1020 }
1021
1022 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1023 {
1024 struct drm_crtc *crtc, *enabled = NULL;
1025
1026 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1027 if (intel_crtc_active(crtc)) {
1028 if (enabled)
1029 return NULL;
1030 enabled = crtc;
1031 }
1032 }
1033
1034 return enabled;
1035 }
1036
1037 static void pineview_update_wm(struct drm_device *dev)
1038 {
1039 struct drm_i915_private *dev_priv = dev->dev_private;
1040 struct drm_crtc *crtc;
1041 const struct cxsr_latency *latency;
1042 u32 reg;
1043 unsigned long wm;
1044
1045 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1046 dev_priv->fsb_freq, dev_priv->mem_freq);
1047 if (!latency) {
1048 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1049 pineview_disable_cxsr(dev);
1050 return;
1051 }
1052
1053 crtc = single_enabled_crtc(dev);
1054 if (crtc) {
1055 int clock = crtc->mode.clock;
1056 int pixel_size = crtc->fb->bits_per_pixel / 8;
1057
1058 /* Display SR */
1059 wm = intel_calculate_wm(clock, &pineview_display_wm,
1060 pineview_display_wm.fifo_size,
1061 pixel_size, latency->display_sr);
1062 reg = I915_READ(DSPFW1);
1063 reg &= ~DSPFW_SR_MASK;
1064 reg |= wm << DSPFW_SR_SHIFT;
1065 I915_WRITE(DSPFW1, reg);
1066 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1067
1068 /* cursor SR */
1069 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1070 pineview_display_wm.fifo_size,
1071 pixel_size, latency->cursor_sr);
1072 reg = I915_READ(DSPFW3);
1073 reg &= ~DSPFW_CURSOR_SR_MASK;
1074 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1075 I915_WRITE(DSPFW3, reg);
1076
1077 /* Display HPLL off SR */
1078 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1079 pineview_display_hplloff_wm.fifo_size,
1080 pixel_size, latency->display_hpll_disable);
1081 reg = I915_READ(DSPFW3);
1082 reg &= ~DSPFW_HPLL_SR_MASK;
1083 reg |= wm & DSPFW_HPLL_SR_MASK;
1084 I915_WRITE(DSPFW3, reg);
1085
1086 /* cursor HPLL off SR */
1087 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1088 pineview_display_hplloff_wm.fifo_size,
1089 pixel_size, latency->cursor_hpll_disable);
1090 reg = I915_READ(DSPFW3);
1091 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1092 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1093 I915_WRITE(DSPFW3, reg);
1094 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1095
1096 /* activate cxsr */
1097 I915_WRITE(DSPFW3,
1098 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1099 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1100 } else {
1101 pineview_disable_cxsr(dev);
1102 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1103 }
1104 }
1105
1106 static bool g4x_compute_wm0(struct drm_device *dev,
1107 int plane,
1108 const struct intel_watermark_params *display,
1109 int display_latency_ns,
1110 const struct intel_watermark_params *cursor,
1111 int cursor_latency_ns,
1112 int *plane_wm,
1113 int *cursor_wm)
1114 {
1115 struct drm_crtc *crtc;
1116 int htotal, hdisplay, clock, pixel_size;
1117 int line_time_us, line_count;
1118 int entries, tlb_miss;
1119
1120 crtc = intel_get_crtc_for_plane(dev, plane);
1121 if (!intel_crtc_active(crtc)) {
1122 *cursor_wm = cursor->guard_size;
1123 *plane_wm = display->guard_size;
1124 return false;
1125 }
1126
1127 htotal = crtc->mode.htotal;
1128 hdisplay = crtc->mode.hdisplay;
1129 clock = crtc->mode.clock;
1130 pixel_size = crtc->fb->bits_per_pixel / 8;
1131
1132 /* Use the small buffer method to calculate plane watermark */
1133 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1134 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1135 if (tlb_miss > 0)
1136 entries += tlb_miss;
1137 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1138 *plane_wm = entries + display->guard_size;
1139 if (*plane_wm > (int)display->max_wm)
1140 *plane_wm = display->max_wm;
1141
1142 /* Use the large buffer method to calculate cursor watermark */
1143 line_time_us = ((htotal * 1000) / clock);
1144 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1145 entries = line_count * 64 * pixel_size;
1146 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1147 if (tlb_miss > 0)
1148 entries += tlb_miss;
1149 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1150 *cursor_wm = entries + cursor->guard_size;
1151 if (*cursor_wm > (int)cursor->max_wm)
1152 *cursor_wm = (int)cursor->max_wm;
1153
1154 return true;
1155 }
1156
1157 /*
1158 * Check the wm result.
1159 *
1160 * If any calculated watermark values is larger than the maximum value that
1161 * can be programmed into the associated watermark register, that watermark
1162 * must be disabled.
1163 */
1164 static bool g4x_check_srwm(struct drm_device *dev,
1165 int display_wm, int cursor_wm,
1166 const struct intel_watermark_params *display,
1167 const struct intel_watermark_params *cursor)
1168 {
1169 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1170 display_wm, cursor_wm);
1171
1172 if (display_wm > display->max_wm) {
1173 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1174 display_wm, display->max_wm);
1175 return false;
1176 }
1177
1178 if (cursor_wm > cursor->max_wm) {
1179 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1180 cursor_wm, cursor->max_wm);
1181 return false;
1182 }
1183
1184 if (!(display_wm || cursor_wm)) {
1185 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1186 return false;
1187 }
1188
1189 return true;
1190 }
1191
1192 static bool g4x_compute_srwm(struct drm_device *dev,
1193 int plane,
1194 int latency_ns,
1195 const struct intel_watermark_params *display,
1196 const struct intel_watermark_params *cursor,
1197 int *display_wm, int *cursor_wm)
1198 {
1199 struct drm_crtc *crtc;
1200 int hdisplay, htotal, pixel_size, clock;
1201 unsigned long line_time_us;
1202 int line_count, line_size;
1203 int small, large;
1204 int entries;
1205
1206 if (!latency_ns) {
1207 *display_wm = *cursor_wm = 0;
1208 return false;
1209 }
1210
1211 crtc = intel_get_crtc_for_plane(dev, plane);
1212 hdisplay = crtc->mode.hdisplay;
1213 htotal = crtc->mode.htotal;
1214 clock = crtc->mode.clock;
1215 pixel_size = crtc->fb->bits_per_pixel / 8;
1216
1217 line_time_us = (htotal * 1000) / clock;
1218 line_count = (latency_ns / line_time_us + 1000) / 1000;
1219 line_size = hdisplay * pixel_size;
1220
1221 /* Use the minimum of the small and large buffer method for primary */
1222 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1223 large = line_count * line_size;
1224
1225 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1226 *display_wm = entries + display->guard_size;
1227
1228 /* calculate the self-refresh watermark for display cursor */
1229 entries = line_count * pixel_size * 64;
1230 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1231 *cursor_wm = entries + cursor->guard_size;
1232
1233 return g4x_check_srwm(dev,
1234 *display_wm, *cursor_wm,
1235 display, cursor);
1236 }
1237
1238 static bool vlv_compute_drain_latency(struct drm_device *dev,
1239 int plane,
1240 int *plane_prec_mult,
1241 int *plane_dl,
1242 int *cursor_prec_mult,
1243 int *cursor_dl)
1244 {
1245 struct drm_crtc *crtc;
1246 int clock, pixel_size;
1247 int entries;
1248
1249 crtc = intel_get_crtc_for_plane(dev, plane);
1250 if (!intel_crtc_active(crtc))
1251 return false;
1252
1253 clock = crtc->mode.clock; /* VESA DOT Clock */
1254 pixel_size = crtc->fb->bits_per_pixel / 8; /* BPP */
1255
1256 entries = (clock / 1000) * pixel_size;
1257 *plane_prec_mult = (entries > 256) ?
1258 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1259 *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1260 pixel_size);
1261
1262 entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */
1263 *cursor_prec_mult = (entries > 256) ?
1264 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1265 *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1266
1267 return true;
1268 }
1269
1270 /*
1271 * Update drain latency registers of memory arbiter
1272 *
1273 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1274 * to be programmed. Each plane has a drain latency multiplier and a drain
1275 * latency value.
1276 */
1277
1278 static void vlv_update_drain_latency(struct drm_device *dev)
1279 {
1280 struct drm_i915_private *dev_priv = dev->dev_private;
1281 int planea_prec, planea_dl, planeb_prec, planeb_dl;
1282 int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1283 int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1284 either 16 or 32 */
1285
1286 /* For plane A, Cursor A */
1287 if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1288 &cursor_prec_mult, &cursora_dl)) {
1289 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1290 DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1291 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1292 DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1293
1294 I915_WRITE(VLV_DDL1, cursora_prec |
1295 (cursora_dl << DDL_CURSORA_SHIFT) |
1296 planea_prec | planea_dl);
1297 }
1298
1299 /* For plane B, Cursor B */
1300 if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1301 &cursor_prec_mult, &cursorb_dl)) {
1302 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1303 DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1304 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1305 DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1306
1307 I915_WRITE(VLV_DDL2, cursorb_prec |
1308 (cursorb_dl << DDL_CURSORB_SHIFT) |
1309 planeb_prec | planeb_dl);
1310 }
1311 }
1312
1313 #define single_plane_enabled(mask) is_power_of_2(mask)
1314
1315 static void valleyview_update_wm(struct drm_device *dev)
1316 {
1317 static const int sr_latency_ns = 12000;
1318 struct drm_i915_private *dev_priv = dev->dev_private;
1319 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1320 int plane_sr, cursor_sr;
1321 int ignore_plane_sr, ignore_cursor_sr;
1322 unsigned int enabled = 0;
1323
1324 vlv_update_drain_latency(dev);
1325
1326 if (g4x_compute_wm0(dev, 0,
1327 &valleyview_wm_info, latency_ns,
1328 &valleyview_cursor_wm_info, latency_ns,
1329 &planea_wm, &cursora_wm))
1330 enabled |= 1;
1331
1332 if (g4x_compute_wm0(dev, 1,
1333 &valleyview_wm_info, latency_ns,
1334 &valleyview_cursor_wm_info, latency_ns,
1335 &planeb_wm, &cursorb_wm))
1336 enabled |= 2;
1337
1338 if (single_plane_enabled(enabled) &&
1339 g4x_compute_srwm(dev, ffs(enabled) - 1,
1340 sr_latency_ns,
1341 &valleyview_wm_info,
1342 &valleyview_cursor_wm_info,
1343 &plane_sr, &ignore_cursor_sr) &&
1344 g4x_compute_srwm(dev, ffs(enabled) - 1,
1345 2*sr_latency_ns,
1346 &valleyview_wm_info,
1347 &valleyview_cursor_wm_info,
1348 &ignore_plane_sr, &cursor_sr)) {
1349 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
1350 } else {
1351 I915_WRITE(FW_BLC_SELF_VLV,
1352 I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
1353 plane_sr = cursor_sr = 0;
1354 }
1355
1356 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1357 planea_wm, cursora_wm,
1358 planeb_wm, cursorb_wm,
1359 plane_sr, cursor_sr);
1360
1361 I915_WRITE(DSPFW1,
1362 (plane_sr << DSPFW_SR_SHIFT) |
1363 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1364 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1365 planea_wm);
1366 I915_WRITE(DSPFW2,
1367 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1368 (cursora_wm << DSPFW_CURSORA_SHIFT));
1369 I915_WRITE(DSPFW3,
1370 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1371 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1372 }
1373
1374 static void g4x_update_wm(struct drm_device *dev)
1375 {
1376 static const int sr_latency_ns = 12000;
1377 struct drm_i915_private *dev_priv = dev->dev_private;
1378 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1379 int plane_sr, cursor_sr;
1380 unsigned int enabled = 0;
1381
1382 if (g4x_compute_wm0(dev, 0,
1383 &g4x_wm_info, latency_ns,
1384 &g4x_cursor_wm_info, latency_ns,
1385 &planea_wm, &cursora_wm))
1386 enabled |= 1;
1387
1388 if (g4x_compute_wm0(dev, 1,
1389 &g4x_wm_info, latency_ns,
1390 &g4x_cursor_wm_info, latency_ns,
1391 &planeb_wm, &cursorb_wm))
1392 enabled |= 2;
1393
1394 if (single_plane_enabled(enabled) &&
1395 g4x_compute_srwm(dev, ffs(enabled) - 1,
1396 sr_latency_ns,
1397 &g4x_wm_info,
1398 &g4x_cursor_wm_info,
1399 &plane_sr, &cursor_sr)) {
1400 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1401 } else {
1402 I915_WRITE(FW_BLC_SELF,
1403 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
1404 plane_sr = cursor_sr = 0;
1405 }
1406
1407 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1408 planea_wm, cursora_wm,
1409 planeb_wm, cursorb_wm,
1410 plane_sr, cursor_sr);
1411
1412 I915_WRITE(DSPFW1,
1413 (plane_sr << DSPFW_SR_SHIFT) |
1414 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1415 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1416 planea_wm);
1417 I915_WRITE(DSPFW2,
1418 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1419 (cursora_wm << DSPFW_CURSORA_SHIFT));
1420 /* HPLL off in SR has some issues on G4x... disable it */
1421 I915_WRITE(DSPFW3,
1422 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1423 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1424 }
1425
1426 static void i965_update_wm(struct drm_device *dev)
1427 {
1428 struct drm_i915_private *dev_priv = dev->dev_private;
1429 struct drm_crtc *crtc;
1430 int srwm = 1;
1431 int cursor_sr = 16;
1432
1433 /* Calc sr entries for one plane configs */
1434 crtc = single_enabled_crtc(dev);
1435 if (crtc) {
1436 /* self-refresh has much higher latency */
1437 static const int sr_latency_ns = 12000;
1438 int clock = crtc->mode.clock;
1439 int htotal = crtc->mode.htotal;
1440 int hdisplay = crtc->mode.hdisplay;
1441 int pixel_size = crtc->fb->bits_per_pixel / 8;
1442 unsigned long line_time_us;
1443 int entries;
1444
1445 line_time_us = ((htotal * 1000) / clock);
1446
1447 /* Use ns/us then divide to preserve precision */
1448 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1449 pixel_size * hdisplay;
1450 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1451 srwm = I965_FIFO_SIZE - entries;
1452 if (srwm < 0)
1453 srwm = 1;
1454 srwm &= 0x1ff;
1455 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1456 entries, srwm);
1457
1458 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1459 pixel_size * 64;
1460 entries = DIV_ROUND_UP(entries,
1461 i965_cursor_wm_info.cacheline_size);
1462 cursor_sr = i965_cursor_wm_info.fifo_size -
1463 (entries + i965_cursor_wm_info.guard_size);
1464
1465 if (cursor_sr > i965_cursor_wm_info.max_wm)
1466 cursor_sr = i965_cursor_wm_info.max_wm;
1467
1468 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1469 "cursor %d\n", srwm, cursor_sr);
1470
1471 if (IS_CRESTLINE(dev))
1472 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1473 } else {
1474 /* Turn off self refresh if both pipes are enabled */
1475 if (IS_CRESTLINE(dev))
1476 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1477 & ~FW_BLC_SELF_EN);
1478 }
1479
1480 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1481 srwm);
1482
1483 /* 965 has limitations... */
1484 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1485 (8 << 16) | (8 << 8) | (8 << 0));
1486 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1487 /* update cursor SR watermark */
1488 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1489 }
1490
1491 static void i9xx_update_wm(struct drm_device *dev)
1492 {
1493 struct drm_i915_private *dev_priv = dev->dev_private;
1494 const struct intel_watermark_params *wm_info;
1495 uint32_t fwater_lo;
1496 uint32_t fwater_hi;
1497 int cwm, srwm = 1;
1498 int fifo_size;
1499 int planea_wm, planeb_wm;
1500 struct drm_crtc *crtc, *enabled = NULL;
1501
1502 if (IS_I945GM(dev))
1503 wm_info = &i945_wm_info;
1504 else if (!IS_GEN2(dev))
1505 wm_info = &i915_wm_info;
1506 else
1507 wm_info = &i855_wm_info;
1508
1509 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1510 crtc = intel_get_crtc_for_plane(dev, 0);
1511 if (intel_crtc_active(crtc)) {
1512 int cpp = crtc->fb->bits_per_pixel / 8;
1513 if (IS_GEN2(dev))
1514 cpp = 4;
1515
1516 planea_wm = intel_calculate_wm(crtc->mode.clock,
1517 wm_info, fifo_size, cpp,
1518 latency_ns);
1519 enabled = crtc;
1520 } else
1521 planea_wm = fifo_size - wm_info->guard_size;
1522
1523 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1524 crtc = intel_get_crtc_for_plane(dev, 1);
1525 if (intel_crtc_active(crtc)) {
1526 int cpp = crtc->fb->bits_per_pixel / 8;
1527 if (IS_GEN2(dev))
1528 cpp = 4;
1529
1530 planeb_wm = intel_calculate_wm(crtc->mode.clock,
1531 wm_info, fifo_size, cpp,
1532 latency_ns);
1533 if (enabled == NULL)
1534 enabled = crtc;
1535 else
1536 enabled = NULL;
1537 } else
1538 planeb_wm = fifo_size - wm_info->guard_size;
1539
1540 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1541
1542 /*
1543 * Overlay gets an aggressive default since video jitter is bad.
1544 */
1545 cwm = 2;
1546
1547 /* Play safe and disable self-refresh before adjusting watermarks. */
1548 if (IS_I945G(dev) || IS_I945GM(dev))
1549 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1550 else if (IS_I915GM(dev))
1551 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
1552
1553 /* Calc sr entries for one plane configs */
1554 if (HAS_FW_BLC(dev) && enabled) {
1555 /* self-refresh has much higher latency */
1556 static const int sr_latency_ns = 6000;
1557 int clock = enabled->mode.clock;
1558 int htotal = enabled->mode.htotal;
1559 int hdisplay = enabled->mode.hdisplay;
1560 int pixel_size = enabled->fb->bits_per_pixel / 8;
1561 unsigned long line_time_us;
1562 int entries;
1563
1564 line_time_us = (htotal * 1000) / clock;
1565
1566 /* Use ns/us then divide to preserve precision */
1567 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1568 pixel_size * hdisplay;
1569 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1570 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1571 srwm = wm_info->fifo_size - entries;
1572 if (srwm < 0)
1573 srwm = 1;
1574
1575 if (IS_I945G(dev) || IS_I945GM(dev))
1576 I915_WRITE(FW_BLC_SELF,
1577 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1578 else if (IS_I915GM(dev))
1579 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1580 }
1581
1582 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1583 planea_wm, planeb_wm, cwm, srwm);
1584
1585 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1586 fwater_hi = (cwm & 0x1f);
1587
1588 /* Set request length to 8 cachelines per fetch */
1589 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1590 fwater_hi = fwater_hi | (1 << 8);
1591
1592 I915_WRITE(FW_BLC, fwater_lo);
1593 I915_WRITE(FW_BLC2, fwater_hi);
1594
1595 if (HAS_FW_BLC(dev)) {
1596 if (enabled) {
1597 if (IS_I945G(dev) || IS_I945GM(dev))
1598 I915_WRITE(FW_BLC_SELF,
1599 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1600 else if (IS_I915GM(dev))
1601 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
1602 DRM_DEBUG_KMS("memory self refresh enabled\n");
1603 } else
1604 DRM_DEBUG_KMS("memory self refresh disabled\n");
1605 }
1606 }
1607
1608 static void i830_update_wm(struct drm_device *dev)
1609 {
1610 struct drm_i915_private *dev_priv = dev->dev_private;
1611 struct drm_crtc *crtc;
1612 uint32_t fwater_lo;
1613 int planea_wm;
1614
1615 crtc = single_enabled_crtc(dev);
1616 if (crtc == NULL)
1617 return;
1618
1619 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
1620 dev_priv->display.get_fifo_size(dev, 0),
1621 4, latency_ns);
1622 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1623 fwater_lo |= (3<<8) | planea_wm;
1624
1625 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1626
1627 I915_WRITE(FW_BLC, fwater_lo);
1628 }
1629
1630 #define ILK_LP0_PLANE_LATENCY 700
1631 #define ILK_LP0_CURSOR_LATENCY 1300
1632
1633 /*
1634 * Check the wm result.
1635 *
1636 * If any calculated watermark values is larger than the maximum value that
1637 * can be programmed into the associated watermark register, that watermark
1638 * must be disabled.
1639 */
1640 static bool ironlake_check_srwm(struct drm_device *dev, int level,
1641 int fbc_wm, int display_wm, int cursor_wm,
1642 const struct intel_watermark_params *display,
1643 const struct intel_watermark_params *cursor)
1644 {
1645 struct drm_i915_private *dev_priv = dev->dev_private;
1646
1647 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
1648 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
1649
1650 if (fbc_wm > SNB_FBC_MAX_SRWM) {
1651 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
1652 fbc_wm, SNB_FBC_MAX_SRWM, level);
1653
1654 /* fbc has it's own way to disable FBC WM */
1655 I915_WRITE(DISP_ARB_CTL,
1656 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
1657 return false;
1658 } else if (INTEL_INFO(dev)->gen >= 6) {
1659 /* enable FBC WM (except on ILK, where it must remain off) */
1660 I915_WRITE(DISP_ARB_CTL,
1661 I915_READ(DISP_ARB_CTL) & ~DISP_FBC_WM_DIS);
1662 }
1663
1664 if (display_wm > display->max_wm) {
1665 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
1666 display_wm, SNB_DISPLAY_MAX_SRWM, level);
1667 return false;
1668 }
1669
1670 if (cursor_wm > cursor->max_wm) {
1671 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
1672 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1673 return false;
1674 }
1675
1676 if (!(fbc_wm || display_wm || cursor_wm)) {
1677 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
1678 return false;
1679 }
1680
1681 return true;
1682 }
1683
1684 /*
1685 * Compute watermark values of WM[1-3],
1686 */
1687 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
1688 int latency_ns,
1689 const struct intel_watermark_params *display,
1690 const struct intel_watermark_params *cursor,
1691 int *fbc_wm, int *display_wm, int *cursor_wm)
1692 {
1693 struct drm_crtc *crtc;
1694 unsigned long line_time_us;
1695 int hdisplay, htotal, pixel_size, clock;
1696 int line_count, line_size;
1697 int small, large;
1698 int entries;
1699
1700 if (!latency_ns) {
1701 *fbc_wm = *display_wm = *cursor_wm = 0;
1702 return false;
1703 }
1704
1705 crtc = intel_get_crtc_for_plane(dev, plane);
1706 hdisplay = crtc->mode.hdisplay;
1707 htotal = crtc->mode.htotal;
1708 clock = crtc->mode.clock;
1709 pixel_size = crtc->fb->bits_per_pixel / 8;
1710
1711 line_time_us = (htotal * 1000) / clock;
1712 line_count = (latency_ns / line_time_us + 1000) / 1000;
1713 line_size = hdisplay * pixel_size;
1714
1715 /* Use the minimum of the small and large buffer method for primary */
1716 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1717 large = line_count * line_size;
1718
1719 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1720 *display_wm = entries + display->guard_size;
1721
1722 /*
1723 * Spec says:
1724 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
1725 */
1726 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
1727
1728 /* calculate the self-refresh watermark for display cursor */
1729 entries = line_count * pixel_size * 64;
1730 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1731 *cursor_wm = entries + cursor->guard_size;
1732
1733 return ironlake_check_srwm(dev, level,
1734 *fbc_wm, *display_wm, *cursor_wm,
1735 display, cursor);
1736 }
1737
1738 static void ironlake_update_wm(struct drm_device *dev)
1739 {
1740 struct drm_i915_private *dev_priv = dev->dev_private;
1741 int fbc_wm, plane_wm, cursor_wm;
1742 unsigned int enabled;
1743
1744 enabled = 0;
1745 if (g4x_compute_wm0(dev, 0,
1746 &ironlake_display_wm_info,
1747 ILK_LP0_PLANE_LATENCY,
1748 &ironlake_cursor_wm_info,
1749 ILK_LP0_CURSOR_LATENCY,
1750 &plane_wm, &cursor_wm)) {
1751 I915_WRITE(WM0_PIPEA_ILK,
1752 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1753 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1754 " plane %d, " "cursor: %d\n",
1755 plane_wm, cursor_wm);
1756 enabled |= 1;
1757 }
1758
1759 if (g4x_compute_wm0(dev, 1,
1760 &ironlake_display_wm_info,
1761 ILK_LP0_PLANE_LATENCY,
1762 &ironlake_cursor_wm_info,
1763 ILK_LP0_CURSOR_LATENCY,
1764 &plane_wm, &cursor_wm)) {
1765 I915_WRITE(WM0_PIPEB_ILK,
1766 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1767 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1768 " plane %d, cursor: %d\n",
1769 plane_wm, cursor_wm);
1770 enabled |= 2;
1771 }
1772
1773 /*
1774 * Calculate and update the self-refresh watermark only when one
1775 * display plane is used.
1776 */
1777 I915_WRITE(WM3_LP_ILK, 0);
1778 I915_WRITE(WM2_LP_ILK, 0);
1779 I915_WRITE(WM1_LP_ILK, 0);
1780
1781 if (!single_plane_enabled(enabled))
1782 return;
1783 enabled = ffs(enabled) - 1;
1784
1785 /* WM1 */
1786 if (!ironlake_compute_srwm(dev, 1, enabled,
1787 ILK_READ_WM1_LATENCY() * 500,
1788 &ironlake_display_srwm_info,
1789 &ironlake_cursor_srwm_info,
1790 &fbc_wm, &plane_wm, &cursor_wm))
1791 return;
1792
1793 I915_WRITE(WM1_LP_ILK,
1794 WM1_LP_SR_EN |
1795 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1796 (fbc_wm << WM1_LP_FBC_SHIFT) |
1797 (plane_wm << WM1_LP_SR_SHIFT) |
1798 cursor_wm);
1799
1800 /* WM2 */
1801 if (!ironlake_compute_srwm(dev, 2, enabled,
1802 ILK_READ_WM2_LATENCY() * 500,
1803 &ironlake_display_srwm_info,
1804 &ironlake_cursor_srwm_info,
1805 &fbc_wm, &plane_wm, &cursor_wm))
1806 return;
1807
1808 I915_WRITE(WM2_LP_ILK,
1809 WM2_LP_EN |
1810 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1811 (fbc_wm << WM1_LP_FBC_SHIFT) |
1812 (plane_wm << WM1_LP_SR_SHIFT) |
1813 cursor_wm);
1814
1815 /*
1816 * WM3 is unsupported on ILK, probably because we don't have latency
1817 * data for that power state
1818 */
1819 }
1820
1821 static void sandybridge_update_wm(struct drm_device *dev)
1822 {
1823 struct drm_i915_private *dev_priv = dev->dev_private;
1824 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
1825 u32 val;
1826 int fbc_wm, plane_wm, cursor_wm;
1827 unsigned int enabled;
1828
1829 enabled = 0;
1830 if (g4x_compute_wm0(dev, 0,
1831 &sandybridge_display_wm_info, latency,
1832 &sandybridge_cursor_wm_info, latency,
1833 &plane_wm, &cursor_wm)) {
1834 val = I915_READ(WM0_PIPEA_ILK);
1835 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1836 I915_WRITE(WM0_PIPEA_ILK, val |
1837 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1838 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1839 " plane %d, " "cursor: %d\n",
1840 plane_wm, cursor_wm);
1841 enabled |= 1;
1842 }
1843
1844 if (g4x_compute_wm0(dev, 1,
1845 &sandybridge_display_wm_info, latency,
1846 &sandybridge_cursor_wm_info, latency,
1847 &plane_wm, &cursor_wm)) {
1848 val = I915_READ(WM0_PIPEB_ILK);
1849 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1850 I915_WRITE(WM0_PIPEB_ILK, val |
1851 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1852 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1853 " plane %d, cursor: %d\n",
1854 plane_wm, cursor_wm);
1855 enabled |= 2;
1856 }
1857
1858 /*
1859 * Calculate and update the self-refresh watermark only when one
1860 * display plane is used.
1861 *
1862 * SNB support 3 levels of watermark.
1863 *
1864 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1865 * and disabled in the descending order
1866 *
1867 */
1868 I915_WRITE(WM3_LP_ILK, 0);
1869 I915_WRITE(WM2_LP_ILK, 0);
1870 I915_WRITE(WM1_LP_ILK, 0);
1871
1872 if (!single_plane_enabled(enabled) ||
1873 dev_priv->sprite_scaling_enabled)
1874 return;
1875 enabled = ffs(enabled) - 1;
1876
1877 /* WM1 */
1878 if (!ironlake_compute_srwm(dev, 1, enabled,
1879 SNB_READ_WM1_LATENCY() * 500,
1880 &sandybridge_display_srwm_info,
1881 &sandybridge_cursor_srwm_info,
1882 &fbc_wm, &plane_wm, &cursor_wm))
1883 return;
1884
1885 I915_WRITE(WM1_LP_ILK,
1886 WM1_LP_SR_EN |
1887 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1888 (fbc_wm << WM1_LP_FBC_SHIFT) |
1889 (plane_wm << WM1_LP_SR_SHIFT) |
1890 cursor_wm);
1891
1892 /* WM2 */
1893 if (!ironlake_compute_srwm(dev, 2, enabled,
1894 SNB_READ_WM2_LATENCY() * 500,
1895 &sandybridge_display_srwm_info,
1896 &sandybridge_cursor_srwm_info,
1897 &fbc_wm, &plane_wm, &cursor_wm))
1898 return;
1899
1900 I915_WRITE(WM2_LP_ILK,
1901 WM2_LP_EN |
1902 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1903 (fbc_wm << WM1_LP_FBC_SHIFT) |
1904 (plane_wm << WM1_LP_SR_SHIFT) |
1905 cursor_wm);
1906
1907 /* WM3 */
1908 if (!ironlake_compute_srwm(dev, 3, enabled,
1909 SNB_READ_WM3_LATENCY() * 500,
1910 &sandybridge_display_srwm_info,
1911 &sandybridge_cursor_srwm_info,
1912 &fbc_wm, &plane_wm, &cursor_wm))
1913 return;
1914
1915 I915_WRITE(WM3_LP_ILK,
1916 WM3_LP_EN |
1917 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1918 (fbc_wm << WM1_LP_FBC_SHIFT) |
1919 (plane_wm << WM1_LP_SR_SHIFT) |
1920 cursor_wm);
1921 }
1922
1923 static void ivybridge_update_wm(struct drm_device *dev)
1924 {
1925 struct drm_i915_private *dev_priv = dev->dev_private;
1926 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
1927 u32 val;
1928 int fbc_wm, plane_wm, cursor_wm;
1929 int ignore_fbc_wm, ignore_plane_wm, ignore_cursor_wm;
1930 unsigned int enabled;
1931
1932 enabled = 0;
1933 if (g4x_compute_wm0(dev, 0,
1934 &sandybridge_display_wm_info, latency,
1935 &sandybridge_cursor_wm_info, latency,
1936 &plane_wm, &cursor_wm)) {
1937 val = I915_READ(WM0_PIPEA_ILK);
1938 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1939 I915_WRITE(WM0_PIPEA_ILK, val |
1940 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1941 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1942 " plane %d, " "cursor: %d\n",
1943 plane_wm, cursor_wm);
1944 enabled |= 1;
1945 }
1946
1947 if (g4x_compute_wm0(dev, 1,
1948 &sandybridge_display_wm_info, latency,
1949 &sandybridge_cursor_wm_info, latency,
1950 &plane_wm, &cursor_wm)) {
1951 val = I915_READ(WM0_PIPEB_ILK);
1952 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1953 I915_WRITE(WM0_PIPEB_ILK, val |
1954 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1955 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1956 " plane %d, cursor: %d\n",
1957 plane_wm, cursor_wm);
1958 enabled |= 2;
1959 }
1960
1961 if (g4x_compute_wm0(dev, 2,
1962 &sandybridge_display_wm_info, latency,
1963 &sandybridge_cursor_wm_info, latency,
1964 &plane_wm, &cursor_wm)) {
1965 val = I915_READ(WM0_PIPEC_IVB);
1966 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1967 I915_WRITE(WM0_PIPEC_IVB, val |
1968 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1969 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
1970 " plane %d, cursor: %d\n",
1971 plane_wm, cursor_wm);
1972 enabled |= 3;
1973 }
1974
1975 /*
1976 * Calculate and update the self-refresh watermark only when one
1977 * display plane is used.
1978 *
1979 * SNB support 3 levels of watermark.
1980 *
1981 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1982 * and disabled in the descending order
1983 *
1984 */
1985 I915_WRITE(WM3_LP_ILK, 0);
1986 I915_WRITE(WM2_LP_ILK, 0);
1987 I915_WRITE(WM1_LP_ILK, 0);
1988
1989 if (!single_plane_enabled(enabled) ||
1990 dev_priv->sprite_scaling_enabled)
1991 return;
1992 enabled = ffs(enabled) - 1;
1993
1994 /* WM1 */
1995 if (!ironlake_compute_srwm(dev, 1, enabled,
1996 SNB_READ_WM1_LATENCY() * 500,
1997 &sandybridge_display_srwm_info,
1998 &sandybridge_cursor_srwm_info,
1999 &fbc_wm, &plane_wm, &cursor_wm))
2000 return;
2001
2002 I915_WRITE(WM1_LP_ILK,
2003 WM1_LP_SR_EN |
2004 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
2005 (fbc_wm << WM1_LP_FBC_SHIFT) |
2006 (plane_wm << WM1_LP_SR_SHIFT) |
2007 cursor_wm);
2008
2009 /* WM2 */
2010 if (!ironlake_compute_srwm(dev, 2, enabled,
2011 SNB_READ_WM2_LATENCY() * 500,
2012 &sandybridge_display_srwm_info,
2013 &sandybridge_cursor_srwm_info,
2014 &fbc_wm, &plane_wm, &cursor_wm))
2015 return;
2016
2017 I915_WRITE(WM2_LP_ILK,
2018 WM2_LP_EN |
2019 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
2020 (fbc_wm << WM1_LP_FBC_SHIFT) |
2021 (plane_wm << WM1_LP_SR_SHIFT) |
2022 cursor_wm);
2023
2024 /* WM3, note we have to correct the cursor latency */
2025 if (!ironlake_compute_srwm(dev, 3, enabled,
2026 SNB_READ_WM3_LATENCY() * 500,
2027 &sandybridge_display_srwm_info,
2028 &sandybridge_cursor_srwm_info,
2029 &fbc_wm, &plane_wm, &ignore_cursor_wm) ||
2030 !ironlake_compute_srwm(dev, 3, enabled,
2031 2 * SNB_READ_WM3_LATENCY() * 500,
2032 &sandybridge_display_srwm_info,
2033 &sandybridge_cursor_srwm_info,
2034 &ignore_fbc_wm, &ignore_plane_wm, &cursor_wm))
2035 return;
2036
2037 I915_WRITE(WM3_LP_ILK,
2038 WM3_LP_EN |
2039 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
2040 (fbc_wm << WM1_LP_FBC_SHIFT) |
2041 (plane_wm << WM1_LP_SR_SHIFT) |
2042 cursor_wm);
2043 }
2044
2045 static void
2046 haswell_update_linetime_wm(struct drm_device *dev, int pipe,
2047 struct drm_display_mode *mode)
2048 {
2049 struct drm_i915_private *dev_priv = dev->dev_private;
2050 u32 temp;
2051
2052 temp = I915_READ(PIPE_WM_LINETIME(pipe));
2053 temp &= ~PIPE_WM_LINETIME_MASK;
2054
2055 /* The WM are computed with base on how long it takes to fill a single
2056 * row at the given clock rate, multiplied by 8.
2057 * */
2058 temp |= PIPE_WM_LINETIME_TIME(
2059 ((mode->crtc_hdisplay * 1000) / mode->clock) * 8);
2060
2061 /* IPS watermarks are only used by pipe A, and are ignored by
2062 * pipes B and C. They are calculated similarly to the common
2063 * linetime values, except that we are using CD clock frequency
2064 * in MHz instead of pixel rate for the division.
2065 *
2066 * This is a placeholder for the IPS watermark calculation code.
2067 */
2068
2069 I915_WRITE(PIPE_WM_LINETIME(pipe), temp);
2070 }
2071
2072 static bool
2073 sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
2074 uint32_t sprite_width, int pixel_size,
2075 const struct intel_watermark_params *display,
2076 int display_latency_ns, int *sprite_wm)
2077 {
2078 struct drm_crtc *crtc;
2079 int clock;
2080 int entries, tlb_miss;
2081
2082 crtc = intel_get_crtc_for_plane(dev, plane);
2083 if (!intel_crtc_active(crtc)) {
2084 *sprite_wm = display->guard_size;
2085 return false;
2086 }
2087
2088 clock = crtc->mode.clock;
2089
2090 /* Use the small buffer method to calculate the sprite watermark */
2091 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
2092 tlb_miss = display->fifo_size*display->cacheline_size -
2093 sprite_width * 8;
2094 if (tlb_miss > 0)
2095 entries += tlb_miss;
2096 entries = DIV_ROUND_UP(entries, display->cacheline_size);
2097 *sprite_wm = entries + display->guard_size;
2098 if (*sprite_wm > (int)display->max_wm)
2099 *sprite_wm = display->max_wm;
2100
2101 return true;
2102 }
2103
2104 static bool
2105 sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
2106 uint32_t sprite_width, int pixel_size,
2107 const struct intel_watermark_params *display,
2108 int latency_ns, int *sprite_wm)
2109 {
2110 struct drm_crtc *crtc;
2111 unsigned long line_time_us;
2112 int clock;
2113 int line_count, line_size;
2114 int small, large;
2115 int entries;
2116
2117 if (!latency_ns) {
2118 *sprite_wm = 0;
2119 return false;
2120 }
2121
2122 crtc = intel_get_crtc_for_plane(dev, plane);
2123 clock = crtc->mode.clock;
2124 if (!clock) {
2125 *sprite_wm = 0;
2126 return false;
2127 }
2128
2129 line_time_us = (sprite_width * 1000) / clock;
2130 if (!line_time_us) {
2131 *sprite_wm = 0;
2132 return false;
2133 }
2134
2135 line_count = (latency_ns / line_time_us + 1000) / 1000;
2136 line_size = sprite_width * pixel_size;
2137
2138 /* Use the minimum of the small and large buffer method for primary */
2139 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
2140 large = line_count * line_size;
2141
2142 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
2143 *sprite_wm = entries + display->guard_size;
2144
2145 return *sprite_wm > 0x3ff ? false : true;
2146 }
2147
2148 static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
2149 uint32_t sprite_width, int pixel_size)
2150 {
2151 struct drm_i915_private *dev_priv = dev->dev_private;
2152 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
2153 u32 val;
2154 int sprite_wm, reg;
2155 int ret;
2156
2157 switch (pipe) {
2158 case 0:
2159 reg = WM0_PIPEA_ILK;
2160 break;
2161 case 1:
2162 reg = WM0_PIPEB_ILK;
2163 break;
2164 case 2:
2165 reg = WM0_PIPEC_IVB;
2166 break;
2167 default:
2168 return; /* bad pipe */
2169 }
2170
2171 ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
2172 &sandybridge_display_wm_info,
2173 latency, &sprite_wm);
2174 if (!ret) {
2175 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %c\n",
2176 pipe_name(pipe));
2177 return;
2178 }
2179
2180 val = I915_READ(reg);
2181 val &= ~WM0_PIPE_SPRITE_MASK;
2182 I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
2183 DRM_DEBUG_KMS("sprite watermarks For pipe %c - %d\n", pipe_name(pipe), sprite_wm);
2184
2185
2186 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2187 pixel_size,
2188 &sandybridge_display_srwm_info,
2189 SNB_READ_WM1_LATENCY() * 500,
2190 &sprite_wm);
2191 if (!ret) {
2192 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %c\n",
2193 pipe_name(pipe));
2194 return;
2195 }
2196 I915_WRITE(WM1S_LP_ILK, sprite_wm);
2197
2198 /* Only IVB has two more LP watermarks for sprite */
2199 if (!IS_IVYBRIDGE(dev))
2200 return;
2201
2202 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2203 pixel_size,
2204 &sandybridge_display_srwm_info,
2205 SNB_READ_WM2_LATENCY() * 500,
2206 &sprite_wm);
2207 if (!ret) {
2208 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %c\n",
2209 pipe_name(pipe));
2210 return;
2211 }
2212 I915_WRITE(WM2S_LP_IVB, sprite_wm);
2213
2214 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2215 pixel_size,
2216 &sandybridge_display_srwm_info,
2217 SNB_READ_WM3_LATENCY() * 500,
2218 &sprite_wm);
2219 if (!ret) {
2220 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %c\n",
2221 pipe_name(pipe));
2222 return;
2223 }
2224 I915_WRITE(WM3S_LP_IVB, sprite_wm);
2225 }
2226
2227 /**
2228 * intel_update_watermarks - update FIFO watermark values based on current modes
2229 *
2230 * Calculate watermark values for the various WM regs based on current mode
2231 * and plane configuration.
2232 *
2233 * There are several cases to deal with here:
2234 * - normal (i.e. non-self-refresh)
2235 * - self-refresh (SR) mode
2236 * - lines are large relative to FIFO size (buffer can hold up to 2)
2237 * - lines are small relative to FIFO size (buffer can hold more than 2
2238 * lines), so need to account for TLB latency
2239 *
2240 * The normal calculation is:
2241 * watermark = dotclock * bytes per pixel * latency
2242 * where latency is platform & configuration dependent (we assume pessimal
2243 * values here).
2244 *
2245 * The SR calculation is:
2246 * watermark = (trunc(latency/line time)+1) * surface width *
2247 * bytes per pixel
2248 * where
2249 * line time = htotal / dotclock
2250 * surface width = hdisplay for normal plane and 64 for cursor
2251 * and latency is assumed to be high, as above.
2252 *
2253 * The final value programmed to the register should always be rounded up,
2254 * and include an extra 2 entries to account for clock crossings.
2255 *
2256 * We don't use the sprite, so we can ignore that. And on Crestline we have
2257 * to set the non-SR watermarks to 8.
2258 */
2259 void intel_update_watermarks(struct drm_device *dev)
2260 {
2261 struct drm_i915_private *dev_priv = dev->dev_private;
2262
2263 if (dev_priv->display.update_wm)
2264 dev_priv->display.update_wm(dev);
2265 }
2266
2267 void intel_update_linetime_watermarks(struct drm_device *dev,
2268 int pipe, struct drm_display_mode *mode)
2269 {
2270 struct drm_i915_private *dev_priv = dev->dev_private;
2271
2272 if (dev_priv->display.update_linetime_wm)
2273 dev_priv->display.update_linetime_wm(dev, pipe, mode);
2274 }
2275
2276 void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
2277 uint32_t sprite_width, int pixel_size)
2278 {
2279 struct drm_i915_private *dev_priv = dev->dev_private;
2280
2281 if (dev_priv->display.update_sprite_wm)
2282 dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
2283 pixel_size);
2284 }
2285
2286 static struct drm_i915_gem_object *
2287 intel_alloc_context_page(struct drm_device *dev)
2288 {
2289 struct drm_i915_gem_object *ctx;
2290 int ret;
2291
2292 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2293
2294 ctx = i915_gem_alloc_object(dev, 4096);
2295 if (!ctx) {
2296 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
2297 return NULL;
2298 }
2299
2300 ret = i915_gem_object_pin(ctx, 4096, true, false);
2301 if (ret) {
2302 DRM_ERROR("failed to pin power context: %d\n", ret);
2303 goto err_unref;
2304 }
2305
2306 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
2307 if (ret) {
2308 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
2309 goto err_unpin;
2310 }
2311
2312 return ctx;
2313
2314 err_unpin:
2315 i915_gem_object_unpin(ctx);
2316 err_unref:
2317 drm_gem_object_unreference(&ctx->base);
2318 return NULL;
2319 }
2320
2321 /**
2322 * Lock protecting IPS related data structures
2323 */
2324 DEFINE_SPINLOCK(mchdev_lock);
2325
2326 /* Global for IPS driver to get at the current i915 device. Protected by
2327 * mchdev_lock. */
2328 static struct drm_i915_private *i915_mch_dev;
2329
2330 bool ironlake_set_drps(struct drm_device *dev, u8 val)
2331 {
2332 struct drm_i915_private *dev_priv = dev->dev_private;
2333 u16 rgvswctl;
2334
2335 assert_spin_locked(&mchdev_lock);
2336
2337 rgvswctl = I915_READ16(MEMSWCTL);
2338 if (rgvswctl & MEMCTL_CMD_STS) {
2339 DRM_DEBUG("gpu busy, RCS change rejected\n");
2340 return false; /* still busy with another command */
2341 }
2342
2343 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
2344 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
2345 I915_WRITE16(MEMSWCTL, rgvswctl);
2346 POSTING_READ16(MEMSWCTL);
2347
2348 rgvswctl |= MEMCTL_CMD_STS;
2349 I915_WRITE16(MEMSWCTL, rgvswctl);
2350
2351 return true;
2352 }
2353
2354 static void ironlake_enable_drps(struct drm_device *dev)
2355 {
2356 struct drm_i915_private *dev_priv = dev->dev_private;
2357 u32 rgvmodectl = I915_READ(MEMMODECTL);
2358 u8 fmax, fmin, fstart, vstart;
2359
2360 spin_lock_irq(&mchdev_lock);
2361
2362 /* Enable temp reporting */
2363 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
2364 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
2365
2366 /* 100ms RC evaluation intervals */
2367 I915_WRITE(RCUPEI, 100000);
2368 I915_WRITE(RCDNEI, 100000);
2369
2370 /* Set max/min thresholds to 90ms and 80ms respectively */
2371 I915_WRITE(RCBMAXAVG, 90000);
2372 I915_WRITE(RCBMINAVG, 80000);
2373
2374 I915_WRITE(MEMIHYST, 1);
2375
2376 /* Set up min, max, and cur for interrupt handling */
2377 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
2378 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
2379 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
2380 MEMMODE_FSTART_SHIFT;
2381
2382 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
2383 PXVFREQ_PX_SHIFT;
2384
2385 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
2386 dev_priv->ips.fstart = fstart;
2387
2388 dev_priv->ips.max_delay = fstart;
2389 dev_priv->ips.min_delay = fmin;
2390 dev_priv->ips.cur_delay = fstart;
2391
2392 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
2393 fmax, fmin, fstart);
2394
2395 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
2396
2397 /*
2398 * Interrupts will be enabled in ironlake_irq_postinstall
2399 */
2400
2401 I915_WRITE(VIDSTART, vstart);
2402 POSTING_READ(VIDSTART);
2403
2404 rgvmodectl |= MEMMODE_SWMODE_EN;
2405 I915_WRITE(MEMMODECTL, rgvmodectl);
2406
2407 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2408 DRM_ERROR("stuck trying to change perf mode\n");
2409 mdelay(1);
2410
2411 ironlake_set_drps(dev, fstart);
2412
2413 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2414 I915_READ(0x112e0);
2415 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
2416 dev_priv->ips.last_count2 = I915_READ(0x112f4);
2417 getrawmonotonic(&dev_priv->ips.last_time2);
2418
2419 spin_unlock_irq(&mchdev_lock);
2420 }
2421
2422 static void ironlake_disable_drps(struct drm_device *dev)
2423 {
2424 struct drm_i915_private *dev_priv = dev->dev_private;
2425 u16 rgvswctl;
2426
2427 spin_lock_irq(&mchdev_lock);
2428
2429 rgvswctl = I915_READ16(MEMSWCTL);
2430
2431 /* Ack interrupts, disable EFC interrupt */
2432 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
2433 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
2434 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
2435 I915_WRITE(DEIIR, DE_PCU_EVENT);
2436 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
2437
2438 /* Go back to the starting frequency */
2439 ironlake_set_drps(dev, dev_priv->ips.fstart);
2440 mdelay(1);
2441 rgvswctl |= MEMCTL_CMD_STS;
2442 I915_WRITE(MEMSWCTL, rgvswctl);
2443 mdelay(1);
2444
2445 spin_unlock_irq(&mchdev_lock);
2446 }
2447
2448 /* There's a funny hw issue where the hw returns all 0 when reading from
2449 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
2450 * ourselves, instead of doing a rmw cycle (which might result in us clearing
2451 * all limits and the gpu stuck at whatever frequency it is at atm).
2452 */
2453 static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 *val)
2454 {
2455 u32 limits;
2456
2457 limits = 0;
2458
2459 if (*val >= dev_priv->rps.max_delay)
2460 *val = dev_priv->rps.max_delay;
2461 limits |= dev_priv->rps.max_delay << 24;
2462
2463 /* Only set the down limit when we've reached the lowest level to avoid
2464 * getting more interrupts, otherwise leave this clear. This prevents a
2465 * race in the hw when coming out of rc6: There's a tiny window where
2466 * the hw runs at the minimal clock before selecting the desired
2467 * frequency, if the down threshold expires in that window we will not
2468 * receive a down interrupt. */
2469 if (*val <= dev_priv->rps.min_delay) {
2470 *val = dev_priv->rps.min_delay;
2471 limits |= dev_priv->rps.min_delay << 16;
2472 }
2473
2474 return limits;
2475 }
2476
2477 void gen6_set_rps(struct drm_device *dev, u8 val)
2478 {
2479 struct drm_i915_private *dev_priv = dev->dev_private;
2480 u32 limits = gen6_rps_limits(dev_priv, &val);
2481
2482 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
2483 WARN_ON(val > dev_priv->rps.max_delay);
2484 WARN_ON(val < dev_priv->rps.min_delay);
2485
2486 if (val == dev_priv->rps.cur_delay)
2487 return;
2488
2489 if (IS_HASWELL(dev))
2490 I915_WRITE(GEN6_RPNSWREQ,
2491 HSW_FREQUENCY(val));
2492 else
2493 I915_WRITE(GEN6_RPNSWREQ,
2494 GEN6_FREQUENCY(val) |
2495 GEN6_OFFSET(0) |
2496 GEN6_AGGRESSIVE_TURBO);
2497
2498 /* Make sure we continue to get interrupts
2499 * until we hit the minimum or maximum frequencies.
2500 */
2501 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
2502
2503 POSTING_READ(GEN6_RPNSWREQ);
2504
2505 dev_priv->rps.cur_delay = val;
2506
2507 trace_intel_gpu_freq_change(val * 50);
2508 }
2509
2510 void valleyview_set_rps(struct drm_device *dev, u8 val)
2511 {
2512 struct drm_i915_private *dev_priv = dev->dev_private;
2513 unsigned long timeout = jiffies + msecs_to_jiffies(10);
2514 u32 limits = gen6_rps_limits(dev_priv, &val);
2515 u32 pval;
2516
2517 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
2518 WARN_ON(val > dev_priv->rps.max_delay);
2519 WARN_ON(val < dev_priv->rps.min_delay);
2520
2521 DRM_DEBUG_DRIVER("gpu freq request from %d to %d\n",
2522 vlv_gpu_freq(dev_priv->mem_freq,
2523 dev_priv->rps.cur_delay),
2524 vlv_gpu_freq(dev_priv->mem_freq, val));
2525
2526 if (val == dev_priv->rps.cur_delay)
2527 return;
2528
2529 valleyview_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
2530
2531 do {
2532 valleyview_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS, &pval);
2533 if (time_after(jiffies, timeout)) {
2534 DRM_DEBUG_DRIVER("timed out waiting for Punit\n");
2535 break;
2536 }
2537 udelay(10);
2538 } while (pval & 1);
2539
2540 valleyview_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS, &pval);
2541 if ((pval >> 8) != val)
2542 DRM_DEBUG_DRIVER("punit overrode freq: %d requested, but got %d\n",
2543 val, pval >> 8);
2544
2545 /* Make sure we continue to get interrupts
2546 * until we hit the minimum or maximum frequencies.
2547 */
2548 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
2549
2550 dev_priv->rps.cur_delay = pval >> 8;
2551
2552 trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv->mem_freq, val));
2553 }
2554
2555
2556 static void gen6_disable_rps(struct drm_device *dev)
2557 {
2558 struct drm_i915_private *dev_priv = dev->dev_private;
2559
2560 I915_WRITE(GEN6_RC_CONTROL, 0);
2561 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
2562 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
2563 I915_WRITE(GEN6_PMIER, 0);
2564 /* Complete PM interrupt masking here doesn't race with the rps work
2565 * item again unmasking PM interrupts because that is using a different
2566 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
2567 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
2568
2569 spin_lock_irq(&dev_priv->rps.lock);
2570 dev_priv->rps.pm_iir = 0;
2571 spin_unlock_irq(&dev_priv->rps.lock);
2572
2573 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
2574 }
2575
2576 static void valleyview_disable_rps(struct drm_device *dev)
2577 {
2578 struct drm_i915_private *dev_priv = dev->dev_private;
2579
2580 I915_WRITE(GEN6_RC_CONTROL, 0);
2581 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
2582 I915_WRITE(GEN6_PMIER, 0);
2583 /* Complete PM interrupt masking here doesn't race with the rps work
2584 * item again unmasking PM interrupts because that is using a different
2585 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
2586 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
2587
2588 spin_lock_irq(&dev_priv->rps.lock);
2589 dev_priv->rps.pm_iir = 0;
2590 spin_unlock_irq(&dev_priv->rps.lock);
2591
2592 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
2593
2594 if (dev_priv->vlv_pctx) {
2595 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
2596 dev_priv->vlv_pctx = NULL;
2597 }
2598 }
2599
2600 int intel_enable_rc6(const struct drm_device *dev)
2601 {
2602 /* Respect the kernel parameter if it is set */
2603 if (i915_enable_rc6 >= 0)
2604 return i915_enable_rc6;
2605
2606 /* Disable RC6 on Ironlake */
2607 if (INTEL_INFO(dev)->gen == 5)
2608 return 0;
2609
2610 if (IS_HASWELL(dev)) {
2611 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
2612 return INTEL_RC6_ENABLE;
2613 }
2614
2615 /* snb/ivb have more than one rc6 state. */
2616 if (INTEL_INFO(dev)->gen == 6) {
2617 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
2618 return INTEL_RC6_ENABLE;
2619 }
2620
2621 DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n");
2622 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
2623 }
2624
2625 static void gen6_enable_rps(struct drm_device *dev)
2626 {
2627 struct drm_i915_private *dev_priv = dev->dev_private;
2628 struct intel_ring_buffer *ring;
2629 u32 rp_state_cap;
2630 u32 gt_perf_status;
2631 u32 rc6vids, pcu_mbox, rc6_mask = 0;
2632 u32 gtfifodbg;
2633 int rc6_mode;
2634 int i, ret;
2635
2636 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
2637
2638 /* Here begins a magic sequence of register writes to enable
2639 * auto-downclocking.
2640 *
2641 * Perhaps there might be some value in exposing these to
2642 * userspace...
2643 */
2644 I915_WRITE(GEN6_RC_STATE, 0);
2645
2646 /* Clear the DBG now so we don't confuse earlier errors */
2647 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
2648 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
2649 I915_WRITE(GTFIFODBG, gtfifodbg);
2650 }
2651
2652 gen6_gt_force_wake_get(dev_priv);
2653
2654 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
2655 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
2656
2657 /* In units of 50MHz */
2658 dev_priv->rps.hw_max = dev_priv->rps.max_delay = rp_state_cap & 0xff;
2659 dev_priv->rps.min_delay = (rp_state_cap & 0xff0000) >> 16;
2660 dev_priv->rps.cur_delay = 0;
2661
2662 /* disable the counters and set deterministic thresholds */
2663 I915_WRITE(GEN6_RC_CONTROL, 0);
2664
2665 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
2666 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
2667 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
2668 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
2669 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
2670
2671 for_each_ring(ring, dev_priv, i)
2672 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2673
2674 I915_WRITE(GEN6_RC_SLEEP, 0);
2675 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
2676 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
2677 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2678 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
2679
2680 /* Check if we are enabling RC6 */
2681 rc6_mode = intel_enable_rc6(dev_priv->dev);
2682 if (rc6_mode & INTEL_RC6_ENABLE)
2683 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
2684
2685 /* We don't use those on Haswell */
2686 if (!IS_HASWELL(dev)) {
2687 if (rc6_mode & INTEL_RC6p_ENABLE)
2688 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2689
2690 if (rc6_mode & INTEL_RC6pp_ENABLE)
2691 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
2692 }
2693
2694 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
2695 (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
2696 (rc6_mask & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
2697 (rc6_mask & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
2698
2699 I915_WRITE(GEN6_RC_CONTROL,
2700 rc6_mask |
2701 GEN6_RC_CTL_EI_MODE(1) |
2702 GEN6_RC_CTL_HW_ENABLE);
2703
2704 if (IS_HASWELL(dev)) {
2705 I915_WRITE(GEN6_RPNSWREQ,
2706 HSW_FREQUENCY(10));
2707 I915_WRITE(GEN6_RC_VIDEO_FREQ,
2708 HSW_FREQUENCY(12));
2709 } else {
2710 I915_WRITE(GEN6_RPNSWREQ,
2711 GEN6_FREQUENCY(10) |
2712 GEN6_OFFSET(0) |
2713 GEN6_AGGRESSIVE_TURBO);
2714 I915_WRITE(GEN6_RC_VIDEO_FREQ,
2715 GEN6_FREQUENCY(12));
2716 }
2717
2718 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
2719 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
2720 dev_priv->rps.max_delay << 24 |
2721 dev_priv->rps.min_delay << 16);
2722
2723 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
2724 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
2725 I915_WRITE(GEN6_RP_UP_EI, 66000);
2726 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
2727
2728 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2729 I915_WRITE(GEN6_RP_CONTROL,
2730 GEN6_RP_MEDIA_TURBO |
2731 GEN6_RP_MEDIA_HW_NORMAL_MODE |
2732 GEN6_RP_MEDIA_IS_GFX |
2733 GEN6_RP_ENABLE |
2734 GEN6_RP_UP_BUSY_AVG |
2735 (IS_HASWELL(dev) ? GEN7_RP_DOWN_IDLE_AVG : GEN6_RP_DOWN_IDLE_CONT));
2736
2737 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
2738 if (!ret && (IS_GEN6(dev) || IS_IVYBRIDGE(dev))) {
2739 pcu_mbox = 0;
2740 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
2741 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
2742 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
2743 (dev_priv->rps.max_delay & 0xff) * 50,
2744 (pcu_mbox & 0xff) * 50);
2745 dev_priv->rps.hw_max = pcu_mbox & 0xff;
2746 }
2747 } else {
2748 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
2749 }
2750
2751 gen6_set_rps(dev_priv->dev, (gt_perf_status & 0xff00) >> 8);
2752
2753 /* requires MSI enabled */
2754 I915_WRITE(GEN6_PMIER, GEN6_PM_DEFERRED_EVENTS);
2755 spin_lock_irq(&dev_priv->rps.lock);
2756 WARN_ON(dev_priv->rps.pm_iir != 0);
2757 I915_WRITE(GEN6_PMIMR, 0);
2758 spin_unlock_irq(&dev_priv->rps.lock);
2759 /* enable all PM interrupts */
2760 I915_WRITE(GEN6_PMINTRMSK, 0);
2761
2762 rc6vids = 0;
2763 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
2764 if (IS_GEN6(dev) && ret) {
2765 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
2766 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
2767 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
2768 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
2769 rc6vids &= 0xffff00;
2770 rc6vids |= GEN6_ENCODE_RC6_VID(450);
2771 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
2772 if (ret)
2773 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
2774 }
2775
2776 gen6_gt_force_wake_put(dev_priv);
2777 }
2778
2779 static void gen6_update_ring_freq(struct drm_device *dev)
2780 {
2781 struct drm_i915_private *dev_priv = dev->dev_private;
2782 int min_freq = 15;
2783 unsigned int gpu_freq;
2784 unsigned int max_ia_freq, min_ring_freq;
2785 int scaling_factor = 180;
2786
2787 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
2788
2789 max_ia_freq = cpufreq_quick_get_max(0);
2790 /*
2791 * Default to measured freq if none found, PCU will ensure we don't go
2792 * over
2793 */
2794 if (!max_ia_freq)
2795 max_ia_freq = tsc_khz;
2796
2797 /* Convert from kHz to MHz */
2798 max_ia_freq /= 1000;
2799
2800 min_ring_freq = I915_READ(MCHBAR_MIRROR_BASE_SNB + DCLK);
2801 /* convert DDR frequency from units of 133.3MHz to bandwidth */
2802 min_ring_freq = (2 * 4 * min_ring_freq + 2) / 3;
2803
2804 /*
2805 * For each potential GPU frequency, load a ring frequency we'd like
2806 * to use for memory access. We do this by specifying the IA frequency
2807 * the PCU should use as a reference to determine the ring frequency.
2808 */
2809 for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay;
2810 gpu_freq--) {
2811 int diff = dev_priv->rps.max_delay - gpu_freq;
2812 unsigned int ia_freq = 0, ring_freq = 0;
2813
2814 if (IS_HASWELL(dev)) {
2815 ring_freq = (gpu_freq * 5 + 3) / 4;
2816 ring_freq = max(min_ring_freq, ring_freq);
2817 /* leave ia_freq as the default, chosen by cpufreq */
2818 } else {
2819 /* On older processors, there is no separate ring
2820 * clock domain, so in order to boost the bandwidth
2821 * of the ring, we need to upclock the CPU (ia_freq).
2822 *
2823 * For GPU frequencies less than 750MHz,
2824 * just use the lowest ring freq.
2825 */
2826 if (gpu_freq < min_freq)
2827 ia_freq = 800;
2828 else
2829 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
2830 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
2831 }
2832
2833 sandybridge_pcode_write(dev_priv,
2834 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
2835 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
2836 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
2837 gpu_freq);
2838 }
2839 }
2840
2841 int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
2842 {
2843 u32 val, rp0;
2844
2845 valleyview_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE, &val);
2846
2847 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
2848 /* Clamp to max */
2849 rp0 = min_t(u32, rp0, 0xea);
2850
2851 return rp0;
2852 }
2853
2854 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
2855 {
2856 u32 val, rpe;
2857
2858 valleyview_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO, &val);
2859 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
2860 valleyview_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI, &val);
2861 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
2862
2863 return rpe;
2864 }
2865
2866 int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
2867 {
2868 u32 val;
2869
2870 valleyview_punit_read(dev_priv, PUNIT_REG_GPU_LFM, &val);
2871
2872 return val & 0xff;
2873 }
2874
2875 static void vlv_rps_timer_work(struct work_struct *work)
2876 {
2877 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
2878 rps.vlv_work.work);
2879
2880 /*
2881 * Timer fired, we must be idle. Drop to min voltage state.
2882 * Note: we use RPe here since it should match the
2883 * Vmin we were shooting for. That should give us better
2884 * perf when we come back out of RC6 than if we used the
2885 * min freq available.
2886 */
2887 mutex_lock(&dev_priv->rps.hw_lock);
2888 valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
2889 mutex_unlock(&dev_priv->rps.hw_lock);
2890 }
2891
2892 static void valleyview_setup_pctx(struct drm_device *dev)
2893 {
2894 struct drm_i915_private *dev_priv = dev->dev_private;
2895 struct drm_i915_gem_object *pctx;
2896 unsigned long pctx_paddr;
2897 u32 pcbr;
2898 int pctx_size = 24*1024;
2899
2900 pcbr = I915_READ(VLV_PCBR);
2901 if (pcbr) {
2902 /* BIOS set it up already, grab the pre-alloc'd space */
2903 int pcbr_offset;
2904
2905 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
2906 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
2907 pcbr_offset,
2908 -1,
2909 pctx_size);
2910 goto out;
2911 }
2912
2913 /*
2914 * From the Gunit register HAS:
2915 * The Gfx driver is expected to program this register and ensure
2916 * proper allocation within Gfx stolen memory. For example, this
2917 * register should be programmed such than the PCBR range does not
2918 * overlap with other ranges, such as the frame buffer, protected
2919 * memory, or any other relevant ranges.
2920 */
2921 pctx = i915_gem_object_create_stolen(dev, pctx_size);
2922 if (!pctx) {
2923 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
2924 return;
2925 }
2926
2927 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
2928 I915_WRITE(VLV_PCBR, pctx_paddr);
2929
2930 out:
2931 dev_priv->vlv_pctx = pctx;
2932 }
2933
2934 static void valleyview_enable_rps(struct drm_device *dev)
2935 {
2936 struct drm_i915_private *dev_priv = dev->dev_private;
2937 struct intel_ring_buffer *ring;
2938 u32 gtfifodbg, val, rpe;
2939 int i;
2940
2941 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
2942
2943 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
2944 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
2945 I915_WRITE(GTFIFODBG, gtfifodbg);
2946 }
2947
2948 valleyview_setup_pctx(dev);
2949
2950 gen6_gt_force_wake_get(dev_priv);
2951
2952 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
2953 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
2954 I915_WRITE(GEN6_RP_UP_EI, 66000);
2955 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
2956
2957 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2958
2959 I915_WRITE(GEN6_RP_CONTROL,
2960 GEN6_RP_MEDIA_TURBO |
2961 GEN6_RP_MEDIA_HW_NORMAL_MODE |
2962 GEN6_RP_MEDIA_IS_GFX |
2963 GEN6_RP_ENABLE |
2964 GEN6_RP_UP_BUSY_AVG |
2965 GEN6_RP_DOWN_IDLE_CONT);
2966
2967 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
2968 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
2969 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
2970
2971 for_each_ring(ring, dev_priv, i)
2972 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2973
2974 I915_WRITE(GEN6_RC6_THRESHOLD, 0xc350);
2975
2976 /* allows RC6 residency counter to work */
2977 I915_WRITE(0x138104, _MASKED_BIT_ENABLE(0x3));
2978 I915_WRITE(GEN6_RC_CONTROL,
2979 GEN7_RC_CTL_TO_MODE);
2980
2981 valleyview_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS, &val);
2982 switch ((val >> 6) & 3) {
2983 case 0:
2984 case 1:
2985 dev_priv->mem_freq = 800;
2986 break;
2987 case 2:
2988 dev_priv->mem_freq = 1066;
2989 break;
2990 case 3:
2991 dev_priv->mem_freq = 1333;
2992 break;
2993 }
2994 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
2995
2996 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
2997 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
2998
2999 DRM_DEBUG_DRIVER("current GPU freq: %d\n",
3000 vlv_gpu_freq(dev_priv->mem_freq, (val >> 8) & 0xff));
3001 dev_priv->rps.cur_delay = (val >> 8) & 0xff;
3002
3003 dev_priv->rps.max_delay = valleyview_rps_max_freq(dev_priv);
3004 dev_priv->rps.hw_max = dev_priv->rps.max_delay;
3005 DRM_DEBUG_DRIVER("max GPU freq: %d\n", vlv_gpu_freq(dev_priv->mem_freq,
3006 dev_priv->rps.max_delay));
3007
3008 rpe = valleyview_rps_rpe_freq(dev_priv);
3009 DRM_DEBUG_DRIVER("RPe GPU freq: %d\n",
3010 vlv_gpu_freq(dev_priv->mem_freq, rpe));
3011 dev_priv->rps.rpe_delay = rpe;
3012
3013 val = valleyview_rps_min_freq(dev_priv);
3014 DRM_DEBUG_DRIVER("min GPU freq: %d\n", vlv_gpu_freq(dev_priv->mem_freq,
3015 val));
3016 dev_priv->rps.min_delay = val;
3017
3018 DRM_DEBUG_DRIVER("setting GPU freq to %d\n",
3019 vlv_gpu_freq(dev_priv->mem_freq, rpe));
3020
3021 INIT_DELAYED_WORK(&dev_priv->rps.vlv_work, vlv_rps_timer_work);
3022
3023 valleyview_set_rps(dev_priv->dev, rpe);
3024
3025 /* requires MSI enabled */
3026 I915_WRITE(GEN6_PMIER, GEN6_PM_DEFERRED_EVENTS);
3027 spin_lock_irq(&dev_priv->rps.lock);
3028 WARN_ON(dev_priv->rps.pm_iir != 0);
3029 I915_WRITE(GEN6_PMIMR, 0);
3030 spin_unlock_irq(&dev_priv->rps.lock);
3031 /* enable all PM interrupts */
3032 I915_WRITE(GEN6_PMINTRMSK, 0);
3033
3034 gen6_gt_force_wake_put(dev_priv);
3035 }
3036
3037 void ironlake_teardown_rc6(struct drm_device *dev)
3038 {
3039 struct drm_i915_private *dev_priv = dev->dev_private;
3040
3041 if (dev_priv->ips.renderctx) {
3042 i915_gem_object_unpin(dev_priv->ips.renderctx);
3043 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
3044 dev_priv->ips.renderctx = NULL;
3045 }
3046
3047 if (dev_priv->ips.pwrctx) {
3048 i915_gem_object_unpin(dev_priv->ips.pwrctx);
3049 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
3050 dev_priv->ips.pwrctx = NULL;
3051 }
3052 }
3053
3054 static void ironlake_disable_rc6(struct drm_device *dev)
3055 {
3056 struct drm_i915_private *dev_priv = dev->dev_private;
3057
3058 if (I915_READ(PWRCTXA)) {
3059 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
3060 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
3061 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
3062 50);
3063
3064 I915_WRITE(PWRCTXA, 0);
3065 POSTING_READ(PWRCTXA);
3066
3067 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
3068 POSTING_READ(RSTDBYCTL);
3069 }
3070 }
3071
3072 static int ironlake_setup_rc6(struct drm_device *dev)
3073 {
3074 struct drm_i915_private *dev_priv = dev->dev_private;
3075
3076 if (dev_priv->ips.renderctx == NULL)
3077 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
3078 if (!dev_priv->ips.renderctx)
3079 return -ENOMEM;
3080
3081 if (dev_priv->ips.pwrctx == NULL)
3082 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
3083 if (!dev_priv->ips.pwrctx) {
3084 ironlake_teardown_rc6(dev);
3085 return -ENOMEM;
3086 }
3087
3088 return 0;
3089 }
3090
3091 static void ironlake_enable_rc6(struct drm_device *dev)
3092 {
3093 struct drm_i915_private *dev_priv = dev->dev_private;
3094 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
3095 bool was_interruptible;
3096 int ret;
3097
3098 /* rc6 disabled by default due to repeated reports of hanging during
3099 * boot and resume.
3100 */
3101 if (!intel_enable_rc6(dev))
3102 return;
3103
3104 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3105
3106 ret = ironlake_setup_rc6(dev);
3107 if (ret)
3108 return;
3109
3110 was_interruptible = dev_priv->mm.interruptible;
3111 dev_priv->mm.interruptible = false;
3112
3113 /*
3114 * GPU can automatically power down the render unit if given a page
3115 * to save state.
3116 */
3117 ret = intel_ring_begin(ring, 6);
3118 if (ret) {
3119 ironlake_teardown_rc6(dev);
3120 dev_priv->mm.interruptible = was_interruptible;
3121 return;
3122 }
3123
3124 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
3125 intel_ring_emit(ring, MI_SET_CONTEXT);
3126 intel_ring_emit(ring, dev_priv->ips.renderctx->gtt_offset |
3127 MI_MM_SPACE_GTT |
3128 MI_SAVE_EXT_STATE_EN |
3129 MI_RESTORE_EXT_STATE_EN |
3130 MI_RESTORE_INHIBIT);
3131 intel_ring_emit(ring, MI_SUSPEND_FLUSH);
3132 intel_ring_emit(ring, MI_NOOP);
3133 intel_ring_emit(ring, MI_FLUSH);
3134 intel_ring_advance(ring);
3135
3136 /*
3137 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
3138 * does an implicit flush, combined with MI_FLUSH above, it should be
3139 * safe to assume that renderctx is valid
3140 */
3141 ret = intel_ring_idle(ring);
3142 dev_priv->mm.interruptible = was_interruptible;
3143 if (ret) {
3144 DRM_ERROR("failed to enable ironlake power savings\n");
3145 ironlake_teardown_rc6(dev);
3146 return;
3147 }
3148
3149 I915_WRITE(PWRCTXA, dev_priv->ips.pwrctx->gtt_offset | PWRCTX_EN);
3150 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
3151 }
3152
3153 static unsigned long intel_pxfreq(u32 vidfreq)
3154 {
3155 unsigned long freq;
3156 int div = (vidfreq & 0x3f0000) >> 16;
3157 int post = (vidfreq & 0x3000) >> 12;
3158 int pre = (vidfreq & 0x7);
3159
3160 if (!pre)
3161 return 0;
3162
3163 freq = ((div * 133333) / ((1<<post) * pre));
3164
3165 return freq;
3166 }
3167
3168 static const struct cparams {
3169 u16 i;
3170 u16 t;
3171 u16 m;
3172 u16 c;
3173 } cparams[] = {
3174 { 1, 1333, 301, 28664 },
3175 { 1, 1066, 294, 24460 },
3176 { 1, 800, 294, 25192 },
3177 { 0, 1333, 276, 27605 },
3178 { 0, 1066, 276, 27605 },
3179 { 0, 800, 231, 23784 },
3180 };
3181
3182 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
3183 {
3184 u64 total_count, diff, ret;
3185 u32 count1, count2, count3, m = 0, c = 0;
3186 unsigned long now = jiffies_to_msecs(jiffies), diff1;
3187 int i;
3188
3189 assert_spin_locked(&mchdev_lock);
3190
3191 diff1 = now - dev_priv->ips.last_time1;
3192
3193 /* Prevent division-by-zero if we are asking too fast.
3194 * Also, we don't get interesting results if we are polling
3195 * faster than once in 10ms, so just return the saved value
3196 * in such cases.
3197 */
3198 if (diff1 <= 10)
3199 return dev_priv->ips.chipset_power;
3200
3201 count1 = I915_READ(DMIEC);
3202 count2 = I915_READ(DDREC);
3203 count3 = I915_READ(CSIEC);
3204
3205 total_count = count1 + count2 + count3;
3206
3207 /* FIXME: handle per-counter overflow */
3208 if (total_count < dev_priv->ips.last_count1) {
3209 diff = ~0UL - dev_priv->ips.last_count1;
3210 diff += total_count;
3211 } else {
3212 diff = total_count - dev_priv->ips.last_count1;
3213 }
3214
3215 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
3216 if (cparams[i].i == dev_priv->ips.c_m &&
3217 cparams[i].t == dev_priv->ips.r_t) {
3218 m = cparams[i].m;
3219 c = cparams[i].c;
3220 break;
3221 }
3222 }
3223
3224 diff = div_u64(diff, diff1);
3225 ret = ((m * diff) + c);
3226 ret = div_u64(ret, 10);
3227
3228 dev_priv->ips.last_count1 = total_count;
3229 dev_priv->ips.last_time1 = now;
3230
3231 dev_priv->ips.chipset_power = ret;
3232
3233 return ret;
3234 }
3235
3236 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
3237 {
3238 unsigned long val;
3239
3240 if (dev_priv->info->gen != 5)
3241 return 0;
3242
3243 spin_lock_irq(&mchdev_lock);
3244
3245 val = __i915_chipset_val(dev_priv);
3246
3247 spin_unlock_irq(&mchdev_lock);
3248
3249 return val;
3250 }
3251
3252 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
3253 {
3254 unsigned long m, x, b;
3255 u32 tsfs;
3256
3257 tsfs = I915_READ(TSFS);
3258
3259 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
3260 x = I915_READ8(TR1);
3261
3262 b = tsfs & TSFS_INTR_MASK;
3263
3264 return ((m * x) / 127) - b;
3265 }
3266
3267 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
3268 {
3269 static const struct v_table {
3270 u16 vd; /* in .1 mil */
3271 u16 vm; /* in .1 mil */
3272 } v_table[] = {
3273 { 0, 0, },
3274 { 375, 0, },
3275 { 500, 0, },
3276 { 625, 0, },
3277 { 750, 0, },
3278 { 875, 0, },
3279 { 1000, 0, },
3280 { 1125, 0, },
3281 { 4125, 3000, },
3282 { 4125, 3000, },
3283 { 4125, 3000, },
3284 { 4125, 3000, },
3285 { 4125, 3000, },
3286 { 4125, 3000, },
3287 { 4125, 3000, },
3288 { 4125, 3000, },
3289 { 4125, 3000, },
3290 { 4125, 3000, },
3291 { 4125, 3000, },
3292 { 4125, 3000, },
3293 { 4125, 3000, },
3294 { 4125, 3000, },
3295 { 4125, 3000, },
3296 { 4125, 3000, },
3297 { 4125, 3000, },
3298 { 4125, 3000, },
3299 { 4125, 3000, },
3300 { 4125, 3000, },
3301 { 4125, 3000, },
3302 { 4125, 3000, },
3303 { 4125, 3000, },
3304 { 4125, 3000, },
3305 { 4250, 3125, },
3306 { 4375, 3250, },
3307 { 4500, 3375, },
3308 { 4625, 3500, },
3309 { 4750, 3625, },
3310 { 4875, 3750, },
3311 { 5000, 3875, },
3312 { 5125, 4000, },
3313 { 5250, 4125, },
3314 { 5375, 4250, },
3315 { 5500, 4375, },
3316 { 5625, 4500, },
3317 { 5750, 4625, },
3318 { 5875, 4750, },
3319 { 6000, 4875, },
3320 { 6125, 5000, },
3321 { 6250, 5125, },
3322 { 6375, 5250, },
3323 { 6500, 5375, },
3324 { 6625, 5500, },
3325 { 6750, 5625, },
3326 { 6875, 5750, },
3327 { 7000, 5875, },
3328 { 7125, 6000, },
3329 { 7250, 6125, },
3330 { 7375, 6250, },
3331 { 7500, 6375, },
3332 { 7625, 6500, },
3333 { 7750, 6625, },
3334 { 7875, 6750, },
3335 { 8000, 6875, },
3336 { 8125, 7000, },
3337 { 8250, 7125, },
3338 { 8375, 7250, },
3339 { 8500, 7375, },
3340 { 8625, 7500, },
3341 { 8750, 7625, },
3342 { 8875, 7750, },
3343 { 9000, 7875, },
3344 { 9125, 8000, },
3345 { 9250, 8125, },
3346 { 9375, 8250, },
3347 { 9500, 8375, },
3348 { 9625, 8500, },
3349 { 9750, 8625, },
3350 { 9875, 8750, },
3351 { 10000, 8875, },
3352 { 10125, 9000, },
3353 { 10250, 9125, },
3354 { 10375, 9250, },
3355 { 10500, 9375, },
3356 { 10625, 9500, },
3357 { 10750, 9625, },
3358 { 10875, 9750, },
3359 { 11000, 9875, },
3360 { 11125, 10000, },
3361 { 11250, 10125, },
3362 { 11375, 10250, },
3363 { 11500, 10375, },
3364 { 11625, 10500, },
3365 { 11750, 10625, },
3366 { 11875, 10750, },
3367 { 12000, 10875, },
3368 { 12125, 11000, },
3369 { 12250, 11125, },
3370 { 12375, 11250, },
3371 { 12500, 11375, },
3372 { 12625, 11500, },
3373 { 12750, 11625, },
3374 { 12875, 11750, },
3375 { 13000, 11875, },
3376 { 13125, 12000, },
3377 { 13250, 12125, },
3378 { 13375, 12250, },
3379 { 13500, 12375, },
3380 { 13625, 12500, },
3381 { 13750, 12625, },
3382 { 13875, 12750, },
3383 { 14000, 12875, },
3384 { 14125, 13000, },
3385 { 14250, 13125, },
3386 { 14375, 13250, },
3387 { 14500, 13375, },
3388 { 14625, 13500, },
3389 { 14750, 13625, },
3390 { 14875, 13750, },
3391 { 15000, 13875, },
3392 { 15125, 14000, },
3393 { 15250, 14125, },
3394 { 15375, 14250, },
3395 { 15500, 14375, },
3396 { 15625, 14500, },
3397 { 15750, 14625, },
3398 { 15875, 14750, },
3399 { 16000, 14875, },
3400 { 16125, 15000, },
3401 };
3402 if (dev_priv->info->is_mobile)
3403 return v_table[pxvid].vm;
3404 else
3405 return v_table[pxvid].vd;
3406 }
3407
3408 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
3409 {
3410 struct timespec now, diff1;
3411 u64 diff;
3412 unsigned long diffms;
3413 u32 count;
3414
3415 assert_spin_locked(&mchdev_lock);
3416
3417 getrawmonotonic(&now);
3418 diff1 = timespec_sub(now, dev_priv->ips.last_time2);
3419
3420 /* Don't divide by 0 */
3421 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
3422 if (!diffms)
3423 return;
3424
3425 count = I915_READ(GFXEC);
3426
3427 if (count < dev_priv->ips.last_count2) {
3428 diff = ~0UL - dev_priv->ips.last_count2;
3429 diff += count;
3430 } else {
3431 diff = count - dev_priv->ips.last_count2;
3432 }
3433
3434 dev_priv->ips.last_count2 = count;
3435 dev_priv->ips.last_time2 = now;
3436
3437 /* More magic constants... */
3438 diff = diff * 1181;
3439 diff = div_u64(diff, diffms * 10);
3440 dev_priv->ips.gfx_power = diff;
3441 }
3442
3443 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
3444 {
3445 if (dev_priv->info->gen != 5)
3446 return;
3447
3448 spin_lock_irq(&mchdev_lock);
3449
3450 __i915_update_gfx_val(dev_priv);
3451
3452 spin_unlock_irq(&mchdev_lock);
3453 }
3454
3455 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
3456 {
3457 unsigned long t, corr, state1, corr2, state2;
3458 u32 pxvid, ext_v;
3459
3460 assert_spin_locked(&mchdev_lock);
3461
3462 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4));
3463 pxvid = (pxvid >> 24) & 0x7f;
3464 ext_v = pvid_to_extvid(dev_priv, pxvid);
3465
3466 state1 = ext_v;
3467
3468 t = i915_mch_val(dev_priv);
3469
3470 /* Revel in the empirically derived constants */
3471
3472 /* Correction factor in 1/100000 units */
3473 if (t > 80)
3474 corr = ((t * 2349) + 135940);
3475 else if (t >= 50)
3476 corr = ((t * 964) + 29317);
3477 else /* < 50 */
3478 corr = ((t * 301) + 1004);
3479
3480 corr = corr * ((150142 * state1) / 10000 - 78642);
3481 corr /= 100000;
3482 corr2 = (corr * dev_priv->ips.corr);
3483
3484 state2 = (corr2 * state1) / 10000;
3485 state2 /= 100; /* convert to mW */
3486
3487 __i915_update_gfx_val(dev_priv);
3488
3489 return dev_priv->ips.gfx_power + state2;
3490 }
3491
3492 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
3493 {
3494 unsigned long val;
3495
3496 if (dev_priv->info->gen != 5)
3497 return 0;
3498
3499 spin_lock_irq(&mchdev_lock);
3500
3501 val = __i915_gfx_val(dev_priv);
3502
3503 spin_unlock_irq(&mchdev_lock);
3504
3505 return val;
3506 }
3507
3508 /**
3509 * i915_read_mch_val - return value for IPS use
3510 *
3511 * Calculate and return a value for the IPS driver to use when deciding whether
3512 * we have thermal and power headroom to increase CPU or GPU power budget.
3513 */
3514 unsigned long i915_read_mch_val(void)
3515 {
3516 struct drm_i915_private *dev_priv;
3517 unsigned long chipset_val, graphics_val, ret = 0;
3518
3519 spin_lock_irq(&mchdev_lock);
3520 if (!i915_mch_dev)
3521 goto out_unlock;
3522 dev_priv = i915_mch_dev;
3523
3524 chipset_val = __i915_chipset_val(dev_priv);
3525 graphics_val = __i915_gfx_val(dev_priv);
3526
3527 ret = chipset_val + graphics_val;
3528
3529 out_unlock:
3530 spin_unlock_irq(&mchdev_lock);
3531
3532 return ret;
3533 }
3534 EXPORT_SYMBOL_GPL(i915_read_mch_val);
3535
3536 /**
3537 * i915_gpu_raise - raise GPU frequency limit
3538 *
3539 * Raise the limit; IPS indicates we have thermal headroom.
3540 */
3541 bool i915_gpu_raise(void)
3542 {
3543 struct drm_i915_private *dev_priv;
3544 bool ret = true;
3545
3546 spin_lock_irq(&mchdev_lock);
3547 if (!i915_mch_dev) {
3548 ret = false;
3549 goto out_unlock;
3550 }
3551 dev_priv = i915_mch_dev;
3552
3553 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
3554 dev_priv->ips.max_delay--;
3555
3556 out_unlock:
3557 spin_unlock_irq(&mchdev_lock);
3558
3559 return ret;
3560 }
3561 EXPORT_SYMBOL_GPL(i915_gpu_raise);
3562
3563 /**
3564 * i915_gpu_lower - lower GPU frequency limit
3565 *
3566 * IPS indicates we're close to a thermal limit, so throttle back the GPU
3567 * frequency maximum.
3568 */
3569 bool i915_gpu_lower(void)
3570 {
3571 struct drm_i915_private *dev_priv;
3572 bool ret = true;
3573
3574 spin_lock_irq(&mchdev_lock);
3575 if (!i915_mch_dev) {
3576 ret = false;
3577 goto out_unlock;
3578 }
3579 dev_priv = i915_mch_dev;
3580
3581 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
3582 dev_priv->ips.max_delay++;
3583
3584 out_unlock:
3585 spin_unlock_irq(&mchdev_lock);
3586
3587 return ret;
3588 }
3589 EXPORT_SYMBOL_GPL(i915_gpu_lower);
3590
3591 /**
3592 * i915_gpu_busy - indicate GPU business to IPS
3593 *
3594 * Tell the IPS driver whether or not the GPU is busy.
3595 */
3596 bool i915_gpu_busy(void)
3597 {
3598 struct drm_i915_private *dev_priv;
3599 struct intel_ring_buffer *ring;
3600 bool ret = false;
3601 int i;
3602
3603 spin_lock_irq(&mchdev_lock);
3604 if (!i915_mch_dev)
3605 goto out_unlock;
3606 dev_priv = i915_mch_dev;
3607
3608 for_each_ring(ring, dev_priv, i)
3609 ret |= !list_empty(&ring->request_list);
3610
3611 out_unlock:
3612 spin_unlock_irq(&mchdev_lock);
3613
3614 return ret;
3615 }
3616 EXPORT_SYMBOL_GPL(i915_gpu_busy);
3617
3618 /**
3619 * i915_gpu_turbo_disable - disable graphics turbo
3620 *
3621 * Disable graphics turbo by resetting the max frequency and setting the
3622 * current frequency to the default.
3623 */
3624 bool i915_gpu_turbo_disable(void)
3625 {
3626 struct drm_i915_private *dev_priv;
3627 bool ret = true;
3628
3629 spin_lock_irq(&mchdev_lock);
3630 if (!i915_mch_dev) {
3631 ret = false;
3632 goto out_unlock;
3633 }
3634 dev_priv = i915_mch_dev;
3635
3636 dev_priv->ips.max_delay = dev_priv->ips.fstart;
3637
3638 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
3639 ret = false;
3640
3641 out_unlock:
3642 spin_unlock_irq(&mchdev_lock);
3643
3644 return ret;
3645 }
3646 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
3647
3648 /**
3649 * Tells the intel_ips driver that the i915 driver is now loaded, if
3650 * IPS got loaded first.
3651 *
3652 * This awkward dance is so that neither module has to depend on the
3653 * other in order for IPS to do the appropriate communication of
3654 * GPU turbo limits to i915.
3655 */
3656 static void
3657 ips_ping_for_i915_load(void)
3658 {
3659 void (*link)(void);
3660
3661 link = symbol_get(ips_link_to_i915_driver);
3662 if (link) {
3663 link();
3664 symbol_put(ips_link_to_i915_driver);
3665 }
3666 }
3667
3668 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
3669 {
3670 /* We only register the i915 ips part with intel-ips once everything is
3671 * set up, to avoid intel-ips sneaking in and reading bogus values. */
3672 spin_lock_irq(&mchdev_lock);
3673 i915_mch_dev = dev_priv;
3674 spin_unlock_irq(&mchdev_lock);
3675
3676 ips_ping_for_i915_load();
3677 }
3678
3679 void intel_gpu_ips_teardown(void)
3680 {
3681 spin_lock_irq(&mchdev_lock);
3682 i915_mch_dev = NULL;
3683 spin_unlock_irq(&mchdev_lock);
3684 }
3685 static void intel_init_emon(struct drm_device *dev)
3686 {
3687 struct drm_i915_private *dev_priv = dev->dev_private;
3688 u32 lcfuse;
3689 u8 pxw[16];
3690 int i;
3691
3692 /* Disable to program */
3693 I915_WRITE(ECR, 0);
3694 POSTING_READ(ECR);
3695
3696 /* Program energy weights for various events */
3697 I915_WRITE(SDEW, 0x15040d00);
3698 I915_WRITE(CSIEW0, 0x007f0000);
3699 I915_WRITE(CSIEW1, 0x1e220004);
3700 I915_WRITE(CSIEW2, 0x04000004);
3701
3702 for (i = 0; i < 5; i++)
3703 I915_WRITE(PEW + (i * 4), 0);
3704 for (i = 0; i < 3; i++)
3705 I915_WRITE(DEW + (i * 4), 0);
3706
3707 /* Program P-state weights to account for frequency power adjustment */
3708 for (i = 0; i < 16; i++) {
3709 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
3710 unsigned long freq = intel_pxfreq(pxvidfreq);
3711 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
3712 PXVFREQ_PX_SHIFT;
3713 unsigned long val;
3714
3715 val = vid * vid;
3716 val *= (freq / 1000);
3717 val *= 255;
3718 val /= (127*127*900);
3719 if (val > 0xff)
3720 DRM_ERROR("bad pxval: %ld\n", val);
3721 pxw[i] = val;
3722 }
3723 /* Render standby states get 0 weight */
3724 pxw[14] = 0;
3725 pxw[15] = 0;
3726
3727 for (i = 0; i < 4; i++) {
3728 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
3729 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
3730 I915_WRITE(PXW + (i * 4), val);
3731 }
3732
3733 /* Adjust magic regs to magic values (more experimental results) */
3734 I915_WRITE(OGW0, 0);
3735 I915_WRITE(OGW1, 0);
3736 I915_WRITE(EG0, 0x00007f00);
3737 I915_WRITE(EG1, 0x0000000e);
3738 I915_WRITE(EG2, 0x000e0000);
3739 I915_WRITE(EG3, 0x68000300);
3740 I915_WRITE(EG4, 0x42000000);
3741 I915_WRITE(EG5, 0x00140031);
3742 I915_WRITE(EG6, 0);
3743 I915_WRITE(EG7, 0);
3744
3745 for (i = 0; i < 8; i++)
3746 I915_WRITE(PXWL + (i * 4), 0);
3747
3748 /* Enable PMON + select events */
3749 I915_WRITE(ECR, 0x80000019);
3750
3751 lcfuse = I915_READ(LCFUSE02);
3752
3753 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
3754 }
3755
3756 void intel_disable_gt_powersave(struct drm_device *dev)
3757 {
3758 struct drm_i915_private *dev_priv = dev->dev_private;
3759
3760 /* Interrupts should be disabled already to avoid re-arming. */
3761 WARN_ON(dev->irq_enabled);
3762
3763 if (IS_IRONLAKE_M(dev)) {
3764 ironlake_disable_drps(dev);
3765 ironlake_disable_rc6(dev);
3766 } else if (INTEL_INFO(dev)->gen >= 6) {
3767 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
3768 cancel_work_sync(&dev_priv->rps.work);
3769 if (IS_VALLEYVIEW(dev))
3770 cancel_delayed_work_sync(&dev_priv->rps.vlv_work);
3771 mutex_lock(&dev_priv->rps.hw_lock);
3772 if (IS_VALLEYVIEW(dev))
3773 valleyview_disable_rps(dev);
3774 else
3775 gen6_disable_rps(dev);
3776 mutex_unlock(&dev_priv->rps.hw_lock);
3777 }
3778 }
3779
3780 static void intel_gen6_powersave_work(struct work_struct *work)
3781 {
3782 struct drm_i915_private *dev_priv =
3783 container_of(work, struct drm_i915_private,
3784 rps.delayed_resume_work.work);
3785 struct drm_device *dev = dev_priv->dev;
3786
3787 mutex_lock(&dev_priv->rps.hw_lock);
3788
3789 if (IS_VALLEYVIEW(dev)) {
3790 valleyview_enable_rps(dev);
3791 } else {
3792 gen6_enable_rps(dev);
3793 gen6_update_ring_freq(dev);
3794 }
3795 mutex_unlock(&dev_priv->rps.hw_lock);
3796 }
3797
3798 void intel_enable_gt_powersave(struct drm_device *dev)
3799 {
3800 struct drm_i915_private *dev_priv = dev->dev_private;
3801
3802 if (IS_IRONLAKE_M(dev)) {
3803 ironlake_enable_drps(dev);
3804 ironlake_enable_rc6(dev);
3805 intel_init_emon(dev);
3806 } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
3807 /*
3808 * PCU communication is slow and this doesn't need to be
3809 * done at any specific time, so do this out of our fast path
3810 * to make resume and init faster.
3811 */
3812 schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
3813 round_jiffies_up_relative(HZ));
3814 }
3815 }
3816
3817 static void ibx_init_clock_gating(struct drm_device *dev)
3818 {
3819 struct drm_i915_private *dev_priv = dev->dev_private;
3820
3821 /*
3822 * On Ibex Peak and Cougar Point, we need to disable clock
3823 * gating for the panel power sequencer or it will fail to
3824 * start up when no ports are active.
3825 */
3826 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
3827 }
3828
3829 static void ironlake_init_clock_gating(struct drm_device *dev)
3830 {
3831 struct drm_i915_private *dev_priv = dev->dev_private;
3832 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
3833
3834 /* Required for FBC */
3835 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
3836 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
3837 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
3838
3839 I915_WRITE(PCH_3DCGDIS0,
3840 MARIUNIT_CLOCK_GATE_DISABLE |
3841 SVSMUNIT_CLOCK_GATE_DISABLE);
3842 I915_WRITE(PCH_3DCGDIS1,
3843 VFMUNIT_CLOCK_GATE_DISABLE);
3844
3845 /*
3846 * According to the spec the following bits should be set in
3847 * order to enable memory self-refresh
3848 * The bit 22/21 of 0x42004
3849 * The bit 5 of 0x42020
3850 * The bit 15 of 0x45000
3851 */
3852 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3853 (I915_READ(ILK_DISPLAY_CHICKEN2) |
3854 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
3855 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
3856 I915_WRITE(DISP_ARB_CTL,
3857 (I915_READ(DISP_ARB_CTL) |
3858 DISP_FBC_WM_DIS));
3859 I915_WRITE(WM3_LP_ILK, 0);
3860 I915_WRITE(WM2_LP_ILK, 0);
3861 I915_WRITE(WM1_LP_ILK, 0);
3862
3863 /*
3864 * Based on the document from hardware guys the following bits
3865 * should be set unconditionally in order to enable FBC.
3866 * The bit 22 of 0x42000
3867 * The bit 22 of 0x42004
3868 * The bit 7,8,9 of 0x42020.
3869 */
3870 if (IS_IRONLAKE_M(dev)) {
3871 I915_WRITE(ILK_DISPLAY_CHICKEN1,
3872 I915_READ(ILK_DISPLAY_CHICKEN1) |
3873 ILK_FBCQ_DIS);
3874 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3875 I915_READ(ILK_DISPLAY_CHICKEN2) |
3876 ILK_DPARB_GATE);
3877 }
3878
3879 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
3880
3881 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3882 I915_READ(ILK_DISPLAY_CHICKEN2) |
3883 ILK_ELPIN_409_SELECT);
3884 I915_WRITE(_3D_CHICKEN2,
3885 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
3886 _3D_CHICKEN2_WM_READ_PIPELINED);
3887
3888 /* WaDisableRenderCachePipelinedFlush:ilk */
3889 I915_WRITE(CACHE_MODE_0,
3890 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3891
3892 ibx_init_clock_gating(dev);
3893 }
3894
3895 static void cpt_init_clock_gating(struct drm_device *dev)
3896 {
3897 struct drm_i915_private *dev_priv = dev->dev_private;
3898 int pipe;
3899 uint32_t val;
3900
3901 /*
3902 * On Ibex Peak and Cougar Point, we need to disable clock
3903 * gating for the panel power sequencer or it will fail to
3904 * start up when no ports are active.
3905 */
3906 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
3907 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
3908 DPLS_EDP_PPS_FIX_DIS);
3909 /* The below fixes the weird display corruption, a few pixels shifted
3910 * downward, on (only) LVDS of some HP laptops with IVY.
3911 */
3912 for_each_pipe(pipe) {
3913 val = I915_READ(TRANS_CHICKEN2(pipe));
3914 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
3915 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
3916 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3917 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
3918 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
3919 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
3920 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3921 I915_WRITE(TRANS_CHICKEN2(pipe), val);
3922 }
3923 /* WADP0ClockGatingDisable */
3924 for_each_pipe(pipe) {
3925 I915_WRITE(TRANS_CHICKEN1(pipe),
3926 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
3927 }
3928 }
3929
3930 static void gen6_check_mch_setup(struct drm_device *dev)
3931 {
3932 struct drm_i915_private *dev_priv = dev->dev_private;
3933 uint32_t tmp;
3934
3935 tmp = I915_READ(MCH_SSKPD);
3936 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) {
3937 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp);
3938 DRM_INFO("This can cause pipe underruns and display issues.\n");
3939 DRM_INFO("Please upgrade your BIOS to fix this.\n");
3940 }
3941 }
3942
3943 static void gen6_init_clock_gating(struct drm_device *dev)
3944 {
3945 struct drm_i915_private *dev_priv = dev->dev_private;
3946 int pipe;
3947 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
3948
3949 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
3950
3951 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3952 I915_READ(ILK_DISPLAY_CHICKEN2) |
3953 ILK_ELPIN_409_SELECT);
3954
3955 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
3956 I915_WRITE(_3D_CHICKEN,
3957 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
3958
3959 /* WaSetupGtModeTdRowDispatch:snb */
3960 if (IS_SNB_GT1(dev))
3961 I915_WRITE(GEN6_GT_MODE,
3962 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
3963
3964 I915_WRITE(WM3_LP_ILK, 0);
3965 I915_WRITE(WM2_LP_ILK, 0);
3966 I915_WRITE(WM1_LP_ILK, 0);
3967
3968 I915_WRITE(CACHE_MODE_0,
3969 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
3970
3971 I915_WRITE(GEN6_UCGCTL1,
3972 I915_READ(GEN6_UCGCTL1) |
3973 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
3974 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
3975
3976 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
3977 * gating disable must be set. Failure to set it results in
3978 * flickering pixels due to Z write ordering failures after
3979 * some amount of runtime in the Mesa "fire" demo, and Unigine
3980 * Sanctuary and Tropics, and apparently anything else with
3981 * alpha test or pixel discard.
3982 *
3983 * According to the spec, bit 11 (RCCUNIT) must also be set,
3984 * but we didn't debug actual testcases to find it out.
3985 *
3986 * Also apply WaDisableVDSUnitClockGating:snb and
3987 * WaDisableRCPBUnitClockGating:snb.
3988 */
3989 I915_WRITE(GEN6_UCGCTL2,
3990 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
3991 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
3992 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
3993
3994 /* Bspec says we need to always set all mask bits. */
3995 I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) |
3996 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL);
3997
3998 /*
3999 * According to the spec the following bits should be
4000 * set in order to enable memory self-refresh and fbc:
4001 * The bit21 and bit22 of 0x42000
4002 * The bit21 and bit22 of 0x42004
4003 * The bit5 and bit7 of 0x42020
4004 * The bit14 of 0x70180
4005 * The bit14 of 0x71180
4006 */
4007 I915_WRITE(ILK_DISPLAY_CHICKEN1,
4008 I915_READ(ILK_DISPLAY_CHICKEN1) |
4009 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
4010 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4011 I915_READ(ILK_DISPLAY_CHICKEN2) |
4012 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
4013 I915_WRITE(ILK_DSPCLK_GATE_D,
4014 I915_READ(ILK_DSPCLK_GATE_D) |
4015 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
4016 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
4017
4018 /* WaMbcDriverBootEnable:snb */
4019 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4020 GEN6_MBCTL_ENABLE_BOOT_FETCH);
4021
4022 for_each_pipe(pipe) {
4023 I915_WRITE(DSPCNTR(pipe),
4024 I915_READ(DSPCNTR(pipe)) |
4025 DISPPLANE_TRICKLE_FEED_DISABLE);
4026 intel_flush_display_plane(dev_priv, pipe);
4027 }
4028
4029 /* The default value should be 0x200 according to docs, but the two
4030 * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
4031 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff));
4032 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
4033
4034 cpt_init_clock_gating(dev);
4035
4036 gen6_check_mch_setup(dev);
4037 }
4038
4039 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
4040 {
4041 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
4042
4043 reg &= ~GEN7_FF_SCHED_MASK;
4044 reg |= GEN7_FF_TS_SCHED_HW;
4045 reg |= GEN7_FF_VS_SCHED_HW;
4046 reg |= GEN7_FF_DS_SCHED_HW;
4047
4048 if (IS_HASWELL(dev_priv->dev))
4049 reg &= ~GEN7_FF_VS_REF_CNT_FFME;
4050
4051 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
4052 }
4053
4054 static void lpt_init_clock_gating(struct drm_device *dev)
4055 {
4056 struct drm_i915_private *dev_priv = dev->dev_private;
4057
4058 /*
4059 * TODO: this bit should only be enabled when really needed, then
4060 * disabled when not needed anymore in order to save power.
4061 */
4062 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
4063 I915_WRITE(SOUTH_DSPCLK_GATE_D,
4064 I915_READ(SOUTH_DSPCLK_GATE_D) |
4065 PCH_LP_PARTITION_LEVEL_DISABLE);
4066 }
4067
4068 static void lpt_suspend_hw(struct drm_device *dev)
4069 {
4070 struct drm_i915_private *dev_priv = dev->dev_private;
4071
4072 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
4073 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
4074
4075 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
4076 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
4077 }
4078 }
4079
4080 static void haswell_init_clock_gating(struct drm_device *dev)
4081 {
4082 struct drm_i915_private *dev_priv = dev->dev_private;
4083 int pipe;
4084
4085 I915_WRITE(WM3_LP_ILK, 0);
4086 I915_WRITE(WM2_LP_ILK, 0);
4087 I915_WRITE(WM1_LP_ILK, 0);
4088
4089 /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
4090 * This implements the WaDisableRCZUnitClockGating:hsw workaround.
4091 */
4092 I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
4093
4094 /* Apply the WaDisableRHWOOptimizationForRenderHang:hsw workaround. */
4095 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4096 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4097
4098 /* WaApplyL3ControlAndL3ChickenMode:hsw */
4099 I915_WRITE(GEN7_L3CNTLREG1,
4100 GEN7_WA_FOR_GEN7_L3_CONTROL);
4101 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
4102 GEN7_WA_L3_CHICKEN_MODE);
4103
4104 /* This is required by WaCatErrorRejectionIssue:hsw */
4105 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4106 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4107 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4108
4109 for_each_pipe(pipe) {
4110 I915_WRITE(DSPCNTR(pipe),
4111 I915_READ(DSPCNTR(pipe)) |
4112 DISPPLANE_TRICKLE_FEED_DISABLE);
4113 intel_flush_display_plane(dev_priv, pipe);
4114 }
4115
4116 /* WaVSRefCountFullforceMissDisable:hsw */
4117 gen7_setup_fixed_func_scheduler(dev_priv);
4118
4119 /* WaDisable4x2SubspanOptimization:hsw */
4120 I915_WRITE(CACHE_MODE_1,
4121 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
4122
4123 /* WaMbcDriverBootEnable:hsw */
4124 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4125 GEN6_MBCTL_ENABLE_BOOT_FETCH);
4126
4127 /* WaSwitchSolVfFArbitrationPriority:hsw */
4128 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
4129
4130 /* XXX: This is a workaround for early silicon revisions and should be
4131 * removed later.
4132 */
4133 I915_WRITE(WM_DBG,
4134 I915_READ(WM_DBG) |
4135 WM_DBG_DISALLOW_MULTIPLE_LP |
4136 WM_DBG_DISALLOW_SPRITE |
4137 WM_DBG_DISALLOW_MAXFIFO);
4138
4139 lpt_init_clock_gating(dev);
4140 }
4141
4142 static void ivybridge_init_clock_gating(struct drm_device *dev)
4143 {
4144 struct drm_i915_private *dev_priv = dev->dev_private;
4145 int pipe;
4146 uint32_t snpcr;
4147
4148 I915_WRITE(WM3_LP_ILK, 0);
4149 I915_WRITE(WM2_LP_ILK, 0);
4150 I915_WRITE(WM1_LP_ILK, 0);
4151
4152 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
4153
4154 /* WaDisableEarlyCull:ivb */
4155 I915_WRITE(_3D_CHICKEN3,
4156 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
4157
4158 /* WaDisableBackToBackFlipFix:ivb */
4159 I915_WRITE(IVB_CHICKEN3,
4160 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
4161 CHICKEN3_DGMG_DONE_FIX_DISABLE);
4162
4163 /* WaDisablePSDDualDispatchEnable:ivb */
4164 if (IS_IVB_GT1(dev))
4165 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
4166 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
4167 else
4168 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
4169 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
4170
4171 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
4172 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4173 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4174
4175 /* WaApplyL3ControlAndL3ChickenMode:ivb */
4176 I915_WRITE(GEN7_L3CNTLREG1,
4177 GEN7_WA_FOR_GEN7_L3_CONTROL);
4178 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
4179 GEN7_WA_L3_CHICKEN_MODE);
4180 if (IS_IVB_GT1(dev))
4181 I915_WRITE(GEN7_ROW_CHICKEN2,
4182 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4183 else
4184 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
4185 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4186
4187
4188 /* WaForceL3Serialization:ivb */
4189 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
4190 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
4191
4192 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4193 * gating disable must be set. Failure to set it results in
4194 * flickering pixels due to Z write ordering failures after
4195 * some amount of runtime in the Mesa "fire" demo, and Unigine
4196 * Sanctuary and Tropics, and apparently anything else with
4197 * alpha test or pixel discard.
4198 *
4199 * According to the spec, bit 11 (RCCUNIT) must also be set,
4200 * but we didn't debug actual testcases to find it out.
4201 *
4202 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
4203 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
4204 */
4205 I915_WRITE(GEN6_UCGCTL2,
4206 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
4207 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4208
4209 /* This is required by WaCatErrorRejectionIssue:ivb */
4210 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4211 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4212 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4213
4214 for_each_pipe(pipe) {
4215 I915_WRITE(DSPCNTR(pipe),
4216 I915_READ(DSPCNTR(pipe)) |
4217 DISPPLANE_TRICKLE_FEED_DISABLE);
4218 intel_flush_display_plane(dev_priv, pipe);
4219 }
4220
4221 /* WaMbcDriverBootEnable:ivb */
4222 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4223 GEN6_MBCTL_ENABLE_BOOT_FETCH);
4224
4225 /* WaVSRefCountFullforceMissDisable:ivb */
4226 gen7_setup_fixed_func_scheduler(dev_priv);
4227
4228 /* WaDisable4x2SubspanOptimization:ivb */
4229 I915_WRITE(CACHE_MODE_1,
4230 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
4231
4232 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4233 snpcr &= ~GEN6_MBC_SNPCR_MASK;
4234 snpcr |= GEN6_MBC_SNPCR_MED;
4235 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
4236
4237 if (!HAS_PCH_NOP(dev))
4238 cpt_init_clock_gating(dev);
4239
4240 gen6_check_mch_setup(dev);
4241 }
4242
4243 static void valleyview_init_clock_gating(struct drm_device *dev)
4244 {
4245 struct drm_i915_private *dev_priv = dev->dev_private;
4246 int pipe;
4247
4248 I915_WRITE(WM3_LP_ILK, 0);
4249 I915_WRITE(WM2_LP_ILK, 0);
4250 I915_WRITE(WM1_LP_ILK, 0);
4251
4252 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
4253
4254 /* WaDisableEarlyCull:vlv */
4255 I915_WRITE(_3D_CHICKEN3,
4256 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
4257
4258 /* WaDisableBackToBackFlipFix:vlv */
4259 I915_WRITE(IVB_CHICKEN3,
4260 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
4261 CHICKEN3_DGMG_DONE_FIX_DISABLE);
4262
4263 /* WaDisablePSDDualDispatchEnable:vlv */
4264 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
4265 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
4266 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
4267
4268 /* Apply the WaDisableRHWOOptimizationForRenderHang:vlv workaround. */
4269 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4270 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4271
4272 /* WaApplyL3ControlAndL3ChickenMode:vlv */
4273 I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
4274 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
4275
4276 /* WaForceL3Serialization:vlv */
4277 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
4278 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
4279
4280 /* WaDisableDopClockGating:vlv */
4281 I915_WRITE(GEN7_ROW_CHICKEN2,
4282 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4283
4284 /* WaForceL3Serialization:vlv */
4285 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
4286 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
4287
4288 /* This is required by WaCatErrorRejectionIssue:vlv */
4289 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4290 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4291 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4292
4293 /* WaMbcDriverBootEnable:vlv */
4294 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4295 GEN6_MBCTL_ENABLE_BOOT_FETCH);
4296
4297
4298 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4299 * gating disable must be set. Failure to set it results in
4300 * flickering pixels due to Z write ordering failures after
4301 * some amount of runtime in the Mesa "fire" demo, and Unigine
4302 * Sanctuary and Tropics, and apparently anything else with
4303 * alpha test or pixel discard.
4304 *
4305 * According to the spec, bit 11 (RCCUNIT) must also be set,
4306 * but we didn't debug actual testcases to find it out.
4307 *
4308 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
4309 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
4310 *
4311 * Also apply WaDisableVDSUnitClockGating:vlv and
4312 * WaDisableRCPBUnitClockGating:vlv.
4313 */
4314 I915_WRITE(GEN6_UCGCTL2,
4315 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
4316 GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
4317 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
4318 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
4319 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4320
4321 I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
4322
4323 for_each_pipe(pipe) {
4324 I915_WRITE(DSPCNTR(pipe),
4325 I915_READ(DSPCNTR(pipe)) |
4326 DISPPLANE_TRICKLE_FEED_DISABLE);
4327 intel_flush_display_plane(dev_priv, pipe);
4328 }
4329
4330 I915_WRITE(CACHE_MODE_1,
4331 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
4332
4333 /*
4334 * WaDisableVLVClockGating_VBIIssue:vlv
4335 * Disable clock gating on th GCFG unit to prevent a delay
4336 * in the reporting of vblank events.
4337 */
4338 I915_WRITE(VLV_GUNIT_CLOCK_GATE, 0xffffffff);
4339
4340 /* Conservative clock gating settings for now */
4341 I915_WRITE(0x9400, 0xffffffff);
4342 I915_WRITE(0x9404, 0xffffffff);
4343 I915_WRITE(0x9408, 0xffffffff);
4344 I915_WRITE(0x940c, 0xffffffff);
4345 I915_WRITE(0x9410, 0xffffffff);
4346 I915_WRITE(0x9414, 0xffffffff);
4347 I915_WRITE(0x9418, 0xffffffff);
4348 }
4349
4350 static void g4x_init_clock_gating(struct drm_device *dev)
4351 {
4352 struct drm_i915_private *dev_priv = dev->dev_private;
4353 uint32_t dspclk_gate;
4354
4355 I915_WRITE(RENCLK_GATE_D1, 0);
4356 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
4357 GS_UNIT_CLOCK_GATE_DISABLE |
4358 CL_UNIT_CLOCK_GATE_DISABLE);
4359 I915_WRITE(RAMCLK_GATE_D, 0);
4360 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
4361 OVRUNIT_CLOCK_GATE_DISABLE |
4362 OVCUNIT_CLOCK_GATE_DISABLE;
4363 if (IS_GM45(dev))
4364 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
4365 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4366
4367 /* WaDisableRenderCachePipelinedFlush */
4368 I915_WRITE(CACHE_MODE_0,
4369 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
4370 }
4371
4372 static void crestline_init_clock_gating(struct drm_device *dev)
4373 {
4374 struct drm_i915_private *dev_priv = dev->dev_private;
4375
4376 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
4377 I915_WRITE(RENCLK_GATE_D2, 0);
4378 I915_WRITE(DSPCLK_GATE_D, 0);
4379 I915_WRITE(RAMCLK_GATE_D, 0);
4380 I915_WRITE16(DEUC, 0);
4381 }
4382
4383 static void broadwater_init_clock_gating(struct drm_device *dev)
4384 {
4385 struct drm_i915_private *dev_priv = dev->dev_private;
4386
4387 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
4388 I965_RCC_CLOCK_GATE_DISABLE |
4389 I965_RCPB_CLOCK_GATE_DISABLE |
4390 I965_ISC_CLOCK_GATE_DISABLE |
4391 I965_FBC_CLOCK_GATE_DISABLE);
4392 I915_WRITE(RENCLK_GATE_D2, 0);
4393 }
4394
4395 static void gen3_init_clock_gating(struct drm_device *dev)
4396 {
4397 struct drm_i915_private *dev_priv = dev->dev_private;
4398 u32 dstate = I915_READ(D_STATE);
4399
4400 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
4401 DSTATE_DOT_CLOCK_GATING;
4402 I915_WRITE(D_STATE, dstate);
4403
4404 if (IS_PINEVIEW(dev))
4405 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
4406
4407 /* IIR "flip pending" means done if this bit is set */
4408 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
4409 }
4410
4411 static void i85x_init_clock_gating(struct drm_device *dev)
4412 {
4413 struct drm_i915_private *dev_priv = dev->dev_private;
4414
4415 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
4416 }
4417
4418 static void i830_init_clock_gating(struct drm_device *dev)
4419 {
4420 struct drm_i915_private *dev_priv = dev->dev_private;
4421
4422 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
4423 }
4424
4425 void intel_init_clock_gating(struct drm_device *dev)
4426 {
4427 struct drm_i915_private *dev_priv = dev->dev_private;
4428
4429 dev_priv->display.init_clock_gating(dev);
4430 }
4431
4432 void intel_suspend_hw(struct drm_device *dev)
4433 {
4434 if (HAS_PCH_LPT(dev))
4435 lpt_suspend_hw(dev);
4436 }
4437
4438 /**
4439 * We should only use the power well if we explicitly asked the hardware to
4440 * enable it, so check if it's enabled and also check if we've requested it to
4441 * be enabled.
4442 */
4443 bool intel_display_power_enabled(struct drm_device *dev,
4444 enum intel_display_power_domain domain)
4445 {
4446 struct drm_i915_private *dev_priv = dev->dev_private;
4447
4448 if (!HAS_POWER_WELL(dev))
4449 return true;
4450
4451 switch (domain) {
4452 case POWER_DOMAIN_PIPE_A:
4453 case POWER_DOMAIN_TRANSCODER_EDP:
4454 return true;
4455 case POWER_DOMAIN_PIPE_B:
4456 case POWER_DOMAIN_PIPE_C:
4457 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
4458 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
4459 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
4460 case POWER_DOMAIN_TRANSCODER_A:
4461 case POWER_DOMAIN_TRANSCODER_B:
4462 case POWER_DOMAIN_TRANSCODER_C:
4463 return I915_READ(HSW_PWR_WELL_DRIVER) ==
4464 (HSW_PWR_WELL_ENABLE | HSW_PWR_WELL_STATE);
4465 default:
4466 BUG();
4467 }
4468 }
4469
4470 void intel_set_power_well(struct drm_device *dev, bool enable)
4471 {
4472 struct drm_i915_private *dev_priv = dev->dev_private;
4473 bool is_enabled, enable_requested;
4474 uint32_t tmp;
4475
4476 if (!HAS_POWER_WELL(dev))
4477 return;
4478
4479 if (!i915_disable_power_well && !enable)
4480 return;
4481
4482 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
4483 is_enabled = tmp & HSW_PWR_WELL_STATE;
4484 enable_requested = tmp & HSW_PWR_WELL_ENABLE;
4485
4486 if (enable) {
4487 if (!enable_requested)
4488 I915_WRITE(HSW_PWR_WELL_DRIVER, HSW_PWR_WELL_ENABLE);
4489
4490 if (!is_enabled) {
4491 DRM_DEBUG_KMS("Enabling power well\n");
4492 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
4493 HSW_PWR_WELL_STATE), 20))
4494 DRM_ERROR("Timeout enabling power well\n");
4495 }
4496 } else {
4497 if (enable_requested) {
4498 I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
4499 DRM_DEBUG_KMS("Requesting to disable the power well\n");
4500 }
4501 }
4502 }
4503
4504 /*
4505 * Starting with Haswell, we have a "Power Down Well" that can be turned off
4506 * when not needed anymore. We have 4 registers that can request the power well
4507 * to be enabled, and it will only be disabled if none of the registers is
4508 * requesting it to be enabled.
4509 */
4510 void intel_init_power_well(struct drm_device *dev)
4511 {
4512 struct drm_i915_private *dev_priv = dev->dev_private;
4513
4514 if (!HAS_POWER_WELL(dev))
4515 return;
4516
4517 /* For now, we need the power well to be always enabled. */
4518 intel_set_power_well(dev, true);
4519
4520 /* We're taking over the BIOS, so clear any requests made by it since
4521 * the driver is in charge now. */
4522 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE)
4523 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
4524 }
4525
4526 /* Set up chip specific power management-related functions */
4527 void intel_init_pm(struct drm_device *dev)
4528 {
4529 struct drm_i915_private *dev_priv = dev->dev_private;
4530
4531 if (I915_HAS_FBC(dev)) {
4532 if (HAS_PCH_SPLIT(dev)) {
4533 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
4534 if (IS_IVYBRIDGE(dev))
4535 dev_priv->display.enable_fbc =
4536 gen7_enable_fbc;
4537 else
4538 dev_priv->display.enable_fbc =
4539 ironlake_enable_fbc;
4540 dev_priv->display.disable_fbc = ironlake_disable_fbc;
4541 } else if (IS_GM45(dev)) {
4542 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
4543 dev_priv->display.enable_fbc = g4x_enable_fbc;
4544 dev_priv->display.disable_fbc = g4x_disable_fbc;
4545 } else if (IS_CRESTLINE(dev)) {
4546 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
4547 dev_priv->display.enable_fbc = i8xx_enable_fbc;
4548 dev_priv->display.disable_fbc = i8xx_disable_fbc;
4549 }
4550 /* 855GM needs testing */
4551 }
4552
4553 /* For cxsr */
4554 if (IS_PINEVIEW(dev))
4555 i915_pineview_get_mem_freq(dev);
4556 else if (IS_GEN5(dev))
4557 i915_ironlake_get_mem_freq(dev);
4558
4559 /* For FIFO watermark updates */
4560 if (HAS_PCH_SPLIT(dev)) {
4561 if (IS_GEN5(dev)) {
4562 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
4563 dev_priv->display.update_wm = ironlake_update_wm;
4564 else {
4565 DRM_DEBUG_KMS("Failed to get proper latency. "
4566 "Disable CxSR\n");
4567 dev_priv->display.update_wm = NULL;
4568 }
4569 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
4570 } else if (IS_GEN6(dev)) {
4571 if (SNB_READ_WM0_LATENCY()) {
4572 dev_priv->display.update_wm = sandybridge_update_wm;
4573 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
4574 } else {
4575 DRM_DEBUG_KMS("Failed to read display plane latency. "
4576 "Disable CxSR\n");
4577 dev_priv->display.update_wm = NULL;
4578 }
4579 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
4580 } else if (IS_IVYBRIDGE(dev)) {
4581 if (SNB_READ_WM0_LATENCY()) {
4582 dev_priv->display.update_wm = ivybridge_update_wm;
4583 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
4584 } else {
4585 DRM_DEBUG_KMS("Failed to read display plane latency. "
4586 "Disable CxSR\n");
4587 dev_priv->display.update_wm = NULL;
4588 }
4589 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
4590 } else if (IS_HASWELL(dev)) {
4591 if (SNB_READ_WM0_LATENCY()) {
4592 dev_priv->display.update_wm = sandybridge_update_wm;
4593 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
4594 dev_priv->display.update_linetime_wm = haswell_update_linetime_wm;
4595 } else {
4596 DRM_DEBUG_KMS("Failed to read display plane latency. "
4597 "Disable CxSR\n");
4598 dev_priv->display.update_wm = NULL;
4599 }
4600 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
4601 } else
4602 dev_priv->display.update_wm = NULL;
4603 } else if (IS_VALLEYVIEW(dev)) {
4604 dev_priv->display.update_wm = valleyview_update_wm;
4605 dev_priv->display.init_clock_gating =
4606 valleyview_init_clock_gating;
4607 } else if (IS_PINEVIEW(dev)) {
4608 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
4609 dev_priv->is_ddr3,
4610 dev_priv->fsb_freq,
4611 dev_priv->mem_freq)) {
4612 DRM_INFO("failed to find known CxSR latency "
4613 "(found ddr%s fsb freq %d, mem freq %d), "
4614 "disabling CxSR\n",
4615 (dev_priv->is_ddr3 == 1) ? "3" : "2",
4616 dev_priv->fsb_freq, dev_priv->mem_freq);
4617 /* Disable CxSR and never update its watermark again */
4618 pineview_disable_cxsr(dev);
4619 dev_priv->display.update_wm = NULL;
4620 } else
4621 dev_priv->display.update_wm = pineview_update_wm;
4622 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
4623 } else if (IS_G4X(dev)) {
4624 dev_priv->display.update_wm = g4x_update_wm;
4625 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
4626 } else if (IS_GEN4(dev)) {
4627 dev_priv->display.update_wm = i965_update_wm;
4628 if (IS_CRESTLINE(dev))
4629 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
4630 else if (IS_BROADWATER(dev))
4631 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
4632 } else if (IS_GEN3(dev)) {
4633 dev_priv->display.update_wm = i9xx_update_wm;
4634 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
4635 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
4636 } else if (IS_I865G(dev)) {
4637 dev_priv->display.update_wm = i830_update_wm;
4638 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
4639 dev_priv->display.get_fifo_size = i830_get_fifo_size;
4640 } else if (IS_I85X(dev)) {
4641 dev_priv->display.update_wm = i9xx_update_wm;
4642 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
4643 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
4644 } else {
4645 dev_priv->display.update_wm = i830_update_wm;
4646 dev_priv->display.init_clock_gating = i830_init_clock_gating;
4647 if (IS_845G(dev))
4648 dev_priv->display.get_fifo_size = i845_get_fifo_size;
4649 else
4650 dev_priv->display.get_fifo_size = i830_get_fifo_size;
4651 }
4652 }
4653
4654 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
4655 {
4656 u32 gt_thread_status_mask;
4657
4658 if (IS_HASWELL(dev_priv->dev))
4659 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK_HSW;
4660 else
4661 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK;
4662
4663 /* w/a for a sporadic read returning 0 by waiting for the GT
4664 * thread to wake up.
4665 */
4666 if (wait_for_atomic_us((I915_READ_NOTRACE(GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_mask) == 0, 500))
4667 DRM_ERROR("GT thread status wait timed out\n");
4668 }
4669
4670 static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv)
4671 {
4672 I915_WRITE_NOTRACE(FORCEWAKE, 0);
4673 POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
4674 }
4675
4676 static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
4677 {
4678 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0,
4679 FORCEWAKE_ACK_TIMEOUT_MS))
4680 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
4681
4682 I915_WRITE_NOTRACE(FORCEWAKE, 1);
4683 POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
4684
4685 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK) & 1),
4686 FORCEWAKE_ACK_TIMEOUT_MS))
4687 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
4688
4689 /* WaRsForcewakeWaitTC0:snb */
4690 __gen6_gt_wait_for_thread_c0(dev_priv);
4691 }
4692
4693 static void __gen6_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv)
4694 {
4695 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff));
4696 /* something from same cacheline, but !FORCEWAKE_MT */
4697 POSTING_READ(ECOBUS);
4698 }
4699
4700 static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
4701 {
4702 u32 forcewake_ack;
4703
4704 if (IS_HASWELL(dev_priv->dev))
4705 forcewake_ack = FORCEWAKE_ACK_HSW;
4706 else
4707 forcewake_ack = FORCEWAKE_MT_ACK;
4708
4709 if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & FORCEWAKE_KERNEL) == 0,
4710 FORCEWAKE_ACK_TIMEOUT_MS))
4711 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
4712
4713 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
4714 /* something from same cacheline, but !FORCEWAKE_MT */
4715 POSTING_READ(ECOBUS);
4716
4717 if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & FORCEWAKE_KERNEL),
4718 FORCEWAKE_ACK_TIMEOUT_MS))
4719 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
4720
4721 /* WaRsForcewakeWaitTC0:ivb,hsw */
4722 __gen6_gt_wait_for_thread_c0(dev_priv);
4723 }
4724
4725 /*
4726 * Generally this is called implicitly by the register read function. However,
4727 * if some sequence requires the GT to not power down then this function should
4728 * be called at the beginning of the sequence followed by a call to
4729 * gen6_gt_force_wake_put() at the end of the sequence.
4730 */
4731 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
4732 {
4733 unsigned long irqflags;
4734
4735 spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
4736 if (dev_priv->forcewake_count++ == 0)
4737 dev_priv->gt.force_wake_get(dev_priv);
4738 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
4739 }
4740
4741 void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
4742 {
4743 u32 gtfifodbg;
4744 gtfifodbg = I915_READ_NOTRACE(GTFIFODBG);
4745 if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK,
4746 "MMIO read or write has been dropped %x\n", gtfifodbg))
4747 I915_WRITE_NOTRACE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK);
4748 }
4749
4750 static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
4751 {
4752 I915_WRITE_NOTRACE(FORCEWAKE, 0);
4753 /* something from same cacheline, but !FORCEWAKE */
4754 POSTING_READ(ECOBUS);
4755 gen6_gt_check_fifodbg(dev_priv);
4756 }
4757
4758 static void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
4759 {
4760 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
4761 /* something from same cacheline, but !FORCEWAKE_MT */
4762 POSTING_READ(ECOBUS);
4763 gen6_gt_check_fifodbg(dev_priv);
4764 }
4765
4766 /*
4767 * see gen6_gt_force_wake_get()
4768 */
4769 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
4770 {
4771 unsigned long irqflags;
4772
4773 spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
4774 if (--dev_priv->forcewake_count == 0)
4775 dev_priv->gt.force_wake_put(dev_priv);
4776 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
4777 }
4778
4779 int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
4780 {
4781 int ret = 0;
4782
4783 if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
4784 int loop = 500;
4785 u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
4786 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
4787 udelay(10);
4788 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
4789 }
4790 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
4791 ++ret;
4792 dev_priv->gt_fifo_count = fifo;
4793 }
4794 dev_priv->gt_fifo_count--;
4795
4796 return ret;
4797 }
4798
4799 static void vlv_force_wake_reset(struct drm_i915_private *dev_priv)
4800 {
4801 I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(0xffff));
4802 /* something from same cacheline, but !FORCEWAKE_VLV */
4803 POSTING_READ(FORCEWAKE_ACK_VLV);
4804 }
4805
4806 static void vlv_force_wake_get(struct drm_i915_private *dev_priv)
4807 {
4808 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & FORCEWAKE_KERNEL) == 0,
4809 FORCEWAKE_ACK_TIMEOUT_MS))
4810 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
4811
4812 I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
4813 I915_WRITE_NOTRACE(FORCEWAKE_MEDIA_VLV,
4814 _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
4815
4816 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & FORCEWAKE_KERNEL),
4817 FORCEWAKE_ACK_TIMEOUT_MS))
4818 DRM_ERROR("Timed out waiting for GT to ack forcewake request.\n");
4819
4820 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_MEDIA_VLV) &
4821 FORCEWAKE_KERNEL),
4822 FORCEWAKE_ACK_TIMEOUT_MS))
4823 DRM_ERROR("Timed out waiting for media to ack forcewake request.\n");
4824
4825 /* WaRsForcewakeWaitTC0:vlv */
4826 __gen6_gt_wait_for_thread_c0(dev_priv);
4827 }
4828
4829 static void vlv_force_wake_put(struct drm_i915_private *dev_priv)
4830 {
4831 I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
4832 I915_WRITE_NOTRACE(FORCEWAKE_MEDIA_VLV,
4833 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
4834 /* The below doubles as a POSTING_READ */
4835 gen6_gt_check_fifodbg(dev_priv);
4836 }
4837
4838 void intel_gt_reset(struct drm_device *dev)
4839 {
4840 struct drm_i915_private *dev_priv = dev->dev_private;
4841
4842 if (IS_VALLEYVIEW(dev)) {
4843 vlv_force_wake_reset(dev_priv);
4844 } else if (INTEL_INFO(dev)->gen >= 6) {
4845 __gen6_gt_force_wake_reset(dev_priv);
4846 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4847 __gen6_gt_force_wake_mt_reset(dev_priv);
4848 }
4849 }
4850
4851 void intel_gt_init(struct drm_device *dev)
4852 {
4853 struct drm_i915_private *dev_priv = dev->dev_private;
4854
4855 spin_lock_init(&dev_priv->gt_lock);
4856
4857 intel_gt_reset(dev);
4858
4859 if (IS_VALLEYVIEW(dev)) {
4860 dev_priv->gt.force_wake_get = vlv_force_wake_get;
4861 dev_priv->gt.force_wake_put = vlv_force_wake_put;
4862 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
4863 dev_priv->gt.force_wake_get = __gen6_gt_force_wake_mt_get;
4864 dev_priv->gt.force_wake_put = __gen6_gt_force_wake_mt_put;
4865 } else if (IS_GEN6(dev)) {
4866 dev_priv->gt.force_wake_get = __gen6_gt_force_wake_get;
4867 dev_priv->gt.force_wake_put = __gen6_gt_force_wake_put;
4868 }
4869 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
4870 intel_gen6_powersave_work);
4871 }
4872
4873 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
4874 {
4875 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4876
4877 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
4878 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
4879 return -EAGAIN;
4880 }
4881
4882 I915_WRITE(GEN6_PCODE_DATA, *val);
4883 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
4884
4885 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
4886 500)) {
4887 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
4888 return -ETIMEDOUT;
4889 }
4890
4891 *val = I915_READ(GEN6_PCODE_DATA);
4892 I915_WRITE(GEN6_PCODE_DATA, 0);
4893
4894 return 0;
4895 }
4896
4897 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
4898 {
4899 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4900
4901 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
4902 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
4903 return -EAGAIN;
4904 }
4905
4906 I915_WRITE(GEN6_PCODE_DATA, val);
4907 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
4908
4909 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
4910 500)) {
4911 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
4912 return -ETIMEDOUT;
4913 }
4914
4915 I915_WRITE(GEN6_PCODE_DATA, 0);
4916
4917 return 0;
4918 }
4919
4920 static int vlv_punit_rw(struct drm_i915_private *dev_priv, u32 port, u8 opcode,
4921 u8 addr, u32 *val)
4922 {
4923 u32 cmd, devfn, be, bar;
4924
4925 bar = 0;
4926 be = 0xf;
4927 devfn = PCI_DEVFN(2, 0);
4928
4929 cmd = (devfn << IOSF_DEVFN_SHIFT) | (opcode << IOSF_OPCODE_SHIFT) |
4930 (port << IOSF_PORT_SHIFT) | (be << IOSF_BYTE_ENABLES_SHIFT) |
4931 (bar << IOSF_BAR_SHIFT);
4932
4933 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4934
4935 if (I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) {
4936 DRM_DEBUG_DRIVER("warning: pcode (%s) mailbox access failed\n",
4937 opcode == PUNIT_OPCODE_REG_READ ?
4938 "read" : "write");
4939 return -EAGAIN;
4940 }
4941
4942 I915_WRITE(VLV_IOSF_ADDR, addr);
4943 if (opcode == PUNIT_OPCODE_REG_WRITE)
4944 I915_WRITE(VLV_IOSF_DATA, *val);
4945 I915_WRITE(VLV_IOSF_DOORBELL_REQ, cmd);
4946
4947 if (wait_for((I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) == 0,
4948 5)) {
4949 DRM_ERROR("timeout waiting for pcode %s (%d) to finish\n",
4950 opcode == PUNIT_OPCODE_REG_READ ? "read" : "write",
4951 addr);
4952 return -ETIMEDOUT;
4953 }
4954
4955 if (opcode == PUNIT_OPCODE_REG_READ)
4956 *val = I915_READ(VLV_IOSF_DATA);
4957 I915_WRITE(VLV_IOSF_DATA, 0);
4958
4959 return 0;
4960 }
4961
4962 int valleyview_punit_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val)
4963 {
4964 return vlv_punit_rw(dev_priv, IOSF_PORT_PUNIT, PUNIT_OPCODE_REG_READ,
4965 addr, val);
4966 }
4967
4968 int valleyview_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val)
4969 {
4970 return vlv_punit_rw(dev_priv, IOSF_PORT_PUNIT, PUNIT_OPCODE_REG_WRITE,
4971 addr, &val);
4972 }
4973
4974 int valleyview_nc_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val)
4975 {
4976 return vlv_punit_rw(dev_priv, IOSF_PORT_NC, PUNIT_OPCODE_REG_READ,
4977 addr, val);
4978 }
4979
4980 int vlv_gpu_freq(int ddr_freq, int val)
4981 {
4982 int mult, base;
4983
4984 switch (ddr_freq) {
4985 case 800:
4986 mult = 20;
4987 base = 120;
4988 break;
4989 case 1066:
4990 mult = 22;
4991 base = 133;
4992 break;
4993 case 1333:
4994 mult = 21;
4995 base = 125;
4996 break;
4997 default:
4998 return -1;
4999 }
5000
5001 return ((val - 0xbd) * mult) + base;
5002 }
5003
5004 int vlv_freq_opcode(int ddr_freq, int val)
5005 {
5006 int mult, base;
5007
5008 switch (ddr_freq) {
5009 case 800:
5010 mult = 20;
5011 base = 120;
5012 break;
5013 case 1066:
5014 mult = 22;
5015 base = 133;
5016 break;
5017 case 1333:
5018 mult = 21;
5019 base = 125;
5020 break;
5021 default:
5022 return -1;
5023 }
5024
5025 val /= mult;
5026 val -= base / mult;
5027 val += 0xbd;
5028
5029 if (val > 0xea)
5030 val = 0xea;
5031
5032 return val;
5033 }
5034
Linux kernel - Deliverables
This page took 0.128235 seconds and 4 git commands to generate.