2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
28 #include <linux/cpufreq.h>
30 #include "intel_drv.h"
31 #include "../../../platform/x86/intel_ips.h"
32 #include <linux/module.h>
34 #define FORCEWAKE_ACK_TIMEOUT_MS 2
36 /* FBC, or Frame Buffer Compression, is a technique employed to compress the
37 * framebuffer contents in-memory, aiming at reducing the required bandwidth
38 * during in-memory transfers and, therefore, reduce the power packet.
40 * The benefits of FBC are mostly visible with solid backgrounds and
41 * variation-less patterns.
43 * FBC-related functionality can be enabled by the means of the
44 * i915.i915_enable_fbc parameter
47 static void i8xx_disable_fbc(struct drm_device
*dev
)
49 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
52 /* Disable compression */
53 fbc_ctl
= I915_READ(FBC_CONTROL
);
54 if ((fbc_ctl
& FBC_CTL_EN
) == 0)
57 fbc_ctl
&= ~FBC_CTL_EN
;
58 I915_WRITE(FBC_CONTROL
, fbc_ctl
);
60 /* Wait for compressing bit to clear */
61 if (wait_for((I915_READ(FBC_STATUS
) & FBC_STAT_COMPRESSING
) == 0, 10)) {
62 DRM_DEBUG_KMS("FBC idle timed out\n");
66 DRM_DEBUG_KMS("disabled FBC\n");
69 static void i8xx_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
71 struct drm_device
*dev
= crtc
->dev
;
72 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
73 struct drm_framebuffer
*fb
= crtc
->fb
;
74 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
75 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
76 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
79 u32 fbc_ctl
, fbc_ctl2
;
81 cfb_pitch
= dev_priv
->cfb_size
/ FBC_LL_SIZE
;
82 if (fb
->pitches
[0] < cfb_pitch
)
83 cfb_pitch
= fb
->pitches
[0];
85 /* FBC_CTL wants 64B units */
86 cfb_pitch
= (cfb_pitch
/ 64) - 1;
87 plane
= intel_crtc
->plane
== 0 ? FBC_CTL_PLANEA
: FBC_CTL_PLANEB
;
90 for (i
= 0; i
< (FBC_LL_SIZE
/ 32) + 1; i
++)
91 I915_WRITE(FBC_TAG
+ (i
* 4), 0);
94 fbc_ctl2
= FBC_CTL_FENCE_DBL
| FBC_CTL_IDLE_IMM
| FBC_CTL_CPU_FENCE
;
96 I915_WRITE(FBC_CONTROL2
, fbc_ctl2
);
97 I915_WRITE(FBC_FENCE_OFF
, crtc
->y
);
100 fbc_ctl
= FBC_CTL_EN
| FBC_CTL_PERIODIC
;
102 fbc_ctl
|= FBC_CTL_C3_IDLE
; /* 945 needs special SR handling */
103 fbc_ctl
|= (cfb_pitch
& 0xff) << FBC_CTL_STRIDE_SHIFT
;
104 fbc_ctl
|= (interval
& 0x2fff) << FBC_CTL_INTERVAL_SHIFT
;
105 fbc_ctl
|= obj
->fence_reg
;
106 I915_WRITE(FBC_CONTROL
, fbc_ctl
);
108 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
109 cfb_pitch
, crtc
->y
, intel_crtc
->plane
);
112 static bool i8xx_fbc_enabled(struct drm_device
*dev
)
114 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
116 return I915_READ(FBC_CONTROL
) & FBC_CTL_EN
;
119 static void g4x_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
121 struct drm_device
*dev
= crtc
->dev
;
122 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
123 struct drm_framebuffer
*fb
= crtc
->fb
;
124 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
125 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
126 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
127 int plane
= intel_crtc
->plane
== 0 ? DPFC_CTL_PLANEA
: DPFC_CTL_PLANEB
;
128 unsigned long stall_watermark
= 200;
131 dpfc_ctl
= plane
| DPFC_SR_EN
| DPFC_CTL_LIMIT_1X
;
132 dpfc_ctl
|= DPFC_CTL_FENCE_EN
| obj
->fence_reg
;
133 I915_WRITE(DPFC_CHICKEN
, DPFC_HT_MODIFY
);
135 I915_WRITE(DPFC_RECOMP_CTL
, DPFC_RECOMP_STALL_EN
|
136 (stall_watermark
<< DPFC_RECOMP_STALL_WM_SHIFT
) |
137 (interval
<< DPFC_RECOMP_TIMER_COUNT_SHIFT
));
138 I915_WRITE(DPFC_FENCE_YOFF
, crtc
->y
);
141 I915_WRITE(DPFC_CONTROL
, I915_READ(DPFC_CONTROL
) | DPFC_CTL_EN
);
143 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc
->plane
);
146 static void g4x_disable_fbc(struct drm_device
*dev
)
148 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
151 /* Disable compression */
152 dpfc_ctl
= I915_READ(DPFC_CONTROL
);
153 if (dpfc_ctl
& DPFC_CTL_EN
) {
154 dpfc_ctl
&= ~DPFC_CTL_EN
;
155 I915_WRITE(DPFC_CONTROL
, dpfc_ctl
);
157 DRM_DEBUG_KMS("disabled FBC\n");
161 static bool g4x_fbc_enabled(struct drm_device
*dev
)
163 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
165 return I915_READ(DPFC_CONTROL
) & DPFC_CTL_EN
;
168 static void sandybridge_blit_fbc_update(struct drm_device
*dev
)
170 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
173 /* Make sure blitter notifies FBC of writes */
174 gen6_gt_force_wake_get(dev_priv
);
175 blt_ecoskpd
= I915_READ(GEN6_BLITTER_ECOSKPD
);
176 blt_ecoskpd
|= GEN6_BLITTER_FBC_NOTIFY
<<
177 GEN6_BLITTER_LOCK_SHIFT
;
178 I915_WRITE(GEN6_BLITTER_ECOSKPD
, blt_ecoskpd
);
179 blt_ecoskpd
|= GEN6_BLITTER_FBC_NOTIFY
;
180 I915_WRITE(GEN6_BLITTER_ECOSKPD
, blt_ecoskpd
);
181 blt_ecoskpd
&= ~(GEN6_BLITTER_FBC_NOTIFY
<<
182 GEN6_BLITTER_LOCK_SHIFT
);
183 I915_WRITE(GEN6_BLITTER_ECOSKPD
, blt_ecoskpd
);
184 POSTING_READ(GEN6_BLITTER_ECOSKPD
);
185 gen6_gt_force_wake_put(dev_priv
);
188 static void ironlake_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
190 struct drm_device
*dev
= crtc
->dev
;
191 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
192 struct drm_framebuffer
*fb
= crtc
->fb
;
193 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
194 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
195 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
196 int plane
= intel_crtc
->plane
== 0 ? DPFC_CTL_PLANEA
: DPFC_CTL_PLANEB
;
197 unsigned long stall_watermark
= 200;
200 dpfc_ctl
= I915_READ(ILK_DPFC_CONTROL
);
201 dpfc_ctl
&= DPFC_RESERVED
;
202 dpfc_ctl
|= (plane
| DPFC_CTL_LIMIT_1X
);
203 /* Set persistent mode for front-buffer rendering, ala X. */
204 dpfc_ctl
|= DPFC_CTL_PERSISTENT_MODE
;
205 dpfc_ctl
|= (DPFC_CTL_FENCE_EN
| obj
->fence_reg
);
206 I915_WRITE(ILK_DPFC_CHICKEN
, DPFC_HT_MODIFY
);
208 I915_WRITE(ILK_DPFC_RECOMP_CTL
, DPFC_RECOMP_STALL_EN
|
209 (stall_watermark
<< DPFC_RECOMP_STALL_WM_SHIFT
) |
210 (interval
<< DPFC_RECOMP_TIMER_COUNT_SHIFT
));
211 I915_WRITE(ILK_DPFC_FENCE_YOFF
, crtc
->y
);
212 I915_WRITE(ILK_FBC_RT_BASE
, obj
->gtt_offset
| ILK_FBC_RT_VALID
);
214 I915_WRITE(ILK_DPFC_CONTROL
, dpfc_ctl
| DPFC_CTL_EN
);
217 I915_WRITE(SNB_DPFC_CTL_SA
,
218 SNB_CPU_FENCE_ENABLE
| obj
->fence_reg
);
219 I915_WRITE(DPFC_CPU_FENCE_OFFSET
, crtc
->y
);
220 sandybridge_blit_fbc_update(dev
);
223 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc
->plane
);
226 static void ironlake_disable_fbc(struct drm_device
*dev
)
228 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
231 /* Disable compression */
232 dpfc_ctl
= I915_READ(ILK_DPFC_CONTROL
);
233 if (dpfc_ctl
& DPFC_CTL_EN
) {
234 dpfc_ctl
&= ~DPFC_CTL_EN
;
235 I915_WRITE(ILK_DPFC_CONTROL
, dpfc_ctl
);
237 DRM_DEBUG_KMS("disabled FBC\n");
241 static bool ironlake_fbc_enabled(struct drm_device
*dev
)
243 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
245 return I915_READ(ILK_DPFC_CONTROL
) & DPFC_CTL_EN
;
248 bool intel_fbc_enabled(struct drm_device
*dev
)
250 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
252 if (!dev_priv
->display
.fbc_enabled
)
255 return dev_priv
->display
.fbc_enabled(dev
);
258 static void intel_fbc_work_fn(struct work_struct
*__work
)
260 struct intel_fbc_work
*work
=
261 container_of(to_delayed_work(__work
),
262 struct intel_fbc_work
, work
);
263 struct drm_device
*dev
= work
->crtc
->dev
;
264 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
266 mutex_lock(&dev
->struct_mutex
);
267 if (work
== dev_priv
->fbc_work
) {
268 /* Double check that we haven't switched fb without cancelling
271 if (work
->crtc
->fb
== work
->fb
) {
272 dev_priv
->display
.enable_fbc(work
->crtc
,
275 dev_priv
->cfb_plane
= to_intel_crtc(work
->crtc
)->plane
;
276 dev_priv
->cfb_fb
= work
->crtc
->fb
->base
.id
;
277 dev_priv
->cfb_y
= work
->crtc
->y
;
280 dev_priv
->fbc_work
= NULL
;
282 mutex_unlock(&dev
->struct_mutex
);
287 static void intel_cancel_fbc_work(struct drm_i915_private
*dev_priv
)
289 if (dev_priv
->fbc_work
== NULL
)
292 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
294 /* Synchronisation is provided by struct_mutex and checking of
295 * dev_priv->fbc_work, so we can perform the cancellation
296 * entirely asynchronously.
298 if (cancel_delayed_work(&dev_priv
->fbc_work
->work
))
299 /* tasklet was killed before being run, clean up */
300 kfree(dev_priv
->fbc_work
);
302 /* Mark the work as no longer wanted so that if it does
303 * wake-up (because the work was already running and waiting
304 * for our mutex), it will discover that is no longer
307 dev_priv
->fbc_work
= NULL
;
310 void intel_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
312 struct intel_fbc_work
*work
;
313 struct drm_device
*dev
= crtc
->dev
;
314 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
316 if (!dev_priv
->display
.enable_fbc
)
319 intel_cancel_fbc_work(dev_priv
);
321 work
= kzalloc(sizeof *work
, GFP_KERNEL
);
323 dev_priv
->display
.enable_fbc(crtc
, interval
);
329 work
->interval
= interval
;
330 INIT_DELAYED_WORK(&work
->work
, intel_fbc_work_fn
);
332 dev_priv
->fbc_work
= work
;
334 DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
336 /* Delay the actual enabling to let pageflipping cease and the
337 * display to settle before starting the compression. Note that
338 * this delay also serves a second purpose: it allows for a
339 * vblank to pass after disabling the FBC before we attempt
340 * to modify the control registers.
342 * A more complicated solution would involve tracking vblanks
343 * following the termination of the page-flipping sequence
344 * and indeed performing the enable as a co-routine and not
345 * waiting synchronously upon the vblank.
347 schedule_delayed_work(&work
->work
, msecs_to_jiffies(50));
350 void intel_disable_fbc(struct drm_device
*dev
)
352 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
354 intel_cancel_fbc_work(dev_priv
);
356 if (!dev_priv
->display
.disable_fbc
)
359 dev_priv
->display
.disable_fbc(dev
);
360 dev_priv
->cfb_plane
= -1;
364 * intel_update_fbc - enable/disable FBC as needed
365 * @dev: the drm_device
367 * Set up the framebuffer compression hardware at mode set time. We
368 * enable it if possible:
369 * - plane A only (on pre-965)
370 * - no pixel mulitply/line duplication
371 * - no alpha buffer discard
373 * - framebuffer <= 2048 in width, 1536 in height
375 * We can't assume that any compression will take place (worst case),
376 * so the compressed buffer has to be the same size as the uncompressed
377 * one. It also must reside (along with the line length buffer) in
380 * We need to enable/disable FBC on a global basis.
382 void intel_update_fbc(struct drm_device
*dev
)
384 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
385 struct drm_crtc
*crtc
= NULL
, *tmp_crtc
;
386 struct intel_crtc
*intel_crtc
;
387 struct drm_framebuffer
*fb
;
388 struct intel_framebuffer
*intel_fb
;
389 struct drm_i915_gem_object
*obj
;
395 if (!I915_HAS_FBC(dev
))
399 * If FBC is already on, we just have to verify that we can
400 * keep it that way...
401 * Need to disable if:
402 * - more than one pipe is active
403 * - changing FBC params (stride, fence, mode)
404 * - new fb is too large to fit in compressed buffer
405 * - going to an unsupported config (interlace, pixel multiply, etc.)
407 list_for_each_entry(tmp_crtc
, &dev
->mode_config
.crtc_list
, head
) {
408 if (to_intel_crtc(tmp_crtc
)->active
&&
409 !to_intel_crtc(tmp_crtc
)->primary_disabled
&&
412 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
413 dev_priv
->no_fbc_reason
= FBC_MULTIPLE_PIPES
;
420 if (!crtc
|| crtc
->fb
== NULL
) {
421 DRM_DEBUG_KMS("no output, disabling\n");
422 dev_priv
->no_fbc_reason
= FBC_NO_OUTPUT
;
426 intel_crtc
= to_intel_crtc(crtc
);
428 intel_fb
= to_intel_framebuffer(fb
);
431 enable_fbc
= i915_enable_fbc
;
432 if (enable_fbc
< 0) {
433 DRM_DEBUG_KMS("fbc set to per-chip default\n");
435 if (INTEL_INFO(dev
)->gen
<= 6)
439 DRM_DEBUG_KMS("fbc disabled per module param\n");
440 dev_priv
->no_fbc_reason
= FBC_MODULE_PARAM
;
443 if ((crtc
->mode
.flags
& DRM_MODE_FLAG_INTERLACE
) ||
444 (crtc
->mode
.flags
& DRM_MODE_FLAG_DBLSCAN
)) {
445 DRM_DEBUG_KMS("mode incompatible with compression, "
447 dev_priv
->no_fbc_reason
= FBC_UNSUPPORTED_MODE
;
450 if ((crtc
->mode
.hdisplay
> 2048) ||
451 (crtc
->mode
.vdisplay
> 1536)) {
452 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
453 dev_priv
->no_fbc_reason
= FBC_MODE_TOO_LARGE
;
456 if ((IS_I915GM(dev
) || IS_I945GM(dev
)) && intel_crtc
->plane
!= 0) {
457 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
458 dev_priv
->no_fbc_reason
= FBC_BAD_PLANE
;
462 /* The use of a CPU fence is mandatory in order to detect writes
463 * by the CPU to the scanout and trigger updates to the FBC.
465 if (obj
->tiling_mode
!= I915_TILING_X
||
466 obj
->fence_reg
== I915_FENCE_REG_NONE
) {
467 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
468 dev_priv
->no_fbc_reason
= FBC_NOT_TILED
;
472 /* If the kernel debugger is active, always disable compression */
476 if (i915_gem_stolen_setup_compression(dev
, intel_fb
->obj
->base
.size
)) {
477 DRM_INFO("not enough stolen space for compressed buffer (need %zd bytes), disabling\n", intel_fb
->obj
->base
.size
);
478 DRM_INFO("hint: you may be able to increase stolen memory size in the BIOS to avoid this\n");
479 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
480 dev_priv
->no_fbc_reason
= FBC_STOLEN_TOO_SMALL
;
484 /* If the scanout has not changed, don't modify the FBC settings.
485 * Note that we make the fundamental assumption that the fb->obj
486 * cannot be unpinned (and have its GTT offset and fence revoked)
487 * without first being decoupled from the scanout and FBC disabled.
489 if (dev_priv
->cfb_plane
== intel_crtc
->plane
&&
490 dev_priv
->cfb_fb
== fb
->base
.id
&&
491 dev_priv
->cfb_y
== crtc
->y
)
494 if (intel_fbc_enabled(dev
)) {
495 /* We update FBC along two paths, after changing fb/crtc
496 * configuration (modeswitching) and after page-flipping
497 * finishes. For the latter, we know that not only did
498 * we disable the FBC at the start of the page-flip
499 * sequence, but also more than one vblank has passed.
501 * For the former case of modeswitching, it is possible
502 * to switch between two FBC valid configurations
503 * instantaneously so we do need to disable the FBC
504 * before we can modify its control registers. We also
505 * have to wait for the next vblank for that to take
506 * effect. However, since we delay enabling FBC we can
507 * assume that a vblank has passed since disabling and
508 * that we can safely alter the registers in the deferred
511 * In the scenario that we go from a valid to invalid
512 * and then back to valid FBC configuration we have
513 * no strict enforcement that a vblank occurred since
514 * disabling the FBC. However, along all current pipe
515 * disabling paths we do need to wait for a vblank at
516 * some point. And we wait before enabling FBC anyway.
518 DRM_DEBUG_KMS("disabling active FBC for update\n");
519 intel_disable_fbc(dev
);
522 intel_enable_fbc(crtc
, 500);
526 /* Multiple disables should be harmless */
527 if (intel_fbc_enabled(dev
)) {
528 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
529 intel_disable_fbc(dev
);
531 i915_gem_stolen_cleanup_compression(dev
);
534 static void i915_pineview_get_mem_freq(struct drm_device
*dev
)
536 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
539 tmp
= I915_READ(CLKCFG
);
541 switch (tmp
& CLKCFG_FSB_MASK
) {
543 dev_priv
->fsb_freq
= 533; /* 133*4 */
546 dev_priv
->fsb_freq
= 800; /* 200*4 */
549 dev_priv
->fsb_freq
= 667; /* 167*4 */
552 dev_priv
->fsb_freq
= 400; /* 100*4 */
556 switch (tmp
& CLKCFG_MEM_MASK
) {
558 dev_priv
->mem_freq
= 533;
561 dev_priv
->mem_freq
= 667;
564 dev_priv
->mem_freq
= 800;
568 /* detect pineview DDR3 setting */
569 tmp
= I915_READ(CSHRDDR3CTL
);
570 dev_priv
->is_ddr3
= (tmp
& CSHRDDR3CTL_DDR3
) ? 1 : 0;
573 static void i915_ironlake_get_mem_freq(struct drm_device
*dev
)
575 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
578 ddrpll
= I915_READ16(DDRMPLL1
);
579 csipll
= I915_READ16(CSIPLL0
);
581 switch (ddrpll
& 0xff) {
583 dev_priv
->mem_freq
= 800;
586 dev_priv
->mem_freq
= 1066;
589 dev_priv
->mem_freq
= 1333;
592 dev_priv
->mem_freq
= 1600;
595 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
597 dev_priv
->mem_freq
= 0;
601 dev_priv
->ips
.r_t
= dev_priv
->mem_freq
;
603 switch (csipll
& 0x3ff) {
605 dev_priv
->fsb_freq
= 3200;
608 dev_priv
->fsb_freq
= 3733;
611 dev_priv
->fsb_freq
= 4266;
614 dev_priv
->fsb_freq
= 4800;
617 dev_priv
->fsb_freq
= 5333;
620 dev_priv
->fsb_freq
= 5866;
623 dev_priv
->fsb_freq
= 6400;
626 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
628 dev_priv
->fsb_freq
= 0;
632 if (dev_priv
->fsb_freq
== 3200) {
633 dev_priv
->ips
.c_m
= 0;
634 } else if (dev_priv
->fsb_freq
> 3200 && dev_priv
->fsb_freq
<= 4800) {
635 dev_priv
->ips
.c_m
= 1;
637 dev_priv
->ips
.c_m
= 2;
641 static const struct cxsr_latency cxsr_latency_table
[] = {
642 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
643 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
644 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
645 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
646 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
648 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
649 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
650 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
651 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
652 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
654 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
655 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
656 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
657 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
658 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
660 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
661 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
662 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
663 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
664 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
666 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
667 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
668 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
669 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
670 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
672 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
673 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
674 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
675 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
676 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
679 static const struct cxsr_latency
*intel_get_cxsr_latency(int is_desktop
,
684 const struct cxsr_latency
*latency
;
687 if (fsb
== 0 || mem
== 0)
690 for (i
= 0; i
< ARRAY_SIZE(cxsr_latency_table
); i
++) {
691 latency
= &cxsr_latency_table
[i
];
692 if (is_desktop
== latency
->is_desktop
&&
693 is_ddr3
== latency
->is_ddr3
&&
694 fsb
== latency
->fsb_freq
&& mem
== latency
->mem_freq
)
698 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
703 static void pineview_disable_cxsr(struct drm_device
*dev
)
705 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
707 /* deactivate cxsr */
708 I915_WRITE(DSPFW3
, I915_READ(DSPFW3
) & ~PINEVIEW_SELF_REFRESH_EN
);
712 * Latency for FIFO fetches is dependent on several factors:
713 * - memory configuration (speed, channels)
715 * - current MCH state
716 * It can be fairly high in some situations, so here we assume a fairly
717 * pessimal value. It's a tradeoff between extra memory fetches (if we
718 * set this value too high, the FIFO will fetch frequently to stay full)
719 * and power consumption (set it too low to save power and we might see
720 * FIFO underruns and display "flicker").
722 * A value of 5us seems to be a good balance; safe for very low end
723 * platforms but not overly aggressive on lower latency configs.
725 static const int latency_ns
= 5000;
727 static int i9xx_get_fifo_size(struct drm_device
*dev
, int plane
)
729 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
730 uint32_t dsparb
= I915_READ(DSPARB
);
733 size
= dsparb
& 0x7f;
735 size
= ((dsparb
>> DSPARB_CSTART_SHIFT
) & 0x7f) - size
;
737 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
738 plane
? "B" : "A", size
);
743 static int i85x_get_fifo_size(struct drm_device
*dev
, int plane
)
745 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
746 uint32_t dsparb
= I915_READ(DSPARB
);
749 size
= dsparb
& 0x1ff;
751 size
= ((dsparb
>> DSPARB_BEND_SHIFT
) & 0x1ff) - size
;
752 size
>>= 1; /* Convert to cachelines */
754 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
755 plane
? "B" : "A", size
);
760 static int i845_get_fifo_size(struct drm_device
*dev
, int plane
)
762 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
763 uint32_t dsparb
= I915_READ(DSPARB
);
766 size
= dsparb
& 0x7f;
767 size
>>= 2; /* Convert to cachelines */
769 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
776 static int i830_get_fifo_size(struct drm_device
*dev
, int plane
)
778 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
779 uint32_t dsparb
= I915_READ(DSPARB
);
782 size
= dsparb
& 0x7f;
783 size
>>= 1; /* Convert to cachelines */
785 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
786 plane
? "B" : "A", size
);
791 /* Pineview has different values for various configs */
792 static const struct intel_watermark_params pineview_display_wm
= {
793 PINEVIEW_DISPLAY_FIFO
,
797 PINEVIEW_FIFO_LINE_SIZE
799 static const struct intel_watermark_params pineview_display_hplloff_wm
= {
800 PINEVIEW_DISPLAY_FIFO
,
802 PINEVIEW_DFT_HPLLOFF_WM
,
804 PINEVIEW_FIFO_LINE_SIZE
806 static const struct intel_watermark_params pineview_cursor_wm
= {
807 PINEVIEW_CURSOR_FIFO
,
808 PINEVIEW_CURSOR_MAX_WM
,
809 PINEVIEW_CURSOR_DFT_WM
,
810 PINEVIEW_CURSOR_GUARD_WM
,
811 PINEVIEW_FIFO_LINE_SIZE
,
813 static const struct intel_watermark_params pineview_cursor_hplloff_wm
= {
814 PINEVIEW_CURSOR_FIFO
,
815 PINEVIEW_CURSOR_MAX_WM
,
816 PINEVIEW_CURSOR_DFT_WM
,
817 PINEVIEW_CURSOR_GUARD_WM
,
818 PINEVIEW_FIFO_LINE_SIZE
820 static const struct intel_watermark_params g4x_wm_info
= {
827 static const struct intel_watermark_params g4x_cursor_wm_info
= {
834 static const struct intel_watermark_params valleyview_wm_info
= {
835 VALLEYVIEW_FIFO_SIZE
,
841 static const struct intel_watermark_params valleyview_cursor_wm_info
= {
843 VALLEYVIEW_CURSOR_MAX_WM
,
848 static const struct intel_watermark_params i965_cursor_wm_info
= {
855 static const struct intel_watermark_params i945_wm_info
= {
862 static const struct intel_watermark_params i915_wm_info
= {
869 static const struct intel_watermark_params i855_wm_info
= {
876 static const struct intel_watermark_params i830_wm_info
= {
884 static const struct intel_watermark_params ironlake_display_wm_info
= {
891 static const struct intel_watermark_params ironlake_cursor_wm_info
= {
898 static const struct intel_watermark_params ironlake_display_srwm_info
= {
900 ILK_DISPLAY_MAX_SRWM
,
901 ILK_DISPLAY_DFT_SRWM
,
905 static const struct intel_watermark_params ironlake_cursor_srwm_info
= {
913 static const struct intel_watermark_params sandybridge_display_wm_info
= {
920 static const struct intel_watermark_params sandybridge_cursor_wm_info
= {
927 static const struct intel_watermark_params sandybridge_display_srwm_info
= {
929 SNB_DISPLAY_MAX_SRWM
,
930 SNB_DISPLAY_DFT_SRWM
,
934 static const struct intel_watermark_params sandybridge_cursor_srwm_info
= {
944 * intel_calculate_wm - calculate watermark level
945 * @clock_in_khz: pixel clock
946 * @wm: chip FIFO params
947 * @pixel_size: display pixel size
948 * @latency_ns: memory latency for the platform
950 * Calculate the watermark level (the level at which the display plane will
951 * start fetching from memory again). Each chip has a different display
952 * FIFO size and allocation, so the caller needs to figure that out and pass
953 * in the correct intel_watermark_params structure.
955 * As the pixel clock runs, the FIFO will be drained at a rate that depends
956 * on the pixel size. When it reaches the watermark level, it'll start
957 * fetching FIFO line sized based chunks from memory until the FIFO fills
958 * past the watermark point. If the FIFO drains completely, a FIFO underrun
959 * will occur, and a display engine hang could result.
961 static unsigned long intel_calculate_wm(unsigned long clock_in_khz
,
962 const struct intel_watermark_params
*wm
,
965 unsigned long latency_ns
)
967 long entries_required
, wm_size
;
970 * Note: we need to make sure we don't overflow for various clock &
972 * clocks go from a few thousand to several hundred thousand.
973 * latency is usually a few thousand
975 entries_required
= ((clock_in_khz
/ 1000) * pixel_size
* latency_ns
) /
977 entries_required
= DIV_ROUND_UP(entries_required
, wm
->cacheline_size
);
979 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required
);
981 wm_size
= fifo_size
- (entries_required
+ wm
->guard_size
);
983 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size
);
985 /* Don't promote wm_size to unsigned... */
986 if (wm_size
> (long)wm
->max_wm
)
987 wm_size
= wm
->max_wm
;
989 wm_size
= wm
->default_wm
;
993 static struct drm_crtc
*single_enabled_crtc(struct drm_device
*dev
)
995 struct drm_crtc
*crtc
, *enabled
= NULL
;
997 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
998 if (to_intel_crtc(crtc
)->active
&& crtc
->fb
) {
1008 static void pineview_update_wm(struct drm_device
*dev
)
1010 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1011 struct drm_crtc
*crtc
;
1012 const struct cxsr_latency
*latency
;
1016 latency
= intel_get_cxsr_latency(IS_PINEVIEW_G(dev
), dev_priv
->is_ddr3
,
1017 dev_priv
->fsb_freq
, dev_priv
->mem_freq
);
1019 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1020 pineview_disable_cxsr(dev
);
1024 crtc
= single_enabled_crtc(dev
);
1026 int clock
= crtc
->mode
.clock
;
1027 int pixel_size
= crtc
->fb
->bits_per_pixel
/ 8;
1030 wm
= intel_calculate_wm(clock
, &pineview_display_wm
,
1031 pineview_display_wm
.fifo_size
,
1032 pixel_size
, latency
->display_sr
);
1033 reg
= I915_READ(DSPFW1
);
1034 reg
&= ~DSPFW_SR_MASK
;
1035 reg
|= wm
<< DSPFW_SR_SHIFT
;
1036 I915_WRITE(DSPFW1
, reg
);
1037 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg
);
1040 wm
= intel_calculate_wm(clock
, &pineview_cursor_wm
,
1041 pineview_display_wm
.fifo_size
,
1042 pixel_size
, latency
->cursor_sr
);
1043 reg
= I915_READ(DSPFW3
);
1044 reg
&= ~DSPFW_CURSOR_SR_MASK
;
1045 reg
|= (wm
& 0x3f) << DSPFW_CURSOR_SR_SHIFT
;
1046 I915_WRITE(DSPFW3
, reg
);
1048 /* Display HPLL off SR */
1049 wm
= intel_calculate_wm(clock
, &pineview_display_hplloff_wm
,
1050 pineview_display_hplloff_wm
.fifo_size
,
1051 pixel_size
, latency
->display_hpll_disable
);
1052 reg
= I915_READ(DSPFW3
);
1053 reg
&= ~DSPFW_HPLL_SR_MASK
;
1054 reg
|= wm
& DSPFW_HPLL_SR_MASK
;
1055 I915_WRITE(DSPFW3
, reg
);
1057 /* cursor HPLL off SR */
1058 wm
= intel_calculate_wm(clock
, &pineview_cursor_hplloff_wm
,
1059 pineview_display_hplloff_wm
.fifo_size
,
1060 pixel_size
, latency
->cursor_hpll_disable
);
1061 reg
= I915_READ(DSPFW3
);
1062 reg
&= ~DSPFW_HPLL_CURSOR_MASK
;
1063 reg
|= (wm
& 0x3f) << DSPFW_HPLL_CURSOR_SHIFT
;
1064 I915_WRITE(DSPFW3
, reg
);
1065 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg
);
1069 I915_READ(DSPFW3
) | PINEVIEW_SELF_REFRESH_EN
);
1070 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1072 pineview_disable_cxsr(dev
);
1073 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1077 static bool g4x_compute_wm0(struct drm_device
*dev
,
1079 const struct intel_watermark_params
*display
,
1080 int display_latency_ns
,
1081 const struct intel_watermark_params
*cursor
,
1082 int cursor_latency_ns
,
1086 struct drm_crtc
*crtc
;
1087 int htotal
, hdisplay
, clock
, pixel_size
;
1088 int line_time_us
, line_count
;
1089 int entries
, tlb_miss
;
1091 crtc
= intel_get_crtc_for_plane(dev
, plane
);
1092 if (crtc
->fb
== NULL
|| !to_intel_crtc(crtc
)->active
) {
1093 *cursor_wm
= cursor
->guard_size
;
1094 *plane_wm
= display
->guard_size
;
1098 htotal
= crtc
->mode
.htotal
;
1099 hdisplay
= crtc
->mode
.hdisplay
;
1100 clock
= crtc
->mode
.clock
;
1101 pixel_size
= crtc
->fb
->bits_per_pixel
/ 8;
1103 /* Use the small buffer method to calculate plane watermark */
1104 entries
= ((clock
* pixel_size
/ 1000) * display_latency_ns
) / 1000;
1105 tlb_miss
= display
->fifo_size
*display
->cacheline_size
- hdisplay
* 8;
1107 entries
+= tlb_miss
;
1108 entries
= DIV_ROUND_UP(entries
, display
->cacheline_size
);
1109 *plane_wm
= entries
+ display
->guard_size
;
1110 if (*plane_wm
> (int)display
->max_wm
)
1111 *plane_wm
= display
->max_wm
;
1113 /* Use the large buffer method to calculate cursor watermark */
1114 line_time_us
= ((htotal
* 1000) / clock
);
1115 line_count
= (cursor_latency_ns
/ line_time_us
+ 1000) / 1000;
1116 entries
= line_count
* 64 * pixel_size
;
1117 tlb_miss
= cursor
->fifo_size
*cursor
->cacheline_size
- hdisplay
* 8;
1119 entries
+= tlb_miss
;
1120 entries
= DIV_ROUND_UP(entries
, cursor
->cacheline_size
);
1121 *cursor_wm
= entries
+ cursor
->guard_size
;
1122 if (*cursor_wm
> (int)cursor
->max_wm
)
1123 *cursor_wm
= (int)cursor
->max_wm
;
1129 * Check the wm result.
1131 * If any calculated watermark values is larger than the maximum value that
1132 * can be programmed into the associated watermark register, that watermark
1135 static bool g4x_check_srwm(struct drm_device
*dev
,
1136 int display_wm
, int cursor_wm
,
1137 const struct intel_watermark_params
*display
,
1138 const struct intel_watermark_params
*cursor
)
1140 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1141 display_wm
, cursor_wm
);
1143 if (display_wm
> display
->max_wm
) {
1144 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1145 display_wm
, display
->max_wm
);
1149 if (cursor_wm
> cursor
->max_wm
) {
1150 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1151 cursor_wm
, cursor
->max_wm
);
1155 if (!(display_wm
|| cursor_wm
)) {
1156 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1163 static bool g4x_compute_srwm(struct drm_device
*dev
,
1166 const struct intel_watermark_params
*display
,
1167 const struct intel_watermark_params
*cursor
,
1168 int *display_wm
, int *cursor_wm
)
1170 struct drm_crtc
*crtc
;
1171 int hdisplay
, htotal
, pixel_size
, clock
;
1172 unsigned long line_time_us
;
1173 int line_count
, line_size
;
1178 *display_wm
= *cursor_wm
= 0;
1182 crtc
= intel_get_crtc_for_plane(dev
, plane
);
1183 hdisplay
= crtc
->mode
.hdisplay
;
1184 htotal
= crtc
->mode
.htotal
;
1185 clock
= crtc
->mode
.clock
;
1186 pixel_size
= crtc
->fb
->bits_per_pixel
/ 8;
1188 line_time_us
= (htotal
* 1000) / clock
;
1189 line_count
= (latency_ns
/ line_time_us
+ 1000) / 1000;
1190 line_size
= hdisplay
* pixel_size
;
1192 /* Use the minimum of the small and large buffer method for primary */
1193 small
= ((clock
* pixel_size
/ 1000) * latency_ns
) / 1000;
1194 large
= line_count
* line_size
;
1196 entries
= DIV_ROUND_UP(min(small
, large
), display
->cacheline_size
);
1197 *display_wm
= entries
+ display
->guard_size
;
1199 /* calculate the self-refresh watermark for display cursor */
1200 entries
= line_count
* pixel_size
* 64;
1201 entries
= DIV_ROUND_UP(entries
, cursor
->cacheline_size
);
1202 *cursor_wm
= entries
+ cursor
->guard_size
;
1204 return g4x_check_srwm(dev
,
1205 *display_wm
, *cursor_wm
,
1209 static bool vlv_compute_drain_latency(struct drm_device
*dev
,
1211 int *plane_prec_mult
,
1213 int *cursor_prec_mult
,
1216 struct drm_crtc
*crtc
;
1217 int clock
, pixel_size
;
1220 crtc
= intel_get_crtc_for_plane(dev
, plane
);
1221 if (crtc
->fb
== NULL
|| !to_intel_crtc(crtc
)->active
)
1224 clock
= crtc
->mode
.clock
; /* VESA DOT Clock */
1225 pixel_size
= crtc
->fb
->bits_per_pixel
/ 8; /* BPP */
1227 entries
= (clock
/ 1000) * pixel_size
;
1228 *plane_prec_mult
= (entries
> 256) ?
1229 DRAIN_LATENCY_PRECISION_32
: DRAIN_LATENCY_PRECISION_16
;
1230 *plane_dl
= (64 * (*plane_prec_mult
) * 4) / ((clock
/ 1000) *
1233 entries
= (clock
/ 1000) * 4; /* BPP is always 4 for cursor */
1234 *cursor_prec_mult
= (entries
> 256) ?
1235 DRAIN_LATENCY_PRECISION_32
: DRAIN_LATENCY_PRECISION_16
;
1236 *cursor_dl
= (64 * (*cursor_prec_mult
) * 4) / ((clock
/ 1000) * 4);
1242 * Update drain latency registers of memory arbiter
1244 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1245 * to be programmed. Each plane has a drain latency multiplier and a drain
1249 static void vlv_update_drain_latency(struct drm_device
*dev
)
1251 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1252 int planea_prec
, planea_dl
, planeb_prec
, planeb_dl
;
1253 int cursora_prec
, cursora_dl
, cursorb_prec
, cursorb_dl
;
1254 int plane_prec_mult
, cursor_prec_mult
; /* Precision multiplier is
1257 /* For plane A, Cursor A */
1258 if (vlv_compute_drain_latency(dev
, 0, &plane_prec_mult
, &planea_dl
,
1259 &cursor_prec_mult
, &cursora_dl
)) {
1260 cursora_prec
= (cursor_prec_mult
== DRAIN_LATENCY_PRECISION_32
) ?
1261 DDL_CURSORA_PRECISION_32
: DDL_CURSORA_PRECISION_16
;
1262 planea_prec
= (plane_prec_mult
== DRAIN_LATENCY_PRECISION_32
) ?
1263 DDL_PLANEA_PRECISION_32
: DDL_PLANEA_PRECISION_16
;
1265 I915_WRITE(VLV_DDL1
, cursora_prec
|
1266 (cursora_dl
<< DDL_CURSORA_SHIFT
) |
1267 planea_prec
| planea_dl
);
1270 /* For plane B, Cursor B */
1271 if (vlv_compute_drain_latency(dev
, 1, &plane_prec_mult
, &planeb_dl
,
1272 &cursor_prec_mult
, &cursorb_dl
)) {
1273 cursorb_prec
= (cursor_prec_mult
== DRAIN_LATENCY_PRECISION_32
) ?
1274 DDL_CURSORB_PRECISION_32
: DDL_CURSORB_PRECISION_16
;
1275 planeb_prec
= (plane_prec_mult
== DRAIN_LATENCY_PRECISION_32
) ?
1276 DDL_PLANEB_PRECISION_32
: DDL_PLANEB_PRECISION_16
;
1278 I915_WRITE(VLV_DDL2
, cursorb_prec
|
1279 (cursorb_dl
<< DDL_CURSORB_SHIFT
) |
1280 planeb_prec
| planeb_dl
);
1284 #define single_plane_enabled(mask) is_power_of_2(mask)
1286 static void valleyview_update_wm(struct drm_device
*dev
)
1288 static const int sr_latency_ns
= 12000;
1289 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1290 int planea_wm
, planeb_wm
, cursora_wm
, cursorb_wm
;
1291 int plane_sr
, cursor_sr
;
1292 int ignore_plane_sr
, ignore_cursor_sr
;
1293 unsigned int enabled
= 0;
1295 vlv_update_drain_latency(dev
);
1297 if (g4x_compute_wm0(dev
, 0,
1298 &valleyview_wm_info
, latency_ns
,
1299 &valleyview_cursor_wm_info
, latency_ns
,
1300 &planea_wm
, &cursora_wm
))
1303 if (g4x_compute_wm0(dev
, 1,
1304 &valleyview_wm_info
, latency_ns
,
1305 &valleyview_cursor_wm_info
, latency_ns
,
1306 &planeb_wm
, &cursorb_wm
))
1309 if (single_plane_enabled(enabled
) &&
1310 g4x_compute_srwm(dev
, ffs(enabled
) - 1,
1312 &valleyview_wm_info
,
1313 &valleyview_cursor_wm_info
,
1314 &plane_sr
, &ignore_cursor_sr
) &&
1315 g4x_compute_srwm(dev
, ffs(enabled
) - 1,
1317 &valleyview_wm_info
,
1318 &valleyview_cursor_wm_info
,
1319 &ignore_plane_sr
, &cursor_sr
)) {
1320 I915_WRITE(FW_BLC_SELF_VLV
, FW_CSPWRDWNEN
);
1322 I915_WRITE(FW_BLC_SELF_VLV
,
1323 I915_READ(FW_BLC_SELF_VLV
) & ~FW_CSPWRDWNEN
);
1324 plane_sr
= cursor_sr
= 0;
1327 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1328 planea_wm
, cursora_wm
,
1329 planeb_wm
, cursorb_wm
,
1330 plane_sr
, cursor_sr
);
1333 (plane_sr
<< DSPFW_SR_SHIFT
) |
1334 (cursorb_wm
<< DSPFW_CURSORB_SHIFT
) |
1335 (planeb_wm
<< DSPFW_PLANEB_SHIFT
) |
1338 (I915_READ(DSPFW2
) & ~DSPFW_CURSORA_MASK
) |
1339 (cursora_wm
<< DSPFW_CURSORA_SHIFT
));
1341 (I915_READ(DSPFW3
) & ~DSPFW_CURSOR_SR_MASK
) |
1342 (cursor_sr
<< DSPFW_CURSOR_SR_SHIFT
));
1345 static void g4x_update_wm(struct drm_device
*dev
)
1347 static const int sr_latency_ns
= 12000;
1348 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1349 int planea_wm
, planeb_wm
, cursora_wm
, cursorb_wm
;
1350 int plane_sr
, cursor_sr
;
1351 unsigned int enabled
= 0;
1353 if (g4x_compute_wm0(dev
, 0,
1354 &g4x_wm_info
, latency_ns
,
1355 &g4x_cursor_wm_info
, latency_ns
,
1356 &planea_wm
, &cursora_wm
))
1359 if (g4x_compute_wm0(dev
, 1,
1360 &g4x_wm_info
, latency_ns
,
1361 &g4x_cursor_wm_info
, latency_ns
,
1362 &planeb_wm
, &cursorb_wm
))
1365 if (single_plane_enabled(enabled
) &&
1366 g4x_compute_srwm(dev
, ffs(enabled
) - 1,
1369 &g4x_cursor_wm_info
,
1370 &plane_sr
, &cursor_sr
)) {
1371 I915_WRITE(FW_BLC_SELF
, FW_BLC_SELF_EN
);
1373 I915_WRITE(FW_BLC_SELF
,
1374 I915_READ(FW_BLC_SELF
) & ~FW_BLC_SELF_EN
);
1375 plane_sr
= cursor_sr
= 0;
1378 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1379 planea_wm
, cursora_wm
,
1380 planeb_wm
, cursorb_wm
,
1381 plane_sr
, cursor_sr
);
1384 (plane_sr
<< DSPFW_SR_SHIFT
) |
1385 (cursorb_wm
<< DSPFW_CURSORB_SHIFT
) |
1386 (planeb_wm
<< DSPFW_PLANEB_SHIFT
) |
1389 (I915_READ(DSPFW2
) & ~DSPFW_CURSORA_MASK
) |
1390 (cursora_wm
<< DSPFW_CURSORA_SHIFT
));
1391 /* HPLL off in SR has some issues on G4x... disable it */
1393 (I915_READ(DSPFW3
) & ~(DSPFW_HPLL_SR_EN
| DSPFW_CURSOR_SR_MASK
)) |
1394 (cursor_sr
<< DSPFW_CURSOR_SR_SHIFT
));
1397 static void i965_update_wm(struct drm_device
*dev
)
1399 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1400 struct drm_crtc
*crtc
;
1404 /* Calc sr entries for one plane configs */
1405 crtc
= single_enabled_crtc(dev
);
1407 /* self-refresh has much higher latency */
1408 static const int sr_latency_ns
= 12000;
1409 int clock
= crtc
->mode
.clock
;
1410 int htotal
= crtc
->mode
.htotal
;
1411 int hdisplay
= crtc
->mode
.hdisplay
;
1412 int pixel_size
= crtc
->fb
->bits_per_pixel
/ 8;
1413 unsigned long line_time_us
;
1416 line_time_us
= ((htotal
* 1000) / clock
);
1418 /* Use ns/us then divide to preserve precision */
1419 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
1420 pixel_size
* hdisplay
;
1421 entries
= DIV_ROUND_UP(entries
, I915_FIFO_LINE_SIZE
);
1422 srwm
= I965_FIFO_SIZE
- entries
;
1426 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1429 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
1431 entries
= DIV_ROUND_UP(entries
,
1432 i965_cursor_wm_info
.cacheline_size
);
1433 cursor_sr
= i965_cursor_wm_info
.fifo_size
-
1434 (entries
+ i965_cursor_wm_info
.guard_size
);
1436 if (cursor_sr
> i965_cursor_wm_info
.max_wm
)
1437 cursor_sr
= i965_cursor_wm_info
.max_wm
;
1439 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1440 "cursor %d\n", srwm
, cursor_sr
);
1442 if (IS_CRESTLINE(dev
))
1443 I915_WRITE(FW_BLC_SELF
, FW_BLC_SELF_EN
);
1445 /* Turn off self refresh if both pipes are enabled */
1446 if (IS_CRESTLINE(dev
))
1447 I915_WRITE(FW_BLC_SELF
, I915_READ(FW_BLC_SELF
)
1451 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1454 /* 965 has limitations... */
1455 I915_WRITE(DSPFW1
, (srwm
<< DSPFW_SR_SHIFT
) |
1456 (8 << 16) | (8 << 8) | (8 << 0));
1457 I915_WRITE(DSPFW2
, (8 << 8) | (8 << 0));
1458 /* update cursor SR watermark */
1459 I915_WRITE(DSPFW3
, (cursor_sr
<< DSPFW_CURSOR_SR_SHIFT
));
1462 static void i9xx_update_wm(struct drm_device
*dev
)
1464 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1465 const struct intel_watermark_params
*wm_info
;
1470 int planea_wm
, planeb_wm
;
1471 struct drm_crtc
*crtc
, *enabled
= NULL
;
1474 wm_info
= &i945_wm_info
;
1475 else if (!IS_GEN2(dev
))
1476 wm_info
= &i915_wm_info
;
1478 wm_info
= &i855_wm_info
;
1480 fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 0);
1481 crtc
= intel_get_crtc_for_plane(dev
, 0);
1482 if (to_intel_crtc(crtc
)->active
&& crtc
->fb
) {
1483 int cpp
= crtc
->fb
->bits_per_pixel
/ 8;
1487 planea_wm
= intel_calculate_wm(crtc
->mode
.clock
,
1488 wm_info
, fifo_size
, cpp
,
1492 planea_wm
= fifo_size
- wm_info
->guard_size
;
1494 fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 1);
1495 crtc
= intel_get_crtc_for_plane(dev
, 1);
1496 if (to_intel_crtc(crtc
)->active
&& crtc
->fb
) {
1497 int cpp
= crtc
->fb
->bits_per_pixel
/ 8;
1501 planeb_wm
= intel_calculate_wm(crtc
->mode
.clock
,
1502 wm_info
, fifo_size
, cpp
,
1504 if (enabled
== NULL
)
1509 planeb_wm
= fifo_size
- wm_info
->guard_size
;
1511 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm
, planeb_wm
);
1514 * Overlay gets an aggressive default since video jitter is bad.
1518 /* Play safe and disable self-refresh before adjusting watermarks. */
1519 if (IS_I945G(dev
) || IS_I945GM(dev
))
1520 I915_WRITE(FW_BLC_SELF
, FW_BLC_SELF_EN_MASK
| 0);
1521 else if (IS_I915GM(dev
))
1522 I915_WRITE(INSTPM
, I915_READ(INSTPM
) & ~INSTPM_SELF_EN
);
1524 /* Calc sr entries for one plane configs */
1525 if (HAS_FW_BLC(dev
) && enabled
) {
1526 /* self-refresh has much higher latency */
1527 static const int sr_latency_ns
= 6000;
1528 int clock
= enabled
->mode
.clock
;
1529 int htotal
= enabled
->mode
.htotal
;
1530 int hdisplay
= enabled
->mode
.hdisplay
;
1531 int pixel_size
= enabled
->fb
->bits_per_pixel
/ 8;
1532 unsigned long line_time_us
;
1535 line_time_us
= (htotal
* 1000) / clock
;
1537 /* Use ns/us then divide to preserve precision */
1538 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
1539 pixel_size
* hdisplay
;
1540 entries
= DIV_ROUND_UP(entries
, wm_info
->cacheline_size
);
1541 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries
);
1542 srwm
= wm_info
->fifo_size
- entries
;
1546 if (IS_I945G(dev
) || IS_I945GM(dev
))
1547 I915_WRITE(FW_BLC_SELF
,
1548 FW_BLC_SELF_FIFO_MASK
| (srwm
& 0xff));
1549 else if (IS_I915GM(dev
))
1550 I915_WRITE(FW_BLC_SELF
, srwm
& 0x3f);
1553 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1554 planea_wm
, planeb_wm
, cwm
, srwm
);
1556 fwater_lo
= ((planeb_wm
& 0x3f) << 16) | (planea_wm
& 0x3f);
1557 fwater_hi
= (cwm
& 0x1f);
1559 /* Set request length to 8 cachelines per fetch */
1560 fwater_lo
= fwater_lo
| (1 << 24) | (1 << 8);
1561 fwater_hi
= fwater_hi
| (1 << 8);
1563 I915_WRITE(FW_BLC
, fwater_lo
);
1564 I915_WRITE(FW_BLC2
, fwater_hi
);
1566 if (HAS_FW_BLC(dev
)) {
1568 if (IS_I945G(dev
) || IS_I945GM(dev
))
1569 I915_WRITE(FW_BLC_SELF
,
1570 FW_BLC_SELF_EN_MASK
| FW_BLC_SELF_EN
);
1571 else if (IS_I915GM(dev
))
1572 I915_WRITE(INSTPM
, I915_READ(INSTPM
) | INSTPM_SELF_EN
);
1573 DRM_DEBUG_KMS("memory self refresh enabled\n");
1575 DRM_DEBUG_KMS("memory self refresh disabled\n");
1579 static void i830_update_wm(struct drm_device
*dev
)
1581 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1582 struct drm_crtc
*crtc
;
1586 crtc
= single_enabled_crtc(dev
);
1590 planea_wm
= intel_calculate_wm(crtc
->mode
.clock
, &i830_wm_info
,
1591 dev_priv
->display
.get_fifo_size(dev
, 0),
1593 fwater_lo
= I915_READ(FW_BLC
) & ~0xfff;
1594 fwater_lo
|= (3<<8) | planea_wm
;
1596 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm
);
1598 I915_WRITE(FW_BLC
, fwater_lo
);
1601 #define ILK_LP0_PLANE_LATENCY 700
1602 #define ILK_LP0_CURSOR_LATENCY 1300
1605 * Check the wm result.
1607 * If any calculated watermark values is larger than the maximum value that
1608 * can be programmed into the associated watermark register, that watermark
1611 static bool ironlake_check_srwm(struct drm_device
*dev
, int level
,
1612 int fbc_wm
, int display_wm
, int cursor_wm
,
1613 const struct intel_watermark_params
*display
,
1614 const struct intel_watermark_params
*cursor
)
1616 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1618 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
1619 " cursor %d\n", level
, display_wm
, fbc_wm
, cursor_wm
);
1621 if (fbc_wm
> SNB_FBC_MAX_SRWM
) {
1622 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
1623 fbc_wm
, SNB_FBC_MAX_SRWM
, level
);
1625 /* fbc has it's own way to disable FBC WM */
1626 I915_WRITE(DISP_ARB_CTL
,
1627 I915_READ(DISP_ARB_CTL
) | DISP_FBC_WM_DIS
);
1631 if (display_wm
> display
->max_wm
) {
1632 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
1633 display_wm
, SNB_DISPLAY_MAX_SRWM
, level
);
1637 if (cursor_wm
> cursor
->max_wm
) {
1638 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
1639 cursor_wm
, SNB_CURSOR_MAX_SRWM
, level
);
1643 if (!(fbc_wm
|| display_wm
|| cursor_wm
)) {
1644 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level
, level
);
1652 * Compute watermark values of WM[1-3],
1654 static bool ironlake_compute_srwm(struct drm_device
*dev
, int level
, int plane
,
1656 const struct intel_watermark_params
*display
,
1657 const struct intel_watermark_params
*cursor
,
1658 int *fbc_wm
, int *display_wm
, int *cursor_wm
)
1660 struct drm_crtc
*crtc
;
1661 unsigned long line_time_us
;
1662 int hdisplay
, htotal
, pixel_size
, clock
;
1663 int line_count
, line_size
;
1668 *fbc_wm
= *display_wm
= *cursor_wm
= 0;
1672 crtc
= intel_get_crtc_for_plane(dev
, plane
);
1673 hdisplay
= crtc
->mode
.hdisplay
;
1674 htotal
= crtc
->mode
.htotal
;
1675 clock
= crtc
->mode
.clock
;
1676 pixel_size
= crtc
->fb
->bits_per_pixel
/ 8;
1678 line_time_us
= (htotal
* 1000) / clock
;
1679 line_count
= (latency_ns
/ line_time_us
+ 1000) / 1000;
1680 line_size
= hdisplay
* pixel_size
;
1682 /* Use the minimum of the small and large buffer method for primary */
1683 small
= ((clock
* pixel_size
/ 1000) * latency_ns
) / 1000;
1684 large
= line_count
* line_size
;
1686 entries
= DIV_ROUND_UP(min(small
, large
), display
->cacheline_size
);
1687 *display_wm
= entries
+ display
->guard_size
;
1691 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
1693 *fbc_wm
= DIV_ROUND_UP(*display_wm
* 64, line_size
) + 2;
1695 /* calculate the self-refresh watermark for display cursor */
1696 entries
= line_count
* pixel_size
* 64;
1697 entries
= DIV_ROUND_UP(entries
, cursor
->cacheline_size
);
1698 *cursor_wm
= entries
+ cursor
->guard_size
;
1700 return ironlake_check_srwm(dev
, level
,
1701 *fbc_wm
, *display_wm
, *cursor_wm
,
1705 static void ironlake_update_wm(struct drm_device
*dev
)
1707 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1708 int fbc_wm
, plane_wm
, cursor_wm
;
1709 unsigned int enabled
;
1712 if (g4x_compute_wm0(dev
, 0,
1713 &ironlake_display_wm_info
,
1714 ILK_LP0_PLANE_LATENCY
,
1715 &ironlake_cursor_wm_info
,
1716 ILK_LP0_CURSOR_LATENCY
,
1717 &plane_wm
, &cursor_wm
)) {
1718 I915_WRITE(WM0_PIPEA_ILK
,
1719 (plane_wm
<< WM0_PIPE_PLANE_SHIFT
) | cursor_wm
);
1720 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1721 " plane %d, " "cursor: %d\n",
1722 plane_wm
, cursor_wm
);
1726 if (g4x_compute_wm0(dev
, 1,
1727 &ironlake_display_wm_info
,
1728 ILK_LP0_PLANE_LATENCY
,
1729 &ironlake_cursor_wm_info
,
1730 ILK_LP0_CURSOR_LATENCY
,
1731 &plane_wm
, &cursor_wm
)) {
1732 I915_WRITE(WM0_PIPEB_ILK
,
1733 (plane_wm
<< WM0_PIPE_PLANE_SHIFT
) | cursor_wm
);
1734 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1735 " plane %d, cursor: %d\n",
1736 plane_wm
, cursor_wm
);
1741 * Calculate and update the self-refresh watermark only when one
1742 * display plane is used.
1744 I915_WRITE(WM3_LP_ILK
, 0);
1745 I915_WRITE(WM2_LP_ILK
, 0);
1746 I915_WRITE(WM1_LP_ILK
, 0);
1748 if (!single_plane_enabled(enabled
))
1750 enabled
= ffs(enabled
) - 1;
1753 if (!ironlake_compute_srwm(dev
, 1, enabled
,
1754 ILK_READ_WM1_LATENCY() * 500,
1755 &ironlake_display_srwm_info
,
1756 &ironlake_cursor_srwm_info
,
1757 &fbc_wm
, &plane_wm
, &cursor_wm
))
1760 I915_WRITE(WM1_LP_ILK
,
1762 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT
) |
1763 (fbc_wm
<< WM1_LP_FBC_SHIFT
) |
1764 (plane_wm
<< WM1_LP_SR_SHIFT
) |
1768 if (!ironlake_compute_srwm(dev
, 2, enabled
,
1769 ILK_READ_WM2_LATENCY() * 500,
1770 &ironlake_display_srwm_info
,
1771 &ironlake_cursor_srwm_info
,
1772 &fbc_wm
, &plane_wm
, &cursor_wm
))
1775 I915_WRITE(WM2_LP_ILK
,
1777 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT
) |
1778 (fbc_wm
<< WM1_LP_FBC_SHIFT
) |
1779 (plane_wm
<< WM1_LP_SR_SHIFT
) |
1783 * WM3 is unsupported on ILK, probably because we don't have latency
1784 * data for that power state
1788 static void sandybridge_update_wm(struct drm_device
*dev
)
1790 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1791 int latency
= SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
1793 int fbc_wm
, plane_wm
, cursor_wm
;
1794 unsigned int enabled
;
1797 if (g4x_compute_wm0(dev
, 0,
1798 &sandybridge_display_wm_info
, latency
,
1799 &sandybridge_cursor_wm_info
, latency
,
1800 &plane_wm
, &cursor_wm
)) {
1801 val
= I915_READ(WM0_PIPEA_ILK
);
1802 val
&= ~(WM0_PIPE_PLANE_MASK
| WM0_PIPE_CURSOR_MASK
);
1803 I915_WRITE(WM0_PIPEA_ILK
, val
|
1804 ((plane_wm
<< WM0_PIPE_PLANE_SHIFT
) | cursor_wm
));
1805 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1806 " plane %d, " "cursor: %d\n",
1807 plane_wm
, cursor_wm
);
1811 if (g4x_compute_wm0(dev
, 1,
1812 &sandybridge_display_wm_info
, latency
,
1813 &sandybridge_cursor_wm_info
, latency
,
1814 &plane_wm
, &cursor_wm
)) {
1815 val
= I915_READ(WM0_PIPEB_ILK
);
1816 val
&= ~(WM0_PIPE_PLANE_MASK
| WM0_PIPE_CURSOR_MASK
);
1817 I915_WRITE(WM0_PIPEB_ILK
, val
|
1818 ((plane_wm
<< WM0_PIPE_PLANE_SHIFT
) | cursor_wm
));
1819 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1820 " plane %d, cursor: %d\n",
1821 plane_wm
, cursor_wm
);
1826 * Calculate and update the self-refresh watermark only when one
1827 * display plane is used.
1829 * SNB support 3 levels of watermark.
1831 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1832 * and disabled in the descending order
1835 I915_WRITE(WM3_LP_ILK
, 0);
1836 I915_WRITE(WM2_LP_ILK
, 0);
1837 I915_WRITE(WM1_LP_ILK
, 0);
1839 if (!single_plane_enabled(enabled
) ||
1840 dev_priv
->sprite_scaling_enabled
)
1842 enabled
= ffs(enabled
) - 1;
1845 if (!ironlake_compute_srwm(dev
, 1, enabled
,
1846 SNB_READ_WM1_LATENCY() * 500,
1847 &sandybridge_display_srwm_info
,
1848 &sandybridge_cursor_srwm_info
,
1849 &fbc_wm
, &plane_wm
, &cursor_wm
))
1852 I915_WRITE(WM1_LP_ILK
,
1854 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT
) |
1855 (fbc_wm
<< WM1_LP_FBC_SHIFT
) |
1856 (plane_wm
<< WM1_LP_SR_SHIFT
) |
1860 if (!ironlake_compute_srwm(dev
, 2, enabled
,
1861 SNB_READ_WM2_LATENCY() * 500,
1862 &sandybridge_display_srwm_info
,
1863 &sandybridge_cursor_srwm_info
,
1864 &fbc_wm
, &plane_wm
, &cursor_wm
))
1867 I915_WRITE(WM2_LP_ILK
,
1869 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT
) |
1870 (fbc_wm
<< WM1_LP_FBC_SHIFT
) |
1871 (plane_wm
<< WM1_LP_SR_SHIFT
) |
1875 if (!ironlake_compute_srwm(dev
, 3, enabled
,
1876 SNB_READ_WM3_LATENCY() * 500,
1877 &sandybridge_display_srwm_info
,
1878 &sandybridge_cursor_srwm_info
,
1879 &fbc_wm
, &plane_wm
, &cursor_wm
))
1882 I915_WRITE(WM3_LP_ILK
,
1884 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT
) |
1885 (fbc_wm
<< WM1_LP_FBC_SHIFT
) |
1886 (plane_wm
<< WM1_LP_SR_SHIFT
) |
1890 static void ivybridge_update_wm(struct drm_device
*dev
)
1892 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1893 int latency
= SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
1895 int fbc_wm
, plane_wm
, cursor_wm
;
1896 int ignore_fbc_wm
, ignore_plane_wm
, ignore_cursor_wm
;
1897 unsigned int enabled
;
1900 if (g4x_compute_wm0(dev
, 0,
1901 &sandybridge_display_wm_info
, latency
,
1902 &sandybridge_cursor_wm_info
, latency
,
1903 &plane_wm
, &cursor_wm
)) {
1904 val
= I915_READ(WM0_PIPEA_ILK
);
1905 val
&= ~(WM0_PIPE_PLANE_MASK
| WM0_PIPE_CURSOR_MASK
);
1906 I915_WRITE(WM0_PIPEA_ILK
, val
|
1907 ((plane_wm
<< WM0_PIPE_PLANE_SHIFT
) | cursor_wm
));
1908 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1909 " plane %d, " "cursor: %d\n",
1910 plane_wm
, cursor_wm
);
1914 if (g4x_compute_wm0(dev
, 1,
1915 &sandybridge_display_wm_info
, latency
,
1916 &sandybridge_cursor_wm_info
, latency
,
1917 &plane_wm
, &cursor_wm
)) {
1918 val
= I915_READ(WM0_PIPEB_ILK
);
1919 val
&= ~(WM0_PIPE_PLANE_MASK
| WM0_PIPE_CURSOR_MASK
);
1920 I915_WRITE(WM0_PIPEB_ILK
, val
|
1921 ((plane_wm
<< WM0_PIPE_PLANE_SHIFT
) | cursor_wm
));
1922 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1923 " plane %d, cursor: %d\n",
1924 plane_wm
, cursor_wm
);
1928 if (g4x_compute_wm0(dev
, 2,
1929 &sandybridge_display_wm_info
, latency
,
1930 &sandybridge_cursor_wm_info
, latency
,
1931 &plane_wm
, &cursor_wm
)) {
1932 val
= I915_READ(WM0_PIPEC_IVB
);
1933 val
&= ~(WM0_PIPE_PLANE_MASK
| WM0_PIPE_CURSOR_MASK
);
1934 I915_WRITE(WM0_PIPEC_IVB
, val
|
1935 ((plane_wm
<< WM0_PIPE_PLANE_SHIFT
) | cursor_wm
));
1936 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
1937 " plane %d, cursor: %d\n",
1938 plane_wm
, cursor_wm
);
1943 * Calculate and update the self-refresh watermark only when one
1944 * display plane is used.
1946 * SNB support 3 levels of watermark.
1948 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1949 * and disabled in the descending order
1952 I915_WRITE(WM3_LP_ILK
, 0);
1953 I915_WRITE(WM2_LP_ILK
, 0);
1954 I915_WRITE(WM1_LP_ILK
, 0);
1956 if (!single_plane_enabled(enabled
) ||
1957 dev_priv
->sprite_scaling_enabled
)
1959 enabled
= ffs(enabled
) - 1;
1962 if (!ironlake_compute_srwm(dev
, 1, enabled
,
1963 SNB_READ_WM1_LATENCY() * 500,
1964 &sandybridge_display_srwm_info
,
1965 &sandybridge_cursor_srwm_info
,
1966 &fbc_wm
, &plane_wm
, &cursor_wm
))
1969 I915_WRITE(WM1_LP_ILK
,
1971 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT
) |
1972 (fbc_wm
<< WM1_LP_FBC_SHIFT
) |
1973 (plane_wm
<< WM1_LP_SR_SHIFT
) |
1977 if (!ironlake_compute_srwm(dev
, 2, enabled
,
1978 SNB_READ_WM2_LATENCY() * 500,
1979 &sandybridge_display_srwm_info
,
1980 &sandybridge_cursor_srwm_info
,
1981 &fbc_wm
, &plane_wm
, &cursor_wm
))
1984 I915_WRITE(WM2_LP_ILK
,
1986 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT
) |
1987 (fbc_wm
<< WM1_LP_FBC_SHIFT
) |
1988 (plane_wm
<< WM1_LP_SR_SHIFT
) |
1991 /* WM3, note we have to correct the cursor latency */
1992 if (!ironlake_compute_srwm(dev
, 3, enabled
,
1993 SNB_READ_WM3_LATENCY() * 500,
1994 &sandybridge_display_srwm_info
,
1995 &sandybridge_cursor_srwm_info
,
1996 &fbc_wm
, &plane_wm
, &ignore_cursor_wm
) ||
1997 !ironlake_compute_srwm(dev
, 3, enabled
,
1998 2 * SNB_READ_WM3_LATENCY() * 500,
1999 &sandybridge_display_srwm_info
,
2000 &sandybridge_cursor_srwm_info
,
2001 &ignore_fbc_wm
, &ignore_plane_wm
, &cursor_wm
))
2004 I915_WRITE(WM3_LP_ILK
,
2006 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT
) |
2007 (fbc_wm
<< WM1_LP_FBC_SHIFT
) |
2008 (plane_wm
<< WM1_LP_SR_SHIFT
) |
2013 haswell_update_linetime_wm(struct drm_device
*dev
, int pipe
,
2014 struct drm_display_mode
*mode
)
2016 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2019 temp
= I915_READ(PIPE_WM_LINETIME(pipe
));
2020 temp
&= ~PIPE_WM_LINETIME_MASK
;
2022 /* The WM are computed with base on how long it takes to fill a single
2023 * row at the given clock rate, multiplied by 8.
2025 temp
|= PIPE_WM_LINETIME_TIME(
2026 ((mode
->crtc_hdisplay
* 1000) / mode
->clock
) * 8);
2028 /* IPS watermarks are only used by pipe A, and are ignored by
2029 * pipes B and C. They are calculated similarly to the common
2030 * linetime values, except that we are using CD clock frequency
2031 * in MHz instead of pixel rate for the division.
2033 * This is a placeholder for the IPS watermark calculation code.
2036 I915_WRITE(PIPE_WM_LINETIME(pipe
), temp
);
2040 sandybridge_compute_sprite_wm(struct drm_device
*dev
, int plane
,
2041 uint32_t sprite_width
, int pixel_size
,
2042 const struct intel_watermark_params
*display
,
2043 int display_latency_ns
, int *sprite_wm
)
2045 struct drm_crtc
*crtc
;
2047 int entries
, tlb_miss
;
2049 crtc
= intel_get_crtc_for_plane(dev
, plane
);
2050 if (crtc
->fb
== NULL
|| !to_intel_crtc(crtc
)->active
) {
2051 *sprite_wm
= display
->guard_size
;
2055 clock
= crtc
->mode
.clock
;
2057 /* Use the small buffer method to calculate the sprite watermark */
2058 entries
= ((clock
* pixel_size
/ 1000) * display_latency_ns
) / 1000;
2059 tlb_miss
= display
->fifo_size
*display
->cacheline_size
-
2062 entries
+= tlb_miss
;
2063 entries
= DIV_ROUND_UP(entries
, display
->cacheline_size
);
2064 *sprite_wm
= entries
+ display
->guard_size
;
2065 if (*sprite_wm
> (int)display
->max_wm
)
2066 *sprite_wm
= display
->max_wm
;
2072 sandybridge_compute_sprite_srwm(struct drm_device
*dev
, int plane
,
2073 uint32_t sprite_width
, int pixel_size
,
2074 const struct intel_watermark_params
*display
,
2075 int latency_ns
, int *sprite_wm
)
2077 struct drm_crtc
*crtc
;
2078 unsigned long line_time_us
;
2080 int line_count
, line_size
;
2089 crtc
= intel_get_crtc_for_plane(dev
, plane
);
2090 clock
= crtc
->mode
.clock
;
2096 line_time_us
= (sprite_width
* 1000) / clock
;
2097 if (!line_time_us
) {
2102 line_count
= (latency_ns
/ line_time_us
+ 1000) / 1000;
2103 line_size
= sprite_width
* pixel_size
;
2105 /* Use the minimum of the small and large buffer method for primary */
2106 small
= ((clock
* pixel_size
/ 1000) * latency_ns
) / 1000;
2107 large
= line_count
* line_size
;
2109 entries
= DIV_ROUND_UP(min(small
, large
), display
->cacheline_size
);
2110 *sprite_wm
= entries
+ display
->guard_size
;
2112 return *sprite_wm
> 0x3ff ? false : true;
2115 static void sandybridge_update_sprite_wm(struct drm_device
*dev
, int pipe
,
2116 uint32_t sprite_width
, int pixel_size
)
2118 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2119 int latency
= SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
2126 reg
= WM0_PIPEA_ILK
;
2129 reg
= WM0_PIPEB_ILK
;
2132 reg
= WM0_PIPEC_IVB
;
2135 return; /* bad pipe */
2138 ret
= sandybridge_compute_sprite_wm(dev
, pipe
, sprite_width
, pixel_size
,
2139 &sandybridge_display_wm_info
,
2140 latency
, &sprite_wm
);
2142 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %d\n",
2147 val
= I915_READ(reg
);
2148 val
&= ~WM0_PIPE_SPRITE_MASK
;
2149 I915_WRITE(reg
, val
| (sprite_wm
<< WM0_PIPE_SPRITE_SHIFT
));
2150 DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe
, sprite_wm
);
2153 ret
= sandybridge_compute_sprite_srwm(dev
, pipe
, sprite_width
,
2155 &sandybridge_display_srwm_info
,
2156 SNB_READ_WM1_LATENCY() * 500,
2159 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %d\n",
2163 I915_WRITE(WM1S_LP_ILK
, sprite_wm
);
2165 /* Only IVB has two more LP watermarks for sprite */
2166 if (!IS_IVYBRIDGE(dev
))
2169 ret
= sandybridge_compute_sprite_srwm(dev
, pipe
, sprite_width
,
2171 &sandybridge_display_srwm_info
,
2172 SNB_READ_WM2_LATENCY() * 500,
2175 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %d\n",
2179 I915_WRITE(WM2S_LP_IVB
, sprite_wm
);
2181 ret
= sandybridge_compute_sprite_srwm(dev
, pipe
, sprite_width
,
2183 &sandybridge_display_srwm_info
,
2184 SNB_READ_WM3_LATENCY() * 500,
2187 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %d\n",
2191 I915_WRITE(WM3S_LP_IVB
, sprite_wm
);
2195 * intel_update_watermarks - update FIFO watermark values based on current modes
2197 * Calculate watermark values for the various WM regs based on current mode
2198 * and plane configuration.
2200 * There are several cases to deal with here:
2201 * - normal (i.e. non-self-refresh)
2202 * - self-refresh (SR) mode
2203 * - lines are large relative to FIFO size (buffer can hold up to 2)
2204 * - lines are small relative to FIFO size (buffer can hold more than 2
2205 * lines), so need to account for TLB latency
2207 * The normal calculation is:
2208 * watermark = dotclock * bytes per pixel * latency
2209 * where latency is platform & configuration dependent (we assume pessimal
2212 * The SR calculation is:
2213 * watermark = (trunc(latency/line time)+1) * surface width *
2216 * line time = htotal / dotclock
2217 * surface width = hdisplay for normal plane and 64 for cursor
2218 * and latency is assumed to be high, as above.
2220 * The final value programmed to the register should always be rounded up,
2221 * and include an extra 2 entries to account for clock crossings.
2223 * We don't use the sprite, so we can ignore that. And on Crestline we have
2224 * to set the non-SR watermarks to 8.
2226 void intel_update_watermarks(struct drm_device
*dev
)
2228 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2230 if (dev_priv
->display
.update_wm
)
2231 dev_priv
->display
.update_wm(dev
);
2234 void intel_update_linetime_watermarks(struct drm_device
*dev
,
2235 int pipe
, struct drm_display_mode
*mode
)
2237 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2239 if (dev_priv
->display
.update_linetime_wm
)
2240 dev_priv
->display
.update_linetime_wm(dev
, pipe
, mode
);
2243 void intel_update_sprite_watermarks(struct drm_device
*dev
, int pipe
,
2244 uint32_t sprite_width
, int pixel_size
)
2246 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2248 if (dev_priv
->display
.update_sprite_wm
)
2249 dev_priv
->display
.update_sprite_wm(dev
, pipe
, sprite_width
,
2253 static struct drm_i915_gem_object
*
2254 intel_alloc_context_page(struct drm_device
*dev
)
2256 struct drm_i915_gem_object
*ctx
;
2259 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
2261 ctx
= i915_gem_alloc_object(dev
, 4096);
2263 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
2267 ret
= i915_gem_object_pin(ctx
, 4096, true, false);
2269 DRM_ERROR("failed to pin power context: %d\n", ret
);
2273 ret
= i915_gem_object_set_to_gtt_domain(ctx
, 1);
2275 DRM_ERROR("failed to set-domain on power context: %d\n", ret
);
2282 i915_gem_object_unpin(ctx
);
2284 drm_gem_object_unreference(&ctx
->base
);
2285 mutex_unlock(&dev
->struct_mutex
);
2290 * Lock protecting IPS related data structures
2292 DEFINE_SPINLOCK(mchdev_lock
);
2294 /* Global for IPS driver to get at the current i915 device. Protected by
2296 static struct drm_i915_private
*i915_mch_dev
;
2298 bool ironlake_set_drps(struct drm_device
*dev
, u8 val
)
2300 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2303 assert_spin_locked(&mchdev_lock
);
2305 rgvswctl
= I915_READ16(MEMSWCTL
);
2306 if (rgvswctl
& MEMCTL_CMD_STS
) {
2307 DRM_DEBUG("gpu busy, RCS change rejected\n");
2308 return false; /* still busy with another command */
2311 rgvswctl
= (MEMCTL_CMD_CHFREQ
<< MEMCTL_CMD_SHIFT
) |
2312 (val
<< MEMCTL_FREQ_SHIFT
) | MEMCTL_SFCAVM
;
2313 I915_WRITE16(MEMSWCTL
, rgvswctl
);
2314 POSTING_READ16(MEMSWCTL
);
2316 rgvswctl
|= MEMCTL_CMD_STS
;
2317 I915_WRITE16(MEMSWCTL
, rgvswctl
);
2322 static void ironlake_enable_drps(struct drm_device
*dev
)
2324 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2325 u32 rgvmodectl
= I915_READ(MEMMODECTL
);
2326 u8 fmax
, fmin
, fstart
, vstart
;
2328 spin_lock_irq(&mchdev_lock
);
2330 /* Enable temp reporting */
2331 I915_WRITE16(PMMISC
, I915_READ(PMMISC
) | MCPPCE_EN
);
2332 I915_WRITE16(TSC1
, I915_READ(TSC1
) | TSE
);
2334 /* 100ms RC evaluation intervals */
2335 I915_WRITE(RCUPEI
, 100000);
2336 I915_WRITE(RCDNEI
, 100000);
2338 /* Set max/min thresholds to 90ms and 80ms respectively */
2339 I915_WRITE(RCBMAXAVG
, 90000);
2340 I915_WRITE(RCBMINAVG
, 80000);
2342 I915_WRITE(MEMIHYST
, 1);
2344 /* Set up min, max, and cur for interrupt handling */
2345 fmax
= (rgvmodectl
& MEMMODE_FMAX_MASK
) >> MEMMODE_FMAX_SHIFT
;
2346 fmin
= (rgvmodectl
& MEMMODE_FMIN_MASK
);
2347 fstart
= (rgvmodectl
& MEMMODE_FSTART_MASK
) >>
2348 MEMMODE_FSTART_SHIFT
;
2350 vstart
= (I915_READ(PXVFREQ_BASE
+ (fstart
* 4)) & PXVFREQ_PX_MASK
) >>
2353 dev_priv
->ips
.fmax
= fmax
; /* IPS callback will increase this */
2354 dev_priv
->ips
.fstart
= fstart
;
2356 dev_priv
->ips
.max_delay
= fstart
;
2357 dev_priv
->ips
.min_delay
= fmin
;
2358 dev_priv
->ips
.cur_delay
= fstart
;
2360 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
2361 fmax
, fmin
, fstart
);
2363 I915_WRITE(MEMINTREN
, MEMINT_CX_SUPR_EN
| MEMINT_EVAL_CHG_EN
);
2366 * Interrupts will be enabled in ironlake_irq_postinstall
2369 I915_WRITE(VIDSTART
, vstart
);
2370 POSTING_READ(VIDSTART
);
2372 rgvmodectl
|= MEMMODE_SWMODE_EN
;
2373 I915_WRITE(MEMMODECTL
, rgvmodectl
);
2375 if (wait_for_atomic((I915_READ(MEMSWCTL
) & MEMCTL_CMD_STS
) == 0, 10))
2376 DRM_ERROR("stuck trying to change perf mode\n");
2379 ironlake_set_drps(dev
, fstart
);
2381 dev_priv
->ips
.last_count1
= I915_READ(0x112e4) + I915_READ(0x112e8) +
2383 dev_priv
->ips
.last_time1
= jiffies_to_msecs(jiffies
);
2384 dev_priv
->ips
.last_count2
= I915_READ(0x112f4);
2385 getrawmonotonic(&dev_priv
->ips
.last_time2
);
2387 spin_unlock_irq(&mchdev_lock
);
2390 static void ironlake_disable_drps(struct drm_device
*dev
)
2392 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2395 spin_lock_irq(&mchdev_lock
);
2397 rgvswctl
= I915_READ16(MEMSWCTL
);
2399 /* Ack interrupts, disable EFC interrupt */
2400 I915_WRITE(MEMINTREN
, I915_READ(MEMINTREN
) & ~MEMINT_EVAL_CHG_EN
);
2401 I915_WRITE(MEMINTRSTS
, MEMINT_EVAL_CHG
);
2402 I915_WRITE(DEIER
, I915_READ(DEIER
) & ~DE_PCU_EVENT
);
2403 I915_WRITE(DEIIR
, DE_PCU_EVENT
);
2404 I915_WRITE(DEIMR
, I915_READ(DEIMR
) | DE_PCU_EVENT
);
2406 /* Go back to the starting frequency */
2407 ironlake_set_drps(dev
, dev_priv
->ips
.fstart
);
2409 rgvswctl
|= MEMCTL_CMD_STS
;
2410 I915_WRITE(MEMSWCTL
, rgvswctl
);
2413 spin_unlock_irq(&mchdev_lock
);
2416 /* There's a funny hw issue where the hw returns all 0 when reading from
2417 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
2418 * ourselves, instead of doing a rmw cycle (which might result in us clearing
2419 * all limits and the gpu stuck at whatever frequency it is at atm).
2421 static u32
gen6_rps_limits(struct drm_i915_private
*dev_priv
, u8
*val
)
2427 if (*val
>= dev_priv
->rps
.max_delay
)
2428 *val
= dev_priv
->rps
.max_delay
;
2429 limits
|= dev_priv
->rps
.max_delay
<< 24;
2431 /* Only set the down limit when we've reached the lowest level to avoid
2432 * getting more interrupts, otherwise leave this clear. This prevents a
2433 * race in the hw when coming out of rc6: There's a tiny window where
2434 * the hw runs at the minimal clock before selecting the desired
2435 * frequency, if the down threshold expires in that window we will not
2436 * receive a down interrupt. */
2437 if (*val
<= dev_priv
->rps
.min_delay
) {
2438 *val
= dev_priv
->rps
.min_delay
;
2439 limits
|= dev_priv
->rps
.min_delay
<< 16;
2445 void gen6_set_rps(struct drm_device
*dev
, u8 val
)
2447 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2448 u32 limits
= gen6_rps_limits(dev_priv
, &val
);
2450 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
2451 WARN_ON(val
> dev_priv
->rps
.max_delay
);
2452 WARN_ON(val
< dev_priv
->rps
.min_delay
);
2454 if (val
== dev_priv
->rps
.cur_delay
)
2457 I915_WRITE(GEN6_RPNSWREQ
,
2458 GEN6_FREQUENCY(val
) |
2460 GEN6_AGGRESSIVE_TURBO
);
2462 /* Make sure we continue to get interrupts
2463 * until we hit the minimum or maximum frequencies.
2465 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS
, limits
);
2467 POSTING_READ(GEN6_RPNSWREQ
);
2469 dev_priv
->rps
.cur_delay
= val
;
2471 trace_intel_gpu_freq_change(val
* 50);
2474 static void gen6_disable_rps(struct drm_device
*dev
)
2476 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2478 I915_WRITE(GEN6_RC_CONTROL
, 0);
2479 I915_WRITE(GEN6_RPNSWREQ
, 1 << 31);
2480 I915_WRITE(GEN6_PMINTRMSK
, 0xffffffff);
2481 I915_WRITE(GEN6_PMIER
, 0);
2482 /* Complete PM interrupt masking here doesn't race with the rps work
2483 * item again unmasking PM interrupts because that is using a different
2484 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
2485 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
2487 spin_lock_irq(&dev_priv
->rps
.lock
);
2488 dev_priv
->rps
.pm_iir
= 0;
2489 spin_unlock_irq(&dev_priv
->rps
.lock
);
2491 I915_WRITE(GEN6_PMIIR
, I915_READ(GEN6_PMIIR
));
2494 int intel_enable_rc6(const struct drm_device
*dev
)
2496 /* Respect the kernel parameter if it is set */
2497 if (i915_enable_rc6
>= 0)
2498 return i915_enable_rc6
;
2500 /* Disable RC6 on Ironlake */
2501 if (INTEL_INFO(dev
)->gen
== 5)
2504 if (IS_HASWELL(dev
)) {
2505 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
2506 return INTEL_RC6_ENABLE
;
2509 /* snb/ivb have more than one rc6 state. */
2510 if (INTEL_INFO(dev
)->gen
== 6) {
2511 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
2512 return INTEL_RC6_ENABLE
;
2515 DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n");
2516 return (INTEL_RC6_ENABLE
| INTEL_RC6p_ENABLE
);
2519 static void gen6_enable_rps(struct drm_device
*dev
)
2521 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2522 struct intel_ring_buffer
*ring
;
2525 u32 rc6vids
, pcu_mbox
, rc6_mask
= 0;
2530 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
2532 /* Here begins a magic sequence of register writes to enable
2533 * auto-downclocking.
2535 * Perhaps there might be some value in exposing these to
2538 I915_WRITE(GEN6_RC_STATE
, 0);
2540 /* Clear the DBG now so we don't confuse earlier errors */
2541 if ((gtfifodbg
= I915_READ(GTFIFODBG
))) {
2542 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg
);
2543 I915_WRITE(GTFIFODBG
, gtfifodbg
);
2546 gen6_gt_force_wake_get(dev_priv
);
2548 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
2549 gt_perf_status
= I915_READ(GEN6_GT_PERF_STATUS
);
2551 /* In units of 100MHz */
2552 dev_priv
->rps
.max_delay
= rp_state_cap
& 0xff;
2553 dev_priv
->rps
.min_delay
= (rp_state_cap
& 0xff0000) >> 16;
2554 dev_priv
->rps
.cur_delay
= 0;
2556 /* disable the counters and set deterministic thresholds */
2557 I915_WRITE(GEN6_RC_CONTROL
, 0);
2559 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT
, 1000 << 16);
2560 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 40 << 16 | 30);
2561 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT
, 30);
2562 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000);
2563 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25);
2565 for_each_ring(ring
, dev_priv
, i
)
2566 I915_WRITE(RING_MAX_IDLE(ring
->mmio_base
), 10);
2568 I915_WRITE(GEN6_RC_SLEEP
, 0);
2569 I915_WRITE(GEN6_RC1e_THRESHOLD
, 1000);
2570 I915_WRITE(GEN6_RC6_THRESHOLD
, 50000);
2571 I915_WRITE(GEN6_RC6p_THRESHOLD
, 100000);
2572 I915_WRITE(GEN6_RC6pp_THRESHOLD
, 64000); /* unused */
2574 /* Check if we are enabling RC6 */
2575 rc6_mode
= intel_enable_rc6(dev_priv
->dev
);
2576 if (rc6_mode
& INTEL_RC6_ENABLE
)
2577 rc6_mask
|= GEN6_RC_CTL_RC6_ENABLE
;
2579 /* We don't use those on Haswell */
2580 if (!IS_HASWELL(dev
)) {
2581 if (rc6_mode
& INTEL_RC6p_ENABLE
)
2582 rc6_mask
|= GEN6_RC_CTL_RC6p_ENABLE
;
2584 if (rc6_mode
& INTEL_RC6pp_ENABLE
)
2585 rc6_mask
|= GEN6_RC_CTL_RC6pp_ENABLE
;
2588 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
2589 (rc6_mask
& GEN6_RC_CTL_RC6_ENABLE
) ? "on" : "off",
2590 (rc6_mask
& GEN6_RC_CTL_RC6p_ENABLE
) ? "on" : "off",
2591 (rc6_mask
& GEN6_RC_CTL_RC6pp_ENABLE
) ? "on" : "off");
2593 I915_WRITE(GEN6_RC_CONTROL
,
2595 GEN6_RC_CTL_EI_MODE(1) |
2596 GEN6_RC_CTL_HW_ENABLE
);
2598 I915_WRITE(GEN6_RPNSWREQ
,
2599 GEN6_FREQUENCY(10) |
2601 GEN6_AGGRESSIVE_TURBO
);
2602 I915_WRITE(GEN6_RC_VIDEO_FREQ
,
2603 GEN6_FREQUENCY(12));
2605 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 1000000);
2606 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS
,
2607 dev_priv
->rps
.max_delay
<< 24 |
2608 dev_priv
->rps
.min_delay
<< 16);
2610 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 59400);
2611 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 245000);
2612 I915_WRITE(GEN6_RP_UP_EI
, 66000);
2613 I915_WRITE(GEN6_RP_DOWN_EI
, 350000);
2615 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
2616 I915_WRITE(GEN6_RP_CONTROL
,
2617 GEN6_RP_MEDIA_TURBO
|
2618 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
2619 GEN6_RP_MEDIA_IS_GFX
|
2621 GEN6_RP_UP_BUSY_AVG
|
2622 (IS_HASWELL(dev
) ? GEN7_RP_DOWN_IDLE_AVG
: GEN6_RP_DOWN_IDLE_CONT
));
2624 ret
= sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_MIN_FREQ_TABLE
, 0);
2627 ret
= sandybridge_pcode_read(dev_priv
, GEN6_READ_OC_PARAMS
, &pcu_mbox
);
2628 if (ret
&& pcu_mbox
& (1<<31)) { /* OC supported */
2629 dev_priv
->rps
.max_delay
= pcu_mbox
& 0xff;
2630 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox
* 50);
2633 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
2636 gen6_set_rps(dev_priv
->dev
, (gt_perf_status
& 0xff00) >> 8);
2638 /* requires MSI enabled */
2639 I915_WRITE(GEN6_PMIER
, GEN6_PM_DEFERRED_EVENTS
);
2640 spin_lock_irq(&dev_priv
->rps
.lock
);
2641 WARN_ON(dev_priv
->rps
.pm_iir
!= 0);
2642 I915_WRITE(GEN6_PMIMR
, 0);
2643 spin_unlock_irq(&dev_priv
->rps
.lock
);
2644 /* enable all PM interrupts */
2645 I915_WRITE(GEN6_PMINTRMSK
, 0);
2648 ret
= sandybridge_pcode_read(dev_priv
, GEN6_PCODE_READ_RC6VIDS
, &rc6vids
);
2649 if (IS_GEN6(dev
) && ret
) {
2650 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
2651 } else if (IS_GEN6(dev
) && (GEN6_DECODE_RC6_VID(rc6vids
& 0xff) < 450)) {
2652 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
2653 GEN6_DECODE_RC6_VID(rc6vids
& 0xff), 450);
2654 rc6vids
&= 0xffff00;
2655 rc6vids
|= GEN6_ENCODE_RC6_VID(450);
2656 ret
= sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_RC6VIDS
, rc6vids
);
2658 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
2661 gen6_gt_force_wake_put(dev_priv
);
2664 static void gen6_update_ring_freq(struct drm_device
*dev
)
2666 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2669 unsigned int ia_freq
, max_ia_freq
;
2670 int scaling_factor
= 180;
2672 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
2674 max_ia_freq
= cpufreq_quick_get_max(0);
2676 * Default to measured freq if none found, PCU will ensure we don't go
2680 max_ia_freq
= tsc_khz
;
2682 /* Convert from kHz to MHz */
2683 max_ia_freq
/= 1000;
2686 * For each potential GPU frequency, load a ring frequency we'd like
2687 * to use for memory access. We do this by specifying the IA frequency
2688 * the PCU should use as a reference to determine the ring frequency.
2690 for (gpu_freq
= dev_priv
->rps
.max_delay
; gpu_freq
>= dev_priv
->rps
.min_delay
;
2692 int diff
= dev_priv
->rps
.max_delay
- gpu_freq
;
2695 * For GPU frequencies less than 750MHz, just use the lowest
2698 if (gpu_freq
< min_freq
)
2701 ia_freq
= max_ia_freq
- ((diff
* scaling_factor
) / 2);
2702 ia_freq
= DIV_ROUND_CLOSEST(ia_freq
, 100);
2703 ia_freq
<<= GEN6_PCODE_FREQ_IA_RATIO_SHIFT
;
2705 sandybridge_pcode_write(dev_priv
,
2706 GEN6_PCODE_WRITE_MIN_FREQ_TABLE
,
2707 ia_freq
| gpu_freq
);
2711 void ironlake_teardown_rc6(struct drm_device
*dev
)
2713 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2715 if (dev_priv
->ips
.renderctx
) {
2716 i915_gem_object_unpin(dev_priv
->ips
.renderctx
);
2717 drm_gem_object_unreference(&dev_priv
->ips
.renderctx
->base
);
2718 dev_priv
->ips
.renderctx
= NULL
;
2721 if (dev_priv
->ips
.pwrctx
) {
2722 i915_gem_object_unpin(dev_priv
->ips
.pwrctx
);
2723 drm_gem_object_unreference(&dev_priv
->ips
.pwrctx
->base
);
2724 dev_priv
->ips
.pwrctx
= NULL
;
2728 static void ironlake_disable_rc6(struct drm_device
*dev
)
2730 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2732 if (I915_READ(PWRCTXA
)) {
2733 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
2734 I915_WRITE(RSTDBYCTL
, I915_READ(RSTDBYCTL
) | RCX_SW_EXIT
);
2735 wait_for(((I915_READ(RSTDBYCTL
) & RSX_STATUS_MASK
) == RSX_STATUS_ON
),
2738 I915_WRITE(PWRCTXA
, 0);
2739 POSTING_READ(PWRCTXA
);
2741 I915_WRITE(RSTDBYCTL
, I915_READ(RSTDBYCTL
) & ~RCX_SW_EXIT
);
2742 POSTING_READ(RSTDBYCTL
);
2746 static int ironlake_setup_rc6(struct drm_device
*dev
)
2748 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2750 if (dev_priv
->ips
.renderctx
== NULL
)
2751 dev_priv
->ips
.renderctx
= intel_alloc_context_page(dev
);
2752 if (!dev_priv
->ips
.renderctx
)
2755 if (dev_priv
->ips
.pwrctx
== NULL
)
2756 dev_priv
->ips
.pwrctx
= intel_alloc_context_page(dev
);
2757 if (!dev_priv
->ips
.pwrctx
) {
2758 ironlake_teardown_rc6(dev
);
2765 static void ironlake_enable_rc6(struct drm_device
*dev
)
2767 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2768 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
2769 bool was_interruptible
;
2772 /* rc6 disabled by default due to repeated reports of hanging during
2775 if (!intel_enable_rc6(dev
))
2778 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
2780 ret
= ironlake_setup_rc6(dev
);
2784 was_interruptible
= dev_priv
->mm
.interruptible
;
2785 dev_priv
->mm
.interruptible
= false;
2788 * GPU can automatically power down the render unit if given a page
2791 ret
= intel_ring_begin(ring
, 6);
2793 ironlake_teardown_rc6(dev
);
2794 dev_priv
->mm
.interruptible
= was_interruptible
;
2798 intel_ring_emit(ring
, MI_SUSPEND_FLUSH
| MI_SUSPEND_FLUSH_EN
);
2799 intel_ring_emit(ring
, MI_SET_CONTEXT
);
2800 intel_ring_emit(ring
, dev_priv
->ips
.renderctx
->gtt_offset
|
2802 MI_SAVE_EXT_STATE_EN
|
2803 MI_RESTORE_EXT_STATE_EN
|
2804 MI_RESTORE_INHIBIT
);
2805 intel_ring_emit(ring
, MI_SUSPEND_FLUSH
);
2806 intel_ring_emit(ring
, MI_NOOP
);
2807 intel_ring_emit(ring
, MI_FLUSH
);
2808 intel_ring_advance(ring
);
2811 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
2812 * does an implicit flush, combined with MI_FLUSH above, it should be
2813 * safe to assume that renderctx is valid
2815 ret
= intel_ring_idle(ring
);
2816 dev_priv
->mm
.interruptible
= was_interruptible
;
2818 DRM_ERROR("failed to enable ironlake power power savings\n");
2819 ironlake_teardown_rc6(dev
);
2823 I915_WRITE(PWRCTXA
, dev_priv
->ips
.pwrctx
->gtt_offset
| PWRCTX_EN
);
2824 I915_WRITE(RSTDBYCTL
, I915_READ(RSTDBYCTL
) & ~RCX_SW_EXIT
);
2827 static unsigned long intel_pxfreq(u32 vidfreq
)
2830 int div
= (vidfreq
& 0x3f0000) >> 16;
2831 int post
= (vidfreq
& 0x3000) >> 12;
2832 int pre
= (vidfreq
& 0x7);
2837 freq
= ((div
* 133333) / ((1<<post
) * pre
));
2842 static const struct cparams
{
2848 { 1, 1333, 301, 28664 },
2849 { 1, 1066, 294, 24460 },
2850 { 1, 800, 294, 25192 },
2851 { 0, 1333, 276, 27605 },
2852 { 0, 1066, 276, 27605 },
2853 { 0, 800, 231, 23784 },
2856 static unsigned long __i915_chipset_val(struct drm_i915_private
*dev_priv
)
2858 u64 total_count
, diff
, ret
;
2859 u32 count1
, count2
, count3
, m
= 0, c
= 0;
2860 unsigned long now
= jiffies_to_msecs(jiffies
), diff1
;
2863 assert_spin_locked(&mchdev_lock
);
2865 diff1
= now
- dev_priv
->ips
.last_time1
;
2867 /* Prevent division-by-zero if we are asking too fast.
2868 * Also, we don't get interesting results if we are polling
2869 * faster than once in 10ms, so just return the saved value
2873 return dev_priv
->ips
.chipset_power
;
2875 count1
= I915_READ(DMIEC
);
2876 count2
= I915_READ(DDREC
);
2877 count3
= I915_READ(CSIEC
);
2879 total_count
= count1
+ count2
+ count3
;
2881 /* FIXME: handle per-counter overflow */
2882 if (total_count
< dev_priv
->ips
.last_count1
) {
2883 diff
= ~0UL - dev_priv
->ips
.last_count1
;
2884 diff
+= total_count
;
2886 diff
= total_count
- dev_priv
->ips
.last_count1
;
2889 for (i
= 0; i
< ARRAY_SIZE(cparams
); i
++) {
2890 if (cparams
[i
].i
== dev_priv
->ips
.c_m
&&
2891 cparams
[i
].t
== dev_priv
->ips
.r_t
) {
2898 diff
= div_u64(diff
, diff1
);
2899 ret
= ((m
* diff
) + c
);
2900 ret
= div_u64(ret
, 10);
2902 dev_priv
->ips
.last_count1
= total_count
;
2903 dev_priv
->ips
.last_time1
= now
;
2905 dev_priv
->ips
.chipset_power
= ret
;
2910 unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
)
2914 if (dev_priv
->info
->gen
!= 5)
2917 spin_lock_irq(&mchdev_lock
);
2919 val
= __i915_chipset_val(dev_priv
);
2921 spin_unlock_irq(&mchdev_lock
);
2926 unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
)
2928 unsigned long m
, x
, b
;
2931 tsfs
= I915_READ(TSFS
);
2933 m
= ((tsfs
& TSFS_SLOPE_MASK
) >> TSFS_SLOPE_SHIFT
);
2934 x
= I915_READ8(TR1
);
2936 b
= tsfs
& TSFS_INTR_MASK
;
2938 return ((m
* x
) / 127) - b
;
2941 static u16
pvid_to_extvid(struct drm_i915_private
*dev_priv
, u8 pxvid
)
2943 static const struct v_table
{
2944 u16 vd
; /* in .1 mil */
2945 u16 vm
; /* in .1 mil */
3076 if (dev_priv
->info
->is_mobile
)
3077 return v_table
[pxvid
].vm
;
3079 return v_table
[pxvid
].vd
;
3082 static void __i915_update_gfx_val(struct drm_i915_private
*dev_priv
)
3084 struct timespec now
, diff1
;
3086 unsigned long diffms
;
3089 assert_spin_locked(&mchdev_lock
);
3091 getrawmonotonic(&now
);
3092 diff1
= timespec_sub(now
, dev_priv
->ips
.last_time2
);
3094 /* Don't divide by 0 */
3095 diffms
= diff1
.tv_sec
* 1000 + diff1
.tv_nsec
/ 1000000;
3099 count
= I915_READ(GFXEC
);
3101 if (count
< dev_priv
->ips
.last_count2
) {
3102 diff
= ~0UL - dev_priv
->ips
.last_count2
;
3105 diff
= count
- dev_priv
->ips
.last_count2
;
3108 dev_priv
->ips
.last_count2
= count
;
3109 dev_priv
->ips
.last_time2
= now
;
3111 /* More magic constants... */
3113 diff
= div_u64(diff
, diffms
* 10);
3114 dev_priv
->ips
.gfx_power
= diff
;
3117 void i915_update_gfx_val(struct drm_i915_private
*dev_priv
)
3119 if (dev_priv
->info
->gen
!= 5)
3122 spin_lock_irq(&mchdev_lock
);
3124 __i915_update_gfx_val(dev_priv
);
3126 spin_unlock_irq(&mchdev_lock
);
3129 static unsigned long __i915_gfx_val(struct drm_i915_private
*dev_priv
)
3131 unsigned long t
, corr
, state1
, corr2
, state2
;
3134 assert_spin_locked(&mchdev_lock
);
3136 pxvid
= I915_READ(PXVFREQ_BASE
+ (dev_priv
->rps
.cur_delay
* 4));
3137 pxvid
= (pxvid
>> 24) & 0x7f;
3138 ext_v
= pvid_to_extvid(dev_priv
, pxvid
);
3142 t
= i915_mch_val(dev_priv
);
3144 /* Revel in the empirically derived constants */
3146 /* Correction factor in 1/100000 units */
3148 corr
= ((t
* 2349) + 135940);
3150 corr
= ((t
* 964) + 29317);
3152 corr
= ((t
* 301) + 1004);
3154 corr
= corr
* ((150142 * state1
) / 10000 - 78642);
3156 corr2
= (corr
* dev_priv
->ips
.corr
);
3158 state2
= (corr2
* state1
) / 10000;
3159 state2
/= 100; /* convert to mW */
3161 __i915_update_gfx_val(dev_priv
);
3163 return dev_priv
->ips
.gfx_power
+ state2
;
3166 unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
)
3170 if (dev_priv
->info
->gen
!= 5)
3173 spin_lock_irq(&mchdev_lock
);
3175 val
= __i915_gfx_val(dev_priv
);
3177 spin_unlock_irq(&mchdev_lock
);
3183 * i915_read_mch_val - return value for IPS use
3185 * Calculate and return a value for the IPS driver to use when deciding whether
3186 * we have thermal and power headroom to increase CPU or GPU power budget.
3188 unsigned long i915_read_mch_val(void)
3190 struct drm_i915_private
*dev_priv
;
3191 unsigned long chipset_val
, graphics_val
, ret
= 0;
3193 spin_lock_irq(&mchdev_lock
);
3196 dev_priv
= i915_mch_dev
;
3198 chipset_val
= __i915_chipset_val(dev_priv
);
3199 graphics_val
= __i915_gfx_val(dev_priv
);
3201 ret
= chipset_val
+ graphics_val
;
3204 spin_unlock_irq(&mchdev_lock
);
3208 EXPORT_SYMBOL_GPL(i915_read_mch_val
);
3211 * i915_gpu_raise - raise GPU frequency limit
3213 * Raise the limit; IPS indicates we have thermal headroom.
3215 bool i915_gpu_raise(void)
3217 struct drm_i915_private
*dev_priv
;
3220 spin_lock_irq(&mchdev_lock
);
3221 if (!i915_mch_dev
) {
3225 dev_priv
= i915_mch_dev
;
3227 if (dev_priv
->ips
.max_delay
> dev_priv
->ips
.fmax
)
3228 dev_priv
->ips
.max_delay
--;
3231 spin_unlock_irq(&mchdev_lock
);
3235 EXPORT_SYMBOL_GPL(i915_gpu_raise
);
3238 * i915_gpu_lower - lower GPU frequency limit
3240 * IPS indicates we're close to a thermal limit, so throttle back the GPU
3241 * frequency maximum.
3243 bool i915_gpu_lower(void)
3245 struct drm_i915_private
*dev_priv
;
3248 spin_lock_irq(&mchdev_lock
);
3249 if (!i915_mch_dev
) {
3253 dev_priv
= i915_mch_dev
;
3255 if (dev_priv
->ips
.max_delay
< dev_priv
->ips
.min_delay
)
3256 dev_priv
->ips
.max_delay
++;
3259 spin_unlock_irq(&mchdev_lock
);
3263 EXPORT_SYMBOL_GPL(i915_gpu_lower
);
3266 * i915_gpu_busy - indicate GPU business to IPS
3268 * Tell the IPS driver whether or not the GPU is busy.
3270 bool i915_gpu_busy(void)
3272 struct drm_i915_private
*dev_priv
;
3273 struct intel_ring_buffer
*ring
;
3277 spin_lock_irq(&mchdev_lock
);
3280 dev_priv
= i915_mch_dev
;
3282 for_each_ring(ring
, dev_priv
, i
)
3283 ret
|= !list_empty(&ring
->request_list
);
3286 spin_unlock_irq(&mchdev_lock
);
3290 EXPORT_SYMBOL_GPL(i915_gpu_busy
);
3293 * i915_gpu_turbo_disable - disable graphics turbo
3295 * Disable graphics turbo by resetting the max frequency and setting the
3296 * current frequency to the default.
3298 bool i915_gpu_turbo_disable(void)
3300 struct drm_i915_private
*dev_priv
;
3303 spin_lock_irq(&mchdev_lock
);
3304 if (!i915_mch_dev
) {
3308 dev_priv
= i915_mch_dev
;
3310 dev_priv
->ips
.max_delay
= dev_priv
->ips
.fstart
;
3312 if (!ironlake_set_drps(dev_priv
->dev
, dev_priv
->ips
.fstart
))
3316 spin_unlock_irq(&mchdev_lock
);
3320 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable
);
3323 * Tells the intel_ips driver that the i915 driver is now loaded, if
3324 * IPS got loaded first.
3326 * This awkward dance is so that neither module has to depend on the
3327 * other in order for IPS to do the appropriate communication of
3328 * GPU turbo limits to i915.
3331 ips_ping_for_i915_load(void)
3335 link
= symbol_get(ips_link_to_i915_driver
);
3338 symbol_put(ips_link_to_i915_driver
);
3342 void intel_gpu_ips_init(struct drm_i915_private
*dev_priv
)
3344 /* We only register the i915 ips part with intel-ips once everything is
3345 * set up, to avoid intel-ips sneaking in and reading bogus values. */
3346 spin_lock_irq(&mchdev_lock
);
3347 i915_mch_dev
= dev_priv
;
3348 spin_unlock_irq(&mchdev_lock
);
3350 ips_ping_for_i915_load();
3353 void intel_gpu_ips_teardown(void)
3355 spin_lock_irq(&mchdev_lock
);
3356 i915_mch_dev
= NULL
;
3357 spin_unlock_irq(&mchdev_lock
);
3359 static void intel_init_emon(struct drm_device
*dev
)
3361 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3366 /* Disable to program */
3370 /* Program energy weights for various events */
3371 I915_WRITE(SDEW
, 0x15040d00);
3372 I915_WRITE(CSIEW0
, 0x007f0000);
3373 I915_WRITE(CSIEW1
, 0x1e220004);
3374 I915_WRITE(CSIEW2
, 0x04000004);
3376 for (i
= 0; i
< 5; i
++)
3377 I915_WRITE(PEW
+ (i
* 4), 0);
3378 for (i
= 0; i
< 3; i
++)
3379 I915_WRITE(DEW
+ (i
* 4), 0);
3381 /* Program P-state weights to account for frequency power adjustment */
3382 for (i
= 0; i
< 16; i
++) {
3383 u32 pxvidfreq
= I915_READ(PXVFREQ_BASE
+ (i
* 4));
3384 unsigned long freq
= intel_pxfreq(pxvidfreq
);
3385 unsigned long vid
= (pxvidfreq
& PXVFREQ_PX_MASK
) >>
3390 val
*= (freq
/ 1000);
3392 val
/= (127*127*900);
3394 DRM_ERROR("bad pxval: %ld\n", val
);
3397 /* Render standby states get 0 weight */
3401 for (i
= 0; i
< 4; i
++) {
3402 u32 val
= (pxw
[i
*4] << 24) | (pxw
[(i
*4)+1] << 16) |
3403 (pxw
[(i
*4)+2] << 8) | (pxw
[(i
*4)+3]);
3404 I915_WRITE(PXW
+ (i
* 4), val
);
3407 /* Adjust magic regs to magic values (more experimental results) */
3408 I915_WRITE(OGW0
, 0);
3409 I915_WRITE(OGW1
, 0);
3410 I915_WRITE(EG0
, 0x00007f00);
3411 I915_WRITE(EG1
, 0x0000000e);
3412 I915_WRITE(EG2
, 0x000e0000);
3413 I915_WRITE(EG3
, 0x68000300);
3414 I915_WRITE(EG4
, 0x42000000);
3415 I915_WRITE(EG5
, 0x00140031);
3419 for (i
= 0; i
< 8; i
++)
3420 I915_WRITE(PXWL
+ (i
* 4), 0);
3422 /* Enable PMON + select events */
3423 I915_WRITE(ECR
, 0x80000019);
3425 lcfuse
= I915_READ(LCFUSE02
);
3427 dev_priv
->ips
.corr
= (lcfuse
& LCFUSE_HIV_MASK
);
3430 void intel_disable_gt_powersave(struct drm_device
*dev
)
3432 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3434 if (IS_IRONLAKE_M(dev
)) {
3435 ironlake_disable_drps(dev
);
3436 ironlake_disable_rc6(dev
);
3437 } else if (INTEL_INFO(dev
)->gen
>= 6 && !IS_VALLEYVIEW(dev
)) {
3438 cancel_delayed_work_sync(&dev_priv
->rps
.delayed_resume_work
);
3439 mutex_lock(&dev_priv
->rps
.hw_lock
);
3440 gen6_disable_rps(dev
);
3441 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3445 static void intel_gen6_powersave_work(struct work_struct
*work
)
3447 struct drm_i915_private
*dev_priv
=
3448 container_of(work
, struct drm_i915_private
,
3449 rps
.delayed_resume_work
.work
);
3450 struct drm_device
*dev
= dev_priv
->dev
;
3452 mutex_lock(&dev_priv
->rps
.hw_lock
);
3453 gen6_enable_rps(dev
);
3454 gen6_update_ring_freq(dev
);
3455 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3458 void intel_enable_gt_powersave(struct drm_device
*dev
)
3460 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3462 if (IS_IRONLAKE_M(dev
)) {
3463 ironlake_enable_drps(dev
);
3464 ironlake_enable_rc6(dev
);
3465 intel_init_emon(dev
);
3466 } else if ((IS_GEN6(dev
) || IS_GEN7(dev
)) && !IS_VALLEYVIEW(dev
)) {
3468 * PCU communication is slow and this doesn't need to be
3469 * done at any specific time, so do this out of our fast path
3470 * to make resume and init faster.
3472 schedule_delayed_work(&dev_priv
->rps
.delayed_resume_work
,
3473 round_jiffies_up_relative(HZ
));
3477 static void ibx_init_clock_gating(struct drm_device
*dev
)
3479 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3482 * On Ibex Peak and Cougar Point, we need to disable clock
3483 * gating for the panel power sequencer or it will fail to
3484 * start up when no ports are active.
3486 I915_WRITE(SOUTH_DSPCLK_GATE_D
, PCH_DPLSUNIT_CLOCK_GATE_DISABLE
);
3489 static void ironlake_init_clock_gating(struct drm_device
*dev
)
3491 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3492 uint32_t dspclk_gate
= ILK_VRHUNIT_CLOCK_GATE_DISABLE
;
3494 /* Required for FBC */
3495 dspclk_gate
|= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE
|
3496 ILK_DPFCUNIT_CLOCK_GATE_DISABLE
|
3497 ILK_DPFDUNIT_CLOCK_GATE_ENABLE
;
3499 I915_WRITE(PCH_3DCGDIS0
,
3500 MARIUNIT_CLOCK_GATE_DISABLE
|
3501 SVSMUNIT_CLOCK_GATE_DISABLE
);
3502 I915_WRITE(PCH_3DCGDIS1
,
3503 VFMUNIT_CLOCK_GATE_DISABLE
);
3506 * According to the spec the following bits should be set in
3507 * order to enable memory self-refresh
3508 * The bit 22/21 of 0x42004
3509 * The bit 5 of 0x42020
3510 * The bit 15 of 0x45000
3512 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
3513 (I915_READ(ILK_DISPLAY_CHICKEN2
) |
3514 ILK_DPARB_GATE
| ILK_VSDPFD_FULL
));
3515 dspclk_gate
|= ILK_DPARBUNIT_CLOCK_GATE_ENABLE
;
3516 I915_WRITE(DISP_ARB_CTL
,
3517 (I915_READ(DISP_ARB_CTL
) |
3519 I915_WRITE(WM3_LP_ILK
, 0);
3520 I915_WRITE(WM2_LP_ILK
, 0);
3521 I915_WRITE(WM1_LP_ILK
, 0);
3524 * Based on the document from hardware guys the following bits
3525 * should be set unconditionally in order to enable FBC.
3526 * The bit 22 of 0x42000
3527 * The bit 22 of 0x42004
3528 * The bit 7,8,9 of 0x42020.
3530 if (IS_IRONLAKE_M(dev
)) {
3531 I915_WRITE(ILK_DISPLAY_CHICKEN1
,
3532 I915_READ(ILK_DISPLAY_CHICKEN1
) |
3534 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
3535 I915_READ(ILK_DISPLAY_CHICKEN2
) |
3539 I915_WRITE(ILK_DSPCLK_GATE_D
, dspclk_gate
);
3541 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
3542 I915_READ(ILK_DISPLAY_CHICKEN2
) |
3543 ILK_ELPIN_409_SELECT
);
3544 I915_WRITE(_3D_CHICKEN2
,
3545 _3D_CHICKEN2_WM_READ_PIPELINED
<< 16 |
3546 _3D_CHICKEN2_WM_READ_PIPELINED
);
3548 /* WaDisableRenderCachePipelinedFlush */
3549 I915_WRITE(CACHE_MODE_0
,
3550 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE
));
3552 ibx_init_clock_gating(dev
);
3555 static void cpt_init_clock_gating(struct drm_device
*dev
)
3557 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3561 * On Ibex Peak and Cougar Point, we need to disable clock
3562 * gating for the panel power sequencer or it will fail to
3563 * start up when no ports are active.
3565 I915_WRITE(SOUTH_DSPCLK_GATE_D
, PCH_DPLSUNIT_CLOCK_GATE_DISABLE
);
3566 I915_WRITE(SOUTH_CHICKEN2
, I915_READ(SOUTH_CHICKEN2
) |
3567 DPLS_EDP_PPS_FIX_DIS
);
3568 /* The below fixes the weird display corruption, a few pixels shifted
3569 * downward, on (only) LVDS of some HP laptops with IVY.
3572 I915_WRITE(TRANS_CHICKEN2(pipe
), TRANS_CHICKEN2_TIMING_OVERRIDE
);
3573 /* WADP0ClockGatingDisable */
3574 for_each_pipe(pipe
) {
3575 I915_WRITE(TRANS_CHICKEN1(pipe
),
3576 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE
);
3580 static void gen6_init_clock_gating(struct drm_device
*dev
)
3582 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3584 uint32_t dspclk_gate
= ILK_VRHUNIT_CLOCK_GATE_DISABLE
;
3586 I915_WRITE(ILK_DSPCLK_GATE_D
, dspclk_gate
);
3588 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
3589 I915_READ(ILK_DISPLAY_CHICKEN2
) |
3590 ILK_ELPIN_409_SELECT
);
3592 /* WaDisableHiZPlanesWhenMSAAEnabled */
3593 I915_WRITE(_3D_CHICKEN
,
3594 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB
));
3596 /* WaSetupGtModeTdRowDispatch */
3597 if (IS_SNB_GT1(dev
))
3598 I915_WRITE(GEN6_GT_MODE
,
3599 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE
));
3601 I915_WRITE(WM3_LP_ILK
, 0);
3602 I915_WRITE(WM2_LP_ILK
, 0);
3603 I915_WRITE(WM1_LP_ILK
, 0);
3605 I915_WRITE(CACHE_MODE_0
,
3606 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB
));
3608 I915_WRITE(GEN6_UCGCTL1
,
3609 I915_READ(GEN6_UCGCTL1
) |
3610 GEN6_BLBUNIT_CLOCK_GATE_DISABLE
|
3611 GEN6_CSUNIT_CLOCK_GATE_DISABLE
);
3613 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
3614 * gating disable must be set. Failure to set it results in
3615 * flickering pixels due to Z write ordering failures after
3616 * some amount of runtime in the Mesa "fire" demo, and Unigine
3617 * Sanctuary and Tropics, and apparently anything else with
3618 * alpha test or pixel discard.
3620 * According to the spec, bit 11 (RCCUNIT) must also be set,
3621 * but we didn't debug actual testcases to find it out.
3623 * Also apply WaDisableVDSUnitClockGating and
3624 * WaDisableRCPBUnitClockGating.
3626 I915_WRITE(GEN6_UCGCTL2
,
3627 GEN7_VDSUNIT_CLOCK_GATE_DISABLE
|
3628 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE
|
3629 GEN6_RCCUNIT_CLOCK_GATE_DISABLE
);
3631 /* Bspec says we need to always set all mask bits. */
3632 I915_WRITE(_3D_CHICKEN3
, (0xFFFF << 16) |
3633 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL
);
3636 * According to the spec the following bits should be
3637 * set in order to enable memory self-refresh and fbc:
3638 * The bit21 and bit22 of 0x42000
3639 * The bit21 and bit22 of 0x42004
3640 * The bit5 and bit7 of 0x42020
3641 * The bit14 of 0x70180
3642 * The bit14 of 0x71180
3644 I915_WRITE(ILK_DISPLAY_CHICKEN1
,
3645 I915_READ(ILK_DISPLAY_CHICKEN1
) |
3646 ILK_FBCQ_DIS
| ILK_PABSTRETCH_DIS
);
3647 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
3648 I915_READ(ILK_DISPLAY_CHICKEN2
) |
3649 ILK_DPARB_GATE
| ILK_VSDPFD_FULL
);
3650 I915_WRITE(ILK_DSPCLK_GATE_D
,
3651 I915_READ(ILK_DSPCLK_GATE_D
) |
3652 ILK_DPARBUNIT_CLOCK_GATE_ENABLE
|
3653 ILK_DPFDUNIT_CLOCK_GATE_ENABLE
);
3655 /* WaMbcDriverBootEnable */
3656 I915_WRITE(GEN6_MBCTL
, I915_READ(GEN6_MBCTL
) |
3657 GEN6_MBCTL_ENABLE_BOOT_FETCH
);
3659 for_each_pipe(pipe
) {
3660 I915_WRITE(DSPCNTR(pipe
),
3661 I915_READ(DSPCNTR(pipe
)) |
3662 DISPPLANE_TRICKLE_FEED_DISABLE
);
3663 intel_flush_display_plane(dev_priv
, pipe
);
3666 /* The default value should be 0x200 according to docs, but the two
3667 * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
3668 I915_WRITE(GEN6_GT_MODE
, _MASKED_BIT_DISABLE(0xffff));
3669 I915_WRITE(GEN6_GT_MODE
, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI
));
3671 cpt_init_clock_gating(dev
);
3674 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private
*dev_priv
)
3676 uint32_t reg
= I915_READ(GEN7_FF_THREAD_MODE
);
3678 reg
&= ~GEN7_FF_SCHED_MASK
;
3679 reg
|= GEN7_FF_TS_SCHED_HW
;
3680 reg
|= GEN7_FF_VS_SCHED_HW
;
3681 reg
|= GEN7_FF_DS_SCHED_HW
;
3683 /* WaVSRefCountFullforceMissDisable */
3684 if (IS_HASWELL(dev_priv
->dev
))
3685 reg
&= ~GEN7_FF_VS_REF_CNT_FFME
;
3687 I915_WRITE(GEN7_FF_THREAD_MODE
, reg
);
3690 static void lpt_init_clock_gating(struct drm_device
*dev
)
3692 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3695 * TODO: this bit should only be enabled when really needed, then
3696 * disabled when not needed anymore in order to save power.
3698 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
)
3699 I915_WRITE(SOUTH_DSPCLK_GATE_D
,
3700 I915_READ(SOUTH_DSPCLK_GATE_D
) |
3701 PCH_LP_PARTITION_LEVEL_DISABLE
);
3704 static void haswell_init_clock_gating(struct drm_device
*dev
)
3706 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3709 I915_WRITE(WM3_LP_ILK
, 0);
3710 I915_WRITE(WM2_LP_ILK
, 0);
3711 I915_WRITE(WM1_LP_ILK
, 0);
3713 /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
3714 * This implements the WaDisableRCZUnitClockGating workaround.
3716 I915_WRITE(GEN6_UCGCTL2
, GEN6_RCZUNIT_CLOCK_GATE_DISABLE
);
3718 /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
3719 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1
,
3720 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC
);
3722 /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
3723 I915_WRITE(GEN7_L3CNTLREG1
,
3724 GEN7_WA_FOR_GEN7_L3_CONTROL
);
3725 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER
,
3726 GEN7_WA_L3_CHICKEN_MODE
);
3728 /* This is required by WaCatErrorRejectionIssue */
3729 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
3730 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
3731 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
3733 for_each_pipe(pipe
) {
3734 I915_WRITE(DSPCNTR(pipe
),
3735 I915_READ(DSPCNTR(pipe
)) |
3736 DISPPLANE_TRICKLE_FEED_DISABLE
);
3737 intel_flush_display_plane(dev_priv
, pipe
);
3740 gen7_setup_fixed_func_scheduler(dev_priv
);
3742 /* WaDisable4x2SubspanOptimization */
3743 I915_WRITE(CACHE_MODE_1
,
3744 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
));
3746 /* WaMbcDriverBootEnable */
3747 I915_WRITE(GEN6_MBCTL
, I915_READ(GEN6_MBCTL
) |
3748 GEN6_MBCTL_ENABLE_BOOT_FETCH
);
3750 /* XXX: This is a workaround for early silicon revisions and should be
3755 WM_DBG_DISALLOW_MULTIPLE_LP
|
3756 WM_DBG_DISALLOW_SPRITE
|
3757 WM_DBG_DISALLOW_MAXFIFO
);
3759 lpt_init_clock_gating(dev
);
3762 static void ivybridge_init_clock_gating(struct drm_device
*dev
)
3764 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3768 I915_WRITE(WM3_LP_ILK
, 0);
3769 I915_WRITE(WM2_LP_ILK
, 0);
3770 I915_WRITE(WM1_LP_ILK
, 0);
3772 I915_WRITE(ILK_DSPCLK_GATE_D
, ILK_VRHUNIT_CLOCK_GATE_DISABLE
);
3774 /* WaDisableEarlyCull */
3775 I915_WRITE(_3D_CHICKEN3
,
3776 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL
));
3778 /* WaDisableBackToBackFlipFix */
3779 I915_WRITE(IVB_CHICKEN3
,
3780 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE
|
3781 CHICKEN3_DGMG_DONE_FIX_DISABLE
);
3783 /* WaDisablePSDDualDispatchEnable */
3784 if (IS_IVB_GT1(dev
))
3785 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1
,
3786 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE
));
3788 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2
,
3789 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE
));
3791 /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
3792 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1
,
3793 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC
);
3795 /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
3796 I915_WRITE(GEN7_L3CNTLREG1
,
3797 GEN7_WA_FOR_GEN7_L3_CONTROL
);
3798 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER
,
3799 GEN7_WA_L3_CHICKEN_MODE
);
3800 if (IS_IVB_GT1(dev
))
3801 I915_WRITE(GEN7_ROW_CHICKEN2
,
3802 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
3804 I915_WRITE(GEN7_ROW_CHICKEN2_GT2
,
3805 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
3808 /* WaForceL3Serialization */
3809 I915_WRITE(GEN7_L3SQCREG4
, I915_READ(GEN7_L3SQCREG4
) &
3810 ~L3SQ_URB_READ_CAM_MATCH_DISABLE
);
3812 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
3813 * gating disable must be set. Failure to set it results in
3814 * flickering pixels due to Z write ordering failures after
3815 * some amount of runtime in the Mesa "fire" demo, and Unigine
3816 * Sanctuary and Tropics, and apparently anything else with
3817 * alpha test or pixel discard.
3819 * According to the spec, bit 11 (RCCUNIT) must also be set,
3820 * but we didn't debug actual testcases to find it out.
3822 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
3823 * This implements the WaDisableRCZUnitClockGating workaround.
3825 I915_WRITE(GEN6_UCGCTL2
,
3826 GEN6_RCZUNIT_CLOCK_GATE_DISABLE
|
3827 GEN6_RCCUNIT_CLOCK_GATE_DISABLE
);
3829 /* This is required by WaCatErrorRejectionIssue */
3830 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
3831 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
3832 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
3834 for_each_pipe(pipe
) {
3835 I915_WRITE(DSPCNTR(pipe
),
3836 I915_READ(DSPCNTR(pipe
)) |
3837 DISPPLANE_TRICKLE_FEED_DISABLE
);
3838 intel_flush_display_plane(dev_priv
, pipe
);
3841 /* WaMbcDriverBootEnable */
3842 I915_WRITE(GEN6_MBCTL
, I915_READ(GEN6_MBCTL
) |
3843 GEN6_MBCTL_ENABLE_BOOT_FETCH
);
3845 gen7_setup_fixed_func_scheduler(dev_priv
);
3847 /* WaDisable4x2SubspanOptimization */
3848 I915_WRITE(CACHE_MODE_1
,
3849 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
));
3851 snpcr
= I915_READ(GEN6_MBCUNIT_SNPCR
);
3852 snpcr
&= ~GEN6_MBC_SNPCR_MASK
;
3853 snpcr
|= GEN6_MBC_SNPCR_MED
;
3854 I915_WRITE(GEN6_MBCUNIT_SNPCR
, snpcr
);
3856 cpt_init_clock_gating(dev
);
3859 static void valleyview_init_clock_gating(struct drm_device
*dev
)
3861 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3864 I915_WRITE(WM3_LP_ILK
, 0);
3865 I915_WRITE(WM2_LP_ILK
, 0);
3866 I915_WRITE(WM1_LP_ILK
, 0);
3868 I915_WRITE(ILK_DSPCLK_GATE_D
, ILK_VRHUNIT_CLOCK_GATE_DISABLE
);
3870 /* WaDisableEarlyCull */
3871 I915_WRITE(_3D_CHICKEN3
,
3872 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL
));
3874 /* WaDisableBackToBackFlipFix */
3875 I915_WRITE(IVB_CHICKEN3
,
3876 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE
|
3877 CHICKEN3_DGMG_DONE_FIX_DISABLE
);
3879 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1
,
3880 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE
));
3882 /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
3883 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1
,
3884 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC
);
3886 /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
3887 I915_WRITE(GEN7_L3CNTLREG1
, I915_READ(GEN7_L3CNTLREG1
) | GEN7_L3AGDIS
);
3888 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER
, GEN7_WA_L3_CHICKEN_MODE
);
3890 /* WaForceL3Serialization */
3891 I915_WRITE(GEN7_L3SQCREG4
, I915_READ(GEN7_L3SQCREG4
) &
3892 ~L3SQ_URB_READ_CAM_MATCH_DISABLE
);
3894 /* WaDisableDopClockGating */
3895 I915_WRITE(GEN7_ROW_CHICKEN2
,
3896 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
3898 /* WaForceL3Serialization */
3899 I915_WRITE(GEN7_L3SQCREG4
, I915_READ(GEN7_L3SQCREG4
) &
3900 ~L3SQ_URB_READ_CAM_MATCH_DISABLE
);
3902 /* This is required by WaCatErrorRejectionIssue */
3903 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
3904 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
3905 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
3907 /* WaMbcDriverBootEnable */
3908 I915_WRITE(GEN6_MBCTL
, I915_READ(GEN6_MBCTL
) |
3909 GEN6_MBCTL_ENABLE_BOOT_FETCH
);
3912 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
3913 * gating disable must be set. Failure to set it results in
3914 * flickering pixels due to Z write ordering failures after
3915 * some amount of runtime in the Mesa "fire" demo, and Unigine
3916 * Sanctuary and Tropics, and apparently anything else with
3917 * alpha test or pixel discard.
3919 * According to the spec, bit 11 (RCCUNIT) must also be set,
3920 * but we didn't debug actual testcases to find it out.
3922 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
3923 * This implements the WaDisableRCZUnitClockGating workaround.
3925 * Also apply WaDisableVDSUnitClockGating and
3926 * WaDisableRCPBUnitClockGating.
3928 I915_WRITE(GEN6_UCGCTL2
,
3929 GEN7_VDSUNIT_CLOCK_GATE_DISABLE
|
3930 GEN7_TDLUNIT_CLOCK_GATE_DISABLE
|
3931 GEN6_RCZUNIT_CLOCK_GATE_DISABLE
|
3932 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE
|
3933 GEN6_RCCUNIT_CLOCK_GATE_DISABLE
);
3935 I915_WRITE(GEN7_UCGCTL4
, GEN7_L3BANK2X_CLOCK_GATE_DISABLE
);
3937 for_each_pipe(pipe
) {
3938 I915_WRITE(DSPCNTR(pipe
),
3939 I915_READ(DSPCNTR(pipe
)) |
3940 DISPPLANE_TRICKLE_FEED_DISABLE
);
3941 intel_flush_display_plane(dev_priv
, pipe
);
3944 I915_WRITE(CACHE_MODE_1
,
3945 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
));
3948 * On ValleyView, the GUnit needs to signal the GT
3949 * when flip and other events complete. So enable
3950 * all the GUnit->GT interrupts here
3952 I915_WRITE(VLV_DPFLIPSTAT
, PIPEB_LINE_COMPARE_INT_EN
|
3953 PIPEB_HLINE_INT_EN
| PIPEB_VBLANK_INT_EN
|
3954 SPRITED_FLIPDONE_INT_EN
| SPRITEC_FLIPDONE_INT_EN
|
3955 PLANEB_FLIPDONE_INT_EN
| PIPEA_LINE_COMPARE_INT_EN
|
3956 PIPEA_HLINE_INT_EN
| PIPEA_VBLANK_INT_EN
|
3957 SPRITEB_FLIPDONE_INT_EN
| SPRITEA_FLIPDONE_INT_EN
|
3958 PLANEA_FLIPDONE_INT_EN
);
3961 * WaDisableVLVClockGating_VBIIssue
3962 * Disable clock gating on th GCFG unit to prevent a delay
3963 * in the reporting of vblank events.
3965 I915_WRITE(VLV_GUNIT_CLOCK_GATE
, GCFG_DIS
);
3968 static void g4x_init_clock_gating(struct drm_device
*dev
)
3970 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3971 uint32_t dspclk_gate
;
3973 I915_WRITE(RENCLK_GATE_D1
, 0);
3974 I915_WRITE(RENCLK_GATE_D2
, VF_UNIT_CLOCK_GATE_DISABLE
|
3975 GS_UNIT_CLOCK_GATE_DISABLE
|
3976 CL_UNIT_CLOCK_GATE_DISABLE
);
3977 I915_WRITE(RAMCLK_GATE_D
, 0);
3978 dspclk_gate
= VRHUNIT_CLOCK_GATE_DISABLE
|
3979 OVRUNIT_CLOCK_GATE_DISABLE
|
3980 OVCUNIT_CLOCK_GATE_DISABLE
;
3982 dspclk_gate
|= DSSUNIT_CLOCK_GATE_DISABLE
;
3983 I915_WRITE(DSPCLK_GATE_D
, dspclk_gate
);
3985 /* WaDisableRenderCachePipelinedFlush */
3986 I915_WRITE(CACHE_MODE_0
,
3987 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE
));
3990 static void crestline_init_clock_gating(struct drm_device
*dev
)
3992 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3994 I915_WRITE(RENCLK_GATE_D1
, I965_RCC_CLOCK_GATE_DISABLE
);
3995 I915_WRITE(RENCLK_GATE_D2
, 0);
3996 I915_WRITE(DSPCLK_GATE_D
, 0);
3997 I915_WRITE(RAMCLK_GATE_D
, 0);
3998 I915_WRITE16(DEUC
, 0);
4001 static void broadwater_init_clock_gating(struct drm_device
*dev
)
4003 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4005 I915_WRITE(RENCLK_GATE_D1
, I965_RCZ_CLOCK_GATE_DISABLE
|
4006 I965_RCC_CLOCK_GATE_DISABLE
|
4007 I965_RCPB_CLOCK_GATE_DISABLE
|
4008 I965_ISC_CLOCK_GATE_DISABLE
|
4009 I965_FBC_CLOCK_GATE_DISABLE
);
4010 I915_WRITE(RENCLK_GATE_D2
, 0);
4013 static void gen3_init_clock_gating(struct drm_device
*dev
)
4015 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4016 u32 dstate
= I915_READ(D_STATE
);
4018 dstate
|= DSTATE_PLL_D3_OFF
| DSTATE_GFX_CLOCK_GATING
|
4019 DSTATE_DOT_CLOCK_GATING
;
4020 I915_WRITE(D_STATE
, dstate
);
4022 if (IS_PINEVIEW(dev
))
4023 I915_WRITE(ECOSKPD
, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY
));
4025 /* IIR "flip pending" means done if this bit is set */
4026 I915_WRITE(ECOSKPD
, _MASKED_BIT_DISABLE(ECO_FLIP_DONE
));
4029 static void i85x_init_clock_gating(struct drm_device
*dev
)
4031 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4033 I915_WRITE(RENCLK_GATE_D1
, SV_CLOCK_GATE_DISABLE
);
4036 static void i830_init_clock_gating(struct drm_device
*dev
)
4038 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4040 I915_WRITE(DSPCLK_GATE_D
, OVRUNIT_CLOCK_GATE_DISABLE
);
4043 void intel_init_clock_gating(struct drm_device
*dev
)
4045 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4047 dev_priv
->display
.init_clock_gating(dev
);
4050 void intel_set_power_well(struct drm_device
*dev
, bool enable
)
4052 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4053 bool is_enabled
, enable_requested
;
4056 if (!IS_HASWELL(dev
))
4059 tmp
= I915_READ(HSW_PWR_WELL_DRIVER
);
4060 is_enabled
= tmp
& HSW_PWR_WELL_STATE
;
4061 enable_requested
= tmp
& HSW_PWR_WELL_ENABLE
;
4064 if (!enable_requested
)
4065 I915_WRITE(HSW_PWR_WELL_DRIVER
, HSW_PWR_WELL_ENABLE
);
4068 DRM_DEBUG_KMS("Enabling power well\n");
4069 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER
) &
4070 HSW_PWR_WELL_STATE
), 20))
4071 DRM_ERROR("Timeout enabling power well\n");
4074 if (enable_requested
) {
4075 I915_WRITE(HSW_PWR_WELL_DRIVER
, 0);
4076 DRM_DEBUG_KMS("Requesting to disable the power well\n");
4082 * Starting with Haswell, we have a "Power Down Well" that can be turned off
4083 * when not needed anymore. We have 4 registers that can request the power well
4084 * to be enabled, and it will only be disabled if none of the registers is
4085 * requesting it to be enabled.
4087 void intel_init_power_well(struct drm_device
*dev
)
4089 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4091 if (!IS_HASWELL(dev
))
4094 /* For now, we need the power well to be always enabled. */
4095 intel_set_power_well(dev
, true);
4097 /* We're taking over the BIOS, so clear any requests made by it since
4098 * the driver is in charge now. */
4099 if (I915_READ(HSW_PWR_WELL_BIOS
) & HSW_PWR_WELL_ENABLE
)
4100 I915_WRITE(HSW_PWR_WELL_BIOS
, 0);
4103 /* Set up chip specific power management-related functions */
4104 void intel_init_pm(struct drm_device
*dev
)
4106 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4108 if (I915_HAS_FBC(dev
)) {
4109 if (HAS_PCH_SPLIT(dev
)) {
4110 dev_priv
->display
.fbc_enabled
= ironlake_fbc_enabled
;
4111 dev_priv
->display
.enable_fbc
= ironlake_enable_fbc
;
4112 dev_priv
->display
.disable_fbc
= ironlake_disable_fbc
;
4113 } else if (IS_GM45(dev
)) {
4114 dev_priv
->display
.fbc_enabled
= g4x_fbc_enabled
;
4115 dev_priv
->display
.enable_fbc
= g4x_enable_fbc
;
4116 dev_priv
->display
.disable_fbc
= g4x_disable_fbc
;
4117 } else if (IS_CRESTLINE(dev
)) {
4118 dev_priv
->display
.fbc_enabled
= i8xx_fbc_enabled
;
4119 dev_priv
->display
.enable_fbc
= i8xx_enable_fbc
;
4120 dev_priv
->display
.disable_fbc
= i8xx_disable_fbc
;
4122 /* 855GM needs testing */
4126 if (IS_PINEVIEW(dev
))
4127 i915_pineview_get_mem_freq(dev
);
4128 else if (IS_GEN5(dev
))
4129 i915_ironlake_get_mem_freq(dev
);
4131 /* For FIFO watermark updates */
4132 if (HAS_PCH_SPLIT(dev
)) {
4134 if (I915_READ(MLTR_ILK
) & ILK_SRLT_MASK
)
4135 dev_priv
->display
.update_wm
= ironlake_update_wm
;
4137 DRM_DEBUG_KMS("Failed to get proper latency. "
4139 dev_priv
->display
.update_wm
= NULL
;
4141 dev_priv
->display
.init_clock_gating
= ironlake_init_clock_gating
;
4142 } else if (IS_GEN6(dev
)) {
4143 if (SNB_READ_WM0_LATENCY()) {
4144 dev_priv
->display
.update_wm
= sandybridge_update_wm
;
4145 dev_priv
->display
.update_sprite_wm
= sandybridge_update_sprite_wm
;
4147 DRM_DEBUG_KMS("Failed to read display plane latency. "
4149 dev_priv
->display
.update_wm
= NULL
;
4151 dev_priv
->display
.init_clock_gating
= gen6_init_clock_gating
;
4152 } else if (IS_IVYBRIDGE(dev
)) {
4153 /* FIXME: detect B0+ stepping and use auto training */
4154 if (SNB_READ_WM0_LATENCY()) {
4155 dev_priv
->display
.update_wm
= ivybridge_update_wm
;
4156 dev_priv
->display
.update_sprite_wm
= sandybridge_update_sprite_wm
;
4158 DRM_DEBUG_KMS("Failed to read display plane latency. "
4160 dev_priv
->display
.update_wm
= NULL
;
4162 dev_priv
->display
.init_clock_gating
= ivybridge_init_clock_gating
;
4163 } else if (IS_HASWELL(dev
)) {
4164 if (SNB_READ_WM0_LATENCY()) {
4165 dev_priv
->display
.update_wm
= sandybridge_update_wm
;
4166 dev_priv
->display
.update_sprite_wm
= sandybridge_update_sprite_wm
;
4167 dev_priv
->display
.update_linetime_wm
= haswell_update_linetime_wm
;
4169 DRM_DEBUG_KMS("Failed to read display plane latency. "
4171 dev_priv
->display
.update_wm
= NULL
;
4173 dev_priv
->display
.init_clock_gating
= haswell_init_clock_gating
;
4175 dev_priv
->display
.update_wm
= NULL
;
4176 } else if (IS_VALLEYVIEW(dev
)) {
4177 dev_priv
->display
.update_wm
= valleyview_update_wm
;
4178 dev_priv
->display
.init_clock_gating
=
4179 valleyview_init_clock_gating
;
4180 } else if (IS_PINEVIEW(dev
)) {
4181 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev
),
4184 dev_priv
->mem_freq
)) {
4185 DRM_INFO("failed to find known CxSR latency "
4186 "(found ddr%s fsb freq %d, mem freq %d), "
4188 (dev_priv
->is_ddr3
== 1) ? "3" : "2",
4189 dev_priv
->fsb_freq
, dev_priv
->mem_freq
);
4190 /* Disable CxSR and never update its watermark again */
4191 pineview_disable_cxsr(dev
);
4192 dev_priv
->display
.update_wm
= NULL
;
4194 dev_priv
->display
.update_wm
= pineview_update_wm
;
4195 dev_priv
->display
.init_clock_gating
= gen3_init_clock_gating
;
4196 } else if (IS_G4X(dev
)) {
4197 dev_priv
->display
.update_wm
= g4x_update_wm
;
4198 dev_priv
->display
.init_clock_gating
= g4x_init_clock_gating
;
4199 } else if (IS_GEN4(dev
)) {
4200 dev_priv
->display
.update_wm
= i965_update_wm
;
4201 if (IS_CRESTLINE(dev
))
4202 dev_priv
->display
.init_clock_gating
= crestline_init_clock_gating
;
4203 else if (IS_BROADWATER(dev
))
4204 dev_priv
->display
.init_clock_gating
= broadwater_init_clock_gating
;
4205 } else if (IS_GEN3(dev
)) {
4206 dev_priv
->display
.update_wm
= i9xx_update_wm
;
4207 dev_priv
->display
.get_fifo_size
= i9xx_get_fifo_size
;
4208 dev_priv
->display
.init_clock_gating
= gen3_init_clock_gating
;
4209 } else if (IS_I865G(dev
)) {
4210 dev_priv
->display
.update_wm
= i830_update_wm
;
4211 dev_priv
->display
.init_clock_gating
= i85x_init_clock_gating
;
4212 dev_priv
->display
.get_fifo_size
= i830_get_fifo_size
;
4213 } else if (IS_I85X(dev
)) {
4214 dev_priv
->display
.update_wm
= i9xx_update_wm
;
4215 dev_priv
->display
.get_fifo_size
= i85x_get_fifo_size
;
4216 dev_priv
->display
.init_clock_gating
= i85x_init_clock_gating
;
4218 dev_priv
->display
.update_wm
= i830_update_wm
;
4219 dev_priv
->display
.init_clock_gating
= i830_init_clock_gating
;
4221 dev_priv
->display
.get_fifo_size
= i845_get_fifo_size
;
4223 dev_priv
->display
.get_fifo_size
= i830_get_fifo_size
;
4227 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private
*dev_priv
)
4229 u32 gt_thread_status_mask
;
4231 if (IS_HASWELL(dev_priv
->dev
))
4232 gt_thread_status_mask
= GEN6_GT_THREAD_STATUS_CORE_MASK_HSW
;
4234 gt_thread_status_mask
= GEN6_GT_THREAD_STATUS_CORE_MASK
;
4236 /* w/a for a sporadic read returning 0 by waiting for the GT
4237 * thread to wake up.
4239 if (wait_for_atomic_us((I915_READ_NOTRACE(GEN6_GT_THREAD_STATUS_REG
) & gt_thread_status_mask
) == 0, 500))
4240 DRM_ERROR("GT thread status wait timed out\n");
4243 static void __gen6_gt_force_wake_reset(struct drm_i915_private
*dev_priv
)
4245 I915_WRITE_NOTRACE(FORCEWAKE
, 0);
4246 POSTING_READ(ECOBUS
); /* something from same cacheline, but !FORCEWAKE */
4249 static void __gen6_gt_force_wake_get(struct drm_i915_private
*dev_priv
)
4253 if (IS_HASWELL(dev_priv
->dev
))
4254 forcewake_ack
= FORCEWAKE_ACK_HSW
;
4256 forcewake_ack
= FORCEWAKE_ACK
;
4258 if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack
) & 1) == 0,
4259 FORCEWAKE_ACK_TIMEOUT_MS
))
4260 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
4262 I915_WRITE_NOTRACE(FORCEWAKE
, FORCEWAKE_KERNEL
);
4263 POSTING_READ(ECOBUS
); /* something from same cacheline, but !FORCEWAKE */
4265 if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack
) & 1),
4266 FORCEWAKE_ACK_TIMEOUT_MS
))
4267 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
4269 __gen6_gt_wait_for_thread_c0(dev_priv
);
4272 static void __gen6_gt_force_wake_mt_reset(struct drm_i915_private
*dev_priv
)
4274 I915_WRITE_NOTRACE(FORCEWAKE_MT
, _MASKED_BIT_DISABLE(0xffff));
4275 POSTING_READ(ECOBUS
); /* something from same cacheline, but !FORCEWAKE */
4278 static void __gen6_gt_force_wake_mt_get(struct drm_i915_private
*dev_priv
)
4282 if (IS_HASWELL(dev_priv
->dev
))
4283 forcewake_ack
= FORCEWAKE_ACK_HSW
;
4285 forcewake_ack
= FORCEWAKE_MT_ACK
;
4287 if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack
) & 1) == 0,
4288 FORCEWAKE_ACK_TIMEOUT_MS
))
4289 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
4291 I915_WRITE_NOTRACE(FORCEWAKE_MT
, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL
));
4292 POSTING_READ(ECOBUS
); /* something from same cacheline, but !FORCEWAKE */
4294 if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack
) & 1),
4295 FORCEWAKE_ACK_TIMEOUT_MS
))
4296 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
4298 __gen6_gt_wait_for_thread_c0(dev_priv
);
4302 * Generally this is called implicitly by the register read function. However,
4303 * if some sequence requires the GT to not power down then this function should
4304 * be called at the beginning of the sequence followed by a call to
4305 * gen6_gt_force_wake_put() at the end of the sequence.
4307 void gen6_gt_force_wake_get(struct drm_i915_private
*dev_priv
)
4309 unsigned long irqflags
;
4311 spin_lock_irqsave(&dev_priv
->gt_lock
, irqflags
);
4312 if (dev_priv
->forcewake_count
++ == 0)
4313 dev_priv
->gt
.force_wake_get(dev_priv
);
4314 spin_unlock_irqrestore(&dev_priv
->gt_lock
, irqflags
);
4317 void gen6_gt_check_fifodbg(struct drm_i915_private
*dev_priv
)
4320 gtfifodbg
= I915_READ_NOTRACE(GTFIFODBG
);
4321 if (WARN(gtfifodbg
& GT_FIFO_CPU_ERROR_MASK
,
4322 "MMIO read or write has been dropped %x\n", gtfifodbg
))
4323 I915_WRITE_NOTRACE(GTFIFODBG
, GT_FIFO_CPU_ERROR_MASK
);
4326 static void __gen6_gt_force_wake_put(struct drm_i915_private
*dev_priv
)
4328 I915_WRITE_NOTRACE(FORCEWAKE
, 0);
4329 /* gen6_gt_check_fifodbg doubles as the POSTING_READ */
4330 gen6_gt_check_fifodbg(dev_priv
);
4333 static void __gen6_gt_force_wake_mt_put(struct drm_i915_private
*dev_priv
)
4335 I915_WRITE_NOTRACE(FORCEWAKE_MT
, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL
));
4336 /* gen6_gt_check_fifodbg doubles as the POSTING_READ */
4337 gen6_gt_check_fifodbg(dev_priv
);
4341 * see gen6_gt_force_wake_get()
4343 void gen6_gt_force_wake_put(struct drm_i915_private
*dev_priv
)
4345 unsigned long irqflags
;
4347 spin_lock_irqsave(&dev_priv
->gt_lock
, irqflags
);
4348 if (--dev_priv
->forcewake_count
== 0)
4349 dev_priv
->gt
.force_wake_put(dev_priv
);
4350 spin_unlock_irqrestore(&dev_priv
->gt_lock
, irqflags
);
4353 int __gen6_gt_wait_for_fifo(struct drm_i915_private
*dev_priv
)
4357 if (dev_priv
->gt_fifo_count
< GT_FIFO_NUM_RESERVED_ENTRIES
) {
4359 u32 fifo
= I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES
);
4360 while (fifo
<= GT_FIFO_NUM_RESERVED_ENTRIES
&& loop
--) {
4362 fifo
= I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES
);
4364 if (WARN_ON(loop
< 0 && fifo
<= GT_FIFO_NUM_RESERVED_ENTRIES
))
4366 dev_priv
->gt_fifo_count
= fifo
;
4368 dev_priv
->gt_fifo_count
--;
4373 static void vlv_force_wake_reset(struct drm_i915_private
*dev_priv
)
4375 I915_WRITE_NOTRACE(FORCEWAKE_VLV
, _MASKED_BIT_DISABLE(0xffff));
4378 static void vlv_force_wake_get(struct drm_i915_private
*dev_priv
)
4380 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV
) & 1) == 0,
4381 FORCEWAKE_ACK_TIMEOUT_MS
))
4382 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
4384 I915_WRITE_NOTRACE(FORCEWAKE_VLV
, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL
));
4386 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV
) & 1),
4387 FORCEWAKE_ACK_TIMEOUT_MS
))
4388 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
4390 __gen6_gt_wait_for_thread_c0(dev_priv
);
4393 static void vlv_force_wake_put(struct drm_i915_private
*dev_priv
)
4395 I915_WRITE_NOTRACE(FORCEWAKE_VLV
, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL
));
4396 /* The below doubles as a POSTING_READ */
4397 gen6_gt_check_fifodbg(dev_priv
);
4400 void intel_gt_reset(struct drm_device
*dev
)
4402 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4404 if (IS_VALLEYVIEW(dev
)) {
4405 vlv_force_wake_reset(dev_priv
);
4406 } else if (INTEL_INFO(dev
)->gen
>= 6) {
4407 __gen6_gt_force_wake_reset(dev_priv
);
4408 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
))
4409 __gen6_gt_force_wake_mt_reset(dev_priv
);
4413 void intel_gt_init(struct drm_device
*dev
)
4415 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4417 spin_lock_init(&dev_priv
->gt_lock
);
4419 intel_gt_reset(dev
);
4421 if (IS_VALLEYVIEW(dev
)) {
4422 dev_priv
->gt
.force_wake_get
= vlv_force_wake_get
;
4423 dev_priv
->gt
.force_wake_put
= vlv_force_wake_put
;
4424 } else if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
)) {
4425 dev_priv
->gt
.force_wake_get
= __gen6_gt_force_wake_mt_get
;
4426 dev_priv
->gt
.force_wake_put
= __gen6_gt_force_wake_mt_put
;
4427 } else if (IS_GEN6(dev
)) {
4428 dev_priv
->gt
.force_wake_get
= __gen6_gt_force_wake_get
;
4429 dev_priv
->gt
.force_wake_put
= __gen6_gt_force_wake_put
;
4431 INIT_DELAYED_WORK(&dev_priv
->rps
.delayed_resume_work
,
4432 intel_gen6_powersave_work
);
4435 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u8 mbox
, u32
*val
)
4437 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
4439 if (I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) {
4440 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
4444 I915_WRITE(GEN6_PCODE_DATA
, *val
);
4445 I915_WRITE(GEN6_PCODE_MAILBOX
, GEN6_PCODE_READY
| mbox
);
4447 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) == 0,
4449 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox
);
4453 *val
= I915_READ(GEN6_PCODE_DATA
);
4454 I915_WRITE(GEN6_PCODE_DATA
, 0);
4459 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
, u8 mbox
, u32 val
)
4461 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
4463 if (I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) {
4464 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
4468 I915_WRITE(GEN6_PCODE_DATA
, val
);
4469 I915_WRITE(GEN6_PCODE_MAILBOX
, GEN6_PCODE_READY
| mbox
);
4471 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) == 0,
4473 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox
);
4477 I915_WRITE(GEN6_PCODE_DATA
, 0);