2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
28 #include <linux/cpufreq.h>
30 #include "intel_drv.h"
31 #include "../../../platform/x86/intel_ips.h"
32 #include <linux/module.h>
33 #include <linux/vgaarb.h>
34 #include <drm/i915_powerwell.h>
35 #include <linux/pm_runtime.h>
38 * RC6 is a special power stage which allows the GPU to enter an very
39 * low-voltage mode when idle, using down to 0V while at this stage. This
40 * stage is entered automatically when the GPU is idle when RC6 support is
41 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
43 * There are different RC6 modes available in Intel GPU, which differentiate
44 * among each other with the latency required to enter and leave RC6 and
45 * voltage consumed by the GPU in different states.
47 * The combination of the following flags define which states GPU is allowed
48 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
49 * RC6pp is deepest RC6. Their support by hardware varies according to the
50 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
51 * which brings the most power savings; deeper states save more power, but
52 * require higher latency to switch to and wake up.
54 #define INTEL_RC6_ENABLE (1<<0)
55 #define INTEL_RC6p_ENABLE (1<<1)
56 #define INTEL_RC6pp_ENABLE (1<<2)
58 /* FBC, or Frame Buffer Compression, is a technique employed to compress the
59 * framebuffer contents in-memory, aiming at reducing the required bandwidth
60 * during in-memory transfers and, therefore, reduce the power packet.
62 * The benefits of FBC are mostly visible with solid backgrounds and
63 * variation-less patterns.
65 * FBC-related functionality can be enabled by the means of the
66 * i915.i915_enable_fbc parameter
69 static void gen9_init_clock_gating(struct drm_device
*dev
)
73 static void i8xx_disable_fbc(struct drm_device
*dev
)
75 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
78 /* Disable compression */
79 fbc_ctl
= I915_READ(FBC_CONTROL
);
80 if ((fbc_ctl
& FBC_CTL_EN
) == 0)
83 fbc_ctl
&= ~FBC_CTL_EN
;
84 I915_WRITE(FBC_CONTROL
, fbc_ctl
);
86 /* Wait for compressing bit to clear */
87 if (wait_for((I915_READ(FBC_STATUS
) & FBC_STAT_COMPRESSING
) == 0, 10)) {
88 DRM_DEBUG_KMS("FBC idle timed out\n");
92 DRM_DEBUG_KMS("disabled FBC\n");
95 static void i8xx_enable_fbc(struct drm_crtc
*crtc
)
97 struct drm_device
*dev
= crtc
->dev
;
98 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
99 struct drm_framebuffer
*fb
= crtc
->primary
->fb
;
100 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
101 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
106 cfb_pitch
= dev_priv
->fbc
.size
/ FBC_LL_SIZE
;
107 if (fb
->pitches
[0] < cfb_pitch
)
108 cfb_pitch
= fb
->pitches
[0];
110 /* FBC_CTL wants 32B or 64B units */
112 cfb_pitch
= (cfb_pitch
/ 32) - 1;
114 cfb_pitch
= (cfb_pitch
/ 64) - 1;
117 for (i
= 0; i
< (FBC_LL_SIZE
/ 32) + 1; i
++)
118 I915_WRITE(FBC_TAG
+ (i
* 4), 0);
124 fbc_ctl2
= FBC_CTL_FENCE_DBL
| FBC_CTL_IDLE_IMM
| FBC_CTL_CPU_FENCE
;
125 fbc_ctl2
|= FBC_CTL_PLANE(intel_crtc
->plane
);
126 I915_WRITE(FBC_CONTROL2
, fbc_ctl2
);
127 I915_WRITE(FBC_FENCE_OFF
, crtc
->y
);
131 fbc_ctl
= I915_READ(FBC_CONTROL
);
132 fbc_ctl
&= 0x3fff << FBC_CTL_INTERVAL_SHIFT
;
133 fbc_ctl
|= FBC_CTL_EN
| FBC_CTL_PERIODIC
;
135 fbc_ctl
|= FBC_CTL_C3_IDLE
; /* 945 needs special SR handling */
136 fbc_ctl
|= (cfb_pitch
& 0xff) << FBC_CTL_STRIDE_SHIFT
;
137 fbc_ctl
|= obj
->fence_reg
;
138 I915_WRITE(FBC_CONTROL
, fbc_ctl
);
140 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c\n",
141 cfb_pitch
, crtc
->y
, plane_name(intel_crtc
->plane
));
144 static bool i8xx_fbc_enabled(struct drm_device
*dev
)
146 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
148 return I915_READ(FBC_CONTROL
) & FBC_CTL_EN
;
151 static void g4x_enable_fbc(struct drm_crtc
*crtc
)
153 struct drm_device
*dev
= crtc
->dev
;
154 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
155 struct drm_framebuffer
*fb
= crtc
->primary
->fb
;
156 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
157 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
160 dpfc_ctl
= DPFC_CTL_PLANE(intel_crtc
->plane
) | DPFC_SR_EN
;
161 if (drm_format_plane_cpp(fb
->pixel_format
, 0) == 2)
162 dpfc_ctl
|= DPFC_CTL_LIMIT_2X
;
164 dpfc_ctl
|= DPFC_CTL_LIMIT_1X
;
165 dpfc_ctl
|= DPFC_CTL_FENCE_EN
| obj
->fence_reg
;
167 I915_WRITE(DPFC_FENCE_YOFF
, crtc
->y
);
170 I915_WRITE(DPFC_CONTROL
, dpfc_ctl
| DPFC_CTL_EN
);
172 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc
->plane
));
175 static void g4x_disable_fbc(struct drm_device
*dev
)
177 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
180 /* Disable compression */
181 dpfc_ctl
= I915_READ(DPFC_CONTROL
);
182 if (dpfc_ctl
& DPFC_CTL_EN
) {
183 dpfc_ctl
&= ~DPFC_CTL_EN
;
184 I915_WRITE(DPFC_CONTROL
, dpfc_ctl
);
186 DRM_DEBUG_KMS("disabled FBC\n");
190 static bool g4x_fbc_enabled(struct drm_device
*dev
)
192 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
194 return I915_READ(DPFC_CONTROL
) & DPFC_CTL_EN
;
197 static void sandybridge_blit_fbc_update(struct drm_device
*dev
)
199 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
202 /* Make sure blitter notifies FBC of writes */
204 /* Blitter is part of Media powerwell on VLV. No impact of
205 * his param in other platforms for now */
206 gen6_gt_force_wake_get(dev_priv
, FORCEWAKE_MEDIA
);
208 blt_ecoskpd
= I915_READ(GEN6_BLITTER_ECOSKPD
);
209 blt_ecoskpd
|= GEN6_BLITTER_FBC_NOTIFY
<<
210 GEN6_BLITTER_LOCK_SHIFT
;
211 I915_WRITE(GEN6_BLITTER_ECOSKPD
, blt_ecoskpd
);
212 blt_ecoskpd
|= GEN6_BLITTER_FBC_NOTIFY
;
213 I915_WRITE(GEN6_BLITTER_ECOSKPD
, blt_ecoskpd
);
214 blt_ecoskpd
&= ~(GEN6_BLITTER_FBC_NOTIFY
<<
215 GEN6_BLITTER_LOCK_SHIFT
);
216 I915_WRITE(GEN6_BLITTER_ECOSKPD
, blt_ecoskpd
);
217 POSTING_READ(GEN6_BLITTER_ECOSKPD
);
219 gen6_gt_force_wake_put(dev_priv
, FORCEWAKE_MEDIA
);
222 static void ironlake_enable_fbc(struct drm_crtc
*crtc
)
224 struct drm_device
*dev
= crtc
->dev
;
225 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
226 struct drm_framebuffer
*fb
= crtc
->primary
->fb
;
227 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
228 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
231 dpfc_ctl
= DPFC_CTL_PLANE(intel_crtc
->plane
);
232 if (drm_format_plane_cpp(fb
->pixel_format
, 0) == 2)
233 dev_priv
->fbc
.threshold
++;
235 switch (dev_priv
->fbc
.threshold
) {
238 dpfc_ctl
|= DPFC_CTL_LIMIT_4X
;
241 dpfc_ctl
|= DPFC_CTL_LIMIT_2X
;
244 dpfc_ctl
|= DPFC_CTL_LIMIT_1X
;
247 dpfc_ctl
|= DPFC_CTL_FENCE_EN
;
249 dpfc_ctl
|= obj
->fence_reg
;
251 I915_WRITE(ILK_DPFC_FENCE_YOFF
, crtc
->y
);
252 I915_WRITE(ILK_FBC_RT_BASE
, i915_gem_obj_ggtt_offset(obj
) | ILK_FBC_RT_VALID
);
254 I915_WRITE(ILK_DPFC_CONTROL
, dpfc_ctl
| DPFC_CTL_EN
);
257 I915_WRITE(SNB_DPFC_CTL_SA
,
258 SNB_CPU_FENCE_ENABLE
| obj
->fence_reg
);
259 I915_WRITE(DPFC_CPU_FENCE_OFFSET
, crtc
->y
);
260 sandybridge_blit_fbc_update(dev
);
263 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc
->plane
));
266 static void ironlake_disable_fbc(struct drm_device
*dev
)
268 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
271 /* Disable compression */
272 dpfc_ctl
= I915_READ(ILK_DPFC_CONTROL
);
273 if (dpfc_ctl
& DPFC_CTL_EN
) {
274 dpfc_ctl
&= ~DPFC_CTL_EN
;
275 I915_WRITE(ILK_DPFC_CONTROL
, dpfc_ctl
);
277 DRM_DEBUG_KMS("disabled FBC\n");
281 static bool ironlake_fbc_enabled(struct drm_device
*dev
)
283 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
285 return I915_READ(ILK_DPFC_CONTROL
) & DPFC_CTL_EN
;
288 static void gen7_enable_fbc(struct drm_crtc
*crtc
)
290 struct drm_device
*dev
= crtc
->dev
;
291 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
292 struct drm_framebuffer
*fb
= crtc
->primary
->fb
;
293 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
294 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
297 dpfc_ctl
= IVB_DPFC_CTL_PLANE(intel_crtc
->plane
);
298 if (drm_format_plane_cpp(fb
->pixel_format
, 0) == 2)
299 dev_priv
->fbc
.threshold
++;
301 switch (dev_priv
->fbc
.threshold
) {
304 dpfc_ctl
|= DPFC_CTL_LIMIT_4X
;
307 dpfc_ctl
|= DPFC_CTL_LIMIT_2X
;
310 dpfc_ctl
|= DPFC_CTL_LIMIT_1X
;
314 dpfc_ctl
|= IVB_DPFC_CTL_FENCE_EN
;
316 if (dev_priv
->fbc
.false_color
)
317 dpfc_ctl
|= FBC_CTL_FALSE_COLOR
;
319 I915_WRITE(ILK_DPFC_CONTROL
, dpfc_ctl
| DPFC_CTL_EN
);
321 if (IS_IVYBRIDGE(dev
)) {
322 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
323 I915_WRITE(ILK_DISPLAY_CHICKEN1
,
324 I915_READ(ILK_DISPLAY_CHICKEN1
) |
327 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
328 I915_WRITE(CHICKEN_PIPESL_1(intel_crtc
->pipe
),
329 I915_READ(CHICKEN_PIPESL_1(intel_crtc
->pipe
)) |
333 I915_WRITE(SNB_DPFC_CTL_SA
,
334 SNB_CPU_FENCE_ENABLE
| obj
->fence_reg
);
335 I915_WRITE(DPFC_CPU_FENCE_OFFSET
, crtc
->y
);
337 sandybridge_blit_fbc_update(dev
);
339 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc
->plane
));
342 bool intel_fbc_enabled(struct drm_device
*dev
)
344 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
346 if (!dev_priv
->display
.fbc_enabled
)
349 return dev_priv
->display
.fbc_enabled(dev
);
352 void gen8_fbc_sw_flush(struct drm_device
*dev
, u32 value
)
354 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
359 I915_WRITE(MSG_FBC_REND_STATE
, value
);
362 static void intel_fbc_work_fn(struct work_struct
*__work
)
364 struct intel_fbc_work
*work
=
365 container_of(to_delayed_work(__work
),
366 struct intel_fbc_work
, work
);
367 struct drm_device
*dev
= work
->crtc
->dev
;
368 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
370 mutex_lock(&dev
->struct_mutex
);
371 if (work
== dev_priv
->fbc
.fbc_work
) {
372 /* Double check that we haven't switched fb without cancelling
375 if (work
->crtc
->primary
->fb
== work
->fb
) {
376 dev_priv
->display
.enable_fbc(work
->crtc
);
378 dev_priv
->fbc
.plane
= to_intel_crtc(work
->crtc
)->plane
;
379 dev_priv
->fbc
.fb_id
= work
->crtc
->primary
->fb
->base
.id
;
380 dev_priv
->fbc
.y
= work
->crtc
->y
;
383 dev_priv
->fbc
.fbc_work
= NULL
;
385 mutex_unlock(&dev
->struct_mutex
);
390 static void intel_cancel_fbc_work(struct drm_i915_private
*dev_priv
)
392 if (dev_priv
->fbc
.fbc_work
== NULL
)
395 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
397 /* Synchronisation is provided by struct_mutex and checking of
398 * dev_priv->fbc.fbc_work, so we can perform the cancellation
399 * entirely asynchronously.
401 if (cancel_delayed_work(&dev_priv
->fbc
.fbc_work
->work
))
402 /* tasklet was killed before being run, clean up */
403 kfree(dev_priv
->fbc
.fbc_work
);
405 /* Mark the work as no longer wanted so that if it does
406 * wake-up (because the work was already running and waiting
407 * for our mutex), it will discover that is no longer
410 dev_priv
->fbc
.fbc_work
= NULL
;
413 static void intel_enable_fbc(struct drm_crtc
*crtc
)
415 struct intel_fbc_work
*work
;
416 struct drm_device
*dev
= crtc
->dev
;
417 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
419 if (!dev_priv
->display
.enable_fbc
)
422 intel_cancel_fbc_work(dev_priv
);
424 work
= kzalloc(sizeof(*work
), GFP_KERNEL
);
426 DRM_ERROR("Failed to allocate FBC work structure\n");
427 dev_priv
->display
.enable_fbc(crtc
);
432 work
->fb
= crtc
->primary
->fb
;
433 INIT_DELAYED_WORK(&work
->work
, intel_fbc_work_fn
);
435 dev_priv
->fbc
.fbc_work
= work
;
437 /* Delay the actual enabling to let pageflipping cease and the
438 * display to settle before starting the compression. Note that
439 * this delay also serves a second purpose: it allows for a
440 * vblank to pass after disabling the FBC before we attempt
441 * to modify the control registers.
443 * A more complicated solution would involve tracking vblanks
444 * following the termination of the page-flipping sequence
445 * and indeed performing the enable as a co-routine and not
446 * waiting synchronously upon the vblank.
448 * WaFbcWaitForVBlankBeforeEnable:ilk,snb
450 schedule_delayed_work(&work
->work
, msecs_to_jiffies(50));
453 void intel_disable_fbc(struct drm_device
*dev
)
455 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
457 intel_cancel_fbc_work(dev_priv
);
459 if (!dev_priv
->display
.disable_fbc
)
462 dev_priv
->display
.disable_fbc(dev
);
463 dev_priv
->fbc
.plane
= -1;
466 static bool set_no_fbc_reason(struct drm_i915_private
*dev_priv
,
467 enum no_fbc_reason reason
)
469 if (dev_priv
->fbc
.no_fbc_reason
== reason
)
472 dev_priv
->fbc
.no_fbc_reason
= reason
;
477 * intel_update_fbc - enable/disable FBC as needed
478 * @dev: the drm_device
480 * Set up the framebuffer compression hardware at mode set time. We
481 * enable it if possible:
482 * - plane A only (on pre-965)
483 * - no pixel mulitply/line duplication
484 * - no alpha buffer discard
486 * - framebuffer <= max_hdisplay in width, max_vdisplay in height
488 * We can't assume that any compression will take place (worst case),
489 * so the compressed buffer has to be the same size as the uncompressed
490 * one. It also must reside (along with the line length buffer) in
493 * We need to enable/disable FBC on a global basis.
495 void intel_update_fbc(struct drm_device
*dev
)
497 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
498 struct drm_crtc
*crtc
= NULL
, *tmp_crtc
;
499 struct intel_crtc
*intel_crtc
;
500 struct drm_framebuffer
*fb
;
501 struct drm_i915_gem_object
*obj
;
502 const struct drm_display_mode
*adjusted_mode
;
503 unsigned int max_width
, max_height
;
506 set_no_fbc_reason(dev_priv
, FBC_UNSUPPORTED
);
510 if (!i915
.powersave
) {
511 if (set_no_fbc_reason(dev_priv
, FBC_MODULE_PARAM
))
512 DRM_DEBUG_KMS("fbc disabled per module param\n");
517 * If FBC is already on, we just have to verify that we can
518 * keep it that way...
519 * Need to disable if:
520 * - more than one pipe is active
521 * - changing FBC params (stride, fence, mode)
522 * - new fb is too large to fit in compressed buffer
523 * - going to an unsupported config (interlace, pixel multiply, etc.)
525 for_each_crtc(dev
, tmp_crtc
) {
526 if (intel_crtc_active(tmp_crtc
) &&
527 to_intel_crtc(tmp_crtc
)->primary_enabled
) {
529 if (set_no_fbc_reason(dev_priv
, FBC_MULTIPLE_PIPES
))
530 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
537 if (!crtc
|| crtc
->primary
->fb
== NULL
) {
538 if (set_no_fbc_reason(dev_priv
, FBC_NO_OUTPUT
))
539 DRM_DEBUG_KMS("no output, disabling\n");
543 intel_crtc
= to_intel_crtc(crtc
);
544 fb
= crtc
->primary
->fb
;
545 obj
= intel_fb_obj(fb
);
546 adjusted_mode
= &intel_crtc
->config
.adjusted_mode
;
548 if (i915
.enable_fbc
< 0) {
549 if (set_no_fbc_reason(dev_priv
, FBC_CHIP_DEFAULT
))
550 DRM_DEBUG_KMS("disabled per chip default\n");
553 if (!i915
.enable_fbc
) {
554 if (set_no_fbc_reason(dev_priv
, FBC_MODULE_PARAM
))
555 DRM_DEBUG_KMS("fbc disabled per module param\n");
558 if ((adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) ||
559 (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLSCAN
)) {
560 if (set_no_fbc_reason(dev_priv
, FBC_UNSUPPORTED_MODE
))
561 DRM_DEBUG_KMS("mode incompatible with compression, "
566 if (INTEL_INFO(dev
)->gen
>= 8 || IS_HASWELL(dev
)) {
569 } else if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5) {
576 if (intel_crtc
->config
.pipe_src_w
> max_width
||
577 intel_crtc
->config
.pipe_src_h
> max_height
) {
578 if (set_no_fbc_reason(dev_priv
, FBC_MODE_TOO_LARGE
))
579 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
582 if ((INTEL_INFO(dev
)->gen
< 4 || HAS_DDI(dev
)) &&
583 intel_crtc
->plane
!= PLANE_A
) {
584 if (set_no_fbc_reason(dev_priv
, FBC_BAD_PLANE
))
585 DRM_DEBUG_KMS("plane not A, disabling compression\n");
589 /* The use of a CPU fence is mandatory in order to detect writes
590 * by the CPU to the scanout and trigger updates to the FBC.
592 if (obj
->tiling_mode
!= I915_TILING_X
||
593 obj
->fence_reg
== I915_FENCE_REG_NONE
) {
594 if (set_no_fbc_reason(dev_priv
, FBC_NOT_TILED
))
595 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
598 if (INTEL_INFO(dev
)->gen
<= 4 && !IS_G4X(dev
) &&
599 to_intel_plane(crtc
->primary
)->rotation
!= BIT(DRM_ROTATE_0
)) {
600 if (set_no_fbc_reason(dev_priv
, FBC_UNSUPPORTED_MODE
))
601 DRM_DEBUG_KMS("Rotation unsupported, disabling\n");
605 /* If the kernel debugger is active, always disable compression */
609 if (i915_gem_stolen_setup_compression(dev
, obj
->base
.size
,
610 drm_format_plane_cpp(fb
->pixel_format
, 0))) {
611 if (set_no_fbc_reason(dev_priv
, FBC_STOLEN_TOO_SMALL
))
612 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
616 /* If the scanout has not changed, don't modify the FBC settings.
617 * Note that we make the fundamental assumption that the fb->obj
618 * cannot be unpinned (and have its GTT offset and fence revoked)
619 * without first being decoupled from the scanout and FBC disabled.
621 if (dev_priv
->fbc
.plane
== intel_crtc
->plane
&&
622 dev_priv
->fbc
.fb_id
== fb
->base
.id
&&
623 dev_priv
->fbc
.y
== crtc
->y
)
626 if (intel_fbc_enabled(dev
)) {
627 /* We update FBC along two paths, after changing fb/crtc
628 * configuration (modeswitching) and after page-flipping
629 * finishes. For the latter, we know that not only did
630 * we disable the FBC at the start of the page-flip
631 * sequence, but also more than one vblank has passed.
633 * For the former case of modeswitching, it is possible
634 * to switch between two FBC valid configurations
635 * instantaneously so we do need to disable the FBC
636 * before we can modify its control registers. We also
637 * have to wait for the next vblank for that to take
638 * effect. However, since we delay enabling FBC we can
639 * assume that a vblank has passed since disabling and
640 * that we can safely alter the registers in the deferred
643 * In the scenario that we go from a valid to invalid
644 * and then back to valid FBC configuration we have
645 * no strict enforcement that a vblank occurred since
646 * disabling the FBC. However, along all current pipe
647 * disabling paths we do need to wait for a vblank at
648 * some point. And we wait before enabling FBC anyway.
650 DRM_DEBUG_KMS("disabling active FBC for update\n");
651 intel_disable_fbc(dev
);
654 intel_enable_fbc(crtc
);
655 dev_priv
->fbc
.no_fbc_reason
= FBC_OK
;
659 /* Multiple disables should be harmless */
660 if (intel_fbc_enabled(dev
)) {
661 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
662 intel_disable_fbc(dev
);
664 i915_gem_stolen_cleanup_compression(dev
);
667 static void i915_pineview_get_mem_freq(struct drm_device
*dev
)
669 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
672 tmp
= I915_READ(CLKCFG
);
674 switch (tmp
& CLKCFG_FSB_MASK
) {
676 dev_priv
->fsb_freq
= 533; /* 133*4 */
679 dev_priv
->fsb_freq
= 800; /* 200*4 */
682 dev_priv
->fsb_freq
= 667; /* 167*4 */
685 dev_priv
->fsb_freq
= 400; /* 100*4 */
689 switch (tmp
& CLKCFG_MEM_MASK
) {
691 dev_priv
->mem_freq
= 533;
694 dev_priv
->mem_freq
= 667;
697 dev_priv
->mem_freq
= 800;
701 /* detect pineview DDR3 setting */
702 tmp
= I915_READ(CSHRDDR3CTL
);
703 dev_priv
->is_ddr3
= (tmp
& CSHRDDR3CTL_DDR3
) ? 1 : 0;
706 static void i915_ironlake_get_mem_freq(struct drm_device
*dev
)
708 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
711 ddrpll
= I915_READ16(DDRMPLL1
);
712 csipll
= I915_READ16(CSIPLL0
);
714 switch (ddrpll
& 0xff) {
716 dev_priv
->mem_freq
= 800;
719 dev_priv
->mem_freq
= 1066;
722 dev_priv
->mem_freq
= 1333;
725 dev_priv
->mem_freq
= 1600;
728 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
730 dev_priv
->mem_freq
= 0;
734 dev_priv
->ips
.r_t
= dev_priv
->mem_freq
;
736 switch (csipll
& 0x3ff) {
738 dev_priv
->fsb_freq
= 3200;
741 dev_priv
->fsb_freq
= 3733;
744 dev_priv
->fsb_freq
= 4266;
747 dev_priv
->fsb_freq
= 4800;
750 dev_priv
->fsb_freq
= 5333;
753 dev_priv
->fsb_freq
= 5866;
756 dev_priv
->fsb_freq
= 6400;
759 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
761 dev_priv
->fsb_freq
= 0;
765 if (dev_priv
->fsb_freq
== 3200) {
766 dev_priv
->ips
.c_m
= 0;
767 } else if (dev_priv
->fsb_freq
> 3200 && dev_priv
->fsb_freq
<= 4800) {
768 dev_priv
->ips
.c_m
= 1;
770 dev_priv
->ips
.c_m
= 2;
774 static const struct cxsr_latency cxsr_latency_table
[] = {
775 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
776 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
777 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
778 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
779 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
781 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
782 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
783 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
784 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
785 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
787 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
788 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
789 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
790 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
791 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
793 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
794 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
795 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
796 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
797 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
799 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
800 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
801 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
802 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
803 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
805 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
806 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
807 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
808 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
809 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
812 static const struct cxsr_latency
*intel_get_cxsr_latency(int is_desktop
,
817 const struct cxsr_latency
*latency
;
820 if (fsb
== 0 || mem
== 0)
823 for (i
= 0; i
< ARRAY_SIZE(cxsr_latency_table
); i
++) {
824 latency
= &cxsr_latency_table
[i
];
825 if (is_desktop
== latency
->is_desktop
&&
826 is_ddr3
== latency
->is_ddr3
&&
827 fsb
== latency
->fsb_freq
&& mem
== latency
->mem_freq
)
831 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
836 void intel_set_memory_cxsr(struct drm_i915_private
*dev_priv
, bool enable
)
838 struct drm_device
*dev
= dev_priv
->dev
;
841 if (IS_VALLEYVIEW(dev
)) {
842 I915_WRITE(FW_BLC_SELF_VLV
, enable
? FW_CSPWRDWNEN
: 0);
843 } else if (IS_G4X(dev
) || IS_CRESTLINE(dev
)) {
844 I915_WRITE(FW_BLC_SELF
, enable
? FW_BLC_SELF_EN
: 0);
845 } else if (IS_PINEVIEW(dev
)) {
846 val
= I915_READ(DSPFW3
) & ~PINEVIEW_SELF_REFRESH_EN
;
847 val
|= enable
? PINEVIEW_SELF_REFRESH_EN
: 0;
848 I915_WRITE(DSPFW3
, val
);
849 } else if (IS_I945G(dev
) || IS_I945GM(dev
)) {
850 val
= enable
? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN
) :
851 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN
);
852 I915_WRITE(FW_BLC_SELF
, val
);
853 } else if (IS_I915GM(dev
)) {
854 val
= enable
? _MASKED_BIT_ENABLE(INSTPM_SELF_EN
) :
855 _MASKED_BIT_DISABLE(INSTPM_SELF_EN
);
856 I915_WRITE(INSTPM
, val
);
861 DRM_DEBUG_KMS("memory self-refresh is %s\n",
862 enable
? "enabled" : "disabled");
866 * Latency for FIFO fetches is dependent on several factors:
867 * - memory configuration (speed, channels)
869 * - current MCH state
870 * It can be fairly high in some situations, so here we assume a fairly
871 * pessimal value. It's a tradeoff between extra memory fetches (if we
872 * set this value too high, the FIFO will fetch frequently to stay full)
873 * and power consumption (set it too low to save power and we might see
874 * FIFO underruns and display "flicker").
876 * A value of 5us seems to be a good balance; safe for very low end
877 * platforms but not overly aggressive on lower latency configs.
879 static const int pessimal_latency_ns
= 5000;
881 static int i9xx_get_fifo_size(struct drm_device
*dev
, int plane
)
883 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
884 uint32_t dsparb
= I915_READ(DSPARB
);
887 size
= dsparb
& 0x7f;
889 size
= ((dsparb
>> DSPARB_CSTART_SHIFT
) & 0x7f) - size
;
891 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
892 plane
? "B" : "A", size
);
897 static int i830_get_fifo_size(struct drm_device
*dev
, int plane
)
899 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
900 uint32_t dsparb
= I915_READ(DSPARB
);
903 size
= dsparb
& 0x1ff;
905 size
= ((dsparb
>> DSPARB_BEND_SHIFT
) & 0x1ff) - size
;
906 size
>>= 1; /* Convert to cachelines */
908 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
909 plane
? "B" : "A", size
);
914 static int i845_get_fifo_size(struct drm_device
*dev
, int plane
)
916 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
917 uint32_t dsparb
= I915_READ(DSPARB
);
920 size
= dsparb
& 0x7f;
921 size
>>= 2; /* Convert to cachelines */
923 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
930 /* Pineview has different values for various configs */
931 static const struct intel_watermark_params pineview_display_wm
= {
932 .fifo_size
= PINEVIEW_DISPLAY_FIFO
,
933 .max_wm
= PINEVIEW_MAX_WM
,
934 .default_wm
= PINEVIEW_DFT_WM
,
935 .guard_size
= PINEVIEW_GUARD_WM
,
936 .cacheline_size
= PINEVIEW_FIFO_LINE_SIZE
,
938 static const struct intel_watermark_params pineview_display_hplloff_wm
= {
939 .fifo_size
= PINEVIEW_DISPLAY_FIFO
,
940 .max_wm
= PINEVIEW_MAX_WM
,
941 .default_wm
= PINEVIEW_DFT_HPLLOFF_WM
,
942 .guard_size
= PINEVIEW_GUARD_WM
,
943 .cacheline_size
= PINEVIEW_FIFO_LINE_SIZE
,
945 static const struct intel_watermark_params pineview_cursor_wm
= {
946 .fifo_size
= PINEVIEW_CURSOR_FIFO
,
947 .max_wm
= PINEVIEW_CURSOR_MAX_WM
,
948 .default_wm
= PINEVIEW_CURSOR_DFT_WM
,
949 .guard_size
= PINEVIEW_CURSOR_GUARD_WM
,
950 .cacheline_size
= PINEVIEW_FIFO_LINE_SIZE
,
952 static const struct intel_watermark_params pineview_cursor_hplloff_wm
= {
953 .fifo_size
= PINEVIEW_CURSOR_FIFO
,
954 .max_wm
= PINEVIEW_CURSOR_MAX_WM
,
955 .default_wm
= PINEVIEW_CURSOR_DFT_WM
,
956 .guard_size
= PINEVIEW_CURSOR_GUARD_WM
,
957 .cacheline_size
= PINEVIEW_FIFO_LINE_SIZE
,
959 static const struct intel_watermark_params g4x_wm_info
= {
960 .fifo_size
= G4X_FIFO_SIZE
,
961 .max_wm
= G4X_MAX_WM
,
962 .default_wm
= G4X_MAX_WM
,
964 .cacheline_size
= G4X_FIFO_LINE_SIZE
,
966 static const struct intel_watermark_params g4x_cursor_wm_info
= {
967 .fifo_size
= I965_CURSOR_FIFO
,
968 .max_wm
= I965_CURSOR_MAX_WM
,
969 .default_wm
= I965_CURSOR_DFT_WM
,
971 .cacheline_size
= G4X_FIFO_LINE_SIZE
,
973 static const struct intel_watermark_params valleyview_wm_info
= {
974 .fifo_size
= VALLEYVIEW_FIFO_SIZE
,
975 .max_wm
= VALLEYVIEW_MAX_WM
,
976 .default_wm
= VALLEYVIEW_MAX_WM
,
978 .cacheline_size
= G4X_FIFO_LINE_SIZE
,
980 static const struct intel_watermark_params valleyview_cursor_wm_info
= {
981 .fifo_size
= I965_CURSOR_FIFO
,
982 .max_wm
= VALLEYVIEW_CURSOR_MAX_WM
,
983 .default_wm
= I965_CURSOR_DFT_WM
,
985 .cacheline_size
= G4X_FIFO_LINE_SIZE
,
987 static const struct intel_watermark_params i965_cursor_wm_info
= {
988 .fifo_size
= I965_CURSOR_FIFO
,
989 .max_wm
= I965_CURSOR_MAX_WM
,
990 .default_wm
= I965_CURSOR_DFT_WM
,
992 .cacheline_size
= I915_FIFO_LINE_SIZE
,
994 static const struct intel_watermark_params i945_wm_info
= {
995 .fifo_size
= I945_FIFO_SIZE
,
996 .max_wm
= I915_MAX_WM
,
999 .cacheline_size
= I915_FIFO_LINE_SIZE
,
1001 static const struct intel_watermark_params i915_wm_info
= {
1002 .fifo_size
= I915_FIFO_SIZE
,
1003 .max_wm
= I915_MAX_WM
,
1006 .cacheline_size
= I915_FIFO_LINE_SIZE
,
1008 static const struct intel_watermark_params i830_a_wm_info
= {
1009 .fifo_size
= I855GM_FIFO_SIZE
,
1010 .max_wm
= I915_MAX_WM
,
1013 .cacheline_size
= I830_FIFO_LINE_SIZE
,
1015 static const struct intel_watermark_params i830_bc_wm_info
= {
1016 .fifo_size
= I855GM_FIFO_SIZE
,
1017 .max_wm
= I915_MAX_WM
/2,
1020 .cacheline_size
= I830_FIFO_LINE_SIZE
,
1022 static const struct intel_watermark_params i845_wm_info
= {
1023 .fifo_size
= I830_FIFO_SIZE
,
1024 .max_wm
= I915_MAX_WM
,
1027 .cacheline_size
= I830_FIFO_LINE_SIZE
,
1031 * intel_calculate_wm - calculate watermark level
1032 * @clock_in_khz: pixel clock
1033 * @wm: chip FIFO params
1034 * @pixel_size: display pixel size
1035 * @latency_ns: memory latency for the platform
1037 * Calculate the watermark level (the level at which the display plane will
1038 * start fetching from memory again). Each chip has a different display
1039 * FIFO size and allocation, so the caller needs to figure that out and pass
1040 * in the correct intel_watermark_params structure.
1042 * As the pixel clock runs, the FIFO will be drained at a rate that depends
1043 * on the pixel size. When it reaches the watermark level, it'll start
1044 * fetching FIFO line sized based chunks from memory until the FIFO fills
1045 * past the watermark point. If the FIFO drains completely, a FIFO underrun
1046 * will occur, and a display engine hang could result.
1048 static unsigned long intel_calculate_wm(unsigned long clock_in_khz
,
1049 const struct intel_watermark_params
*wm
,
1052 unsigned long latency_ns
)
1054 long entries_required
, wm_size
;
1057 * Note: we need to make sure we don't overflow for various clock &
1059 * clocks go from a few thousand to several hundred thousand.
1060 * latency is usually a few thousand
1062 entries_required
= ((clock_in_khz
/ 1000) * pixel_size
* latency_ns
) /
1064 entries_required
= DIV_ROUND_UP(entries_required
, wm
->cacheline_size
);
1066 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required
);
1068 wm_size
= fifo_size
- (entries_required
+ wm
->guard_size
);
1070 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size
);
1072 /* Don't promote wm_size to unsigned... */
1073 if (wm_size
> (long)wm
->max_wm
)
1074 wm_size
= wm
->max_wm
;
1076 wm_size
= wm
->default_wm
;
1080 static struct drm_crtc
*single_enabled_crtc(struct drm_device
*dev
)
1082 struct drm_crtc
*crtc
, *enabled
= NULL
;
1084 for_each_crtc(dev
, crtc
) {
1085 if (intel_crtc_active(crtc
)) {
1095 static void pineview_update_wm(struct drm_crtc
*unused_crtc
)
1097 struct drm_device
*dev
= unused_crtc
->dev
;
1098 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1099 struct drm_crtc
*crtc
;
1100 const struct cxsr_latency
*latency
;
1104 latency
= intel_get_cxsr_latency(IS_PINEVIEW_G(dev
), dev_priv
->is_ddr3
,
1105 dev_priv
->fsb_freq
, dev_priv
->mem_freq
);
1107 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1108 intel_set_memory_cxsr(dev_priv
, false);
1112 crtc
= single_enabled_crtc(dev
);
1114 const struct drm_display_mode
*adjusted_mode
;
1115 int pixel_size
= crtc
->primary
->fb
->bits_per_pixel
/ 8;
1118 adjusted_mode
= &to_intel_crtc(crtc
)->config
.adjusted_mode
;
1119 clock
= adjusted_mode
->crtc_clock
;
1122 wm
= intel_calculate_wm(clock
, &pineview_display_wm
,
1123 pineview_display_wm
.fifo_size
,
1124 pixel_size
, latency
->display_sr
);
1125 reg
= I915_READ(DSPFW1
);
1126 reg
&= ~DSPFW_SR_MASK
;
1127 reg
|= wm
<< DSPFW_SR_SHIFT
;
1128 I915_WRITE(DSPFW1
, reg
);
1129 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg
);
1132 wm
= intel_calculate_wm(clock
, &pineview_cursor_wm
,
1133 pineview_display_wm
.fifo_size
,
1134 pixel_size
, latency
->cursor_sr
);
1135 reg
= I915_READ(DSPFW3
);
1136 reg
&= ~DSPFW_CURSOR_SR_MASK
;
1137 reg
|= (wm
& 0x3f) << DSPFW_CURSOR_SR_SHIFT
;
1138 I915_WRITE(DSPFW3
, reg
);
1140 /* Display HPLL off SR */
1141 wm
= intel_calculate_wm(clock
, &pineview_display_hplloff_wm
,
1142 pineview_display_hplloff_wm
.fifo_size
,
1143 pixel_size
, latency
->display_hpll_disable
);
1144 reg
= I915_READ(DSPFW3
);
1145 reg
&= ~DSPFW_HPLL_SR_MASK
;
1146 reg
|= wm
& DSPFW_HPLL_SR_MASK
;
1147 I915_WRITE(DSPFW3
, reg
);
1149 /* cursor HPLL off SR */
1150 wm
= intel_calculate_wm(clock
, &pineview_cursor_hplloff_wm
,
1151 pineview_display_hplloff_wm
.fifo_size
,
1152 pixel_size
, latency
->cursor_hpll_disable
);
1153 reg
= I915_READ(DSPFW3
);
1154 reg
&= ~DSPFW_HPLL_CURSOR_MASK
;
1155 reg
|= (wm
& 0x3f) << DSPFW_HPLL_CURSOR_SHIFT
;
1156 I915_WRITE(DSPFW3
, reg
);
1157 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg
);
1159 intel_set_memory_cxsr(dev_priv
, true);
1161 intel_set_memory_cxsr(dev_priv
, false);
1165 static bool g4x_compute_wm0(struct drm_device
*dev
,
1167 const struct intel_watermark_params
*display
,
1168 int display_latency_ns
,
1169 const struct intel_watermark_params
*cursor
,
1170 int cursor_latency_ns
,
1174 struct drm_crtc
*crtc
;
1175 const struct drm_display_mode
*adjusted_mode
;
1176 int htotal
, hdisplay
, clock
, pixel_size
;
1177 int line_time_us
, line_count
;
1178 int entries
, tlb_miss
;
1180 crtc
= intel_get_crtc_for_plane(dev
, plane
);
1181 if (!intel_crtc_active(crtc
)) {
1182 *cursor_wm
= cursor
->guard_size
;
1183 *plane_wm
= display
->guard_size
;
1187 adjusted_mode
= &to_intel_crtc(crtc
)->config
.adjusted_mode
;
1188 clock
= adjusted_mode
->crtc_clock
;
1189 htotal
= adjusted_mode
->crtc_htotal
;
1190 hdisplay
= to_intel_crtc(crtc
)->config
.pipe_src_w
;
1191 pixel_size
= crtc
->primary
->fb
->bits_per_pixel
/ 8;
1193 /* Use the small buffer method to calculate plane watermark */
1194 entries
= ((clock
* pixel_size
/ 1000) * display_latency_ns
) / 1000;
1195 tlb_miss
= display
->fifo_size
*display
->cacheline_size
- hdisplay
* 8;
1197 entries
+= tlb_miss
;
1198 entries
= DIV_ROUND_UP(entries
, display
->cacheline_size
);
1199 *plane_wm
= entries
+ display
->guard_size
;
1200 if (*plane_wm
> (int)display
->max_wm
)
1201 *plane_wm
= display
->max_wm
;
1203 /* Use the large buffer method to calculate cursor watermark */
1204 line_time_us
= max(htotal
* 1000 / clock
, 1);
1205 line_count
= (cursor_latency_ns
/ line_time_us
+ 1000) / 1000;
1206 entries
= line_count
* to_intel_crtc(crtc
)->cursor_width
* pixel_size
;
1207 tlb_miss
= cursor
->fifo_size
*cursor
->cacheline_size
- hdisplay
* 8;
1209 entries
+= tlb_miss
;
1210 entries
= DIV_ROUND_UP(entries
, cursor
->cacheline_size
);
1211 *cursor_wm
= entries
+ cursor
->guard_size
;
1212 if (*cursor_wm
> (int)cursor
->max_wm
)
1213 *cursor_wm
= (int)cursor
->max_wm
;
1219 * Check the wm result.
1221 * If any calculated watermark values is larger than the maximum value that
1222 * can be programmed into the associated watermark register, that watermark
1225 static bool g4x_check_srwm(struct drm_device
*dev
,
1226 int display_wm
, int cursor_wm
,
1227 const struct intel_watermark_params
*display
,
1228 const struct intel_watermark_params
*cursor
)
1230 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1231 display_wm
, cursor_wm
);
1233 if (display_wm
> display
->max_wm
) {
1234 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1235 display_wm
, display
->max_wm
);
1239 if (cursor_wm
> cursor
->max_wm
) {
1240 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1241 cursor_wm
, cursor
->max_wm
);
1245 if (!(display_wm
|| cursor_wm
)) {
1246 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1253 static bool g4x_compute_srwm(struct drm_device
*dev
,
1256 const struct intel_watermark_params
*display
,
1257 const struct intel_watermark_params
*cursor
,
1258 int *display_wm
, int *cursor_wm
)
1260 struct drm_crtc
*crtc
;
1261 const struct drm_display_mode
*adjusted_mode
;
1262 int hdisplay
, htotal
, pixel_size
, clock
;
1263 unsigned long line_time_us
;
1264 int line_count
, line_size
;
1269 *display_wm
= *cursor_wm
= 0;
1273 crtc
= intel_get_crtc_for_plane(dev
, plane
);
1274 adjusted_mode
= &to_intel_crtc(crtc
)->config
.adjusted_mode
;
1275 clock
= adjusted_mode
->crtc_clock
;
1276 htotal
= adjusted_mode
->crtc_htotal
;
1277 hdisplay
= to_intel_crtc(crtc
)->config
.pipe_src_w
;
1278 pixel_size
= crtc
->primary
->fb
->bits_per_pixel
/ 8;
1280 line_time_us
= max(htotal
* 1000 / clock
, 1);
1281 line_count
= (latency_ns
/ line_time_us
+ 1000) / 1000;
1282 line_size
= hdisplay
* pixel_size
;
1284 /* Use the minimum of the small and large buffer method for primary */
1285 small
= ((clock
* pixel_size
/ 1000) * latency_ns
) / 1000;
1286 large
= line_count
* line_size
;
1288 entries
= DIV_ROUND_UP(min(small
, large
), display
->cacheline_size
);
1289 *display_wm
= entries
+ display
->guard_size
;
1291 /* calculate the self-refresh watermark for display cursor */
1292 entries
= line_count
* pixel_size
* to_intel_crtc(crtc
)->cursor_width
;
1293 entries
= DIV_ROUND_UP(entries
, cursor
->cacheline_size
);
1294 *cursor_wm
= entries
+ cursor
->guard_size
;
1296 return g4x_check_srwm(dev
,
1297 *display_wm
, *cursor_wm
,
1301 static bool vlv_compute_drain_latency(struct drm_crtc
*crtc
,
1307 int clock
= to_intel_crtc(crtc
)->config
.adjusted_mode
.crtc_clock
;
1309 if (WARN(clock
== 0, "Pixel clock is zero!\n"))
1312 if (WARN(pixel_size
== 0, "Pixel size is zero!\n"))
1315 entries
= DIV_ROUND_UP(clock
, 1000) * pixel_size
;
1316 *prec_mult
= (entries
> 128) ? DRAIN_LATENCY_PRECISION_64
:
1317 DRAIN_LATENCY_PRECISION_32
;
1318 *drain_latency
= (64 * (*prec_mult
) * 4) / entries
;
1320 if (*drain_latency
> DRAIN_LATENCY_MASK
)
1321 *drain_latency
= DRAIN_LATENCY_MASK
;
1327 * Update drain latency registers of memory arbiter
1329 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1330 * to be programmed. Each plane has a drain latency multiplier and a drain
1334 static void vlv_update_drain_latency(struct drm_crtc
*crtc
)
1336 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
1337 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1340 enum pipe pipe
= intel_crtc
->pipe
;
1341 int plane_prec
, prec_mult
, plane_dl
;
1343 plane_dl
= I915_READ(VLV_DDL(pipe
)) & ~(DDL_PLANE_PRECISION_64
|
1344 DRAIN_LATENCY_MASK
| DDL_CURSOR_PRECISION_64
|
1345 (DRAIN_LATENCY_MASK
<< DDL_CURSOR_SHIFT
));
1347 if (!intel_crtc_active(crtc
)) {
1348 I915_WRITE(VLV_DDL(pipe
), plane_dl
);
1352 /* Primary plane Drain Latency */
1353 pixel_size
= crtc
->primary
->fb
->bits_per_pixel
/ 8; /* BPP */
1354 if (vlv_compute_drain_latency(crtc
, pixel_size
, &prec_mult
, &drain_latency
)) {
1355 plane_prec
= (prec_mult
== DRAIN_LATENCY_PRECISION_64
) ?
1356 DDL_PLANE_PRECISION_64
:
1357 DDL_PLANE_PRECISION_32
;
1358 plane_dl
|= plane_prec
| drain_latency
;
1361 /* Cursor Drain Latency
1362 * BPP is always 4 for cursor
1366 /* Program cursor DL only if it is enabled */
1367 if (intel_crtc
->cursor_base
&&
1368 vlv_compute_drain_latency(crtc
, pixel_size
, &prec_mult
, &drain_latency
)) {
1369 plane_prec
= (prec_mult
== DRAIN_LATENCY_PRECISION_64
) ?
1370 DDL_CURSOR_PRECISION_64
:
1371 DDL_CURSOR_PRECISION_32
;
1372 plane_dl
|= plane_prec
| (drain_latency
<< DDL_CURSOR_SHIFT
);
1375 I915_WRITE(VLV_DDL(pipe
), plane_dl
);
1378 #define single_plane_enabled(mask) is_power_of_2(mask)
1380 static void valleyview_update_wm(struct drm_crtc
*crtc
)
1382 struct drm_device
*dev
= crtc
->dev
;
1383 static const int sr_latency_ns
= 12000;
1384 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1385 int planea_wm
, planeb_wm
, cursora_wm
, cursorb_wm
;
1386 int plane_sr
, cursor_sr
;
1387 int ignore_plane_sr
, ignore_cursor_sr
;
1388 unsigned int enabled
= 0;
1391 vlv_update_drain_latency(crtc
);
1393 if (g4x_compute_wm0(dev
, PIPE_A
,
1394 &valleyview_wm_info
, pessimal_latency_ns
,
1395 &valleyview_cursor_wm_info
, pessimal_latency_ns
,
1396 &planea_wm
, &cursora_wm
))
1397 enabled
|= 1 << PIPE_A
;
1399 if (g4x_compute_wm0(dev
, PIPE_B
,
1400 &valleyview_wm_info
, pessimal_latency_ns
,
1401 &valleyview_cursor_wm_info
, pessimal_latency_ns
,
1402 &planeb_wm
, &cursorb_wm
))
1403 enabled
|= 1 << PIPE_B
;
1405 if (single_plane_enabled(enabled
) &&
1406 g4x_compute_srwm(dev
, ffs(enabled
) - 1,
1408 &valleyview_wm_info
,
1409 &valleyview_cursor_wm_info
,
1410 &plane_sr
, &ignore_cursor_sr
) &&
1411 g4x_compute_srwm(dev
, ffs(enabled
) - 1,
1413 &valleyview_wm_info
,
1414 &valleyview_cursor_wm_info
,
1415 &ignore_plane_sr
, &cursor_sr
)) {
1416 cxsr_enabled
= true;
1418 cxsr_enabled
= false;
1419 intel_set_memory_cxsr(dev_priv
, false);
1420 plane_sr
= cursor_sr
= 0;
1423 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1424 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1425 planea_wm
, cursora_wm
,
1426 planeb_wm
, cursorb_wm
,
1427 plane_sr
, cursor_sr
);
1430 (plane_sr
<< DSPFW_SR_SHIFT
) |
1431 (cursorb_wm
<< DSPFW_CURSORB_SHIFT
) |
1432 (planeb_wm
<< DSPFW_PLANEB_SHIFT
) |
1433 (planea_wm
<< DSPFW_PLANEA_SHIFT
));
1435 (I915_READ(DSPFW2
) & ~DSPFW_CURSORA_MASK
) |
1436 (cursora_wm
<< DSPFW_CURSORA_SHIFT
));
1438 (I915_READ(DSPFW3
) & ~DSPFW_CURSOR_SR_MASK
) |
1439 (cursor_sr
<< DSPFW_CURSOR_SR_SHIFT
));
1442 intel_set_memory_cxsr(dev_priv
, true);
1445 static void cherryview_update_wm(struct drm_crtc
*crtc
)
1447 struct drm_device
*dev
= crtc
->dev
;
1448 static const int sr_latency_ns
= 12000;
1449 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1450 int planea_wm
, planeb_wm
, planec_wm
;
1451 int cursora_wm
, cursorb_wm
, cursorc_wm
;
1452 int plane_sr
, cursor_sr
;
1453 int ignore_plane_sr
, ignore_cursor_sr
;
1454 unsigned int enabled
= 0;
1457 vlv_update_drain_latency(crtc
);
1459 if (g4x_compute_wm0(dev
, PIPE_A
,
1460 &valleyview_wm_info
, pessimal_latency_ns
,
1461 &valleyview_cursor_wm_info
, pessimal_latency_ns
,
1462 &planea_wm
, &cursora_wm
))
1463 enabled
|= 1 << PIPE_A
;
1465 if (g4x_compute_wm0(dev
, PIPE_B
,
1466 &valleyview_wm_info
, pessimal_latency_ns
,
1467 &valleyview_cursor_wm_info
, pessimal_latency_ns
,
1468 &planeb_wm
, &cursorb_wm
))
1469 enabled
|= 1 << PIPE_B
;
1471 if (g4x_compute_wm0(dev
, PIPE_C
,
1472 &valleyview_wm_info
, pessimal_latency_ns
,
1473 &valleyview_cursor_wm_info
, pessimal_latency_ns
,
1474 &planec_wm
, &cursorc_wm
))
1475 enabled
|= 1 << PIPE_C
;
1477 if (single_plane_enabled(enabled
) &&
1478 g4x_compute_srwm(dev
, ffs(enabled
) - 1,
1480 &valleyview_wm_info
,
1481 &valleyview_cursor_wm_info
,
1482 &plane_sr
, &ignore_cursor_sr
) &&
1483 g4x_compute_srwm(dev
, ffs(enabled
) - 1,
1485 &valleyview_wm_info
,
1486 &valleyview_cursor_wm_info
,
1487 &ignore_plane_sr
, &cursor_sr
)) {
1488 cxsr_enabled
= true;
1490 cxsr_enabled
= false;
1491 intel_set_memory_cxsr(dev_priv
, false);
1492 plane_sr
= cursor_sr
= 0;
1495 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1496 "B: plane=%d, cursor=%d, C: plane=%d, cursor=%d, "
1497 "SR: plane=%d, cursor=%d\n",
1498 planea_wm
, cursora_wm
,
1499 planeb_wm
, cursorb_wm
,
1500 planec_wm
, cursorc_wm
,
1501 plane_sr
, cursor_sr
);
1504 (plane_sr
<< DSPFW_SR_SHIFT
) |
1505 (cursorb_wm
<< DSPFW_CURSORB_SHIFT
) |
1506 (planeb_wm
<< DSPFW_PLANEB_SHIFT
) |
1507 (planea_wm
<< DSPFW_PLANEA_SHIFT
));
1509 (I915_READ(DSPFW2
) & ~DSPFW_CURSORA_MASK
) |
1510 (cursora_wm
<< DSPFW_CURSORA_SHIFT
));
1512 (I915_READ(DSPFW3
) & ~DSPFW_CURSOR_SR_MASK
) |
1513 (cursor_sr
<< DSPFW_CURSOR_SR_SHIFT
));
1514 I915_WRITE(DSPFW9_CHV
,
1515 (I915_READ(DSPFW9_CHV
) & ~(DSPFW_PLANEC_MASK
|
1516 DSPFW_CURSORC_MASK
)) |
1517 (planec_wm
<< DSPFW_PLANEC_SHIFT
) |
1518 (cursorc_wm
<< DSPFW_CURSORC_SHIFT
));
1521 intel_set_memory_cxsr(dev_priv
, true);
1524 static void valleyview_update_sprite_wm(struct drm_plane
*plane
,
1525 struct drm_crtc
*crtc
,
1526 uint32_t sprite_width
,
1527 uint32_t sprite_height
,
1529 bool enabled
, bool scaled
)
1531 struct drm_device
*dev
= crtc
->dev
;
1532 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1533 int pipe
= to_intel_plane(plane
)->pipe
;
1534 int sprite
= to_intel_plane(plane
)->plane
;
1540 sprite_dl
= I915_READ(VLV_DDL(pipe
)) & ~(DDL_SPRITE_PRECISION_64(sprite
) |
1541 (DRAIN_LATENCY_MASK
<< DDL_SPRITE_SHIFT(sprite
)));
1543 if (enabled
&& vlv_compute_drain_latency(crtc
, pixel_size
, &prec_mult
,
1545 plane_prec
= (prec_mult
== DRAIN_LATENCY_PRECISION_64
) ?
1546 DDL_SPRITE_PRECISION_64(sprite
) :
1547 DDL_SPRITE_PRECISION_32(sprite
);
1548 sprite_dl
|= plane_prec
|
1549 (drain_latency
<< DDL_SPRITE_SHIFT(sprite
));
1552 I915_WRITE(VLV_DDL(pipe
), sprite_dl
);
1555 static void g4x_update_wm(struct drm_crtc
*crtc
)
1557 struct drm_device
*dev
= crtc
->dev
;
1558 static const int sr_latency_ns
= 12000;
1559 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1560 int planea_wm
, planeb_wm
, cursora_wm
, cursorb_wm
;
1561 int plane_sr
, cursor_sr
;
1562 unsigned int enabled
= 0;
1565 if (g4x_compute_wm0(dev
, PIPE_A
,
1566 &g4x_wm_info
, pessimal_latency_ns
,
1567 &g4x_cursor_wm_info
, pessimal_latency_ns
,
1568 &planea_wm
, &cursora_wm
))
1569 enabled
|= 1 << PIPE_A
;
1571 if (g4x_compute_wm0(dev
, PIPE_B
,
1572 &g4x_wm_info
, pessimal_latency_ns
,
1573 &g4x_cursor_wm_info
, pessimal_latency_ns
,
1574 &planeb_wm
, &cursorb_wm
))
1575 enabled
|= 1 << PIPE_B
;
1577 if (single_plane_enabled(enabled
) &&
1578 g4x_compute_srwm(dev
, ffs(enabled
) - 1,
1581 &g4x_cursor_wm_info
,
1582 &plane_sr
, &cursor_sr
)) {
1583 cxsr_enabled
= true;
1585 cxsr_enabled
= false;
1586 intel_set_memory_cxsr(dev_priv
, false);
1587 plane_sr
= cursor_sr
= 0;
1590 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1591 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1592 planea_wm
, cursora_wm
,
1593 planeb_wm
, cursorb_wm
,
1594 plane_sr
, cursor_sr
);
1597 (plane_sr
<< DSPFW_SR_SHIFT
) |
1598 (cursorb_wm
<< DSPFW_CURSORB_SHIFT
) |
1599 (planeb_wm
<< DSPFW_PLANEB_SHIFT
) |
1600 (planea_wm
<< DSPFW_PLANEA_SHIFT
));
1602 (I915_READ(DSPFW2
) & ~DSPFW_CURSORA_MASK
) |
1603 (cursora_wm
<< DSPFW_CURSORA_SHIFT
));
1604 /* HPLL off in SR has some issues on G4x... disable it */
1606 (I915_READ(DSPFW3
) & ~(DSPFW_HPLL_SR_EN
| DSPFW_CURSOR_SR_MASK
)) |
1607 (cursor_sr
<< DSPFW_CURSOR_SR_SHIFT
));
1610 intel_set_memory_cxsr(dev_priv
, true);
1613 static void i965_update_wm(struct drm_crtc
*unused_crtc
)
1615 struct drm_device
*dev
= unused_crtc
->dev
;
1616 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1617 struct drm_crtc
*crtc
;
1622 /* Calc sr entries for one plane configs */
1623 crtc
= single_enabled_crtc(dev
);
1625 /* self-refresh has much higher latency */
1626 static const int sr_latency_ns
= 12000;
1627 const struct drm_display_mode
*adjusted_mode
=
1628 &to_intel_crtc(crtc
)->config
.adjusted_mode
;
1629 int clock
= adjusted_mode
->crtc_clock
;
1630 int htotal
= adjusted_mode
->crtc_htotal
;
1631 int hdisplay
= to_intel_crtc(crtc
)->config
.pipe_src_w
;
1632 int pixel_size
= crtc
->primary
->fb
->bits_per_pixel
/ 8;
1633 unsigned long line_time_us
;
1636 line_time_us
= max(htotal
* 1000 / clock
, 1);
1638 /* Use ns/us then divide to preserve precision */
1639 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
1640 pixel_size
* hdisplay
;
1641 entries
= DIV_ROUND_UP(entries
, I915_FIFO_LINE_SIZE
);
1642 srwm
= I965_FIFO_SIZE
- entries
;
1646 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1649 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
1650 pixel_size
* to_intel_crtc(crtc
)->cursor_width
;
1651 entries
= DIV_ROUND_UP(entries
,
1652 i965_cursor_wm_info
.cacheline_size
);
1653 cursor_sr
= i965_cursor_wm_info
.fifo_size
-
1654 (entries
+ i965_cursor_wm_info
.guard_size
);
1656 if (cursor_sr
> i965_cursor_wm_info
.max_wm
)
1657 cursor_sr
= i965_cursor_wm_info
.max_wm
;
1659 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1660 "cursor %d\n", srwm
, cursor_sr
);
1662 cxsr_enabled
= true;
1664 cxsr_enabled
= false;
1665 /* Turn off self refresh if both pipes are enabled */
1666 intel_set_memory_cxsr(dev_priv
, false);
1669 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1672 /* 965 has limitations... */
1673 I915_WRITE(DSPFW1
, (srwm
<< DSPFW_SR_SHIFT
) |
1674 (8 << DSPFW_CURSORB_SHIFT
) |
1675 (8 << DSPFW_PLANEB_SHIFT
) |
1676 (8 << DSPFW_PLANEA_SHIFT
));
1677 I915_WRITE(DSPFW2
, (8 << DSPFW_CURSORA_SHIFT
) |
1678 (8 << DSPFW_PLANEC_SHIFT_OLD
));
1679 /* update cursor SR watermark */
1680 I915_WRITE(DSPFW3
, (cursor_sr
<< DSPFW_CURSOR_SR_SHIFT
));
1683 intel_set_memory_cxsr(dev_priv
, true);
1686 static void i9xx_update_wm(struct drm_crtc
*unused_crtc
)
1688 struct drm_device
*dev
= unused_crtc
->dev
;
1689 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1690 const struct intel_watermark_params
*wm_info
;
1695 int planea_wm
, planeb_wm
;
1696 struct drm_crtc
*crtc
, *enabled
= NULL
;
1699 wm_info
= &i945_wm_info
;
1700 else if (!IS_GEN2(dev
))
1701 wm_info
= &i915_wm_info
;
1703 wm_info
= &i830_a_wm_info
;
1705 fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 0);
1706 crtc
= intel_get_crtc_for_plane(dev
, 0);
1707 if (intel_crtc_active(crtc
)) {
1708 const struct drm_display_mode
*adjusted_mode
;
1709 int cpp
= crtc
->primary
->fb
->bits_per_pixel
/ 8;
1713 adjusted_mode
= &to_intel_crtc(crtc
)->config
.adjusted_mode
;
1714 planea_wm
= intel_calculate_wm(adjusted_mode
->crtc_clock
,
1715 wm_info
, fifo_size
, cpp
,
1716 pessimal_latency_ns
);
1719 planea_wm
= fifo_size
- wm_info
->guard_size
;
1720 if (planea_wm
> (long)wm_info
->max_wm
)
1721 planea_wm
= wm_info
->max_wm
;
1725 wm_info
= &i830_bc_wm_info
;
1727 fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 1);
1728 crtc
= intel_get_crtc_for_plane(dev
, 1);
1729 if (intel_crtc_active(crtc
)) {
1730 const struct drm_display_mode
*adjusted_mode
;
1731 int cpp
= crtc
->primary
->fb
->bits_per_pixel
/ 8;
1735 adjusted_mode
= &to_intel_crtc(crtc
)->config
.adjusted_mode
;
1736 planeb_wm
= intel_calculate_wm(adjusted_mode
->crtc_clock
,
1737 wm_info
, fifo_size
, cpp
,
1738 pessimal_latency_ns
);
1739 if (enabled
== NULL
)
1744 planeb_wm
= fifo_size
- wm_info
->guard_size
;
1745 if (planeb_wm
> (long)wm_info
->max_wm
)
1746 planeb_wm
= wm_info
->max_wm
;
1749 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm
, planeb_wm
);
1751 if (IS_I915GM(dev
) && enabled
) {
1752 struct drm_i915_gem_object
*obj
;
1754 obj
= intel_fb_obj(enabled
->primary
->fb
);
1756 /* self-refresh seems busted with untiled */
1757 if (obj
->tiling_mode
== I915_TILING_NONE
)
1762 * Overlay gets an aggressive default since video jitter is bad.
1766 /* Play safe and disable self-refresh before adjusting watermarks. */
1767 intel_set_memory_cxsr(dev_priv
, false);
1769 /* Calc sr entries for one plane configs */
1770 if (HAS_FW_BLC(dev
) && enabled
) {
1771 /* self-refresh has much higher latency */
1772 static const int sr_latency_ns
= 6000;
1773 const struct drm_display_mode
*adjusted_mode
=
1774 &to_intel_crtc(enabled
)->config
.adjusted_mode
;
1775 int clock
= adjusted_mode
->crtc_clock
;
1776 int htotal
= adjusted_mode
->crtc_htotal
;
1777 int hdisplay
= to_intel_crtc(enabled
)->config
.pipe_src_w
;
1778 int pixel_size
= enabled
->primary
->fb
->bits_per_pixel
/ 8;
1779 unsigned long line_time_us
;
1782 line_time_us
= max(htotal
* 1000 / clock
, 1);
1784 /* Use ns/us then divide to preserve precision */
1785 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
1786 pixel_size
* hdisplay
;
1787 entries
= DIV_ROUND_UP(entries
, wm_info
->cacheline_size
);
1788 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries
);
1789 srwm
= wm_info
->fifo_size
- entries
;
1793 if (IS_I945G(dev
) || IS_I945GM(dev
))
1794 I915_WRITE(FW_BLC_SELF
,
1795 FW_BLC_SELF_FIFO_MASK
| (srwm
& 0xff));
1796 else if (IS_I915GM(dev
))
1797 I915_WRITE(FW_BLC_SELF
, srwm
& 0x3f);
1800 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1801 planea_wm
, planeb_wm
, cwm
, srwm
);
1803 fwater_lo
= ((planeb_wm
& 0x3f) << 16) | (planea_wm
& 0x3f);
1804 fwater_hi
= (cwm
& 0x1f);
1806 /* Set request length to 8 cachelines per fetch */
1807 fwater_lo
= fwater_lo
| (1 << 24) | (1 << 8);
1808 fwater_hi
= fwater_hi
| (1 << 8);
1810 I915_WRITE(FW_BLC
, fwater_lo
);
1811 I915_WRITE(FW_BLC2
, fwater_hi
);
1814 intel_set_memory_cxsr(dev_priv
, true);
1817 static void i845_update_wm(struct drm_crtc
*unused_crtc
)
1819 struct drm_device
*dev
= unused_crtc
->dev
;
1820 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1821 struct drm_crtc
*crtc
;
1822 const struct drm_display_mode
*adjusted_mode
;
1826 crtc
= single_enabled_crtc(dev
);
1830 adjusted_mode
= &to_intel_crtc(crtc
)->config
.adjusted_mode
;
1831 planea_wm
= intel_calculate_wm(adjusted_mode
->crtc_clock
,
1833 dev_priv
->display
.get_fifo_size(dev
, 0),
1834 4, pessimal_latency_ns
);
1835 fwater_lo
= I915_READ(FW_BLC
) & ~0xfff;
1836 fwater_lo
|= (3<<8) | planea_wm
;
1838 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm
);
1840 I915_WRITE(FW_BLC
, fwater_lo
);
1843 static uint32_t ilk_pipe_pixel_rate(struct drm_device
*dev
,
1844 struct drm_crtc
*crtc
)
1846 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1847 uint32_t pixel_rate
;
1849 pixel_rate
= intel_crtc
->config
.adjusted_mode
.crtc_clock
;
1851 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1852 * adjust the pixel_rate here. */
1854 if (intel_crtc
->config
.pch_pfit
.enabled
) {
1855 uint64_t pipe_w
, pipe_h
, pfit_w
, pfit_h
;
1856 uint32_t pfit_size
= intel_crtc
->config
.pch_pfit
.size
;
1858 pipe_w
= intel_crtc
->config
.pipe_src_w
;
1859 pipe_h
= intel_crtc
->config
.pipe_src_h
;
1860 pfit_w
= (pfit_size
>> 16) & 0xFFFF;
1861 pfit_h
= pfit_size
& 0xFFFF;
1862 if (pipe_w
< pfit_w
)
1864 if (pipe_h
< pfit_h
)
1867 pixel_rate
= div_u64((uint64_t) pixel_rate
* pipe_w
* pipe_h
,
1874 /* latency must be in 0.1us units. */
1875 static uint32_t ilk_wm_method1(uint32_t pixel_rate
, uint8_t bytes_per_pixel
,
1880 if (WARN(latency
== 0, "Latency value missing\n"))
1883 ret
= (uint64_t) pixel_rate
* bytes_per_pixel
* latency
;
1884 ret
= DIV_ROUND_UP_ULL(ret
, 64 * 10000) + 2;
1889 /* latency must be in 0.1us units. */
1890 static uint32_t ilk_wm_method2(uint32_t pixel_rate
, uint32_t pipe_htotal
,
1891 uint32_t horiz_pixels
, uint8_t bytes_per_pixel
,
1896 if (WARN(latency
== 0, "Latency value missing\n"))
1899 ret
= (latency
* pixel_rate
) / (pipe_htotal
* 10000);
1900 ret
= (ret
+ 1) * horiz_pixels
* bytes_per_pixel
;
1901 ret
= DIV_ROUND_UP(ret
, 64) + 2;
1905 static uint32_t ilk_wm_fbc(uint32_t pri_val
, uint32_t horiz_pixels
,
1906 uint8_t bytes_per_pixel
)
1908 return DIV_ROUND_UP(pri_val
* 64, horiz_pixels
* bytes_per_pixel
) + 2;
1911 struct ilk_pipe_wm_parameters
{
1913 uint32_t pipe_htotal
;
1914 uint32_t pixel_rate
;
1915 struct intel_plane_wm_parameters pri
;
1916 struct intel_plane_wm_parameters spr
;
1917 struct intel_plane_wm_parameters cur
;
1920 struct ilk_wm_maximums
{
1927 /* used in computing the new watermarks state */
1928 struct intel_wm_config
{
1929 unsigned int num_pipes_active
;
1930 bool sprites_enabled
;
1931 bool sprites_scaled
;
1935 * For both WM_PIPE and WM_LP.
1936 * mem_value must be in 0.1us units.
1938 static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters
*params
,
1942 uint32_t method1
, method2
;
1944 if (!params
->active
|| !params
->pri
.enabled
)
1947 method1
= ilk_wm_method1(params
->pixel_rate
,
1948 params
->pri
.bytes_per_pixel
,
1954 method2
= ilk_wm_method2(params
->pixel_rate
,
1955 params
->pipe_htotal
,
1956 params
->pri
.horiz_pixels
,
1957 params
->pri
.bytes_per_pixel
,
1960 return min(method1
, method2
);
1964 * For both WM_PIPE and WM_LP.
1965 * mem_value must be in 0.1us units.
1967 static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters
*params
,
1970 uint32_t method1
, method2
;
1972 if (!params
->active
|| !params
->spr
.enabled
)
1975 method1
= ilk_wm_method1(params
->pixel_rate
,
1976 params
->spr
.bytes_per_pixel
,
1978 method2
= ilk_wm_method2(params
->pixel_rate
,
1979 params
->pipe_htotal
,
1980 params
->spr
.horiz_pixels
,
1981 params
->spr
.bytes_per_pixel
,
1983 return min(method1
, method2
);
1987 * For both WM_PIPE and WM_LP.
1988 * mem_value must be in 0.1us units.
1990 static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters
*params
,
1993 if (!params
->active
|| !params
->cur
.enabled
)
1996 return ilk_wm_method2(params
->pixel_rate
,
1997 params
->pipe_htotal
,
1998 params
->cur
.horiz_pixels
,
1999 params
->cur
.bytes_per_pixel
,
2003 /* Only for WM_LP. */
2004 static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters
*params
,
2007 if (!params
->active
|| !params
->pri
.enabled
)
2010 return ilk_wm_fbc(pri_val
,
2011 params
->pri
.horiz_pixels
,
2012 params
->pri
.bytes_per_pixel
);
2015 static unsigned int ilk_display_fifo_size(const struct drm_device
*dev
)
2017 if (INTEL_INFO(dev
)->gen
>= 8)
2019 else if (INTEL_INFO(dev
)->gen
>= 7)
2025 static unsigned int ilk_plane_wm_reg_max(const struct drm_device
*dev
,
2026 int level
, bool is_sprite
)
2028 if (INTEL_INFO(dev
)->gen
>= 8)
2029 /* BDW primary/sprite plane watermarks */
2030 return level
== 0 ? 255 : 2047;
2031 else if (INTEL_INFO(dev
)->gen
>= 7)
2032 /* IVB/HSW primary/sprite plane watermarks */
2033 return level
== 0 ? 127 : 1023;
2034 else if (!is_sprite
)
2035 /* ILK/SNB primary plane watermarks */
2036 return level
== 0 ? 127 : 511;
2038 /* ILK/SNB sprite plane watermarks */
2039 return level
== 0 ? 63 : 255;
2042 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device
*dev
,
2045 if (INTEL_INFO(dev
)->gen
>= 7)
2046 return level
== 0 ? 63 : 255;
2048 return level
== 0 ? 31 : 63;
2051 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device
*dev
)
2053 if (INTEL_INFO(dev
)->gen
>= 8)
2059 /* Calculate the maximum primary/sprite plane watermark */
2060 static unsigned int ilk_plane_wm_max(const struct drm_device
*dev
,
2062 const struct intel_wm_config
*config
,
2063 enum intel_ddb_partitioning ddb_partitioning
,
2066 unsigned int fifo_size
= ilk_display_fifo_size(dev
);
2068 /* if sprites aren't enabled, sprites get nothing */
2069 if (is_sprite
&& !config
->sprites_enabled
)
2072 /* HSW allows LP1+ watermarks even with multiple pipes */
2073 if (level
== 0 || config
->num_pipes_active
> 1) {
2074 fifo_size
/= INTEL_INFO(dev
)->num_pipes
;
2077 * For some reason the non self refresh
2078 * FIFO size is only half of the self
2079 * refresh FIFO size on ILK/SNB.
2081 if (INTEL_INFO(dev
)->gen
<= 6)
2085 if (config
->sprites_enabled
) {
2086 /* level 0 is always calculated with 1:1 split */
2087 if (level
> 0 && ddb_partitioning
== INTEL_DDB_PART_5_6
) {
2096 /* clamp to max that the registers can hold */
2097 return min(fifo_size
, ilk_plane_wm_reg_max(dev
, level
, is_sprite
));
2100 /* Calculate the maximum cursor plane watermark */
2101 static unsigned int ilk_cursor_wm_max(const struct drm_device
*dev
,
2103 const struct intel_wm_config
*config
)
2105 /* HSW LP1+ watermarks w/ multiple pipes */
2106 if (level
> 0 && config
->num_pipes_active
> 1)
2109 /* otherwise just report max that registers can hold */
2110 return ilk_cursor_wm_reg_max(dev
, level
);
2113 static void ilk_compute_wm_maximums(const struct drm_device
*dev
,
2115 const struct intel_wm_config
*config
,
2116 enum intel_ddb_partitioning ddb_partitioning
,
2117 struct ilk_wm_maximums
*max
)
2119 max
->pri
= ilk_plane_wm_max(dev
, level
, config
, ddb_partitioning
, false);
2120 max
->spr
= ilk_plane_wm_max(dev
, level
, config
, ddb_partitioning
, true);
2121 max
->cur
= ilk_cursor_wm_max(dev
, level
, config
);
2122 max
->fbc
= ilk_fbc_wm_reg_max(dev
);
2125 static void ilk_compute_wm_reg_maximums(struct drm_device
*dev
,
2127 struct ilk_wm_maximums
*max
)
2129 max
->pri
= ilk_plane_wm_reg_max(dev
, level
, false);
2130 max
->spr
= ilk_plane_wm_reg_max(dev
, level
, true);
2131 max
->cur
= ilk_cursor_wm_reg_max(dev
, level
);
2132 max
->fbc
= ilk_fbc_wm_reg_max(dev
);
2135 static bool ilk_validate_wm_level(int level
,
2136 const struct ilk_wm_maximums
*max
,
2137 struct intel_wm_level
*result
)
2141 /* already determined to be invalid? */
2142 if (!result
->enable
)
2145 result
->enable
= result
->pri_val
<= max
->pri
&&
2146 result
->spr_val
<= max
->spr
&&
2147 result
->cur_val
<= max
->cur
;
2149 ret
= result
->enable
;
2152 * HACK until we can pre-compute everything,
2153 * and thus fail gracefully if LP0 watermarks
2156 if (level
== 0 && !result
->enable
) {
2157 if (result
->pri_val
> max
->pri
)
2158 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2159 level
, result
->pri_val
, max
->pri
);
2160 if (result
->spr_val
> max
->spr
)
2161 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2162 level
, result
->spr_val
, max
->spr
);
2163 if (result
->cur_val
> max
->cur
)
2164 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2165 level
, result
->cur_val
, max
->cur
);
2167 result
->pri_val
= min_t(uint32_t, result
->pri_val
, max
->pri
);
2168 result
->spr_val
= min_t(uint32_t, result
->spr_val
, max
->spr
);
2169 result
->cur_val
= min_t(uint32_t, result
->cur_val
, max
->cur
);
2170 result
->enable
= true;
2176 static void ilk_compute_wm_level(const struct drm_i915_private
*dev_priv
,
2178 const struct ilk_pipe_wm_parameters
*p
,
2179 struct intel_wm_level
*result
)
2181 uint16_t pri_latency
= dev_priv
->wm
.pri_latency
[level
];
2182 uint16_t spr_latency
= dev_priv
->wm
.spr_latency
[level
];
2183 uint16_t cur_latency
= dev_priv
->wm
.cur_latency
[level
];
2185 /* WM1+ latency values stored in 0.5us units */
2192 result
->pri_val
= ilk_compute_pri_wm(p
, pri_latency
, level
);
2193 result
->spr_val
= ilk_compute_spr_wm(p
, spr_latency
);
2194 result
->cur_val
= ilk_compute_cur_wm(p
, cur_latency
);
2195 result
->fbc_val
= ilk_compute_fbc_wm(p
, result
->pri_val
);
2196 result
->enable
= true;
2200 hsw_compute_linetime_wm(struct drm_device
*dev
, struct drm_crtc
*crtc
)
2202 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2203 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2204 struct drm_display_mode
*mode
= &intel_crtc
->config
.adjusted_mode
;
2205 u32 linetime
, ips_linetime
;
2207 if (!intel_crtc_active(crtc
))
2210 /* The WM are computed with base on how long it takes to fill a single
2211 * row at the given clock rate, multiplied by 8.
2213 linetime
= DIV_ROUND_CLOSEST(mode
->crtc_htotal
* 1000 * 8,
2215 ips_linetime
= DIV_ROUND_CLOSEST(mode
->crtc_htotal
* 1000 * 8,
2216 intel_ddi_get_cdclk_freq(dev_priv
));
2218 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime
) |
2219 PIPE_WM_LINETIME_TIME(linetime
);
2222 static void intel_read_wm_latency(struct drm_device
*dev
, uint16_t wm
[5])
2224 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2226 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2227 uint64_t sskpd
= I915_READ64(MCH_SSKPD
);
2229 wm
[0] = (sskpd
>> 56) & 0xFF;
2231 wm
[0] = sskpd
& 0xF;
2232 wm
[1] = (sskpd
>> 4) & 0xFF;
2233 wm
[2] = (sskpd
>> 12) & 0xFF;
2234 wm
[3] = (sskpd
>> 20) & 0x1FF;
2235 wm
[4] = (sskpd
>> 32) & 0x1FF;
2236 } else if (INTEL_INFO(dev
)->gen
>= 6) {
2237 uint32_t sskpd
= I915_READ(MCH_SSKPD
);
2239 wm
[0] = (sskpd
>> SSKPD_WM0_SHIFT
) & SSKPD_WM_MASK
;
2240 wm
[1] = (sskpd
>> SSKPD_WM1_SHIFT
) & SSKPD_WM_MASK
;
2241 wm
[2] = (sskpd
>> SSKPD_WM2_SHIFT
) & SSKPD_WM_MASK
;
2242 wm
[3] = (sskpd
>> SSKPD_WM3_SHIFT
) & SSKPD_WM_MASK
;
2243 } else if (INTEL_INFO(dev
)->gen
>= 5) {
2244 uint32_t mltr
= I915_READ(MLTR_ILK
);
2246 /* ILK primary LP0 latency is 700 ns */
2248 wm
[1] = (mltr
>> MLTR_WM1_SHIFT
) & ILK_SRLT_MASK
;
2249 wm
[2] = (mltr
>> MLTR_WM2_SHIFT
) & ILK_SRLT_MASK
;
2253 static void intel_fixup_spr_wm_latency(struct drm_device
*dev
, uint16_t wm
[5])
2255 /* ILK sprite LP0 latency is 1300 ns */
2256 if (INTEL_INFO(dev
)->gen
== 5)
2260 static void intel_fixup_cur_wm_latency(struct drm_device
*dev
, uint16_t wm
[5])
2262 /* ILK cursor LP0 latency is 1300 ns */
2263 if (INTEL_INFO(dev
)->gen
== 5)
2266 /* WaDoubleCursorLP3Latency:ivb */
2267 if (IS_IVYBRIDGE(dev
))
2271 int ilk_wm_max_level(const struct drm_device
*dev
)
2273 /* how many WM levels are we expecting */
2274 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2276 else if (INTEL_INFO(dev
)->gen
>= 6)
2281 static void intel_print_wm_latency(struct drm_device
*dev
,
2283 const uint16_t wm
[5])
2285 int level
, max_level
= ilk_wm_max_level(dev
);
2287 for (level
= 0; level
<= max_level
; level
++) {
2288 unsigned int latency
= wm
[level
];
2291 DRM_ERROR("%s WM%d latency not provided\n",
2296 /* WM1+ latency values in 0.5us units */
2300 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2301 name
, level
, wm
[level
],
2302 latency
/ 10, latency
% 10);
2306 static bool ilk_increase_wm_latency(struct drm_i915_private
*dev_priv
,
2307 uint16_t wm
[5], uint16_t min
)
2309 int level
, max_level
= ilk_wm_max_level(dev_priv
->dev
);
2314 wm
[0] = max(wm
[0], min
);
2315 for (level
= 1; level
<= max_level
; level
++)
2316 wm
[level
] = max_t(uint16_t, wm
[level
], DIV_ROUND_UP(min
, 5));
2321 static void snb_wm_latency_quirk(struct drm_device
*dev
)
2323 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2327 * The BIOS provided WM memory latency values are often
2328 * inadequate for high resolution displays. Adjust them.
2330 changed
= ilk_increase_wm_latency(dev_priv
, dev_priv
->wm
.pri_latency
, 12) |
2331 ilk_increase_wm_latency(dev_priv
, dev_priv
->wm
.spr_latency
, 12) |
2332 ilk_increase_wm_latency(dev_priv
, dev_priv
->wm
.cur_latency
, 12);
2337 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2338 intel_print_wm_latency(dev
, "Primary", dev_priv
->wm
.pri_latency
);
2339 intel_print_wm_latency(dev
, "Sprite", dev_priv
->wm
.spr_latency
);
2340 intel_print_wm_latency(dev
, "Cursor", dev_priv
->wm
.cur_latency
);
2343 static void ilk_setup_wm_latency(struct drm_device
*dev
)
2345 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2347 intel_read_wm_latency(dev
, dev_priv
->wm
.pri_latency
);
2349 memcpy(dev_priv
->wm
.spr_latency
, dev_priv
->wm
.pri_latency
,
2350 sizeof(dev_priv
->wm
.pri_latency
));
2351 memcpy(dev_priv
->wm
.cur_latency
, dev_priv
->wm
.pri_latency
,
2352 sizeof(dev_priv
->wm
.pri_latency
));
2354 intel_fixup_spr_wm_latency(dev
, dev_priv
->wm
.spr_latency
);
2355 intel_fixup_cur_wm_latency(dev
, dev_priv
->wm
.cur_latency
);
2357 intel_print_wm_latency(dev
, "Primary", dev_priv
->wm
.pri_latency
);
2358 intel_print_wm_latency(dev
, "Sprite", dev_priv
->wm
.spr_latency
);
2359 intel_print_wm_latency(dev
, "Cursor", dev_priv
->wm
.cur_latency
);
2362 snb_wm_latency_quirk(dev
);
2365 static void ilk_compute_wm_parameters(struct drm_crtc
*crtc
,
2366 struct ilk_pipe_wm_parameters
*p
)
2368 struct drm_device
*dev
= crtc
->dev
;
2369 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2370 enum pipe pipe
= intel_crtc
->pipe
;
2371 struct drm_plane
*plane
;
2373 if (!intel_crtc_active(crtc
))
2377 p
->pipe_htotal
= intel_crtc
->config
.adjusted_mode
.crtc_htotal
;
2378 p
->pixel_rate
= ilk_pipe_pixel_rate(dev
, crtc
);
2379 p
->pri
.bytes_per_pixel
= crtc
->primary
->fb
->bits_per_pixel
/ 8;
2380 p
->cur
.bytes_per_pixel
= 4;
2381 p
->pri
.horiz_pixels
= intel_crtc
->config
.pipe_src_w
;
2382 p
->cur
.horiz_pixels
= intel_crtc
->cursor_width
;
2383 /* TODO: for now, assume primary and cursor planes are always enabled. */
2384 p
->pri
.enabled
= true;
2385 p
->cur
.enabled
= true;
2387 drm_for_each_legacy_plane(plane
, &dev
->mode_config
.plane_list
) {
2388 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
2390 if (intel_plane
->pipe
== pipe
) {
2391 p
->spr
= intel_plane
->wm
;
2397 static void ilk_compute_wm_config(struct drm_device
*dev
,
2398 struct intel_wm_config
*config
)
2400 struct intel_crtc
*intel_crtc
;
2402 /* Compute the currently _active_ config */
2403 for_each_intel_crtc(dev
, intel_crtc
) {
2404 const struct intel_pipe_wm
*wm
= &intel_crtc
->wm
.active
;
2406 if (!wm
->pipe_enabled
)
2409 config
->sprites_enabled
|= wm
->sprites_enabled
;
2410 config
->sprites_scaled
|= wm
->sprites_scaled
;
2411 config
->num_pipes_active
++;
2415 /* Compute new watermarks for the pipe */
2416 static bool intel_compute_pipe_wm(struct drm_crtc
*crtc
,
2417 const struct ilk_pipe_wm_parameters
*params
,
2418 struct intel_pipe_wm
*pipe_wm
)
2420 struct drm_device
*dev
= crtc
->dev
;
2421 const struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2422 int level
, max_level
= ilk_wm_max_level(dev
);
2423 /* LP0 watermark maximums depend on this pipe alone */
2424 struct intel_wm_config config
= {
2425 .num_pipes_active
= 1,
2426 .sprites_enabled
= params
->spr
.enabled
,
2427 .sprites_scaled
= params
->spr
.scaled
,
2429 struct ilk_wm_maximums max
;
2431 pipe_wm
->pipe_enabled
= params
->active
;
2432 pipe_wm
->sprites_enabled
= params
->spr
.enabled
;
2433 pipe_wm
->sprites_scaled
= params
->spr
.scaled
;
2435 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2436 if (INTEL_INFO(dev
)->gen
<= 6 && params
->spr
.enabled
)
2439 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2440 if (params
->spr
.scaled
)
2443 ilk_compute_wm_level(dev_priv
, 0, params
, &pipe_wm
->wm
[0]);
2445 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2446 pipe_wm
->linetime
= hsw_compute_linetime_wm(dev
, crtc
);
2448 /* LP0 watermarks always use 1/2 DDB partitioning */
2449 ilk_compute_wm_maximums(dev
, 0, &config
, INTEL_DDB_PART_1_2
, &max
);
2451 /* At least LP0 must be valid */
2452 if (!ilk_validate_wm_level(0, &max
, &pipe_wm
->wm
[0]))
2455 ilk_compute_wm_reg_maximums(dev
, 1, &max
);
2457 for (level
= 1; level
<= max_level
; level
++) {
2458 struct intel_wm_level wm
= {};
2460 ilk_compute_wm_level(dev_priv
, level
, params
, &wm
);
2463 * Disable any watermark level that exceeds the
2464 * register maximums since such watermarks are
2467 if (!ilk_validate_wm_level(level
, &max
, &wm
))
2470 pipe_wm
->wm
[level
] = wm
;
2477 * Merge the watermarks from all active pipes for a specific level.
2479 static void ilk_merge_wm_level(struct drm_device
*dev
,
2481 struct intel_wm_level
*ret_wm
)
2483 const struct intel_crtc
*intel_crtc
;
2485 ret_wm
->enable
= true;
2487 for_each_intel_crtc(dev
, intel_crtc
) {
2488 const struct intel_pipe_wm
*active
= &intel_crtc
->wm
.active
;
2489 const struct intel_wm_level
*wm
= &active
->wm
[level
];
2491 if (!active
->pipe_enabled
)
2495 * The watermark values may have been used in the past,
2496 * so we must maintain them in the registers for some
2497 * time even if the level is now disabled.
2500 ret_wm
->enable
= false;
2502 ret_wm
->pri_val
= max(ret_wm
->pri_val
, wm
->pri_val
);
2503 ret_wm
->spr_val
= max(ret_wm
->spr_val
, wm
->spr_val
);
2504 ret_wm
->cur_val
= max(ret_wm
->cur_val
, wm
->cur_val
);
2505 ret_wm
->fbc_val
= max(ret_wm
->fbc_val
, wm
->fbc_val
);
2510 * Merge all low power watermarks for all active pipes.
2512 static void ilk_wm_merge(struct drm_device
*dev
,
2513 const struct intel_wm_config
*config
,
2514 const struct ilk_wm_maximums
*max
,
2515 struct intel_pipe_wm
*merged
)
2517 int level
, max_level
= ilk_wm_max_level(dev
);
2518 int last_enabled_level
= max_level
;
2520 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2521 if ((INTEL_INFO(dev
)->gen
<= 6 || IS_IVYBRIDGE(dev
)) &&
2522 config
->num_pipes_active
> 1)
2525 /* ILK: FBC WM must be disabled always */
2526 merged
->fbc_wm_enabled
= INTEL_INFO(dev
)->gen
>= 6;
2528 /* merge each WM1+ level */
2529 for (level
= 1; level
<= max_level
; level
++) {
2530 struct intel_wm_level
*wm
= &merged
->wm
[level
];
2532 ilk_merge_wm_level(dev
, level
, wm
);
2534 if (level
> last_enabled_level
)
2536 else if (!ilk_validate_wm_level(level
, max
, wm
))
2537 /* make sure all following levels get disabled */
2538 last_enabled_level
= level
- 1;
2541 * The spec says it is preferred to disable
2542 * FBC WMs instead of disabling a WM level.
2544 if (wm
->fbc_val
> max
->fbc
) {
2546 merged
->fbc_wm_enabled
= false;
2551 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2553 * FIXME this is racy. FBC might get enabled later.
2554 * What we should check here is whether FBC can be
2555 * enabled sometime later.
2557 if (IS_GEN5(dev
) && !merged
->fbc_wm_enabled
&& intel_fbc_enabled(dev
)) {
2558 for (level
= 2; level
<= max_level
; level
++) {
2559 struct intel_wm_level
*wm
= &merged
->wm
[level
];
2566 static int ilk_wm_lp_to_level(int wm_lp
, const struct intel_pipe_wm
*pipe_wm
)
2568 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2569 return wm_lp
+ (wm_lp
>= 2 && pipe_wm
->wm
[4].enable
);
2572 /* The value we need to program into the WM_LPx latency field */
2573 static unsigned int ilk_wm_lp_latency(struct drm_device
*dev
, int level
)
2575 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2577 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2580 return dev_priv
->wm
.pri_latency
[level
];
2583 static void ilk_compute_wm_results(struct drm_device
*dev
,
2584 const struct intel_pipe_wm
*merged
,
2585 enum intel_ddb_partitioning partitioning
,
2586 struct ilk_wm_values
*results
)
2588 struct intel_crtc
*intel_crtc
;
2591 results
->enable_fbc_wm
= merged
->fbc_wm_enabled
;
2592 results
->partitioning
= partitioning
;
2594 /* LP1+ register values */
2595 for (wm_lp
= 1; wm_lp
<= 3; wm_lp
++) {
2596 const struct intel_wm_level
*r
;
2598 level
= ilk_wm_lp_to_level(wm_lp
, merged
);
2600 r
= &merged
->wm
[level
];
2603 * Maintain the watermark values even if the level is
2604 * disabled. Doing otherwise could cause underruns.
2606 results
->wm_lp
[wm_lp
- 1] =
2607 (ilk_wm_lp_latency(dev
, level
) << WM1_LP_LATENCY_SHIFT
) |
2608 (r
->pri_val
<< WM1_LP_SR_SHIFT
) |
2612 results
->wm_lp
[wm_lp
- 1] |= WM1_LP_SR_EN
;
2614 if (INTEL_INFO(dev
)->gen
>= 8)
2615 results
->wm_lp
[wm_lp
- 1] |=
2616 r
->fbc_val
<< WM1_LP_FBC_SHIFT_BDW
;
2618 results
->wm_lp
[wm_lp
- 1] |=
2619 r
->fbc_val
<< WM1_LP_FBC_SHIFT
;
2622 * Always set WM1S_LP_EN when spr_val != 0, even if the
2623 * level is disabled. Doing otherwise could cause underruns.
2625 if (INTEL_INFO(dev
)->gen
<= 6 && r
->spr_val
) {
2626 WARN_ON(wm_lp
!= 1);
2627 results
->wm_lp_spr
[wm_lp
- 1] = WM1S_LP_EN
| r
->spr_val
;
2629 results
->wm_lp_spr
[wm_lp
- 1] = r
->spr_val
;
2632 /* LP0 register values */
2633 for_each_intel_crtc(dev
, intel_crtc
) {
2634 enum pipe pipe
= intel_crtc
->pipe
;
2635 const struct intel_wm_level
*r
=
2636 &intel_crtc
->wm
.active
.wm
[0];
2638 if (WARN_ON(!r
->enable
))
2641 results
->wm_linetime
[pipe
] = intel_crtc
->wm
.active
.linetime
;
2643 results
->wm_pipe
[pipe
] =
2644 (r
->pri_val
<< WM0_PIPE_PLANE_SHIFT
) |
2645 (r
->spr_val
<< WM0_PIPE_SPRITE_SHIFT
) |
2650 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2651 * case both are at the same level. Prefer r1 in case they're the same. */
2652 static struct intel_pipe_wm
*ilk_find_best_result(struct drm_device
*dev
,
2653 struct intel_pipe_wm
*r1
,
2654 struct intel_pipe_wm
*r2
)
2656 int level
, max_level
= ilk_wm_max_level(dev
);
2657 int level1
= 0, level2
= 0;
2659 for (level
= 1; level
<= max_level
; level
++) {
2660 if (r1
->wm
[level
].enable
)
2662 if (r2
->wm
[level
].enable
)
2666 if (level1
== level2
) {
2667 if (r2
->fbc_wm_enabled
&& !r1
->fbc_wm_enabled
)
2671 } else if (level1
> level2
) {
2678 /* dirty bits used to track which watermarks need changes */
2679 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2680 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2681 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2682 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2683 #define WM_DIRTY_FBC (1 << 24)
2684 #define WM_DIRTY_DDB (1 << 25)
2686 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private
*dev_priv
,
2687 const struct ilk_wm_values
*old
,
2688 const struct ilk_wm_values
*new)
2690 unsigned int dirty
= 0;
2694 for_each_pipe(dev_priv
, pipe
) {
2695 if (old
->wm_linetime
[pipe
] != new->wm_linetime
[pipe
]) {
2696 dirty
|= WM_DIRTY_LINETIME(pipe
);
2697 /* Must disable LP1+ watermarks too */
2698 dirty
|= WM_DIRTY_LP_ALL
;
2701 if (old
->wm_pipe
[pipe
] != new->wm_pipe
[pipe
]) {
2702 dirty
|= WM_DIRTY_PIPE(pipe
);
2703 /* Must disable LP1+ watermarks too */
2704 dirty
|= WM_DIRTY_LP_ALL
;
2708 if (old
->enable_fbc_wm
!= new->enable_fbc_wm
) {
2709 dirty
|= WM_DIRTY_FBC
;
2710 /* Must disable LP1+ watermarks too */
2711 dirty
|= WM_DIRTY_LP_ALL
;
2714 if (old
->partitioning
!= new->partitioning
) {
2715 dirty
|= WM_DIRTY_DDB
;
2716 /* Must disable LP1+ watermarks too */
2717 dirty
|= WM_DIRTY_LP_ALL
;
2720 /* LP1+ watermarks already deemed dirty, no need to continue */
2721 if (dirty
& WM_DIRTY_LP_ALL
)
2724 /* Find the lowest numbered LP1+ watermark in need of an update... */
2725 for (wm_lp
= 1; wm_lp
<= 3; wm_lp
++) {
2726 if (old
->wm_lp
[wm_lp
- 1] != new->wm_lp
[wm_lp
- 1] ||
2727 old
->wm_lp_spr
[wm_lp
- 1] != new->wm_lp_spr
[wm_lp
- 1])
2731 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2732 for (; wm_lp
<= 3; wm_lp
++)
2733 dirty
|= WM_DIRTY_LP(wm_lp
);
2738 static bool _ilk_disable_lp_wm(struct drm_i915_private
*dev_priv
,
2741 struct ilk_wm_values
*previous
= &dev_priv
->wm
.hw
;
2742 bool changed
= false;
2744 if (dirty
& WM_DIRTY_LP(3) && previous
->wm_lp
[2] & WM1_LP_SR_EN
) {
2745 previous
->wm_lp
[2] &= ~WM1_LP_SR_EN
;
2746 I915_WRITE(WM3_LP_ILK
, previous
->wm_lp
[2]);
2749 if (dirty
& WM_DIRTY_LP(2) && previous
->wm_lp
[1] & WM1_LP_SR_EN
) {
2750 previous
->wm_lp
[1] &= ~WM1_LP_SR_EN
;
2751 I915_WRITE(WM2_LP_ILK
, previous
->wm_lp
[1]);
2754 if (dirty
& WM_DIRTY_LP(1) && previous
->wm_lp
[0] & WM1_LP_SR_EN
) {
2755 previous
->wm_lp
[0] &= ~WM1_LP_SR_EN
;
2756 I915_WRITE(WM1_LP_ILK
, previous
->wm_lp
[0]);
2761 * Don't touch WM1S_LP_EN here.
2762 * Doing so could cause underruns.
2769 * The spec says we shouldn't write when we don't need, because every write
2770 * causes WMs to be re-evaluated, expending some power.
2772 static void ilk_write_wm_values(struct drm_i915_private
*dev_priv
,
2773 struct ilk_wm_values
*results
)
2775 struct drm_device
*dev
= dev_priv
->dev
;
2776 struct ilk_wm_values
*previous
= &dev_priv
->wm
.hw
;
2780 dirty
= ilk_compute_wm_dirty(dev_priv
, previous
, results
);
2784 _ilk_disable_lp_wm(dev_priv
, dirty
);
2786 if (dirty
& WM_DIRTY_PIPE(PIPE_A
))
2787 I915_WRITE(WM0_PIPEA_ILK
, results
->wm_pipe
[0]);
2788 if (dirty
& WM_DIRTY_PIPE(PIPE_B
))
2789 I915_WRITE(WM0_PIPEB_ILK
, results
->wm_pipe
[1]);
2790 if (dirty
& WM_DIRTY_PIPE(PIPE_C
))
2791 I915_WRITE(WM0_PIPEC_IVB
, results
->wm_pipe
[2]);
2793 if (dirty
& WM_DIRTY_LINETIME(PIPE_A
))
2794 I915_WRITE(PIPE_WM_LINETIME(PIPE_A
), results
->wm_linetime
[0]);
2795 if (dirty
& WM_DIRTY_LINETIME(PIPE_B
))
2796 I915_WRITE(PIPE_WM_LINETIME(PIPE_B
), results
->wm_linetime
[1]);
2797 if (dirty
& WM_DIRTY_LINETIME(PIPE_C
))
2798 I915_WRITE(PIPE_WM_LINETIME(PIPE_C
), results
->wm_linetime
[2]);
2800 if (dirty
& WM_DIRTY_DDB
) {
2801 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2802 val
= I915_READ(WM_MISC
);
2803 if (results
->partitioning
== INTEL_DDB_PART_1_2
)
2804 val
&= ~WM_MISC_DATA_PARTITION_5_6
;
2806 val
|= WM_MISC_DATA_PARTITION_5_6
;
2807 I915_WRITE(WM_MISC
, val
);
2809 val
= I915_READ(DISP_ARB_CTL2
);
2810 if (results
->partitioning
== INTEL_DDB_PART_1_2
)
2811 val
&= ~DISP_DATA_PARTITION_5_6
;
2813 val
|= DISP_DATA_PARTITION_5_6
;
2814 I915_WRITE(DISP_ARB_CTL2
, val
);
2818 if (dirty
& WM_DIRTY_FBC
) {
2819 val
= I915_READ(DISP_ARB_CTL
);
2820 if (results
->enable_fbc_wm
)
2821 val
&= ~DISP_FBC_WM_DIS
;
2823 val
|= DISP_FBC_WM_DIS
;
2824 I915_WRITE(DISP_ARB_CTL
, val
);
2827 if (dirty
& WM_DIRTY_LP(1) &&
2828 previous
->wm_lp_spr
[0] != results
->wm_lp_spr
[0])
2829 I915_WRITE(WM1S_LP_ILK
, results
->wm_lp_spr
[0]);
2831 if (INTEL_INFO(dev
)->gen
>= 7) {
2832 if (dirty
& WM_DIRTY_LP(2) && previous
->wm_lp_spr
[1] != results
->wm_lp_spr
[1])
2833 I915_WRITE(WM2S_LP_IVB
, results
->wm_lp_spr
[1]);
2834 if (dirty
& WM_DIRTY_LP(3) && previous
->wm_lp_spr
[2] != results
->wm_lp_spr
[2])
2835 I915_WRITE(WM3S_LP_IVB
, results
->wm_lp_spr
[2]);
2838 if (dirty
& WM_DIRTY_LP(1) && previous
->wm_lp
[0] != results
->wm_lp
[0])
2839 I915_WRITE(WM1_LP_ILK
, results
->wm_lp
[0]);
2840 if (dirty
& WM_DIRTY_LP(2) && previous
->wm_lp
[1] != results
->wm_lp
[1])
2841 I915_WRITE(WM2_LP_ILK
, results
->wm_lp
[1]);
2842 if (dirty
& WM_DIRTY_LP(3) && previous
->wm_lp
[2] != results
->wm_lp
[2])
2843 I915_WRITE(WM3_LP_ILK
, results
->wm_lp
[2]);
2845 dev_priv
->wm
.hw
= *results
;
2848 static bool ilk_disable_lp_wm(struct drm_device
*dev
)
2850 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2852 return _ilk_disable_lp_wm(dev_priv
, WM_DIRTY_LP_ALL
);
2855 static void ilk_update_wm(struct drm_crtc
*crtc
)
2857 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2858 struct drm_device
*dev
= crtc
->dev
;
2859 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2860 struct ilk_wm_maximums max
;
2861 struct ilk_pipe_wm_parameters params
= {};
2862 struct ilk_wm_values results
= {};
2863 enum intel_ddb_partitioning partitioning
;
2864 struct intel_pipe_wm pipe_wm
= {};
2865 struct intel_pipe_wm lp_wm_1_2
= {}, lp_wm_5_6
= {}, *best_lp_wm
;
2866 struct intel_wm_config config
= {};
2868 ilk_compute_wm_parameters(crtc
, ¶ms
);
2870 intel_compute_pipe_wm(crtc
, ¶ms
, &pipe_wm
);
2872 if (!memcmp(&intel_crtc
->wm
.active
, &pipe_wm
, sizeof(pipe_wm
)))
2875 intel_crtc
->wm
.active
= pipe_wm
;
2877 ilk_compute_wm_config(dev
, &config
);
2879 ilk_compute_wm_maximums(dev
, 1, &config
, INTEL_DDB_PART_1_2
, &max
);
2880 ilk_wm_merge(dev
, &config
, &max
, &lp_wm_1_2
);
2882 /* 5/6 split only in single pipe config on IVB+ */
2883 if (INTEL_INFO(dev
)->gen
>= 7 &&
2884 config
.num_pipes_active
== 1 && config
.sprites_enabled
) {
2885 ilk_compute_wm_maximums(dev
, 1, &config
, INTEL_DDB_PART_5_6
, &max
);
2886 ilk_wm_merge(dev
, &config
, &max
, &lp_wm_5_6
);
2888 best_lp_wm
= ilk_find_best_result(dev
, &lp_wm_1_2
, &lp_wm_5_6
);
2890 best_lp_wm
= &lp_wm_1_2
;
2893 partitioning
= (best_lp_wm
== &lp_wm_1_2
) ?
2894 INTEL_DDB_PART_1_2
: INTEL_DDB_PART_5_6
;
2896 ilk_compute_wm_results(dev
, best_lp_wm
, partitioning
, &results
);
2898 ilk_write_wm_values(dev_priv
, &results
);
2902 ilk_update_sprite_wm(struct drm_plane
*plane
,
2903 struct drm_crtc
*crtc
,
2904 uint32_t sprite_width
, uint32_t sprite_height
,
2905 int pixel_size
, bool enabled
, bool scaled
)
2907 struct drm_device
*dev
= plane
->dev
;
2908 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
2910 intel_plane
->wm
.enabled
= enabled
;
2911 intel_plane
->wm
.scaled
= scaled
;
2912 intel_plane
->wm
.horiz_pixels
= sprite_width
;
2913 intel_plane
->wm
.vert_pixels
= sprite_width
;
2914 intel_plane
->wm
.bytes_per_pixel
= pixel_size
;
2917 * IVB workaround: must disable low power watermarks for at least
2918 * one frame before enabling scaling. LP watermarks can be re-enabled
2919 * when scaling is disabled.
2921 * WaCxSRDisabledForSpriteScaling:ivb
2923 if (IS_IVYBRIDGE(dev
) && scaled
&& ilk_disable_lp_wm(dev
))
2924 intel_wait_for_vblank(dev
, intel_plane
->pipe
);
2926 ilk_update_wm(crtc
);
2929 static void ilk_pipe_wm_get_hw_state(struct drm_crtc
*crtc
)
2931 struct drm_device
*dev
= crtc
->dev
;
2932 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2933 struct ilk_wm_values
*hw
= &dev_priv
->wm
.hw
;
2934 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2935 struct intel_pipe_wm
*active
= &intel_crtc
->wm
.active
;
2936 enum pipe pipe
= intel_crtc
->pipe
;
2937 static const unsigned int wm0_pipe_reg
[] = {
2938 [PIPE_A
] = WM0_PIPEA_ILK
,
2939 [PIPE_B
] = WM0_PIPEB_ILK
,
2940 [PIPE_C
] = WM0_PIPEC_IVB
,
2943 hw
->wm_pipe
[pipe
] = I915_READ(wm0_pipe_reg
[pipe
]);
2944 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2945 hw
->wm_linetime
[pipe
] = I915_READ(PIPE_WM_LINETIME(pipe
));
2947 active
->pipe_enabled
= intel_crtc_active(crtc
);
2949 if (active
->pipe_enabled
) {
2950 u32 tmp
= hw
->wm_pipe
[pipe
];
2953 * For active pipes LP0 watermark is marked as
2954 * enabled, and LP1+ watermaks as disabled since
2955 * we can't really reverse compute them in case
2956 * multiple pipes are active.
2958 active
->wm
[0].enable
= true;
2959 active
->wm
[0].pri_val
= (tmp
& WM0_PIPE_PLANE_MASK
) >> WM0_PIPE_PLANE_SHIFT
;
2960 active
->wm
[0].spr_val
= (tmp
& WM0_PIPE_SPRITE_MASK
) >> WM0_PIPE_SPRITE_SHIFT
;
2961 active
->wm
[0].cur_val
= tmp
& WM0_PIPE_CURSOR_MASK
;
2962 active
->linetime
= hw
->wm_linetime
[pipe
];
2964 int level
, max_level
= ilk_wm_max_level(dev
);
2967 * For inactive pipes, all watermark levels
2968 * should be marked as enabled but zeroed,
2969 * which is what we'd compute them to.
2971 for (level
= 0; level
<= max_level
; level
++)
2972 active
->wm
[level
].enable
= true;
2976 void ilk_wm_get_hw_state(struct drm_device
*dev
)
2978 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2979 struct ilk_wm_values
*hw
= &dev_priv
->wm
.hw
;
2980 struct drm_crtc
*crtc
;
2982 for_each_crtc(dev
, crtc
)
2983 ilk_pipe_wm_get_hw_state(crtc
);
2985 hw
->wm_lp
[0] = I915_READ(WM1_LP_ILK
);
2986 hw
->wm_lp
[1] = I915_READ(WM2_LP_ILK
);
2987 hw
->wm_lp
[2] = I915_READ(WM3_LP_ILK
);
2989 hw
->wm_lp_spr
[0] = I915_READ(WM1S_LP_ILK
);
2990 if (INTEL_INFO(dev
)->gen
>= 7) {
2991 hw
->wm_lp_spr
[1] = I915_READ(WM2S_LP_IVB
);
2992 hw
->wm_lp_spr
[2] = I915_READ(WM3S_LP_IVB
);
2995 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2996 hw
->partitioning
= (I915_READ(WM_MISC
) & WM_MISC_DATA_PARTITION_5_6
) ?
2997 INTEL_DDB_PART_5_6
: INTEL_DDB_PART_1_2
;
2998 else if (IS_IVYBRIDGE(dev
))
2999 hw
->partitioning
= (I915_READ(DISP_ARB_CTL2
) & DISP_DATA_PARTITION_5_6
) ?
3000 INTEL_DDB_PART_5_6
: INTEL_DDB_PART_1_2
;
3003 !(I915_READ(DISP_ARB_CTL
) & DISP_FBC_WM_DIS
);
3007 * intel_update_watermarks - update FIFO watermark values based on current modes
3009 * Calculate watermark values for the various WM regs based on current mode
3010 * and plane configuration.
3012 * There are several cases to deal with here:
3013 * - normal (i.e. non-self-refresh)
3014 * - self-refresh (SR) mode
3015 * - lines are large relative to FIFO size (buffer can hold up to 2)
3016 * - lines are small relative to FIFO size (buffer can hold more than 2
3017 * lines), so need to account for TLB latency
3019 * The normal calculation is:
3020 * watermark = dotclock * bytes per pixel * latency
3021 * where latency is platform & configuration dependent (we assume pessimal
3024 * The SR calculation is:
3025 * watermark = (trunc(latency/line time)+1) * surface width *
3028 * line time = htotal / dotclock
3029 * surface width = hdisplay for normal plane and 64 for cursor
3030 * and latency is assumed to be high, as above.
3032 * The final value programmed to the register should always be rounded up,
3033 * and include an extra 2 entries to account for clock crossings.
3035 * We don't use the sprite, so we can ignore that. And on Crestline we have
3036 * to set the non-SR watermarks to 8.
3038 void intel_update_watermarks(struct drm_crtc
*crtc
)
3040 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
3042 if (dev_priv
->display
.update_wm
)
3043 dev_priv
->display
.update_wm(crtc
);
3046 void intel_update_sprite_watermarks(struct drm_plane
*plane
,
3047 struct drm_crtc
*crtc
,
3048 uint32_t sprite_width
,
3049 uint32_t sprite_height
,
3051 bool enabled
, bool scaled
)
3053 struct drm_i915_private
*dev_priv
= plane
->dev
->dev_private
;
3055 if (dev_priv
->display
.update_sprite_wm
)
3056 dev_priv
->display
.update_sprite_wm(plane
, crtc
,
3057 sprite_width
, sprite_height
,
3058 pixel_size
, enabled
, scaled
);
3061 static struct drm_i915_gem_object
*
3062 intel_alloc_context_page(struct drm_device
*dev
)
3064 struct drm_i915_gem_object
*ctx
;
3067 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
3069 ctx
= i915_gem_alloc_object(dev
, 4096);
3071 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
3075 ret
= i915_gem_obj_ggtt_pin(ctx
, 4096, 0);
3077 DRM_ERROR("failed to pin power context: %d\n", ret
);
3081 ret
= i915_gem_object_set_to_gtt_domain(ctx
, 1);
3083 DRM_ERROR("failed to set-domain on power context: %d\n", ret
);
3090 i915_gem_object_ggtt_unpin(ctx
);
3092 drm_gem_object_unreference(&ctx
->base
);
3097 * Lock protecting IPS related data structures
3099 DEFINE_SPINLOCK(mchdev_lock
);
3101 /* Global for IPS driver to get at the current i915 device. Protected by
3103 static struct drm_i915_private
*i915_mch_dev
;
3105 bool ironlake_set_drps(struct drm_device
*dev
, u8 val
)
3107 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3110 assert_spin_locked(&mchdev_lock
);
3112 rgvswctl
= I915_READ16(MEMSWCTL
);
3113 if (rgvswctl
& MEMCTL_CMD_STS
) {
3114 DRM_DEBUG("gpu busy, RCS change rejected\n");
3115 return false; /* still busy with another command */
3118 rgvswctl
= (MEMCTL_CMD_CHFREQ
<< MEMCTL_CMD_SHIFT
) |
3119 (val
<< MEMCTL_FREQ_SHIFT
) | MEMCTL_SFCAVM
;
3120 I915_WRITE16(MEMSWCTL
, rgvswctl
);
3121 POSTING_READ16(MEMSWCTL
);
3123 rgvswctl
|= MEMCTL_CMD_STS
;
3124 I915_WRITE16(MEMSWCTL
, rgvswctl
);
3129 static void ironlake_enable_drps(struct drm_device
*dev
)
3131 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3132 u32 rgvmodectl
= I915_READ(MEMMODECTL
);
3133 u8 fmax
, fmin
, fstart
, vstart
;
3135 spin_lock_irq(&mchdev_lock
);
3137 /* Enable temp reporting */
3138 I915_WRITE16(PMMISC
, I915_READ(PMMISC
) | MCPPCE_EN
);
3139 I915_WRITE16(TSC1
, I915_READ(TSC1
) | TSE
);
3141 /* 100ms RC evaluation intervals */
3142 I915_WRITE(RCUPEI
, 100000);
3143 I915_WRITE(RCDNEI
, 100000);
3145 /* Set max/min thresholds to 90ms and 80ms respectively */
3146 I915_WRITE(RCBMAXAVG
, 90000);
3147 I915_WRITE(RCBMINAVG
, 80000);
3149 I915_WRITE(MEMIHYST
, 1);
3151 /* Set up min, max, and cur for interrupt handling */
3152 fmax
= (rgvmodectl
& MEMMODE_FMAX_MASK
) >> MEMMODE_FMAX_SHIFT
;
3153 fmin
= (rgvmodectl
& MEMMODE_FMIN_MASK
);
3154 fstart
= (rgvmodectl
& MEMMODE_FSTART_MASK
) >>
3155 MEMMODE_FSTART_SHIFT
;
3157 vstart
= (I915_READ(PXVFREQ_BASE
+ (fstart
* 4)) & PXVFREQ_PX_MASK
) >>
3160 dev_priv
->ips
.fmax
= fmax
; /* IPS callback will increase this */
3161 dev_priv
->ips
.fstart
= fstart
;
3163 dev_priv
->ips
.max_delay
= fstart
;
3164 dev_priv
->ips
.min_delay
= fmin
;
3165 dev_priv
->ips
.cur_delay
= fstart
;
3167 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
3168 fmax
, fmin
, fstart
);
3170 I915_WRITE(MEMINTREN
, MEMINT_CX_SUPR_EN
| MEMINT_EVAL_CHG_EN
);
3173 * Interrupts will be enabled in ironlake_irq_postinstall
3176 I915_WRITE(VIDSTART
, vstart
);
3177 POSTING_READ(VIDSTART
);
3179 rgvmodectl
|= MEMMODE_SWMODE_EN
;
3180 I915_WRITE(MEMMODECTL
, rgvmodectl
);
3182 if (wait_for_atomic((I915_READ(MEMSWCTL
) & MEMCTL_CMD_STS
) == 0, 10))
3183 DRM_ERROR("stuck trying to change perf mode\n");
3186 ironlake_set_drps(dev
, fstart
);
3188 dev_priv
->ips
.last_count1
= I915_READ(0x112e4) + I915_READ(0x112e8) +
3190 dev_priv
->ips
.last_time1
= jiffies_to_msecs(jiffies
);
3191 dev_priv
->ips
.last_count2
= I915_READ(0x112f4);
3192 dev_priv
->ips
.last_time2
= ktime_get_raw_ns();
3194 spin_unlock_irq(&mchdev_lock
);
3197 static void ironlake_disable_drps(struct drm_device
*dev
)
3199 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3202 spin_lock_irq(&mchdev_lock
);
3204 rgvswctl
= I915_READ16(MEMSWCTL
);
3206 /* Ack interrupts, disable EFC interrupt */
3207 I915_WRITE(MEMINTREN
, I915_READ(MEMINTREN
) & ~MEMINT_EVAL_CHG_EN
);
3208 I915_WRITE(MEMINTRSTS
, MEMINT_EVAL_CHG
);
3209 I915_WRITE(DEIER
, I915_READ(DEIER
) & ~DE_PCU_EVENT
);
3210 I915_WRITE(DEIIR
, DE_PCU_EVENT
);
3211 I915_WRITE(DEIMR
, I915_READ(DEIMR
) | DE_PCU_EVENT
);
3213 /* Go back to the starting frequency */
3214 ironlake_set_drps(dev
, dev_priv
->ips
.fstart
);
3216 rgvswctl
|= MEMCTL_CMD_STS
;
3217 I915_WRITE(MEMSWCTL
, rgvswctl
);
3220 spin_unlock_irq(&mchdev_lock
);
3223 /* There's a funny hw issue where the hw returns all 0 when reading from
3224 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3225 * ourselves, instead of doing a rmw cycle (which might result in us clearing
3226 * all limits and the gpu stuck at whatever frequency it is at atm).
3228 static u32
gen6_rps_limits(struct drm_i915_private
*dev_priv
, u8 val
)
3232 /* Only set the down limit when we've reached the lowest level to avoid
3233 * getting more interrupts, otherwise leave this clear. This prevents a
3234 * race in the hw when coming out of rc6: There's a tiny window where
3235 * the hw runs at the minimal clock before selecting the desired
3236 * frequency, if the down threshold expires in that window we will not
3237 * receive a down interrupt. */
3238 limits
= dev_priv
->rps
.max_freq_softlimit
<< 24;
3239 if (val
<= dev_priv
->rps
.min_freq_softlimit
)
3240 limits
|= dev_priv
->rps
.min_freq_softlimit
<< 16;
3245 static void gen6_set_rps_thresholds(struct drm_i915_private
*dev_priv
, u8 val
)
3249 if (dev_priv
->rps
.is_bdw_sw_turbo
)
3252 new_power
= dev_priv
->rps
.power
;
3253 switch (dev_priv
->rps
.power
) {
3255 if (val
> dev_priv
->rps
.efficient_freq
+ 1 && val
> dev_priv
->rps
.cur_freq
)
3256 new_power
= BETWEEN
;
3260 if (val
<= dev_priv
->rps
.efficient_freq
&& val
< dev_priv
->rps
.cur_freq
)
3261 new_power
= LOW_POWER
;
3262 else if (val
>= dev_priv
->rps
.rp0_freq
&& val
> dev_priv
->rps
.cur_freq
)
3263 new_power
= HIGH_POWER
;
3267 if (val
< (dev_priv
->rps
.rp1_freq
+ dev_priv
->rps
.rp0_freq
) >> 1 && val
< dev_priv
->rps
.cur_freq
)
3268 new_power
= BETWEEN
;
3271 /* Max/min bins are special */
3272 if (val
== dev_priv
->rps
.min_freq_softlimit
)
3273 new_power
= LOW_POWER
;
3274 if (val
== dev_priv
->rps
.max_freq_softlimit
)
3275 new_power
= HIGH_POWER
;
3276 if (new_power
== dev_priv
->rps
.power
)
3279 /* Note the units here are not exactly 1us, but 1280ns. */
3280 switch (new_power
) {
3282 /* Upclock if more than 95% busy over 16ms */
3283 I915_WRITE(GEN6_RP_UP_EI
, 12500);
3284 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 11800);
3286 /* Downclock if less than 85% busy over 32ms */
3287 I915_WRITE(GEN6_RP_DOWN_EI
, 25000);
3288 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 21250);
3290 I915_WRITE(GEN6_RP_CONTROL
,
3291 GEN6_RP_MEDIA_TURBO
|
3292 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
3293 GEN6_RP_MEDIA_IS_GFX
|
3295 GEN6_RP_UP_BUSY_AVG
|
3296 GEN6_RP_DOWN_IDLE_AVG
);
3300 /* Upclock if more than 90% busy over 13ms */
3301 I915_WRITE(GEN6_RP_UP_EI
, 10250);
3302 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 9225);
3304 /* Downclock if less than 75% busy over 32ms */
3305 I915_WRITE(GEN6_RP_DOWN_EI
, 25000);
3306 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 18750);
3308 I915_WRITE(GEN6_RP_CONTROL
,
3309 GEN6_RP_MEDIA_TURBO
|
3310 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
3311 GEN6_RP_MEDIA_IS_GFX
|
3313 GEN6_RP_UP_BUSY_AVG
|
3314 GEN6_RP_DOWN_IDLE_AVG
);
3318 /* Upclock if more than 85% busy over 10ms */
3319 I915_WRITE(GEN6_RP_UP_EI
, 8000);
3320 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 6800);
3322 /* Downclock if less than 60% busy over 32ms */
3323 I915_WRITE(GEN6_RP_DOWN_EI
, 25000);
3324 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 15000);
3326 I915_WRITE(GEN6_RP_CONTROL
,
3327 GEN6_RP_MEDIA_TURBO
|
3328 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
3329 GEN6_RP_MEDIA_IS_GFX
|
3331 GEN6_RP_UP_BUSY_AVG
|
3332 GEN6_RP_DOWN_IDLE_AVG
);
3336 dev_priv
->rps
.power
= new_power
;
3337 dev_priv
->rps
.last_adj
= 0;
3340 static u32
gen6_rps_pm_mask(struct drm_i915_private
*dev_priv
, u8 val
)
3344 if (val
> dev_priv
->rps
.min_freq_softlimit
)
3345 mask
|= GEN6_PM_RP_DOWN_THRESHOLD
| GEN6_PM_RP_DOWN_TIMEOUT
;
3346 if (val
< dev_priv
->rps
.max_freq_softlimit
)
3347 mask
|= GEN6_PM_RP_UP_THRESHOLD
;
3349 mask
|= dev_priv
->pm_rps_events
& (GEN6_PM_RP_DOWN_EI_EXPIRED
| GEN6_PM_RP_UP_EI_EXPIRED
);
3350 mask
&= dev_priv
->pm_rps_events
;
3352 /* IVB and SNB hard hangs on looping batchbuffer
3353 * if GEN6_PM_UP_EI_EXPIRED is masked.
3355 if (INTEL_INFO(dev_priv
->dev
)->gen
<= 7 && !IS_HASWELL(dev_priv
->dev
))
3356 mask
|= GEN6_PM_RP_UP_EI_EXPIRED
;
3358 if (IS_GEN8(dev_priv
->dev
))
3359 mask
|= GEN8_PMINTR_REDIRECT_TO_NON_DISP
;
3364 /* gen6_set_rps is called to update the frequency request, but should also be
3365 * called when the range (min_delay and max_delay) is modified so that we can
3366 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
3367 void gen6_set_rps(struct drm_device
*dev
, u8 val
)
3369 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3371 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
3372 WARN_ON(val
> dev_priv
->rps
.max_freq_softlimit
);
3373 WARN_ON(val
< dev_priv
->rps
.min_freq_softlimit
);
3375 /* min/max delay may still have been modified so be sure to
3376 * write the limits value.
3378 if (val
!= dev_priv
->rps
.cur_freq
) {
3379 gen6_set_rps_thresholds(dev_priv
, val
);
3381 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
3382 I915_WRITE(GEN6_RPNSWREQ
,
3383 HSW_FREQUENCY(val
));
3385 I915_WRITE(GEN6_RPNSWREQ
,
3386 GEN6_FREQUENCY(val
) |
3388 GEN6_AGGRESSIVE_TURBO
);
3391 /* Make sure we continue to get interrupts
3392 * until we hit the minimum or maximum frequencies.
3394 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS
, gen6_rps_limits(dev_priv
, val
));
3395 I915_WRITE(GEN6_PMINTRMSK
, gen6_rps_pm_mask(dev_priv
, val
));
3397 POSTING_READ(GEN6_RPNSWREQ
);
3399 dev_priv
->rps
.cur_freq
= val
;
3400 trace_intel_gpu_freq_change(val
* 50);
3403 /* vlv_set_rps_idle: Set the frequency to Rpn if Gfx clocks are down
3405 * * If Gfx is Idle, then
3406 * 1. Mask Turbo interrupts
3407 * 2. Bring up Gfx clock
3408 * 3. Change the freq to Rpn and wait till P-Unit updates freq
3409 * 4. Clear the Force GFX CLK ON bit so that Gfx can down
3410 * 5. Unmask Turbo interrupts
3412 static void vlv_set_rps_idle(struct drm_i915_private
*dev_priv
)
3414 struct drm_device
*dev
= dev_priv
->dev
;
3416 /* Latest VLV doesn't need to force the gfx clock */
3417 if (dev
->pdev
->revision
>= 0xd) {
3418 valleyview_set_rps(dev_priv
->dev
, dev_priv
->rps
.min_freq_softlimit
);
3423 * When we are idle. Drop to min voltage state.
3426 if (dev_priv
->rps
.cur_freq
<= dev_priv
->rps
.min_freq_softlimit
)
3429 /* Mask turbo interrupt so that they will not come in between */
3430 I915_WRITE(GEN6_PMINTRMSK
, 0xffffffff);
3432 vlv_force_gfx_clock(dev_priv
, true);
3434 dev_priv
->rps
.cur_freq
= dev_priv
->rps
.min_freq_softlimit
;
3436 vlv_punit_write(dev_priv
, PUNIT_REG_GPU_FREQ_REQ
,
3437 dev_priv
->rps
.min_freq_softlimit
);
3439 if (wait_for(((vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
))
3440 & GENFREQSTATUS
) == 0, 5))
3441 DRM_ERROR("timed out waiting for Punit\n");
3443 vlv_force_gfx_clock(dev_priv
, false);
3445 I915_WRITE(GEN6_PMINTRMSK
,
3446 gen6_rps_pm_mask(dev_priv
, dev_priv
->rps
.cur_freq
));
3449 void gen6_rps_idle(struct drm_i915_private
*dev_priv
)
3451 struct drm_device
*dev
= dev_priv
->dev
;
3453 mutex_lock(&dev_priv
->rps
.hw_lock
);
3454 if (dev_priv
->rps
.enabled
) {
3455 if (IS_CHERRYVIEW(dev
))
3456 valleyview_set_rps(dev_priv
->dev
, dev_priv
->rps
.min_freq_softlimit
);
3457 else if (IS_VALLEYVIEW(dev
))
3458 vlv_set_rps_idle(dev_priv
);
3459 else if (!dev_priv
->rps
.is_bdw_sw_turbo
3460 || atomic_read(&dev_priv
->rps
.sw_turbo
.flip_received
)){
3461 gen6_set_rps(dev_priv
->dev
, dev_priv
->rps
.min_freq_softlimit
);
3464 dev_priv
->rps
.last_adj
= 0;
3466 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3469 void gen6_rps_boost(struct drm_i915_private
*dev_priv
)
3471 struct drm_device
*dev
= dev_priv
->dev
;
3473 mutex_lock(&dev_priv
->rps
.hw_lock
);
3474 if (dev_priv
->rps
.enabled
) {
3475 if (IS_VALLEYVIEW(dev
))
3476 valleyview_set_rps(dev_priv
->dev
, dev_priv
->rps
.max_freq_softlimit
);
3477 else if (!dev_priv
->rps
.is_bdw_sw_turbo
3478 || atomic_read(&dev_priv
->rps
.sw_turbo
.flip_received
)){
3479 gen6_set_rps(dev_priv
->dev
, dev_priv
->rps
.max_freq_softlimit
);
3482 dev_priv
->rps
.last_adj
= 0;
3484 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3487 void valleyview_set_rps(struct drm_device
*dev
, u8 val
)
3489 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3491 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
3492 WARN_ON(val
> dev_priv
->rps
.max_freq_softlimit
);
3493 WARN_ON(val
< dev_priv
->rps
.min_freq_softlimit
);
3495 DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
3496 vlv_gpu_freq(dev_priv
, dev_priv
->rps
.cur_freq
),
3497 dev_priv
->rps
.cur_freq
,
3498 vlv_gpu_freq(dev_priv
, val
), val
);
3500 if (WARN_ONCE(IS_CHERRYVIEW(dev
) && (val
& 1),
3501 "Odd GPU freq value\n"))
3504 if (val
!= dev_priv
->rps
.cur_freq
)
3505 vlv_punit_write(dev_priv
, PUNIT_REG_GPU_FREQ_REQ
, val
);
3507 I915_WRITE(GEN6_PMINTRMSK
, gen6_rps_pm_mask(dev_priv
, val
));
3509 dev_priv
->rps
.cur_freq
= val
;
3510 trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv
, val
));
3513 static void gen8_disable_rps_interrupts(struct drm_device
*dev
)
3515 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3516 if (IS_BROADWELL(dev
) && dev_priv
->rps
.is_bdw_sw_turbo
){
3517 if (atomic_read(&dev_priv
->rps
.sw_turbo
.flip_received
))
3518 del_timer(&dev_priv
->rps
.sw_turbo
.flip_timer
);
3519 dev_priv
-> rps
.is_bdw_sw_turbo
= false;
3521 I915_WRITE(GEN6_PMINTRMSK
, ~GEN8_PMINTR_REDIRECT_TO_NON_DISP
);
3522 I915_WRITE(GEN8_GT_IER(2), I915_READ(GEN8_GT_IER(2)) &
3523 ~dev_priv
->pm_rps_events
);
3524 /* Complete PM interrupt masking here doesn't race with the rps work
3525 * item again unmasking PM interrupts because that is using a different
3526 * register (GEN8_GT_IMR(2)) to mask PM interrupts. The only risk is in
3527 * leaving stale bits in GEN8_GT_IIR(2) and GEN8_GT_IMR(2) which
3528 * gen8_enable_rps will clean up. */
3530 spin_lock_irq(&dev_priv
->irq_lock
);
3531 dev_priv
->rps
.pm_iir
= 0;
3532 spin_unlock_irq(&dev_priv
->irq_lock
);
3534 I915_WRITE(GEN8_GT_IIR(2), dev_priv
->pm_rps_events
);
3538 static void gen6_disable_rps_interrupts(struct drm_device
*dev
)
3540 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3542 I915_WRITE(GEN6_PMINTRMSK
, 0xffffffff);
3543 I915_WRITE(GEN6_PMIER
, I915_READ(GEN6_PMIER
) &
3544 ~dev_priv
->pm_rps_events
);
3545 /* Complete PM interrupt masking here doesn't race with the rps work
3546 * item again unmasking PM interrupts because that is using a different
3547 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3548 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3550 spin_lock_irq(&dev_priv
->irq_lock
);
3551 dev_priv
->rps
.pm_iir
= 0;
3552 spin_unlock_irq(&dev_priv
->irq_lock
);
3554 I915_WRITE(GEN6_PMIIR
, dev_priv
->pm_rps_events
);
3557 static void gen6_disable_rps(struct drm_device
*dev
)
3559 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3561 I915_WRITE(GEN6_RC_CONTROL
, 0);
3562 I915_WRITE(GEN6_RPNSWREQ
, 1 << 31);
3564 if (IS_BROADWELL(dev
))
3565 gen8_disable_rps_interrupts(dev
);
3567 gen6_disable_rps_interrupts(dev
);
3570 static void cherryview_disable_rps(struct drm_device
*dev
)
3572 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3574 I915_WRITE(GEN6_RC_CONTROL
, 0);
3576 gen8_disable_rps_interrupts(dev
);
3579 static void valleyview_disable_rps(struct drm_device
*dev
)
3581 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3583 /* we're doing forcewake before Disabling RC6,
3584 * This what the BIOS expects when going into suspend */
3585 gen6_gt_force_wake_get(dev_priv
, FORCEWAKE_ALL
);
3587 I915_WRITE(GEN6_RC_CONTROL
, 0);
3589 gen6_gt_force_wake_put(dev_priv
, FORCEWAKE_ALL
);
3591 gen6_disable_rps_interrupts(dev
);
3594 static void intel_print_rc6_info(struct drm_device
*dev
, u32 mode
)
3596 if (IS_VALLEYVIEW(dev
)) {
3597 if (mode
& (GEN7_RC_CTL_TO_MODE
| GEN6_RC_CTL_EI_MODE(1)))
3598 mode
= GEN6_RC_CTL_RC6_ENABLE
;
3602 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
3603 (mode
& GEN6_RC_CTL_RC6_ENABLE
) ? "on" : "off",
3604 (mode
& GEN6_RC_CTL_RC6p_ENABLE
) ? "on" : "off",
3605 (mode
& GEN6_RC_CTL_RC6pp_ENABLE
) ? "on" : "off");
3608 static int sanitize_rc6_option(const struct drm_device
*dev
, int enable_rc6
)
3610 /* No RC6 before Ironlake */
3611 if (INTEL_INFO(dev
)->gen
< 5)
3614 /* RC6 is only on Ironlake mobile not on desktop */
3615 if (INTEL_INFO(dev
)->gen
== 5 && !IS_IRONLAKE_M(dev
))
3618 /* Respect the kernel parameter if it is set */
3619 if (enable_rc6
>= 0) {
3622 if (INTEL_INFO(dev
)->gen
== 6 || IS_IVYBRIDGE(dev
))
3623 mask
= INTEL_RC6_ENABLE
| INTEL_RC6p_ENABLE
|
3626 mask
= INTEL_RC6_ENABLE
;
3628 if ((enable_rc6
& mask
) != enable_rc6
)
3629 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
3630 enable_rc6
& mask
, enable_rc6
, mask
);
3632 return enable_rc6
& mask
;
3635 /* Disable RC6 on Ironlake */
3636 if (INTEL_INFO(dev
)->gen
== 5)
3639 if (IS_IVYBRIDGE(dev
))
3640 return (INTEL_RC6_ENABLE
| INTEL_RC6p_ENABLE
);
3642 return INTEL_RC6_ENABLE
;
3645 int intel_enable_rc6(const struct drm_device
*dev
)
3647 return i915
.enable_rc6
;
3650 static void gen8_enable_rps_interrupts(struct drm_device
*dev
)
3652 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3654 spin_lock_irq(&dev_priv
->irq_lock
);
3655 WARN_ON(dev_priv
->rps
.pm_iir
);
3656 gen8_enable_pm_irq(dev_priv
, dev_priv
->pm_rps_events
);
3657 I915_WRITE(GEN8_GT_IIR(2), dev_priv
->pm_rps_events
);
3658 spin_unlock_irq(&dev_priv
->irq_lock
);
3661 static void gen6_enable_rps_interrupts(struct drm_device
*dev
)
3663 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3665 spin_lock_irq(&dev_priv
->irq_lock
);
3666 WARN_ON(dev_priv
->rps
.pm_iir
);
3667 gen6_enable_pm_irq(dev_priv
, dev_priv
->pm_rps_events
);
3668 I915_WRITE(GEN6_PMIIR
, dev_priv
->pm_rps_events
);
3669 spin_unlock_irq(&dev_priv
->irq_lock
);
3672 static void parse_rp_state_cap(struct drm_i915_private
*dev_priv
, u32 rp_state_cap
)
3674 /* All of these values are in units of 50MHz */
3675 dev_priv
->rps
.cur_freq
= 0;
3676 /* static values from HW: RP0 < RPe < RP1 < RPn (min_freq) */
3677 dev_priv
->rps
.rp1_freq
= (rp_state_cap
>> 8) & 0xff;
3678 dev_priv
->rps
.rp0_freq
= (rp_state_cap
>> 0) & 0xff;
3679 dev_priv
->rps
.min_freq
= (rp_state_cap
>> 16) & 0xff;
3680 /* XXX: only BYT has a special efficient freq */
3681 dev_priv
->rps
.efficient_freq
= dev_priv
->rps
.rp1_freq
;
3682 /* hw_max = RP0 until we check for overclocking */
3683 dev_priv
->rps
.max_freq
= dev_priv
->rps
.rp0_freq
;
3685 /* Preserve min/max settings in case of re-init */
3686 if (dev_priv
->rps
.max_freq_softlimit
== 0)
3687 dev_priv
->rps
.max_freq_softlimit
= dev_priv
->rps
.max_freq
;
3689 if (dev_priv
->rps
.min_freq_softlimit
== 0)
3690 dev_priv
->rps
.min_freq_softlimit
= dev_priv
->rps
.min_freq
;
3693 static void bdw_sw_calculate_freq(struct drm_device
*dev
,
3694 struct intel_rps_bdw_cal
*c
, u32
*cur_time
, u32
*c0
)
3696 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3698 u32 busyness_pct
= 0;
3699 u32 elapsed_time
= 0;
3702 if (!c
|| !cur_time
|| !c0
)
3705 if (0 == c
->last_c0
)
3708 /* Check Evaluation interval */
3709 elapsed_time
= *cur_time
- c
->last_ts
;
3710 if (elapsed_time
< c
->eval_interval
)
3713 mutex_lock(&dev_priv
->rps
.hw_lock
);
3716 * c0 unit in 32*1.28 usec, elapsed_time unit in 1 usec.
3717 * Whole busyness_pct calculation should be
3718 * busy = ((u64)(*c0 - c->last_c0) << 5 << 7) / 100;
3719 * busyness_pct = (u32)(busy * 100 / elapsed_time);
3720 * The final formula is to simplify CPU calculation
3722 busy
= (u64
)(*c0
- c
->last_c0
) << 12;
3723 do_div(busy
, elapsed_time
);
3724 busyness_pct
= (u32
)busy
;
3726 if (c
->is_up
&& busyness_pct
>= c
->it_threshold_pct
)
3727 new_freq
= (u16
)dev_priv
->rps
.cur_freq
+ 3;
3728 if (!c
->is_up
&& busyness_pct
<= c
->it_threshold_pct
)
3729 new_freq
= (u16
)dev_priv
->rps
.cur_freq
- 1;
3731 /* Adjust to new frequency busyness and compare with threshold */
3732 if (0 != new_freq
) {
3733 if (new_freq
> dev_priv
->rps
.max_freq_softlimit
)
3734 new_freq
= dev_priv
->rps
.max_freq_softlimit
;
3735 else if (new_freq
< dev_priv
->rps
.min_freq_softlimit
)
3736 new_freq
= dev_priv
->rps
.min_freq_softlimit
;
3738 gen6_set_rps(dev
, new_freq
);
3741 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3745 c
->last_ts
= *cur_time
;
3748 static void gen8_set_frequency_RP0(struct work_struct
*work
)
3750 struct intel_rps_bdw_turbo
*p_bdw_turbo
=
3751 container_of(work
, struct intel_rps_bdw_turbo
, work_max_freq
);
3752 struct intel_gen6_power_mgmt
*p_power_mgmt
=
3753 container_of(p_bdw_turbo
, struct intel_gen6_power_mgmt
, sw_turbo
);
3754 struct drm_i915_private
*dev_priv
=
3755 container_of(p_power_mgmt
, struct drm_i915_private
, rps
);
3757 mutex_lock(&dev_priv
->rps
.hw_lock
);
3758 gen6_set_rps(dev_priv
->dev
, dev_priv
->rps
.rp0_freq
);
3759 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3762 static void flip_active_timeout_handler(unsigned long var
)
3764 struct drm_i915_private
*dev_priv
= (struct drm_i915_private
*) var
;
3766 del_timer(&dev_priv
->rps
.sw_turbo
.flip_timer
);
3767 atomic_set(&dev_priv
->rps
.sw_turbo
.flip_received
, false);
3769 queue_work(dev_priv
->wq
, &dev_priv
->rps
.sw_turbo
.work_max_freq
);
3772 void bdw_software_turbo(struct drm_device
*dev
)
3774 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3776 u32 current_time
= I915_READ(TIMESTAMP_CTR
); /* unit in usec */
3777 u32 current_c0
= I915_READ(MCHBAR_PCU_C0
); /* unit in 32*1.28 usec */
3779 bdw_sw_calculate_freq(dev
, &dev_priv
->rps
.sw_turbo
.up
,
3780 ¤t_time
, ¤t_c0
);
3781 bdw_sw_calculate_freq(dev
, &dev_priv
->rps
.sw_turbo
.down
,
3782 ¤t_time
, ¤t_c0
);
3785 static void gen8_enable_rps(struct drm_device
*dev
)
3787 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3788 struct intel_engine_cs
*ring
;
3789 uint32_t rc6_mask
= 0, rp_state_cap
;
3790 uint32_t threshold_up_pct
, threshold_down_pct
;
3791 uint32_t ei_up
, ei_down
; /* up and down evaluation interval */
3795 /* Use software Turbo for BDW */
3796 dev_priv
->rps
.is_bdw_sw_turbo
= IS_BROADWELL(dev
);
3798 /* 1a: Software RC state - RC0 */
3799 I915_WRITE(GEN6_RC_STATE
, 0);
3801 /* 1c & 1d: Get forcewake during program sequence. Although the driver
3802 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
3803 gen6_gt_force_wake_get(dev_priv
, FORCEWAKE_ALL
);
3805 /* 2a: Disable RC states. */
3806 I915_WRITE(GEN6_RC_CONTROL
, 0);
3808 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
3809 parse_rp_state_cap(dev_priv
, rp_state_cap
);
3811 /* 2b: Program RC6 thresholds.*/
3812 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 40 << 16);
3813 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000); /* 12500 * 1280ns */
3814 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25); /* 25 * 1280ns */
3815 for_each_ring(ring
, dev_priv
, unused
)
3816 I915_WRITE(RING_MAX_IDLE(ring
->mmio_base
), 10);
3817 I915_WRITE(GEN6_RC_SLEEP
, 0);
3818 if (IS_BROADWELL(dev
))
3819 I915_WRITE(GEN6_RC6_THRESHOLD
, 625); /* 800us/1.28 for TO */
3821 I915_WRITE(GEN6_RC6_THRESHOLD
, 50000); /* 50/125ms per EI */
3824 if (intel_enable_rc6(dev
) & INTEL_RC6_ENABLE
)
3825 rc6_mask
= GEN6_RC_CTL_RC6_ENABLE
;
3826 intel_print_rc6_info(dev
, rc6_mask
);
3827 if (IS_BROADWELL(dev
))
3828 I915_WRITE(GEN6_RC_CONTROL
, GEN6_RC_CTL_HW_ENABLE
|
3829 GEN7_RC_CTL_TO_MODE
|
3832 I915_WRITE(GEN6_RC_CONTROL
, GEN6_RC_CTL_HW_ENABLE
|
3833 GEN6_RC_CTL_EI_MODE(1) |
3836 /* 4 Program defaults and thresholds for RPS*/
3837 I915_WRITE(GEN6_RPNSWREQ
,
3838 HSW_FREQUENCY(dev_priv
->rps
.rp1_freq
));
3839 I915_WRITE(GEN6_RC_VIDEO_FREQ
,
3840 HSW_FREQUENCY(dev_priv
->rps
.rp1_freq
));
3841 ei_up
= 84480; /* 84.48ms */
3843 threshold_up_pct
= 90; /* x percent busy */
3844 threshold_down_pct
= 70;
3846 if (dev_priv
->rps
.is_bdw_sw_turbo
) {
3847 dev_priv
->rps
.sw_turbo
.up
.it_threshold_pct
= threshold_up_pct
;
3848 dev_priv
->rps
.sw_turbo
.up
.eval_interval
= ei_up
;
3849 dev_priv
->rps
.sw_turbo
.up
.is_up
= true;
3850 dev_priv
->rps
.sw_turbo
.up
.last_ts
= 0;
3851 dev_priv
->rps
.sw_turbo
.up
.last_c0
= 0;
3853 dev_priv
->rps
.sw_turbo
.down
.it_threshold_pct
= threshold_down_pct
;
3854 dev_priv
->rps
.sw_turbo
.down
.eval_interval
= ei_down
;
3855 dev_priv
->rps
.sw_turbo
.down
.is_up
= false;
3856 dev_priv
->rps
.sw_turbo
.down
.last_ts
= 0;
3857 dev_priv
->rps
.sw_turbo
.down
.last_c0
= 0;
3859 /* Start the timer to track if flip comes*/
3860 dev_priv
->rps
.sw_turbo
.timeout
= 200*1000; /* in us */
3862 init_timer(&dev_priv
->rps
.sw_turbo
.flip_timer
);
3863 dev_priv
->rps
.sw_turbo
.flip_timer
.function
= flip_active_timeout_handler
;
3864 dev_priv
->rps
.sw_turbo
.flip_timer
.data
= (unsigned long) dev_priv
;
3865 dev_priv
->rps
.sw_turbo
.flip_timer
.expires
=
3866 usecs_to_jiffies(dev_priv
->rps
.sw_turbo
.timeout
) + jiffies
;
3867 add_timer(&dev_priv
->rps
.sw_turbo
.flip_timer
);
3868 INIT_WORK(&dev_priv
->rps
.sw_turbo
.work_max_freq
, gen8_set_frequency_RP0
);
3870 atomic_set(&dev_priv
->rps
.sw_turbo
.flip_received
, true);
3872 /* NB: Docs say 1s, and 1000000 - which aren't equivalent
3873 * 1 second timeout*/
3874 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, FREQ_1_28_US(1000000));
3876 /* Docs recommend 900MHz, and 300 MHz respectively */
3877 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS
,
3878 dev_priv
->rps
.max_freq_softlimit
<< 24 |
3879 dev_priv
->rps
.min_freq_softlimit
<< 16);
3881 I915_WRITE(GEN6_RP_UP_THRESHOLD
,
3882 FREQ_1_28_US(ei_up
* threshold_up_pct
/ 100));
3883 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
,
3884 FREQ_1_28_US(ei_down
* threshold_down_pct
/ 100));
3885 I915_WRITE(GEN6_RP_UP_EI
,
3886 FREQ_1_28_US(ei_up
));
3887 I915_WRITE(GEN6_RP_DOWN_EI
,
3888 FREQ_1_28_US(ei_down
));
3890 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
3894 rp_ctl_flag
= GEN6_RP_MEDIA_TURBO
|
3895 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
3896 GEN6_RP_MEDIA_IS_GFX
|
3897 GEN6_RP_UP_BUSY_AVG
|
3898 GEN6_RP_DOWN_IDLE_AVG
;
3899 if (!dev_priv
->rps
.is_bdw_sw_turbo
)
3900 rp_ctl_flag
|= GEN6_RP_ENABLE
;
3902 I915_WRITE(GEN6_RP_CONTROL
, rp_ctl_flag
);
3904 /* 6: Ring frequency + overclocking
3905 * (our driver does this later */
3906 gen6_set_rps(dev
, (I915_READ(GEN6_GT_PERF_STATUS
) & 0xff00) >> 8);
3907 if (!dev_priv
->rps
.is_bdw_sw_turbo
)
3908 gen8_enable_rps_interrupts(dev
);
3910 gen6_gt_force_wake_put(dev_priv
, FORCEWAKE_ALL
);
3913 static void gen6_enable_rps(struct drm_device
*dev
)
3915 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3916 struct intel_engine_cs
*ring
;
3918 u32 rc6vids
, pcu_mbox
= 0, rc6_mask
= 0;
3923 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
3925 /* Here begins a magic sequence of register writes to enable
3926 * auto-downclocking.
3928 * Perhaps there might be some value in exposing these to
3931 I915_WRITE(GEN6_RC_STATE
, 0);
3933 /* Clear the DBG now so we don't confuse earlier errors */
3934 if ((gtfifodbg
= I915_READ(GTFIFODBG
))) {
3935 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg
);
3936 I915_WRITE(GTFIFODBG
, gtfifodbg
);
3939 gen6_gt_force_wake_get(dev_priv
, FORCEWAKE_ALL
);
3941 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
3943 parse_rp_state_cap(dev_priv
, rp_state_cap
);
3945 /* disable the counters and set deterministic thresholds */
3946 I915_WRITE(GEN6_RC_CONTROL
, 0);
3948 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT
, 1000 << 16);
3949 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 40 << 16 | 30);
3950 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT
, 30);
3951 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000);
3952 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25);
3954 for_each_ring(ring
, dev_priv
, i
)
3955 I915_WRITE(RING_MAX_IDLE(ring
->mmio_base
), 10);
3957 I915_WRITE(GEN6_RC_SLEEP
, 0);
3958 I915_WRITE(GEN6_RC1e_THRESHOLD
, 1000);
3959 if (IS_IVYBRIDGE(dev
))
3960 I915_WRITE(GEN6_RC6_THRESHOLD
, 125000);
3962 I915_WRITE(GEN6_RC6_THRESHOLD
, 50000);
3963 I915_WRITE(GEN6_RC6p_THRESHOLD
, 150000);
3964 I915_WRITE(GEN6_RC6pp_THRESHOLD
, 64000); /* unused */
3966 /* Check if we are enabling RC6 */
3967 rc6_mode
= intel_enable_rc6(dev_priv
->dev
);
3968 if (rc6_mode
& INTEL_RC6_ENABLE
)
3969 rc6_mask
|= GEN6_RC_CTL_RC6_ENABLE
;
3971 /* We don't use those on Haswell */
3972 if (!IS_HASWELL(dev
)) {
3973 if (rc6_mode
& INTEL_RC6p_ENABLE
)
3974 rc6_mask
|= GEN6_RC_CTL_RC6p_ENABLE
;
3976 if (rc6_mode
& INTEL_RC6pp_ENABLE
)
3977 rc6_mask
|= GEN6_RC_CTL_RC6pp_ENABLE
;
3980 intel_print_rc6_info(dev
, rc6_mask
);
3982 I915_WRITE(GEN6_RC_CONTROL
,
3984 GEN6_RC_CTL_EI_MODE(1) |
3985 GEN6_RC_CTL_HW_ENABLE
);
3987 /* Power down if completely idle for over 50ms */
3988 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 50000);
3989 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
3991 ret
= sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_MIN_FREQ_TABLE
, 0);
3993 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
3995 ret
= sandybridge_pcode_read(dev_priv
, GEN6_READ_OC_PARAMS
, &pcu_mbox
);
3996 if (!ret
&& (pcu_mbox
& (1<<31))) { /* OC supported */
3997 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
3998 (dev_priv
->rps
.max_freq_softlimit
& 0xff) * 50,
3999 (pcu_mbox
& 0xff) * 50);
4000 dev_priv
->rps
.max_freq
= pcu_mbox
& 0xff;
4003 dev_priv
->rps
.power
= HIGH_POWER
; /* force a reset */
4004 gen6_set_rps(dev_priv
->dev
, dev_priv
->rps
.min_freq_softlimit
);
4006 gen6_enable_rps_interrupts(dev
);
4009 ret
= sandybridge_pcode_read(dev_priv
, GEN6_PCODE_READ_RC6VIDS
, &rc6vids
);
4010 if (IS_GEN6(dev
) && ret
) {
4011 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
4012 } else if (IS_GEN6(dev
) && (GEN6_DECODE_RC6_VID(rc6vids
& 0xff) < 450)) {
4013 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
4014 GEN6_DECODE_RC6_VID(rc6vids
& 0xff), 450);
4015 rc6vids
&= 0xffff00;
4016 rc6vids
|= GEN6_ENCODE_RC6_VID(450);
4017 ret
= sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_RC6VIDS
, rc6vids
);
4019 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
4022 gen6_gt_force_wake_put(dev_priv
, FORCEWAKE_ALL
);
4025 static void __gen6_update_ring_freq(struct drm_device
*dev
)
4027 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4029 unsigned int gpu_freq
;
4030 unsigned int max_ia_freq
, min_ring_freq
;
4031 int scaling_factor
= 180;
4032 struct cpufreq_policy
*policy
;
4034 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
4036 policy
= cpufreq_cpu_get(0);
4038 max_ia_freq
= policy
->cpuinfo
.max_freq
;
4039 cpufreq_cpu_put(policy
);
4042 * Default to measured freq if none found, PCU will ensure we
4045 max_ia_freq
= tsc_khz
;
4048 /* Convert from kHz to MHz */
4049 max_ia_freq
/= 1000;
4051 min_ring_freq
= I915_READ(DCLK
) & 0xf;
4052 /* convert DDR frequency from units of 266.6MHz to bandwidth */
4053 min_ring_freq
= mult_frac(min_ring_freq
, 8, 3);
4056 * For each potential GPU frequency, load a ring frequency we'd like
4057 * to use for memory access. We do this by specifying the IA frequency
4058 * the PCU should use as a reference to determine the ring frequency.
4060 for (gpu_freq
= dev_priv
->rps
.max_freq_softlimit
; gpu_freq
>= dev_priv
->rps
.min_freq_softlimit
;
4062 int diff
= dev_priv
->rps
.max_freq_softlimit
- gpu_freq
;
4063 unsigned int ia_freq
= 0, ring_freq
= 0;
4065 if (INTEL_INFO(dev
)->gen
>= 8) {
4066 /* max(2 * GT, DDR). NB: GT is 50MHz units */
4067 ring_freq
= max(min_ring_freq
, gpu_freq
);
4068 } else if (IS_HASWELL(dev
)) {
4069 ring_freq
= mult_frac(gpu_freq
, 5, 4);
4070 ring_freq
= max(min_ring_freq
, ring_freq
);
4071 /* leave ia_freq as the default, chosen by cpufreq */
4073 /* On older processors, there is no separate ring
4074 * clock domain, so in order to boost the bandwidth
4075 * of the ring, we need to upclock the CPU (ia_freq).
4077 * For GPU frequencies less than 750MHz,
4078 * just use the lowest ring freq.
4080 if (gpu_freq
< min_freq
)
4083 ia_freq
= max_ia_freq
- ((diff
* scaling_factor
) / 2);
4084 ia_freq
= DIV_ROUND_CLOSEST(ia_freq
, 100);
4087 sandybridge_pcode_write(dev_priv
,
4088 GEN6_PCODE_WRITE_MIN_FREQ_TABLE
,
4089 ia_freq
<< GEN6_PCODE_FREQ_IA_RATIO_SHIFT
|
4090 ring_freq
<< GEN6_PCODE_FREQ_RING_RATIO_SHIFT
|
4095 void gen6_update_ring_freq(struct drm_device
*dev
)
4097 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4099 if (INTEL_INFO(dev
)->gen
< 6 || IS_VALLEYVIEW(dev
))
4102 mutex_lock(&dev_priv
->rps
.hw_lock
);
4103 __gen6_update_ring_freq(dev
);
4104 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4107 static int cherryview_rps_max_freq(struct drm_i915_private
*dev_priv
)
4111 val
= vlv_punit_read(dev_priv
, PUNIT_GPU_STATUS_REG
);
4112 rp0
= (val
>> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT
) & PUNIT_GPU_STATUS_MAX_FREQ_MASK
;
4117 static int cherryview_rps_rpe_freq(struct drm_i915_private
*dev_priv
)
4121 val
= vlv_punit_read(dev_priv
, PUNIT_GPU_DUTYCYCLE_REG
);
4122 rpe
= (val
>> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT
) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK
;
4127 static int cherryview_rps_guar_freq(struct drm_i915_private
*dev_priv
)
4131 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
4132 rp1
= (val
>> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT
) & PUNIT_GPU_STATUS_MAX_FREQ_MASK
;
4137 static int cherryview_rps_min_freq(struct drm_i915_private
*dev_priv
)
4141 val
= vlv_punit_read(dev_priv
, PUNIT_GPU_STATUS_REG
);
4142 rpn
= (val
>> PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT
) & PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK
;
4146 static int valleyview_rps_guar_freq(struct drm_i915_private
*dev_priv
)
4150 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FREQ_FUSE
);
4152 rp1
= (val
& FB_GFX_FGUARANTEED_FREQ_FUSE_MASK
) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT
;
4157 static int valleyview_rps_max_freq(struct drm_i915_private
*dev_priv
)
4161 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FREQ_FUSE
);
4163 rp0
= (val
& FB_GFX_MAX_FREQ_FUSE_MASK
) >> FB_GFX_MAX_FREQ_FUSE_SHIFT
;
4165 rp0
= min_t(u32
, rp0
, 0xea);
4170 static int valleyview_rps_rpe_freq(struct drm_i915_private
*dev_priv
)
4174 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FMAX_FUSE_LO
);
4175 rpe
= (val
& FB_FMAX_VMIN_FREQ_LO_MASK
) >> FB_FMAX_VMIN_FREQ_LO_SHIFT
;
4176 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FMAX_FUSE_HI
);
4177 rpe
|= (val
& FB_FMAX_VMIN_FREQ_HI_MASK
) << 5;
4182 static int valleyview_rps_min_freq(struct drm_i915_private
*dev_priv
)
4184 return vlv_punit_read(dev_priv
, PUNIT_REG_GPU_LFM
) & 0xff;
4187 /* Check that the pctx buffer wasn't move under us. */
4188 static void valleyview_check_pctx(struct drm_i915_private
*dev_priv
)
4190 unsigned long pctx_addr
= I915_READ(VLV_PCBR
) & ~4095;
4192 WARN_ON(pctx_addr
!= dev_priv
->mm
.stolen_base
+
4193 dev_priv
->vlv_pctx
->stolen
->start
);
4197 /* Check that the pcbr address is not empty. */
4198 static void cherryview_check_pctx(struct drm_i915_private
*dev_priv
)
4200 unsigned long pctx_addr
= I915_READ(VLV_PCBR
) & ~4095;
4202 WARN_ON((pctx_addr
>> VLV_PCBR_ADDR_SHIFT
) == 0);
4205 static void cherryview_setup_pctx(struct drm_device
*dev
)
4207 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4208 unsigned long pctx_paddr
, paddr
;
4209 struct i915_gtt
*gtt
= &dev_priv
->gtt
;
4211 int pctx_size
= 32*1024;
4213 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
4215 pcbr
= I915_READ(VLV_PCBR
);
4216 if ((pcbr
>> VLV_PCBR_ADDR_SHIFT
) == 0) {
4217 paddr
= (dev_priv
->mm
.stolen_base
+
4218 (gtt
->stolen_size
- pctx_size
));
4220 pctx_paddr
= (paddr
& (~4095));
4221 I915_WRITE(VLV_PCBR
, pctx_paddr
);
4225 static void valleyview_setup_pctx(struct drm_device
*dev
)
4227 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4228 struct drm_i915_gem_object
*pctx
;
4229 unsigned long pctx_paddr
;
4231 int pctx_size
= 24*1024;
4233 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
4235 pcbr
= I915_READ(VLV_PCBR
);
4237 /* BIOS set it up already, grab the pre-alloc'd space */
4240 pcbr_offset
= (pcbr
& (~4095)) - dev_priv
->mm
.stolen_base
;
4241 pctx
= i915_gem_object_create_stolen_for_preallocated(dev_priv
->dev
,
4243 I915_GTT_OFFSET_NONE
,
4249 * From the Gunit register HAS:
4250 * The Gfx driver is expected to program this register and ensure
4251 * proper allocation within Gfx stolen memory. For example, this
4252 * register should be programmed such than the PCBR range does not
4253 * overlap with other ranges, such as the frame buffer, protected
4254 * memory, or any other relevant ranges.
4256 pctx
= i915_gem_object_create_stolen(dev
, pctx_size
);
4258 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
4262 pctx_paddr
= dev_priv
->mm
.stolen_base
+ pctx
->stolen
->start
;
4263 I915_WRITE(VLV_PCBR
, pctx_paddr
);
4266 dev_priv
->vlv_pctx
= pctx
;
4269 static void valleyview_cleanup_pctx(struct drm_device
*dev
)
4271 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4273 if (WARN_ON(!dev_priv
->vlv_pctx
))
4276 drm_gem_object_unreference(&dev_priv
->vlv_pctx
->base
);
4277 dev_priv
->vlv_pctx
= NULL
;
4280 static void valleyview_init_gt_powersave(struct drm_device
*dev
)
4282 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4285 valleyview_setup_pctx(dev
);
4287 mutex_lock(&dev_priv
->rps
.hw_lock
);
4289 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
4290 switch ((val
>> 6) & 3) {
4293 dev_priv
->mem_freq
= 800;
4296 dev_priv
->mem_freq
= 1066;
4299 dev_priv
->mem_freq
= 1333;
4302 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv
->mem_freq
);
4304 dev_priv
->rps
.max_freq
= valleyview_rps_max_freq(dev_priv
);
4305 dev_priv
->rps
.rp0_freq
= dev_priv
->rps
.max_freq
;
4306 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
4307 vlv_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
),
4308 dev_priv
->rps
.max_freq
);
4310 dev_priv
->rps
.efficient_freq
= valleyview_rps_rpe_freq(dev_priv
);
4311 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
4312 vlv_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
),
4313 dev_priv
->rps
.efficient_freq
);
4315 dev_priv
->rps
.rp1_freq
= valleyview_rps_guar_freq(dev_priv
);
4316 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
4317 vlv_gpu_freq(dev_priv
, dev_priv
->rps
.rp1_freq
),
4318 dev_priv
->rps
.rp1_freq
);
4320 dev_priv
->rps
.min_freq
= valleyview_rps_min_freq(dev_priv
);
4321 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
4322 vlv_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
),
4323 dev_priv
->rps
.min_freq
);
4325 /* Preserve min/max settings in case of re-init */
4326 if (dev_priv
->rps
.max_freq_softlimit
== 0)
4327 dev_priv
->rps
.max_freq_softlimit
= dev_priv
->rps
.max_freq
;
4329 if (dev_priv
->rps
.min_freq_softlimit
== 0)
4330 dev_priv
->rps
.min_freq_softlimit
= dev_priv
->rps
.min_freq
;
4332 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4335 static void cherryview_init_gt_powersave(struct drm_device
*dev
)
4337 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4340 cherryview_setup_pctx(dev
);
4342 mutex_lock(&dev_priv
->rps
.hw_lock
);
4344 val
= vlv_punit_read(dev_priv
, CCK_FUSE_REG
);
4345 switch ((val
>> 2) & 0x7) {
4348 dev_priv
->rps
.cz_freq
= 200;
4349 dev_priv
->mem_freq
= 1600;
4352 dev_priv
->rps
.cz_freq
= 267;
4353 dev_priv
->mem_freq
= 1600;
4356 dev_priv
->rps
.cz_freq
= 333;
4357 dev_priv
->mem_freq
= 2000;
4360 dev_priv
->rps
.cz_freq
= 320;
4361 dev_priv
->mem_freq
= 1600;
4364 dev_priv
->rps
.cz_freq
= 400;
4365 dev_priv
->mem_freq
= 1600;
4368 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv
->mem_freq
);
4370 dev_priv
->rps
.max_freq
= cherryview_rps_max_freq(dev_priv
);
4371 dev_priv
->rps
.rp0_freq
= dev_priv
->rps
.max_freq
;
4372 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
4373 vlv_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
),
4374 dev_priv
->rps
.max_freq
);
4376 dev_priv
->rps
.efficient_freq
= cherryview_rps_rpe_freq(dev_priv
);
4377 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
4378 vlv_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
),
4379 dev_priv
->rps
.efficient_freq
);
4381 dev_priv
->rps
.rp1_freq
= cherryview_rps_guar_freq(dev_priv
);
4382 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
4383 vlv_gpu_freq(dev_priv
, dev_priv
->rps
.rp1_freq
),
4384 dev_priv
->rps
.rp1_freq
);
4386 dev_priv
->rps
.min_freq
= cherryview_rps_min_freq(dev_priv
);
4387 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
4388 vlv_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
),
4389 dev_priv
->rps
.min_freq
);
4391 WARN_ONCE((dev_priv
->rps
.max_freq
|
4392 dev_priv
->rps
.efficient_freq
|
4393 dev_priv
->rps
.rp1_freq
|
4394 dev_priv
->rps
.min_freq
) & 1,
4395 "Odd GPU freq values\n");
4397 /* Preserve min/max settings in case of re-init */
4398 if (dev_priv
->rps
.max_freq_softlimit
== 0)
4399 dev_priv
->rps
.max_freq_softlimit
= dev_priv
->rps
.max_freq
;
4401 if (dev_priv
->rps
.min_freq_softlimit
== 0)
4402 dev_priv
->rps
.min_freq_softlimit
= dev_priv
->rps
.min_freq
;
4404 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4407 static void valleyview_cleanup_gt_powersave(struct drm_device
*dev
)
4409 valleyview_cleanup_pctx(dev
);
4412 static void cherryview_enable_rps(struct drm_device
*dev
)
4414 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4415 struct intel_engine_cs
*ring
;
4416 u32 gtfifodbg
, val
, rc6_mode
= 0, pcbr
;
4419 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
4421 gtfifodbg
= I915_READ(GTFIFODBG
);
4423 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4425 I915_WRITE(GTFIFODBG
, gtfifodbg
);
4428 cherryview_check_pctx(dev_priv
);
4430 /* 1a & 1b: Get forcewake during program sequence. Although the driver
4431 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4432 gen6_gt_force_wake_get(dev_priv
, FORCEWAKE_ALL
);
4434 /* 2a: Program RC6 thresholds.*/
4435 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 40 << 16);
4436 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000); /* 12500 * 1280ns */
4437 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25); /* 25 * 1280ns */
4439 for_each_ring(ring
, dev_priv
, i
)
4440 I915_WRITE(RING_MAX_IDLE(ring
->mmio_base
), 10);
4441 I915_WRITE(GEN6_RC_SLEEP
, 0);
4443 I915_WRITE(GEN6_RC6_THRESHOLD
, 50000); /* 50/125ms per EI */
4445 /* allows RC6 residency counter to work */
4446 I915_WRITE(VLV_COUNTER_CONTROL
,
4447 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH
|
4448 VLV_MEDIA_RC6_COUNT_EN
|
4449 VLV_RENDER_RC6_COUNT_EN
));
4451 /* For now we assume BIOS is allocating and populating the PCBR */
4452 pcbr
= I915_READ(VLV_PCBR
);
4454 DRM_DEBUG_DRIVER("PCBR offset : 0x%x\n", pcbr
);
4457 if ((intel_enable_rc6(dev
) & INTEL_RC6_ENABLE
) &&
4458 (pcbr
>> VLV_PCBR_ADDR_SHIFT
))
4459 rc6_mode
= GEN6_RC_CTL_EI_MODE(1);
4461 I915_WRITE(GEN6_RC_CONTROL
, rc6_mode
);
4463 /* 4 Program defaults and thresholds for RPS*/
4464 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 59400);
4465 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 245000);
4466 I915_WRITE(GEN6_RP_UP_EI
, 66000);
4467 I915_WRITE(GEN6_RP_DOWN_EI
, 350000);
4469 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
4471 /* WaDisablePwrmtrEvent:chv (pre-production hw) */
4472 I915_WRITE(0xA80C, I915_READ(0xA80C) & 0x00ffffff);
4473 I915_WRITE(0xA810, I915_READ(0xA810) & 0xffffff00);
4476 I915_WRITE(GEN6_RP_CONTROL
,
4477 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
4478 GEN6_RP_MEDIA_IS_GFX
| /* WaSetMaskForGfxBusyness:chv (pre-production hw ?) */
4480 GEN6_RP_UP_BUSY_AVG
|
4481 GEN6_RP_DOWN_IDLE_AVG
);
4483 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
4485 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val
& 0x10 ? "yes" : "no");
4486 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val
);
4488 dev_priv
->rps
.cur_freq
= (val
>> 8) & 0xff;
4489 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
4490 vlv_gpu_freq(dev_priv
, dev_priv
->rps
.cur_freq
),
4491 dev_priv
->rps
.cur_freq
);
4493 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
4494 vlv_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
),
4495 dev_priv
->rps
.efficient_freq
);
4497 valleyview_set_rps(dev_priv
->dev
, dev_priv
->rps
.efficient_freq
);
4499 gen8_enable_rps_interrupts(dev
);
4501 gen6_gt_force_wake_put(dev_priv
, FORCEWAKE_ALL
);
4504 static void valleyview_enable_rps(struct drm_device
*dev
)
4506 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4507 struct intel_engine_cs
*ring
;
4508 u32 gtfifodbg
, val
, rc6_mode
= 0;
4511 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
4513 valleyview_check_pctx(dev_priv
);
4515 if ((gtfifodbg
= I915_READ(GTFIFODBG
))) {
4516 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4518 I915_WRITE(GTFIFODBG
, gtfifodbg
);
4521 /* If VLV, Forcewake all wells, else re-direct to regular path */
4522 gen6_gt_force_wake_get(dev_priv
, FORCEWAKE_ALL
);
4524 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 59400);
4525 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 245000);
4526 I915_WRITE(GEN6_RP_UP_EI
, 66000);
4527 I915_WRITE(GEN6_RP_DOWN_EI
, 350000);
4529 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
4530 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 0xf4240);
4532 I915_WRITE(GEN6_RP_CONTROL
,
4533 GEN6_RP_MEDIA_TURBO
|
4534 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
4535 GEN6_RP_MEDIA_IS_GFX
|
4537 GEN6_RP_UP_BUSY_AVG
|
4538 GEN6_RP_DOWN_IDLE_CONT
);
4540 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 0x00280000);
4541 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000);
4542 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25);
4544 for_each_ring(ring
, dev_priv
, i
)
4545 I915_WRITE(RING_MAX_IDLE(ring
->mmio_base
), 10);
4547 I915_WRITE(GEN6_RC6_THRESHOLD
, 0x557);
4549 /* allows RC6 residency counter to work */
4550 I915_WRITE(VLV_COUNTER_CONTROL
,
4551 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN
|
4552 VLV_RENDER_RC0_COUNT_EN
|
4553 VLV_MEDIA_RC6_COUNT_EN
|
4554 VLV_RENDER_RC6_COUNT_EN
));
4556 if (intel_enable_rc6(dev
) & INTEL_RC6_ENABLE
)
4557 rc6_mode
= GEN7_RC_CTL_TO_MODE
| VLV_RC_CTL_CTX_RST_PARALLEL
;
4559 intel_print_rc6_info(dev
, rc6_mode
);
4561 I915_WRITE(GEN6_RC_CONTROL
, rc6_mode
);
4563 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
4565 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val
& 0x10 ? "yes" : "no");
4566 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val
);
4568 dev_priv
->rps
.cur_freq
= (val
>> 8) & 0xff;
4569 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
4570 vlv_gpu_freq(dev_priv
, dev_priv
->rps
.cur_freq
),
4571 dev_priv
->rps
.cur_freq
);
4573 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
4574 vlv_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
),
4575 dev_priv
->rps
.efficient_freq
);
4577 valleyview_set_rps(dev_priv
->dev
, dev_priv
->rps
.efficient_freq
);
4579 gen6_enable_rps_interrupts(dev
);
4581 gen6_gt_force_wake_put(dev_priv
, FORCEWAKE_ALL
);
4584 void ironlake_teardown_rc6(struct drm_device
*dev
)
4586 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4588 if (dev_priv
->ips
.renderctx
) {
4589 i915_gem_object_ggtt_unpin(dev_priv
->ips
.renderctx
);
4590 drm_gem_object_unreference(&dev_priv
->ips
.renderctx
->base
);
4591 dev_priv
->ips
.renderctx
= NULL
;
4594 if (dev_priv
->ips
.pwrctx
) {
4595 i915_gem_object_ggtt_unpin(dev_priv
->ips
.pwrctx
);
4596 drm_gem_object_unreference(&dev_priv
->ips
.pwrctx
->base
);
4597 dev_priv
->ips
.pwrctx
= NULL
;
4601 static void ironlake_disable_rc6(struct drm_device
*dev
)
4603 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4605 if (I915_READ(PWRCTXA
)) {
4606 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
4607 I915_WRITE(RSTDBYCTL
, I915_READ(RSTDBYCTL
) | RCX_SW_EXIT
);
4608 wait_for(((I915_READ(RSTDBYCTL
) & RSX_STATUS_MASK
) == RSX_STATUS_ON
),
4611 I915_WRITE(PWRCTXA
, 0);
4612 POSTING_READ(PWRCTXA
);
4614 I915_WRITE(RSTDBYCTL
, I915_READ(RSTDBYCTL
) & ~RCX_SW_EXIT
);
4615 POSTING_READ(RSTDBYCTL
);
4619 static int ironlake_setup_rc6(struct drm_device
*dev
)
4621 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4623 if (dev_priv
->ips
.renderctx
== NULL
)
4624 dev_priv
->ips
.renderctx
= intel_alloc_context_page(dev
);
4625 if (!dev_priv
->ips
.renderctx
)
4628 if (dev_priv
->ips
.pwrctx
== NULL
)
4629 dev_priv
->ips
.pwrctx
= intel_alloc_context_page(dev
);
4630 if (!dev_priv
->ips
.pwrctx
) {
4631 ironlake_teardown_rc6(dev
);
4638 static void ironlake_enable_rc6(struct drm_device
*dev
)
4640 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4641 struct intel_engine_cs
*ring
= &dev_priv
->ring
[RCS
];
4642 bool was_interruptible
;
4645 /* rc6 disabled by default due to repeated reports of hanging during
4648 if (!intel_enable_rc6(dev
))
4651 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
4653 ret
= ironlake_setup_rc6(dev
);
4657 was_interruptible
= dev_priv
->mm
.interruptible
;
4658 dev_priv
->mm
.interruptible
= false;
4661 * GPU can automatically power down the render unit if given a page
4664 ret
= intel_ring_begin(ring
, 6);
4666 ironlake_teardown_rc6(dev
);
4667 dev_priv
->mm
.interruptible
= was_interruptible
;
4671 intel_ring_emit(ring
, MI_SUSPEND_FLUSH
| MI_SUSPEND_FLUSH_EN
);
4672 intel_ring_emit(ring
, MI_SET_CONTEXT
);
4673 intel_ring_emit(ring
, i915_gem_obj_ggtt_offset(dev_priv
->ips
.renderctx
) |
4675 MI_SAVE_EXT_STATE_EN
|
4676 MI_RESTORE_EXT_STATE_EN
|
4677 MI_RESTORE_INHIBIT
);
4678 intel_ring_emit(ring
, MI_SUSPEND_FLUSH
);
4679 intel_ring_emit(ring
, MI_NOOP
);
4680 intel_ring_emit(ring
, MI_FLUSH
);
4681 intel_ring_advance(ring
);
4684 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
4685 * does an implicit flush, combined with MI_FLUSH above, it should be
4686 * safe to assume that renderctx is valid
4688 ret
= intel_ring_idle(ring
);
4689 dev_priv
->mm
.interruptible
= was_interruptible
;
4691 DRM_ERROR("failed to enable ironlake power savings\n");
4692 ironlake_teardown_rc6(dev
);
4696 I915_WRITE(PWRCTXA
, i915_gem_obj_ggtt_offset(dev_priv
->ips
.pwrctx
) | PWRCTX_EN
);
4697 I915_WRITE(RSTDBYCTL
, I915_READ(RSTDBYCTL
) & ~RCX_SW_EXIT
);
4699 intel_print_rc6_info(dev
, GEN6_RC_CTL_RC6_ENABLE
);
4702 static unsigned long intel_pxfreq(u32 vidfreq
)
4705 int div
= (vidfreq
& 0x3f0000) >> 16;
4706 int post
= (vidfreq
& 0x3000) >> 12;
4707 int pre
= (vidfreq
& 0x7);
4712 freq
= ((div
* 133333) / ((1<<post
) * pre
));
4717 static const struct cparams
{
4723 { 1, 1333, 301, 28664 },
4724 { 1, 1066, 294, 24460 },
4725 { 1, 800, 294, 25192 },
4726 { 0, 1333, 276, 27605 },
4727 { 0, 1066, 276, 27605 },
4728 { 0, 800, 231, 23784 },
4731 static unsigned long __i915_chipset_val(struct drm_i915_private
*dev_priv
)
4733 u64 total_count
, diff
, ret
;
4734 u32 count1
, count2
, count3
, m
= 0, c
= 0;
4735 unsigned long now
= jiffies_to_msecs(jiffies
), diff1
;
4738 assert_spin_locked(&mchdev_lock
);
4740 diff1
= now
- dev_priv
->ips
.last_time1
;
4742 /* Prevent division-by-zero if we are asking too fast.
4743 * Also, we don't get interesting results if we are polling
4744 * faster than once in 10ms, so just return the saved value
4748 return dev_priv
->ips
.chipset_power
;
4750 count1
= I915_READ(DMIEC
);
4751 count2
= I915_READ(DDREC
);
4752 count3
= I915_READ(CSIEC
);
4754 total_count
= count1
+ count2
+ count3
;
4756 /* FIXME: handle per-counter overflow */
4757 if (total_count
< dev_priv
->ips
.last_count1
) {
4758 diff
= ~0UL - dev_priv
->ips
.last_count1
;
4759 diff
+= total_count
;
4761 diff
= total_count
- dev_priv
->ips
.last_count1
;
4764 for (i
= 0; i
< ARRAY_SIZE(cparams
); i
++) {
4765 if (cparams
[i
].i
== dev_priv
->ips
.c_m
&&
4766 cparams
[i
].t
== dev_priv
->ips
.r_t
) {
4773 diff
= div_u64(diff
, diff1
);
4774 ret
= ((m
* diff
) + c
);
4775 ret
= div_u64(ret
, 10);
4777 dev_priv
->ips
.last_count1
= total_count
;
4778 dev_priv
->ips
.last_time1
= now
;
4780 dev_priv
->ips
.chipset_power
= ret
;
4785 unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
)
4787 struct drm_device
*dev
= dev_priv
->dev
;
4790 if (INTEL_INFO(dev
)->gen
!= 5)
4793 spin_lock_irq(&mchdev_lock
);
4795 val
= __i915_chipset_val(dev_priv
);
4797 spin_unlock_irq(&mchdev_lock
);
4802 unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
)
4804 unsigned long m
, x
, b
;
4807 tsfs
= I915_READ(TSFS
);
4809 m
= ((tsfs
& TSFS_SLOPE_MASK
) >> TSFS_SLOPE_SHIFT
);
4810 x
= I915_READ8(TR1
);
4812 b
= tsfs
& TSFS_INTR_MASK
;
4814 return ((m
* x
) / 127) - b
;
4817 static u16
pvid_to_extvid(struct drm_i915_private
*dev_priv
, u8 pxvid
)
4819 struct drm_device
*dev
= dev_priv
->dev
;
4820 static const struct v_table
{
4821 u16 vd
; /* in .1 mil */
4822 u16 vm
; /* in .1 mil */
4953 if (INTEL_INFO(dev
)->is_mobile
)
4954 return v_table
[pxvid
].vm
;
4956 return v_table
[pxvid
].vd
;
4959 static void __i915_update_gfx_val(struct drm_i915_private
*dev_priv
)
4961 u64 now
, diff
, diffms
;
4964 assert_spin_locked(&mchdev_lock
);
4966 now
= ktime_get_raw_ns();
4967 diffms
= now
- dev_priv
->ips
.last_time2
;
4968 do_div(diffms
, NSEC_PER_MSEC
);
4970 /* Don't divide by 0 */
4974 count
= I915_READ(GFXEC
);
4976 if (count
< dev_priv
->ips
.last_count2
) {
4977 diff
= ~0UL - dev_priv
->ips
.last_count2
;
4980 diff
= count
- dev_priv
->ips
.last_count2
;
4983 dev_priv
->ips
.last_count2
= count
;
4984 dev_priv
->ips
.last_time2
= now
;
4986 /* More magic constants... */
4988 diff
= div_u64(diff
, diffms
* 10);
4989 dev_priv
->ips
.gfx_power
= diff
;
4992 void i915_update_gfx_val(struct drm_i915_private
*dev_priv
)
4994 struct drm_device
*dev
= dev_priv
->dev
;
4996 if (INTEL_INFO(dev
)->gen
!= 5)
4999 spin_lock_irq(&mchdev_lock
);
5001 __i915_update_gfx_val(dev_priv
);
5003 spin_unlock_irq(&mchdev_lock
);
5006 static unsigned long __i915_gfx_val(struct drm_i915_private
*dev_priv
)
5008 unsigned long t
, corr
, state1
, corr2
, state2
;
5011 assert_spin_locked(&mchdev_lock
);
5013 pxvid
= I915_READ(PXVFREQ_BASE
+ (dev_priv
->rps
.cur_freq
* 4));
5014 pxvid
= (pxvid
>> 24) & 0x7f;
5015 ext_v
= pvid_to_extvid(dev_priv
, pxvid
);
5019 t
= i915_mch_val(dev_priv
);
5021 /* Revel in the empirically derived constants */
5023 /* Correction factor in 1/100000 units */
5025 corr
= ((t
* 2349) + 135940);
5027 corr
= ((t
* 964) + 29317);
5029 corr
= ((t
* 301) + 1004);
5031 corr
= corr
* ((150142 * state1
) / 10000 - 78642);
5033 corr2
= (corr
* dev_priv
->ips
.corr
);
5035 state2
= (corr2
* state1
) / 10000;
5036 state2
/= 100; /* convert to mW */
5038 __i915_update_gfx_val(dev_priv
);
5040 return dev_priv
->ips
.gfx_power
+ state2
;
5043 unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
)
5045 struct drm_device
*dev
= dev_priv
->dev
;
5048 if (INTEL_INFO(dev
)->gen
!= 5)
5051 spin_lock_irq(&mchdev_lock
);
5053 val
= __i915_gfx_val(dev_priv
);
5055 spin_unlock_irq(&mchdev_lock
);
5061 * i915_read_mch_val - return value for IPS use
5063 * Calculate and return a value for the IPS driver to use when deciding whether
5064 * we have thermal and power headroom to increase CPU or GPU power budget.
5066 unsigned long i915_read_mch_val(void)
5068 struct drm_i915_private
*dev_priv
;
5069 unsigned long chipset_val
, graphics_val
, ret
= 0;
5071 spin_lock_irq(&mchdev_lock
);
5074 dev_priv
= i915_mch_dev
;
5076 chipset_val
= __i915_chipset_val(dev_priv
);
5077 graphics_val
= __i915_gfx_val(dev_priv
);
5079 ret
= chipset_val
+ graphics_val
;
5082 spin_unlock_irq(&mchdev_lock
);
5086 EXPORT_SYMBOL_GPL(i915_read_mch_val
);
5089 * i915_gpu_raise - raise GPU frequency limit
5091 * Raise the limit; IPS indicates we have thermal headroom.
5093 bool i915_gpu_raise(void)
5095 struct drm_i915_private
*dev_priv
;
5098 spin_lock_irq(&mchdev_lock
);
5099 if (!i915_mch_dev
) {
5103 dev_priv
= i915_mch_dev
;
5105 if (dev_priv
->ips
.max_delay
> dev_priv
->ips
.fmax
)
5106 dev_priv
->ips
.max_delay
--;
5109 spin_unlock_irq(&mchdev_lock
);
5113 EXPORT_SYMBOL_GPL(i915_gpu_raise
);
5116 * i915_gpu_lower - lower GPU frequency limit
5118 * IPS indicates we're close to a thermal limit, so throttle back the GPU
5119 * frequency maximum.
5121 bool i915_gpu_lower(void)
5123 struct drm_i915_private
*dev_priv
;
5126 spin_lock_irq(&mchdev_lock
);
5127 if (!i915_mch_dev
) {
5131 dev_priv
= i915_mch_dev
;
5133 if (dev_priv
->ips
.max_delay
< dev_priv
->ips
.min_delay
)
5134 dev_priv
->ips
.max_delay
++;
5137 spin_unlock_irq(&mchdev_lock
);
5141 EXPORT_SYMBOL_GPL(i915_gpu_lower
);
5144 * i915_gpu_busy - indicate GPU business to IPS
5146 * Tell the IPS driver whether or not the GPU is busy.
5148 bool i915_gpu_busy(void)
5150 struct drm_i915_private
*dev_priv
;
5151 struct intel_engine_cs
*ring
;
5155 spin_lock_irq(&mchdev_lock
);
5158 dev_priv
= i915_mch_dev
;
5160 for_each_ring(ring
, dev_priv
, i
)
5161 ret
|= !list_empty(&ring
->request_list
);
5164 spin_unlock_irq(&mchdev_lock
);
5168 EXPORT_SYMBOL_GPL(i915_gpu_busy
);
5171 * i915_gpu_turbo_disable - disable graphics turbo
5173 * Disable graphics turbo by resetting the max frequency and setting the
5174 * current frequency to the default.
5176 bool i915_gpu_turbo_disable(void)
5178 struct drm_i915_private
*dev_priv
;
5181 spin_lock_irq(&mchdev_lock
);
5182 if (!i915_mch_dev
) {
5186 dev_priv
= i915_mch_dev
;
5188 dev_priv
->ips
.max_delay
= dev_priv
->ips
.fstart
;
5190 if (!ironlake_set_drps(dev_priv
->dev
, dev_priv
->ips
.fstart
))
5194 spin_unlock_irq(&mchdev_lock
);
5198 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable
);
5201 * Tells the intel_ips driver that the i915 driver is now loaded, if
5202 * IPS got loaded first.
5204 * This awkward dance is so that neither module has to depend on the
5205 * other in order for IPS to do the appropriate communication of
5206 * GPU turbo limits to i915.
5209 ips_ping_for_i915_load(void)
5213 link
= symbol_get(ips_link_to_i915_driver
);
5216 symbol_put(ips_link_to_i915_driver
);
5220 void intel_gpu_ips_init(struct drm_i915_private
*dev_priv
)
5222 /* We only register the i915 ips part with intel-ips once everything is
5223 * set up, to avoid intel-ips sneaking in and reading bogus values. */
5224 spin_lock_irq(&mchdev_lock
);
5225 i915_mch_dev
= dev_priv
;
5226 spin_unlock_irq(&mchdev_lock
);
5228 ips_ping_for_i915_load();
5231 void intel_gpu_ips_teardown(void)
5233 spin_lock_irq(&mchdev_lock
);
5234 i915_mch_dev
= NULL
;
5235 spin_unlock_irq(&mchdev_lock
);
5238 static void intel_init_emon(struct drm_device
*dev
)
5240 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5245 /* Disable to program */
5249 /* Program energy weights for various events */
5250 I915_WRITE(SDEW
, 0x15040d00);
5251 I915_WRITE(CSIEW0
, 0x007f0000);
5252 I915_WRITE(CSIEW1
, 0x1e220004);
5253 I915_WRITE(CSIEW2
, 0x04000004);
5255 for (i
= 0; i
< 5; i
++)
5256 I915_WRITE(PEW
+ (i
* 4), 0);
5257 for (i
= 0; i
< 3; i
++)
5258 I915_WRITE(DEW
+ (i
* 4), 0);
5260 /* Program P-state weights to account for frequency power adjustment */
5261 for (i
= 0; i
< 16; i
++) {
5262 u32 pxvidfreq
= I915_READ(PXVFREQ_BASE
+ (i
* 4));
5263 unsigned long freq
= intel_pxfreq(pxvidfreq
);
5264 unsigned long vid
= (pxvidfreq
& PXVFREQ_PX_MASK
) >>
5269 val
*= (freq
/ 1000);
5271 val
/= (127*127*900);
5273 DRM_ERROR("bad pxval: %ld\n", val
);
5276 /* Render standby states get 0 weight */
5280 for (i
= 0; i
< 4; i
++) {
5281 u32 val
= (pxw
[i
*4] << 24) | (pxw
[(i
*4)+1] << 16) |
5282 (pxw
[(i
*4)+2] << 8) | (pxw
[(i
*4)+3]);
5283 I915_WRITE(PXW
+ (i
* 4), val
);
5286 /* Adjust magic regs to magic values (more experimental results) */
5287 I915_WRITE(OGW0
, 0);
5288 I915_WRITE(OGW1
, 0);
5289 I915_WRITE(EG0
, 0x00007f00);
5290 I915_WRITE(EG1
, 0x0000000e);
5291 I915_WRITE(EG2
, 0x000e0000);
5292 I915_WRITE(EG3
, 0x68000300);
5293 I915_WRITE(EG4
, 0x42000000);
5294 I915_WRITE(EG5
, 0x00140031);
5298 for (i
= 0; i
< 8; i
++)
5299 I915_WRITE(PXWL
+ (i
* 4), 0);
5301 /* Enable PMON + select events */
5302 I915_WRITE(ECR
, 0x80000019);
5304 lcfuse
= I915_READ(LCFUSE02
);
5306 dev_priv
->ips
.corr
= (lcfuse
& LCFUSE_HIV_MASK
);
5309 void intel_init_gt_powersave(struct drm_device
*dev
)
5311 i915
.enable_rc6
= sanitize_rc6_option(dev
, i915
.enable_rc6
);
5313 if (IS_CHERRYVIEW(dev
))
5314 cherryview_init_gt_powersave(dev
);
5315 else if (IS_VALLEYVIEW(dev
))
5316 valleyview_init_gt_powersave(dev
);
5319 void intel_cleanup_gt_powersave(struct drm_device
*dev
)
5321 if (IS_CHERRYVIEW(dev
))
5323 else if (IS_VALLEYVIEW(dev
))
5324 valleyview_cleanup_gt_powersave(dev
);
5328 * intel_suspend_gt_powersave - suspend PM work and helper threads
5331 * We don't want to disable RC6 or other features here, we just want
5332 * to make sure any work we've queued has finished and won't bother
5333 * us while we're suspended.
5335 void intel_suspend_gt_powersave(struct drm_device
*dev
)
5337 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5339 /* Interrupts should be disabled already to avoid re-arming. */
5340 WARN_ON(intel_irqs_enabled(dev_priv
));
5342 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
5344 cancel_work_sync(&dev_priv
->rps
.work
);
5346 /* Force GPU to min freq during suspend */
5347 gen6_rps_idle(dev_priv
);
5350 void intel_disable_gt_powersave(struct drm_device
*dev
)
5352 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5354 /* Interrupts should be disabled already to avoid re-arming. */
5355 WARN_ON(intel_irqs_enabled(dev_priv
));
5357 if (IS_IRONLAKE_M(dev
)) {
5358 ironlake_disable_drps(dev
);
5359 ironlake_disable_rc6(dev
);
5360 } else if (INTEL_INFO(dev
)->gen
>= 6) {
5361 intel_suspend_gt_powersave(dev
);
5363 mutex_lock(&dev_priv
->rps
.hw_lock
);
5364 if (IS_CHERRYVIEW(dev
))
5365 cherryview_disable_rps(dev
);
5366 else if (IS_VALLEYVIEW(dev
))
5367 valleyview_disable_rps(dev
);
5369 gen6_disable_rps(dev
);
5370 dev_priv
->rps
.enabled
= false;
5371 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5375 static void intel_gen6_powersave_work(struct work_struct
*work
)
5377 struct drm_i915_private
*dev_priv
=
5378 container_of(work
, struct drm_i915_private
,
5379 rps
.delayed_resume_work
.work
);
5380 struct drm_device
*dev
= dev_priv
->dev
;
5382 dev_priv
->rps
.is_bdw_sw_turbo
= false;
5384 mutex_lock(&dev_priv
->rps
.hw_lock
);
5386 if (IS_CHERRYVIEW(dev
)) {
5387 cherryview_enable_rps(dev
);
5388 } else if (IS_VALLEYVIEW(dev
)) {
5389 valleyview_enable_rps(dev
);
5390 } else if (IS_BROADWELL(dev
)) {
5391 gen8_enable_rps(dev
);
5392 __gen6_update_ring_freq(dev
);
5394 gen6_enable_rps(dev
);
5395 __gen6_update_ring_freq(dev
);
5397 dev_priv
->rps
.enabled
= true;
5398 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5400 intel_runtime_pm_put(dev_priv
);
5403 void intel_enable_gt_powersave(struct drm_device
*dev
)
5405 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5407 if (IS_IRONLAKE_M(dev
)) {
5408 mutex_lock(&dev
->struct_mutex
);
5409 ironlake_enable_drps(dev
);
5410 ironlake_enable_rc6(dev
);
5411 intel_init_emon(dev
);
5412 mutex_unlock(&dev
->struct_mutex
);
5413 } else if (INTEL_INFO(dev
)->gen
>= 6) {
5415 * PCU communication is slow and this doesn't need to be
5416 * done at any specific time, so do this out of our fast path
5417 * to make resume and init faster.
5419 * We depend on the HW RC6 power context save/restore
5420 * mechanism when entering D3 through runtime PM suspend. So
5421 * disable RPM until RPS/RC6 is properly setup. We can only
5422 * get here via the driver load/system resume/runtime resume
5423 * paths, so the _noresume version is enough (and in case of
5424 * runtime resume it's necessary).
5426 if (schedule_delayed_work(&dev_priv
->rps
.delayed_resume_work
,
5427 round_jiffies_up_relative(HZ
)))
5428 intel_runtime_pm_get_noresume(dev_priv
);
5432 void intel_reset_gt_powersave(struct drm_device
*dev
)
5434 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5436 dev_priv
->rps
.enabled
= false;
5437 intel_enable_gt_powersave(dev
);
5440 static void ibx_init_clock_gating(struct drm_device
*dev
)
5442 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5445 * On Ibex Peak and Cougar Point, we need to disable clock
5446 * gating for the panel power sequencer or it will fail to
5447 * start up when no ports are active.
5449 I915_WRITE(SOUTH_DSPCLK_GATE_D
, PCH_DPLSUNIT_CLOCK_GATE_DISABLE
);
5452 static void g4x_disable_trickle_feed(struct drm_device
*dev
)
5454 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5457 for_each_pipe(dev_priv
, pipe
) {
5458 I915_WRITE(DSPCNTR(pipe
),
5459 I915_READ(DSPCNTR(pipe
)) |
5460 DISPPLANE_TRICKLE_FEED_DISABLE
);
5461 intel_flush_primary_plane(dev_priv
, pipe
);
5465 static void ilk_init_lp_watermarks(struct drm_device
*dev
)
5467 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5469 I915_WRITE(WM3_LP_ILK
, I915_READ(WM3_LP_ILK
) & ~WM1_LP_SR_EN
);
5470 I915_WRITE(WM2_LP_ILK
, I915_READ(WM2_LP_ILK
) & ~WM1_LP_SR_EN
);
5471 I915_WRITE(WM1_LP_ILK
, I915_READ(WM1_LP_ILK
) & ~WM1_LP_SR_EN
);
5474 * Don't touch WM1S_LP_EN here.
5475 * Doing so could cause underruns.
5479 static void ironlake_init_clock_gating(struct drm_device
*dev
)
5481 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5482 uint32_t dspclk_gate
= ILK_VRHUNIT_CLOCK_GATE_DISABLE
;
5486 * WaFbcDisableDpfcClockGating:ilk
5488 dspclk_gate
|= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE
|
5489 ILK_DPFCUNIT_CLOCK_GATE_DISABLE
|
5490 ILK_DPFDUNIT_CLOCK_GATE_ENABLE
;
5492 I915_WRITE(PCH_3DCGDIS0
,
5493 MARIUNIT_CLOCK_GATE_DISABLE
|
5494 SVSMUNIT_CLOCK_GATE_DISABLE
);
5495 I915_WRITE(PCH_3DCGDIS1
,
5496 VFMUNIT_CLOCK_GATE_DISABLE
);
5499 * According to the spec the following bits should be set in
5500 * order to enable memory self-refresh
5501 * The bit 22/21 of 0x42004
5502 * The bit 5 of 0x42020
5503 * The bit 15 of 0x45000
5505 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
5506 (I915_READ(ILK_DISPLAY_CHICKEN2
) |
5507 ILK_DPARB_GATE
| ILK_VSDPFD_FULL
));
5508 dspclk_gate
|= ILK_DPARBUNIT_CLOCK_GATE_ENABLE
;
5509 I915_WRITE(DISP_ARB_CTL
,
5510 (I915_READ(DISP_ARB_CTL
) |
5513 ilk_init_lp_watermarks(dev
);
5516 * Based on the document from hardware guys the following bits
5517 * should be set unconditionally in order to enable FBC.
5518 * The bit 22 of 0x42000
5519 * The bit 22 of 0x42004
5520 * The bit 7,8,9 of 0x42020.
5522 if (IS_IRONLAKE_M(dev
)) {
5523 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
5524 I915_WRITE(ILK_DISPLAY_CHICKEN1
,
5525 I915_READ(ILK_DISPLAY_CHICKEN1
) |
5527 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
5528 I915_READ(ILK_DISPLAY_CHICKEN2
) |
5532 I915_WRITE(ILK_DSPCLK_GATE_D
, dspclk_gate
);
5534 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
5535 I915_READ(ILK_DISPLAY_CHICKEN2
) |
5536 ILK_ELPIN_409_SELECT
);
5537 I915_WRITE(_3D_CHICKEN2
,
5538 _3D_CHICKEN2_WM_READ_PIPELINED
<< 16 |
5539 _3D_CHICKEN2_WM_READ_PIPELINED
);
5541 /* WaDisableRenderCachePipelinedFlush:ilk */
5542 I915_WRITE(CACHE_MODE_0
,
5543 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE
));
5545 /* WaDisable_RenderCache_OperationalFlush:ilk */
5546 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
5548 g4x_disable_trickle_feed(dev
);
5550 ibx_init_clock_gating(dev
);
5553 static void cpt_init_clock_gating(struct drm_device
*dev
)
5555 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5560 * On Ibex Peak and Cougar Point, we need to disable clock
5561 * gating for the panel power sequencer or it will fail to
5562 * start up when no ports are active.
5564 I915_WRITE(SOUTH_DSPCLK_GATE_D
, PCH_DPLSUNIT_CLOCK_GATE_DISABLE
|
5565 PCH_DPLUNIT_CLOCK_GATE_DISABLE
|
5566 PCH_CPUNIT_CLOCK_GATE_DISABLE
);
5567 I915_WRITE(SOUTH_CHICKEN2
, I915_READ(SOUTH_CHICKEN2
) |
5568 DPLS_EDP_PPS_FIX_DIS
);
5569 /* The below fixes the weird display corruption, a few pixels shifted
5570 * downward, on (only) LVDS of some HP laptops with IVY.
5572 for_each_pipe(dev_priv
, pipe
) {
5573 val
= I915_READ(TRANS_CHICKEN2(pipe
));
5574 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
5575 val
&= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED
;
5576 if (dev_priv
->vbt
.fdi_rx_polarity_inverted
)
5577 val
|= TRANS_CHICKEN2_FDI_POLARITY_REVERSED
;
5578 val
&= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK
;
5579 val
&= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER
;
5580 val
&= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH
;
5581 I915_WRITE(TRANS_CHICKEN2(pipe
), val
);
5583 /* WADP0ClockGatingDisable */
5584 for_each_pipe(dev_priv
, pipe
) {
5585 I915_WRITE(TRANS_CHICKEN1(pipe
),
5586 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE
);
5590 static void gen6_check_mch_setup(struct drm_device
*dev
)
5592 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5595 tmp
= I915_READ(MCH_SSKPD
);
5596 if ((tmp
& MCH_SSKPD_WM0_MASK
) != MCH_SSKPD_WM0_VAL
)
5597 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
5601 static void gen6_init_clock_gating(struct drm_device
*dev
)
5603 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5604 uint32_t dspclk_gate
= ILK_VRHUNIT_CLOCK_GATE_DISABLE
;
5606 I915_WRITE(ILK_DSPCLK_GATE_D
, dspclk_gate
);
5608 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
5609 I915_READ(ILK_DISPLAY_CHICKEN2
) |
5610 ILK_ELPIN_409_SELECT
);
5612 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
5613 I915_WRITE(_3D_CHICKEN
,
5614 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB
));
5616 /* WaSetupGtModeTdRowDispatch:snb */
5617 if (IS_SNB_GT1(dev
))
5618 I915_WRITE(GEN6_GT_MODE
,
5619 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE
));
5621 /* WaDisable_RenderCache_OperationalFlush:snb */
5622 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
5625 * BSpec recoomends 8x4 when MSAA is used,
5626 * however in practice 16x4 seems fastest.
5628 * Note that PS/WM thread counts depend on the WIZ hashing
5629 * disable bit, which we don't touch here, but it's good
5630 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5632 I915_WRITE(GEN6_GT_MODE
,
5633 GEN6_WIZ_HASHING_MASK
| GEN6_WIZ_HASHING_16x4
);
5635 ilk_init_lp_watermarks(dev
);
5637 I915_WRITE(CACHE_MODE_0
,
5638 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB
));
5640 I915_WRITE(GEN6_UCGCTL1
,
5641 I915_READ(GEN6_UCGCTL1
) |
5642 GEN6_BLBUNIT_CLOCK_GATE_DISABLE
|
5643 GEN6_CSUNIT_CLOCK_GATE_DISABLE
);
5645 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5646 * gating disable must be set. Failure to set it results in
5647 * flickering pixels due to Z write ordering failures after
5648 * some amount of runtime in the Mesa "fire" demo, and Unigine
5649 * Sanctuary and Tropics, and apparently anything else with
5650 * alpha test or pixel discard.
5652 * According to the spec, bit 11 (RCCUNIT) must also be set,
5653 * but we didn't debug actual testcases to find it out.
5655 * WaDisableRCCUnitClockGating:snb
5656 * WaDisableRCPBUnitClockGating:snb
5658 I915_WRITE(GEN6_UCGCTL2
,
5659 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE
|
5660 GEN6_RCCUNIT_CLOCK_GATE_DISABLE
);
5662 /* WaStripsFansDisableFastClipPerformanceFix:snb */
5663 I915_WRITE(_3D_CHICKEN3
,
5664 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL
));
5668 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
5669 * 3DSTATE_SF number of SF output attributes is more than 16."
5671 I915_WRITE(_3D_CHICKEN3
,
5672 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH
));
5675 * According to the spec the following bits should be
5676 * set in order to enable memory self-refresh and fbc:
5677 * The bit21 and bit22 of 0x42000
5678 * The bit21 and bit22 of 0x42004
5679 * The bit5 and bit7 of 0x42020
5680 * The bit14 of 0x70180
5681 * The bit14 of 0x71180
5683 * WaFbcAsynchFlipDisableFbcQueue:snb
5685 I915_WRITE(ILK_DISPLAY_CHICKEN1
,
5686 I915_READ(ILK_DISPLAY_CHICKEN1
) |
5687 ILK_FBCQ_DIS
| ILK_PABSTRETCH_DIS
);
5688 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
5689 I915_READ(ILK_DISPLAY_CHICKEN2
) |
5690 ILK_DPARB_GATE
| ILK_VSDPFD_FULL
);
5691 I915_WRITE(ILK_DSPCLK_GATE_D
,
5692 I915_READ(ILK_DSPCLK_GATE_D
) |
5693 ILK_DPARBUNIT_CLOCK_GATE_ENABLE
|
5694 ILK_DPFDUNIT_CLOCK_GATE_ENABLE
);
5696 g4x_disable_trickle_feed(dev
);
5698 cpt_init_clock_gating(dev
);
5700 gen6_check_mch_setup(dev
);
5703 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private
*dev_priv
)
5705 uint32_t reg
= I915_READ(GEN7_FF_THREAD_MODE
);
5708 * WaVSThreadDispatchOverride:ivb,vlv
5710 * This actually overrides the dispatch
5711 * mode for all thread types.
5713 reg
&= ~GEN7_FF_SCHED_MASK
;
5714 reg
|= GEN7_FF_TS_SCHED_HW
;
5715 reg
|= GEN7_FF_VS_SCHED_HW
;
5716 reg
|= GEN7_FF_DS_SCHED_HW
;
5718 I915_WRITE(GEN7_FF_THREAD_MODE
, reg
);
5721 static void lpt_init_clock_gating(struct drm_device
*dev
)
5723 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5726 * TODO: this bit should only be enabled when really needed, then
5727 * disabled when not needed anymore in order to save power.
5729 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
)
5730 I915_WRITE(SOUTH_DSPCLK_GATE_D
,
5731 I915_READ(SOUTH_DSPCLK_GATE_D
) |
5732 PCH_LP_PARTITION_LEVEL_DISABLE
);
5734 /* WADPOClockGatingDisable:hsw */
5735 I915_WRITE(_TRANSA_CHICKEN1
,
5736 I915_READ(_TRANSA_CHICKEN1
) |
5737 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE
);
5740 static void lpt_suspend_hw(struct drm_device
*dev
)
5742 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5744 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
5745 uint32_t val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
5747 val
&= ~PCH_LP_PARTITION_LEVEL_DISABLE
;
5748 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
5752 static void broadwell_init_clock_gating(struct drm_device
*dev
)
5754 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5757 I915_WRITE(WM3_LP_ILK
, 0);
5758 I915_WRITE(WM2_LP_ILK
, 0);
5759 I915_WRITE(WM1_LP_ILK
, 0);
5761 /* FIXME(BDW): Check all the w/a, some might only apply to
5762 * pre-production hw. */
5765 I915_WRITE(GAMTARBMODE
, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE
));
5767 I915_WRITE(_3D_CHICKEN3
,
5768 _MASKED_BIT_ENABLE(_3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2)));
5771 /* WaSwitchSolVfFArbitrationPriority:bdw */
5772 I915_WRITE(GAM_ECOCHK
, I915_READ(GAM_ECOCHK
) | HSW_ECOCHK_ARB_PRIO_SOL
);
5774 /* WaPsrDPAMaskVBlankInSRD:bdw */
5775 I915_WRITE(CHICKEN_PAR1_1
,
5776 I915_READ(CHICKEN_PAR1_1
) | DPA_MASK_VBLANK_SRD
);
5778 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
5779 for_each_pipe(dev_priv
, pipe
) {
5780 I915_WRITE(CHICKEN_PIPESL_1(pipe
),
5781 I915_READ(CHICKEN_PIPESL_1(pipe
)) |
5782 BDW_DPRS_MASK_VBLANK_SRD
);
5785 /* WaVSRefCountFullforceMissDisable:bdw */
5786 /* WaDSRefCountFullforceMissDisable:bdw */
5787 I915_WRITE(GEN7_FF_THREAD_MODE
,
5788 I915_READ(GEN7_FF_THREAD_MODE
) &
5789 ~(GEN8_FF_DS_REF_CNT_FFME
| GEN7_FF_VS_REF_CNT_FFME
));
5791 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL
,
5792 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE
));
5794 /* WaDisableSDEUnitClockGating:bdw */
5795 I915_WRITE(GEN8_UCGCTL6
, I915_READ(GEN8_UCGCTL6
) |
5796 GEN8_SDEUNIT_CLOCK_GATE_DISABLE
);
5798 lpt_init_clock_gating(dev
);
5801 static void haswell_init_clock_gating(struct drm_device
*dev
)
5803 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5805 ilk_init_lp_watermarks(dev
);
5807 /* L3 caching of data atomics doesn't work -- disable it. */
5808 I915_WRITE(HSW_SCRATCH1
, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE
);
5809 I915_WRITE(HSW_ROW_CHICKEN3
,
5810 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE
));
5812 /* This is required by WaCatErrorRejectionIssue:hsw */
5813 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
5814 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
5815 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
5817 /* WaVSRefCountFullforceMissDisable:hsw */
5818 I915_WRITE(GEN7_FF_THREAD_MODE
,
5819 I915_READ(GEN7_FF_THREAD_MODE
) & ~GEN7_FF_VS_REF_CNT_FFME
);
5821 /* WaDisable_RenderCache_OperationalFlush:hsw */
5822 I915_WRITE(CACHE_MODE_0_GEN7
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
5824 /* enable HiZ Raw Stall Optimization */
5825 I915_WRITE(CACHE_MODE_0_GEN7
,
5826 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE
));
5828 /* WaDisable4x2SubspanOptimization:hsw */
5829 I915_WRITE(CACHE_MODE_1
,
5830 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
));
5833 * BSpec recommends 8x4 when MSAA is used,
5834 * however in practice 16x4 seems fastest.
5836 * Note that PS/WM thread counts depend on the WIZ hashing
5837 * disable bit, which we don't touch here, but it's good
5838 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5840 I915_WRITE(GEN7_GT_MODE
,
5841 GEN6_WIZ_HASHING_MASK
| GEN6_WIZ_HASHING_16x4
);
5843 /* WaSwitchSolVfFArbitrationPriority:hsw */
5844 I915_WRITE(GAM_ECOCHK
, I915_READ(GAM_ECOCHK
) | HSW_ECOCHK_ARB_PRIO_SOL
);
5846 /* WaRsPkgCStateDisplayPMReq:hsw */
5847 I915_WRITE(CHICKEN_PAR1_1
,
5848 I915_READ(CHICKEN_PAR1_1
) | FORCE_ARB_IDLE_PLANES
);
5850 lpt_init_clock_gating(dev
);
5853 static void ivybridge_init_clock_gating(struct drm_device
*dev
)
5855 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5858 ilk_init_lp_watermarks(dev
);
5860 I915_WRITE(ILK_DSPCLK_GATE_D
, ILK_VRHUNIT_CLOCK_GATE_DISABLE
);
5862 /* WaDisableEarlyCull:ivb */
5863 I915_WRITE(_3D_CHICKEN3
,
5864 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL
));
5866 /* WaDisableBackToBackFlipFix:ivb */
5867 I915_WRITE(IVB_CHICKEN3
,
5868 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE
|
5869 CHICKEN3_DGMG_DONE_FIX_DISABLE
);
5871 /* WaDisablePSDDualDispatchEnable:ivb */
5872 if (IS_IVB_GT1(dev
))
5873 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1
,
5874 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE
));
5876 /* WaDisable_RenderCache_OperationalFlush:ivb */
5877 I915_WRITE(CACHE_MODE_0_GEN7
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
5879 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
5880 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1
,
5881 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC
);
5883 /* WaApplyL3ControlAndL3ChickenMode:ivb */
5884 I915_WRITE(GEN7_L3CNTLREG1
,
5885 GEN7_WA_FOR_GEN7_L3_CONTROL
);
5886 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER
,
5887 GEN7_WA_L3_CHICKEN_MODE
);
5888 if (IS_IVB_GT1(dev
))
5889 I915_WRITE(GEN7_ROW_CHICKEN2
,
5890 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
5892 /* must write both registers */
5893 I915_WRITE(GEN7_ROW_CHICKEN2
,
5894 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
5895 I915_WRITE(GEN7_ROW_CHICKEN2_GT2
,
5896 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
5899 /* WaForceL3Serialization:ivb */
5900 I915_WRITE(GEN7_L3SQCREG4
, I915_READ(GEN7_L3SQCREG4
) &
5901 ~L3SQ_URB_READ_CAM_MATCH_DISABLE
);
5904 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5905 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
5907 I915_WRITE(GEN6_UCGCTL2
,
5908 GEN6_RCZUNIT_CLOCK_GATE_DISABLE
);
5910 /* This is required by WaCatErrorRejectionIssue:ivb */
5911 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
5912 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
5913 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
5915 g4x_disable_trickle_feed(dev
);
5917 gen7_setup_fixed_func_scheduler(dev_priv
);
5919 if (0) { /* causes HiZ corruption on ivb:gt1 */
5920 /* enable HiZ Raw Stall Optimization */
5921 I915_WRITE(CACHE_MODE_0_GEN7
,
5922 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE
));
5925 /* WaDisable4x2SubspanOptimization:ivb */
5926 I915_WRITE(CACHE_MODE_1
,
5927 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
));
5930 * BSpec recommends 8x4 when MSAA is used,
5931 * however in practice 16x4 seems fastest.
5933 * Note that PS/WM thread counts depend on the WIZ hashing
5934 * disable bit, which we don't touch here, but it's good
5935 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5937 I915_WRITE(GEN7_GT_MODE
,
5938 GEN6_WIZ_HASHING_MASK
| GEN6_WIZ_HASHING_16x4
);
5940 snpcr
= I915_READ(GEN6_MBCUNIT_SNPCR
);
5941 snpcr
&= ~GEN6_MBC_SNPCR_MASK
;
5942 snpcr
|= GEN6_MBC_SNPCR_MED
;
5943 I915_WRITE(GEN6_MBCUNIT_SNPCR
, snpcr
);
5945 if (!HAS_PCH_NOP(dev
))
5946 cpt_init_clock_gating(dev
);
5948 gen6_check_mch_setup(dev
);
5951 static void valleyview_init_clock_gating(struct drm_device
*dev
)
5953 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5955 I915_WRITE(DSPCLK_GATE_D
, VRHUNIT_CLOCK_GATE_DISABLE
);
5957 /* WaDisableEarlyCull:vlv */
5958 I915_WRITE(_3D_CHICKEN3
,
5959 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL
));
5961 /* WaDisableBackToBackFlipFix:vlv */
5962 I915_WRITE(IVB_CHICKEN3
,
5963 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE
|
5964 CHICKEN3_DGMG_DONE_FIX_DISABLE
);
5966 /* WaPsdDispatchEnable:vlv */
5967 /* WaDisablePSDDualDispatchEnable:vlv */
5968 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1
,
5969 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP
|
5970 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE
));
5972 /* WaDisable_RenderCache_OperationalFlush:vlv */
5973 I915_WRITE(CACHE_MODE_0_GEN7
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
5975 /* WaForceL3Serialization:vlv */
5976 I915_WRITE(GEN7_L3SQCREG4
, I915_READ(GEN7_L3SQCREG4
) &
5977 ~L3SQ_URB_READ_CAM_MATCH_DISABLE
);
5979 /* WaDisableDopClockGating:vlv */
5980 I915_WRITE(GEN7_ROW_CHICKEN2
,
5981 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
5983 /* This is required by WaCatErrorRejectionIssue:vlv */
5984 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
5985 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
5986 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
5988 gen7_setup_fixed_func_scheduler(dev_priv
);
5991 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5992 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
5994 I915_WRITE(GEN6_UCGCTL2
,
5995 GEN6_RCZUNIT_CLOCK_GATE_DISABLE
);
5997 /* WaDisableL3Bank2xClockGate:vlv
5998 * Disabling L3 clock gating- MMIO 940c[25] = 1
5999 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
6000 I915_WRITE(GEN7_UCGCTL4
,
6001 I915_READ(GEN7_UCGCTL4
) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE
);
6003 I915_WRITE(MI_ARB_VLV
, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
);
6006 * BSpec says this must be set, even though
6007 * WaDisable4x2SubspanOptimization isn't listed for VLV.
6009 I915_WRITE(CACHE_MODE_1
,
6010 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
));
6013 * WaIncreaseL3CreditsForVLVB0:vlv
6014 * This is the hardware default actually.
6016 I915_WRITE(GEN7_L3SQCREG1
, VLV_B0_WA_L3SQCREG1_VALUE
);
6019 * WaDisableVLVClockGating_VBIIssue:vlv
6020 * Disable clock gating on th GCFG unit to prevent a delay
6021 * in the reporting of vblank events.
6023 I915_WRITE(VLV_GUNIT_CLOCK_GATE
, GCFG_DIS
);
6026 static void cherryview_init_clock_gating(struct drm_device
*dev
)
6028 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6030 I915_WRITE(DSPCLK_GATE_D
, VRHUNIT_CLOCK_GATE_DISABLE
);
6032 I915_WRITE(MI_ARB_VLV
, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
);
6034 /* WaVSRefCountFullforceMissDisable:chv */
6035 /* WaDSRefCountFullforceMissDisable:chv */
6036 I915_WRITE(GEN7_FF_THREAD_MODE
,
6037 I915_READ(GEN7_FF_THREAD_MODE
) &
6038 ~(GEN8_FF_DS_REF_CNT_FFME
| GEN7_FF_VS_REF_CNT_FFME
));
6040 /* WaDisableSemaphoreAndSyncFlipWait:chv */
6041 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL
,
6042 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE
));
6044 /* WaDisableCSUnitClockGating:chv */
6045 I915_WRITE(GEN6_UCGCTL1
, I915_READ(GEN6_UCGCTL1
) |
6046 GEN6_CSUNIT_CLOCK_GATE_DISABLE
);
6048 /* WaDisableSDEUnitClockGating:chv */
6049 I915_WRITE(GEN8_UCGCTL6
, I915_READ(GEN8_UCGCTL6
) |
6050 GEN8_SDEUNIT_CLOCK_GATE_DISABLE
);
6052 /* WaDisableGunitClockGating:chv (pre-production hw) */
6053 I915_WRITE(VLV_GUNIT_CLOCK_GATE
, I915_READ(VLV_GUNIT_CLOCK_GATE
) |
6056 /* WaDisableFfDopClockGating:chv (pre-production hw) */
6057 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL
,
6058 _MASKED_BIT_ENABLE(GEN8_FF_DOP_CLOCK_GATE_DISABLE
));
6060 /* WaDisableDopClockGating:chv (pre-production hw) */
6061 I915_WRITE(GEN6_UCGCTL1
, I915_READ(GEN6_UCGCTL1
) |
6062 GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE
);
6065 static void g4x_init_clock_gating(struct drm_device
*dev
)
6067 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6068 uint32_t dspclk_gate
;
6070 I915_WRITE(RENCLK_GATE_D1
, 0);
6071 I915_WRITE(RENCLK_GATE_D2
, VF_UNIT_CLOCK_GATE_DISABLE
|
6072 GS_UNIT_CLOCK_GATE_DISABLE
|
6073 CL_UNIT_CLOCK_GATE_DISABLE
);
6074 I915_WRITE(RAMCLK_GATE_D
, 0);
6075 dspclk_gate
= VRHUNIT_CLOCK_GATE_DISABLE
|
6076 OVRUNIT_CLOCK_GATE_DISABLE
|
6077 OVCUNIT_CLOCK_GATE_DISABLE
;
6079 dspclk_gate
|= DSSUNIT_CLOCK_GATE_DISABLE
;
6080 I915_WRITE(DSPCLK_GATE_D
, dspclk_gate
);
6082 /* WaDisableRenderCachePipelinedFlush */
6083 I915_WRITE(CACHE_MODE_0
,
6084 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE
));
6086 /* WaDisable_RenderCache_OperationalFlush:g4x */
6087 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
6089 g4x_disable_trickle_feed(dev
);
6092 static void crestline_init_clock_gating(struct drm_device
*dev
)
6094 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6096 I915_WRITE(RENCLK_GATE_D1
, I965_RCC_CLOCK_GATE_DISABLE
);
6097 I915_WRITE(RENCLK_GATE_D2
, 0);
6098 I915_WRITE(DSPCLK_GATE_D
, 0);
6099 I915_WRITE(RAMCLK_GATE_D
, 0);
6100 I915_WRITE16(DEUC
, 0);
6101 I915_WRITE(MI_ARB_STATE
,
6102 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
));
6104 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6105 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
6108 static void broadwater_init_clock_gating(struct drm_device
*dev
)
6110 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6112 I915_WRITE(RENCLK_GATE_D1
, I965_RCZ_CLOCK_GATE_DISABLE
|
6113 I965_RCC_CLOCK_GATE_DISABLE
|
6114 I965_RCPB_CLOCK_GATE_DISABLE
|
6115 I965_ISC_CLOCK_GATE_DISABLE
|
6116 I965_FBC_CLOCK_GATE_DISABLE
);
6117 I915_WRITE(RENCLK_GATE_D2
, 0);
6118 I915_WRITE(MI_ARB_STATE
,
6119 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
));
6121 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6122 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
6125 static void gen3_init_clock_gating(struct drm_device
*dev
)
6127 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6128 u32 dstate
= I915_READ(D_STATE
);
6130 dstate
|= DSTATE_PLL_D3_OFF
| DSTATE_GFX_CLOCK_GATING
|
6131 DSTATE_DOT_CLOCK_GATING
;
6132 I915_WRITE(D_STATE
, dstate
);
6134 if (IS_PINEVIEW(dev
))
6135 I915_WRITE(ECOSKPD
, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY
));
6137 /* IIR "flip pending" means done if this bit is set */
6138 I915_WRITE(ECOSKPD
, _MASKED_BIT_DISABLE(ECO_FLIP_DONE
));
6140 /* interrupts should cause a wake up from C3 */
6141 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN
));
6143 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
6144 I915_WRITE(MI_ARB_STATE
, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE
));
6146 I915_WRITE(MI_ARB_STATE
,
6147 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
));
6150 static void i85x_init_clock_gating(struct drm_device
*dev
)
6152 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6154 I915_WRITE(RENCLK_GATE_D1
, SV_CLOCK_GATE_DISABLE
);
6156 /* interrupts should cause a wake up from C3 */
6157 I915_WRITE(MI_STATE
, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN
) |
6158 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE
));
6160 I915_WRITE(MEM_MODE
,
6161 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE
));
6164 static void i830_init_clock_gating(struct drm_device
*dev
)
6166 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6168 I915_WRITE(DSPCLK_GATE_D
, OVRUNIT_CLOCK_GATE_DISABLE
);
6170 I915_WRITE(MEM_MODE
,
6171 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE
) |
6172 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE
));
6175 void intel_init_clock_gating(struct drm_device
*dev
)
6177 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6179 dev_priv
->display
.init_clock_gating(dev
);
6182 void intel_suspend_hw(struct drm_device
*dev
)
6184 if (HAS_PCH_LPT(dev
))
6185 lpt_suspend_hw(dev
);
6188 #define for_each_power_well(i, power_well, domain_mask, power_domains) \
6190 i < (power_domains)->power_well_count && \
6191 ((power_well) = &(power_domains)->power_wells[i]); \
6193 if ((power_well)->domains & (domain_mask))
6195 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
6196 for (i = (power_domains)->power_well_count - 1; \
6197 i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
6199 if ((power_well)->domains & (domain_mask))
6202 * We should only use the power well if we explicitly asked the hardware to
6203 * enable it, so check if it's enabled and also check if we've requested it to
6206 static bool hsw_power_well_enabled(struct drm_i915_private
*dev_priv
,
6207 struct i915_power_well
*power_well
)
6209 return I915_READ(HSW_PWR_WELL_DRIVER
) ==
6210 (HSW_PWR_WELL_ENABLE_REQUEST
| HSW_PWR_WELL_STATE_ENABLED
);
6213 bool intel_display_power_enabled_unlocked(struct drm_i915_private
*dev_priv
,
6214 enum intel_display_power_domain domain
)
6216 struct i915_power_domains
*power_domains
;
6217 struct i915_power_well
*power_well
;
6221 if (dev_priv
->pm
.suspended
)
6224 power_domains
= &dev_priv
->power_domains
;
6228 for_each_power_well_rev(i
, power_well
, BIT(domain
), power_domains
) {
6229 if (power_well
->always_on
)
6232 if (!power_well
->hw_enabled
) {
6241 bool intel_display_power_enabled(struct drm_i915_private
*dev_priv
,
6242 enum intel_display_power_domain domain
)
6244 struct i915_power_domains
*power_domains
;
6247 power_domains
= &dev_priv
->power_domains
;
6249 mutex_lock(&power_domains
->lock
);
6250 ret
= intel_display_power_enabled_unlocked(dev_priv
, domain
);
6251 mutex_unlock(&power_domains
->lock
);
6257 * Starting with Haswell, we have a "Power Down Well" that can be turned off
6258 * when not needed anymore. We have 4 registers that can request the power well
6259 * to be enabled, and it will only be disabled if none of the registers is
6260 * requesting it to be enabled.
6262 static void hsw_power_well_post_enable(struct drm_i915_private
*dev_priv
)
6264 struct drm_device
*dev
= dev_priv
->dev
;
6267 * After we re-enable the power well, if we touch VGA register 0x3d5
6268 * we'll get unclaimed register interrupts. This stops after we write
6269 * anything to the VGA MSR register. The vgacon module uses this
6270 * register all the time, so if we unbind our driver and, as a
6271 * consequence, bind vgacon, we'll get stuck in an infinite loop at
6272 * console_unlock(). So make here we touch the VGA MSR register, making
6273 * sure vgacon can keep working normally without triggering interrupts
6274 * and error messages.
6276 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
6277 outb(inb(VGA_MSR_READ
), VGA_MSR_WRITE
);
6278 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
6280 if (IS_BROADWELL(dev
) || (INTEL_INFO(dev
)->gen
>= 9))
6281 gen8_irq_power_well_post_enable(dev_priv
);
6284 static void hsw_set_power_well(struct drm_i915_private
*dev_priv
,
6285 struct i915_power_well
*power_well
, bool enable
)
6287 bool is_enabled
, enable_requested
;
6290 tmp
= I915_READ(HSW_PWR_WELL_DRIVER
);
6291 is_enabled
= tmp
& HSW_PWR_WELL_STATE_ENABLED
;
6292 enable_requested
= tmp
& HSW_PWR_WELL_ENABLE_REQUEST
;
6295 if (!enable_requested
)
6296 I915_WRITE(HSW_PWR_WELL_DRIVER
,
6297 HSW_PWR_WELL_ENABLE_REQUEST
);
6300 DRM_DEBUG_KMS("Enabling power well\n");
6301 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER
) &
6302 HSW_PWR_WELL_STATE_ENABLED
), 20))
6303 DRM_ERROR("Timeout enabling power well\n");
6306 hsw_power_well_post_enable(dev_priv
);
6308 if (enable_requested
) {
6309 I915_WRITE(HSW_PWR_WELL_DRIVER
, 0);
6310 POSTING_READ(HSW_PWR_WELL_DRIVER
);
6311 DRM_DEBUG_KMS("Requesting to disable the power well\n");
6316 static void hsw_power_well_sync_hw(struct drm_i915_private
*dev_priv
,
6317 struct i915_power_well
*power_well
)
6319 hsw_set_power_well(dev_priv
, power_well
, power_well
->count
> 0);
6322 * We're taking over the BIOS, so clear any requests made by it since
6323 * the driver is in charge now.
6325 if (I915_READ(HSW_PWR_WELL_BIOS
) & HSW_PWR_WELL_ENABLE_REQUEST
)
6326 I915_WRITE(HSW_PWR_WELL_BIOS
, 0);
6329 static void hsw_power_well_enable(struct drm_i915_private
*dev_priv
,
6330 struct i915_power_well
*power_well
)
6332 hsw_set_power_well(dev_priv
, power_well
, true);
6335 static void hsw_power_well_disable(struct drm_i915_private
*dev_priv
,
6336 struct i915_power_well
*power_well
)
6338 hsw_set_power_well(dev_priv
, power_well
, false);
6341 static void i9xx_always_on_power_well_noop(struct drm_i915_private
*dev_priv
,
6342 struct i915_power_well
*power_well
)
6346 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private
*dev_priv
,
6347 struct i915_power_well
*power_well
)
6352 static void vlv_set_power_well(struct drm_i915_private
*dev_priv
,
6353 struct i915_power_well
*power_well
, bool enable
)
6355 enum punit_power_well power_well_id
= power_well
->data
;
6360 mask
= PUNIT_PWRGT_MASK(power_well_id
);
6361 state
= enable
? PUNIT_PWRGT_PWR_ON(power_well_id
) :
6362 PUNIT_PWRGT_PWR_GATE(power_well_id
);
6364 mutex_lock(&dev_priv
->rps
.hw_lock
);
6367 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
6372 ctrl
= vlv_punit_read(dev_priv
, PUNIT_REG_PWRGT_CTRL
);
6375 vlv_punit_write(dev_priv
, PUNIT_REG_PWRGT_CTRL
, ctrl
);
6377 if (wait_for(COND
, 100))
6378 DRM_ERROR("timout setting power well state %08x (%08x)\n",
6380 vlv_punit_read(dev_priv
, PUNIT_REG_PWRGT_CTRL
));
6385 mutex_unlock(&dev_priv
->rps
.hw_lock
);
6388 static void vlv_power_well_sync_hw(struct drm_i915_private
*dev_priv
,
6389 struct i915_power_well
*power_well
)
6391 vlv_set_power_well(dev_priv
, power_well
, power_well
->count
> 0);
6394 static void vlv_power_well_enable(struct drm_i915_private
*dev_priv
,
6395 struct i915_power_well
*power_well
)
6397 vlv_set_power_well(dev_priv
, power_well
, true);
6400 static void vlv_power_well_disable(struct drm_i915_private
*dev_priv
,
6401 struct i915_power_well
*power_well
)
6403 vlv_set_power_well(dev_priv
, power_well
, false);
6406 static bool vlv_power_well_enabled(struct drm_i915_private
*dev_priv
,
6407 struct i915_power_well
*power_well
)
6409 int power_well_id
= power_well
->data
;
6410 bool enabled
= false;
6415 mask
= PUNIT_PWRGT_MASK(power_well_id
);
6416 ctrl
= PUNIT_PWRGT_PWR_ON(power_well_id
);
6418 mutex_lock(&dev_priv
->rps
.hw_lock
);
6420 state
= vlv_punit_read(dev_priv
, PUNIT_REG_PWRGT_STATUS
) & mask
;
6422 * We only ever set the power-on and power-gate states, anything
6423 * else is unexpected.
6425 WARN_ON(state
!= PUNIT_PWRGT_PWR_ON(power_well_id
) &&
6426 state
!= PUNIT_PWRGT_PWR_GATE(power_well_id
));
6431 * A transient state at this point would mean some unexpected party
6432 * is poking at the power controls too.
6434 ctrl
= vlv_punit_read(dev_priv
, PUNIT_REG_PWRGT_CTRL
) & mask
;
6435 WARN_ON(ctrl
!= state
);
6437 mutex_unlock(&dev_priv
->rps
.hw_lock
);
6442 static void vlv_display_power_well_enable(struct drm_i915_private
*dev_priv
,
6443 struct i915_power_well
*power_well
)
6445 WARN_ON_ONCE(power_well
->data
!= PUNIT_POWER_WELL_DISP2D
);
6447 vlv_set_power_well(dev_priv
, power_well
, true);
6449 spin_lock_irq(&dev_priv
->irq_lock
);
6450 valleyview_enable_display_irqs(dev_priv
);
6451 spin_unlock_irq(&dev_priv
->irq_lock
);
6454 * During driver initialization/resume we can avoid restoring the
6455 * part of the HW/SW state that will be inited anyway explicitly.
6457 if (dev_priv
->power_domains
.initializing
)
6460 intel_hpd_init(dev_priv
->dev
);
6462 i915_redisable_vga_power_on(dev_priv
->dev
);
6465 static void vlv_display_power_well_disable(struct drm_i915_private
*dev_priv
,
6466 struct i915_power_well
*power_well
)
6468 WARN_ON_ONCE(power_well
->data
!= PUNIT_POWER_WELL_DISP2D
);
6470 spin_lock_irq(&dev_priv
->irq_lock
);
6471 valleyview_disable_display_irqs(dev_priv
);
6472 spin_unlock_irq(&dev_priv
->irq_lock
);
6474 vlv_set_power_well(dev_priv
, power_well
, false);
6476 vlv_power_sequencer_reset(dev_priv
);
6479 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private
*dev_priv
,
6480 struct i915_power_well
*power_well
)
6482 WARN_ON_ONCE(power_well
->data
!= PUNIT_POWER_WELL_DPIO_CMN_BC
);
6485 * Enable the CRI clock source so we can get at the
6486 * display and the reference clock for VGA
6487 * hotplug / manual detection.
6489 I915_WRITE(DPLL(PIPE_B
), I915_READ(DPLL(PIPE_B
)) |
6490 DPLL_REFA_CLK_ENABLE_VLV
| DPLL_INTEGRATED_CRI_CLK_VLV
);
6491 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
6493 vlv_set_power_well(dev_priv
, power_well
, true);
6496 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
6497 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
6498 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
6499 * b. The other bits such as sfr settings / modesel may all
6502 * This should only be done on init and resume from S3 with
6503 * both PLLs disabled, or we risk losing DPIO and PLL
6506 I915_WRITE(DPIO_CTL
, I915_READ(DPIO_CTL
) | DPIO_CMNRST
);
6509 static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private
*dev_priv
,
6510 struct i915_power_well
*power_well
)
6514 WARN_ON_ONCE(power_well
->data
!= PUNIT_POWER_WELL_DPIO_CMN_BC
);
6516 for_each_pipe(dev_priv
, pipe
)
6517 assert_pll_disabled(dev_priv
, pipe
);
6519 /* Assert common reset */
6520 I915_WRITE(DPIO_CTL
, I915_READ(DPIO_CTL
) & ~DPIO_CMNRST
);
6522 vlv_set_power_well(dev_priv
, power_well
, false);
6525 static void chv_dpio_cmn_power_well_enable(struct drm_i915_private
*dev_priv
,
6526 struct i915_power_well
*power_well
)
6530 WARN_ON_ONCE(power_well
->data
!= PUNIT_POWER_WELL_DPIO_CMN_BC
&&
6531 power_well
->data
!= PUNIT_POWER_WELL_DPIO_CMN_D
);
6534 * Enable the CRI clock source so we can get at the
6535 * display and the reference clock for VGA
6536 * hotplug / manual detection.
6538 if (power_well
->data
== PUNIT_POWER_WELL_DPIO_CMN_BC
) {
6540 I915_WRITE(DPLL(PIPE_B
), I915_READ(DPLL(PIPE_B
)) |
6541 DPLL_REFA_CLK_ENABLE_VLV
);
6542 I915_WRITE(DPLL(PIPE_B
), I915_READ(DPLL(PIPE_B
)) |
6543 DPLL_REFA_CLK_ENABLE_VLV
| DPLL_INTEGRATED_CRI_CLK_VLV
);
6546 I915_WRITE(DPLL(PIPE_C
), I915_READ(DPLL(PIPE_C
)) |
6547 DPLL_REFA_CLK_ENABLE_VLV
| DPLL_INTEGRATED_CRI_CLK_VLV
);
6549 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
6550 vlv_set_power_well(dev_priv
, power_well
, true);
6552 /* Poll for phypwrgood signal */
6553 if (wait_for(I915_READ(DISPLAY_PHY_STATUS
) & PHY_POWERGOOD(phy
), 1))
6554 DRM_ERROR("Display PHY %d is not power up\n", phy
);
6556 I915_WRITE(DISPLAY_PHY_CONTROL
, I915_READ(DISPLAY_PHY_CONTROL
) |
6557 PHY_COM_LANE_RESET_DEASSERT(phy
));
6560 static void chv_dpio_cmn_power_well_disable(struct drm_i915_private
*dev_priv
,
6561 struct i915_power_well
*power_well
)
6565 WARN_ON_ONCE(power_well
->data
!= PUNIT_POWER_WELL_DPIO_CMN_BC
&&
6566 power_well
->data
!= PUNIT_POWER_WELL_DPIO_CMN_D
);
6568 if (power_well
->data
== PUNIT_POWER_WELL_DPIO_CMN_BC
) {
6570 assert_pll_disabled(dev_priv
, PIPE_A
);
6571 assert_pll_disabled(dev_priv
, PIPE_B
);
6574 assert_pll_disabled(dev_priv
, PIPE_C
);
6577 I915_WRITE(DISPLAY_PHY_CONTROL
, I915_READ(DISPLAY_PHY_CONTROL
) &
6578 ~PHY_COM_LANE_RESET_DEASSERT(phy
));
6580 vlv_set_power_well(dev_priv
, power_well
, false);
6583 static bool chv_pipe_power_well_enabled(struct drm_i915_private
*dev_priv
,
6584 struct i915_power_well
*power_well
)
6586 enum pipe pipe
= power_well
->data
;
6590 mutex_lock(&dev_priv
->rps
.hw_lock
);
6592 state
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) & DP_SSS_MASK(pipe
);
6594 * We only ever set the power-on and power-gate states, anything
6595 * else is unexpected.
6597 WARN_ON(state
!= DP_SSS_PWR_ON(pipe
) && state
!= DP_SSS_PWR_GATE(pipe
));
6598 enabled
= state
== DP_SSS_PWR_ON(pipe
);
6601 * A transient state at this point would mean some unexpected party
6602 * is poking at the power controls too.
6604 ctrl
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) & DP_SSC_MASK(pipe
);
6605 WARN_ON(ctrl
<< 16 != state
);
6607 mutex_unlock(&dev_priv
->rps
.hw_lock
);
6612 static void chv_set_pipe_power_well(struct drm_i915_private
*dev_priv
,
6613 struct i915_power_well
*power_well
,
6616 enum pipe pipe
= power_well
->data
;
6620 state
= enable
? DP_SSS_PWR_ON(pipe
) : DP_SSS_PWR_GATE(pipe
);
6622 mutex_lock(&dev_priv
->rps
.hw_lock
);
6625 ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state)
6630 ctrl
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
6631 ctrl
&= ~DP_SSC_MASK(pipe
);
6632 ctrl
|= enable
? DP_SSC_PWR_ON(pipe
) : DP_SSC_PWR_GATE(pipe
);
6633 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, ctrl
);
6635 if (wait_for(COND
, 100))
6636 DRM_ERROR("timout setting power well state %08x (%08x)\n",
6638 vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
));
6643 mutex_unlock(&dev_priv
->rps
.hw_lock
);
6646 static void chv_pipe_power_well_sync_hw(struct drm_i915_private
*dev_priv
,
6647 struct i915_power_well
*power_well
)
6649 chv_set_pipe_power_well(dev_priv
, power_well
, power_well
->count
> 0);
6652 static void chv_pipe_power_well_enable(struct drm_i915_private
*dev_priv
,
6653 struct i915_power_well
*power_well
)
6655 WARN_ON_ONCE(power_well
->data
!= PIPE_A
&&
6656 power_well
->data
!= PIPE_B
&&
6657 power_well
->data
!= PIPE_C
);
6659 chv_set_pipe_power_well(dev_priv
, power_well
, true);
6662 static void chv_pipe_power_well_disable(struct drm_i915_private
*dev_priv
,
6663 struct i915_power_well
*power_well
)
6665 WARN_ON_ONCE(power_well
->data
!= PIPE_A
&&
6666 power_well
->data
!= PIPE_B
&&
6667 power_well
->data
!= PIPE_C
);
6669 chv_set_pipe_power_well(dev_priv
, power_well
, false);
6672 static void check_power_well_state(struct drm_i915_private
*dev_priv
,
6673 struct i915_power_well
*power_well
)
6675 bool enabled
= power_well
->ops
->is_enabled(dev_priv
, power_well
);
6677 if (power_well
->always_on
|| !i915
.disable_power_well
) {
6684 if (enabled
!= (power_well
->count
> 0))
6690 WARN(1, "state mismatch for '%s' (always_on %d hw state %d use-count %d disable_power_well %d\n",
6691 power_well
->name
, power_well
->always_on
, enabled
,
6692 power_well
->count
, i915
.disable_power_well
);
6695 void intel_display_power_get(struct drm_i915_private
*dev_priv
,
6696 enum intel_display_power_domain domain
)
6698 struct i915_power_domains
*power_domains
;
6699 struct i915_power_well
*power_well
;
6702 intel_runtime_pm_get(dev_priv
);
6704 power_domains
= &dev_priv
->power_domains
;
6706 mutex_lock(&power_domains
->lock
);
6708 for_each_power_well(i
, power_well
, BIT(domain
), power_domains
) {
6709 if (!power_well
->count
++) {
6710 DRM_DEBUG_KMS("enabling %s\n", power_well
->name
);
6711 power_well
->ops
->enable(dev_priv
, power_well
);
6712 power_well
->hw_enabled
= true;
6715 check_power_well_state(dev_priv
, power_well
);
6718 power_domains
->domain_use_count
[domain
]++;
6720 mutex_unlock(&power_domains
->lock
);
6723 void intel_display_power_put(struct drm_i915_private
*dev_priv
,
6724 enum intel_display_power_domain domain
)
6726 struct i915_power_domains
*power_domains
;
6727 struct i915_power_well
*power_well
;
6730 power_domains
= &dev_priv
->power_domains
;
6732 mutex_lock(&power_domains
->lock
);
6734 WARN_ON(!power_domains
->domain_use_count
[domain
]);
6735 power_domains
->domain_use_count
[domain
]--;
6737 for_each_power_well_rev(i
, power_well
, BIT(domain
), power_domains
) {
6738 WARN_ON(!power_well
->count
);
6740 if (!--power_well
->count
&& i915
.disable_power_well
) {
6741 DRM_DEBUG_KMS("disabling %s\n", power_well
->name
);
6742 power_well
->hw_enabled
= false;
6743 power_well
->ops
->disable(dev_priv
, power_well
);
6746 check_power_well_state(dev_priv
, power_well
);
6749 mutex_unlock(&power_domains
->lock
);
6751 intel_runtime_pm_put(dev_priv
);
6754 static struct i915_power_domains
*hsw_pwr
;
6756 /* Display audio driver power well request */
6757 int i915_request_power_well(void)
6759 struct drm_i915_private
*dev_priv
;
6764 dev_priv
= container_of(hsw_pwr
, struct drm_i915_private
,
6766 intel_display_power_get(dev_priv
, POWER_DOMAIN_AUDIO
);
6769 EXPORT_SYMBOL_GPL(i915_request_power_well
);
6771 /* Display audio driver power well release */
6772 int i915_release_power_well(void)
6774 struct drm_i915_private
*dev_priv
;
6779 dev_priv
= container_of(hsw_pwr
, struct drm_i915_private
,
6781 intel_display_power_put(dev_priv
, POWER_DOMAIN_AUDIO
);
6784 EXPORT_SYMBOL_GPL(i915_release_power_well
);
6787 * Private interface for the audio driver to get CDCLK in kHz.
6789 * Caller must request power well using i915_request_power_well() prior to
6792 int i915_get_cdclk_freq(void)
6794 struct drm_i915_private
*dev_priv
;
6799 dev_priv
= container_of(hsw_pwr
, struct drm_i915_private
,
6802 return intel_ddi_get_cdclk_freq(dev_priv
);
6804 EXPORT_SYMBOL_GPL(i915_get_cdclk_freq
);
6807 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
6809 #define HSW_ALWAYS_ON_POWER_DOMAINS ( \
6810 BIT(POWER_DOMAIN_PIPE_A) | \
6811 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
6812 BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
6813 BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
6814 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6815 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6816 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6817 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6818 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
6819 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
6820 BIT(POWER_DOMAIN_PORT_CRT) | \
6821 BIT(POWER_DOMAIN_PLLS) | \
6822 BIT(POWER_DOMAIN_INIT))
6823 #define HSW_DISPLAY_POWER_DOMAINS ( \
6824 (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \
6825 BIT(POWER_DOMAIN_INIT))
6827 #define BDW_ALWAYS_ON_POWER_DOMAINS ( \
6828 HSW_ALWAYS_ON_POWER_DOMAINS | \
6829 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
6830 #define BDW_DISPLAY_POWER_DOMAINS ( \
6831 (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) | \
6832 BIT(POWER_DOMAIN_INIT))
6834 #define VLV_ALWAYS_ON_POWER_DOMAINS BIT(POWER_DOMAIN_INIT)
6835 #define VLV_DISPLAY_POWER_DOMAINS POWER_DOMAIN_MASK
6837 #define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \
6838 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6839 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6840 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6841 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6842 BIT(POWER_DOMAIN_PORT_CRT) | \
6843 BIT(POWER_DOMAIN_INIT))
6845 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \
6846 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6847 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6848 BIT(POWER_DOMAIN_INIT))
6850 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \
6851 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6852 BIT(POWER_DOMAIN_INIT))
6854 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \
6855 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6856 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6857 BIT(POWER_DOMAIN_INIT))
6859 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \
6860 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6861 BIT(POWER_DOMAIN_INIT))
6863 #define CHV_PIPE_A_POWER_DOMAINS ( \
6864 BIT(POWER_DOMAIN_PIPE_A) | \
6865 BIT(POWER_DOMAIN_INIT))
6867 #define CHV_PIPE_B_POWER_DOMAINS ( \
6868 BIT(POWER_DOMAIN_PIPE_B) | \
6869 BIT(POWER_DOMAIN_INIT))
6871 #define CHV_PIPE_C_POWER_DOMAINS ( \
6872 BIT(POWER_DOMAIN_PIPE_C) | \
6873 BIT(POWER_DOMAIN_INIT))
6875 #define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \
6876 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6877 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6878 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6879 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6880 BIT(POWER_DOMAIN_INIT))
6882 #define CHV_DPIO_CMN_D_POWER_DOMAINS ( \
6883 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
6884 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
6885 BIT(POWER_DOMAIN_INIT))
6887 #define CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS ( \
6888 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
6889 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
6890 BIT(POWER_DOMAIN_INIT))
6892 #define CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS ( \
6893 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
6894 BIT(POWER_DOMAIN_INIT))
6896 static const struct i915_power_well_ops i9xx_always_on_power_well_ops
= {
6897 .sync_hw
= i9xx_always_on_power_well_noop
,
6898 .enable
= i9xx_always_on_power_well_noop
,
6899 .disable
= i9xx_always_on_power_well_noop
,
6900 .is_enabled
= i9xx_always_on_power_well_enabled
,
6903 static const struct i915_power_well_ops chv_pipe_power_well_ops
= {
6904 .sync_hw
= chv_pipe_power_well_sync_hw
,
6905 .enable
= chv_pipe_power_well_enable
,
6906 .disable
= chv_pipe_power_well_disable
,
6907 .is_enabled
= chv_pipe_power_well_enabled
,
6910 static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops
= {
6911 .sync_hw
= vlv_power_well_sync_hw
,
6912 .enable
= chv_dpio_cmn_power_well_enable
,
6913 .disable
= chv_dpio_cmn_power_well_disable
,
6914 .is_enabled
= vlv_power_well_enabled
,
6917 static struct i915_power_well i9xx_always_on_power_well
[] = {
6919 .name
= "always-on",
6921 .domains
= POWER_DOMAIN_MASK
,
6922 .ops
= &i9xx_always_on_power_well_ops
,
6926 static const struct i915_power_well_ops hsw_power_well_ops
= {
6927 .sync_hw
= hsw_power_well_sync_hw
,
6928 .enable
= hsw_power_well_enable
,
6929 .disable
= hsw_power_well_disable
,
6930 .is_enabled
= hsw_power_well_enabled
,
6933 static struct i915_power_well hsw_power_wells
[] = {
6935 .name
= "always-on",
6937 .domains
= HSW_ALWAYS_ON_POWER_DOMAINS
,
6938 .ops
= &i9xx_always_on_power_well_ops
,
6942 .domains
= HSW_DISPLAY_POWER_DOMAINS
,
6943 .ops
= &hsw_power_well_ops
,
6947 static struct i915_power_well bdw_power_wells
[] = {
6949 .name
= "always-on",
6951 .domains
= BDW_ALWAYS_ON_POWER_DOMAINS
,
6952 .ops
= &i9xx_always_on_power_well_ops
,
6956 .domains
= BDW_DISPLAY_POWER_DOMAINS
,
6957 .ops
= &hsw_power_well_ops
,
6961 static const struct i915_power_well_ops vlv_display_power_well_ops
= {
6962 .sync_hw
= vlv_power_well_sync_hw
,
6963 .enable
= vlv_display_power_well_enable
,
6964 .disable
= vlv_display_power_well_disable
,
6965 .is_enabled
= vlv_power_well_enabled
,
6968 static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops
= {
6969 .sync_hw
= vlv_power_well_sync_hw
,
6970 .enable
= vlv_dpio_cmn_power_well_enable
,
6971 .disable
= vlv_dpio_cmn_power_well_disable
,
6972 .is_enabled
= vlv_power_well_enabled
,
6975 static const struct i915_power_well_ops vlv_dpio_power_well_ops
= {
6976 .sync_hw
= vlv_power_well_sync_hw
,
6977 .enable
= vlv_power_well_enable
,
6978 .disable
= vlv_power_well_disable
,
6979 .is_enabled
= vlv_power_well_enabled
,
6982 static struct i915_power_well vlv_power_wells
[] = {
6984 .name
= "always-on",
6986 .domains
= VLV_ALWAYS_ON_POWER_DOMAINS
,
6987 .ops
= &i9xx_always_on_power_well_ops
,
6991 .domains
= VLV_DISPLAY_POWER_DOMAINS
,
6992 .data
= PUNIT_POWER_WELL_DISP2D
,
6993 .ops
= &vlv_display_power_well_ops
,
6996 .name
= "dpio-tx-b-01",
6997 .domains
= VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS
|
6998 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS
|
6999 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS
|
7000 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS
,
7001 .ops
= &vlv_dpio_power_well_ops
,
7002 .data
= PUNIT_POWER_WELL_DPIO_TX_B_LANES_01
,
7005 .name
= "dpio-tx-b-23",
7006 .domains
= VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS
|
7007 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS
|
7008 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS
|
7009 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS
,
7010 .ops
= &vlv_dpio_power_well_ops
,
7011 .data
= PUNIT_POWER_WELL_DPIO_TX_B_LANES_23
,
7014 .name
= "dpio-tx-c-01",
7015 .domains
= VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS
|
7016 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS
|
7017 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS
|
7018 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS
,
7019 .ops
= &vlv_dpio_power_well_ops
,
7020 .data
= PUNIT_POWER_WELL_DPIO_TX_C_LANES_01
,
7023 .name
= "dpio-tx-c-23",
7024 .domains
= VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS
|
7025 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS
|
7026 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS
|
7027 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS
,
7028 .ops
= &vlv_dpio_power_well_ops
,
7029 .data
= PUNIT_POWER_WELL_DPIO_TX_C_LANES_23
,
7032 .name
= "dpio-common",
7033 .domains
= VLV_DPIO_CMN_BC_POWER_DOMAINS
,
7034 .data
= PUNIT_POWER_WELL_DPIO_CMN_BC
,
7035 .ops
= &vlv_dpio_cmn_power_well_ops
,
7039 static struct i915_power_well chv_power_wells
[] = {
7041 .name
= "always-on",
7043 .domains
= VLV_ALWAYS_ON_POWER_DOMAINS
,
7044 .ops
= &i9xx_always_on_power_well_ops
,
7049 .domains
= VLV_DISPLAY_POWER_DOMAINS
,
7050 .data
= PUNIT_POWER_WELL_DISP2D
,
7051 .ops
= &vlv_display_power_well_ops
,
7055 .domains
= CHV_PIPE_A_POWER_DOMAINS
,
7057 .ops
= &chv_pipe_power_well_ops
,
7061 .domains
= CHV_PIPE_B_POWER_DOMAINS
,
7063 .ops
= &chv_pipe_power_well_ops
,
7067 .domains
= CHV_PIPE_C_POWER_DOMAINS
,
7069 .ops
= &chv_pipe_power_well_ops
,
7073 .name
= "dpio-common-bc",
7075 * XXX: cmnreset for one PHY seems to disturb the other.
7076 * As a workaround keep both powered on at the same
7079 .domains
= CHV_DPIO_CMN_BC_POWER_DOMAINS
| CHV_DPIO_CMN_D_POWER_DOMAINS
,
7080 .data
= PUNIT_POWER_WELL_DPIO_CMN_BC
,
7081 .ops
= &chv_dpio_cmn_power_well_ops
,
7084 .name
= "dpio-common-d",
7086 * XXX: cmnreset for one PHY seems to disturb the other.
7087 * As a workaround keep both powered on at the same
7090 .domains
= CHV_DPIO_CMN_BC_POWER_DOMAINS
| CHV_DPIO_CMN_D_POWER_DOMAINS
,
7091 .data
= PUNIT_POWER_WELL_DPIO_CMN_D
,
7092 .ops
= &chv_dpio_cmn_power_well_ops
,
7096 .name
= "dpio-tx-b-01",
7097 .domains
= VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS
|
7098 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS
,
7099 .ops
= &vlv_dpio_power_well_ops
,
7100 .data
= PUNIT_POWER_WELL_DPIO_TX_B_LANES_01
,
7103 .name
= "dpio-tx-b-23",
7104 .domains
= VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS
|
7105 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS
,
7106 .ops
= &vlv_dpio_power_well_ops
,
7107 .data
= PUNIT_POWER_WELL_DPIO_TX_B_LANES_23
,
7110 .name
= "dpio-tx-c-01",
7111 .domains
= VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS
|
7112 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS
,
7113 .ops
= &vlv_dpio_power_well_ops
,
7114 .data
= PUNIT_POWER_WELL_DPIO_TX_C_LANES_01
,
7117 .name
= "dpio-tx-c-23",
7118 .domains
= VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS
|
7119 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS
,
7120 .ops
= &vlv_dpio_power_well_ops
,
7121 .data
= PUNIT_POWER_WELL_DPIO_TX_C_LANES_23
,
7124 .name
= "dpio-tx-d-01",
7125 .domains
= CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS
|
7126 CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS
,
7127 .ops
= &vlv_dpio_power_well_ops
,
7128 .data
= PUNIT_POWER_WELL_DPIO_TX_D_LANES_01
,
7131 .name
= "dpio-tx-d-23",
7132 .domains
= CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS
|
7133 CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS
,
7134 .ops
= &vlv_dpio_power_well_ops
,
7135 .data
= PUNIT_POWER_WELL_DPIO_TX_D_LANES_23
,
7140 static struct i915_power_well
*lookup_power_well(struct drm_i915_private
*dev_priv
,
7141 enum punit_power_well power_well_id
)
7143 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
7144 struct i915_power_well
*power_well
;
7147 for_each_power_well(i
, power_well
, POWER_DOMAIN_MASK
, power_domains
) {
7148 if (power_well
->data
== power_well_id
)
7155 #define set_power_wells(power_domains, __power_wells) ({ \
7156 (power_domains)->power_wells = (__power_wells); \
7157 (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \
7160 int intel_power_domains_init(struct drm_i915_private
*dev_priv
)
7162 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
7164 mutex_init(&power_domains
->lock
);
7167 * The enabling order will be from lower to higher indexed wells,
7168 * the disabling order is reversed.
7170 if (IS_HASWELL(dev_priv
->dev
)) {
7171 set_power_wells(power_domains
, hsw_power_wells
);
7172 hsw_pwr
= power_domains
;
7173 } else if (IS_BROADWELL(dev_priv
->dev
)) {
7174 set_power_wells(power_domains
, bdw_power_wells
);
7175 hsw_pwr
= power_domains
;
7176 } else if (IS_CHERRYVIEW(dev_priv
->dev
)) {
7177 set_power_wells(power_domains
, chv_power_wells
);
7178 } else if (IS_VALLEYVIEW(dev_priv
->dev
)) {
7179 set_power_wells(power_domains
, vlv_power_wells
);
7181 set_power_wells(power_domains
, i9xx_always_on_power_well
);
7187 void intel_power_domains_remove(struct drm_i915_private
*dev_priv
)
7192 static void intel_power_domains_resume(struct drm_i915_private
*dev_priv
)
7194 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
7195 struct i915_power_well
*power_well
;
7198 mutex_lock(&power_domains
->lock
);
7199 for_each_power_well(i
, power_well
, POWER_DOMAIN_MASK
, power_domains
) {
7200 power_well
->ops
->sync_hw(dev_priv
, power_well
);
7201 power_well
->hw_enabled
= power_well
->ops
->is_enabled(dev_priv
,
7204 mutex_unlock(&power_domains
->lock
);
7207 static void vlv_cmnlane_wa(struct drm_i915_private
*dev_priv
)
7209 struct i915_power_well
*cmn
=
7210 lookup_power_well(dev_priv
, PUNIT_POWER_WELL_DPIO_CMN_BC
);
7211 struct i915_power_well
*disp2d
=
7212 lookup_power_well(dev_priv
, PUNIT_POWER_WELL_DISP2D
);
7214 /* nothing to do if common lane is already off */
7215 if (!cmn
->ops
->is_enabled(dev_priv
, cmn
))
7218 /* If the display might be already active skip this */
7219 if (disp2d
->ops
->is_enabled(dev_priv
, disp2d
) &&
7220 I915_READ(DPIO_CTL
) & DPIO_CMNRST
)
7223 DRM_DEBUG_KMS("toggling display PHY side reset\n");
7225 /* cmnlane needs DPLL registers */
7226 disp2d
->ops
->enable(dev_priv
, disp2d
);
7229 * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
7230 * Need to assert and de-assert PHY SB reset by gating the
7231 * common lane power, then un-gating it.
7232 * Simply ungating isn't enough to reset the PHY enough to get
7233 * ports and lanes running.
7235 cmn
->ops
->disable(dev_priv
, cmn
);
7238 void intel_power_domains_init_hw(struct drm_i915_private
*dev_priv
)
7240 struct drm_device
*dev
= dev_priv
->dev
;
7241 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
7243 power_domains
->initializing
= true;
7245 if (IS_VALLEYVIEW(dev
) && !IS_CHERRYVIEW(dev
)) {
7246 mutex_lock(&power_domains
->lock
);
7247 vlv_cmnlane_wa(dev_priv
);
7248 mutex_unlock(&power_domains
->lock
);
7251 /* For now, we need the power well to be always enabled. */
7252 intel_display_set_init_power(dev_priv
, true);
7253 intel_power_domains_resume(dev_priv
);
7254 power_domains
->initializing
= false;
7257 void intel_aux_display_runtime_get(struct drm_i915_private
*dev_priv
)
7259 intel_runtime_pm_get(dev_priv
);
7262 void intel_aux_display_runtime_put(struct drm_i915_private
*dev_priv
)
7264 intel_runtime_pm_put(dev_priv
);
7267 void intel_runtime_pm_get(struct drm_i915_private
*dev_priv
)
7269 struct drm_device
*dev
= dev_priv
->dev
;
7270 struct device
*device
= &dev
->pdev
->dev
;
7272 if (!HAS_RUNTIME_PM(dev
))
7275 pm_runtime_get_sync(device
);
7276 WARN(dev_priv
->pm
.suspended
, "Device still suspended.\n");
7279 void intel_runtime_pm_get_noresume(struct drm_i915_private
*dev_priv
)
7281 struct drm_device
*dev
= dev_priv
->dev
;
7282 struct device
*device
= &dev
->pdev
->dev
;
7284 if (!HAS_RUNTIME_PM(dev
))
7287 WARN(dev_priv
->pm
.suspended
, "Getting nosync-ref while suspended.\n");
7288 pm_runtime_get_noresume(device
);
7291 void intel_runtime_pm_put(struct drm_i915_private
*dev_priv
)
7293 struct drm_device
*dev
= dev_priv
->dev
;
7294 struct device
*device
= &dev
->pdev
->dev
;
7296 if (!HAS_RUNTIME_PM(dev
))
7299 pm_runtime_mark_last_busy(device
);
7300 pm_runtime_put_autosuspend(device
);
7303 void intel_init_runtime_pm(struct drm_i915_private
*dev_priv
)
7305 struct drm_device
*dev
= dev_priv
->dev
;
7306 struct device
*device
= &dev
->pdev
->dev
;
7308 if (!HAS_RUNTIME_PM(dev
))
7311 pm_runtime_set_active(device
);
7314 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
7317 if (!intel_enable_rc6(dev
)) {
7318 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
7322 pm_runtime_set_autosuspend_delay(device
, 10000); /* 10s */
7323 pm_runtime_mark_last_busy(device
);
7324 pm_runtime_use_autosuspend(device
);
7326 pm_runtime_put_autosuspend(device
);
7329 void intel_fini_runtime_pm(struct drm_i915_private
*dev_priv
)
7331 struct drm_device
*dev
= dev_priv
->dev
;
7332 struct device
*device
= &dev
->pdev
->dev
;
7334 if (!HAS_RUNTIME_PM(dev
))
7337 if (!intel_enable_rc6(dev
))
7340 /* Make sure we're not suspended first. */
7341 pm_runtime_get_sync(device
);
7342 pm_runtime_disable(device
);
7345 /* Set up chip specific power management-related functions */
7346 void intel_init_pm(struct drm_device
*dev
)
7348 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7351 if (INTEL_INFO(dev
)->gen
>= 7) {
7352 dev_priv
->display
.fbc_enabled
= ironlake_fbc_enabled
;
7353 dev_priv
->display
.enable_fbc
= gen7_enable_fbc
;
7354 dev_priv
->display
.disable_fbc
= ironlake_disable_fbc
;
7355 } else if (INTEL_INFO(dev
)->gen
>= 5) {
7356 dev_priv
->display
.fbc_enabled
= ironlake_fbc_enabled
;
7357 dev_priv
->display
.enable_fbc
= ironlake_enable_fbc
;
7358 dev_priv
->display
.disable_fbc
= ironlake_disable_fbc
;
7359 } else if (IS_GM45(dev
)) {
7360 dev_priv
->display
.fbc_enabled
= g4x_fbc_enabled
;
7361 dev_priv
->display
.enable_fbc
= g4x_enable_fbc
;
7362 dev_priv
->display
.disable_fbc
= g4x_disable_fbc
;
7364 dev_priv
->display
.fbc_enabled
= i8xx_fbc_enabled
;
7365 dev_priv
->display
.enable_fbc
= i8xx_enable_fbc
;
7366 dev_priv
->display
.disable_fbc
= i8xx_disable_fbc
;
7368 /* This value was pulled out of someone's hat */
7369 I915_WRITE(FBC_CONTROL
, 500 << FBC_CTL_INTERVAL_SHIFT
);
7374 if (IS_PINEVIEW(dev
))
7375 i915_pineview_get_mem_freq(dev
);
7376 else if (IS_GEN5(dev
))
7377 i915_ironlake_get_mem_freq(dev
);
7379 /* For FIFO watermark updates */
7380 if (HAS_PCH_SPLIT(dev
)) {
7381 ilk_setup_wm_latency(dev
);
7383 if ((IS_GEN5(dev
) && dev_priv
->wm
.pri_latency
[1] &&
7384 dev_priv
->wm
.spr_latency
[1] && dev_priv
->wm
.cur_latency
[1]) ||
7385 (!IS_GEN5(dev
) && dev_priv
->wm
.pri_latency
[0] &&
7386 dev_priv
->wm
.spr_latency
[0] && dev_priv
->wm
.cur_latency
[0])) {
7387 dev_priv
->display
.update_wm
= ilk_update_wm
;
7388 dev_priv
->display
.update_sprite_wm
= ilk_update_sprite_wm
;
7390 DRM_DEBUG_KMS("Failed to read display plane latency. "
7395 dev_priv
->display
.init_clock_gating
= ironlake_init_clock_gating
;
7396 else if (IS_GEN6(dev
))
7397 dev_priv
->display
.init_clock_gating
= gen6_init_clock_gating
;
7398 else if (IS_IVYBRIDGE(dev
))
7399 dev_priv
->display
.init_clock_gating
= ivybridge_init_clock_gating
;
7400 else if (IS_HASWELL(dev
))
7401 dev_priv
->display
.init_clock_gating
= haswell_init_clock_gating
;
7402 else if (INTEL_INFO(dev
)->gen
== 8)
7403 dev_priv
->display
.init_clock_gating
= broadwell_init_clock_gating
;
7404 else if (INTEL_INFO(dev
)->gen
== 9)
7405 dev_priv
->display
.init_clock_gating
= gen9_init_clock_gating
;
7406 } else if (IS_CHERRYVIEW(dev
)) {
7407 dev_priv
->display
.update_wm
= cherryview_update_wm
;
7408 dev_priv
->display
.update_sprite_wm
= valleyview_update_sprite_wm
;
7409 dev_priv
->display
.init_clock_gating
=
7410 cherryview_init_clock_gating
;
7411 } else if (IS_VALLEYVIEW(dev
)) {
7412 dev_priv
->display
.update_wm
= valleyview_update_wm
;
7413 dev_priv
->display
.update_sprite_wm
= valleyview_update_sprite_wm
;
7414 dev_priv
->display
.init_clock_gating
=
7415 valleyview_init_clock_gating
;
7416 } else if (IS_PINEVIEW(dev
)) {
7417 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev
),
7420 dev_priv
->mem_freq
)) {
7421 DRM_INFO("failed to find known CxSR latency "
7422 "(found ddr%s fsb freq %d, mem freq %d), "
7424 (dev_priv
->is_ddr3
== 1) ? "3" : "2",
7425 dev_priv
->fsb_freq
, dev_priv
->mem_freq
);
7426 /* Disable CxSR and never update its watermark again */
7427 intel_set_memory_cxsr(dev_priv
, false);
7428 dev_priv
->display
.update_wm
= NULL
;
7430 dev_priv
->display
.update_wm
= pineview_update_wm
;
7431 dev_priv
->display
.init_clock_gating
= gen3_init_clock_gating
;
7432 } else if (IS_G4X(dev
)) {
7433 dev_priv
->display
.update_wm
= g4x_update_wm
;
7434 dev_priv
->display
.init_clock_gating
= g4x_init_clock_gating
;
7435 } else if (IS_GEN4(dev
)) {
7436 dev_priv
->display
.update_wm
= i965_update_wm
;
7437 if (IS_CRESTLINE(dev
))
7438 dev_priv
->display
.init_clock_gating
= crestline_init_clock_gating
;
7439 else if (IS_BROADWATER(dev
))
7440 dev_priv
->display
.init_clock_gating
= broadwater_init_clock_gating
;
7441 } else if (IS_GEN3(dev
)) {
7442 dev_priv
->display
.update_wm
= i9xx_update_wm
;
7443 dev_priv
->display
.get_fifo_size
= i9xx_get_fifo_size
;
7444 dev_priv
->display
.init_clock_gating
= gen3_init_clock_gating
;
7445 } else if (IS_GEN2(dev
)) {
7446 if (INTEL_INFO(dev
)->num_pipes
== 1) {
7447 dev_priv
->display
.update_wm
= i845_update_wm
;
7448 dev_priv
->display
.get_fifo_size
= i845_get_fifo_size
;
7450 dev_priv
->display
.update_wm
= i9xx_update_wm
;
7451 dev_priv
->display
.get_fifo_size
= i830_get_fifo_size
;
7454 if (IS_I85X(dev
) || IS_I865G(dev
))
7455 dev_priv
->display
.init_clock_gating
= i85x_init_clock_gating
;
7457 dev_priv
->display
.init_clock_gating
= i830_init_clock_gating
;
7459 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
7463 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u8 mbox
, u32
*val
)
7465 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
7467 if (I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) {
7468 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7472 I915_WRITE(GEN6_PCODE_DATA
, *val
);
7473 I915_WRITE(GEN6_PCODE_MAILBOX
, GEN6_PCODE_READY
| mbox
);
7475 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) == 0,
7477 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox
);
7481 *val
= I915_READ(GEN6_PCODE_DATA
);
7482 I915_WRITE(GEN6_PCODE_DATA
, 0);
7487 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
, u8 mbox
, u32 val
)
7489 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
7491 if (I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) {
7492 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7496 I915_WRITE(GEN6_PCODE_DATA
, val
);
7497 I915_WRITE(GEN6_PCODE_MAILBOX
, GEN6_PCODE_READY
| mbox
);
7499 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) == 0,
7501 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox
);
7505 I915_WRITE(GEN6_PCODE_DATA
, 0);
7510 static int byt_gpu_freq(struct drm_i915_private
*dev_priv
, int val
)
7515 switch (dev_priv
->mem_freq
) {
7529 return DIV_ROUND_CLOSEST(dev_priv
->mem_freq
* (val
+ 6 - 0xbd), 4 * div
);
7532 static int byt_freq_opcode(struct drm_i915_private
*dev_priv
, int val
)
7537 switch (dev_priv
->mem_freq
) {
7551 return DIV_ROUND_CLOSEST(4 * mul
* val
, dev_priv
->mem_freq
) + 0xbd - 6;
7554 static int chv_gpu_freq(struct drm_i915_private
*dev_priv
, int val
)
7558 switch (dev_priv
->rps
.cz_freq
) {
7574 freq
= (DIV_ROUND_CLOSEST((dev_priv
->rps
.cz_freq
* val
), 2 * div
) / 2);
7579 static int chv_freq_opcode(struct drm_i915_private
*dev_priv
, int val
)
7583 switch (dev_priv
->rps
.cz_freq
) {
7599 /* CHV needs even values */
7600 opcode
= (DIV_ROUND_CLOSEST((val
* 2 * mul
), dev_priv
->rps
.cz_freq
) * 2);
7605 int vlv_gpu_freq(struct drm_i915_private
*dev_priv
, int val
)
7609 if (IS_CHERRYVIEW(dev_priv
->dev
))
7610 ret
= chv_gpu_freq(dev_priv
, val
);
7611 else if (IS_VALLEYVIEW(dev_priv
->dev
))
7612 ret
= byt_gpu_freq(dev_priv
, val
);
7617 int vlv_freq_opcode(struct drm_i915_private
*dev_priv
, int val
)
7621 if (IS_CHERRYVIEW(dev_priv
->dev
))
7622 ret
= chv_freq_opcode(dev_priv
, val
);
7623 else if (IS_VALLEYVIEW(dev_priv
->dev
))
7624 ret
= byt_freq_opcode(dev_priv
, val
);
7629 void intel_pm_setup(struct drm_device
*dev
)
7631 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7633 mutex_init(&dev_priv
->rps
.hw_lock
);
7635 INIT_DELAYED_WORK(&dev_priv
->rps
.delayed_resume_work
,
7636 intel_gen6_powersave_work
);
7638 dev_priv
->pm
.suspended
= false;
7639 dev_priv
->pm
._irqs_disabled
= false;