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drm/i915: Parametrize VLV_DDL registers
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_pm.c
1 /*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28 #include <linux/cpufreq.h>
29 #include "i915_drv.h"
30 #include "intel_drv.h"
31 #include "../../../platform/x86/intel_ips.h"
32 #include <linux/module.h>
33 #include <linux/vgaarb.h>
34 #include <drm/i915_powerwell.h>
35 #include <linux/pm_runtime.h>
36
37 /**
38 * RC6 is a special power stage which allows the GPU to enter an very
39 * low-voltage mode when idle, using down to 0V while at this stage. This
40 * stage is entered automatically when the GPU is idle when RC6 support is
41 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
42 *
43 * There are different RC6 modes available in Intel GPU, which differentiate
44 * among each other with the latency required to enter and leave RC6 and
45 * voltage consumed by the GPU in different states.
46 *
47 * The combination of the following flags define which states GPU is allowed
48 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
49 * RC6pp is deepest RC6. Their support by hardware varies according to the
50 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
51 * which brings the most power savings; deeper states save more power, but
52 * require higher latency to switch to and wake up.
53 */
54 #define INTEL_RC6_ENABLE (1<<0)
55 #define INTEL_RC6p_ENABLE (1<<1)
56 #define INTEL_RC6pp_ENABLE (1<<2)
57
58 /* FBC, or Frame Buffer Compression, is a technique employed to compress the
59 * framebuffer contents in-memory, aiming at reducing the required bandwidth
60 * during in-memory transfers and, therefore, reduce the power packet.
61 *
62 * The benefits of FBC are mostly visible with solid backgrounds and
63 * variation-less patterns.
64 *
65 * FBC-related functionality can be enabled by the means of the
66 * i915.i915_enable_fbc parameter
67 */
68
69 static void i8xx_disable_fbc(struct drm_device *dev)
70 {
71 struct drm_i915_private *dev_priv = dev->dev_private;
72 u32 fbc_ctl;
73
74 /* Disable compression */
75 fbc_ctl = I915_READ(FBC_CONTROL);
76 if ((fbc_ctl & FBC_CTL_EN) == 0)
77 return;
78
79 fbc_ctl &= ~FBC_CTL_EN;
80 I915_WRITE(FBC_CONTROL, fbc_ctl);
81
82 /* Wait for compressing bit to clear */
83 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
84 DRM_DEBUG_KMS("FBC idle timed out\n");
85 return;
86 }
87
88 DRM_DEBUG_KMS("disabled FBC\n");
89 }
90
91 static void i8xx_enable_fbc(struct drm_crtc *crtc)
92 {
93 struct drm_device *dev = crtc->dev;
94 struct drm_i915_private *dev_priv = dev->dev_private;
95 struct drm_framebuffer *fb = crtc->primary->fb;
96 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
97 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
98 int cfb_pitch;
99 int i;
100 u32 fbc_ctl;
101
102 cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
103 if (fb->pitches[0] < cfb_pitch)
104 cfb_pitch = fb->pitches[0];
105
106 /* FBC_CTL wants 32B or 64B units */
107 if (IS_GEN2(dev))
108 cfb_pitch = (cfb_pitch / 32) - 1;
109 else
110 cfb_pitch = (cfb_pitch / 64) - 1;
111
112 /* Clear old tags */
113 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
114 I915_WRITE(FBC_TAG + (i * 4), 0);
115
116 if (IS_GEN4(dev)) {
117 u32 fbc_ctl2;
118
119 /* Set it up... */
120 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
121 fbc_ctl2 |= FBC_CTL_PLANE(intel_crtc->plane);
122 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
123 I915_WRITE(FBC_FENCE_OFF, crtc->y);
124 }
125
126 /* enable it... */
127 fbc_ctl = I915_READ(FBC_CONTROL);
128 fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT;
129 fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
130 if (IS_I945GM(dev))
131 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
132 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
133 fbc_ctl |= obj->fence_reg;
134 I915_WRITE(FBC_CONTROL, fbc_ctl);
135
136 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c\n",
137 cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
138 }
139
140 static bool i8xx_fbc_enabled(struct drm_device *dev)
141 {
142 struct drm_i915_private *dev_priv = dev->dev_private;
143
144 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
145 }
146
147 static void g4x_enable_fbc(struct drm_crtc *crtc)
148 {
149 struct drm_device *dev = crtc->dev;
150 struct drm_i915_private *dev_priv = dev->dev_private;
151 struct drm_framebuffer *fb = crtc->primary->fb;
152 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
153 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
154 u32 dpfc_ctl;
155
156 dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane) | DPFC_SR_EN;
157 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
158 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
159 else
160 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
161 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
162
163 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
164
165 /* enable it... */
166 I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
167
168 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
169 }
170
171 static void g4x_disable_fbc(struct drm_device *dev)
172 {
173 struct drm_i915_private *dev_priv = dev->dev_private;
174 u32 dpfc_ctl;
175
176 /* Disable compression */
177 dpfc_ctl = I915_READ(DPFC_CONTROL);
178 if (dpfc_ctl & DPFC_CTL_EN) {
179 dpfc_ctl &= ~DPFC_CTL_EN;
180 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
181
182 DRM_DEBUG_KMS("disabled FBC\n");
183 }
184 }
185
186 static bool g4x_fbc_enabled(struct drm_device *dev)
187 {
188 struct drm_i915_private *dev_priv = dev->dev_private;
189
190 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
191 }
192
193 static void sandybridge_blit_fbc_update(struct drm_device *dev)
194 {
195 struct drm_i915_private *dev_priv = dev->dev_private;
196 u32 blt_ecoskpd;
197
198 /* Make sure blitter notifies FBC of writes */
199
200 /* Blitter is part of Media powerwell on VLV. No impact of
201 * his param in other platforms for now */
202 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_MEDIA);
203
204 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
205 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
206 GEN6_BLITTER_LOCK_SHIFT;
207 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
208 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
209 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
210 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
211 GEN6_BLITTER_LOCK_SHIFT);
212 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
213 POSTING_READ(GEN6_BLITTER_ECOSKPD);
214
215 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_MEDIA);
216 }
217
218 static void ironlake_enable_fbc(struct drm_crtc *crtc)
219 {
220 struct drm_device *dev = crtc->dev;
221 struct drm_i915_private *dev_priv = dev->dev_private;
222 struct drm_framebuffer *fb = crtc->primary->fb;
223 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
224 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
225 u32 dpfc_ctl;
226
227 dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane);
228 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
229 dev_priv->fbc.threshold++;
230
231 switch (dev_priv->fbc.threshold) {
232 case 4:
233 case 3:
234 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
235 break;
236 case 2:
237 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
238 break;
239 case 1:
240 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
241 break;
242 }
243 dpfc_ctl |= DPFC_CTL_FENCE_EN;
244 if (IS_GEN5(dev))
245 dpfc_ctl |= obj->fence_reg;
246
247 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
248 I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
249 /* enable it... */
250 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
251
252 if (IS_GEN6(dev)) {
253 I915_WRITE(SNB_DPFC_CTL_SA,
254 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
255 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
256 sandybridge_blit_fbc_update(dev);
257 }
258
259 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
260 }
261
262 static void ironlake_disable_fbc(struct drm_device *dev)
263 {
264 struct drm_i915_private *dev_priv = dev->dev_private;
265 u32 dpfc_ctl;
266
267 /* Disable compression */
268 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
269 if (dpfc_ctl & DPFC_CTL_EN) {
270 dpfc_ctl &= ~DPFC_CTL_EN;
271 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
272
273 DRM_DEBUG_KMS("disabled FBC\n");
274 }
275 }
276
277 static bool ironlake_fbc_enabled(struct drm_device *dev)
278 {
279 struct drm_i915_private *dev_priv = dev->dev_private;
280
281 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
282 }
283
284 static void gen7_enable_fbc(struct drm_crtc *crtc)
285 {
286 struct drm_device *dev = crtc->dev;
287 struct drm_i915_private *dev_priv = dev->dev_private;
288 struct drm_framebuffer *fb = crtc->primary->fb;
289 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
290 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
291 u32 dpfc_ctl;
292
293 dpfc_ctl = IVB_DPFC_CTL_PLANE(intel_crtc->plane);
294 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
295 dev_priv->fbc.threshold++;
296
297 switch (dev_priv->fbc.threshold) {
298 case 4:
299 case 3:
300 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
301 break;
302 case 2:
303 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
304 break;
305 case 1:
306 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
307 break;
308 }
309
310 dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
311
312 if (dev_priv->fbc.false_color)
313 dpfc_ctl |= FBC_CTL_FALSE_COLOR;
314
315 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
316
317 if (IS_IVYBRIDGE(dev)) {
318 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
319 I915_WRITE(ILK_DISPLAY_CHICKEN1,
320 I915_READ(ILK_DISPLAY_CHICKEN1) |
321 ILK_FBCQ_DIS);
322 } else {
323 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
324 I915_WRITE(CHICKEN_PIPESL_1(intel_crtc->pipe),
325 I915_READ(CHICKEN_PIPESL_1(intel_crtc->pipe)) |
326 HSW_FBCQ_DIS);
327 }
328
329 I915_WRITE(SNB_DPFC_CTL_SA,
330 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
331 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
332
333 sandybridge_blit_fbc_update(dev);
334
335 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
336 }
337
338 bool intel_fbc_enabled(struct drm_device *dev)
339 {
340 struct drm_i915_private *dev_priv = dev->dev_private;
341
342 if (!dev_priv->display.fbc_enabled)
343 return false;
344
345 return dev_priv->display.fbc_enabled(dev);
346 }
347
348 static void intel_fbc_work_fn(struct work_struct *__work)
349 {
350 struct intel_fbc_work *work =
351 container_of(to_delayed_work(__work),
352 struct intel_fbc_work, work);
353 struct drm_device *dev = work->crtc->dev;
354 struct drm_i915_private *dev_priv = dev->dev_private;
355
356 mutex_lock(&dev->struct_mutex);
357 if (work == dev_priv->fbc.fbc_work) {
358 /* Double check that we haven't switched fb without cancelling
359 * the prior work.
360 */
361 if (work->crtc->primary->fb == work->fb) {
362 dev_priv->display.enable_fbc(work->crtc);
363
364 dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;
365 dev_priv->fbc.fb_id = work->crtc->primary->fb->base.id;
366 dev_priv->fbc.y = work->crtc->y;
367 }
368
369 dev_priv->fbc.fbc_work = NULL;
370 }
371 mutex_unlock(&dev->struct_mutex);
372
373 kfree(work);
374 }
375
376 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
377 {
378 if (dev_priv->fbc.fbc_work == NULL)
379 return;
380
381 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
382
383 /* Synchronisation is provided by struct_mutex and checking of
384 * dev_priv->fbc.fbc_work, so we can perform the cancellation
385 * entirely asynchronously.
386 */
387 if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
388 /* tasklet was killed before being run, clean up */
389 kfree(dev_priv->fbc.fbc_work);
390
391 /* Mark the work as no longer wanted so that if it does
392 * wake-up (because the work was already running and waiting
393 * for our mutex), it will discover that is no longer
394 * necessary to run.
395 */
396 dev_priv->fbc.fbc_work = NULL;
397 }
398
399 static void intel_enable_fbc(struct drm_crtc *crtc)
400 {
401 struct intel_fbc_work *work;
402 struct drm_device *dev = crtc->dev;
403 struct drm_i915_private *dev_priv = dev->dev_private;
404
405 if (!dev_priv->display.enable_fbc)
406 return;
407
408 intel_cancel_fbc_work(dev_priv);
409
410 work = kzalloc(sizeof(*work), GFP_KERNEL);
411 if (work == NULL) {
412 DRM_ERROR("Failed to allocate FBC work structure\n");
413 dev_priv->display.enable_fbc(crtc);
414 return;
415 }
416
417 work->crtc = crtc;
418 work->fb = crtc->primary->fb;
419 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
420
421 dev_priv->fbc.fbc_work = work;
422
423 /* Delay the actual enabling to let pageflipping cease and the
424 * display to settle before starting the compression. Note that
425 * this delay also serves a second purpose: it allows for a
426 * vblank to pass after disabling the FBC before we attempt
427 * to modify the control registers.
428 *
429 * A more complicated solution would involve tracking vblanks
430 * following the termination of the page-flipping sequence
431 * and indeed performing the enable as a co-routine and not
432 * waiting synchronously upon the vblank.
433 *
434 * WaFbcWaitForVBlankBeforeEnable:ilk,snb
435 */
436 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
437 }
438
439 void intel_disable_fbc(struct drm_device *dev)
440 {
441 struct drm_i915_private *dev_priv = dev->dev_private;
442
443 intel_cancel_fbc_work(dev_priv);
444
445 if (!dev_priv->display.disable_fbc)
446 return;
447
448 dev_priv->display.disable_fbc(dev);
449 dev_priv->fbc.plane = -1;
450 }
451
452 static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
453 enum no_fbc_reason reason)
454 {
455 if (dev_priv->fbc.no_fbc_reason == reason)
456 return false;
457
458 dev_priv->fbc.no_fbc_reason = reason;
459 return true;
460 }
461
462 /**
463 * intel_update_fbc - enable/disable FBC as needed
464 * @dev: the drm_device
465 *
466 * Set up the framebuffer compression hardware at mode set time. We
467 * enable it if possible:
468 * - plane A only (on pre-965)
469 * - no pixel mulitply/line duplication
470 * - no alpha buffer discard
471 * - no dual wide
472 * - framebuffer <= max_hdisplay in width, max_vdisplay in height
473 *
474 * We can't assume that any compression will take place (worst case),
475 * so the compressed buffer has to be the same size as the uncompressed
476 * one. It also must reside (along with the line length buffer) in
477 * stolen memory.
478 *
479 * We need to enable/disable FBC on a global basis.
480 */
481 void intel_update_fbc(struct drm_device *dev)
482 {
483 struct drm_i915_private *dev_priv = dev->dev_private;
484 struct drm_crtc *crtc = NULL, *tmp_crtc;
485 struct intel_crtc *intel_crtc;
486 struct drm_framebuffer *fb;
487 struct drm_i915_gem_object *obj;
488 const struct drm_display_mode *adjusted_mode;
489 unsigned int max_width, max_height;
490
491 if (!HAS_FBC(dev)) {
492 set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED);
493 return;
494 }
495
496 if (!i915.powersave) {
497 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
498 DRM_DEBUG_KMS("fbc disabled per module param\n");
499 return;
500 }
501
502 /*
503 * If FBC is already on, we just have to verify that we can
504 * keep it that way...
505 * Need to disable if:
506 * - more than one pipe is active
507 * - changing FBC params (stride, fence, mode)
508 * - new fb is too large to fit in compressed buffer
509 * - going to an unsupported config (interlace, pixel multiply, etc.)
510 */
511 for_each_crtc(dev, tmp_crtc) {
512 if (intel_crtc_active(tmp_crtc) &&
513 to_intel_crtc(tmp_crtc)->primary_enabled) {
514 if (crtc) {
515 if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
516 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
517 goto out_disable;
518 }
519 crtc = tmp_crtc;
520 }
521 }
522
523 if (!crtc || crtc->primary->fb == NULL) {
524 if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
525 DRM_DEBUG_KMS("no output, disabling\n");
526 goto out_disable;
527 }
528
529 intel_crtc = to_intel_crtc(crtc);
530 fb = crtc->primary->fb;
531 obj = intel_fb_obj(fb);
532 adjusted_mode = &intel_crtc->config.adjusted_mode;
533
534 if (i915.enable_fbc < 0) {
535 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
536 DRM_DEBUG_KMS("disabled per chip default\n");
537 goto out_disable;
538 }
539 if (!i915.enable_fbc) {
540 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
541 DRM_DEBUG_KMS("fbc disabled per module param\n");
542 goto out_disable;
543 }
544 if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ||
545 (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
546 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
547 DRM_DEBUG_KMS("mode incompatible with compression, "
548 "disabling\n");
549 goto out_disable;
550 }
551
552 if (INTEL_INFO(dev)->gen >= 8 || IS_HASWELL(dev)) {
553 max_width = 4096;
554 max_height = 4096;
555 } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
556 max_width = 4096;
557 max_height = 2048;
558 } else {
559 max_width = 2048;
560 max_height = 1536;
561 }
562 if (intel_crtc->config.pipe_src_w > max_width ||
563 intel_crtc->config.pipe_src_h > max_height) {
564 if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
565 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
566 goto out_disable;
567 }
568 if ((INTEL_INFO(dev)->gen < 4 || HAS_DDI(dev)) &&
569 intel_crtc->plane != PLANE_A) {
570 if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
571 DRM_DEBUG_KMS("plane not A, disabling compression\n");
572 goto out_disable;
573 }
574
575 /* The use of a CPU fence is mandatory in order to detect writes
576 * by the CPU to the scanout and trigger updates to the FBC.
577 */
578 if (obj->tiling_mode != I915_TILING_X ||
579 obj->fence_reg == I915_FENCE_REG_NONE) {
580 if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED))
581 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
582 goto out_disable;
583 }
584
585 /* If the kernel debugger is active, always disable compression */
586 if (in_dbg_master())
587 goto out_disable;
588
589 if (i915_gem_stolen_setup_compression(dev, obj->base.size,
590 drm_format_plane_cpp(fb->pixel_format, 0))) {
591 if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL))
592 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
593 goto out_disable;
594 }
595
596 /* If the scanout has not changed, don't modify the FBC settings.
597 * Note that we make the fundamental assumption that the fb->obj
598 * cannot be unpinned (and have its GTT offset and fence revoked)
599 * without first being decoupled from the scanout and FBC disabled.
600 */
601 if (dev_priv->fbc.plane == intel_crtc->plane &&
602 dev_priv->fbc.fb_id == fb->base.id &&
603 dev_priv->fbc.y == crtc->y)
604 return;
605
606 if (intel_fbc_enabled(dev)) {
607 /* We update FBC along two paths, after changing fb/crtc
608 * configuration (modeswitching) and after page-flipping
609 * finishes. For the latter, we know that not only did
610 * we disable the FBC at the start of the page-flip
611 * sequence, but also more than one vblank has passed.
612 *
613 * For the former case of modeswitching, it is possible
614 * to switch between two FBC valid configurations
615 * instantaneously so we do need to disable the FBC
616 * before we can modify its control registers. We also
617 * have to wait for the next vblank for that to take
618 * effect. However, since we delay enabling FBC we can
619 * assume that a vblank has passed since disabling and
620 * that we can safely alter the registers in the deferred
621 * callback.
622 *
623 * In the scenario that we go from a valid to invalid
624 * and then back to valid FBC configuration we have
625 * no strict enforcement that a vblank occurred since
626 * disabling the FBC. However, along all current pipe
627 * disabling paths we do need to wait for a vblank at
628 * some point. And we wait before enabling FBC anyway.
629 */
630 DRM_DEBUG_KMS("disabling active FBC for update\n");
631 intel_disable_fbc(dev);
632 }
633
634 intel_enable_fbc(crtc);
635 dev_priv->fbc.no_fbc_reason = FBC_OK;
636 return;
637
638 out_disable:
639 /* Multiple disables should be harmless */
640 if (intel_fbc_enabled(dev)) {
641 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
642 intel_disable_fbc(dev);
643 }
644 i915_gem_stolen_cleanup_compression(dev);
645 }
646
647 static void i915_pineview_get_mem_freq(struct drm_device *dev)
648 {
649 struct drm_i915_private *dev_priv = dev->dev_private;
650 u32 tmp;
651
652 tmp = I915_READ(CLKCFG);
653
654 switch (tmp & CLKCFG_FSB_MASK) {
655 case CLKCFG_FSB_533:
656 dev_priv->fsb_freq = 533; /* 133*4 */
657 break;
658 case CLKCFG_FSB_800:
659 dev_priv->fsb_freq = 800; /* 200*4 */
660 break;
661 case CLKCFG_FSB_667:
662 dev_priv->fsb_freq = 667; /* 167*4 */
663 break;
664 case CLKCFG_FSB_400:
665 dev_priv->fsb_freq = 400; /* 100*4 */
666 break;
667 }
668
669 switch (tmp & CLKCFG_MEM_MASK) {
670 case CLKCFG_MEM_533:
671 dev_priv->mem_freq = 533;
672 break;
673 case CLKCFG_MEM_667:
674 dev_priv->mem_freq = 667;
675 break;
676 case CLKCFG_MEM_800:
677 dev_priv->mem_freq = 800;
678 break;
679 }
680
681 /* detect pineview DDR3 setting */
682 tmp = I915_READ(CSHRDDR3CTL);
683 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
684 }
685
686 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
687 {
688 struct drm_i915_private *dev_priv = dev->dev_private;
689 u16 ddrpll, csipll;
690
691 ddrpll = I915_READ16(DDRMPLL1);
692 csipll = I915_READ16(CSIPLL0);
693
694 switch (ddrpll & 0xff) {
695 case 0xc:
696 dev_priv->mem_freq = 800;
697 break;
698 case 0x10:
699 dev_priv->mem_freq = 1066;
700 break;
701 case 0x14:
702 dev_priv->mem_freq = 1333;
703 break;
704 case 0x18:
705 dev_priv->mem_freq = 1600;
706 break;
707 default:
708 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
709 ddrpll & 0xff);
710 dev_priv->mem_freq = 0;
711 break;
712 }
713
714 dev_priv->ips.r_t = dev_priv->mem_freq;
715
716 switch (csipll & 0x3ff) {
717 case 0x00c:
718 dev_priv->fsb_freq = 3200;
719 break;
720 case 0x00e:
721 dev_priv->fsb_freq = 3733;
722 break;
723 case 0x010:
724 dev_priv->fsb_freq = 4266;
725 break;
726 case 0x012:
727 dev_priv->fsb_freq = 4800;
728 break;
729 case 0x014:
730 dev_priv->fsb_freq = 5333;
731 break;
732 case 0x016:
733 dev_priv->fsb_freq = 5866;
734 break;
735 case 0x018:
736 dev_priv->fsb_freq = 6400;
737 break;
738 default:
739 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
740 csipll & 0x3ff);
741 dev_priv->fsb_freq = 0;
742 break;
743 }
744
745 if (dev_priv->fsb_freq == 3200) {
746 dev_priv->ips.c_m = 0;
747 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
748 dev_priv->ips.c_m = 1;
749 } else {
750 dev_priv->ips.c_m = 2;
751 }
752 }
753
754 static const struct cxsr_latency cxsr_latency_table[] = {
755 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
756 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
757 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
758 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
759 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
760
761 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
762 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
763 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
764 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
765 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
766
767 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
768 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
769 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
770 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
771 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
772
773 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
774 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
775 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
776 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
777 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
778
779 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
780 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
781 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
782 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
783 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
784
785 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
786 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
787 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
788 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
789 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
790 };
791
792 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
793 int is_ddr3,
794 int fsb,
795 int mem)
796 {
797 const struct cxsr_latency *latency;
798 int i;
799
800 if (fsb == 0 || mem == 0)
801 return NULL;
802
803 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
804 latency = &cxsr_latency_table[i];
805 if (is_desktop == latency->is_desktop &&
806 is_ddr3 == latency->is_ddr3 &&
807 fsb == latency->fsb_freq && mem == latency->mem_freq)
808 return latency;
809 }
810
811 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
812
813 return NULL;
814 }
815
816 void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
817 {
818 struct drm_device *dev = dev_priv->dev;
819 u32 val;
820
821 if (IS_VALLEYVIEW(dev)) {
822 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
823 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
824 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
825 } else if (IS_PINEVIEW(dev)) {
826 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
827 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
828 I915_WRITE(DSPFW3, val);
829 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
830 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
831 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
832 I915_WRITE(FW_BLC_SELF, val);
833 } else if (IS_I915GM(dev)) {
834 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
835 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
836 I915_WRITE(INSTPM, val);
837 } else {
838 return;
839 }
840
841 DRM_DEBUG_KMS("memory self-refresh is %s\n",
842 enable ? "enabled" : "disabled");
843 }
844
845 /*
846 * Latency for FIFO fetches is dependent on several factors:
847 * - memory configuration (speed, channels)
848 * - chipset
849 * - current MCH state
850 * It can be fairly high in some situations, so here we assume a fairly
851 * pessimal value. It's a tradeoff between extra memory fetches (if we
852 * set this value too high, the FIFO will fetch frequently to stay full)
853 * and power consumption (set it too low to save power and we might see
854 * FIFO underruns and display "flicker").
855 *
856 * A value of 5us seems to be a good balance; safe for very low end
857 * platforms but not overly aggressive on lower latency configs.
858 */
859 static const int latency_ns = 5000;
860
861 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
862 {
863 struct drm_i915_private *dev_priv = dev->dev_private;
864 uint32_t dsparb = I915_READ(DSPARB);
865 int size;
866
867 size = dsparb & 0x7f;
868 if (plane)
869 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
870
871 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
872 plane ? "B" : "A", size);
873
874 return size;
875 }
876
877 static int i830_get_fifo_size(struct drm_device *dev, int plane)
878 {
879 struct drm_i915_private *dev_priv = dev->dev_private;
880 uint32_t dsparb = I915_READ(DSPARB);
881 int size;
882
883 size = dsparb & 0x1ff;
884 if (plane)
885 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
886 size >>= 1; /* Convert to cachelines */
887
888 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
889 plane ? "B" : "A", size);
890
891 return size;
892 }
893
894 static int i845_get_fifo_size(struct drm_device *dev, int plane)
895 {
896 struct drm_i915_private *dev_priv = dev->dev_private;
897 uint32_t dsparb = I915_READ(DSPARB);
898 int size;
899
900 size = dsparb & 0x7f;
901 size >>= 2; /* Convert to cachelines */
902
903 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
904 plane ? "B" : "A",
905 size);
906
907 return size;
908 }
909
910 /* Pineview has different values for various configs */
911 static const struct intel_watermark_params pineview_display_wm = {
912 .fifo_size = PINEVIEW_DISPLAY_FIFO,
913 .max_wm = PINEVIEW_MAX_WM,
914 .default_wm = PINEVIEW_DFT_WM,
915 .guard_size = PINEVIEW_GUARD_WM,
916 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
917 };
918 static const struct intel_watermark_params pineview_display_hplloff_wm = {
919 .fifo_size = PINEVIEW_DISPLAY_FIFO,
920 .max_wm = PINEVIEW_MAX_WM,
921 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
922 .guard_size = PINEVIEW_GUARD_WM,
923 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
924 };
925 static const struct intel_watermark_params pineview_cursor_wm = {
926 .fifo_size = PINEVIEW_CURSOR_FIFO,
927 .max_wm = PINEVIEW_CURSOR_MAX_WM,
928 .default_wm = PINEVIEW_CURSOR_DFT_WM,
929 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
930 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
931 };
932 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
933 .fifo_size = PINEVIEW_CURSOR_FIFO,
934 .max_wm = PINEVIEW_CURSOR_MAX_WM,
935 .default_wm = PINEVIEW_CURSOR_DFT_WM,
936 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
937 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
938 };
939 static const struct intel_watermark_params g4x_wm_info = {
940 .fifo_size = G4X_FIFO_SIZE,
941 .max_wm = G4X_MAX_WM,
942 .default_wm = G4X_MAX_WM,
943 .guard_size = 2,
944 .cacheline_size = G4X_FIFO_LINE_SIZE,
945 };
946 static const struct intel_watermark_params g4x_cursor_wm_info = {
947 .fifo_size = I965_CURSOR_FIFO,
948 .max_wm = I965_CURSOR_MAX_WM,
949 .default_wm = I965_CURSOR_DFT_WM,
950 .guard_size = 2,
951 .cacheline_size = G4X_FIFO_LINE_SIZE,
952 };
953 static const struct intel_watermark_params valleyview_wm_info = {
954 .fifo_size = VALLEYVIEW_FIFO_SIZE,
955 .max_wm = VALLEYVIEW_MAX_WM,
956 .default_wm = VALLEYVIEW_MAX_WM,
957 .guard_size = 2,
958 .cacheline_size = G4X_FIFO_LINE_SIZE,
959 };
960 static const struct intel_watermark_params valleyview_cursor_wm_info = {
961 .fifo_size = I965_CURSOR_FIFO,
962 .max_wm = VALLEYVIEW_CURSOR_MAX_WM,
963 .default_wm = I965_CURSOR_DFT_WM,
964 .guard_size = 2,
965 .cacheline_size = G4X_FIFO_LINE_SIZE,
966 };
967 static const struct intel_watermark_params i965_cursor_wm_info = {
968 .fifo_size = I965_CURSOR_FIFO,
969 .max_wm = I965_CURSOR_MAX_WM,
970 .default_wm = I965_CURSOR_DFT_WM,
971 .guard_size = 2,
972 .cacheline_size = I915_FIFO_LINE_SIZE,
973 };
974 static const struct intel_watermark_params i945_wm_info = {
975 .fifo_size = I945_FIFO_SIZE,
976 .max_wm = I915_MAX_WM,
977 .default_wm = 1,
978 .guard_size = 2,
979 .cacheline_size = I915_FIFO_LINE_SIZE,
980 };
981 static const struct intel_watermark_params i915_wm_info = {
982 .fifo_size = I915_FIFO_SIZE,
983 .max_wm = I915_MAX_WM,
984 .default_wm = 1,
985 .guard_size = 2,
986 .cacheline_size = I915_FIFO_LINE_SIZE,
987 };
988 static const struct intel_watermark_params i830_wm_info = {
989 .fifo_size = I855GM_FIFO_SIZE,
990 .max_wm = I915_MAX_WM,
991 .default_wm = 1,
992 .guard_size = 2,
993 .cacheline_size = I830_FIFO_LINE_SIZE,
994 };
995 static const struct intel_watermark_params i845_wm_info = {
996 .fifo_size = I830_FIFO_SIZE,
997 .max_wm = I915_MAX_WM,
998 .default_wm = 1,
999 .guard_size = 2,
1000 .cacheline_size = I830_FIFO_LINE_SIZE,
1001 };
1002
1003 /**
1004 * intel_calculate_wm - calculate watermark level
1005 * @clock_in_khz: pixel clock
1006 * @wm: chip FIFO params
1007 * @pixel_size: display pixel size
1008 * @latency_ns: memory latency for the platform
1009 *
1010 * Calculate the watermark level (the level at which the display plane will
1011 * start fetching from memory again). Each chip has a different display
1012 * FIFO size and allocation, so the caller needs to figure that out and pass
1013 * in the correct intel_watermark_params structure.
1014 *
1015 * As the pixel clock runs, the FIFO will be drained at a rate that depends
1016 * on the pixel size. When it reaches the watermark level, it'll start
1017 * fetching FIFO line sized based chunks from memory until the FIFO fills
1018 * past the watermark point. If the FIFO drains completely, a FIFO underrun
1019 * will occur, and a display engine hang could result.
1020 */
1021 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
1022 const struct intel_watermark_params *wm,
1023 int fifo_size,
1024 int pixel_size,
1025 unsigned long latency_ns)
1026 {
1027 long entries_required, wm_size;
1028
1029 /*
1030 * Note: we need to make sure we don't overflow for various clock &
1031 * latency values.
1032 * clocks go from a few thousand to several hundred thousand.
1033 * latency is usually a few thousand
1034 */
1035 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
1036 1000;
1037 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
1038
1039 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
1040
1041 wm_size = fifo_size - (entries_required + wm->guard_size);
1042
1043 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
1044
1045 /* Don't promote wm_size to unsigned... */
1046 if (wm_size > (long)wm->max_wm)
1047 wm_size = wm->max_wm;
1048 if (wm_size <= 0)
1049 wm_size = wm->default_wm;
1050 return wm_size;
1051 }
1052
1053 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1054 {
1055 struct drm_crtc *crtc, *enabled = NULL;
1056
1057 for_each_crtc(dev, crtc) {
1058 if (intel_crtc_active(crtc)) {
1059 if (enabled)
1060 return NULL;
1061 enabled = crtc;
1062 }
1063 }
1064
1065 return enabled;
1066 }
1067
1068 static void pineview_update_wm(struct drm_crtc *unused_crtc)
1069 {
1070 struct drm_device *dev = unused_crtc->dev;
1071 struct drm_i915_private *dev_priv = dev->dev_private;
1072 struct drm_crtc *crtc;
1073 const struct cxsr_latency *latency;
1074 u32 reg;
1075 unsigned long wm;
1076
1077 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1078 dev_priv->fsb_freq, dev_priv->mem_freq);
1079 if (!latency) {
1080 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1081 intel_set_memory_cxsr(dev_priv, false);
1082 return;
1083 }
1084
1085 crtc = single_enabled_crtc(dev);
1086 if (crtc) {
1087 const struct drm_display_mode *adjusted_mode;
1088 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1089 int clock;
1090
1091 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1092 clock = adjusted_mode->crtc_clock;
1093
1094 /* Display SR */
1095 wm = intel_calculate_wm(clock, &pineview_display_wm,
1096 pineview_display_wm.fifo_size,
1097 pixel_size, latency->display_sr);
1098 reg = I915_READ(DSPFW1);
1099 reg &= ~DSPFW_SR_MASK;
1100 reg |= wm << DSPFW_SR_SHIFT;
1101 I915_WRITE(DSPFW1, reg);
1102 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1103
1104 /* cursor SR */
1105 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1106 pineview_display_wm.fifo_size,
1107 pixel_size, latency->cursor_sr);
1108 reg = I915_READ(DSPFW3);
1109 reg &= ~DSPFW_CURSOR_SR_MASK;
1110 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1111 I915_WRITE(DSPFW3, reg);
1112
1113 /* Display HPLL off SR */
1114 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1115 pineview_display_hplloff_wm.fifo_size,
1116 pixel_size, latency->display_hpll_disable);
1117 reg = I915_READ(DSPFW3);
1118 reg &= ~DSPFW_HPLL_SR_MASK;
1119 reg |= wm & DSPFW_HPLL_SR_MASK;
1120 I915_WRITE(DSPFW3, reg);
1121
1122 /* cursor HPLL off SR */
1123 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1124 pineview_display_hplloff_wm.fifo_size,
1125 pixel_size, latency->cursor_hpll_disable);
1126 reg = I915_READ(DSPFW3);
1127 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1128 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1129 I915_WRITE(DSPFW3, reg);
1130 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1131
1132 intel_set_memory_cxsr(dev_priv, true);
1133 } else {
1134 intel_set_memory_cxsr(dev_priv, false);
1135 }
1136 }
1137
1138 static bool g4x_compute_wm0(struct drm_device *dev,
1139 int plane,
1140 const struct intel_watermark_params *display,
1141 int display_latency_ns,
1142 const struct intel_watermark_params *cursor,
1143 int cursor_latency_ns,
1144 int *plane_wm,
1145 int *cursor_wm)
1146 {
1147 struct drm_crtc *crtc;
1148 const struct drm_display_mode *adjusted_mode;
1149 int htotal, hdisplay, clock, pixel_size;
1150 int line_time_us, line_count;
1151 int entries, tlb_miss;
1152
1153 crtc = intel_get_crtc_for_plane(dev, plane);
1154 if (!intel_crtc_active(crtc)) {
1155 *cursor_wm = cursor->guard_size;
1156 *plane_wm = display->guard_size;
1157 return false;
1158 }
1159
1160 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1161 clock = adjusted_mode->crtc_clock;
1162 htotal = adjusted_mode->crtc_htotal;
1163 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1164 pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1165
1166 /* Use the small buffer method to calculate plane watermark */
1167 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1168 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1169 if (tlb_miss > 0)
1170 entries += tlb_miss;
1171 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1172 *plane_wm = entries + display->guard_size;
1173 if (*plane_wm > (int)display->max_wm)
1174 *plane_wm = display->max_wm;
1175
1176 /* Use the large buffer method to calculate cursor watermark */
1177 line_time_us = max(htotal * 1000 / clock, 1);
1178 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1179 entries = line_count * to_intel_crtc(crtc)->cursor_width * pixel_size;
1180 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1181 if (tlb_miss > 0)
1182 entries += tlb_miss;
1183 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1184 *cursor_wm = entries + cursor->guard_size;
1185 if (*cursor_wm > (int)cursor->max_wm)
1186 *cursor_wm = (int)cursor->max_wm;
1187
1188 return true;
1189 }
1190
1191 /*
1192 * Check the wm result.
1193 *
1194 * If any calculated watermark values is larger than the maximum value that
1195 * can be programmed into the associated watermark register, that watermark
1196 * must be disabled.
1197 */
1198 static bool g4x_check_srwm(struct drm_device *dev,
1199 int display_wm, int cursor_wm,
1200 const struct intel_watermark_params *display,
1201 const struct intel_watermark_params *cursor)
1202 {
1203 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1204 display_wm, cursor_wm);
1205
1206 if (display_wm > display->max_wm) {
1207 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1208 display_wm, display->max_wm);
1209 return false;
1210 }
1211
1212 if (cursor_wm > cursor->max_wm) {
1213 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1214 cursor_wm, cursor->max_wm);
1215 return false;
1216 }
1217
1218 if (!(display_wm || cursor_wm)) {
1219 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1220 return false;
1221 }
1222
1223 return true;
1224 }
1225
1226 static bool g4x_compute_srwm(struct drm_device *dev,
1227 int plane,
1228 int latency_ns,
1229 const struct intel_watermark_params *display,
1230 const struct intel_watermark_params *cursor,
1231 int *display_wm, int *cursor_wm)
1232 {
1233 struct drm_crtc *crtc;
1234 const struct drm_display_mode *adjusted_mode;
1235 int hdisplay, htotal, pixel_size, clock;
1236 unsigned long line_time_us;
1237 int line_count, line_size;
1238 int small, large;
1239 int entries;
1240
1241 if (!latency_ns) {
1242 *display_wm = *cursor_wm = 0;
1243 return false;
1244 }
1245
1246 crtc = intel_get_crtc_for_plane(dev, plane);
1247 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1248 clock = adjusted_mode->crtc_clock;
1249 htotal = adjusted_mode->crtc_htotal;
1250 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1251 pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1252
1253 line_time_us = max(htotal * 1000 / clock, 1);
1254 line_count = (latency_ns / line_time_us + 1000) / 1000;
1255 line_size = hdisplay * pixel_size;
1256
1257 /* Use the minimum of the small and large buffer method for primary */
1258 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1259 large = line_count * line_size;
1260
1261 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1262 *display_wm = entries + display->guard_size;
1263
1264 /* calculate the self-refresh watermark for display cursor */
1265 entries = line_count * pixel_size * to_intel_crtc(crtc)->cursor_width;
1266 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1267 *cursor_wm = entries + cursor->guard_size;
1268
1269 return g4x_check_srwm(dev,
1270 *display_wm, *cursor_wm,
1271 display, cursor);
1272 }
1273
1274 static bool vlv_compute_drain_latency(struct drm_device *dev,
1275 int plane,
1276 int *plane_prec_mult,
1277 int *plane_dl,
1278 int *cursor_prec_mult,
1279 int *cursor_dl)
1280 {
1281 struct drm_crtc *crtc;
1282 int clock, pixel_size;
1283 int entries;
1284
1285 crtc = intel_get_crtc_for_plane(dev, plane);
1286 if (!intel_crtc_active(crtc))
1287 return false;
1288
1289 clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
1290 pixel_size = crtc->primary->fb->bits_per_pixel / 8; /* BPP */
1291
1292 entries = (clock / 1000) * pixel_size;
1293 *plane_prec_mult = (entries > 128) ?
1294 DRAIN_LATENCY_PRECISION_64 : DRAIN_LATENCY_PRECISION_32;
1295 *plane_dl = (64 * (*plane_prec_mult) * 4) / entries;
1296
1297 entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */
1298 *cursor_prec_mult = (entries > 128) ?
1299 DRAIN_LATENCY_PRECISION_64 : DRAIN_LATENCY_PRECISION_32;
1300 *cursor_dl = (64 * (*cursor_prec_mult) * 4) / entries;
1301
1302 return true;
1303 }
1304
1305 /*
1306 * Update drain latency registers of memory arbiter
1307 *
1308 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1309 * to be programmed. Each plane has a drain latency multiplier and a drain
1310 * latency value.
1311 */
1312
1313 static void vlv_update_drain_latency(struct drm_device *dev)
1314 {
1315 struct drm_i915_private *dev_priv = dev->dev_private;
1316 enum pipe pipe;
1317
1318 for_each_pipe(pipe) {
1319 int plane_prec, plane_dl;
1320 int cursor_prec, cursor_dl;
1321 int plane_prec_mult, cursor_prec_mult;
1322
1323 if (!vlv_compute_drain_latency(dev, pipe, &plane_prec_mult, &plane_dl,
1324 &cursor_prec_mult, &cursor_dl))
1325 continue;
1326
1327 /*
1328 * FIXME CHV spec still lists 16 and 32 as the precision
1329 * values. Need to figure out if spec is outdated or what.
1330 */
1331 cursor_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_64) ?
1332 DDL_CURSOR_PRECISION_64 : DDL_CURSOR_PRECISION_32;
1333 plane_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_64) ?
1334 DDL_PLANE_PRECISION_64 : DDL_PLANE_PRECISION_32;
1335
1336 I915_WRITE(VLV_DDL(pipe), cursor_prec |
1337 (cursor_dl << DDL_CURSOR_SHIFT) |
1338 plane_prec | (plane_dl << DDL_PLANE_SHIFT));
1339 }
1340 }
1341
1342 #define single_plane_enabled(mask) is_power_of_2(mask)
1343
1344 static void valleyview_update_wm(struct drm_crtc *crtc)
1345 {
1346 struct drm_device *dev = crtc->dev;
1347 static const int sr_latency_ns = 12000;
1348 struct drm_i915_private *dev_priv = dev->dev_private;
1349 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1350 int plane_sr, cursor_sr;
1351 int ignore_plane_sr, ignore_cursor_sr;
1352 unsigned int enabled = 0;
1353 bool cxsr_enabled;
1354
1355 vlv_update_drain_latency(dev);
1356
1357 if (g4x_compute_wm0(dev, PIPE_A,
1358 &valleyview_wm_info, latency_ns,
1359 &valleyview_cursor_wm_info, latency_ns,
1360 &planea_wm, &cursora_wm))
1361 enabled |= 1 << PIPE_A;
1362
1363 if (g4x_compute_wm0(dev, PIPE_B,
1364 &valleyview_wm_info, latency_ns,
1365 &valleyview_cursor_wm_info, latency_ns,
1366 &planeb_wm, &cursorb_wm))
1367 enabled |= 1 << PIPE_B;
1368
1369 if (single_plane_enabled(enabled) &&
1370 g4x_compute_srwm(dev, ffs(enabled) - 1,
1371 sr_latency_ns,
1372 &valleyview_wm_info,
1373 &valleyview_cursor_wm_info,
1374 &plane_sr, &ignore_cursor_sr) &&
1375 g4x_compute_srwm(dev, ffs(enabled) - 1,
1376 2*sr_latency_ns,
1377 &valleyview_wm_info,
1378 &valleyview_cursor_wm_info,
1379 &ignore_plane_sr, &cursor_sr)) {
1380 cxsr_enabled = true;
1381 } else {
1382 cxsr_enabled = false;
1383 intel_set_memory_cxsr(dev_priv, false);
1384 plane_sr = cursor_sr = 0;
1385 }
1386
1387 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1388 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1389 planea_wm, cursora_wm,
1390 planeb_wm, cursorb_wm,
1391 plane_sr, cursor_sr);
1392
1393 I915_WRITE(DSPFW1,
1394 (plane_sr << DSPFW_SR_SHIFT) |
1395 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1396 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1397 (planea_wm << DSPFW_PLANEA_SHIFT));
1398 I915_WRITE(DSPFW2,
1399 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1400 (cursora_wm << DSPFW_CURSORA_SHIFT));
1401 I915_WRITE(DSPFW3,
1402 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1403 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1404
1405 if (cxsr_enabled)
1406 intel_set_memory_cxsr(dev_priv, true);
1407 }
1408
1409 static void g4x_update_wm(struct drm_crtc *crtc)
1410 {
1411 struct drm_device *dev = crtc->dev;
1412 static const int sr_latency_ns = 12000;
1413 struct drm_i915_private *dev_priv = dev->dev_private;
1414 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1415 int plane_sr, cursor_sr;
1416 unsigned int enabled = 0;
1417 bool cxsr_enabled;
1418
1419 if (g4x_compute_wm0(dev, PIPE_A,
1420 &g4x_wm_info, latency_ns,
1421 &g4x_cursor_wm_info, latency_ns,
1422 &planea_wm, &cursora_wm))
1423 enabled |= 1 << PIPE_A;
1424
1425 if (g4x_compute_wm0(dev, PIPE_B,
1426 &g4x_wm_info, latency_ns,
1427 &g4x_cursor_wm_info, latency_ns,
1428 &planeb_wm, &cursorb_wm))
1429 enabled |= 1 << PIPE_B;
1430
1431 if (single_plane_enabled(enabled) &&
1432 g4x_compute_srwm(dev, ffs(enabled) - 1,
1433 sr_latency_ns,
1434 &g4x_wm_info,
1435 &g4x_cursor_wm_info,
1436 &plane_sr, &cursor_sr)) {
1437 cxsr_enabled = true;
1438 } else {
1439 cxsr_enabled = false;
1440 intel_set_memory_cxsr(dev_priv, false);
1441 plane_sr = cursor_sr = 0;
1442 }
1443
1444 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1445 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1446 planea_wm, cursora_wm,
1447 planeb_wm, cursorb_wm,
1448 plane_sr, cursor_sr);
1449
1450 I915_WRITE(DSPFW1,
1451 (plane_sr << DSPFW_SR_SHIFT) |
1452 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1453 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1454 (planea_wm << DSPFW_PLANEA_SHIFT));
1455 I915_WRITE(DSPFW2,
1456 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1457 (cursora_wm << DSPFW_CURSORA_SHIFT));
1458 /* HPLL off in SR has some issues on G4x... disable it */
1459 I915_WRITE(DSPFW3,
1460 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1461 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1462
1463 if (cxsr_enabled)
1464 intel_set_memory_cxsr(dev_priv, true);
1465 }
1466
1467 static void i965_update_wm(struct drm_crtc *unused_crtc)
1468 {
1469 struct drm_device *dev = unused_crtc->dev;
1470 struct drm_i915_private *dev_priv = dev->dev_private;
1471 struct drm_crtc *crtc;
1472 int srwm = 1;
1473 int cursor_sr = 16;
1474 bool cxsr_enabled;
1475
1476 /* Calc sr entries for one plane configs */
1477 crtc = single_enabled_crtc(dev);
1478 if (crtc) {
1479 /* self-refresh has much higher latency */
1480 static const int sr_latency_ns = 12000;
1481 const struct drm_display_mode *adjusted_mode =
1482 &to_intel_crtc(crtc)->config.adjusted_mode;
1483 int clock = adjusted_mode->crtc_clock;
1484 int htotal = adjusted_mode->crtc_htotal;
1485 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1486 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1487 unsigned long line_time_us;
1488 int entries;
1489
1490 line_time_us = max(htotal * 1000 / clock, 1);
1491
1492 /* Use ns/us then divide to preserve precision */
1493 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1494 pixel_size * hdisplay;
1495 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1496 srwm = I965_FIFO_SIZE - entries;
1497 if (srwm < 0)
1498 srwm = 1;
1499 srwm &= 0x1ff;
1500 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1501 entries, srwm);
1502
1503 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1504 pixel_size * to_intel_crtc(crtc)->cursor_width;
1505 entries = DIV_ROUND_UP(entries,
1506 i965_cursor_wm_info.cacheline_size);
1507 cursor_sr = i965_cursor_wm_info.fifo_size -
1508 (entries + i965_cursor_wm_info.guard_size);
1509
1510 if (cursor_sr > i965_cursor_wm_info.max_wm)
1511 cursor_sr = i965_cursor_wm_info.max_wm;
1512
1513 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1514 "cursor %d\n", srwm, cursor_sr);
1515
1516 cxsr_enabled = true;
1517 } else {
1518 cxsr_enabled = false;
1519 /* Turn off self refresh if both pipes are enabled */
1520 intel_set_memory_cxsr(dev_priv, false);
1521 }
1522
1523 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1524 srwm);
1525
1526 /* 965 has limitations... */
1527 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1528 (8 << DSPFW_CURSORB_SHIFT) |
1529 (8 << DSPFW_PLANEB_SHIFT) |
1530 (8 << DSPFW_PLANEA_SHIFT));
1531 I915_WRITE(DSPFW2, (8 << DSPFW_CURSORA_SHIFT) |
1532 (8 << DSPFW_PLANEC_SHIFT_OLD));
1533 /* update cursor SR watermark */
1534 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1535
1536 if (cxsr_enabled)
1537 intel_set_memory_cxsr(dev_priv, true);
1538 }
1539
1540 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1541 {
1542 struct drm_device *dev = unused_crtc->dev;
1543 struct drm_i915_private *dev_priv = dev->dev_private;
1544 const struct intel_watermark_params *wm_info;
1545 uint32_t fwater_lo;
1546 uint32_t fwater_hi;
1547 int cwm, srwm = 1;
1548 int fifo_size;
1549 int planea_wm, planeb_wm;
1550 struct drm_crtc *crtc, *enabled = NULL;
1551
1552 if (IS_I945GM(dev))
1553 wm_info = &i945_wm_info;
1554 else if (!IS_GEN2(dev))
1555 wm_info = &i915_wm_info;
1556 else
1557 wm_info = &i830_wm_info;
1558
1559 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1560 crtc = intel_get_crtc_for_plane(dev, 0);
1561 if (intel_crtc_active(crtc)) {
1562 const struct drm_display_mode *adjusted_mode;
1563 int cpp = crtc->primary->fb->bits_per_pixel / 8;
1564 if (IS_GEN2(dev))
1565 cpp = 4;
1566
1567 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1568 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1569 wm_info, fifo_size, cpp,
1570 latency_ns);
1571 enabled = crtc;
1572 } else
1573 planea_wm = fifo_size - wm_info->guard_size;
1574
1575 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1576 crtc = intel_get_crtc_for_plane(dev, 1);
1577 if (intel_crtc_active(crtc)) {
1578 const struct drm_display_mode *adjusted_mode;
1579 int cpp = crtc->primary->fb->bits_per_pixel / 8;
1580 if (IS_GEN2(dev))
1581 cpp = 4;
1582
1583 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1584 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1585 wm_info, fifo_size, cpp,
1586 latency_ns);
1587 if (enabled == NULL)
1588 enabled = crtc;
1589 else
1590 enabled = NULL;
1591 } else
1592 planeb_wm = fifo_size - wm_info->guard_size;
1593
1594 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1595
1596 if (IS_I915GM(dev) && enabled) {
1597 struct drm_i915_gem_object *obj;
1598
1599 obj = intel_fb_obj(enabled->primary->fb);
1600
1601 /* self-refresh seems busted with untiled */
1602 if (obj->tiling_mode == I915_TILING_NONE)
1603 enabled = NULL;
1604 }
1605
1606 /*
1607 * Overlay gets an aggressive default since video jitter is bad.
1608 */
1609 cwm = 2;
1610
1611 /* Play safe and disable self-refresh before adjusting watermarks. */
1612 intel_set_memory_cxsr(dev_priv, false);
1613
1614 /* Calc sr entries for one plane configs */
1615 if (HAS_FW_BLC(dev) && enabled) {
1616 /* self-refresh has much higher latency */
1617 static const int sr_latency_ns = 6000;
1618 const struct drm_display_mode *adjusted_mode =
1619 &to_intel_crtc(enabled)->config.adjusted_mode;
1620 int clock = adjusted_mode->crtc_clock;
1621 int htotal = adjusted_mode->crtc_htotal;
1622 int hdisplay = to_intel_crtc(enabled)->config.pipe_src_w;
1623 int pixel_size = enabled->primary->fb->bits_per_pixel / 8;
1624 unsigned long line_time_us;
1625 int entries;
1626
1627 line_time_us = max(htotal * 1000 / clock, 1);
1628
1629 /* Use ns/us then divide to preserve precision */
1630 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1631 pixel_size * hdisplay;
1632 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1633 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1634 srwm = wm_info->fifo_size - entries;
1635 if (srwm < 0)
1636 srwm = 1;
1637
1638 if (IS_I945G(dev) || IS_I945GM(dev))
1639 I915_WRITE(FW_BLC_SELF,
1640 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1641 else if (IS_I915GM(dev))
1642 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1643 }
1644
1645 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1646 planea_wm, planeb_wm, cwm, srwm);
1647
1648 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1649 fwater_hi = (cwm & 0x1f);
1650
1651 /* Set request length to 8 cachelines per fetch */
1652 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1653 fwater_hi = fwater_hi | (1 << 8);
1654
1655 I915_WRITE(FW_BLC, fwater_lo);
1656 I915_WRITE(FW_BLC2, fwater_hi);
1657
1658 if (enabled)
1659 intel_set_memory_cxsr(dev_priv, true);
1660 }
1661
1662 static void i845_update_wm(struct drm_crtc *unused_crtc)
1663 {
1664 struct drm_device *dev = unused_crtc->dev;
1665 struct drm_i915_private *dev_priv = dev->dev_private;
1666 struct drm_crtc *crtc;
1667 const struct drm_display_mode *adjusted_mode;
1668 uint32_t fwater_lo;
1669 int planea_wm;
1670
1671 crtc = single_enabled_crtc(dev);
1672 if (crtc == NULL)
1673 return;
1674
1675 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1676 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1677 &i845_wm_info,
1678 dev_priv->display.get_fifo_size(dev, 0),
1679 4, latency_ns);
1680 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1681 fwater_lo |= (3<<8) | planea_wm;
1682
1683 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1684
1685 I915_WRITE(FW_BLC, fwater_lo);
1686 }
1687
1688 static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
1689 struct drm_crtc *crtc)
1690 {
1691 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1692 uint32_t pixel_rate;
1693
1694 pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock;
1695
1696 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1697 * adjust the pixel_rate here. */
1698
1699 if (intel_crtc->config.pch_pfit.enabled) {
1700 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1701 uint32_t pfit_size = intel_crtc->config.pch_pfit.size;
1702
1703 pipe_w = intel_crtc->config.pipe_src_w;
1704 pipe_h = intel_crtc->config.pipe_src_h;
1705 pfit_w = (pfit_size >> 16) & 0xFFFF;
1706 pfit_h = pfit_size & 0xFFFF;
1707 if (pipe_w < pfit_w)
1708 pipe_w = pfit_w;
1709 if (pipe_h < pfit_h)
1710 pipe_h = pfit_h;
1711
1712 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1713 pfit_w * pfit_h);
1714 }
1715
1716 return pixel_rate;
1717 }
1718
1719 /* latency must be in 0.1us units. */
1720 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
1721 uint32_t latency)
1722 {
1723 uint64_t ret;
1724
1725 if (WARN(latency == 0, "Latency value missing\n"))
1726 return UINT_MAX;
1727
1728 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1729 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1730
1731 return ret;
1732 }
1733
1734 /* latency must be in 0.1us units. */
1735 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1736 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1737 uint32_t latency)
1738 {
1739 uint32_t ret;
1740
1741 if (WARN(latency == 0, "Latency value missing\n"))
1742 return UINT_MAX;
1743
1744 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1745 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1746 ret = DIV_ROUND_UP(ret, 64) + 2;
1747 return ret;
1748 }
1749
1750 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1751 uint8_t bytes_per_pixel)
1752 {
1753 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1754 }
1755
1756 struct ilk_pipe_wm_parameters {
1757 bool active;
1758 uint32_t pipe_htotal;
1759 uint32_t pixel_rate;
1760 struct intel_plane_wm_parameters pri;
1761 struct intel_plane_wm_parameters spr;
1762 struct intel_plane_wm_parameters cur;
1763 };
1764
1765 struct ilk_wm_maximums {
1766 uint16_t pri;
1767 uint16_t spr;
1768 uint16_t cur;
1769 uint16_t fbc;
1770 };
1771
1772 /* used in computing the new watermarks state */
1773 struct intel_wm_config {
1774 unsigned int num_pipes_active;
1775 bool sprites_enabled;
1776 bool sprites_scaled;
1777 };
1778
1779 /*
1780 * For both WM_PIPE and WM_LP.
1781 * mem_value must be in 0.1us units.
1782 */
1783 static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params,
1784 uint32_t mem_value,
1785 bool is_lp)
1786 {
1787 uint32_t method1, method2;
1788
1789 if (!params->active || !params->pri.enabled)
1790 return 0;
1791
1792 method1 = ilk_wm_method1(params->pixel_rate,
1793 params->pri.bytes_per_pixel,
1794 mem_value);
1795
1796 if (!is_lp)
1797 return method1;
1798
1799 method2 = ilk_wm_method2(params->pixel_rate,
1800 params->pipe_htotal,
1801 params->pri.horiz_pixels,
1802 params->pri.bytes_per_pixel,
1803 mem_value);
1804
1805 return min(method1, method2);
1806 }
1807
1808 /*
1809 * For both WM_PIPE and WM_LP.
1810 * mem_value must be in 0.1us units.
1811 */
1812 static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params,
1813 uint32_t mem_value)
1814 {
1815 uint32_t method1, method2;
1816
1817 if (!params->active || !params->spr.enabled)
1818 return 0;
1819
1820 method1 = ilk_wm_method1(params->pixel_rate,
1821 params->spr.bytes_per_pixel,
1822 mem_value);
1823 method2 = ilk_wm_method2(params->pixel_rate,
1824 params->pipe_htotal,
1825 params->spr.horiz_pixels,
1826 params->spr.bytes_per_pixel,
1827 mem_value);
1828 return min(method1, method2);
1829 }
1830
1831 /*
1832 * For both WM_PIPE and WM_LP.
1833 * mem_value must be in 0.1us units.
1834 */
1835 static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params,
1836 uint32_t mem_value)
1837 {
1838 if (!params->active || !params->cur.enabled)
1839 return 0;
1840
1841 return ilk_wm_method2(params->pixel_rate,
1842 params->pipe_htotal,
1843 params->cur.horiz_pixels,
1844 params->cur.bytes_per_pixel,
1845 mem_value);
1846 }
1847
1848 /* Only for WM_LP. */
1849 static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params,
1850 uint32_t pri_val)
1851 {
1852 if (!params->active || !params->pri.enabled)
1853 return 0;
1854
1855 return ilk_wm_fbc(pri_val,
1856 params->pri.horiz_pixels,
1857 params->pri.bytes_per_pixel);
1858 }
1859
1860 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1861 {
1862 if (INTEL_INFO(dev)->gen >= 8)
1863 return 3072;
1864 else if (INTEL_INFO(dev)->gen >= 7)
1865 return 768;
1866 else
1867 return 512;
1868 }
1869
1870 static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1871 int level, bool is_sprite)
1872 {
1873 if (INTEL_INFO(dev)->gen >= 8)
1874 /* BDW primary/sprite plane watermarks */
1875 return level == 0 ? 255 : 2047;
1876 else if (INTEL_INFO(dev)->gen >= 7)
1877 /* IVB/HSW primary/sprite plane watermarks */
1878 return level == 0 ? 127 : 1023;
1879 else if (!is_sprite)
1880 /* ILK/SNB primary plane watermarks */
1881 return level == 0 ? 127 : 511;
1882 else
1883 /* ILK/SNB sprite plane watermarks */
1884 return level == 0 ? 63 : 255;
1885 }
1886
1887 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1888 int level)
1889 {
1890 if (INTEL_INFO(dev)->gen >= 7)
1891 return level == 0 ? 63 : 255;
1892 else
1893 return level == 0 ? 31 : 63;
1894 }
1895
1896 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1897 {
1898 if (INTEL_INFO(dev)->gen >= 8)
1899 return 31;
1900 else
1901 return 15;
1902 }
1903
1904 /* Calculate the maximum primary/sprite plane watermark */
1905 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1906 int level,
1907 const struct intel_wm_config *config,
1908 enum intel_ddb_partitioning ddb_partitioning,
1909 bool is_sprite)
1910 {
1911 unsigned int fifo_size = ilk_display_fifo_size(dev);
1912
1913 /* if sprites aren't enabled, sprites get nothing */
1914 if (is_sprite && !config->sprites_enabled)
1915 return 0;
1916
1917 /* HSW allows LP1+ watermarks even with multiple pipes */
1918 if (level == 0 || config->num_pipes_active > 1) {
1919 fifo_size /= INTEL_INFO(dev)->num_pipes;
1920
1921 /*
1922 * For some reason the non self refresh
1923 * FIFO size is only half of the self
1924 * refresh FIFO size on ILK/SNB.
1925 */
1926 if (INTEL_INFO(dev)->gen <= 6)
1927 fifo_size /= 2;
1928 }
1929
1930 if (config->sprites_enabled) {
1931 /* level 0 is always calculated with 1:1 split */
1932 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1933 if (is_sprite)
1934 fifo_size *= 5;
1935 fifo_size /= 6;
1936 } else {
1937 fifo_size /= 2;
1938 }
1939 }
1940
1941 /* clamp to max that the registers can hold */
1942 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
1943 }
1944
1945 /* Calculate the maximum cursor plane watermark */
1946 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
1947 int level,
1948 const struct intel_wm_config *config)
1949 {
1950 /* HSW LP1+ watermarks w/ multiple pipes */
1951 if (level > 0 && config->num_pipes_active > 1)
1952 return 64;
1953
1954 /* otherwise just report max that registers can hold */
1955 return ilk_cursor_wm_reg_max(dev, level);
1956 }
1957
1958 static void ilk_compute_wm_maximums(const struct drm_device *dev,
1959 int level,
1960 const struct intel_wm_config *config,
1961 enum intel_ddb_partitioning ddb_partitioning,
1962 struct ilk_wm_maximums *max)
1963 {
1964 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1965 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1966 max->cur = ilk_cursor_wm_max(dev, level, config);
1967 max->fbc = ilk_fbc_wm_reg_max(dev);
1968 }
1969
1970 static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1971 int level,
1972 struct ilk_wm_maximums *max)
1973 {
1974 max->pri = ilk_plane_wm_reg_max(dev, level, false);
1975 max->spr = ilk_plane_wm_reg_max(dev, level, true);
1976 max->cur = ilk_cursor_wm_reg_max(dev, level);
1977 max->fbc = ilk_fbc_wm_reg_max(dev);
1978 }
1979
1980 static bool ilk_validate_wm_level(int level,
1981 const struct ilk_wm_maximums *max,
1982 struct intel_wm_level *result)
1983 {
1984 bool ret;
1985
1986 /* already determined to be invalid? */
1987 if (!result->enable)
1988 return false;
1989
1990 result->enable = result->pri_val <= max->pri &&
1991 result->spr_val <= max->spr &&
1992 result->cur_val <= max->cur;
1993
1994 ret = result->enable;
1995
1996 /*
1997 * HACK until we can pre-compute everything,
1998 * and thus fail gracefully if LP0 watermarks
1999 * are exceeded...
2000 */
2001 if (level == 0 && !result->enable) {
2002 if (result->pri_val > max->pri)
2003 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2004 level, result->pri_val, max->pri);
2005 if (result->spr_val > max->spr)
2006 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2007 level, result->spr_val, max->spr);
2008 if (result->cur_val > max->cur)
2009 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2010 level, result->cur_val, max->cur);
2011
2012 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2013 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2014 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2015 result->enable = true;
2016 }
2017
2018 return ret;
2019 }
2020
2021 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
2022 int level,
2023 const struct ilk_pipe_wm_parameters *p,
2024 struct intel_wm_level *result)
2025 {
2026 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2027 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2028 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2029
2030 /* WM1+ latency values stored in 0.5us units */
2031 if (level > 0) {
2032 pri_latency *= 5;
2033 spr_latency *= 5;
2034 cur_latency *= 5;
2035 }
2036
2037 result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
2038 result->spr_val = ilk_compute_spr_wm(p, spr_latency);
2039 result->cur_val = ilk_compute_cur_wm(p, cur_latency);
2040 result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
2041 result->enable = true;
2042 }
2043
2044 static uint32_t
2045 hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
2046 {
2047 struct drm_i915_private *dev_priv = dev->dev_private;
2048 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2049 struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
2050 u32 linetime, ips_linetime;
2051
2052 if (!intel_crtc_active(crtc))
2053 return 0;
2054
2055 /* The WM are computed with base on how long it takes to fill a single
2056 * row at the given clock rate, multiplied by 8.
2057 * */
2058 linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
2059 mode->crtc_clock);
2060 ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
2061 intel_ddi_get_cdclk_freq(dev_priv));
2062
2063 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2064 PIPE_WM_LINETIME_TIME(linetime);
2065 }
2066
2067 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5])
2068 {
2069 struct drm_i915_private *dev_priv = dev->dev_private;
2070
2071 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2072 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2073
2074 wm[0] = (sskpd >> 56) & 0xFF;
2075 if (wm[0] == 0)
2076 wm[0] = sskpd & 0xF;
2077 wm[1] = (sskpd >> 4) & 0xFF;
2078 wm[2] = (sskpd >> 12) & 0xFF;
2079 wm[3] = (sskpd >> 20) & 0x1FF;
2080 wm[4] = (sskpd >> 32) & 0x1FF;
2081 } else if (INTEL_INFO(dev)->gen >= 6) {
2082 uint32_t sskpd = I915_READ(MCH_SSKPD);
2083
2084 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2085 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2086 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2087 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2088 } else if (INTEL_INFO(dev)->gen >= 5) {
2089 uint32_t mltr = I915_READ(MLTR_ILK);
2090
2091 /* ILK primary LP0 latency is 700 ns */
2092 wm[0] = 7;
2093 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2094 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2095 }
2096 }
2097
2098 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2099 {
2100 /* ILK sprite LP0 latency is 1300 ns */
2101 if (INTEL_INFO(dev)->gen == 5)
2102 wm[0] = 13;
2103 }
2104
2105 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2106 {
2107 /* ILK cursor LP0 latency is 1300 ns */
2108 if (INTEL_INFO(dev)->gen == 5)
2109 wm[0] = 13;
2110
2111 /* WaDoubleCursorLP3Latency:ivb */
2112 if (IS_IVYBRIDGE(dev))
2113 wm[3] *= 2;
2114 }
2115
2116 int ilk_wm_max_level(const struct drm_device *dev)
2117 {
2118 /* how many WM levels are we expecting */
2119 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2120 return 4;
2121 else if (INTEL_INFO(dev)->gen >= 6)
2122 return 3;
2123 else
2124 return 2;
2125 }
2126
2127 static void intel_print_wm_latency(struct drm_device *dev,
2128 const char *name,
2129 const uint16_t wm[5])
2130 {
2131 int level, max_level = ilk_wm_max_level(dev);
2132
2133 for (level = 0; level <= max_level; level++) {
2134 unsigned int latency = wm[level];
2135
2136 if (latency == 0) {
2137 DRM_ERROR("%s WM%d latency not provided\n",
2138 name, level);
2139 continue;
2140 }
2141
2142 /* WM1+ latency values in 0.5us units */
2143 if (level > 0)
2144 latency *= 5;
2145
2146 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2147 name, level, wm[level],
2148 latency / 10, latency % 10);
2149 }
2150 }
2151
2152 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2153 uint16_t wm[5], uint16_t min)
2154 {
2155 int level, max_level = ilk_wm_max_level(dev_priv->dev);
2156
2157 if (wm[0] >= min)
2158 return false;
2159
2160 wm[0] = max(wm[0], min);
2161 for (level = 1; level <= max_level; level++)
2162 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2163
2164 return true;
2165 }
2166
2167 static void snb_wm_latency_quirk(struct drm_device *dev)
2168 {
2169 struct drm_i915_private *dev_priv = dev->dev_private;
2170 bool changed;
2171
2172 /*
2173 * The BIOS provided WM memory latency values are often
2174 * inadequate for high resolution displays. Adjust them.
2175 */
2176 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2177 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2178 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2179
2180 if (!changed)
2181 return;
2182
2183 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2184 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2185 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2186 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2187 }
2188
2189 static void ilk_setup_wm_latency(struct drm_device *dev)
2190 {
2191 struct drm_i915_private *dev_priv = dev->dev_private;
2192
2193 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2194
2195 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2196 sizeof(dev_priv->wm.pri_latency));
2197 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2198 sizeof(dev_priv->wm.pri_latency));
2199
2200 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2201 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2202
2203 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2204 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2205 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2206
2207 if (IS_GEN6(dev))
2208 snb_wm_latency_quirk(dev);
2209 }
2210
2211 static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
2212 struct ilk_pipe_wm_parameters *p)
2213 {
2214 struct drm_device *dev = crtc->dev;
2215 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2216 enum pipe pipe = intel_crtc->pipe;
2217 struct drm_plane *plane;
2218
2219 if (!intel_crtc_active(crtc))
2220 return;
2221
2222 p->active = true;
2223 p->pipe_htotal = intel_crtc->config.adjusted_mode.crtc_htotal;
2224 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
2225 p->pri.bytes_per_pixel = crtc->primary->fb->bits_per_pixel / 8;
2226 p->cur.bytes_per_pixel = 4;
2227 p->pri.horiz_pixels = intel_crtc->config.pipe_src_w;
2228 p->cur.horiz_pixels = intel_crtc->cursor_width;
2229 /* TODO: for now, assume primary and cursor planes are always enabled. */
2230 p->pri.enabled = true;
2231 p->cur.enabled = true;
2232
2233 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
2234 struct intel_plane *intel_plane = to_intel_plane(plane);
2235
2236 if (intel_plane->pipe == pipe) {
2237 p->spr = intel_plane->wm;
2238 break;
2239 }
2240 }
2241 }
2242
2243 static void ilk_compute_wm_config(struct drm_device *dev,
2244 struct intel_wm_config *config)
2245 {
2246 struct intel_crtc *intel_crtc;
2247
2248 /* Compute the currently _active_ config */
2249 for_each_intel_crtc(dev, intel_crtc) {
2250 const struct intel_pipe_wm *wm = &intel_crtc->wm.active;
2251
2252 if (!wm->pipe_enabled)
2253 continue;
2254
2255 config->sprites_enabled |= wm->sprites_enabled;
2256 config->sprites_scaled |= wm->sprites_scaled;
2257 config->num_pipes_active++;
2258 }
2259 }
2260
2261 /* Compute new watermarks for the pipe */
2262 static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
2263 const struct ilk_pipe_wm_parameters *params,
2264 struct intel_pipe_wm *pipe_wm)
2265 {
2266 struct drm_device *dev = crtc->dev;
2267 const struct drm_i915_private *dev_priv = dev->dev_private;
2268 int level, max_level = ilk_wm_max_level(dev);
2269 /* LP0 watermark maximums depend on this pipe alone */
2270 struct intel_wm_config config = {
2271 .num_pipes_active = 1,
2272 .sprites_enabled = params->spr.enabled,
2273 .sprites_scaled = params->spr.scaled,
2274 };
2275 struct ilk_wm_maximums max;
2276
2277 pipe_wm->pipe_enabled = params->active;
2278 pipe_wm->sprites_enabled = params->spr.enabled;
2279 pipe_wm->sprites_scaled = params->spr.scaled;
2280
2281 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2282 if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled)
2283 max_level = 1;
2284
2285 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2286 if (params->spr.scaled)
2287 max_level = 0;
2288
2289 ilk_compute_wm_level(dev_priv, 0, params, &pipe_wm->wm[0]);
2290
2291 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2292 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
2293
2294 /* LP0 watermarks always use 1/2 DDB partitioning */
2295 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2296
2297 /* At least LP0 must be valid */
2298 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
2299 return false;
2300
2301 ilk_compute_wm_reg_maximums(dev, 1, &max);
2302
2303 for (level = 1; level <= max_level; level++) {
2304 struct intel_wm_level wm = {};
2305
2306 ilk_compute_wm_level(dev_priv, level, params, &wm);
2307
2308 /*
2309 * Disable any watermark level that exceeds the
2310 * register maximums since such watermarks are
2311 * always invalid.
2312 */
2313 if (!ilk_validate_wm_level(level, &max, &wm))
2314 break;
2315
2316 pipe_wm->wm[level] = wm;
2317 }
2318
2319 return true;
2320 }
2321
2322 /*
2323 * Merge the watermarks from all active pipes for a specific level.
2324 */
2325 static void ilk_merge_wm_level(struct drm_device *dev,
2326 int level,
2327 struct intel_wm_level *ret_wm)
2328 {
2329 const struct intel_crtc *intel_crtc;
2330
2331 ret_wm->enable = true;
2332
2333 for_each_intel_crtc(dev, intel_crtc) {
2334 const struct intel_pipe_wm *active = &intel_crtc->wm.active;
2335 const struct intel_wm_level *wm = &active->wm[level];
2336
2337 if (!active->pipe_enabled)
2338 continue;
2339
2340 /*
2341 * The watermark values may have been used in the past,
2342 * so we must maintain them in the registers for some
2343 * time even if the level is now disabled.
2344 */
2345 if (!wm->enable)
2346 ret_wm->enable = false;
2347
2348 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2349 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2350 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2351 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2352 }
2353 }
2354
2355 /*
2356 * Merge all low power watermarks for all active pipes.
2357 */
2358 static void ilk_wm_merge(struct drm_device *dev,
2359 const struct intel_wm_config *config,
2360 const struct ilk_wm_maximums *max,
2361 struct intel_pipe_wm *merged)
2362 {
2363 int level, max_level = ilk_wm_max_level(dev);
2364 int last_enabled_level = max_level;
2365
2366 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2367 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2368 config->num_pipes_active > 1)
2369 return;
2370
2371 /* ILK: FBC WM must be disabled always */
2372 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
2373
2374 /* merge each WM1+ level */
2375 for (level = 1; level <= max_level; level++) {
2376 struct intel_wm_level *wm = &merged->wm[level];
2377
2378 ilk_merge_wm_level(dev, level, wm);
2379
2380 if (level > last_enabled_level)
2381 wm->enable = false;
2382 else if (!ilk_validate_wm_level(level, max, wm))
2383 /* make sure all following levels get disabled */
2384 last_enabled_level = level - 1;
2385
2386 /*
2387 * The spec says it is preferred to disable
2388 * FBC WMs instead of disabling a WM level.
2389 */
2390 if (wm->fbc_val > max->fbc) {
2391 if (wm->enable)
2392 merged->fbc_wm_enabled = false;
2393 wm->fbc_val = 0;
2394 }
2395 }
2396
2397 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2398 /*
2399 * FIXME this is racy. FBC might get enabled later.
2400 * What we should check here is whether FBC can be
2401 * enabled sometime later.
2402 */
2403 if (IS_GEN5(dev) && !merged->fbc_wm_enabled && intel_fbc_enabled(dev)) {
2404 for (level = 2; level <= max_level; level++) {
2405 struct intel_wm_level *wm = &merged->wm[level];
2406
2407 wm->enable = false;
2408 }
2409 }
2410 }
2411
2412 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2413 {
2414 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2415 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2416 }
2417
2418 /* The value we need to program into the WM_LPx latency field */
2419 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2420 {
2421 struct drm_i915_private *dev_priv = dev->dev_private;
2422
2423 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2424 return 2 * level;
2425 else
2426 return dev_priv->wm.pri_latency[level];
2427 }
2428
2429 static void ilk_compute_wm_results(struct drm_device *dev,
2430 const struct intel_pipe_wm *merged,
2431 enum intel_ddb_partitioning partitioning,
2432 struct ilk_wm_values *results)
2433 {
2434 struct intel_crtc *intel_crtc;
2435 int level, wm_lp;
2436
2437 results->enable_fbc_wm = merged->fbc_wm_enabled;
2438 results->partitioning = partitioning;
2439
2440 /* LP1+ register values */
2441 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2442 const struct intel_wm_level *r;
2443
2444 level = ilk_wm_lp_to_level(wm_lp, merged);
2445
2446 r = &merged->wm[level];
2447
2448 /*
2449 * Maintain the watermark values even if the level is
2450 * disabled. Doing otherwise could cause underruns.
2451 */
2452 results->wm_lp[wm_lp - 1] =
2453 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2454 (r->pri_val << WM1_LP_SR_SHIFT) |
2455 r->cur_val;
2456
2457 if (r->enable)
2458 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2459
2460 if (INTEL_INFO(dev)->gen >= 8)
2461 results->wm_lp[wm_lp - 1] |=
2462 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2463 else
2464 results->wm_lp[wm_lp - 1] |=
2465 r->fbc_val << WM1_LP_FBC_SHIFT;
2466
2467 /*
2468 * Always set WM1S_LP_EN when spr_val != 0, even if the
2469 * level is disabled. Doing otherwise could cause underruns.
2470 */
2471 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2472 WARN_ON(wm_lp != 1);
2473 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2474 } else
2475 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2476 }
2477
2478 /* LP0 register values */
2479 for_each_intel_crtc(dev, intel_crtc) {
2480 enum pipe pipe = intel_crtc->pipe;
2481 const struct intel_wm_level *r =
2482 &intel_crtc->wm.active.wm[0];
2483
2484 if (WARN_ON(!r->enable))
2485 continue;
2486
2487 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
2488
2489 results->wm_pipe[pipe] =
2490 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2491 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2492 r->cur_val;
2493 }
2494 }
2495
2496 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2497 * case both are at the same level. Prefer r1 in case they're the same. */
2498 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2499 struct intel_pipe_wm *r1,
2500 struct intel_pipe_wm *r2)
2501 {
2502 int level, max_level = ilk_wm_max_level(dev);
2503 int level1 = 0, level2 = 0;
2504
2505 for (level = 1; level <= max_level; level++) {
2506 if (r1->wm[level].enable)
2507 level1 = level;
2508 if (r2->wm[level].enable)
2509 level2 = level;
2510 }
2511
2512 if (level1 == level2) {
2513 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2514 return r2;
2515 else
2516 return r1;
2517 } else if (level1 > level2) {
2518 return r1;
2519 } else {
2520 return r2;
2521 }
2522 }
2523
2524 /* dirty bits used to track which watermarks need changes */
2525 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2526 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2527 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2528 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2529 #define WM_DIRTY_FBC (1 << 24)
2530 #define WM_DIRTY_DDB (1 << 25)
2531
2532 static unsigned int ilk_compute_wm_dirty(struct drm_device *dev,
2533 const struct ilk_wm_values *old,
2534 const struct ilk_wm_values *new)
2535 {
2536 unsigned int dirty = 0;
2537 enum pipe pipe;
2538 int wm_lp;
2539
2540 for_each_pipe(pipe) {
2541 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2542 dirty |= WM_DIRTY_LINETIME(pipe);
2543 /* Must disable LP1+ watermarks too */
2544 dirty |= WM_DIRTY_LP_ALL;
2545 }
2546
2547 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2548 dirty |= WM_DIRTY_PIPE(pipe);
2549 /* Must disable LP1+ watermarks too */
2550 dirty |= WM_DIRTY_LP_ALL;
2551 }
2552 }
2553
2554 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2555 dirty |= WM_DIRTY_FBC;
2556 /* Must disable LP1+ watermarks too */
2557 dirty |= WM_DIRTY_LP_ALL;
2558 }
2559
2560 if (old->partitioning != new->partitioning) {
2561 dirty |= WM_DIRTY_DDB;
2562 /* Must disable LP1+ watermarks too */
2563 dirty |= WM_DIRTY_LP_ALL;
2564 }
2565
2566 /* LP1+ watermarks already deemed dirty, no need to continue */
2567 if (dirty & WM_DIRTY_LP_ALL)
2568 return dirty;
2569
2570 /* Find the lowest numbered LP1+ watermark in need of an update... */
2571 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2572 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2573 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2574 break;
2575 }
2576
2577 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2578 for (; wm_lp <= 3; wm_lp++)
2579 dirty |= WM_DIRTY_LP(wm_lp);
2580
2581 return dirty;
2582 }
2583
2584 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2585 unsigned int dirty)
2586 {
2587 struct ilk_wm_values *previous = &dev_priv->wm.hw;
2588 bool changed = false;
2589
2590 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2591 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2592 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2593 changed = true;
2594 }
2595 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2596 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2597 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2598 changed = true;
2599 }
2600 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2601 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2602 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2603 changed = true;
2604 }
2605
2606 /*
2607 * Don't touch WM1S_LP_EN here.
2608 * Doing so could cause underruns.
2609 */
2610
2611 return changed;
2612 }
2613
2614 /*
2615 * The spec says we shouldn't write when we don't need, because every write
2616 * causes WMs to be re-evaluated, expending some power.
2617 */
2618 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2619 struct ilk_wm_values *results)
2620 {
2621 struct drm_device *dev = dev_priv->dev;
2622 struct ilk_wm_values *previous = &dev_priv->wm.hw;
2623 unsigned int dirty;
2624 uint32_t val;
2625
2626 dirty = ilk_compute_wm_dirty(dev, previous, results);
2627 if (!dirty)
2628 return;
2629
2630 _ilk_disable_lp_wm(dev_priv, dirty);
2631
2632 if (dirty & WM_DIRTY_PIPE(PIPE_A))
2633 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2634 if (dirty & WM_DIRTY_PIPE(PIPE_B))
2635 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2636 if (dirty & WM_DIRTY_PIPE(PIPE_C))
2637 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2638
2639 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2640 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2641 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2642 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2643 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2644 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2645
2646 if (dirty & WM_DIRTY_DDB) {
2647 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2648 val = I915_READ(WM_MISC);
2649 if (results->partitioning == INTEL_DDB_PART_1_2)
2650 val &= ~WM_MISC_DATA_PARTITION_5_6;
2651 else
2652 val |= WM_MISC_DATA_PARTITION_5_6;
2653 I915_WRITE(WM_MISC, val);
2654 } else {
2655 val = I915_READ(DISP_ARB_CTL2);
2656 if (results->partitioning == INTEL_DDB_PART_1_2)
2657 val &= ~DISP_DATA_PARTITION_5_6;
2658 else
2659 val |= DISP_DATA_PARTITION_5_6;
2660 I915_WRITE(DISP_ARB_CTL2, val);
2661 }
2662 }
2663
2664 if (dirty & WM_DIRTY_FBC) {
2665 val = I915_READ(DISP_ARB_CTL);
2666 if (results->enable_fbc_wm)
2667 val &= ~DISP_FBC_WM_DIS;
2668 else
2669 val |= DISP_FBC_WM_DIS;
2670 I915_WRITE(DISP_ARB_CTL, val);
2671 }
2672
2673 if (dirty & WM_DIRTY_LP(1) &&
2674 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2675 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2676
2677 if (INTEL_INFO(dev)->gen >= 7) {
2678 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2679 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2680 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2681 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2682 }
2683
2684 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2685 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2686 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2687 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2688 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2689 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2690
2691 dev_priv->wm.hw = *results;
2692 }
2693
2694 static bool ilk_disable_lp_wm(struct drm_device *dev)
2695 {
2696 struct drm_i915_private *dev_priv = dev->dev_private;
2697
2698 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2699 }
2700
2701 static void ilk_update_wm(struct drm_crtc *crtc)
2702 {
2703 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2704 struct drm_device *dev = crtc->dev;
2705 struct drm_i915_private *dev_priv = dev->dev_private;
2706 struct ilk_wm_maximums max;
2707 struct ilk_pipe_wm_parameters params = {};
2708 struct ilk_wm_values results = {};
2709 enum intel_ddb_partitioning partitioning;
2710 struct intel_pipe_wm pipe_wm = {};
2711 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
2712 struct intel_wm_config config = {};
2713
2714 ilk_compute_wm_parameters(crtc, &params);
2715
2716 intel_compute_pipe_wm(crtc, &params, &pipe_wm);
2717
2718 if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
2719 return;
2720
2721 intel_crtc->wm.active = pipe_wm;
2722
2723 ilk_compute_wm_config(dev, &config);
2724
2725 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
2726 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
2727
2728 /* 5/6 split only in single pipe config on IVB+ */
2729 if (INTEL_INFO(dev)->gen >= 7 &&
2730 config.num_pipes_active == 1 && config.sprites_enabled) {
2731 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
2732 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
2733
2734 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
2735 } else {
2736 best_lp_wm = &lp_wm_1_2;
2737 }
2738
2739 partitioning = (best_lp_wm == &lp_wm_1_2) ?
2740 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
2741
2742 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
2743
2744 ilk_write_wm_values(dev_priv, &results);
2745 }
2746
2747 static void
2748 ilk_update_sprite_wm(struct drm_plane *plane,
2749 struct drm_crtc *crtc,
2750 uint32_t sprite_width, uint32_t sprite_height,
2751 int pixel_size, bool enabled, bool scaled)
2752 {
2753 struct drm_device *dev = plane->dev;
2754 struct intel_plane *intel_plane = to_intel_plane(plane);
2755
2756 intel_plane->wm.enabled = enabled;
2757 intel_plane->wm.scaled = scaled;
2758 intel_plane->wm.horiz_pixels = sprite_width;
2759 intel_plane->wm.vert_pixels = sprite_width;
2760 intel_plane->wm.bytes_per_pixel = pixel_size;
2761
2762 /*
2763 * IVB workaround: must disable low power watermarks for at least
2764 * one frame before enabling scaling. LP watermarks can be re-enabled
2765 * when scaling is disabled.
2766 *
2767 * WaCxSRDisabledForSpriteScaling:ivb
2768 */
2769 if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev))
2770 intel_wait_for_vblank(dev, intel_plane->pipe);
2771
2772 ilk_update_wm(crtc);
2773 }
2774
2775 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
2776 {
2777 struct drm_device *dev = crtc->dev;
2778 struct drm_i915_private *dev_priv = dev->dev_private;
2779 struct ilk_wm_values *hw = &dev_priv->wm.hw;
2780 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2781 struct intel_pipe_wm *active = &intel_crtc->wm.active;
2782 enum pipe pipe = intel_crtc->pipe;
2783 static const unsigned int wm0_pipe_reg[] = {
2784 [PIPE_A] = WM0_PIPEA_ILK,
2785 [PIPE_B] = WM0_PIPEB_ILK,
2786 [PIPE_C] = WM0_PIPEC_IVB,
2787 };
2788
2789 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
2790 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2791 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
2792
2793 active->pipe_enabled = intel_crtc_active(crtc);
2794
2795 if (active->pipe_enabled) {
2796 u32 tmp = hw->wm_pipe[pipe];
2797
2798 /*
2799 * For active pipes LP0 watermark is marked as
2800 * enabled, and LP1+ watermaks as disabled since
2801 * we can't really reverse compute them in case
2802 * multiple pipes are active.
2803 */
2804 active->wm[0].enable = true;
2805 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
2806 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
2807 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
2808 active->linetime = hw->wm_linetime[pipe];
2809 } else {
2810 int level, max_level = ilk_wm_max_level(dev);
2811
2812 /*
2813 * For inactive pipes, all watermark levels
2814 * should be marked as enabled but zeroed,
2815 * which is what we'd compute them to.
2816 */
2817 for (level = 0; level <= max_level; level++)
2818 active->wm[level].enable = true;
2819 }
2820 }
2821
2822 void ilk_wm_get_hw_state(struct drm_device *dev)
2823 {
2824 struct drm_i915_private *dev_priv = dev->dev_private;
2825 struct ilk_wm_values *hw = &dev_priv->wm.hw;
2826 struct drm_crtc *crtc;
2827
2828 for_each_crtc(dev, crtc)
2829 ilk_pipe_wm_get_hw_state(crtc);
2830
2831 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
2832 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
2833 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
2834
2835 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
2836 if (INTEL_INFO(dev)->gen >= 7) {
2837 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
2838 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
2839 }
2840
2841 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2842 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
2843 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
2844 else if (IS_IVYBRIDGE(dev))
2845 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
2846 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
2847
2848 hw->enable_fbc_wm =
2849 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
2850 }
2851
2852 /**
2853 * intel_update_watermarks - update FIFO watermark values based on current modes
2854 *
2855 * Calculate watermark values for the various WM regs based on current mode
2856 * and plane configuration.
2857 *
2858 * There are several cases to deal with here:
2859 * - normal (i.e. non-self-refresh)
2860 * - self-refresh (SR) mode
2861 * - lines are large relative to FIFO size (buffer can hold up to 2)
2862 * - lines are small relative to FIFO size (buffer can hold more than 2
2863 * lines), so need to account for TLB latency
2864 *
2865 * The normal calculation is:
2866 * watermark = dotclock * bytes per pixel * latency
2867 * where latency is platform & configuration dependent (we assume pessimal
2868 * values here).
2869 *
2870 * The SR calculation is:
2871 * watermark = (trunc(latency/line time)+1) * surface width *
2872 * bytes per pixel
2873 * where
2874 * line time = htotal / dotclock
2875 * surface width = hdisplay for normal plane and 64 for cursor
2876 * and latency is assumed to be high, as above.
2877 *
2878 * The final value programmed to the register should always be rounded up,
2879 * and include an extra 2 entries to account for clock crossings.
2880 *
2881 * We don't use the sprite, so we can ignore that. And on Crestline we have
2882 * to set the non-SR watermarks to 8.
2883 */
2884 void intel_update_watermarks(struct drm_crtc *crtc)
2885 {
2886 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
2887
2888 if (dev_priv->display.update_wm)
2889 dev_priv->display.update_wm(crtc);
2890 }
2891
2892 void intel_update_sprite_watermarks(struct drm_plane *plane,
2893 struct drm_crtc *crtc,
2894 uint32_t sprite_width,
2895 uint32_t sprite_height,
2896 int pixel_size,
2897 bool enabled, bool scaled)
2898 {
2899 struct drm_i915_private *dev_priv = plane->dev->dev_private;
2900
2901 if (dev_priv->display.update_sprite_wm)
2902 dev_priv->display.update_sprite_wm(plane, crtc,
2903 sprite_width, sprite_height,
2904 pixel_size, enabled, scaled);
2905 }
2906
2907 static struct drm_i915_gem_object *
2908 intel_alloc_context_page(struct drm_device *dev)
2909 {
2910 struct drm_i915_gem_object *ctx;
2911 int ret;
2912
2913 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2914
2915 ctx = i915_gem_alloc_object(dev, 4096);
2916 if (!ctx) {
2917 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
2918 return NULL;
2919 }
2920
2921 ret = i915_gem_obj_ggtt_pin(ctx, 4096, 0);
2922 if (ret) {
2923 DRM_ERROR("failed to pin power context: %d\n", ret);
2924 goto err_unref;
2925 }
2926
2927 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
2928 if (ret) {
2929 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
2930 goto err_unpin;
2931 }
2932
2933 return ctx;
2934
2935 err_unpin:
2936 i915_gem_object_ggtt_unpin(ctx);
2937 err_unref:
2938 drm_gem_object_unreference(&ctx->base);
2939 return NULL;
2940 }
2941
2942 /**
2943 * Lock protecting IPS related data structures
2944 */
2945 DEFINE_SPINLOCK(mchdev_lock);
2946
2947 /* Global for IPS driver to get at the current i915 device. Protected by
2948 * mchdev_lock. */
2949 static struct drm_i915_private *i915_mch_dev;
2950
2951 bool ironlake_set_drps(struct drm_device *dev, u8 val)
2952 {
2953 struct drm_i915_private *dev_priv = dev->dev_private;
2954 u16 rgvswctl;
2955
2956 assert_spin_locked(&mchdev_lock);
2957
2958 rgvswctl = I915_READ16(MEMSWCTL);
2959 if (rgvswctl & MEMCTL_CMD_STS) {
2960 DRM_DEBUG("gpu busy, RCS change rejected\n");
2961 return false; /* still busy with another command */
2962 }
2963
2964 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
2965 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
2966 I915_WRITE16(MEMSWCTL, rgvswctl);
2967 POSTING_READ16(MEMSWCTL);
2968
2969 rgvswctl |= MEMCTL_CMD_STS;
2970 I915_WRITE16(MEMSWCTL, rgvswctl);
2971
2972 return true;
2973 }
2974
2975 static void ironlake_enable_drps(struct drm_device *dev)
2976 {
2977 struct drm_i915_private *dev_priv = dev->dev_private;
2978 u32 rgvmodectl = I915_READ(MEMMODECTL);
2979 u8 fmax, fmin, fstart, vstart;
2980
2981 spin_lock_irq(&mchdev_lock);
2982
2983 /* Enable temp reporting */
2984 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
2985 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
2986
2987 /* 100ms RC evaluation intervals */
2988 I915_WRITE(RCUPEI, 100000);
2989 I915_WRITE(RCDNEI, 100000);
2990
2991 /* Set max/min thresholds to 90ms and 80ms respectively */
2992 I915_WRITE(RCBMAXAVG, 90000);
2993 I915_WRITE(RCBMINAVG, 80000);
2994
2995 I915_WRITE(MEMIHYST, 1);
2996
2997 /* Set up min, max, and cur for interrupt handling */
2998 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
2999 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
3000 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
3001 MEMMODE_FSTART_SHIFT;
3002
3003 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
3004 PXVFREQ_PX_SHIFT;
3005
3006 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
3007 dev_priv->ips.fstart = fstart;
3008
3009 dev_priv->ips.max_delay = fstart;
3010 dev_priv->ips.min_delay = fmin;
3011 dev_priv->ips.cur_delay = fstart;
3012
3013 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
3014 fmax, fmin, fstart);
3015
3016 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
3017
3018 /*
3019 * Interrupts will be enabled in ironlake_irq_postinstall
3020 */
3021
3022 I915_WRITE(VIDSTART, vstart);
3023 POSTING_READ(VIDSTART);
3024
3025 rgvmodectl |= MEMMODE_SWMODE_EN;
3026 I915_WRITE(MEMMODECTL, rgvmodectl);
3027
3028 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
3029 DRM_ERROR("stuck trying to change perf mode\n");
3030 mdelay(1);
3031
3032 ironlake_set_drps(dev, fstart);
3033
3034 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
3035 I915_READ(0x112e0);
3036 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
3037 dev_priv->ips.last_count2 = I915_READ(0x112f4);
3038 getrawmonotonic(&dev_priv->ips.last_time2);
3039
3040 spin_unlock_irq(&mchdev_lock);
3041 }
3042
3043 static void ironlake_disable_drps(struct drm_device *dev)
3044 {
3045 struct drm_i915_private *dev_priv = dev->dev_private;
3046 u16 rgvswctl;
3047
3048 spin_lock_irq(&mchdev_lock);
3049
3050 rgvswctl = I915_READ16(MEMSWCTL);
3051
3052 /* Ack interrupts, disable EFC interrupt */
3053 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
3054 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
3055 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
3056 I915_WRITE(DEIIR, DE_PCU_EVENT);
3057 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
3058
3059 /* Go back to the starting frequency */
3060 ironlake_set_drps(dev, dev_priv->ips.fstart);
3061 mdelay(1);
3062 rgvswctl |= MEMCTL_CMD_STS;
3063 I915_WRITE(MEMSWCTL, rgvswctl);
3064 mdelay(1);
3065
3066 spin_unlock_irq(&mchdev_lock);
3067 }
3068
3069 /* There's a funny hw issue where the hw returns all 0 when reading from
3070 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3071 * ourselves, instead of doing a rmw cycle (which might result in us clearing
3072 * all limits and the gpu stuck at whatever frequency it is at atm).
3073 */
3074 static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)
3075 {
3076 u32 limits;
3077
3078 /* Only set the down limit when we've reached the lowest level to avoid
3079 * getting more interrupts, otherwise leave this clear. This prevents a
3080 * race in the hw when coming out of rc6: There's a tiny window where
3081 * the hw runs at the minimal clock before selecting the desired
3082 * frequency, if the down threshold expires in that window we will not
3083 * receive a down interrupt. */
3084 limits = dev_priv->rps.max_freq_softlimit << 24;
3085 if (val <= dev_priv->rps.min_freq_softlimit)
3086 limits |= dev_priv->rps.min_freq_softlimit << 16;
3087
3088 return limits;
3089 }
3090
3091 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
3092 {
3093 int new_power;
3094
3095 new_power = dev_priv->rps.power;
3096 switch (dev_priv->rps.power) {
3097 case LOW_POWER:
3098 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
3099 new_power = BETWEEN;
3100 break;
3101
3102 case BETWEEN:
3103 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
3104 new_power = LOW_POWER;
3105 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
3106 new_power = HIGH_POWER;
3107 break;
3108
3109 case HIGH_POWER:
3110 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
3111 new_power = BETWEEN;
3112 break;
3113 }
3114 /* Max/min bins are special */
3115 if (val == dev_priv->rps.min_freq_softlimit)
3116 new_power = LOW_POWER;
3117 if (val == dev_priv->rps.max_freq_softlimit)
3118 new_power = HIGH_POWER;
3119 if (new_power == dev_priv->rps.power)
3120 return;
3121
3122 /* Note the units here are not exactly 1us, but 1280ns. */
3123 switch (new_power) {
3124 case LOW_POWER:
3125 /* Upclock if more than 95% busy over 16ms */
3126 I915_WRITE(GEN6_RP_UP_EI, 12500);
3127 I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800);
3128
3129 /* Downclock if less than 85% busy over 32ms */
3130 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3131 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250);
3132
3133 I915_WRITE(GEN6_RP_CONTROL,
3134 GEN6_RP_MEDIA_TURBO |
3135 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3136 GEN6_RP_MEDIA_IS_GFX |
3137 GEN6_RP_ENABLE |
3138 GEN6_RP_UP_BUSY_AVG |
3139 GEN6_RP_DOWN_IDLE_AVG);
3140 break;
3141
3142 case BETWEEN:
3143 /* Upclock if more than 90% busy over 13ms */
3144 I915_WRITE(GEN6_RP_UP_EI, 10250);
3145 I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225);
3146
3147 /* Downclock if less than 75% busy over 32ms */
3148 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3149 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750);
3150
3151 I915_WRITE(GEN6_RP_CONTROL,
3152 GEN6_RP_MEDIA_TURBO |
3153 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3154 GEN6_RP_MEDIA_IS_GFX |
3155 GEN6_RP_ENABLE |
3156 GEN6_RP_UP_BUSY_AVG |
3157 GEN6_RP_DOWN_IDLE_AVG);
3158 break;
3159
3160 case HIGH_POWER:
3161 /* Upclock if more than 85% busy over 10ms */
3162 I915_WRITE(GEN6_RP_UP_EI, 8000);
3163 I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800);
3164
3165 /* Downclock if less than 60% busy over 32ms */
3166 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3167 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000);
3168
3169 I915_WRITE(GEN6_RP_CONTROL,
3170 GEN6_RP_MEDIA_TURBO |
3171 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3172 GEN6_RP_MEDIA_IS_GFX |
3173 GEN6_RP_ENABLE |
3174 GEN6_RP_UP_BUSY_AVG |
3175 GEN6_RP_DOWN_IDLE_AVG);
3176 break;
3177 }
3178
3179 dev_priv->rps.power = new_power;
3180 dev_priv->rps.last_adj = 0;
3181 }
3182
3183 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
3184 {
3185 u32 mask = 0;
3186
3187 if (val > dev_priv->rps.min_freq_softlimit)
3188 mask |= GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
3189 if (val < dev_priv->rps.max_freq_softlimit)
3190 mask |= GEN6_PM_RP_UP_THRESHOLD;
3191
3192 mask |= dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED);
3193 mask &= dev_priv->pm_rps_events;
3194
3195 /* IVB and SNB hard hangs on looping batchbuffer
3196 * if GEN6_PM_UP_EI_EXPIRED is masked.
3197 */
3198 if (INTEL_INFO(dev_priv->dev)->gen <= 7 && !IS_HASWELL(dev_priv->dev))
3199 mask |= GEN6_PM_RP_UP_EI_EXPIRED;
3200
3201 if (IS_GEN8(dev_priv->dev))
3202 mask |= GEN8_PMINTR_REDIRECT_TO_NON_DISP;
3203
3204 return ~mask;
3205 }
3206
3207 /* gen6_set_rps is called to update the frequency request, but should also be
3208 * called when the range (min_delay and max_delay) is modified so that we can
3209 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
3210 void gen6_set_rps(struct drm_device *dev, u8 val)
3211 {
3212 struct drm_i915_private *dev_priv = dev->dev_private;
3213
3214 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3215 WARN_ON(val > dev_priv->rps.max_freq_softlimit);
3216 WARN_ON(val < dev_priv->rps.min_freq_softlimit);
3217
3218 /* min/max delay may still have been modified so be sure to
3219 * write the limits value.
3220 */
3221 if (val != dev_priv->rps.cur_freq) {
3222 gen6_set_rps_thresholds(dev_priv, val);
3223
3224 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3225 I915_WRITE(GEN6_RPNSWREQ,
3226 HSW_FREQUENCY(val));
3227 else
3228 I915_WRITE(GEN6_RPNSWREQ,
3229 GEN6_FREQUENCY(val) |
3230 GEN6_OFFSET(0) |
3231 GEN6_AGGRESSIVE_TURBO);
3232 }
3233
3234 /* Make sure we continue to get interrupts
3235 * until we hit the minimum or maximum frequencies.
3236 */
3237 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, gen6_rps_limits(dev_priv, val));
3238 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
3239
3240 POSTING_READ(GEN6_RPNSWREQ);
3241
3242 dev_priv->rps.cur_freq = val;
3243 trace_intel_gpu_freq_change(val * 50);
3244 }
3245
3246 /* vlv_set_rps_idle: Set the frequency to Rpn if Gfx clocks are down
3247 *
3248 * * If Gfx is Idle, then
3249 * 1. Mask Turbo interrupts
3250 * 2. Bring up Gfx clock
3251 * 3. Change the freq to Rpn and wait till P-Unit updates freq
3252 * 4. Clear the Force GFX CLK ON bit so that Gfx can down
3253 * 5. Unmask Turbo interrupts
3254 */
3255 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
3256 {
3257 struct drm_device *dev = dev_priv->dev;
3258
3259 /* Latest VLV doesn't need to force the gfx clock */
3260 if (dev->pdev->revision >= 0xd) {
3261 valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3262 return;
3263 }
3264
3265 /*
3266 * When we are idle. Drop to min voltage state.
3267 */
3268
3269 if (dev_priv->rps.cur_freq <= dev_priv->rps.min_freq_softlimit)
3270 return;
3271
3272 /* Mask turbo interrupt so that they will not come in between */
3273 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3274
3275 vlv_force_gfx_clock(dev_priv, true);
3276
3277 dev_priv->rps.cur_freq = dev_priv->rps.min_freq_softlimit;
3278
3279 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ,
3280 dev_priv->rps.min_freq_softlimit);
3281
3282 if (wait_for(((vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS))
3283 & GENFREQSTATUS) == 0, 5))
3284 DRM_ERROR("timed out waiting for Punit\n");
3285
3286 vlv_force_gfx_clock(dev_priv, false);
3287
3288 I915_WRITE(GEN6_PMINTRMSK,
3289 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
3290 }
3291
3292 void gen6_rps_idle(struct drm_i915_private *dev_priv)
3293 {
3294 struct drm_device *dev = dev_priv->dev;
3295
3296 mutex_lock(&dev_priv->rps.hw_lock);
3297 if (dev_priv->rps.enabled) {
3298 if (IS_CHERRYVIEW(dev))
3299 valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3300 else if (IS_VALLEYVIEW(dev))
3301 vlv_set_rps_idle(dev_priv);
3302 else
3303 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3304 dev_priv->rps.last_adj = 0;
3305 }
3306 mutex_unlock(&dev_priv->rps.hw_lock);
3307 }
3308
3309 void gen6_rps_boost(struct drm_i915_private *dev_priv)
3310 {
3311 struct drm_device *dev = dev_priv->dev;
3312
3313 mutex_lock(&dev_priv->rps.hw_lock);
3314 if (dev_priv->rps.enabled) {
3315 if (IS_VALLEYVIEW(dev))
3316 valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
3317 else
3318 gen6_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
3319 dev_priv->rps.last_adj = 0;
3320 }
3321 mutex_unlock(&dev_priv->rps.hw_lock);
3322 }
3323
3324 void valleyview_set_rps(struct drm_device *dev, u8 val)
3325 {
3326 struct drm_i915_private *dev_priv = dev->dev_private;
3327
3328 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3329 WARN_ON(val > dev_priv->rps.max_freq_softlimit);
3330 WARN_ON(val < dev_priv->rps.min_freq_softlimit);
3331
3332 DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
3333 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
3334 dev_priv->rps.cur_freq,
3335 vlv_gpu_freq(dev_priv, val), val);
3336
3337 if (val != dev_priv->rps.cur_freq)
3338 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
3339
3340 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
3341
3342 dev_priv->rps.cur_freq = val;
3343 trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val));
3344 }
3345
3346 static void gen8_disable_rps_interrupts(struct drm_device *dev)
3347 {
3348 struct drm_i915_private *dev_priv = dev->dev_private;
3349
3350 I915_WRITE(GEN6_PMINTRMSK, ~GEN8_PMINTR_REDIRECT_TO_NON_DISP);
3351 I915_WRITE(GEN8_GT_IER(2), I915_READ(GEN8_GT_IER(2)) &
3352 ~dev_priv->pm_rps_events);
3353 /* Complete PM interrupt masking here doesn't race with the rps work
3354 * item again unmasking PM interrupts because that is using a different
3355 * register (GEN8_GT_IMR(2)) to mask PM interrupts. The only risk is in
3356 * leaving stale bits in GEN8_GT_IIR(2) and GEN8_GT_IMR(2) which
3357 * gen8_enable_rps will clean up. */
3358
3359 spin_lock_irq(&dev_priv->irq_lock);
3360 dev_priv->rps.pm_iir = 0;
3361 spin_unlock_irq(&dev_priv->irq_lock);
3362
3363 I915_WRITE(GEN8_GT_IIR(2), dev_priv->pm_rps_events);
3364 }
3365
3366 static void gen6_disable_rps_interrupts(struct drm_device *dev)
3367 {
3368 struct drm_i915_private *dev_priv = dev->dev_private;
3369
3370 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3371 I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) &
3372 ~dev_priv->pm_rps_events);
3373 /* Complete PM interrupt masking here doesn't race with the rps work
3374 * item again unmasking PM interrupts because that is using a different
3375 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3376 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3377
3378 spin_lock_irq(&dev_priv->irq_lock);
3379 dev_priv->rps.pm_iir = 0;
3380 spin_unlock_irq(&dev_priv->irq_lock);
3381
3382 I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events);
3383 }
3384
3385 static void gen6_disable_rps(struct drm_device *dev)
3386 {
3387 struct drm_i915_private *dev_priv = dev->dev_private;
3388
3389 I915_WRITE(GEN6_RC_CONTROL, 0);
3390 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
3391
3392 if (IS_BROADWELL(dev))
3393 gen8_disable_rps_interrupts(dev);
3394 else
3395 gen6_disable_rps_interrupts(dev);
3396 }
3397
3398 static void cherryview_disable_rps(struct drm_device *dev)
3399 {
3400 struct drm_i915_private *dev_priv = dev->dev_private;
3401
3402 I915_WRITE(GEN6_RC_CONTROL, 0);
3403
3404 gen8_disable_rps_interrupts(dev);
3405 }
3406
3407 static void valleyview_disable_rps(struct drm_device *dev)
3408 {
3409 struct drm_i915_private *dev_priv = dev->dev_private;
3410
3411 I915_WRITE(GEN6_RC_CONTROL, 0);
3412
3413 gen6_disable_rps_interrupts(dev);
3414 }
3415
3416 static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
3417 {
3418 if (IS_VALLEYVIEW(dev)) {
3419 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
3420 mode = GEN6_RC_CTL_RC6_ENABLE;
3421 else
3422 mode = 0;
3423 }
3424 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
3425 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3426 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3427 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
3428 }
3429
3430 static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
3431 {
3432 /* No RC6 before Ironlake */
3433 if (INTEL_INFO(dev)->gen < 5)
3434 return 0;
3435
3436 /* RC6 is only on Ironlake mobile not on desktop */
3437 if (INTEL_INFO(dev)->gen == 5 && !IS_IRONLAKE_M(dev))
3438 return 0;
3439
3440 /* Respect the kernel parameter if it is set */
3441 if (enable_rc6 >= 0) {
3442 int mask;
3443
3444 if (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
3445 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
3446 INTEL_RC6pp_ENABLE;
3447 else
3448 mask = INTEL_RC6_ENABLE;
3449
3450 if ((enable_rc6 & mask) != enable_rc6)
3451 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
3452 enable_rc6 & mask, enable_rc6, mask);
3453
3454 return enable_rc6 & mask;
3455 }
3456
3457 /* Disable RC6 on Ironlake */
3458 if (INTEL_INFO(dev)->gen == 5)
3459 return 0;
3460
3461 if (IS_IVYBRIDGE(dev))
3462 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
3463
3464 return INTEL_RC6_ENABLE;
3465 }
3466
3467 int intel_enable_rc6(const struct drm_device *dev)
3468 {
3469 return i915.enable_rc6;
3470 }
3471
3472 static void gen8_enable_rps_interrupts(struct drm_device *dev)
3473 {
3474 struct drm_i915_private *dev_priv = dev->dev_private;
3475
3476 spin_lock_irq(&dev_priv->irq_lock);
3477 WARN_ON(dev_priv->rps.pm_iir);
3478 gen8_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
3479 I915_WRITE(GEN8_GT_IIR(2), dev_priv->pm_rps_events);
3480 spin_unlock_irq(&dev_priv->irq_lock);
3481 }
3482
3483 static void gen6_enable_rps_interrupts(struct drm_device *dev)
3484 {
3485 struct drm_i915_private *dev_priv = dev->dev_private;
3486
3487 spin_lock_irq(&dev_priv->irq_lock);
3488 WARN_ON(dev_priv->rps.pm_iir);
3489 gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
3490 I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events);
3491 spin_unlock_irq(&dev_priv->irq_lock);
3492 }
3493
3494 static void parse_rp_state_cap(struct drm_i915_private *dev_priv, u32 rp_state_cap)
3495 {
3496 /* All of these values are in units of 50MHz */
3497 dev_priv->rps.cur_freq = 0;
3498 /* static values from HW: RP0 < RPe < RP1 < RPn (min_freq) */
3499 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
3500 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
3501 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
3502 /* XXX: only BYT has a special efficient freq */
3503 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
3504 /* hw_max = RP0 until we check for overclocking */
3505 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
3506
3507 /* Preserve min/max settings in case of re-init */
3508 if (dev_priv->rps.max_freq_softlimit == 0)
3509 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
3510
3511 if (dev_priv->rps.min_freq_softlimit == 0)
3512 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
3513 }
3514
3515 static void gen8_enable_rps(struct drm_device *dev)
3516 {
3517 struct drm_i915_private *dev_priv = dev->dev_private;
3518 struct intel_engine_cs *ring;
3519 uint32_t rc6_mask = 0, rp_state_cap;
3520 int unused;
3521
3522 /* 1a: Software RC state - RC0 */
3523 I915_WRITE(GEN6_RC_STATE, 0);
3524
3525 /* 1c & 1d: Get forcewake during program sequence. Although the driver
3526 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
3527 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3528
3529 /* 2a: Disable RC states. */
3530 I915_WRITE(GEN6_RC_CONTROL, 0);
3531
3532 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3533 parse_rp_state_cap(dev_priv, rp_state_cap);
3534
3535 /* 2b: Program RC6 thresholds.*/
3536 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
3537 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
3538 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
3539 for_each_ring(ring, dev_priv, unused)
3540 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3541 I915_WRITE(GEN6_RC_SLEEP, 0);
3542 if (IS_BROADWELL(dev))
3543 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
3544 else
3545 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
3546
3547 /* 3: Enable RC6 */
3548 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
3549 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
3550 intel_print_rc6_info(dev, rc6_mask);
3551 if (IS_BROADWELL(dev))
3552 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
3553 GEN7_RC_CTL_TO_MODE |
3554 rc6_mask);
3555 else
3556 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
3557 GEN6_RC_CTL_EI_MODE(1) |
3558 rc6_mask);
3559
3560 /* 4 Program defaults and thresholds for RPS*/
3561 I915_WRITE(GEN6_RPNSWREQ,
3562 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
3563 I915_WRITE(GEN6_RC_VIDEO_FREQ,
3564 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
3565 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
3566 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
3567
3568 /* Docs recommend 900MHz, and 300 MHz respectively */
3569 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
3570 dev_priv->rps.max_freq_softlimit << 24 |
3571 dev_priv->rps.min_freq_softlimit << 16);
3572
3573 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
3574 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
3575 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
3576 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
3577
3578 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3579
3580 /* 5: Enable RPS */
3581 I915_WRITE(GEN6_RP_CONTROL,
3582 GEN6_RP_MEDIA_TURBO |
3583 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3584 GEN6_RP_MEDIA_IS_GFX |
3585 GEN6_RP_ENABLE |
3586 GEN6_RP_UP_BUSY_AVG |
3587 GEN6_RP_DOWN_IDLE_AVG);
3588
3589 /* 6: Ring frequency + overclocking (our driver does this later */
3590
3591 gen6_set_rps(dev, (I915_READ(GEN6_GT_PERF_STATUS) & 0xff00) >> 8);
3592
3593 gen8_enable_rps_interrupts(dev);
3594
3595 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3596 }
3597
3598 static void gen6_enable_rps(struct drm_device *dev)
3599 {
3600 struct drm_i915_private *dev_priv = dev->dev_private;
3601 struct intel_engine_cs *ring;
3602 u32 rp_state_cap;
3603 u32 gt_perf_status;
3604 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
3605 u32 gtfifodbg;
3606 int rc6_mode;
3607 int i, ret;
3608
3609 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3610
3611 /* Here begins a magic sequence of register writes to enable
3612 * auto-downclocking.
3613 *
3614 * Perhaps there might be some value in exposing these to
3615 * userspace...
3616 */
3617 I915_WRITE(GEN6_RC_STATE, 0);
3618
3619 /* Clear the DBG now so we don't confuse earlier errors */
3620 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3621 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3622 I915_WRITE(GTFIFODBG, gtfifodbg);
3623 }
3624
3625 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3626
3627 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3628 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
3629
3630 parse_rp_state_cap(dev_priv, rp_state_cap);
3631
3632 /* disable the counters and set deterministic thresholds */
3633 I915_WRITE(GEN6_RC_CONTROL, 0);
3634
3635 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
3636 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
3637 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
3638 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3639 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3640
3641 for_each_ring(ring, dev_priv, i)
3642 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3643
3644 I915_WRITE(GEN6_RC_SLEEP, 0);
3645 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
3646 if (IS_IVYBRIDGE(dev))
3647 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
3648 else
3649 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
3650 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
3651 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
3652
3653 /* Check if we are enabling RC6 */
3654 rc6_mode = intel_enable_rc6(dev_priv->dev);
3655 if (rc6_mode & INTEL_RC6_ENABLE)
3656 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
3657
3658 /* We don't use those on Haswell */
3659 if (!IS_HASWELL(dev)) {
3660 if (rc6_mode & INTEL_RC6p_ENABLE)
3661 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
3662
3663 if (rc6_mode & INTEL_RC6pp_ENABLE)
3664 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
3665 }
3666
3667 intel_print_rc6_info(dev, rc6_mask);
3668
3669 I915_WRITE(GEN6_RC_CONTROL,
3670 rc6_mask |
3671 GEN6_RC_CTL_EI_MODE(1) |
3672 GEN6_RC_CTL_HW_ENABLE);
3673
3674 /* Power down if completely idle for over 50ms */
3675 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
3676 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3677
3678 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
3679 if (ret)
3680 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
3681
3682 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
3683 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
3684 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
3685 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
3686 (pcu_mbox & 0xff) * 50);
3687 dev_priv->rps.max_freq = pcu_mbox & 0xff;
3688 }
3689
3690 dev_priv->rps.power = HIGH_POWER; /* force a reset */
3691 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3692
3693 gen6_enable_rps_interrupts(dev);
3694
3695 rc6vids = 0;
3696 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
3697 if (IS_GEN6(dev) && ret) {
3698 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
3699 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
3700 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
3701 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
3702 rc6vids &= 0xffff00;
3703 rc6vids |= GEN6_ENCODE_RC6_VID(450);
3704 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
3705 if (ret)
3706 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
3707 }
3708
3709 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3710 }
3711
3712 static void __gen6_update_ring_freq(struct drm_device *dev)
3713 {
3714 struct drm_i915_private *dev_priv = dev->dev_private;
3715 int min_freq = 15;
3716 unsigned int gpu_freq;
3717 unsigned int max_ia_freq, min_ring_freq;
3718 int scaling_factor = 180;
3719 struct cpufreq_policy *policy;
3720
3721 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3722
3723 policy = cpufreq_cpu_get(0);
3724 if (policy) {
3725 max_ia_freq = policy->cpuinfo.max_freq;
3726 cpufreq_cpu_put(policy);
3727 } else {
3728 /*
3729 * Default to measured freq if none found, PCU will ensure we
3730 * don't go over
3731 */
3732 max_ia_freq = tsc_khz;
3733 }
3734
3735 /* Convert from kHz to MHz */
3736 max_ia_freq /= 1000;
3737
3738 min_ring_freq = I915_READ(DCLK) & 0xf;
3739 /* convert DDR frequency from units of 266.6MHz to bandwidth */
3740 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3741
3742 /*
3743 * For each potential GPU frequency, load a ring frequency we'd like
3744 * to use for memory access. We do this by specifying the IA frequency
3745 * the PCU should use as a reference to determine the ring frequency.
3746 */
3747 for (gpu_freq = dev_priv->rps.max_freq_softlimit; gpu_freq >= dev_priv->rps.min_freq_softlimit;
3748 gpu_freq--) {
3749 int diff = dev_priv->rps.max_freq_softlimit - gpu_freq;
3750 unsigned int ia_freq = 0, ring_freq = 0;
3751
3752 if (INTEL_INFO(dev)->gen >= 8) {
3753 /* max(2 * GT, DDR). NB: GT is 50MHz units */
3754 ring_freq = max(min_ring_freq, gpu_freq);
3755 } else if (IS_HASWELL(dev)) {
3756 ring_freq = mult_frac(gpu_freq, 5, 4);
3757 ring_freq = max(min_ring_freq, ring_freq);
3758 /* leave ia_freq as the default, chosen by cpufreq */
3759 } else {
3760 /* On older processors, there is no separate ring
3761 * clock domain, so in order to boost the bandwidth
3762 * of the ring, we need to upclock the CPU (ia_freq).
3763 *
3764 * For GPU frequencies less than 750MHz,
3765 * just use the lowest ring freq.
3766 */
3767 if (gpu_freq < min_freq)
3768 ia_freq = 800;
3769 else
3770 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
3771 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
3772 }
3773
3774 sandybridge_pcode_write(dev_priv,
3775 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3776 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
3777 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
3778 gpu_freq);
3779 }
3780 }
3781
3782 void gen6_update_ring_freq(struct drm_device *dev)
3783 {
3784 struct drm_i915_private *dev_priv = dev->dev_private;
3785
3786 if (INTEL_INFO(dev)->gen < 6 || IS_VALLEYVIEW(dev))
3787 return;
3788
3789 mutex_lock(&dev_priv->rps.hw_lock);
3790 __gen6_update_ring_freq(dev);
3791 mutex_unlock(&dev_priv->rps.hw_lock);
3792 }
3793
3794 static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
3795 {
3796 u32 val, rp0;
3797
3798 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
3799 rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & PUNIT_GPU_STATUS_MAX_FREQ_MASK;
3800
3801 return rp0;
3802 }
3803
3804 static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
3805 {
3806 u32 val, rpe;
3807
3808 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
3809 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
3810
3811 return rpe;
3812 }
3813
3814 static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
3815 {
3816 u32 val, rp1;
3817
3818 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
3819 rp1 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & PUNIT_GPU_STATUS_MAX_FREQ_MASK;
3820
3821 return rp1;
3822 }
3823
3824 static int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
3825 {
3826 u32 val, rpn;
3827
3828 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
3829 rpn = (val >> PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT) & PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK;
3830 return rpn;
3831 }
3832
3833 static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
3834 {
3835 u32 val, rp1;
3836
3837 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
3838
3839 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
3840
3841 return rp1;
3842 }
3843
3844 static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
3845 {
3846 u32 val, rp0;
3847
3848 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
3849
3850 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
3851 /* Clamp to max */
3852 rp0 = min_t(u32, rp0, 0xea);
3853
3854 return rp0;
3855 }
3856
3857 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
3858 {
3859 u32 val, rpe;
3860
3861 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
3862 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
3863 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
3864 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
3865
3866 return rpe;
3867 }
3868
3869 static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
3870 {
3871 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
3872 }
3873
3874 /* Check that the pctx buffer wasn't move under us. */
3875 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
3876 {
3877 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
3878
3879 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
3880 dev_priv->vlv_pctx->stolen->start);
3881 }
3882
3883
3884 /* Check that the pcbr address is not empty. */
3885 static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
3886 {
3887 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
3888
3889 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
3890 }
3891
3892 static void cherryview_setup_pctx(struct drm_device *dev)
3893 {
3894 struct drm_i915_private *dev_priv = dev->dev_private;
3895 unsigned long pctx_paddr, paddr;
3896 struct i915_gtt *gtt = &dev_priv->gtt;
3897 u32 pcbr;
3898 int pctx_size = 32*1024;
3899
3900 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3901
3902 pcbr = I915_READ(VLV_PCBR);
3903 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
3904 paddr = (dev_priv->mm.stolen_base +
3905 (gtt->stolen_size - pctx_size));
3906
3907 pctx_paddr = (paddr & (~4095));
3908 I915_WRITE(VLV_PCBR, pctx_paddr);
3909 }
3910 }
3911
3912 static void valleyview_setup_pctx(struct drm_device *dev)
3913 {
3914 struct drm_i915_private *dev_priv = dev->dev_private;
3915 struct drm_i915_gem_object *pctx;
3916 unsigned long pctx_paddr;
3917 u32 pcbr;
3918 int pctx_size = 24*1024;
3919
3920 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3921
3922 pcbr = I915_READ(VLV_PCBR);
3923 if (pcbr) {
3924 /* BIOS set it up already, grab the pre-alloc'd space */
3925 int pcbr_offset;
3926
3927 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
3928 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
3929 pcbr_offset,
3930 I915_GTT_OFFSET_NONE,
3931 pctx_size);
3932 goto out;
3933 }
3934
3935 /*
3936 * From the Gunit register HAS:
3937 * The Gfx driver is expected to program this register and ensure
3938 * proper allocation within Gfx stolen memory. For example, this
3939 * register should be programmed such than the PCBR range does not
3940 * overlap with other ranges, such as the frame buffer, protected
3941 * memory, or any other relevant ranges.
3942 */
3943 pctx = i915_gem_object_create_stolen(dev, pctx_size);
3944 if (!pctx) {
3945 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
3946 return;
3947 }
3948
3949 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
3950 I915_WRITE(VLV_PCBR, pctx_paddr);
3951
3952 out:
3953 dev_priv->vlv_pctx = pctx;
3954 }
3955
3956 static void valleyview_cleanup_pctx(struct drm_device *dev)
3957 {
3958 struct drm_i915_private *dev_priv = dev->dev_private;
3959
3960 if (WARN_ON(!dev_priv->vlv_pctx))
3961 return;
3962
3963 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
3964 dev_priv->vlv_pctx = NULL;
3965 }
3966
3967 static void valleyview_init_gt_powersave(struct drm_device *dev)
3968 {
3969 struct drm_i915_private *dev_priv = dev->dev_private;
3970
3971 valleyview_setup_pctx(dev);
3972
3973 mutex_lock(&dev_priv->rps.hw_lock);
3974
3975 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
3976 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
3977 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
3978 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
3979 dev_priv->rps.max_freq);
3980
3981 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
3982 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
3983 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
3984 dev_priv->rps.efficient_freq);
3985
3986 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
3987 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
3988 vlv_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
3989 dev_priv->rps.rp1_freq);
3990
3991 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
3992 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
3993 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
3994 dev_priv->rps.min_freq);
3995
3996 /* Preserve min/max settings in case of re-init */
3997 if (dev_priv->rps.max_freq_softlimit == 0)
3998 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
3999
4000 if (dev_priv->rps.min_freq_softlimit == 0)
4001 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
4002
4003 mutex_unlock(&dev_priv->rps.hw_lock);
4004 }
4005
4006 static void cherryview_init_gt_powersave(struct drm_device *dev)
4007 {
4008 struct drm_i915_private *dev_priv = dev->dev_private;
4009
4010 cherryview_setup_pctx(dev);
4011
4012 mutex_lock(&dev_priv->rps.hw_lock);
4013
4014 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
4015 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
4016 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
4017 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4018 dev_priv->rps.max_freq);
4019
4020 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
4021 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
4022 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4023 dev_priv->rps.efficient_freq);
4024
4025 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
4026 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
4027 vlv_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
4028 dev_priv->rps.rp1_freq);
4029
4030 dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv);
4031 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
4032 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4033 dev_priv->rps.min_freq);
4034
4035 /* Preserve min/max settings in case of re-init */
4036 if (dev_priv->rps.max_freq_softlimit == 0)
4037 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4038
4039 if (dev_priv->rps.min_freq_softlimit == 0)
4040 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
4041
4042 mutex_unlock(&dev_priv->rps.hw_lock);
4043 }
4044
4045 static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
4046 {
4047 valleyview_cleanup_pctx(dev);
4048 }
4049
4050 static void cherryview_enable_rps(struct drm_device *dev)
4051 {
4052 struct drm_i915_private *dev_priv = dev->dev_private;
4053 struct intel_engine_cs *ring;
4054 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
4055 int i;
4056
4057 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4058
4059 gtfifodbg = I915_READ(GTFIFODBG);
4060 if (gtfifodbg) {
4061 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4062 gtfifodbg);
4063 I915_WRITE(GTFIFODBG, gtfifodbg);
4064 }
4065
4066 cherryview_check_pctx(dev_priv);
4067
4068 /* 1a & 1b: Get forcewake during program sequence. Although the driver
4069 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4070 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
4071
4072 /* 2a: Program RC6 thresholds.*/
4073 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4074 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4075 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4076
4077 for_each_ring(ring, dev_priv, i)
4078 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4079 I915_WRITE(GEN6_RC_SLEEP, 0);
4080
4081 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
4082
4083 /* allows RC6 residency counter to work */
4084 I915_WRITE(VLV_COUNTER_CONTROL,
4085 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
4086 VLV_MEDIA_RC6_COUNT_EN |
4087 VLV_RENDER_RC6_COUNT_EN));
4088
4089 /* For now we assume BIOS is allocating and populating the PCBR */
4090 pcbr = I915_READ(VLV_PCBR);
4091
4092 DRM_DEBUG_DRIVER("PCBR offset : 0x%x\n", pcbr);
4093
4094 /* 3: Enable RC6 */
4095 if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
4096 (pcbr >> VLV_PCBR_ADDR_SHIFT))
4097 rc6_mode = GEN6_RC_CTL_EI_MODE(1);
4098
4099 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
4100
4101 /* 4 Program defaults and thresholds for RPS*/
4102 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
4103 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
4104 I915_WRITE(GEN6_RP_UP_EI, 66000);
4105 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
4106
4107 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4108
4109 /* WaDisablePwrmtrEvent:chv (pre-production hw) */
4110 I915_WRITE(0xA80C, I915_READ(0xA80C) & 0x00ffffff);
4111 I915_WRITE(0xA810, I915_READ(0xA810) & 0xffffff00);
4112
4113 /* 5: Enable RPS */
4114 I915_WRITE(GEN6_RP_CONTROL,
4115 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4116 GEN6_RP_MEDIA_IS_GFX | /* WaSetMaskForGfxBusyness:chv (pre-production hw ?) */
4117 GEN6_RP_ENABLE |
4118 GEN6_RP_UP_BUSY_AVG |
4119 GEN6_RP_DOWN_IDLE_AVG);
4120
4121 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4122
4123 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
4124 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
4125
4126 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
4127 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
4128 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
4129 dev_priv->rps.cur_freq);
4130
4131 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
4132 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4133 dev_priv->rps.efficient_freq);
4134
4135 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
4136
4137 gen8_enable_rps_interrupts(dev);
4138
4139 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
4140 }
4141
4142 static void valleyview_enable_rps(struct drm_device *dev)
4143 {
4144 struct drm_i915_private *dev_priv = dev->dev_private;
4145 struct intel_engine_cs *ring;
4146 u32 gtfifodbg, val, rc6_mode = 0;
4147 int i;
4148
4149 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4150
4151 valleyview_check_pctx(dev_priv);
4152
4153 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
4154 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4155 gtfifodbg);
4156 I915_WRITE(GTFIFODBG, gtfifodbg);
4157 }
4158
4159 /* If VLV, Forcewake all wells, else re-direct to regular path */
4160 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
4161
4162 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
4163 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
4164 I915_WRITE(GEN6_RP_UP_EI, 66000);
4165 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
4166
4167 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4168 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 0xf4240);
4169
4170 I915_WRITE(GEN6_RP_CONTROL,
4171 GEN6_RP_MEDIA_TURBO |
4172 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4173 GEN6_RP_MEDIA_IS_GFX |
4174 GEN6_RP_ENABLE |
4175 GEN6_RP_UP_BUSY_AVG |
4176 GEN6_RP_DOWN_IDLE_CONT);
4177
4178 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
4179 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4180 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4181
4182 for_each_ring(ring, dev_priv, i)
4183 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4184
4185 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
4186
4187 /* allows RC6 residency counter to work */
4188 I915_WRITE(VLV_COUNTER_CONTROL,
4189 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
4190 VLV_RENDER_RC0_COUNT_EN |
4191 VLV_MEDIA_RC6_COUNT_EN |
4192 VLV_RENDER_RC6_COUNT_EN));
4193
4194 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4195 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
4196
4197 intel_print_rc6_info(dev, rc6_mode);
4198
4199 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
4200
4201 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4202
4203 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
4204 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
4205
4206 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
4207 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
4208 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
4209 dev_priv->rps.cur_freq);
4210
4211 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
4212 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4213 dev_priv->rps.efficient_freq);
4214
4215 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
4216
4217 gen6_enable_rps_interrupts(dev);
4218
4219 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
4220 }
4221
4222 void ironlake_teardown_rc6(struct drm_device *dev)
4223 {
4224 struct drm_i915_private *dev_priv = dev->dev_private;
4225
4226 if (dev_priv->ips.renderctx) {
4227 i915_gem_object_ggtt_unpin(dev_priv->ips.renderctx);
4228 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
4229 dev_priv->ips.renderctx = NULL;
4230 }
4231
4232 if (dev_priv->ips.pwrctx) {
4233 i915_gem_object_ggtt_unpin(dev_priv->ips.pwrctx);
4234 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
4235 dev_priv->ips.pwrctx = NULL;
4236 }
4237 }
4238
4239 static void ironlake_disable_rc6(struct drm_device *dev)
4240 {
4241 struct drm_i915_private *dev_priv = dev->dev_private;
4242
4243 if (I915_READ(PWRCTXA)) {
4244 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
4245 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
4246 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
4247 50);
4248
4249 I915_WRITE(PWRCTXA, 0);
4250 POSTING_READ(PWRCTXA);
4251
4252 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
4253 POSTING_READ(RSTDBYCTL);
4254 }
4255 }
4256
4257 static int ironlake_setup_rc6(struct drm_device *dev)
4258 {
4259 struct drm_i915_private *dev_priv = dev->dev_private;
4260
4261 if (dev_priv->ips.renderctx == NULL)
4262 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
4263 if (!dev_priv->ips.renderctx)
4264 return -ENOMEM;
4265
4266 if (dev_priv->ips.pwrctx == NULL)
4267 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
4268 if (!dev_priv->ips.pwrctx) {
4269 ironlake_teardown_rc6(dev);
4270 return -ENOMEM;
4271 }
4272
4273 return 0;
4274 }
4275
4276 static void ironlake_enable_rc6(struct drm_device *dev)
4277 {
4278 struct drm_i915_private *dev_priv = dev->dev_private;
4279 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
4280 bool was_interruptible;
4281 int ret;
4282
4283 /* rc6 disabled by default due to repeated reports of hanging during
4284 * boot and resume.
4285 */
4286 if (!intel_enable_rc6(dev))
4287 return;
4288
4289 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4290
4291 ret = ironlake_setup_rc6(dev);
4292 if (ret)
4293 return;
4294
4295 was_interruptible = dev_priv->mm.interruptible;
4296 dev_priv->mm.interruptible = false;
4297
4298 /*
4299 * GPU can automatically power down the render unit if given a page
4300 * to save state.
4301 */
4302 ret = intel_ring_begin(ring, 6);
4303 if (ret) {
4304 ironlake_teardown_rc6(dev);
4305 dev_priv->mm.interruptible = was_interruptible;
4306 return;
4307 }
4308
4309 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
4310 intel_ring_emit(ring, MI_SET_CONTEXT);
4311 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) |
4312 MI_MM_SPACE_GTT |
4313 MI_SAVE_EXT_STATE_EN |
4314 MI_RESTORE_EXT_STATE_EN |
4315 MI_RESTORE_INHIBIT);
4316 intel_ring_emit(ring, MI_SUSPEND_FLUSH);
4317 intel_ring_emit(ring, MI_NOOP);
4318 intel_ring_emit(ring, MI_FLUSH);
4319 intel_ring_advance(ring);
4320
4321 /*
4322 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
4323 * does an implicit flush, combined with MI_FLUSH above, it should be
4324 * safe to assume that renderctx is valid
4325 */
4326 ret = intel_ring_idle(ring);
4327 dev_priv->mm.interruptible = was_interruptible;
4328 if (ret) {
4329 DRM_ERROR("failed to enable ironlake power savings\n");
4330 ironlake_teardown_rc6(dev);
4331 return;
4332 }
4333
4334 I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN);
4335 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
4336
4337 intel_print_rc6_info(dev, GEN6_RC_CTL_RC6_ENABLE);
4338 }
4339
4340 static unsigned long intel_pxfreq(u32 vidfreq)
4341 {
4342 unsigned long freq;
4343 int div = (vidfreq & 0x3f0000) >> 16;
4344 int post = (vidfreq & 0x3000) >> 12;
4345 int pre = (vidfreq & 0x7);
4346
4347 if (!pre)
4348 return 0;
4349
4350 freq = ((div * 133333) / ((1<<post) * pre));
4351
4352 return freq;
4353 }
4354
4355 static const struct cparams {
4356 u16 i;
4357 u16 t;
4358 u16 m;
4359 u16 c;
4360 } cparams[] = {
4361 { 1, 1333, 301, 28664 },
4362 { 1, 1066, 294, 24460 },
4363 { 1, 800, 294, 25192 },
4364 { 0, 1333, 276, 27605 },
4365 { 0, 1066, 276, 27605 },
4366 { 0, 800, 231, 23784 },
4367 };
4368
4369 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
4370 {
4371 u64 total_count, diff, ret;
4372 u32 count1, count2, count3, m = 0, c = 0;
4373 unsigned long now = jiffies_to_msecs(jiffies), diff1;
4374 int i;
4375
4376 assert_spin_locked(&mchdev_lock);
4377
4378 diff1 = now - dev_priv->ips.last_time1;
4379
4380 /* Prevent division-by-zero if we are asking too fast.
4381 * Also, we don't get interesting results if we are polling
4382 * faster than once in 10ms, so just return the saved value
4383 * in such cases.
4384 */
4385 if (diff1 <= 10)
4386 return dev_priv->ips.chipset_power;
4387
4388 count1 = I915_READ(DMIEC);
4389 count2 = I915_READ(DDREC);
4390 count3 = I915_READ(CSIEC);
4391
4392 total_count = count1 + count2 + count3;
4393
4394 /* FIXME: handle per-counter overflow */
4395 if (total_count < dev_priv->ips.last_count1) {
4396 diff = ~0UL - dev_priv->ips.last_count1;
4397 diff += total_count;
4398 } else {
4399 diff = total_count - dev_priv->ips.last_count1;
4400 }
4401
4402 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
4403 if (cparams[i].i == dev_priv->ips.c_m &&
4404 cparams[i].t == dev_priv->ips.r_t) {
4405 m = cparams[i].m;
4406 c = cparams[i].c;
4407 break;
4408 }
4409 }
4410
4411 diff = div_u64(diff, diff1);
4412 ret = ((m * diff) + c);
4413 ret = div_u64(ret, 10);
4414
4415 dev_priv->ips.last_count1 = total_count;
4416 dev_priv->ips.last_time1 = now;
4417
4418 dev_priv->ips.chipset_power = ret;
4419
4420 return ret;
4421 }
4422
4423 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
4424 {
4425 struct drm_device *dev = dev_priv->dev;
4426 unsigned long val;
4427
4428 if (INTEL_INFO(dev)->gen != 5)
4429 return 0;
4430
4431 spin_lock_irq(&mchdev_lock);
4432
4433 val = __i915_chipset_val(dev_priv);
4434
4435 spin_unlock_irq(&mchdev_lock);
4436
4437 return val;
4438 }
4439
4440 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
4441 {
4442 unsigned long m, x, b;
4443 u32 tsfs;
4444
4445 tsfs = I915_READ(TSFS);
4446
4447 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
4448 x = I915_READ8(TR1);
4449
4450 b = tsfs & TSFS_INTR_MASK;
4451
4452 return ((m * x) / 127) - b;
4453 }
4454
4455 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
4456 {
4457 struct drm_device *dev = dev_priv->dev;
4458 static const struct v_table {
4459 u16 vd; /* in .1 mil */
4460 u16 vm; /* in .1 mil */
4461 } v_table[] = {
4462 { 0, 0, },
4463 { 375, 0, },
4464 { 500, 0, },
4465 { 625, 0, },
4466 { 750, 0, },
4467 { 875, 0, },
4468 { 1000, 0, },
4469 { 1125, 0, },
4470 { 4125, 3000, },
4471 { 4125, 3000, },
4472 { 4125, 3000, },
4473 { 4125, 3000, },
4474 { 4125, 3000, },
4475 { 4125, 3000, },
4476 { 4125, 3000, },
4477 { 4125, 3000, },
4478 { 4125, 3000, },
4479 { 4125, 3000, },
4480 { 4125, 3000, },
4481 { 4125, 3000, },
4482 { 4125, 3000, },
4483 { 4125, 3000, },
4484 { 4125, 3000, },
4485 { 4125, 3000, },
4486 { 4125, 3000, },
4487 { 4125, 3000, },
4488 { 4125, 3000, },
4489 { 4125, 3000, },
4490 { 4125, 3000, },
4491 { 4125, 3000, },
4492 { 4125, 3000, },
4493 { 4125, 3000, },
4494 { 4250, 3125, },
4495 { 4375, 3250, },
4496 { 4500, 3375, },
4497 { 4625, 3500, },
4498 { 4750, 3625, },
4499 { 4875, 3750, },
4500 { 5000, 3875, },
4501 { 5125, 4000, },
4502 { 5250, 4125, },
4503 { 5375, 4250, },
4504 { 5500, 4375, },
4505 { 5625, 4500, },
4506 { 5750, 4625, },
4507 { 5875, 4750, },
4508 { 6000, 4875, },
4509 { 6125, 5000, },
4510 { 6250, 5125, },
4511 { 6375, 5250, },
4512 { 6500, 5375, },
4513 { 6625, 5500, },
4514 { 6750, 5625, },
4515 { 6875, 5750, },
4516 { 7000, 5875, },
4517 { 7125, 6000, },
4518 { 7250, 6125, },
4519 { 7375, 6250, },
4520 { 7500, 6375, },
4521 { 7625, 6500, },
4522 { 7750, 6625, },
4523 { 7875, 6750, },
4524 { 8000, 6875, },
4525 { 8125, 7000, },
4526 { 8250, 7125, },
4527 { 8375, 7250, },
4528 { 8500, 7375, },
4529 { 8625, 7500, },
4530 { 8750, 7625, },
4531 { 8875, 7750, },
4532 { 9000, 7875, },
4533 { 9125, 8000, },
4534 { 9250, 8125, },
4535 { 9375, 8250, },
4536 { 9500, 8375, },
4537 { 9625, 8500, },
4538 { 9750, 8625, },
4539 { 9875, 8750, },
4540 { 10000, 8875, },
4541 { 10125, 9000, },
4542 { 10250, 9125, },
4543 { 10375, 9250, },
4544 { 10500, 9375, },
4545 { 10625, 9500, },
4546 { 10750, 9625, },
4547 { 10875, 9750, },
4548 { 11000, 9875, },
4549 { 11125, 10000, },
4550 { 11250, 10125, },
4551 { 11375, 10250, },
4552 { 11500, 10375, },
4553 { 11625, 10500, },
4554 { 11750, 10625, },
4555 { 11875, 10750, },
4556 { 12000, 10875, },
4557 { 12125, 11000, },
4558 { 12250, 11125, },
4559 { 12375, 11250, },
4560 { 12500, 11375, },
4561 { 12625, 11500, },
4562 { 12750, 11625, },
4563 { 12875, 11750, },
4564 { 13000, 11875, },
4565 { 13125, 12000, },
4566 { 13250, 12125, },
4567 { 13375, 12250, },
4568 { 13500, 12375, },
4569 { 13625, 12500, },
4570 { 13750, 12625, },
4571 { 13875, 12750, },
4572 { 14000, 12875, },
4573 { 14125, 13000, },
4574 { 14250, 13125, },
4575 { 14375, 13250, },
4576 { 14500, 13375, },
4577 { 14625, 13500, },
4578 { 14750, 13625, },
4579 { 14875, 13750, },
4580 { 15000, 13875, },
4581 { 15125, 14000, },
4582 { 15250, 14125, },
4583 { 15375, 14250, },
4584 { 15500, 14375, },
4585 { 15625, 14500, },
4586 { 15750, 14625, },
4587 { 15875, 14750, },
4588 { 16000, 14875, },
4589 { 16125, 15000, },
4590 };
4591 if (INTEL_INFO(dev)->is_mobile)
4592 return v_table[pxvid].vm;
4593 else
4594 return v_table[pxvid].vd;
4595 }
4596
4597 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
4598 {
4599 struct timespec now, diff1;
4600 u64 diff;
4601 unsigned long diffms;
4602 u32 count;
4603
4604 assert_spin_locked(&mchdev_lock);
4605
4606 getrawmonotonic(&now);
4607 diff1 = timespec_sub(now, dev_priv->ips.last_time2);
4608
4609 /* Don't divide by 0 */
4610 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
4611 if (!diffms)
4612 return;
4613
4614 count = I915_READ(GFXEC);
4615
4616 if (count < dev_priv->ips.last_count2) {
4617 diff = ~0UL - dev_priv->ips.last_count2;
4618 diff += count;
4619 } else {
4620 diff = count - dev_priv->ips.last_count2;
4621 }
4622
4623 dev_priv->ips.last_count2 = count;
4624 dev_priv->ips.last_time2 = now;
4625
4626 /* More magic constants... */
4627 diff = diff * 1181;
4628 diff = div_u64(diff, diffms * 10);
4629 dev_priv->ips.gfx_power = diff;
4630 }
4631
4632 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
4633 {
4634 struct drm_device *dev = dev_priv->dev;
4635
4636 if (INTEL_INFO(dev)->gen != 5)
4637 return;
4638
4639 spin_lock_irq(&mchdev_lock);
4640
4641 __i915_update_gfx_val(dev_priv);
4642
4643 spin_unlock_irq(&mchdev_lock);
4644 }
4645
4646 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
4647 {
4648 unsigned long t, corr, state1, corr2, state2;
4649 u32 pxvid, ext_v;
4650
4651 assert_spin_locked(&mchdev_lock);
4652
4653 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_freq * 4));
4654 pxvid = (pxvid >> 24) & 0x7f;
4655 ext_v = pvid_to_extvid(dev_priv, pxvid);
4656
4657 state1 = ext_v;
4658
4659 t = i915_mch_val(dev_priv);
4660
4661 /* Revel in the empirically derived constants */
4662
4663 /* Correction factor in 1/100000 units */
4664 if (t > 80)
4665 corr = ((t * 2349) + 135940);
4666 else if (t >= 50)
4667 corr = ((t * 964) + 29317);
4668 else /* < 50 */
4669 corr = ((t * 301) + 1004);
4670
4671 corr = corr * ((150142 * state1) / 10000 - 78642);
4672 corr /= 100000;
4673 corr2 = (corr * dev_priv->ips.corr);
4674
4675 state2 = (corr2 * state1) / 10000;
4676 state2 /= 100; /* convert to mW */
4677
4678 __i915_update_gfx_val(dev_priv);
4679
4680 return dev_priv->ips.gfx_power + state2;
4681 }
4682
4683 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
4684 {
4685 struct drm_device *dev = dev_priv->dev;
4686 unsigned long val;
4687
4688 if (INTEL_INFO(dev)->gen != 5)
4689 return 0;
4690
4691 spin_lock_irq(&mchdev_lock);
4692
4693 val = __i915_gfx_val(dev_priv);
4694
4695 spin_unlock_irq(&mchdev_lock);
4696
4697 return val;
4698 }
4699
4700 /**
4701 * i915_read_mch_val - return value for IPS use
4702 *
4703 * Calculate and return a value for the IPS driver to use when deciding whether
4704 * we have thermal and power headroom to increase CPU or GPU power budget.
4705 */
4706 unsigned long i915_read_mch_val(void)
4707 {
4708 struct drm_i915_private *dev_priv;
4709 unsigned long chipset_val, graphics_val, ret = 0;
4710
4711 spin_lock_irq(&mchdev_lock);
4712 if (!i915_mch_dev)
4713 goto out_unlock;
4714 dev_priv = i915_mch_dev;
4715
4716 chipset_val = __i915_chipset_val(dev_priv);
4717 graphics_val = __i915_gfx_val(dev_priv);
4718
4719 ret = chipset_val + graphics_val;
4720
4721 out_unlock:
4722 spin_unlock_irq(&mchdev_lock);
4723
4724 return ret;
4725 }
4726 EXPORT_SYMBOL_GPL(i915_read_mch_val);
4727
4728 /**
4729 * i915_gpu_raise - raise GPU frequency limit
4730 *
4731 * Raise the limit; IPS indicates we have thermal headroom.
4732 */
4733 bool i915_gpu_raise(void)
4734 {
4735 struct drm_i915_private *dev_priv;
4736 bool ret = true;
4737
4738 spin_lock_irq(&mchdev_lock);
4739 if (!i915_mch_dev) {
4740 ret = false;
4741 goto out_unlock;
4742 }
4743 dev_priv = i915_mch_dev;
4744
4745 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
4746 dev_priv->ips.max_delay--;
4747
4748 out_unlock:
4749 spin_unlock_irq(&mchdev_lock);
4750
4751 return ret;
4752 }
4753 EXPORT_SYMBOL_GPL(i915_gpu_raise);
4754
4755 /**
4756 * i915_gpu_lower - lower GPU frequency limit
4757 *
4758 * IPS indicates we're close to a thermal limit, so throttle back the GPU
4759 * frequency maximum.
4760 */
4761 bool i915_gpu_lower(void)
4762 {
4763 struct drm_i915_private *dev_priv;
4764 bool ret = true;
4765
4766 spin_lock_irq(&mchdev_lock);
4767 if (!i915_mch_dev) {
4768 ret = false;
4769 goto out_unlock;
4770 }
4771 dev_priv = i915_mch_dev;
4772
4773 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
4774 dev_priv->ips.max_delay++;
4775
4776 out_unlock:
4777 spin_unlock_irq(&mchdev_lock);
4778
4779 return ret;
4780 }
4781 EXPORT_SYMBOL_GPL(i915_gpu_lower);
4782
4783 /**
4784 * i915_gpu_busy - indicate GPU business to IPS
4785 *
4786 * Tell the IPS driver whether or not the GPU is busy.
4787 */
4788 bool i915_gpu_busy(void)
4789 {
4790 struct drm_i915_private *dev_priv;
4791 struct intel_engine_cs *ring;
4792 bool ret = false;
4793 int i;
4794
4795 spin_lock_irq(&mchdev_lock);
4796 if (!i915_mch_dev)
4797 goto out_unlock;
4798 dev_priv = i915_mch_dev;
4799
4800 for_each_ring(ring, dev_priv, i)
4801 ret |= !list_empty(&ring->request_list);
4802
4803 out_unlock:
4804 spin_unlock_irq(&mchdev_lock);
4805
4806 return ret;
4807 }
4808 EXPORT_SYMBOL_GPL(i915_gpu_busy);
4809
4810 /**
4811 * i915_gpu_turbo_disable - disable graphics turbo
4812 *
4813 * Disable graphics turbo by resetting the max frequency and setting the
4814 * current frequency to the default.
4815 */
4816 bool i915_gpu_turbo_disable(void)
4817 {
4818 struct drm_i915_private *dev_priv;
4819 bool ret = true;
4820
4821 spin_lock_irq(&mchdev_lock);
4822 if (!i915_mch_dev) {
4823 ret = false;
4824 goto out_unlock;
4825 }
4826 dev_priv = i915_mch_dev;
4827
4828 dev_priv->ips.max_delay = dev_priv->ips.fstart;
4829
4830 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
4831 ret = false;
4832
4833 out_unlock:
4834 spin_unlock_irq(&mchdev_lock);
4835
4836 return ret;
4837 }
4838 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
4839
4840 /**
4841 * Tells the intel_ips driver that the i915 driver is now loaded, if
4842 * IPS got loaded first.
4843 *
4844 * This awkward dance is so that neither module has to depend on the
4845 * other in order for IPS to do the appropriate communication of
4846 * GPU turbo limits to i915.
4847 */
4848 static void
4849 ips_ping_for_i915_load(void)
4850 {
4851 void (*link)(void);
4852
4853 link = symbol_get(ips_link_to_i915_driver);
4854 if (link) {
4855 link();
4856 symbol_put(ips_link_to_i915_driver);
4857 }
4858 }
4859
4860 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
4861 {
4862 /* We only register the i915 ips part with intel-ips once everything is
4863 * set up, to avoid intel-ips sneaking in and reading bogus values. */
4864 spin_lock_irq(&mchdev_lock);
4865 i915_mch_dev = dev_priv;
4866 spin_unlock_irq(&mchdev_lock);
4867
4868 ips_ping_for_i915_load();
4869 }
4870
4871 void intel_gpu_ips_teardown(void)
4872 {
4873 spin_lock_irq(&mchdev_lock);
4874 i915_mch_dev = NULL;
4875 spin_unlock_irq(&mchdev_lock);
4876 }
4877
4878 static void intel_init_emon(struct drm_device *dev)
4879 {
4880 struct drm_i915_private *dev_priv = dev->dev_private;
4881 u32 lcfuse;
4882 u8 pxw[16];
4883 int i;
4884
4885 /* Disable to program */
4886 I915_WRITE(ECR, 0);
4887 POSTING_READ(ECR);
4888
4889 /* Program energy weights for various events */
4890 I915_WRITE(SDEW, 0x15040d00);
4891 I915_WRITE(CSIEW0, 0x007f0000);
4892 I915_WRITE(CSIEW1, 0x1e220004);
4893 I915_WRITE(CSIEW2, 0x04000004);
4894
4895 for (i = 0; i < 5; i++)
4896 I915_WRITE(PEW + (i * 4), 0);
4897 for (i = 0; i < 3; i++)
4898 I915_WRITE(DEW + (i * 4), 0);
4899
4900 /* Program P-state weights to account for frequency power adjustment */
4901 for (i = 0; i < 16; i++) {
4902 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
4903 unsigned long freq = intel_pxfreq(pxvidfreq);
4904 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
4905 PXVFREQ_PX_SHIFT;
4906 unsigned long val;
4907
4908 val = vid * vid;
4909 val *= (freq / 1000);
4910 val *= 255;
4911 val /= (127*127*900);
4912 if (val > 0xff)
4913 DRM_ERROR("bad pxval: %ld\n", val);
4914 pxw[i] = val;
4915 }
4916 /* Render standby states get 0 weight */
4917 pxw[14] = 0;
4918 pxw[15] = 0;
4919
4920 for (i = 0; i < 4; i++) {
4921 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
4922 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
4923 I915_WRITE(PXW + (i * 4), val);
4924 }
4925
4926 /* Adjust magic regs to magic values (more experimental results) */
4927 I915_WRITE(OGW0, 0);
4928 I915_WRITE(OGW1, 0);
4929 I915_WRITE(EG0, 0x00007f00);
4930 I915_WRITE(EG1, 0x0000000e);
4931 I915_WRITE(EG2, 0x000e0000);
4932 I915_WRITE(EG3, 0x68000300);
4933 I915_WRITE(EG4, 0x42000000);
4934 I915_WRITE(EG5, 0x00140031);
4935 I915_WRITE(EG6, 0);
4936 I915_WRITE(EG7, 0);
4937
4938 for (i = 0; i < 8; i++)
4939 I915_WRITE(PXWL + (i * 4), 0);
4940
4941 /* Enable PMON + select events */
4942 I915_WRITE(ECR, 0x80000019);
4943
4944 lcfuse = I915_READ(LCFUSE02);
4945
4946 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
4947 }
4948
4949 void intel_init_gt_powersave(struct drm_device *dev)
4950 {
4951 i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
4952
4953 if (IS_CHERRYVIEW(dev))
4954 cherryview_init_gt_powersave(dev);
4955 else if (IS_VALLEYVIEW(dev))
4956 valleyview_init_gt_powersave(dev);
4957 }
4958
4959 void intel_cleanup_gt_powersave(struct drm_device *dev)
4960 {
4961 if (IS_CHERRYVIEW(dev))
4962 return;
4963 else if (IS_VALLEYVIEW(dev))
4964 valleyview_cleanup_gt_powersave(dev);
4965 }
4966
4967 /**
4968 * intel_suspend_gt_powersave - suspend PM work and helper threads
4969 * @dev: drm device
4970 *
4971 * We don't want to disable RC6 or other features here, we just want
4972 * to make sure any work we've queued has finished and won't bother
4973 * us while we're suspended.
4974 */
4975 void intel_suspend_gt_powersave(struct drm_device *dev)
4976 {
4977 struct drm_i915_private *dev_priv = dev->dev_private;
4978
4979 /* Interrupts should be disabled already to avoid re-arming. */
4980 WARN_ON(intel_irqs_enabled(dev_priv));
4981
4982 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4983
4984 cancel_work_sync(&dev_priv->rps.work);
4985
4986 /* Force GPU to min freq during suspend */
4987 gen6_rps_idle(dev_priv);
4988 }
4989
4990 void intel_disable_gt_powersave(struct drm_device *dev)
4991 {
4992 struct drm_i915_private *dev_priv = dev->dev_private;
4993
4994 /* Interrupts should be disabled already to avoid re-arming. */
4995 WARN_ON(intel_irqs_enabled(dev_priv));
4996
4997 if (IS_IRONLAKE_M(dev)) {
4998 ironlake_disable_drps(dev);
4999 ironlake_disable_rc6(dev);
5000 } else if (INTEL_INFO(dev)->gen >= 6) {
5001 intel_suspend_gt_powersave(dev);
5002
5003 mutex_lock(&dev_priv->rps.hw_lock);
5004 if (IS_CHERRYVIEW(dev))
5005 cherryview_disable_rps(dev);
5006 else if (IS_VALLEYVIEW(dev))
5007 valleyview_disable_rps(dev);
5008 else
5009 gen6_disable_rps(dev);
5010 dev_priv->rps.enabled = false;
5011 mutex_unlock(&dev_priv->rps.hw_lock);
5012 }
5013 }
5014
5015 static void intel_gen6_powersave_work(struct work_struct *work)
5016 {
5017 struct drm_i915_private *dev_priv =
5018 container_of(work, struct drm_i915_private,
5019 rps.delayed_resume_work.work);
5020 struct drm_device *dev = dev_priv->dev;
5021
5022 mutex_lock(&dev_priv->rps.hw_lock);
5023
5024 if (IS_CHERRYVIEW(dev)) {
5025 cherryview_enable_rps(dev);
5026 } else if (IS_VALLEYVIEW(dev)) {
5027 valleyview_enable_rps(dev);
5028 } else if (IS_BROADWELL(dev)) {
5029 gen8_enable_rps(dev);
5030 __gen6_update_ring_freq(dev);
5031 } else {
5032 gen6_enable_rps(dev);
5033 __gen6_update_ring_freq(dev);
5034 }
5035 dev_priv->rps.enabled = true;
5036 mutex_unlock(&dev_priv->rps.hw_lock);
5037
5038 intel_runtime_pm_put(dev_priv);
5039 }
5040
5041 void intel_enable_gt_powersave(struct drm_device *dev)
5042 {
5043 struct drm_i915_private *dev_priv = dev->dev_private;
5044
5045 if (IS_IRONLAKE_M(dev)) {
5046 mutex_lock(&dev->struct_mutex);
5047 ironlake_enable_drps(dev);
5048 ironlake_enable_rc6(dev);
5049 intel_init_emon(dev);
5050 mutex_unlock(&dev->struct_mutex);
5051 } else if (INTEL_INFO(dev)->gen >= 6) {
5052 /*
5053 * PCU communication is slow and this doesn't need to be
5054 * done at any specific time, so do this out of our fast path
5055 * to make resume and init faster.
5056 *
5057 * We depend on the HW RC6 power context save/restore
5058 * mechanism when entering D3 through runtime PM suspend. So
5059 * disable RPM until RPS/RC6 is properly setup. We can only
5060 * get here via the driver load/system resume/runtime resume
5061 * paths, so the _noresume version is enough (and in case of
5062 * runtime resume it's necessary).
5063 */
5064 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
5065 round_jiffies_up_relative(HZ)))
5066 intel_runtime_pm_get_noresume(dev_priv);
5067 }
5068 }
5069
5070 void intel_reset_gt_powersave(struct drm_device *dev)
5071 {
5072 struct drm_i915_private *dev_priv = dev->dev_private;
5073
5074 dev_priv->rps.enabled = false;
5075 intel_enable_gt_powersave(dev);
5076 }
5077
5078 static void ibx_init_clock_gating(struct drm_device *dev)
5079 {
5080 struct drm_i915_private *dev_priv = dev->dev_private;
5081
5082 /*
5083 * On Ibex Peak and Cougar Point, we need to disable clock
5084 * gating for the panel power sequencer or it will fail to
5085 * start up when no ports are active.
5086 */
5087 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
5088 }
5089
5090 static void g4x_disable_trickle_feed(struct drm_device *dev)
5091 {
5092 struct drm_i915_private *dev_priv = dev->dev_private;
5093 int pipe;
5094
5095 for_each_pipe(pipe) {
5096 I915_WRITE(DSPCNTR(pipe),
5097 I915_READ(DSPCNTR(pipe)) |
5098 DISPPLANE_TRICKLE_FEED_DISABLE);
5099 intel_flush_primary_plane(dev_priv, pipe);
5100 }
5101 }
5102
5103 static void ilk_init_lp_watermarks(struct drm_device *dev)
5104 {
5105 struct drm_i915_private *dev_priv = dev->dev_private;
5106
5107 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
5108 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
5109 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
5110
5111 /*
5112 * Don't touch WM1S_LP_EN here.
5113 * Doing so could cause underruns.
5114 */
5115 }
5116
5117 static void ironlake_init_clock_gating(struct drm_device *dev)
5118 {
5119 struct drm_i915_private *dev_priv = dev->dev_private;
5120 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
5121
5122 /*
5123 * Required for FBC
5124 * WaFbcDisableDpfcClockGating:ilk
5125 */
5126 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
5127 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
5128 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
5129
5130 I915_WRITE(PCH_3DCGDIS0,
5131 MARIUNIT_CLOCK_GATE_DISABLE |
5132 SVSMUNIT_CLOCK_GATE_DISABLE);
5133 I915_WRITE(PCH_3DCGDIS1,
5134 VFMUNIT_CLOCK_GATE_DISABLE);
5135
5136 /*
5137 * According to the spec the following bits should be set in
5138 * order to enable memory self-refresh
5139 * The bit 22/21 of 0x42004
5140 * The bit 5 of 0x42020
5141 * The bit 15 of 0x45000
5142 */
5143 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5144 (I915_READ(ILK_DISPLAY_CHICKEN2) |
5145 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
5146 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
5147 I915_WRITE(DISP_ARB_CTL,
5148 (I915_READ(DISP_ARB_CTL) |
5149 DISP_FBC_WM_DIS));
5150
5151 ilk_init_lp_watermarks(dev);
5152
5153 /*
5154 * Based on the document from hardware guys the following bits
5155 * should be set unconditionally in order to enable FBC.
5156 * The bit 22 of 0x42000
5157 * The bit 22 of 0x42004
5158 * The bit 7,8,9 of 0x42020.
5159 */
5160 if (IS_IRONLAKE_M(dev)) {
5161 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
5162 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5163 I915_READ(ILK_DISPLAY_CHICKEN1) |
5164 ILK_FBCQ_DIS);
5165 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5166 I915_READ(ILK_DISPLAY_CHICKEN2) |
5167 ILK_DPARB_GATE);
5168 }
5169
5170 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
5171
5172 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5173 I915_READ(ILK_DISPLAY_CHICKEN2) |
5174 ILK_ELPIN_409_SELECT);
5175 I915_WRITE(_3D_CHICKEN2,
5176 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
5177 _3D_CHICKEN2_WM_READ_PIPELINED);
5178
5179 /* WaDisableRenderCachePipelinedFlush:ilk */
5180 I915_WRITE(CACHE_MODE_0,
5181 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
5182
5183 /* WaDisable_RenderCache_OperationalFlush:ilk */
5184 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5185
5186 g4x_disable_trickle_feed(dev);
5187
5188 ibx_init_clock_gating(dev);
5189 }
5190
5191 static void cpt_init_clock_gating(struct drm_device *dev)
5192 {
5193 struct drm_i915_private *dev_priv = dev->dev_private;
5194 int pipe;
5195 uint32_t val;
5196
5197 /*
5198 * On Ibex Peak and Cougar Point, we need to disable clock
5199 * gating for the panel power sequencer or it will fail to
5200 * start up when no ports are active.
5201 */
5202 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
5203 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
5204 PCH_CPUNIT_CLOCK_GATE_DISABLE);
5205 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
5206 DPLS_EDP_PPS_FIX_DIS);
5207 /* The below fixes the weird display corruption, a few pixels shifted
5208 * downward, on (only) LVDS of some HP laptops with IVY.
5209 */
5210 for_each_pipe(pipe) {
5211 val = I915_READ(TRANS_CHICKEN2(pipe));
5212 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
5213 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
5214 if (dev_priv->vbt.fdi_rx_polarity_inverted)
5215 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
5216 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
5217 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
5218 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
5219 I915_WRITE(TRANS_CHICKEN2(pipe), val);
5220 }
5221 /* WADP0ClockGatingDisable */
5222 for_each_pipe(pipe) {
5223 I915_WRITE(TRANS_CHICKEN1(pipe),
5224 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
5225 }
5226 }
5227
5228 static void gen6_check_mch_setup(struct drm_device *dev)
5229 {
5230 struct drm_i915_private *dev_priv = dev->dev_private;
5231 uint32_t tmp;
5232
5233 tmp = I915_READ(MCH_SSKPD);
5234 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
5235 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
5236 tmp);
5237 }
5238
5239 static void gen6_init_clock_gating(struct drm_device *dev)
5240 {
5241 struct drm_i915_private *dev_priv = dev->dev_private;
5242 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
5243
5244 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
5245
5246 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5247 I915_READ(ILK_DISPLAY_CHICKEN2) |
5248 ILK_ELPIN_409_SELECT);
5249
5250 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
5251 I915_WRITE(_3D_CHICKEN,
5252 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
5253
5254 /* WaSetupGtModeTdRowDispatch:snb */
5255 if (IS_SNB_GT1(dev))
5256 I915_WRITE(GEN6_GT_MODE,
5257 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
5258
5259 /* WaDisable_RenderCache_OperationalFlush:snb */
5260 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5261
5262 /*
5263 * BSpec recoomends 8x4 when MSAA is used,
5264 * however in practice 16x4 seems fastest.
5265 *
5266 * Note that PS/WM thread counts depend on the WIZ hashing
5267 * disable bit, which we don't touch here, but it's good
5268 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5269 */
5270 I915_WRITE(GEN6_GT_MODE,
5271 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5272
5273 ilk_init_lp_watermarks(dev);
5274
5275 I915_WRITE(CACHE_MODE_0,
5276 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
5277
5278 I915_WRITE(GEN6_UCGCTL1,
5279 I915_READ(GEN6_UCGCTL1) |
5280 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
5281 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
5282
5283 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5284 * gating disable must be set. Failure to set it results in
5285 * flickering pixels due to Z write ordering failures after
5286 * some amount of runtime in the Mesa "fire" demo, and Unigine
5287 * Sanctuary and Tropics, and apparently anything else with
5288 * alpha test or pixel discard.
5289 *
5290 * According to the spec, bit 11 (RCCUNIT) must also be set,
5291 * but we didn't debug actual testcases to find it out.
5292 *
5293 * WaDisableRCCUnitClockGating:snb
5294 * WaDisableRCPBUnitClockGating:snb
5295 */
5296 I915_WRITE(GEN6_UCGCTL2,
5297 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
5298 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5299
5300 /* WaStripsFansDisableFastClipPerformanceFix:snb */
5301 I915_WRITE(_3D_CHICKEN3,
5302 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
5303
5304 /*
5305 * Bspec says:
5306 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
5307 * 3DSTATE_SF number of SF output attributes is more than 16."
5308 */
5309 I915_WRITE(_3D_CHICKEN3,
5310 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
5311
5312 /*
5313 * According to the spec the following bits should be
5314 * set in order to enable memory self-refresh and fbc:
5315 * The bit21 and bit22 of 0x42000
5316 * The bit21 and bit22 of 0x42004
5317 * The bit5 and bit7 of 0x42020
5318 * The bit14 of 0x70180
5319 * The bit14 of 0x71180
5320 *
5321 * WaFbcAsynchFlipDisableFbcQueue:snb
5322 */
5323 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5324 I915_READ(ILK_DISPLAY_CHICKEN1) |
5325 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
5326 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5327 I915_READ(ILK_DISPLAY_CHICKEN2) |
5328 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
5329 I915_WRITE(ILK_DSPCLK_GATE_D,
5330 I915_READ(ILK_DSPCLK_GATE_D) |
5331 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
5332 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
5333
5334 g4x_disable_trickle_feed(dev);
5335
5336 cpt_init_clock_gating(dev);
5337
5338 gen6_check_mch_setup(dev);
5339 }
5340
5341 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
5342 {
5343 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
5344
5345 /*
5346 * WaVSThreadDispatchOverride:ivb,vlv
5347 *
5348 * This actually overrides the dispatch
5349 * mode for all thread types.
5350 */
5351 reg &= ~GEN7_FF_SCHED_MASK;
5352 reg |= GEN7_FF_TS_SCHED_HW;
5353 reg |= GEN7_FF_VS_SCHED_HW;
5354 reg |= GEN7_FF_DS_SCHED_HW;
5355
5356 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
5357 }
5358
5359 static void lpt_init_clock_gating(struct drm_device *dev)
5360 {
5361 struct drm_i915_private *dev_priv = dev->dev_private;
5362
5363 /*
5364 * TODO: this bit should only be enabled when really needed, then
5365 * disabled when not needed anymore in order to save power.
5366 */
5367 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
5368 I915_WRITE(SOUTH_DSPCLK_GATE_D,
5369 I915_READ(SOUTH_DSPCLK_GATE_D) |
5370 PCH_LP_PARTITION_LEVEL_DISABLE);
5371
5372 /* WADPOClockGatingDisable:hsw */
5373 I915_WRITE(_TRANSA_CHICKEN1,
5374 I915_READ(_TRANSA_CHICKEN1) |
5375 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
5376 }
5377
5378 static void lpt_suspend_hw(struct drm_device *dev)
5379 {
5380 struct drm_i915_private *dev_priv = dev->dev_private;
5381
5382 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
5383 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
5384
5385 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
5386 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
5387 }
5388 }
5389
5390 static void gen8_init_clock_gating(struct drm_device *dev)
5391 {
5392 struct drm_i915_private *dev_priv = dev->dev_private;
5393 enum pipe pipe;
5394
5395 I915_WRITE(WM3_LP_ILK, 0);
5396 I915_WRITE(WM2_LP_ILK, 0);
5397 I915_WRITE(WM1_LP_ILK, 0);
5398
5399 /* FIXME(BDW): Check all the w/a, some might only apply to
5400 * pre-production hw. */
5401
5402 /* WaDisablePartialInstShootdown:bdw */
5403 I915_WRITE(GEN8_ROW_CHICKEN,
5404 _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE));
5405
5406 /* WaDisableThreadStallDopClockGating:bdw */
5407 /* FIXME: Unclear whether we really need this on production bdw. */
5408 I915_WRITE(GEN8_ROW_CHICKEN,
5409 _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
5410
5411 /*
5412 * This GEN8_CENTROID_PIXEL_OPT_DIS W/A is only needed for
5413 * pre-production hardware
5414 */
5415 I915_WRITE(HALF_SLICE_CHICKEN3,
5416 _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS));
5417 I915_WRITE(HALF_SLICE_CHICKEN3,
5418 _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
5419 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE));
5420
5421 I915_WRITE(_3D_CHICKEN3,
5422 _MASKED_BIT_ENABLE(_3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2)));
5423
5424 I915_WRITE(COMMON_SLICE_CHICKEN2,
5425 _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE));
5426
5427 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5428 _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE));
5429
5430 /* WaDisableDopClockGating:bdw May not be needed for production */
5431 I915_WRITE(GEN7_ROW_CHICKEN2,
5432 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5433
5434 /* WaSwitchSolVfFArbitrationPriority:bdw */
5435 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
5436
5437 /* WaPsrDPAMaskVBlankInSRD:bdw */
5438 I915_WRITE(CHICKEN_PAR1_1,
5439 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
5440
5441 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
5442 for_each_pipe(pipe) {
5443 I915_WRITE(CHICKEN_PIPESL_1(pipe),
5444 I915_READ(CHICKEN_PIPESL_1(pipe)) |
5445 BDW_DPRS_MASK_VBLANK_SRD);
5446 }
5447
5448 /* Use Force Non-Coherent whenever executing a 3D context. This is a
5449 * workaround for for a possible hang in the unlikely event a TLB
5450 * invalidation occurs during a PSD flush.
5451 */
5452 I915_WRITE(HDC_CHICKEN0,
5453 I915_READ(HDC_CHICKEN0) |
5454 _MASKED_BIT_ENABLE(HDC_FORCE_NON_COHERENT));
5455
5456 /* WaVSRefCountFullforceMissDisable:bdw */
5457 /* WaDSRefCountFullforceMissDisable:bdw */
5458 I915_WRITE(GEN7_FF_THREAD_MODE,
5459 I915_READ(GEN7_FF_THREAD_MODE) &
5460 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
5461
5462 /*
5463 * BSpec recommends 8x4 when MSAA is used,
5464 * however in practice 16x4 seems fastest.
5465 *
5466 * Note that PS/WM thread counts depend on the WIZ hashing
5467 * disable bit, which we don't touch here, but it's good
5468 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5469 */
5470 I915_WRITE(GEN7_GT_MODE,
5471 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5472
5473 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
5474 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
5475
5476 /* WaDisableSDEUnitClockGating:bdw */
5477 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
5478 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5479
5480 /* Wa4x4STCOptimizationDisable:bdw */
5481 I915_WRITE(CACHE_MODE_1,
5482 _MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE));
5483 }
5484
5485 static void haswell_init_clock_gating(struct drm_device *dev)
5486 {
5487 struct drm_i915_private *dev_priv = dev->dev_private;
5488
5489 ilk_init_lp_watermarks(dev);
5490
5491 /* L3 caching of data atomics doesn't work -- disable it. */
5492 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
5493 I915_WRITE(HSW_ROW_CHICKEN3,
5494 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
5495
5496 /* This is required by WaCatErrorRejectionIssue:hsw */
5497 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5498 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5499 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5500
5501 /* WaVSRefCountFullforceMissDisable:hsw */
5502 I915_WRITE(GEN7_FF_THREAD_MODE,
5503 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
5504
5505 /* WaDisable_RenderCache_OperationalFlush:hsw */
5506 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5507
5508 /* enable HiZ Raw Stall Optimization */
5509 I915_WRITE(CACHE_MODE_0_GEN7,
5510 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
5511
5512 /* WaDisable4x2SubspanOptimization:hsw */
5513 I915_WRITE(CACHE_MODE_1,
5514 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5515
5516 /*
5517 * BSpec recommends 8x4 when MSAA is used,
5518 * however in practice 16x4 seems fastest.
5519 *
5520 * Note that PS/WM thread counts depend on the WIZ hashing
5521 * disable bit, which we don't touch here, but it's good
5522 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5523 */
5524 I915_WRITE(GEN7_GT_MODE,
5525 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5526
5527 /* WaSwitchSolVfFArbitrationPriority:hsw */
5528 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
5529
5530 /* WaRsPkgCStateDisplayPMReq:hsw */
5531 I915_WRITE(CHICKEN_PAR1_1,
5532 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
5533
5534 lpt_init_clock_gating(dev);
5535 }
5536
5537 static void ivybridge_init_clock_gating(struct drm_device *dev)
5538 {
5539 struct drm_i915_private *dev_priv = dev->dev_private;
5540 uint32_t snpcr;
5541
5542 ilk_init_lp_watermarks(dev);
5543
5544 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
5545
5546 /* WaDisableEarlyCull:ivb */
5547 I915_WRITE(_3D_CHICKEN3,
5548 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5549
5550 /* WaDisableBackToBackFlipFix:ivb */
5551 I915_WRITE(IVB_CHICKEN3,
5552 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5553 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5554
5555 /* WaDisablePSDDualDispatchEnable:ivb */
5556 if (IS_IVB_GT1(dev))
5557 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5558 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5559
5560 /* WaDisable_RenderCache_OperationalFlush:ivb */
5561 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5562
5563 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
5564 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5565 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5566
5567 /* WaApplyL3ControlAndL3ChickenMode:ivb */
5568 I915_WRITE(GEN7_L3CNTLREG1,
5569 GEN7_WA_FOR_GEN7_L3_CONTROL);
5570 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
5571 GEN7_WA_L3_CHICKEN_MODE);
5572 if (IS_IVB_GT1(dev))
5573 I915_WRITE(GEN7_ROW_CHICKEN2,
5574 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5575 else {
5576 /* must write both registers */
5577 I915_WRITE(GEN7_ROW_CHICKEN2,
5578 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5579 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
5580 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5581 }
5582
5583 /* WaForceL3Serialization:ivb */
5584 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5585 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5586
5587 /*
5588 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5589 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
5590 */
5591 I915_WRITE(GEN6_UCGCTL2,
5592 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
5593
5594 /* This is required by WaCatErrorRejectionIssue:ivb */
5595 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5596 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5597 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5598
5599 g4x_disable_trickle_feed(dev);
5600
5601 gen7_setup_fixed_func_scheduler(dev_priv);
5602
5603 if (0) { /* causes HiZ corruption on ivb:gt1 */
5604 /* enable HiZ Raw Stall Optimization */
5605 I915_WRITE(CACHE_MODE_0_GEN7,
5606 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
5607 }
5608
5609 /* WaDisable4x2SubspanOptimization:ivb */
5610 I915_WRITE(CACHE_MODE_1,
5611 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5612
5613 /*
5614 * BSpec recommends 8x4 when MSAA is used,
5615 * however in practice 16x4 seems fastest.
5616 *
5617 * Note that PS/WM thread counts depend on the WIZ hashing
5618 * disable bit, which we don't touch here, but it's good
5619 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5620 */
5621 I915_WRITE(GEN7_GT_MODE,
5622 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5623
5624 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5625 snpcr &= ~GEN6_MBC_SNPCR_MASK;
5626 snpcr |= GEN6_MBC_SNPCR_MED;
5627 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5628
5629 if (!HAS_PCH_NOP(dev))
5630 cpt_init_clock_gating(dev);
5631
5632 gen6_check_mch_setup(dev);
5633 }
5634
5635 static void valleyview_init_clock_gating(struct drm_device *dev)
5636 {
5637 struct drm_i915_private *dev_priv = dev->dev_private;
5638 u32 val;
5639
5640 mutex_lock(&dev_priv->rps.hw_lock);
5641 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5642 mutex_unlock(&dev_priv->rps.hw_lock);
5643 switch ((val >> 6) & 3) {
5644 case 0:
5645 case 1:
5646 dev_priv->mem_freq = 800;
5647 break;
5648 case 2:
5649 dev_priv->mem_freq = 1066;
5650 break;
5651 case 3:
5652 dev_priv->mem_freq = 1333;
5653 break;
5654 }
5655 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
5656
5657 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
5658
5659 /* WaDisableEarlyCull:vlv */
5660 I915_WRITE(_3D_CHICKEN3,
5661 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5662
5663 /* WaDisableBackToBackFlipFix:vlv */
5664 I915_WRITE(IVB_CHICKEN3,
5665 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5666 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5667
5668 /* WaPsdDispatchEnable:vlv */
5669 /* WaDisablePSDDualDispatchEnable:vlv */
5670 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5671 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
5672 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5673
5674 /* WaDisable_RenderCache_OperationalFlush:vlv */
5675 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5676
5677 /* WaForceL3Serialization:vlv */
5678 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5679 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5680
5681 /* WaDisableDopClockGating:vlv */
5682 I915_WRITE(GEN7_ROW_CHICKEN2,
5683 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5684
5685 /* This is required by WaCatErrorRejectionIssue:vlv */
5686 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5687 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5688 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5689
5690 gen7_setup_fixed_func_scheduler(dev_priv);
5691
5692 /*
5693 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5694 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
5695 */
5696 I915_WRITE(GEN6_UCGCTL2,
5697 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
5698
5699 /* WaDisableL3Bank2xClockGate:vlv
5700 * Disabling L3 clock gating- MMIO 940c[25] = 1
5701 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
5702 I915_WRITE(GEN7_UCGCTL4,
5703 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
5704
5705 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
5706
5707 /*
5708 * BSpec says this must be set, even though
5709 * WaDisable4x2SubspanOptimization isn't listed for VLV.
5710 */
5711 I915_WRITE(CACHE_MODE_1,
5712 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5713
5714 /*
5715 * WaIncreaseL3CreditsForVLVB0:vlv
5716 * This is the hardware default actually.
5717 */
5718 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
5719
5720 /*
5721 * WaDisableVLVClockGating_VBIIssue:vlv
5722 * Disable clock gating on th GCFG unit to prevent a delay
5723 * in the reporting of vblank events.
5724 */
5725 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
5726 }
5727
5728 static void cherryview_init_clock_gating(struct drm_device *dev)
5729 {
5730 struct drm_i915_private *dev_priv = dev->dev_private;
5731 u32 val;
5732
5733 mutex_lock(&dev_priv->rps.hw_lock);
5734 val = vlv_punit_read(dev_priv, CCK_FUSE_REG);
5735 mutex_unlock(&dev_priv->rps.hw_lock);
5736 switch ((val >> 2) & 0x7) {
5737 case 0:
5738 case 1:
5739 dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_200;
5740 dev_priv->mem_freq = 1600;
5741 break;
5742 case 2:
5743 dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_267;
5744 dev_priv->mem_freq = 1600;
5745 break;
5746 case 3:
5747 dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_333;
5748 dev_priv->mem_freq = 2000;
5749 break;
5750 case 4:
5751 dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_320;
5752 dev_priv->mem_freq = 1600;
5753 break;
5754 case 5:
5755 dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_400;
5756 dev_priv->mem_freq = 1600;
5757 break;
5758 }
5759 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
5760
5761 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
5762
5763 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
5764
5765 /* WaDisablePartialInstShootdown:chv */
5766 I915_WRITE(GEN8_ROW_CHICKEN,
5767 _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE));
5768
5769 /* WaDisableThreadStallDopClockGating:chv */
5770 I915_WRITE(GEN8_ROW_CHICKEN,
5771 _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
5772
5773 /* WaVSRefCountFullforceMissDisable:chv */
5774 /* WaDSRefCountFullforceMissDisable:chv */
5775 I915_WRITE(GEN7_FF_THREAD_MODE,
5776 I915_READ(GEN7_FF_THREAD_MODE) &
5777 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
5778
5779 /* WaDisableSemaphoreAndSyncFlipWait:chv */
5780 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
5781 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
5782
5783 /* WaDisableCSUnitClockGating:chv */
5784 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
5785 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
5786
5787 /* WaDisableSDEUnitClockGating:chv */
5788 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
5789 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5790
5791 /* WaDisableSamplerPowerBypass:chv (pre-production hw) */
5792 I915_WRITE(HALF_SLICE_CHICKEN3,
5793 _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
5794
5795 /* WaDisableGunitClockGating:chv (pre-production hw) */
5796 I915_WRITE(VLV_GUNIT_CLOCK_GATE, I915_READ(VLV_GUNIT_CLOCK_GATE) |
5797 GINT_DIS);
5798
5799 /* WaDisableFfDopClockGating:chv (pre-production hw) */
5800 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
5801 _MASKED_BIT_ENABLE(GEN8_FF_DOP_CLOCK_GATE_DISABLE));
5802
5803 /* WaDisableDopClockGating:chv (pre-production hw) */
5804 I915_WRITE(GEN7_ROW_CHICKEN2,
5805 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5806 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
5807 GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
5808 }
5809
5810 static void g4x_init_clock_gating(struct drm_device *dev)
5811 {
5812 struct drm_i915_private *dev_priv = dev->dev_private;
5813 uint32_t dspclk_gate;
5814
5815 I915_WRITE(RENCLK_GATE_D1, 0);
5816 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5817 GS_UNIT_CLOCK_GATE_DISABLE |
5818 CL_UNIT_CLOCK_GATE_DISABLE);
5819 I915_WRITE(RAMCLK_GATE_D, 0);
5820 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5821 OVRUNIT_CLOCK_GATE_DISABLE |
5822 OVCUNIT_CLOCK_GATE_DISABLE;
5823 if (IS_GM45(dev))
5824 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5825 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5826
5827 /* WaDisableRenderCachePipelinedFlush */
5828 I915_WRITE(CACHE_MODE_0,
5829 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
5830
5831 /* WaDisable_RenderCache_OperationalFlush:g4x */
5832 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5833
5834 g4x_disable_trickle_feed(dev);
5835 }
5836
5837 static void crestline_init_clock_gating(struct drm_device *dev)
5838 {
5839 struct drm_i915_private *dev_priv = dev->dev_private;
5840
5841 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5842 I915_WRITE(RENCLK_GATE_D2, 0);
5843 I915_WRITE(DSPCLK_GATE_D, 0);
5844 I915_WRITE(RAMCLK_GATE_D, 0);
5845 I915_WRITE16(DEUC, 0);
5846 I915_WRITE(MI_ARB_STATE,
5847 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
5848
5849 /* WaDisable_RenderCache_OperationalFlush:gen4 */
5850 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5851 }
5852
5853 static void broadwater_init_clock_gating(struct drm_device *dev)
5854 {
5855 struct drm_i915_private *dev_priv = dev->dev_private;
5856
5857 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5858 I965_RCC_CLOCK_GATE_DISABLE |
5859 I965_RCPB_CLOCK_GATE_DISABLE |
5860 I965_ISC_CLOCK_GATE_DISABLE |
5861 I965_FBC_CLOCK_GATE_DISABLE);
5862 I915_WRITE(RENCLK_GATE_D2, 0);
5863 I915_WRITE(MI_ARB_STATE,
5864 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
5865
5866 /* WaDisable_RenderCache_OperationalFlush:gen4 */
5867 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5868 }
5869
5870 static void gen3_init_clock_gating(struct drm_device *dev)
5871 {
5872 struct drm_i915_private *dev_priv = dev->dev_private;
5873 u32 dstate = I915_READ(D_STATE);
5874
5875 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5876 DSTATE_DOT_CLOCK_GATING;
5877 I915_WRITE(D_STATE, dstate);
5878
5879 if (IS_PINEVIEW(dev))
5880 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
5881
5882 /* IIR "flip pending" means done if this bit is set */
5883 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
5884
5885 /* interrupts should cause a wake up from C3 */
5886 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
5887
5888 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
5889 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
5890 }
5891
5892 static void i85x_init_clock_gating(struct drm_device *dev)
5893 {
5894 struct drm_i915_private *dev_priv = dev->dev_private;
5895
5896 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5897
5898 /* interrupts should cause a wake up from C3 */
5899 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
5900 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
5901 }
5902
5903 static void i830_init_clock_gating(struct drm_device *dev)
5904 {
5905 struct drm_i915_private *dev_priv = dev->dev_private;
5906
5907 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5908 }
5909
5910 void intel_init_clock_gating(struct drm_device *dev)
5911 {
5912 struct drm_i915_private *dev_priv = dev->dev_private;
5913
5914 dev_priv->display.init_clock_gating(dev);
5915 }
5916
5917 void intel_suspend_hw(struct drm_device *dev)
5918 {
5919 if (HAS_PCH_LPT(dev))
5920 lpt_suspend_hw(dev);
5921 }
5922
5923 #define for_each_power_well(i, power_well, domain_mask, power_domains) \
5924 for (i = 0; \
5925 i < (power_domains)->power_well_count && \
5926 ((power_well) = &(power_domains)->power_wells[i]); \
5927 i++) \
5928 if ((power_well)->domains & (domain_mask))
5929
5930 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
5931 for (i = (power_domains)->power_well_count - 1; \
5932 i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
5933 i--) \
5934 if ((power_well)->domains & (domain_mask))
5935
5936 /**
5937 * We should only use the power well if we explicitly asked the hardware to
5938 * enable it, so check if it's enabled and also check if we've requested it to
5939 * be enabled.
5940 */
5941 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
5942 struct i915_power_well *power_well)
5943 {
5944 return I915_READ(HSW_PWR_WELL_DRIVER) ==
5945 (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
5946 }
5947
5948 bool intel_display_power_enabled_unlocked(struct drm_i915_private *dev_priv,
5949 enum intel_display_power_domain domain)
5950 {
5951 struct i915_power_domains *power_domains;
5952 struct i915_power_well *power_well;
5953 bool is_enabled;
5954 int i;
5955
5956 if (dev_priv->pm.suspended)
5957 return false;
5958
5959 power_domains = &dev_priv->power_domains;
5960
5961 is_enabled = true;
5962
5963 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
5964 if (power_well->always_on)
5965 continue;
5966
5967 if (!power_well->hw_enabled) {
5968 is_enabled = false;
5969 break;
5970 }
5971 }
5972
5973 return is_enabled;
5974 }
5975
5976 bool intel_display_power_enabled(struct drm_i915_private *dev_priv,
5977 enum intel_display_power_domain domain)
5978 {
5979 struct i915_power_domains *power_domains;
5980 bool ret;
5981
5982 power_domains = &dev_priv->power_domains;
5983
5984 mutex_lock(&power_domains->lock);
5985 ret = intel_display_power_enabled_unlocked(dev_priv, domain);
5986 mutex_unlock(&power_domains->lock);
5987
5988 return ret;
5989 }
5990
5991 /*
5992 * Starting with Haswell, we have a "Power Down Well" that can be turned off
5993 * when not needed anymore. We have 4 registers that can request the power well
5994 * to be enabled, and it will only be disabled if none of the registers is
5995 * requesting it to be enabled.
5996 */
5997 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
5998 {
5999 struct drm_device *dev = dev_priv->dev;
6000
6001 /*
6002 * After we re-enable the power well, if we touch VGA register 0x3d5
6003 * we'll get unclaimed register interrupts. This stops after we write
6004 * anything to the VGA MSR register. The vgacon module uses this
6005 * register all the time, so if we unbind our driver and, as a
6006 * consequence, bind vgacon, we'll get stuck in an infinite loop at
6007 * console_unlock(). So make here we touch the VGA MSR register, making
6008 * sure vgacon can keep working normally without triggering interrupts
6009 * and error messages.
6010 */
6011 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
6012 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
6013 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
6014
6015 if (IS_BROADWELL(dev))
6016 gen8_irq_power_well_post_enable(dev_priv);
6017 }
6018
6019 static void hsw_set_power_well(struct drm_i915_private *dev_priv,
6020 struct i915_power_well *power_well, bool enable)
6021 {
6022 bool is_enabled, enable_requested;
6023 uint32_t tmp;
6024
6025 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
6026 is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
6027 enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
6028
6029 if (enable) {
6030 if (!enable_requested)
6031 I915_WRITE(HSW_PWR_WELL_DRIVER,
6032 HSW_PWR_WELL_ENABLE_REQUEST);
6033
6034 if (!is_enabled) {
6035 DRM_DEBUG_KMS("Enabling power well\n");
6036 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
6037 HSW_PWR_WELL_STATE_ENABLED), 20))
6038 DRM_ERROR("Timeout enabling power well\n");
6039 }
6040
6041 hsw_power_well_post_enable(dev_priv);
6042 } else {
6043 if (enable_requested) {
6044 I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
6045 POSTING_READ(HSW_PWR_WELL_DRIVER);
6046 DRM_DEBUG_KMS("Requesting to disable the power well\n");
6047 }
6048 }
6049 }
6050
6051 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
6052 struct i915_power_well *power_well)
6053 {
6054 hsw_set_power_well(dev_priv, power_well, power_well->count > 0);
6055
6056 /*
6057 * We're taking over the BIOS, so clear any requests made by it since
6058 * the driver is in charge now.
6059 */
6060 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
6061 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
6062 }
6063
6064 static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
6065 struct i915_power_well *power_well)
6066 {
6067 hsw_set_power_well(dev_priv, power_well, true);
6068 }
6069
6070 static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
6071 struct i915_power_well *power_well)
6072 {
6073 hsw_set_power_well(dev_priv, power_well, false);
6074 }
6075
6076 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
6077 struct i915_power_well *power_well)
6078 {
6079 }
6080
6081 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
6082 struct i915_power_well *power_well)
6083 {
6084 return true;
6085 }
6086
6087 static void vlv_set_power_well(struct drm_i915_private *dev_priv,
6088 struct i915_power_well *power_well, bool enable)
6089 {
6090 enum punit_power_well power_well_id = power_well->data;
6091 u32 mask;
6092 u32 state;
6093 u32 ctrl;
6094
6095 mask = PUNIT_PWRGT_MASK(power_well_id);
6096 state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) :
6097 PUNIT_PWRGT_PWR_GATE(power_well_id);
6098
6099 mutex_lock(&dev_priv->rps.hw_lock);
6100
6101 #define COND \
6102 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
6103
6104 if (COND)
6105 goto out;
6106
6107 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
6108 ctrl &= ~mask;
6109 ctrl |= state;
6110 vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
6111
6112 if (wait_for(COND, 100))
6113 DRM_ERROR("timout setting power well state %08x (%08x)\n",
6114 state,
6115 vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
6116
6117 #undef COND
6118
6119 out:
6120 mutex_unlock(&dev_priv->rps.hw_lock);
6121 }
6122
6123 static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv,
6124 struct i915_power_well *power_well)
6125 {
6126 vlv_set_power_well(dev_priv, power_well, power_well->count > 0);
6127 }
6128
6129 static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
6130 struct i915_power_well *power_well)
6131 {
6132 vlv_set_power_well(dev_priv, power_well, true);
6133 }
6134
6135 static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
6136 struct i915_power_well *power_well)
6137 {
6138 vlv_set_power_well(dev_priv, power_well, false);
6139 }
6140
6141 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
6142 struct i915_power_well *power_well)
6143 {
6144 int power_well_id = power_well->data;
6145 bool enabled = false;
6146 u32 mask;
6147 u32 state;
6148 u32 ctrl;
6149
6150 mask = PUNIT_PWRGT_MASK(power_well_id);
6151 ctrl = PUNIT_PWRGT_PWR_ON(power_well_id);
6152
6153 mutex_lock(&dev_priv->rps.hw_lock);
6154
6155 state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
6156 /*
6157 * We only ever set the power-on and power-gate states, anything
6158 * else is unexpected.
6159 */
6160 WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) &&
6161 state != PUNIT_PWRGT_PWR_GATE(power_well_id));
6162 if (state == ctrl)
6163 enabled = true;
6164
6165 /*
6166 * A transient state at this point would mean some unexpected party
6167 * is poking at the power controls too.
6168 */
6169 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
6170 WARN_ON(ctrl != state);
6171
6172 mutex_unlock(&dev_priv->rps.hw_lock);
6173
6174 return enabled;
6175 }
6176
6177 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
6178 struct i915_power_well *power_well)
6179 {
6180 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
6181
6182 vlv_set_power_well(dev_priv, power_well, true);
6183
6184 spin_lock_irq(&dev_priv->irq_lock);
6185 valleyview_enable_display_irqs(dev_priv);
6186 spin_unlock_irq(&dev_priv->irq_lock);
6187
6188 /*
6189 * During driver initialization/resume we can avoid restoring the
6190 * part of the HW/SW state that will be inited anyway explicitly.
6191 */
6192 if (dev_priv->power_domains.initializing)
6193 return;
6194
6195 intel_hpd_init(dev_priv->dev);
6196
6197 i915_redisable_vga_power_on(dev_priv->dev);
6198 }
6199
6200 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
6201 struct i915_power_well *power_well)
6202 {
6203 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
6204
6205 spin_lock_irq(&dev_priv->irq_lock);
6206 valleyview_disable_display_irqs(dev_priv);
6207 spin_unlock_irq(&dev_priv->irq_lock);
6208
6209 vlv_set_power_well(dev_priv, power_well, false);
6210 }
6211
6212 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
6213 struct i915_power_well *power_well)
6214 {
6215 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
6216
6217 /*
6218 * Enable the CRI clock source so we can get at the
6219 * display and the reference clock for VGA
6220 * hotplug / manual detection.
6221 */
6222 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
6223 DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
6224 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
6225
6226 vlv_set_power_well(dev_priv, power_well, true);
6227
6228 /*
6229 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
6230 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
6231 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
6232 * b. The other bits such as sfr settings / modesel may all
6233 * be set to 0.
6234 *
6235 * This should only be done on init and resume from S3 with
6236 * both PLLs disabled, or we risk losing DPIO and PLL
6237 * synchronization.
6238 */
6239 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
6240 }
6241
6242 static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
6243 struct i915_power_well *power_well)
6244 {
6245 struct drm_device *dev = dev_priv->dev;
6246 enum pipe pipe;
6247
6248 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
6249
6250 for_each_pipe(pipe)
6251 assert_pll_disabled(dev_priv, pipe);
6252
6253 /* Assert common reset */
6254 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST);
6255
6256 vlv_set_power_well(dev_priv, power_well, false);
6257 }
6258
6259 static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
6260 struct i915_power_well *power_well)
6261 {
6262 enum dpio_phy phy;
6263
6264 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
6265 power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
6266
6267 /*
6268 * Enable the CRI clock source so we can get at the
6269 * display and the reference clock for VGA
6270 * hotplug / manual detection.
6271 */
6272 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
6273 phy = DPIO_PHY0;
6274 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
6275 DPLL_REFA_CLK_ENABLE_VLV);
6276 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
6277 DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
6278 } else {
6279 phy = DPIO_PHY1;
6280 I915_WRITE(DPLL(PIPE_C), I915_READ(DPLL(PIPE_C)) |
6281 DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
6282 }
6283 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
6284 vlv_set_power_well(dev_priv, power_well, true);
6285
6286 /* Poll for phypwrgood signal */
6287 if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1))
6288 DRM_ERROR("Display PHY %d is not power up\n", phy);
6289
6290 I915_WRITE(DISPLAY_PHY_CONTROL,
6291 PHY_COM_LANE_RESET_DEASSERT(phy, I915_READ(DISPLAY_PHY_CONTROL)));
6292 }
6293
6294 static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
6295 struct i915_power_well *power_well)
6296 {
6297 enum dpio_phy phy;
6298
6299 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
6300 power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
6301
6302 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
6303 phy = DPIO_PHY0;
6304 assert_pll_disabled(dev_priv, PIPE_A);
6305 assert_pll_disabled(dev_priv, PIPE_B);
6306 } else {
6307 phy = DPIO_PHY1;
6308 assert_pll_disabled(dev_priv, PIPE_C);
6309 }
6310
6311 I915_WRITE(DISPLAY_PHY_CONTROL,
6312 PHY_COM_LANE_RESET_ASSERT(phy, I915_READ(DISPLAY_PHY_CONTROL)));
6313
6314 vlv_set_power_well(dev_priv, power_well, false);
6315 }
6316
6317 static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,
6318 struct i915_power_well *power_well)
6319 {
6320 enum pipe pipe = power_well->data;
6321 bool enabled;
6322 u32 state, ctrl;
6323
6324 mutex_lock(&dev_priv->rps.hw_lock);
6325
6326 state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe);
6327 /*
6328 * We only ever set the power-on and power-gate states, anything
6329 * else is unexpected.
6330 */
6331 WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe));
6332 enabled = state == DP_SSS_PWR_ON(pipe);
6333
6334 /*
6335 * A transient state at this point would mean some unexpected party
6336 * is poking at the power controls too.
6337 */
6338 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe);
6339 WARN_ON(ctrl << 16 != state);
6340
6341 mutex_unlock(&dev_priv->rps.hw_lock);
6342
6343 return enabled;
6344 }
6345
6346 static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
6347 struct i915_power_well *power_well,
6348 bool enable)
6349 {
6350 enum pipe pipe = power_well->data;
6351 u32 state;
6352 u32 ctrl;
6353
6354 state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe);
6355
6356 mutex_lock(&dev_priv->rps.hw_lock);
6357
6358 #define COND \
6359 ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state)
6360
6361 if (COND)
6362 goto out;
6363
6364 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
6365 ctrl &= ~DP_SSC_MASK(pipe);
6366 ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe);
6367 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl);
6368
6369 if (wait_for(COND, 100))
6370 DRM_ERROR("timout setting power well state %08x (%08x)\n",
6371 state,
6372 vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ));
6373
6374 #undef COND
6375
6376 out:
6377 mutex_unlock(&dev_priv->rps.hw_lock);
6378 }
6379
6380 static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv,
6381 struct i915_power_well *power_well)
6382 {
6383 chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0);
6384 }
6385
6386 static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
6387 struct i915_power_well *power_well)
6388 {
6389 WARN_ON_ONCE(power_well->data != PIPE_A &&
6390 power_well->data != PIPE_B &&
6391 power_well->data != PIPE_C);
6392
6393 chv_set_pipe_power_well(dev_priv, power_well, true);
6394 }
6395
6396 static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
6397 struct i915_power_well *power_well)
6398 {
6399 WARN_ON_ONCE(power_well->data != PIPE_A &&
6400 power_well->data != PIPE_B &&
6401 power_well->data != PIPE_C);
6402
6403 chv_set_pipe_power_well(dev_priv, power_well, false);
6404 }
6405
6406 static void check_power_well_state(struct drm_i915_private *dev_priv,
6407 struct i915_power_well *power_well)
6408 {
6409 bool enabled = power_well->ops->is_enabled(dev_priv, power_well);
6410
6411 if (power_well->always_on || !i915.disable_power_well) {
6412 if (!enabled)
6413 goto mismatch;
6414
6415 return;
6416 }
6417
6418 if (enabled != (power_well->count > 0))
6419 goto mismatch;
6420
6421 return;
6422
6423 mismatch:
6424 WARN(1, "state mismatch for '%s' (always_on %d hw state %d use-count %d disable_power_well %d\n",
6425 power_well->name, power_well->always_on, enabled,
6426 power_well->count, i915.disable_power_well);
6427 }
6428
6429 void intel_display_power_get(struct drm_i915_private *dev_priv,
6430 enum intel_display_power_domain domain)
6431 {
6432 struct i915_power_domains *power_domains;
6433 struct i915_power_well *power_well;
6434 int i;
6435
6436 intel_runtime_pm_get(dev_priv);
6437
6438 power_domains = &dev_priv->power_domains;
6439
6440 mutex_lock(&power_domains->lock);
6441
6442 for_each_power_well(i, power_well, BIT(domain), power_domains) {
6443 if (!power_well->count++) {
6444 DRM_DEBUG_KMS("enabling %s\n", power_well->name);
6445 power_well->ops->enable(dev_priv, power_well);
6446 power_well->hw_enabled = true;
6447 }
6448
6449 check_power_well_state(dev_priv, power_well);
6450 }
6451
6452 power_domains->domain_use_count[domain]++;
6453
6454 mutex_unlock(&power_domains->lock);
6455 }
6456
6457 void intel_display_power_put(struct drm_i915_private *dev_priv,
6458 enum intel_display_power_domain domain)
6459 {
6460 struct i915_power_domains *power_domains;
6461 struct i915_power_well *power_well;
6462 int i;
6463
6464 power_domains = &dev_priv->power_domains;
6465
6466 mutex_lock(&power_domains->lock);
6467
6468 WARN_ON(!power_domains->domain_use_count[domain]);
6469 power_domains->domain_use_count[domain]--;
6470
6471 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
6472 WARN_ON(!power_well->count);
6473
6474 if (!--power_well->count && i915.disable_power_well) {
6475 DRM_DEBUG_KMS("disabling %s\n", power_well->name);
6476 power_well->hw_enabled = false;
6477 power_well->ops->disable(dev_priv, power_well);
6478 }
6479
6480 check_power_well_state(dev_priv, power_well);
6481 }
6482
6483 mutex_unlock(&power_domains->lock);
6484
6485 intel_runtime_pm_put(dev_priv);
6486 }
6487
6488 static struct i915_power_domains *hsw_pwr;
6489
6490 /* Display audio driver power well request */
6491 int i915_request_power_well(void)
6492 {
6493 struct drm_i915_private *dev_priv;
6494
6495 if (!hsw_pwr)
6496 return -ENODEV;
6497
6498 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
6499 power_domains);
6500 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
6501 return 0;
6502 }
6503 EXPORT_SYMBOL_GPL(i915_request_power_well);
6504
6505 /* Display audio driver power well release */
6506 int i915_release_power_well(void)
6507 {
6508 struct drm_i915_private *dev_priv;
6509
6510 if (!hsw_pwr)
6511 return -ENODEV;
6512
6513 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
6514 power_domains);
6515 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
6516 return 0;
6517 }
6518 EXPORT_SYMBOL_GPL(i915_release_power_well);
6519
6520 /*
6521 * Private interface for the audio driver to get CDCLK in kHz.
6522 *
6523 * Caller must request power well using i915_request_power_well() prior to
6524 * making the call.
6525 */
6526 int i915_get_cdclk_freq(void)
6527 {
6528 struct drm_i915_private *dev_priv;
6529
6530 if (!hsw_pwr)
6531 return -ENODEV;
6532
6533 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
6534 power_domains);
6535
6536 return intel_ddi_get_cdclk_freq(dev_priv);
6537 }
6538 EXPORT_SYMBOL_GPL(i915_get_cdclk_freq);
6539
6540
6541 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
6542
6543 #define HSW_ALWAYS_ON_POWER_DOMAINS ( \
6544 BIT(POWER_DOMAIN_PIPE_A) | \
6545 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
6546 BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
6547 BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
6548 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6549 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6550 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6551 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6552 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
6553 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
6554 BIT(POWER_DOMAIN_PORT_CRT) | \
6555 BIT(POWER_DOMAIN_PLLS) | \
6556 BIT(POWER_DOMAIN_INIT))
6557 #define HSW_DISPLAY_POWER_DOMAINS ( \
6558 (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \
6559 BIT(POWER_DOMAIN_INIT))
6560
6561 #define BDW_ALWAYS_ON_POWER_DOMAINS ( \
6562 HSW_ALWAYS_ON_POWER_DOMAINS | \
6563 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
6564 #define BDW_DISPLAY_POWER_DOMAINS ( \
6565 (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) | \
6566 BIT(POWER_DOMAIN_INIT))
6567
6568 #define VLV_ALWAYS_ON_POWER_DOMAINS BIT(POWER_DOMAIN_INIT)
6569 #define VLV_DISPLAY_POWER_DOMAINS POWER_DOMAIN_MASK
6570
6571 #define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \
6572 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6573 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6574 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6575 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6576 BIT(POWER_DOMAIN_PORT_CRT) | \
6577 BIT(POWER_DOMAIN_INIT))
6578
6579 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \
6580 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6581 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6582 BIT(POWER_DOMAIN_INIT))
6583
6584 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \
6585 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6586 BIT(POWER_DOMAIN_INIT))
6587
6588 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \
6589 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6590 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6591 BIT(POWER_DOMAIN_INIT))
6592
6593 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \
6594 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6595 BIT(POWER_DOMAIN_INIT))
6596
6597 #define CHV_PIPE_A_POWER_DOMAINS ( \
6598 BIT(POWER_DOMAIN_PIPE_A) | \
6599 BIT(POWER_DOMAIN_INIT))
6600
6601 #define CHV_PIPE_B_POWER_DOMAINS ( \
6602 BIT(POWER_DOMAIN_PIPE_B) | \
6603 BIT(POWER_DOMAIN_INIT))
6604
6605 #define CHV_PIPE_C_POWER_DOMAINS ( \
6606 BIT(POWER_DOMAIN_PIPE_C) | \
6607 BIT(POWER_DOMAIN_INIT))
6608
6609 #define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \
6610 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6611 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6612 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6613 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6614 BIT(POWER_DOMAIN_INIT))
6615
6616 #define CHV_DPIO_CMN_D_POWER_DOMAINS ( \
6617 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
6618 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
6619 BIT(POWER_DOMAIN_INIT))
6620
6621 #define CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS ( \
6622 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
6623 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
6624 BIT(POWER_DOMAIN_INIT))
6625
6626 #define CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS ( \
6627 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
6628 BIT(POWER_DOMAIN_INIT))
6629
6630 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
6631 .sync_hw = i9xx_always_on_power_well_noop,
6632 .enable = i9xx_always_on_power_well_noop,
6633 .disable = i9xx_always_on_power_well_noop,
6634 .is_enabled = i9xx_always_on_power_well_enabled,
6635 };
6636
6637 static const struct i915_power_well_ops chv_pipe_power_well_ops = {
6638 .sync_hw = chv_pipe_power_well_sync_hw,
6639 .enable = chv_pipe_power_well_enable,
6640 .disable = chv_pipe_power_well_disable,
6641 .is_enabled = chv_pipe_power_well_enabled,
6642 };
6643
6644 static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = {
6645 .sync_hw = vlv_power_well_sync_hw,
6646 .enable = chv_dpio_cmn_power_well_enable,
6647 .disable = chv_dpio_cmn_power_well_disable,
6648 .is_enabled = vlv_power_well_enabled,
6649 };
6650
6651 static struct i915_power_well i9xx_always_on_power_well[] = {
6652 {
6653 .name = "always-on",
6654 .always_on = 1,
6655 .domains = POWER_DOMAIN_MASK,
6656 .ops = &i9xx_always_on_power_well_ops,
6657 },
6658 };
6659
6660 static const struct i915_power_well_ops hsw_power_well_ops = {
6661 .sync_hw = hsw_power_well_sync_hw,
6662 .enable = hsw_power_well_enable,
6663 .disable = hsw_power_well_disable,
6664 .is_enabled = hsw_power_well_enabled,
6665 };
6666
6667 static struct i915_power_well hsw_power_wells[] = {
6668 {
6669 .name = "always-on",
6670 .always_on = 1,
6671 .domains = HSW_ALWAYS_ON_POWER_DOMAINS,
6672 .ops = &i9xx_always_on_power_well_ops,
6673 },
6674 {
6675 .name = "display",
6676 .domains = HSW_DISPLAY_POWER_DOMAINS,
6677 .ops = &hsw_power_well_ops,
6678 },
6679 };
6680
6681 static struct i915_power_well bdw_power_wells[] = {
6682 {
6683 .name = "always-on",
6684 .always_on = 1,
6685 .domains = BDW_ALWAYS_ON_POWER_DOMAINS,
6686 .ops = &i9xx_always_on_power_well_ops,
6687 },
6688 {
6689 .name = "display",
6690 .domains = BDW_DISPLAY_POWER_DOMAINS,
6691 .ops = &hsw_power_well_ops,
6692 },
6693 };
6694
6695 static const struct i915_power_well_ops vlv_display_power_well_ops = {
6696 .sync_hw = vlv_power_well_sync_hw,
6697 .enable = vlv_display_power_well_enable,
6698 .disable = vlv_display_power_well_disable,
6699 .is_enabled = vlv_power_well_enabled,
6700 };
6701
6702 static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = {
6703 .sync_hw = vlv_power_well_sync_hw,
6704 .enable = vlv_dpio_cmn_power_well_enable,
6705 .disable = vlv_dpio_cmn_power_well_disable,
6706 .is_enabled = vlv_power_well_enabled,
6707 };
6708
6709 static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
6710 .sync_hw = vlv_power_well_sync_hw,
6711 .enable = vlv_power_well_enable,
6712 .disable = vlv_power_well_disable,
6713 .is_enabled = vlv_power_well_enabled,
6714 };
6715
6716 static struct i915_power_well vlv_power_wells[] = {
6717 {
6718 .name = "always-on",
6719 .always_on = 1,
6720 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
6721 .ops = &i9xx_always_on_power_well_ops,
6722 },
6723 {
6724 .name = "display",
6725 .domains = VLV_DISPLAY_POWER_DOMAINS,
6726 .data = PUNIT_POWER_WELL_DISP2D,
6727 .ops = &vlv_display_power_well_ops,
6728 },
6729 {
6730 .name = "dpio-tx-b-01",
6731 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6732 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6733 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6734 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6735 .ops = &vlv_dpio_power_well_ops,
6736 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
6737 },
6738 {
6739 .name = "dpio-tx-b-23",
6740 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6741 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6742 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6743 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6744 .ops = &vlv_dpio_power_well_ops,
6745 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
6746 },
6747 {
6748 .name = "dpio-tx-c-01",
6749 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6750 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6751 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6752 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6753 .ops = &vlv_dpio_power_well_ops,
6754 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
6755 },
6756 {
6757 .name = "dpio-tx-c-23",
6758 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6759 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6760 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6761 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6762 .ops = &vlv_dpio_power_well_ops,
6763 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
6764 },
6765 {
6766 .name = "dpio-common",
6767 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
6768 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
6769 .ops = &vlv_dpio_cmn_power_well_ops,
6770 },
6771 };
6772
6773 static struct i915_power_well chv_power_wells[] = {
6774 {
6775 .name = "always-on",
6776 .always_on = 1,
6777 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
6778 .ops = &i9xx_always_on_power_well_ops,
6779 },
6780 #if 0
6781 {
6782 .name = "display",
6783 .domains = VLV_DISPLAY_POWER_DOMAINS,
6784 .data = PUNIT_POWER_WELL_DISP2D,
6785 .ops = &vlv_display_power_well_ops,
6786 },
6787 {
6788 .name = "pipe-a",
6789 .domains = CHV_PIPE_A_POWER_DOMAINS,
6790 .data = PIPE_A,
6791 .ops = &chv_pipe_power_well_ops,
6792 },
6793 {
6794 .name = "pipe-b",
6795 .domains = CHV_PIPE_B_POWER_DOMAINS,
6796 .data = PIPE_B,
6797 .ops = &chv_pipe_power_well_ops,
6798 },
6799 {
6800 .name = "pipe-c",
6801 .domains = CHV_PIPE_C_POWER_DOMAINS,
6802 .data = PIPE_C,
6803 .ops = &chv_pipe_power_well_ops,
6804 },
6805 #endif
6806 {
6807 .name = "dpio-common-bc",
6808 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS,
6809 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
6810 .ops = &chv_dpio_cmn_power_well_ops,
6811 },
6812 {
6813 .name = "dpio-common-d",
6814 .domains = CHV_DPIO_CMN_D_POWER_DOMAINS,
6815 .data = PUNIT_POWER_WELL_DPIO_CMN_D,
6816 .ops = &chv_dpio_cmn_power_well_ops,
6817 },
6818 #if 0
6819 {
6820 .name = "dpio-tx-b-01",
6821 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6822 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS,
6823 .ops = &vlv_dpio_power_well_ops,
6824 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
6825 },
6826 {
6827 .name = "dpio-tx-b-23",
6828 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6829 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS,
6830 .ops = &vlv_dpio_power_well_ops,
6831 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
6832 },
6833 {
6834 .name = "dpio-tx-c-01",
6835 .domains = VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6836 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6837 .ops = &vlv_dpio_power_well_ops,
6838 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
6839 },
6840 {
6841 .name = "dpio-tx-c-23",
6842 .domains = VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6843 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6844 .ops = &vlv_dpio_power_well_ops,
6845 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
6846 },
6847 {
6848 .name = "dpio-tx-d-01",
6849 .domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS |
6850 CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS,
6851 .ops = &vlv_dpio_power_well_ops,
6852 .data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_01,
6853 },
6854 {
6855 .name = "dpio-tx-d-23",
6856 .domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS |
6857 CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS,
6858 .ops = &vlv_dpio_power_well_ops,
6859 .data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_23,
6860 },
6861 #endif
6862 };
6863
6864 static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv,
6865 enum punit_power_well power_well_id)
6866 {
6867 struct i915_power_domains *power_domains = &dev_priv->power_domains;
6868 struct i915_power_well *power_well;
6869 int i;
6870
6871 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
6872 if (power_well->data == power_well_id)
6873 return power_well;
6874 }
6875
6876 return NULL;
6877 }
6878
6879 #define set_power_wells(power_domains, __power_wells) ({ \
6880 (power_domains)->power_wells = (__power_wells); \
6881 (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \
6882 })
6883
6884 int intel_power_domains_init(struct drm_i915_private *dev_priv)
6885 {
6886 struct i915_power_domains *power_domains = &dev_priv->power_domains;
6887
6888 mutex_init(&power_domains->lock);
6889
6890 /*
6891 * The enabling order will be from lower to higher indexed wells,
6892 * the disabling order is reversed.
6893 */
6894 if (IS_HASWELL(dev_priv->dev)) {
6895 set_power_wells(power_domains, hsw_power_wells);
6896 hsw_pwr = power_domains;
6897 } else if (IS_BROADWELL(dev_priv->dev)) {
6898 set_power_wells(power_domains, bdw_power_wells);
6899 hsw_pwr = power_domains;
6900 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
6901 set_power_wells(power_domains, chv_power_wells);
6902 } else if (IS_VALLEYVIEW(dev_priv->dev)) {
6903 set_power_wells(power_domains, vlv_power_wells);
6904 } else {
6905 set_power_wells(power_domains, i9xx_always_on_power_well);
6906 }
6907
6908 return 0;
6909 }
6910
6911 void intel_power_domains_remove(struct drm_i915_private *dev_priv)
6912 {
6913 hsw_pwr = NULL;
6914 }
6915
6916 static void intel_power_domains_resume(struct drm_i915_private *dev_priv)
6917 {
6918 struct i915_power_domains *power_domains = &dev_priv->power_domains;
6919 struct i915_power_well *power_well;
6920 int i;
6921
6922 mutex_lock(&power_domains->lock);
6923 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
6924 power_well->ops->sync_hw(dev_priv, power_well);
6925 power_well->hw_enabled = power_well->ops->is_enabled(dev_priv,
6926 power_well);
6927 }
6928 mutex_unlock(&power_domains->lock);
6929 }
6930
6931 static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
6932 {
6933 struct i915_power_well *cmn =
6934 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
6935 struct i915_power_well *disp2d =
6936 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D);
6937
6938 /* nothing to do if common lane is already off */
6939 if (!cmn->ops->is_enabled(dev_priv, cmn))
6940 return;
6941
6942 /* If the display might be already active skip this */
6943 if (disp2d->ops->is_enabled(dev_priv, disp2d) &&
6944 I915_READ(DPIO_CTL) & DPIO_CMNRST)
6945 return;
6946
6947 DRM_DEBUG_KMS("toggling display PHY side reset\n");
6948
6949 /* cmnlane needs DPLL registers */
6950 disp2d->ops->enable(dev_priv, disp2d);
6951
6952 /*
6953 * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
6954 * Need to assert and de-assert PHY SB reset by gating the
6955 * common lane power, then un-gating it.
6956 * Simply ungating isn't enough to reset the PHY enough to get
6957 * ports and lanes running.
6958 */
6959 cmn->ops->disable(dev_priv, cmn);
6960 }
6961
6962 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv)
6963 {
6964 struct drm_device *dev = dev_priv->dev;
6965 struct i915_power_domains *power_domains = &dev_priv->power_domains;
6966
6967 power_domains->initializing = true;
6968
6969 if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
6970 mutex_lock(&power_domains->lock);
6971 vlv_cmnlane_wa(dev_priv);
6972 mutex_unlock(&power_domains->lock);
6973 }
6974
6975 /* For now, we need the power well to be always enabled. */
6976 intel_display_set_init_power(dev_priv, true);
6977 intel_power_domains_resume(dev_priv);
6978 power_domains->initializing = false;
6979 }
6980
6981 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)
6982 {
6983 intel_runtime_pm_get(dev_priv);
6984 }
6985
6986 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)
6987 {
6988 intel_runtime_pm_put(dev_priv);
6989 }
6990
6991 void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
6992 {
6993 struct drm_device *dev = dev_priv->dev;
6994 struct device *device = &dev->pdev->dev;
6995
6996 if (!HAS_RUNTIME_PM(dev))
6997 return;
6998
6999 pm_runtime_get_sync(device);
7000 WARN(dev_priv->pm.suspended, "Device still suspended.\n");
7001 }
7002
7003 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv)
7004 {
7005 struct drm_device *dev = dev_priv->dev;
7006 struct device *device = &dev->pdev->dev;
7007
7008 if (!HAS_RUNTIME_PM(dev))
7009 return;
7010
7011 WARN(dev_priv->pm.suspended, "Getting nosync-ref while suspended.\n");
7012 pm_runtime_get_noresume(device);
7013 }
7014
7015 void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
7016 {
7017 struct drm_device *dev = dev_priv->dev;
7018 struct device *device = &dev->pdev->dev;
7019
7020 if (!HAS_RUNTIME_PM(dev))
7021 return;
7022
7023 pm_runtime_mark_last_busy(device);
7024 pm_runtime_put_autosuspend(device);
7025 }
7026
7027 void intel_init_runtime_pm(struct drm_i915_private *dev_priv)
7028 {
7029 struct drm_device *dev = dev_priv->dev;
7030 struct device *device = &dev->pdev->dev;
7031
7032 if (!HAS_RUNTIME_PM(dev))
7033 return;
7034
7035 pm_runtime_set_active(device);
7036
7037 /*
7038 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
7039 * requirement.
7040 */
7041 if (!intel_enable_rc6(dev)) {
7042 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
7043 return;
7044 }
7045
7046 pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
7047 pm_runtime_mark_last_busy(device);
7048 pm_runtime_use_autosuspend(device);
7049
7050 pm_runtime_put_autosuspend(device);
7051 }
7052
7053 void intel_fini_runtime_pm(struct drm_i915_private *dev_priv)
7054 {
7055 struct drm_device *dev = dev_priv->dev;
7056 struct device *device = &dev->pdev->dev;
7057
7058 if (!HAS_RUNTIME_PM(dev))
7059 return;
7060
7061 if (!intel_enable_rc6(dev))
7062 return;
7063
7064 /* Make sure we're not suspended first. */
7065 pm_runtime_get_sync(device);
7066 pm_runtime_disable(device);
7067 }
7068
7069 /* Set up chip specific power management-related functions */
7070 void intel_init_pm(struct drm_device *dev)
7071 {
7072 struct drm_i915_private *dev_priv = dev->dev_private;
7073
7074 if (HAS_FBC(dev)) {
7075 if (INTEL_INFO(dev)->gen >= 7) {
7076 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
7077 dev_priv->display.enable_fbc = gen7_enable_fbc;
7078 dev_priv->display.disable_fbc = ironlake_disable_fbc;
7079 } else if (INTEL_INFO(dev)->gen >= 5) {
7080 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
7081 dev_priv->display.enable_fbc = ironlake_enable_fbc;
7082 dev_priv->display.disable_fbc = ironlake_disable_fbc;
7083 } else if (IS_GM45(dev)) {
7084 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
7085 dev_priv->display.enable_fbc = g4x_enable_fbc;
7086 dev_priv->display.disable_fbc = g4x_disable_fbc;
7087 } else {
7088 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
7089 dev_priv->display.enable_fbc = i8xx_enable_fbc;
7090 dev_priv->display.disable_fbc = i8xx_disable_fbc;
7091
7092 /* This value was pulled out of someone's hat */
7093 I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);
7094 }
7095 }
7096
7097 /* For cxsr */
7098 if (IS_PINEVIEW(dev))
7099 i915_pineview_get_mem_freq(dev);
7100 else if (IS_GEN5(dev))
7101 i915_ironlake_get_mem_freq(dev);
7102
7103 /* For FIFO watermark updates */
7104 if (HAS_PCH_SPLIT(dev)) {
7105 ilk_setup_wm_latency(dev);
7106
7107 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
7108 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7109 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7110 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
7111 dev_priv->display.update_wm = ilk_update_wm;
7112 dev_priv->display.update_sprite_wm = ilk_update_sprite_wm;
7113 } else {
7114 DRM_DEBUG_KMS("Failed to read display plane latency. "
7115 "Disable CxSR\n");
7116 }
7117
7118 if (IS_GEN5(dev))
7119 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7120 else if (IS_GEN6(dev))
7121 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7122 else if (IS_IVYBRIDGE(dev))
7123 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7124 else if (IS_HASWELL(dev))
7125 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7126 else if (INTEL_INFO(dev)->gen == 8)
7127 dev_priv->display.init_clock_gating = gen8_init_clock_gating;
7128 } else if (IS_CHERRYVIEW(dev)) {
7129 dev_priv->display.update_wm = valleyview_update_wm;
7130 dev_priv->display.init_clock_gating =
7131 cherryview_init_clock_gating;
7132 } else if (IS_VALLEYVIEW(dev)) {
7133 dev_priv->display.update_wm = valleyview_update_wm;
7134 dev_priv->display.init_clock_gating =
7135 valleyview_init_clock_gating;
7136 } else if (IS_PINEVIEW(dev)) {
7137 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7138 dev_priv->is_ddr3,
7139 dev_priv->fsb_freq,
7140 dev_priv->mem_freq)) {
7141 DRM_INFO("failed to find known CxSR latency "
7142 "(found ddr%s fsb freq %d, mem freq %d), "
7143 "disabling CxSR\n",
7144 (dev_priv->is_ddr3 == 1) ? "3" : "2",
7145 dev_priv->fsb_freq, dev_priv->mem_freq);
7146 /* Disable CxSR and never update its watermark again */
7147 intel_set_memory_cxsr(dev_priv, false);
7148 dev_priv->display.update_wm = NULL;
7149 } else
7150 dev_priv->display.update_wm = pineview_update_wm;
7151 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7152 } else if (IS_G4X(dev)) {
7153 dev_priv->display.update_wm = g4x_update_wm;
7154 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7155 } else if (IS_GEN4(dev)) {
7156 dev_priv->display.update_wm = i965_update_wm;
7157 if (IS_CRESTLINE(dev))
7158 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7159 else if (IS_BROADWATER(dev))
7160 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7161 } else if (IS_GEN3(dev)) {
7162 dev_priv->display.update_wm = i9xx_update_wm;
7163 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7164 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7165 } else if (IS_GEN2(dev)) {
7166 if (INTEL_INFO(dev)->num_pipes == 1) {
7167 dev_priv->display.update_wm = i845_update_wm;
7168 dev_priv->display.get_fifo_size = i845_get_fifo_size;
7169 } else {
7170 dev_priv->display.update_wm = i9xx_update_wm;
7171 dev_priv->display.get_fifo_size = i830_get_fifo_size;
7172 }
7173
7174 if (IS_I85X(dev) || IS_I865G(dev))
7175 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7176 else
7177 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7178 } else {
7179 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
7180 }
7181 }
7182
7183 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
7184 {
7185 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7186
7187 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7188 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7189 return -EAGAIN;
7190 }
7191
7192 I915_WRITE(GEN6_PCODE_DATA, *val);
7193 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7194
7195 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7196 500)) {
7197 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7198 return -ETIMEDOUT;
7199 }
7200
7201 *val = I915_READ(GEN6_PCODE_DATA);
7202 I915_WRITE(GEN6_PCODE_DATA, 0);
7203
7204 return 0;
7205 }
7206
7207 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
7208 {
7209 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7210
7211 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7212 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7213 return -EAGAIN;
7214 }
7215
7216 I915_WRITE(GEN6_PCODE_DATA, val);
7217 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7218
7219 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7220 500)) {
7221 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7222 return -ETIMEDOUT;
7223 }
7224
7225 I915_WRITE(GEN6_PCODE_DATA, 0);
7226
7227 return 0;
7228 }
7229
7230 static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7231 {
7232 int div;
7233
7234 /* 4 x czclk */
7235 switch (dev_priv->mem_freq) {
7236 case 800:
7237 div = 10;
7238 break;
7239 case 1066:
7240 div = 12;
7241 break;
7242 case 1333:
7243 div = 16;
7244 break;
7245 default:
7246 return -1;
7247 }
7248
7249 return DIV_ROUND_CLOSEST(dev_priv->mem_freq * (val + 6 - 0xbd), 4 * div);
7250 }
7251
7252 static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
7253 {
7254 int mul;
7255
7256 /* 4 x czclk */
7257 switch (dev_priv->mem_freq) {
7258 case 800:
7259 mul = 10;
7260 break;
7261 case 1066:
7262 mul = 12;
7263 break;
7264 case 1333:
7265 mul = 16;
7266 break;
7267 default:
7268 return -1;
7269 }
7270
7271 return DIV_ROUND_CLOSEST(4 * mul * val, dev_priv->mem_freq) + 0xbd - 6;
7272 }
7273
7274 static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
7275 {
7276 int div, freq;
7277
7278 switch (dev_priv->rps.cz_freq) {
7279 case 200:
7280 div = 5;
7281 break;
7282 case 267:
7283 div = 6;
7284 break;
7285 case 320:
7286 case 333:
7287 case 400:
7288 div = 8;
7289 break;
7290 default:
7291 return -1;
7292 }
7293
7294 freq = (DIV_ROUND_CLOSEST((dev_priv->rps.cz_freq * val), 2 * div) / 2);
7295
7296 return freq;
7297 }
7298
7299 static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
7300 {
7301 int mul, opcode;
7302
7303 switch (dev_priv->rps.cz_freq) {
7304 case 200:
7305 mul = 5;
7306 break;
7307 case 267:
7308 mul = 6;
7309 break;
7310 case 320:
7311 case 333:
7312 case 400:
7313 mul = 8;
7314 break;
7315 default:
7316 return -1;
7317 }
7318
7319 opcode = (DIV_ROUND_CLOSEST((val * 2 * mul), dev_priv->rps.cz_freq) * 2);
7320
7321 return opcode;
7322 }
7323
7324 int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val)
7325 {
7326 int ret = -1;
7327
7328 if (IS_CHERRYVIEW(dev_priv->dev))
7329 ret = chv_gpu_freq(dev_priv, val);
7330 else if (IS_VALLEYVIEW(dev_priv->dev))
7331 ret = byt_gpu_freq(dev_priv, val);
7332
7333 return ret;
7334 }
7335
7336 int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val)
7337 {
7338 int ret = -1;
7339
7340 if (IS_CHERRYVIEW(dev_priv->dev))
7341 ret = chv_freq_opcode(dev_priv, val);
7342 else if (IS_VALLEYVIEW(dev_priv->dev))
7343 ret = byt_freq_opcode(dev_priv, val);
7344
7345 return ret;
7346 }
7347
7348 void intel_pm_setup(struct drm_device *dev)
7349 {
7350 struct drm_i915_private *dev_priv = dev->dev_private;
7351
7352 mutex_init(&dev_priv->rps.hw_lock);
7353
7354 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
7355 intel_gen6_powersave_work);
7356
7357 dev_priv->pm.suspended = false;
7358 dev_priv->pm._irqs_disabled = false;
7359 }
Linux kernel - Deliverables
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