2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
28 #include <linux/cpufreq.h>
30 #include "intel_drv.h"
31 #include "../../../platform/x86/intel_ips.h"
32 #include <linux/module.h>
33 #include <linux/vgaarb.h>
34 #include <drm/i915_powerwell.h>
35 #include <linux/pm_runtime.h>
38 * RC6 is a special power stage which allows the GPU to enter an very
39 * low-voltage mode when idle, using down to 0V while at this stage. This
40 * stage is entered automatically when the GPU is idle when RC6 support is
41 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
43 * There are different RC6 modes available in Intel GPU, which differentiate
44 * among each other with the latency required to enter and leave RC6 and
45 * voltage consumed by the GPU in different states.
47 * The combination of the following flags define which states GPU is allowed
48 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
49 * RC6pp is deepest RC6. Their support by hardware varies according to the
50 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
51 * which brings the most power savings; deeper states save more power, but
52 * require higher latency to switch to and wake up.
54 #define INTEL_RC6_ENABLE (1<<0)
55 #define INTEL_RC6p_ENABLE (1<<1)
56 #define INTEL_RC6pp_ENABLE (1<<2)
58 /* FBC, or Frame Buffer Compression, is a technique employed to compress the
59 * framebuffer contents in-memory, aiming at reducing the required bandwidth
60 * during in-memory transfers and, therefore, reduce the power packet.
62 * The benefits of FBC are mostly visible with solid backgrounds and
63 * variation-less patterns.
65 * FBC-related functionality can be enabled by the means of the
66 * i915.i915_enable_fbc parameter
69 static void i8xx_disable_fbc(struct drm_device
*dev
)
71 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
74 /* Disable compression */
75 fbc_ctl
= I915_READ(FBC_CONTROL
);
76 if ((fbc_ctl
& FBC_CTL_EN
) == 0)
79 fbc_ctl
&= ~FBC_CTL_EN
;
80 I915_WRITE(FBC_CONTROL
, fbc_ctl
);
82 /* Wait for compressing bit to clear */
83 if (wait_for((I915_READ(FBC_STATUS
) & FBC_STAT_COMPRESSING
) == 0, 10)) {
84 DRM_DEBUG_KMS("FBC idle timed out\n");
88 DRM_DEBUG_KMS("disabled FBC\n");
91 static void i8xx_enable_fbc(struct drm_crtc
*crtc
)
93 struct drm_device
*dev
= crtc
->dev
;
94 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
95 struct drm_framebuffer
*fb
= crtc
->primary
->fb
;
96 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
97 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
102 cfb_pitch
= dev_priv
->fbc
.size
/ FBC_LL_SIZE
;
103 if (fb
->pitches
[0] < cfb_pitch
)
104 cfb_pitch
= fb
->pitches
[0];
106 /* FBC_CTL wants 32B or 64B units */
108 cfb_pitch
= (cfb_pitch
/ 32) - 1;
110 cfb_pitch
= (cfb_pitch
/ 64) - 1;
113 for (i
= 0; i
< (FBC_LL_SIZE
/ 32) + 1; i
++)
114 I915_WRITE(FBC_TAG
+ (i
* 4), 0);
120 fbc_ctl2
= FBC_CTL_FENCE_DBL
| FBC_CTL_IDLE_IMM
| FBC_CTL_CPU_FENCE
;
121 fbc_ctl2
|= FBC_CTL_PLANE(intel_crtc
->plane
);
122 I915_WRITE(FBC_CONTROL2
, fbc_ctl2
);
123 I915_WRITE(FBC_FENCE_OFF
, crtc
->y
);
127 fbc_ctl
= I915_READ(FBC_CONTROL
);
128 fbc_ctl
&= 0x3fff << FBC_CTL_INTERVAL_SHIFT
;
129 fbc_ctl
|= FBC_CTL_EN
| FBC_CTL_PERIODIC
;
131 fbc_ctl
|= FBC_CTL_C3_IDLE
; /* 945 needs special SR handling */
132 fbc_ctl
|= (cfb_pitch
& 0xff) << FBC_CTL_STRIDE_SHIFT
;
133 fbc_ctl
|= obj
->fence_reg
;
134 I915_WRITE(FBC_CONTROL
, fbc_ctl
);
136 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c\n",
137 cfb_pitch
, crtc
->y
, plane_name(intel_crtc
->plane
));
140 static bool i8xx_fbc_enabled(struct drm_device
*dev
)
142 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
144 return I915_READ(FBC_CONTROL
) & FBC_CTL_EN
;
147 static void g4x_enable_fbc(struct drm_crtc
*crtc
)
149 struct drm_device
*dev
= crtc
->dev
;
150 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
151 struct drm_framebuffer
*fb
= crtc
->primary
->fb
;
152 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
153 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
156 dpfc_ctl
= DPFC_CTL_PLANE(intel_crtc
->plane
) | DPFC_SR_EN
;
157 if (drm_format_plane_cpp(fb
->pixel_format
, 0) == 2)
158 dpfc_ctl
|= DPFC_CTL_LIMIT_2X
;
160 dpfc_ctl
|= DPFC_CTL_LIMIT_1X
;
161 dpfc_ctl
|= DPFC_CTL_FENCE_EN
| obj
->fence_reg
;
163 I915_WRITE(DPFC_FENCE_YOFF
, crtc
->y
);
166 I915_WRITE(DPFC_CONTROL
, dpfc_ctl
| DPFC_CTL_EN
);
168 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc
->plane
));
171 static void g4x_disable_fbc(struct drm_device
*dev
)
173 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
176 /* Disable compression */
177 dpfc_ctl
= I915_READ(DPFC_CONTROL
);
178 if (dpfc_ctl
& DPFC_CTL_EN
) {
179 dpfc_ctl
&= ~DPFC_CTL_EN
;
180 I915_WRITE(DPFC_CONTROL
, dpfc_ctl
);
182 DRM_DEBUG_KMS("disabled FBC\n");
186 static bool g4x_fbc_enabled(struct drm_device
*dev
)
188 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
190 return I915_READ(DPFC_CONTROL
) & DPFC_CTL_EN
;
193 static void sandybridge_blit_fbc_update(struct drm_device
*dev
)
195 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
198 /* Make sure blitter notifies FBC of writes */
200 /* Blitter is part of Media powerwell on VLV. No impact of
201 * his param in other platforms for now */
202 gen6_gt_force_wake_get(dev_priv
, FORCEWAKE_MEDIA
);
204 blt_ecoskpd
= I915_READ(GEN6_BLITTER_ECOSKPD
);
205 blt_ecoskpd
|= GEN6_BLITTER_FBC_NOTIFY
<<
206 GEN6_BLITTER_LOCK_SHIFT
;
207 I915_WRITE(GEN6_BLITTER_ECOSKPD
, blt_ecoskpd
);
208 blt_ecoskpd
|= GEN6_BLITTER_FBC_NOTIFY
;
209 I915_WRITE(GEN6_BLITTER_ECOSKPD
, blt_ecoskpd
);
210 blt_ecoskpd
&= ~(GEN6_BLITTER_FBC_NOTIFY
<<
211 GEN6_BLITTER_LOCK_SHIFT
);
212 I915_WRITE(GEN6_BLITTER_ECOSKPD
, blt_ecoskpd
);
213 POSTING_READ(GEN6_BLITTER_ECOSKPD
);
215 gen6_gt_force_wake_put(dev_priv
, FORCEWAKE_MEDIA
);
218 static void ironlake_enable_fbc(struct drm_crtc
*crtc
)
220 struct drm_device
*dev
= crtc
->dev
;
221 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
222 struct drm_framebuffer
*fb
= crtc
->primary
->fb
;
223 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
224 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
227 dpfc_ctl
= DPFC_CTL_PLANE(intel_crtc
->plane
);
228 if (drm_format_plane_cpp(fb
->pixel_format
, 0) == 2)
229 dev_priv
->fbc
.threshold
++;
231 switch (dev_priv
->fbc
.threshold
) {
234 dpfc_ctl
|= DPFC_CTL_LIMIT_4X
;
237 dpfc_ctl
|= DPFC_CTL_LIMIT_2X
;
240 dpfc_ctl
|= DPFC_CTL_LIMIT_1X
;
243 dpfc_ctl
|= DPFC_CTL_FENCE_EN
;
245 dpfc_ctl
|= obj
->fence_reg
;
247 I915_WRITE(ILK_DPFC_FENCE_YOFF
, crtc
->y
);
248 I915_WRITE(ILK_FBC_RT_BASE
, i915_gem_obj_ggtt_offset(obj
) | ILK_FBC_RT_VALID
);
250 I915_WRITE(ILK_DPFC_CONTROL
, dpfc_ctl
| DPFC_CTL_EN
);
253 I915_WRITE(SNB_DPFC_CTL_SA
,
254 SNB_CPU_FENCE_ENABLE
| obj
->fence_reg
);
255 I915_WRITE(DPFC_CPU_FENCE_OFFSET
, crtc
->y
);
256 sandybridge_blit_fbc_update(dev
);
259 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc
->plane
));
262 static void ironlake_disable_fbc(struct drm_device
*dev
)
264 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
267 /* Disable compression */
268 dpfc_ctl
= I915_READ(ILK_DPFC_CONTROL
);
269 if (dpfc_ctl
& DPFC_CTL_EN
) {
270 dpfc_ctl
&= ~DPFC_CTL_EN
;
271 I915_WRITE(ILK_DPFC_CONTROL
, dpfc_ctl
);
273 DRM_DEBUG_KMS("disabled FBC\n");
277 static bool ironlake_fbc_enabled(struct drm_device
*dev
)
279 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
281 return I915_READ(ILK_DPFC_CONTROL
) & DPFC_CTL_EN
;
284 static void gen7_enable_fbc(struct drm_crtc
*crtc
)
286 struct drm_device
*dev
= crtc
->dev
;
287 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
288 struct drm_framebuffer
*fb
= crtc
->primary
->fb
;
289 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
290 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
293 dpfc_ctl
= IVB_DPFC_CTL_PLANE(intel_crtc
->plane
);
294 if (drm_format_plane_cpp(fb
->pixel_format
, 0) == 2)
295 dev_priv
->fbc
.threshold
++;
297 switch (dev_priv
->fbc
.threshold
) {
300 dpfc_ctl
|= DPFC_CTL_LIMIT_4X
;
303 dpfc_ctl
|= DPFC_CTL_LIMIT_2X
;
306 dpfc_ctl
|= DPFC_CTL_LIMIT_1X
;
310 dpfc_ctl
|= IVB_DPFC_CTL_FENCE_EN
;
312 I915_WRITE(ILK_DPFC_CONTROL
, dpfc_ctl
| DPFC_CTL_EN
);
314 if (IS_IVYBRIDGE(dev
)) {
315 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
316 I915_WRITE(ILK_DISPLAY_CHICKEN1
,
317 I915_READ(ILK_DISPLAY_CHICKEN1
) |
320 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
321 I915_WRITE(CHICKEN_PIPESL_1(intel_crtc
->pipe
),
322 I915_READ(CHICKEN_PIPESL_1(intel_crtc
->pipe
)) |
326 I915_WRITE(SNB_DPFC_CTL_SA
,
327 SNB_CPU_FENCE_ENABLE
| obj
->fence_reg
);
328 I915_WRITE(DPFC_CPU_FENCE_OFFSET
, crtc
->y
);
330 sandybridge_blit_fbc_update(dev
);
332 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc
->plane
));
335 bool intel_fbc_enabled(struct drm_device
*dev
)
337 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
339 if (!dev_priv
->display
.fbc_enabled
)
342 return dev_priv
->display
.fbc_enabled(dev
);
345 static void intel_fbc_work_fn(struct work_struct
*__work
)
347 struct intel_fbc_work
*work
=
348 container_of(to_delayed_work(__work
),
349 struct intel_fbc_work
, work
);
350 struct drm_device
*dev
= work
->crtc
->dev
;
351 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
353 mutex_lock(&dev
->struct_mutex
);
354 if (work
== dev_priv
->fbc
.fbc_work
) {
355 /* Double check that we haven't switched fb without cancelling
358 if (work
->crtc
->primary
->fb
== work
->fb
) {
359 dev_priv
->display
.enable_fbc(work
->crtc
);
361 dev_priv
->fbc
.plane
= to_intel_crtc(work
->crtc
)->plane
;
362 dev_priv
->fbc
.fb_id
= work
->crtc
->primary
->fb
->base
.id
;
363 dev_priv
->fbc
.y
= work
->crtc
->y
;
366 dev_priv
->fbc
.fbc_work
= NULL
;
368 mutex_unlock(&dev
->struct_mutex
);
373 static void intel_cancel_fbc_work(struct drm_i915_private
*dev_priv
)
375 if (dev_priv
->fbc
.fbc_work
== NULL
)
378 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
380 /* Synchronisation is provided by struct_mutex and checking of
381 * dev_priv->fbc.fbc_work, so we can perform the cancellation
382 * entirely asynchronously.
384 if (cancel_delayed_work(&dev_priv
->fbc
.fbc_work
->work
))
385 /* tasklet was killed before being run, clean up */
386 kfree(dev_priv
->fbc
.fbc_work
);
388 /* Mark the work as no longer wanted so that if it does
389 * wake-up (because the work was already running and waiting
390 * for our mutex), it will discover that is no longer
393 dev_priv
->fbc
.fbc_work
= NULL
;
396 static void intel_enable_fbc(struct drm_crtc
*crtc
)
398 struct intel_fbc_work
*work
;
399 struct drm_device
*dev
= crtc
->dev
;
400 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
402 if (!dev_priv
->display
.enable_fbc
)
405 intel_cancel_fbc_work(dev_priv
);
407 work
= kzalloc(sizeof(*work
), GFP_KERNEL
);
409 DRM_ERROR("Failed to allocate FBC work structure\n");
410 dev_priv
->display
.enable_fbc(crtc
);
415 work
->fb
= crtc
->primary
->fb
;
416 INIT_DELAYED_WORK(&work
->work
, intel_fbc_work_fn
);
418 dev_priv
->fbc
.fbc_work
= work
;
420 /* Delay the actual enabling to let pageflipping cease and the
421 * display to settle before starting the compression. Note that
422 * this delay also serves a second purpose: it allows for a
423 * vblank to pass after disabling the FBC before we attempt
424 * to modify the control registers.
426 * A more complicated solution would involve tracking vblanks
427 * following the termination of the page-flipping sequence
428 * and indeed performing the enable as a co-routine and not
429 * waiting synchronously upon the vblank.
431 * WaFbcWaitForVBlankBeforeEnable:ilk,snb
433 schedule_delayed_work(&work
->work
, msecs_to_jiffies(50));
436 void intel_disable_fbc(struct drm_device
*dev
)
438 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
440 intel_cancel_fbc_work(dev_priv
);
442 if (!dev_priv
->display
.disable_fbc
)
445 dev_priv
->display
.disable_fbc(dev
);
446 dev_priv
->fbc
.plane
= -1;
449 static bool set_no_fbc_reason(struct drm_i915_private
*dev_priv
,
450 enum no_fbc_reason reason
)
452 if (dev_priv
->fbc
.no_fbc_reason
== reason
)
455 dev_priv
->fbc
.no_fbc_reason
= reason
;
460 * intel_update_fbc - enable/disable FBC as needed
461 * @dev: the drm_device
463 * Set up the framebuffer compression hardware at mode set time. We
464 * enable it if possible:
465 * - plane A only (on pre-965)
466 * - no pixel mulitply/line duplication
467 * - no alpha buffer discard
469 * - framebuffer <= max_hdisplay in width, max_vdisplay in height
471 * We can't assume that any compression will take place (worst case),
472 * so the compressed buffer has to be the same size as the uncompressed
473 * one. It also must reside (along with the line length buffer) in
476 * We need to enable/disable FBC on a global basis.
478 void intel_update_fbc(struct drm_device
*dev
)
480 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
481 struct drm_crtc
*crtc
= NULL
, *tmp_crtc
;
482 struct intel_crtc
*intel_crtc
;
483 struct drm_framebuffer
*fb
;
484 struct drm_i915_gem_object
*obj
;
485 const struct drm_display_mode
*adjusted_mode
;
486 unsigned int max_width
, max_height
;
489 set_no_fbc_reason(dev_priv
, FBC_UNSUPPORTED
);
493 if (!i915
.powersave
) {
494 if (set_no_fbc_reason(dev_priv
, FBC_MODULE_PARAM
))
495 DRM_DEBUG_KMS("fbc disabled per module param\n");
500 * If FBC is already on, we just have to verify that we can
501 * keep it that way...
502 * Need to disable if:
503 * - more than one pipe is active
504 * - changing FBC params (stride, fence, mode)
505 * - new fb is too large to fit in compressed buffer
506 * - going to an unsupported config (interlace, pixel multiply, etc.)
508 for_each_crtc(dev
, tmp_crtc
) {
509 if (intel_crtc_active(tmp_crtc
) &&
510 to_intel_crtc(tmp_crtc
)->primary_enabled
) {
512 if (set_no_fbc_reason(dev_priv
, FBC_MULTIPLE_PIPES
))
513 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
520 if (!crtc
|| crtc
->primary
->fb
== NULL
) {
521 if (set_no_fbc_reason(dev_priv
, FBC_NO_OUTPUT
))
522 DRM_DEBUG_KMS("no output, disabling\n");
526 intel_crtc
= to_intel_crtc(crtc
);
527 fb
= crtc
->primary
->fb
;
528 obj
= intel_fb_obj(fb
);
529 adjusted_mode
= &intel_crtc
->config
.adjusted_mode
;
531 if (i915
.enable_fbc
< 0) {
532 if (set_no_fbc_reason(dev_priv
, FBC_CHIP_DEFAULT
))
533 DRM_DEBUG_KMS("disabled per chip default\n");
536 if (!i915
.enable_fbc
) {
537 if (set_no_fbc_reason(dev_priv
, FBC_MODULE_PARAM
))
538 DRM_DEBUG_KMS("fbc disabled per module param\n");
541 if ((adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) ||
542 (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLSCAN
)) {
543 if (set_no_fbc_reason(dev_priv
, FBC_UNSUPPORTED_MODE
))
544 DRM_DEBUG_KMS("mode incompatible with compression, "
549 if (INTEL_INFO(dev
)->gen
>= 8 || IS_HASWELL(dev
)) {
552 } else if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5) {
559 if (intel_crtc
->config
.pipe_src_w
> max_width
||
560 intel_crtc
->config
.pipe_src_h
> max_height
) {
561 if (set_no_fbc_reason(dev_priv
, FBC_MODE_TOO_LARGE
))
562 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
565 if ((INTEL_INFO(dev
)->gen
< 4 || HAS_DDI(dev
)) &&
566 intel_crtc
->plane
!= PLANE_A
) {
567 if (set_no_fbc_reason(dev_priv
, FBC_BAD_PLANE
))
568 DRM_DEBUG_KMS("plane not A, disabling compression\n");
572 /* The use of a CPU fence is mandatory in order to detect writes
573 * by the CPU to the scanout and trigger updates to the FBC.
575 if (obj
->tiling_mode
!= I915_TILING_X
||
576 obj
->fence_reg
== I915_FENCE_REG_NONE
) {
577 if (set_no_fbc_reason(dev_priv
, FBC_NOT_TILED
))
578 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
582 /* If the kernel debugger is active, always disable compression */
586 if (i915_gem_stolen_setup_compression(dev
, obj
->base
.size
,
587 drm_format_plane_cpp(fb
->pixel_format
, 0))) {
588 if (set_no_fbc_reason(dev_priv
, FBC_STOLEN_TOO_SMALL
))
589 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
593 /* If the scanout has not changed, don't modify the FBC settings.
594 * Note that we make the fundamental assumption that the fb->obj
595 * cannot be unpinned (and have its GTT offset and fence revoked)
596 * without first being decoupled from the scanout and FBC disabled.
598 if (dev_priv
->fbc
.plane
== intel_crtc
->plane
&&
599 dev_priv
->fbc
.fb_id
== fb
->base
.id
&&
600 dev_priv
->fbc
.y
== crtc
->y
)
603 if (intel_fbc_enabled(dev
)) {
604 /* We update FBC along two paths, after changing fb/crtc
605 * configuration (modeswitching) and after page-flipping
606 * finishes. For the latter, we know that not only did
607 * we disable the FBC at the start of the page-flip
608 * sequence, but also more than one vblank has passed.
610 * For the former case of modeswitching, it is possible
611 * to switch between two FBC valid configurations
612 * instantaneously so we do need to disable the FBC
613 * before we can modify its control registers. We also
614 * have to wait for the next vblank for that to take
615 * effect. However, since we delay enabling FBC we can
616 * assume that a vblank has passed since disabling and
617 * that we can safely alter the registers in the deferred
620 * In the scenario that we go from a valid to invalid
621 * and then back to valid FBC configuration we have
622 * no strict enforcement that a vblank occurred since
623 * disabling the FBC. However, along all current pipe
624 * disabling paths we do need to wait for a vblank at
625 * some point. And we wait before enabling FBC anyway.
627 DRM_DEBUG_KMS("disabling active FBC for update\n");
628 intel_disable_fbc(dev
);
631 intel_enable_fbc(crtc
);
632 dev_priv
->fbc
.no_fbc_reason
= FBC_OK
;
636 /* Multiple disables should be harmless */
637 if (intel_fbc_enabled(dev
)) {
638 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
639 intel_disable_fbc(dev
);
641 i915_gem_stolen_cleanup_compression(dev
);
644 static void i915_pineview_get_mem_freq(struct drm_device
*dev
)
646 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
649 tmp
= I915_READ(CLKCFG
);
651 switch (tmp
& CLKCFG_FSB_MASK
) {
653 dev_priv
->fsb_freq
= 533; /* 133*4 */
656 dev_priv
->fsb_freq
= 800; /* 200*4 */
659 dev_priv
->fsb_freq
= 667; /* 167*4 */
662 dev_priv
->fsb_freq
= 400; /* 100*4 */
666 switch (tmp
& CLKCFG_MEM_MASK
) {
668 dev_priv
->mem_freq
= 533;
671 dev_priv
->mem_freq
= 667;
674 dev_priv
->mem_freq
= 800;
678 /* detect pineview DDR3 setting */
679 tmp
= I915_READ(CSHRDDR3CTL
);
680 dev_priv
->is_ddr3
= (tmp
& CSHRDDR3CTL_DDR3
) ? 1 : 0;
683 static void i915_ironlake_get_mem_freq(struct drm_device
*dev
)
685 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
688 ddrpll
= I915_READ16(DDRMPLL1
);
689 csipll
= I915_READ16(CSIPLL0
);
691 switch (ddrpll
& 0xff) {
693 dev_priv
->mem_freq
= 800;
696 dev_priv
->mem_freq
= 1066;
699 dev_priv
->mem_freq
= 1333;
702 dev_priv
->mem_freq
= 1600;
705 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
707 dev_priv
->mem_freq
= 0;
711 dev_priv
->ips
.r_t
= dev_priv
->mem_freq
;
713 switch (csipll
& 0x3ff) {
715 dev_priv
->fsb_freq
= 3200;
718 dev_priv
->fsb_freq
= 3733;
721 dev_priv
->fsb_freq
= 4266;
724 dev_priv
->fsb_freq
= 4800;
727 dev_priv
->fsb_freq
= 5333;
730 dev_priv
->fsb_freq
= 5866;
733 dev_priv
->fsb_freq
= 6400;
736 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
738 dev_priv
->fsb_freq
= 0;
742 if (dev_priv
->fsb_freq
== 3200) {
743 dev_priv
->ips
.c_m
= 0;
744 } else if (dev_priv
->fsb_freq
> 3200 && dev_priv
->fsb_freq
<= 4800) {
745 dev_priv
->ips
.c_m
= 1;
747 dev_priv
->ips
.c_m
= 2;
751 static const struct cxsr_latency cxsr_latency_table
[] = {
752 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
753 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
754 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
755 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
756 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
758 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
759 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
760 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
761 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
762 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
764 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
765 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
766 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
767 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
768 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
770 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
771 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
772 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
773 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
774 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
776 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
777 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
778 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
779 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
780 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
782 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
783 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
784 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
785 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
786 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
789 static const struct cxsr_latency
*intel_get_cxsr_latency(int is_desktop
,
794 const struct cxsr_latency
*latency
;
797 if (fsb
== 0 || mem
== 0)
800 for (i
= 0; i
< ARRAY_SIZE(cxsr_latency_table
); i
++) {
801 latency
= &cxsr_latency_table
[i
];
802 if (is_desktop
== latency
->is_desktop
&&
803 is_ddr3
== latency
->is_ddr3
&&
804 fsb
== latency
->fsb_freq
&& mem
== latency
->mem_freq
)
808 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
813 void intel_set_memory_cxsr(struct drm_i915_private
*dev_priv
, bool enable
)
815 struct drm_device
*dev
= dev_priv
->dev
;
818 if (IS_VALLEYVIEW(dev
)) {
819 I915_WRITE(FW_BLC_SELF_VLV
, enable
? FW_CSPWRDWNEN
: 0);
820 } else if (IS_G4X(dev
) || IS_CRESTLINE(dev
)) {
821 I915_WRITE(FW_BLC_SELF
, enable
? FW_BLC_SELF_EN
: 0);
822 } else if (IS_PINEVIEW(dev
)) {
823 val
= I915_READ(DSPFW3
) & ~PINEVIEW_SELF_REFRESH_EN
;
824 val
|= enable
? PINEVIEW_SELF_REFRESH_EN
: 0;
825 I915_WRITE(DSPFW3
, val
);
826 } else if (IS_I945G(dev
) || IS_I945GM(dev
)) {
827 val
= enable
? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN
) :
828 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN
);
829 I915_WRITE(FW_BLC_SELF
, val
);
830 } else if (IS_I915GM(dev
)) {
831 val
= enable
? _MASKED_BIT_ENABLE(INSTPM_SELF_EN
) :
832 _MASKED_BIT_DISABLE(INSTPM_SELF_EN
);
833 I915_WRITE(INSTPM
, val
);
838 DRM_DEBUG_KMS("memory self-refresh is %s\n",
839 enable
? "enabled" : "disabled");
843 * Latency for FIFO fetches is dependent on several factors:
844 * - memory configuration (speed, channels)
846 * - current MCH state
847 * It can be fairly high in some situations, so here we assume a fairly
848 * pessimal value. It's a tradeoff between extra memory fetches (if we
849 * set this value too high, the FIFO will fetch frequently to stay full)
850 * and power consumption (set it too low to save power and we might see
851 * FIFO underruns and display "flicker").
853 * A value of 5us seems to be a good balance; safe for very low end
854 * platforms but not overly aggressive on lower latency configs.
856 static const int latency_ns
= 5000;
858 static int i9xx_get_fifo_size(struct drm_device
*dev
, int plane
)
860 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
861 uint32_t dsparb
= I915_READ(DSPARB
);
864 size
= dsparb
& 0x7f;
866 size
= ((dsparb
>> DSPARB_CSTART_SHIFT
) & 0x7f) - size
;
868 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
869 plane
? "B" : "A", size
);
874 static int i830_get_fifo_size(struct drm_device
*dev
, int plane
)
876 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
877 uint32_t dsparb
= I915_READ(DSPARB
);
880 size
= dsparb
& 0x1ff;
882 size
= ((dsparb
>> DSPARB_BEND_SHIFT
) & 0x1ff) - size
;
883 size
>>= 1; /* Convert to cachelines */
885 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
886 plane
? "B" : "A", size
);
891 static int i845_get_fifo_size(struct drm_device
*dev
, int plane
)
893 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
894 uint32_t dsparb
= I915_READ(DSPARB
);
897 size
= dsparb
& 0x7f;
898 size
>>= 2; /* Convert to cachelines */
900 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
907 /* Pineview has different values for various configs */
908 static const struct intel_watermark_params pineview_display_wm
= {
909 .fifo_size
= PINEVIEW_DISPLAY_FIFO
,
910 .max_wm
= PINEVIEW_MAX_WM
,
911 .default_wm
= PINEVIEW_DFT_WM
,
912 .guard_size
= PINEVIEW_GUARD_WM
,
913 .cacheline_size
= PINEVIEW_FIFO_LINE_SIZE
,
915 static const struct intel_watermark_params pineview_display_hplloff_wm
= {
916 .fifo_size
= PINEVIEW_DISPLAY_FIFO
,
917 .max_wm
= PINEVIEW_MAX_WM
,
918 .default_wm
= PINEVIEW_DFT_HPLLOFF_WM
,
919 .guard_size
= PINEVIEW_GUARD_WM
,
920 .cacheline_size
= PINEVIEW_FIFO_LINE_SIZE
,
922 static const struct intel_watermark_params pineview_cursor_wm
= {
923 .fifo_size
= PINEVIEW_CURSOR_FIFO
,
924 .max_wm
= PINEVIEW_CURSOR_MAX_WM
,
925 .default_wm
= PINEVIEW_CURSOR_DFT_WM
,
926 .guard_size
= PINEVIEW_CURSOR_GUARD_WM
,
927 .cacheline_size
= PINEVIEW_FIFO_LINE_SIZE
,
929 static const struct intel_watermark_params pineview_cursor_hplloff_wm
= {
930 .fifo_size
= PINEVIEW_CURSOR_FIFO
,
931 .max_wm
= PINEVIEW_CURSOR_MAX_WM
,
932 .default_wm
= PINEVIEW_CURSOR_DFT_WM
,
933 .guard_size
= PINEVIEW_CURSOR_GUARD_WM
,
934 .cacheline_size
= PINEVIEW_FIFO_LINE_SIZE
,
936 static const struct intel_watermark_params g4x_wm_info
= {
937 .fifo_size
= G4X_FIFO_SIZE
,
938 .max_wm
= G4X_MAX_WM
,
939 .default_wm
= G4X_MAX_WM
,
941 .cacheline_size
= G4X_FIFO_LINE_SIZE
,
943 static const struct intel_watermark_params g4x_cursor_wm_info
= {
944 .fifo_size
= I965_CURSOR_FIFO
,
945 .max_wm
= I965_CURSOR_MAX_WM
,
946 .default_wm
= I965_CURSOR_DFT_WM
,
948 .cacheline_size
= G4X_FIFO_LINE_SIZE
,
950 static const struct intel_watermark_params valleyview_wm_info
= {
951 .fifo_size
= VALLEYVIEW_FIFO_SIZE
,
952 .max_wm
= VALLEYVIEW_MAX_WM
,
953 .default_wm
= VALLEYVIEW_MAX_WM
,
955 .cacheline_size
= G4X_FIFO_LINE_SIZE
,
957 static const struct intel_watermark_params valleyview_cursor_wm_info
= {
958 .fifo_size
= I965_CURSOR_FIFO
,
959 .max_wm
= VALLEYVIEW_CURSOR_MAX_WM
,
960 .default_wm
= I965_CURSOR_DFT_WM
,
962 .cacheline_size
= G4X_FIFO_LINE_SIZE
,
964 static const struct intel_watermark_params i965_cursor_wm_info
= {
965 .fifo_size
= I965_CURSOR_FIFO
,
966 .max_wm
= I965_CURSOR_MAX_WM
,
967 .default_wm
= I965_CURSOR_DFT_WM
,
969 .cacheline_size
= I915_FIFO_LINE_SIZE
,
971 static const struct intel_watermark_params i945_wm_info
= {
972 .fifo_size
= I945_FIFO_SIZE
,
973 .max_wm
= I915_MAX_WM
,
976 .cacheline_size
= I915_FIFO_LINE_SIZE
,
978 static const struct intel_watermark_params i915_wm_info
= {
979 .fifo_size
= I915_FIFO_SIZE
,
980 .max_wm
= I915_MAX_WM
,
983 .cacheline_size
= I915_FIFO_LINE_SIZE
,
985 static const struct intel_watermark_params i830_wm_info
= {
986 .fifo_size
= I855GM_FIFO_SIZE
,
987 .max_wm
= I915_MAX_WM
,
990 .cacheline_size
= I830_FIFO_LINE_SIZE
,
992 static const struct intel_watermark_params i845_wm_info
= {
993 .fifo_size
= I830_FIFO_SIZE
,
994 .max_wm
= I915_MAX_WM
,
997 .cacheline_size
= I830_FIFO_LINE_SIZE
,
1001 * intel_calculate_wm - calculate watermark level
1002 * @clock_in_khz: pixel clock
1003 * @wm: chip FIFO params
1004 * @pixel_size: display pixel size
1005 * @latency_ns: memory latency for the platform
1007 * Calculate the watermark level (the level at which the display plane will
1008 * start fetching from memory again). Each chip has a different display
1009 * FIFO size and allocation, so the caller needs to figure that out and pass
1010 * in the correct intel_watermark_params structure.
1012 * As the pixel clock runs, the FIFO will be drained at a rate that depends
1013 * on the pixel size. When it reaches the watermark level, it'll start
1014 * fetching FIFO line sized based chunks from memory until the FIFO fills
1015 * past the watermark point. If the FIFO drains completely, a FIFO underrun
1016 * will occur, and a display engine hang could result.
1018 static unsigned long intel_calculate_wm(unsigned long clock_in_khz
,
1019 const struct intel_watermark_params
*wm
,
1022 unsigned long latency_ns
)
1024 long entries_required
, wm_size
;
1027 * Note: we need to make sure we don't overflow for various clock &
1029 * clocks go from a few thousand to several hundred thousand.
1030 * latency is usually a few thousand
1032 entries_required
= ((clock_in_khz
/ 1000) * pixel_size
* latency_ns
) /
1034 entries_required
= DIV_ROUND_UP(entries_required
, wm
->cacheline_size
);
1036 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required
);
1038 wm_size
= fifo_size
- (entries_required
+ wm
->guard_size
);
1040 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size
);
1042 /* Don't promote wm_size to unsigned... */
1043 if (wm_size
> (long)wm
->max_wm
)
1044 wm_size
= wm
->max_wm
;
1046 wm_size
= wm
->default_wm
;
1050 static struct drm_crtc
*single_enabled_crtc(struct drm_device
*dev
)
1052 struct drm_crtc
*crtc
, *enabled
= NULL
;
1054 for_each_crtc(dev
, crtc
) {
1055 if (intel_crtc_active(crtc
)) {
1065 static void pineview_update_wm(struct drm_crtc
*unused_crtc
)
1067 struct drm_device
*dev
= unused_crtc
->dev
;
1068 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1069 struct drm_crtc
*crtc
;
1070 const struct cxsr_latency
*latency
;
1074 latency
= intel_get_cxsr_latency(IS_PINEVIEW_G(dev
), dev_priv
->is_ddr3
,
1075 dev_priv
->fsb_freq
, dev_priv
->mem_freq
);
1077 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1078 intel_set_memory_cxsr(dev_priv
, false);
1082 crtc
= single_enabled_crtc(dev
);
1084 const struct drm_display_mode
*adjusted_mode
;
1085 int pixel_size
= crtc
->primary
->fb
->bits_per_pixel
/ 8;
1088 adjusted_mode
= &to_intel_crtc(crtc
)->config
.adjusted_mode
;
1089 clock
= adjusted_mode
->crtc_clock
;
1092 wm
= intel_calculate_wm(clock
, &pineview_display_wm
,
1093 pineview_display_wm
.fifo_size
,
1094 pixel_size
, latency
->display_sr
);
1095 reg
= I915_READ(DSPFW1
);
1096 reg
&= ~DSPFW_SR_MASK
;
1097 reg
|= wm
<< DSPFW_SR_SHIFT
;
1098 I915_WRITE(DSPFW1
, reg
);
1099 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg
);
1102 wm
= intel_calculate_wm(clock
, &pineview_cursor_wm
,
1103 pineview_display_wm
.fifo_size
,
1104 pixel_size
, latency
->cursor_sr
);
1105 reg
= I915_READ(DSPFW3
);
1106 reg
&= ~DSPFW_CURSOR_SR_MASK
;
1107 reg
|= (wm
& 0x3f) << DSPFW_CURSOR_SR_SHIFT
;
1108 I915_WRITE(DSPFW3
, reg
);
1110 /* Display HPLL off SR */
1111 wm
= intel_calculate_wm(clock
, &pineview_display_hplloff_wm
,
1112 pineview_display_hplloff_wm
.fifo_size
,
1113 pixel_size
, latency
->display_hpll_disable
);
1114 reg
= I915_READ(DSPFW3
);
1115 reg
&= ~DSPFW_HPLL_SR_MASK
;
1116 reg
|= wm
& DSPFW_HPLL_SR_MASK
;
1117 I915_WRITE(DSPFW3
, reg
);
1119 /* cursor HPLL off SR */
1120 wm
= intel_calculate_wm(clock
, &pineview_cursor_hplloff_wm
,
1121 pineview_display_hplloff_wm
.fifo_size
,
1122 pixel_size
, latency
->cursor_hpll_disable
);
1123 reg
= I915_READ(DSPFW3
);
1124 reg
&= ~DSPFW_HPLL_CURSOR_MASK
;
1125 reg
|= (wm
& 0x3f) << DSPFW_HPLL_CURSOR_SHIFT
;
1126 I915_WRITE(DSPFW3
, reg
);
1127 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg
);
1129 intel_set_memory_cxsr(dev_priv
, true);
1131 intel_set_memory_cxsr(dev_priv
, false);
1135 static bool g4x_compute_wm0(struct drm_device
*dev
,
1137 const struct intel_watermark_params
*display
,
1138 int display_latency_ns
,
1139 const struct intel_watermark_params
*cursor
,
1140 int cursor_latency_ns
,
1144 struct drm_crtc
*crtc
;
1145 const struct drm_display_mode
*adjusted_mode
;
1146 int htotal
, hdisplay
, clock
, pixel_size
;
1147 int line_time_us
, line_count
;
1148 int entries
, tlb_miss
;
1150 crtc
= intel_get_crtc_for_plane(dev
, plane
);
1151 if (!intel_crtc_active(crtc
)) {
1152 *cursor_wm
= cursor
->guard_size
;
1153 *plane_wm
= display
->guard_size
;
1157 adjusted_mode
= &to_intel_crtc(crtc
)->config
.adjusted_mode
;
1158 clock
= adjusted_mode
->crtc_clock
;
1159 htotal
= adjusted_mode
->crtc_htotal
;
1160 hdisplay
= to_intel_crtc(crtc
)->config
.pipe_src_w
;
1161 pixel_size
= crtc
->primary
->fb
->bits_per_pixel
/ 8;
1163 /* Use the small buffer method to calculate plane watermark */
1164 entries
= ((clock
* pixel_size
/ 1000) * display_latency_ns
) / 1000;
1165 tlb_miss
= display
->fifo_size
*display
->cacheline_size
- hdisplay
* 8;
1167 entries
+= tlb_miss
;
1168 entries
= DIV_ROUND_UP(entries
, display
->cacheline_size
);
1169 *plane_wm
= entries
+ display
->guard_size
;
1170 if (*plane_wm
> (int)display
->max_wm
)
1171 *plane_wm
= display
->max_wm
;
1173 /* Use the large buffer method to calculate cursor watermark */
1174 line_time_us
= max(htotal
* 1000 / clock
, 1);
1175 line_count
= (cursor_latency_ns
/ line_time_us
+ 1000) / 1000;
1176 entries
= line_count
* to_intel_crtc(crtc
)->cursor_width
* pixel_size
;
1177 tlb_miss
= cursor
->fifo_size
*cursor
->cacheline_size
- hdisplay
* 8;
1179 entries
+= tlb_miss
;
1180 entries
= DIV_ROUND_UP(entries
, cursor
->cacheline_size
);
1181 *cursor_wm
= entries
+ cursor
->guard_size
;
1182 if (*cursor_wm
> (int)cursor
->max_wm
)
1183 *cursor_wm
= (int)cursor
->max_wm
;
1189 * Check the wm result.
1191 * If any calculated watermark values is larger than the maximum value that
1192 * can be programmed into the associated watermark register, that watermark
1195 static bool g4x_check_srwm(struct drm_device
*dev
,
1196 int display_wm
, int cursor_wm
,
1197 const struct intel_watermark_params
*display
,
1198 const struct intel_watermark_params
*cursor
)
1200 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1201 display_wm
, cursor_wm
);
1203 if (display_wm
> display
->max_wm
) {
1204 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1205 display_wm
, display
->max_wm
);
1209 if (cursor_wm
> cursor
->max_wm
) {
1210 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1211 cursor_wm
, cursor
->max_wm
);
1215 if (!(display_wm
|| cursor_wm
)) {
1216 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1223 static bool g4x_compute_srwm(struct drm_device
*dev
,
1226 const struct intel_watermark_params
*display
,
1227 const struct intel_watermark_params
*cursor
,
1228 int *display_wm
, int *cursor_wm
)
1230 struct drm_crtc
*crtc
;
1231 const struct drm_display_mode
*adjusted_mode
;
1232 int hdisplay
, htotal
, pixel_size
, clock
;
1233 unsigned long line_time_us
;
1234 int line_count
, line_size
;
1239 *display_wm
= *cursor_wm
= 0;
1243 crtc
= intel_get_crtc_for_plane(dev
, plane
);
1244 adjusted_mode
= &to_intel_crtc(crtc
)->config
.adjusted_mode
;
1245 clock
= adjusted_mode
->crtc_clock
;
1246 htotal
= adjusted_mode
->crtc_htotal
;
1247 hdisplay
= to_intel_crtc(crtc
)->config
.pipe_src_w
;
1248 pixel_size
= crtc
->primary
->fb
->bits_per_pixel
/ 8;
1250 line_time_us
= max(htotal
* 1000 / clock
, 1);
1251 line_count
= (latency_ns
/ line_time_us
+ 1000) / 1000;
1252 line_size
= hdisplay
* pixel_size
;
1254 /* Use the minimum of the small and large buffer method for primary */
1255 small
= ((clock
* pixel_size
/ 1000) * latency_ns
) / 1000;
1256 large
= line_count
* line_size
;
1258 entries
= DIV_ROUND_UP(min(small
, large
), display
->cacheline_size
);
1259 *display_wm
= entries
+ display
->guard_size
;
1261 /* calculate the self-refresh watermark for display cursor */
1262 entries
= line_count
* pixel_size
* to_intel_crtc(crtc
)->cursor_width
;
1263 entries
= DIV_ROUND_UP(entries
, cursor
->cacheline_size
);
1264 *cursor_wm
= entries
+ cursor
->guard_size
;
1266 return g4x_check_srwm(dev
,
1267 *display_wm
, *cursor_wm
,
1271 static bool vlv_compute_drain_latency(struct drm_device
*dev
,
1273 int *plane_prec_mult
,
1275 int *cursor_prec_mult
,
1278 struct drm_crtc
*crtc
;
1279 int clock
, pixel_size
;
1282 crtc
= intel_get_crtc_for_plane(dev
, plane
);
1283 if (!intel_crtc_active(crtc
))
1286 clock
= to_intel_crtc(crtc
)->config
.adjusted_mode
.crtc_clock
;
1287 pixel_size
= crtc
->primary
->fb
->bits_per_pixel
/ 8; /* BPP */
1289 entries
= (clock
/ 1000) * pixel_size
;
1290 *plane_prec_mult
= (entries
> 256) ?
1291 DRAIN_LATENCY_PRECISION_32
: DRAIN_LATENCY_PRECISION_16
;
1292 *plane_dl
= (64 * (*plane_prec_mult
) * 4) / ((clock
/ 1000) *
1295 entries
= (clock
/ 1000) * 4; /* BPP is always 4 for cursor */
1296 *cursor_prec_mult
= (entries
> 256) ?
1297 DRAIN_LATENCY_PRECISION_32
: DRAIN_LATENCY_PRECISION_16
;
1298 *cursor_dl
= (64 * (*cursor_prec_mult
) * 4) / ((clock
/ 1000) * 4);
1304 * Update drain latency registers of memory arbiter
1306 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1307 * to be programmed. Each plane has a drain latency multiplier and a drain
1311 static void vlv_update_drain_latency(struct drm_device
*dev
)
1313 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1314 int planea_prec
, planea_dl
, planeb_prec
, planeb_dl
;
1315 int cursora_prec
, cursora_dl
, cursorb_prec
, cursorb_dl
;
1316 int plane_prec_mult
, cursor_prec_mult
; /* Precision multiplier is
1319 /* For plane A, Cursor A */
1320 if (vlv_compute_drain_latency(dev
, 0, &plane_prec_mult
, &planea_dl
,
1321 &cursor_prec_mult
, &cursora_dl
)) {
1322 cursora_prec
= (cursor_prec_mult
== DRAIN_LATENCY_PRECISION_32
) ?
1323 DDL_CURSORA_PRECISION_32
: DDL_CURSORA_PRECISION_16
;
1324 planea_prec
= (plane_prec_mult
== DRAIN_LATENCY_PRECISION_32
) ?
1325 DDL_PLANEA_PRECISION_32
: DDL_PLANEA_PRECISION_16
;
1327 I915_WRITE(VLV_DDL1
, cursora_prec
|
1328 (cursora_dl
<< DDL_CURSORA_SHIFT
) |
1329 planea_prec
| planea_dl
);
1332 /* For plane B, Cursor B */
1333 if (vlv_compute_drain_latency(dev
, 1, &plane_prec_mult
, &planeb_dl
,
1334 &cursor_prec_mult
, &cursorb_dl
)) {
1335 cursorb_prec
= (cursor_prec_mult
== DRAIN_LATENCY_PRECISION_32
) ?
1336 DDL_CURSORB_PRECISION_32
: DDL_CURSORB_PRECISION_16
;
1337 planeb_prec
= (plane_prec_mult
== DRAIN_LATENCY_PRECISION_32
) ?
1338 DDL_PLANEB_PRECISION_32
: DDL_PLANEB_PRECISION_16
;
1340 I915_WRITE(VLV_DDL2
, cursorb_prec
|
1341 (cursorb_dl
<< DDL_CURSORB_SHIFT
) |
1342 planeb_prec
| planeb_dl
);
1346 #define single_plane_enabled(mask) is_power_of_2(mask)
1348 static void valleyview_update_wm(struct drm_crtc
*crtc
)
1350 struct drm_device
*dev
= crtc
->dev
;
1351 static const int sr_latency_ns
= 12000;
1352 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1353 int planea_wm
, planeb_wm
, cursora_wm
, cursorb_wm
;
1354 int plane_sr
, cursor_sr
;
1355 int ignore_plane_sr
, ignore_cursor_sr
;
1356 unsigned int enabled
= 0;
1359 vlv_update_drain_latency(dev
);
1361 if (g4x_compute_wm0(dev
, PIPE_A
,
1362 &valleyview_wm_info
, latency_ns
,
1363 &valleyview_cursor_wm_info
, latency_ns
,
1364 &planea_wm
, &cursora_wm
))
1365 enabled
|= 1 << PIPE_A
;
1367 if (g4x_compute_wm0(dev
, PIPE_B
,
1368 &valleyview_wm_info
, latency_ns
,
1369 &valleyview_cursor_wm_info
, latency_ns
,
1370 &planeb_wm
, &cursorb_wm
))
1371 enabled
|= 1 << PIPE_B
;
1373 if (single_plane_enabled(enabled
) &&
1374 g4x_compute_srwm(dev
, ffs(enabled
) - 1,
1376 &valleyview_wm_info
,
1377 &valleyview_cursor_wm_info
,
1378 &plane_sr
, &ignore_cursor_sr
) &&
1379 g4x_compute_srwm(dev
, ffs(enabled
) - 1,
1381 &valleyview_wm_info
,
1382 &valleyview_cursor_wm_info
,
1383 &ignore_plane_sr
, &cursor_sr
)) {
1384 cxsr_enabled
= true;
1386 cxsr_enabled
= false;
1387 intel_set_memory_cxsr(dev_priv
, false);
1388 plane_sr
= cursor_sr
= 0;
1391 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1392 planea_wm
, cursora_wm
,
1393 planeb_wm
, cursorb_wm
,
1394 plane_sr
, cursor_sr
);
1397 (plane_sr
<< DSPFW_SR_SHIFT
) |
1398 (cursorb_wm
<< DSPFW_CURSORB_SHIFT
) |
1399 (planeb_wm
<< DSPFW_PLANEB_SHIFT
) |
1402 (I915_READ(DSPFW2
) & ~DSPFW_CURSORA_MASK
) |
1403 (cursora_wm
<< DSPFW_CURSORA_SHIFT
));
1405 (I915_READ(DSPFW3
) & ~DSPFW_CURSOR_SR_MASK
) |
1406 (cursor_sr
<< DSPFW_CURSOR_SR_SHIFT
));
1409 intel_set_memory_cxsr(dev_priv
, true);
1412 static void g4x_update_wm(struct drm_crtc
*crtc
)
1414 struct drm_device
*dev
= crtc
->dev
;
1415 static const int sr_latency_ns
= 12000;
1416 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1417 int planea_wm
, planeb_wm
, cursora_wm
, cursorb_wm
;
1418 int plane_sr
, cursor_sr
;
1419 unsigned int enabled
= 0;
1422 if (g4x_compute_wm0(dev
, PIPE_A
,
1423 &g4x_wm_info
, latency_ns
,
1424 &g4x_cursor_wm_info
, latency_ns
,
1425 &planea_wm
, &cursora_wm
))
1426 enabled
|= 1 << PIPE_A
;
1428 if (g4x_compute_wm0(dev
, PIPE_B
,
1429 &g4x_wm_info
, latency_ns
,
1430 &g4x_cursor_wm_info
, latency_ns
,
1431 &planeb_wm
, &cursorb_wm
))
1432 enabled
|= 1 << PIPE_B
;
1434 if (single_plane_enabled(enabled
) &&
1435 g4x_compute_srwm(dev
, ffs(enabled
) - 1,
1438 &g4x_cursor_wm_info
,
1439 &plane_sr
, &cursor_sr
)) {
1440 cxsr_enabled
= true;
1442 cxsr_enabled
= false;
1443 intel_set_memory_cxsr(dev_priv
, false);
1444 plane_sr
= cursor_sr
= 0;
1447 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1448 planea_wm
, cursora_wm
,
1449 planeb_wm
, cursorb_wm
,
1450 plane_sr
, cursor_sr
);
1453 (plane_sr
<< DSPFW_SR_SHIFT
) |
1454 (cursorb_wm
<< DSPFW_CURSORB_SHIFT
) |
1455 (planeb_wm
<< DSPFW_PLANEB_SHIFT
) |
1458 (I915_READ(DSPFW2
) & ~DSPFW_CURSORA_MASK
) |
1459 (cursora_wm
<< DSPFW_CURSORA_SHIFT
));
1460 /* HPLL off in SR has some issues on G4x... disable it */
1462 (I915_READ(DSPFW3
) & ~(DSPFW_HPLL_SR_EN
| DSPFW_CURSOR_SR_MASK
)) |
1463 (cursor_sr
<< DSPFW_CURSOR_SR_SHIFT
));
1466 intel_set_memory_cxsr(dev_priv
, true);
1469 static void i965_update_wm(struct drm_crtc
*unused_crtc
)
1471 struct drm_device
*dev
= unused_crtc
->dev
;
1472 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1473 struct drm_crtc
*crtc
;
1478 /* Calc sr entries for one plane configs */
1479 crtc
= single_enabled_crtc(dev
);
1481 /* self-refresh has much higher latency */
1482 static const int sr_latency_ns
= 12000;
1483 const struct drm_display_mode
*adjusted_mode
=
1484 &to_intel_crtc(crtc
)->config
.adjusted_mode
;
1485 int clock
= adjusted_mode
->crtc_clock
;
1486 int htotal
= adjusted_mode
->crtc_htotal
;
1487 int hdisplay
= to_intel_crtc(crtc
)->config
.pipe_src_w
;
1488 int pixel_size
= crtc
->primary
->fb
->bits_per_pixel
/ 8;
1489 unsigned long line_time_us
;
1492 line_time_us
= max(htotal
* 1000 / clock
, 1);
1494 /* Use ns/us then divide to preserve precision */
1495 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
1496 pixel_size
* hdisplay
;
1497 entries
= DIV_ROUND_UP(entries
, I915_FIFO_LINE_SIZE
);
1498 srwm
= I965_FIFO_SIZE
- entries
;
1502 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1505 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
1506 pixel_size
* to_intel_crtc(crtc
)->cursor_width
;
1507 entries
= DIV_ROUND_UP(entries
,
1508 i965_cursor_wm_info
.cacheline_size
);
1509 cursor_sr
= i965_cursor_wm_info
.fifo_size
-
1510 (entries
+ i965_cursor_wm_info
.guard_size
);
1512 if (cursor_sr
> i965_cursor_wm_info
.max_wm
)
1513 cursor_sr
= i965_cursor_wm_info
.max_wm
;
1515 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1516 "cursor %d\n", srwm
, cursor_sr
);
1518 cxsr_enabled
= true;
1520 cxsr_enabled
= false;
1521 /* Turn off self refresh if both pipes are enabled */
1522 intel_set_memory_cxsr(dev_priv
, false);
1525 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1528 /* 965 has limitations... */
1529 I915_WRITE(DSPFW1
, (srwm
<< DSPFW_SR_SHIFT
) |
1530 (8 << 16) | (8 << 8) | (8 << 0));
1531 I915_WRITE(DSPFW2
, (8 << 8) | (8 << 0));
1532 /* update cursor SR watermark */
1533 I915_WRITE(DSPFW3
, (cursor_sr
<< DSPFW_CURSOR_SR_SHIFT
));
1536 intel_set_memory_cxsr(dev_priv
, true);
1539 static void i9xx_update_wm(struct drm_crtc
*unused_crtc
)
1541 struct drm_device
*dev
= unused_crtc
->dev
;
1542 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1543 const struct intel_watermark_params
*wm_info
;
1548 int planea_wm
, planeb_wm
;
1549 struct drm_crtc
*crtc
, *enabled
= NULL
;
1552 wm_info
= &i945_wm_info
;
1553 else if (!IS_GEN2(dev
))
1554 wm_info
= &i915_wm_info
;
1556 wm_info
= &i830_wm_info
;
1558 fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 0);
1559 crtc
= intel_get_crtc_for_plane(dev
, 0);
1560 if (intel_crtc_active(crtc
)) {
1561 const struct drm_display_mode
*adjusted_mode
;
1562 int cpp
= crtc
->primary
->fb
->bits_per_pixel
/ 8;
1566 adjusted_mode
= &to_intel_crtc(crtc
)->config
.adjusted_mode
;
1567 planea_wm
= intel_calculate_wm(adjusted_mode
->crtc_clock
,
1568 wm_info
, fifo_size
, cpp
,
1572 planea_wm
= fifo_size
- wm_info
->guard_size
;
1574 fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 1);
1575 crtc
= intel_get_crtc_for_plane(dev
, 1);
1576 if (intel_crtc_active(crtc
)) {
1577 const struct drm_display_mode
*adjusted_mode
;
1578 int cpp
= crtc
->primary
->fb
->bits_per_pixel
/ 8;
1582 adjusted_mode
= &to_intel_crtc(crtc
)->config
.adjusted_mode
;
1583 planeb_wm
= intel_calculate_wm(adjusted_mode
->crtc_clock
,
1584 wm_info
, fifo_size
, cpp
,
1586 if (enabled
== NULL
)
1591 planeb_wm
= fifo_size
- wm_info
->guard_size
;
1593 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm
, planeb_wm
);
1595 if (IS_I915GM(dev
) && enabled
) {
1596 struct drm_i915_gem_object
*obj
;
1598 obj
= intel_fb_obj(enabled
->primary
->fb
);
1600 /* self-refresh seems busted with untiled */
1601 if (obj
->tiling_mode
== I915_TILING_NONE
)
1606 * Overlay gets an aggressive default since video jitter is bad.
1610 /* Play safe and disable self-refresh before adjusting watermarks. */
1611 intel_set_memory_cxsr(dev_priv
, false);
1613 /* Calc sr entries for one plane configs */
1614 if (HAS_FW_BLC(dev
) && enabled
) {
1615 /* self-refresh has much higher latency */
1616 static const int sr_latency_ns
= 6000;
1617 const struct drm_display_mode
*adjusted_mode
=
1618 &to_intel_crtc(enabled
)->config
.adjusted_mode
;
1619 int clock
= adjusted_mode
->crtc_clock
;
1620 int htotal
= adjusted_mode
->crtc_htotal
;
1621 int hdisplay
= to_intel_crtc(enabled
)->config
.pipe_src_w
;
1622 int pixel_size
= enabled
->primary
->fb
->bits_per_pixel
/ 8;
1623 unsigned long line_time_us
;
1626 line_time_us
= max(htotal
* 1000 / clock
, 1);
1628 /* Use ns/us then divide to preserve precision */
1629 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
1630 pixel_size
* hdisplay
;
1631 entries
= DIV_ROUND_UP(entries
, wm_info
->cacheline_size
);
1632 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries
);
1633 srwm
= wm_info
->fifo_size
- entries
;
1637 if (IS_I945G(dev
) || IS_I945GM(dev
))
1638 I915_WRITE(FW_BLC_SELF
,
1639 FW_BLC_SELF_FIFO_MASK
| (srwm
& 0xff));
1640 else if (IS_I915GM(dev
))
1641 I915_WRITE(FW_BLC_SELF
, srwm
& 0x3f);
1644 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1645 planea_wm
, planeb_wm
, cwm
, srwm
);
1647 fwater_lo
= ((planeb_wm
& 0x3f) << 16) | (planea_wm
& 0x3f);
1648 fwater_hi
= (cwm
& 0x1f);
1650 /* Set request length to 8 cachelines per fetch */
1651 fwater_lo
= fwater_lo
| (1 << 24) | (1 << 8);
1652 fwater_hi
= fwater_hi
| (1 << 8);
1654 I915_WRITE(FW_BLC
, fwater_lo
);
1655 I915_WRITE(FW_BLC2
, fwater_hi
);
1658 intel_set_memory_cxsr(dev_priv
, true);
1661 static void i845_update_wm(struct drm_crtc
*unused_crtc
)
1663 struct drm_device
*dev
= unused_crtc
->dev
;
1664 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1665 struct drm_crtc
*crtc
;
1666 const struct drm_display_mode
*adjusted_mode
;
1670 crtc
= single_enabled_crtc(dev
);
1674 adjusted_mode
= &to_intel_crtc(crtc
)->config
.adjusted_mode
;
1675 planea_wm
= intel_calculate_wm(adjusted_mode
->crtc_clock
,
1677 dev_priv
->display
.get_fifo_size(dev
, 0),
1679 fwater_lo
= I915_READ(FW_BLC
) & ~0xfff;
1680 fwater_lo
|= (3<<8) | planea_wm
;
1682 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm
);
1684 I915_WRITE(FW_BLC
, fwater_lo
);
1687 static uint32_t ilk_pipe_pixel_rate(struct drm_device
*dev
,
1688 struct drm_crtc
*crtc
)
1690 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1691 uint32_t pixel_rate
;
1693 pixel_rate
= intel_crtc
->config
.adjusted_mode
.crtc_clock
;
1695 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1696 * adjust the pixel_rate here. */
1698 if (intel_crtc
->config
.pch_pfit
.enabled
) {
1699 uint64_t pipe_w
, pipe_h
, pfit_w
, pfit_h
;
1700 uint32_t pfit_size
= intel_crtc
->config
.pch_pfit
.size
;
1702 pipe_w
= intel_crtc
->config
.pipe_src_w
;
1703 pipe_h
= intel_crtc
->config
.pipe_src_h
;
1704 pfit_w
= (pfit_size
>> 16) & 0xFFFF;
1705 pfit_h
= pfit_size
& 0xFFFF;
1706 if (pipe_w
< pfit_w
)
1708 if (pipe_h
< pfit_h
)
1711 pixel_rate
= div_u64((uint64_t) pixel_rate
* pipe_w
* pipe_h
,
1718 /* latency must be in 0.1us units. */
1719 static uint32_t ilk_wm_method1(uint32_t pixel_rate
, uint8_t bytes_per_pixel
,
1724 if (WARN(latency
== 0, "Latency value missing\n"))
1727 ret
= (uint64_t) pixel_rate
* bytes_per_pixel
* latency
;
1728 ret
= DIV_ROUND_UP_ULL(ret
, 64 * 10000) + 2;
1733 /* latency must be in 0.1us units. */
1734 static uint32_t ilk_wm_method2(uint32_t pixel_rate
, uint32_t pipe_htotal
,
1735 uint32_t horiz_pixels
, uint8_t bytes_per_pixel
,
1740 if (WARN(latency
== 0, "Latency value missing\n"))
1743 ret
= (latency
* pixel_rate
) / (pipe_htotal
* 10000);
1744 ret
= (ret
+ 1) * horiz_pixels
* bytes_per_pixel
;
1745 ret
= DIV_ROUND_UP(ret
, 64) + 2;
1749 static uint32_t ilk_wm_fbc(uint32_t pri_val
, uint32_t horiz_pixels
,
1750 uint8_t bytes_per_pixel
)
1752 return DIV_ROUND_UP(pri_val
* 64, horiz_pixels
* bytes_per_pixel
) + 2;
1755 struct ilk_pipe_wm_parameters
{
1757 uint32_t pipe_htotal
;
1758 uint32_t pixel_rate
;
1759 struct intel_plane_wm_parameters pri
;
1760 struct intel_plane_wm_parameters spr
;
1761 struct intel_plane_wm_parameters cur
;
1764 struct ilk_wm_maximums
{
1771 /* used in computing the new watermarks state */
1772 struct intel_wm_config
{
1773 unsigned int num_pipes_active
;
1774 bool sprites_enabled
;
1775 bool sprites_scaled
;
1779 * For both WM_PIPE and WM_LP.
1780 * mem_value must be in 0.1us units.
1782 static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters
*params
,
1786 uint32_t method1
, method2
;
1788 if (!params
->active
|| !params
->pri
.enabled
)
1791 method1
= ilk_wm_method1(params
->pixel_rate
,
1792 params
->pri
.bytes_per_pixel
,
1798 method2
= ilk_wm_method2(params
->pixel_rate
,
1799 params
->pipe_htotal
,
1800 params
->pri
.horiz_pixels
,
1801 params
->pri
.bytes_per_pixel
,
1804 return min(method1
, method2
);
1808 * For both WM_PIPE and WM_LP.
1809 * mem_value must be in 0.1us units.
1811 static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters
*params
,
1814 uint32_t method1
, method2
;
1816 if (!params
->active
|| !params
->spr
.enabled
)
1819 method1
= ilk_wm_method1(params
->pixel_rate
,
1820 params
->spr
.bytes_per_pixel
,
1822 method2
= ilk_wm_method2(params
->pixel_rate
,
1823 params
->pipe_htotal
,
1824 params
->spr
.horiz_pixels
,
1825 params
->spr
.bytes_per_pixel
,
1827 return min(method1
, method2
);
1831 * For both WM_PIPE and WM_LP.
1832 * mem_value must be in 0.1us units.
1834 static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters
*params
,
1837 if (!params
->active
|| !params
->cur
.enabled
)
1840 return ilk_wm_method2(params
->pixel_rate
,
1841 params
->pipe_htotal
,
1842 params
->cur
.horiz_pixels
,
1843 params
->cur
.bytes_per_pixel
,
1847 /* Only for WM_LP. */
1848 static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters
*params
,
1851 if (!params
->active
|| !params
->pri
.enabled
)
1854 return ilk_wm_fbc(pri_val
,
1855 params
->pri
.horiz_pixels
,
1856 params
->pri
.bytes_per_pixel
);
1859 static unsigned int ilk_display_fifo_size(const struct drm_device
*dev
)
1861 if (INTEL_INFO(dev
)->gen
>= 8)
1863 else if (INTEL_INFO(dev
)->gen
>= 7)
1869 static unsigned int ilk_plane_wm_reg_max(const struct drm_device
*dev
,
1870 int level
, bool is_sprite
)
1872 if (INTEL_INFO(dev
)->gen
>= 8)
1873 /* BDW primary/sprite plane watermarks */
1874 return level
== 0 ? 255 : 2047;
1875 else if (INTEL_INFO(dev
)->gen
>= 7)
1876 /* IVB/HSW primary/sprite plane watermarks */
1877 return level
== 0 ? 127 : 1023;
1878 else if (!is_sprite
)
1879 /* ILK/SNB primary plane watermarks */
1880 return level
== 0 ? 127 : 511;
1882 /* ILK/SNB sprite plane watermarks */
1883 return level
== 0 ? 63 : 255;
1886 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device
*dev
,
1889 if (INTEL_INFO(dev
)->gen
>= 7)
1890 return level
== 0 ? 63 : 255;
1892 return level
== 0 ? 31 : 63;
1895 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device
*dev
)
1897 if (INTEL_INFO(dev
)->gen
>= 8)
1903 /* Calculate the maximum primary/sprite plane watermark */
1904 static unsigned int ilk_plane_wm_max(const struct drm_device
*dev
,
1906 const struct intel_wm_config
*config
,
1907 enum intel_ddb_partitioning ddb_partitioning
,
1910 unsigned int fifo_size
= ilk_display_fifo_size(dev
);
1912 /* if sprites aren't enabled, sprites get nothing */
1913 if (is_sprite
&& !config
->sprites_enabled
)
1916 /* HSW allows LP1+ watermarks even with multiple pipes */
1917 if (level
== 0 || config
->num_pipes_active
> 1) {
1918 fifo_size
/= INTEL_INFO(dev
)->num_pipes
;
1921 * For some reason the non self refresh
1922 * FIFO size is only half of the self
1923 * refresh FIFO size on ILK/SNB.
1925 if (INTEL_INFO(dev
)->gen
<= 6)
1929 if (config
->sprites_enabled
) {
1930 /* level 0 is always calculated with 1:1 split */
1931 if (level
> 0 && ddb_partitioning
== INTEL_DDB_PART_5_6
) {
1940 /* clamp to max that the registers can hold */
1941 return min(fifo_size
, ilk_plane_wm_reg_max(dev
, level
, is_sprite
));
1944 /* Calculate the maximum cursor plane watermark */
1945 static unsigned int ilk_cursor_wm_max(const struct drm_device
*dev
,
1947 const struct intel_wm_config
*config
)
1949 /* HSW LP1+ watermarks w/ multiple pipes */
1950 if (level
> 0 && config
->num_pipes_active
> 1)
1953 /* otherwise just report max that registers can hold */
1954 return ilk_cursor_wm_reg_max(dev
, level
);
1957 static void ilk_compute_wm_maximums(const struct drm_device
*dev
,
1959 const struct intel_wm_config
*config
,
1960 enum intel_ddb_partitioning ddb_partitioning
,
1961 struct ilk_wm_maximums
*max
)
1963 max
->pri
= ilk_plane_wm_max(dev
, level
, config
, ddb_partitioning
, false);
1964 max
->spr
= ilk_plane_wm_max(dev
, level
, config
, ddb_partitioning
, true);
1965 max
->cur
= ilk_cursor_wm_max(dev
, level
, config
);
1966 max
->fbc
= ilk_fbc_wm_reg_max(dev
);
1969 static void ilk_compute_wm_reg_maximums(struct drm_device
*dev
,
1971 struct ilk_wm_maximums
*max
)
1973 max
->pri
= ilk_plane_wm_reg_max(dev
, level
, false);
1974 max
->spr
= ilk_plane_wm_reg_max(dev
, level
, true);
1975 max
->cur
= ilk_cursor_wm_reg_max(dev
, level
);
1976 max
->fbc
= ilk_fbc_wm_reg_max(dev
);
1979 static bool ilk_validate_wm_level(int level
,
1980 const struct ilk_wm_maximums
*max
,
1981 struct intel_wm_level
*result
)
1985 /* already determined to be invalid? */
1986 if (!result
->enable
)
1989 result
->enable
= result
->pri_val
<= max
->pri
&&
1990 result
->spr_val
<= max
->spr
&&
1991 result
->cur_val
<= max
->cur
;
1993 ret
= result
->enable
;
1996 * HACK until we can pre-compute everything,
1997 * and thus fail gracefully if LP0 watermarks
2000 if (level
== 0 && !result
->enable
) {
2001 if (result
->pri_val
> max
->pri
)
2002 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2003 level
, result
->pri_val
, max
->pri
);
2004 if (result
->spr_val
> max
->spr
)
2005 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2006 level
, result
->spr_val
, max
->spr
);
2007 if (result
->cur_val
> max
->cur
)
2008 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2009 level
, result
->cur_val
, max
->cur
);
2011 result
->pri_val
= min_t(uint32_t, result
->pri_val
, max
->pri
);
2012 result
->spr_val
= min_t(uint32_t, result
->spr_val
, max
->spr
);
2013 result
->cur_val
= min_t(uint32_t, result
->cur_val
, max
->cur
);
2014 result
->enable
= true;
2020 static void ilk_compute_wm_level(const struct drm_i915_private
*dev_priv
,
2022 const struct ilk_pipe_wm_parameters
*p
,
2023 struct intel_wm_level
*result
)
2025 uint16_t pri_latency
= dev_priv
->wm
.pri_latency
[level
];
2026 uint16_t spr_latency
= dev_priv
->wm
.spr_latency
[level
];
2027 uint16_t cur_latency
= dev_priv
->wm
.cur_latency
[level
];
2029 /* WM1+ latency values stored in 0.5us units */
2036 result
->pri_val
= ilk_compute_pri_wm(p
, pri_latency
, level
);
2037 result
->spr_val
= ilk_compute_spr_wm(p
, spr_latency
);
2038 result
->cur_val
= ilk_compute_cur_wm(p
, cur_latency
);
2039 result
->fbc_val
= ilk_compute_fbc_wm(p
, result
->pri_val
);
2040 result
->enable
= true;
2044 hsw_compute_linetime_wm(struct drm_device
*dev
, struct drm_crtc
*crtc
)
2046 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2047 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2048 struct drm_display_mode
*mode
= &intel_crtc
->config
.adjusted_mode
;
2049 u32 linetime
, ips_linetime
;
2051 if (!intel_crtc_active(crtc
))
2054 /* The WM are computed with base on how long it takes to fill a single
2055 * row at the given clock rate, multiplied by 8.
2057 linetime
= DIV_ROUND_CLOSEST(mode
->crtc_htotal
* 1000 * 8,
2059 ips_linetime
= DIV_ROUND_CLOSEST(mode
->crtc_htotal
* 1000 * 8,
2060 intel_ddi_get_cdclk_freq(dev_priv
));
2062 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime
) |
2063 PIPE_WM_LINETIME_TIME(linetime
);
2066 static void intel_read_wm_latency(struct drm_device
*dev
, uint16_t wm
[5])
2068 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2070 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2071 uint64_t sskpd
= I915_READ64(MCH_SSKPD
);
2073 wm
[0] = (sskpd
>> 56) & 0xFF;
2075 wm
[0] = sskpd
& 0xF;
2076 wm
[1] = (sskpd
>> 4) & 0xFF;
2077 wm
[2] = (sskpd
>> 12) & 0xFF;
2078 wm
[3] = (sskpd
>> 20) & 0x1FF;
2079 wm
[4] = (sskpd
>> 32) & 0x1FF;
2080 } else if (INTEL_INFO(dev
)->gen
>= 6) {
2081 uint32_t sskpd
= I915_READ(MCH_SSKPD
);
2083 wm
[0] = (sskpd
>> SSKPD_WM0_SHIFT
) & SSKPD_WM_MASK
;
2084 wm
[1] = (sskpd
>> SSKPD_WM1_SHIFT
) & SSKPD_WM_MASK
;
2085 wm
[2] = (sskpd
>> SSKPD_WM2_SHIFT
) & SSKPD_WM_MASK
;
2086 wm
[3] = (sskpd
>> SSKPD_WM3_SHIFT
) & SSKPD_WM_MASK
;
2087 } else if (INTEL_INFO(dev
)->gen
>= 5) {
2088 uint32_t mltr
= I915_READ(MLTR_ILK
);
2090 /* ILK primary LP0 latency is 700 ns */
2092 wm
[1] = (mltr
>> MLTR_WM1_SHIFT
) & ILK_SRLT_MASK
;
2093 wm
[2] = (mltr
>> MLTR_WM2_SHIFT
) & ILK_SRLT_MASK
;
2097 static void intel_fixup_spr_wm_latency(struct drm_device
*dev
, uint16_t wm
[5])
2099 /* ILK sprite LP0 latency is 1300 ns */
2100 if (INTEL_INFO(dev
)->gen
== 5)
2104 static void intel_fixup_cur_wm_latency(struct drm_device
*dev
, uint16_t wm
[5])
2106 /* ILK cursor LP0 latency is 1300 ns */
2107 if (INTEL_INFO(dev
)->gen
== 5)
2110 /* WaDoubleCursorLP3Latency:ivb */
2111 if (IS_IVYBRIDGE(dev
))
2115 int ilk_wm_max_level(const struct drm_device
*dev
)
2117 /* how many WM levels are we expecting */
2118 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2120 else if (INTEL_INFO(dev
)->gen
>= 6)
2126 static void intel_print_wm_latency(struct drm_device
*dev
,
2128 const uint16_t wm
[5])
2130 int level
, max_level
= ilk_wm_max_level(dev
);
2132 for (level
= 0; level
<= max_level
; level
++) {
2133 unsigned int latency
= wm
[level
];
2136 DRM_ERROR("%s WM%d latency not provided\n",
2141 /* WM1+ latency values in 0.5us units */
2145 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2146 name
, level
, wm
[level
],
2147 latency
/ 10, latency
% 10);
2151 static bool ilk_increase_wm_latency(struct drm_i915_private
*dev_priv
,
2152 uint16_t wm
[5], uint16_t min
)
2154 int level
, max_level
= ilk_wm_max_level(dev_priv
->dev
);
2159 wm
[0] = max(wm
[0], min
);
2160 for (level
= 1; level
<= max_level
; level
++)
2161 wm
[level
] = max_t(uint16_t, wm
[level
], DIV_ROUND_UP(min
, 5));
2166 static void snb_wm_latency_quirk(struct drm_device
*dev
)
2168 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2172 * The BIOS provided WM memory latency values are often
2173 * inadequate for high resolution displays. Adjust them.
2175 changed
= ilk_increase_wm_latency(dev_priv
, dev_priv
->wm
.pri_latency
, 12) |
2176 ilk_increase_wm_latency(dev_priv
, dev_priv
->wm
.spr_latency
, 12) |
2177 ilk_increase_wm_latency(dev_priv
, dev_priv
->wm
.cur_latency
, 12);
2182 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2183 intel_print_wm_latency(dev
, "Primary", dev_priv
->wm
.pri_latency
);
2184 intel_print_wm_latency(dev
, "Sprite", dev_priv
->wm
.spr_latency
);
2185 intel_print_wm_latency(dev
, "Cursor", dev_priv
->wm
.cur_latency
);
2188 static void ilk_setup_wm_latency(struct drm_device
*dev
)
2190 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2192 intel_read_wm_latency(dev
, dev_priv
->wm
.pri_latency
);
2194 memcpy(dev_priv
->wm
.spr_latency
, dev_priv
->wm
.pri_latency
,
2195 sizeof(dev_priv
->wm
.pri_latency
));
2196 memcpy(dev_priv
->wm
.cur_latency
, dev_priv
->wm
.pri_latency
,
2197 sizeof(dev_priv
->wm
.pri_latency
));
2199 intel_fixup_spr_wm_latency(dev
, dev_priv
->wm
.spr_latency
);
2200 intel_fixup_cur_wm_latency(dev
, dev_priv
->wm
.cur_latency
);
2202 intel_print_wm_latency(dev
, "Primary", dev_priv
->wm
.pri_latency
);
2203 intel_print_wm_latency(dev
, "Sprite", dev_priv
->wm
.spr_latency
);
2204 intel_print_wm_latency(dev
, "Cursor", dev_priv
->wm
.cur_latency
);
2207 snb_wm_latency_quirk(dev
);
2210 static void ilk_compute_wm_parameters(struct drm_crtc
*crtc
,
2211 struct ilk_pipe_wm_parameters
*p
)
2213 struct drm_device
*dev
= crtc
->dev
;
2214 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2215 enum pipe pipe
= intel_crtc
->pipe
;
2216 struct drm_plane
*plane
;
2218 if (!intel_crtc_active(crtc
))
2222 p
->pipe_htotal
= intel_crtc
->config
.adjusted_mode
.crtc_htotal
;
2223 p
->pixel_rate
= ilk_pipe_pixel_rate(dev
, crtc
);
2224 p
->pri
.bytes_per_pixel
= crtc
->primary
->fb
->bits_per_pixel
/ 8;
2225 p
->cur
.bytes_per_pixel
= 4;
2226 p
->pri
.horiz_pixels
= intel_crtc
->config
.pipe_src_w
;
2227 p
->cur
.horiz_pixels
= intel_crtc
->cursor_width
;
2228 /* TODO: for now, assume primary and cursor planes are always enabled. */
2229 p
->pri
.enabled
= true;
2230 p
->cur
.enabled
= true;
2232 drm_for_each_legacy_plane(plane
, &dev
->mode_config
.plane_list
) {
2233 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
2235 if (intel_plane
->pipe
== pipe
) {
2236 p
->spr
= intel_plane
->wm
;
2242 static void ilk_compute_wm_config(struct drm_device
*dev
,
2243 struct intel_wm_config
*config
)
2245 struct intel_crtc
*intel_crtc
;
2247 /* Compute the currently _active_ config */
2248 for_each_intel_crtc(dev
, intel_crtc
) {
2249 const struct intel_pipe_wm
*wm
= &intel_crtc
->wm
.active
;
2251 if (!wm
->pipe_enabled
)
2254 config
->sprites_enabled
|= wm
->sprites_enabled
;
2255 config
->sprites_scaled
|= wm
->sprites_scaled
;
2256 config
->num_pipes_active
++;
2260 /* Compute new watermarks for the pipe */
2261 static bool intel_compute_pipe_wm(struct drm_crtc
*crtc
,
2262 const struct ilk_pipe_wm_parameters
*params
,
2263 struct intel_pipe_wm
*pipe_wm
)
2265 struct drm_device
*dev
= crtc
->dev
;
2266 const struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2267 int level
, max_level
= ilk_wm_max_level(dev
);
2268 /* LP0 watermark maximums depend on this pipe alone */
2269 struct intel_wm_config config
= {
2270 .num_pipes_active
= 1,
2271 .sprites_enabled
= params
->spr
.enabled
,
2272 .sprites_scaled
= params
->spr
.scaled
,
2274 struct ilk_wm_maximums max
;
2276 pipe_wm
->pipe_enabled
= params
->active
;
2277 pipe_wm
->sprites_enabled
= params
->spr
.enabled
;
2278 pipe_wm
->sprites_scaled
= params
->spr
.scaled
;
2280 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2281 if (INTEL_INFO(dev
)->gen
<= 6 && params
->spr
.enabled
)
2284 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2285 if (params
->spr
.scaled
)
2288 ilk_compute_wm_level(dev_priv
, 0, params
, &pipe_wm
->wm
[0]);
2290 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2291 pipe_wm
->linetime
= hsw_compute_linetime_wm(dev
, crtc
);
2293 /* LP0 watermarks always use 1/2 DDB partitioning */
2294 ilk_compute_wm_maximums(dev
, 0, &config
, INTEL_DDB_PART_1_2
, &max
);
2296 /* At least LP0 must be valid */
2297 if (!ilk_validate_wm_level(0, &max
, &pipe_wm
->wm
[0]))
2300 ilk_compute_wm_reg_maximums(dev
, 1, &max
);
2302 for (level
= 1; level
<= max_level
; level
++) {
2303 struct intel_wm_level wm
= {};
2305 ilk_compute_wm_level(dev_priv
, level
, params
, &wm
);
2308 * Disable any watermark level that exceeds the
2309 * register maximums since such watermarks are
2312 if (!ilk_validate_wm_level(level
, &max
, &wm
))
2315 pipe_wm
->wm
[level
] = wm
;
2322 * Merge the watermarks from all active pipes for a specific level.
2324 static void ilk_merge_wm_level(struct drm_device
*dev
,
2326 struct intel_wm_level
*ret_wm
)
2328 const struct intel_crtc
*intel_crtc
;
2330 ret_wm
->enable
= true;
2332 for_each_intel_crtc(dev
, intel_crtc
) {
2333 const struct intel_pipe_wm
*active
= &intel_crtc
->wm
.active
;
2334 const struct intel_wm_level
*wm
= &active
->wm
[level
];
2336 if (!active
->pipe_enabled
)
2340 * The watermark values may have been used in the past,
2341 * so we must maintain them in the registers for some
2342 * time even if the level is now disabled.
2345 ret_wm
->enable
= false;
2347 ret_wm
->pri_val
= max(ret_wm
->pri_val
, wm
->pri_val
);
2348 ret_wm
->spr_val
= max(ret_wm
->spr_val
, wm
->spr_val
);
2349 ret_wm
->cur_val
= max(ret_wm
->cur_val
, wm
->cur_val
);
2350 ret_wm
->fbc_val
= max(ret_wm
->fbc_val
, wm
->fbc_val
);
2355 * Merge all low power watermarks for all active pipes.
2357 static void ilk_wm_merge(struct drm_device
*dev
,
2358 const struct intel_wm_config
*config
,
2359 const struct ilk_wm_maximums
*max
,
2360 struct intel_pipe_wm
*merged
)
2362 int level
, max_level
= ilk_wm_max_level(dev
);
2363 int last_enabled_level
= max_level
;
2365 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2366 if ((INTEL_INFO(dev
)->gen
<= 6 || IS_IVYBRIDGE(dev
)) &&
2367 config
->num_pipes_active
> 1)
2370 /* ILK: FBC WM must be disabled always */
2371 merged
->fbc_wm_enabled
= INTEL_INFO(dev
)->gen
>= 6;
2373 /* merge each WM1+ level */
2374 for (level
= 1; level
<= max_level
; level
++) {
2375 struct intel_wm_level
*wm
= &merged
->wm
[level
];
2377 ilk_merge_wm_level(dev
, level
, wm
);
2379 if (level
> last_enabled_level
)
2381 else if (!ilk_validate_wm_level(level
, max
, wm
))
2382 /* make sure all following levels get disabled */
2383 last_enabled_level
= level
- 1;
2386 * The spec says it is preferred to disable
2387 * FBC WMs instead of disabling a WM level.
2389 if (wm
->fbc_val
> max
->fbc
) {
2391 merged
->fbc_wm_enabled
= false;
2396 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2398 * FIXME this is racy. FBC might get enabled later.
2399 * What we should check here is whether FBC can be
2400 * enabled sometime later.
2402 if (IS_GEN5(dev
) && !merged
->fbc_wm_enabled
&& intel_fbc_enabled(dev
)) {
2403 for (level
= 2; level
<= max_level
; level
++) {
2404 struct intel_wm_level
*wm
= &merged
->wm
[level
];
2411 static int ilk_wm_lp_to_level(int wm_lp
, const struct intel_pipe_wm
*pipe_wm
)
2413 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2414 return wm_lp
+ (wm_lp
>= 2 && pipe_wm
->wm
[4].enable
);
2417 /* The value we need to program into the WM_LPx latency field */
2418 static unsigned int ilk_wm_lp_latency(struct drm_device
*dev
, int level
)
2420 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2422 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2425 return dev_priv
->wm
.pri_latency
[level
];
2428 static void ilk_compute_wm_results(struct drm_device
*dev
,
2429 const struct intel_pipe_wm
*merged
,
2430 enum intel_ddb_partitioning partitioning
,
2431 struct ilk_wm_values
*results
)
2433 struct intel_crtc
*intel_crtc
;
2436 results
->enable_fbc_wm
= merged
->fbc_wm_enabled
;
2437 results
->partitioning
= partitioning
;
2439 /* LP1+ register values */
2440 for (wm_lp
= 1; wm_lp
<= 3; wm_lp
++) {
2441 const struct intel_wm_level
*r
;
2443 level
= ilk_wm_lp_to_level(wm_lp
, merged
);
2445 r
= &merged
->wm
[level
];
2448 * Maintain the watermark values even if the level is
2449 * disabled. Doing otherwise could cause underruns.
2451 results
->wm_lp
[wm_lp
- 1] =
2452 (ilk_wm_lp_latency(dev
, level
) << WM1_LP_LATENCY_SHIFT
) |
2453 (r
->pri_val
<< WM1_LP_SR_SHIFT
) |
2457 results
->wm_lp
[wm_lp
- 1] |= WM1_LP_SR_EN
;
2459 if (INTEL_INFO(dev
)->gen
>= 8)
2460 results
->wm_lp
[wm_lp
- 1] |=
2461 r
->fbc_val
<< WM1_LP_FBC_SHIFT_BDW
;
2463 results
->wm_lp
[wm_lp
- 1] |=
2464 r
->fbc_val
<< WM1_LP_FBC_SHIFT
;
2467 * Always set WM1S_LP_EN when spr_val != 0, even if the
2468 * level is disabled. Doing otherwise could cause underruns.
2470 if (INTEL_INFO(dev
)->gen
<= 6 && r
->spr_val
) {
2471 WARN_ON(wm_lp
!= 1);
2472 results
->wm_lp_spr
[wm_lp
- 1] = WM1S_LP_EN
| r
->spr_val
;
2474 results
->wm_lp_spr
[wm_lp
- 1] = r
->spr_val
;
2477 /* LP0 register values */
2478 for_each_intel_crtc(dev
, intel_crtc
) {
2479 enum pipe pipe
= intel_crtc
->pipe
;
2480 const struct intel_wm_level
*r
=
2481 &intel_crtc
->wm
.active
.wm
[0];
2483 if (WARN_ON(!r
->enable
))
2486 results
->wm_linetime
[pipe
] = intel_crtc
->wm
.active
.linetime
;
2488 results
->wm_pipe
[pipe
] =
2489 (r
->pri_val
<< WM0_PIPE_PLANE_SHIFT
) |
2490 (r
->spr_val
<< WM0_PIPE_SPRITE_SHIFT
) |
2495 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2496 * case both are at the same level. Prefer r1 in case they're the same. */
2497 static struct intel_pipe_wm
*ilk_find_best_result(struct drm_device
*dev
,
2498 struct intel_pipe_wm
*r1
,
2499 struct intel_pipe_wm
*r2
)
2501 int level
, max_level
= ilk_wm_max_level(dev
);
2502 int level1
= 0, level2
= 0;
2504 for (level
= 1; level
<= max_level
; level
++) {
2505 if (r1
->wm
[level
].enable
)
2507 if (r2
->wm
[level
].enable
)
2511 if (level1
== level2
) {
2512 if (r2
->fbc_wm_enabled
&& !r1
->fbc_wm_enabled
)
2516 } else if (level1
> level2
) {
2523 /* dirty bits used to track which watermarks need changes */
2524 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2525 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2526 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2527 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2528 #define WM_DIRTY_FBC (1 << 24)
2529 #define WM_DIRTY_DDB (1 << 25)
2531 static unsigned int ilk_compute_wm_dirty(struct drm_device
*dev
,
2532 const struct ilk_wm_values
*old
,
2533 const struct ilk_wm_values
*new)
2535 unsigned int dirty
= 0;
2539 for_each_pipe(pipe
) {
2540 if (old
->wm_linetime
[pipe
] != new->wm_linetime
[pipe
]) {
2541 dirty
|= WM_DIRTY_LINETIME(pipe
);
2542 /* Must disable LP1+ watermarks too */
2543 dirty
|= WM_DIRTY_LP_ALL
;
2546 if (old
->wm_pipe
[pipe
] != new->wm_pipe
[pipe
]) {
2547 dirty
|= WM_DIRTY_PIPE(pipe
);
2548 /* Must disable LP1+ watermarks too */
2549 dirty
|= WM_DIRTY_LP_ALL
;
2553 if (old
->enable_fbc_wm
!= new->enable_fbc_wm
) {
2554 dirty
|= WM_DIRTY_FBC
;
2555 /* Must disable LP1+ watermarks too */
2556 dirty
|= WM_DIRTY_LP_ALL
;
2559 if (old
->partitioning
!= new->partitioning
) {
2560 dirty
|= WM_DIRTY_DDB
;
2561 /* Must disable LP1+ watermarks too */
2562 dirty
|= WM_DIRTY_LP_ALL
;
2565 /* LP1+ watermarks already deemed dirty, no need to continue */
2566 if (dirty
& WM_DIRTY_LP_ALL
)
2569 /* Find the lowest numbered LP1+ watermark in need of an update... */
2570 for (wm_lp
= 1; wm_lp
<= 3; wm_lp
++) {
2571 if (old
->wm_lp
[wm_lp
- 1] != new->wm_lp
[wm_lp
- 1] ||
2572 old
->wm_lp_spr
[wm_lp
- 1] != new->wm_lp_spr
[wm_lp
- 1])
2576 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2577 for (; wm_lp
<= 3; wm_lp
++)
2578 dirty
|= WM_DIRTY_LP(wm_lp
);
2583 static bool _ilk_disable_lp_wm(struct drm_i915_private
*dev_priv
,
2586 struct ilk_wm_values
*previous
= &dev_priv
->wm
.hw
;
2587 bool changed
= false;
2589 if (dirty
& WM_DIRTY_LP(3) && previous
->wm_lp
[2] & WM1_LP_SR_EN
) {
2590 previous
->wm_lp
[2] &= ~WM1_LP_SR_EN
;
2591 I915_WRITE(WM3_LP_ILK
, previous
->wm_lp
[2]);
2594 if (dirty
& WM_DIRTY_LP(2) && previous
->wm_lp
[1] & WM1_LP_SR_EN
) {
2595 previous
->wm_lp
[1] &= ~WM1_LP_SR_EN
;
2596 I915_WRITE(WM2_LP_ILK
, previous
->wm_lp
[1]);
2599 if (dirty
& WM_DIRTY_LP(1) && previous
->wm_lp
[0] & WM1_LP_SR_EN
) {
2600 previous
->wm_lp
[0] &= ~WM1_LP_SR_EN
;
2601 I915_WRITE(WM1_LP_ILK
, previous
->wm_lp
[0]);
2606 * Don't touch WM1S_LP_EN here.
2607 * Doing so could cause underruns.
2614 * The spec says we shouldn't write when we don't need, because every write
2615 * causes WMs to be re-evaluated, expending some power.
2617 static void ilk_write_wm_values(struct drm_i915_private
*dev_priv
,
2618 struct ilk_wm_values
*results
)
2620 struct drm_device
*dev
= dev_priv
->dev
;
2621 struct ilk_wm_values
*previous
= &dev_priv
->wm
.hw
;
2625 dirty
= ilk_compute_wm_dirty(dev
, previous
, results
);
2629 _ilk_disable_lp_wm(dev_priv
, dirty
);
2631 if (dirty
& WM_DIRTY_PIPE(PIPE_A
))
2632 I915_WRITE(WM0_PIPEA_ILK
, results
->wm_pipe
[0]);
2633 if (dirty
& WM_DIRTY_PIPE(PIPE_B
))
2634 I915_WRITE(WM0_PIPEB_ILK
, results
->wm_pipe
[1]);
2635 if (dirty
& WM_DIRTY_PIPE(PIPE_C
))
2636 I915_WRITE(WM0_PIPEC_IVB
, results
->wm_pipe
[2]);
2638 if (dirty
& WM_DIRTY_LINETIME(PIPE_A
))
2639 I915_WRITE(PIPE_WM_LINETIME(PIPE_A
), results
->wm_linetime
[0]);
2640 if (dirty
& WM_DIRTY_LINETIME(PIPE_B
))
2641 I915_WRITE(PIPE_WM_LINETIME(PIPE_B
), results
->wm_linetime
[1]);
2642 if (dirty
& WM_DIRTY_LINETIME(PIPE_C
))
2643 I915_WRITE(PIPE_WM_LINETIME(PIPE_C
), results
->wm_linetime
[2]);
2645 if (dirty
& WM_DIRTY_DDB
) {
2646 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2647 val
= I915_READ(WM_MISC
);
2648 if (results
->partitioning
== INTEL_DDB_PART_1_2
)
2649 val
&= ~WM_MISC_DATA_PARTITION_5_6
;
2651 val
|= WM_MISC_DATA_PARTITION_5_6
;
2652 I915_WRITE(WM_MISC
, val
);
2654 val
= I915_READ(DISP_ARB_CTL2
);
2655 if (results
->partitioning
== INTEL_DDB_PART_1_2
)
2656 val
&= ~DISP_DATA_PARTITION_5_6
;
2658 val
|= DISP_DATA_PARTITION_5_6
;
2659 I915_WRITE(DISP_ARB_CTL2
, val
);
2663 if (dirty
& WM_DIRTY_FBC
) {
2664 val
= I915_READ(DISP_ARB_CTL
);
2665 if (results
->enable_fbc_wm
)
2666 val
&= ~DISP_FBC_WM_DIS
;
2668 val
|= DISP_FBC_WM_DIS
;
2669 I915_WRITE(DISP_ARB_CTL
, val
);
2672 if (dirty
& WM_DIRTY_LP(1) &&
2673 previous
->wm_lp_spr
[0] != results
->wm_lp_spr
[0])
2674 I915_WRITE(WM1S_LP_ILK
, results
->wm_lp_spr
[0]);
2676 if (INTEL_INFO(dev
)->gen
>= 7) {
2677 if (dirty
& WM_DIRTY_LP(2) && previous
->wm_lp_spr
[1] != results
->wm_lp_spr
[1])
2678 I915_WRITE(WM2S_LP_IVB
, results
->wm_lp_spr
[1]);
2679 if (dirty
& WM_DIRTY_LP(3) && previous
->wm_lp_spr
[2] != results
->wm_lp_spr
[2])
2680 I915_WRITE(WM3S_LP_IVB
, results
->wm_lp_spr
[2]);
2683 if (dirty
& WM_DIRTY_LP(1) && previous
->wm_lp
[0] != results
->wm_lp
[0])
2684 I915_WRITE(WM1_LP_ILK
, results
->wm_lp
[0]);
2685 if (dirty
& WM_DIRTY_LP(2) && previous
->wm_lp
[1] != results
->wm_lp
[1])
2686 I915_WRITE(WM2_LP_ILK
, results
->wm_lp
[1]);
2687 if (dirty
& WM_DIRTY_LP(3) && previous
->wm_lp
[2] != results
->wm_lp
[2])
2688 I915_WRITE(WM3_LP_ILK
, results
->wm_lp
[2]);
2690 dev_priv
->wm
.hw
= *results
;
2693 static bool ilk_disable_lp_wm(struct drm_device
*dev
)
2695 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2697 return _ilk_disable_lp_wm(dev_priv
, WM_DIRTY_LP_ALL
);
2700 static void ilk_update_wm(struct drm_crtc
*crtc
)
2702 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2703 struct drm_device
*dev
= crtc
->dev
;
2704 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2705 struct ilk_wm_maximums max
;
2706 struct ilk_pipe_wm_parameters params
= {};
2707 struct ilk_wm_values results
= {};
2708 enum intel_ddb_partitioning partitioning
;
2709 struct intel_pipe_wm pipe_wm
= {};
2710 struct intel_pipe_wm lp_wm_1_2
= {}, lp_wm_5_6
= {}, *best_lp_wm
;
2711 struct intel_wm_config config
= {};
2713 ilk_compute_wm_parameters(crtc
, ¶ms
);
2715 intel_compute_pipe_wm(crtc
, ¶ms
, &pipe_wm
);
2717 if (!memcmp(&intel_crtc
->wm
.active
, &pipe_wm
, sizeof(pipe_wm
)))
2720 intel_crtc
->wm
.active
= pipe_wm
;
2722 ilk_compute_wm_config(dev
, &config
);
2724 ilk_compute_wm_maximums(dev
, 1, &config
, INTEL_DDB_PART_1_2
, &max
);
2725 ilk_wm_merge(dev
, &config
, &max
, &lp_wm_1_2
);
2727 /* 5/6 split only in single pipe config on IVB+ */
2728 if (INTEL_INFO(dev
)->gen
>= 7 &&
2729 config
.num_pipes_active
== 1 && config
.sprites_enabled
) {
2730 ilk_compute_wm_maximums(dev
, 1, &config
, INTEL_DDB_PART_5_6
, &max
);
2731 ilk_wm_merge(dev
, &config
, &max
, &lp_wm_5_6
);
2733 best_lp_wm
= ilk_find_best_result(dev
, &lp_wm_1_2
, &lp_wm_5_6
);
2735 best_lp_wm
= &lp_wm_1_2
;
2738 partitioning
= (best_lp_wm
== &lp_wm_1_2
) ?
2739 INTEL_DDB_PART_1_2
: INTEL_DDB_PART_5_6
;
2741 ilk_compute_wm_results(dev
, best_lp_wm
, partitioning
, &results
);
2743 ilk_write_wm_values(dev_priv
, &results
);
2746 static void ilk_update_sprite_wm(struct drm_plane
*plane
,
2747 struct drm_crtc
*crtc
,
2748 uint32_t sprite_width
, int pixel_size
,
2749 bool enabled
, bool scaled
)
2751 struct drm_device
*dev
= plane
->dev
;
2752 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
2754 intel_plane
->wm
.enabled
= enabled
;
2755 intel_plane
->wm
.scaled
= scaled
;
2756 intel_plane
->wm
.horiz_pixels
= sprite_width
;
2757 intel_plane
->wm
.bytes_per_pixel
= pixel_size
;
2760 * IVB workaround: must disable low power watermarks for at least
2761 * one frame before enabling scaling. LP watermarks can be re-enabled
2762 * when scaling is disabled.
2764 * WaCxSRDisabledForSpriteScaling:ivb
2766 if (IS_IVYBRIDGE(dev
) && scaled
&& ilk_disable_lp_wm(dev
))
2767 intel_wait_for_vblank(dev
, intel_plane
->pipe
);
2769 ilk_update_wm(crtc
);
2772 static void ilk_pipe_wm_get_hw_state(struct drm_crtc
*crtc
)
2774 struct drm_device
*dev
= crtc
->dev
;
2775 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2776 struct ilk_wm_values
*hw
= &dev_priv
->wm
.hw
;
2777 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2778 struct intel_pipe_wm
*active
= &intel_crtc
->wm
.active
;
2779 enum pipe pipe
= intel_crtc
->pipe
;
2780 static const unsigned int wm0_pipe_reg
[] = {
2781 [PIPE_A
] = WM0_PIPEA_ILK
,
2782 [PIPE_B
] = WM0_PIPEB_ILK
,
2783 [PIPE_C
] = WM0_PIPEC_IVB
,
2786 hw
->wm_pipe
[pipe
] = I915_READ(wm0_pipe_reg
[pipe
]);
2787 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2788 hw
->wm_linetime
[pipe
] = I915_READ(PIPE_WM_LINETIME(pipe
));
2790 active
->pipe_enabled
= intel_crtc_active(crtc
);
2792 if (active
->pipe_enabled
) {
2793 u32 tmp
= hw
->wm_pipe
[pipe
];
2796 * For active pipes LP0 watermark is marked as
2797 * enabled, and LP1+ watermaks as disabled since
2798 * we can't really reverse compute them in case
2799 * multiple pipes are active.
2801 active
->wm
[0].enable
= true;
2802 active
->wm
[0].pri_val
= (tmp
& WM0_PIPE_PLANE_MASK
) >> WM0_PIPE_PLANE_SHIFT
;
2803 active
->wm
[0].spr_val
= (tmp
& WM0_PIPE_SPRITE_MASK
) >> WM0_PIPE_SPRITE_SHIFT
;
2804 active
->wm
[0].cur_val
= tmp
& WM0_PIPE_CURSOR_MASK
;
2805 active
->linetime
= hw
->wm_linetime
[pipe
];
2807 int level
, max_level
= ilk_wm_max_level(dev
);
2810 * For inactive pipes, all watermark levels
2811 * should be marked as enabled but zeroed,
2812 * which is what we'd compute them to.
2814 for (level
= 0; level
<= max_level
; level
++)
2815 active
->wm
[level
].enable
= true;
2819 void ilk_wm_get_hw_state(struct drm_device
*dev
)
2821 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2822 struct ilk_wm_values
*hw
= &dev_priv
->wm
.hw
;
2823 struct drm_crtc
*crtc
;
2825 for_each_crtc(dev
, crtc
)
2826 ilk_pipe_wm_get_hw_state(crtc
);
2828 hw
->wm_lp
[0] = I915_READ(WM1_LP_ILK
);
2829 hw
->wm_lp
[1] = I915_READ(WM2_LP_ILK
);
2830 hw
->wm_lp
[2] = I915_READ(WM3_LP_ILK
);
2832 hw
->wm_lp_spr
[0] = I915_READ(WM1S_LP_ILK
);
2833 if (INTEL_INFO(dev
)->gen
>= 7) {
2834 hw
->wm_lp_spr
[1] = I915_READ(WM2S_LP_IVB
);
2835 hw
->wm_lp_spr
[2] = I915_READ(WM3S_LP_IVB
);
2838 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2839 hw
->partitioning
= (I915_READ(WM_MISC
) & WM_MISC_DATA_PARTITION_5_6
) ?
2840 INTEL_DDB_PART_5_6
: INTEL_DDB_PART_1_2
;
2841 else if (IS_IVYBRIDGE(dev
))
2842 hw
->partitioning
= (I915_READ(DISP_ARB_CTL2
) & DISP_DATA_PARTITION_5_6
) ?
2843 INTEL_DDB_PART_5_6
: INTEL_DDB_PART_1_2
;
2846 !(I915_READ(DISP_ARB_CTL
) & DISP_FBC_WM_DIS
);
2850 * intel_update_watermarks - update FIFO watermark values based on current modes
2852 * Calculate watermark values for the various WM regs based on current mode
2853 * and plane configuration.
2855 * There are several cases to deal with here:
2856 * - normal (i.e. non-self-refresh)
2857 * - self-refresh (SR) mode
2858 * - lines are large relative to FIFO size (buffer can hold up to 2)
2859 * - lines are small relative to FIFO size (buffer can hold more than 2
2860 * lines), so need to account for TLB latency
2862 * The normal calculation is:
2863 * watermark = dotclock * bytes per pixel * latency
2864 * where latency is platform & configuration dependent (we assume pessimal
2867 * The SR calculation is:
2868 * watermark = (trunc(latency/line time)+1) * surface width *
2871 * line time = htotal / dotclock
2872 * surface width = hdisplay for normal plane and 64 for cursor
2873 * and latency is assumed to be high, as above.
2875 * The final value programmed to the register should always be rounded up,
2876 * and include an extra 2 entries to account for clock crossings.
2878 * We don't use the sprite, so we can ignore that. And on Crestline we have
2879 * to set the non-SR watermarks to 8.
2881 void intel_update_watermarks(struct drm_crtc
*crtc
)
2883 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
2885 if (dev_priv
->display
.update_wm
)
2886 dev_priv
->display
.update_wm(crtc
);
2889 void intel_update_sprite_watermarks(struct drm_plane
*plane
,
2890 struct drm_crtc
*crtc
,
2891 uint32_t sprite_width
, int pixel_size
,
2892 bool enabled
, bool scaled
)
2894 struct drm_i915_private
*dev_priv
= plane
->dev
->dev_private
;
2896 if (dev_priv
->display
.update_sprite_wm
)
2897 dev_priv
->display
.update_sprite_wm(plane
, crtc
, sprite_width
,
2898 pixel_size
, enabled
, scaled
);
2901 static struct drm_i915_gem_object
*
2902 intel_alloc_context_page(struct drm_device
*dev
)
2904 struct drm_i915_gem_object
*ctx
;
2907 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
2909 ctx
= i915_gem_alloc_object(dev
, 4096);
2911 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
2915 ret
= i915_gem_obj_ggtt_pin(ctx
, 4096, 0);
2917 DRM_ERROR("failed to pin power context: %d\n", ret
);
2921 ret
= i915_gem_object_set_to_gtt_domain(ctx
, 1);
2923 DRM_ERROR("failed to set-domain on power context: %d\n", ret
);
2930 i915_gem_object_ggtt_unpin(ctx
);
2932 drm_gem_object_unreference(&ctx
->base
);
2937 * Lock protecting IPS related data structures
2939 DEFINE_SPINLOCK(mchdev_lock
);
2941 /* Global for IPS driver to get at the current i915 device. Protected by
2943 static struct drm_i915_private
*i915_mch_dev
;
2945 bool ironlake_set_drps(struct drm_device
*dev
, u8 val
)
2947 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2950 assert_spin_locked(&mchdev_lock
);
2952 rgvswctl
= I915_READ16(MEMSWCTL
);
2953 if (rgvswctl
& MEMCTL_CMD_STS
) {
2954 DRM_DEBUG("gpu busy, RCS change rejected\n");
2955 return false; /* still busy with another command */
2958 rgvswctl
= (MEMCTL_CMD_CHFREQ
<< MEMCTL_CMD_SHIFT
) |
2959 (val
<< MEMCTL_FREQ_SHIFT
) | MEMCTL_SFCAVM
;
2960 I915_WRITE16(MEMSWCTL
, rgvswctl
);
2961 POSTING_READ16(MEMSWCTL
);
2963 rgvswctl
|= MEMCTL_CMD_STS
;
2964 I915_WRITE16(MEMSWCTL
, rgvswctl
);
2969 static void ironlake_enable_drps(struct drm_device
*dev
)
2971 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2972 u32 rgvmodectl
= I915_READ(MEMMODECTL
);
2973 u8 fmax
, fmin
, fstart
, vstart
;
2975 spin_lock_irq(&mchdev_lock
);
2977 /* Enable temp reporting */
2978 I915_WRITE16(PMMISC
, I915_READ(PMMISC
) | MCPPCE_EN
);
2979 I915_WRITE16(TSC1
, I915_READ(TSC1
) | TSE
);
2981 /* 100ms RC evaluation intervals */
2982 I915_WRITE(RCUPEI
, 100000);
2983 I915_WRITE(RCDNEI
, 100000);
2985 /* Set max/min thresholds to 90ms and 80ms respectively */
2986 I915_WRITE(RCBMAXAVG
, 90000);
2987 I915_WRITE(RCBMINAVG
, 80000);
2989 I915_WRITE(MEMIHYST
, 1);
2991 /* Set up min, max, and cur for interrupt handling */
2992 fmax
= (rgvmodectl
& MEMMODE_FMAX_MASK
) >> MEMMODE_FMAX_SHIFT
;
2993 fmin
= (rgvmodectl
& MEMMODE_FMIN_MASK
);
2994 fstart
= (rgvmodectl
& MEMMODE_FSTART_MASK
) >>
2995 MEMMODE_FSTART_SHIFT
;
2997 vstart
= (I915_READ(PXVFREQ_BASE
+ (fstart
* 4)) & PXVFREQ_PX_MASK
) >>
3000 dev_priv
->ips
.fmax
= fmax
; /* IPS callback will increase this */
3001 dev_priv
->ips
.fstart
= fstart
;
3003 dev_priv
->ips
.max_delay
= fstart
;
3004 dev_priv
->ips
.min_delay
= fmin
;
3005 dev_priv
->ips
.cur_delay
= fstart
;
3007 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
3008 fmax
, fmin
, fstart
);
3010 I915_WRITE(MEMINTREN
, MEMINT_CX_SUPR_EN
| MEMINT_EVAL_CHG_EN
);
3013 * Interrupts will be enabled in ironlake_irq_postinstall
3016 I915_WRITE(VIDSTART
, vstart
);
3017 POSTING_READ(VIDSTART
);
3019 rgvmodectl
|= MEMMODE_SWMODE_EN
;
3020 I915_WRITE(MEMMODECTL
, rgvmodectl
);
3022 if (wait_for_atomic((I915_READ(MEMSWCTL
) & MEMCTL_CMD_STS
) == 0, 10))
3023 DRM_ERROR("stuck trying to change perf mode\n");
3026 ironlake_set_drps(dev
, fstart
);
3028 dev_priv
->ips
.last_count1
= I915_READ(0x112e4) + I915_READ(0x112e8) +
3030 dev_priv
->ips
.last_time1
= jiffies_to_msecs(jiffies
);
3031 dev_priv
->ips
.last_count2
= I915_READ(0x112f4);
3032 getrawmonotonic(&dev_priv
->ips
.last_time2
);
3034 spin_unlock_irq(&mchdev_lock
);
3037 static void ironlake_disable_drps(struct drm_device
*dev
)
3039 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3042 spin_lock_irq(&mchdev_lock
);
3044 rgvswctl
= I915_READ16(MEMSWCTL
);
3046 /* Ack interrupts, disable EFC interrupt */
3047 I915_WRITE(MEMINTREN
, I915_READ(MEMINTREN
) & ~MEMINT_EVAL_CHG_EN
);
3048 I915_WRITE(MEMINTRSTS
, MEMINT_EVAL_CHG
);
3049 I915_WRITE(DEIER
, I915_READ(DEIER
) & ~DE_PCU_EVENT
);
3050 I915_WRITE(DEIIR
, DE_PCU_EVENT
);
3051 I915_WRITE(DEIMR
, I915_READ(DEIMR
) | DE_PCU_EVENT
);
3053 /* Go back to the starting frequency */
3054 ironlake_set_drps(dev
, dev_priv
->ips
.fstart
);
3056 rgvswctl
|= MEMCTL_CMD_STS
;
3057 I915_WRITE(MEMSWCTL
, rgvswctl
);
3060 spin_unlock_irq(&mchdev_lock
);
3063 /* There's a funny hw issue where the hw returns all 0 when reading from
3064 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3065 * ourselves, instead of doing a rmw cycle (which might result in us clearing
3066 * all limits and the gpu stuck at whatever frequency it is at atm).
3068 static u32
gen6_rps_limits(struct drm_i915_private
*dev_priv
, u8 val
)
3072 /* Only set the down limit when we've reached the lowest level to avoid
3073 * getting more interrupts, otherwise leave this clear. This prevents a
3074 * race in the hw when coming out of rc6: There's a tiny window where
3075 * the hw runs at the minimal clock before selecting the desired
3076 * frequency, if the down threshold expires in that window we will not
3077 * receive a down interrupt. */
3078 limits
= dev_priv
->rps
.max_freq_softlimit
<< 24;
3079 if (val
<= dev_priv
->rps
.min_freq_softlimit
)
3080 limits
|= dev_priv
->rps
.min_freq_softlimit
<< 16;
3085 static void gen6_set_rps_thresholds(struct drm_i915_private
*dev_priv
, u8 val
)
3089 new_power
= dev_priv
->rps
.power
;
3090 switch (dev_priv
->rps
.power
) {
3092 if (val
> dev_priv
->rps
.efficient_freq
+ 1 && val
> dev_priv
->rps
.cur_freq
)
3093 new_power
= BETWEEN
;
3097 if (val
<= dev_priv
->rps
.efficient_freq
&& val
< dev_priv
->rps
.cur_freq
)
3098 new_power
= LOW_POWER
;
3099 else if (val
>= dev_priv
->rps
.rp0_freq
&& val
> dev_priv
->rps
.cur_freq
)
3100 new_power
= HIGH_POWER
;
3104 if (val
< (dev_priv
->rps
.rp1_freq
+ dev_priv
->rps
.rp0_freq
) >> 1 && val
< dev_priv
->rps
.cur_freq
)
3105 new_power
= BETWEEN
;
3108 /* Max/min bins are special */
3109 if (val
== dev_priv
->rps
.min_freq_softlimit
)
3110 new_power
= LOW_POWER
;
3111 if (val
== dev_priv
->rps
.max_freq_softlimit
)
3112 new_power
= HIGH_POWER
;
3113 if (new_power
== dev_priv
->rps
.power
)
3116 /* Note the units here are not exactly 1us, but 1280ns. */
3117 switch (new_power
) {
3119 /* Upclock if more than 95% busy over 16ms */
3120 I915_WRITE(GEN6_RP_UP_EI
, 12500);
3121 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 11800);
3123 /* Downclock if less than 85% busy over 32ms */
3124 I915_WRITE(GEN6_RP_DOWN_EI
, 25000);
3125 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 21250);
3127 I915_WRITE(GEN6_RP_CONTROL
,
3128 GEN6_RP_MEDIA_TURBO
|
3129 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
3130 GEN6_RP_MEDIA_IS_GFX
|
3132 GEN6_RP_UP_BUSY_AVG
|
3133 GEN6_RP_DOWN_IDLE_AVG
);
3137 /* Upclock if more than 90% busy over 13ms */
3138 I915_WRITE(GEN6_RP_UP_EI
, 10250);
3139 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 9225);
3141 /* Downclock if less than 75% busy over 32ms */
3142 I915_WRITE(GEN6_RP_DOWN_EI
, 25000);
3143 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 18750);
3145 I915_WRITE(GEN6_RP_CONTROL
,
3146 GEN6_RP_MEDIA_TURBO
|
3147 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
3148 GEN6_RP_MEDIA_IS_GFX
|
3150 GEN6_RP_UP_BUSY_AVG
|
3151 GEN6_RP_DOWN_IDLE_AVG
);
3155 /* Upclock if more than 85% busy over 10ms */
3156 I915_WRITE(GEN6_RP_UP_EI
, 8000);
3157 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 6800);
3159 /* Downclock if less than 60% busy over 32ms */
3160 I915_WRITE(GEN6_RP_DOWN_EI
, 25000);
3161 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 15000);
3163 I915_WRITE(GEN6_RP_CONTROL
,
3164 GEN6_RP_MEDIA_TURBO
|
3165 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
3166 GEN6_RP_MEDIA_IS_GFX
|
3168 GEN6_RP_UP_BUSY_AVG
|
3169 GEN6_RP_DOWN_IDLE_AVG
);
3173 dev_priv
->rps
.power
= new_power
;
3174 dev_priv
->rps
.last_adj
= 0;
3177 static u32
gen6_rps_pm_mask(struct drm_i915_private
*dev_priv
, u8 val
)
3181 if (val
> dev_priv
->rps
.min_freq_softlimit
)
3182 mask
|= GEN6_PM_RP_DOWN_THRESHOLD
| GEN6_PM_RP_DOWN_TIMEOUT
;
3183 if (val
< dev_priv
->rps
.max_freq_softlimit
)
3184 mask
|= GEN6_PM_RP_UP_THRESHOLD
;
3186 mask
|= dev_priv
->pm_rps_events
& (GEN6_PM_RP_DOWN_EI_EXPIRED
| GEN6_PM_RP_UP_EI_EXPIRED
);
3187 mask
&= dev_priv
->pm_rps_events
;
3189 /* IVB and SNB hard hangs on looping batchbuffer
3190 * if GEN6_PM_UP_EI_EXPIRED is masked.
3192 if (INTEL_INFO(dev_priv
->dev
)->gen
<= 7 && !IS_HASWELL(dev_priv
->dev
))
3193 mask
|= GEN6_PM_RP_UP_EI_EXPIRED
;
3195 if (IS_GEN8(dev_priv
->dev
))
3196 mask
|= GEN8_PMINTR_REDIRECT_TO_NON_DISP
;
3201 /* gen6_set_rps is called to update the frequency request, but should also be
3202 * called when the range (min_delay and max_delay) is modified so that we can
3203 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
3204 void gen6_set_rps(struct drm_device
*dev
, u8 val
)
3206 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3208 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
3209 WARN_ON(val
> dev_priv
->rps
.max_freq_softlimit
);
3210 WARN_ON(val
< dev_priv
->rps
.min_freq_softlimit
);
3212 /* min/max delay may still have been modified so be sure to
3213 * write the limits value.
3215 if (val
!= dev_priv
->rps
.cur_freq
) {
3216 gen6_set_rps_thresholds(dev_priv
, val
);
3218 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
3219 I915_WRITE(GEN6_RPNSWREQ
,
3220 HSW_FREQUENCY(val
));
3222 I915_WRITE(GEN6_RPNSWREQ
,
3223 GEN6_FREQUENCY(val
) |
3225 GEN6_AGGRESSIVE_TURBO
);
3228 /* Make sure we continue to get interrupts
3229 * until we hit the minimum or maximum frequencies.
3231 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS
, gen6_rps_limits(dev_priv
, val
));
3232 I915_WRITE(GEN6_PMINTRMSK
, gen6_rps_pm_mask(dev_priv
, val
));
3234 POSTING_READ(GEN6_RPNSWREQ
);
3236 dev_priv
->rps
.cur_freq
= val
;
3237 trace_intel_gpu_freq_change(val
* 50);
3240 /* vlv_set_rps_idle: Set the frequency to Rpn if Gfx clocks are down
3242 * * If Gfx is Idle, then
3243 * 1. Mask Turbo interrupts
3244 * 2. Bring up Gfx clock
3245 * 3. Change the freq to Rpn and wait till P-Unit updates freq
3246 * 4. Clear the Force GFX CLK ON bit so that Gfx can down
3247 * 5. Unmask Turbo interrupts
3249 static void vlv_set_rps_idle(struct drm_i915_private
*dev_priv
)
3251 struct drm_device
*dev
= dev_priv
->dev
;
3253 /* Latest VLV doesn't need to force the gfx clock */
3254 if (dev
->pdev
->revision
>= 0xd) {
3255 valleyview_set_rps(dev_priv
->dev
, dev_priv
->rps
.min_freq_softlimit
);
3260 * When we are idle. Drop to min voltage state.
3263 if (dev_priv
->rps
.cur_freq
<= dev_priv
->rps
.min_freq_softlimit
)
3266 /* Mask turbo interrupt so that they will not come in between */
3267 I915_WRITE(GEN6_PMINTRMSK
, 0xffffffff);
3269 vlv_force_gfx_clock(dev_priv
, true);
3271 dev_priv
->rps
.cur_freq
= dev_priv
->rps
.min_freq_softlimit
;
3273 vlv_punit_write(dev_priv
, PUNIT_REG_GPU_FREQ_REQ
,
3274 dev_priv
->rps
.min_freq_softlimit
);
3276 if (wait_for(((vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
))
3277 & GENFREQSTATUS
) == 0, 5))
3278 DRM_ERROR("timed out waiting for Punit\n");
3280 vlv_force_gfx_clock(dev_priv
, false);
3282 I915_WRITE(GEN6_PMINTRMSK
,
3283 gen6_rps_pm_mask(dev_priv
, dev_priv
->rps
.cur_freq
));
3286 void gen6_rps_idle(struct drm_i915_private
*dev_priv
)
3288 struct drm_device
*dev
= dev_priv
->dev
;
3290 mutex_lock(&dev_priv
->rps
.hw_lock
);
3291 if (dev_priv
->rps
.enabled
) {
3292 if (IS_VALLEYVIEW(dev
))
3293 vlv_set_rps_idle(dev_priv
);
3295 gen6_set_rps(dev_priv
->dev
, dev_priv
->rps
.min_freq_softlimit
);
3296 dev_priv
->rps
.last_adj
= 0;
3298 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3301 void gen6_rps_boost(struct drm_i915_private
*dev_priv
)
3303 struct drm_device
*dev
= dev_priv
->dev
;
3305 mutex_lock(&dev_priv
->rps
.hw_lock
);
3306 if (dev_priv
->rps
.enabled
) {
3307 if (IS_VALLEYVIEW(dev
))
3308 valleyview_set_rps(dev_priv
->dev
, dev_priv
->rps
.max_freq_softlimit
);
3310 gen6_set_rps(dev_priv
->dev
, dev_priv
->rps
.max_freq_softlimit
);
3311 dev_priv
->rps
.last_adj
= 0;
3313 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3316 void valleyview_set_rps(struct drm_device
*dev
, u8 val
)
3318 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3320 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
3321 WARN_ON(val
> dev_priv
->rps
.max_freq_softlimit
);
3322 WARN_ON(val
< dev_priv
->rps
.min_freq_softlimit
);
3324 DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
3325 vlv_gpu_freq(dev_priv
, dev_priv
->rps
.cur_freq
),
3326 dev_priv
->rps
.cur_freq
,
3327 vlv_gpu_freq(dev_priv
, val
), val
);
3329 if (val
!= dev_priv
->rps
.cur_freq
)
3330 vlv_punit_write(dev_priv
, PUNIT_REG_GPU_FREQ_REQ
, val
);
3332 I915_WRITE(GEN6_PMINTRMSK
, gen6_rps_pm_mask(dev_priv
, val
));
3334 dev_priv
->rps
.cur_freq
= val
;
3335 trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv
, val
));
3338 static void gen8_disable_rps_interrupts(struct drm_device
*dev
)
3340 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3342 I915_WRITE(GEN6_PMINTRMSK
, ~GEN8_PMINTR_REDIRECT_TO_NON_DISP
);
3343 I915_WRITE(GEN8_GT_IER(2), I915_READ(GEN8_GT_IER(2)) &
3344 ~dev_priv
->pm_rps_events
);
3345 /* Complete PM interrupt masking here doesn't race with the rps work
3346 * item again unmasking PM interrupts because that is using a different
3347 * register (GEN8_GT_IMR(2)) to mask PM interrupts. The only risk is in
3348 * leaving stale bits in GEN8_GT_IIR(2) and GEN8_GT_IMR(2) which
3349 * gen8_enable_rps will clean up. */
3351 spin_lock_irq(&dev_priv
->irq_lock
);
3352 dev_priv
->rps
.pm_iir
= 0;
3353 spin_unlock_irq(&dev_priv
->irq_lock
);
3355 I915_WRITE(GEN8_GT_IIR(2), dev_priv
->pm_rps_events
);
3358 static void gen6_disable_rps_interrupts(struct drm_device
*dev
)
3360 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3362 I915_WRITE(GEN6_PMINTRMSK
, 0xffffffff);
3363 I915_WRITE(GEN6_PMIER
, I915_READ(GEN6_PMIER
) &
3364 ~dev_priv
->pm_rps_events
);
3365 /* Complete PM interrupt masking here doesn't race with the rps work
3366 * item again unmasking PM interrupts because that is using a different
3367 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3368 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3370 spin_lock_irq(&dev_priv
->irq_lock
);
3371 dev_priv
->rps
.pm_iir
= 0;
3372 spin_unlock_irq(&dev_priv
->irq_lock
);
3374 I915_WRITE(GEN6_PMIIR
, dev_priv
->pm_rps_events
);
3377 static void gen6_disable_rps(struct drm_device
*dev
)
3379 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3381 I915_WRITE(GEN6_RC_CONTROL
, 0);
3382 I915_WRITE(GEN6_RPNSWREQ
, 1 << 31);
3384 if (IS_BROADWELL(dev
))
3385 gen8_disable_rps_interrupts(dev
);
3387 gen6_disable_rps_interrupts(dev
);
3390 static void cherryview_disable_rps(struct drm_device
*dev
)
3392 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3394 I915_WRITE(GEN6_RC_CONTROL
, 0);
3397 static void valleyview_disable_rps(struct drm_device
*dev
)
3399 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3401 I915_WRITE(GEN6_RC_CONTROL
, 0);
3403 gen6_disable_rps_interrupts(dev
);
3406 static void intel_print_rc6_info(struct drm_device
*dev
, u32 mode
)
3408 if (IS_VALLEYVIEW(dev
)) {
3409 if (mode
& (GEN7_RC_CTL_TO_MODE
| GEN6_RC_CTL_EI_MODE(1)))
3410 mode
= GEN6_RC_CTL_RC6_ENABLE
;
3414 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
3415 (mode
& GEN6_RC_CTL_RC6_ENABLE
) ? "on" : "off",
3416 (mode
& GEN6_RC_CTL_RC6p_ENABLE
) ? "on" : "off",
3417 (mode
& GEN6_RC_CTL_RC6pp_ENABLE
) ? "on" : "off");
3420 static int sanitize_rc6_option(const struct drm_device
*dev
, int enable_rc6
)
3422 /* No RC6 before Ironlake */
3423 if (INTEL_INFO(dev
)->gen
< 5)
3426 /* RC6 is only on Ironlake mobile not on desktop */
3427 if (INTEL_INFO(dev
)->gen
== 5 && !IS_IRONLAKE_M(dev
))
3430 /* Respect the kernel parameter if it is set */
3431 if (enable_rc6
>= 0) {
3434 if (INTEL_INFO(dev
)->gen
== 6 || IS_IVYBRIDGE(dev
))
3435 mask
= INTEL_RC6_ENABLE
| INTEL_RC6p_ENABLE
|
3438 mask
= INTEL_RC6_ENABLE
;
3440 if ((enable_rc6
& mask
) != enable_rc6
)
3441 DRM_INFO("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
3442 enable_rc6
& mask
, enable_rc6
, mask
);
3444 return enable_rc6
& mask
;
3447 /* Disable RC6 on Ironlake */
3448 if (INTEL_INFO(dev
)->gen
== 5)
3451 if (IS_IVYBRIDGE(dev
))
3452 return (INTEL_RC6_ENABLE
| INTEL_RC6p_ENABLE
);
3454 return INTEL_RC6_ENABLE
;
3457 int intel_enable_rc6(const struct drm_device
*dev
)
3459 return i915
.enable_rc6
;
3462 static void gen8_enable_rps_interrupts(struct drm_device
*dev
)
3464 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3466 spin_lock_irq(&dev_priv
->irq_lock
);
3467 WARN_ON(dev_priv
->rps
.pm_iir
);
3468 bdw_enable_pm_irq(dev_priv
, dev_priv
->pm_rps_events
);
3469 I915_WRITE(GEN8_GT_IIR(2), dev_priv
->pm_rps_events
);
3470 spin_unlock_irq(&dev_priv
->irq_lock
);
3473 static void gen6_enable_rps_interrupts(struct drm_device
*dev
)
3475 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3477 spin_lock_irq(&dev_priv
->irq_lock
);
3478 WARN_ON(dev_priv
->rps
.pm_iir
);
3479 snb_enable_pm_irq(dev_priv
, dev_priv
->pm_rps_events
);
3480 I915_WRITE(GEN6_PMIIR
, dev_priv
->pm_rps_events
);
3481 spin_unlock_irq(&dev_priv
->irq_lock
);
3484 static void parse_rp_state_cap(struct drm_i915_private
*dev_priv
, u32 rp_state_cap
)
3486 /* All of these values are in units of 50MHz */
3487 dev_priv
->rps
.cur_freq
= 0;
3488 /* static values from HW: RP0 < RPe < RP1 < RPn (min_freq) */
3489 dev_priv
->rps
.rp1_freq
= (rp_state_cap
>> 8) & 0xff;
3490 dev_priv
->rps
.rp0_freq
= (rp_state_cap
>> 0) & 0xff;
3491 dev_priv
->rps
.min_freq
= (rp_state_cap
>> 16) & 0xff;
3492 /* XXX: only BYT has a special efficient freq */
3493 dev_priv
->rps
.efficient_freq
= dev_priv
->rps
.rp1_freq
;
3494 /* hw_max = RP0 until we check for overclocking */
3495 dev_priv
->rps
.max_freq
= dev_priv
->rps
.rp0_freq
;
3497 /* Preserve min/max settings in case of re-init */
3498 if (dev_priv
->rps
.max_freq_softlimit
== 0)
3499 dev_priv
->rps
.max_freq_softlimit
= dev_priv
->rps
.max_freq
;
3501 if (dev_priv
->rps
.min_freq_softlimit
== 0)
3502 dev_priv
->rps
.min_freq_softlimit
= dev_priv
->rps
.min_freq
;
3505 static void gen8_enable_rps(struct drm_device
*dev
)
3507 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3508 struct intel_engine_cs
*ring
;
3509 uint32_t rc6_mask
= 0, rp_state_cap
;
3512 /* 1a: Software RC state - RC0 */
3513 I915_WRITE(GEN6_RC_STATE
, 0);
3515 /* 1c & 1d: Get forcewake during program sequence. Although the driver
3516 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
3517 gen6_gt_force_wake_get(dev_priv
, FORCEWAKE_ALL
);
3519 /* 2a: Disable RC states. */
3520 I915_WRITE(GEN6_RC_CONTROL
, 0);
3522 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
3523 parse_rp_state_cap(dev_priv
, rp_state_cap
);
3525 /* 2b: Program RC6 thresholds.*/
3526 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 40 << 16);
3527 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000); /* 12500 * 1280ns */
3528 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25); /* 25 * 1280ns */
3529 for_each_ring(ring
, dev_priv
, unused
)
3530 I915_WRITE(RING_MAX_IDLE(ring
->mmio_base
), 10);
3531 I915_WRITE(GEN6_RC_SLEEP
, 0);
3532 if (IS_BROADWELL(dev
))
3533 I915_WRITE(GEN6_RC6_THRESHOLD
, 625); /* 800us/1.28 for TO */
3535 I915_WRITE(GEN6_RC6_THRESHOLD
, 50000); /* 50/125ms per EI */
3538 if (intel_enable_rc6(dev
) & INTEL_RC6_ENABLE
)
3539 rc6_mask
= GEN6_RC_CTL_RC6_ENABLE
;
3540 intel_print_rc6_info(dev
, rc6_mask
);
3541 if (IS_BROADWELL(dev
))
3542 I915_WRITE(GEN6_RC_CONTROL
, GEN6_RC_CTL_HW_ENABLE
|
3543 GEN7_RC_CTL_TO_MODE
|
3546 I915_WRITE(GEN6_RC_CONTROL
, GEN6_RC_CTL_HW_ENABLE
|
3547 GEN6_RC_CTL_EI_MODE(1) |
3550 /* 4 Program defaults and thresholds for RPS*/
3551 I915_WRITE(GEN6_RPNSWREQ
,
3552 HSW_FREQUENCY(dev_priv
->rps
.rp1_freq
));
3553 I915_WRITE(GEN6_RC_VIDEO_FREQ
,
3554 HSW_FREQUENCY(dev_priv
->rps
.rp1_freq
));
3555 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
3556 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 100000000 / 128); /* 1 second timeout */
3558 /* Docs recommend 900MHz, and 300 MHz respectively */
3559 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS
,
3560 dev_priv
->rps
.max_freq_softlimit
<< 24 |
3561 dev_priv
->rps
.min_freq_softlimit
<< 16);
3563 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 7600000 / 128); /* 76ms busyness per EI, 90% */
3564 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 31300000 / 128); /* 313ms busyness per EI, 70%*/
3565 I915_WRITE(GEN6_RP_UP_EI
, 66000); /* 84.48ms, XXX: random? */
3566 I915_WRITE(GEN6_RP_DOWN_EI
, 350000); /* 448ms, XXX: random? */
3568 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
3571 I915_WRITE(GEN6_RP_CONTROL
,
3572 GEN6_RP_MEDIA_TURBO
|
3573 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
3574 GEN6_RP_MEDIA_IS_GFX
|
3576 GEN6_RP_UP_BUSY_AVG
|
3577 GEN6_RP_DOWN_IDLE_AVG
);
3579 /* 6: Ring frequency + overclocking (our driver does this later */
3581 gen6_set_rps(dev
, (I915_READ(GEN6_GT_PERF_STATUS
) & 0xff00) >> 8);
3583 gen8_enable_rps_interrupts(dev
);
3585 gen6_gt_force_wake_put(dev_priv
, FORCEWAKE_ALL
);
3588 static void gen6_enable_rps(struct drm_device
*dev
)
3590 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3591 struct intel_engine_cs
*ring
;
3594 u32 rc6vids
, pcu_mbox
= 0, rc6_mask
= 0;
3599 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
3601 /* Here begins a magic sequence of register writes to enable
3602 * auto-downclocking.
3604 * Perhaps there might be some value in exposing these to
3607 I915_WRITE(GEN6_RC_STATE
, 0);
3609 /* Clear the DBG now so we don't confuse earlier errors */
3610 if ((gtfifodbg
= I915_READ(GTFIFODBG
))) {
3611 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg
);
3612 I915_WRITE(GTFIFODBG
, gtfifodbg
);
3615 gen6_gt_force_wake_get(dev_priv
, FORCEWAKE_ALL
);
3617 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
3618 gt_perf_status
= I915_READ(GEN6_GT_PERF_STATUS
);
3620 parse_rp_state_cap(dev_priv
, rp_state_cap
);
3622 /* disable the counters and set deterministic thresholds */
3623 I915_WRITE(GEN6_RC_CONTROL
, 0);
3625 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT
, 1000 << 16);
3626 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 40 << 16 | 30);
3627 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT
, 30);
3628 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000);
3629 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25);
3631 for_each_ring(ring
, dev_priv
, i
)
3632 I915_WRITE(RING_MAX_IDLE(ring
->mmio_base
), 10);
3634 I915_WRITE(GEN6_RC_SLEEP
, 0);
3635 I915_WRITE(GEN6_RC1e_THRESHOLD
, 1000);
3636 if (IS_IVYBRIDGE(dev
))
3637 I915_WRITE(GEN6_RC6_THRESHOLD
, 125000);
3639 I915_WRITE(GEN6_RC6_THRESHOLD
, 50000);
3640 I915_WRITE(GEN6_RC6p_THRESHOLD
, 150000);
3641 I915_WRITE(GEN6_RC6pp_THRESHOLD
, 64000); /* unused */
3643 /* Check if we are enabling RC6 */
3644 rc6_mode
= intel_enable_rc6(dev_priv
->dev
);
3645 if (rc6_mode
& INTEL_RC6_ENABLE
)
3646 rc6_mask
|= GEN6_RC_CTL_RC6_ENABLE
;
3648 /* We don't use those on Haswell */
3649 if (!IS_HASWELL(dev
)) {
3650 if (rc6_mode
& INTEL_RC6p_ENABLE
)
3651 rc6_mask
|= GEN6_RC_CTL_RC6p_ENABLE
;
3653 if (rc6_mode
& INTEL_RC6pp_ENABLE
)
3654 rc6_mask
|= GEN6_RC_CTL_RC6pp_ENABLE
;
3657 intel_print_rc6_info(dev
, rc6_mask
);
3659 I915_WRITE(GEN6_RC_CONTROL
,
3661 GEN6_RC_CTL_EI_MODE(1) |
3662 GEN6_RC_CTL_HW_ENABLE
);
3664 /* Power down if completely idle for over 50ms */
3665 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 50000);
3666 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
3668 ret
= sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_MIN_FREQ_TABLE
, 0);
3670 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
3672 ret
= sandybridge_pcode_read(dev_priv
, GEN6_READ_OC_PARAMS
, &pcu_mbox
);
3673 if (!ret
&& (pcu_mbox
& (1<<31))) { /* OC supported */
3674 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
3675 (dev_priv
->rps
.max_freq_softlimit
& 0xff) * 50,
3676 (pcu_mbox
& 0xff) * 50);
3677 dev_priv
->rps
.max_freq
= pcu_mbox
& 0xff;
3680 dev_priv
->rps
.power
= HIGH_POWER
; /* force a reset */
3681 gen6_set_rps(dev_priv
->dev
, dev_priv
->rps
.min_freq_softlimit
);
3683 gen6_enable_rps_interrupts(dev
);
3686 ret
= sandybridge_pcode_read(dev_priv
, GEN6_PCODE_READ_RC6VIDS
, &rc6vids
);
3687 if (IS_GEN6(dev
) && ret
) {
3688 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
3689 } else if (IS_GEN6(dev
) && (GEN6_DECODE_RC6_VID(rc6vids
& 0xff) < 450)) {
3690 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
3691 GEN6_DECODE_RC6_VID(rc6vids
& 0xff), 450);
3692 rc6vids
&= 0xffff00;
3693 rc6vids
|= GEN6_ENCODE_RC6_VID(450);
3694 ret
= sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_RC6VIDS
, rc6vids
);
3696 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
3699 gen6_gt_force_wake_put(dev_priv
, FORCEWAKE_ALL
);
3702 static void __gen6_update_ring_freq(struct drm_device
*dev
)
3704 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3706 unsigned int gpu_freq
;
3707 unsigned int max_ia_freq
, min_ring_freq
;
3708 int scaling_factor
= 180;
3709 struct cpufreq_policy
*policy
;
3711 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
3713 policy
= cpufreq_cpu_get(0);
3715 max_ia_freq
= policy
->cpuinfo
.max_freq
;
3716 cpufreq_cpu_put(policy
);
3719 * Default to measured freq if none found, PCU will ensure we
3722 max_ia_freq
= tsc_khz
;
3725 /* Convert from kHz to MHz */
3726 max_ia_freq
/= 1000;
3728 min_ring_freq
= I915_READ(DCLK
) & 0xf;
3729 /* convert DDR frequency from units of 266.6MHz to bandwidth */
3730 min_ring_freq
= mult_frac(min_ring_freq
, 8, 3);
3733 * For each potential GPU frequency, load a ring frequency we'd like
3734 * to use for memory access. We do this by specifying the IA frequency
3735 * the PCU should use as a reference to determine the ring frequency.
3737 for (gpu_freq
= dev_priv
->rps
.max_freq_softlimit
; gpu_freq
>= dev_priv
->rps
.min_freq_softlimit
;
3739 int diff
= dev_priv
->rps
.max_freq_softlimit
- gpu_freq
;
3740 unsigned int ia_freq
= 0, ring_freq
= 0;
3742 if (INTEL_INFO(dev
)->gen
>= 8) {
3743 /* max(2 * GT, DDR). NB: GT is 50MHz units */
3744 ring_freq
= max(min_ring_freq
, gpu_freq
);
3745 } else if (IS_HASWELL(dev
)) {
3746 ring_freq
= mult_frac(gpu_freq
, 5, 4);
3747 ring_freq
= max(min_ring_freq
, ring_freq
);
3748 /* leave ia_freq as the default, chosen by cpufreq */
3750 /* On older processors, there is no separate ring
3751 * clock domain, so in order to boost the bandwidth
3752 * of the ring, we need to upclock the CPU (ia_freq).
3754 * For GPU frequencies less than 750MHz,
3755 * just use the lowest ring freq.
3757 if (gpu_freq
< min_freq
)
3760 ia_freq
= max_ia_freq
- ((diff
* scaling_factor
) / 2);
3761 ia_freq
= DIV_ROUND_CLOSEST(ia_freq
, 100);
3764 sandybridge_pcode_write(dev_priv
,
3765 GEN6_PCODE_WRITE_MIN_FREQ_TABLE
,
3766 ia_freq
<< GEN6_PCODE_FREQ_IA_RATIO_SHIFT
|
3767 ring_freq
<< GEN6_PCODE_FREQ_RING_RATIO_SHIFT
|
3772 void gen6_update_ring_freq(struct drm_device
*dev
)
3774 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3776 if (INTEL_INFO(dev
)->gen
< 6 || IS_VALLEYVIEW(dev
))
3779 mutex_lock(&dev_priv
->rps
.hw_lock
);
3780 __gen6_update_ring_freq(dev
);
3781 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3784 int cherryview_rps_max_freq(struct drm_i915_private
*dev_priv
)
3788 val
= vlv_punit_read(dev_priv
, PUNIT_GPU_STATUS_REG
);
3789 rp0
= (val
>> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT
) & PUNIT_GPU_STATUS_MAX_FREQ_MASK
;
3794 static int cherryview_rps_rpe_freq(struct drm_i915_private
*dev_priv
)
3798 val
= vlv_punit_read(dev_priv
, PUNIT_GPU_DUTYCYCLE_REG
);
3799 rpe
= (val
>> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT
) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK
;
3804 int cherryview_rps_min_freq(struct drm_i915_private
*dev_priv
)
3808 val
= vlv_punit_read(dev_priv
, PUNIT_GPU_STATUS_REG
);
3809 rpn
= (val
>> PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT
) & PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK
;
3813 int valleyview_rps_max_freq(struct drm_i915_private
*dev_priv
)
3817 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FREQ_FUSE
);
3819 rp0
= (val
& FB_GFX_MAX_FREQ_FUSE_MASK
) >> FB_GFX_MAX_FREQ_FUSE_SHIFT
;
3821 rp0
= min_t(u32
, rp0
, 0xea);
3826 static int valleyview_rps_rpe_freq(struct drm_i915_private
*dev_priv
)
3830 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FMAX_FUSE_LO
);
3831 rpe
= (val
& FB_FMAX_VMIN_FREQ_LO_MASK
) >> FB_FMAX_VMIN_FREQ_LO_SHIFT
;
3832 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FMAX_FUSE_HI
);
3833 rpe
|= (val
& FB_FMAX_VMIN_FREQ_HI_MASK
) << 5;
3838 int valleyview_rps_min_freq(struct drm_i915_private
*dev_priv
)
3840 return vlv_punit_read(dev_priv
, PUNIT_REG_GPU_LFM
) & 0xff;
3843 /* Check that the pctx buffer wasn't move under us. */
3844 static void valleyview_check_pctx(struct drm_i915_private
*dev_priv
)
3846 unsigned long pctx_addr
= I915_READ(VLV_PCBR
) & ~4095;
3848 WARN_ON(pctx_addr
!= dev_priv
->mm
.stolen_base
+
3849 dev_priv
->vlv_pctx
->stolen
->start
);
3853 /* Check that the pcbr address is not empty. */
3854 static void cherryview_check_pctx(struct drm_i915_private
*dev_priv
)
3856 unsigned long pctx_addr
= I915_READ(VLV_PCBR
) & ~4095;
3858 WARN_ON((pctx_addr
>> VLV_PCBR_ADDR_SHIFT
) == 0);
3861 static void cherryview_setup_pctx(struct drm_device
*dev
)
3863 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3864 unsigned long pctx_paddr
, paddr
;
3865 struct i915_gtt
*gtt
= &dev_priv
->gtt
;
3867 int pctx_size
= 32*1024;
3869 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
3871 pcbr
= I915_READ(VLV_PCBR
);
3872 if ((pcbr
>> VLV_PCBR_ADDR_SHIFT
) == 0) {
3873 paddr
= (dev_priv
->mm
.stolen_base
+
3874 (gtt
->stolen_size
- pctx_size
));
3876 pctx_paddr
= (paddr
& (~4095));
3877 I915_WRITE(VLV_PCBR
, pctx_paddr
);
3881 static void valleyview_setup_pctx(struct drm_device
*dev
)
3883 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3884 struct drm_i915_gem_object
*pctx
;
3885 unsigned long pctx_paddr
;
3887 int pctx_size
= 24*1024;
3889 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
3891 pcbr
= I915_READ(VLV_PCBR
);
3893 /* BIOS set it up already, grab the pre-alloc'd space */
3896 pcbr_offset
= (pcbr
& (~4095)) - dev_priv
->mm
.stolen_base
;
3897 pctx
= i915_gem_object_create_stolen_for_preallocated(dev_priv
->dev
,
3899 I915_GTT_OFFSET_NONE
,
3905 * From the Gunit register HAS:
3906 * The Gfx driver is expected to program this register and ensure
3907 * proper allocation within Gfx stolen memory. For example, this
3908 * register should be programmed such than the PCBR range does not
3909 * overlap with other ranges, such as the frame buffer, protected
3910 * memory, or any other relevant ranges.
3912 pctx
= i915_gem_object_create_stolen(dev
, pctx_size
);
3914 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
3918 pctx_paddr
= dev_priv
->mm
.stolen_base
+ pctx
->stolen
->start
;
3919 I915_WRITE(VLV_PCBR
, pctx_paddr
);
3922 dev_priv
->vlv_pctx
= pctx
;
3925 static void valleyview_cleanup_pctx(struct drm_device
*dev
)
3927 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3929 if (WARN_ON(!dev_priv
->vlv_pctx
))
3932 drm_gem_object_unreference(&dev_priv
->vlv_pctx
->base
);
3933 dev_priv
->vlv_pctx
= NULL
;
3936 static void valleyview_init_gt_powersave(struct drm_device
*dev
)
3938 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3940 valleyview_setup_pctx(dev
);
3942 mutex_lock(&dev_priv
->rps
.hw_lock
);
3944 dev_priv
->rps
.max_freq
= valleyview_rps_max_freq(dev_priv
);
3945 dev_priv
->rps
.rp0_freq
= dev_priv
->rps
.max_freq
;
3946 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
3947 vlv_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
),
3948 dev_priv
->rps
.max_freq
);
3950 dev_priv
->rps
.efficient_freq
= valleyview_rps_rpe_freq(dev_priv
);
3951 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
3952 vlv_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
),
3953 dev_priv
->rps
.efficient_freq
);
3955 dev_priv
->rps
.min_freq
= valleyview_rps_min_freq(dev_priv
);
3956 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
3957 vlv_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
),
3958 dev_priv
->rps
.min_freq
);
3960 /* Preserve min/max settings in case of re-init */
3961 if (dev_priv
->rps
.max_freq_softlimit
== 0)
3962 dev_priv
->rps
.max_freq_softlimit
= dev_priv
->rps
.max_freq
;
3964 if (dev_priv
->rps
.min_freq_softlimit
== 0)
3965 dev_priv
->rps
.min_freq_softlimit
= dev_priv
->rps
.min_freq
;
3967 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3970 static void cherryview_init_gt_powersave(struct drm_device
*dev
)
3972 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3974 cherryview_setup_pctx(dev
);
3976 mutex_lock(&dev_priv
->rps
.hw_lock
);
3978 dev_priv
->rps
.max_freq
= cherryview_rps_max_freq(dev_priv
);
3979 dev_priv
->rps
.rp0_freq
= dev_priv
->rps
.max_freq
;
3980 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
3981 vlv_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
),
3982 dev_priv
->rps
.max_freq
);
3984 dev_priv
->rps
.efficient_freq
= cherryview_rps_rpe_freq(dev_priv
);
3985 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
3986 vlv_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
),
3987 dev_priv
->rps
.efficient_freq
);
3989 dev_priv
->rps
.min_freq
= cherryview_rps_min_freq(dev_priv
);
3990 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
3991 vlv_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
),
3992 dev_priv
->rps
.min_freq
);
3994 /* Preserve min/max settings in case of re-init */
3995 if (dev_priv
->rps
.max_freq_softlimit
== 0)
3996 dev_priv
->rps
.max_freq_softlimit
= dev_priv
->rps
.max_freq
;
3998 if (dev_priv
->rps
.min_freq_softlimit
== 0)
3999 dev_priv
->rps
.min_freq_softlimit
= dev_priv
->rps
.min_freq
;
4001 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4004 static void valleyview_cleanup_gt_powersave(struct drm_device
*dev
)
4006 valleyview_cleanup_pctx(dev
);
4009 static void cherryview_enable_rps(struct drm_device
*dev
)
4011 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4012 struct intel_engine_cs
*ring
;
4013 u32 gtfifodbg
, val
, rc6_mode
= 0, pcbr
;
4016 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
4018 gtfifodbg
= I915_READ(GTFIFODBG
);
4020 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4022 I915_WRITE(GTFIFODBG
, gtfifodbg
);
4025 cherryview_check_pctx(dev_priv
);
4027 /* 1a & 1b: Get forcewake during program sequence. Although the driver
4028 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4029 gen6_gt_force_wake_get(dev_priv
, FORCEWAKE_ALL
);
4031 /* 2a: Program RC6 thresholds.*/
4032 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 40 << 16);
4033 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000); /* 12500 * 1280ns */
4034 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25); /* 25 * 1280ns */
4036 for_each_ring(ring
, dev_priv
, i
)
4037 I915_WRITE(RING_MAX_IDLE(ring
->mmio_base
), 10);
4038 I915_WRITE(GEN6_RC_SLEEP
, 0);
4040 I915_WRITE(GEN6_RC6_THRESHOLD
, 50000); /* 50/125ms per EI */
4042 /* allows RC6 residency counter to work */
4043 I915_WRITE(VLV_COUNTER_CONTROL
,
4044 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH
|
4045 VLV_MEDIA_RC6_COUNT_EN
|
4046 VLV_RENDER_RC6_COUNT_EN
));
4048 /* For now we assume BIOS is allocating and populating the PCBR */
4049 pcbr
= I915_READ(VLV_PCBR
);
4051 DRM_DEBUG_DRIVER("PCBR offset : 0x%x\n", pcbr
);
4054 if ((intel_enable_rc6(dev
) & INTEL_RC6_ENABLE
) &&
4055 (pcbr
>> VLV_PCBR_ADDR_SHIFT
))
4056 rc6_mode
= GEN6_RC_CTL_EI_MODE(1);
4058 I915_WRITE(GEN6_RC_CONTROL
, rc6_mode
);
4060 /* 4 Program defaults and thresholds for RPS*/
4061 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 59400);
4062 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 245000);
4063 I915_WRITE(GEN6_RP_UP_EI
, 66000);
4064 I915_WRITE(GEN6_RP_DOWN_EI
, 350000);
4066 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
4068 /* WaDisablePwrmtrEvent:chv (pre-production hw) */
4069 I915_WRITE(0xA80C, I915_READ(0xA80C) & 0x00ffffff);
4070 I915_WRITE(0xA810, I915_READ(0xA810) & 0xffffff00);
4073 I915_WRITE(GEN6_RP_CONTROL
,
4074 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
4075 GEN6_RP_MEDIA_IS_GFX
| /* WaSetMaskForGfxBusyness:chv (pre-production hw ?) */
4077 GEN6_RP_UP_BUSY_AVG
|
4078 GEN6_RP_DOWN_IDLE_AVG
);
4080 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
4082 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val
& 0x10 ? "yes" : "no");
4083 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val
);
4085 dev_priv
->rps
.cur_freq
= (val
>> 8) & 0xff;
4086 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
4087 vlv_gpu_freq(dev_priv
, dev_priv
->rps
.cur_freq
),
4088 dev_priv
->rps
.cur_freq
);
4090 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
4091 vlv_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
),
4092 dev_priv
->rps
.efficient_freq
);
4094 valleyview_set_rps(dev_priv
->dev
, dev_priv
->rps
.efficient_freq
);
4096 gen6_gt_force_wake_put(dev_priv
, FORCEWAKE_ALL
);
4099 static void valleyview_enable_rps(struct drm_device
*dev
)
4101 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4102 struct intel_engine_cs
*ring
;
4103 u32 gtfifodbg
, val
, rc6_mode
= 0;
4106 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
4108 valleyview_check_pctx(dev_priv
);
4110 if ((gtfifodbg
= I915_READ(GTFIFODBG
))) {
4111 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4113 I915_WRITE(GTFIFODBG
, gtfifodbg
);
4116 /* If VLV, Forcewake all wells, else re-direct to regular path */
4117 gen6_gt_force_wake_get(dev_priv
, FORCEWAKE_ALL
);
4119 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 59400);
4120 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 245000);
4121 I915_WRITE(GEN6_RP_UP_EI
, 66000);
4122 I915_WRITE(GEN6_RP_DOWN_EI
, 350000);
4124 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
4125 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 0xf4240);
4127 I915_WRITE(GEN6_RP_CONTROL
,
4128 GEN6_RP_MEDIA_TURBO
|
4129 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
4130 GEN6_RP_MEDIA_IS_GFX
|
4132 GEN6_RP_UP_BUSY_AVG
|
4133 GEN6_RP_DOWN_IDLE_CONT
);
4135 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 0x00280000);
4136 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000);
4137 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25);
4139 for_each_ring(ring
, dev_priv
, i
)
4140 I915_WRITE(RING_MAX_IDLE(ring
->mmio_base
), 10);
4142 I915_WRITE(GEN6_RC6_THRESHOLD
, 0x557);
4144 /* allows RC6 residency counter to work */
4145 I915_WRITE(VLV_COUNTER_CONTROL
,
4146 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN
|
4147 VLV_RENDER_RC0_COUNT_EN
|
4148 VLV_MEDIA_RC6_COUNT_EN
|
4149 VLV_RENDER_RC6_COUNT_EN
));
4151 if (intel_enable_rc6(dev
) & INTEL_RC6_ENABLE
)
4152 rc6_mode
= GEN7_RC_CTL_TO_MODE
| VLV_RC_CTL_CTX_RST_PARALLEL
;
4154 intel_print_rc6_info(dev
, rc6_mode
);
4156 I915_WRITE(GEN6_RC_CONTROL
, rc6_mode
);
4158 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
4160 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val
& 0x10 ? "yes" : "no");
4161 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val
);
4163 dev_priv
->rps
.cur_freq
= (val
>> 8) & 0xff;
4164 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
4165 vlv_gpu_freq(dev_priv
, dev_priv
->rps
.cur_freq
),
4166 dev_priv
->rps
.cur_freq
);
4168 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
4169 vlv_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
),
4170 dev_priv
->rps
.efficient_freq
);
4172 valleyview_set_rps(dev_priv
->dev
, dev_priv
->rps
.efficient_freq
);
4174 gen6_enable_rps_interrupts(dev
);
4176 gen6_gt_force_wake_put(dev_priv
, FORCEWAKE_ALL
);
4179 void ironlake_teardown_rc6(struct drm_device
*dev
)
4181 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4183 if (dev_priv
->ips
.renderctx
) {
4184 i915_gem_object_ggtt_unpin(dev_priv
->ips
.renderctx
);
4185 drm_gem_object_unreference(&dev_priv
->ips
.renderctx
->base
);
4186 dev_priv
->ips
.renderctx
= NULL
;
4189 if (dev_priv
->ips
.pwrctx
) {
4190 i915_gem_object_ggtt_unpin(dev_priv
->ips
.pwrctx
);
4191 drm_gem_object_unreference(&dev_priv
->ips
.pwrctx
->base
);
4192 dev_priv
->ips
.pwrctx
= NULL
;
4196 static void ironlake_disable_rc6(struct drm_device
*dev
)
4198 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4200 if (I915_READ(PWRCTXA
)) {
4201 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
4202 I915_WRITE(RSTDBYCTL
, I915_READ(RSTDBYCTL
) | RCX_SW_EXIT
);
4203 wait_for(((I915_READ(RSTDBYCTL
) & RSX_STATUS_MASK
) == RSX_STATUS_ON
),
4206 I915_WRITE(PWRCTXA
, 0);
4207 POSTING_READ(PWRCTXA
);
4209 I915_WRITE(RSTDBYCTL
, I915_READ(RSTDBYCTL
) & ~RCX_SW_EXIT
);
4210 POSTING_READ(RSTDBYCTL
);
4214 static int ironlake_setup_rc6(struct drm_device
*dev
)
4216 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4218 if (dev_priv
->ips
.renderctx
== NULL
)
4219 dev_priv
->ips
.renderctx
= intel_alloc_context_page(dev
);
4220 if (!dev_priv
->ips
.renderctx
)
4223 if (dev_priv
->ips
.pwrctx
== NULL
)
4224 dev_priv
->ips
.pwrctx
= intel_alloc_context_page(dev
);
4225 if (!dev_priv
->ips
.pwrctx
) {
4226 ironlake_teardown_rc6(dev
);
4233 static void ironlake_enable_rc6(struct drm_device
*dev
)
4235 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4236 struct intel_engine_cs
*ring
= &dev_priv
->ring
[RCS
];
4237 bool was_interruptible
;
4240 /* rc6 disabled by default due to repeated reports of hanging during
4243 if (!intel_enable_rc6(dev
))
4246 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
4248 ret
= ironlake_setup_rc6(dev
);
4252 was_interruptible
= dev_priv
->mm
.interruptible
;
4253 dev_priv
->mm
.interruptible
= false;
4256 * GPU can automatically power down the render unit if given a page
4259 ret
= intel_ring_begin(ring
, 6);
4261 ironlake_teardown_rc6(dev
);
4262 dev_priv
->mm
.interruptible
= was_interruptible
;
4266 intel_ring_emit(ring
, MI_SUSPEND_FLUSH
| MI_SUSPEND_FLUSH_EN
);
4267 intel_ring_emit(ring
, MI_SET_CONTEXT
);
4268 intel_ring_emit(ring
, i915_gem_obj_ggtt_offset(dev_priv
->ips
.renderctx
) |
4270 MI_SAVE_EXT_STATE_EN
|
4271 MI_RESTORE_EXT_STATE_EN
|
4272 MI_RESTORE_INHIBIT
);
4273 intel_ring_emit(ring
, MI_SUSPEND_FLUSH
);
4274 intel_ring_emit(ring
, MI_NOOP
);
4275 intel_ring_emit(ring
, MI_FLUSH
);
4276 intel_ring_advance(ring
);
4279 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
4280 * does an implicit flush, combined with MI_FLUSH above, it should be
4281 * safe to assume that renderctx is valid
4283 ret
= intel_ring_idle(ring
);
4284 dev_priv
->mm
.interruptible
= was_interruptible
;
4286 DRM_ERROR("failed to enable ironlake power savings\n");
4287 ironlake_teardown_rc6(dev
);
4291 I915_WRITE(PWRCTXA
, i915_gem_obj_ggtt_offset(dev_priv
->ips
.pwrctx
) | PWRCTX_EN
);
4292 I915_WRITE(RSTDBYCTL
, I915_READ(RSTDBYCTL
) & ~RCX_SW_EXIT
);
4294 intel_print_rc6_info(dev
, GEN6_RC_CTL_RC6_ENABLE
);
4297 static unsigned long intel_pxfreq(u32 vidfreq
)
4300 int div
= (vidfreq
& 0x3f0000) >> 16;
4301 int post
= (vidfreq
& 0x3000) >> 12;
4302 int pre
= (vidfreq
& 0x7);
4307 freq
= ((div
* 133333) / ((1<<post
) * pre
));
4312 static const struct cparams
{
4318 { 1, 1333, 301, 28664 },
4319 { 1, 1066, 294, 24460 },
4320 { 1, 800, 294, 25192 },
4321 { 0, 1333, 276, 27605 },
4322 { 0, 1066, 276, 27605 },
4323 { 0, 800, 231, 23784 },
4326 static unsigned long __i915_chipset_val(struct drm_i915_private
*dev_priv
)
4328 u64 total_count
, diff
, ret
;
4329 u32 count1
, count2
, count3
, m
= 0, c
= 0;
4330 unsigned long now
= jiffies_to_msecs(jiffies
), diff1
;
4333 assert_spin_locked(&mchdev_lock
);
4335 diff1
= now
- dev_priv
->ips
.last_time1
;
4337 /* Prevent division-by-zero if we are asking too fast.
4338 * Also, we don't get interesting results if we are polling
4339 * faster than once in 10ms, so just return the saved value
4343 return dev_priv
->ips
.chipset_power
;
4345 count1
= I915_READ(DMIEC
);
4346 count2
= I915_READ(DDREC
);
4347 count3
= I915_READ(CSIEC
);
4349 total_count
= count1
+ count2
+ count3
;
4351 /* FIXME: handle per-counter overflow */
4352 if (total_count
< dev_priv
->ips
.last_count1
) {
4353 diff
= ~0UL - dev_priv
->ips
.last_count1
;
4354 diff
+= total_count
;
4356 diff
= total_count
- dev_priv
->ips
.last_count1
;
4359 for (i
= 0; i
< ARRAY_SIZE(cparams
); i
++) {
4360 if (cparams
[i
].i
== dev_priv
->ips
.c_m
&&
4361 cparams
[i
].t
== dev_priv
->ips
.r_t
) {
4368 diff
= div_u64(diff
, diff1
);
4369 ret
= ((m
* diff
) + c
);
4370 ret
= div_u64(ret
, 10);
4372 dev_priv
->ips
.last_count1
= total_count
;
4373 dev_priv
->ips
.last_time1
= now
;
4375 dev_priv
->ips
.chipset_power
= ret
;
4380 unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
)
4382 struct drm_device
*dev
= dev_priv
->dev
;
4385 if (INTEL_INFO(dev
)->gen
!= 5)
4388 spin_lock_irq(&mchdev_lock
);
4390 val
= __i915_chipset_val(dev_priv
);
4392 spin_unlock_irq(&mchdev_lock
);
4397 unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
)
4399 unsigned long m
, x
, b
;
4402 tsfs
= I915_READ(TSFS
);
4404 m
= ((tsfs
& TSFS_SLOPE_MASK
) >> TSFS_SLOPE_SHIFT
);
4405 x
= I915_READ8(TR1
);
4407 b
= tsfs
& TSFS_INTR_MASK
;
4409 return ((m
* x
) / 127) - b
;
4412 static u16
pvid_to_extvid(struct drm_i915_private
*dev_priv
, u8 pxvid
)
4414 struct drm_device
*dev
= dev_priv
->dev
;
4415 static const struct v_table
{
4416 u16 vd
; /* in .1 mil */
4417 u16 vm
; /* in .1 mil */
4548 if (INTEL_INFO(dev
)->is_mobile
)
4549 return v_table
[pxvid
].vm
;
4551 return v_table
[pxvid
].vd
;
4554 static void __i915_update_gfx_val(struct drm_i915_private
*dev_priv
)
4556 struct timespec now
, diff1
;
4558 unsigned long diffms
;
4561 assert_spin_locked(&mchdev_lock
);
4563 getrawmonotonic(&now
);
4564 diff1
= timespec_sub(now
, dev_priv
->ips
.last_time2
);
4566 /* Don't divide by 0 */
4567 diffms
= diff1
.tv_sec
* 1000 + diff1
.tv_nsec
/ 1000000;
4571 count
= I915_READ(GFXEC
);
4573 if (count
< dev_priv
->ips
.last_count2
) {
4574 diff
= ~0UL - dev_priv
->ips
.last_count2
;
4577 diff
= count
- dev_priv
->ips
.last_count2
;
4580 dev_priv
->ips
.last_count2
= count
;
4581 dev_priv
->ips
.last_time2
= now
;
4583 /* More magic constants... */
4585 diff
= div_u64(diff
, diffms
* 10);
4586 dev_priv
->ips
.gfx_power
= diff
;
4589 void i915_update_gfx_val(struct drm_i915_private
*dev_priv
)
4591 struct drm_device
*dev
= dev_priv
->dev
;
4593 if (INTEL_INFO(dev
)->gen
!= 5)
4596 spin_lock_irq(&mchdev_lock
);
4598 __i915_update_gfx_val(dev_priv
);
4600 spin_unlock_irq(&mchdev_lock
);
4603 static unsigned long __i915_gfx_val(struct drm_i915_private
*dev_priv
)
4605 unsigned long t
, corr
, state1
, corr2
, state2
;
4608 assert_spin_locked(&mchdev_lock
);
4610 pxvid
= I915_READ(PXVFREQ_BASE
+ (dev_priv
->rps
.cur_freq
* 4));
4611 pxvid
= (pxvid
>> 24) & 0x7f;
4612 ext_v
= pvid_to_extvid(dev_priv
, pxvid
);
4616 t
= i915_mch_val(dev_priv
);
4618 /* Revel in the empirically derived constants */
4620 /* Correction factor in 1/100000 units */
4622 corr
= ((t
* 2349) + 135940);
4624 corr
= ((t
* 964) + 29317);
4626 corr
= ((t
* 301) + 1004);
4628 corr
= corr
* ((150142 * state1
) / 10000 - 78642);
4630 corr2
= (corr
* dev_priv
->ips
.corr
);
4632 state2
= (corr2
* state1
) / 10000;
4633 state2
/= 100; /* convert to mW */
4635 __i915_update_gfx_val(dev_priv
);
4637 return dev_priv
->ips
.gfx_power
+ state2
;
4640 unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
)
4642 struct drm_device
*dev
= dev_priv
->dev
;
4645 if (INTEL_INFO(dev
)->gen
!= 5)
4648 spin_lock_irq(&mchdev_lock
);
4650 val
= __i915_gfx_val(dev_priv
);
4652 spin_unlock_irq(&mchdev_lock
);
4658 * i915_read_mch_val - return value for IPS use
4660 * Calculate and return a value for the IPS driver to use when deciding whether
4661 * we have thermal and power headroom to increase CPU or GPU power budget.
4663 unsigned long i915_read_mch_val(void)
4665 struct drm_i915_private
*dev_priv
;
4666 unsigned long chipset_val
, graphics_val
, ret
= 0;
4668 spin_lock_irq(&mchdev_lock
);
4671 dev_priv
= i915_mch_dev
;
4673 chipset_val
= __i915_chipset_val(dev_priv
);
4674 graphics_val
= __i915_gfx_val(dev_priv
);
4676 ret
= chipset_val
+ graphics_val
;
4679 spin_unlock_irq(&mchdev_lock
);
4683 EXPORT_SYMBOL_GPL(i915_read_mch_val
);
4686 * i915_gpu_raise - raise GPU frequency limit
4688 * Raise the limit; IPS indicates we have thermal headroom.
4690 bool i915_gpu_raise(void)
4692 struct drm_i915_private
*dev_priv
;
4695 spin_lock_irq(&mchdev_lock
);
4696 if (!i915_mch_dev
) {
4700 dev_priv
= i915_mch_dev
;
4702 if (dev_priv
->ips
.max_delay
> dev_priv
->ips
.fmax
)
4703 dev_priv
->ips
.max_delay
--;
4706 spin_unlock_irq(&mchdev_lock
);
4710 EXPORT_SYMBOL_GPL(i915_gpu_raise
);
4713 * i915_gpu_lower - lower GPU frequency limit
4715 * IPS indicates we're close to a thermal limit, so throttle back the GPU
4716 * frequency maximum.
4718 bool i915_gpu_lower(void)
4720 struct drm_i915_private
*dev_priv
;
4723 spin_lock_irq(&mchdev_lock
);
4724 if (!i915_mch_dev
) {
4728 dev_priv
= i915_mch_dev
;
4730 if (dev_priv
->ips
.max_delay
< dev_priv
->ips
.min_delay
)
4731 dev_priv
->ips
.max_delay
++;
4734 spin_unlock_irq(&mchdev_lock
);
4738 EXPORT_SYMBOL_GPL(i915_gpu_lower
);
4741 * i915_gpu_busy - indicate GPU business to IPS
4743 * Tell the IPS driver whether or not the GPU is busy.
4745 bool i915_gpu_busy(void)
4747 struct drm_i915_private
*dev_priv
;
4748 struct intel_engine_cs
*ring
;
4752 spin_lock_irq(&mchdev_lock
);
4755 dev_priv
= i915_mch_dev
;
4757 for_each_ring(ring
, dev_priv
, i
)
4758 ret
|= !list_empty(&ring
->request_list
);
4761 spin_unlock_irq(&mchdev_lock
);
4765 EXPORT_SYMBOL_GPL(i915_gpu_busy
);
4768 * i915_gpu_turbo_disable - disable graphics turbo
4770 * Disable graphics turbo by resetting the max frequency and setting the
4771 * current frequency to the default.
4773 bool i915_gpu_turbo_disable(void)
4775 struct drm_i915_private
*dev_priv
;
4778 spin_lock_irq(&mchdev_lock
);
4779 if (!i915_mch_dev
) {
4783 dev_priv
= i915_mch_dev
;
4785 dev_priv
->ips
.max_delay
= dev_priv
->ips
.fstart
;
4787 if (!ironlake_set_drps(dev_priv
->dev
, dev_priv
->ips
.fstart
))
4791 spin_unlock_irq(&mchdev_lock
);
4795 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable
);
4798 * Tells the intel_ips driver that the i915 driver is now loaded, if
4799 * IPS got loaded first.
4801 * This awkward dance is so that neither module has to depend on the
4802 * other in order for IPS to do the appropriate communication of
4803 * GPU turbo limits to i915.
4806 ips_ping_for_i915_load(void)
4810 link
= symbol_get(ips_link_to_i915_driver
);
4813 symbol_put(ips_link_to_i915_driver
);
4817 void intel_gpu_ips_init(struct drm_i915_private
*dev_priv
)
4819 /* We only register the i915 ips part with intel-ips once everything is
4820 * set up, to avoid intel-ips sneaking in and reading bogus values. */
4821 spin_lock_irq(&mchdev_lock
);
4822 i915_mch_dev
= dev_priv
;
4823 spin_unlock_irq(&mchdev_lock
);
4825 ips_ping_for_i915_load();
4828 void intel_gpu_ips_teardown(void)
4830 spin_lock_irq(&mchdev_lock
);
4831 i915_mch_dev
= NULL
;
4832 spin_unlock_irq(&mchdev_lock
);
4835 static void intel_init_emon(struct drm_device
*dev
)
4837 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4842 /* Disable to program */
4846 /* Program energy weights for various events */
4847 I915_WRITE(SDEW
, 0x15040d00);
4848 I915_WRITE(CSIEW0
, 0x007f0000);
4849 I915_WRITE(CSIEW1
, 0x1e220004);
4850 I915_WRITE(CSIEW2
, 0x04000004);
4852 for (i
= 0; i
< 5; i
++)
4853 I915_WRITE(PEW
+ (i
* 4), 0);
4854 for (i
= 0; i
< 3; i
++)
4855 I915_WRITE(DEW
+ (i
* 4), 0);
4857 /* Program P-state weights to account for frequency power adjustment */
4858 for (i
= 0; i
< 16; i
++) {
4859 u32 pxvidfreq
= I915_READ(PXVFREQ_BASE
+ (i
* 4));
4860 unsigned long freq
= intel_pxfreq(pxvidfreq
);
4861 unsigned long vid
= (pxvidfreq
& PXVFREQ_PX_MASK
) >>
4866 val
*= (freq
/ 1000);
4868 val
/= (127*127*900);
4870 DRM_ERROR("bad pxval: %ld\n", val
);
4873 /* Render standby states get 0 weight */
4877 for (i
= 0; i
< 4; i
++) {
4878 u32 val
= (pxw
[i
*4] << 24) | (pxw
[(i
*4)+1] << 16) |
4879 (pxw
[(i
*4)+2] << 8) | (pxw
[(i
*4)+3]);
4880 I915_WRITE(PXW
+ (i
* 4), val
);
4883 /* Adjust magic regs to magic values (more experimental results) */
4884 I915_WRITE(OGW0
, 0);
4885 I915_WRITE(OGW1
, 0);
4886 I915_WRITE(EG0
, 0x00007f00);
4887 I915_WRITE(EG1
, 0x0000000e);
4888 I915_WRITE(EG2
, 0x000e0000);
4889 I915_WRITE(EG3
, 0x68000300);
4890 I915_WRITE(EG4
, 0x42000000);
4891 I915_WRITE(EG5
, 0x00140031);
4895 for (i
= 0; i
< 8; i
++)
4896 I915_WRITE(PXWL
+ (i
* 4), 0);
4898 /* Enable PMON + select events */
4899 I915_WRITE(ECR
, 0x80000019);
4901 lcfuse
= I915_READ(LCFUSE02
);
4903 dev_priv
->ips
.corr
= (lcfuse
& LCFUSE_HIV_MASK
);
4906 void intel_init_gt_powersave(struct drm_device
*dev
)
4908 i915
.enable_rc6
= sanitize_rc6_option(dev
, i915
.enable_rc6
);
4910 if (IS_CHERRYVIEW(dev
))
4911 cherryview_init_gt_powersave(dev
);
4912 else if (IS_VALLEYVIEW(dev
))
4913 valleyview_init_gt_powersave(dev
);
4916 void intel_cleanup_gt_powersave(struct drm_device
*dev
)
4918 if (IS_CHERRYVIEW(dev
))
4920 else if (IS_VALLEYVIEW(dev
))
4921 valleyview_cleanup_gt_powersave(dev
);
4925 * intel_suspend_gt_powersave - suspend PM work and helper threads
4928 * We don't want to disable RC6 or other features here, we just want
4929 * to make sure any work we've queued has finished and won't bother
4930 * us while we're suspended.
4932 void intel_suspend_gt_powersave(struct drm_device
*dev
)
4934 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4936 /* Interrupts should be disabled already to avoid re-arming. */
4937 WARN_ON(dev
->irq_enabled
&& !dev_priv
->pm
.irqs_disabled
);
4939 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
4941 cancel_work_sync(&dev_priv
->rps
.work
);
4944 void intel_disable_gt_powersave(struct drm_device
*dev
)
4946 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4948 /* Interrupts should be disabled already to avoid re-arming. */
4949 WARN_ON(dev
->irq_enabled
&& !dev_priv
->pm
.irqs_disabled
);
4951 if (IS_IRONLAKE_M(dev
)) {
4952 ironlake_disable_drps(dev
);
4953 ironlake_disable_rc6(dev
);
4954 } else if (INTEL_INFO(dev
)->gen
>= 6) {
4955 intel_suspend_gt_powersave(dev
);
4957 mutex_lock(&dev_priv
->rps
.hw_lock
);
4958 if (IS_CHERRYVIEW(dev
))
4959 cherryview_disable_rps(dev
);
4960 else if (IS_VALLEYVIEW(dev
))
4961 valleyview_disable_rps(dev
);
4963 gen6_disable_rps(dev
);
4964 dev_priv
->rps
.enabled
= false;
4965 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4969 static void intel_gen6_powersave_work(struct work_struct
*work
)
4971 struct drm_i915_private
*dev_priv
=
4972 container_of(work
, struct drm_i915_private
,
4973 rps
.delayed_resume_work
.work
);
4974 struct drm_device
*dev
= dev_priv
->dev
;
4976 mutex_lock(&dev_priv
->rps
.hw_lock
);
4978 if (IS_CHERRYVIEW(dev
)) {
4979 cherryview_enable_rps(dev
);
4980 } else if (IS_VALLEYVIEW(dev
)) {
4981 valleyview_enable_rps(dev
);
4982 } else if (IS_BROADWELL(dev
)) {
4983 gen8_enable_rps(dev
);
4984 __gen6_update_ring_freq(dev
);
4986 gen6_enable_rps(dev
);
4987 __gen6_update_ring_freq(dev
);
4989 dev_priv
->rps
.enabled
= true;
4990 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4992 intel_runtime_pm_put(dev_priv
);
4995 void intel_enable_gt_powersave(struct drm_device
*dev
)
4997 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4999 if (IS_IRONLAKE_M(dev
)) {
5000 mutex_lock(&dev
->struct_mutex
);
5001 ironlake_enable_drps(dev
);
5002 ironlake_enable_rc6(dev
);
5003 intel_init_emon(dev
);
5004 mutex_unlock(&dev
->struct_mutex
);
5005 } else if (INTEL_INFO(dev
)->gen
>= 6) {
5007 * PCU communication is slow and this doesn't need to be
5008 * done at any specific time, so do this out of our fast path
5009 * to make resume and init faster.
5011 * We depend on the HW RC6 power context save/restore
5012 * mechanism when entering D3 through runtime PM suspend. So
5013 * disable RPM until RPS/RC6 is properly setup. We can only
5014 * get here via the driver load/system resume/runtime resume
5015 * paths, so the _noresume version is enough (and in case of
5016 * runtime resume it's necessary).
5018 if (schedule_delayed_work(&dev_priv
->rps
.delayed_resume_work
,
5019 round_jiffies_up_relative(HZ
)))
5020 intel_runtime_pm_get_noresume(dev_priv
);
5024 void intel_reset_gt_powersave(struct drm_device
*dev
)
5026 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5028 dev_priv
->rps
.enabled
= false;
5029 intel_enable_gt_powersave(dev
);
5032 static void ibx_init_clock_gating(struct drm_device
*dev
)
5034 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5037 * On Ibex Peak and Cougar Point, we need to disable clock
5038 * gating for the panel power sequencer or it will fail to
5039 * start up when no ports are active.
5041 I915_WRITE(SOUTH_DSPCLK_GATE_D
, PCH_DPLSUNIT_CLOCK_GATE_DISABLE
);
5044 static void g4x_disable_trickle_feed(struct drm_device
*dev
)
5046 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5049 for_each_pipe(pipe
) {
5050 I915_WRITE(DSPCNTR(pipe
),
5051 I915_READ(DSPCNTR(pipe
)) |
5052 DISPPLANE_TRICKLE_FEED_DISABLE
);
5053 intel_flush_primary_plane(dev_priv
, pipe
);
5057 static void ilk_init_lp_watermarks(struct drm_device
*dev
)
5059 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5061 I915_WRITE(WM3_LP_ILK
, I915_READ(WM3_LP_ILK
) & ~WM1_LP_SR_EN
);
5062 I915_WRITE(WM2_LP_ILK
, I915_READ(WM2_LP_ILK
) & ~WM1_LP_SR_EN
);
5063 I915_WRITE(WM1_LP_ILK
, I915_READ(WM1_LP_ILK
) & ~WM1_LP_SR_EN
);
5066 * Don't touch WM1S_LP_EN here.
5067 * Doing so could cause underruns.
5071 static void ironlake_init_clock_gating(struct drm_device
*dev
)
5073 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5074 uint32_t dspclk_gate
= ILK_VRHUNIT_CLOCK_GATE_DISABLE
;
5078 * WaFbcDisableDpfcClockGating:ilk
5080 dspclk_gate
|= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE
|
5081 ILK_DPFCUNIT_CLOCK_GATE_DISABLE
|
5082 ILK_DPFDUNIT_CLOCK_GATE_ENABLE
;
5084 I915_WRITE(PCH_3DCGDIS0
,
5085 MARIUNIT_CLOCK_GATE_DISABLE
|
5086 SVSMUNIT_CLOCK_GATE_DISABLE
);
5087 I915_WRITE(PCH_3DCGDIS1
,
5088 VFMUNIT_CLOCK_GATE_DISABLE
);
5091 * According to the spec the following bits should be set in
5092 * order to enable memory self-refresh
5093 * The bit 22/21 of 0x42004
5094 * The bit 5 of 0x42020
5095 * The bit 15 of 0x45000
5097 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
5098 (I915_READ(ILK_DISPLAY_CHICKEN2
) |
5099 ILK_DPARB_GATE
| ILK_VSDPFD_FULL
));
5100 dspclk_gate
|= ILK_DPARBUNIT_CLOCK_GATE_ENABLE
;
5101 I915_WRITE(DISP_ARB_CTL
,
5102 (I915_READ(DISP_ARB_CTL
) |
5105 ilk_init_lp_watermarks(dev
);
5108 * Based on the document from hardware guys the following bits
5109 * should be set unconditionally in order to enable FBC.
5110 * The bit 22 of 0x42000
5111 * The bit 22 of 0x42004
5112 * The bit 7,8,9 of 0x42020.
5114 if (IS_IRONLAKE_M(dev
)) {
5115 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
5116 I915_WRITE(ILK_DISPLAY_CHICKEN1
,
5117 I915_READ(ILK_DISPLAY_CHICKEN1
) |
5119 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
5120 I915_READ(ILK_DISPLAY_CHICKEN2
) |
5124 I915_WRITE(ILK_DSPCLK_GATE_D
, dspclk_gate
);
5126 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
5127 I915_READ(ILK_DISPLAY_CHICKEN2
) |
5128 ILK_ELPIN_409_SELECT
);
5129 I915_WRITE(_3D_CHICKEN2
,
5130 _3D_CHICKEN2_WM_READ_PIPELINED
<< 16 |
5131 _3D_CHICKEN2_WM_READ_PIPELINED
);
5133 /* WaDisableRenderCachePipelinedFlush:ilk */
5134 I915_WRITE(CACHE_MODE_0
,
5135 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE
));
5137 /* WaDisable_RenderCache_OperationalFlush:ilk */
5138 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
5140 g4x_disable_trickle_feed(dev
);
5142 ibx_init_clock_gating(dev
);
5145 static void cpt_init_clock_gating(struct drm_device
*dev
)
5147 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5152 * On Ibex Peak and Cougar Point, we need to disable clock
5153 * gating for the panel power sequencer or it will fail to
5154 * start up when no ports are active.
5156 I915_WRITE(SOUTH_DSPCLK_GATE_D
, PCH_DPLSUNIT_CLOCK_GATE_DISABLE
|
5157 PCH_DPLUNIT_CLOCK_GATE_DISABLE
|
5158 PCH_CPUNIT_CLOCK_GATE_DISABLE
);
5159 I915_WRITE(SOUTH_CHICKEN2
, I915_READ(SOUTH_CHICKEN2
) |
5160 DPLS_EDP_PPS_FIX_DIS
);
5161 /* The below fixes the weird display corruption, a few pixels shifted
5162 * downward, on (only) LVDS of some HP laptops with IVY.
5164 for_each_pipe(pipe
) {
5165 val
= I915_READ(TRANS_CHICKEN2(pipe
));
5166 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
5167 val
&= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED
;
5168 if (dev_priv
->vbt
.fdi_rx_polarity_inverted
)
5169 val
|= TRANS_CHICKEN2_FDI_POLARITY_REVERSED
;
5170 val
&= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK
;
5171 val
&= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER
;
5172 val
&= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH
;
5173 I915_WRITE(TRANS_CHICKEN2(pipe
), val
);
5175 /* WADP0ClockGatingDisable */
5176 for_each_pipe(pipe
) {
5177 I915_WRITE(TRANS_CHICKEN1(pipe
),
5178 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE
);
5182 static void gen6_check_mch_setup(struct drm_device
*dev
)
5184 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5187 tmp
= I915_READ(MCH_SSKPD
);
5188 if ((tmp
& MCH_SSKPD_WM0_MASK
) != MCH_SSKPD_WM0_VAL
) {
5189 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp
);
5190 DRM_INFO("This can cause pipe underruns and display issues.\n");
5191 DRM_INFO("Please upgrade your BIOS to fix this.\n");
5195 static void gen6_init_clock_gating(struct drm_device
*dev
)
5197 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5198 uint32_t dspclk_gate
= ILK_VRHUNIT_CLOCK_GATE_DISABLE
;
5200 I915_WRITE(ILK_DSPCLK_GATE_D
, dspclk_gate
);
5202 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
5203 I915_READ(ILK_DISPLAY_CHICKEN2
) |
5204 ILK_ELPIN_409_SELECT
);
5206 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
5207 I915_WRITE(_3D_CHICKEN
,
5208 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB
));
5210 /* WaSetupGtModeTdRowDispatch:snb */
5211 if (IS_SNB_GT1(dev
))
5212 I915_WRITE(GEN6_GT_MODE
,
5213 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE
));
5215 /* WaDisable_RenderCache_OperationalFlush:snb */
5216 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
5219 * BSpec recoomends 8x4 when MSAA is used,
5220 * however in practice 16x4 seems fastest.
5222 * Note that PS/WM thread counts depend on the WIZ hashing
5223 * disable bit, which we don't touch here, but it's good
5224 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5226 I915_WRITE(GEN6_GT_MODE
,
5227 GEN6_WIZ_HASHING_MASK
| GEN6_WIZ_HASHING_16x4
);
5229 ilk_init_lp_watermarks(dev
);
5231 I915_WRITE(CACHE_MODE_0
,
5232 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB
));
5234 I915_WRITE(GEN6_UCGCTL1
,
5235 I915_READ(GEN6_UCGCTL1
) |
5236 GEN6_BLBUNIT_CLOCK_GATE_DISABLE
|
5237 GEN6_CSUNIT_CLOCK_GATE_DISABLE
);
5239 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5240 * gating disable must be set. Failure to set it results in
5241 * flickering pixels due to Z write ordering failures after
5242 * some amount of runtime in the Mesa "fire" demo, and Unigine
5243 * Sanctuary and Tropics, and apparently anything else with
5244 * alpha test or pixel discard.
5246 * According to the spec, bit 11 (RCCUNIT) must also be set,
5247 * but we didn't debug actual testcases to find it out.
5249 * WaDisableRCCUnitClockGating:snb
5250 * WaDisableRCPBUnitClockGating:snb
5252 I915_WRITE(GEN6_UCGCTL2
,
5253 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE
|
5254 GEN6_RCCUNIT_CLOCK_GATE_DISABLE
);
5256 /* WaStripsFansDisableFastClipPerformanceFix:snb */
5257 I915_WRITE(_3D_CHICKEN3
,
5258 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL
));
5262 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
5263 * 3DSTATE_SF number of SF output attributes is more than 16."
5265 I915_WRITE(_3D_CHICKEN3
,
5266 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH
));
5269 * According to the spec the following bits should be
5270 * set in order to enable memory self-refresh and fbc:
5271 * The bit21 and bit22 of 0x42000
5272 * The bit21 and bit22 of 0x42004
5273 * The bit5 and bit7 of 0x42020
5274 * The bit14 of 0x70180
5275 * The bit14 of 0x71180
5277 * WaFbcAsynchFlipDisableFbcQueue:snb
5279 I915_WRITE(ILK_DISPLAY_CHICKEN1
,
5280 I915_READ(ILK_DISPLAY_CHICKEN1
) |
5281 ILK_FBCQ_DIS
| ILK_PABSTRETCH_DIS
);
5282 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
5283 I915_READ(ILK_DISPLAY_CHICKEN2
) |
5284 ILK_DPARB_GATE
| ILK_VSDPFD_FULL
);
5285 I915_WRITE(ILK_DSPCLK_GATE_D
,
5286 I915_READ(ILK_DSPCLK_GATE_D
) |
5287 ILK_DPARBUNIT_CLOCK_GATE_ENABLE
|
5288 ILK_DPFDUNIT_CLOCK_GATE_ENABLE
);
5290 g4x_disable_trickle_feed(dev
);
5292 cpt_init_clock_gating(dev
);
5294 gen6_check_mch_setup(dev
);
5297 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private
*dev_priv
)
5299 uint32_t reg
= I915_READ(GEN7_FF_THREAD_MODE
);
5302 * WaVSThreadDispatchOverride:ivb,vlv
5304 * This actually overrides the dispatch
5305 * mode for all thread types.
5307 reg
&= ~GEN7_FF_SCHED_MASK
;
5308 reg
|= GEN7_FF_TS_SCHED_HW
;
5309 reg
|= GEN7_FF_VS_SCHED_HW
;
5310 reg
|= GEN7_FF_DS_SCHED_HW
;
5312 I915_WRITE(GEN7_FF_THREAD_MODE
, reg
);
5315 static void lpt_init_clock_gating(struct drm_device
*dev
)
5317 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5320 * TODO: this bit should only be enabled when really needed, then
5321 * disabled when not needed anymore in order to save power.
5323 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
)
5324 I915_WRITE(SOUTH_DSPCLK_GATE_D
,
5325 I915_READ(SOUTH_DSPCLK_GATE_D
) |
5326 PCH_LP_PARTITION_LEVEL_DISABLE
);
5328 /* WADPOClockGatingDisable:hsw */
5329 I915_WRITE(_TRANSA_CHICKEN1
,
5330 I915_READ(_TRANSA_CHICKEN1
) |
5331 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE
);
5334 static void lpt_suspend_hw(struct drm_device
*dev
)
5336 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5338 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
5339 uint32_t val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
5341 val
&= ~PCH_LP_PARTITION_LEVEL_DISABLE
;
5342 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
5346 static void gen8_init_clock_gating(struct drm_device
*dev
)
5348 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5351 I915_WRITE(WM3_LP_ILK
, 0);
5352 I915_WRITE(WM2_LP_ILK
, 0);
5353 I915_WRITE(WM1_LP_ILK
, 0);
5355 /* FIXME(BDW): Check all the w/a, some might only apply to
5356 * pre-production hw. */
5358 /* WaDisablePartialInstShootdown:bdw */
5359 I915_WRITE(GEN8_ROW_CHICKEN
,
5360 _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE
));
5362 /* WaDisableThreadStallDopClockGating:bdw */
5363 /* FIXME: Unclear whether we really need this on production bdw. */
5364 I915_WRITE(GEN8_ROW_CHICKEN
,
5365 _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE
));
5368 * This GEN8_CENTROID_PIXEL_OPT_DIS W/A is only needed for
5369 * pre-production hardware
5371 I915_WRITE(HALF_SLICE_CHICKEN3
,
5372 _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS
));
5373 I915_WRITE(HALF_SLICE_CHICKEN3
,
5374 _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS
));
5375 I915_WRITE(GAMTARBMODE
, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE
));
5377 I915_WRITE(_3D_CHICKEN3
,
5378 _MASKED_BIT_ENABLE(_3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2)));
5380 I915_WRITE(COMMON_SLICE_CHICKEN2
,
5381 _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE
));
5383 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1
,
5384 _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE
));
5386 /* WaDisableDopClockGating:bdw May not be needed for production */
5387 I915_WRITE(GEN7_ROW_CHICKEN2
,
5388 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
5390 /* WaSwitchSolVfFArbitrationPriority:bdw */
5391 I915_WRITE(GAM_ECOCHK
, I915_READ(GAM_ECOCHK
) | HSW_ECOCHK_ARB_PRIO_SOL
);
5393 /* WaPsrDPAMaskVBlankInSRD:bdw */
5394 I915_WRITE(CHICKEN_PAR1_1
,
5395 I915_READ(CHICKEN_PAR1_1
) | DPA_MASK_VBLANK_SRD
);
5397 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
5398 for_each_pipe(pipe
) {
5399 I915_WRITE(CHICKEN_PIPESL_1(pipe
),
5400 I915_READ(CHICKEN_PIPESL_1(pipe
)) |
5401 BDW_DPRS_MASK_VBLANK_SRD
);
5404 /* Use Force Non-Coherent whenever executing a 3D context. This is a
5405 * workaround for for a possible hang in the unlikely event a TLB
5406 * invalidation occurs during a PSD flush.
5408 I915_WRITE(HDC_CHICKEN0
,
5409 I915_READ(HDC_CHICKEN0
) |
5410 _MASKED_BIT_ENABLE(HDC_FORCE_NON_COHERENT
));
5412 /* WaVSRefCountFullforceMissDisable:bdw */
5413 /* WaDSRefCountFullforceMissDisable:bdw */
5414 I915_WRITE(GEN7_FF_THREAD_MODE
,
5415 I915_READ(GEN7_FF_THREAD_MODE
) &
5416 ~(GEN8_FF_DS_REF_CNT_FFME
| GEN7_FF_VS_REF_CNT_FFME
));
5419 * BSpec recommends 8x4 when MSAA is used,
5420 * however in practice 16x4 seems fastest.
5422 * Note that PS/WM thread counts depend on the WIZ hashing
5423 * disable bit, which we don't touch here, but it's good
5424 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5426 I915_WRITE(GEN7_GT_MODE
,
5427 GEN6_WIZ_HASHING_MASK
| GEN6_WIZ_HASHING_16x4
);
5429 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL
,
5430 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE
));
5432 /* WaDisableSDEUnitClockGating:bdw */
5433 I915_WRITE(GEN8_UCGCTL6
, I915_READ(GEN8_UCGCTL6
) |
5434 GEN8_SDEUNIT_CLOCK_GATE_DISABLE
);
5436 /* Wa4x4STCOptimizationDisable:bdw */
5437 I915_WRITE(CACHE_MODE_1
,
5438 _MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE
));
5441 static void haswell_init_clock_gating(struct drm_device
*dev
)
5443 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5445 ilk_init_lp_watermarks(dev
);
5447 /* L3 caching of data atomics doesn't work -- disable it. */
5448 I915_WRITE(HSW_SCRATCH1
, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE
);
5449 I915_WRITE(HSW_ROW_CHICKEN3
,
5450 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE
));
5452 /* This is required by WaCatErrorRejectionIssue:hsw */
5453 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
5454 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
5455 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
5457 /* WaVSRefCountFullforceMissDisable:hsw */
5458 I915_WRITE(GEN7_FF_THREAD_MODE
,
5459 I915_READ(GEN7_FF_THREAD_MODE
) & ~GEN7_FF_VS_REF_CNT_FFME
);
5461 /* WaDisable_RenderCache_OperationalFlush:hsw */
5462 I915_WRITE(CACHE_MODE_0_GEN7
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
5464 /* enable HiZ Raw Stall Optimization */
5465 I915_WRITE(CACHE_MODE_0_GEN7
,
5466 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE
));
5468 /* WaDisable4x2SubspanOptimization:hsw */
5469 I915_WRITE(CACHE_MODE_1
,
5470 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
));
5473 * BSpec recommends 8x4 when MSAA is used,
5474 * however in practice 16x4 seems fastest.
5476 * Note that PS/WM thread counts depend on the WIZ hashing
5477 * disable bit, which we don't touch here, but it's good
5478 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5480 I915_WRITE(GEN7_GT_MODE
,
5481 GEN6_WIZ_HASHING_MASK
| GEN6_WIZ_HASHING_16x4
);
5483 /* WaSwitchSolVfFArbitrationPriority:hsw */
5484 I915_WRITE(GAM_ECOCHK
, I915_READ(GAM_ECOCHK
) | HSW_ECOCHK_ARB_PRIO_SOL
);
5486 /* WaRsPkgCStateDisplayPMReq:hsw */
5487 I915_WRITE(CHICKEN_PAR1_1
,
5488 I915_READ(CHICKEN_PAR1_1
) | FORCE_ARB_IDLE_PLANES
);
5490 lpt_init_clock_gating(dev
);
5493 static void ivybridge_init_clock_gating(struct drm_device
*dev
)
5495 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5498 ilk_init_lp_watermarks(dev
);
5500 I915_WRITE(ILK_DSPCLK_GATE_D
, ILK_VRHUNIT_CLOCK_GATE_DISABLE
);
5502 /* WaDisableEarlyCull:ivb */
5503 I915_WRITE(_3D_CHICKEN3
,
5504 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL
));
5506 /* WaDisableBackToBackFlipFix:ivb */
5507 I915_WRITE(IVB_CHICKEN3
,
5508 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE
|
5509 CHICKEN3_DGMG_DONE_FIX_DISABLE
);
5511 /* WaDisablePSDDualDispatchEnable:ivb */
5512 if (IS_IVB_GT1(dev
))
5513 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1
,
5514 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE
));
5516 /* WaDisable_RenderCache_OperationalFlush:ivb */
5517 I915_WRITE(CACHE_MODE_0_GEN7
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
5519 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
5520 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1
,
5521 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC
);
5523 /* WaApplyL3ControlAndL3ChickenMode:ivb */
5524 I915_WRITE(GEN7_L3CNTLREG1
,
5525 GEN7_WA_FOR_GEN7_L3_CONTROL
);
5526 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER
,
5527 GEN7_WA_L3_CHICKEN_MODE
);
5528 if (IS_IVB_GT1(dev
))
5529 I915_WRITE(GEN7_ROW_CHICKEN2
,
5530 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
5532 /* must write both registers */
5533 I915_WRITE(GEN7_ROW_CHICKEN2
,
5534 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
5535 I915_WRITE(GEN7_ROW_CHICKEN2_GT2
,
5536 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
5539 /* WaForceL3Serialization:ivb */
5540 I915_WRITE(GEN7_L3SQCREG4
, I915_READ(GEN7_L3SQCREG4
) &
5541 ~L3SQ_URB_READ_CAM_MATCH_DISABLE
);
5544 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5545 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
5547 I915_WRITE(GEN6_UCGCTL2
,
5548 GEN6_RCZUNIT_CLOCK_GATE_DISABLE
);
5550 /* This is required by WaCatErrorRejectionIssue:ivb */
5551 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
5552 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
5553 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
5555 g4x_disable_trickle_feed(dev
);
5557 gen7_setup_fixed_func_scheduler(dev_priv
);
5559 if (0) { /* causes HiZ corruption on ivb:gt1 */
5560 /* enable HiZ Raw Stall Optimization */
5561 I915_WRITE(CACHE_MODE_0_GEN7
,
5562 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE
));
5565 /* WaDisable4x2SubspanOptimization:ivb */
5566 I915_WRITE(CACHE_MODE_1
,
5567 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
));
5570 * BSpec recommends 8x4 when MSAA is used,
5571 * however in practice 16x4 seems fastest.
5573 * Note that PS/WM thread counts depend on the WIZ hashing
5574 * disable bit, which we don't touch here, but it's good
5575 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5577 I915_WRITE(GEN7_GT_MODE
,
5578 GEN6_WIZ_HASHING_MASK
| GEN6_WIZ_HASHING_16x4
);
5580 snpcr
= I915_READ(GEN6_MBCUNIT_SNPCR
);
5581 snpcr
&= ~GEN6_MBC_SNPCR_MASK
;
5582 snpcr
|= GEN6_MBC_SNPCR_MED
;
5583 I915_WRITE(GEN6_MBCUNIT_SNPCR
, snpcr
);
5585 if (!HAS_PCH_NOP(dev
))
5586 cpt_init_clock_gating(dev
);
5588 gen6_check_mch_setup(dev
);
5591 static void valleyview_init_clock_gating(struct drm_device
*dev
)
5593 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5596 mutex_lock(&dev_priv
->rps
.hw_lock
);
5597 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
5598 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5599 switch ((val
>> 6) & 3) {
5602 dev_priv
->mem_freq
= 800;
5605 dev_priv
->mem_freq
= 1066;
5608 dev_priv
->mem_freq
= 1333;
5611 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv
->mem_freq
);
5613 I915_WRITE(DSPCLK_GATE_D
, VRHUNIT_CLOCK_GATE_DISABLE
);
5615 /* WaDisableEarlyCull:vlv */
5616 I915_WRITE(_3D_CHICKEN3
,
5617 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL
));
5619 /* WaDisableBackToBackFlipFix:vlv */
5620 I915_WRITE(IVB_CHICKEN3
,
5621 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE
|
5622 CHICKEN3_DGMG_DONE_FIX_DISABLE
);
5624 /* WaPsdDispatchEnable:vlv */
5625 /* WaDisablePSDDualDispatchEnable:vlv */
5626 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1
,
5627 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP
|
5628 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE
));
5630 /* WaDisable_RenderCache_OperationalFlush:vlv */
5631 I915_WRITE(CACHE_MODE_0_GEN7
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
5633 /* WaForceL3Serialization:vlv */
5634 I915_WRITE(GEN7_L3SQCREG4
, I915_READ(GEN7_L3SQCREG4
) &
5635 ~L3SQ_URB_READ_CAM_MATCH_DISABLE
);
5637 /* WaDisableDopClockGating:vlv */
5638 I915_WRITE(GEN7_ROW_CHICKEN2
,
5639 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
5641 /* This is required by WaCatErrorRejectionIssue:vlv */
5642 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
5643 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
5644 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
5646 gen7_setup_fixed_func_scheduler(dev_priv
);
5649 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5650 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
5652 I915_WRITE(GEN6_UCGCTL2
,
5653 GEN6_RCZUNIT_CLOCK_GATE_DISABLE
);
5655 /* WaDisableL3Bank2xClockGate:vlv
5656 * Disabling L3 clock gating- MMIO 940c[25] = 1
5657 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
5658 I915_WRITE(GEN7_UCGCTL4
,
5659 I915_READ(GEN7_UCGCTL4
) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE
);
5661 I915_WRITE(MI_ARB_VLV
, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
);
5664 * BSpec says this must be set, even though
5665 * WaDisable4x2SubspanOptimization isn't listed for VLV.
5667 I915_WRITE(CACHE_MODE_1
,
5668 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
));
5671 * WaIncreaseL3CreditsForVLVB0:vlv
5672 * This is the hardware default actually.
5674 I915_WRITE(GEN7_L3SQCREG1
, VLV_B0_WA_L3SQCREG1_VALUE
);
5677 * WaDisableVLVClockGating_VBIIssue:vlv
5678 * Disable clock gating on th GCFG unit to prevent a delay
5679 * in the reporting of vblank events.
5681 I915_WRITE(VLV_GUNIT_CLOCK_GATE
, GCFG_DIS
);
5684 static void cherryview_init_clock_gating(struct drm_device
*dev
)
5686 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5688 I915_WRITE(DSPCLK_GATE_D
, VRHUNIT_CLOCK_GATE_DISABLE
);
5690 I915_WRITE(MI_ARB_VLV
, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
);
5692 /* WaDisablePartialInstShootdown:chv */
5693 I915_WRITE(GEN8_ROW_CHICKEN
,
5694 _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE
));
5696 /* WaDisableThreadStallDopClockGating:chv */
5697 I915_WRITE(GEN8_ROW_CHICKEN
,
5698 _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE
));
5700 /* WaVSRefCountFullforceMissDisable:chv */
5701 /* WaDSRefCountFullforceMissDisable:chv */
5702 I915_WRITE(GEN7_FF_THREAD_MODE
,
5703 I915_READ(GEN7_FF_THREAD_MODE
) &
5704 ~(GEN8_FF_DS_REF_CNT_FFME
| GEN7_FF_VS_REF_CNT_FFME
));
5706 /* WaDisableSemaphoreAndSyncFlipWait:chv */
5707 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL
,
5708 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE
));
5710 /* WaDisableCSUnitClockGating:chv */
5711 I915_WRITE(GEN6_UCGCTL1
, I915_READ(GEN6_UCGCTL1
) |
5712 GEN6_CSUNIT_CLOCK_GATE_DISABLE
);
5714 /* WaDisableSDEUnitClockGating:chv */
5715 I915_WRITE(GEN8_UCGCTL6
, I915_READ(GEN8_UCGCTL6
) |
5716 GEN8_SDEUNIT_CLOCK_GATE_DISABLE
);
5718 /* WaDisableSamplerPowerBypass:chv (pre-production hw) */
5719 I915_WRITE(HALF_SLICE_CHICKEN3
,
5720 _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS
));
5722 /* WaDisableGunitClockGating:chv (pre-production hw) */
5723 I915_WRITE(VLV_GUNIT_CLOCK_GATE
, I915_READ(VLV_GUNIT_CLOCK_GATE
) |
5726 /* WaDisableFfDopClockGating:chv (pre-production hw) */
5727 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL
,
5728 _MASKED_BIT_ENABLE(GEN8_FF_DOP_CLOCK_GATE_DISABLE
));
5730 /* WaDisableDopClockGating:chv (pre-production hw) */
5731 I915_WRITE(GEN7_ROW_CHICKEN2
,
5732 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
5733 I915_WRITE(GEN6_UCGCTL1
, I915_READ(GEN6_UCGCTL1
) |
5734 GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE
);
5737 static void g4x_init_clock_gating(struct drm_device
*dev
)
5739 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5740 uint32_t dspclk_gate
;
5742 I915_WRITE(RENCLK_GATE_D1
, 0);
5743 I915_WRITE(RENCLK_GATE_D2
, VF_UNIT_CLOCK_GATE_DISABLE
|
5744 GS_UNIT_CLOCK_GATE_DISABLE
|
5745 CL_UNIT_CLOCK_GATE_DISABLE
);
5746 I915_WRITE(RAMCLK_GATE_D
, 0);
5747 dspclk_gate
= VRHUNIT_CLOCK_GATE_DISABLE
|
5748 OVRUNIT_CLOCK_GATE_DISABLE
|
5749 OVCUNIT_CLOCK_GATE_DISABLE
;
5751 dspclk_gate
|= DSSUNIT_CLOCK_GATE_DISABLE
;
5752 I915_WRITE(DSPCLK_GATE_D
, dspclk_gate
);
5754 /* WaDisableRenderCachePipelinedFlush */
5755 I915_WRITE(CACHE_MODE_0
,
5756 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE
));
5758 /* WaDisable_RenderCache_OperationalFlush:g4x */
5759 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
5761 g4x_disable_trickle_feed(dev
);
5764 static void crestline_init_clock_gating(struct drm_device
*dev
)
5766 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5768 I915_WRITE(RENCLK_GATE_D1
, I965_RCC_CLOCK_GATE_DISABLE
);
5769 I915_WRITE(RENCLK_GATE_D2
, 0);
5770 I915_WRITE(DSPCLK_GATE_D
, 0);
5771 I915_WRITE(RAMCLK_GATE_D
, 0);
5772 I915_WRITE16(DEUC
, 0);
5773 I915_WRITE(MI_ARB_STATE
,
5774 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
));
5776 /* WaDisable_RenderCache_OperationalFlush:gen4 */
5777 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
5780 static void broadwater_init_clock_gating(struct drm_device
*dev
)
5782 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5784 I915_WRITE(RENCLK_GATE_D1
, I965_RCZ_CLOCK_GATE_DISABLE
|
5785 I965_RCC_CLOCK_GATE_DISABLE
|
5786 I965_RCPB_CLOCK_GATE_DISABLE
|
5787 I965_ISC_CLOCK_GATE_DISABLE
|
5788 I965_FBC_CLOCK_GATE_DISABLE
);
5789 I915_WRITE(RENCLK_GATE_D2
, 0);
5790 I915_WRITE(MI_ARB_STATE
,
5791 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
));
5793 /* WaDisable_RenderCache_OperationalFlush:gen4 */
5794 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
5797 static void gen3_init_clock_gating(struct drm_device
*dev
)
5799 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5800 u32 dstate
= I915_READ(D_STATE
);
5802 dstate
|= DSTATE_PLL_D3_OFF
| DSTATE_GFX_CLOCK_GATING
|
5803 DSTATE_DOT_CLOCK_GATING
;
5804 I915_WRITE(D_STATE
, dstate
);
5806 if (IS_PINEVIEW(dev
))
5807 I915_WRITE(ECOSKPD
, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY
));
5809 /* IIR "flip pending" means done if this bit is set */
5810 I915_WRITE(ECOSKPD
, _MASKED_BIT_DISABLE(ECO_FLIP_DONE
));
5812 /* interrupts should cause a wake up from C3 */
5813 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN
));
5815 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
5816 I915_WRITE(MI_ARB_STATE
, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE
));
5819 static void i85x_init_clock_gating(struct drm_device
*dev
)
5821 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5823 I915_WRITE(RENCLK_GATE_D1
, SV_CLOCK_GATE_DISABLE
);
5825 /* interrupts should cause a wake up from C3 */
5826 I915_WRITE(MI_STATE
, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN
) |
5827 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE
));
5830 static void i830_init_clock_gating(struct drm_device
*dev
)
5832 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5834 I915_WRITE(DSPCLK_GATE_D
, OVRUNIT_CLOCK_GATE_DISABLE
);
5837 void intel_init_clock_gating(struct drm_device
*dev
)
5839 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5841 dev_priv
->display
.init_clock_gating(dev
);
5844 void intel_suspend_hw(struct drm_device
*dev
)
5846 if (HAS_PCH_LPT(dev
))
5847 lpt_suspend_hw(dev
);
5850 #define for_each_power_well(i, power_well, domain_mask, power_domains) \
5852 i < (power_domains)->power_well_count && \
5853 ((power_well) = &(power_domains)->power_wells[i]); \
5855 if ((power_well)->domains & (domain_mask))
5857 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
5858 for (i = (power_domains)->power_well_count - 1; \
5859 i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
5861 if ((power_well)->domains & (domain_mask))
5864 * We should only use the power well if we explicitly asked the hardware to
5865 * enable it, so check if it's enabled and also check if we've requested it to
5868 static bool hsw_power_well_enabled(struct drm_i915_private
*dev_priv
,
5869 struct i915_power_well
*power_well
)
5871 return I915_READ(HSW_PWR_WELL_DRIVER
) ==
5872 (HSW_PWR_WELL_ENABLE_REQUEST
| HSW_PWR_WELL_STATE_ENABLED
);
5875 bool intel_display_power_enabled_unlocked(struct drm_i915_private
*dev_priv
,
5876 enum intel_display_power_domain domain
)
5878 struct i915_power_domains
*power_domains
;
5879 struct i915_power_well
*power_well
;
5883 if (dev_priv
->pm
.suspended
)
5886 power_domains
= &dev_priv
->power_domains
;
5890 for_each_power_well_rev(i
, power_well
, BIT(domain
), power_domains
) {
5891 if (power_well
->always_on
)
5894 if (!power_well
->hw_enabled
) {
5903 bool intel_display_power_enabled(struct drm_i915_private
*dev_priv
,
5904 enum intel_display_power_domain domain
)
5906 struct i915_power_domains
*power_domains
;
5909 power_domains
= &dev_priv
->power_domains
;
5911 mutex_lock(&power_domains
->lock
);
5912 ret
= intel_display_power_enabled_unlocked(dev_priv
, domain
);
5913 mutex_unlock(&power_domains
->lock
);
5919 * Starting with Haswell, we have a "Power Down Well" that can be turned off
5920 * when not needed anymore. We have 4 registers that can request the power well
5921 * to be enabled, and it will only be disabled if none of the registers is
5922 * requesting it to be enabled.
5924 static void hsw_power_well_post_enable(struct drm_i915_private
*dev_priv
)
5926 struct drm_device
*dev
= dev_priv
->dev
;
5927 unsigned long irqflags
;
5930 * After we re-enable the power well, if we touch VGA register 0x3d5
5931 * we'll get unclaimed register interrupts. This stops after we write
5932 * anything to the VGA MSR register. The vgacon module uses this
5933 * register all the time, so if we unbind our driver and, as a
5934 * consequence, bind vgacon, we'll get stuck in an infinite loop at
5935 * console_unlock(). So make here we touch the VGA MSR register, making
5936 * sure vgacon can keep working normally without triggering interrupts
5937 * and error messages.
5939 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
5940 outb(inb(VGA_MSR_READ
), VGA_MSR_WRITE
);
5941 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
5943 if (IS_BROADWELL(dev
)) {
5944 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
5945 I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_B
),
5946 dev_priv
->de_irq_mask
[PIPE_B
]);
5947 I915_WRITE(GEN8_DE_PIPE_IER(PIPE_B
),
5948 ~dev_priv
->de_irq_mask
[PIPE_B
] |
5950 I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_C
),
5951 dev_priv
->de_irq_mask
[PIPE_C
]);
5952 I915_WRITE(GEN8_DE_PIPE_IER(PIPE_C
),
5953 ~dev_priv
->de_irq_mask
[PIPE_C
] |
5955 POSTING_READ(GEN8_DE_PIPE_IER(PIPE_C
));
5956 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
5960 static void hsw_set_power_well(struct drm_i915_private
*dev_priv
,
5961 struct i915_power_well
*power_well
, bool enable
)
5963 bool is_enabled
, enable_requested
;
5966 tmp
= I915_READ(HSW_PWR_WELL_DRIVER
);
5967 is_enabled
= tmp
& HSW_PWR_WELL_STATE_ENABLED
;
5968 enable_requested
= tmp
& HSW_PWR_WELL_ENABLE_REQUEST
;
5971 if (!enable_requested
)
5972 I915_WRITE(HSW_PWR_WELL_DRIVER
,
5973 HSW_PWR_WELL_ENABLE_REQUEST
);
5976 DRM_DEBUG_KMS("Enabling power well\n");
5977 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER
) &
5978 HSW_PWR_WELL_STATE_ENABLED
), 20))
5979 DRM_ERROR("Timeout enabling power well\n");
5982 hsw_power_well_post_enable(dev_priv
);
5984 if (enable_requested
) {
5985 I915_WRITE(HSW_PWR_WELL_DRIVER
, 0);
5986 POSTING_READ(HSW_PWR_WELL_DRIVER
);
5987 DRM_DEBUG_KMS("Requesting to disable the power well\n");
5992 static void hsw_power_well_sync_hw(struct drm_i915_private
*dev_priv
,
5993 struct i915_power_well
*power_well
)
5995 hsw_set_power_well(dev_priv
, power_well
, power_well
->count
> 0);
5998 * We're taking over the BIOS, so clear any requests made by it since
5999 * the driver is in charge now.
6001 if (I915_READ(HSW_PWR_WELL_BIOS
) & HSW_PWR_WELL_ENABLE_REQUEST
)
6002 I915_WRITE(HSW_PWR_WELL_BIOS
, 0);
6005 static void hsw_power_well_enable(struct drm_i915_private
*dev_priv
,
6006 struct i915_power_well
*power_well
)
6008 hsw_set_power_well(dev_priv
, power_well
, true);
6011 static void hsw_power_well_disable(struct drm_i915_private
*dev_priv
,
6012 struct i915_power_well
*power_well
)
6014 hsw_set_power_well(dev_priv
, power_well
, false);
6017 static void i9xx_always_on_power_well_noop(struct drm_i915_private
*dev_priv
,
6018 struct i915_power_well
*power_well
)
6022 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private
*dev_priv
,
6023 struct i915_power_well
*power_well
)
6028 static void vlv_set_power_well(struct drm_i915_private
*dev_priv
,
6029 struct i915_power_well
*power_well
, bool enable
)
6031 enum punit_power_well power_well_id
= power_well
->data
;
6036 mask
= PUNIT_PWRGT_MASK(power_well_id
);
6037 state
= enable
? PUNIT_PWRGT_PWR_ON(power_well_id
) :
6038 PUNIT_PWRGT_PWR_GATE(power_well_id
);
6040 mutex_lock(&dev_priv
->rps
.hw_lock
);
6043 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
6048 ctrl
= vlv_punit_read(dev_priv
, PUNIT_REG_PWRGT_CTRL
);
6051 vlv_punit_write(dev_priv
, PUNIT_REG_PWRGT_CTRL
, ctrl
);
6053 if (wait_for(COND
, 100))
6054 DRM_ERROR("timout setting power well state %08x (%08x)\n",
6056 vlv_punit_read(dev_priv
, PUNIT_REG_PWRGT_CTRL
));
6061 mutex_unlock(&dev_priv
->rps
.hw_lock
);
6064 static void vlv_power_well_sync_hw(struct drm_i915_private
*dev_priv
,
6065 struct i915_power_well
*power_well
)
6067 vlv_set_power_well(dev_priv
, power_well
, power_well
->count
> 0);
6070 static void vlv_power_well_enable(struct drm_i915_private
*dev_priv
,
6071 struct i915_power_well
*power_well
)
6073 vlv_set_power_well(dev_priv
, power_well
, true);
6076 static void vlv_power_well_disable(struct drm_i915_private
*dev_priv
,
6077 struct i915_power_well
*power_well
)
6079 vlv_set_power_well(dev_priv
, power_well
, false);
6082 static bool vlv_power_well_enabled(struct drm_i915_private
*dev_priv
,
6083 struct i915_power_well
*power_well
)
6085 int power_well_id
= power_well
->data
;
6086 bool enabled
= false;
6091 mask
= PUNIT_PWRGT_MASK(power_well_id
);
6092 ctrl
= PUNIT_PWRGT_PWR_ON(power_well_id
);
6094 mutex_lock(&dev_priv
->rps
.hw_lock
);
6096 state
= vlv_punit_read(dev_priv
, PUNIT_REG_PWRGT_STATUS
) & mask
;
6098 * We only ever set the power-on and power-gate states, anything
6099 * else is unexpected.
6101 WARN_ON(state
!= PUNIT_PWRGT_PWR_ON(power_well_id
) &&
6102 state
!= PUNIT_PWRGT_PWR_GATE(power_well_id
));
6107 * A transient state at this point would mean some unexpected party
6108 * is poking at the power controls too.
6110 ctrl
= vlv_punit_read(dev_priv
, PUNIT_REG_PWRGT_CTRL
) & mask
;
6111 WARN_ON(ctrl
!= state
);
6113 mutex_unlock(&dev_priv
->rps
.hw_lock
);
6118 static void vlv_display_power_well_enable(struct drm_i915_private
*dev_priv
,
6119 struct i915_power_well
*power_well
)
6121 WARN_ON_ONCE(power_well
->data
!= PUNIT_POWER_WELL_DISP2D
);
6123 vlv_set_power_well(dev_priv
, power_well
, true);
6125 spin_lock_irq(&dev_priv
->irq_lock
);
6126 valleyview_enable_display_irqs(dev_priv
);
6127 spin_unlock_irq(&dev_priv
->irq_lock
);
6130 * During driver initialization/resume we can avoid restoring the
6131 * part of the HW/SW state that will be inited anyway explicitly.
6133 if (dev_priv
->power_domains
.initializing
)
6136 intel_hpd_init(dev_priv
->dev
);
6138 i915_redisable_vga_power_on(dev_priv
->dev
);
6141 static void vlv_display_power_well_disable(struct drm_i915_private
*dev_priv
,
6142 struct i915_power_well
*power_well
)
6144 WARN_ON_ONCE(power_well
->data
!= PUNIT_POWER_WELL_DISP2D
);
6146 spin_lock_irq(&dev_priv
->irq_lock
);
6147 valleyview_disable_display_irqs(dev_priv
);
6148 spin_unlock_irq(&dev_priv
->irq_lock
);
6150 vlv_set_power_well(dev_priv
, power_well
, false);
6153 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private
*dev_priv
,
6154 struct i915_power_well
*power_well
)
6156 WARN_ON_ONCE(power_well
->data
!= PUNIT_POWER_WELL_DPIO_CMN_BC
);
6159 * Enable the CRI clock source so we can get at the
6160 * display and the reference clock for VGA
6161 * hotplug / manual detection.
6163 I915_WRITE(DPLL(PIPE_B
), I915_READ(DPLL(PIPE_B
)) |
6164 DPLL_REFA_CLK_ENABLE_VLV
| DPLL_INTEGRATED_CRI_CLK_VLV
);
6165 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
6167 vlv_set_power_well(dev_priv
, power_well
, true);
6170 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
6171 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
6172 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
6173 * b. The other bits such as sfr settings / modesel may all
6176 * This should only be done on init and resume from S3 with
6177 * both PLLs disabled, or we risk losing DPIO and PLL
6180 I915_WRITE(DPIO_CTL
, I915_READ(DPIO_CTL
) | DPIO_CMNRST
);
6183 static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private
*dev_priv
,
6184 struct i915_power_well
*power_well
)
6186 struct drm_device
*dev
= dev_priv
->dev
;
6189 WARN_ON_ONCE(power_well
->data
!= PUNIT_POWER_WELL_DPIO_CMN_BC
);
6192 assert_pll_disabled(dev_priv
, pipe
);
6194 /* Assert common reset */
6195 I915_WRITE(DPIO_CTL
, I915_READ(DPIO_CTL
) & ~DPIO_CMNRST
);
6197 vlv_set_power_well(dev_priv
, power_well
, false);
6200 static void check_power_well_state(struct drm_i915_private
*dev_priv
,
6201 struct i915_power_well
*power_well
)
6203 bool enabled
= power_well
->ops
->is_enabled(dev_priv
, power_well
);
6205 if (power_well
->always_on
|| !i915
.disable_power_well
) {
6212 if (enabled
!= (power_well
->count
> 0))
6218 WARN(1, "state mismatch for '%s' (always_on %d hw state %d use-count %d disable_power_well %d\n",
6219 power_well
->name
, power_well
->always_on
, enabled
,
6220 power_well
->count
, i915
.disable_power_well
);
6223 void intel_display_power_get(struct drm_i915_private
*dev_priv
,
6224 enum intel_display_power_domain domain
)
6226 struct i915_power_domains
*power_domains
;
6227 struct i915_power_well
*power_well
;
6230 intel_runtime_pm_get(dev_priv
);
6232 power_domains
= &dev_priv
->power_domains
;
6234 mutex_lock(&power_domains
->lock
);
6236 for_each_power_well(i
, power_well
, BIT(domain
), power_domains
) {
6237 if (!power_well
->count
++) {
6238 DRM_DEBUG_KMS("enabling %s\n", power_well
->name
);
6239 power_well
->ops
->enable(dev_priv
, power_well
);
6240 power_well
->hw_enabled
= true;
6243 check_power_well_state(dev_priv
, power_well
);
6246 power_domains
->domain_use_count
[domain
]++;
6248 mutex_unlock(&power_domains
->lock
);
6251 void intel_display_power_put(struct drm_i915_private
*dev_priv
,
6252 enum intel_display_power_domain domain
)
6254 struct i915_power_domains
*power_domains
;
6255 struct i915_power_well
*power_well
;
6258 power_domains
= &dev_priv
->power_domains
;
6260 mutex_lock(&power_domains
->lock
);
6262 WARN_ON(!power_domains
->domain_use_count
[domain
]);
6263 power_domains
->domain_use_count
[domain
]--;
6265 for_each_power_well_rev(i
, power_well
, BIT(domain
), power_domains
) {
6266 WARN_ON(!power_well
->count
);
6268 if (!--power_well
->count
&& i915
.disable_power_well
) {
6269 DRM_DEBUG_KMS("disabling %s\n", power_well
->name
);
6270 power_well
->hw_enabled
= false;
6271 power_well
->ops
->disable(dev_priv
, power_well
);
6274 check_power_well_state(dev_priv
, power_well
);
6277 mutex_unlock(&power_domains
->lock
);
6279 intel_runtime_pm_put(dev_priv
);
6282 static struct i915_power_domains
*hsw_pwr
;
6284 /* Display audio driver power well request */
6285 int i915_request_power_well(void)
6287 struct drm_i915_private
*dev_priv
;
6292 dev_priv
= container_of(hsw_pwr
, struct drm_i915_private
,
6294 intel_display_power_get(dev_priv
, POWER_DOMAIN_AUDIO
);
6297 EXPORT_SYMBOL_GPL(i915_request_power_well
);
6299 /* Display audio driver power well release */
6300 int i915_release_power_well(void)
6302 struct drm_i915_private
*dev_priv
;
6307 dev_priv
= container_of(hsw_pwr
, struct drm_i915_private
,
6309 intel_display_power_put(dev_priv
, POWER_DOMAIN_AUDIO
);
6312 EXPORT_SYMBOL_GPL(i915_release_power_well
);
6315 * Private interface for the audio driver to get CDCLK in kHz.
6317 * Caller must request power well using i915_request_power_well() prior to
6320 int i915_get_cdclk_freq(void)
6322 struct drm_i915_private
*dev_priv
;
6327 dev_priv
= container_of(hsw_pwr
, struct drm_i915_private
,
6330 return intel_ddi_get_cdclk_freq(dev_priv
);
6332 EXPORT_SYMBOL_GPL(i915_get_cdclk_freq
);
6335 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
6337 #define HSW_ALWAYS_ON_POWER_DOMAINS ( \
6338 BIT(POWER_DOMAIN_PIPE_A) | \
6339 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
6340 BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
6341 BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
6342 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6343 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6344 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6345 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6346 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
6347 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
6348 BIT(POWER_DOMAIN_PORT_CRT) | \
6349 BIT(POWER_DOMAIN_PLLS) | \
6350 BIT(POWER_DOMAIN_INIT))
6351 #define HSW_DISPLAY_POWER_DOMAINS ( \
6352 (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \
6353 BIT(POWER_DOMAIN_INIT))
6355 #define BDW_ALWAYS_ON_POWER_DOMAINS ( \
6356 HSW_ALWAYS_ON_POWER_DOMAINS | \
6357 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
6358 #define BDW_DISPLAY_POWER_DOMAINS ( \
6359 (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) | \
6360 BIT(POWER_DOMAIN_INIT))
6362 #define VLV_ALWAYS_ON_POWER_DOMAINS BIT(POWER_DOMAIN_INIT)
6363 #define VLV_DISPLAY_POWER_DOMAINS POWER_DOMAIN_MASK
6365 #define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \
6366 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6367 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6368 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6369 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6370 BIT(POWER_DOMAIN_PORT_CRT) | \
6371 BIT(POWER_DOMAIN_INIT))
6373 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \
6374 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6375 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6376 BIT(POWER_DOMAIN_INIT))
6378 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \
6379 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6380 BIT(POWER_DOMAIN_INIT))
6382 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \
6383 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6384 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6385 BIT(POWER_DOMAIN_INIT))
6387 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \
6388 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6389 BIT(POWER_DOMAIN_INIT))
6391 static const struct i915_power_well_ops i9xx_always_on_power_well_ops
= {
6392 .sync_hw
= i9xx_always_on_power_well_noop
,
6393 .enable
= i9xx_always_on_power_well_noop
,
6394 .disable
= i9xx_always_on_power_well_noop
,
6395 .is_enabled
= i9xx_always_on_power_well_enabled
,
6398 static struct i915_power_well i9xx_always_on_power_well
[] = {
6400 .name
= "always-on",
6402 .domains
= POWER_DOMAIN_MASK
,
6403 .ops
= &i9xx_always_on_power_well_ops
,
6407 static const struct i915_power_well_ops hsw_power_well_ops
= {
6408 .sync_hw
= hsw_power_well_sync_hw
,
6409 .enable
= hsw_power_well_enable
,
6410 .disable
= hsw_power_well_disable
,
6411 .is_enabled
= hsw_power_well_enabled
,
6414 static struct i915_power_well hsw_power_wells
[] = {
6416 .name
= "always-on",
6418 .domains
= HSW_ALWAYS_ON_POWER_DOMAINS
,
6419 .ops
= &i9xx_always_on_power_well_ops
,
6423 .domains
= HSW_DISPLAY_POWER_DOMAINS
,
6424 .ops
= &hsw_power_well_ops
,
6428 static struct i915_power_well bdw_power_wells
[] = {
6430 .name
= "always-on",
6432 .domains
= BDW_ALWAYS_ON_POWER_DOMAINS
,
6433 .ops
= &i9xx_always_on_power_well_ops
,
6437 .domains
= BDW_DISPLAY_POWER_DOMAINS
,
6438 .ops
= &hsw_power_well_ops
,
6442 static const struct i915_power_well_ops vlv_display_power_well_ops
= {
6443 .sync_hw
= vlv_power_well_sync_hw
,
6444 .enable
= vlv_display_power_well_enable
,
6445 .disable
= vlv_display_power_well_disable
,
6446 .is_enabled
= vlv_power_well_enabled
,
6449 static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops
= {
6450 .sync_hw
= vlv_power_well_sync_hw
,
6451 .enable
= vlv_dpio_cmn_power_well_enable
,
6452 .disable
= vlv_dpio_cmn_power_well_disable
,
6453 .is_enabled
= vlv_power_well_enabled
,
6456 static const struct i915_power_well_ops vlv_dpio_power_well_ops
= {
6457 .sync_hw
= vlv_power_well_sync_hw
,
6458 .enable
= vlv_power_well_enable
,
6459 .disable
= vlv_power_well_disable
,
6460 .is_enabled
= vlv_power_well_enabled
,
6463 static struct i915_power_well vlv_power_wells
[] = {
6465 .name
= "always-on",
6467 .domains
= VLV_ALWAYS_ON_POWER_DOMAINS
,
6468 .ops
= &i9xx_always_on_power_well_ops
,
6472 .domains
= VLV_DISPLAY_POWER_DOMAINS
,
6473 .data
= PUNIT_POWER_WELL_DISP2D
,
6474 .ops
= &vlv_display_power_well_ops
,
6477 .name
= "dpio-tx-b-01",
6478 .domains
= VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS
|
6479 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS
|
6480 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS
|
6481 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS
,
6482 .ops
= &vlv_dpio_power_well_ops
,
6483 .data
= PUNIT_POWER_WELL_DPIO_TX_B_LANES_01
,
6486 .name
= "dpio-tx-b-23",
6487 .domains
= VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS
|
6488 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS
|
6489 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS
|
6490 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS
,
6491 .ops
= &vlv_dpio_power_well_ops
,
6492 .data
= PUNIT_POWER_WELL_DPIO_TX_B_LANES_23
,
6495 .name
= "dpio-tx-c-01",
6496 .domains
= VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS
|
6497 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS
|
6498 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS
|
6499 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS
,
6500 .ops
= &vlv_dpio_power_well_ops
,
6501 .data
= PUNIT_POWER_WELL_DPIO_TX_C_LANES_01
,
6504 .name
= "dpio-tx-c-23",
6505 .domains
= VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS
|
6506 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS
|
6507 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS
|
6508 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS
,
6509 .ops
= &vlv_dpio_power_well_ops
,
6510 .data
= PUNIT_POWER_WELL_DPIO_TX_C_LANES_23
,
6513 .name
= "dpio-common",
6514 .domains
= VLV_DPIO_CMN_BC_POWER_DOMAINS
,
6515 .data
= PUNIT_POWER_WELL_DPIO_CMN_BC
,
6516 .ops
= &vlv_dpio_cmn_power_well_ops
,
6520 static struct i915_power_well
*lookup_power_well(struct drm_i915_private
*dev_priv
,
6521 enum punit_power_well power_well_id
)
6523 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
6524 struct i915_power_well
*power_well
;
6527 for_each_power_well(i
, power_well
, POWER_DOMAIN_MASK
, power_domains
) {
6528 if (power_well
->data
== power_well_id
)
6535 #define set_power_wells(power_domains, __power_wells) ({ \
6536 (power_domains)->power_wells = (__power_wells); \
6537 (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \
6540 int intel_power_domains_init(struct drm_i915_private
*dev_priv
)
6542 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
6544 mutex_init(&power_domains
->lock
);
6547 * The enabling order will be from lower to higher indexed wells,
6548 * the disabling order is reversed.
6550 if (IS_HASWELL(dev_priv
->dev
)) {
6551 set_power_wells(power_domains
, hsw_power_wells
);
6552 hsw_pwr
= power_domains
;
6553 } else if (IS_BROADWELL(dev_priv
->dev
)) {
6554 set_power_wells(power_domains
, bdw_power_wells
);
6555 hsw_pwr
= power_domains
;
6556 } else if (IS_VALLEYVIEW(dev_priv
->dev
)) {
6557 set_power_wells(power_domains
, vlv_power_wells
);
6559 set_power_wells(power_domains
, i9xx_always_on_power_well
);
6565 void intel_power_domains_remove(struct drm_i915_private
*dev_priv
)
6570 static void intel_power_domains_resume(struct drm_i915_private
*dev_priv
)
6572 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
6573 struct i915_power_well
*power_well
;
6576 mutex_lock(&power_domains
->lock
);
6577 for_each_power_well(i
, power_well
, POWER_DOMAIN_MASK
, power_domains
) {
6578 power_well
->ops
->sync_hw(dev_priv
, power_well
);
6579 power_well
->hw_enabled
= power_well
->ops
->is_enabled(dev_priv
,
6582 mutex_unlock(&power_domains
->lock
);
6585 static void vlv_cmnlane_wa(struct drm_i915_private
*dev_priv
)
6587 struct i915_power_well
*cmn
=
6588 lookup_power_well(dev_priv
, PUNIT_POWER_WELL_DPIO_CMN_BC
);
6589 struct i915_power_well
*disp2d
=
6590 lookup_power_well(dev_priv
, PUNIT_POWER_WELL_DISP2D
);
6592 /* nothing to do if common lane is already off */
6593 if (!cmn
->ops
->is_enabled(dev_priv
, cmn
))
6596 /* If the display might be already active skip this */
6597 if (disp2d
->ops
->is_enabled(dev_priv
, disp2d
) &&
6598 I915_READ(DPIO_CTL
) & DPIO_CMNRST
)
6601 DRM_DEBUG_KMS("toggling display PHY side reset\n");
6603 /* cmnlane needs DPLL registers */
6604 disp2d
->ops
->enable(dev_priv
, disp2d
);
6607 * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
6608 * Need to assert and de-assert PHY SB reset by gating the
6609 * common lane power, then un-gating it.
6610 * Simply ungating isn't enough to reset the PHY enough to get
6611 * ports and lanes running.
6613 cmn
->ops
->disable(dev_priv
, cmn
);
6616 void intel_power_domains_init_hw(struct drm_i915_private
*dev_priv
)
6618 struct drm_device
*dev
= dev_priv
->dev
;
6619 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
6621 power_domains
->initializing
= true;
6623 if (IS_VALLEYVIEW(dev
) && !IS_CHERRYVIEW(dev
)) {
6624 mutex_lock(&power_domains
->lock
);
6625 vlv_cmnlane_wa(dev_priv
);
6626 mutex_unlock(&power_domains
->lock
);
6629 /* For now, we need the power well to be always enabled. */
6630 intel_display_set_init_power(dev_priv
, true);
6631 intel_power_domains_resume(dev_priv
);
6632 power_domains
->initializing
= false;
6635 void intel_aux_display_runtime_get(struct drm_i915_private
*dev_priv
)
6637 intel_runtime_pm_get(dev_priv
);
6640 void intel_aux_display_runtime_put(struct drm_i915_private
*dev_priv
)
6642 intel_runtime_pm_put(dev_priv
);
6645 void intel_runtime_pm_get(struct drm_i915_private
*dev_priv
)
6647 struct drm_device
*dev
= dev_priv
->dev
;
6648 struct device
*device
= &dev
->pdev
->dev
;
6650 if (!HAS_RUNTIME_PM(dev
))
6653 pm_runtime_get_sync(device
);
6654 WARN(dev_priv
->pm
.suspended
, "Device still suspended.\n");
6657 void intel_runtime_pm_get_noresume(struct drm_i915_private
*dev_priv
)
6659 struct drm_device
*dev
= dev_priv
->dev
;
6660 struct device
*device
= &dev
->pdev
->dev
;
6662 if (!HAS_RUNTIME_PM(dev
))
6665 WARN(dev_priv
->pm
.suspended
, "Getting nosync-ref while suspended.\n");
6666 pm_runtime_get_noresume(device
);
6669 void intel_runtime_pm_put(struct drm_i915_private
*dev_priv
)
6671 struct drm_device
*dev
= dev_priv
->dev
;
6672 struct device
*device
= &dev
->pdev
->dev
;
6674 if (!HAS_RUNTIME_PM(dev
))
6677 pm_runtime_mark_last_busy(device
);
6678 pm_runtime_put_autosuspend(device
);
6681 void intel_init_runtime_pm(struct drm_i915_private
*dev_priv
)
6683 struct drm_device
*dev
= dev_priv
->dev
;
6684 struct device
*device
= &dev
->pdev
->dev
;
6686 if (!HAS_RUNTIME_PM(dev
))
6689 pm_runtime_set_active(device
);
6692 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6695 if (!intel_enable_rc6(dev
)) {
6696 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6700 pm_runtime_set_autosuspend_delay(device
, 10000); /* 10s */
6701 pm_runtime_mark_last_busy(device
);
6702 pm_runtime_use_autosuspend(device
);
6704 pm_runtime_put_autosuspend(device
);
6707 void intel_fini_runtime_pm(struct drm_i915_private
*dev_priv
)
6709 struct drm_device
*dev
= dev_priv
->dev
;
6710 struct device
*device
= &dev
->pdev
->dev
;
6712 if (!HAS_RUNTIME_PM(dev
))
6715 if (!intel_enable_rc6(dev
))
6718 /* Make sure we're not suspended first. */
6719 pm_runtime_get_sync(device
);
6720 pm_runtime_disable(device
);
6723 /* Set up chip specific power management-related functions */
6724 void intel_init_pm(struct drm_device
*dev
)
6726 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6729 if (INTEL_INFO(dev
)->gen
>= 7) {
6730 dev_priv
->display
.fbc_enabled
= ironlake_fbc_enabled
;
6731 dev_priv
->display
.enable_fbc
= gen7_enable_fbc
;
6732 dev_priv
->display
.disable_fbc
= ironlake_disable_fbc
;
6733 } else if (INTEL_INFO(dev
)->gen
>= 5) {
6734 dev_priv
->display
.fbc_enabled
= ironlake_fbc_enabled
;
6735 dev_priv
->display
.enable_fbc
= ironlake_enable_fbc
;
6736 dev_priv
->display
.disable_fbc
= ironlake_disable_fbc
;
6737 } else if (IS_GM45(dev
)) {
6738 dev_priv
->display
.fbc_enabled
= g4x_fbc_enabled
;
6739 dev_priv
->display
.enable_fbc
= g4x_enable_fbc
;
6740 dev_priv
->display
.disable_fbc
= g4x_disable_fbc
;
6742 dev_priv
->display
.fbc_enabled
= i8xx_fbc_enabled
;
6743 dev_priv
->display
.enable_fbc
= i8xx_enable_fbc
;
6744 dev_priv
->display
.disable_fbc
= i8xx_disable_fbc
;
6746 /* This value was pulled out of someone's hat */
6747 I915_WRITE(FBC_CONTROL
, 500 << FBC_CTL_INTERVAL_SHIFT
);
6752 if (IS_PINEVIEW(dev
))
6753 i915_pineview_get_mem_freq(dev
);
6754 else if (IS_GEN5(dev
))
6755 i915_ironlake_get_mem_freq(dev
);
6757 /* For FIFO watermark updates */
6758 if (HAS_PCH_SPLIT(dev
)) {
6759 ilk_setup_wm_latency(dev
);
6761 if ((IS_GEN5(dev
) && dev_priv
->wm
.pri_latency
[1] &&
6762 dev_priv
->wm
.spr_latency
[1] && dev_priv
->wm
.cur_latency
[1]) ||
6763 (!IS_GEN5(dev
) && dev_priv
->wm
.pri_latency
[0] &&
6764 dev_priv
->wm
.spr_latency
[0] && dev_priv
->wm
.cur_latency
[0])) {
6765 dev_priv
->display
.update_wm
= ilk_update_wm
;
6766 dev_priv
->display
.update_sprite_wm
= ilk_update_sprite_wm
;
6768 DRM_DEBUG_KMS("Failed to read display plane latency. "
6773 dev_priv
->display
.init_clock_gating
= ironlake_init_clock_gating
;
6774 else if (IS_GEN6(dev
))
6775 dev_priv
->display
.init_clock_gating
= gen6_init_clock_gating
;
6776 else if (IS_IVYBRIDGE(dev
))
6777 dev_priv
->display
.init_clock_gating
= ivybridge_init_clock_gating
;
6778 else if (IS_HASWELL(dev
))
6779 dev_priv
->display
.init_clock_gating
= haswell_init_clock_gating
;
6780 else if (INTEL_INFO(dev
)->gen
== 8)
6781 dev_priv
->display
.init_clock_gating
= gen8_init_clock_gating
;
6782 } else if (IS_CHERRYVIEW(dev
)) {
6783 dev_priv
->display
.update_wm
= valleyview_update_wm
;
6784 dev_priv
->display
.init_clock_gating
=
6785 cherryview_init_clock_gating
;
6786 } else if (IS_VALLEYVIEW(dev
)) {
6787 dev_priv
->display
.update_wm
= valleyview_update_wm
;
6788 dev_priv
->display
.init_clock_gating
=
6789 valleyview_init_clock_gating
;
6790 } else if (IS_PINEVIEW(dev
)) {
6791 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev
),
6794 dev_priv
->mem_freq
)) {
6795 DRM_INFO("failed to find known CxSR latency "
6796 "(found ddr%s fsb freq %d, mem freq %d), "
6798 (dev_priv
->is_ddr3
== 1) ? "3" : "2",
6799 dev_priv
->fsb_freq
, dev_priv
->mem_freq
);
6800 /* Disable CxSR and never update its watermark again */
6801 intel_set_memory_cxsr(dev_priv
, false);
6802 dev_priv
->display
.update_wm
= NULL
;
6804 dev_priv
->display
.update_wm
= pineview_update_wm
;
6805 dev_priv
->display
.init_clock_gating
= gen3_init_clock_gating
;
6806 } else if (IS_G4X(dev
)) {
6807 dev_priv
->display
.update_wm
= g4x_update_wm
;
6808 dev_priv
->display
.init_clock_gating
= g4x_init_clock_gating
;
6809 } else if (IS_GEN4(dev
)) {
6810 dev_priv
->display
.update_wm
= i965_update_wm
;
6811 if (IS_CRESTLINE(dev
))
6812 dev_priv
->display
.init_clock_gating
= crestline_init_clock_gating
;
6813 else if (IS_BROADWATER(dev
))
6814 dev_priv
->display
.init_clock_gating
= broadwater_init_clock_gating
;
6815 } else if (IS_GEN3(dev
)) {
6816 dev_priv
->display
.update_wm
= i9xx_update_wm
;
6817 dev_priv
->display
.get_fifo_size
= i9xx_get_fifo_size
;
6818 dev_priv
->display
.init_clock_gating
= gen3_init_clock_gating
;
6819 } else if (IS_GEN2(dev
)) {
6820 if (INTEL_INFO(dev
)->num_pipes
== 1) {
6821 dev_priv
->display
.update_wm
= i845_update_wm
;
6822 dev_priv
->display
.get_fifo_size
= i845_get_fifo_size
;
6824 dev_priv
->display
.update_wm
= i9xx_update_wm
;
6825 dev_priv
->display
.get_fifo_size
= i830_get_fifo_size
;
6828 if (IS_I85X(dev
) || IS_I865G(dev
))
6829 dev_priv
->display
.init_clock_gating
= i85x_init_clock_gating
;
6831 dev_priv
->display
.init_clock_gating
= i830_init_clock_gating
;
6833 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
6837 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u8 mbox
, u32
*val
)
6839 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
6841 if (I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) {
6842 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
6846 I915_WRITE(GEN6_PCODE_DATA
, *val
);
6847 I915_WRITE(GEN6_PCODE_MAILBOX
, GEN6_PCODE_READY
| mbox
);
6849 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) == 0,
6851 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox
);
6855 *val
= I915_READ(GEN6_PCODE_DATA
);
6856 I915_WRITE(GEN6_PCODE_DATA
, 0);
6861 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
, u8 mbox
, u32 val
)
6863 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
6865 if (I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) {
6866 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
6870 I915_WRITE(GEN6_PCODE_DATA
, val
);
6871 I915_WRITE(GEN6_PCODE_MAILBOX
, GEN6_PCODE_READY
| mbox
);
6873 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) == 0,
6875 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox
);
6879 I915_WRITE(GEN6_PCODE_DATA
, 0);
6884 int vlv_gpu_freq(struct drm_i915_private
*dev_priv
, int val
)
6889 switch (dev_priv
->mem_freq
) {
6903 return DIV_ROUND_CLOSEST(dev_priv
->mem_freq
* (val
+ 6 - 0xbd), 4 * div
);
6906 int vlv_freq_opcode(struct drm_i915_private
*dev_priv
, int val
)
6911 switch (dev_priv
->mem_freq
) {
6925 return DIV_ROUND_CLOSEST(4 * mul
* val
, dev_priv
->mem_freq
) + 0xbd - 6;
6928 void intel_pm_setup(struct drm_device
*dev
)
6930 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6932 mutex_init(&dev_priv
->rps
.hw_lock
);
6934 INIT_DELAYED_WORK(&dev_priv
->rps
.delayed_resume_work
,
6935 intel_gen6_powersave_work
);
6937 dev_priv
->pm
.suspended
= false;
6938 dev_priv
->pm
.irqs_disabled
= false;