projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge branch 'drm-next-3.18' of git://people.freedesktop.org/~agd5f/linux into drm...
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_pm.c
1 /*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28 #include <linux/cpufreq.h>
29 #include "i915_drv.h"
30 #include "intel_drv.h"
31 #include "../../../platform/x86/intel_ips.h"
32 #include <linux/module.h>
33 #include <linux/vgaarb.h>
34 #include <drm/i915_powerwell.h>
35 #include <linux/pm_runtime.h>
36
37 /**
38 * RC6 is a special power stage which allows the GPU to enter an very
39 * low-voltage mode when idle, using down to 0V while at this stage. This
40 * stage is entered automatically when the GPU is idle when RC6 support is
41 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
42 *
43 * There are different RC6 modes available in Intel GPU, which differentiate
44 * among each other with the latency required to enter and leave RC6 and
45 * voltage consumed by the GPU in different states.
46 *
47 * The combination of the following flags define which states GPU is allowed
48 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
49 * RC6pp is deepest RC6. Their support by hardware varies according to the
50 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
51 * which brings the most power savings; deeper states save more power, but
52 * require higher latency to switch to and wake up.
53 */
54 #define INTEL_RC6_ENABLE (1<<0)
55 #define INTEL_RC6p_ENABLE (1<<1)
56 #define INTEL_RC6pp_ENABLE (1<<2)
57
58 /* FBC, or Frame Buffer Compression, is a technique employed to compress the
59 * framebuffer contents in-memory, aiming at reducing the required bandwidth
60 * during in-memory transfers and, therefore, reduce the power packet.
61 *
62 * The benefits of FBC are mostly visible with solid backgrounds and
63 * variation-less patterns.
64 *
65 * FBC-related functionality can be enabled by the means of the
66 * i915.i915_enable_fbc parameter
67 */
68
69 static void i8xx_disable_fbc(struct drm_device *dev)
70 {
71 struct drm_i915_private *dev_priv = dev->dev_private;
72 u32 fbc_ctl;
73
74 /* Disable compression */
75 fbc_ctl = I915_READ(FBC_CONTROL);
76 if ((fbc_ctl & FBC_CTL_EN) == 0)
77 return;
78
79 fbc_ctl &= ~FBC_CTL_EN;
80 I915_WRITE(FBC_CONTROL, fbc_ctl);
81
82 /* Wait for compressing bit to clear */
83 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
84 DRM_DEBUG_KMS("FBC idle timed out\n");
85 return;
86 }
87
88 DRM_DEBUG_KMS("disabled FBC\n");
89 }
90
91 static void i8xx_enable_fbc(struct drm_crtc *crtc)
92 {
93 struct drm_device *dev = crtc->dev;
94 struct drm_i915_private *dev_priv = dev->dev_private;
95 struct drm_framebuffer *fb = crtc->primary->fb;
96 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
97 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
98 int cfb_pitch;
99 int i;
100 u32 fbc_ctl;
101
102 cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
103 if (fb->pitches[0] < cfb_pitch)
104 cfb_pitch = fb->pitches[0];
105
106 /* FBC_CTL wants 32B or 64B units */
107 if (IS_GEN2(dev))
108 cfb_pitch = (cfb_pitch / 32) - 1;
109 else
110 cfb_pitch = (cfb_pitch / 64) - 1;
111
112 /* Clear old tags */
113 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
114 I915_WRITE(FBC_TAG + (i * 4), 0);
115
116 if (IS_GEN4(dev)) {
117 u32 fbc_ctl2;
118
119 /* Set it up... */
120 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
121 fbc_ctl2 |= FBC_CTL_PLANE(intel_crtc->plane);
122 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
123 I915_WRITE(FBC_FENCE_OFF, crtc->y);
124 }
125
126 /* enable it... */
127 fbc_ctl = I915_READ(FBC_CONTROL);
128 fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT;
129 fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
130 if (IS_I945GM(dev))
131 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
132 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
133 fbc_ctl |= obj->fence_reg;
134 I915_WRITE(FBC_CONTROL, fbc_ctl);
135
136 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c\n",
137 cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
138 }
139
140 static bool i8xx_fbc_enabled(struct drm_device *dev)
141 {
142 struct drm_i915_private *dev_priv = dev->dev_private;
143
144 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
145 }
146
147 static void g4x_enable_fbc(struct drm_crtc *crtc)
148 {
149 struct drm_device *dev = crtc->dev;
150 struct drm_i915_private *dev_priv = dev->dev_private;
151 struct drm_framebuffer *fb = crtc->primary->fb;
152 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
153 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
154 u32 dpfc_ctl;
155
156 dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane) | DPFC_SR_EN;
157 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
158 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
159 else
160 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
161 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
162
163 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
164
165 /* enable it... */
166 I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
167
168 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
169 }
170
171 static void g4x_disable_fbc(struct drm_device *dev)
172 {
173 struct drm_i915_private *dev_priv = dev->dev_private;
174 u32 dpfc_ctl;
175
176 /* Disable compression */
177 dpfc_ctl = I915_READ(DPFC_CONTROL);
178 if (dpfc_ctl & DPFC_CTL_EN) {
179 dpfc_ctl &= ~DPFC_CTL_EN;
180 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
181
182 DRM_DEBUG_KMS("disabled FBC\n");
183 }
184 }
185
186 static bool g4x_fbc_enabled(struct drm_device *dev)
187 {
188 struct drm_i915_private *dev_priv = dev->dev_private;
189
190 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
191 }
192
193 static void sandybridge_blit_fbc_update(struct drm_device *dev)
194 {
195 struct drm_i915_private *dev_priv = dev->dev_private;
196 u32 blt_ecoskpd;
197
198 /* Make sure blitter notifies FBC of writes */
199
200 /* Blitter is part of Media powerwell on VLV. No impact of
201 * his param in other platforms for now */
202 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_MEDIA);
203
204 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
205 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
206 GEN6_BLITTER_LOCK_SHIFT;
207 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
208 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
209 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
210 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
211 GEN6_BLITTER_LOCK_SHIFT);
212 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
213 POSTING_READ(GEN6_BLITTER_ECOSKPD);
214
215 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_MEDIA);
216 }
217
218 static void ironlake_enable_fbc(struct drm_crtc *crtc)
219 {
220 struct drm_device *dev = crtc->dev;
221 struct drm_i915_private *dev_priv = dev->dev_private;
222 struct drm_framebuffer *fb = crtc->primary->fb;
223 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
224 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
225 u32 dpfc_ctl;
226
227 dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane);
228 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
229 dev_priv->fbc.threshold++;
230
231 switch (dev_priv->fbc.threshold) {
232 case 4:
233 case 3:
234 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
235 break;
236 case 2:
237 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
238 break;
239 case 1:
240 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
241 break;
242 }
243 dpfc_ctl |= DPFC_CTL_FENCE_EN;
244 if (IS_GEN5(dev))
245 dpfc_ctl |= obj->fence_reg;
246
247 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
248 I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
249 /* enable it... */
250 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
251
252 if (IS_GEN6(dev)) {
253 I915_WRITE(SNB_DPFC_CTL_SA,
254 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
255 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
256 sandybridge_blit_fbc_update(dev);
257 }
258
259 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
260 }
261
262 static void ironlake_disable_fbc(struct drm_device *dev)
263 {
264 struct drm_i915_private *dev_priv = dev->dev_private;
265 u32 dpfc_ctl;
266
267 /* Disable compression */
268 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
269 if (dpfc_ctl & DPFC_CTL_EN) {
270 dpfc_ctl &= ~DPFC_CTL_EN;
271 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
272
273 DRM_DEBUG_KMS("disabled FBC\n");
274 }
275 }
276
277 static bool ironlake_fbc_enabled(struct drm_device *dev)
278 {
279 struct drm_i915_private *dev_priv = dev->dev_private;
280
281 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
282 }
283
284 static void gen7_enable_fbc(struct drm_crtc *crtc)
285 {
286 struct drm_device *dev = crtc->dev;
287 struct drm_i915_private *dev_priv = dev->dev_private;
288 struct drm_framebuffer *fb = crtc->primary->fb;
289 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
290 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
291 u32 dpfc_ctl;
292
293 dpfc_ctl = IVB_DPFC_CTL_PLANE(intel_crtc->plane);
294 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
295 dev_priv->fbc.threshold++;
296
297 switch (dev_priv->fbc.threshold) {
298 case 4:
299 case 3:
300 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
301 break;
302 case 2:
303 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
304 break;
305 case 1:
306 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
307 break;
308 }
309
310 dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
311
312 if (dev_priv->fbc.false_color)
313 dpfc_ctl |= FBC_CTL_FALSE_COLOR;
314
315 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
316
317 if (IS_IVYBRIDGE(dev)) {
318 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
319 I915_WRITE(ILK_DISPLAY_CHICKEN1,
320 I915_READ(ILK_DISPLAY_CHICKEN1) |
321 ILK_FBCQ_DIS);
322 } else {
323 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
324 I915_WRITE(CHICKEN_PIPESL_1(intel_crtc->pipe),
325 I915_READ(CHICKEN_PIPESL_1(intel_crtc->pipe)) |
326 HSW_FBCQ_DIS);
327 }
328
329 I915_WRITE(SNB_DPFC_CTL_SA,
330 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
331 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
332
333 sandybridge_blit_fbc_update(dev);
334
335 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
336 }
337
338 bool intel_fbc_enabled(struct drm_device *dev)
339 {
340 struct drm_i915_private *dev_priv = dev->dev_private;
341
342 if (!dev_priv->display.fbc_enabled)
343 return false;
344
345 return dev_priv->display.fbc_enabled(dev);
346 }
347
348 static void intel_fbc_work_fn(struct work_struct *__work)
349 {
350 struct intel_fbc_work *work =
351 container_of(to_delayed_work(__work),
352 struct intel_fbc_work, work);
353 struct drm_device *dev = work->crtc->dev;
354 struct drm_i915_private *dev_priv = dev->dev_private;
355
356 mutex_lock(&dev->struct_mutex);
357 if (work == dev_priv->fbc.fbc_work) {
358 /* Double check that we haven't switched fb without cancelling
359 * the prior work.
360 */
361 if (work->crtc->primary->fb == work->fb) {
362 dev_priv->display.enable_fbc(work->crtc);
363
364 dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;
365 dev_priv->fbc.fb_id = work->crtc->primary->fb->base.id;
366 dev_priv->fbc.y = work->crtc->y;
367 }
368
369 dev_priv->fbc.fbc_work = NULL;
370 }
371 mutex_unlock(&dev->struct_mutex);
372
373 kfree(work);
374 }
375
376 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
377 {
378 if (dev_priv->fbc.fbc_work == NULL)
379 return;
380
381 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
382
383 /* Synchronisation is provided by struct_mutex and checking of
384 * dev_priv->fbc.fbc_work, so we can perform the cancellation
385 * entirely asynchronously.
386 */
387 if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
388 /* tasklet was killed before being run, clean up */
389 kfree(dev_priv->fbc.fbc_work);
390
391 /* Mark the work as no longer wanted so that if it does
392 * wake-up (because the work was already running and waiting
393 * for our mutex), it will discover that is no longer
394 * necessary to run.
395 */
396 dev_priv->fbc.fbc_work = NULL;
397 }
398
399 static void intel_enable_fbc(struct drm_crtc *crtc)
400 {
401 struct intel_fbc_work *work;
402 struct drm_device *dev = crtc->dev;
403 struct drm_i915_private *dev_priv = dev->dev_private;
404
405 if (!dev_priv->display.enable_fbc)
406 return;
407
408 intel_cancel_fbc_work(dev_priv);
409
410 work = kzalloc(sizeof(*work), GFP_KERNEL);
411 if (work == NULL) {
412 DRM_ERROR("Failed to allocate FBC work structure\n");
413 dev_priv->display.enable_fbc(crtc);
414 return;
415 }
416
417 work->crtc = crtc;
418 work->fb = crtc->primary->fb;
419 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
420
421 dev_priv->fbc.fbc_work = work;
422
423 /* Delay the actual enabling to let pageflipping cease and the
424 * display to settle before starting the compression. Note that
425 * this delay also serves a second purpose: it allows for a
426 * vblank to pass after disabling the FBC before we attempt
427 * to modify the control registers.
428 *
429 * A more complicated solution would involve tracking vblanks
430 * following the termination of the page-flipping sequence
431 * and indeed performing the enable as a co-routine and not
432 * waiting synchronously upon the vblank.
433 *
434 * WaFbcWaitForVBlankBeforeEnable:ilk,snb
435 */
436 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
437 }
438
439 void intel_disable_fbc(struct drm_device *dev)
440 {
441 struct drm_i915_private *dev_priv = dev->dev_private;
442
443 intel_cancel_fbc_work(dev_priv);
444
445 if (!dev_priv->display.disable_fbc)
446 return;
447
448 dev_priv->display.disable_fbc(dev);
449 dev_priv->fbc.plane = -1;
450 }
451
452 static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
453 enum no_fbc_reason reason)
454 {
455 if (dev_priv->fbc.no_fbc_reason == reason)
456 return false;
457
458 dev_priv->fbc.no_fbc_reason = reason;
459 return true;
460 }
461
462 /**
463 * intel_update_fbc - enable/disable FBC as needed
464 * @dev: the drm_device
465 *
466 * Set up the framebuffer compression hardware at mode set time. We
467 * enable it if possible:
468 * - plane A only (on pre-965)
469 * - no pixel mulitply/line duplication
470 * - no alpha buffer discard
471 * - no dual wide
472 * - framebuffer <= max_hdisplay in width, max_vdisplay in height
473 *
474 * We can't assume that any compression will take place (worst case),
475 * so the compressed buffer has to be the same size as the uncompressed
476 * one. It also must reside (along with the line length buffer) in
477 * stolen memory.
478 *
479 * We need to enable/disable FBC on a global basis.
480 */
481 void intel_update_fbc(struct drm_device *dev)
482 {
483 struct drm_i915_private *dev_priv = dev->dev_private;
484 struct drm_crtc *crtc = NULL, *tmp_crtc;
485 struct intel_crtc *intel_crtc;
486 struct drm_framebuffer *fb;
487 struct drm_i915_gem_object *obj;
488 const struct drm_display_mode *adjusted_mode;
489 unsigned int max_width, max_height;
490
491 if (!HAS_FBC(dev)) {
492 set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED);
493 return;
494 }
495
496 if (!i915.powersave) {
497 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
498 DRM_DEBUG_KMS("fbc disabled per module param\n");
499 return;
500 }
501
502 /*
503 * If FBC is already on, we just have to verify that we can
504 * keep it that way...
505 * Need to disable if:
506 * - more than one pipe is active
507 * - changing FBC params (stride, fence, mode)
508 * - new fb is too large to fit in compressed buffer
509 * - going to an unsupported config (interlace, pixel multiply, etc.)
510 */
511 for_each_crtc(dev, tmp_crtc) {
512 if (intel_crtc_active(tmp_crtc) &&
513 to_intel_crtc(tmp_crtc)->primary_enabled) {
514 if (crtc) {
515 if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
516 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
517 goto out_disable;
518 }
519 crtc = tmp_crtc;
520 }
521 }
522
523 if (!crtc || crtc->primary->fb == NULL) {
524 if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
525 DRM_DEBUG_KMS("no output, disabling\n");
526 goto out_disable;
527 }
528
529 intel_crtc = to_intel_crtc(crtc);
530 fb = crtc->primary->fb;
531 obj = intel_fb_obj(fb);
532 adjusted_mode = &intel_crtc->config.adjusted_mode;
533
534 if (i915.enable_fbc < 0) {
535 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
536 DRM_DEBUG_KMS("disabled per chip default\n");
537 goto out_disable;
538 }
539 if (!i915.enable_fbc) {
540 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
541 DRM_DEBUG_KMS("fbc disabled per module param\n");
542 goto out_disable;
543 }
544 if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ||
545 (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
546 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
547 DRM_DEBUG_KMS("mode incompatible with compression, "
548 "disabling\n");
549 goto out_disable;
550 }
551
552 if (INTEL_INFO(dev)->gen >= 8 || IS_HASWELL(dev)) {
553 max_width = 4096;
554 max_height = 4096;
555 } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
556 max_width = 4096;
557 max_height = 2048;
558 } else {
559 max_width = 2048;
560 max_height = 1536;
561 }
562 if (intel_crtc->config.pipe_src_w > max_width ||
563 intel_crtc->config.pipe_src_h > max_height) {
564 if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
565 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
566 goto out_disable;
567 }
568 if ((INTEL_INFO(dev)->gen < 4 || HAS_DDI(dev)) &&
569 intel_crtc->plane != PLANE_A) {
570 if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
571 DRM_DEBUG_KMS("plane not A, disabling compression\n");
572 goto out_disable;
573 }
574
575 /* The use of a CPU fence is mandatory in order to detect writes
576 * by the CPU to the scanout and trigger updates to the FBC.
577 */
578 if (obj->tiling_mode != I915_TILING_X ||
579 obj->fence_reg == I915_FENCE_REG_NONE) {
580 if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED))
581 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
582 goto out_disable;
583 }
584
585 /* If the kernel debugger is active, always disable compression */
586 if (in_dbg_master())
587 goto out_disable;
588
589 if (i915_gem_stolen_setup_compression(dev, obj->base.size,
590 drm_format_plane_cpp(fb->pixel_format, 0))) {
591 if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL))
592 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
593 goto out_disable;
594 }
595
596 /* If the scanout has not changed, don't modify the FBC settings.
597 * Note that we make the fundamental assumption that the fb->obj
598 * cannot be unpinned (and have its GTT offset and fence revoked)
599 * without first being decoupled from the scanout and FBC disabled.
600 */
601 if (dev_priv->fbc.plane == intel_crtc->plane &&
602 dev_priv->fbc.fb_id == fb->base.id &&
603 dev_priv->fbc.y == crtc->y)
604 return;
605
606 if (intel_fbc_enabled(dev)) {
607 /* We update FBC along two paths, after changing fb/crtc
608 * configuration (modeswitching) and after page-flipping
609 * finishes. For the latter, we know that not only did
610 * we disable the FBC at the start of the page-flip
611 * sequence, but also more than one vblank has passed.
612 *
613 * For the former case of modeswitching, it is possible
614 * to switch between two FBC valid configurations
615 * instantaneously so we do need to disable the FBC
616 * before we can modify its control registers. We also
617 * have to wait for the next vblank for that to take
618 * effect. However, since we delay enabling FBC we can
619 * assume that a vblank has passed since disabling and
620 * that we can safely alter the registers in the deferred
621 * callback.
622 *
623 * In the scenario that we go from a valid to invalid
624 * and then back to valid FBC configuration we have
625 * no strict enforcement that a vblank occurred since
626 * disabling the FBC. However, along all current pipe
627 * disabling paths we do need to wait for a vblank at
628 * some point. And we wait before enabling FBC anyway.
629 */
630 DRM_DEBUG_KMS("disabling active FBC for update\n");
631 intel_disable_fbc(dev);
632 }
633
634 intel_enable_fbc(crtc);
635 dev_priv->fbc.no_fbc_reason = FBC_OK;
636 return;
637
638 out_disable:
639 /* Multiple disables should be harmless */
640 if (intel_fbc_enabled(dev)) {
641 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
642 intel_disable_fbc(dev);
643 }
644 i915_gem_stolen_cleanup_compression(dev);
645 }
646
647 static void i915_pineview_get_mem_freq(struct drm_device *dev)
648 {
649 struct drm_i915_private *dev_priv = dev->dev_private;
650 u32 tmp;
651
652 tmp = I915_READ(CLKCFG);
653
654 switch (tmp & CLKCFG_FSB_MASK) {
655 case CLKCFG_FSB_533:
656 dev_priv->fsb_freq = 533; /* 133*4 */
657 break;
658 case CLKCFG_FSB_800:
659 dev_priv->fsb_freq = 800; /* 200*4 */
660 break;
661 case CLKCFG_FSB_667:
662 dev_priv->fsb_freq = 667; /* 167*4 */
663 break;
664 case CLKCFG_FSB_400:
665 dev_priv->fsb_freq = 400; /* 100*4 */
666 break;
667 }
668
669 switch (tmp & CLKCFG_MEM_MASK) {
670 case CLKCFG_MEM_533:
671 dev_priv->mem_freq = 533;
672 break;
673 case CLKCFG_MEM_667:
674 dev_priv->mem_freq = 667;
675 break;
676 case CLKCFG_MEM_800:
677 dev_priv->mem_freq = 800;
678 break;
679 }
680
681 /* detect pineview DDR3 setting */
682 tmp = I915_READ(CSHRDDR3CTL);
683 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
684 }
685
686 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
687 {
688 struct drm_i915_private *dev_priv = dev->dev_private;
689 u16 ddrpll, csipll;
690
691 ddrpll = I915_READ16(DDRMPLL1);
692 csipll = I915_READ16(CSIPLL0);
693
694 switch (ddrpll & 0xff) {
695 case 0xc:
696 dev_priv->mem_freq = 800;
697 break;
698 case 0x10:
699 dev_priv->mem_freq = 1066;
700 break;
701 case 0x14:
702 dev_priv->mem_freq = 1333;
703 break;
704 case 0x18:
705 dev_priv->mem_freq = 1600;
706 break;
707 default:
708 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
709 ddrpll & 0xff);
710 dev_priv->mem_freq = 0;
711 break;
712 }
713
714 dev_priv->ips.r_t = dev_priv->mem_freq;
715
716 switch (csipll & 0x3ff) {
717 case 0x00c:
718 dev_priv->fsb_freq = 3200;
719 break;
720 case 0x00e:
721 dev_priv->fsb_freq = 3733;
722 break;
723 case 0x010:
724 dev_priv->fsb_freq = 4266;
725 break;
726 case 0x012:
727 dev_priv->fsb_freq = 4800;
728 break;
729 case 0x014:
730 dev_priv->fsb_freq = 5333;
731 break;
732 case 0x016:
733 dev_priv->fsb_freq = 5866;
734 break;
735 case 0x018:
736 dev_priv->fsb_freq = 6400;
737 break;
738 default:
739 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
740 csipll & 0x3ff);
741 dev_priv->fsb_freq = 0;
742 break;
743 }
744
745 if (dev_priv->fsb_freq == 3200) {
746 dev_priv->ips.c_m = 0;
747 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
748 dev_priv->ips.c_m = 1;
749 } else {
750 dev_priv->ips.c_m = 2;
751 }
752 }
753
754 static const struct cxsr_latency cxsr_latency_table[] = {
755 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
756 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
757 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
758 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
759 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
760
761 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
762 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
763 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
764 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
765 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
766
767 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
768 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
769 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
770 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
771 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
772
773 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
774 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
775 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
776 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
777 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
778
779 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
780 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
781 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
782 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
783 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
784
785 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
786 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
787 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
788 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
789 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
790 };
791
792 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
793 int is_ddr3,
794 int fsb,
795 int mem)
796 {
797 const struct cxsr_latency *latency;
798 int i;
799
800 if (fsb == 0 || mem == 0)
801 return NULL;
802
803 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
804 latency = &cxsr_latency_table[i];
805 if (is_desktop == latency->is_desktop &&
806 is_ddr3 == latency->is_ddr3 &&
807 fsb == latency->fsb_freq && mem == latency->mem_freq)
808 return latency;
809 }
810
811 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
812
813 return NULL;
814 }
815
816 void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
817 {
818 struct drm_device *dev = dev_priv->dev;
819 u32 val;
820
821 if (IS_VALLEYVIEW(dev)) {
822 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
823 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
824 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
825 } else if (IS_PINEVIEW(dev)) {
826 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
827 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
828 I915_WRITE(DSPFW3, val);
829 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
830 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
831 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
832 I915_WRITE(FW_BLC_SELF, val);
833 } else if (IS_I915GM(dev)) {
834 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
835 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
836 I915_WRITE(INSTPM, val);
837 } else {
838 return;
839 }
840
841 DRM_DEBUG_KMS("memory self-refresh is %s\n",
842 enable ? "enabled" : "disabled");
843 }
844
845 /*
846 * Latency for FIFO fetches is dependent on several factors:
847 * - memory configuration (speed, channels)
848 * - chipset
849 * - current MCH state
850 * It can be fairly high in some situations, so here we assume a fairly
851 * pessimal value. It's a tradeoff between extra memory fetches (if we
852 * set this value too high, the FIFO will fetch frequently to stay full)
853 * and power consumption (set it too low to save power and we might see
854 * FIFO underruns and display "flicker").
855 *
856 * A value of 5us seems to be a good balance; safe for very low end
857 * platforms but not overly aggressive on lower latency configs.
858 */
859 static const int latency_ns = 5000;
860
861 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
862 {
863 struct drm_i915_private *dev_priv = dev->dev_private;
864 uint32_t dsparb = I915_READ(DSPARB);
865 int size;
866
867 size = dsparb & 0x7f;
868 if (plane)
869 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
870
871 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
872 plane ? "B" : "A", size);
873
874 return size;
875 }
876
877 static int i830_get_fifo_size(struct drm_device *dev, int plane)
878 {
879 struct drm_i915_private *dev_priv = dev->dev_private;
880 uint32_t dsparb = I915_READ(DSPARB);
881 int size;
882
883 size = dsparb & 0x1ff;
884 if (plane)
885 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
886 size >>= 1; /* Convert to cachelines */
887
888 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
889 plane ? "B" : "A", size);
890
891 return size;
892 }
893
894 static int i845_get_fifo_size(struct drm_device *dev, int plane)
895 {
896 struct drm_i915_private *dev_priv = dev->dev_private;
897 uint32_t dsparb = I915_READ(DSPARB);
898 int size;
899
900 size = dsparb & 0x7f;
901 size >>= 2; /* Convert to cachelines */
902
903 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
904 plane ? "B" : "A",
905 size);
906
907 return size;
908 }
909
910 /* Pineview has different values for various configs */
911 static const struct intel_watermark_params pineview_display_wm = {
912 .fifo_size = PINEVIEW_DISPLAY_FIFO,
913 .max_wm = PINEVIEW_MAX_WM,
914 .default_wm = PINEVIEW_DFT_WM,
915 .guard_size = PINEVIEW_GUARD_WM,
916 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
917 };
918 static const struct intel_watermark_params pineview_display_hplloff_wm = {
919 .fifo_size = PINEVIEW_DISPLAY_FIFO,
920 .max_wm = PINEVIEW_MAX_WM,
921 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
922 .guard_size = PINEVIEW_GUARD_WM,
923 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
924 };
925 static const struct intel_watermark_params pineview_cursor_wm = {
926 .fifo_size = PINEVIEW_CURSOR_FIFO,
927 .max_wm = PINEVIEW_CURSOR_MAX_WM,
928 .default_wm = PINEVIEW_CURSOR_DFT_WM,
929 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
930 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
931 };
932 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
933 .fifo_size = PINEVIEW_CURSOR_FIFO,
934 .max_wm = PINEVIEW_CURSOR_MAX_WM,
935 .default_wm = PINEVIEW_CURSOR_DFT_WM,
936 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
937 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
938 };
939 static const struct intel_watermark_params g4x_wm_info = {
940 .fifo_size = G4X_FIFO_SIZE,
941 .max_wm = G4X_MAX_WM,
942 .default_wm = G4X_MAX_WM,
943 .guard_size = 2,
944 .cacheline_size = G4X_FIFO_LINE_SIZE,
945 };
946 static const struct intel_watermark_params g4x_cursor_wm_info = {
947 .fifo_size = I965_CURSOR_FIFO,
948 .max_wm = I965_CURSOR_MAX_WM,
949 .default_wm = I965_CURSOR_DFT_WM,
950 .guard_size = 2,
951 .cacheline_size = G4X_FIFO_LINE_SIZE,
952 };
953 static const struct intel_watermark_params valleyview_wm_info = {
954 .fifo_size = VALLEYVIEW_FIFO_SIZE,
955 .max_wm = VALLEYVIEW_MAX_WM,
956 .default_wm = VALLEYVIEW_MAX_WM,
957 .guard_size = 2,
958 .cacheline_size = G4X_FIFO_LINE_SIZE,
959 };
960 static const struct intel_watermark_params valleyview_cursor_wm_info = {
961 .fifo_size = I965_CURSOR_FIFO,
962 .max_wm = VALLEYVIEW_CURSOR_MAX_WM,
963 .default_wm = I965_CURSOR_DFT_WM,
964 .guard_size = 2,
965 .cacheline_size = G4X_FIFO_LINE_SIZE,
966 };
967 static const struct intel_watermark_params i965_cursor_wm_info = {
968 .fifo_size = I965_CURSOR_FIFO,
969 .max_wm = I965_CURSOR_MAX_WM,
970 .default_wm = I965_CURSOR_DFT_WM,
971 .guard_size = 2,
972 .cacheline_size = I915_FIFO_LINE_SIZE,
973 };
974 static const struct intel_watermark_params i945_wm_info = {
975 .fifo_size = I945_FIFO_SIZE,
976 .max_wm = I915_MAX_WM,
977 .default_wm = 1,
978 .guard_size = 2,
979 .cacheline_size = I915_FIFO_LINE_SIZE,
980 };
981 static const struct intel_watermark_params i915_wm_info = {
982 .fifo_size = I915_FIFO_SIZE,
983 .max_wm = I915_MAX_WM,
984 .default_wm = 1,
985 .guard_size = 2,
986 .cacheline_size = I915_FIFO_LINE_SIZE,
987 };
988 static const struct intel_watermark_params i830_wm_info = {
989 .fifo_size = I855GM_FIFO_SIZE,
990 .max_wm = I915_MAX_WM,
991 .default_wm = 1,
992 .guard_size = 2,
993 .cacheline_size = I830_FIFO_LINE_SIZE,
994 };
995 static const struct intel_watermark_params i845_wm_info = {
996 .fifo_size = I830_FIFO_SIZE,
997 .max_wm = I915_MAX_WM,
998 .default_wm = 1,
999 .guard_size = 2,
1000 .cacheline_size = I830_FIFO_LINE_SIZE,
1001 };
1002
1003 /**
1004 * intel_calculate_wm - calculate watermark level
1005 * @clock_in_khz: pixel clock
1006 * @wm: chip FIFO params
1007 * @pixel_size: display pixel size
1008 * @latency_ns: memory latency for the platform
1009 *
1010 * Calculate the watermark level (the level at which the display plane will
1011 * start fetching from memory again). Each chip has a different display
1012 * FIFO size and allocation, so the caller needs to figure that out and pass
1013 * in the correct intel_watermark_params structure.
1014 *
1015 * As the pixel clock runs, the FIFO will be drained at a rate that depends
1016 * on the pixel size. When it reaches the watermark level, it'll start
1017 * fetching FIFO line sized based chunks from memory until the FIFO fills
1018 * past the watermark point. If the FIFO drains completely, a FIFO underrun
1019 * will occur, and a display engine hang could result.
1020 */
1021 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
1022 const struct intel_watermark_params *wm,
1023 int fifo_size,
1024 int pixel_size,
1025 unsigned long latency_ns)
1026 {
1027 long entries_required, wm_size;
1028
1029 /*
1030 * Note: we need to make sure we don't overflow for various clock &
1031 * latency values.
1032 * clocks go from a few thousand to several hundred thousand.
1033 * latency is usually a few thousand
1034 */
1035 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
1036 1000;
1037 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
1038
1039 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
1040
1041 wm_size = fifo_size - (entries_required + wm->guard_size);
1042
1043 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
1044
1045 /* Don't promote wm_size to unsigned... */
1046 if (wm_size > (long)wm->max_wm)
1047 wm_size = wm->max_wm;
1048 if (wm_size <= 0)
1049 wm_size = wm->default_wm;
1050 return wm_size;
1051 }
1052
1053 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1054 {
1055 struct drm_crtc *crtc, *enabled = NULL;
1056
1057 for_each_crtc(dev, crtc) {
1058 if (intel_crtc_active(crtc)) {
1059 if (enabled)
1060 return NULL;
1061 enabled = crtc;
1062 }
1063 }
1064
1065 return enabled;
1066 }
1067
1068 static void pineview_update_wm(struct drm_crtc *unused_crtc)
1069 {
1070 struct drm_device *dev = unused_crtc->dev;
1071 struct drm_i915_private *dev_priv = dev->dev_private;
1072 struct drm_crtc *crtc;
1073 const struct cxsr_latency *latency;
1074 u32 reg;
1075 unsigned long wm;
1076
1077 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1078 dev_priv->fsb_freq, dev_priv->mem_freq);
1079 if (!latency) {
1080 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1081 intel_set_memory_cxsr(dev_priv, false);
1082 return;
1083 }
1084
1085 crtc = single_enabled_crtc(dev);
1086 if (crtc) {
1087 const struct drm_display_mode *adjusted_mode;
1088 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1089 int clock;
1090
1091 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1092 clock = adjusted_mode->crtc_clock;
1093
1094 /* Display SR */
1095 wm = intel_calculate_wm(clock, &pineview_display_wm,
1096 pineview_display_wm.fifo_size,
1097 pixel_size, latency->display_sr);
1098 reg = I915_READ(DSPFW1);
1099 reg &= ~DSPFW_SR_MASK;
1100 reg |= wm << DSPFW_SR_SHIFT;
1101 I915_WRITE(DSPFW1, reg);
1102 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1103
1104 /* cursor SR */
1105 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1106 pineview_display_wm.fifo_size,
1107 pixel_size, latency->cursor_sr);
1108 reg = I915_READ(DSPFW3);
1109 reg &= ~DSPFW_CURSOR_SR_MASK;
1110 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1111 I915_WRITE(DSPFW3, reg);
1112
1113 /* Display HPLL off SR */
1114 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1115 pineview_display_hplloff_wm.fifo_size,
1116 pixel_size, latency->display_hpll_disable);
1117 reg = I915_READ(DSPFW3);
1118 reg &= ~DSPFW_HPLL_SR_MASK;
1119 reg |= wm & DSPFW_HPLL_SR_MASK;
1120 I915_WRITE(DSPFW3, reg);
1121
1122 /* cursor HPLL off SR */
1123 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1124 pineview_display_hplloff_wm.fifo_size,
1125 pixel_size, latency->cursor_hpll_disable);
1126 reg = I915_READ(DSPFW3);
1127 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1128 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1129 I915_WRITE(DSPFW3, reg);
1130 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1131
1132 intel_set_memory_cxsr(dev_priv, true);
1133 } else {
1134 intel_set_memory_cxsr(dev_priv, false);
1135 }
1136 }
1137
1138 static bool g4x_compute_wm0(struct drm_device *dev,
1139 int plane,
1140 const struct intel_watermark_params *display,
1141 int display_latency_ns,
1142 const struct intel_watermark_params *cursor,
1143 int cursor_latency_ns,
1144 int *plane_wm,
1145 int *cursor_wm)
1146 {
1147 struct drm_crtc *crtc;
1148 const struct drm_display_mode *adjusted_mode;
1149 int htotal, hdisplay, clock, pixel_size;
1150 int line_time_us, line_count;
1151 int entries, tlb_miss;
1152
1153 crtc = intel_get_crtc_for_plane(dev, plane);
1154 if (!intel_crtc_active(crtc)) {
1155 *cursor_wm = cursor->guard_size;
1156 *plane_wm = display->guard_size;
1157 return false;
1158 }
1159
1160 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1161 clock = adjusted_mode->crtc_clock;
1162 htotal = adjusted_mode->crtc_htotal;
1163 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1164 pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1165
1166 /* Use the small buffer method to calculate plane watermark */
1167 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1168 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1169 if (tlb_miss > 0)
1170 entries += tlb_miss;
1171 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1172 *plane_wm = entries + display->guard_size;
1173 if (*plane_wm > (int)display->max_wm)
1174 *plane_wm = display->max_wm;
1175
1176 /* Use the large buffer method to calculate cursor watermark */
1177 line_time_us = max(htotal * 1000 / clock, 1);
1178 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1179 entries = line_count * to_intel_crtc(crtc)->cursor_width * pixel_size;
1180 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1181 if (tlb_miss > 0)
1182 entries += tlb_miss;
1183 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1184 *cursor_wm = entries + cursor->guard_size;
1185 if (*cursor_wm > (int)cursor->max_wm)
1186 *cursor_wm = (int)cursor->max_wm;
1187
1188 return true;
1189 }
1190
1191 /*
1192 * Check the wm result.
1193 *
1194 * If any calculated watermark values is larger than the maximum value that
1195 * can be programmed into the associated watermark register, that watermark
1196 * must be disabled.
1197 */
1198 static bool g4x_check_srwm(struct drm_device *dev,
1199 int display_wm, int cursor_wm,
1200 const struct intel_watermark_params *display,
1201 const struct intel_watermark_params *cursor)
1202 {
1203 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1204 display_wm, cursor_wm);
1205
1206 if (display_wm > display->max_wm) {
1207 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1208 display_wm, display->max_wm);
1209 return false;
1210 }
1211
1212 if (cursor_wm > cursor->max_wm) {
1213 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1214 cursor_wm, cursor->max_wm);
1215 return false;
1216 }
1217
1218 if (!(display_wm || cursor_wm)) {
1219 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1220 return false;
1221 }
1222
1223 return true;
1224 }
1225
1226 static bool g4x_compute_srwm(struct drm_device *dev,
1227 int plane,
1228 int latency_ns,
1229 const struct intel_watermark_params *display,
1230 const struct intel_watermark_params *cursor,
1231 int *display_wm, int *cursor_wm)
1232 {
1233 struct drm_crtc *crtc;
1234 const struct drm_display_mode *adjusted_mode;
1235 int hdisplay, htotal, pixel_size, clock;
1236 unsigned long line_time_us;
1237 int line_count, line_size;
1238 int small, large;
1239 int entries;
1240
1241 if (!latency_ns) {
1242 *display_wm = *cursor_wm = 0;
1243 return false;
1244 }
1245
1246 crtc = intel_get_crtc_for_plane(dev, plane);
1247 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1248 clock = adjusted_mode->crtc_clock;
1249 htotal = adjusted_mode->crtc_htotal;
1250 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1251 pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1252
1253 line_time_us = max(htotal * 1000 / clock, 1);
1254 line_count = (latency_ns / line_time_us + 1000) / 1000;
1255 line_size = hdisplay * pixel_size;
1256
1257 /* Use the minimum of the small and large buffer method for primary */
1258 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1259 large = line_count * line_size;
1260
1261 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1262 *display_wm = entries + display->guard_size;
1263
1264 /* calculate the self-refresh watermark for display cursor */
1265 entries = line_count * pixel_size * to_intel_crtc(crtc)->cursor_width;
1266 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1267 *cursor_wm = entries + cursor->guard_size;
1268
1269 return g4x_check_srwm(dev,
1270 *display_wm, *cursor_wm,
1271 display, cursor);
1272 }
1273
1274 static bool vlv_compute_drain_latency(struct drm_crtc *crtc,
1275 int pixel_size,
1276 int *prec_mult,
1277 int *drain_latency)
1278 {
1279 int entries;
1280 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
1281
1282 if (WARN(clock == 0, "Pixel clock is zero!\n"))
1283 return false;
1284
1285 if (WARN(pixel_size == 0, "Pixel size is zero!\n"))
1286 return false;
1287
1288 entries = DIV_ROUND_UP(clock, 1000) * pixel_size;
1289 *prec_mult = (entries > 128) ? DRAIN_LATENCY_PRECISION_64 :
1290 DRAIN_LATENCY_PRECISION_32;
1291 *drain_latency = (64 * (*prec_mult) * 4) / entries;
1292
1293 if (*drain_latency > DRAIN_LATENCY_MASK)
1294 *drain_latency = DRAIN_LATENCY_MASK;
1295
1296 return true;
1297 }
1298
1299 /*
1300 * Update drain latency registers of memory arbiter
1301 *
1302 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1303 * to be programmed. Each plane has a drain latency multiplier and a drain
1304 * latency value.
1305 */
1306
1307 static void vlv_update_drain_latency(struct drm_crtc *crtc)
1308 {
1309 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1310 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1311 int pixel_size;
1312 int drain_latency;
1313 enum pipe pipe = intel_crtc->pipe;
1314 int plane_prec, prec_mult, plane_dl;
1315
1316 plane_dl = I915_READ(VLV_DDL(pipe)) & ~(DDL_PLANE_PRECISION_64 |
1317 DRAIN_LATENCY_MASK | DDL_CURSOR_PRECISION_64 |
1318 (DRAIN_LATENCY_MASK << DDL_CURSOR_SHIFT));
1319
1320 if (!intel_crtc_active(crtc)) {
1321 I915_WRITE(VLV_DDL(pipe), plane_dl);
1322 return;
1323 }
1324
1325 /* Primary plane Drain Latency */
1326 pixel_size = crtc->primary->fb->bits_per_pixel / 8; /* BPP */
1327 if (vlv_compute_drain_latency(crtc, pixel_size, &prec_mult, &drain_latency)) {
1328 plane_prec = (prec_mult == DRAIN_LATENCY_PRECISION_64) ?
1329 DDL_PLANE_PRECISION_64 :
1330 DDL_PLANE_PRECISION_32;
1331 plane_dl |= plane_prec | drain_latency;
1332 }
1333
1334 /* Cursor Drain Latency
1335 * BPP is always 4 for cursor
1336 */
1337 pixel_size = 4;
1338
1339 /* Program cursor DL only if it is enabled */
1340 if (intel_crtc->cursor_base &&
1341 vlv_compute_drain_latency(crtc, pixel_size, &prec_mult, &drain_latency)) {
1342 plane_prec = (prec_mult == DRAIN_LATENCY_PRECISION_64) ?
1343 DDL_CURSOR_PRECISION_64 :
1344 DDL_CURSOR_PRECISION_32;
1345 plane_dl |= plane_prec | (drain_latency << DDL_CURSOR_SHIFT);
1346 }
1347
1348 I915_WRITE(VLV_DDL(pipe), plane_dl);
1349 }
1350
1351 #define single_plane_enabled(mask) is_power_of_2(mask)
1352
1353 static void valleyview_update_wm(struct drm_crtc *crtc)
1354 {
1355 struct drm_device *dev = crtc->dev;
1356 static const int sr_latency_ns = 12000;
1357 struct drm_i915_private *dev_priv = dev->dev_private;
1358 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1359 int plane_sr, cursor_sr;
1360 int ignore_plane_sr, ignore_cursor_sr;
1361 unsigned int enabled = 0;
1362 bool cxsr_enabled;
1363
1364 vlv_update_drain_latency(crtc);
1365
1366 if (g4x_compute_wm0(dev, PIPE_A,
1367 &valleyview_wm_info, latency_ns,
1368 &valleyview_cursor_wm_info, latency_ns,
1369 &planea_wm, &cursora_wm))
1370 enabled |= 1 << PIPE_A;
1371
1372 if (g4x_compute_wm0(dev, PIPE_B,
1373 &valleyview_wm_info, latency_ns,
1374 &valleyview_cursor_wm_info, latency_ns,
1375 &planeb_wm, &cursorb_wm))
1376 enabled |= 1 << PIPE_B;
1377
1378 if (single_plane_enabled(enabled) &&
1379 g4x_compute_srwm(dev, ffs(enabled) - 1,
1380 sr_latency_ns,
1381 &valleyview_wm_info,
1382 &valleyview_cursor_wm_info,
1383 &plane_sr, &ignore_cursor_sr) &&
1384 g4x_compute_srwm(dev, ffs(enabled) - 1,
1385 2*sr_latency_ns,
1386 &valleyview_wm_info,
1387 &valleyview_cursor_wm_info,
1388 &ignore_plane_sr, &cursor_sr)) {
1389 cxsr_enabled = true;
1390 } else {
1391 cxsr_enabled = false;
1392 intel_set_memory_cxsr(dev_priv, false);
1393 plane_sr = cursor_sr = 0;
1394 }
1395
1396 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1397 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1398 planea_wm, cursora_wm,
1399 planeb_wm, cursorb_wm,
1400 plane_sr, cursor_sr);
1401
1402 I915_WRITE(DSPFW1,
1403 (plane_sr << DSPFW_SR_SHIFT) |
1404 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1405 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1406 (planea_wm << DSPFW_PLANEA_SHIFT));
1407 I915_WRITE(DSPFW2,
1408 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1409 (cursora_wm << DSPFW_CURSORA_SHIFT));
1410 I915_WRITE(DSPFW3,
1411 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1412 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1413
1414 if (cxsr_enabled)
1415 intel_set_memory_cxsr(dev_priv, true);
1416 }
1417
1418 static void cherryview_update_wm(struct drm_crtc *crtc)
1419 {
1420 struct drm_device *dev = crtc->dev;
1421 static const int sr_latency_ns = 12000;
1422 struct drm_i915_private *dev_priv = dev->dev_private;
1423 int planea_wm, planeb_wm, planec_wm;
1424 int cursora_wm, cursorb_wm, cursorc_wm;
1425 int plane_sr, cursor_sr;
1426 int ignore_plane_sr, ignore_cursor_sr;
1427 unsigned int enabled = 0;
1428 bool cxsr_enabled;
1429
1430 vlv_update_drain_latency(crtc);
1431
1432 if (g4x_compute_wm0(dev, PIPE_A,
1433 &valleyview_wm_info, latency_ns,
1434 &valleyview_cursor_wm_info, latency_ns,
1435 &planea_wm, &cursora_wm))
1436 enabled |= 1 << PIPE_A;
1437
1438 if (g4x_compute_wm0(dev, PIPE_B,
1439 &valleyview_wm_info, latency_ns,
1440 &valleyview_cursor_wm_info, latency_ns,
1441 &planeb_wm, &cursorb_wm))
1442 enabled |= 1 << PIPE_B;
1443
1444 if (g4x_compute_wm0(dev, PIPE_C,
1445 &valleyview_wm_info, latency_ns,
1446 &valleyview_cursor_wm_info, latency_ns,
1447 &planec_wm, &cursorc_wm))
1448 enabled |= 1 << PIPE_C;
1449
1450 if (single_plane_enabled(enabled) &&
1451 g4x_compute_srwm(dev, ffs(enabled) - 1,
1452 sr_latency_ns,
1453 &valleyview_wm_info,
1454 &valleyview_cursor_wm_info,
1455 &plane_sr, &ignore_cursor_sr) &&
1456 g4x_compute_srwm(dev, ffs(enabled) - 1,
1457 2*sr_latency_ns,
1458 &valleyview_wm_info,
1459 &valleyview_cursor_wm_info,
1460 &ignore_plane_sr, &cursor_sr)) {
1461 cxsr_enabled = true;
1462 } else {
1463 cxsr_enabled = false;
1464 intel_set_memory_cxsr(dev_priv, false);
1465 plane_sr = cursor_sr = 0;
1466 }
1467
1468 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1469 "B: plane=%d, cursor=%d, C: plane=%d, cursor=%d, "
1470 "SR: plane=%d, cursor=%d\n",
1471 planea_wm, cursora_wm,
1472 planeb_wm, cursorb_wm,
1473 planec_wm, cursorc_wm,
1474 plane_sr, cursor_sr);
1475
1476 I915_WRITE(DSPFW1,
1477 (plane_sr << DSPFW_SR_SHIFT) |
1478 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1479 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1480 (planea_wm << DSPFW_PLANEA_SHIFT));
1481 I915_WRITE(DSPFW2,
1482 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1483 (cursora_wm << DSPFW_CURSORA_SHIFT));
1484 I915_WRITE(DSPFW3,
1485 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1486 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1487 I915_WRITE(DSPFW9_CHV,
1488 (I915_READ(DSPFW9_CHV) & ~(DSPFW_PLANEC_MASK |
1489 DSPFW_CURSORC_MASK)) |
1490 (planec_wm << DSPFW_PLANEC_SHIFT) |
1491 (cursorc_wm << DSPFW_CURSORC_SHIFT));
1492
1493 if (cxsr_enabled)
1494 intel_set_memory_cxsr(dev_priv, true);
1495 }
1496
1497 static void valleyview_update_sprite_wm(struct drm_plane *plane,
1498 struct drm_crtc *crtc,
1499 uint32_t sprite_width,
1500 uint32_t sprite_height,
1501 int pixel_size,
1502 bool enabled, bool scaled)
1503 {
1504 struct drm_device *dev = crtc->dev;
1505 struct drm_i915_private *dev_priv = dev->dev_private;
1506 int pipe = to_intel_plane(plane)->pipe;
1507 int sprite = to_intel_plane(plane)->plane;
1508 int drain_latency;
1509 int plane_prec;
1510 int sprite_dl;
1511 int prec_mult;
1512
1513 sprite_dl = I915_READ(VLV_DDL(pipe)) & ~(DDL_SPRITE_PRECISION_64(sprite) |
1514 (DRAIN_LATENCY_MASK << DDL_SPRITE_SHIFT(sprite)));
1515
1516 if (enabled && vlv_compute_drain_latency(crtc, pixel_size, &prec_mult,
1517 &drain_latency)) {
1518 plane_prec = (prec_mult == DRAIN_LATENCY_PRECISION_64) ?
1519 DDL_SPRITE_PRECISION_64(sprite) :
1520 DDL_SPRITE_PRECISION_32(sprite);
1521 sprite_dl |= plane_prec |
1522 (drain_latency << DDL_SPRITE_SHIFT(sprite));
1523 }
1524
1525 I915_WRITE(VLV_DDL(pipe), sprite_dl);
1526 }
1527
1528 static void g4x_update_wm(struct drm_crtc *crtc)
1529 {
1530 struct drm_device *dev = crtc->dev;
1531 static const int sr_latency_ns = 12000;
1532 struct drm_i915_private *dev_priv = dev->dev_private;
1533 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1534 int plane_sr, cursor_sr;
1535 unsigned int enabled = 0;
1536 bool cxsr_enabled;
1537
1538 if (g4x_compute_wm0(dev, PIPE_A,
1539 &g4x_wm_info, latency_ns,
1540 &g4x_cursor_wm_info, latency_ns,
1541 &planea_wm, &cursora_wm))
1542 enabled |= 1 << PIPE_A;
1543
1544 if (g4x_compute_wm0(dev, PIPE_B,
1545 &g4x_wm_info, latency_ns,
1546 &g4x_cursor_wm_info, latency_ns,
1547 &planeb_wm, &cursorb_wm))
1548 enabled |= 1 << PIPE_B;
1549
1550 if (single_plane_enabled(enabled) &&
1551 g4x_compute_srwm(dev, ffs(enabled) - 1,
1552 sr_latency_ns,
1553 &g4x_wm_info,
1554 &g4x_cursor_wm_info,
1555 &plane_sr, &cursor_sr)) {
1556 cxsr_enabled = true;
1557 } else {
1558 cxsr_enabled = false;
1559 intel_set_memory_cxsr(dev_priv, false);
1560 plane_sr = cursor_sr = 0;
1561 }
1562
1563 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1564 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1565 planea_wm, cursora_wm,
1566 planeb_wm, cursorb_wm,
1567 plane_sr, cursor_sr);
1568
1569 I915_WRITE(DSPFW1,
1570 (plane_sr << DSPFW_SR_SHIFT) |
1571 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1572 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1573 (planea_wm << DSPFW_PLANEA_SHIFT));
1574 I915_WRITE(DSPFW2,
1575 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1576 (cursora_wm << DSPFW_CURSORA_SHIFT));
1577 /* HPLL off in SR has some issues on G4x... disable it */
1578 I915_WRITE(DSPFW3,
1579 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1580 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1581
1582 if (cxsr_enabled)
1583 intel_set_memory_cxsr(dev_priv, true);
1584 }
1585
1586 static void i965_update_wm(struct drm_crtc *unused_crtc)
1587 {
1588 struct drm_device *dev = unused_crtc->dev;
1589 struct drm_i915_private *dev_priv = dev->dev_private;
1590 struct drm_crtc *crtc;
1591 int srwm = 1;
1592 int cursor_sr = 16;
1593 bool cxsr_enabled;
1594
1595 /* Calc sr entries for one plane configs */
1596 crtc = single_enabled_crtc(dev);
1597 if (crtc) {
1598 /* self-refresh has much higher latency */
1599 static const int sr_latency_ns = 12000;
1600 const struct drm_display_mode *adjusted_mode =
1601 &to_intel_crtc(crtc)->config.adjusted_mode;
1602 int clock = adjusted_mode->crtc_clock;
1603 int htotal = adjusted_mode->crtc_htotal;
1604 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1605 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1606 unsigned long line_time_us;
1607 int entries;
1608
1609 line_time_us = max(htotal * 1000 / clock, 1);
1610
1611 /* Use ns/us then divide to preserve precision */
1612 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1613 pixel_size * hdisplay;
1614 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1615 srwm = I965_FIFO_SIZE - entries;
1616 if (srwm < 0)
1617 srwm = 1;
1618 srwm &= 0x1ff;
1619 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1620 entries, srwm);
1621
1622 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1623 pixel_size * to_intel_crtc(crtc)->cursor_width;
1624 entries = DIV_ROUND_UP(entries,
1625 i965_cursor_wm_info.cacheline_size);
1626 cursor_sr = i965_cursor_wm_info.fifo_size -
1627 (entries + i965_cursor_wm_info.guard_size);
1628
1629 if (cursor_sr > i965_cursor_wm_info.max_wm)
1630 cursor_sr = i965_cursor_wm_info.max_wm;
1631
1632 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1633 "cursor %d\n", srwm, cursor_sr);
1634
1635 cxsr_enabled = true;
1636 } else {
1637 cxsr_enabled = false;
1638 /* Turn off self refresh if both pipes are enabled */
1639 intel_set_memory_cxsr(dev_priv, false);
1640 }
1641
1642 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1643 srwm);
1644
1645 /* 965 has limitations... */
1646 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1647 (8 << DSPFW_CURSORB_SHIFT) |
1648 (8 << DSPFW_PLANEB_SHIFT) |
1649 (8 << DSPFW_PLANEA_SHIFT));
1650 I915_WRITE(DSPFW2, (8 << DSPFW_CURSORA_SHIFT) |
1651 (8 << DSPFW_PLANEC_SHIFT_OLD));
1652 /* update cursor SR watermark */
1653 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1654
1655 if (cxsr_enabled)
1656 intel_set_memory_cxsr(dev_priv, true);
1657 }
1658
1659 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1660 {
1661 struct drm_device *dev = unused_crtc->dev;
1662 struct drm_i915_private *dev_priv = dev->dev_private;
1663 const struct intel_watermark_params *wm_info;
1664 uint32_t fwater_lo;
1665 uint32_t fwater_hi;
1666 int cwm, srwm = 1;
1667 int fifo_size;
1668 int planea_wm, planeb_wm;
1669 struct drm_crtc *crtc, *enabled = NULL;
1670
1671 if (IS_I945GM(dev))
1672 wm_info = &i945_wm_info;
1673 else if (!IS_GEN2(dev))
1674 wm_info = &i915_wm_info;
1675 else
1676 wm_info = &i830_wm_info;
1677
1678 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1679 crtc = intel_get_crtc_for_plane(dev, 0);
1680 if (intel_crtc_active(crtc)) {
1681 const struct drm_display_mode *adjusted_mode;
1682 int cpp = crtc->primary->fb->bits_per_pixel / 8;
1683 if (IS_GEN2(dev))
1684 cpp = 4;
1685
1686 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1687 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1688 wm_info, fifo_size, cpp,
1689 latency_ns);
1690 enabled = crtc;
1691 } else
1692 planea_wm = fifo_size - wm_info->guard_size;
1693
1694 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1695 crtc = intel_get_crtc_for_plane(dev, 1);
1696 if (intel_crtc_active(crtc)) {
1697 const struct drm_display_mode *adjusted_mode;
1698 int cpp = crtc->primary->fb->bits_per_pixel / 8;
1699 if (IS_GEN2(dev))
1700 cpp = 4;
1701
1702 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1703 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1704 wm_info, fifo_size, cpp,
1705 latency_ns);
1706 if (enabled == NULL)
1707 enabled = crtc;
1708 else
1709 enabled = NULL;
1710 } else
1711 planeb_wm = fifo_size - wm_info->guard_size;
1712
1713 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1714
1715 if (IS_I915GM(dev) && enabled) {
1716 struct drm_i915_gem_object *obj;
1717
1718 obj = intel_fb_obj(enabled->primary->fb);
1719
1720 /* self-refresh seems busted with untiled */
1721 if (obj->tiling_mode == I915_TILING_NONE)
1722 enabled = NULL;
1723 }
1724
1725 /*
1726 * Overlay gets an aggressive default since video jitter is bad.
1727 */
1728 cwm = 2;
1729
1730 /* Play safe and disable self-refresh before adjusting watermarks. */
1731 intel_set_memory_cxsr(dev_priv, false);
1732
1733 /* Calc sr entries for one plane configs */
1734 if (HAS_FW_BLC(dev) && enabled) {
1735 /* self-refresh has much higher latency */
1736 static const int sr_latency_ns = 6000;
1737 const struct drm_display_mode *adjusted_mode =
1738 &to_intel_crtc(enabled)->config.adjusted_mode;
1739 int clock = adjusted_mode->crtc_clock;
1740 int htotal = adjusted_mode->crtc_htotal;
1741 int hdisplay = to_intel_crtc(enabled)->config.pipe_src_w;
1742 int pixel_size = enabled->primary->fb->bits_per_pixel / 8;
1743 unsigned long line_time_us;
1744 int entries;
1745
1746 line_time_us = max(htotal * 1000 / clock, 1);
1747
1748 /* Use ns/us then divide to preserve precision */
1749 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1750 pixel_size * hdisplay;
1751 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1752 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1753 srwm = wm_info->fifo_size - entries;
1754 if (srwm < 0)
1755 srwm = 1;
1756
1757 if (IS_I945G(dev) || IS_I945GM(dev))
1758 I915_WRITE(FW_BLC_SELF,
1759 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1760 else if (IS_I915GM(dev))
1761 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1762 }
1763
1764 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1765 planea_wm, planeb_wm, cwm, srwm);
1766
1767 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1768 fwater_hi = (cwm & 0x1f);
1769
1770 /* Set request length to 8 cachelines per fetch */
1771 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1772 fwater_hi = fwater_hi | (1 << 8);
1773
1774 I915_WRITE(FW_BLC, fwater_lo);
1775 I915_WRITE(FW_BLC2, fwater_hi);
1776
1777 if (enabled)
1778 intel_set_memory_cxsr(dev_priv, true);
1779 }
1780
1781 static void i845_update_wm(struct drm_crtc *unused_crtc)
1782 {
1783 struct drm_device *dev = unused_crtc->dev;
1784 struct drm_i915_private *dev_priv = dev->dev_private;
1785 struct drm_crtc *crtc;
1786 const struct drm_display_mode *adjusted_mode;
1787 uint32_t fwater_lo;
1788 int planea_wm;
1789
1790 crtc = single_enabled_crtc(dev);
1791 if (crtc == NULL)
1792 return;
1793
1794 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1795 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1796 &i845_wm_info,
1797 dev_priv->display.get_fifo_size(dev, 0),
1798 4, latency_ns);
1799 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1800 fwater_lo |= (3<<8) | planea_wm;
1801
1802 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1803
1804 I915_WRITE(FW_BLC, fwater_lo);
1805 }
1806
1807 static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
1808 struct drm_crtc *crtc)
1809 {
1810 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1811 uint32_t pixel_rate;
1812
1813 pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock;
1814
1815 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1816 * adjust the pixel_rate here. */
1817
1818 if (intel_crtc->config.pch_pfit.enabled) {
1819 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1820 uint32_t pfit_size = intel_crtc->config.pch_pfit.size;
1821
1822 pipe_w = intel_crtc->config.pipe_src_w;
1823 pipe_h = intel_crtc->config.pipe_src_h;
1824 pfit_w = (pfit_size >> 16) & 0xFFFF;
1825 pfit_h = pfit_size & 0xFFFF;
1826 if (pipe_w < pfit_w)
1827 pipe_w = pfit_w;
1828 if (pipe_h < pfit_h)
1829 pipe_h = pfit_h;
1830
1831 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1832 pfit_w * pfit_h);
1833 }
1834
1835 return pixel_rate;
1836 }
1837
1838 /* latency must be in 0.1us units. */
1839 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
1840 uint32_t latency)
1841 {
1842 uint64_t ret;
1843
1844 if (WARN(latency == 0, "Latency value missing\n"))
1845 return UINT_MAX;
1846
1847 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1848 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1849
1850 return ret;
1851 }
1852
1853 /* latency must be in 0.1us units. */
1854 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1855 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1856 uint32_t latency)
1857 {
1858 uint32_t ret;
1859
1860 if (WARN(latency == 0, "Latency value missing\n"))
1861 return UINT_MAX;
1862
1863 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1864 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1865 ret = DIV_ROUND_UP(ret, 64) + 2;
1866 return ret;
1867 }
1868
1869 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1870 uint8_t bytes_per_pixel)
1871 {
1872 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1873 }
1874
1875 struct ilk_pipe_wm_parameters {
1876 bool active;
1877 uint32_t pipe_htotal;
1878 uint32_t pixel_rate;
1879 struct intel_plane_wm_parameters pri;
1880 struct intel_plane_wm_parameters spr;
1881 struct intel_plane_wm_parameters cur;
1882 };
1883
1884 struct ilk_wm_maximums {
1885 uint16_t pri;
1886 uint16_t spr;
1887 uint16_t cur;
1888 uint16_t fbc;
1889 };
1890
1891 /* used in computing the new watermarks state */
1892 struct intel_wm_config {
1893 unsigned int num_pipes_active;
1894 bool sprites_enabled;
1895 bool sprites_scaled;
1896 };
1897
1898 /*
1899 * For both WM_PIPE and WM_LP.
1900 * mem_value must be in 0.1us units.
1901 */
1902 static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params,
1903 uint32_t mem_value,
1904 bool is_lp)
1905 {
1906 uint32_t method1, method2;
1907
1908 if (!params->active || !params->pri.enabled)
1909 return 0;
1910
1911 method1 = ilk_wm_method1(params->pixel_rate,
1912 params->pri.bytes_per_pixel,
1913 mem_value);
1914
1915 if (!is_lp)
1916 return method1;
1917
1918 method2 = ilk_wm_method2(params->pixel_rate,
1919 params->pipe_htotal,
1920 params->pri.horiz_pixels,
1921 params->pri.bytes_per_pixel,
1922 mem_value);
1923
1924 return min(method1, method2);
1925 }
1926
1927 /*
1928 * For both WM_PIPE and WM_LP.
1929 * mem_value must be in 0.1us units.
1930 */
1931 static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params,
1932 uint32_t mem_value)
1933 {
1934 uint32_t method1, method2;
1935
1936 if (!params->active || !params->spr.enabled)
1937 return 0;
1938
1939 method1 = ilk_wm_method1(params->pixel_rate,
1940 params->spr.bytes_per_pixel,
1941 mem_value);
1942 method2 = ilk_wm_method2(params->pixel_rate,
1943 params->pipe_htotal,
1944 params->spr.horiz_pixels,
1945 params->spr.bytes_per_pixel,
1946 mem_value);
1947 return min(method1, method2);
1948 }
1949
1950 /*
1951 * For both WM_PIPE and WM_LP.
1952 * mem_value must be in 0.1us units.
1953 */
1954 static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params,
1955 uint32_t mem_value)
1956 {
1957 if (!params->active || !params->cur.enabled)
1958 return 0;
1959
1960 return ilk_wm_method2(params->pixel_rate,
1961 params->pipe_htotal,
1962 params->cur.horiz_pixels,
1963 params->cur.bytes_per_pixel,
1964 mem_value);
1965 }
1966
1967 /* Only for WM_LP. */
1968 static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params,
1969 uint32_t pri_val)
1970 {
1971 if (!params->active || !params->pri.enabled)
1972 return 0;
1973
1974 return ilk_wm_fbc(pri_val,
1975 params->pri.horiz_pixels,
1976 params->pri.bytes_per_pixel);
1977 }
1978
1979 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1980 {
1981 if (INTEL_INFO(dev)->gen >= 8)
1982 return 3072;
1983 else if (INTEL_INFO(dev)->gen >= 7)
1984 return 768;
1985 else
1986 return 512;
1987 }
1988
1989 static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1990 int level, bool is_sprite)
1991 {
1992 if (INTEL_INFO(dev)->gen >= 8)
1993 /* BDW primary/sprite plane watermarks */
1994 return level == 0 ? 255 : 2047;
1995 else if (INTEL_INFO(dev)->gen >= 7)
1996 /* IVB/HSW primary/sprite plane watermarks */
1997 return level == 0 ? 127 : 1023;
1998 else if (!is_sprite)
1999 /* ILK/SNB primary plane watermarks */
2000 return level == 0 ? 127 : 511;
2001 else
2002 /* ILK/SNB sprite plane watermarks */
2003 return level == 0 ? 63 : 255;
2004 }
2005
2006 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
2007 int level)
2008 {
2009 if (INTEL_INFO(dev)->gen >= 7)
2010 return level == 0 ? 63 : 255;
2011 else
2012 return level == 0 ? 31 : 63;
2013 }
2014
2015 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
2016 {
2017 if (INTEL_INFO(dev)->gen >= 8)
2018 return 31;
2019 else
2020 return 15;
2021 }
2022
2023 /* Calculate the maximum primary/sprite plane watermark */
2024 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
2025 int level,
2026 const struct intel_wm_config *config,
2027 enum intel_ddb_partitioning ddb_partitioning,
2028 bool is_sprite)
2029 {
2030 unsigned int fifo_size = ilk_display_fifo_size(dev);
2031
2032 /* if sprites aren't enabled, sprites get nothing */
2033 if (is_sprite && !config->sprites_enabled)
2034 return 0;
2035
2036 /* HSW allows LP1+ watermarks even with multiple pipes */
2037 if (level == 0 || config->num_pipes_active > 1) {
2038 fifo_size /= INTEL_INFO(dev)->num_pipes;
2039
2040 /*
2041 * For some reason the non self refresh
2042 * FIFO size is only half of the self
2043 * refresh FIFO size on ILK/SNB.
2044 */
2045 if (INTEL_INFO(dev)->gen <= 6)
2046 fifo_size /= 2;
2047 }
2048
2049 if (config->sprites_enabled) {
2050 /* level 0 is always calculated with 1:1 split */
2051 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
2052 if (is_sprite)
2053 fifo_size *= 5;
2054 fifo_size /= 6;
2055 } else {
2056 fifo_size /= 2;
2057 }
2058 }
2059
2060 /* clamp to max that the registers can hold */
2061 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
2062 }
2063
2064 /* Calculate the maximum cursor plane watermark */
2065 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
2066 int level,
2067 const struct intel_wm_config *config)
2068 {
2069 /* HSW LP1+ watermarks w/ multiple pipes */
2070 if (level > 0 && config->num_pipes_active > 1)
2071 return 64;
2072
2073 /* otherwise just report max that registers can hold */
2074 return ilk_cursor_wm_reg_max(dev, level);
2075 }
2076
2077 static void ilk_compute_wm_maximums(const struct drm_device *dev,
2078 int level,
2079 const struct intel_wm_config *config,
2080 enum intel_ddb_partitioning ddb_partitioning,
2081 struct ilk_wm_maximums *max)
2082 {
2083 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
2084 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
2085 max->cur = ilk_cursor_wm_max(dev, level, config);
2086 max->fbc = ilk_fbc_wm_reg_max(dev);
2087 }
2088
2089 static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
2090 int level,
2091 struct ilk_wm_maximums *max)
2092 {
2093 max->pri = ilk_plane_wm_reg_max(dev, level, false);
2094 max->spr = ilk_plane_wm_reg_max(dev, level, true);
2095 max->cur = ilk_cursor_wm_reg_max(dev, level);
2096 max->fbc = ilk_fbc_wm_reg_max(dev);
2097 }
2098
2099 static bool ilk_validate_wm_level(int level,
2100 const struct ilk_wm_maximums *max,
2101 struct intel_wm_level *result)
2102 {
2103 bool ret;
2104
2105 /* already determined to be invalid? */
2106 if (!result->enable)
2107 return false;
2108
2109 result->enable = result->pri_val <= max->pri &&
2110 result->spr_val <= max->spr &&
2111 result->cur_val <= max->cur;
2112
2113 ret = result->enable;
2114
2115 /*
2116 * HACK until we can pre-compute everything,
2117 * and thus fail gracefully if LP0 watermarks
2118 * are exceeded...
2119 */
2120 if (level == 0 && !result->enable) {
2121 if (result->pri_val > max->pri)
2122 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2123 level, result->pri_val, max->pri);
2124 if (result->spr_val > max->spr)
2125 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2126 level, result->spr_val, max->spr);
2127 if (result->cur_val > max->cur)
2128 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2129 level, result->cur_val, max->cur);
2130
2131 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2132 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2133 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2134 result->enable = true;
2135 }
2136
2137 return ret;
2138 }
2139
2140 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
2141 int level,
2142 const struct ilk_pipe_wm_parameters *p,
2143 struct intel_wm_level *result)
2144 {
2145 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2146 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2147 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2148
2149 /* WM1+ latency values stored in 0.5us units */
2150 if (level > 0) {
2151 pri_latency *= 5;
2152 spr_latency *= 5;
2153 cur_latency *= 5;
2154 }
2155
2156 result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
2157 result->spr_val = ilk_compute_spr_wm(p, spr_latency);
2158 result->cur_val = ilk_compute_cur_wm(p, cur_latency);
2159 result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
2160 result->enable = true;
2161 }
2162
2163 static uint32_t
2164 hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
2165 {
2166 struct drm_i915_private *dev_priv = dev->dev_private;
2167 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2168 struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
2169 u32 linetime, ips_linetime;
2170
2171 if (!intel_crtc_active(crtc))
2172 return 0;
2173
2174 /* The WM are computed with base on how long it takes to fill a single
2175 * row at the given clock rate, multiplied by 8.
2176 * */
2177 linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
2178 mode->crtc_clock);
2179 ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
2180 intel_ddi_get_cdclk_freq(dev_priv));
2181
2182 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2183 PIPE_WM_LINETIME_TIME(linetime);
2184 }
2185
2186 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5])
2187 {
2188 struct drm_i915_private *dev_priv = dev->dev_private;
2189
2190 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2191 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2192
2193 wm[0] = (sskpd >> 56) & 0xFF;
2194 if (wm[0] == 0)
2195 wm[0] = sskpd & 0xF;
2196 wm[1] = (sskpd >> 4) & 0xFF;
2197 wm[2] = (sskpd >> 12) & 0xFF;
2198 wm[3] = (sskpd >> 20) & 0x1FF;
2199 wm[4] = (sskpd >> 32) & 0x1FF;
2200 } else if (INTEL_INFO(dev)->gen >= 6) {
2201 uint32_t sskpd = I915_READ(MCH_SSKPD);
2202
2203 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2204 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2205 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2206 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2207 } else if (INTEL_INFO(dev)->gen >= 5) {
2208 uint32_t mltr = I915_READ(MLTR_ILK);
2209
2210 /* ILK primary LP0 latency is 700 ns */
2211 wm[0] = 7;
2212 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2213 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2214 }
2215 }
2216
2217 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2218 {
2219 /* ILK sprite LP0 latency is 1300 ns */
2220 if (INTEL_INFO(dev)->gen == 5)
2221 wm[0] = 13;
2222 }
2223
2224 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2225 {
2226 /* ILK cursor LP0 latency is 1300 ns */
2227 if (INTEL_INFO(dev)->gen == 5)
2228 wm[0] = 13;
2229
2230 /* WaDoubleCursorLP3Latency:ivb */
2231 if (IS_IVYBRIDGE(dev))
2232 wm[3] *= 2;
2233 }
2234
2235 int ilk_wm_max_level(const struct drm_device *dev)
2236 {
2237 /* how many WM levels are we expecting */
2238 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2239 return 4;
2240 else if (INTEL_INFO(dev)->gen >= 6)
2241 return 3;
2242 else
2243 return 2;
2244 }
2245
2246 static void intel_print_wm_latency(struct drm_device *dev,
2247 const char *name,
2248 const uint16_t wm[5])
2249 {
2250 int level, max_level = ilk_wm_max_level(dev);
2251
2252 for (level = 0; level <= max_level; level++) {
2253 unsigned int latency = wm[level];
2254
2255 if (latency == 0) {
2256 DRM_ERROR("%s WM%d latency not provided\n",
2257 name, level);
2258 continue;
2259 }
2260
2261 /* WM1+ latency values in 0.5us units */
2262 if (level > 0)
2263 latency *= 5;
2264
2265 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2266 name, level, wm[level],
2267 latency / 10, latency % 10);
2268 }
2269 }
2270
2271 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2272 uint16_t wm[5], uint16_t min)
2273 {
2274 int level, max_level = ilk_wm_max_level(dev_priv->dev);
2275
2276 if (wm[0] >= min)
2277 return false;
2278
2279 wm[0] = max(wm[0], min);
2280 for (level = 1; level <= max_level; level++)
2281 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2282
2283 return true;
2284 }
2285
2286 static void snb_wm_latency_quirk(struct drm_device *dev)
2287 {
2288 struct drm_i915_private *dev_priv = dev->dev_private;
2289 bool changed;
2290
2291 /*
2292 * The BIOS provided WM memory latency values are often
2293 * inadequate for high resolution displays. Adjust them.
2294 */
2295 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2296 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2297 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2298
2299 if (!changed)
2300 return;
2301
2302 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2303 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2304 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2305 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2306 }
2307
2308 static void ilk_setup_wm_latency(struct drm_device *dev)
2309 {
2310 struct drm_i915_private *dev_priv = dev->dev_private;
2311
2312 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2313
2314 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2315 sizeof(dev_priv->wm.pri_latency));
2316 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2317 sizeof(dev_priv->wm.pri_latency));
2318
2319 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2320 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2321
2322 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2323 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2324 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2325
2326 if (IS_GEN6(dev))
2327 snb_wm_latency_quirk(dev);
2328 }
2329
2330 static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
2331 struct ilk_pipe_wm_parameters *p)
2332 {
2333 struct drm_device *dev = crtc->dev;
2334 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2335 enum pipe pipe = intel_crtc->pipe;
2336 struct drm_plane *plane;
2337
2338 if (!intel_crtc_active(crtc))
2339 return;
2340
2341 p->active = true;
2342 p->pipe_htotal = intel_crtc->config.adjusted_mode.crtc_htotal;
2343 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
2344 p->pri.bytes_per_pixel = crtc->primary->fb->bits_per_pixel / 8;
2345 p->cur.bytes_per_pixel = 4;
2346 p->pri.horiz_pixels = intel_crtc->config.pipe_src_w;
2347 p->cur.horiz_pixels = intel_crtc->cursor_width;
2348 /* TODO: for now, assume primary and cursor planes are always enabled. */
2349 p->pri.enabled = true;
2350 p->cur.enabled = true;
2351
2352 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
2353 struct intel_plane *intel_plane = to_intel_plane(plane);
2354
2355 if (intel_plane->pipe == pipe) {
2356 p->spr = intel_plane->wm;
2357 break;
2358 }
2359 }
2360 }
2361
2362 static void ilk_compute_wm_config(struct drm_device *dev,
2363 struct intel_wm_config *config)
2364 {
2365 struct intel_crtc *intel_crtc;
2366
2367 /* Compute the currently _active_ config */
2368 for_each_intel_crtc(dev, intel_crtc) {
2369 const struct intel_pipe_wm *wm = &intel_crtc->wm.active;
2370
2371 if (!wm->pipe_enabled)
2372 continue;
2373
2374 config->sprites_enabled |= wm->sprites_enabled;
2375 config->sprites_scaled |= wm->sprites_scaled;
2376 config->num_pipes_active++;
2377 }
2378 }
2379
2380 /* Compute new watermarks for the pipe */
2381 static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
2382 const struct ilk_pipe_wm_parameters *params,
2383 struct intel_pipe_wm *pipe_wm)
2384 {
2385 struct drm_device *dev = crtc->dev;
2386 const struct drm_i915_private *dev_priv = dev->dev_private;
2387 int level, max_level = ilk_wm_max_level(dev);
2388 /* LP0 watermark maximums depend on this pipe alone */
2389 struct intel_wm_config config = {
2390 .num_pipes_active = 1,
2391 .sprites_enabled = params->spr.enabled,
2392 .sprites_scaled = params->spr.scaled,
2393 };
2394 struct ilk_wm_maximums max;
2395
2396 pipe_wm->pipe_enabled = params->active;
2397 pipe_wm->sprites_enabled = params->spr.enabled;
2398 pipe_wm->sprites_scaled = params->spr.scaled;
2399
2400 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2401 if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled)
2402 max_level = 1;
2403
2404 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2405 if (params->spr.scaled)
2406 max_level = 0;
2407
2408 ilk_compute_wm_level(dev_priv, 0, params, &pipe_wm->wm[0]);
2409
2410 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2411 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
2412
2413 /* LP0 watermarks always use 1/2 DDB partitioning */
2414 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2415
2416 /* At least LP0 must be valid */
2417 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
2418 return false;
2419
2420 ilk_compute_wm_reg_maximums(dev, 1, &max);
2421
2422 for (level = 1; level <= max_level; level++) {
2423 struct intel_wm_level wm = {};
2424
2425 ilk_compute_wm_level(dev_priv, level, params, &wm);
2426
2427 /*
2428 * Disable any watermark level that exceeds the
2429 * register maximums since such watermarks are
2430 * always invalid.
2431 */
2432 if (!ilk_validate_wm_level(level, &max, &wm))
2433 break;
2434
2435 pipe_wm->wm[level] = wm;
2436 }
2437
2438 return true;
2439 }
2440
2441 /*
2442 * Merge the watermarks from all active pipes for a specific level.
2443 */
2444 static void ilk_merge_wm_level(struct drm_device *dev,
2445 int level,
2446 struct intel_wm_level *ret_wm)
2447 {
2448 const struct intel_crtc *intel_crtc;
2449
2450 ret_wm->enable = true;
2451
2452 for_each_intel_crtc(dev, intel_crtc) {
2453 const struct intel_pipe_wm *active = &intel_crtc->wm.active;
2454 const struct intel_wm_level *wm = &active->wm[level];
2455
2456 if (!active->pipe_enabled)
2457 continue;
2458
2459 /*
2460 * The watermark values may have been used in the past,
2461 * so we must maintain them in the registers for some
2462 * time even if the level is now disabled.
2463 */
2464 if (!wm->enable)
2465 ret_wm->enable = false;
2466
2467 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2468 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2469 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2470 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2471 }
2472 }
2473
2474 /*
2475 * Merge all low power watermarks for all active pipes.
2476 */
2477 static void ilk_wm_merge(struct drm_device *dev,
2478 const struct intel_wm_config *config,
2479 const struct ilk_wm_maximums *max,
2480 struct intel_pipe_wm *merged)
2481 {
2482 int level, max_level = ilk_wm_max_level(dev);
2483 int last_enabled_level = max_level;
2484
2485 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2486 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2487 config->num_pipes_active > 1)
2488 return;
2489
2490 /* ILK: FBC WM must be disabled always */
2491 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
2492
2493 /* merge each WM1+ level */
2494 for (level = 1; level <= max_level; level++) {
2495 struct intel_wm_level *wm = &merged->wm[level];
2496
2497 ilk_merge_wm_level(dev, level, wm);
2498
2499 if (level > last_enabled_level)
2500 wm->enable = false;
2501 else if (!ilk_validate_wm_level(level, max, wm))
2502 /* make sure all following levels get disabled */
2503 last_enabled_level = level - 1;
2504
2505 /*
2506 * The spec says it is preferred to disable
2507 * FBC WMs instead of disabling a WM level.
2508 */
2509 if (wm->fbc_val > max->fbc) {
2510 if (wm->enable)
2511 merged->fbc_wm_enabled = false;
2512 wm->fbc_val = 0;
2513 }
2514 }
2515
2516 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2517 /*
2518 * FIXME this is racy. FBC might get enabled later.
2519 * What we should check here is whether FBC can be
2520 * enabled sometime later.
2521 */
2522 if (IS_GEN5(dev) && !merged->fbc_wm_enabled && intel_fbc_enabled(dev)) {
2523 for (level = 2; level <= max_level; level++) {
2524 struct intel_wm_level *wm = &merged->wm[level];
2525
2526 wm->enable = false;
2527 }
2528 }
2529 }
2530
2531 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2532 {
2533 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2534 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2535 }
2536
2537 /* The value we need to program into the WM_LPx latency field */
2538 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2539 {
2540 struct drm_i915_private *dev_priv = dev->dev_private;
2541
2542 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2543 return 2 * level;
2544 else
2545 return dev_priv->wm.pri_latency[level];
2546 }
2547
2548 static void ilk_compute_wm_results(struct drm_device *dev,
2549 const struct intel_pipe_wm *merged,
2550 enum intel_ddb_partitioning partitioning,
2551 struct ilk_wm_values *results)
2552 {
2553 struct intel_crtc *intel_crtc;
2554 int level, wm_lp;
2555
2556 results->enable_fbc_wm = merged->fbc_wm_enabled;
2557 results->partitioning = partitioning;
2558
2559 /* LP1+ register values */
2560 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2561 const struct intel_wm_level *r;
2562
2563 level = ilk_wm_lp_to_level(wm_lp, merged);
2564
2565 r = &merged->wm[level];
2566
2567 /*
2568 * Maintain the watermark values even if the level is
2569 * disabled. Doing otherwise could cause underruns.
2570 */
2571 results->wm_lp[wm_lp - 1] =
2572 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2573 (r->pri_val << WM1_LP_SR_SHIFT) |
2574 r->cur_val;
2575
2576 if (r->enable)
2577 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2578
2579 if (INTEL_INFO(dev)->gen >= 8)
2580 results->wm_lp[wm_lp - 1] |=
2581 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2582 else
2583 results->wm_lp[wm_lp - 1] |=
2584 r->fbc_val << WM1_LP_FBC_SHIFT;
2585
2586 /*
2587 * Always set WM1S_LP_EN when spr_val != 0, even if the
2588 * level is disabled. Doing otherwise could cause underruns.
2589 */
2590 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2591 WARN_ON(wm_lp != 1);
2592 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2593 } else
2594 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2595 }
2596
2597 /* LP0 register values */
2598 for_each_intel_crtc(dev, intel_crtc) {
2599 enum pipe pipe = intel_crtc->pipe;
2600 const struct intel_wm_level *r =
2601 &intel_crtc->wm.active.wm[0];
2602
2603 if (WARN_ON(!r->enable))
2604 continue;
2605
2606 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
2607
2608 results->wm_pipe[pipe] =
2609 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2610 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2611 r->cur_val;
2612 }
2613 }
2614
2615 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2616 * case both are at the same level. Prefer r1 in case they're the same. */
2617 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2618 struct intel_pipe_wm *r1,
2619 struct intel_pipe_wm *r2)
2620 {
2621 int level, max_level = ilk_wm_max_level(dev);
2622 int level1 = 0, level2 = 0;
2623
2624 for (level = 1; level <= max_level; level++) {
2625 if (r1->wm[level].enable)
2626 level1 = level;
2627 if (r2->wm[level].enable)
2628 level2 = level;
2629 }
2630
2631 if (level1 == level2) {
2632 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2633 return r2;
2634 else
2635 return r1;
2636 } else if (level1 > level2) {
2637 return r1;
2638 } else {
2639 return r2;
2640 }
2641 }
2642
2643 /* dirty bits used to track which watermarks need changes */
2644 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2645 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2646 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2647 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2648 #define WM_DIRTY_FBC (1 << 24)
2649 #define WM_DIRTY_DDB (1 << 25)
2650
2651 static unsigned int ilk_compute_wm_dirty(struct drm_device *dev,
2652 const struct ilk_wm_values *old,
2653 const struct ilk_wm_values *new)
2654 {
2655 unsigned int dirty = 0;
2656 enum pipe pipe;
2657 int wm_lp;
2658
2659 for_each_pipe(pipe) {
2660 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2661 dirty |= WM_DIRTY_LINETIME(pipe);
2662 /* Must disable LP1+ watermarks too */
2663 dirty |= WM_DIRTY_LP_ALL;
2664 }
2665
2666 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2667 dirty |= WM_DIRTY_PIPE(pipe);
2668 /* Must disable LP1+ watermarks too */
2669 dirty |= WM_DIRTY_LP_ALL;
2670 }
2671 }
2672
2673 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2674 dirty |= WM_DIRTY_FBC;
2675 /* Must disable LP1+ watermarks too */
2676 dirty |= WM_DIRTY_LP_ALL;
2677 }
2678
2679 if (old->partitioning != new->partitioning) {
2680 dirty |= WM_DIRTY_DDB;
2681 /* Must disable LP1+ watermarks too */
2682 dirty |= WM_DIRTY_LP_ALL;
2683 }
2684
2685 /* LP1+ watermarks already deemed dirty, no need to continue */
2686 if (dirty & WM_DIRTY_LP_ALL)
2687 return dirty;
2688
2689 /* Find the lowest numbered LP1+ watermark in need of an update... */
2690 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2691 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2692 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2693 break;
2694 }
2695
2696 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2697 for (; wm_lp <= 3; wm_lp++)
2698 dirty |= WM_DIRTY_LP(wm_lp);
2699
2700 return dirty;
2701 }
2702
2703 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2704 unsigned int dirty)
2705 {
2706 struct ilk_wm_values *previous = &dev_priv->wm.hw;
2707 bool changed = false;
2708
2709 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2710 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2711 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2712 changed = true;
2713 }
2714 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2715 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2716 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2717 changed = true;
2718 }
2719 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2720 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2721 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2722 changed = true;
2723 }
2724
2725 /*
2726 * Don't touch WM1S_LP_EN here.
2727 * Doing so could cause underruns.
2728 */
2729
2730 return changed;
2731 }
2732
2733 /*
2734 * The spec says we shouldn't write when we don't need, because every write
2735 * causes WMs to be re-evaluated, expending some power.
2736 */
2737 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2738 struct ilk_wm_values *results)
2739 {
2740 struct drm_device *dev = dev_priv->dev;
2741 struct ilk_wm_values *previous = &dev_priv->wm.hw;
2742 unsigned int dirty;
2743 uint32_t val;
2744
2745 dirty = ilk_compute_wm_dirty(dev, previous, results);
2746 if (!dirty)
2747 return;
2748
2749 _ilk_disable_lp_wm(dev_priv, dirty);
2750
2751 if (dirty & WM_DIRTY_PIPE(PIPE_A))
2752 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2753 if (dirty & WM_DIRTY_PIPE(PIPE_B))
2754 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2755 if (dirty & WM_DIRTY_PIPE(PIPE_C))
2756 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2757
2758 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2759 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2760 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2761 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2762 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2763 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2764
2765 if (dirty & WM_DIRTY_DDB) {
2766 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2767 val = I915_READ(WM_MISC);
2768 if (results->partitioning == INTEL_DDB_PART_1_2)
2769 val &= ~WM_MISC_DATA_PARTITION_5_6;
2770 else
2771 val |= WM_MISC_DATA_PARTITION_5_6;
2772 I915_WRITE(WM_MISC, val);
2773 } else {
2774 val = I915_READ(DISP_ARB_CTL2);
2775 if (results->partitioning == INTEL_DDB_PART_1_2)
2776 val &= ~DISP_DATA_PARTITION_5_6;
2777 else
2778 val |= DISP_DATA_PARTITION_5_6;
2779 I915_WRITE(DISP_ARB_CTL2, val);
2780 }
2781 }
2782
2783 if (dirty & WM_DIRTY_FBC) {
2784 val = I915_READ(DISP_ARB_CTL);
2785 if (results->enable_fbc_wm)
2786 val &= ~DISP_FBC_WM_DIS;
2787 else
2788 val |= DISP_FBC_WM_DIS;
2789 I915_WRITE(DISP_ARB_CTL, val);
2790 }
2791
2792 if (dirty & WM_DIRTY_LP(1) &&
2793 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2794 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2795
2796 if (INTEL_INFO(dev)->gen >= 7) {
2797 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2798 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2799 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2800 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2801 }
2802
2803 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2804 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2805 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2806 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2807 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2808 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2809
2810 dev_priv->wm.hw = *results;
2811 }
2812
2813 static bool ilk_disable_lp_wm(struct drm_device *dev)
2814 {
2815 struct drm_i915_private *dev_priv = dev->dev_private;
2816
2817 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2818 }
2819
2820 static void ilk_update_wm(struct drm_crtc *crtc)
2821 {
2822 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2823 struct drm_device *dev = crtc->dev;
2824 struct drm_i915_private *dev_priv = dev->dev_private;
2825 struct ilk_wm_maximums max;
2826 struct ilk_pipe_wm_parameters params = {};
2827 struct ilk_wm_values results = {};
2828 enum intel_ddb_partitioning partitioning;
2829 struct intel_pipe_wm pipe_wm = {};
2830 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
2831 struct intel_wm_config config = {};
2832
2833 ilk_compute_wm_parameters(crtc, &params);
2834
2835 intel_compute_pipe_wm(crtc, &params, &pipe_wm);
2836
2837 if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
2838 return;
2839
2840 intel_crtc->wm.active = pipe_wm;
2841
2842 ilk_compute_wm_config(dev, &config);
2843
2844 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
2845 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
2846
2847 /* 5/6 split only in single pipe config on IVB+ */
2848 if (INTEL_INFO(dev)->gen >= 7 &&
2849 config.num_pipes_active == 1 && config.sprites_enabled) {
2850 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
2851 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
2852
2853 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
2854 } else {
2855 best_lp_wm = &lp_wm_1_2;
2856 }
2857
2858 partitioning = (best_lp_wm == &lp_wm_1_2) ?
2859 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
2860
2861 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
2862
2863 ilk_write_wm_values(dev_priv, &results);
2864 }
2865
2866 static void
2867 ilk_update_sprite_wm(struct drm_plane *plane,
2868 struct drm_crtc *crtc,
2869 uint32_t sprite_width, uint32_t sprite_height,
2870 int pixel_size, bool enabled, bool scaled)
2871 {
2872 struct drm_device *dev = plane->dev;
2873 struct intel_plane *intel_plane = to_intel_plane(plane);
2874
2875 intel_plane->wm.enabled = enabled;
2876 intel_plane->wm.scaled = scaled;
2877 intel_plane->wm.horiz_pixels = sprite_width;
2878 intel_plane->wm.vert_pixels = sprite_width;
2879 intel_plane->wm.bytes_per_pixel = pixel_size;
2880
2881 /*
2882 * IVB workaround: must disable low power watermarks for at least
2883 * one frame before enabling scaling. LP watermarks can be re-enabled
2884 * when scaling is disabled.
2885 *
2886 * WaCxSRDisabledForSpriteScaling:ivb
2887 */
2888 if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev))
2889 intel_wait_for_vblank(dev, intel_plane->pipe);
2890
2891 ilk_update_wm(crtc);
2892 }
2893
2894 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
2895 {
2896 struct drm_device *dev = crtc->dev;
2897 struct drm_i915_private *dev_priv = dev->dev_private;
2898 struct ilk_wm_values *hw = &dev_priv->wm.hw;
2899 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2900 struct intel_pipe_wm *active = &intel_crtc->wm.active;
2901 enum pipe pipe = intel_crtc->pipe;
2902 static const unsigned int wm0_pipe_reg[] = {
2903 [PIPE_A] = WM0_PIPEA_ILK,
2904 [PIPE_B] = WM0_PIPEB_ILK,
2905 [PIPE_C] = WM0_PIPEC_IVB,
2906 };
2907
2908 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
2909 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2910 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
2911
2912 active->pipe_enabled = intel_crtc_active(crtc);
2913
2914 if (active->pipe_enabled) {
2915 u32 tmp = hw->wm_pipe[pipe];
2916
2917 /*
2918 * For active pipes LP0 watermark is marked as
2919 * enabled, and LP1+ watermaks as disabled since
2920 * we can't really reverse compute them in case
2921 * multiple pipes are active.
2922 */
2923 active->wm[0].enable = true;
2924 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
2925 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
2926 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
2927 active->linetime = hw->wm_linetime[pipe];
2928 } else {
2929 int level, max_level = ilk_wm_max_level(dev);
2930
2931 /*
2932 * For inactive pipes, all watermark levels
2933 * should be marked as enabled but zeroed,
2934 * which is what we'd compute them to.
2935 */
2936 for (level = 0; level <= max_level; level++)
2937 active->wm[level].enable = true;
2938 }
2939 }
2940
2941 void ilk_wm_get_hw_state(struct drm_device *dev)
2942 {
2943 struct drm_i915_private *dev_priv = dev->dev_private;
2944 struct ilk_wm_values *hw = &dev_priv->wm.hw;
2945 struct drm_crtc *crtc;
2946
2947 for_each_crtc(dev, crtc)
2948 ilk_pipe_wm_get_hw_state(crtc);
2949
2950 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
2951 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
2952 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
2953
2954 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
2955 if (INTEL_INFO(dev)->gen >= 7) {
2956 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
2957 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
2958 }
2959
2960 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2961 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
2962 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
2963 else if (IS_IVYBRIDGE(dev))
2964 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
2965 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
2966
2967 hw->enable_fbc_wm =
2968 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
2969 }
2970
2971 /**
2972 * intel_update_watermarks - update FIFO watermark values based on current modes
2973 *
2974 * Calculate watermark values for the various WM regs based on current mode
2975 * and plane configuration.
2976 *
2977 * There are several cases to deal with here:
2978 * - normal (i.e. non-self-refresh)
2979 * - self-refresh (SR) mode
2980 * - lines are large relative to FIFO size (buffer can hold up to 2)
2981 * - lines are small relative to FIFO size (buffer can hold more than 2
2982 * lines), so need to account for TLB latency
2983 *
2984 * The normal calculation is:
2985 * watermark = dotclock * bytes per pixel * latency
2986 * where latency is platform & configuration dependent (we assume pessimal
2987 * values here).
2988 *
2989 * The SR calculation is:
2990 * watermark = (trunc(latency/line time)+1) * surface width *
2991 * bytes per pixel
2992 * where
2993 * line time = htotal / dotclock
2994 * surface width = hdisplay for normal plane and 64 for cursor
2995 * and latency is assumed to be high, as above.
2996 *
2997 * The final value programmed to the register should always be rounded up,
2998 * and include an extra 2 entries to account for clock crossings.
2999 *
3000 * We don't use the sprite, so we can ignore that. And on Crestline we have
3001 * to set the non-SR watermarks to 8.
3002 */
3003 void intel_update_watermarks(struct drm_crtc *crtc)
3004 {
3005 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
3006
3007 if (dev_priv->display.update_wm)
3008 dev_priv->display.update_wm(crtc);
3009 }
3010
3011 void intel_update_sprite_watermarks(struct drm_plane *plane,
3012 struct drm_crtc *crtc,
3013 uint32_t sprite_width,
3014 uint32_t sprite_height,
3015 int pixel_size,
3016 bool enabled, bool scaled)
3017 {
3018 struct drm_i915_private *dev_priv = plane->dev->dev_private;
3019
3020 if (dev_priv->display.update_sprite_wm)
3021 dev_priv->display.update_sprite_wm(plane, crtc,
3022 sprite_width, sprite_height,
3023 pixel_size, enabled, scaled);
3024 }
3025
3026 static struct drm_i915_gem_object *
3027 intel_alloc_context_page(struct drm_device *dev)
3028 {
3029 struct drm_i915_gem_object *ctx;
3030 int ret;
3031
3032 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3033
3034 ctx = i915_gem_alloc_object(dev, 4096);
3035 if (!ctx) {
3036 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
3037 return NULL;
3038 }
3039
3040 ret = i915_gem_obj_ggtt_pin(ctx, 4096, 0);
3041 if (ret) {
3042 DRM_ERROR("failed to pin power context: %d\n", ret);
3043 goto err_unref;
3044 }
3045
3046 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
3047 if (ret) {
3048 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
3049 goto err_unpin;
3050 }
3051
3052 return ctx;
3053
3054 err_unpin:
3055 i915_gem_object_ggtt_unpin(ctx);
3056 err_unref:
3057 drm_gem_object_unreference(&ctx->base);
3058 return NULL;
3059 }
3060
3061 /**
3062 * Lock protecting IPS related data structures
3063 */
3064 DEFINE_SPINLOCK(mchdev_lock);
3065
3066 /* Global for IPS driver to get at the current i915 device. Protected by
3067 * mchdev_lock. */
3068 static struct drm_i915_private *i915_mch_dev;
3069
3070 bool ironlake_set_drps(struct drm_device *dev, u8 val)
3071 {
3072 struct drm_i915_private *dev_priv = dev->dev_private;
3073 u16 rgvswctl;
3074
3075 assert_spin_locked(&mchdev_lock);
3076
3077 rgvswctl = I915_READ16(MEMSWCTL);
3078 if (rgvswctl & MEMCTL_CMD_STS) {
3079 DRM_DEBUG("gpu busy, RCS change rejected\n");
3080 return false; /* still busy with another command */
3081 }
3082
3083 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
3084 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
3085 I915_WRITE16(MEMSWCTL, rgvswctl);
3086 POSTING_READ16(MEMSWCTL);
3087
3088 rgvswctl |= MEMCTL_CMD_STS;
3089 I915_WRITE16(MEMSWCTL, rgvswctl);
3090
3091 return true;
3092 }
3093
3094 static void ironlake_enable_drps(struct drm_device *dev)
3095 {
3096 struct drm_i915_private *dev_priv = dev->dev_private;
3097 u32 rgvmodectl = I915_READ(MEMMODECTL);
3098 u8 fmax, fmin, fstart, vstart;
3099
3100 spin_lock_irq(&mchdev_lock);
3101
3102 /* Enable temp reporting */
3103 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
3104 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
3105
3106 /* 100ms RC evaluation intervals */
3107 I915_WRITE(RCUPEI, 100000);
3108 I915_WRITE(RCDNEI, 100000);
3109
3110 /* Set max/min thresholds to 90ms and 80ms respectively */
3111 I915_WRITE(RCBMAXAVG, 90000);
3112 I915_WRITE(RCBMINAVG, 80000);
3113
3114 I915_WRITE(MEMIHYST, 1);
3115
3116 /* Set up min, max, and cur for interrupt handling */
3117 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
3118 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
3119 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
3120 MEMMODE_FSTART_SHIFT;
3121
3122 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
3123 PXVFREQ_PX_SHIFT;
3124
3125 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
3126 dev_priv->ips.fstart = fstart;
3127
3128 dev_priv->ips.max_delay = fstart;
3129 dev_priv->ips.min_delay = fmin;
3130 dev_priv->ips.cur_delay = fstart;
3131
3132 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
3133 fmax, fmin, fstart);
3134
3135 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
3136
3137 /*
3138 * Interrupts will be enabled in ironlake_irq_postinstall
3139 */
3140
3141 I915_WRITE(VIDSTART, vstart);
3142 POSTING_READ(VIDSTART);
3143
3144 rgvmodectl |= MEMMODE_SWMODE_EN;
3145 I915_WRITE(MEMMODECTL, rgvmodectl);
3146
3147 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
3148 DRM_ERROR("stuck trying to change perf mode\n");
3149 mdelay(1);
3150
3151 ironlake_set_drps(dev, fstart);
3152
3153 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
3154 I915_READ(0x112e0);
3155 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
3156 dev_priv->ips.last_count2 = I915_READ(0x112f4);
3157 dev_priv->ips.last_time2 = ktime_get_raw_ns();
3158
3159 spin_unlock_irq(&mchdev_lock);
3160 }
3161
3162 static void ironlake_disable_drps(struct drm_device *dev)
3163 {
3164 struct drm_i915_private *dev_priv = dev->dev_private;
3165 u16 rgvswctl;
3166
3167 spin_lock_irq(&mchdev_lock);
3168
3169 rgvswctl = I915_READ16(MEMSWCTL);
3170
3171 /* Ack interrupts, disable EFC interrupt */
3172 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
3173 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
3174 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
3175 I915_WRITE(DEIIR, DE_PCU_EVENT);
3176 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
3177
3178 /* Go back to the starting frequency */
3179 ironlake_set_drps(dev, dev_priv->ips.fstart);
3180 mdelay(1);
3181 rgvswctl |= MEMCTL_CMD_STS;
3182 I915_WRITE(MEMSWCTL, rgvswctl);
3183 mdelay(1);
3184
3185 spin_unlock_irq(&mchdev_lock);
3186 }
3187
3188 /* There's a funny hw issue where the hw returns all 0 when reading from
3189 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3190 * ourselves, instead of doing a rmw cycle (which might result in us clearing
3191 * all limits and the gpu stuck at whatever frequency it is at atm).
3192 */
3193 static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)
3194 {
3195 u32 limits;
3196
3197 /* Only set the down limit when we've reached the lowest level to avoid
3198 * getting more interrupts, otherwise leave this clear. This prevents a
3199 * race in the hw when coming out of rc6: There's a tiny window where
3200 * the hw runs at the minimal clock before selecting the desired
3201 * frequency, if the down threshold expires in that window we will not
3202 * receive a down interrupt. */
3203 limits = dev_priv->rps.max_freq_softlimit << 24;
3204 if (val <= dev_priv->rps.min_freq_softlimit)
3205 limits |= dev_priv->rps.min_freq_softlimit << 16;
3206
3207 return limits;
3208 }
3209
3210 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
3211 {
3212 int new_power;
3213
3214 new_power = dev_priv->rps.power;
3215 switch (dev_priv->rps.power) {
3216 case LOW_POWER:
3217 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
3218 new_power = BETWEEN;
3219 break;
3220
3221 case BETWEEN:
3222 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
3223 new_power = LOW_POWER;
3224 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
3225 new_power = HIGH_POWER;
3226 break;
3227
3228 case HIGH_POWER:
3229 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
3230 new_power = BETWEEN;
3231 break;
3232 }
3233 /* Max/min bins are special */
3234 if (val == dev_priv->rps.min_freq_softlimit)
3235 new_power = LOW_POWER;
3236 if (val == dev_priv->rps.max_freq_softlimit)
3237 new_power = HIGH_POWER;
3238 if (new_power == dev_priv->rps.power)
3239 return;
3240
3241 /* Note the units here are not exactly 1us, but 1280ns. */
3242 switch (new_power) {
3243 case LOW_POWER:
3244 /* Upclock if more than 95% busy over 16ms */
3245 I915_WRITE(GEN6_RP_UP_EI, 12500);
3246 I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800);
3247
3248 /* Downclock if less than 85% busy over 32ms */
3249 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3250 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250);
3251
3252 I915_WRITE(GEN6_RP_CONTROL,
3253 GEN6_RP_MEDIA_TURBO |
3254 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3255 GEN6_RP_MEDIA_IS_GFX |
3256 GEN6_RP_ENABLE |
3257 GEN6_RP_UP_BUSY_AVG |
3258 GEN6_RP_DOWN_IDLE_AVG);
3259 break;
3260
3261 case BETWEEN:
3262 /* Upclock if more than 90% busy over 13ms */
3263 I915_WRITE(GEN6_RP_UP_EI, 10250);
3264 I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225);
3265
3266 /* Downclock if less than 75% busy over 32ms */
3267 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3268 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750);
3269
3270 I915_WRITE(GEN6_RP_CONTROL,
3271 GEN6_RP_MEDIA_TURBO |
3272 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3273 GEN6_RP_MEDIA_IS_GFX |
3274 GEN6_RP_ENABLE |
3275 GEN6_RP_UP_BUSY_AVG |
3276 GEN6_RP_DOWN_IDLE_AVG);
3277 break;
3278
3279 case HIGH_POWER:
3280 /* Upclock if more than 85% busy over 10ms */
3281 I915_WRITE(GEN6_RP_UP_EI, 8000);
3282 I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800);
3283
3284 /* Downclock if less than 60% busy over 32ms */
3285 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3286 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000);
3287
3288 I915_WRITE(GEN6_RP_CONTROL,
3289 GEN6_RP_MEDIA_TURBO |
3290 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3291 GEN6_RP_MEDIA_IS_GFX |
3292 GEN6_RP_ENABLE |
3293 GEN6_RP_UP_BUSY_AVG |
3294 GEN6_RP_DOWN_IDLE_AVG);
3295 break;
3296 }
3297
3298 dev_priv->rps.power = new_power;
3299 dev_priv->rps.last_adj = 0;
3300 }
3301
3302 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
3303 {
3304 u32 mask = 0;
3305
3306 if (val > dev_priv->rps.min_freq_softlimit)
3307 mask |= GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
3308 if (val < dev_priv->rps.max_freq_softlimit)
3309 mask |= GEN6_PM_RP_UP_THRESHOLD;
3310
3311 mask |= dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED);
3312 mask &= dev_priv->pm_rps_events;
3313
3314 /* IVB and SNB hard hangs on looping batchbuffer
3315 * if GEN6_PM_UP_EI_EXPIRED is masked.
3316 */
3317 if (INTEL_INFO(dev_priv->dev)->gen <= 7 && !IS_HASWELL(dev_priv->dev))
3318 mask |= GEN6_PM_RP_UP_EI_EXPIRED;
3319
3320 if (IS_GEN8(dev_priv->dev))
3321 mask |= GEN8_PMINTR_REDIRECT_TO_NON_DISP;
3322
3323 return ~mask;
3324 }
3325
3326 /* gen6_set_rps is called to update the frequency request, but should also be
3327 * called when the range (min_delay and max_delay) is modified so that we can
3328 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
3329 void gen6_set_rps(struct drm_device *dev, u8 val)
3330 {
3331 struct drm_i915_private *dev_priv = dev->dev_private;
3332
3333 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3334 WARN_ON(val > dev_priv->rps.max_freq_softlimit);
3335 WARN_ON(val < dev_priv->rps.min_freq_softlimit);
3336
3337 /* min/max delay may still have been modified so be sure to
3338 * write the limits value.
3339 */
3340 if (val != dev_priv->rps.cur_freq) {
3341 gen6_set_rps_thresholds(dev_priv, val);
3342
3343 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3344 I915_WRITE(GEN6_RPNSWREQ,
3345 HSW_FREQUENCY(val));
3346 else
3347 I915_WRITE(GEN6_RPNSWREQ,
3348 GEN6_FREQUENCY(val) |
3349 GEN6_OFFSET(0) |
3350 GEN6_AGGRESSIVE_TURBO);
3351 }
3352
3353 /* Make sure we continue to get interrupts
3354 * until we hit the minimum or maximum frequencies.
3355 */
3356 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, gen6_rps_limits(dev_priv, val));
3357 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
3358
3359 POSTING_READ(GEN6_RPNSWREQ);
3360
3361 dev_priv->rps.cur_freq = val;
3362 trace_intel_gpu_freq_change(val * 50);
3363 }
3364
3365 /* vlv_set_rps_idle: Set the frequency to Rpn if Gfx clocks are down
3366 *
3367 * * If Gfx is Idle, then
3368 * 1. Mask Turbo interrupts
3369 * 2. Bring up Gfx clock
3370 * 3. Change the freq to Rpn and wait till P-Unit updates freq
3371 * 4. Clear the Force GFX CLK ON bit so that Gfx can down
3372 * 5. Unmask Turbo interrupts
3373 */
3374 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
3375 {
3376 struct drm_device *dev = dev_priv->dev;
3377
3378 /* Latest VLV doesn't need to force the gfx clock */
3379 if (dev->pdev->revision >= 0xd) {
3380 valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3381 return;
3382 }
3383
3384 /*
3385 * When we are idle. Drop to min voltage state.
3386 */
3387
3388 if (dev_priv->rps.cur_freq <= dev_priv->rps.min_freq_softlimit)
3389 return;
3390
3391 /* Mask turbo interrupt so that they will not come in between */
3392 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3393
3394 vlv_force_gfx_clock(dev_priv, true);
3395
3396 dev_priv->rps.cur_freq = dev_priv->rps.min_freq_softlimit;
3397
3398 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ,
3399 dev_priv->rps.min_freq_softlimit);
3400
3401 if (wait_for(((vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS))
3402 & GENFREQSTATUS) == 0, 5))
3403 DRM_ERROR("timed out waiting for Punit\n");
3404
3405 vlv_force_gfx_clock(dev_priv, false);
3406
3407 I915_WRITE(GEN6_PMINTRMSK,
3408 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
3409 }
3410
3411 void gen6_rps_idle(struct drm_i915_private *dev_priv)
3412 {
3413 struct drm_device *dev = dev_priv->dev;
3414
3415 mutex_lock(&dev_priv->rps.hw_lock);
3416 if (dev_priv->rps.enabled) {
3417 if (IS_CHERRYVIEW(dev))
3418 valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3419 else if (IS_VALLEYVIEW(dev))
3420 vlv_set_rps_idle(dev_priv);
3421 else
3422 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3423 dev_priv->rps.last_adj = 0;
3424 }
3425 mutex_unlock(&dev_priv->rps.hw_lock);
3426 }
3427
3428 void gen6_rps_boost(struct drm_i915_private *dev_priv)
3429 {
3430 struct drm_device *dev = dev_priv->dev;
3431
3432 mutex_lock(&dev_priv->rps.hw_lock);
3433 if (dev_priv->rps.enabled) {
3434 if (IS_VALLEYVIEW(dev))
3435 valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
3436 else
3437 gen6_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
3438 dev_priv->rps.last_adj = 0;
3439 }
3440 mutex_unlock(&dev_priv->rps.hw_lock);
3441 }
3442
3443 void valleyview_set_rps(struct drm_device *dev, u8 val)
3444 {
3445 struct drm_i915_private *dev_priv = dev->dev_private;
3446
3447 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3448 WARN_ON(val > dev_priv->rps.max_freq_softlimit);
3449 WARN_ON(val < dev_priv->rps.min_freq_softlimit);
3450
3451 DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
3452 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
3453 dev_priv->rps.cur_freq,
3454 vlv_gpu_freq(dev_priv, val), val);
3455
3456 if (val != dev_priv->rps.cur_freq)
3457 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
3458
3459 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
3460
3461 dev_priv->rps.cur_freq = val;
3462 trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val));
3463 }
3464
3465 static void gen8_disable_rps_interrupts(struct drm_device *dev)
3466 {
3467 struct drm_i915_private *dev_priv = dev->dev_private;
3468
3469 I915_WRITE(GEN6_PMINTRMSK, ~GEN8_PMINTR_REDIRECT_TO_NON_DISP);
3470 I915_WRITE(GEN8_GT_IER(2), I915_READ(GEN8_GT_IER(2)) &
3471 ~dev_priv->pm_rps_events);
3472 /* Complete PM interrupt masking here doesn't race with the rps work
3473 * item again unmasking PM interrupts because that is using a different
3474 * register (GEN8_GT_IMR(2)) to mask PM interrupts. The only risk is in
3475 * leaving stale bits in GEN8_GT_IIR(2) and GEN8_GT_IMR(2) which
3476 * gen8_enable_rps will clean up. */
3477
3478 spin_lock_irq(&dev_priv->irq_lock);
3479 dev_priv->rps.pm_iir = 0;
3480 spin_unlock_irq(&dev_priv->irq_lock);
3481
3482 I915_WRITE(GEN8_GT_IIR(2), dev_priv->pm_rps_events);
3483 }
3484
3485 static void gen6_disable_rps_interrupts(struct drm_device *dev)
3486 {
3487 struct drm_i915_private *dev_priv = dev->dev_private;
3488
3489 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3490 I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) &
3491 ~dev_priv->pm_rps_events);
3492 /* Complete PM interrupt masking here doesn't race with the rps work
3493 * item again unmasking PM interrupts because that is using a different
3494 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3495 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3496
3497 spin_lock_irq(&dev_priv->irq_lock);
3498 dev_priv->rps.pm_iir = 0;
3499 spin_unlock_irq(&dev_priv->irq_lock);
3500
3501 I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events);
3502 }
3503
3504 static void gen6_disable_rps(struct drm_device *dev)
3505 {
3506 struct drm_i915_private *dev_priv = dev->dev_private;
3507
3508 I915_WRITE(GEN6_RC_CONTROL, 0);
3509 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
3510
3511 if (IS_BROADWELL(dev))
3512 gen8_disable_rps_interrupts(dev);
3513 else
3514 gen6_disable_rps_interrupts(dev);
3515 }
3516
3517 static void cherryview_disable_rps(struct drm_device *dev)
3518 {
3519 struct drm_i915_private *dev_priv = dev->dev_private;
3520
3521 I915_WRITE(GEN6_RC_CONTROL, 0);
3522
3523 gen8_disable_rps_interrupts(dev);
3524 }
3525
3526 static void valleyview_disable_rps(struct drm_device *dev)
3527 {
3528 struct drm_i915_private *dev_priv = dev->dev_private;
3529
3530 I915_WRITE(GEN6_RC_CONTROL, 0);
3531
3532 gen6_disable_rps_interrupts(dev);
3533 }
3534
3535 static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
3536 {
3537 if (IS_VALLEYVIEW(dev)) {
3538 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
3539 mode = GEN6_RC_CTL_RC6_ENABLE;
3540 else
3541 mode = 0;
3542 }
3543 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
3544 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3545 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3546 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
3547 }
3548
3549 static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
3550 {
3551 /* No RC6 before Ironlake */
3552 if (INTEL_INFO(dev)->gen < 5)
3553 return 0;
3554
3555 /* RC6 is only on Ironlake mobile not on desktop */
3556 if (INTEL_INFO(dev)->gen == 5 && !IS_IRONLAKE_M(dev))
3557 return 0;
3558
3559 /* Respect the kernel parameter if it is set */
3560 if (enable_rc6 >= 0) {
3561 int mask;
3562
3563 if (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
3564 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
3565 INTEL_RC6pp_ENABLE;
3566 else
3567 mask = INTEL_RC6_ENABLE;
3568
3569 if ((enable_rc6 & mask) != enable_rc6)
3570 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
3571 enable_rc6 & mask, enable_rc6, mask);
3572
3573 return enable_rc6 & mask;
3574 }
3575
3576 /* Disable RC6 on Ironlake */
3577 if (INTEL_INFO(dev)->gen == 5)
3578 return 0;
3579
3580 if (IS_IVYBRIDGE(dev))
3581 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
3582
3583 return INTEL_RC6_ENABLE;
3584 }
3585
3586 int intel_enable_rc6(const struct drm_device *dev)
3587 {
3588 return i915.enable_rc6;
3589 }
3590
3591 static void gen8_enable_rps_interrupts(struct drm_device *dev)
3592 {
3593 struct drm_i915_private *dev_priv = dev->dev_private;
3594
3595 spin_lock_irq(&dev_priv->irq_lock);
3596 WARN_ON(dev_priv->rps.pm_iir);
3597 gen8_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
3598 I915_WRITE(GEN8_GT_IIR(2), dev_priv->pm_rps_events);
3599 spin_unlock_irq(&dev_priv->irq_lock);
3600 }
3601
3602 static void gen6_enable_rps_interrupts(struct drm_device *dev)
3603 {
3604 struct drm_i915_private *dev_priv = dev->dev_private;
3605
3606 spin_lock_irq(&dev_priv->irq_lock);
3607 WARN_ON(dev_priv->rps.pm_iir);
3608 gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
3609 I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events);
3610 spin_unlock_irq(&dev_priv->irq_lock);
3611 }
3612
3613 static void parse_rp_state_cap(struct drm_i915_private *dev_priv, u32 rp_state_cap)
3614 {
3615 /* All of these values are in units of 50MHz */
3616 dev_priv->rps.cur_freq = 0;
3617 /* static values from HW: RP0 < RPe < RP1 < RPn (min_freq) */
3618 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
3619 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
3620 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
3621 /* XXX: only BYT has a special efficient freq */
3622 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
3623 /* hw_max = RP0 until we check for overclocking */
3624 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
3625
3626 /* Preserve min/max settings in case of re-init */
3627 if (dev_priv->rps.max_freq_softlimit == 0)
3628 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
3629
3630 if (dev_priv->rps.min_freq_softlimit == 0)
3631 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
3632 }
3633
3634 static void gen8_enable_rps(struct drm_device *dev)
3635 {
3636 struct drm_i915_private *dev_priv = dev->dev_private;
3637 struct intel_engine_cs *ring;
3638 uint32_t rc6_mask = 0, rp_state_cap;
3639 int unused;
3640
3641 /* 1a: Software RC state - RC0 */
3642 I915_WRITE(GEN6_RC_STATE, 0);
3643
3644 /* 1c & 1d: Get forcewake during program sequence. Although the driver
3645 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
3646 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3647
3648 /* 2a: Disable RC states. */
3649 I915_WRITE(GEN6_RC_CONTROL, 0);
3650
3651 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3652 parse_rp_state_cap(dev_priv, rp_state_cap);
3653
3654 /* 2b: Program RC6 thresholds.*/
3655 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
3656 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
3657 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
3658 for_each_ring(ring, dev_priv, unused)
3659 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3660 I915_WRITE(GEN6_RC_SLEEP, 0);
3661 if (IS_BROADWELL(dev))
3662 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
3663 else
3664 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
3665
3666 /* 3: Enable RC6 */
3667 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
3668 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
3669 intel_print_rc6_info(dev, rc6_mask);
3670 if (IS_BROADWELL(dev))
3671 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
3672 GEN7_RC_CTL_TO_MODE |
3673 rc6_mask);
3674 else
3675 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
3676 GEN6_RC_CTL_EI_MODE(1) |
3677 rc6_mask);
3678
3679 /* 4 Program defaults and thresholds for RPS*/
3680 I915_WRITE(GEN6_RPNSWREQ,
3681 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
3682 I915_WRITE(GEN6_RC_VIDEO_FREQ,
3683 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
3684 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
3685 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
3686
3687 /* Docs recommend 900MHz, and 300 MHz respectively */
3688 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
3689 dev_priv->rps.max_freq_softlimit << 24 |
3690 dev_priv->rps.min_freq_softlimit << 16);
3691
3692 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
3693 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
3694 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
3695 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
3696
3697 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3698
3699 /* 5: Enable RPS */
3700 I915_WRITE(GEN6_RP_CONTROL,
3701 GEN6_RP_MEDIA_TURBO |
3702 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3703 GEN6_RP_MEDIA_IS_GFX |
3704 GEN6_RP_ENABLE |
3705 GEN6_RP_UP_BUSY_AVG |
3706 GEN6_RP_DOWN_IDLE_AVG);
3707
3708 /* 6: Ring frequency + overclocking (our driver does this later */
3709
3710 gen6_set_rps(dev, (I915_READ(GEN6_GT_PERF_STATUS) & 0xff00) >> 8);
3711
3712 gen8_enable_rps_interrupts(dev);
3713
3714 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3715 }
3716
3717 static void gen6_enable_rps(struct drm_device *dev)
3718 {
3719 struct drm_i915_private *dev_priv = dev->dev_private;
3720 struct intel_engine_cs *ring;
3721 u32 rp_state_cap;
3722 u32 gt_perf_status;
3723 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
3724 u32 gtfifodbg;
3725 int rc6_mode;
3726 int i, ret;
3727
3728 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3729
3730 /* Here begins a magic sequence of register writes to enable
3731 * auto-downclocking.
3732 *
3733 * Perhaps there might be some value in exposing these to
3734 * userspace...
3735 */
3736 I915_WRITE(GEN6_RC_STATE, 0);
3737
3738 /* Clear the DBG now so we don't confuse earlier errors */
3739 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3740 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3741 I915_WRITE(GTFIFODBG, gtfifodbg);
3742 }
3743
3744 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3745
3746 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3747 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
3748
3749 parse_rp_state_cap(dev_priv, rp_state_cap);
3750
3751 /* disable the counters and set deterministic thresholds */
3752 I915_WRITE(GEN6_RC_CONTROL, 0);
3753
3754 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
3755 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
3756 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
3757 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3758 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3759
3760 for_each_ring(ring, dev_priv, i)
3761 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3762
3763 I915_WRITE(GEN6_RC_SLEEP, 0);
3764 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
3765 if (IS_IVYBRIDGE(dev))
3766 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
3767 else
3768 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
3769 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
3770 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
3771
3772 /* Check if we are enabling RC6 */
3773 rc6_mode = intel_enable_rc6(dev_priv->dev);
3774 if (rc6_mode & INTEL_RC6_ENABLE)
3775 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
3776
3777 /* We don't use those on Haswell */
3778 if (!IS_HASWELL(dev)) {
3779 if (rc6_mode & INTEL_RC6p_ENABLE)
3780 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
3781
3782 if (rc6_mode & INTEL_RC6pp_ENABLE)
3783 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
3784 }
3785
3786 intel_print_rc6_info(dev, rc6_mask);
3787
3788 I915_WRITE(GEN6_RC_CONTROL,
3789 rc6_mask |
3790 GEN6_RC_CTL_EI_MODE(1) |
3791 GEN6_RC_CTL_HW_ENABLE);
3792
3793 /* Power down if completely idle for over 50ms */
3794 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
3795 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3796
3797 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
3798 if (ret)
3799 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
3800
3801 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
3802 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
3803 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
3804 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
3805 (pcu_mbox & 0xff) * 50);
3806 dev_priv->rps.max_freq = pcu_mbox & 0xff;
3807 }
3808
3809 dev_priv->rps.power = HIGH_POWER; /* force a reset */
3810 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3811
3812 gen6_enable_rps_interrupts(dev);
3813
3814 rc6vids = 0;
3815 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
3816 if (IS_GEN6(dev) && ret) {
3817 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
3818 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
3819 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
3820 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
3821 rc6vids &= 0xffff00;
3822 rc6vids |= GEN6_ENCODE_RC6_VID(450);
3823 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
3824 if (ret)
3825 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
3826 }
3827
3828 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3829 }
3830
3831 static void __gen6_update_ring_freq(struct drm_device *dev)
3832 {
3833 struct drm_i915_private *dev_priv = dev->dev_private;
3834 int min_freq = 15;
3835 unsigned int gpu_freq;
3836 unsigned int max_ia_freq, min_ring_freq;
3837 int scaling_factor = 180;
3838 struct cpufreq_policy *policy;
3839
3840 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3841
3842 policy = cpufreq_cpu_get(0);
3843 if (policy) {
3844 max_ia_freq = policy->cpuinfo.max_freq;
3845 cpufreq_cpu_put(policy);
3846 } else {
3847 /*
3848 * Default to measured freq if none found, PCU will ensure we
3849 * don't go over
3850 */
3851 max_ia_freq = tsc_khz;
3852 }
3853
3854 /* Convert from kHz to MHz */
3855 max_ia_freq /= 1000;
3856
3857 min_ring_freq = I915_READ(DCLK) & 0xf;
3858 /* convert DDR frequency from units of 266.6MHz to bandwidth */
3859 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3860
3861 /*
3862 * For each potential GPU frequency, load a ring frequency we'd like
3863 * to use for memory access. We do this by specifying the IA frequency
3864 * the PCU should use as a reference to determine the ring frequency.
3865 */
3866 for (gpu_freq = dev_priv->rps.max_freq_softlimit; gpu_freq >= dev_priv->rps.min_freq_softlimit;
3867 gpu_freq--) {
3868 int diff = dev_priv->rps.max_freq_softlimit - gpu_freq;
3869 unsigned int ia_freq = 0, ring_freq = 0;
3870
3871 if (INTEL_INFO(dev)->gen >= 8) {
3872 /* max(2 * GT, DDR). NB: GT is 50MHz units */
3873 ring_freq = max(min_ring_freq, gpu_freq);
3874 } else if (IS_HASWELL(dev)) {
3875 ring_freq = mult_frac(gpu_freq, 5, 4);
3876 ring_freq = max(min_ring_freq, ring_freq);
3877 /* leave ia_freq as the default, chosen by cpufreq */
3878 } else {
3879 /* On older processors, there is no separate ring
3880 * clock domain, so in order to boost the bandwidth
3881 * of the ring, we need to upclock the CPU (ia_freq).
3882 *
3883 * For GPU frequencies less than 750MHz,
3884 * just use the lowest ring freq.
3885 */
3886 if (gpu_freq < min_freq)
3887 ia_freq = 800;
3888 else
3889 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
3890 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
3891 }
3892
3893 sandybridge_pcode_write(dev_priv,
3894 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3895 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
3896 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
3897 gpu_freq);
3898 }
3899 }
3900
3901 void gen6_update_ring_freq(struct drm_device *dev)
3902 {
3903 struct drm_i915_private *dev_priv = dev->dev_private;
3904
3905 if (INTEL_INFO(dev)->gen < 6 || IS_VALLEYVIEW(dev))
3906 return;
3907
3908 mutex_lock(&dev_priv->rps.hw_lock);
3909 __gen6_update_ring_freq(dev);
3910 mutex_unlock(&dev_priv->rps.hw_lock);
3911 }
3912
3913 static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
3914 {
3915 u32 val, rp0;
3916
3917 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
3918 rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & PUNIT_GPU_STATUS_MAX_FREQ_MASK;
3919
3920 return rp0;
3921 }
3922
3923 static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
3924 {
3925 u32 val, rpe;
3926
3927 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
3928 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
3929
3930 return rpe;
3931 }
3932
3933 static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
3934 {
3935 u32 val, rp1;
3936
3937 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
3938 rp1 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & PUNIT_GPU_STATUS_MAX_FREQ_MASK;
3939
3940 return rp1;
3941 }
3942
3943 static int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
3944 {
3945 u32 val, rpn;
3946
3947 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
3948 rpn = (val >> PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT) & PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK;
3949 return rpn;
3950 }
3951
3952 static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
3953 {
3954 u32 val, rp1;
3955
3956 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
3957
3958 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
3959
3960 return rp1;
3961 }
3962
3963 static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
3964 {
3965 u32 val, rp0;
3966
3967 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
3968
3969 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
3970 /* Clamp to max */
3971 rp0 = min_t(u32, rp0, 0xea);
3972
3973 return rp0;
3974 }
3975
3976 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
3977 {
3978 u32 val, rpe;
3979
3980 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
3981 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
3982 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
3983 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
3984
3985 return rpe;
3986 }
3987
3988 static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
3989 {
3990 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
3991 }
3992
3993 /* Check that the pctx buffer wasn't move under us. */
3994 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
3995 {
3996 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
3997
3998 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
3999 dev_priv->vlv_pctx->stolen->start);
4000 }
4001
4002
4003 /* Check that the pcbr address is not empty. */
4004 static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
4005 {
4006 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
4007
4008 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
4009 }
4010
4011 static void cherryview_setup_pctx(struct drm_device *dev)
4012 {
4013 struct drm_i915_private *dev_priv = dev->dev_private;
4014 unsigned long pctx_paddr, paddr;
4015 struct i915_gtt *gtt = &dev_priv->gtt;
4016 u32 pcbr;
4017 int pctx_size = 32*1024;
4018
4019 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4020
4021 pcbr = I915_READ(VLV_PCBR);
4022 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
4023 paddr = (dev_priv->mm.stolen_base +
4024 (gtt->stolen_size - pctx_size));
4025
4026 pctx_paddr = (paddr & (~4095));
4027 I915_WRITE(VLV_PCBR, pctx_paddr);
4028 }
4029 }
4030
4031 static void valleyview_setup_pctx(struct drm_device *dev)
4032 {
4033 struct drm_i915_private *dev_priv = dev->dev_private;
4034 struct drm_i915_gem_object *pctx;
4035 unsigned long pctx_paddr;
4036 u32 pcbr;
4037 int pctx_size = 24*1024;
4038
4039 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4040
4041 pcbr = I915_READ(VLV_PCBR);
4042 if (pcbr) {
4043 /* BIOS set it up already, grab the pre-alloc'd space */
4044 int pcbr_offset;
4045
4046 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
4047 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
4048 pcbr_offset,
4049 I915_GTT_OFFSET_NONE,
4050 pctx_size);
4051 goto out;
4052 }
4053
4054 /*
4055 * From the Gunit register HAS:
4056 * The Gfx driver is expected to program this register and ensure
4057 * proper allocation within Gfx stolen memory. For example, this
4058 * register should be programmed such than the PCBR range does not
4059 * overlap with other ranges, such as the frame buffer, protected
4060 * memory, or any other relevant ranges.
4061 */
4062 pctx = i915_gem_object_create_stolen(dev, pctx_size);
4063 if (!pctx) {
4064 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
4065 return;
4066 }
4067
4068 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
4069 I915_WRITE(VLV_PCBR, pctx_paddr);
4070
4071 out:
4072 dev_priv->vlv_pctx = pctx;
4073 }
4074
4075 static void valleyview_cleanup_pctx(struct drm_device *dev)
4076 {
4077 struct drm_i915_private *dev_priv = dev->dev_private;
4078
4079 if (WARN_ON(!dev_priv->vlv_pctx))
4080 return;
4081
4082 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
4083 dev_priv->vlv_pctx = NULL;
4084 }
4085
4086 static void valleyview_init_gt_powersave(struct drm_device *dev)
4087 {
4088 struct drm_i915_private *dev_priv = dev->dev_private;
4089
4090 valleyview_setup_pctx(dev);
4091
4092 mutex_lock(&dev_priv->rps.hw_lock);
4093
4094 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
4095 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
4096 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
4097 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4098 dev_priv->rps.max_freq);
4099
4100 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
4101 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
4102 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4103 dev_priv->rps.efficient_freq);
4104
4105 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
4106 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
4107 vlv_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
4108 dev_priv->rps.rp1_freq);
4109
4110 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
4111 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
4112 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4113 dev_priv->rps.min_freq);
4114
4115 /* Preserve min/max settings in case of re-init */
4116 if (dev_priv->rps.max_freq_softlimit == 0)
4117 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4118
4119 if (dev_priv->rps.min_freq_softlimit == 0)
4120 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
4121
4122 mutex_unlock(&dev_priv->rps.hw_lock);
4123 }
4124
4125 static void cherryview_init_gt_powersave(struct drm_device *dev)
4126 {
4127 struct drm_i915_private *dev_priv = dev->dev_private;
4128
4129 cherryview_setup_pctx(dev);
4130
4131 mutex_lock(&dev_priv->rps.hw_lock);
4132
4133 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
4134 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
4135 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
4136 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4137 dev_priv->rps.max_freq);
4138
4139 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
4140 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
4141 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4142 dev_priv->rps.efficient_freq);
4143
4144 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
4145 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
4146 vlv_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
4147 dev_priv->rps.rp1_freq);
4148
4149 dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv);
4150 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
4151 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4152 dev_priv->rps.min_freq);
4153
4154 /* Preserve min/max settings in case of re-init */
4155 if (dev_priv->rps.max_freq_softlimit == 0)
4156 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4157
4158 if (dev_priv->rps.min_freq_softlimit == 0)
4159 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
4160
4161 mutex_unlock(&dev_priv->rps.hw_lock);
4162 }
4163
4164 static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
4165 {
4166 valleyview_cleanup_pctx(dev);
4167 }
4168
4169 static void cherryview_enable_rps(struct drm_device *dev)
4170 {
4171 struct drm_i915_private *dev_priv = dev->dev_private;
4172 struct intel_engine_cs *ring;
4173 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
4174 int i;
4175
4176 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4177
4178 gtfifodbg = I915_READ(GTFIFODBG);
4179 if (gtfifodbg) {
4180 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4181 gtfifodbg);
4182 I915_WRITE(GTFIFODBG, gtfifodbg);
4183 }
4184
4185 cherryview_check_pctx(dev_priv);
4186
4187 /* 1a & 1b: Get forcewake during program sequence. Although the driver
4188 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4189 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
4190
4191 /* 2a: Program RC6 thresholds.*/
4192 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4193 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4194 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4195
4196 for_each_ring(ring, dev_priv, i)
4197 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4198 I915_WRITE(GEN6_RC_SLEEP, 0);
4199
4200 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
4201
4202 /* allows RC6 residency counter to work */
4203 I915_WRITE(VLV_COUNTER_CONTROL,
4204 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
4205 VLV_MEDIA_RC6_COUNT_EN |
4206 VLV_RENDER_RC6_COUNT_EN));
4207
4208 /* For now we assume BIOS is allocating and populating the PCBR */
4209 pcbr = I915_READ(VLV_PCBR);
4210
4211 DRM_DEBUG_DRIVER("PCBR offset : 0x%x\n", pcbr);
4212
4213 /* 3: Enable RC6 */
4214 if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
4215 (pcbr >> VLV_PCBR_ADDR_SHIFT))
4216 rc6_mode = GEN6_RC_CTL_EI_MODE(1);
4217
4218 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
4219
4220 /* 4 Program defaults and thresholds for RPS*/
4221 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
4222 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
4223 I915_WRITE(GEN6_RP_UP_EI, 66000);
4224 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
4225
4226 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4227
4228 /* WaDisablePwrmtrEvent:chv (pre-production hw) */
4229 I915_WRITE(0xA80C, I915_READ(0xA80C) & 0x00ffffff);
4230 I915_WRITE(0xA810, I915_READ(0xA810) & 0xffffff00);
4231
4232 /* 5: Enable RPS */
4233 I915_WRITE(GEN6_RP_CONTROL,
4234 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4235 GEN6_RP_MEDIA_IS_GFX | /* WaSetMaskForGfxBusyness:chv (pre-production hw ?) */
4236 GEN6_RP_ENABLE |
4237 GEN6_RP_UP_BUSY_AVG |
4238 GEN6_RP_DOWN_IDLE_AVG);
4239
4240 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4241
4242 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
4243 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
4244
4245 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
4246 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
4247 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
4248 dev_priv->rps.cur_freq);
4249
4250 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
4251 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4252 dev_priv->rps.efficient_freq);
4253
4254 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
4255
4256 gen8_enable_rps_interrupts(dev);
4257
4258 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
4259 }
4260
4261 static void valleyview_enable_rps(struct drm_device *dev)
4262 {
4263 struct drm_i915_private *dev_priv = dev->dev_private;
4264 struct intel_engine_cs *ring;
4265 u32 gtfifodbg, val, rc6_mode = 0;
4266 int i;
4267
4268 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4269
4270 valleyview_check_pctx(dev_priv);
4271
4272 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
4273 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4274 gtfifodbg);
4275 I915_WRITE(GTFIFODBG, gtfifodbg);
4276 }
4277
4278 /* If VLV, Forcewake all wells, else re-direct to regular path */
4279 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
4280
4281 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
4282 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
4283 I915_WRITE(GEN6_RP_UP_EI, 66000);
4284 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
4285
4286 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4287 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 0xf4240);
4288
4289 I915_WRITE(GEN6_RP_CONTROL,
4290 GEN6_RP_MEDIA_TURBO |
4291 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4292 GEN6_RP_MEDIA_IS_GFX |
4293 GEN6_RP_ENABLE |
4294 GEN6_RP_UP_BUSY_AVG |
4295 GEN6_RP_DOWN_IDLE_CONT);
4296
4297 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
4298 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4299 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4300
4301 for_each_ring(ring, dev_priv, i)
4302 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4303
4304 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
4305
4306 /* allows RC6 residency counter to work */
4307 I915_WRITE(VLV_COUNTER_CONTROL,
4308 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
4309 VLV_RENDER_RC0_COUNT_EN |
4310 VLV_MEDIA_RC6_COUNT_EN |
4311 VLV_RENDER_RC6_COUNT_EN));
4312
4313 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4314 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
4315
4316 intel_print_rc6_info(dev, rc6_mode);
4317
4318 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
4319
4320 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4321
4322 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
4323 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
4324
4325 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
4326 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
4327 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
4328 dev_priv->rps.cur_freq);
4329
4330 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
4331 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4332 dev_priv->rps.efficient_freq);
4333
4334 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
4335
4336 gen6_enable_rps_interrupts(dev);
4337
4338 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
4339 }
4340
4341 void ironlake_teardown_rc6(struct drm_device *dev)
4342 {
4343 struct drm_i915_private *dev_priv = dev->dev_private;
4344
4345 if (dev_priv->ips.renderctx) {
4346 i915_gem_object_ggtt_unpin(dev_priv->ips.renderctx);
4347 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
4348 dev_priv->ips.renderctx = NULL;
4349 }
4350
4351 if (dev_priv->ips.pwrctx) {
4352 i915_gem_object_ggtt_unpin(dev_priv->ips.pwrctx);
4353 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
4354 dev_priv->ips.pwrctx = NULL;
4355 }
4356 }
4357
4358 static void ironlake_disable_rc6(struct drm_device *dev)
4359 {
4360 struct drm_i915_private *dev_priv = dev->dev_private;
4361
4362 if (I915_READ(PWRCTXA)) {
4363 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
4364 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
4365 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
4366 50);
4367
4368 I915_WRITE(PWRCTXA, 0);
4369 POSTING_READ(PWRCTXA);
4370
4371 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
4372 POSTING_READ(RSTDBYCTL);
4373 }
4374 }
4375
4376 static int ironlake_setup_rc6(struct drm_device *dev)
4377 {
4378 struct drm_i915_private *dev_priv = dev->dev_private;
4379
4380 if (dev_priv->ips.renderctx == NULL)
4381 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
4382 if (!dev_priv->ips.renderctx)
4383 return -ENOMEM;
4384
4385 if (dev_priv->ips.pwrctx == NULL)
4386 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
4387 if (!dev_priv->ips.pwrctx) {
4388 ironlake_teardown_rc6(dev);
4389 return -ENOMEM;
4390 }
4391
4392 return 0;
4393 }
4394
4395 static void ironlake_enable_rc6(struct drm_device *dev)
4396 {
4397 struct drm_i915_private *dev_priv = dev->dev_private;
4398 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
4399 bool was_interruptible;
4400 int ret;
4401
4402 /* rc6 disabled by default due to repeated reports of hanging during
4403 * boot and resume.
4404 */
4405 if (!intel_enable_rc6(dev))
4406 return;
4407
4408 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4409
4410 ret = ironlake_setup_rc6(dev);
4411 if (ret)
4412 return;
4413
4414 was_interruptible = dev_priv->mm.interruptible;
4415 dev_priv->mm.interruptible = false;
4416
4417 /*
4418 * GPU can automatically power down the render unit if given a page
4419 * to save state.
4420 */
4421 ret = intel_ring_begin(ring, 6);
4422 if (ret) {
4423 ironlake_teardown_rc6(dev);
4424 dev_priv->mm.interruptible = was_interruptible;
4425 return;
4426 }
4427
4428 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
4429 intel_ring_emit(ring, MI_SET_CONTEXT);
4430 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) |
4431 MI_MM_SPACE_GTT |
4432 MI_SAVE_EXT_STATE_EN |
4433 MI_RESTORE_EXT_STATE_EN |
4434 MI_RESTORE_INHIBIT);
4435 intel_ring_emit(ring, MI_SUSPEND_FLUSH);
4436 intel_ring_emit(ring, MI_NOOP);
4437 intel_ring_emit(ring, MI_FLUSH);
4438 intel_ring_advance(ring);
4439
4440 /*
4441 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
4442 * does an implicit flush, combined with MI_FLUSH above, it should be
4443 * safe to assume that renderctx is valid
4444 */
4445 ret = intel_ring_idle(ring);
4446 dev_priv->mm.interruptible = was_interruptible;
4447 if (ret) {
4448 DRM_ERROR("failed to enable ironlake power savings\n");
4449 ironlake_teardown_rc6(dev);
4450 return;
4451 }
4452
4453 I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN);
4454 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
4455
4456 intel_print_rc6_info(dev, GEN6_RC_CTL_RC6_ENABLE);
4457 }
4458
4459 static unsigned long intel_pxfreq(u32 vidfreq)
4460 {
4461 unsigned long freq;
4462 int div = (vidfreq & 0x3f0000) >> 16;
4463 int post = (vidfreq & 0x3000) >> 12;
4464 int pre = (vidfreq & 0x7);
4465
4466 if (!pre)
4467 return 0;
4468
4469 freq = ((div * 133333) / ((1<<post) * pre));
4470
4471 return freq;
4472 }
4473
4474 static const struct cparams {
4475 u16 i;
4476 u16 t;
4477 u16 m;
4478 u16 c;
4479 } cparams[] = {
4480 { 1, 1333, 301, 28664 },
4481 { 1, 1066, 294, 24460 },
4482 { 1, 800, 294, 25192 },
4483 { 0, 1333, 276, 27605 },
4484 { 0, 1066, 276, 27605 },
4485 { 0, 800, 231, 23784 },
4486 };
4487
4488 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
4489 {
4490 u64 total_count, diff, ret;
4491 u32 count1, count2, count3, m = 0, c = 0;
4492 unsigned long now = jiffies_to_msecs(jiffies), diff1;
4493 int i;
4494
4495 assert_spin_locked(&mchdev_lock);
4496
4497 diff1 = now - dev_priv->ips.last_time1;
4498
4499 /* Prevent division-by-zero if we are asking too fast.
4500 * Also, we don't get interesting results if we are polling
4501 * faster than once in 10ms, so just return the saved value
4502 * in such cases.
4503 */
4504 if (diff1 <= 10)
4505 return dev_priv->ips.chipset_power;
4506
4507 count1 = I915_READ(DMIEC);
4508 count2 = I915_READ(DDREC);
4509 count3 = I915_READ(CSIEC);
4510
4511 total_count = count1 + count2 + count3;
4512
4513 /* FIXME: handle per-counter overflow */
4514 if (total_count < dev_priv->ips.last_count1) {
4515 diff = ~0UL - dev_priv->ips.last_count1;
4516 diff += total_count;
4517 } else {
4518 diff = total_count - dev_priv->ips.last_count1;
4519 }
4520
4521 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
4522 if (cparams[i].i == dev_priv->ips.c_m &&
4523 cparams[i].t == dev_priv->ips.r_t) {
4524 m = cparams[i].m;
4525 c = cparams[i].c;
4526 break;
4527 }
4528 }
4529
4530 diff = div_u64(diff, diff1);
4531 ret = ((m * diff) + c);
4532 ret = div_u64(ret, 10);
4533
4534 dev_priv->ips.last_count1 = total_count;
4535 dev_priv->ips.last_time1 = now;
4536
4537 dev_priv->ips.chipset_power = ret;
4538
4539 return ret;
4540 }
4541
4542 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
4543 {
4544 struct drm_device *dev = dev_priv->dev;
4545 unsigned long val;
4546
4547 if (INTEL_INFO(dev)->gen != 5)
4548 return 0;
4549
4550 spin_lock_irq(&mchdev_lock);
4551
4552 val = __i915_chipset_val(dev_priv);
4553
4554 spin_unlock_irq(&mchdev_lock);
4555
4556 return val;
4557 }
4558
4559 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
4560 {
4561 unsigned long m, x, b;
4562 u32 tsfs;
4563
4564 tsfs = I915_READ(TSFS);
4565
4566 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
4567 x = I915_READ8(TR1);
4568
4569 b = tsfs & TSFS_INTR_MASK;
4570
4571 return ((m * x) / 127) - b;
4572 }
4573
4574 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
4575 {
4576 struct drm_device *dev = dev_priv->dev;
4577 static const struct v_table {
4578 u16 vd; /* in .1 mil */
4579 u16 vm; /* in .1 mil */
4580 } v_table[] = {
4581 { 0, 0, },
4582 { 375, 0, },
4583 { 500, 0, },
4584 { 625, 0, },
4585 { 750, 0, },
4586 { 875, 0, },
4587 { 1000, 0, },
4588 { 1125, 0, },
4589 { 4125, 3000, },
4590 { 4125, 3000, },
4591 { 4125, 3000, },
4592 { 4125, 3000, },
4593 { 4125, 3000, },
4594 { 4125, 3000, },
4595 { 4125, 3000, },
4596 { 4125, 3000, },
4597 { 4125, 3000, },
4598 { 4125, 3000, },
4599 { 4125, 3000, },
4600 { 4125, 3000, },
4601 { 4125, 3000, },
4602 { 4125, 3000, },
4603 { 4125, 3000, },
4604 { 4125, 3000, },
4605 { 4125, 3000, },
4606 { 4125, 3000, },
4607 { 4125, 3000, },
4608 { 4125, 3000, },
4609 { 4125, 3000, },
4610 { 4125, 3000, },
4611 { 4125, 3000, },
4612 { 4125, 3000, },
4613 { 4250, 3125, },
4614 { 4375, 3250, },
4615 { 4500, 3375, },
4616 { 4625, 3500, },
4617 { 4750, 3625, },
4618 { 4875, 3750, },
4619 { 5000, 3875, },
4620 { 5125, 4000, },
4621 { 5250, 4125, },
4622 { 5375, 4250, },
4623 { 5500, 4375, },
4624 { 5625, 4500, },
4625 { 5750, 4625, },
4626 { 5875, 4750, },
4627 { 6000, 4875, },
4628 { 6125, 5000, },
4629 { 6250, 5125, },
4630 { 6375, 5250, },
4631 { 6500, 5375, },
4632 { 6625, 5500, },
4633 { 6750, 5625, },
4634 { 6875, 5750, },
4635 { 7000, 5875, },
4636 { 7125, 6000, },
4637 { 7250, 6125, },
4638 { 7375, 6250, },
4639 { 7500, 6375, },
4640 { 7625, 6500, },
4641 { 7750, 6625, },
4642 { 7875, 6750, },
4643 { 8000, 6875, },
4644 { 8125, 7000, },
4645 { 8250, 7125, },
4646 { 8375, 7250, },
4647 { 8500, 7375, },
4648 { 8625, 7500, },
4649 { 8750, 7625, },
4650 { 8875, 7750, },
4651 { 9000, 7875, },
4652 { 9125, 8000, },
4653 { 9250, 8125, },
4654 { 9375, 8250, },
4655 { 9500, 8375, },
4656 { 9625, 8500, },
4657 { 9750, 8625, },
4658 { 9875, 8750, },
4659 { 10000, 8875, },
4660 { 10125, 9000, },
4661 { 10250, 9125, },
4662 { 10375, 9250, },
4663 { 10500, 9375, },
4664 { 10625, 9500, },
4665 { 10750, 9625, },
4666 { 10875, 9750, },
4667 { 11000, 9875, },
4668 { 11125, 10000, },
4669 { 11250, 10125, },
4670 { 11375, 10250, },
4671 { 11500, 10375, },
4672 { 11625, 10500, },
4673 { 11750, 10625, },
4674 { 11875, 10750, },
4675 { 12000, 10875, },
4676 { 12125, 11000, },
4677 { 12250, 11125, },
4678 { 12375, 11250, },
4679 { 12500, 11375, },
4680 { 12625, 11500, },
4681 { 12750, 11625, },
4682 { 12875, 11750, },
4683 { 13000, 11875, },
4684 { 13125, 12000, },
4685 { 13250, 12125, },
4686 { 13375, 12250, },
4687 { 13500, 12375, },
4688 { 13625, 12500, },
4689 { 13750, 12625, },
4690 { 13875, 12750, },
4691 { 14000, 12875, },
4692 { 14125, 13000, },
4693 { 14250, 13125, },
4694 { 14375, 13250, },
4695 { 14500, 13375, },
4696 { 14625, 13500, },
4697 { 14750, 13625, },
4698 { 14875, 13750, },
4699 { 15000, 13875, },
4700 { 15125, 14000, },
4701 { 15250, 14125, },
4702 { 15375, 14250, },
4703 { 15500, 14375, },
4704 { 15625, 14500, },
4705 { 15750, 14625, },
4706 { 15875, 14750, },
4707 { 16000, 14875, },
4708 { 16125, 15000, },
4709 };
4710 if (INTEL_INFO(dev)->is_mobile)
4711 return v_table[pxvid].vm;
4712 else
4713 return v_table[pxvid].vd;
4714 }
4715
4716 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
4717 {
4718 u64 now, diff, diffms;
4719 u32 count;
4720
4721 assert_spin_locked(&mchdev_lock);
4722
4723 now = ktime_get_raw_ns();
4724 diffms = now - dev_priv->ips.last_time2;
4725 do_div(diffms, NSEC_PER_MSEC);
4726
4727 /* Don't divide by 0 */
4728 if (!diffms)
4729 return;
4730
4731 count = I915_READ(GFXEC);
4732
4733 if (count < dev_priv->ips.last_count2) {
4734 diff = ~0UL - dev_priv->ips.last_count2;
4735 diff += count;
4736 } else {
4737 diff = count - dev_priv->ips.last_count2;
4738 }
4739
4740 dev_priv->ips.last_count2 = count;
4741 dev_priv->ips.last_time2 = now;
4742
4743 /* More magic constants... */
4744 diff = diff * 1181;
4745 diff = div_u64(diff, diffms * 10);
4746 dev_priv->ips.gfx_power = diff;
4747 }
4748
4749 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
4750 {
4751 struct drm_device *dev = dev_priv->dev;
4752
4753 if (INTEL_INFO(dev)->gen != 5)
4754 return;
4755
4756 spin_lock_irq(&mchdev_lock);
4757
4758 __i915_update_gfx_val(dev_priv);
4759
4760 spin_unlock_irq(&mchdev_lock);
4761 }
4762
4763 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
4764 {
4765 unsigned long t, corr, state1, corr2, state2;
4766 u32 pxvid, ext_v;
4767
4768 assert_spin_locked(&mchdev_lock);
4769
4770 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_freq * 4));
4771 pxvid = (pxvid >> 24) & 0x7f;
4772 ext_v = pvid_to_extvid(dev_priv, pxvid);
4773
4774 state1 = ext_v;
4775
4776 t = i915_mch_val(dev_priv);
4777
4778 /* Revel in the empirically derived constants */
4779
4780 /* Correction factor in 1/100000 units */
4781 if (t > 80)
4782 corr = ((t * 2349) + 135940);
4783 else if (t >= 50)
4784 corr = ((t * 964) + 29317);
4785 else /* < 50 */
4786 corr = ((t * 301) + 1004);
4787
4788 corr = corr * ((150142 * state1) / 10000 - 78642);
4789 corr /= 100000;
4790 corr2 = (corr * dev_priv->ips.corr);
4791
4792 state2 = (corr2 * state1) / 10000;
4793 state2 /= 100; /* convert to mW */
4794
4795 __i915_update_gfx_val(dev_priv);
4796
4797 return dev_priv->ips.gfx_power + state2;
4798 }
4799
4800 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
4801 {
4802 struct drm_device *dev = dev_priv->dev;
4803 unsigned long val;
4804
4805 if (INTEL_INFO(dev)->gen != 5)
4806 return 0;
4807
4808 spin_lock_irq(&mchdev_lock);
4809
4810 val = __i915_gfx_val(dev_priv);
4811
4812 spin_unlock_irq(&mchdev_lock);
4813
4814 return val;
4815 }
4816
4817 /**
4818 * i915_read_mch_val - return value for IPS use
4819 *
4820 * Calculate and return a value for the IPS driver to use when deciding whether
4821 * we have thermal and power headroom to increase CPU or GPU power budget.
4822 */
4823 unsigned long i915_read_mch_val(void)
4824 {
4825 struct drm_i915_private *dev_priv;
4826 unsigned long chipset_val, graphics_val, ret = 0;
4827
4828 spin_lock_irq(&mchdev_lock);
4829 if (!i915_mch_dev)
4830 goto out_unlock;
4831 dev_priv = i915_mch_dev;
4832
4833 chipset_val = __i915_chipset_val(dev_priv);
4834 graphics_val = __i915_gfx_val(dev_priv);
4835
4836 ret = chipset_val + graphics_val;
4837
4838 out_unlock:
4839 spin_unlock_irq(&mchdev_lock);
4840
4841 return ret;
4842 }
4843 EXPORT_SYMBOL_GPL(i915_read_mch_val);
4844
4845 /**
4846 * i915_gpu_raise - raise GPU frequency limit
4847 *
4848 * Raise the limit; IPS indicates we have thermal headroom.
4849 */
4850 bool i915_gpu_raise(void)
4851 {
4852 struct drm_i915_private *dev_priv;
4853 bool ret = true;
4854
4855 spin_lock_irq(&mchdev_lock);
4856 if (!i915_mch_dev) {
4857 ret = false;
4858 goto out_unlock;
4859 }
4860 dev_priv = i915_mch_dev;
4861
4862 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
4863 dev_priv->ips.max_delay--;
4864
4865 out_unlock:
4866 spin_unlock_irq(&mchdev_lock);
4867
4868 return ret;
4869 }
4870 EXPORT_SYMBOL_GPL(i915_gpu_raise);
4871
4872 /**
4873 * i915_gpu_lower - lower GPU frequency limit
4874 *
4875 * IPS indicates we're close to a thermal limit, so throttle back the GPU
4876 * frequency maximum.
4877 */
4878 bool i915_gpu_lower(void)
4879 {
4880 struct drm_i915_private *dev_priv;
4881 bool ret = true;
4882
4883 spin_lock_irq(&mchdev_lock);
4884 if (!i915_mch_dev) {
4885 ret = false;
4886 goto out_unlock;
4887 }
4888 dev_priv = i915_mch_dev;
4889
4890 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
4891 dev_priv->ips.max_delay++;
4892
4893 out_unlock:
4894 spin_unlock_irq(&mchdev_lock);
4895
4896 return ret;
4897 }
4898 EXPORT_SYMBOL_GPL(i915_gpu_lower);
4899
4900 /**
4901 * i915_gpu_busy - indicate GPU business to IPS
4902 *
4903 * Tell the IPS driver whether or not the GPU is busy.
4904 */
4905 bool i915_gpu_busy(void)
4906 {
4907 struct drm_i915_private *dev_priv;
4908 struct intel_engine_cs *ring;
4909 bool ret = false;
4910 int i;
4911
4912 spin_lock_irq(&mchdev_lock);
4913 if (!i915_mch_dev)
4914 goto out_unlock;
4915 dev_priv = i915_mch_dev;
4916
4917 for_each_ring(ring, dev_priv, i)
4918 ret |= !list_empty(&ring->request_list);
4919
4920 out_unlock:
4921 spin_unlock_irq(&mchdev_lock);
4922
4923 return ret;
4924 }
4925 EXPORT_SYMBOL_GPL(i915_gpu_busy);
4926
4927 /**
4928 * i915_gpu_turbo_disable - disable graphics turbo
4929 *
4930 * Disable graphics turbo by resetting the max frequency and setting the
4931 * current frequency to the default.
4932 */
4933 bool i915_gpu_turbo_disable(void)
4934 {
4935 struct drm_i915_private *dev_priv;
4936 bool ret = true;
4937
4938 spin_lock_irq(&mchdev_lock);
4939 if (!i915_mch_dev) {
4940 ret = false;
4941 goto out_unlock;
4942 }
4943 dev_priv = i915_mch_dev;
4944
4945 dev_priv->ips.max_delay = dev_priv->ips.fstart;
4946
4947 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
4948 ret = false;
4949
4950 out_unlock:
4951 spin_unlock_irq(&mchdev_lock);
4952
4953 return ret;
4954 }
4955 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
4956
4957 /**
4958 * Tells the intel_ips driver that the i915 driver is now loaded, if
4959 * IPS got loaded first.
4960 *
4961 * This awkward dance is so that neither module has to depend on the
4962 * other in order for IPS to do the appropriate communication of
4963 * GPU turbo limits to i915.
4964 */
4965 static void
4966 ips_ping_for_i915_load(void)
4967 {
4968 void (*link)(void);
4969
4970 link = symbol_get(ips_link_to_i915_driver);
4971 if (link) {
4972 link();
4973 symbol_put(ips_link_to_i915_driver);
4974 }
4975 }
4976
4977 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
4978 {
4979 /* We only register the i915 ips part with intel-ips once everything is
4980 * set up, to avoid intel-ips sneaking in and reading bogus values. */
4981 spin_lock_irq(&mchdev_lock);
4982 i915_mch_dev = dev_priv;
4983 spin_unlock_irq(&mchdev_lock);
4984
4985 ips_ping_for_i915_load();
4986 }
4987
4988 void intel_gpu_ips_teardown(void)
4989 {
4990 spin_lock_irq(&mchdev_lock);
4991 i915_mch_dev = NULL;
4992 spin_unlock_irq(&mchdev_lock);
4993 }
4994
4995 static void intel_init_emon(struct drm_device *dev)
4996 {
4997 struct drm_i915_private *dev_priv = dev->dev_private;
4998 u32 lcfuse;
4999 u8 pxw[16];
5000 int i;
5001
5002 /* Disable to program */
5003 I915_WRITE(ECR, 0);
5004 POSTING_READ(ECR);
5005
5006 /* Program energy weights for various events */
5007 I915_WRITE(SDEW, 0x15040d00);
5008 I915_WRITE(CSIEW0, 0x007f0000);
5009 I915_WRITE(CSIEW1, 0x1e220004);
5010 I915_WRITE(CSIEW2, 0x04000004);
5011
5012 for (i = 0; i < 5; i++)
5013 I915_WRITE(PEW + (i * 4), 0);
5014 for (i = 0; i < 3; i++)
5015 I915_WRITE(DEW + (i * 4), 0);
5016
5017 /* Program P-state weights to account for frequency power adjustment */
5018 for (i = 0; i < 16; i++) {
5019 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
5020 unsigned long freq = intel_pxfreq(pxvidfreq);
5021 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5022 PXVFREQ_PX_SHIFT;
5023 unsigned long val;
5024
5025 val = vid * vid;
5026 val *= (freq / 1000);
5027 val *= 255;
5028 val /= (127*127*900);
5029 if (val > 0xff)
5030 DRM_ERROR("bad pxval: %ld\n", val);
5031 pxw[i] = val;
5032 }
5033 /* Render standby states get 0 weight */
5034 pxw[14] = 0;
5035 pxw[15] = 0;
5036
5037 for (i = 0; i < 4; i++) {
5038 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5039 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
5040 I915_WRITE(PXW + (i * 4), val);
5041 }
5042
5043 /* Adjust magic regs to magic values (more experimental results) */
5044 I915_WRITE(OGW0, 0);
5045 I915_WRITE(OGW1, 0);
5046 I915_WRITE(EG0, 0x00007f00);
5047 I915_WRITE(EG1, 0x0000000e);
5048 I915_WRITE(EG2, 0x000e0000);
5049 I915_WRITE(EG3, 0x68000300);
5050 I915_WRITE(EG4, 0x42000000);
5051 I915_WRITE(EG5, 0x00140031);
5052 I915_WRITE(EG6, 0);
5053 I915_WRITE(EG7, 0);
5054
5055 for (i = 0; i < 8; i++)
5056 I915_WRITE(PXWL + (i * 4), 0);
5057
5058 /* Enable PMON + select events */
5059 I915_WRITE(ECR, 0x80000019);
5060
5061 lcfuse = I915_READ(LCFUSE02);
5062
5063 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
5064 }
5065
5066 void intel_init_gt_powersave(struct drm_device *dev)
5067 {
5068 i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
5069
5070 if (IS_CHERRYVIEW(dev))
5071 cherryview_init_gt_powersave(dev);
5072 else if (IS_VALLEYVIEW(dev))
5073 valleyview_init_gt_powersave(dev);
5074 }
5075
5076 void intel_cleanup_gt_powersave(struct drm_device *dev)
5077 {
5078 if (IS_CHERRYVIEW(dev))
5079 return;
5080 else if (IS_VALLEYVIEW(dev))
5081 valleyview_cleanup_gt_powersave(dev);
5082 }
5083
5084 /**
5085 * intel_suspend_gt_powersave - suspend PM work and helper threads
5086 * @dev: drm device
5087 *
5088 * We don't want to disable RC6 or other features here, we just want
5089 * to make sure any work we've queued has finished and won't bother
5090 * us while we're suspended.
5091 */
5092 void intel_suspend_gt_powersave(struct drm_device *dev)
5093 {
5094 struct drm_i915_private *dev_priv = dev->dev_private;
5095
5096 /* Interrupts should be disabled already to avoid re-arming. */
5097 WARN_ON(intel_irqs_enabled(dev_priv));
5098
5099 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
5100
5101 cancel_work_sync(&dev_priv->rps.work);
5102
5103 /* Force GPU to min freq during suspend */
5104 gen6_rps_idle(dev_priv);
5105 }
5106
5107 void intel_disable_gt_powersave(struct drm_device *dev)
5108 {
5109 struct drm_i915_private *dev_priv = dev->dev_private;
5110
5111 /* Interrupts should be disabled already to avoid re-arming. */
5112 WARN_ON(intel_irqs_enabled(dev_priv));
5113
5114 if (IS_IRONLAKE_M(dev)) {
5115 ironlake_disable_drps(dev);
5116 ironlake_disable_rc6(dev);
5117 } else if (INTEL_INFO(dev)->gen >= 6) {
5118 intel_suspend_gt_powersave(dev);
5119
5120 mutex_lock(&dev_priv->rps.hw_lock);
5121 if (IS_CHERRYVIEW(dev))
5122 cherryview_disable_rps(dev);
5123 else if (IS_VALLEYVIEW(dev))
5124 valleyview_disable_rps(dev);
5125 else
5126 gen6_disable_rps(dev);
5127 dev_priv->rps.enabled = false;
5128 mutex_unlock(&dev_priv->rps.hw_lock);
5129 }
5130 }
5131
5132 static void intel_gen6_powersave_work(struct work_struct *work)
5133 {
5134 struct drm_i915_private *dev_priv =
5135 container_of(work, struct drm_i915_private,
5136 rps.delayed_resume_work.work);
5137 struct drm_device *dev = dev_priv->dev;
5138
5139 mutex_lock(&dev_priv->rps.hw_lock);
5140
5141 if (IS_CHERRYVIEW(dev)) {
5142 cherryview_enable_rps(dev);
5143 } else if (IS_VALLEYVIEW(dev)) {
5144 valleyview_enable_rps(dev);
5145 } else if (IS_BROADWELL(dev)) {
5146 gen8_enable_rps(dev);
5147 __gen6_update_ring_freq(dev);
5148 } else {
5149 gen6_enable_rps(dev);
5150 __gen6_update_ring_freq(dev);
5151 }
5152 dev_priv->rps.enabled = true;
5153 mutex_unlock(&dev_priv->rps.hw_lock);
5154
5155 intel_runtime_pm_put(dev_priv);
5156 }
5157
5158 void intel_enable_gt_powersave(struct drm_device *dev)
5159 {
5160 struct drm_i915_private *dev_priv = dev->dev_private;
5161
5162 if (IS_IRONLAKE_M(dev)) {
5163 mutex_lock(&dev->struct_mutex);
5164 ironlake_enable_drps(dev);
5165 ironlake_enable_rc6(dev);
5166 intel_init_emon(dev);
5167 mutex_unlock(&dev->struct_mutex);
5168 } else if (INTEL_INFO(dev)->gen >= 6) {
5169 /*
5170 * PCU communication is slow and this doesn't need to be
5171 * done at any specific time, so do this out of our fast path
5172 * to make resume and init faster.
5173 *
5174 * We depend on the HW RC6 power context save/restore
5175 * mechanism when entering D3 through runtime PM suspend. So
5176 * disable RPM until RPS/RC6 is properly setup. We can only
5177 * get here via the driver load/system resume/runtime resume
5178 * paths, so the _noresume version is enough (and in case of
5179 * runtime resume it's necessary).
5180 */
5181 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
5182 round_jiffies_up_relative(HZ)))
5183 intel_runtime_pm_get_noresume(dev_priv);
5184 }
5185 }
5186
5187 void intel_reset_gt_powersave(struct drm_device *dev)
5188 {
5189 struct drm_i915_private *dev_priv = dev->dev_private;
5190
5191 dev_priv->rps.enabled = false;
5192 intel_enable_gt_powersave(dev);
5193 }
5194
5195 static void ibx_init_clock_gating(struct drm_device *dev)
5196 {
5197 struct drm_i915_private *dev_priv = dev->dev_private;
5198
5199 /*
5200 * On Ibex Peak and Cougar Point, we need to disable clock
5201 * gating for the panel power sequencer or it will fail to
5202 * start up when no ports are active.
5203 */
5204 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
5205 }
5206
5207 static void g4x_disable_trickle_feed(struct drm_device *dev)
5208 {
5209 struct drm_i915_private *dev_priv = dev->dev_private;
5210 int pipe;
5211
5212 for_each_pipe(pipe) {
5213 I915_WRITE(DSPCNTR(pipe),
5214 I915_READ(DSPCNTR(pipe)) |
5215 DISPPLANE_TRICKLE_FEED_DISABLE);
5216 intel_flush_primary_plane(dev_priv, pipe);
5217 }
5218 }
5219
5220 static void ilk_init_lp_watermarks(struct drm_device *dev)
5221 {
5222 struct drm_i915_private *dev_priv = dev->dev_private;
5223
5224 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
5225 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
5226 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
5227
5228 /*
5229 * Don't touch WM1S_LP_EN here.
5230 * Doing so could cause underruns.
5231 */
5232 }
5233
5234 static void ironlake_init_clock_gating(struct drm_device *dev)
5235 {
5236 struct drm_i915_private *dev_priv = dev->dev_private;
5237 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
5238
5239 /*
5240 * Required for FBC
5241 * WaFbcDisableDpfcClockGating:ilk
5242 */
5243 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
5244 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
5245 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
5246
5247 I915_WRITE(PCH_3DCGDIS0,
5248 MARIUNIT_CLOCK_GATE_DISABLE |
5249 SVSMUNIT_CLOCK_GATE_DISABLE);
5250 I915_WRITE(PCH_3DCGDIS1,
5251 VFMUNIT_CLOCK_GATE_DISABLE);
5252
5253 /*
5254 * According to the spec the following bits should be set in
5255 * order to enable memory self-refresh
5256 * The bit 22/21 of 0x42004
5257 * The bit 5 of 0x42020
5258 * The bit 15 of 0x45000
5259 */
5260 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5261 (I915_READ(ILK_DISPLAY_CHICKEN2) |
5262 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
5263 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
5264 I915_WRITE(DISP_ARB_CTL,
5265 (I915_READ(DISP_ARB_CTL) |
5266 DISP_FBC_WM_DIS));
5267
5268 ilk_init_lp_watermarks(dev);
5269
5270 /*
5271 * Based on the document from hardware guys the following bits
5272 * should be set unconditionally in order to enable FBC.
5273 * The bit 22 of 0x42000
5274 * The bit 22 of 0x42004
5275 * The bit 7,8,9 of 0x42020.
5276 */
5277 if (IS_IRONLAKE_M(dev)) {
5278 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
5279 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5280 I915_READ(ILK_DISPLAY_CHICKEN1) |
5281 ILK_FBCQ_DIS);
5282 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5283 I915_READ(ILK_DISPLAY_CHICKEN2) |
5284 ILK_DPARB_GATE);
5285 }
5286
5287 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
5288
5289 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5290 I915_READ(ILK_DISPLAY_CHICKEN2) |
5291 ILK_ELPIN_409_SELECT);
5292 I915_WRITE(_3D_CHICKEN2,
5293 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
5294 _3D_CHICKEN2_WM_READ_PIPELINED);
5295
5296 /* WaDisableRenderCachePipelinedFlush:ilk */
5297 I915_WRITE(CACHE_MODE_0,
5298 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
5299
5300 /* WaDisable_RenderCache_OperationalFlush:ilk */
5301 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5302
5303 g4x_disable_trickle_feed(dev);
5304
5305 ibx_init_clock_gating(dev);
5306 }
5307
5308 static void cpt_init_clock_gating(struct drm_device *dev)
5309 {
5310 struct drm_i915_private *dev_priv = dev->dev_private;
5311 int pipe;
5312 uint32_t val;
5313
5314 /*
5315 * On Ibex Peak and Cougar Point, we need to disable clock
5316 * gating for the panel power sequencer or it will fail to
5317 * start up when no ports are active.
5318 */
5319 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
5320 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
5321 PCH_CPUNIT_CLOCK_GATE_DISABLE);
5322 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
5323 DPLS_EDP_PPS_FIX_DIS);
5324 /* The below fixes the weird display corruption, a few pixels shifted
5325 * downward, on (only) LVDS of some HP laptops with IVY.
5326 */
5327 for_each_pipe(pipe) {
5328 val = I915_READ(TRANS_CHICKEN2(pipe));
5329 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
5330 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
5331 if (dev_priv->vbt.fdi_rx_polarity_inverted)
5332 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
5333 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
5334 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
5335 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
5336 I915_WRITE(TRANS_CHICKEN2(pipe), val);
5337 }
5338 /* WADP0ClockGatingDisable */
5339 for_each_pipe(pipe) {
5340 I915_WRITE(TRANS_CHICKEN1(pipe),
5341 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
5342 }
5343 }
5344
5345 static void gen6_check_mch_setup(struct drm_device *dev)
5346 {
5347 struct drm_i915_private *dev_priv = dev->dev_private;
5348 uint32_t tmp;
5349
5350 tmp = I915_READ(MCH_SSKPD);
5351 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
5352 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
5353 tmp);
5354 }
5355
5356 static void gen6_init_clock_gating(struct drm_device *dev)
5357 {
5358 struct drm_i915_private *dev_priv = dev->dev_private;
5359 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
5360
5361 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
5362
5363 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5364 I915_READ(ILK_DISPLAY_CHICKEN2) |
5365 ILK_ELPIN_409_SELECT);
5366
5367 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
5368 I915_WRITE(_3D_CHICKEN,
5369 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
5370
5371 /* WaSetupGtModeTdRowDispatch:snb */
5372 if (IS_SNB_GT1(dev))
5373 I915_WRITE(GEN6_GT_MODE,
5374 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
5375
5376 /* WaDisable_RenderCache_OperationalFlush:snb */
5377 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5378
5379 /*
5380 * BSpec recoomends 8x4 when MSAA is used,
5381 * however in practice 16x4 seems fastest.
5382 *
5383 * Note that PS/WM thread counts depend on the WIZ hashing
5384 * disable bit, which we don't touch here, but it's good
5385 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5386 */
5387 I915_WRITE(GEN6_GT_MODE,
5388 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5389
5390 ilk_init_lp_watermarks(dev);
5391
5392 I915_WRITE(CACHE_MODE_0,
5393 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
5394
5395 I915_WRITE(GEN6_UCGCTL1,
5396 I915_READ(GEN6_UCGCTL1) |
5397 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
5398 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
5399
5400 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5401 * gating disable must be set. Failure to set it results in
5402 * flickering pixels due to Z write ordering failures after
5403 * some amount of runtime in the Mesa "fire" demo, and Unigine
5404 * Sanctuary and Tropics, and apparently anything else with
5405 * alpha test or pixel discard.
5406 *
5407 * According to the spec, bit 11 (RCCUNIT) must also be set,
5408 * but we didn't debug actual testcases to find it out.
5409 *
5410 * WaDisableRCCUnitClockGating:snb
5411 * WaDisableRCPBUnitClockGating:snb
5412 */
5413 I915_WRITE(GEN6_UCGCTL2,
5414 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
5415 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5416
5417 /* WaStripsFansDisableFastClipPerformanceFix:snb */
5418 I915_WRITE(_3D_CHICKEN3,
5419 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
5420
5421 /*
5422 * Bspec says:
5423 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
5424 * 3DSTATE_SF number of SF output attributes is more than 16."
5425 */
5426 I915_WRITE(_3D_CHICKEN3,
5427 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
5428
5429 /*
5430 * According to the spec the following bits should be
5431 * set in order to enable memory self-refresh and fbc:
5432 * The bit21 and bit22 of 0x42000
5433 * The bit21 and bit22 of 0x42004
5434 * The bit5 and bit7 of 0x42020
5435 * The bit14 of 0x70180
5436 * The bit14 of 0x71180
5437 *
5438 * WaFbcAsynchFlipDisableFbcQueue:snb
5439 */
5440 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5441 I915_READ(ILK_DISPLAY_CHICKEN1) |
5442 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
5443 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5444 I915_READ(ILK_DISPLAY_CHICKEN2) |
5445 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
5446 I915_WRITE(ILK_DSPCLK_GATE_D,
5447 I915_READ(ILK_DSPCLK_GATE_D) |
5448 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
5449 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
5450
5451 g4x_disable_trickle_feed(dev);
5452
5453 cpt_init_clock_gating(dev);
5454
5455 gen6_check_mch_setup(dev);
5456 }
5457
5458 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
5459 {
5460 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
5461
5462 /*
5463 * WaVSThreadDispatchOverride:ivb,vlv
5464 *
5465 * This actually overrides the dispatch
5466 * mode for all thread types.
5467 */
5468 reg &= ~GEN7_FF_SCHED_MASK;
5469 reg |= GEN7_FF_TS_SCHED_HW;
5470 reg |= GEN7_FF_VS_SCHED_HW;
5471 reg |= GEN7_FF_DS_SCHED_HW;
5472
5473 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
5474 }
5475
5476 static void lpt_init_clock_gating(struct drm_device *dev)
5477 {
5478 struct drm_i915_private *dev_priv = dev->dev_private;
5479
5480 /*
5481 * TODO: this bit should only be enabled when really needed, then
5482 * disabled when not needed anymore in order to save power.
5483 */
5484 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
5485 I915_WRITE(SOUTH_DSPCLK_GATE_D,
5486 I915_READ(SOUTH_DSPCLK_GATE_D) |
5487 PCH_LP_PARTITION_LEVEL_DISABLE);
5488
5489 /* WADPOClockGatingDisable:hsw */
5490 I915_WRITE(_TRANSA_CHICKEN1,
5491 I915_READ(_TRANSA_CHICKEN1) |
5492 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
5493 }
5494
5495 static void lpt_suspend_hw(struct drm_device *dev)
5496 {
5497 struct drm_i915_private *dev_priv = dev->dev_private;
5498
5499 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
5500 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
5501
5502 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
5503 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
5504 }
5505 }
5506
5507 static void gen8_init_clock_gating(struct drm_device *dev)
5508 {
5509 struct drm_i915_private *dev_priv = dev->dev_private;
5510 enum pipe pipe;
5511
5512 I915_WRITE(WM3_LP_ILK, 0);
5513 I915_WRITE(WM2_LP_ILK, 0);
5514 I915_WRITE(WM1_LP_ILK, 0);
5515
5516 /* FIXME(BDW): Check all the w/a, some might only apply to
5517 * pre-production hw. */
5518
5519 /* WaDisablePartialInstShootdown:bdw */
5520 I915_WRITE(GEN8_ROW_CHICKEN,
5521 _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE));
5522
5523 /* WaDisableThreadStallDopClockGating:bdw */
5524 /* FIXME: Unclear whether we really need this on production bdw. */
5525 I915_WRITE(GEN8_ROW_CHICKEN,
5526 _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
5527
5528 /*
5529 * This GEN8_CENTROID_PIXEL_OPT_DIS W/A is only needed for
5530 * pre-production hardware
5531 */
5532 I915_WRITE(HALF_SLICE_CHICKEN3,
5533 _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS));
5534 I915_WRITE(HALF_SLICE_CHICKEN3,
5535 _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
5536 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE));
5537
5538 I915_WRITE(_3D_CHICKEN3,
5539 _MASKED_BIT_ENABLE(_3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2)));
5540
5541 I915_WRITE(COMMON_SLICE_CHICKEN2,
5542 _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE));
5543
5544 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5545 _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE));
5546
5547 /* WaDisableDopClockGating:bdw May not be needed for production */
5548 I915_WRITE(GEN7_ROW_CHICKEN2,
5549 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5550
5551 /* WaSwitchSolVfFArbitrationPriority:bdw */
5552 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
5553
5554 /* WaPsrDPAMaskVBlankInSRD:bdw */
5555 I915_WRITE(CHICKEN_PAR1_1,
5556 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
5557
5558 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
5559 for_each_pipe(pipe) {
5560 I915_WRITE(CHICKEN_PIPESL_1(pipe),
5561 I915_READ(CHICKEN_PIPESL_1(pipe)) |
5562 BDW_DPRS_MASK_VBLANK_SRD);
5563 }
5564
5565 /* Use Force Non-Coherent whenever executing a 3D context. This is a
5566 * workaround for for a possible hang in the unlikely event a TLB
5567 * invalidation occurs during a PSD flush.
5568 */
5569 I915_WRITE(HDC_CHICKEN0,
5570 I915_READ(HDC_CHICKEN0) |
5571 _MASKED_BIT_ENABLE(HDC_FORCE_NON_COHERENT));
5572
5573 /* WaVSRefCountFullforceMissDisable:bdw */
5574 /* WaDSRefCountFullforceMissDisable:bdw */
5575 I915_WRITE(GEN7_FF_THREAD_MODE,
5576 I915_READ(GEN7_FF_THREAD_MODE) &
5577 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
5578
5579 /*
5580 * BSpec recommends 8x4 when MSAA is used,
5581 * however in practice 16x4 seems fastest.
5582 *
5583 * Note that PS/WM thread counts depend on the WIZ hashing
5584 * disable bit, which we don't touch here, but it's good
5585 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5586 */
5587 I915_WRITE(GEN7_GT_MODE,
5588 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5589
5590 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
5591 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
5592
5593 /* WaDisableSDEUnitClockGating:bdw */
5594 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
5595 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5596
5597 /* Wa4x4STCOptimizationDisable:bdw */
5598 I915_WRITE(CACHE_MODE_1,
5599 _MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE));
5600 }
5601
5602 static void haswell_init_clock_gating(struct drm_device *dev)
5603 {
5604 struct drm_i915_private *dev_priv = dev->dev_private;
5605
5606 ilk_init_lp_watermarks(dev);
5607
5608 /* L3 caching of data atomics doesn't work -- disable it. */
5609 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
5610 I915_WRITE(HSW_ROW_CHICKEN3,
5611 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
5612
5613 /* This is required by WaCatErrorRejectionIssue:hsw */
5614 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5615 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5616 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5617
5618 /* WaVSRefCountFullforceMissDisable:hsw */
5619 I915_WRITE(GEN7_FF_THREAD_MODE,
5620 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
5621
5622 /* WaDisable_RenderCache_OperationalFlush:hsw */
5623 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5624
5625 /* enable HiZ Raw Stall Optimization */
5626 I915_WRITE(CACHE_MODE_0_GEN7,
5627 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
5628
5629 /* WaDisable4x2SubspanOptimization:hsw */
5630 I915_WRITE(CACHE_MODE_1,
5631 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5632
5633 /*
5634 * BSpec recommends 8x4 when MSAA is used,
5635 * however in practice 16x4 seems fastest.
5636 *
5637 * Note that PS/WM thread counts depend on the WIZ hashing
5638 * disable bit, which we don't touch here, but it's good
5639 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5640 */
5641 I915_WRITE(GEN7_GT_MODE,
5642 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5643
5644 /* WaSwitchSolVfFArbitrationPriority:hsw */
5645 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
5646
5647 /* WaRsPkgCStateDisplayPMReq:hsw */
5648 I915_WRITE(CHICKEN_PAR1_1,
5649 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
5650
5651 lpt_init_clock_gating(dev);
5652 }
5653
5654 static void ivybridge_init_clock_gating(struct drm_device *dev)
5655 {
5656 struct drm_i915_private *dev_priv = dev->dev_private;
5657 uint32_t snpcr;
5658
5659 ilk_init_lp_watermarks(dev);
5660
5661 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
5662
5663 /* WaDisableEarlyCull:ivb */
5664 I915_WRITE(_3D_CHICKEN3,
5665 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5666
5667 /* WaDisableBackToBackFlipFix:ivb */
5668 I915_WRITE(IVB_CHICKEN3,
5669 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5670 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5671
5672 /* WaDisablePSDDualDispatchEnable:ivb */
5673 if (IS_IVB_GT1(dev))
5674 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5675 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5676
5677 /* WaDisable_RenderCache_OperationalFlush:ivb */
5678 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5679
5680 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
5681 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5682 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5683
5684 /* WaApplyL3ControlAndL3ChickenMode:ivb */
5685 I915_WRITE(GEN7_L3CNTLREG1,
5686 GEN7_WA_FOR_GEN7_L3_CONTROL);
5687 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
5688 GEN7_WA_L3_CHICKEN_MODE);
5689 if (IS_IVB_GT1(dev))
5690 I915_WRITE(GEN7_ROW_CHICKEN2,
5691 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5692 else {
5693 /* must write both registers */
5694 I915_WRITE(GEN7_ROW_CHICKEN2,
5695 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5696 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
5697 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5698 }
5699
5700 /* WaForceL3Serialization:ivb */
5701 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5702 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5703
5704 /*
5705 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5706 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
5707 */
5708 I915_WRITE(GEN6_UCGCTL2,
5709 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
5710
5711 /* This is required by WaCatErrorRejectionIssue:ivb */
5712 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5713 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5714 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5715
5716 g4x_disable_trickle_feed(dev);
5717
5718 gen7_setup_fixed_func_scheduler(dev_priv);
5719
5720 if (0) { /* causes HiZ corruption on ivb:gt1 */
5721 /* enable HiZ Raw Stall Optimization */
5722 I915_WRITE(CACHE_MODE_0_GEN7,
5723 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
5724 }
5725
5726 /* WaDisable4x2SubspanOptimization:ivb */
5727 I915_WRITE(CACHE_MODE_1,
5728 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5729
5730 /*
5731 * BSpec recommends 8x4 when MSAA is used,
5732 * however in practice 16x4 seems fastest.
5733 *
5734 * Note that PS/WM thread counts depend on the WIZ hashing
5735 * disable bit, which we don't touch here, but it's good
5736 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5737 */
5738 I915_WRITE(GEN7_GT_MODE,
5739 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5740
5741 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5742 snpcr &= ~GEN6_MBC_SNPCR_MASK;
5743 snpcr |= GEN6_MBC_SNPCR_MED;
5744 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5745
5746 if (!HAS_PCH_NOP(dev))
5747 cpt_init_clock_gating(dev);
5748
5749 gen6_check_mch_setup(dev);
5750 }
5751
5752 static void valleyview_init_clock_gating(struct drm_device *dev)
5753 {
5754 struct drm_i915_private *dev_priv = dev->dev_private;
5755 u32 val;
5756
5757 mutex_lock(&dev_priv->rps.hw_lock);
5758 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5759 mutex_unlock(&dev_priv->rps.hw_lock);
5760 switch ((val >> 6) & 3) {
5761 case 0:
5762 case 1:
5763 dev_priv->mem_freq = 800;
5764 break;
5765 case 2:
5766 dev_priv->mem_freq = 1066;
5767 break;
5768 case 3:
5769 dev_priv->mem_freq = 1333;
5770 break;
5771 }
5772 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
5773
5774 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
5775
5776 /* WaDisableEarlyCull:vlv */
5777 I915_WRITE(_3D_CHICKEN3,
5778 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5779
5780 /* WaDisableBackToBackFlipFix:vlv */
5781 I915_WRITE(IVB_CHICKEN3,
5782 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5783 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5784
5785 /* WaPsdDispatchEnable:vlv */
5786 /* WaDisablePSDDualDispatchEnable:vlv */
5787 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5788 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
5789 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5790
5791 /* WaDisable_RenderCache_OperationalFlush:vlv */
5792 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5793
5794 /* WaForceL3Serialization:vlv */
5795 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5796 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5797
5798 /* WaDisableDopClockGating:vlv */
5799 I915_WRITE(GEN7_ROW_CHICKEN2,
5800 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5801
5802 /* This is required by WaCatErrorRejectionIssue:vlv */
5803 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5804 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5805 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5806
5807 gen7_setup_fixed_func_scheduler(dev_priv);
5808
5809 /*
5810 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5811 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
5812 */
5813 I915_WRITE(GEN6_UCGCTL2,
5814 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
5815
5816 /* WaDisableL3Bank2xClockGate:vlv
5817 * Disabling L3 clock gating- MMIO 940c[25] = 1
5818 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
5819 I915_WRITE(GEN7_UCGCTL4,
5820 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
5821
5822 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
5823
5824 /*
5825 * BSpec says this must be set, even though
5826 * WaDisable4x2SubspanOptimization isn't listed for VLV.
5827 */
5828 I915_WRITE(CACHE_MODE_1,
5829 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5830
5831 /*
5832 * WaIncreaseL3CreditsForVLVB0:vlv
5833 * This is the hardware default actually.
5834 */
5835 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
5836
5837 /*
5838 * WaDisableVLVClockGating_VBIIssue:vlv
5839 * Disable clock gating on th GCFG unit to prevent a delay
5840 * in the reporting of vblank events.
5841 */
5842 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
5843 }
5844
5845 static void cherryview_init_clock_gating(struct drm_device *dev)
5846 {
5847 struct drm_i915_private *dev_priv = dev->dev_private;
5848 u32 val;
5849
5850 mutex_lock(&dev_priv->rps.hw_lock);
5851 val = vlv_punit_read(dev_priv, CCK_FUSE_REG);
5852 mutex_unlock(&dev_priv->rps.hw_lock);
5853 switch ((val >> 2) & 0x7) {
5854 case 0:
5855 case 1:
5856 dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_200;
5857 dev_priv->mem_freq = 1600;
5858 break;
5859 case 2:
5860 dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_267;
5861 dev_priv->mem_freq = 1600;
5862 break;
5863 case 3:
5864 dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_333;
5865 dev_priv->mem_freq = 2000;
5866 break;
5867 case 4:
5868 dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_320;
5869 dev_priv->mem_freq = 1600;
5870 break;
5871 case 5:
5872 dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_400;
5873 dev_priv->mem_freq = 1600;
5874 break;
5875 }
5876 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
5877
5878 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
5879
5880 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
5881
5882 /* WaDisablePartialInstShootdown:chv */
5883 I915_WRITE(GEN8_ROW_CHICKEN,
5884 _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE));
5885
5886 /* WaDisableThreadStallDopClockGating:chv */
5887 I915_WRITE(GEN8_ROW_CHICKEN,
5888 _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
5889
5890 /* WaVSRefCountFullforceMissDisable:chv */
5891 /* WaDSRefCountFullforceMissDisable:chv */
5892 I915_WRITE(GEN7_FF_THREAD_MODE,
5893 I915_READ(GEN7_FF_THREAD_MODE) &
5894 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
5895
5896 /* WaDisableSemaphoreAndSyncFlipWait:chv */
5897 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
5898 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
5899
5900 /* WaDisableCSUnitClockGating:chv */
5901 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
5902 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
5903
5904 /* WaDisableSDEUnitClockGating:chv */
5905 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
5906 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5907
5908 /* WaDisableSamplerPowerBypass:chv (pre-production hw) */
5909 I915_WRITE(HALF_SLICE_CHICKEN3,
5910 _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
5911
5912 /* WaDisableGunitClockGating:chv (pre-production hw) */
5913 I915_WRITE(VLV_GUNIT_CLOCK_GATE, I915_READ(VLV_GUNIT_CLOCK_GATE) |
5914 GINT_DIS);
5915
5916 /* WaDisableFfDopClockGating:chv (pre-production hw) */
5917 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
5918 _MASKED_BIT_ENABLE(GEN8_FF_DOP_CLOCK_GATE_DISABLE));
5919
5920 /* WaDisableDopClockGating:chv (pre-production hw) */
5921 I915_WRITE(GEN7_ROW_CHICKEN2,
5922 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5923 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
5924 GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
5925 }
5926
5927 static void g4x_init_clock_gating(struct drm_device *dev)
5928 {
5929 struct drm_i915_private *dev_priv = dev->dev_private;
5930 uint32_t dspclk_gate;
5931
5932 I915_WRITE(RENCLK_GATE_D1, 0);
5933 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5934 GS_UNIT_CLOCK_GATE_DISABLE |
5935 CL_UNIT_CLOCK_GATE_DISABLE);
5936 I915_WRITE(RAMCLK_GATE_D, 0);
5937 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5938 OVRUNIT_CLOCK_GATE_DISABLE |
5939 OVCUNIT_CLOCK_GATE_DISABLE;
5940 if (IS_GM45(dev))
5941 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5942 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5943
5944 /* WaDisableRenderCachePipelinedFlush */
5945 I915_WRITE(CACHE_MODE_0,
5946 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
5947
5948 /* WaDisable_RenderCache_OperationalFlush:g4x */
5949 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5950
5951 g4x_disable_trickle_feed(dev);
5952 }
5953
5954 static void crestline_init_clock_gating(struct drm_device *dev)
5955 {
5956 struct drm_i915_private *dev_priv = dev->dev_private;
5957
5958 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5959 I915_WRITE(RENCLK_GATE_D2, 0);
5960 I915_WRITE(DSPCLK_GATE_D, 0);
5961 I915_WRITE(RAMCLK_GATE_D, 0);
5962 I915_WRITE16(DEUC, 0);
5963 I915_WRITE(MI_ARB_STATE,
5964 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
5965
5966 /* WaDisable_RenderCache_OperationalFlush:gen4 */
5967 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5968 }
5969
5970 static void broadwater_init_clock_gating(struct drm_device *dev)
5971 {
5972 struct drm_i915_private *dev_priv = dev->dev_private;
5973
5974 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5975 I965_RCC_CLOCK_GATE_DISABLE |
5976 I965_RCPB_CLOCK_GATE_DISABLE |
5977 I965_ISC_CLOCK_GATE_DISABLE |
5978 I965_FBC_CLOCK_GATE_DISABLE);
5979 I915_WRITE(RENCLK_GATE_D2, 0);
5980 I915_WRITE(MI_ARB_STATE,
5981 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
5982
5983 /* WaDisable_RenderCache_OperationalFlush:gen4 */
5984 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5985 }
5986
5987 static void gen3_init_clock_gating(struct drm_device *dev)
5988 {
5989 struct drm_i915_private *dev_priv = dev->dev_private;
5990 u32 dstate = I915_READ(D_STATE);
5991
5992 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5993 DSTATE_DOT_CLOCK_GATING;
5994 I915_WRITE(D_STATE, dstate);
5995
5996 if (IS_PINEVIEW(dev))
5997 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
5998
5999 /* IIR "flip pending" means done if this bit is set */
6000 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
6001
6002 /* interrupts should cause a wake up from C3 */
6003 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
6004
6005 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
6006 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
6007 }
6008
6009 static void i85x_init_clock_gating(struct drm_device *dev)
6010 {
6011 struct drm_i915_private *dev_priv = dev->dev_private;
6012
6013 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
6014
6015 /* interrupts should cause a wake up from C3 */
6016 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
6017 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
6018 }
6019
6020 static void i830_init_clock_gating(struct drm_device *dev)
6021 {
6022 struct drm_i915_private *dev_priv = dev->dev_private;
6023
6024 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
6025 }
6026
6027 void intel_init_clock_gating(struct drm_device *dev)
6028 {
6029 struct drm_i915_private *dev_priv = dev->dev_private;
6030
6031 dev_priv->display.init_clock_gating(dev);
6032 }
6033
6034 void intel_suspend_hw(struct drm_device *dev)
6035 {
6036 if (HAS_PCH_LPT(dev))
6037 lpt_suspend_hw(dev);
6038 }
6039
6040 #define for_each_power_well(i, power_well, domain_mask, power_domains) \
6041 for (i = 0; \
6042 i < (power_domains)->power_well_count && \
6043 ((power_well) = &(power_domains)->power_wells[i]); \
6044 i++) \
6045 if ((power_well)->domains & (domain_mask))
6046
6047 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
6048 for (i = (power_domains)->power_well_count - 1; \
6049 i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
6050 i--) \
6051 if ((power_well)->domains & (domain_mask))
6052
6053 /**
6054 * We should only use the power well if we explicitly asked the hardware to
6055 * enable it, so check if it's enabled and also check if we've requested it to
6056 * be enabled.
6057 */
6058 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
6059 struct i915_power_well *power_well)
6060 {
6061 return I915_READ(HSW_PWR_WELL_DRIVER) ==
6062 (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
6063 }
6064
6065 bool intel_display_power_enabled_unlocked(struct drm_i915_private *dev_priv,
6066 enum intel_display_power_domain domain)
6067 {
6068 struct i915_power_domains *power_domains;
6069 struct i915_power_well *power_well;
6070 bool is_enabled;
6071 int i;
6072
6073 if (dev_priv->pm.suspended)
6074 return false;
6075
6076 power_domains = &dev_priv->power_domains;
6077
6078 is_enabled = true;
6079
6080 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
6081 if (power_well->always_on)
6082 continue;
6083
6084 if (!power_well->hw_enabled) {
6085 is_enabled = false;
6086 break;
6087 }
6088 }
6089
6090 return is_enabled;
6091 }
6092
6093 bool intel_display_power_enabled(struct drm_i915_private *dev_priv,
6094 enum intel_display_power_domain domain)
6095 {
6096 struct i915_power_domains *power_domains;
6097 bool ret;
6098
6099 power_domains = &dev_priv->power_domains;
6100
6101 mutex_lock(&power_domains->lock);
6102 ret = intel_display_power_enabled_unlocked(dev_priv, domain);
6103 mutex_unlock(&power_domains->lock);
6104
6105 return ret;
6106 }
6107
6108 /*
6109 * Starting with Haswell, we have a "Power Down Well" that can be turned off
6110 * when not needed anymore. We have 4 registers that can request the power well
6111 * to be enabled, and it will only be disabled if none of the registers is
6112 * requesting it to be enabled.
6113 */
6114 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
6115 {
6116 struct drm_device *dev = dev_priv->dev;
6117
6118 /*
6119 * After we re-enable the power well, if we touch VGA register 0x3d5
6120 * we'll get unclaimed register interrupts. This stops after we write
6121 * anything to the VGA MSR register. The vgacon module uses this
6122 * register all the time, so if we unbind our driver and, as a
6123 * consequence, bind vgacon, we'll get stuck in an infinite loop at
6124 * console_unlock(). So make here we touch the VGA MSR register, making
6125 * sure vgacon can keep working normally without triggering interrupts
6126 * and error messages.
6127 */
6128 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
6129 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
6130 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
6131
6132 if (IS_BROADWELL(dev))
6133 gen8_irq_power_well_post_enable(dev_priv);
6134 }
6135
6136 static void hsw_set_power_well(struct drm_i915_private *dev_priv,
6137 struct i915_power_well *power_well, bool enable)
6138 {
6139 bool is_enabled, enable_requested;
6140 uint32_t tmp;
6141
6142 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
6143 is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
6144 enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
6145
6146 if (enable) {
6147 if (!enable_requested)
6148 I915_WRITE(HSW_PWR_WELL_DRIVER,
6149 HSW_PWR_WELL_ENABLE_REQUEST);
6150
6151 if (!is_enabled) {
6152 DRM_DEBUG_KMS("Enabling power well\n");
6153 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
6154 HSW_PWR_WELL_STATE_ENABLED), 20))
6155 DRM_ERROR("Timeout enabling power well\n");
6156 }
6157
6158 hsw_power_well_post_enable(dev_priv);
6159 } else {
6160 if (enable_requested) {
6161 I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
6162 POSTING_READ(HSW_PWR_WELL_DRIVER);
6163 DRM_DEBUG_KMS("Requesting to disable the power well\n");
6164 }
6165 }
6166 }
6167
6168 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
6169 struct i915_power_well *power_well)
6170 {
6171 hsw_set_power_well(dev_priv, power_well, power_well->count > 0);
6172
6173 /*
6174 * We're taking over the BIOS, so clear any requests made by it since
6175 * the driver is in charge now.
6176 */
6177 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
6178 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
6179 }
6180
6181 static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
6182 struct i915_power_well *power_well)
6183 {
6184 hsw_set_power_well(dev_priv, power_well, true);
6185 }
6186
6187 static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
6188 struct i915_power_well *power_well)
6189 {
6190 hsw_set_power_well(dev_priv, power_well, false);
6191 }
6192
6193 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
6194 struct i915_power_well *power_well)
6195 {
6196 }
6197
6198 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
6199 struct i915_power_well *power_well)
6200 {
6201 return true;
6202 }
6203
6204 static void vlv_set_power_well(struct drm_i915_private *dev_priv,
6205 struct i915_power_well *power_well, bool enable)
6206 {
6207 enum punit_power_well power_well_id = power_well->data;
6208 u32 mask;
6209 u32 state;
6210 u32 ctrl;
6211
6212 mask = PUNIT_PWRGT_MASK(power_well_id);
6213 state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) :
6214 PUNIT_PWRGT_PWR_GATE(power_well_id);
6215
6216 mutex_lock(&dev_priv->rps.hw_lock);
6217
6218 #define COND \
6219 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
6220
6221 if (COND)
6222 goto out;
6223
6224 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
6225 ctrl &= ~mask;
6226 ctrl |= state;
6227 vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
6228
6229 if (wait_for(COND, 100))
6230 DRM_ERROR("timout setting power well state %08x (%08x)\n",
6231 state,
6232 vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
6233
6234 #undef COND
6235
6236 out:
6237 mutex_unlock(&dev_priv->rps.hw_lock);
6238 }
6239
6240 static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv,
6241 struct i915_power_well *power_well)
6242 {
6243 vlv_set_power_well(dev_priv, power_well, power_well->count > 0);
6244 }
6245
6246 static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
6247 struct i915_power_well *power_well)
6248 {
6249 vlv_set_power_well(dev_priv, power_well, true);
6250 }
6251
6252 static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
6253 struct i915_power_well *power_well)
6254 {
6255 vlv_set_power_well(dev_priv, power_well, false);
6256 }
6257
6258 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
6259 struct i915_power_well *power_well)
6260 {
6261 int power_well_id = power_well->data;
6262 bool enabled = false;
6263 u32 mask;
6264 u32 state;
6265 u32 ctrl;
6266
6267 mask = PUNIT_PWRGT_MASK(power_well_id);
6268 ctrl = PUNIT_PWRGT_PWR_ON(power_well_id);
6269
6270 mutex_lock(&dev_priv->rps.hw_lock);
6271
6272 state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
6273 /*
6274 * We only ever set the power-on and power-gate states, anything
6275 * else is unexpected.
6276 */
6277 WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) &&
6278 state != PUNIT_PWRGT_PWR_GATE(power_well_id));
6279 if (state == ctrl)
6280 enabled = true;
6281
6282 /*
6283 * A transient state at this point would mean some unexpected party
6284 * is poking at the power controls too.
6285 */
6286 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
6287 WARN_ON(ctrl != state);
6288
6289 mutex_unlock(&dev_priv->rps.hw_lock);
6290
6291 return enabled;
6292 }
6293
6294 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
6295 struct i915_power_well *power_well)
6296 {
6297 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
6298
6299 vlv_set_power_well(dev_priv, power_well, true);
6300
6301 spin_lock_irq(&dev_priv->irq_lock);
6302 valleyview_enable_display_irqs(dev_priv);
6303 spin_unlock_irq(&dev_priv->irq_lock);
6304
6305 /*
6306 * During driver initialization/resume we can avoid restoring the
6307 * part of the HW/SW state that will be inited anyway explicitly.
6308 */
6309 if (dev_priv->power_domains.initializing)
6310 return;
6311
6312 intel_hpd_init(dev_priv->dev);
6313
6314 i915_redisable_vga_power_on(dev_priv->dev);
6315 }
6316
6317 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
6318 struct i915_power_well *power_well)
6319 {
6320 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
6321
6322 spin_lock_irq(&dev_priv->irq_lock);
6323 valleyview_disable_display_irqs(dev_priv);
6324 spin_unlock_irq(&dev_priv->irq_lock);
6325
6326 vlv_set_power_well(dev_priv, power_well, false);
6327 }
6328
6329 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
6330 struct i915_power_well *power_well)
6331 {
6332 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
6333
6334 /*
6335 * Enable the CRI clock source so we can get at the
6336 * display and the reference clock for VGA
6337 * hotplug / manual detection.
6338 */
6339 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
6340 DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
6341 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
6342
6343 vlv_set_power_well(dev_priv, power_well, true);
6344
6345 /*
6346 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
6347 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
6348 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
6349 * b. The other bits such as sfr settings / modesel may all
6350 * be set to 0.
6351 *
6352 * This should only be done on init and resume from S3 with
6353 * both PLLs disabled, or we risk losing DPIO and PLL
6354 * synchronization.
6355 */
6356 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
6357 }
6358
6359 static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
6360 struct i915_power_well *power_well)
6361 {
6362 struct drm_device *dev = dev_priv->dev;
6363 enum pipe pipe;
6364
6365 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
6366
6367 for_each_pipe(pipe)
6368 assert_pll_disabled(dev_priv, pipe);
6369
6370 /* Assert common reset */
6371 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST);
6372
6373 vlv_set_power_well(dev_priv, power_well, false);
6374 }
6375
6376 static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
6377 struct i915_power_well *power_well)
6378 {
6379 enum dpio_phy phy;
6380
6381 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
6382 power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
6383
6384 /*
6385 * Enable the CRI clock source so we can get at the
6386 * display and the reference clock for VGA
6387 * hotplug / manual detection.
6388 */
6389 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
6390 phy = DPIO_PHY0;
6391 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
6392 DPLL_REFA_CLK_ENABLE_VLV);
6393 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
6394 DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
6395 } else {
6396 phy = DPIO_PHY1;
6397 I915_WRITE(DPLL(PIPE_C), I915_READ(DPLL(PIPE_C)) |
6398 DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
6399 }
6400 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
6401 vlv_set_power_well(dev_priv, power_well, true);
6402
6403 /* Poll for phypwrgood signal */
6404 if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1))
6405 DRM_ERROR("Display PHY %d is not power up\n", phy);
6406
6407 I915_WRITE(DISPLAY_PHY_CONTROL, I915_READ(DISPLAY_PHY_CONTROL) |
6408 PHY_COM_LANE_RESET_DEASSERT(phy));
6409 }
6410
6411 static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
6412 struct i915_power_well *power_well)
6413 {
6414 enum dpio_phy phy;
6415
6416 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
6417 power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
6418
6419 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
6420 phy = DPIO_PHY0;
6421 assert_pll_disabled(dev_priv, PIPE_A);
6422 assert_pll_disabled(dev_priv, PIPE_B);
6423 } else {
6424 phy = DPIO_PHY1;
6425 assert_pll_disabled(dev_priv, PIPE_C);
6426 }
6427
6428 I915_WRITE(DISPLAY_PHY_CONTROL, I915_READ(DISPLAY_PHY_CONTROL) &
6429 ~PHY_COM_LANE_RESET_DEASSERT(phy));
6430
6431 vlv_set_power_well(dev_priv, power_well, false);
6432 }
6433
6434 static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,
6435 struct i915_power_well *power_well)
6436 {
6437 enum pipe pipe = power_well->data;
6438 bool enabled;
6439 u32 state, ctrl;
6440
6441 mutex_lock(&dev_priv->rps.hw_lock);
6442
6443 state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe);
6444 /*
6445 * We only ever set the power-on and power-gate states, anything
6446 * else is unexpected.
6447 */
6448 WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe));
6449 enabled = state == DP_SSS_PWR_ON(pipe);
6450
6451 /*
6452 * A transient state at this point would mean some unexpected party
6453 * is poking at the power controls too.
6454 */
6455 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe);
6456 WARN_ON(ctrl << 16 != state);
6457
6458 mutex_unlock(&dev_priv->rps.hw_lock);
6459
6460 return enabled;
6461 }
6462
6463 static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
6464 struct i915_power_well *power_well,
6465 bool enable)
6466 {
6467 enum pipe pipe = power_well->data;
6468 u32 state;
6469 u32 ctrl;
6470
6471 state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe);
6472
6473 mutex_lock(&dev_priv->rps.hw_lock);
6474
6475 #define COND \
6476 ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state)
6477
6478 if (COND)
6479 goto out;
6480
6481 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
6482 ctrl &= ~DP_SSC_MASK(pipe);
6483 ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe);
6484 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl);
6485
6486 if (wait_for(COND, 100))
6487 DRM_ERROR("timout setting power well state %08x (%08x)\n",
6488 state,
6489 vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ));
6490
6491 #undef COND
6492
6493 out:
6494 mutex_unlock(&dev_priv->rps.hw_lock);
6495 }
6496
6497 static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv,
6498 struct i915_power_well *power_well)
6499 {
6500 chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0);
6501 }
6502
6503 static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
6504 struct i915_power_well *power_well)
6505 {
6506 WARN_ON_ONCE(power_well->data != PIPE_A &&
6507 power_well->data != PIPE_B &&
6508 power_well->data != PIPE_C);
6509
6510 chv_set_pipe_power_well(dev_priv, power_well, true);
6511 }
6512
6513 static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
6514 struct i915_power_well *power_well)
6515 {
6516 WARN_ON_ONCE(power_well->data != PIPE_A &&
6517 power_well->data != PIPE_B &&
6518 power_well->data != PIPE_C);
6519
6520 chv_set_pipe_power_well(dev_priv, power_well, false);
6521 }
6522
6523 static void check_power_well_state(struct drm_i915_private *dev_priv,
6524 struct i915_power_well *power_well)
6525 {
6526 bool enabled = power_well->ops->is_enabled(dev_priv, power_well);
6527
6528 if (power_well->always_on || !i915.disable_power_well) {
6529 if (!enabled)
6530 goto mismatch;
6531
6532 return;
6533 }
6534
6535 if (enabled != (power_well->count > 0))
6536 goto mismatch;
6537
6538 return;
6539
6540 mismatch:
6541 WARN(1, "state mismatch for '%s' (always_on %d hw state %d use-count %d disable_power_well %d\n",
6542 power_well->name, power_well->always_on, enabled,
6543 power_well->count, i915.disable_power_well);
6544 }
6545
6546 void intel_display_power_get(struct drm_i915_private *dev_priv,
6547 enum intel_display_power_domain domain)
6548 {
6549 struct i915_power_domains *power_domains;
6550 struct i915_power_well *power_well;
6551 int i;
6552
6553 intel_runtime_pm_get(dev_priv);
6554
6555 power_domains = &dev_priv->power_domains;
6556
6557 mutex_lock(&power_domains->lock);
6558
6559 for_each_power_well(i, power_well, BIT(domain), power_domains) {
6560 if (!power_well->count++) {
6561 DRM_DEBUG_KMS("enabling %s\n", power_well->name);
6562 power_well->ops->enable(dev_priv, power_well);
6563 power_well->hw_enabled = true;
6564 }
6565
6566 check_power_well_state(dev_priv, power_well);
6567 }
6568
6569 power_domains->domain_use_count[domain]++;
6570
6571 mutex_unlock(&power_domains->lock);
6572 }
6573
6574 void intel_display_power_put(struct drm_i915_private *dev_priv,
6575 enum intel_display_power_domain domain)
6576 {
6577 struct i915_power_domains *power_domains;
6578 struct i915_power_well *power_well;
6579 int i;
6580
6581 power_domains = &dev_priv->power_domains;
6582
6583 mutex_lock(&power_domains->lock);
6584
6585 WARN_ON(!power_domains->domain_use_count[domain]);
6586 power_domains->domain_use_count[domain]--;
6587
6588 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
6589 WARN_ON(!power_well->count);
6590
6591 if (!--power_well->count && i915.disable_power_well) {
6592 DRM_DEBUG_KMS("disabling %s\n", power_well->name);
6593 power_well->hw_enabled = false;
6594 power_well->ops->disable(dev_priv, power_well);
6595 }
6596
6597 check_power_well_state(dev_priv, power_well);
6598 }
6599
6600 mutex_unlock(&power_domains->lock);
6601
6602 intel_runtime_pm_put(dev_priv);
6603 }
6604
6605 static struct i915_power_domains *hsw_pwr;
6606
6607 /* Display audio driver power well request */
6608 int i915_request_power_well(void)
6609 {
6610 struct drm_i915_private *dev_priv;
6611
6612 if (!hsw_pwr)
6613 return -ENODEV;
6614
6615 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
6616 power_domains);
6617 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
6618 return 0;
6619 }
6620 EXPORT_SYMBOL_GPL(i915_request_power_well);
6621
6622 /* Display audio driver power well release */
6623 int i915_release_power_well(void)
6624 {
6625 struct drm_i915_private *dev_priv;
6626
6627 if (!hsw_pwr)
6628 return -ENODEV;
6629
6630 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
6631 power_domains);
6632 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
6633 return 0;
6634 }
6635 EXPORT_SYMBOL_GPL(i915_release_power_well);
6636
6637 /*
6638 * Private interface for the audio driver to get CDCLK in kHz.
6639 *
6640 * Caller must request power well using i915_request_power_well() prior to
6641 * making the call.
6642 */
6643 int i915_get_cdclk_freq(void)
6644 {
6645 struct drm_i915_private *dev_priv;
6646
6647 if (!hsw_pwr)
6648 return -ENODEV;
6649
6650 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
6651 power_domains);
6652
6653 return intel_ddi_get_cdclk_freq(dev_priv);
6654 }
6655 EXPORT_SYMBOL_GPL(i915_get_cdclk_freq);
6656
6657
6658 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
6659
6660 #define HSW_ALWAYS_ON_POWER_DOMAINS ( \
6661 BIT(POWER_DOMAIN_PIPE_A) | \
6662 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
6663 BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
6664 BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
6665 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6666 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6667 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6668 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6669 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
6670 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
6671 BIT(POWER_DOMAIN_PORT_CRT) | \
6672 BIT(POWER_DOMAIN_PLLS) | \
6673 BIT(POWER_DOMAIN_INIT))
6674 #define HSW_DISPLAY_POWER_DOMAINS ( \
6675 (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \
6676 BIT(POWER_DOMAIN_INIT))
6677
6678 #define BDW_ALWAYS_ON_POWER_DOMAINS ( \
6679 HSW_ALWAYS_ON_POWER_DOMAINS | \
6680 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
6681 #define BDW_DISPLAY_POWER_DOMAINS ( \
6682 (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) | \
6683 BIT(POWER_DOMAIN_INIT))
6684
6685 #define VLV_ALWAYS_ON_POWER_DOMAINS BIT(POWER_DOMAIN_INIT)
6686 #define VLV_DISPLAY_POWER_DOMAINS POWER_DOMAIN_MASK
6687
6688 #define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \
6689 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6690 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6691 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6692 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6693 BIT(POWER_DOMAIN_PORT_CRT) | \
6694 BIT(POWER_DOMAIN_INIT))
6695
6696 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \
6697 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6698 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6699 BIT(POWER_DOMAIN_INIT))
6700
6701 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \
6702 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6703 BIT(POWER_DOMAIN_INIT))
6704
6705 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \
6706 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6707 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6708 BIT(POWER_DOMAIN_INIT))
6709
6710 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \
6711 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6712 BIT(POWER_DOMAIN_INIT))
6713
6714 #define CHV_PIPE_A_POWER_DOMAINS ( \
6715 BIT(POWER_DOMAIN_PIPE_A) | \
6716 BIT(POWER_DOMAIN_INIT))
6717
6718 #define CHV_PIPE_B_POWER_DOMAINS ( \
6719 BIT(POWER_DOMAIN_PIPE_B) | \
6720 BIT(POWER_DOMAIN_INIT))
6721
6722 #define CHV_PIPE_C_POWER_DOMAINS ( \
6723 BIT(POWER_DOMAIN_PIPE_C) | \
6724 BIT(POWER_DOMAIN_INIT))
6725
6726 #define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \
6727 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6728 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6729 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6730 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6731 BIT(POWER_DOMAIN_INIT))
6732
6733 #define CHV_DPIO_CMN_D_POWER_DOMAINS ( \
6734 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
6735 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
6736 BIT(POWER_DOMAIN_INIT))
6737
6738 #define CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS ( \
6739 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
6740 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
6741 BIT(POWER_DOMAIN_INIT))
6742
6743 #define CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS ( \
6744 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
6745 BIT(POWER_DOMAIN_INIT))
6746
6747 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
6748 .sync_hw = i9xx_always_on_power_well_noop,
6749 .enable = i9xx_always_on_power_well_noop,
6750 .disable = i9xx_always_on_power_well_noop,
6751 .is_enabled = i9xx_always_on_power_well_enabled,
6752 };
6753
6754 static const struct i915_power_well_ops chv_pipe_power_well_ops = {
6755 .sync_hw = chv_pipe_power_well_sync_hw,
6756 .enable = chv_pipe_power_well_enable,
6757 .disable = chv_pipe_power_well_disable,
6758 .is_enabled = chv_pipe_power_well_enabled,
6759 };
6760
6761 static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = {
6762 .sync_hw = vlv_power_well_sync_hw,
6763 .enable = chv_dpio_cmn_power_well_enable,
6764 .disable = chv_dpio_cmn_power_well_disable,
6765 .is_enabled = vlv_power_well_enabled,
6766 };
6767
6768 static struct i915_power_well i9xx_always_on_power_well[] = {
6769 {
6770 .name = "always-on",
6771 .always_on = 1,
6772 .domains = POWER_DOMAIN_MASK,
6773 .ops = &i9xx_always_on_power_well_ops,
6774 },
6775 };
6776
6777 static const struct i915_power_well_ops hsw_power_well_ops = {
6778 .sync_hw = hsw_power_well_sync_hw,
6779 .enable = hsw_power_well_enable,
6780 .disable = hsw_power_well_disable,
6781 .is_enabled = hsw_power_well_enabled,
6782 };
6783
6784 static struct i915_power_well hsw_power_wells[] = {
6785 {
6786 .name = "always-on",
6787 .always_on = 1,
6788 .domains = HSW_ALWAYS_ON_POWER_DOMAINS,
6789 .ops = &i9xx_always_on_power_well_ops,
6790 },
6791 {
6792 .name = "display",
6793 .domains = HSW_DISPLAY_POWER_DOMAINS,
6794 .ops = &hsw_power_well_ops,
6795 },
6796 };
6797
6798 static struct i915_power_well bdw_power_wells[] = {
6799 {
6800 .name = "always-on",
6801 .always_on = 1,
6802 .domains = BDW_ALWAYS_ON_POWER_DOMAINS,
6803 .ops = &i9xx_always_on_power_well_ops,
6804 },
6805 {
6806 .name = "display",
6807 .domains = BDW_DISPLAY_POWER_DOMAINS,
6808 .ops = &hsw_power_well_ops,
6809 },
6810 };
6811
6812 static const struct i915_power_well_ops vlv_display_power_well_ops = {
6813 .sync_hw = vlv_power_well_sync_hw,
6814 .enable = vlv_display_power_well_enable,
6815 .disable = vlv_display_power_well_disable,
6816 .is_enabled = vlv_power_well_enabled,
6817 };
6818
6819 static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = {
6820 .sync_hw = vlv_power_well_sync_hw,
6821 .enable = vlv_dpio_cmn_power_well_enable,
6822 .disable = vlv_dpio_cmn_power_well_disable,
6823 .is_enabled = vlv_power_well_enabled,
6824 };
6825
6826 static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
6827 .sync_hw = vlv_power_well_sync_hw,
6828 .enable = vlv_power_well_enable,
6829 .disable = vlv_power_well_disable,
6830 .is_enabled = vlv_power_well_enabled,
6831 };
6832
6833 static struct i915_power_well vlv_power_wells[] = {
6834 {
6835 .name = "always-on",
6836 .always_on = 1,
6837 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
6838 .ops = &i9xx_always_on_power_well_ops,
6839 },
6840 {
6841 .name = "display",
6842 .domains = VLV_DISPLAY_POWER_DOMAINS,
6843 .data = PUNIT_POWER_WELL_DISP2D,
6844 .ops = &vlv_display_power_well_ops,
6845 },
6846 {
6847 .name = "dpio-tx-b-01",
6848 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6849 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6850 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6851 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6852 .ops = &vlv_dpio_power_well_ops,
6853 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
6854 },
6855 {
6856 .name = "dpio-tx-b-23",
6857 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6858 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6859 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6860 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6861 .ops = &vlv_dpio_power_well_ops,
6862 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
6863 },
6864 {
6865 .name = "dpio-tx-c-01",
6866 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6867 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6868 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6869 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6870 .ops = &vlv_dpio_power_well_ops,
6871 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
6872 },
6873 {
6874 .name = "dpio-tx-c-23",
6875 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6876 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6877 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6878 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6879 .ops = &vlv_dpio_power_well_ops,
6880 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
6881 },
6882 {
6883 .name = "dpio-common",
6884 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
6885 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
6886 .ops = &vlv_dpio_cmn_power_well_ops,
6887 },
6888 };
6889
6890 static struct i915_power_well chv_power_wells[] = {
6891 {
6892 .name = "always-on",
6893 .always_on = 1,
6894 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
6895 .ops = &i9xx_always_on_power_well_ops,
6896 },
6897 #if 0
6898 {
6899 .name = "display",
6900 .domains = VLV_DISPLAY_POWER_DOMAINS,
6901 .data = PUNIT_POWER_WELL_DISP2D,
6902 .ops = &vlv_display_power_well_ops,
6903 },
6904 {
6905 .name = "pipe-a",
6906 .domains = CHV_PIPE_A_POWER_DOMAINS,
6907 .data = PIPE_A,
6908 .ops = &chv_pipe_power_well_ops,
6909 },
6910 {
6911 .name = "pipe-b",
6912 .domains = CHV_PIPE_B_POWER_DOMAINS,
6913 .data = PIPE_B,
6914 .ops = &chv_pipe_power_well_ops,
6915 },
6916 {
6917 .name = "pipe-c",
6918 .domains = CHV_PIPE_C_POWER_DOMAINS,
6919 .data = PIPE_C,
6920 .ops = &chv_pipe_power_well_ops,
6921 },
6922 #endif
6923 {
6924 .name = "dpio-common-bc",
6925 /*
6926 * XXX: cmnreset for one PHY seems to disturb the other.
6927 * As a workaround keep both powered on at the same
6928 * time for now.
6929 */
6930 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS | CHV_DPIO_CMN_D_POWER_DOMAINS,
6931 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
6932 .ops = &chv_dpio_cmn_power_well_ops,
6933 },
6934 {
6935 .name = "dpio-common-d",
6936 /*
6937 * XXX: cmnreset for one PHY seems to disturb the other.
6938 * As a workaround keep both powered on at the same
6939 * time for now.
6940 */
6941 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS | CHV_DPIO_CMN_D_POWER_DOMAINS,
6942 .data = PUNIT_POWER_WELL_DPIO_CMN_D,
6943 .ops = &chv_dpio_cmn_power_well_ops,
6944 },
6945 #if 0
6946 {
6947 .name = "dpio-tx-b-01",
6948 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6949 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS,
6950 .ops = &vlv_dpio_power_well_ops,
6951 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
6952 },
6953 {
6954 .name = "dpio-tx-b-23",
6955 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6956 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS,
6957 .ops = &vlv_dpio_power_well_ops,
6958 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
6959 },
6960 {
6961 .name = "dpio-tx-c-01",
6962 .domains = VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6963 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6964 .ops = &vlv_dpio_power_well_ops,
6965 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
6966 },
6967 {
6968 .name = "dpio-tx-c-23",
6969 .domains = VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6970 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6971 .ops = &vlv_dpio_power_well_ops,
6972 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
6973 },
6974 {
6975 .name = "dpio-tx-d-01",
6976 .domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS |
6977 CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS,
6978 .ops = &vlv_dpio_power_well_ops,
6979 .data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_01,
6980 },
6981 {
6982 .name = "dpio-tx-d-23",
6983 .domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS |
6984 CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS,
6985 .ops = &vlv_dpio_power_well_ops,
6986 .data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_23,
6987 },
6988 #endif
6989 };
6990
6991 static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv,
6992 enum punit_power_well power_well_id)
6993 {
6994 struct i915_power_domains *power_domains = &dev_priv->power_domains;
6995 struct i915_power_well *power_well;
6996 int i;
6997
6998 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
6999 if (power_well->data == power_well_id)
7000 return power_well;
7001 }
7002
7003 return NULL;
7004 }
7005
7006 #define set_power_wells(power_domains, __power_wells) ({ \
7007 (power_domains)->power_wells = (__power_wells); \
7008 (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \
7009 })
7010
7011 int intel_power_domains_init(struct drm_i915_private *dev_priv)
7012 {
7013 struct i915_power_domains *power_domains = &dev_priv->power_domains;
7014
7015 mutex_init(&power_domains->lock);
7016
7017 /*
7018 * The enabling order will be from lower to higher indexed wells,
7019 * the disabling order is reversed.
7020 */
7021 if (IS_HASWELL(dev_priv->dev)) {
7022 set_power_wells(power_domains, hsw_power_wells);
7023 hsw_pwr = power_domains;
7024 } else if (IS_BROADWELL(dev_priv->dev)) {
7025 set_power_wells(power_domains, bdw_power_wells);
7026 hsw_pwr = power_domains;
7027 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
7028 set_power_wells(power_domains, chv_power_wells);
7029 } else if (IS_VALLEYVIEW(dev_priv->dev)) {
7030 set_power_wells(power_domains, vlv_power_wells);
7031 } else {
7032 set_power_wells(power_domains, i9xx_always_on_power_well);
7033 }
7034
7035 return 0;
7036 }
7037
7038 void intel_power_domains_remove(struct drm_i915_private *dev_priv)
7039 {
7040 hsw_pwr = NULL;
7041 }
7042
7043 static void intel_power_domains_resume(struct drm_i915_private *dev_priv)
7044 {
7045 struct i915_power_domains *power_domains = &dev_priv->power_domains;
7046 struct i915_power_well *power_well;
7047 int i;
7048
7049 mutex_lock(&power_domains->lock);
7050 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
7051 power_well->ops->sync_hw(dev_priv, power_well);
7052 power_well->hw_enabled = power_well->ops->is_enabled(dev_priv,
7053 power_well);
7054 }
7055 mutex_unlock(&power_domains->lock);
7056 }
7057
7058 static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
7059 {
7060 struct i915_power_well *cmn =
7061 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
7062 struct i915_power_well *disp2d =
7063 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D);
7064
7065 /* nothing to do if common lane is already off */
7066 if (!cmn->ops->is_enabled(dev_priv, cmn))
7067 return;
7068
7069 /* If the display might be already active skip this */
7070 if (disp2d->ops->is_enabled(dev_priv, disp2d) &&
7071 I915_READ(DPIO_CTL) & DPIO_CMNRST)
7072 return;
7073
7074 DRM_DEBUG_KMS("toggling display PHY side reset\n");
7075
7076 /* cmnlane needs DPLL registers */
7077 disp2d->ops->enable(dev_priv, disp2d);
7078
7079 /*
7080 * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
7081 * Need to assert and de-assert PHY SB reset by gating the
7082 * common lane power, then un-gating it.
7083 * Simply ungating isn't enough to reset the PHY enough to get
7084 * ports and lanes running.
7085 */
7086 cmn->ops->disable(dev_priv, cmn);
7087 }
7088
7089 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv)
7090 {
7091 struct drm_device *dev = dev_priv->dev;
7092 struct i915_power_domains *power_domains = &dev_priv->power_domains;
7093
7094 power_domains->initializing = true;
7095
7096 if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
7097 mutex_lock(&power_domains->lock);
7098 vlv_cmnlane_wa(dev_priv);
7099 mutex_unlock(&power_domains->lock);
7100 }
7101
7102 /* For now, we need the power well to be always enabled. */
7103 intel_display_set_init_power(dev_priv, true);
7104 intel_power_domains_resume(dev_priv);
7105 power_domains->initializing = false;
7106 }
7107
7108 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)
7109 {
7110 intel_runtime_pm_get(dev_priv);
7111 }
7112
7113 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)
7114 {
7115 intel_runtime_pm_put(dev_priv);
7116 }
7117
7118 void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
7119 {
7120 struct drm_device *dev = dev_priv->dev;
7121 struct device *device = &dev->pdev->dev;
7122
7123 if (!HAS_RUNTIME_PM(dev))
7124 return;
7125
7126 pm_runtime_get_sync(device);
7127 WARN(dev_priv->pm.suspended, "Device still suspended.\n");
7128 }
7129
7130 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv)
7131 {
7132 struct drm_device *dev = dev_priv->dev;
7133 struct device *device = &dev->pdev->dev;
7134
7135 if (!HAS_RUNTIME_PM(dev))
7136 return;
7137
7138 WARN(dev_priv->pm.suspended, "Getting nosync-ref while suspended.\n");
7139 pm_runtime_get_noresume(device);
7140 }
7141
7142 void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
7143 {
7144 struct drm_device *dev = dev_priv->dev;
7145 struct device *device = &dev->pdev->dev;
7146
7147 if (!HAS_RUNTIME_PM(dev))
7148 return;
7149
7150 pm_runtime_mark_last_busy(device);
7151 pm_runtime_put_autosuspend(device);
7152 }
7153
7154 void intel_init_runtime_pm(struct drm_i915_private *dev_priv)
7155 {
7156 struct drm_device *dev = dev_priv->dev;
7157 struct device *device = &dev->pdev->dev;
7158
7159 if (!HAS_RUNTIME_PM(dev))
7160 return;
7161
7162 pm_runtime_set_active(device);
7163
7164 /*
7165 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
7166 * requirement.
7167 */
7168 if (!intel_enable_rc6(dev)) {
7169 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
7170 return;
7171 }
7172
7173 pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
7174 pm_runtime_mark_last_busy(device);
7175 pm_runtime_use_autosuspend(device);
7176
7177 pm_runtime_put_autosuspend(device);
7178 }
7179
7180 void intel_fini_runtime_pm(struct drm_i915_private *dev_priv)
7181 {
7182 struct drm_device *dev = dev_priv->dev;
7183 struct device *device = &dev->pdev->dev;
7184
7185 if (!HAS_RUNTIME_PM(dev))
7186 return;
7187
7188 if (!intel_enable_rc6(dev))
7189 return;
7190
7191 /* Make sure we're not suspended first. */
7192 pm_runtime_get_sync(device);
7193 pm_runtime_disable(device);
7194 }
7195
7196 /* Set up chip specific power management-related functions */
7197 void intel_init_pm(struct drm_device *dev)
7198 {
7199 struct drm_i915_private *dev_priv = dev->dev_private;
7200
7201 if (HAS_FBC(dev)) {
7202 if (INTEL_INFO(dev)->gen >= 7) {
7203 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
7204 dev_priv->display.enable_fbc = gen7_enable_fbc;
7205 dev_priv->display.disable_fbc = ironlake_disable_fbc;
7206 } else if (INTEL_INFO(dev)->gen >= 5) {
7207 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
7208 dev_priv->display.enable_fbc = ironlake_enable_fbc;
7209 dev_priv->display.disable_fbc = ironlake_disable_fbc;
7210 } else if (IS_GM45(dev)) {
7211 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
7212 dev_priv->display.enable_fbc = g4x_enable_fbc;
7213 dev_priv->display.disable_fbc = g4x_disable_fbc;
7214 } else {
7215 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
7216 dev_priv->display.enable_fbc = i8xx_enable_fbc;
7217 dev_priv->display.disable_fbc = i8xx_disable_fbc;
7218
7219 /* This value was pulled out of someone's hat */
7220 I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);
7221 }
7222 }
7223
7224 /* For cxsr */
7225 if (IS_PINEVIEW(dev))
7226 i915_pineview_get_mem_freq(dev);
7227 else if (IS_GEN5(dev))
7228 i915_ironlake_get_mem_freq(dev);
7229
7230 /* For FIFO watermark updates */
7231 if (HAS_PCH_SPLIT(dev)) {
7232 ilk_setup_wm_latency(dev);
7233
7234 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
7235 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7236 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7237 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
7238 dev_priv->display.update_wm = ilk_update_wm;
7239 dev_priv->display.update_sprite_wm = ilk_update_sprite_wm;
7240 } else {
7241 DRM_DEBUG_KMS("Failed to read display plane latency. "
7242 "Disable CxSR\n");
7243 }
7244
7245 if (IS_GEN5(dev))
7246 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7247 else if (IS_GEN6(dev))
7248 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7249 else if (IS_IVYBRIDGE(dev))
7250 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7251 else if (IS_HASWELL(dev))
7252 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7253 else if (INTEL_INFO(dev)->gen == 8)
7254 dev_priv->display.init_clock_gating = gen8_init_clock_gating;
7255 } else if (IS_CHERRYVIEW(dev)) {
7256 dev_priv->display.update_wm = cherryview_update_wm;
7257 dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;
7258 dev_priv->display.init_clock_gating =
7259 cherryview_init_clock_gating;
7260 } else if (IS_VALLEYVIEW(dev)) {
7261 dev_priv->display.update_wm = valleyview_update_wm;
7262 dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;
7263 dev_priv->display.init_clock_gating =
7264 valleyview_init_clock_gating;
7265 } else if (IS_PINEVIEW(dev)) {
7266 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7267 dev_priv->is_ddr3,
7268 dev_priv->fsb_freq,
7269 dev_priv->mem_freq)) {
7270 DRM_INFO("failed to find known CxSR latency "
7271 "(found ddr%s fsb freq %d, mem freq %d), "
7272 "disabling CxSR\n",
7273 (dev_priv->is_ddr3 == 1) ? "3" : "2",
7274 dev_priv->fsb_freq, dev_priv->mem_freq);
7275 /* Disable CxSR and never update its watermark again */
7276 intel_set_memory_cxsr(dev_priv, false);
7277 dev_priv->display.update_wm = NULL;
7278 } else
7279 dev_priv->display.update_wm = pineview_update_wm;
7280 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7281 } else if (IS_G4X(dev)) {
7282 dev_priv->display.update_wm = g4x_update_wm;
7283 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7284 } else if (IS_GEN4(dev)) {
7285 dev_priv->display.update_wm = i965_update_wm;
7286 if (IS_CRESTLINE(dev))
7287 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7288 else if (IS_BROADWATER(dev))
7289 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7290 } else if (IS_GEN3(dev)) {
7291 dev_priv->display.update_wm = i9xx_update_wm;
7292 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7293 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7294 } else if (IS_GEN2(dev)) {
7295 if (INTEL_INFO(dev)->num_pipes == 1) {
7296 dev_priv->display.update_wm = i845_update_wm;
7297 dev_priv->display.get_fifo_size = i845_get_fifo_size;
7298 } else {
7299 dev_priv->display.update_wm = i9xx_update_wm;
7300 dev_priv->display.get_fifo_size = i830_get_fifo_size;
7301 }
7302
7303 if (IS_I85X(dev) || IS_I865G(dev))
7304 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7305 else
7306 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7307 } else {
7308 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
7309 }
7310 }
7311
7312 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
7313 {
7314 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7315
7316 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7317 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7318 return -EAGAIN;
7319 }
7320
7321 I915_WRITE(GEN6_PCODE_DATA, *val);
7322 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7323
7324 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7325 500)) {
7326 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7327 return -ETIMEDOUT;
7328 }
7329
7330 *val = I915_READ(GEN6_PCODE_DATA);
7331 I915_WRITE(GEN6_PCODE_DATA, 0);
7332
7333 return 0;
7334 }
7335
7336 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
7337 {
7338 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7339
7340 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7341 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7342 return -EAGAIN;
7343 }
7344
7345 I915_WRITE(GEN6_PCODE_DATA, val);
7346 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7347
7348 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7349 500)) {
7350 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7351 return -ETIMEDOUT;
7352 }
7353
7354 I915_WRITE(GEN6_PCODE_DATA, 0);
7355
7356 return 0;
7357 }
7358
7359 static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7360 {
7361 int div;
7362
7363 /* 4 x czclk */
7364 switch (dev_priv->mem_freq) {
7365 case 800:
7366 div = 10;
7367 break;
7368 case 1066:
7369 div = 12;
7370 break;
7371 case 1333:
7372 div = 16;
7373 break;
7374 default:
7375 return -1;
7376 }
7377
7378 return DIV_ROUND_CLOSEST(dev_priv->mem_freq * (val + 6 - 0xbd), 4 * div);
7379 }
7380
7381 static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
7382 {
7383 int mul;
7384
7385 /* 4 x czclk */
7386 switch (dev_priv->mem_freq) {
7387 case 800:
7388 mul = 10;
7389 break;
7390 case 1066:
7391 mul = 12;
7392 break;
7393 case 1333:
7394 mul = 16;
7395 break;
7396 default:
7397 return -1;
7398 }
7399
7400 return DIV_ROUND_CLOSEST(4 * mul * val, dev_priv->mem_freq) + 0xbd - 6;
7401 }
7402
7403 static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
7404 {
7405 int div, freq;
7406
7407 switch (dev_priv->rps.cz_freq) {
7408 case 200:
7409 div = 5;
7410 break;
7411 case 267:
7412 div = 6;
7413 break;
7414 case 320:
7415 case 333:
7416 case 400:
7417 div = 8;
7418 break;
7419 default:
7420 return -1;
7421 }
7422
7423 freq = (DIV_ROUND_CLOSEST((dev_priv->rps.cz_freq * val), 2 * div) / 2);
7424
7425 return freq;
7426 }
7427
7428 static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
7429 {
7430 int mul, opcode;
7431
7432 switch (dev_priv->rps.cz_freq) {
7433 case 200:
7434 mul = 5;
7435 break;
7436 case 267:
7437 mul = 6;
7438 break;
7439 case 320:
7440 case 333:
7441 case 400:
7442 mul = 8;
7443 break;
7444 default:
7445 return -1;
7446 }
7447
7448 opcode = (DIV_ROUND_CLOSEST((val * 2 * mul), dev_priv->rps.cz_freq) * 2);
7449
7450 return opcode;
7451 }
7452
7453 int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val)
7454 {
7455 int ret = -1;
7456
7457 if (IS_CHERRYVIEW(dev_priv->dev))
7458 ret = chv_gpu_freq(dev_priv, val);
7459 else if (IS_VALLEYVIEW(dev_priv->dev))
7460 ret = byt_gpu_freq(dev_priv, val);
7461
7462 return ret;
7463 }
7464
7465 int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val)
7466 {
7467 int ret = -1;
7468
7469 if (IS_CHERRYVIEW(dev_priv->dev))
7470 ret = chv_freq_opcode(dev_priv, val);
7471 else if (IS_VALLEYVIEW(dev_priv->dev))
7472 ret = byt_freq_opcode(dev_priv, val);
7473
7474 return ret;
7475 }
7476
7477 void intel_pm_setup(struct drm_device *dev)
7478 {
7479 struct drm_i915_private *dev_priv = dev->dev_private;
7480
7481 mutex_init(&dev_priv->rps.hw_lock);
7482
7483 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
7484 intel_gen6_powersave_work);
7485
7486 dev_priv->pm.suspended = false;
7487 dev_priv->pm._irqs_disabled = false;
7488 }
Linux kernel - Deliverables
This page took 0.22782 seconds and 6 git commands to generate.