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drm/i915: Add 180 degree primary plane rotation support
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_pm.c
1 /*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28 #include <linux/cpufreq.h>
29 #include "i915_drv.h"
30 #include "intel_drv.h"
31 #include "../../../platform/x86/intel_ips.h"
32 #include <linux/module.h>
33 #include <linux/vgaarb.h>
34 #include <drm/i915_powerwell.h>
35 #include <linux/pm_runtime.h>
36
37 /**
38 * RC6 is a special power stage which allows the GPU to enter an very
39 * low-voltage mode when idle, using down to 0V while at this stage. This
40 * stage is entered automatically when the GPU is idle when RC6 support is
41 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
42 *
43 * There are different RC6 modes available in Intel GPU, which differentiate
44 * among each other with the latency required to enter and leave RC6 and
45 * voltage consumed by the GPU in different states.
46 *
47 * The combination of the following flags define which states GPU is allowed
48 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
49 * RC6pp is deepest RC6. Their support by hardware varies according to the
50 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
51 * which brings the most power savings; deeper states save more power, but
52 * require higher latency to switch to and wake up.
53 */
54 #define INTEL_RC6_ENABLE (1<<0)
55 #define INTEL_RC6p_ENABLE (1<<1)
56 #define INTEL_RC6pp_ENABLE (1<<2)
57
58 /* FBC, or Frame Buffer Compression, is a technique employed to compress the
59 * framebuffer contents in-memory, aiming at reducing the required bandwidth
60 * during in-memory transfers and, therefore, reduce the power packet.
61 *
62 * The benefits of FBC are mostly visible with solid backgrounds and
63 * variation-less patterns.
64 *
65 * FBC-related functionality can be enabled by the means of the
66 * i915.i915_enable_fbc parameter
67 */
68
69 static void i8xx_disable_fbc(struct drm_device *dev)
70 {
71 struct drm_i915_private *dev_priv = dev->dev_private;
72 u32 fbc_ctl;
73
74 /* Disable compression */
75 fbc_ctl = I915_READ(FBC_CONTROL);
76 if ((fbc_ctl & FBC_CTL_EN) == 0)
77 return;
78
79 fbc_ctl &= ~FBC_CTL_EN;
80 I915_WRITE(FBC_CONTROL, fbc_ctl);
81
82 /* Wait for compressing bit to clear */
83 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
84 DRM_DEBUG_KMS("FBC idle timed out\n");
85 return;
86 }
87
88 DRM_DEBUG_KMS("disabled FBC\n");
89 }
90
91 static void i8xx_enable_fbc(struct drm_crtc *crtc)
92 {
93 struct drm_device *dev = crtc->dev;
94 struct drm_i915_private *dev_priv = dev->dev_private;
95 struct drm_framebuffer *fb = crtc->primary->fb;
96 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
97 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
98 int cfb_pitch;
99 int i;
100 u32 fbc_ctl;
101
102 cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
103 if (fb->pitches[0] < cfb_pitch)
104 cfb_pitch = fb->pitches[0];
105
106 /* FBC_CTL wants 32B or 64B units */
107 if (IS_GEN2(dev))
108 cfb_pitch = (cfb_pitch / 32) - 1;
109 else
110 cfb_pitch = (cfb_pitch / 64) - 1;
111
112 /* Clear old tags */
113 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
114 I915_WRITE(FBC_TAG + (i * 4), 0);
115
116 if (IS_GEN4(dev)) {
117 u32 fbc_ctl2;
118
119 /* Set it up... */
120 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
121 fbc_ctl2 |= FBC_CTL_PLANE(intel_crtc->plane);
122 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
123 I915_WRITE(FBC_FENCE_OFF, crtc->y);
124 }
125
126 /* enable it... */
127 fbc_ctl = I915_READ(FBC_CONTROL);
128 fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT;
129 fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
130 if (IS_I945GM(dev))
131 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
132 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
133 fbc_ctl |= obj->fence_reg;
134 I915_WRITE(FBC_CONTROL, fbc_ctl);
135
136 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c\n",
137 cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
138 }
139
140 static bool i8xx_fbc_enabled(struct drm_device *dev)
141 {
142 struct drm_i915_private *dev_priv = dev->dev_private;
143
144 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
145 }
146
147 static void g4x_enable_fbc(struct drm_crtc *crtc)
148 {
149 struct drm_device *dev = crtc->dev;
150 struct drm_i915_private *dev_priv = dev->dev_private;
151 struct drm_framebuffer *fb = crtc->primary->fb;
152 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
153 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
154 u32 dpfc_ctl;
155
156 dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane) | DPFC_SR_EN;
157 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
158 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
159 else
160 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
161 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
162
163 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
164
165 /* enable it... */
166 I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
167
168 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
169 }
170
171 static void g4x_disable_fbc(struct drm_device *dev)
172 {
173 struct drm_i915_private *dev_priv = dev->dev_private;
174 u32 dpfc_ctl;
175
176 /* Disable compression */
177 dpfc_ctl = I915_READ(DPFC_CONTROL);
178 if (dpfc_ctl & DPFC_CTL_EN) {
179 dpfc_ctl &= ~DPFC_CTL_EN;
180 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
181
182 DRM_DEBUG_KMS("disabled FBC\n");
183 }
184 }
185
186 static bool g4x_fbc_enabled(struct drm_device *dev)
187 {
188 struct drm_i915_private *dev_priv = dev->dev_private;
189
190 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
191 }
192
193 static void sandybridge_blit_fbc_update(struct drm_device *dev)
194 {
195 struct drm_i915_private *dev_priv = dev->dev_private;
196 u32 blt_ecoskpd;
197
198 /* Make sure blitter notifies FBC of writes */
199
200 /* Blitter is part of Media powerwell on VLV. No impact of
201 * his param in other platforms for now */
202 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_MEDIA);
203
204 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
205 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
206 GEN6_BLITTER_LOCK_SHIFT;
207 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
208 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
209 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
210 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
211 GEN6_BLITTER_LOCK_SHIFT);
212 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
213 POSTING_READ(GEN6_BLITTER_ECOSKPD);
214
215 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_MEDIA);
216 }
217
218 static void ironlake_enable_fbc(struct drm_crtc *crtc)
219 {
220 struct drm_device *dev = crtc->dev;
221 struct drm_i915_private *dev_priv = dev->dev_private;
222 struct drm_framebuffer *fb = crtc->primary->fb;
223 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
224 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
225 u32 dpfc_ctl;
226
227 dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane);
228 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
229 dev_priv->fbc.threshold++;
230
231 switch (dev_priv->fbc.threshold) {
232 case 4:
233 case 3:
234 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
235 break;
236 case 2:
237 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
238 break;
239 case 1:
240 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
241 break;
242 }
243 dpfc_ctl |= DPFC_CTL_FENCE_EN;
244 if (IS_GEN5(dev))
245 dpfc_ctl |= obj->fence_reg;
246
247 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
248 I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
249 /* enable it... */
250 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
251
252 if (IS_GEN6(dev)) {
253 I915_WRITE(SNB_DPFC_CTL_SA,
254 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
255 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
256 sandybridge_blit_fbc_update(dev);
257 }
258
259 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
260 }
261
262 static void ironlake_disable_fbc(struct drm_device *dev)
263 {
264 struct drm_i915_private *dev_priv = dev->dev_private;
265 u32 dpfc_ctl;
266
267 /* Disable compression */
268 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
269 if (dpfc_ctl & DPFC_CTL_EN) {
270 dpfc_ctl &= ~DPFC_CTL_EN;
271 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
272
273 DRM_DEBUG_KMS("disabled FBC\n");
274 }
275 }
276
277 static bool ironlake_fbc_enabled(struct drm_device *dev)
278 {
279 struct drm_i915_private *dev_priv = dev->dev_private;
280
281 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
282 }
283
284 static void gen7_enable_fbc(struct drm_crtc *crtc)
285 {
286 struct drm_device *dev = crtc->dev;
287 struct drm_i915_private *dev_priv = dev->dev_private;
288 struct drm_framebuffer *fb = crtc->primary->fb;
289 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
290 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
291 u32 dpfc_ctl;
292
293 dpfc_ctl = IVB_DPFC_CTL_PLANE(intel_crtc->plane);
294 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
295 dev_priv->fbc.threshold++;
296
297 switch (dev_priv->fbc.threshold) {
298 case 4:
299 case 3:
300 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
301 break;
302 case 2:
303 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
304 break;
305 case 1:
306 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
307 break;
308 }
309
310 dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
311
312 if (dev_priv->fbc.false_color)
313 dpfc_ctl |= FBC_CTL_FALSE_COLOR;
314
315 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
316
317 if (IS_IVYBRIDGE(dev)) {
318 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
319 I915_WRITE(ILK_DISPLAY_CHICKEN1,
320 I915_READ(ILK_DISPLAY_CHICKEN1) |
321 ILK_FBCQ_DIS);
322 } else {
323 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
324 I915_WRITE(CHICKEN_PIPESL_1(intel_crtc->pipe),
325 I915_READ(CHICKEN_PIPESL_1(intel_crtc->pipe)) |
326 HSW_FBCQ_DIS);
327 }
328
329 I915_WRITE(SNB_DPFC_CTL_SA,
330 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
331 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
332
333 sandybridge_blit_fbc_update(dev);
334
335 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
336 }
337
338 bool intel_fbc_enabled(struct drm_device *dev)
339 {
340 struct drm_i915_private *dev_priv = dev->dev_private;
341
342 if (!dev_priv->display.fbc_enabled)
343 return false;
344
345 return dev_priv->display.fbc_enabled(dev);
346 }
347
348 static void intel_fbc_work_fn(struct work_struct *__work)
349 {
350 struct intel_fbc_work *work =
351 container_of(to_delayed_work(__work),
352 struct intel_fbc_work, work);
353 struct drm_device *dev = work->crtc->dev;
354 struct drm_i915_private *dev_priv = dev->dev_private;
355
356 mutex_lock(&dev->struct_mutex);
357 if (work == dev_priv->fbc.fbc_work) {
358 /* Double check that we haven't switched fb without cancelling
359 * the prior work.
360 */
361 if (work->crtc->primary->fb == work->fb) {
362 dev_priv->display.enable_fbc(work->crtc);
363
364 dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;
365 dev_priv->fbc.fb_id = work->crtc->primary->fb->base.id;
366 dev_priv->fbc.y = work->crtc->y;
367 }
368
369 dev_priv->fbc.fbc_work = NULL;
370 }
371 mutex_unlock(&dev->struct_mutex);
372
373 kfree(work);
374 }
375
376 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
377 {
378 if (dev_priv->fbc.fbc_work == NULL)
379 return;
380
381 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
382
383 /* Synchronisation is provided by struct_mutex and checking of
384 * dev_priv->fbc.fbc_work, so we can perform the cancellation
385 * entirely asynchronously.
386 */
387 if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
388 /* tasklet was killed before being run, clean up */
389 kfree(dev_priv->fbc.fbc_work);
390
391 /* Mark the work as no longer wanted so that if it does
392 * wake-up (because the work was already running and waiting
393 * for our mutex), it will discover that is no longer
394 * necessary to run.
395 */
396 dev_priv->fbc.fbc_work = NULL;
397 }
398
399 static void intel_enable_fbc(struct drm_crtc *crtc)
400 {
401 struct intel_fbc_work *work;
402 struct drm_device *dev = crtc->dev;
403 struct drm_i915_private *dev_priv = dev->dev_private;
404
405 if (!dev_priv->display.enable_fbc)
406 return;
407
408 intel_cancel_fbc_work(dev_priv);
409
410 work = kzalloc(sizeof(*work), GFP_KERNEL);
411 if (work == NULL) {
412 DRM_ERROR("Failed to allocate FBC work structure\n");
413 dev_priv->display.enable_fbc(crtc);
414 return;
415 }
416
417 work->crtc = crtc;
418 work->fb = crtc->primary->fb;
419 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
420
421 dev_priv->fbc.fbc_work = work;
422
423 /* Delay the actual enabling to let pageflipping cease and the
424 * display to settle before starting the compression. Note that
425 * this delay also serves a second purpose: it allows for a
426 * vblank to pass after disabling the FBC before we attempt
427 * to modify the control registers.
428 *
429 * A more complicated solution would involve tracking vblanks
430 * following the termination of the page-flipping sequence
431 * and indeed performing the enable as a co-routine and not
432 * waiting synchronously upon the vblank.
433 *
434 * WaFbcWaitForVBlankBeforeEnable:ilk,snb
435 */
436 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
437 }
438
439 void intel_disable_fbc(struct drm_device *dev)
440 {
441 struct drm_i915_private *dev_priv = dev->dev_private;
442
443 intel_cancel_fbc_work(dev_priv);
444
445 if (!dev_priv->display.disable_fbc)
446 return;
447
448 dev_priv->display.disable_fbc(dev);
449 dev_priv->fbc.plane = -1;
450 }
451
452 static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
453 enum no_fbc_reason reason)
454 {
455 if (dev_priv->fbc.no_fbc_reason == reason)
456 return false;
457
458 dev_priv->fbc.no_fbc_reason = reason;
459 return true;
460 }
461
462 /**
463 * intel_update_fbc - enable/disable FBC as needed
464 * @dev: the drm_device
465 *
466 * Set up the framebuffer compression hardware at mode set time. We
467 * enable it if possible:
468 * - plane A only (on pre-965)
469 * - no pixel mulitply/line duplication
470 * - no alpha buffer discard
471 * - no dual wide
472 * - framebuffer <= max_hdisplay in width, max_vdisplay in height
473 *
474 * We can't assume that any compression will take place (worst case),
475 * so the compressed buffer has to be the same size as the uncompressed
476 * one. It also must reside (along with the line length buffer) in
477 * stolen memory.
478 *
479 * We need to enable/disable FBC on a global basis.
480 */
481 void intel_update_fbc(struct drm_device *dev)
482 {
483 struct drm_i915_private *dev_priv = dev->dev_private;
484 struct drm_crtc *crtc = NULL, *tmp_crtc;
485 struct intel_crtc *intel_crtc;
486 struct drm_framebuffer *fb;
487 struct drm_i915_gem_object *obj;
488 const struct drm_display_mode *adjusted_mode;
489 unsigned int max_width, max_height;
490
491 if (!HAS_FBC(dev)) {
492 set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED);
493 return;
494 }
495
496 if (!i915.powersave) {
497 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
498 DRM_DEBUG_KMS("fbc disabled per module param\n");
499 return;
500 }
501
502 /*
503 * If FBC is already on, we just have to verify that we can
504 * keep it that way...
505 * Need to disable if:
506 * - more than one pipe is active
507 * - changing FBC params (stride, fence, mode)
508 * - new fb is too large to fit in compressed buffer
509 * - going to an unsupported config (interlace, pixel multiply, etc.)
510 */
511 for_each_crtc(dev, tmp_crtc) {
512 if (intel_crtc_active(tmp_crtc) &&
513 to_intel_crtc(tmp_crtc)->primary_enabled) {
514 if (crtc) {
515 if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
516 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
517 goto out_disable;
518 }
519 crtc = tmp_crtc;
520 }
521 }
522
523 if (!crtc || crtc->primary->fb == NULL) {
524 if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
525 DRM_DEBUG_KMS("no output, disabling\n");
526 goto out_disable;
527 }
528
529 intel_crtc = to_intel_crtc(crtc);
530 fb = crtc->primary->fb;
531 obj = intel_fb_obj(fb);
532 adjusted_mode = &intel_crtc->config.adjusted_mode;
533
534 if (i915.enable_fbc < 0) {
535 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
536 DRM_DEBUG_KMS("disabled per chip default\n");
537 goto out_disable;
538 }
539 if (!i915.enable_fbc) {
540 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
541 DRM_DEBUG_KMS("fbc disabled per module param\n");
542 goto out_disable;
543 }
544 if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ||
545 (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
546 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
547 DRM_DEBUG_KMS("mode incompatible with compression, "
548 "disabling\n");
549 goto out_disable;
550 }
551
552 if (INTEL_INFO(dev)->gen >= 8 || IS_HASWELL(dev)) {
553 max_width = 4096;
554 max_height = 4096;
555 } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
556 max_width = 4096;
557 max_height = 2048;
558 } else {
559 max_width = 2048;
560 max_height = 1536;
561 }
562 if (intel_crtc->config.pipe_src_w > max_width ||
563 intel_crtc->config.pipe_src_h > max_height) {
564 if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
565 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
566 goto out_disable;
567 }
568 if ((INTEL_INFO(dev)->gen < 4 || HAS_DDI(dev)) &&
569 intel_crtc->plane != PLANE_A) {
570 if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
571 DRM_DEBUG_KMS("plane not A, disabling compression\n");
572 goto out_disable;
573 }
574
575 /* The use of a CPU fence is mandatory in order to detect writes
576 * by the CPU to the scanout and trigger updates to the FBC.
577 */
578 if (obj->tiling_mode != I915_TILING_X ||
579 obj->fence_reg == I915_FENCE_REG_NONE) {
580 if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED))
581 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
582 goto out_disable;
583 }
584 if (INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
585 to_intel_plane(crtc->primary)->rotation != BIT(DRM_ROTATE_0)) {
586 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
587 DRM_DEBUG_KMS("Rotation unsupported, disabling\n");
588 goto out_disable;
589 }
590
591 /* If the kernel debugger is active, always disable compression */
592 if (in_dbg_master())
593 goto out_disable;
594
595 if (i915_gem_stolen_setup_compression(dev, obj->base.size,
596 drm_format_plane_cpp(fb->pixel_format, 0))) {
597 if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL))
598 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
599 goto out_disable;
600 }
601
602 /* If the scanout has not changed, don't modify the FBC settings.
603 * Note that we make the fundamental assumption that the fb->obj
604 * cannot be unpinned (and have its GTT offset and fence revoked)
605 * without first being decoupled from the scanout and FBC disabled.
606 */
607 if (dev_priv->fbc.plane == intel_crtc->plane &&
608 dev_priv->fbc.fb_id == fb->base.id &&
609 dev_priv->fbc.y == crtc->y)
610 return;
611
612 if (intel_fbc_enabled(dev)) {
613 /* We update FBC along two paths, after changing fb/crtc
614 * configuration (modeswitching) and after page-flipping
615 * finishes. For the latter, we know that not only did
616 * we disable the FBC at the start of the page-flip
617 * sequence, but also more than one vblank has passed.
618 *
619 * For the former case of modeswitching, it is possible
620 * to switch between two FBC valid configurations
621 * instantaneously so we do need to disable the FBC
622 * before we can modify its control registers. We also
623 * have to wait for the next vblank for that to take
624 * effect. However, since we delay enabling FBC we can
625 * assume that a vblank has passed since disabling and
626 * that we can safely alter the registers in the deferred
627 * callback.
628 *
629 * In the scenario that we go from a valid to invalid
630 * and then back to valid FBC configuration we have
631 * no strict enforcement that a vblank occurred since
632 * disabling the FBC. However, along all current pipe
633 * disabling paths we do need to wait for a vblank at
634 * some point. And we wait before enabling FBC anyway.
635 */
636 DRM_DEBUG_KMS("disabling active FBC for update\n");
637 intel_disable_fbc(dev);
638 }
639
640 intel_enable_fbc(crtc);
641 dev_priv->fbc.no_fbc_reason = FBC_OK;
642 return;
643
644 out_disable:
645 /* Multiple disables should be harmless */
646 if (intel_fbc_enabled(dev)) {
647 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
648 intel_disable_fbc(dev);
649 }
650 i915_gem_stolen_cleanup_compression(dev);
651 }
652
653 static void i915_pineview_get_mem_freq(struct drm_device *dev)
654 {
655 struct drm_i915_private *dev_priv = dev->dev_private;
656 u32 tmp;
657
658 tmp = I915_READ(CLKCFG);
659
660 switch (tmp & CLKCFG_FSB_MASK) {
661 case CLKCFG_FSB_533:
662 dev_priv->fsb_freq = 533; /* 133*4 */
663 break;
664 case CLKCFG_FSB_800:
665 dev_priv->fsb_freq = 800; /* 200*4 */
666 break;
667 case CLKCFG_FSB_667:
668 dev_priv->fsb_freq = 667; /* 167*4 */
669 break;
670 case CLKCFG_FSB_400:
671 dev_priv->fsb_freq = 400; /* 100*4 */
672 break;
673 }
674
675 switch (tmp & CLKCFG_MEM_MASK) {
676 case CLKCFG_MEM_533:
677 dev_priv->mem_freq = 533;
678 break;
679 case CLKCFG_MEM_667:
680 dev_priv->mem_freq = 667;
681 break;
682 case CLKCFG_MEM_800:
683 dev_priv->mem_freq = 800;
684 break;
685 }
686
687 /* detect pineview DDR3 setting */
688 tmp = I915_READ(CSHRDDR3CTL);
689 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
690 }
691
692 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
693 {
694 struct drm_i915_private *dev_priv = dev->dev_private;
695 u16 ddrpll, csipll;
696
697 ddrpll = I915_READ16(DDRMPLL1);
698 csipll = I915_READ16(CSIPLL0);
699
700 switch (ddrpll & 0xff) {
701 case 0xc:
702 dev_priv->mem_freq = 800;
703 break;
704 case 0x10:
705 dev_priv->mem_freq = 1066;
706 break;
707 case 0x14:
708 dev_priv->mem_freq = 1333;
709 break;
710 case 0x18:
711 dev_priv->mem_freq = 1600;
712 break;
713 default:
714 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
715 ddrpll & 0xff);
716 dev_priv->mem_freq = 0;
717 break;
718 }
719
720 dev_priv->ips.r_t = dev_priv->mem_freq;
721
722 switch (csipll & 0x3ff) {
723 case 0x00c:
724 dev_priv->fsb_freq = 3200;
725 break;
726 case 0x00e:
727 dev_priv->fsb_freq = 3733;
728 break;
729 case 0x010:
730 dev_priv->fsb_freq = 4266;
731 break;
732 case 0x012:
733 dev_priv->fsb_freq = 4800;
734 break;
735 case 0x014:
736 dev_priv->fsb_freq = 5333;
737 break;
738 case 0x016:
739 dev_priv->fsb_freq = 5866;
740 break;
741 case 0x018:
742 dev_priv->fsb_freq = 6400;
743 break;
744 default:
745 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
746 csipll & 0x3ff);
747 dev_priv->fsb_freq = 0;
748 break;
749 }
750
751 if (dev_priv->fsb_freq == 3200) {
752 dev_priv->ips.c_m = 0;
753 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
754 dev_priv->ips.c_m = 1;
755 } else {
756 dev_priv->ips.c_m = 2;
757 }
758 }
759
760 static const struct cxsr_latency cxsr_latency_table[] = {
761 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
762 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
763 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
764 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
765 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
766
767 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
768 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
769 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
770 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
771 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
772
773 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
774 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
775 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
776 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
777 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
778
779 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
780 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
781 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
782 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
783 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
784
785 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
786 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
787 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
788 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
789 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
790
791 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
792 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
793 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
794 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
795 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
796 };
797
798 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
799 int is_ddr3,
800 int fsb,
801 int mem)
802 {
803 const struct cxsr_latency *latency;
804 int i;
805
806 if (fsb == 0 || mem == 0)
807 return NULL;
808
809 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
810 latency = &cxsr_latency_table[i];
811 if (is_desktop == latency->is_desktop &&
812 is_ddr3 == latency->is_ddr3 &&
813 fsb == latency->fsb_freq && mem == latency->mem_freq)
814 return latency;
815 }
816
817 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
818
819 return NULL;
820 }
821
822 void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
823 {
824 struct drm_device *dev = dev_priv->dev;
825 u32 val;
826
827 if (IS_VALLEYVIEW(dev)) {
828 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
829 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
830 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
831 } else if (IS_PINEVIEW(dev)) {
832 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
833 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
834 I915_WRITE(DSPFW3, val);
835 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
836 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
837 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
838 I915_WRITE(FW_BLC_SELF, val);
839 } else if (IS_I915GM(dev)) {
840 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
841 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
842 I915_WRITE(INSTPM, val);
843 } else {
844 return;
845 }
846
847 DRM_DEBUG_KMS("memory self-refresh is %s\n",
848 enable ? "enabled" : "disabled");
849 }
850
851 /*
852 * Latency for FIFO fetches is dependent on several factors:
853 * - memory configuration (speed, channels)
854 * - chipset
855 * - current MCH state
856 * It can be fairly high in some situations, so here we assume a fairly
857 * pessimal value. It's a tradeoff between extra memory fetches (if we
858 * set this value too high, the FIFO will fetch frequently to stay full)
859 * and power consumption (set it too low to save power and we might see
860 * FIFO underruns and display "flicker").
861 *
862 * A value of 5us seems to be a good balance; safe for very low end
863 * platforms but not overly aggressive on lower latency configs.
864 */
865 static const int latency_ns = 5000;
866
867 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
868 {
869 struct drm_i915_private *dev_priv = dev->dev_private;
870 uint32_t dsparb = I915_READ(DSPARB);
871 int size;
872
873 size = dsparb & 0x7f;
874 if (plane)
875 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
876
877 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
878 plane ? "B" : "A", size);
879
880 return size;
881 }
882
883 static int i830_get_fifo_size(struct drm_device *dev, int plane)
884 {
885 struct drm_i915_private *dev_priv = dev->dev_private;
886 uint32_t dsparb = I915_READ(DSPARB);
887 int size;
888
889 size = dsparb & 0x1ff;
890 if (plane)
891 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
892 size >>= 1; /* Convert to cachelines */
893
894 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
895 plane ? "B" : "A", size);
896
897 return size;
898 }
899
900 static int i845_get_fifo_size(struct drm_device *dev, int plane)
901 {
902 struct drm_i915_private *dev_priv = dev->dev_private;
903 uint32_t dsparb = I915_READ(DSPARB);
904 int size;
905
906 size = dsparb & 0x7f;
907 size >>= 2; /* Convert to cachelines */
908
909 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
910 plane ? "B" : "A",
911 size);
912
913 return size;
914 }
915
916 /* Pineview has different values for various configs */
917 static const struct intel_watermark_params pineview_display_wm = {
918 .fifo_size = PINEVIEW_DISPLAY_FIFO,
919 .max_wm = PINEVIEW_MAX_WM,
920 .default_wm = PINEVIEW_DFT_WM,
921 .guard_size = PINEVIEW_GUARD_WM,
922 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
923 };
924 static const struct intel_watermark_params pineview_display_hplloff_wm = {
925 .fifo_size = PINEVIEW_DISPLAY_FIFO,
926 .max_wm = PINEVIEW_MAX_WM,
927 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
928 .guard_size = PINEVIEW_GUARD_WM,
929 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
930 };
931 static const struct intel_watermark_params pineview_cursor_wm = {
932 .fifo_size = PINEVIEW_CURSOR_FIFO,
933 .max_wm = PINEVIEW_CURSOR_MAX_WM,
934 .default_wm = PINEVIEW_CURSOR_DFT_WM,
935 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
936 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
937 };
938 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
939 .fifo_size = PINEVIEW_CURSOR_FIFO,
940 .max_wm = PINEVIEW_CURSOR_MAX_WM,
941 .default_wm = PINEVIEW_CURSOR_DFT_WM,
942 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
943 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
944 };
945 static const struct intel_watermark_params g4x_wm_info = {
946 .fifo_size = G4X_FIFO_SIZE,
947 .max_wm = G4X_MAX_WM,
948 .default_wm = G4X_MAX_WM,
949 .guard_size = 2,
950 .cacheline_size = G4X_FIFO_LINE_SIZE,
951 };
952 static const struct intel_watermark_params g4x_cursor_wm_info = {
953 .fifo_size = I965_CURSOR_FIFO,
954 .max_wm = I965_CURSOR_MAX_WM,
955 .default_wm = I965_CURSOR_DFT_WM,
956 .guard_size = 2,
957 .cacheline_size = G4X_FIFO_LINE_SIZE,
958 };
959 static const struct intel_watermark_params valleyview_wm_info = {
960 .fifo_size = VALLEYVIEW_FIFO_SIZE,
961 .max_wm = VALLEYVIEW_MAX_WM,
962 .default_wm = VALLEYVIEW_MAX_WM,
963 .guard_size = 2,
964 .cacheline_size = G4X_FIFO_LINE_SIZE,
965 };
966 static const struct intel_watermark_params valleyview_cursor_wm_info = {
967 .fifo_size = I965_CURSOR_FIFO,
968 .max_wm = VALLEYVIEW_CURSOR_MAX_WM,
969 .default_wm = I965_CURSOR_DFT_WM,
970 .guard_size = 2,
971 .cacheline_size = G4X_FIFO_LINE_SIZE,
972 };
973 static const struct intel_watermark_params i965_cursor_wm_info = {
974 .fifo_size = I965_CURSOR_FIFO,
975 .max_wm = I965_CURSOR_MAX_WM,
976 .default_wm = I965_CURSOR_DFT_WM,
977 .guard_size = 2,
978 .cacheline_size = I915_FIFO_LINE_SIZE,
979 };
980 static const struct intel_watermark_params i945_wm_info = {
981 .fifo_size = I945_FIFO_SIZE,
982 .max_wm = I915_MAX_WM,
983 .default_wm = 1,
984 .guard_size = 2,
985 .cacheline_size = I915_FIFO_LINE_SIZE,
986 };
987 static const struct intel_watermark_params i915_wm_info = {
988 .fifo_size = I915_FIFO_SIZE,
989 .max_wm = I915_MAX_WM,
990 .default_wm = 1,
991 .guard_size = 2,
992 .cacheline_size = I915_FIFO_LINE_SIZE,
993 };
994 static const struct intel_watermark_params i830_wm_info = {
995 .fifo_size = I855GM_FIFO_SIZE,
996 .max_wm = I915_MAX_WM,
997 .default_wm = 1,
998 .guard_size = 2,
999 .cacheline_size = I830_FIFO_LINE_SIZE,
1000 };
1001 static const struct intel_watermark_params i845_wm_info = {
1002 .fifo_size = I830_FIFO_SIZE,
1003 .max_wm = I915_MAX_WM,
1004 .default_wm = 1,
1005 .guard_size = 2,
1006 .cacheline_size = I830_FIFO_LINE_SIZE,
1007 };
1008
1009 /**
1010 * intel_calculate_wm - calculate watermark level
1011 * @clock_in_khz: pixel clock
1012 * @wm: chip FIFO params
1013 * @pixel_size: display pixel size
1014 * @latency_ns: memory latency for the platform
1015 *
1016 * Calculate the watermark level (the level at which the display plane will
1017 * start fetching from memory again). Each chip has a different display
1018 * FIFO size and allocation, so the caller needs to figure that out and pass
1019 * in the correct intel_watermark_params structure.
1020 *
1021 * As the pixel clock runs, the FIFO will be drained at a rate that depends
1022 * on the pixel size. When it reaches the watermark level, it'll start
1023 * fetching FIFO line sized based chunks from memory until the FIFO fills
1024 * past the watermark point. If the FIFO drains completely, a FIFO underrun
1025 * will occur, and a display engine hang could result.
1026 */
1027 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
1028 const struct intel_watermark_params *wm,
1029 int fifo_size,
1030 int pixel_size,
1031 unsigned long latency_ns)
1032 {
1033 long entries_required, wm_size;
1034
1035 /*
1036 * Note: we need to make sure we don't overflow for various clock &
1037 * latency values.
1038 * clocks go from a few thousand to several hundred thousand.
1039 * latency is usually a few thousand
1040 */
1041 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
1042 1000;
1043 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
1044
1045 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
1046
1047 wm_size = fifo_size - (entries_required + wm->guard_size);
1048
1049 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
1050
1051 /* Don't promote wm_size to unsigned... */
1052 if (wm_size > (long)wm->max_wm)
1053 wm_size = wm->max_wm;
1054 if (wm_size <= 0)
1055 wm_size = wm->default_wm;
1056 return wm_size;
1057 }
1058
1059 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1060 {
1061 struct drm_crtc *crtc, *enabled = NULL;
1062
1063 for_each_crtc(dev, crtc) {
1064 if (intel_crtc_active(crtc)) {
1065 if (enabled)
1066 return NULL;
1067 enabled = crtc;
1068 }
1069 }
1070
1071 return enabled;
1072 }
1073
1074 static void pineview_update_wm(struct drm_crtc *unused_crtc)
1075 {
1076 struct drm_device *dev = unused_crtc->dev;
1077 struct drm_i915_private *dev_priv = dev->dev_private;
1078 struct drm_crtc *crtc;
1079 const struct cxsr_latency *latency;
1080 u32 reg;
1081 unsigned long wm;
1082
1083 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1084 dev_priv->fsb_freq, dev_priv->mem_freq);
1085 if (!latency) {
1086 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1087 intel_set_memory_cxsr(dev_priv, false);
1088 return;
1089 }
1090
1091 crtc = single_enabled_crtc(dev);
1092 if (crtc) {
1093 const struct drm_display_mode *adjusted_mode;
1094 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1095 int clock;
1096
1097 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1098 clock = adjusted_mode->crtc_clock;
1099
1100 /* Display SR */
1101 wm = intel_calculate_wm(clock, &pineview_display_wm,
1102 pineview_display_wm.fifo_size,
1103 pixel_size, latency->display_sr);
1104 reg = I915_READ(DSPFW1);
1105 reg &= ~DSPFW_SR_MASK;
1106 reg |= wm << DSPFW_SR_SHIFT;
1107 I915_WRITE(DSPFW1, reg);
1108 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1109
1110 /* cursor SR */
1111 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1112 pineview_display_wm.fifo_size,
1113 pixel_size, latency->cursor_sr);
1114 reg = I915_READ(DSPFW3);
1115 reg &= ~DSPFW_CURSOR_SR_MASK;
1116 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1117 I915_WRITE(DSPFW3, reg);
1118
1119 /* Display HPLL off SR */
1120 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1121 pineview_display_hplloff_wm.fifo_size,
1122 pixel_size, latency->display_hpll_disable);
1123 reg = I915_READ(DSPFW3);
1124 reg &= ~DSPFW_HPLL_SR_MASK;
1125 reg |= wm & DSPFW_HPLL_SR_MASK;
1126 I915_WRITE(DSPFW3, reg);
1127
1128 /* cursor HPLL off SR */
1129 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1130 pineview_display_hplloff_wm.fifo_size,
1131 pixel_size, latency->cursor_hpll_disable);
1132 reg = I915_READ(DSPFW3);
1133 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1134 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1135 I915_WRITE(DSPFW3, reg);
1136 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1137
1138 intel_set_memory_cxsr(dev_priv, true);
1139 } else {
1140 intel_set_memory_cxsr(dev_priv, false);
1141 }
1142 }
1143
1144 static bool g4x_compute_wm0(struct drm_device *dev,
1145 int plane,
1146 const struct intel_watermark_params *display,
1147 int display_latency_ns,
1148 const struct intel_watermark_params *cursor,
1149 int cursor_latency_ns,
1150 int *plane_wm,
1151 int *cursor_wm)
1152 {
1153 struct drm_crtc *crtc;
1154 const struct drm_display_mode *adjusted_mode;
1155 int htotal, hdisplay, clock, pixel_size;
1156 int line_time_us, line_count;
1157 int entries, tlb_miss;
1158
1159 crtc = intel_get_crtc_for_plane(dev, plane);
1160 if (!intel_crtc_active(crtc)) {
1161 *cursor_wm = cursor->guard_size;
1162 *plane_wm = display->guard_size;
1163 return false;
1164 }
1165
1166 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1167 clock = adjusted_mode->crtc_clock;
1168 htotal = adjusted_mode->crtc_htotal;
1169 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1170 pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1171
1172 /* Use the small buffer method to calculate plane watermark */
1173 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1174 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1175 if (tlb_miss > 0)
1176 entries += tlb_miss;
1177 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1178 *plane_wm = entries + display->guard_size;
1179 if (*plane_wm > (int)display->max_wm)
1180 *plane_wm = display->max_wm;
1181
1182 /* Use the large buffer method to calculate cursor watermark */
1183 line_time_us = max(htotal * 1000 / clock, 1);
1184 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1185 entries = line_count * to_intel_crtc(crtc)->cursor_width * pixel_size;
1186 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1187 if (tlb_miss > 0)
1188 entries += tlb_miss;
1189 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1190 *cursor_wm = entries + cursor->guard_size;
1191 if (*cursor_wm > (int)cursor->max_wm)
1192 *cursor_wm = (int)cursor->max_wm;
1193
1194 return true;
1195 }
1196
1197 /*
1198 * Check the wm result.
1199 *
1200 * If any calculated watermark values is larger than the maximum value that
1201 * can be programmed into the associated watermark register, that watermark
1202 * must be disabled.
1203 */
1204 static bool g4x_check_srwm(struct drm_device *dev,
1205 int display_wm, int cursor_wm,
1206 const struct intel_watermark_params *display,
1207 const struct intel_watermark_params *cursor)
1208 {
1209 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1210 display_wm, cursor_wm);
1211
1212 if (display_wm > display->max_wm) {
1213 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1214 display_wm, display->max_wm);
1215 return false;
1216 }
1217
1218 if (cursor_wm > cursor->max_wm) {
1219 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1220 cursor_wm, cursor->max_wm);
1221 return false;
1222 }
1223
1224 if (!(display_wm || cursor_wm)) {
1225 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1226 return false;
1227 }
1228
1229 return true;
1230 }
1231
1232 static bool g4x_compute_srwm(struct drm_device *dev,
1233 int plane,
1234 int latency_ns,
1235 const struct intel_watermark_params *display,
1236 const struct intel_watermark_params *cursor,
1237 int *display_wm, int *cursor_wm)
1238 {
1239 struct drm_crtc *crtc;
1240 const struct drm_display_mode *adjusted_mode;
1241 int hdisplay, htotal, pixel_size, clock;
1242 unsigned long line_time_us;
1243 int line_count, line_size;
1244 int small, large;
1245 int entries;
1246
1247 if (!latency_ns) {
1248 *display_wm = *cursor_wm = 0;
1249 return false;
1250 }
1251
1252 crtc = intel_get_crtc_for_plane(dev, plane);
1253 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1254 clock = adjusted_mode->crtc_clock;
1255 htotal = adjusted_mode->crtc_htotal;
1256 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1257 pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1258
1259 line_time_us = max(htotal * 1000 / clock, 1);
1260 line_count = (latency_ns / line_time_us + 1000) / 1000;
1261 line_size = hdisplay * pixel_size;
1262
1263 /* Use the minimum of the small and large buffer method for primary */
1264 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1265 large = line_count * line_size;
1266
1267 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1268 *display_wm = entries + display->guard_size;
1269
1270 /* calculate the self-refresh watermark for display cursor */
1271 entries = line_count * pixel_size * to_intel_crtc(crtc)->cursor_width;
1272 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1273 *cursor_wm = entries + cursor->guard_size;
1274
1275 return g4x_check_srwm(dev,
1276 *display_wm, *cursor_wm,
1277 display, cursor);
1278 }
1279
1280 static bool vlv_compute_drain_latency(struct drm_crtc *crtc,
1281 int pixel_size,
1282 int *prec_mult,
1283 int *drain_latency)
1284 {
1285 int entries;
1286 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
1287
1288 if (WARN(clock == 0, "Pixel clock is zero!\n"))
1289 return false;
1290
1291 if (WARN(pixel_size == 0, "Pixel size is zero!\n"))
1292 return false;
1293
1294 entries = DIV_ROUND_UP(clock, 1000) * pixel_size;
1295 *prec_mult = (entries > 128) ? DRAIN_LATENCY_PRECISION_64 :
1296 DRAIN_LATENCY_PRECISION_32;
1297 *drain_latency = (64 * (*prec_mult) * 4) / entries;
1298
1299 if (*drain_latency > DRAIN_LATENCY_MASK)
1300 *drain_latency = DRAIN_LATENCY_MASK;
1301
1302 return true;
1303 }
1304
1305 /*
1306 * Update drain latency registers of memory arbiter
1307 *
1308 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1309 * to be programmed. Each plane has a drain latency multiplier and a drain
1310 * latency value.
1311 */
1312
1313 static void vlv_update_drain_latency(struct drm_crtc *crtc)
1314 {
1315 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1316 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1317 int pixel_size;
1318 int drain_latency;
1319 enum pipe pipe = intel_crtc->pipe;
1320 int plane_prec, prec_mult, plane_dl;
1321
1322 plane_dl = I915_READ(VLV_DDL(pipe)) & ~(DDL_PLANE_PRECISION_64 |
1323 DRAIN_LATENCY_MASK | DDL_CURSOR_PRECISION_64 |
1324 (DRAIN_LATENCY_MASK << DDL_CURSOR_SHIFT));
1325
1326 if (!intel_crtc_active(crtc)) {
1327 I915_WRITE(VLV_DDL(pipe), plane_dl);
1328 return;
1329 }
1330
1331 /* Primary plane Drain Latency */
1332 pixel_size = crtc->primary->fb->bits_per_pixel / 8; /* BPP */
1333 if (vlv_compute_drain_latency(crtc, pixel_size, &prec_mult, &drain_latency)) {
1334 plane_prec = (prec_mult == DRAIN_LATENCY_PRECISION_64) ?
1335 DDL_PLANE_PRECISION_64 :
1336 DDL_PLANE_PRECISION_32;
1337 plane_dl |= plane_prec | drain_latency;
1338 }
1339
1340 /* Cursor Drain Latency
1341 * BPP is always 4 for cursor
1342 */
1343 pixel_size = 4;
1344
1345 /* Program cursor DL only if it is enabled */
1346 if (intel_crtc->cursor_base &&
1347 vlv_compute_drain_latency(crtc, pixel_size, &prec_mult, &drain_latency)) {
1348 plane_prec = (prec_mult == DRAIN_LATENCY_PRECISION_64) ?
1349 DDL_CURSOR_PRECISION_64 :
1350 DDL_CURSOR_PRECISION_32;
1351 plane_dl |= plane_prec | (drain_latency << DDL_CURSOR_SHIFT);
1352 }
1353
1354 I915_WRITE(VLV_DDL(pipe), plane_dl);
1355 }
1356
1357 #define single_plane_enabled(mask) is_power_of_2(mask)
1358
1359 static void valleyview_update_wm(struct drm_crtc *crtc)
1360 {
1361 struct drm_device *dev = crtc->dev;
1362 static const int sr_latency_ns = 12000;
1363 struct drm_i915_private *dev_priv = dev->dev_private;
1364 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1365 int plane_sr, cursor_sr;
1366 int ignore_plane_sr, ignore_cursor_sr;
1367 unsigned int enabled = 0;
1368 bool cxsr_enabled;
1369
1370 vlv_update_drain_latency(crtc);
1371
1372 if (g4x_compute_wm0(dev, PIPE_A,
1373 &valleyview_wm_info, latency_ns,
1374 &valleyview_cursor_wm_info, latency_ns,
1375 &planea_wm, &cursora_wm))
1376 enabled |= 1 << PIPE_A;
1377
1378 if (g4x_compute_wm0(dev, PIPE_B,
1379 &valleyview_wm_info, latency_ns,
1380 &valleyview_cursor_wm_info, latency_ns,
1381 &planeb_wm, &cursorb_wm))
1382 enabled |= 1 << PIPE_B;
1383
1384 if (single_plane_enabled(enabled) &&
1385 g4x_compute_srwm(dev, ffs(enabled) - 1,
1386 sr_latency_ns,
1387 &valleyview_wm_info,
1388 &valleyview_cursor_wm_info,
1389 &plane_sr, &ignore_cursor_sr) &&
1390 g4x_compute_srwm(dev, ffs(enabled) - 1,
1391 2*sr_latency_ns,
1392 &valleyview_wm_info,
1393 &valleyview_cursor_wm_info,
1394 &ignore_plane_sr, &cursor_sr)) {
1395 cxsr_enabled = true;
1396 } else {
1397 cxsr_enabled = false;
1398 intel_set_memory_cxsr(dev_priv, false);
1399 plane_sr = cursor_sr = 0;
1400 }
1401
1402 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1403 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1404 planea_wm, cursora_wm,
1405 planeb_wm, cursorb_wm,
1406 plane_sr, cursor_sr);
1407
1408 I915_WRITE(DSPFW1,
1409 (plane_sr << DSPFW_SR_SHIFT) |
1410 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1411 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1412 (planea_wm << DSPFW_PLANEA_SHIFT));
1413 I915_WRITE(DSPFW2,
1414 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1415 (cursora_wm << DSPFW_CURSORA_SHIFT));
1416 I915_WRITE(DSPFW3,
1417 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1418 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1419
1420 if (cxsr_enabled)
1421 intel_set_memory_cxsr(dev_priv, true);
1422 }
1423
1424 static void cherryview_update_wm(struct drm_crtc *crtc)
1425 {
1426 struct drm_device *dev = crtc->dev;
1427 static const int sr_latency_ns = 12000;
1428 struct drm_i915_private *dev_priv = dev->dev_private;
1429 int planea_wm, planeb_wm, planec_wm;
1430 int cursora_wm, cursorb_wm, cursorc_wm;
1431 int plane_sr, cursor_sr;
1432 int ignore_plane_sr, ignore_cursor_sr;
1433 unsigned int enabled = 0;
1434 bool cxsr_enabled;
1435
1436 vlv_update_drain_latency(crtc);
1437
1438 if (g4x_compute_wm0(dev, PIPE_A,
1439 &valleyview_wm_info, latency_ns,
1440 &valleyview_cursor_wm_info, latency_ns,
1441 &planea_wm, &cursora_wm))
1442 enabled |= 1 << PIPE_A;
1443
1444 if (g4x_compute_wm0(dev, PIPE_B,
1445 &valleyview_wm_info, latency_ns,
1446 &valleyview_cursor_wm_info, latency_ns,
1447 &planeb_wm, &cursorb_wm))
1448 enabled |= 1 << PIPE_B;
1449
1450 if (g4x_compute_wm0(dev, PIPE_C,
1451 &valleyview_wm_info, latency_ns,
1452 &valleyview_cursor_wm_info, latency_ns,
1453 &planec_wm, &cursorc_wm))
1454 enabled |= 1 << PIPE_C;
1455
1456 if (single_plane_enabled(enabled) &&
1457 g4x_compute_srwm(dev, ffs(enabled) - 1,
1458 sr_latency_ns,
1459 &valleyview_wm_info,
1460 &valleyview_cursor_wm_info,
1461 &plane_sr, &ignore_cursor_sr) &&
1462 g4x_compute_srwm(dev, ffs(enabled) - 1,
1463 2*sr_latency_ns,
1464 &valleyview_wm_info,
1465 &valleyview_cursor_wm_info,
1466 &ignore_plane_sr, &cursor_sr)) {
1467 cxsr_enabled = true;
1468 } else {
1469 cxsr_enabled = false;
1470 intel_set_memory_cxsr(dev_priv, false);
1471 plane_sr = cursor_sr = 0;
1472 }
1473
1474 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1475 "B: plane=%d, cursor=%d, C: plane=%d, cursor=%d, "
1476 "SR: plane=%d, cursor=%d\n",
1477 planea_wm, cursora_wm,
1478 planeb_wm, cursorb_wm,
1479 planec_wm, cursorc_wm,
1480 plane_sr, cursor_sr);
1481
1482 I915_WRITE(DSPFW1,
1483 (plane_sr << DSPFW_SR_SHIFT) |
1484 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1485 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1486 (planea_wm << DSPFW_PLANEA_SHIFT));
1487 I915_WRITE(DSPFW2,
1488 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1489 (cursora_wm << DSPFW_CURSORA_SHIFT));
1490 I915_WRITE(DSPFW3,
1491 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1492 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1493 I915_WRITE(DSPFW9_CHV,
1494 (I915_READ(DSPFW9_CHV) & ~(DSPFW_PLANEC_MASK |
1495 DSPFW_CURSORC_MASK)) |
1496 (planec_wm << DSPFW_PLANEC_SHIFT) |
1497 (cursorc_wm << DSPFW_CURSORC_SHIFT));
1498
1499 if (cxsr_enabled)
1500 intel_set_memory_cxsr(dev_priv, true);
1501 }
1502
1503 static void valleyview_update_sprite_wm(struct drm_plane *plane,
1504 struct drm_crtc *crtc,
1505 uint32_t sprite_width,
1506 uint32_t sprite_height,
1507 int pixel_size,
1508 bool enabled, bool scaled)
1509 {
1510 struct drm_device *dev = crtc->dev;
1511 struct drm_i915_private *dev_priv = dev->dev_private;
1512 int pipe = to_intel_plane(plane)->pipe;
1513 int sprite = to_intel_plane(plane)->plane;
1514 int drain_latency;
1515 int plane_prec;
1516 int sprite_dl;
1517 int prec_mult;
1518
1519 sprite_dl = I915_READ(VLV_DDL(pipe)) & ~(DDL_SPRITE_PRECISION_64(sprite) |
1520 (DRAIN_LATENCY_MASK << DDL_SPRITE_SHIFT(sprite)));
1521
1522 if (enabled && vlv_compute_drain_latency(crtc, pixel_size, &prec_mult,
1523 &drain_latency)) {
1524 plane_prec = (prec_mult == DRAIN_LATENCY_PRECISION_64) ?
1525 DDL_SPRITE_PRECISION_64(sprite) :
1526 DDL_SPRITE_PRECISION_32(sprite);
1527 sprite_dl |= plane_prec |
1528 (drain_latency << DDL_SPRITE_SHIFT(sprite));
1529 }
1530
1531 I915_WRITE(VLV_DDL(pipe), sprite_dl);
1532 }
1533
1534 static void g4x_update_wm(struct drm_crtc *crtc)
1535 {
1536 struct drm_device *dev = crtc->dev;
1537 static const int sr_latency_ns = 12000;
1538 struct drm_i915_private *dev_priv = dev->dev_private;
1539 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1540 int plane_sr, cursor_sr;
1541 unsigned int enabled = 0;
1542 bool cxsr_enabled;
1543
1544 if (g4x_compute_wm0(dev, PIPE_A,
1545 &g4x_wm_info, latency_ns,
1546 &g4x_cursor_wm_info, latency_ns,
1547 &planea_wm, &cursora_wm))
1548 enabled |= 1 << PIPE_A;
1549
1550 if (g4x_compute_wm0(dev, PIPE_B,
1551 &g4x_wm_info, latency_ns,
1552 &g4x_cursor_wm_info, latency_ns,
1553 &planeb_wm, &cursorb_wm))
1554 enabled |= 1 << PIPE_B;
1555
1556 if (single_plane_enabled(enabled) &&
1557 g4x_compute_srwm(dev, ffs(enabled) - 1,
1558 sr_latency_ns,
1559 &g4x_wm_info,
1560 &g4x_cursor_wm_info,
1561 &plane_sr, &cursor_sr)) {
1562 cxsr_enabled = true;
1563 } else {
1564 cxsr_enabled = false;
1565 intel_set_memory_cxsr(dev_priv, false);
1566 plane_sr = cursor_sr = 0;
1567 }
1568
1569 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1570 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1571 planea_wm, cursora_wm,
1572 planeb_wm, cursorb_wm,
1573 plane_sr, cursor_sr);
1574
1575 I915_WRITE(DSPFW1,
1576 (plane_sr << DSPFW_SR_SHIFT) |
1577 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1578 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1579 (planea_wm << DSPFW_PLANEA_SHIFT));
1580 I915_WRITE(DSPFW2,
1581 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1582 (cursora_wm << DSPFW_CURSORA_SHIFT));
1583 /* HPLL off in SR has some issues on G4x... disable it */
1584 I915_WRITE(DSPFW3,
1585 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1586 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1587
1588 if (cxsr_enabled)
1589 intel_set_memory_cxsr(dev_priv, true);
1590 }
1591
1592 static void i965_update_wm(struct drm_crtc *unused_crtc)
1593 {
1594 struct drm_device *dev = unused_crtc->dev;
1595 struct drm_i915_private *dev_priv = dev->dev_private;
1596 struct drm_crtc *crtc;
1597 int srwm = 1;
1598 int cursor_sr = 16;
1599 bool cxsr_enabled;
1600
1601 /* Calc sr entries for one plane configs */
1602 crtc = single_enabled_crtc(dev);
1603 if (crtc) {
1604 /* self-refresh has much higher latency */
1605 static const int sr_latency_ns = 12000;
1606 const struct drm_display_mode *adjusted_mode =
1607 &to_intel_crtc(crtc)->config.adjusted_mode;
1608 int clock = adjusted_mode->crtc_clock;
1609 int htotal = adjusted_mode->crtc_htotal;
1610 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1611 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1612 unsigned long line_time_us;
1613 int entries;
1614
1615 line_time_us = max(htotal * 1000 / clock, 1);
1616
1617 /* Use ns/us then divide to preserve precision */
1618 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1619 pixel_size * hdisplay;
1620 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1621 srwm = I965_FIFO_SIZE - entries;
1622 if (srwm < 0)
1623 srwm = 1;
1624 srwm &= 0x1ff;
1625 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1626 entries, srwm);
1627
1628 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1629 pixel_size * to_intel_crtc(crtc)->cursor_width;
1630 entries = DIV_ROUND_UP(entries,
1631 i965_cursor_wm_info.cacheline_size);
1632 cursor_sr = i965_cursor_wm_info.fifo_size -
1633 (entries + i965_cursor_wm_info.guard_size);
1634
1635 if (cursor_sr > i965_cursor_wm_info.max_wm)
1636 cursor_sr = i965_cursor_wm_info.max_wm;
1637
1638 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1639 "cursor %d\n", srwm, cursor_sr);
1640
1641 cxsr_enabled = true;
1642 } else {
1643 cxsr_enabled = false;
1644 /* Turn off self refresh if both pipes are enabled */
1645 intel_set_memory_cxsr(dev_priv, false);
1646 }
1647
1648 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1649 srwm);
1650
1651 /* 965 has limitations... */
1652 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1653 (8 << DSPFW_CURSORB_SHIFT) |
1654 (8 << DSPFW_PLANEB_SHIFT) |
1655 (8 << DSPFW_PLANEA_SHIFT));
1656 I915_WRITE(DSPFW2, (8 << DSPFW_CURSORA_SHIFT) |
1657 (8 << DSPFW_PLANEC_SHIFT_OLD));
1658 /* update cursor SR watermark */
1659 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1660
1661 if (cxsr_enabled)
1662 intel_set_memory_cxsr(dev_priv, true);
1663 }
1664
1665 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1666 {
1667 struct drm_device *dev = unused_crtc->dev;
1668 struct drm_i915_private *dev_priv = dev->dev_private;
1669 const struct intel_watermark_params *wm_info;
1670 uint32_t fwater_lo;
1671 uint32_t fwater_hi;
1672 int cwm, srwm = 1;
1673 int fifo_size;
1674 int planea_wm, planeb_wm;
1675 struct drm_crtc *crtc, *enabled = NULL;
1676
1677 if (IS_I945GM(dev))
1678 wm_info = &i945_wm_info;
1679 else if (!IS_GEN2(dev))
1680 wm_info = &i915_wm_info;
1681 else
1682 wm_info = &i830_wm_info;
1683
1684 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1685 crtc = intel_get_crtc_for_plane(dev, 0);
1686 if (intel_crtc_active(crtc)) {
1687 const struct drm_display_mode *adjusted_mode;
1688 int cpp = crtc->primary->fb->bits_per_pixel / 8;
1689 if (IS_GEN2(dev))
1690 cpp = 4;
1691
1692 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1693 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1694 wm_info, fifo_size, cpp,
1695 latency_ns);
1696 enabled = crtc;
1697 } else
1698 planea_wm = fifo_size - wm_info->guard_size;
1699
1700 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1701 crtc = intel_get_crtc_for_plane(dev, 1);
1702 if (intel_crtc_active(crtc)) {
1703 const struct drm_display_mode *adjusted_mode;
1704 int cpp = crtc->primary->fb->bits_per_pixel / 8;
1705 if (IS_GEN2(dev))
1706 cpp = 4;
1707
1708 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1709 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1710 wm_info, fifo_size, cpp,
1711 latency_ns);
1712 if (enabled == NULL)
1713 enabled = crtc;
1714 else
1715 enabled = NULL;
1716 } else
1717 planeb_wm = fifo_size - wm_info->guard_size;
1718
1719 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1720
1721 if (IS_I915GM(dev) && enabled) {
1722 struct drm_i915_gem_object *obj;
1723
1724 obj = intel_fb_obj(enabled->primary->fb);
1725
1726 /* self-refresh seems busted with untiled */
1727 if (obj->tiling_mode == I915_TILING_NONE)
1728 enabled = NULL;
1729 }
1730
1731 /*
1732 * Overlay gets an aggressive default since video jitter is bad.
1733 */
1734 cwm = 2;
1735
1736 /* Play safe and disable self-refresh before adjusting watermarks. */
1737 intel_set_memory_cxsr(dev_priv, false);
1738
1739 /* Calc sr entries for one plane configs */
1740 if (HAS_FW_BLC(dev) && enabled) {
1741 /* self-refresh has much higher latency */
1742 static const int sr_latency_ns = 6000;
1743 const struct drm_display_mode *adjusted_mode =
1744 &to_intel_crtc(enabled)->config.adjusted_mode;
1745 int clock = adjusted_mode->crtc_clock;
1746 int htotal = adjusted_mode->crtc_htotal;
1747 int hdisplay = to_intel_crtc(enabled)->config.pipe_src_w;
1748 int pixel_size = enabled->primary->fb->bits_per_pixel / 8;
1749 unsigned long line_time_us;
1750 int entries;
1751
1752 line_time_us = max(htotal * 1000 / clock, 1);
1753
1754 /* Use ns/us then divide to preserve precision */
1755 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1756 pixel_size * hdisplay;
1757 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1758 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1759 srwm = wm_info->fifo_size - entries;
1760 if (srwm < 0)
1761 srwm = 1;
1762
1763 if (IS_I945G(dev) || IS_I945GM(dev))
1764 I915_WRITE(FW_BLC_SELF,
1765 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1766 else if (IS_I915GM(dev))
1767 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1768 }
1769
1770 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1771 planea_wm, planeb_wm, cwm, srwm);
1772
1773 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1774 fwater_hi = (cwm & 0x1f);
1775
1776 /* Set request length to 8 cachelines per fetch */
1777 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1778 fwater_hi = fwater_hi | (1 << 8);
1779
1780 I915_WRITE(FW_BLC, fwater_lo);
1781 I915_WRITE(FW_BLC2, fwater_hi);
1782
1783 if (enabled)
1784 intel_set_memory_cxsr(dev_priv, true);
1785 }
1786
1787 static void i845_update_wm(struct drm_crtc *unused_crtc)
1788 {
1789 struct drm_device *dev = unused_crtc->dev;
1790 struct drm_i915_private *dev_priv = dev->dev_private;
1791 struct drm_crtc *crtc;
1792 const struct drm_display_mode *adjusted_mode;
1793 uint32_t fwater_lo;
1794 int planea_wm;
1795
1796 crtc = single_enabled_crtc(dev);
1797 if (crtc == NULL)
1798 return;
1799
1800 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1801 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1802 &i845_wm_info,
1803 dev_priv->display.get_fifo_size(dev, 0),
1804 4, latency_ns);
1805 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1806 fwater_lo |= (3<<8) | planea_wm;
1807
1808 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1809
1810 I915_WRITE(FW_BLC, fwater_lo);
1811 }
1812
1813 static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
1814 struct drm_crtc *crtc)
1815 {
1816 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1817 uint32_t pixel_rate;
1818
1819 pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock;
1820
1821 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1822 * adjust the pixel_rate here. */
1823
1824 if (intel_crtc->config.pch_pfit.enabled) {
1825 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1826 uint32_t pfit_size = intel_crtc->config.pch_pfit.size;
1827
1828 pipe_w = intel_crtc->config.pipe_src_w;
1829 pipe_h = intel_crtc->config.pipe_src_h;
1830 pfit_w = (pfit_size >> 16) & 0xFFFF;
1831 pfit_h = pfit_size & 0xFFFF;
1832 if (pipe_w < pfit_w)
1833 pipe_w = pfit_w;
1834 if (pipe_h < pfit_h)
1835 pipe_h = pfit_h;
1836
1837 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1838 pfit_w * pfit_h);
1839 }
1840
1841 return pixel_rate;
1842 }
1843
1844 /* latency must be in 0.1us units. */
1845 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
1846 uint32_t latency)
1847 {
1848 uint64_t ret;
1849
1850 if (WARN(latency == 0, "Latency value missing\n"))
1851 return UINT_MAX;
1852
1853 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1854 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1855
1856 return ret;
1857 }
1858
1859 /* latency must be in 0.1us units. */
1860 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1861 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1862 uint32_t latency)
1863 {
1864 uint32_t ret;
1865
1866 if (WARN(latency == 0, "Latency value missing\n"))
1867 return UINT_MAX;
1868
1869 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1870 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1871 ret = DIV_ROUND_UP(ret, 64) + 2;
1872 return ret;
1873 }
1874
1875 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1876 uint8_t bytes_per_pixel)
1877 {
1878 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1879 }
1880
1881 struct ilk_pipe_wm_parameters {
1882 bool active;
1883 uint32_t pipe_htotal;
1884 uint32_t pixel_rate;
1885 struct intel_plane_wm_parameters pri;
1886 struct intel_plane_wm_parameters spr;
1887 struct intel_plane_wm_parameters cur;
1888 };
1889
1890 struct ilk_wm_maximums {
1891 uint16_t pri;
1892 uint16_t spr;
1893 uint16_t cur;
1894 uint16_t fbc;
1895 };
1896
1897 /* used in computing the new watermarks state */
1898 struct intel_wm_config {
1899 unsigned int num_pipes_active;
1900 bool sprites_enabled;
1901 bool sprites_scaled;
1902 };
1903
1904 /*
1905 * For both WM_PIPE and WM_LP.
1906 * mem_value must be in 0.1us units.
1907 */
1908 static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params,
1909 uint32_t mem_value,
1910 bool is_lp)
1911 {
1912 uint32_t method1, method2;
1913
1914 if (!params->active || !params->pri.enabled)
1915 return 0;
1916
1917 method1 = ilk_wm_method1(params->pixel_rate,
1918 params->pri.bytes_per_pixel,
1919 mem_value);
1920
1921 if (!is_lp)
1922 return method1;
1923
1924 method2 = ilk_wm_method2(params->pixel_rate,
1925 params->pipe_htotal,
1926 params->pri.horiz_pixels,
1927 params->pri.bytes_per_pixel,
1928 mem_value);
1929
1930 return min(method1, method2);
1931 }
1932
1933 /*
1934 * For both WM_PIPE and WM_LP.
1935 * mem_value must be in 0.1us units.
1936 */
1937 static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params,
1938 uint32_t mem_value)
1939 {
1940 uint32_t method1, method2;
1941
1942 if (!params->active || !params->spr.enabled)
1943 return 0;
1944
1945 method1 = ilk_wm_method1(params->pixel_rate,
1946 params->spr.bytes_per_pixel,
1947 mem_value);
1948 method2 = ilk_wm_method2(params->pixel_rate,
1949 params->pipe_htotal,
1950 params->spr.horiz_pixels,
1951 params->spr.bytes_per_pixel,
1952 mem_value);
1953 return min(method1, method2);
1954 }
1955
1956 /*
1957 * For both WM_PIPE and WM_LP.
1958 * mem_value must be in 0.1us units.
1959 */
1960 static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params,
1961 uint32_t mem_value)
1962 {
1963 if (!params->active || !params->cur.enabled)
1964 return 0;
1965
1966 return ilk_wm_method2(params->pixel_rate,
1967 params->pipe_htotal,
1968 params->cur.horiz_pixels,
1969 params->cur.bytes_per_pixel,
1970 mem_value);
1971 }
1972
1973 /* Only for WM_LP. */
1974 static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params,
1975 uint32_t pri_val)
1976 {
1977 if (!params->active || !params->pri.enabled)
1978 return 0;
1979
1980 return ilk_wm_fbc(pri_val,
1981 params->pri.horiz_pixels,
1982 params->pri.bytes_per_pixel);
1983 }
1984
1985 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1986 {
1987 if (INTEL_INFO(dev)->gen >= 8)
1988 return 3072;
1989 else if (INTEL_INFO(dev)->gen >= 7)
1990 return 768;
1991 else
1992 return 512;
1993 }
1994
1995 static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1996 int level, bool is_sprite)
1997 {
1998 if (INTEL_INFO(dev)->gen >= 8)
1999 /* BDW primary/sprite plane watermarks */
2000 return level == 0 ? 255 : 2047;
2001 else if (INTEL_INFO(dev)->gen >= 7)
2002 /* IVB/HSW primary/sprite plane watermarks */
2003 return level == 0 ? 127 : 1023;
2004 else if (!is_sprite)
2005 /* ILK/SNB primary plane watermarks */
2006 return level == 0 ? 127 : 511;
2007 else
2008 /* ILK/SNB sprite plane watermarks */
2009 return level == 0 ? 63 : 255;
2010 }
2011
2012 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
2013 int level)
2014 {
2015 if (INTEL_INFO(dev)->gen >= 7)
2016 return level == 0 ? 63 : 255;
2017 else
2018 return level == 0 ? 31 : 63;
2019 }
2020
2021 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
2022 {
2023 if (INTEL_INFO(dev)->gen >= 8)
2024 return 31;
2025 else
2026 return 15;
2027 }
2028
2029 /* Calculate the maximum primary/sprite plane watermark */
2030 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
2031 int level,
2032 const struct intel_wm_config *config,
2033 enum intel_ddb_partitioning ddb_partitioning,
2034 bool is_sprite)
2035 {
2036 unsigned int fifo_size = ilk_display_fifo_size(dev);
2037
2038 /* if sprites aren't enabled, sprites get nothing */
2039 if (is_sprite && !config->sprites_enabled)
2040 return 0;
2041
2042 /* HSW allows LP1+ watermarks even with multiple pipes */
2043 if (level == 0 || config->num_pipes_active > 1) {
2044 fifo_size /= INTEL_INFO(dev)->num_pipes;
2045
2046 /*
2047 * For some reason the non self refresh
2048 * FIFO size is only half of the self
2049 * refresh FIFO size on ILK/SNB.
2050 */
2051 if (INTEL_INFO(dev)->gen <= 6)
2052 fifo_size /= 2;
2053 }
2054
2055 if (config->sprites_enabled) {
2056 /* level 0 is always calculated with 1:1 split */
2057 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
2058 if (is_sprite)
2059 fifo_size *= 5;
2060 fifo_size /= 6;
2061 } else {
2062 fifo_size /= 2;
2063 }
2064 }
2065
2066 /* clamp to max that the registers can hold */
2067 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
2068 }
2069
2070 /* Calculate the maximum cursor plane watermark */
2071 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
2072 int level,
2073 const struct intel_wm_config *config)
2074 {
2075 /* HSW LP1+ watermarks w/ multiple pipes */
2076 if (level > 0 && config->num_pipes_active > 1)
2077 return 64;
2078
2079 /* otherwise just report max that registers can hold */
2080 return ilk_cursor_wm_reg_max(dev, level);
2081 }
2082
2083 static void ilk_compute_wm_maximums(const struct drm_device *dev,
2084 int level,
2085 const struct intel_wm_config *config,
2086 enum intel_ddb_partitioning ddb_partitioning,
2087 struct ilk_wm_maximums *max)
2088 {
2089 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
2090 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
2091 max->cur = ilk_cursor_wm_max(dev, level, config);
2092 max->fbc = ilk_fbc_wm_reg_max(dev);
2093 }
2094
2095 static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
2096 int level,
2097 struct ilk_wm_maximums *max)
2098 {
2099 max->pri = ilk_plane_wm_reg_max(dev, level, false);
2100 max->spr = ilk_plane_wm_reg_max(dev, level, true);
2101 max->cur = ilk_cursor_wm_reg_max(dev, level);
2102 max->fbc = ilk_fbc_wm_reg_max(dev);
2103 }
2104
2105 static bool ilk_validate_wm_level(int level,
2106 const struct ilk_wm_maximums *max,
2107 struct intel_wm_level *result)
2108 {
2109 bool ret;
2110
2111 /* already determined to be invalid? */
2112 if (!result->enable)
2113 return false;
2114
2115 result->enable = result->pri_val <= max->pri &&
2116 result->spr_val <= max->spr &&
2117 result->cur_val <= max->cur;
2118
2119 ret = result->enable;
2120
2121 /*
2122 * HACK until we can pre-compute everything,
2123 * and thus fail gracefully if LP0 watermarks
2124 * are exceeded...
2125 */
2126 if (level == 0 && !result->enable) {
2127 if (result->pri_val > max->pri)
2128 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2129 level, result->pri_val, max->pri);
2130 if (result->spr_val > max->spr)
2131 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2132 level, result->spr_val, max->spr);
2133 if (result->cur_val > max->cur)
2134 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2135 level, result->cur_val, max->cur);
2136
2137 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2138 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2139 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2140 result->enable = true;
2141 }
2142
2143 return ret;
2144 }
2145
2146 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
2147 int level,
2148 const struct ilk_pipe_wm_parameters *p,
2149 struct intel_wm_level *result)
2150 {
2151 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2152 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2153 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2154
2155 /* WM1+ latency values stored in 0.5us units */
2156 if (level > 0) {
2157 pri_latency *= 5;
2158 spr_latency *= 5;
2159 cur_latency *= 5;
2160 }
2161
2162 result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
2163 result->spr_val = ilk_compute_spr_wm(p, spr_latency);
2164 result->cur_val = ilk_compute_cur_wm(p, cur_latency);
2165 result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
2166 result->enable = true;
2167 }
2168
2169 static uint32_t
2170 hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
2171 {
2172 struct drm_i915_private *dev_priv = dev->dev_private;
2173 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2174 struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
2175 u32 linetime, ips_linetime;
2176
2177 if (!intel_crtc_active(crtc))
2178 return 0;
2179
2180 /* The WM are computed with base on how long it takes to fill a single
2181 * row at the given clock rate, multiplied by 8.
2182 * */
2183 linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
2184 mode->crtc_clock);
2185 ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
2186 intel_ddi_get_cdclk_freq(dev_priv));
2187
2188 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2189 PIPE_WM_LINETIME_TIME(linetime);
2190 }
2191
2192 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5])
2193 {
2194 struct drm_i915_private *dev_priv = dev->dev_private;
2195
2196 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2197 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2198
2199 wm[0] = (sskpd >> 56) & 0xFF;
2200 if (wm[0] == 0)
2201 wm[0] = sskpd & 0xF;
2202 wm[1] = (sskpd >> 4) & 0xFF;
2203 wm[2] = (sskpd >> 12) & 0xFF;
2204 wm[3] = (sskpd >> 20) & 0x1FF;
2205 wm[4] = (sskpd >> 32) & 0x1FF;
2206 } else if (INTEL_INFO(dev)->gen >= 6) {
2207 uint32_t sskpd = I915_READ(MCH_SSKPD);
2208
2209 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2210 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2211 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2212 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2213 } else if (INTEL_INFO(dev)->gen >= 5) {
2214 uint32_t mltr = I915_READ(MLTR_ILK);
2215
2216 /* ILK primary LP0 latency is 700 ns */
2217 wm[0] = 7;
2218 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2219 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2220 }
2221 }
2222
2223 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2224 {
2225 /* ILK sprite LP0 latency is 1300 ns */
2226 if (INTEL_INFO(dev)->gen == 5)
2227 wm[0] = 13;
2228 }
2229
2230 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2231 {
2232 /* ILK cursor LP0 latency is 1300 ns */
2233 if (INTEL_INFO(dev)->gen == 5)
2234 wm[0] = 13;
2235
2236 /* WaDoubleCursorLP3Latency:ivb */
2237 if (IS_IVYBRIDGE(dev))
2238 wm[3] *= 2;
2239 }
2240
2241 int ilk_wm_max_level(const struct drm_device *dev)
2242 {
2243 /* how many WM levels are we expecting */
2244 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2245 return 4;
2246 else if (INTEL_INFO(dev)->gen >= 6)
2247 return 3;
2248 else
2249 return 2;
2250 }
2251
2252 static void intel_print_wm_latency(struct drm_device *dev,
2253 const char *name,
2254 const uint16_t wm[5])
2255 {
2256 int level, max_level = ilk_wm_max_level(dev);
2257
2258 for (level = 0; level <= max_level; level++) {
2259 unsigned int latency = wm[level];
2260
2261 if (latency == 0) {
2262 DRM_ERROR("%s WM%d latency not provided\n",
2263 name, level);
2264 continue;
2265 }
2266
2267 /* WM1+ latency values in 0.5us units */
2268 if (level > 0)
2269 latency *= 5;
2270
2271 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2272 name, level, wm[level],
2273 latency / 10, latency % 10);
2274 }
2275 }
2276
2277 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2278 uint16_t wm[5], uint16_t min)
2279 {
2280 int level, max_level = ilk_wm_max_level(dev_priv->dev);
2281
2282 if (wm[0] >= min)
2283 return false;
2284
2285 wm[0] = max(wm[0], min);
2286 for (level = 1; level <= max_level; level++)
2287 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2288
2289 return true;
2290 }
2291
2292 static void snb_wm_latency_quirk(struct drm_device *dev)
2293 {
2294 struct drm_i915_private *dev_priv = dev->dev_private;
2295 bool changed;
2296
2297 /*
2298 * The BIOS provided WM memory latency values are often
2299 * inadequate for high resolution displays. Adjust them.
2300 */
2301 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2302 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2303 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2304
2305 if (!changed)
2306 return;
2307
2308 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2309 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2310 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2311 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2312 }
2313
2314 static void ilk_setup_wm_latency(struct drm_device *dev)
2315 {
2316 struct drm_i915_private *dev_priv = dev->dev_private;
2317
2318 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2319
2320 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2321 sizeof(dev_priv->wm.pri_latency));
2322 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2323 sizeof(dev_priv->wm.pri_latency));
2324
2325 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2326 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2327
2328 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2329 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2330 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2331
2332 if (IS_GEN6(dev))
2333 snb_wm_latency_quirk(dev);
2334 }
2335
2336 static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
2337 struct ilk_pipe_wm_parameters *p)
2338 {
2339 struct drm_device *dev = crtc->dev;
2340 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2341 enum pipe pipe = intel_crtc->pipe;
2342 struct drm_plane *plane;
2343
2344 if (!intel_crtc_active(crtc))
2345 return;
2346
2347 p->active = true;
2348 p->pipe_htotal = intel_crtc->config.adjusted_mode.crtc_htotal;
2349 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
2350 p->pri.bytes_per_pixel = crtc->primary->fb->bits_per_pixel / 8;
2351 p->cur.bytes_per_pixel = 4;
2352 p->pri.horiz_pixels = intel_crtc->config.pipe_src_w;
2353 p->cur.horiz_pixels = intel_crtc->cursor_width;
2354 /* TODO: for now, assume primary and cursor planes are always enabled. */
2355 p->pri.enabled = true;
2356 p->cur.enabled = true;
2357
2358 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
2359 struct intel_plane *intel_plane = to_intel_plane(plane);
2360
2361 if (intel_plane->pipe == pipe) {
2362 p->spr = intel_plane->wm;
2363 break;
2364 }
2365 }
2366 }
2367
2368 static void ilk_compute_wm_config(struct drm_device *dev,
2369 struct intel_wm_config *config)
2370 {
2371 struct intel_crtc *intel_crtc;
2372
2373 /* Compute the currently _active_ config */
2374 for_each_intel_crtc(dev, intel_crtc) {
2375 const struct intel_pipe_wm *wm = &intel_crtc->wm.active;
2376
2377 if (!wm->pipe_enabled)
2378 continue;
2379
2380 config->sprites_enabled |= wm->sprites_enabled;
2381 config->sprites_scaled |= wm->sprites_scaled;
2382 config->num_pipes_active++;
2383 }
2384 }
2385
2386 /* Compute new watermarks for the pipe */
2387 static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
2388 const struct ilk_pipe_wm_parameters *params,
2389 struct intel_pipe_wm *pipe_wm)
2390 {
2391 struct drm_device *dev = crtc->dev;
2392 const struct drm_i915_private *dev_priv = dev->dev_private;
2393 int level, max_level = ilk_wm_max_level(dev);
2394 /* LP0 watermark maximums depend on this pipe alone */
2395 struct intel_wm_config config = {
2396 .num_pipes_active = 1,
2397 .sprites_enabled = params->spr.enabled,
2398 .sprites_scaled = params->spr.scaled,
2399 };
2400 struct ilk_wm_maximums max;
2401
2402 pipe_wm->pipe_enabled = params->active;
2403 pipe_wm->sprites_enabled = params->spr.enabled;
2404 pipe_wm->sprites_scaled = params->spr.scaled;
2405
2406 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2407 if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled)
2408 max_level = 1;
2409
2410 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2411 if (params->spr.scaled)
2412 max_level = 0;
2413
2414 ilk_compute_wm_level(dev_priv, 0, params, &pipe_wm->wm[0]);
2415
2416 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2417 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
2418
2419 /* LP0 watermarks always use 1/2 DDB partitioning */
2420 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2421
2422 /* At least LP0 must be valid */
2423 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
2424 return false;
2425
2426 ilk_compute_wm_reg_maximums(dev, 1, &max);
2427
2428 for (level = 1; level <= max_level; level++) {
2429 struct intel_wm_level wm = {};
2430
2431 ilk_compute_wm_level(dev_priv, level, params, &wm);
2432
2433 /*
2434 * Disable any watermark level that exceeds the
2435 * register maximums since such watermarks are
2436 * always invalid.
2437 */
2438 if (!ilk_validate_wm_level(level, &max, &wm))
2439 break;
2440
2441 pipe_wm->wm[level] = wm;
2442 }
2443
2444 return true;
2445 }
2446
2447 /*
2448 * Merge the watermarks from all active pipes for a specific level.
2449 */
2450 static void ilk_merge_wm_level(struct drm_device *dev,
2451 int level,
2452 struct intel_wm_level *ret_wm)
2453 {
2454 const struct intel_crtc *intel_crtc;
2455
2456 ret_wm->enable = true;
2457
2458 for_each_intel_crtc(dev, intel_crtc) {
2459 const struct intel_pipe_wm *active = &intel_crtc->wm.active;
2460 const struct intel_wm_level *wm = &active->wm[level];
2461
2462 if (!active->pipe_enabled)
2463 continue;
2464
2465 /*
2466 * The watermark values may have been used in the past,
2467 * so we must maintain them in the registers for some
2468 * time even if the level is now disabled.
2469 */
2470 if (!wm->enable)
2471 ret_wm->enable = false;
2472
2473 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2474 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2475 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2476 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2477 }
2478 }
2479
2480 /*
2481 * Merge all low power watermarks for all active pipes.
2482 */
2483 static void ilk_wm_merge(struct drm_device *dev,
2484 const struct intel_wm_config *config,
2485 const struct ilk_wm_maximums *max,
2486 struct intel_pipe_wm *merged)
2487 {
2488 int level, max_level = ilk_wm_max_level(dev);
2489 int last_enabled_level = max_level;
2490
2491 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2492 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2493 config->num_pipes_active > 1)
2494 return;
2495
2496 /* ILK: FBC WM must be disabled always */
2497 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
2498
2499 /* merge each WM1+ level */
2500 for (level = 1; level <= max_level; level++) {
2501 struct intel_wm_level *wm = &merged->wm[level];
2502
2503 ilk_merge_wm_level(dev, level, wm);
2504
2505 if (level > last_enabled_level)
2506 wm->enable = false;
2507 else if (!ilk_validate_wm_level(level, max, wm))
2508 /* make sure all following levels get disabled */
2509 last_enabled_level = level - 1;
2510
2511 /*
2512 * The spec says it is preferred to disable
2513 * FBC WMs instead of disabling a WM level.
2514 */
2515 if (wm->fbc_val > max->fbc) {
2516 if (wm->enable)
2517 merged->fbc_wm_enabled = false;
2518 wm->fbc_val = 0;
2519 }
2520 }
2521
2522 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2523 /*
2524 * FIXME this is racy. FBC might get enabled later.
2525 * What we should check here is whether FBC can be
2526 * enabled sometime later.
2527 */
2528 if (IS_GEN5(dev) && !merged->fbc_wm_enabled && intel_fbc_enabled(dev)) {
2529 for (level = 2; level <= max_level; level++) {
2530 struct intel_wm_level *wm = &merged->wm[level];
2531
2532 wm->enable = false;
2533 }
2534 }
2535 }
2536
2537 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2538 {
2539 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2540 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2541 }
2542
2543 /* The value we need to program into the WM_LPx latency field */
2544 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2545 {
2546 struct drm_i915_private *dev_priv = dev->dev_private;
2547
2548 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2549 return 2 * level;
2550 else
2551 return dev_priv->wm.pri_latency[level];
2552 }
2553
2554 static void ilk_compute_wm_results(struct drm_device *dev,
2555 const struct intel_pipe_wm *merged,
2556 enum intel_ddb_partitioning partitioning,
2557 struct ilk_wm_values *results)
2558 {
2559 struct intel_crtc *intel_crtc;
2560 int level, wm_lp;
2561
2562 results->enable_fbc_wm = merged->fbc_wm_enabled;
2563 results->partitioning = partitioning;
2564
2565 /* LP1+ register values */
2566 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2567 const struct intel_wm_level *r;
2568
2569 level = ilk_wm_lp_to_level(wm_lp, merged);
2570
2571 r = &merged->wm[level];
2572
2573 /*
2574 * Maintain the watermark values even if the level is
2575 * disabled. Doing otherwise could cause underruns.
2576 */
2577 results->wm_lp[wm_lp - 1] =
2578 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2579 (r->pri_val << WM1_LP_SR_SHIFT) |
2580 r->cur_val;
2581
2582 if (r->enable)
2583 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2584
2585 if (INTEL_INFO(dev)->gen >= 8)
2586 results->wm_lp[wm_lp - 1] |=
2587 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2588 else
2589 results->wm_lp[wm_lp - 1] |=
2590 r->fbc_val << WM1_LP_FBC_SHIFT;
2591
2592 /*
2593 * Always set WM1S_LP_EN when spr_val != 0, even if the
2594 * level is disabled. Doing otherwise could cause underruns.
2595 */
2596 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2597 WARN_ON(wm_lp != 1);
2598 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2599 } else
2600 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2601 }
2602
2603 /* LP0 register values */
2604 for_each_intel_crtc(dev, intel_crtc) {
2605 enum pipe pipe = intel_crtc->pipe;
2606 const struct intel_wm_level *r =
2607 &intel_crtc->wm.active.wm[0];
2608
2609 if (WARN_ON(!r->enable))
2610 continue;
2611
2612 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
2613
2614 results->wm_pipe[pipe] =
2615 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2616 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2617 r->cur_val;
2618 }
2619 }
2620
2621 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2622 * case both are at the same level. Prefer r1 in case they're the same. */
2623 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2624 struct intel_pipe_wm *r1,
2625 struct intel_pipe_wm *r2)
2626 {
2627 int level, max_level = ilk_wm_max_level(dev);
2628 int level1 = 0, level2 = 0;
2629
2630 for (level = 1; level <= max_level; level++) {
2631 if (r1->wm[level].enable)
2632 level1 = level;
2633 if (r2->wm[level].enable)
2634 level2 = level;
2635 }
2636
2637 if (level1 == level2) {
2638 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2639 return r2;
2640 else
2641 return r1;
2642 } else if (level1 > level2) {
2643 return r1;
2644 } else {
2645 return r2;
2646 }
2647 }
2648
2649 /* dirty bits used to track which watermarks need changes */
2650 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2651 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2652 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2653 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2654 #define WM_DIRTY_FBC (1 << 24)
2655 #define WM_DIRTY_DDB (1 << 25)
2656
2657 static unsigned int ilk_compute_wm_dirty(struct drm_device *dev,
2658 const struct ilk_wm_values *old,
2659 const struct ilk_wm_values *new)
2660 {
2661 unsigned int dirty = 0;
2662 enum pipe pipe;
2663 int wm_lp;
2664
2665 for_each_pipe(pipe) {
2666 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2667 dirty |= WM_DIRTY_LINETIME(pipe);
2668 /* Must disable LP1+ watermarks too */
2669 dirty |= WM_DIRTY_LP_ALL;
2670 }
2671
2672 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2673 dirty |= WM_DIRTY_PIPE(pipe);
2674 /* Must disable LP1+ watermarks too */
2675 dirty |= WM_DIRTY_LP_ALL;
2676 }
2677 }
2678
2679 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2680 dirty |= WM_DIRTY_FBC;
2681 /* Must disable LP1+ watermarks too */
2682 dirty |= WM_DIRTY_LP_ALL;
2683 }
2684
2685 if (old->partitioning != new->partitioning) {
2686 dirty |= WM_DIRTY_DDB;
2687 /* Must disable LP1+ watermarks too */
2688 dirty |= WM_DIRTY_LP_ALL;
2689 }
2690
2691 /* LP1+ watermarks already deemed dirty, no need to continue */
2692 if (dirty & WM_DIRTY_LP_ALL)
2693 return dirty;
2694
2695 /* Find the lowest numbered LP1+ watermark in need of an update... */
2696 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2697 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2698 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2699 break;
2700 }
2701
2702 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2703 for (; wm_lp <= 3; wm_lp++)
2704 dirty |= WM_DIRTY_LP(wm_lp);
2705
2706 return dirty;
2707 }
2708
2709 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2710 unsigned int dirty)
2711 {
2712 struct ilk_wm_values *previous = &dev_priv->wm.hw;
2713 bool changed = false;
2714
2715 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2716 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2717 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2718 changed = true;
2719 }
2720 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2721 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2722 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2723 changed = true;
2724 }
2725 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2726 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2727 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2728 changed = true;
2729 }
2730
2731 /*
2732 * Don't touch WM1S_LP_EN here.
2733 * Doing so could cause underruns.
2734 */
2735
2736 return changed;
2737 }
2738
2739 /*
2740 * The spec says we shouldn't write when we don't need, because every write
2741 * causes WMs to be re-evaluated, expending some power.
2742 */
2743 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2744 struct ilk_wm_values *results)
2745 {
2746 struct drm_device *dev = dev_priv->dev;
2747 struct ilk_wm_values *previous = &dev_priv->wm.hw;
2748 unsigned int dirty;
2749 uint32_t val;
2750
2751 dirty = ilk_compute_wm_dirty(dev, previous, results);
2752 if (!dirty)
2753 return;
2754
2755 _ilk_disable_lp_wm(dev_priv, dirty);
2756
2757 if (dirty & WM_DIRTY_PIPE(PIPE_A))
2758 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2759 if (dirty & WM_DIRTY_PIPE(PIPE_B))
2760 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2761 if (dirty & WM_DIRTY_PIPE(PIPE_C))
2762 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2763
2764 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2765 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2766 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2767 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2768 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2769 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2770
2771 if (dirty & WM_DIRTY_DDB) {
2772 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2773 val = I915_READ(WM_MISC);
2774 if (results->partitioning == INTEL_DDB_PART_1_2)
2775 val &= ~WM_MISC_DATA_PARTITION_5_6;
2776 else
2777 val |= WM_MISC_DATA_PARTITION_5_6;
2778 I915_WRITE(WM_MISC, val);
2779 } else {
2780 val = I915_READ(DISP_ARB_CTL2);
2781 if (results->partitioning == INTEL_DDB_PART_1_2)
2782 val &= ~DISP_DATA_PARTITION_5_6;
2783 else
2784 val |= DISP_DATA_PARTITION_5_6;
2785 I915_WRITE(DISP_ARB_CTL2, val);
2786 }
2787 }
2788
2789 if (dirty & WM_DIRTY_FBC) {
2790 val = I915_READ(DISP_ARB_CTL);
2791 if (results->enable_fbc_wm)
2792 val &= ~DISP_FBC_WM_DIS;
2793 else
2794 val |= DISP_FBC_WM_DIS;
2795 I915_WRITE(DISP_ARB_CTL, val);
2796 }
2797
2798 if (dirty & WM_DIRTY_LP(1) &&
2799 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2800 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2801
2802 if (INTEL_INFO(dev)->gen >= 7) {
2803 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2804 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2805 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2806 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2807 }
2808
2809 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2810 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2811 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2812 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2813 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2814 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2815
2816 dev_priv->wm.hw = *results;
2817 }
2818
2819 static bool ilk_disable_lp_wm(struct drm_device *dev)
2820 {
2821 struct drm_i915_private *dev_priv = dev->dev_private;
2822
2823 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2824 }
2825
2826 static void ilk_update_wm(struct drm_crtc *crtc)
2827 {
2828 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2829 struct drm_device *dev = crtc->dev;
2830 struct drm_i915_private *dev_priv = dev->dev_private;
2831 struct ilk_wm_maximums max;
2832 struct ilk_pipe_wm_parameters params = {};
2833 struct ilk_wm_values results = {};
2834 enum intel_ddb_partitioning partitioning;
2835 struct intel_pipe_wm pipe_wm = {};
2836 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
2837 struct intel_wm_config config = {};
2838
2839 ilk_compute_wm_parameters(crtc, &params);
2840
2841 intel_compute_pipe_wm(crtc, &params, &pipe_wm);
2842
2843 if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
2844 return;
2845
2846 intel_crtc->wm.active = pipe_wm;
2847
2848 ilk_compute_wm_config(dev, &config);
2849
2850 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
2851 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
2852
2853 /* 5/6 split only in single pipe config on IVB+ */
2854 if (INTEL_INFO(dev)->gen >= 7 &&
2855 config.num_pipes_active == 1 && config.sprites_enabled) {
2856 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
2857 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
2858
2859 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
2860 } else {
2861 best_lp_wm = &lp_wm_1_2;
2862 }
2863
2864 partitioning = (best_lp_wm == &lp_wm_1_2) ?
2865 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
2866
2867 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
2868
2869 ilk_write_wm_values(dev_priv, &results);
2870 }
2871
2872 static void
2873 ilk_update_sprite_wm(struct drm_plane *plane,
2874 struct drm_crtc *crtc,
2875 uint32_t sprite_width, uint32_t sprite_height,
2876 int pixel_size, bool enabled, bool scaled)
2877 {
2878 struct drm_device *dev = plane->dev;
2879 struct intel_plane *intel_plane = to_intel_plane(plane);
2880
2881 intel_plane->wm.enabled = enabled;
2882 intel_plane->wm.scaled = scaled;
2883 intel_plane->wm.horiz_pixels = sprite_width;
2884 intel_plane->wm.vert_pixels = sprite_width;
2885 intel_plane->wm.bytes_per_pixel = pixel_size;
2886
2887 /*
2888 * IVB workaround: must disable low power watermarks for at least
2889 * one frame before enabling scaling. LP watermarks can be re-enabled
2890 * when scaling is disabled.
2891 *
2892 * WaCxSRDisabledForSpriteScaling:ivb
2893 */
2894 if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev))
2895 intel_wait_for_vblank(dev, intel_plane->pipe);
2896
2897 ilk_update_wm(crtc);
2898 }
2899
2900 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
2901 {
2902 struct drm_device *dev = crtc->dev;
2903 struct drm_i915_private *dev_priv = dev->dev_private;
2904 struct ilk_wm_values *hw = &dev_priv->wm.hw;
2905 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2906 struct intel_pipe_wm *active = &intel_crtc->wm.active;
2907 enum pipe pipe = intel_crtc->pipe;
2908 static const unsigned int wm0_pipe_reg[] = {
2909 [PIPE_A] = WM0_PIPEA_ILK,
2910 [PIPE_B] = WM0_PIPEB_ILK,
2911 [PIPE_C] = WM0_PIPEC_IVB,
2912 };
2913
2914 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
2915 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2916 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
2917
2918 active->pipe_enabled = intel_crtc_active(crtc);
2919
2920 if (active->pipe_enabled) {
2921 u32 tmp = hw->wm_pipe[pipe];
2922
2923 /*
2924 * For active pipes LP0 watermark is marked as
2925 * enabled, and LP1+ watermaks as disabled since
2926 * we can't really reverse compute them in case
2927 * multiple pipes are active.
2928 */
2929 active->wm[0].enable = true;
2930 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
2931 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
2932 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
2933 active->linetime = hw->wm_linetime[pipe];
2934 } else {
2935 int level, max_level = ilk_wm_max_level(dev);
2936
2937 /*
2938 * For inactive pipes, all watermark levels
2939 * should be marked as enabled but zeroed,
2940 * which is what we'd compute them to.
2941 */
2942 for (level = 0; level <= max_level; level++)
2943 active->wm[level].enable = true;
2944 }
2945 }
2946
2947 void ilk_wm_get_hw_state(struct drm_device *dev)
2948 {
2949 struct drm_i915_private *dev_priv = dev->dev_private;
2950 struct ilk_wm_values *hw = &dev_priv->wm.hw;
2951 struct drm_crtc *crtc;
2952
2953 for_each_crtc(dev, crtc)
2954 ilk_pipe_wm_get_hw_state(crtc);
2955
2956 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
2957 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
2958 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
2959
2960 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
2961 if (INTEL_INFO(dev)->gen >= 7) {
2962 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
2963 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
2964 }
2965
2966 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2967 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
2968 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
2969 else if (IS_IVYBRIDGE(dev))
2970 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
2971 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
2972
2973 hw->enable_fbc_wm =
2974 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
2975 }
2976
2977 /**
2978 * intel_update_watermarks - update FIFO watermark values based on current modes
2979 *
2980 * Calculate watermark values for the various WM regs based on current mode
2981 * and plane configuration.
2982 *
2983 * There are several cases to deal with here:
2984 * - normal (i.e. non-self-refresh)
2985 * - self-refresh (SR) mode
2986 * - lines are large relative to FIFO size (buffer can hold up to 2)
2987 * - lines are small relative to FIFO size (buffer can hold more than 2
2988 * lines), so need to account for TLB latency
2989 *
2990 * The normal calculation is:
2991 * watermark = dotclock * bytes per pixel * latency
2992 * where latency is platform & configuration dependent (we assume pessimal
2993 * values here).
2994 *
2995 * The SR calculation is:
2996 * watermark = (trunc(latency/line time)+1) * surface width *
2997 * bytes per pixel
2998 * where
2999 * line time = htotal / dotclock
3000 * surface width = hdisplay for normal plane and 64 for cursor
3001 * and latency is assumed to be high, as above.
3002 *
3003 * The final value programmed to the register should always be rounded up,
3004 * and include an extra 2 entries to account for clock crossings.
3005 *
3006 * We don't use the sprite, so we can ignore that. And on Crestline we have
3007 * to set the non-SR watermarks to 8.
3008 */
3009 void intel_update_watermarks(struct drm_crtc *crtc)
3010 {
3011 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
3012
3013 if (dev_priv->display.update_wm)
3014 dev_priv->display.update_wm(crtc);
3015 }
3016
3017 void intel_update_sprite_watermarks(struct drm_plane *plane,
3018 struct drm_crtc *crtc,
3019 uint32_t sprite_width,
3020 uint32_t sprite_height,
3021 int pixel_size,
3022 bool enabled, bool scaled)
3023 {
3024 struct drm_i915_private *dev_priv = plane->dev->dev_private;
3025
3026 if (dev_priv->display.update_sprite_wm)
3027 dev_priv->display.update_sprite_wm(plane, crtc,
3028 sprite_width, sprite_height,
3029 pixel_size, enabled, scaled);
3030 }
3031
3032 static struct drm_i915_gem_object *
3033 intel_alloc_context_page(struct drm_device *dev)
3034 {
3035 struct drm_i915_gem_object *ctx;
3036 int ret;
3037
3038 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3039
3040 ctx = i915_gem_alloc_object(dev, 4096);
3041 if (!ctx) {
3042 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
3043 return NULL;
3044 }
3045
3046 ret = i915_gem_obj_ggtt_pin(ctx, 4096, 0);
3047 if (ret) {
3048 DRM_ERROR("failed to pin power context: %d\n", ret);
3049 goto err_unref;
3050 }
3051
3052 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
3053 if (ret) {
3054 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
3055 goto err_unpin;
3056 }
3057
3058 return ctx;
3059
3060 err_unpin:
3061 i915_gem_object_ggtt_unpin(ctx);
3062 err_unref:
3063 drm_gem_object_unreference(&ctx->base);
3064 return NULL;
3065 }
3066
3067 /**
3068 * Lock protecting IPS related data structures
3069 */
3070 DEFINE_SPINLOCK(mchdev_lock);
3071
3072 /* Global for IPS driver to get at the current i915 device. Protected by
3073 * mchdev_lock. */
3074 static struct drm_i915_private *i915_mch_dev;
3075
3076 bool ironlake_set_drps(struct drm_device *dev, u8 val)
3077 {
3078 struct drm_i915_private *dev_priv = dev->dev_private;
3079 u16 rgvswctl;
3080
3081 assert_spin_locked(&mchdev_lock);
3082
3083 rgvswctl = I915_READ16(MEMSWCTL);
3084 if (rgvswctl & MEMCTL_CMD_STS) {
3085 DRM_DEBUG("gpu busy, RCS change rejected\n");
3086 return false; /* still busy with another command */
3087 }
3088
3089 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
3090 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
3091 I915_WRITE16(MEMSWCTL, rgvswctl);
3092 POSTING_READ16(MEMSWCTL);
3093
3094 rgvswctl |= MEMCTL_CMD_STS;
3095 I915_WRITE16(MEMSWCTL, rgvswctl);
3096
3097 return true;
3098 }
3099
3100 static void ironlake_enable_drps(struct drm_device *dev)
3101 {
3102 struct drm_i915_private *dev_priv = dev->dev_private;
3103 u32 rgvmodectl = I915_READ(MEMMODECTL);
3104 u8 fmax, fmin, fstart, vstart;
3105
3106 spin_lock_irq(&mchdev_lock);
3107
3108 /* Enable temp reporting */
3109 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
3110 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
3111
3112 /* 100ms RC evaluation intervals */
3113 I915_WRITE(RCUPEI, 100000);
3114 I915_WRITE(RCDNEI, 100000);
3115
3116 /* Set max/min thresholds to 90ms and 80ms respectively */
3117 I915_WRITE(RCBMAXAVG, 90000);
3118 I915_WRITE(RCBMINAVG, 80000);
3119
3120 I915_WRITE(MEMIHYST, 1);
3121
3122 /* Set up min, max, and cur for interrupt handling */
3123 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
3124 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
3125 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
3126 MEMMODE_FSTART_SHIFT;
3127
3128 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
3129 PXVFREQ_PX_SHIFT;
3130
3131 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
3132 dev_priv->ips.fstart = fstart;
3133
3134 dev_priv->ips.max_delay = fstart;
3135 dev_priv->ips.min_delay = fmin;
3136 dev_priv->ips.cur_delay = fstart;
3137
3138 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
3139 fmax, fmin, fstart);
3140
3141 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
3142
3143 /*
3144 * Interrupts will be enabled in ironlake_irq_postinstall
3145 */
3146
3147 I915_WRITE(VIDSTART, vstart);
3148 POSTING_READ(VIDSTART);
3149
3150 rgvmodectl |= MEMMODE_SWMODE_EN;
3151 I915_WRITE(MEMMODECTL, rgvmodectl);
3152
3153 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
3154 DRM_ERROR("stuck trying to change perf mode\n");
3155 mdelay(1);
3156
3157 ironlake_set_drps(dev, fstart);
3158
3159 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
3160 I915_READ(0x112e0);
3161 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
3162 dev_priv->ips.last_count2 = I915_READ(0x112f4);
3163 dev_priv->ips.last_time2 = ktime_get_raw_ns();
3164
3165 spin_unlock_irq(&mchdev_lock);
3166 }
3167
3168 static void ironlake_disable_drps(struct drm_device *dev)
3169 {
3170 struct drm_i915_private *dev_priv = dev->dev_private;
3171 u16 rgvswctl;
3172
3173 spin_lock_irq(&mchdev_lock);
3174
3175 rgvswctl = I915_READ16(MEMSWCTL);
3176
3177 /* Ack interrupts, disable EFC interrupt */
3178 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
3179 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
3180 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
3181 I915_WRITE(DEIIR, DE_PCU_EVENT);
3182 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
3183
3184 /* Go back to the starting frequency */
3185 ironlake_set_drps(dev, dev_priv->ips.fstart);
3186 mdelay(1);
3187 rgvswctl |= MEMCTL_CMD_STS;
3188 I915_WRITE(MEMSWCTL, rgvswctl);
3189 mdelay(1);
3190
3191 spin_unlock_irq(&mchdev_lock);
3192 }
3193
3194 /* There's a funny hw issue where the hw returns all 0 when reading from
3195 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3196 * ourselves, instead of doing a rmw cycle (which might result in us clearing
3197 * all limits and the gpu stuck at whatever frequency it is at atm).
3198 */
3199 static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)
3200 {
3201 u32 limits;
3202
3203 /* Only set the down limit when we've reached the lowest level to avoid
3204 * getting more interrupts, otherwise leave this clear. This prevents a
3205 * race in the hw when coming out of rc6: There's a tiny window where
3206 * the hw runs at the minimal clock before selecting the desired
3207 * frequency, if the down threshold expires in that window we will not
3208 * receive a down interrupt. */
3209 limits = dev_priv->rps.max_freq_softlimit << 24;
3210 if (val <= dev_priv->rps.min_freq_softlimit)
3211 limits |= dev_priv->rps.min_freq_softlimit << 16;
3212
3213 return limits;
3214 }
3215
3216 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
3217 {
3218 int new_power;
3219
3220 new_power = dev_priv->rps.power;
3221 switch (dev_priv->rps.power) {
3222 case LOW_POWER:
3223 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
3224 new_power = BETWEEN;
3225 break;
3226
3227 case BETWEEN:
3228 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
3229 new_power = LOW_POWER;
3230 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
3231 new_power = HIGH_POWER;
3232 break;
3233
3234 case HIGH_POWER:
3235 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
3236 new_power = BETWEEN;
3237 break;
3238 }
3239 /* Max/min bins are special */
3240 if (val == dev_priv->rps.min_freq_softlimit)
3241 new_power = LOW_POWER;
3242 if (val == dev_priv->rps.max_freq_softlimit)
3243 new_power = HIGH_POWER;
3244 if (new_power == dev_priv->rps.power)
3245 return;
3246
3247 /* Note the units here are not exactly 1us, but 1280ns. */
3248 switch (new_power) {
3249 case LOW_POWER:
3250 /* Upclock if more than 95% busy over 16ms */
3251 I915_WRITE(GEN6_RP_UP_EI, 12500);
3252 I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800);
3253
3254 /* Downclock if less than 85% busy over 32ms */
3255 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3256 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250);
3257
3258 I915_WRITE(GEN6_RP_CONTROL,
3259 GEN6_RP_MEDIA_TURBO |
3260 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3261 GEN6_RP_MEDIA_IS_GFX |
3262 GEN6_RP_ENABLE |
3263 GEN6_RP_UP_BUSY_AVG |
3264 GEN6_RP_DOWN_IDLE_AVG);
3265 break;
3266
3267 case BETWEEN:
3268 /* Upclock if more than 90% busy over 13ms */
3269 I915_WRITE(GEN6_RP_UP_EI, 10250);
3270 I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225);
3271
3272 /* Downclock if less than 75% busy over 32ms */
3273 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3274 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750);
3275
3276 I915_WRITE(GEN6_RP_CONTROL,
3277 GEN6_RP_MEDIA_TURBO |
3278 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3279 GEN6_RP_MEDIA_IS_GFX |
3280 GEN6_RP_ENABLE |
3281 GEN6_RP_UP_BUSY_AVG |
3282 GEN6_RP_DOWN_IDLE_AVG);
3283 break;
3284
3285 case HIGH_POWER:
3286 /* Upclock if more than 85% busy over 10ms */
3287 I915_WRITE(GEN6_RP_UP_EI, 8000);
3288 I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800);
3289
3290 /* Downclock if less than 60% busy over 32ms */
3291 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3292 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000);
3293
3294 I915_WRITE(GEN6_RP_CONTROL,
3295 GEN6_RP_MEDIA_TURBO |
3296 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3297 GEN6_RP_MEDIA_IS_GFX |
3298 GEN6_RP_ENABLE |
3299 GEN6_RP_UP_BUSY_AVG |
3300 GEN6_RP_DOWN_IDLE_AVG);
3301 break;
3302 }
3303
3304 dev_priv->rps.power = new_power;
3305 dev_priv->rps.last_adj = 0;
3306 }
3307
3308 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
3309 {
3310 u32 mask = 0;
3311
3312 if (val > dev_priv->rps.min_freq_softlimit)
3313 mask |= GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
3314 if (val < dev_priv->rps.max_freq_softlimit)
3315 mask |= GEN6_PM_RP_UP_THRESHOLD;
3316
3317 mask |= dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED);
3318 mask &= dev_priv->pm_rps_events;
3319
3320 /* IVB and SNB hard hangs on looping batchbuffer
3321 * if GEN6_PM_UP_EI_EXPIRED is masked.
3322 */
3323 if (INTEL_INFO(dev_priv->dev)->gen <= 7 && !IS_HASWELL(dev_priv->dev))
3324 mask |= GEN6_PM_RP_UP_EI_EXPIRED;
3325
3326 if (IS_GEN8(dev_priv->dev))
3327 mask |= GEN8_PMINTR_REDIRECT_TO_NON_DISP;
3328
3329 return ~mask;
3330 }
3331
3332 /* gen6_set_rps is called to update the frequency request, but should also be
3333 * called when the range (min_delay and max_delay) is modified so that we can
3334 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
3335 void gen6_set_rps(struct drm_device *dev, u8 val)
3336 {
3337 struct drm_i915_private *dev_priv = dev->dev_private;
3338
3339 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3340 WARN_ON(val > dev_priv->rps.max_freq_softlimit);
3341 WARN_ON(val < dev_priv->rps.min_freq_softlimit);
3342
3343 /* min/max delay may still have been modified so be sure to
3344 * write the limits value.
3345 */
3346 if (val != dev_priv->rps.cur_freq) {
3347 gen6_set_rps_thresholds(dev_priv, val);
3348
3349 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3350 I915_WRITE(GEN6_RPNSWREQ,
3351 HSW_FREQUENCY(val));
3352 else
3353 I915_WRITE(GEN6_RPNSWREQ,
3354 GEN6_FREQUENCY(val) |
3355 GEN6_OFFSET(0) |
3356 GEN6_AGGRESSIVE_TURBO);
3357 }
3358
3359 /* Make sure we continue to get interrupts
3360 * until we hit the minimum or maximum frequencies.
3361 */
3362 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, gen6_rps_limits(dev_priv, val));
3363 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
3364
3365 POSTING_READ(GEN6_RPNSWREQ);
3366
3367 dev_priv->rps.cur_freq = val;
3368 trace_intel_gpu_freq_change(val * 50);
3369 }
3370
3371 /* vlv_set_rps_idle: Set the frequency to Rpn if Gfx clocks are down
3372 *
3373 * * If Gfx is Idle, then
3374 * 1. Mask Turbo interrupts
3375 * 2. Bring up Gfx clock
3376 * 3. Change the freq to Rpn and wait till P-Unit updates freq
3377 * 4. Clear the Force GFX CLK ON bit so that Gfx can down
3378 * 5. Unmask Turbo interrupts
3379 */
3380 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
3381 {
3382 struct drm_device *dev = dev_priv->dev;
3383
3384 /* Latest VLV doesn't need to force the gfx clock */
3385 if (dev->pdev->revision >= 0xd) {
3386 valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3387 return;
3388 }
3389
3390 /*
3391 * When we are idle. Drop to min voltage state.
3392 */
3393
3394 if (dev_priv->rps.cur_freq <= dev_priv->rps.min_freq_softlimit)
3395 return;
3396
3397 /* Mask turbo interrupt so that they will not come in between */
3398 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3399
3400 vlv_force_gfx_clock(dev_priv, true);
3401
3402 dev_priv->rps.cur_freq = dev_priv->rps.min_freq_softlimit;
3403
3404 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ,
3405 dev_priv->rps.min_freq_softlimit);
3406
3407 if (wait_for(((vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS))
3408 & GENFREQSTATUS) == 0, 5))
3409 DRM_ERROR("timed out waiting for Punit\n");
3410
3411 vlv_force_gfx_clock(dev_priv, false);
3412
3413 I915_WRITE(GEN6_PMINTRMSK,
3414 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
3415 }
3416
3417 void gen6_rps_idle(struct drm_i915_private *dev_priv)
3418 {
3419 struct drm_device *dev = dev_priv->dev;
3420
3421 mutex_lock(&dev_priv->rps.hw_lock);
3422 if (dev_priv->rps.enabled) {
3423 if (IS_CHERRYVIEW(dev))
3424 valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3425 else if (IS_VALLEYVIEW(dev))
3426 vlv_set_rps_idle(dev_priv);
3427 else
3428 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3429 dev_priv->rps.last_adj = 0;
3430 }
3431 mutex_unlock(&dev_priv->rps.hw_lock);
3432 }
3433
3434 void gen6_rps_boost(struct drm_i915_private *dev_priv)
3435 {
3436 struct drm_device *dev = dev_priv->dev;
3437
3438 mutex_lock(&dev_priv->rps.hw_lock);
3439 if (dev_priv->rps.enabled) {
3440 if (IS_VALLEYVIEW(dev))
3441 valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
3442 else
3443 gen6_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
3444 dev_priv->rps.last_adj = 0;
3445 }
3446 mutex_unlock(&dev_priv->rps.hw_lock);
3447 }
3448
3449 void valleyview_set_rps(struct drm_device *dev, u8 val)
3450 {
3451 struct drm_i915_private *dev_priv = dev->dev_private;
3452
3453 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3454 WARN_ON(val > dev_priv->rps.max_freq_softlimit);
3455 WARN_ON(val < dev_priv->rps.min_freq_softlimit);
3456
3457 DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
3458 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
3459 dev_priv->rps.cur_freq,
3460 vlv_gpu_freq(dev_priv, val), val);
3461
3462 if (val != dev_priv->rps.cur_freq)
3463 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
3464
3465 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
3466
3467 dev_priv->rps.cur_freq = val;
3468 trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val));
3469 }
3470
3471 static void gen8_disable_rps_interrupts(struct drm_device *dev)
3472 {
3473 struct drm_i915_private *dev_priv = dev->dev_private;
3474
3475 I915_WRITE(GEN6_PMINTRMSK, ~GEN8_PMINTR_REDIRECT_TO_NON_DISP);
3476 I915_WRITE(GEN8_GT_IER(2), I915_READ(GEN8_GT_IER(2)) &
3477 ~dev_priv->pm_rps_events);
3478 /* Complete PM interrupt masking here doesn't race with the rps work
3479 * item again unmasking PM interrupts because that is using a different
3480 * register (GEN8_GT_IMR(2)) to mask PM interrupts. The only risk is in
3481 * leaving stale bits in GEN8_GT_IIR(2) and GEN8_GT_IMR(2) which
3482 * gen8_enable_rps will clean up. */
3483
3484 spin_lock_irq(&dev_priv->irq_lock);
3485 dev_priv->rps.pm_iir = 0;
3486 spin_unlock_irq(&dev_priv->irq_lock);
3487
3488 I915_WRITE(GEN8_GT_IIR(2), dev_priv->pm_rps_events);
3489 }
3490
3491 static void gen6_disable_rps_interrupts(struct drm_device *dev)
3492 {
3493 struct drm_i915_private *dev_priv = dev->dev_private;
3494
3495 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3496 I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) &
3497 ~dev_priv->pm_rps_events);
3498 /* Complete PM interrupt masking here doesn't race with the rps work
3499 * item again unmasking PM interrupts because that is using a different
3500 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3501 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3502
3503 spin_lock_irq(&dev_priv->irq_lock);
3504 dev_priv->rps.pm_iir = 0;
3505 spin_unlock_irq(&dev_priv->irq_lock);
3506
3507 I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events);
3508 }
3509
3510 static void gen6_disable_rps(struct drm_device *dev)
3511 {
3512 struct drm_i915_private *dev_priv = dev->dev_private;
3513
3514 I915_WRITE(GEN6_RC_CONTROL, 0);
3515 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
3516
3517 if (IS_BROADWELL(dev))
3518 gen8_disable_rps_interrupts(dev);
3519 else
3520 gen6_disable_rps_interrupts(dev);
3521 }
3522
3523 static void cherryview_disable_rps(struct drm_device *dev)
3524 {
3525 struct drm_i915_private *dev_priv = dev->dev_private;
3526
3527 I915_WRITE(GEN6_RC_CONTROL, 0);
3528
3529 gen8_disable_rps_interrupts(dev);
3530 }
3531
3532 static void valleyview_disable_rps(struct drm_device *dev)
3533 {
3534 struct drm_i915_private *dev_priv = dev->dev_private;
3535
3536 I915_WRITE(GEN6_RC_CONTROL, 0);
3537
3538 gen6_disable_rps_interrupts(dev);
3539 }
3540
3541 static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
3542 {
3543 if (IS_VALLEYVIEW(dev)) {
3544 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
3545 mode = GEN6_RC_CTL_RC6_ENABLE;
3546 else
3547 mode = 0;
3548 }
3549 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
3550 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3551 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3552 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
3553 }
3554
3555 static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
3556 {
3557 /* No RC6 before Ironlake */
3558 if (INTEL_INFO(dev)->gen < 5)
3559 return 0;
3560
3561 /* RC6 is only on Ironlake mobile not on desktop */
3562 if (INTEL_INFO(dev)->gen == 5 && !IS_IRONLAKE_M(dev))
3563 return 0;
3564
3565 /* Respect the kernel parameter if it is set */
3566 if (enable_rc6 >= 0) {
3567 int mask;
3568
3569 if (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
3570 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
3571 INTEL_RC6pp_ENABLE;
3572 else
3573 mask = INTEL_RC6_ENABLE;
3574
3575 if ((enable_rc6 & mask) != enable_rc6)
3576 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
3577 enable_rc6 & mask, enable_rc6, mask);
3578
3579 return enable_rc6 & mask;
3580 }
3581
3582 /* Disable RC6 on Ironlake */
3583 if (INTEL_INFO(dev)->gen == 5)
3584 return 0;
3585
3586 if (IS_IVYBRIDGE(dev))
3587 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
3588
3589 return INTEL_RC6_ENABLE;
3590 }
3591
3592 int intel_enable_rc6(const struct drm_device *dev)
3593 {
3594 return i915.enable_rc6;
3595 }
3596
3597 static void gen8_enable_rps_interrupts(struct drm_device *dev)
3598 {
3599 struct drm_i915_private *dev_priv = dev->dev_private;
3600
3601 spin_lock_irq(&dev_priv->irq_lock);
3602 WARN_ON(dev_priv->rps.pm_iir);
3603 gen8_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
3604 I915_WRITE(GEN8_GT_IIR(2), dev_priv->pm_rps_events);
3605 spin_unlock_irq(&dev_priv->irq_lock);
3606 }
3607
3608 static void gen6_enable_rps_interrupts(struct drm_device *dev)
3609 {
3610 struct drm_i915_private *dev_priv = dev->dev_private;
3611
3612 spin_lock_irq(&dev_priv->irq_lock);
3613 WARN_ON(dev_priv->rps.pm_iir);
3614 gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
3615 I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events);
3616 spin_unlock_irq(&dev_priv->irq_lock);
3617 }
3618
3619 static void parse_rp_state_cap(struct drm_i915_private *dev_priv, u32 rp_state_cap)
3620 {
3621 /* All of these values are in units of 50MHz */
3622 dev_priv->rps.cur_freq = 0;
3623 /* static values from HW: RP0 < RPe < RP1 < RPn (min_freq) */
3624 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
3625 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
3626 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
3627 /* XXX: only BYT has a special efficient freq */
3628 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
3629 /* hw_max = RP0 until we check for overclocking */
3630 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
3631
3632 /* Preserve min/max settings in case of re-init */
3633 if (dev_priv->rps.max_freq_softlimit == 0)
3634 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
3635
3636 if (dev_priv->rps.min_freq_softlimit == 0)
3637 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
3638 }
3639
3640 static void gen8_enable_rps(struct drm_device *dev)
3641 {
3642 struct drm_i915_private *dev_priv = dev->dev_private;
3643 struct intel_engine_cs *ring;
3644 uint32_t rc6_mask = 0, rp_state_cap;
3645 int unused;
3646
3647 /* 1a: Software RC state - RC0 */
3648 I915_WRITE(GEN6_RC_STATE, 0);
3649
3650 /* 1c & 1d: Get forcewake during program sequence. Although the driver
3651 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
3652 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3653
3654 /* 2a: Disable RC states. */
3655 I915_WRITE(GEN6_RC_CONTROL, 0);
3656
3657 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3658 parse_rp_state_cap(dev_priv, rp_state_cap);
3659
3660 /* 2b: Program RC6 thresholds.*/
3661 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
3662 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
3663 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
3664 for_each_ring(ring, dev_priv, unused)
3665 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3666 I915_WRITE(GEN6_RC_SLEEP, 0);
3667 if (IS_BROADWELL(dev))
3668 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
3669 else
3670 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
3671
3672 /* 3: Enable RC6 */
3673 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
3674 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
3675 intel_print_rc6_info(dev, rc6_mask);
3676 if (IS_BROADWELL(dev))
3677 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
3678 GEN7_RC_CTL_TO_MODE |
3679 rc6_mask);
3680 else
3681 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
3682 GEN6_RC_CTL_EI_MODE(1) |
3683 rc6_mask);
3684
3685 /* 4 Program defaults and thresholds for RPS*/
3686 I915_WRITE(GEN6_RPNSWREQ,
3687 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
3688 I915_WRITE(GEN6_RC_VIDEO_FREQ,
3689 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
3690 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
3691 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
3692
3693 /* Docs recommend 900MHz, and 300 MHz respectively */
3694 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
3695 dev_priv->rps.max_freq_softlimit << 24 |
3696 dev_priv->rps.min_freq_softlimit << 16);
3697
3698 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
3699 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
3700 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
3701 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
3702
3703 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3704
3705 /* 5: Enable RPS */
3706 I915_WRITE(GEN6_RP_CONTROL,
3707 GEN6_RP_MEDIA_TURBO |
3708 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3709 GEN6_RP_MEDIA_IS_GFX |
3710 GEN6_RP_ENABLE |
3711 GEN6_RP_UP_BUSY_AVG |
3712 GEN6_RP_DOWN_IDLE_AVG);
3713
3714 /* 6: Ring frequency + overclocking (our driver does this later */
3715
3716 gen6_set_rps(dev, (I915_READ(GEN6_GT_PERF_STATUS) & 0xff00) >> 8);
3717
3718 gen8_enable_rps_interrupts(dev);
3719
3720 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3721 }
3722
3723 static void gen6_enable_rps(struct drm_device *dev)
3724 {
3725 struct drm_i915_private *dev_priv = dev->dev_private;
3726 struct intel_engine_cs *ring;
3727 u32 rp_state_cap;
3728 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
3729 u32 gtfifodbg;
3730 int rc6_mode;
3731 int i, ret;
3732
3733 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3734
3735 /* Here begins a magic sequence of register writes to enable
3736 * auto-downclocking.
3737 *
3738 * Perhaps there might be some value in exposing these to
3739 * userspace...
3740 */
3741 I915_WRITE(GEN6_RC_STATE, 0);
3742
3743 /* Clear the DBG now so we don't confuse earlier errors */
3744 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3745 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3746 I915_WRITE(GTFIFODBG, gtfifodbg);
3747 }
3748
3749 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3750
3751 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3752
3753 parse_rp_state_cap(dev_priv, rp_state_cap);
3754
3755 /* disable the counters and set deterministic thresholds */
3756 I915_WRITE(GEN6_RC_CONTROL, 0);
3757
3758 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
3759 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
3760 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
3761 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3762 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3763
3764 for_each_ring(ring, dev_priv, i)
3765 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3766
3767 I915_WRITE(GEN6_RC_SLEEP, 0);
3768 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
3769 if (IS_IVYBRIDGE(dev))
3770 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
3771 else
3772 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
3773 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
3774 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
3775
3776 /* Check if we are enabling RC6 */
3777 rc6_mode = intel_enable_rc6(dev_priv->dev);
3778 if (rc6_mode & INTEL_RC6_ENABLE)
3779 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
3780
3781 /* We don't use those on Haswell */
3782 if (!IS_HASWELL(dev)) {
3783 if (rc6_mode & INTEL_RC6p_ENABLE)
3784 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
3785
3786 if (rc6_mode & INTEL_RC6pp_ENABLE)
3787 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
3788 }
3789
3790 intel_print_rc6_info(dev, rc6_mask);
3791
3792 I915_WRITE(GEN6_RC_CONTROL,
3793 rc6_mask |
3794 GEN6_RC_CTL_EI_MODE(1) |
3795 GEN6_RC_CTL_HW_ENABLE);
3796
3797 /* Power down if completely idle for over 50ms */
3798 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
3799 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3800
3801 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
3802 if (ret)
3803 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
3804
3805 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
3806 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
3807 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
3808 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
3809 (pcu_mbox & 0xff) * 50);
3810 dev_priv->rps.max_freq = pcu_mbox & 0xff;
3811 }
3812
3813 dev_priv->rps.power = HIGH_POWER; /* force a reset */
3814 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3815
3816 gen6_enable_rps_interrupts(dev);
3817
3818 rc6vids = 0;
3819 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
3820 if (IS_GEN6(dev) && ret) {
3821 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
3822 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
3823 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
3824 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
3825 rc6vids &= 0xffff00;
3826 rc6vids |= GEN6_ENCODE_RC6_VID(450);
3827 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
3828 if (ret)
3829 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
3830 }
3831
3832 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3833 }
3834
3835 static void __gen6_update_ring_freq(struct drm_device *dev)
3836 {
3837 struct drm_i915_private *dev_priv = dev->dev_private;
3838 int min_freq = 15;
3839 unsigned int gpu_freq;
3840 unsigned int max_ia_freq, min_ring_freq;
3841 int scaling_factor = 180;
3842 struct cpufreq_policy *policy;
3843
3844 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3845
3846 policy = cpufreq_cpu_get(0);
3847 if (policy) {
3848 max_ia_freq = policy->cpuinfo.max_freq;
3849 cpufreq_cpu_put(policy);
3850 } else {
3851 /*
3852 * Default to measured freq if none found, PCU will ensure we
3853 * don't go over
3854 */
3855 max_ia_freq = tsc_khz;
3856 }
3857
3858 /* Convert from kHz to MHz */
3859 max_ia_freq /= 1000;
3860
3861 min_ring_freq = I915_READ(DCLK) & 0xf;
3862 /* convert DDR frequency from units of 266.6MHz to bandwidth */
3863 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3864
3865 /*
3866 * For each potential GPU frequency, load a ring frequency we'd like
3867 * to use for memory access. We do this by specifying the IA frequency
3868 * the PCU should use as a reference to determine the ring frequency.
3869 */
3870 for (gpu_freq = dev_priv->rps.max_freq_softlimit; gpu_freq >= dev_priv->rps.min_freq_softlimit;
3871 gpu_freq--) {
3872 int diff = dev_priv->rps.max_freq_softlimit - gpu_freq;
3873 unsigned int ia_freq = 0, ring_freq = 0;
3874
3875 if (INTEL_INFO(dev)->gen >= 8) {
3876 /* max(2 * GT, DDR). NB: GT is 50MHz units */
3877 ring_freq = max(min_ring_freq, gpu_freq);
3878 } else if (IS_HASWELL(dev)) {
3879 ring_freq = mult_frac(gpu_freq, 5, 4);
3880 ring_freq = max(min_ring_freq, ring_freq);
3881 /* leave ia_freq as the default, chosen by cpufreq */
3882 } else {
3883 /* On older processors, there is no separate ring
3884 * clock domain, so in order to boost the bandwidth
3885 * of the ring, we need to upclock the CPU (ia_freq).
3886 *
3887 * For GPU frequencies less than 750MHz,
3888 * just use the lowest ring freq.
3889 */
3890 if (gpu_freq < min_freq)
3891 ia_freq = 800;
3892 else
3893 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
3894 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
3895 }
3896
3897 sandybridge_pcode_write(dev_priv,
3898 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3899 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
3900 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
3901 gpu_freq);
3902 }
3903 }
3904
3905 void gen6_update_ring_freq(struct drm_device *dev)
3906 {
3907 struct drm_i915_private *dev_priv = dev->dev_private;
3908
3909 if (INTEL_INFO(dev)->gen < 6 || IS_VALLEYVIEW(dev))
3910 return;
3911
3912 mutex_lock(&dev_priv->rps.hw_lock);
3913 __gen6_update_ring_freq(dev);
3914 mutex_unlock(&dev_priv->rps.hw_lock);
3915 }
3916
3917 static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
3918 {
3919 u32 val, rp0;
3920
3921 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
3922 rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & PUNIT_GPU_STATUS_MAX_FREQ_MASK;
3923
3924 return rp0;
3925 }
3926
3927 static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
3928 {
3929 u32 val, rpe;
3930
3931 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
3932 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
3933
3934 return rpe;
3935 }
3936
3937 static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
3938 {
3939 u32 val, rp1;
3940
3941 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
3942 rp1 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & PUNIT_GPU_STATUS_MAX_FREQ_MASK;
3943
3944 return rp1;
3945 }
3946
3947 static int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
3948 {
3949 u32 val, rpn;
3950
3951 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
3952 rpn = (val >> PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT) & PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK;
3953 return rpn;
3954 }
3955
3956 static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
3957 {
3958 u32 val, rp1;
3959
3960 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
3961
3962 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
3963
3964 return rp1;
3965 }
3966
3967 static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
3968 {
3969 u32 val, rp0;
3970
3971 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
3972
3973 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
3974 /* Clamp to max */
3975 rp0 = min_t(u32, rp0, 0xea);
3976
3977 return rp0;
3978 }
3979
3980 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
3981 {
3982 u32 val, rpe;
3983
3984 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
3985 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
3986 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
3987 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
3988
3989 return rpe;
3990 }
3991
3992 static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
3993 {
3994 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
3995 }
3996
3997 /* Check that the pctx buffer wasn't move under us. */
3998 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
3999 {
4000 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
4001
4002 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
4003 dev_priv->vlv_pctx->stolen->start);
4004 }
4005
4006
4007 /* Check that the pcbr address is not empty. */
4008 static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
4009 {
4010 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
4011
4012 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
4013 }
4014
4015 static void cherryview_setup_pctx(struct drm_device *dev)
4016 {
4017 struct drm_i915_private *dev_priv = dev->dev_private;
4018 unsigned long pctx_paddr, paddr;
4019 struct i915_gtt *gtt = &dev_priv->gtt;
4020 u32 pcbr;
4021 int pctx_size = 32*1024;
4022
4023 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4024
4025 pcbr = I915_READ(VLV_PCBR);
4026 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
4027 paddr = (dev_priv->mm.stolen_base +
4028 (gtt->stolen_size - pctx_size));
4029
4030 pctx_paddr = (paddr & (~4095));
4031 I915_WRITE(VLV_PCBR, pctx_paddr);
4032 }
4033 }
4034
4035 static void valleyview_setup_pctx(struct drm_device *dev)
4036 {
4037 struct drm_i915_private *dev_priv = dev->dev_private;
4038 struct drm_i915_gem_object *pctx;
4039 unsigned long pctx_paddr;
4040 u32 pcbr;
4041 int pctx_size = 24*1024;
4042
4043 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4044
4045 pcbr = I915_READ(VLV_PCBR);
4046 if (pcbr) {
4047 /* BIOS set it up already, grab the pre-alloc'd space */
4048 int pcbr_offset;
4049
4050 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
4051 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
4052 pcbr_offset,
4053 I915_GTT_OFFSET_NONE,
4054 pctx_size);
4055 goto out;
4056 }
4057
4058 /*
4059 * From the Gunit register HAS:
4060 * The Gfx driver is expected to program this register and ensure
4061 * proper allocation within Gfx stolen memory. For example, this
4062 * register should be programmed such than the PCBR range does not
4063 * overlap with other ranges, such as the frame buffer, protected
4064 * memory, or any other relevant ranges.
4065 */
4066 pctx = i915_gem_object_create_stolen(dev, pctx_size);
4067 if (!pctx) {
4068 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
4069 return;
4070 }
4071
4072 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
4073 I915_WRITE(VLV_PCBR, pctx_paddr);
4074
4075 out:
4076 dev_priv->vlv_pctx = pctx;
4077 }
4078
4079 static void valleyview_cleanup_pctx(struct drm_device *dev)
4080 {
4081 struct drm_i915_private *dev_priv = dev->dev_private;
4082
4083 if (WARN_ON(!dev_priv->vlv_pctx))
4084 return;
4085
4086 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
4087 dev_priv->vlv_pctx = NULL;
4088 }
4089
4090 static void valleyview_init_gt_powersave(struct drm_device *dev)
4091 {
4092 struct drm_i915_private *dev_priv = dev->dev_private;
4093
4094 valleyview_setup_pctx(dev);
4095
4096 mutex_lock(&dev_priv->rps.hw_lock);
4097
4098 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
4099 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
4100 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
4101 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4102 dev_priv->rps.max_freq);
4103
4104 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
4105 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
4106 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4107 dev_priv->rps.efficient_freq);
4108
4109 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
4110 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
4111 vlv_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
4112 dev_priv->rps.rp1_freq);
4113
4114 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
4115 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
4116 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4117 dev_priv->rps.min_freq);
4118
4119 /* Preserve min/max settings in case of re-init */
4120 if (dev_priv->rps.max_freq_softlimit == 0)
4121 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4122
4123 if (dev_priv->rps.min_freq_softlimit == 0)
4124 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
4125
4126 mutex_unlock(&dev_priv->rps.hw_lock);
4127 }
4128
4129 static void cherryview_init_gt_powersave(struct drm_device *dev)
4130 {
4131 struct drm_i915_private *dev_priv = dev->dev_private;
4132
4133 cherryview_setup_pctx(dev);
4134
4135 mutex_lock(&dev_priv->rps.hw_lock);
4136
4137 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
4138 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
4139 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
4140 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4141 dev_priv->rps.max_freq);
4142
4143 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
4144 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
4145 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4146 dev_priv->rps.efficient_freq);
4147
4148 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
4149 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
4150 vlv_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
4151 dev_priv->rps.rp1_freq);
4152
4153 dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv);
4154 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
4155 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4156 dev_priv->rps.min_freq);
4157
4158 /* Preserve min/max settings in case of re-init */
4159 if (dev_priv->rps.max_freq_softlimit == 0)
4160 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4161
4162 if (dev_priv->rps.min_freq_softlimit == 0)
4163 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
4164
4165 mutex_unlock(&dev_priv->rps.hw_lock);
4166 }
4167
4168 static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
4169 {
4170 valleyview_cleanup_pctx(dev);
4171 }
4172
4173 static void cherryview_enable_rps(struct drm_device *dev)
4174 {
4175 struct drm_i915_private *dev_priv = dev->dev_private;
4176 struct intel_engine_cs *ring;
4177 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
4178 int i;
4179
4180 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4181
4182 gtfifodbg = I915_READ(GTFIFODBG);
4183 if (gtfifodbg) {
4184 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4185 gtfifodbg);
4186 I915_WRITE(GTFIFODBG, gtfifodbg);
4187 }
4188
4189 cherryview_check_pctx(dev_priv);
4190
4191 /* 1a & 1b: Get forcewake during program sequence. Although the driver
4192 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4193 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
4194
4195 /* 2a: Program RC6 thresholds.*/
4196 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4197 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4198 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4199
4200 for_each_ring(ring, dev_priv, i)
4201 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4202 I915_WRITE(GEN6_RC_SLEEP, 0);
4203
4204 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
4205
4206 /* allows RC6 residency counter to work */
4207 I915_WRITE(VLV_COUNTER_CONTROL,
4208 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
4209 VLV_MEDIA_RC6_COUNT_EN |
4210 VLV_RENDER_RC6_COUNT_EN));
4211
4212 /* For now we assume BIOS is allocating and populating the PCBR */
4213 pcbr = I915_READ(VLV_PCBR);
4214
4215 DRM_DEBUG_DRIVER("PCBR offset : 0x%x\n", pcbr);
4216
4217 /* 3: Enable RC6 */
4218 if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
4219 (pcbr >> VLV_PCBR_ADDR_SHIFT))
4220 rc6_mode = GEN6_RC_CTL_EI_MODE(1);
4221
4222 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
4223
4224 /* 4 Program defaults and thresholds for RPS*/
4225 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
4226 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
4227 I915_WRITE(GEN6_RP_UP_EI, 66000);
4228 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
4229
4230 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4231
4232 /* WaDisablePwrmtrEvent:chv (pre-production hw) */
4233 I915_WRITE(0xA80C, I915_READ(0xA80C) & 0x00ffffff);
4234 I915_WRITE(0xA810, I915_READ(0xA810) & 0xffffff00);
4235
4236 /* 5: Enable RPS */
4237 I915_WRITE(GEN6_RP_CONTROL,
4238 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4239 GEN6_RP_MEDIA_IS_GFX | /* WaSetMaskForGfxBusyness:chv (pre-production hw ?) */
4240 GEN6_RP_ENABLE |
4241 GEN6_RP_UP_BUSY_AVG |
4242 GEN6_RP_DOWN_IDLE_AVG);
4243
4244 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4245
4246 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
4247 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
4248
4249 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
4250 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
4251 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
4252 dev_priv->rps.cur_freq);
4253
4254 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
4255 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4256 dev_priv->rps.efficient_freq);
4257
4258 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
4259
4260 gen8_enable_rps_interrupts(dev);
4261
4262 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
4263 }
4264
4265 static void valleyview_enable_rps(struct drm_device *dev)
4266 {
4267 struct drm_i915_private *dev_priv = dev->dev_private;
4268 struct intel_engine_cs *ring;
4269 u32 gtfifodbg, val, rc6_mode = 0;
4270 int i;
4271
4272 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4273
4274 valleyview_check_pctx(dev_priv);
4275
4276 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
4277 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4278 gtfifodbg);
4279 I915_WRITE(GTFIFODBG, gtfifodbg);
4280 }
4281
4282 /* If VLV, Forcewake all wells, else re-direct to regular path */
4283 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
4284
4285 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
4286 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
4287 I915_WRITE(GEN6_RP_UP_EI, 66000);
4288 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
4289
4290 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4291 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 0xf4240);
4292
4293 I915_WRITE(GEN6_RP_CONTROL,
4294 GEN6_RP_MEDIA_TURBO |
4295 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4296 GEN6_RP_MEDIA_IS_GFX |
4297 GEN6_RP_ENABLE |
4298 GEN6_RP_UP_BUSY_AVG |
4299 GEN6_RP_DOWN_IDLE_CONT);
4300
4301 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
4302 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4303 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4304
4305 for_each_ring(ring, dev_priv, i)
4306 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4307
4308 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
4309
4310 /* allows RC6 residency counter to work */
4311 I915_WRITE(VLV_COUNTER_CONTROL,
4312 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
4313 VLV_RENDER_RC0_COUNT_EN |
4314 VLV_MEDIA_RC6_COUNT_EN |
4315 VLV_RENDER_RC6_COUNT_EN));
4316
4317 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4318 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
4319
4320 intel_print_rc6_info(dev, rc6_mode);
4321
4322 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
4323
4324 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4325
4326 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
4327 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
4328
4329 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
4330 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
4331 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
4332 dev_priv->rps.cur_freq);
4333
4334 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
4335 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4336 dev_priv->rps.efficient_freq);
4337
4338 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
4339
4340 gen6_enable_rps_interrupts(dev);
4341
4342 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
4343 }
4344
4345 void ironlake_teardown_rc6(struct drm_device *dev)
4346 {
4347 struct drm_i915_private *dev_priv = dev->dev_private;
4348
4349 if (dev_priv->ips.renderctx) {
4350 i915_gem_object_ggtt_unpin(dev_priv->ips.renderctx);
4351 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
4352 dev_priv->ips.renderctx = NULL;
4353 }
4354
4355 if (dev_priv->ips.pwrctx) {
4356 i915_gem_object_ggtt_unpin(dev_priv->ips.pwrctx);
4357 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
4358 dev_priv->ips.pwrctx = NULL;
4359 }
4360 }
4361
4362 static void ironlake_disable_rc6(struct drm_device *dev)
4363 {
4364 struct drm_i915_private *dev_priv = dev->dev_private;
4365
4366 if (I915_READ(PWRCTXA)) {
4367 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
4368 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
4369 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
4370 50);
4371
4372 I915_WRITE(PWRCTXA, 0);
4373 POSTING_READ(PWRCTXA);
4374
4375 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
4376 POSTING_READ(RSTDBYCTL);
4377 }
4378 }
4379
4380 static int ironlake_setup_rc6(struct drm_device *dev)
4381 {
4382 struct drm_i915_private *dev_priv = dev->dev_private;
4383
4384 if (dev_priv->ips.renderctx == NULL)
4385 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
4386 if (!dev_priv->ips.renderctx)
4387 return -ENOMEM;
4388
4389 if (dev_priv->ips.pwrctx == NULL)
4390 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
4391 if (!dev_priv->ips.pwrctx) {
4392 ironlake_teardown_rc6(dev);
4393 return -ENOMEM;
4394 }
4395
4396 return 0;
4397 }
4398
4399 static void ironlake_enable_rc6(struct drm_device *dev)
4400 {
4401 struct drm_i915_private *dev_priv = dev->dev_private;
4402 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
4403 bool was_interruptible;
4404 int ret;
4405
4406 /* rc6 disabled by default due to repeated reports of hanging during
4407 * boot and resume.
4408 */
4409 if (!intel_enable_rc6(dev))
4410 return;
4411
4412 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4413
4414 ret = ironlake_setup_rc6(dev);
4415 if (ret)
4416 return;
4417
4418 was_interruptible = dev_priv->mm.interruptible;
4419 dev_priv->mm.interruptible = false;
4420
4421 /*
4422 * GPU can automatically power down the render unit if given a page
4423 * to save state.
4424 */
4425 ret = intel_ring_begin(ring, 6);
4426 if (ret) {
4427 ironlake_teardown_rc6(dev);
4428 dev_priv->mm.interruptible = was_interruptible;
4429 return;
4430 }
4431
4432 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
4433 intel_ring_emit(ring, MI_SET_CONTEXT);
4434 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) |
4435 MI_MM_SPACE_GTT |
4436 MI_SAVE_EXT_STATE_EN |
4437 MI_RESTORE_EXT_STATE_EN |
4438 MI_RESTORE_INHIBIT);
4439 intel_ring_emit(ring, MI_SUSPEND_FLUSH);
4440 intel_ring_emit(ring, MI_NOOP);
4441 intel_ring_emit(ring, MI_FLUSH);
4442 intel_ring_advance(ring);
4443
4444 /*
4445 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
4446 * does an implicit flush, combined with MI_FLUSH above, it should be
4447 * safe to assume that renderctx is valid
4448 */
4449 ret = intel_ring_idle(ring);
4450 dev_priv->mm.interruptible = was_interruptible;
4451 if (ret) {
4452 DRM_ERROR("failed to enable ironlake power savings\n");
4453 ironlake_teardown_rc6(dev);
4454 return;
4455 }
4456
4457 I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN);
4458 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
4459
4460 intel_print_rc6_info(dev, GEN6_RC_CTL_RC6_ENABLE);
4461 }
4462
4463 static unsigned long intel_pxfreq(u32 vidfreq)
4464 {
4465 unsigned long freq;
4466 int div = (vidfreq & 0x3f0000) >> 16;
4467 int post = (vidfreq & 0x3000) >> 12;
4468 int pre = (vidfreq & 0x7);
4469
4470 if (!pre)
4471 return 0;
4472
4473 freq = ((div * 133333) / ((1<<post) * pre));
4474
4475 return freq;
4476 }
4477
4478 static const struct cparams {
4479 u16 i;
4480 u16 t;
4481 u16 m;
4482 u16 c;
4483 } cparams[] = {
4484 { 1, 1333, 301, 28664 },
4485 { 1, 1066, 294, 24460 },
4486 { 1, 800, 294, 25192 },
4487 { 0, 1333, 276, 27605 },
4488 { 0, 1066, 276, 27605 },
4489 { 0, 800, 231, 23784 },
4490 };
4491
4492 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
4493 {
4494 u64 total_count, diff, ret;
4495 u32 count1, count2, count3, m = 0, c = 0;
4496 unsigned long now = jiffies_to_msecs(jiffies), diff1;
4497 int i;
4498
4499 assert_spin_locked(&mchdev_lock);
4500
4501 diff1 = now - dev_priv->ips.last_time1;
4502
4503 /* Prevent division-by-zero if we are asking too fast.
4504 * Also, we don't get interesting results if we are polling
4505 * faster than once in 10ms, so just return the saved value
4506 * in such cases.
4507 */
4508 if (diff1 <= 10)
4509 return dev_priv->ips.chipset_power;
4510
4511 count1 = I915_READ(DMIEC);
4512 count2 = I915_READ(DDREC);
4513 count3 = I915_READ(CSIEC);
4514
4515 total_count = count1 + count2 + count3;
4516
4517 /* FIXME: handle per-counter overflow */
4518 if (total_count < dev_priv->ips.last_count1) {
4519 diff = ~0UL - dev_priv->ips.last_count1;
4520 diff += total_count;
4521 } else {
4522 diff = total_count - dev_priv->ips.last_count1;
4523 }
4524
4525 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
4526 if (cparams[i].i == dev_priv->ips.c_m &&
4527 cparams[i].t == dev_priv->ips.r_t) {
4528 m = cparams[i].m;
4529 c = cparams[i].c;
4530 break;
4531 }
4532 }
4533
4534 diff = div_u64(diff, diff1);
4535 ret = ((m * diff) + c);
4536 ret = div_u64(ret, 10);
4537
4538 dev_priv->ips.last_count1 = total_count;
4539 dev_priv->ips.last_time1 = now;
4540
4541 dev_priv->ips.chipset_power = ret;
4542
4543 return ret;
4544 }
4545
4546 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
4547 {
4548 struct drm_device *dev = dev_priv->dev;
4549 unsigned long val;
4550
4551 if (INTEL_INFO(dev)->gen != 5)
4552 return 0;
4553
4554 spin_lock_irq(&mchdev_lock);
4555
4556 val = __i915_chipset_val(dev_priv);
4557
4558 spin_unlock_irq(&mchdev_lock);
4559
4560 return val;
4561 }
4562
4563 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
4564 {
4565 unsigned long m, x, b;
4566 u32 tsfs;
4567
4568 tsfs = I915_READ(TSFS);
4569
4570 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
4571 x = I915_READ8(TR1);
4572
4573 b = tsfs & TSFS_INTR_MASK;
4574
4575 return ((m * x) / 127) - b;
4576 }
4577
4578 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
4579 {
4580 struct drm_device *dev = dev_priv->dev;
4581 static const struct v_table {
4582 u16 vd; /* in .1 mil */
4583 u16 vm; /* in .1 mil */
4584 } v_table[] = {
4585 { 0, 0, },
4586 { 375, 0, },
4587 { 500, 0, },
4588 { 625, 0, },
4589 { 750, 0, },
4590 { 875, 0, },
4591 { 1000, 0, },
4592 { 1125, 0, },
4593 { 4125, 3000, },
4594 { 4125, 3000, },
4595 { 4125, 3000, },
4596 { 4125, 3000, },
4597 { 4125, 3000, },
4598 { 4125, 3000, },
4599 { 4125, 3000, },
4600 { 4125, 3000, },
4601 { 4125, 3000, },
4602 { 4125, 3000, },
4603 { 4125, 3000, },
4604 { 4125, 3000, },
4605 { 4125, 3000, },
4606 { 4125, 3000, },
4607 { 4125, 3000, },
4608 { 4125, 3000, },
4609 { 4125, 3000, },
4610 { 4125, 3000, },
4611 { 4125, 3000, },
4612 { 4125, 3000, },
4613 { 4125, 3000, },
4614 { 4125, 3000, },
4615 { 4125, 3000, },
4616 { 4125, 3000, },
4617 { 4250, 3125, },
4618 { 4375, 3250, },
4619 { 4500, 3375, },
4620 { 4625, 3500, },
4621 { 4750, 3625, },
4622 { 4875, 3750, },
4623 { 5000, 3875, },
4624 { 5125, 4000, },
4625 { 5250, 4125, },
4626 { 5375, 4250, },
4627 { 5500, 4375, },
4628 { 5625, 4500, },
4629 { 5750, 4625, },
4630 { 5875, 4750, },
4631 { 6000, 4875, },
4632 { 6125, 5000, },
4633 { 6250, 5125, },
4634 { 6375, 5250, },
4635 { 6500, 5375, },
4636 { 6625, 5500, },
4637 { 6750, 5625, },
4638 { 6875, 5750, },
4639 { 7000, 5875, },
4640 { 7125, 6000, },
4641 { 7250, 6125, },
4642 { 7375, 6250, },
4643 { 7500, 6375, },
4644 { 7625, 6500, },
4645 { 7750, 6625, },
4646 { 7875, 6750, },
4647 { 8000, 6875, },
4648 { 8125, 7000, },
4649 { 8250, 7125, },
4650 { 8375, 7250, },
4651 { 8500, 7375, },
4652 { 8625, 7500, },
4653 { 8750, 7625, },
4654 { 8875, 7750, },
4655 { 9000, 7875, },
4656 { 9125, 8000, },
4657 { 9250, 8125, },
4658 { 9375, 8250, },
4659 { 9500, 8375, },
4660 { 9625, 8500, },
4661 { 9750, 8625, },
4662 { 9875, 8750, },
4663 { 10000, 8875, },
4664 { 10125, 9000, },
4665 { 10250, 9125, },
4666 { 10375, 9250, },
4667 { 10500, 9375, },
4668 { 10625, 9500, },
4669 { 10750, 9625, },
4670 { 10875, 9750, },
4671 { 11000, 9875, },
4672 { 11125, 10000, },
4673 { 11250, 10125, },
4674 { 11375, 10250, },
4675 { 11500, 10375, },
4676 { 11625, 10500, },
4677 { 11750, 10625, },
4678 { 11875, 10750, },
4679 { 12000, 10875, },
4680 { 12125, 11000, },
4681 { 12250, 11125, },
4682 { 12375, 11250, },
4683 { 12500, 11375, },
4684 { 12625, 11500, },
4685 { 12750, 11625, },
4686 { 12875, 11750, },
4687 { 13000, 11875, },
4688 { 13125, 12000, },
4689 { 13250, 12125, },
4690 { 13375, 12250, },
4691 { 13500, 12375, },
4692 { 13625, 12500, },
4693 { 13750, 12625, },
4694 { 13875, 12750, },
4695 { 14000, 12875, },
4696 { 14125, 13000, },
4697 { 14250, 13125, },
4698 { 14375, 13250, },
4699 { 14500, 13375, },
4700 { 14625, 13500, },
4701 { 14750, 13625, },
4702 { 14875, 13750, },
4703 { 15000, 13875, },
4704 { 15125, 14000, },
4705 { 15250, 14125, },
4706 { 15375, 14250, },
4707 { 15500, 14375, },
4708 { 15625, 14500, },
4709 { 15750, 14625, },
4710 { 15875, 14750, },
4711 { 16000, 14875, },
4712 { 16125, 15000, },
4713 };
4714 if (INTEL_INFO(dev)->is_mobile)
4715 return v_table[pxvid].vm;
4716 else
4717 return v_table[pxvid].vd;
4718 }
4719
4720 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
4721 {
4722 u64 now, diff, diffms;
4723 u32 count;
4724
4725 assert_spin_locked(&mchdev_lock);
4726
4727 now = ktime_get_raw_ns();
4728 diffms = now - dev_priv->ips.last_time2;
4729 do_div(diffms, NSEC_PER_MSEC);
4730
4731 /* Don't divide by 0 */
4732 if (!diffms)
4733 return;
4734
4735 count = I915_READ(GFXEC);
4736
4737 if (count < dev_priv->ips.last_count2) {
4738 diff = ~0UL - dev_priv->ips.last_count2;
4739 diff += count;
4740 } else {
4741 diff = count - dev_priv->ips.last_count2;
4742 }
4743
4744 dev_priv->ips.last_count2 = count;
4745 dev_priv->ips.last_time2 = now;
4746
4747 /* More magic constants... */
4748 diff = diff * 1181;
4749 diff = div_u64(diff, diffms * 10);
4750 dev_priv->ips.gfx_power = diff;
4751 }
4752
4753 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
4754 {
4755 struct drm_device *dev = dev_priv->dev;
4756
4757 if (INTEL_INFO(dev)->gen != 5)
4758 return;
4759
4760 spin_lock_irq(&mchdev_lock);
4761
4762 __i915_update_gfx_val(dev_priv);
4763
4764 spin_unlock_irq(&mchdev_lock);
4765 }
4766
4767 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
4768 {
4769 unsigned long t, corr, state1, corr2, state2;
4770 u32 pxvid, ext_v;
4771
4772 assert_spin_locked(&mchdev_lock);
4773
4774 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_freq * 4));
4775 pxvid = (pxvid >> 24) & 0x7f;
4776 ext_v = pvid_to_extvid(dev_priv, pxvid);
4777
4778 state1 = ext_v;
4779
4780 t = i915_mch_val(dev_priv);
4781
4782 /* Revel in the empirically derived constants */
4783
4784 /* Correction factor in 1/100000 units */
4785 if (t > 80)
4786 corr = ((t * 2349) + 135940);
4787 else if (t >= 50)
4788 corr = ((t * 964) + 29317);
4789 else /* < 50 */
4790 corr = ((t * 301) + 1004);
4791
4792 corr = corr * ((150142 * state1) / 10000 - 78642);
4793 corr /= 100000;
4794 corr2 = (corr * dev_priv->ips.corr);
4795
4796 state2 = (corr2 * state1) / 10000;
4797 state2 /= 100; /* convert to mW */
4798
4799 __i915_update_gfx_val(dev_priv);
4800
4801 return dev_priv->ips.gfx_power + state2;
4802 }
4803
4804 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
4805 {
4806 struct drm_device *dev = dev_priv->dev;
4807 unsigned long val;
4808
4809 if (INTEL_INFO(dev)->gen != 5)
4810 return 0;
4811
4812 spin_lock_irq(&mchdev_lock);
4813
4814 val = __i915_gfx_val(dev_priv);
4815
4816 spin_unlock_irq(&mchdev_lock);
4817
4818 return val;
4819 }
4820
4821 /**
4822 * i915_read_mch_val - return value for IPS use
4823 *
4824 * Calculate and return a value for the IPS driver to use when deciding whether
4825 * we have thermal and power headroom to increase CPU or GPU power budget.
4826 */
4827 unsigned long i915_read_mch_val(void)
4828 {
4829 struct drm_i915_private *dev_priv;
4830 unsigned long chipset_val, graphics_val, ret = 0;
4831
4832 spin_lock_irq(&mchdev_lock);
4833 if (!i915_mch_dev)
4834 goto out_unlock;
4835 dev_priv = i915_mch_dev;
4836
4837 chipset_val = __i915_chipset_val(dev_priv);
4838 graphics_val = __i915_gfx_val(dev_priv);
4839
4840 ret = chipset_val + graphics_val;
4841
4842 out_unlock:
4843 spin_unlock_irq(&mchdev_lock);
4844
4845 return ret;
4846 }
4847 EXPORT_SYMBOL_GPL(i915_read_mch_val);
4848
4849 /**
4850 * i915_gpu_raise - raise GPU frequency limit
4851 *
4852 * Raise the limit; IPS indicates we have thermal headroom.
4853 */
4854 bool i915_gpu_raise(void)
4855 {
4856 struct drm_i915_private *dev_priv;
4857 bool ret = true;
4858
4859 spin_lock_irq(&mchdev_lock);
4860 if (!i915_mch_dev) {
4861 ret = false;
4862 goto out_unlock;
4863 }
4864 dev_priv = i915_mch_dev;
4865
4866 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
4867 dev_priv->ips.max_delay--;
4868
4869 out_unlock:
4870 spin_unlock_irq(&mchdev_lock);
4871
4872 return ret;
4873 }
4874 EXPORT_SYMBOL_GPL(i915_gpu_raise);
4875
4876 /**
4877 * i915_gpu_lower - lower GPU frequency limit
4878 *
4879 * IPS indicates we're close to a thermal limit, so throttle back the GPU
4880 * frequency maximum.
4881 */
4882 bool i915_gpu_lower(void)
4883 {
4884 struct drm_i915_private *dev_priv;
4885 bool ret = true;
4886
4887 spin_lock_irq(&mchdev_lock);
4888 if (!i915_mch_dev) {
4889 ret = false;
4890 goto out_unlock;
4891 }
4892 dev_priv = i915_mch_dev;
4893
4894 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
4895 dev_priv->ips.max_delay++;
4896
4897 out_unlock:
4898 spin_unlock_irq(&mchdev_lock);
4899
4900 return ret;
4901 }
4902 EXPORT_SYMBOL_GPL(i915_gpu_lower);
4903
4904 /**
4905 * i915_gpu_busy - indicate GPU business to IPS
4906 *
4907 * Tell the IPS driver whether or not the GPU is busy.
4908 */
4909 bool i915_gpu_busy(void)
4910 {
4911 struct drm_i915_private *dev_priv;
4912 struct intel_engine_cs *ring;
4913 bool ret = false;
4914 int i;
4915
4916 spin_lock_irq(&mchdev_lock);
4917 if (!i915_mch_dev)
4918 goto out_unlock;
4919 dev_priv = i915_mch_dev;
4920
4921 for_each_ring(ring, dev_priv, i)
4922 ret |= !list_empty(&ring->request_list);
4923
4924 out_unlock:
4925 spin_unlock_irq(&mchdev_lock);
4926
4927 return ret;
4928 }
4929 EXPORT_SYMBOL_GPL(i915_gpu_busy);
4930
4931 /**
4932 * i915_gpu_turbo_disable - disable graphics turbo
4933 *
4934 * Disable graphics turbo by resetting the max frequency and setting the
4935 * current frequency to the default.
4936 */
4937 bool i915_gpu_turbo_disable(void)
4938 {
4939 struct drm_i915_private *dev_priv;
4940 bool ret = true;
4941
4942 spin_lock_irq(&mchdev_lock);
4943 if (!i915_mch_dev) {
4944 ret = false;
4945 goto out_unlock;
4946 }
4947 dev_priv = i915_mch_dev;
4948
4949 dev_priv->ips.max_delay = dev_priv->ips.fstart;
4950
4951 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
4952 ret = false;
4953
4954 out_unlock:
4955 spin_unlock_irq(&mchdev_lock);
4956
4957 return ret;
4958 }
4959 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
4960
4961 /**
4962 * Tells the intel_ips driver that the i915 driver is now loaded, if
4963 * IPS got loaded first.
4964 *
4965 * This awkward dance is so that neither module has to depend on the
4966 * other in order for IPS to do the appropriate communication of
4967 * GPU turbo limits to i915.
4968 */
4969 static void
4970 ips_ping_for_i915_load(void)
4971 {
4972 void (*link)(void);
4973
4974 link = symbol_get(ips_link_to_i915_driver);
4975 if (link) {
4976 link();
4977 symbol_put(ips_link_to_i915_driver);
4978 }
4979 }
4980
4981 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
4982 {
4983 /* We only register the i915 ips part with intel-ips once everything is
4984 * set up, to avoid intel-ips sneaking in and reading bogus values. */
4985 spin_lock_irq(&mchdev_lock);
4986 i915_mch_dev = dev_priv;
4987 spin_unlock_irq(&mchdev_lock);
4988
4989 ips_ping_for_i915_load();
4990 }
4991
4992 void intel_gpu_ips_teardown(void)
4993 {
4994 spin_lock_irq(&mchdev_lock);
4995 i915_mch_dev = NULL;
4996 spin_unlock_irq(&mchdev_lock);
4997 }
4998
4999 static void intel_init_emon(struct drm_device *dev)
5000 {
5001 struct drm_i915_private *dev_priv = dev->dev_private;
5002 u32 lcfuse;
5003 u8 pxw[16];
5004 int i;
5005
5006 /* Disable to program */
5007 I915_WRITE(ECR, 0);
5008 POSTING_READ(ECR);
5009
5010 /* Program energy weights for various events */
5011 I915_WRITE(SDEW, 0x15040d00);
5012 I915_WRITE(CSIEW0, 0x007f0000);
5013 I915_WRITE(CSIEW1, 0x1e220004);
5014 I915_WRITE(CSIEW2, 0x04000004);
5015
5016 for (i = 0; i < 5; i++)
5017 I915_WRITE(PEW + (i * 4), 0);
5018 for (i = 0; i < 3; i++)
5019 I915_WRITE(DEW + (i * 4), 0);
5020
5021 /* Program P-state weights to account for frequency power adjustment */
5022 for (i = 0; i < 16; i++) {
5023 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
5024 unsigned long freq = intel_pxfreq(pxvidfreq);
5025 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5026 PXVFREQ_PX_SHIFT;
5027 unsigned long val;
5028
5029 val = vid * vid;
5030 val *= (freq / 1000);
5031 val *= 255;
5032 val /= (127*127*900);
5033 if (val > 0xff)
5034 DRM_ERROR("bad pxval: %ld\n", val);
5035 pxw[i] = val;
5036 }
5037 /* Render standby states get 0 weight */
5038 pxw[14] = 0;
5039 pxw[15] = 0;
5040
5041 for (i = 0; i < 4; i++) {
5042 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5043 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
5044 I915_WRITE(PXW + (i * 4), val);
5045 }
5046
5047 /* Adjust magic regs to magic values (more experimental results) */
5048 I915_WRITE(OGW0, 0);
5049 I915_WRITE(OGW1, 0);
5050 I915_WRITE(EG0, 0x00007f00);
5051 I915_WRITE(EG1, 0x0000000e);
5052 I915_WRITE(EG2, 0x000e0000);
5053 I915_WRITE(EG3, 0x68000300);
5054 I915_WRITE(EG4, 0x42000000);
5055 I915_WRITE(EG5, 0x00140031);
5056 I915_WRITE(EG6, 0);
5057 I915_WRITE(EG7, 0);
5058
5059 for (i = 0; i < 8; i++)
5060 I915_WRITE(PXWL + (i * 4), 0);
5061
5062 /* Enable PMON + select events */
5063 I915_WRITE(ECR, 0x80000019);
5064
5065 lcfuse = I915_READ(LCFUSE02);
5066
5067 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
5068 }
5069
5070 void intel_init_gt_powersave(struct drm_device *dev)
5071 {
5072 i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
5073
5074 if (IS_CHERRYVIEW(dev))
5075 cherryview_init_gt_powersave(dev);
5076 else if (IS_VALLEYVIEW(dev))
5077 valleyview_init_gt_powersave(dev);
5078 }
5079
5080 void intel_cleanup_gt_powersave(struct drm_device *dev)
5081 {
5082 if (IS_CHERRYVIEW(dev))
5083 return;
5084 else if (IS_VALLEYVIEW(dev))
5085 valleyview_cleanup_gt_powersave(dev);
5086 }
5087
5088 /**
5089 * intel_suspend_gt_powersave - suspend PM work and helper threads
5090 * @dev: drm device
5091 *
5092 * We don't want to disable RC6 or other features here, we just want
5093 * to make sure any work we've queued has finished and won't bother
5094 * us while we're suspended.
5095 */
5096 void intel_suspend_gt_powersave(struct drm_device *dev)
5097 {
5098 struct drm_i915_private *dev_priv = dev->dev_private;
5099
5100 /* Interrupts should be disabled already to avoid re-arming. */
5101 WARN_ON(intel_irqs_enabled(dev_priv));
5102
5103 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
5104
5105 cancel_work_sync(&dev_priv->rps.work);
5106
5107 /* Force GPU to min freq during suspend */
5108 gen6_rps_idle(dev_priv);
5109 }
5110
5111 void intel_disable_gt_powersave(struct drm_device *dev)
5112 {
5113 struct drm_i915_private *dev_priv = dev->dev_private;
5114
5115 /* Interrupts should be disabled already to avoid re-arming. */
5116 WARN_ON(intel_irqs_enabled(dev_priv));
5117
5118 if (IS_IRONLAKE_M(dev)) {
5119 ironlake_disable_drps(dev);
5120 ironlake_disable_rc6(dev);
5121 } else if (INTEL_INFO(dev)->gen >= 6) {
5122 intel_suspend_gt_powersave(dev);
5123
5124 mutex_lock(&dev_priv->rps.hw_lock);
5125 if (IS_CHERRYVIEW(dev))
5126 cherryview_disable_rps(dev);
5127 else if (IS_VALLEYVIEW(dev))
5128 valleyview_disable_rps(dev);
5129 else
5130 gen6_disable_rps(dev);
5131 dev_priv->rps.enabled = false;
5132 mutex_unlock(&dev_priv->rps.hw_lock);
5133 }
5134 }
5135
5136 static void intel_gen6_powersave_work(struct work_struct *work)
5137 {
5138 struct drm_i915_private *dev_priv =
5139 container_of(work, struct drm_i915_private,
5140 rps.delayed_resume_work.work);
5141 struct drm_device *dev = dev_priv->dev;
5142
5143 mutex_lock(&dev_priv->rps.hw_lock);
5144
5145 if (IS_CHERRYVIEW(dev)) {
5146 cherryview_enable_rps(dev);
5147 } else if (IS_VALLEYVIEW(dev)) {
5148 valleyview_enable_rps(dev);
5149 } else if (IS_BROADWELL(dev)) {
5150 gen8_enable_rps(dev);
5151 __gen6_update_ring_freq(dev);
5152 } else {
5153 gen6_enable_rps(dev);
5154 __gen6_update_ring_freq(dev);
5155 }
5156 dev_priv->rps.enabled = true;
5157 mutex_unlock(&dev_priv->rps.hw_lock);
5158
5159 intel_runtime_pm_put(dev_priv);
5160 }
5161
5162 void intel_enable_gt_powersave(struct drm_device *dev)
5163 {
5164 struct drm_i915_private *dev_priv = dev->dev_private;
5165
5166 if (IS_IRONLAKE_M(dev)) {
5167 mutex_lock(&dev->struct_mutex);
5168 ironlake_enable_drps(dev);
5169 ironlake_enable_rc6(dev);
5170 intel_init_emon(dev);
5171 mutex_unlock(&dev->struct_mutex);
5172 } else if (INTEL_INFO(dev)->gen >= 6) {
5173 /*
5174 * PCU communication is slow and this doesn't need to be
5175 * done at any specific time, so do this out of our fast path
5176 * to make resume and init faster.
5177 *
5178 * We depend on the HW RC6 power context save/restore
5179 * mechanism when entering D3 through runtime PM suspend. So
5180 * disable RPM until RPS/RC6 is properly setup. We can only
5181 * get here via the driver load/system resume/runtime resume
5182 * paths, so the _noresume version is enough (and in case of
5183 * runtime resume it's necessary).
5184 */
5185 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
5186 round_jiffies_up_relative(HZ)))
5187 intel_runtime_pm_get_noresume(dev_priv);
5188 }
5189 }
5190
5191 void intel_reset_gt_powersave(struct drm_device *dev)
5192 {
5193 struct drm_i915_private *dev_priv = dev->dev_private;
5194
5195 dev_priv->rps.enabled = false;
5196 intel_enable_gt_powersave(dev);
5197 }
5198
5199 static void ibx_init_clock_gating(struct drm_device *dev)
5200 {
5201 struct drm_i915_private *dev_priv = dev->dev_private;
5202
5203 /*
5204 * On Ibex Peak and Cougar Point, we need to disable clock
5205 * gating for the panel power sequencer or it will fail to
5206 * start up when no ports are active.
5207 */
5208 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
5209 }
5210
5211 static void g4x_disable_trickle_feed(struct drm_device *dev)
5212 {
5213 struct drm_i915_private *dev_priv = dev->dev_private;
5214 int pipe;
5215
5216 for_each_pipe(pipe) {
5217 I915_WRITE(DSPCNTR(pipe),
5218 I915_READ(DSPCNTR(pipe)) |
5219 DISPPLANE_TRICKLE_FEED_DISABLE);
5220 intel_flush_primary_plane(dev_priv, pipe);
5221 }
5222 }
5223
5224 static void ilk_init_lp_watermarks(struct drm_device *dev)
5225 {
5226 struct drm_i915_private *dev_priv = dev->dev_private;
5227
5228 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
5229 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
5230 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
5231
5232 /*
5233 * Don't touch WM1S_LP_EN here.
5234 * Doing so could cause underruns.
5235 */
5236 }
5237
5238 static void ironlake_init_clock_gating(struct drm_device *dev)
5239 {
5240 struct drm_i915_private *dev_priv = dev->dev_private;
5241 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
5242
5243 /*
5244 * Required for FBC
5245 * WaFbcDisableDpfcClockGating:ilk
5246 */
5247 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
5248 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
5249 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
5250
5251 I915_WRITE(PCH_3DCGDIS0,
5252 MARIUNIT_CLOCK_GATE_DISABLE |
5253 SVSMUNIT_CLOCK_GATE_DISABLE);
5254 I915_WRITE(PCH_3DCGDIS1,
5255 VFMUNIT_CLOCK_GATE_DISABLE);
5256
5257 /*
5258 * According to the spec the following bits should be set in
5259 * order to enable memory self-refresh
5260 * The bit 22/21 of 0x42004
5261 * The bit 5 of 0x42020
5262 * The bit 15 of 0x45000
5263 */
5264 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5265 (I915_READ(ILK_DISPLAY_CHICKEN2) |
5266 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
5267 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
5268 I915_WRITE(DISP_ARB_CTL,
5269 (I915_READ(DISP_ARB_CTL) |
5270 DISP_FBC_WM_DIS));
5271
5272 ilk_init_lp_watermarks(dev);
5273
5274 /*
5275 * Based on the document from hardware guys the following bits
5276 * should be set unconditionally in order to enable FBC.
5277 * The bit 22 of 0x42000
5278 * The bit 22 of 0x42004
5279 * The bit 7,8,9 of 0x42020.
5280 */
5281 if (IS_IRONLAKE_M(dev)) {
5282 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
5283 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5284 I915_READ(ILK_DISPLAY_CHICKEN1) |
5285 ILK_FBCQ_DIS);
5286 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5287 I915_READ(ILK_DISPLAY_CHICKEN2) |
5288 ILK_DPARB_GATE);
5289 }
5290
5291 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
5292
5293 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5294 I915_READ(ILK_DISPLAY_CHICKEN2) |
5295 ILK_ELPIN_409_SELECT);
5296 I915_WRITE(_3D_CHICKEN2,
5297 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
5298 _3D_CHICKEN2_WM_READ_PIPELINED);
5299
5300 /* WaDisableRenderCachePipelinedFlush:ilk */
5301 I915_WRITE(CACHE_MODE_0,
5302 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
5303
5304 /* WaDisable_RenderCache_OperationalFlush:ilk */
5305 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5306
5307 g4x_disable_trickle_feed(dev);
5308
5309 ibx_init_clock_gating(dev);
5310 }
5311
5312 static void cpt_init_clock_gating(struct drm_device *dev)
5313 {
5314 struct drm_i915_private *dev_priv = dev->dev_private;
5315 int pipe;
5316 uint32_t val;
5317
5318 /*
5319 * On Ibex Peak and Cougar Point, we need to disable clock
5320 * gating for the panel power sequencer or it will fail to
5321 * start up when no ports are active.
5322 */
5323 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
5324 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
5325 PCH_CPUNIT_CLOCK_GATE_DISABLE);
5326 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
5327 DPLS_EDP_PPS_FIX_DIS);
5328 /* The below fixes the weird display corruption, a few pixels shifted
5329 * downward, on (only) LVDS of some HP laptops with IVY.
5330 */
5331 for_each_pipe(pipe) {
5332 val = I915_READ(TRANS_CHICKEN2(pipe));
5333 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
5334 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
5335 if (dev_priv->vbt.fdi_rx_polarity_inverted)
5336 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
5337 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
5338 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
5339 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
5340 I915_WRITE(TRANS_CHICKEN2(pipe), val);
5341 }
5342 /* WADP0ClockGatingDisable */
5343 for_each_pipe(pipe) {
5344 I915_WRITE(TRANS_CHICKEN1(pipe),
5345 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
5346 }
5347 }
5348
5349 static void gen6_check_mch_setup(struct drm_device *dev)
5350 {
5351 struct drm_i915_private *dev_priv = dev->dev_private;
5352 uint32_t tmp;
5353
5354 tmp = I915_READ(MCH_SSKPD);
5355 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
5356 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
5357 tmp);
5358 }
5359
5360 static void gen6_init_clock_gating(struct drm_device *dev)
5361 {
5362 struct drm_i915_private *dev_priv = dev->dev_private;
5363 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
5364
5365 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
5366
5367 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5368 I915_READ(ILK_DISPLAY_CHICKEN2) |
5369 ILK_ELPIN_409_SELECT);
5370
5371 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
5372 I915_WRITE(_3D_CHICKEN,
5373 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
5374
5375 /* WaSetupGtModeTdRowDispatch:snb */
5376 if (IS_SNB_GT1(dev))
5377 I915_WRITE(GEN6_GT_MODE,
5378 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
5379
5380 /* WaDisable_RenderCache_OperationalFlush:snb */
5381 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5382
5383 /*
5384 * BSpec recoomends 8x4 when MSAA is used,
5385 * however in practice 16x4 seems fastest.
5386 *
5387 * Note that PS/WM thread counts depend on the WIZ hashing
5388 * disable bit, which we don't touch here, but it's good
5389 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5390 */
5391 I915_WRITE(GEN6_GT_MODE,
5392 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5393
5394 ilk_init_lp_watermarks(dev);
5395
5396 I915_WRITE(CACHE_MODE_0,
5397 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
5398
5399 I915_WRITE(GEN6_UCGCTL1,
5400 I915_READ(GEN6_UCGCTL1) |
5401 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
5402 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
5403
5404 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5405 * gating disable must be set. Failure to set it results in
5406 * flickering pixels due to Z write ordering failures after
5407 * some amount of runtime in the Mesa "fire" demo, and Unigine
5408 * Sanctuary and Tropics, and apparently anything else with
5409 * alpha test or pixel discard.
5410 *
5411 * According to the spec, bit 11 (RCCUNIT) must also be set,
5412 * but we didn't debug actual testcases to find it out.
5413 *
5414 * WaDisableRCCUnitClockGating:snb
5415 * WaDisableRCPBUnitClockGating:snb
5416 */
5417 I915_WRITE(GEN6_UCGCTL2,
5418 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
5419 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5420
5421 /* WaStripsFansDisableFastClipPerformanceFix:snb */
5422 I915_WRITE(_3D_CHICKEN3,
5423 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
5424
5425 /*
5426 * Bspec says:
5427 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
5428 * 3DSTATE_SF number of SF output attributes is more than 16."
5429 */
5430 I915_WRITE(_3D_CHICKEN3,
5431 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
5432
5433 /*
5434 * According to the spec the following bits should be
5435 * set in order to enable memory self-refresh and fbc:
5436 * The bit21 and bit22 of 0x42000
5437 * The bit21 and bit22 of 0x42004
5438 * The bit5 and bit7 of 0x42020
5439 * The bit14 of 0x70180
5440 * The bit14 of 0x71180
5441 *
5442 * WaFbcAsynchFlipDisableFbcQueue:snb
5443 */
5444 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5445 I915_READ(ILK_DISPLAY_CHICKEN1) |
5446 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
5447 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5448 I915_READ(ILK_DISPLAY_CHICKEN2) |
5449 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
5450 I915_WRITE(ILK_DSPCLK_GATE_D,
5451 I915_READ(ILK_DSPCLK_GATE_D) |
5452 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
5453 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
5454
5455 g4x_disable_trickle_feed(dev);
5456
5457 cpt_init_clock_gating(dev);
5458
5459 gen6_check_mch_setup(dev);
5460 }
5461
5462 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
5463 {
5464 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
5465
5466 /*
5467 * WaVSThreadDispatchOverride:ivb,vlv
5468 *
5469 * This actually overrides the dispatch
5470 * mode for all thread types.
5471 */
5472 reg &= ~GEN7_FF_SCHED_MASK;
5473 reg |= GEN7_FF_TS_SCHED_HW;
5474 reg |= GEN7_FF_VS_SCHED_HW;
5475 reg |= GEN7_FF_DS_SCHED_HW;
5476
5477 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
5478 }
5479
5480 static void lpt_init_clock_gating(struct drm_device *dev)
5481 {
5482 struct drm_i915_private *dev_priv = dev->dev_private;
5483
5484 /*
5485 * TODO: this bit should only be enabled when really needed, then
5486 * disabled when not needed anymore in order to save power.
5487 */
5488 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
5489 I915_WRITE(SOUTH_DSPCLK_GATE_D,
5490 I915_READ(SOUTH_DSPCLK_GATE_D) |
5491 PCH_LP_PARTITION_LEVEL_DISABLE);
5492
5493 /* WADPOClockGatingDisable:hsw */
5494 I915_WRITE(_TRANSA_CHICKEN1,
5495 I915_READ(_TRANSA_CHICKEN1) |
5496 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
5497 }
5498
5499 static void lpt_suspend_hw(struct drm_device *dev)
5500 {
5501 struct drm_i915_private *dev_priv = dev->dev_private;
5502
5503 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
5504 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
5505
5506 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
5507 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
5508 }
5509 }
5510
5511 static void gen8_init_clock_gating(struct drm_device *dev)
5512 {
5513 struct drm_i915_private *dev_priv = dev->dev_private;
5514 enum pipe pipe;
5515
5516 I915_WRITE(WM3_LP_ILK, 0);
5517 I915_WRITE(WM2_LP_ILK, 0);
5518 I915_WRITE(WM1_LP_ILK, 0);
5519
5520 /* FIXME(BDW): Check all the w/a, some might only apply to
5521 * pre-production hw. */
5522
5523 /* WaDisablePartialInstShootdown:bdw */
5524 I915_WRITE(GEN8_ROW_CHICKEN,
5525 _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE));
5526
5527 /* WaDisableThreadStallDopClockGating:bdw */
5528 /* FIXME: Unclear whether we really need this on production bdw. */
5529 I915_WRITE(GEN8_ROW_CHICKEN,
5530 _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
5531
5532 /*
5533 * This GEN8_CENTROID_PIXEL_OPT_DIS W/A is only needed for
5534 * pre-production hardware
5535 */
5536 I915_WRITE(HALF_SLICE_CHICKEN3,
5537 _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS));
5538 I915_WRITE(HALF_SLICE_CHICKEN3,
5539 _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
5540 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE));
5541
5542 I915_WRITE(_3D_CHICKEN3,
5543 _MASKED_BIT_ENABLE(_3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2)));
5544
5545 I915_WRITE(COMMON_SLICE_CHICKEN2,
5546 _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE));
5547
5548 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5549 _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE));
5550
5551 /* WaDisableDopClockGating:bdw May not be needed for production */
5552 I915_WRITE(GEN7_ROW_CHICKEN2,
5553 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5554
5555 /* WaSwitchSolVfFArbitrationPriority:bdw */
5556 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
5557
5558 /* WaPsrDPAMaskVBlankInSRD:bdw */
5559 I915_WRITE(CHICKEN_PAR1_1,
5560 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
5561
5562 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
5563 for_each_pipe(pipe) {
5564 I915_WRITE(CHICKEN_PIPESL_1(pipe),
5565 I915_READ(CHICKEN_PIPESL_1(pipe)) |
5566 BDW_DPRS_MASK_VBLANK_SRD);
5567 }
5568
5569 /* Use Force Non-Coherent whenever executing a 3D context. This is a
5570 * workaround for for a possible hang in the unlikely event a TLB
5571 * invalidation occurs during a PSD flush.
5572 */
5573 I915_WRITE(HDC_CHICKEN0,
5574 I915_READ(HDC_CHICKEN0) |
5575 _MASKED_BIT_ENABLE(HDC_FORCE_NON_COHERENT));
5576
5577 /* WaVSRefCountFullforceMissDisable:bdw */
5578 /* WaDSRefCountFullforceMissDisable:bdw */
5579 I915_WRITE(GEN7_FF_THREAD_MODE,
5580 I915_READ(GEN7_FF_THREAD_MODE) &
5581 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
5582
5583 /*
5584 * BSpec recommends 8x4 when MSAA is used,
5585 * however in practice 16x4 seems fastest.
5586 *
5587 * Note that PS/WM thread counts depend on the WIZ hashing
5588 * disable bit, which we don't touch here, but it's good
5589 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5590 */
5591 I915_WRITE(GEN7_GT_MODE,
5592 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5593
5594 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
5595 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
5596
5597 /* WaDisableSDEUnitClockGating:bdw */
5598 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
5599 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5600
5601 /* Wa4x4STCOptimizationDisable:bdw */
5602 I915_WRITE(CACHE_MODE_1,
5603 _MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE));
5604 }
5605
5606 static void haswell_init_clock_gating(struct drm_device *dev)
5607 {
5608 struct drm_i915_private *dev_priv = dev->dev_private;
5609
5610 ilk_init_lp_watermarks(dev);
5611
5612 /* L3 caching of data atomics doesn't work -- disable it. */
5613 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
5614 I915_WRITE(HSW_ROW_CHICKEN3,
5615 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
5616
5617 /* This is required by WaCatErrorRejectionIssue:hsw */
5618 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5619 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5620 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5621
5622 /* WaVSRefCountFullforceMissDisable:hsw */
5623 I915_WRITE(GEN7_FF_THREAD_MODE,
5624 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
5625
5626 /* WaDisable_RenderCache_OperationalFlush:hsw */
5627 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5628
5629 /* enable HiZ Raw Stall Optimization */
5630 I915_WRITE(CACHE_MODE_0_GEN7,
5631 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
5632
5633 /* WaDisable4x2SubspanOptimization:hsw */
5634 I915_WRITE(CACHE_MODE_1,
5635 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5636
5637 /*
5638 * BSpec recommends 8x4 when MSAA is used,
5639 * however in practice 16x4 seems fastest.
5640 *
5641 * Note that PS/WM thread counts depend on the WIZ hashing
5642 * disable bit, which we don't touch here, but it's good
5643 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5644 */
5645 I915_WRITE(GEN7_GT_MODE,
5646 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5647
5648 /* WaSwitchSolVfFArbitrationPriority:hsw */
5649 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
5650
5651 /* WaRsPkgCStateDisplayPMReq:hsw */
5652 I915_WRITE(CHICKEN_PAR1_1,
5653 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
5654
5655 lpt_init_clock_gating(dev);
5656 }
5657
5658 static void ivybridge_init_clock_gating(struct drm_device *dev)
5659 {
5660 struct drm_i915_private *dev_priv = dev->dev_private;
5661 uint32_t snpcr;
5662
5663 ilk_init_lp_watermarks(dev);
5664
5665 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
5666
5667 /* WaDisableEarlyCull:ivb */
5668 I915_WRITE(_3D_CHICKEN3,
5669 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5670
5671 /* WaDisableBackToBackFlipFix:ivb */
5672 I915_WRITE(IVB_CHICKEN3,
5673 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5674 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5675
5676 /* WaDisablePSDDualDispatchEnable:ivb */
5677 if (IS_IVB_GT1(dev))
5678 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5679 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5680
5681 /* WaDisable_RenderCache_OperationalFlush:ivb */
5682 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5683
5684 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
5685 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5686 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5687
5688 /* WaApplyL3ControlAndL3ChickenMode:ivb */
5689 I915_WRITE(GEN7_L3CNTLREG1,
5690 GEN7_WA_FOR_GEN7_L3_CONTROL);
5691 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
5692 GEN7_WA_L3_CHICKEN_MODE);
5693 if (IS_IVB_GT1(dev))
5694 I915_WRITE(GEN7_ROW_CHICKEN2,
5695 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5696 else {
5697 /* must write both registers */
5698 I915_WRITE(GEN7_ROW_CHICKEN2,
5699 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5700 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
5701 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5702 }
5703
5704 /* WaForceL3Serialization:ivb */
5705 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5706 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5707
5708 /*
5709 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5710 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
5711 */
5712 I915_WRITE(GEN6_UCGCTL2,
5713 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
5714
5715 /* This is required by WaCatErrorRejectionIssue:ivb */
5716 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5717 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5718 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5719
5720 g4x_disable_trickle_feed(dev);
5721
5722 gen7_setup_fixed_func_scheduler(dev_priv);
5723
5724 if (0) { /* causes HiZ corruption on ivb:gt1 */
5725 /* enable HiZ Raw Stall Optimization */
5726 I915_WRITE(CACHE_MODE_0_GEN7,
5727 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
5728 }
5729
5730 /* WaDisable4x2SubspanOptimization:ivb */
5731 I915_WRITE(CACHE_MODE_1,
5732 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5733
5734 /*
5735 * BSpec recommends 8x4 when MSAA is used,
5736 * however in practice 16x4 seems fastest.
5737 *
5738 * Note that PS/WM thread counts depend on the WIZ hashing
5739 * disable bit, which we don't touch here, but it's good
5740 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5741 */
5742 I915_WRITE(GEN7_GT_MODE,
5743 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5744
5745 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5746 snpcr &= ~GEN6_MBC_SNPCR_MASK;
5747 snpcr |= GEN6_MBC_SNPCR_MED;
5748 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5749
5750 if (!HAS_PCH_NOP(dev))
5751 cpt_init_clock_gating(dev);
5752
5753 gen6_check_mch_setup(dev);
5754 }
5755
5756 static void valleyview_init_clock_gating(struct drm_device *dev)
5757 {
5758 struct drm_i915_private *dev_priv = dev->dev_private;
5759 u32 val;
5760
5761 mutex_lock(&dev_priv->rps.hw_lock);
5762 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5763 mutex_unlock(&dev_priv->rps.hw_lock);
5764 switch ((val >> 6) & 3) {
5765 case 0:
5766 case 1:
5767 dev_priv->mem_freq = 800;
5768 break;
5769 case 2:
5770 dev_priv->mem_freq = 1066;
5771 break;
5772 case 3:
5773 dev_priv->mem_freq = 1333;
5774 break;
5775 }
5776 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
5777
5778 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
5779
5780 /* WaDisableEarlyCull:vlv */
5781 I915_WRITE(_3D_CHICKEN3,
5782 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5783
5784 /* WaDisableBackToBackFlipFix:vlv */
5785 I915_WRITE(IVB_CHICKEN3,
5786 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5787 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5788
5789 /* WaPsdDispatchEnable:vlv */
5790 /* WaDisablePSDDualDispatchEnable:vlv */
5791 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5792 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
5793 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5794
5795 /* WaDisable_RenderCache_OperationalFlush:vlv */
5796 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5797
5798 /* WaForceL3Serialization:vlv */
5799 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5800 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5801
5802 /* WaDisableDopClockGating:vlv */
5803 I915_WRITE(GEN7_ROW_CHICKEN2,
5804 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5805
5806 /* This is required by WaCatErrorRejectionIssue:vlv */
5807 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5808 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5809 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5810
5811 gen7_setup_fixed_func_scheduler(dev_priv);
5812
5813 /*
5814 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5815 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
5816 */
5817 I915_WRITE(GEN6_UCGCTL2,
5818 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
5819
5820 /* WaDisableL3Bank2xClockGate:vlv
5821 * Disabling L3 clock gating- MMIO 940c[25] = 1
5822 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
5823 I915_WRITE(GEN7_UCGCTL4,
5824 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
5825
5826 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
5827
5828 /*
5829 * BSpec says this must be set, even though
5830 * WaDisable4x2SubspanOptimization isn't listed for VLV.
5831 */
5832 I915_WRITE(CACHE_MODE_1,
5833 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5834
5835 /*
5836 * WaIncreaseL3CreditsForVLVB0:vlv
5837 * This is the hardware default actually.
5838 */
5839 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
5840
5841 /*
5842 * WaDisableVLVClockGating_VBIIssue:vlv
5843 * Disable clock gating on th GCFG unit to prevent a delay
5844 * in the reporting of vblank events.
5845 */
5846 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
5847 }
5848
5849 static void cherryview_init_clock_gating(struct drm_device *dev)
5850 {
5851 struct drm_i915_private *dev_priv = dev->dev_private;
5852 u32 val;
5853
5854 mutex_lock(&dev_priv->rps.hw_lock);
5855 val = vlv_punit_read(dev_priv, CCK_FUSE_REG);
5856 mutex_unlock(&dev_priv->rps.hw_lock);
5857 switch ((val >> 2) & 0x7) {
5858 case 0:
5859 case 1:
5860 dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_200;
5861 dev_priv->mem_freq = 1600;
5862 break;
5863 case 2:
5864 dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_267;
5865 dev_priv->mem_freq = 1600;
5866 break;
5867 case 3:
5868 dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_333;
5869 dev_priv->mem_freq = 2000;
5870 break;
5871 case 4:
5872 dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_320;
5873 dev_priv->mem_freq = 1600;
5874 break;
5875 case 5:
5876 dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_400;
5877 dev_priv->mem_freq = 1600;
5878 break;
5879 }
5880 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
5881
5882 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
5883
5884 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
5885
5886 /* WaDisablePartialInstShootdown:chv */
5887 I915_WRITE(GEN8_ROW_CHICKEN,
5888 _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE));
5889
5890 /* WaDisableThreadStallDopClockGating:chv */
5891 I915_WRITE(GEN8_ROW_CHICKEN,
5892 _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
5893
5894 /* WaVSRefCountFullforceMissDisable:chv */
5895 /* WaDSRefCountFullforceMissDisable:chv */
5896 I915_WRITE(GEN7_FF_THREAD_MODE,
5897 I915_READ(GEN7_FF_THREAD_MODE) &
5898 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
5899
5900 /* WaDisableSemaphoreAndSyncFlipWait:chv */
5901 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
5902 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
5903
5904 /* WaDisableCSUnitClockGating:chv */
5905 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
5906 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
5907
5908 /* WaDisableSDEUnitClockGating:chv */
5909 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
5910 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5911
5912 /* WaDisableSamplerPowerBypass:chv (pre-production hw) */
5913 I915_WRITE(HALF_SLICE_CHICKEN3,
5914 _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
5915
5916 /* WaDisableGunitClockGating:chv (pre-production hw) */
5917 I915_WRITE(VLV_GUNIT_CLOCK_GATE, I915_READ(VLV_GUNIT_CLOCK_GATE) |
5918 GINT_DIS);
5919
5920 /* WaDisableFfDopClockGating:chv (pre-production hw) */
5921 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
5922 _MASKED_BIT_ENABLE(GEN8_FF_DOP_CLOCK_GATE_DISABLE));
5923
5924 /* WaDisableDopClockGating:chv (pre-production hw) */
5925 I915_WRITE(GEN7_ROW_CHICKEN2,
5926 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5927 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
5928 GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
5929 }
5930
5931 static void g4x_init_clock_gating(struct drm_device *dev)
5932 {
5933 struct drm_i915_private *dev_priv = dev->dev_private;
5934 uint32_t dspclk_gate;
5935
5936 I915_WRITE(RENCLK_GATE_D1, 0);
5937 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5938 GS_UNIT_CLOCK_GATE_DISABLE |
5939 CL_UNIT_CLOCK_GATE_DISABLE);
5940 I915_WRITE(RAMCLK_GATE_D, 0);
5941 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5942 OVRUNIT_CLOCK_GATE_DISABLE |
5943 OVCUNIT_CLOCK_GATE_DISABLE;
5944 if (IS_GM45(dev))
5945 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5946 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5947
5948 /* WaDisableRenderCachePipelinedFlush */
5949 I915_WRITE(CACHE_MODE_0,
5950 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
5951
5952 /* WaDisable_RenderCache_OperationalFlush:g4x */
5953 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5954
5955 g4x_disable_trickle_feed(dev);
5956 }
5957
5958 static void crestline_init_clock_gating(struct drm_device *dev)
5959 {
5960 struct drm_i915_private *dev_priv = dev->dev_private;
5961
5962 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5963 I915_WRITE(RENCLK_GATE_D2, 0);
5964 I915_WRITE(DSPCLK_GATE_D, 0);
5965 I915_WRITE(RAMCLK_GATE_D, 0);
5966 I915_WRITE16(DEUC, 0);
5967 I915_WRITE(MI_ARB_STATE,
5968 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
5969
5970 /* WaDisable_RenderCache_OperationalFlush:gen4 */
5971 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5972 }
5973
5974 static void broadwater_init_clock_gating(struct drm_device *dev)
5975 {
5976 struct drm_i915_private *dev_priv = dev->dev_private;
5977
5978 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5979 I965_RCC_CLOCK_GATE_DISABLE |
5980 I965_RCPB_CLOCK_GATE_DISABLE |
5981 I965_ISC_CLOCK_GATE_DISABLE |
5982 I965_FBC_CLOCK_GATE_DISABLE);
5983 I915_WRITE(RENCLK_GATE_D2, 0);
5984 I915_WRITE(MI_ARB_STATE,
5985 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
5986
5987 /* WaDisable_RenderCache_OperationalFlush:gen4 */
5988 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5989 }
5990
5991 static void gen3_init_clock_gating(struct drm_device *dev)
5992 {
5993 struct drm_i915_private *dev_priv = dev->dev_private;
5994 u32 dstate = I915_READ(D_STATE);
5995
5996 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5997 DSTATE_DOT_CLOCK_GATING;
5998 I915_WRITE(D_STATE, dstate);
5999
6000 if (IS_PINEVIEW(dev))
6001 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
6002
6003 /* IIR "flip pending" means done if this bit is set */
6004 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
6005
6006 /* interrupts should cause a wake up from C3 */
6007 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
6008
6009 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
6010 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
6011 }
6012
6013 static void i85x_init_clock_gating(struct drm_device *dev)
6014 {
6015 struct drm_i915_private *dev_priv = dev->dev_private;
6016
6017 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
6018
6019 /* interrupts should cause a wake up from C3 */
6020 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
6021 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
6022 }
6023
6024 static void i830_init_clock_gating(struct drm_device *dev)
6025 {
6026 struct drm_i915_private *dev_priv = dev->dev_private;
6027
6028 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
6029 }
6030
6031 void intel_init_clock_gating(struct drm_device *dev)
6032 {
6033 struct drm_i915_private *dev_priv = dev->dev_private;
6034
6035 dev_priv->display.init_clock_gating(dev);
6036 }
6037
6038 void intel_suspend_hw(struct drm_device *dev)
6039 {
6040 if (HAS_PCH_LPT(dev))
6041 lpt_suspend_hw(dev);
6042 }
6043
6044 #define for_each_power_well(i, power_well, domain_mask, power_domains) \
6045 for (i = 0; \
6046 i < (power_domains)->power_well_count && \
6047 ((power_well) = &(power_domains)->power_wells[i]); \
6048 i++) \
6049 if ((power_well)->domains & (domain_mask))
6050
6051 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
6052 for (i = (power_domains)->power_well_count - 1; \
6053 i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
6054 i--) \
6055 if ((power_well)->domains & (domain_mask))
6056
6057 /**
6058 * We should only use the power well if we explicitly asked the hardware to
6059 * enable it, so check if it's enabled and also check if we've requested it to
6060 * be enabled.
6061 */
6062 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
6063 struct i915_power_well *power_well)
6064 {
6065 return I915_READ(HSW_PWR_WELL_DRIVER) ==
6066 (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
6067 }
6068
6069 bool intel_display_power_enabled_unlocked(struct drm_i915_private *dev_priv,
6070 enum intel_display_power_domain domain)
6071 {
6072 struct i915_power_domains *power_domains;
6073 struct i915_power_well *power_well;
6074 bool is_enabled;
6075 int i;
6076
6077 if (dev_priv->pm.suspended)
6078 return false;
6079
6080 power_domains = &dev_priv->power_domains;
6081
6082 is_enabled = true;
6083
6084 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
6085 if (power_well->always_on)
6086 continue;
6087
6088 if (!power_well->hw_enabled) {
6089 is_enabled = false;
6090 break;
6091 }
6092 }
6093
6094 return is_enabled;
6095 }
6096
6097 bool intel_display_power_enabled(struct drm_i915_private *dev_priv,
6098 enum intel_display_power_domain domain)
6099 {
6100 struct i915_power_domains *power_domains;
6101 bool ret;
6102
6103 power_domains = &dev_priv->power_domains;
6104
6105 mutex_lock(&power_domains->lock);
6106 ret = intel_display_power_enabled_unlocked(dev_priv, domain);
6107 mutex_unlock(&power_domains->lock);
6108
6109 return ret;
6110 }
6111
6112 /*
6113 * Starting with Haswell, we have a "Power Down Well" that can be turned off
6114 * when not needed anymore. We have 4 registers that can request the power well
6115 * to be enabled, and it will only be disabled if none of the registers is
6116 * requesting it to be enabled.
6117 */
6118 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
6119 {
6120 struct drm_device *dev = dev_priv->dev;
6121
6122 /*
6123 * After we re-enable the power well, if we touch VGA register 0x3d5
6124 * we'll get unclaimed register interrupts. This stops after we write
6125 * anything to the VGA MSR register. The vgacon module uses this
6126 * register all the time, so if we unbind our driver and, as a
6127 * consequence, bind vgacon, we'll get stuck in an infinite loop at
6128 * console_unlock(). So make here we touch the VGA MSR register, making
6129 * sure vgacon can keep working normally without triggering interrupts
6130 * and error messages.
6131 */
6132 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
6133 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
6134 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
6135
6136 if (IS_BROADWELL(dev))
6137 gen8_irq_power_well_post_enable(dev_priv);
6138 }
6139
6140 static void hsw_set_power_well(struct drm_i915_private *dev_priv,
6141 struct i915_power_well *power_well, bool enable)
6142 {
6143 bool is_enabled, enable_requested;
6144 uint32_t tmp;
6145
6146 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
6147 is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
6148 enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
6149
6150 if (enable) {
6151 if (!enable_requested)
6152 I915_WRITE(HSW_PWR_WELL_DRIVER,
6153 HSW_PWR_WELL_ENABLE_REQUEST);
6154
6155 if (!is_enabled) {
6156 DRM_DEBUG_KMS("Enabling power well\n");
6157 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
6158 HSW_PWR_WELL_STATE_ENABLED), 20))
6159 DRM_ERROR("Timeout enabling power well\n");
6160 }
6161
6162 hsw_power_well_post_enable(dev_priv);
6163 } else {
6164 if (enable_requested) {
6165 I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
6166 POSTING_READ(HSW_PWR_WELL_DRIVER);
6167 DRM_DEBUG_KMS("Requesting to disable the power well\n");
6168 }
6169 }
6170 }
6171
6172 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
6173 struct i915_power_well *power_well)
6174 {
6175 hsw_set_power_well(dev_priv, power_well, power_well->count > 0);
6176
6177 /*
6178 * We're taking over the BIOS, so clear any requests made by it since
6179 * the driver is in charge now.
6180 */
6181 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
6182 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
6183 }
6184
6185 static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
6186 struct i915_power_well *power_well)
6187 {
6188 hsw_set_power_well(dev_priv, power_well, true);
6189 }
6190
6191 static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
6192 struct i915_power_well *power_well)
6193 {
6194 hsw_set_power_well(dev_priv, power_well, false);
6195 }
6196
6197 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
6198 struct i915_power_well *power_well)
6199 {
6200 }
6201
6202 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
6203 struct i915_power_well *power_well)
6204 {
6205 return true;
6206 }
6207
6208 static void vlv_set_power_well(struct drm_i915_private *dev_priv,
6209 struct i915_power_well *power_well, bool enable)
6210 {
6211 enum punit_power_well power_well_id = power_well->data;
6212 u32 mask;
6213 u32 state;
6214 u32 ctrl;
6215
6216 mask = PUNIT_PWRGT_MASK(power_well_id);
6217 state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) :
6218 PUNIT_PWRGT_PWR_GATE(power_well_id);
6219
6220 mutex_lock(&dev_priv->rps.hw_lock);
6221
6222 #define COND \
6223 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
6224
6225 if (COND)
6226 goto out;
6227
6228 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
6229 ctrl &= ~mask;
6230 ctrl |= state;
6231 vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
6232
6233 if (wait_for(COND, 100))
6234 DRM_ERROR("timout setting power well state %08x (%08x)\n",
6235 state,
6236 vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
6237
6238 #undef COND
6239
6240 out:
6241 mutex_unlock(&dev_priv->rps.hw_lock);
6242 }
6243
6244 static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv,
6245 struct i915_power_well *power_well)
6246 {
6247 vlv_set_power_well(dev_priv, power_well, power_well->count > 0);
6248 }
6249
6250 static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
6251 struct i915_power_well *power_well)
6252 {
6253 vlv_set_power_well(dev_priv, power_well, true);
6254 }
6255
6256 static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
6257 struct i915_power_well *power_well)
6258 {
6259 vlv_set_power_well(dev_priv, power_well, false);
6260 }
6261
6262 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
6263 struct i915_power_well *power_well)
6264 {
6265 int power_well_id = power_well->data;
6266 bool enabled = false;
6267 u32 mask;
6268 u32 state;
6269 u32 ctrl;
6270
6271 mask = PUNIT_PWRGT_MASK(power_well_id);
6272 ctrl = PUNIT_PWRGT_PWR_ON(power_well_id);
6273
6274 mutex_lock(&dev_priv->rps.hw_lock);
6275
6276 state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
6277 /*
6278 * We only ever set the power-on and power-gate states, anything
6279 * else is unexpected.
6280 */
6281 WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) &&
6282 state != PUNIT_PWRGT_PWR_GATE(power_well_id));
6283 if (state == ctrl)
6284 enabled = true;
6285
6286 /*
6287 * A transient state at this point would mean some unexpected party
6288 * is poking at the power controls too.
6289 */
6290 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
6291 WARN_ON(ctrl != state);
6292
6293 mutex_unlock(&dev_priv->rps.hw_lock);
6294
6295 return enabled;
6296 }
6297
6298 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
6299 struct i915_power_well *power_well)
6300 {
6301 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
6302
6303 vlv_set_power_well(dev_priv, power_well, true);
6304
6305 spin_lock_irq(&dev_priv->irq_lock);
6306 valleyview_enable_display_irqs(dev_priv);
6307 spin_unlock_irq(&dev_priv->irq_lock);
6308
6309 /*
6310 * During driver initialization/resume we can avoid restoring the
6311 * part of the HW/SW state that will be inited anyway explicitly.
6312 */
6313 if (dev_priv->power_domains.initializing)
6314 return;
6315
6316 intel_hpd_init(dev_priv->dev);
6317
6318 i915_redisable_vga_power_on(dev_priv->dev);
6319 }
6320
6321 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
6322 struct i915_power_well *power_well)
6323 {
6324 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
6325
6326 spin_lock_irq(&dev_priv->irq_lock);
6327 valleyview_disable_display_irqs(dev_priv);
6328 spin_unlock_irq(&dev_priv->irq_lock);
6329
6330 vlv_set_power_well(dev_priv, power_well, false);
6331 }
6332
6333 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
6334 struct i915_power_well *power_well)
6335 {
6336 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
6337
6338 /*
6339 * Enable the CRI clock source so we can get at the
6340 * display and the reference clock for VGA
6341 * hotplug / manual detection.
6342 */
6343 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
6344 DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
6345 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
6346
6347 vlv_set_power_well(dev_priv, power_well, true);
6348
6349 /*
6350 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
6351 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
6352 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
6353 * b. The other bits such as sfr settings / modesel may all
6354 * be set to 0.
6355 *
6356 * This should only be done on init and resume from S3 with
6357 * both PLLs disabled, or we risk losing DPIO and PLL
6358 * synchronization.
6359 */
6360 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
6361 }
6362
6363 static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
6364 struct i915_power_well *power_well)
6365 {
6366 struct drm_device *dev = dev_priv->dev;
6367 enum pipe pipe;
6368
6369 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
6370
6371 for_each_pipe(pipe)
6372 assert_pll_disabled(dev_priv, pipe);
6373
6374 /* Assert common reset */
6375 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST);
6376
6377 vlv_set_power_well(dev_priv, power_well, false);
6378 }
6379
6380 static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
6381 struct i915_power_well *power_well)
6382 {
6383 enum dpio_phy phy;
6384
6385 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
6386 power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
6387
6388 /*
6389 * Enable the CRI clock source so we can get at the
6390 * display and the reference clock for VGA
6391 * hotplug / manual detection.
6392 */
6393 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
6394 phy = DPIO_PHY0;
6395 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
6396 DPLL_REFA_CLK_ENABLE_VLV);
6397 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
6398 DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
6399 } else {
6400 phy = DPIO_PHY1;
6401 I915_WRITE(DPLL(PIPE_C), I915_READ(DPLL(PIPE_C)) |
6402 DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
6403 }
6404 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
6405 vlv_set_power_well(dev_priv, power_well, true);
6406
6407 /* Poll for phypwrgood signal */
6408 if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1))
6409 DRM_ERROR("Display PHY %d is not power up\n", phy);
6410
6411 I915_WRITE(DISPLAY_PHY_CONTROL, I915_READ(DISPLAY_PHY_CONTROL) |
6412 PHY_COM_LANE_RESET_DEASSERT(phy));
6413 }
6414
6415 static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
6416 struct i915_power_well *power_well)
6417 {
6418 enum dpio_phy phy;
6419
6420 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
6421 power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
6422
6423 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
6424 phy = DPIO_PHY0;
6425 assert_pll_disabled(dev_priv, PIPE_A);
6426 assert_pll_disabled(dev_priv, PIPE_B);
6427 } else {
6428 phy = DPIO_PHY1;
6429 assert_pll_disabled(dev_priv, PIPE_C);
6430 }
6431
6432 I915_WRITE(DISPLAY_PHY_CONTROL, I915_READ(DISPLAY_PHY_CONTROL) &
6433 ~PHY_COM_LANE_RESET_DEASSERT(phy));
6434
6435 vlv_set_power_well(dev_priv, power_well, false);
6436 }
6437
6438 static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,
6439 struct i915_power_well *power_well)
6440 {
6441 enum pipe pipe = power_well->data;
6442 bool enabled;
6443 u32 state, ctrl;
6444
6445 mutex_lock(&dev_priv->rps.hw_lock);
6446
6447 state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe);
6448 /*
6449 * We only ever set the power-on and power-gate states, anything
6450 * else is unexpected.
6451 */
6452 WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe));
6453 enabled = state == DP_SSS_PWR_ON(pipe);
6454
6455 /*
6456 * A transient state at this point would mean some unexpected party
6457 * is poking at the power controls too.
6458 */
6459 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe);
6460 WARN_ON(ctrl << 16 != state);
6461
6462 mutex_unlock(&dev_priv->rps.hw_lock);
6463
6464 return enabled;
6465 }
6466
6467 static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
6468 struct i915_power_well *power_well,
6469 bool enable)
6470 {
6471 enum pipe pipe = power_well->data;
6472 u32 state;
6473 u32 ctrl;
6474
6475 state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe);
6476
6477 mutex_lock(&dev_priv->rps.hw_lock);
6478
6479 #define COND \
6480 ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state)
6481
6482 if (COND)
6483 goto out;
6484
6485 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
6486 ctrl &= ~DP_SSC_MASK(pipe);
6487 ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe);
6488 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl);
6489
6490 if (wait_for(COND, 100))
6491 DRM_ERROR("timout setting power well state %08x (%08x)\n",
6492 state,
6493 vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ));
6494
6495 #undef COND
6496
6497 out:
6498 mutex_unlock(&dev_priv->rps.hw_lock);
6499 }
6500
6501 static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv,
6502 struct i915_power_well *power_well)
6503 {
6504 chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0);
6505 }
6506
6507 static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
6508 struct i915_power_well *power_well)
6509 {
6510 WARN_ON_ONCE(power_well->data != PIPE_A &&
6511 power_well->data != PIPE_B &&
6512 power_well->data != PIPE_C);
6513
6514 chv_set_pipe_power_well(dev_priv, power_well, true);
6515 }
6516
6517 static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
6518 struct i915_power_well *power_well)
6519 {
6520 WARN_ON_ONCE(power_well->data != PIPE_A &&
6521 power_well->data != PIPE_B &&
6522 power_well->data != PIPE_C);
6523
6524 chv_set_pipe_power_well(dev_priv, power_well, false);
6525 }
6526
6527 static void check_power_well_state(struct drm_i915_private *dev_priv,
6528 struct i915_power_well *power_well)
6529 {
6530 bool enabled = power_well->ops->is_enabled(dev_priv, power_well);
6531
6532 if (power_well->always_on || !i915.disable_power_well) {
6533 if (!enabled)
6534 goto mismatch;
6535
6536 return;
6537 }
6538
6539 if (enabled != (power_well->count > 0))
6540 goto mismatch;
6541
6542 return;
6543
6544 mismatch:
6545 WARN(1, "state mismatch for '%s' (always_on %d hw state %d use-count %d disable_power_well %d\n",
6546 power_well->name, power_well->always_on, enabled,
6547 power_well->count, i915.disable_power_well);
6548 }
6549
6550 void intel_display_power_get(struct drm_i915_private *dev_priv,
6551 enum intel_display_power_domain domain)
6552 {
6553 struct i915_power_domains *power_domains;
6554 struct i915_power_well *power_well;
6555 int i;
6556
6557 intel_runtime_pm_get(dev_priv);
6558
6559 power_domains = &dev_priv->power_domains;
6560
6561 mutex_lock(&power_domains->lock);
6562
6563 for_each_power_well(i, power_well, BIT(domain), power_domains) {
6564 if (!power_well->count++) {
6565 DRM_DEBUG_KMS("enabling %s\n", power_well->name);
6566 power_well->ops->enable(dev_priv, power_well);
6567 power_well->hw_enabled = true;
6568 }
6569
6570 check_power_well_state(dev_priv, power_well);
6571 }
6572
6573 power_domains->domain_use_count[domain]++;
6574
6575 mutex_unlock(&power_domains->lock);
6576 }
6577
6578 void intel_display_power_put(struct drm_i915_private *dev_priv,
6579 enum intel_display_power_domain domain)
6580 {
6581 struct i915_power_domains *power_domains;
6582 struct i915_power_well *power_well;
6583 int i;
6584
6585 power_domains = &dev_priv->power_domains;
6586
6587 mutex_lock(&power_domains->lock);
6588
6589 WARN_ON(!power_domains->domain_use_count[domain]);
6590 power_domains->domain_use_count[domain]--;
6591
6592 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
6593 WARN_ON(!power_well->count);
6594
6595 if (!--power_well->count && i915.disable_power_well) {
6596 DRM_DEBUG_KMS("disabling %s\n", power_well->name);
6597 power_well->hw_enabled = false;
6598 power_well->ops->disable(dev_priv, power_well);
6599 }
6600
6601 check_power_well_state(dev_priv, power_well);
6602 }
6603
6604 mutex_unlock(&power_domains->lock);
6605
6606 intel_runtime_pm_put(dev_priv);
6607 }
6608
6609 static struct i915_power_domains *hsw_pwr;
6610
6611 /* Display audio driver power well request */
6612 int i915_request_power_well(void)
6613 {
6614 struct drm_i915_private *dev_priv;
6615
6616 if (!hsw_pwr)
6617 return -ENODEV;
6618
6619 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
6620 power_domains);
6621 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
6622 return 0;
6623 }
6624 EXPORT_SYMBOL_GPL(i915_request_power_well);
6625
6626 /* Display audio driver power well release */
6627 int i915_release_power_well(void)
6628 {
6629 struct drm_i915_private *dev_priv;
6630
6631 if (!hsw_pwr)
6632 return -ENODEV;
6633
6634 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
6635 power_domains);
6636 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
6637 return 0;
6638 }
6639 EXPORT_SYMBOL_GPL(i915_release_power_well);
6640
6641 /*
6642 * Private interface for the audio driver to get CDCLK in kHz.
6643 *
6644 * Caller must request power well using i915_request_power_well() prior to
6645 * making the call.
6646 */
6647 int i915_get_cdclk_freq(void)
6648 {
6649 struct drm_i915_private *dev_priv;
6650
6651 if (!hsw_pwr)
6652 return -ENODEV;
6653
6654 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
6655 power_domains);
6656
6657 return intel_ddi_get_cdclk_freq(dev_priv);
6658 }
6659 EXPORT_SYMBOL_GPL(i915_get_cdclk_freq);
6660
6661
6662 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
6663
6664 #define HSW_ALWAYS_ON_POWER_DOMAINS ( \
6665 BIT(POWER_DOMAIN_PIPE_A) | \
6666 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
6667 BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
6668 BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
6669 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6670 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6671 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6672 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6673 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
6674 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
6675 BIT(POWER_DOMAIN_PORT_CRT) | \
6676 BIT(POWER_DOMAIN_PLLS) | \
6677 BIT(POWER_DOMAIN_INIT))
6678 #define HSW_DISPLAY_POWER_DOMAINS ( \
6679 (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \
6680 BIT(POWER_DOMAIN_INIT))
6681
6682 #define BDW_ALWAYS_ON_POWER_DOMAINS ( \
6683 HSW_ALWAYS_ON_POWER_DOMAINS | \
6684 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
6685 #define BDW_DISPLAY_POWER_DOMAINS ( \
6686 (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) | \
6687 BIT(POWER_DOMAIN_INIT))
6688
6689 #define VLV_ALWAYS_ON_POWER_DOMAINS BIT(POWER_DOMAIN_INIT)
6690 #define VLV_DISPLAY_POWER_DOMAINS POWER_DOMAIN_MASK
6691
6692 #define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \
6693 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6694 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6695 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6696 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6697 BIT(POWER_DOMAIN_PORT_CRT) | \
6698 BIT(POWER_DOMAIN_INIT))
6699
6700 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \
6701 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6702 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6703 BIT(POWER_DOMAIN_INIT))
6704
6705 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \
6706 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6707 BIT(POWER_DOMAIN_INIT))
6708
6709 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \
6710 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6711 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6712 BIT(POWER_DOMAIN_INIT))
6713
6714 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \
6715 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6716 BIT(POWER_DOMAIN_INIT))
6717
6718 #define CHV_PIPE_A_POWER_DOMAINS ( \
6719 BIT(POWER_DOMAIN_PIPE_A) | \
6720 BIT(POWER_DOMAIN_INIT))
6721
6722 #define CHV_PIPE_B_POWER_DOMAINS ( \
6723 BIT(POWER_DOMAIN_PIPE_B) | \
6724 BIT(POWER_DOMAIN_INIT))
6725
6726 #define CHV_PIPE_C_POWER_DOMAINS ( \
6727 BIT(POWER_DOMAIN_PIPE_C) | \
6728 BIT(POWER_DOMAIN_INIT))
6729
6730 #define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \
6731 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6732 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6733 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6734 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6735 BIT(POWER_DOMAIN_INIT))
6736
6737 #define CHV_DPIO_CMN_D_POWER_DOMAINS ( \
6738 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
6739 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
6740 BIT(POWER_DOMAIN_INIT))
6741
6742 #define CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS ( \
6743 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
6744 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
6745 BIT(POWER_DOMAIN_INIT))
6746
6747 #define CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS ( \
6748 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
6749 BIT(POWER_DOMAIN_INIT))
6750
6751 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
6752 .sync_hw = i9xx_always_on_power_well_noop,
6753 .enable = i9xx_always_on_power_well_noop,
6754 .disable = i9xx_always_on_power_well_noop,
6755 .is_enabled = i9xx_always_on_power_well_enabled,
6756 };
6757
6758 static const struct i915_power_well_ops chv_pipe_power_well_ops = {
6759 .sync_hw = chv_pipe_power_well_sync_hw,
6760 .enable = chv_pipe_power_well_enable,
6761 .disable = chv_pipe_power_well_disable,
6762 .is_enabled = chv_pipe_power_well_enabled,
6763 };
6764
6765 static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = {
6766 .sync_hw = vlv_power_well_sync_hw,
6767 .enable = chv_dpio_cmn_power_well_enable,
6768 .disable = chv_dpio_cmn_power_well_disable,
6769 .is_enabled = vlv_power_well_enabled,
6770 };
6771
6772 static struct i915_power_well i9xx_always_on_power_well[] = {
6773 {
6774 .name = "always-on",
6775 .always_on = 1,
6776 .domains = POWER_DOMAIN_MASK,
6777 .ops = &i9xx_always_on_power_well_ops,
6778 },
6779 };
6780
6781 static const struct i915_power_well_ops hsw_power_well_ops = {
6782 .sync_hw = hsw_power_well_sync_hw,
6783 .enable = hsw_power_well_enable,
6784 .disable = hsw_power_well_disable,
6785 .is_enabled = hsw_power_well_enabled,
6786 };
6787
6788 static struct i915_power_well hsw_power_wells[] = {
6789 {
6790 .name = "always-on",
6791 .always_on = 1,
6792 .domains = HSW_ALWAYS_ON_POWER_DOMAINS,
6793 .ops = &i9xx_always_on_power_well_ops,
6794 },
6795 {
6796 .name = "display",
6797 .domains = HSW_DISPLAY_POWER_DOMAINS,
6798 .ops = &hsw_power_well_ops,
6799 },
6800 };
6801
6802 static struct i915_power_well bdw_power_wells[] = {
6803 {
6804 .name = "always-on",
6805 .always_on = 1,
6806 .domains = BDW_ALWAYS_ON_POWER_DOMAINS,
6807 .ops = &i9xx_always_on_power_well_ops,
6808 },
6809 {
6810 .name = "display",
6811 .domains = BDW_DISPLAY_POWER_DOMAINS,
6812 .ops = &hsw_power_well_ops,
6813 },
6814 };
6815
6816 static const struct i915_power_well_ops vlv_display_power_well_ops = {
6817 .sync_hw = vlv_power_well_sync_hw,
6818 .enable = vlv_display_power_well_enable,
6819 .disable = vlv_display_power_well_disable,
6820 .is_enabled = vlv_power_well_enabled,
6821 };
6822
6823 static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = {
6824 .sync_hw = vlv_power_well_sync_hw,
6825 .enable = vlv_dpio_cmn_power_well_enable,
6826 .disable = vlv_dpio_cmn_power_well_disable,
6827 .is_enabled = vlv_power_well_enabled,
6828 };
6829
6830 static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
6831 .sync_hw = vlv_power_well_sync_hw,
6832 .enable = vlv_power_well_enable,
6833 .disable = vlv_power_well_disable,
6834 .is_enabled = vlv_power_well_enabled,
6835 };
6836
6837 static struct i915_power_well vlv_power_wells[] = {
6838 {
6839 .name = "always-on",
6840 .always_on = 1,
6841 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
6842 .ops = &i9xx_always_on_power_well_ops,
6843 },
6844 {
6845 .name = "display",
6846 .domains = VLV_DISPLAY_POWER_DOMAINS,
6847 .data = PUNIT_POWER_WELL_DISP2D,
6848 .ops = &vlv_display_power_well_ops,
6849 },
6850 {
6851 .name = "dpio-tx-b-01",
6852 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6853 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6854 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6855 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6856 .ops = &vlv_dpio_power_well_ops,
6857 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
6858 },
6859 {
6860 .name = "dpio-tx-b-23",
6861 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6862 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6863 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6864 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6865 .ops = &vlv_dpio_power_well_ops,
6866 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
6867 },
6868 {
6869 .name = "dpio-tx-c-01",
6870 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6871 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6872 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6873 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6874 .ops = &vlv_dpio_power_well_ops,
6875 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
6876 },
6877 {
6878 .name = "dpio-tx-c-23",
6879 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6880 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6881 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6882 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6883 .ops = &vlv_dpio_power_well_ops,
6884 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
6885 },
6886 {
6887 .name = "dpio-common",
6888 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
6889 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
6890 .ops = &vlv_dpio_cmn_power_well_ops,
6891 },
6892 };
6893
6894 static struct i915_power_well chv_power_wells[] = {
6895 {
6896 .name = "always-on",
6897 .always_on = 1,
6898 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
6899 .ops = &i9xx_always_on_power_well_ops,
6900 },
6901 #if 0
6902 {
6903 .name = "display",
6904 .domains = VLV_DISPLAY_POWER_DOMAINS,
6905 .data = PUNIT_POWER_WELL_DISP2D,
6906 .ops = &vlv_display_power_well_ops,
6907 },
6908 {
6909 .name = "pipe-a",
6910 .domains = CHV_PIPE_A_POWER_DOMAINS,
6911 .data = PIPE_A,
6912 .ops = &chv_pipe_power_well_ops,
6913 },
6914 {
6915 .name = "pipe-b",
6916 .domains = CHV_PIPE_B_POWER_DOMAINS,
6917 .data = PIPE_B,
6918 .ops = &chv_pipe_power_well_ops,
6919 },
6920 {
6921 .name = "pipe-c",
6922 .domains = CHV_PIPE_C_POWER_DOMAINS,
6923 .data = PIPE_C,
6924 .ops = &chv_pipe_power_well_ops,
6925 },
6926 #endif
6927 {
6928 .name = "dpio-common-bc",
6929 /*
6930 * XXX: cmnreset for one PHY seems to disturb the other.
6931 * As a workaround keep both powered on at the same
6932 * time for now.
6933 */
6934 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS | CHV_DPIO_CMN_D_POWER_DOMAINS,
6935 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
6936 .ops = &chv_dpio_cmn_power_well_ops,
6937 },
6938 {
6939 .name = "dpio-common-d",
6940 /*
6941 * XXX: cmnreset for one PHY seems to disturb the other.
6942 * As a workaround keep both powered on at the same
6943 * time for now.
6944 */
6945 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS | CHV_DPIO_CMN_D_POWER_DOMAINS,
6946 .data = PUNIT_POWER_WELL_DPIO_CMN_D,
6947 .ops = &chv_dpio_cmn_power_well_ops,
6948 },
6949 #if 0
6950 {
6951 .name = "dpio-tx-b-01",
6952 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6953 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS,
6954 .ops = &vlv_dpio_power_well_ops,
6955 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
6956 },
6957 {
6958 .name = "dpio-tx-b-23",
6959 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6960 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS,
6961 .ops = &vlv_dpio_power_well_ops,
6962 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
6963 },
6964 {
6965 .name = "dpio-tx-c-01",
6966 .domains = VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6967 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6968 .ops = &vlv_dpio_power_well_ops,
6969 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
6970 },
6971 {
6972 .name = "dpio-tx-c-23",
6973 .domains = VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6974 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6975 .ops = &vlv_dpio_power_well_ops,
6976 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
6977 },
6978 {
6979 .name = "dpio-tx-d-01",
6980 .domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS |
6981 CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS,
6982 .ops = &vlv_dpio_power_well_ops,
6983 .data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_01,
6984 },
6985 {
6986 .name = "dpio-tx-d-23",
6987 .domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS |
6988 CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS,
6989 .ops = &vlv_dpio_power_well_ops,
6990 .data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_23,
6991 },
6992 #endif
6993 };
6994
6995 static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv,
6996 enum punit_power_well power_well_id)
6997 {
6998 struct i915_power_domains *power_domains = &dev_priv->power_domains;
6999 struct i915_power_well *power_well;
7000 int i;
7001
7002 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
7003 if (power_well->data == power_well_id)
7004 return power_well;
7005 }
7006
7007 return NULL;
7008 }
7009
7010 #define set_power_wells(power_domains, __power_wells) ({ \
7011 (power_domains)->power_wells = (__power_wells); \
7012 (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \
7013 })
7014
7015 int intel_power_domains_init(struct drm_i915_private *dev_priv)
7016 {
7017 struct i915_power_domains *power_domains = &dev_priv->power_domains;
7018
7019 mutex_init(&power_domains->lock);
7020
7021 /*
7022 * The enabling order will be from lower to higher indexed wells,
7023 * the disabling order is reversed.
7024 */
7025 if (IS_HASWELL(dev_priv->dev)) {
7026 set_power_wells(power_domains, hsw_power_wells);
7027 hsw_pwr = power_domains;
7028 } else if (IS_BROADWELL(dev_priv->dev)) {
7029 set_power_wells(power_domains, bdw_power_wells);
7030 hsw_pwr = power_domains;
7031 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
7032 set_power_wells(power_domains, chv_power_wells);
7033 } else if (IS_VALLEYVIEW(dev_priv->dev)) {
7034 set_power_wells(power_domains, vlv_power_wells);
7035 } else {
7036 set_power_wells(power_domains, i9xx_always_on_power_well);
7037 }
7038
7039 return 0;
7040 }
7041
7042 void intel_power_domains_remove(struct drm_i915_private *dev_priv)
7043 {
7044 hsw_pwr = NULL;
7045 }
7046
7047 static void intel_power_domains_resume(struct drm_i915_private *dev_priv)
7048 {
7049 struct i915_power_domains *power_domains = &dev_priv->power_domains;
7050 struct i915_power_well *power_well;
7051 int i;
7052
7053 mutex_lock(&power_domains->lock);
7054 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
7055 power_well->ops->sync_hw(dev_priv, power_well);
7056 power_well->hw_enabled = power_well->ops->is_enabled(dev_priv,
7057 power_well);
7058 }
7059 mutex_unlock(&power_domains->lock);
7060 }
7061
7062 static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
7063 {
7064 struct i915_power_well *cmn =
7065 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
7066 struct i915_power_well *disp2d =
7067 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D);
7068
7069 /* nothing to do if common lane is already off */
7070 if (!cmn->ops->is_enabled(dev_priv, cmn))
7071 return;
7072
7073 /* If the display might be already active skip this */
7074 if (disp2d->ops->is_enabled(dev_priv, disp2d) &&
7075 I915_READ(DPIO_CTL) & DPIO_CMNRST)
7076 return;
7077
7078 DRM_DEBUG_KMS("toggling display PHY side reset\n");
7079
7080 /* cmnlane needs DPLL registers */
7081 disp2d->ops->enable(dev_priv, disp2d);
7082
7083 /*
7084 * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
7085 * Need to assert and de-assert PHY SB reset by gating the
7086 * common lane power, then un-gating it.
7087 * Simply ungating isn't enough to reset the PHY enough to get
7088 * ports and lanes running.
7089 */
7090 cmn->ops->disable(dev_priv, cmn);
7091 }
7092
7093 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv)
7094 {
7095 struct drm_device *dev = dev_priv->dev;
7096 struct i915_power_domains *power_domains = &dev_priv->power_domains;
7097
7098 power_domains->initializing = true;
7099
7100 if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
7101 mutex_lock(&power_domains->lock);
7102 vlv_cmnlane_wa(dev_priv);
7103 mutex_unlock(&power_domains->lock);
7104 }
7105
7106 /* For now, we need the power well to be always enabled. */
7107 intel_display_set_init_power(dev_priv, true);
7108 intel_power_domains_resume(dev_priv);
7109 power_domains->initializing = false;
7110 }
7111
7112 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)
7113 {
7114 intel_runtime_pm_get(dev_priv);
7115 }
7116
7117 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)
7118 {
7119 intel_runtime_pm_put(dev_priv);
7120 }
7121
7122 void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
7123 {
7124 struct drm_device *dev = dev_priv->dev;
7125 struct device *device = &dev->pdev->dev;
7126
7127 if (!HAS_RUNTIME_PM(dev))
7128 return;
7129
7130 pm_runtime_get_sync(device);
7131 WARN(dev_priv->pm.suspended, "Device still suspended.\n");
7132 }
7133
7134 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv)
7135 {
7136 struct drm_device *dev = dev_priv->dev;
7137 struct device *device = &dev->pdev->dev;
7138
7139 if (!HAS_RUNTIME_PM(dev))
7140 return;
7141
7142 WARN(dev_priv->pm.suspended, "Getting nosync-ref while suspended.\n");
7143 pm_runtime_get_noresume(device);
7144 }
7145
7146 void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
7147 {
7148 struct drm_device *dev = dev_priv->dev;
7149 struct device *device = &dev->pdev->dev;
7150
7151 if (!HAS_RUNTIME_PM(dev))
7152 return;
7153
7154 pm_runtime_mark_last_busy(device);
7155 pm_runtime_put_autosuspend(device);
7156 }
7157
7158 void intel_init_runtime_pm(struct drm_i915_private *dev_priv)
7159 {
7160 struct drm_device *dev = dev_priv->dev;
7161 struct device *device = &dev->pdev->dev;
7162
7163 if (!HAS_RUNTIME_PM(dev))
7164 return;
7165
7166 pm_runtime_set_active(device);
7167
7168 /*
7169 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
7170 * requirement.
7171 */
7172 if (!intel_enable_rc6(dev)) {
7173 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
7174 return;
7175 }
7176
7177 pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
7178 pm_runtime_mark_last_busy(device);
7179 pm_runtime_use_autosuspend(device);
7180
7181 pm_runtime_put_autosuspend(device);
7182 }
7183
7184 void intel_fini_runtime_pm(struct drm_i915_private *dev_priv)
7185 {
7186 struct drm_device *dev = dev_priv->dev;
7187 struct device *device = &dev->pdev->dev;
7188
7189 if (!HAS_RUNTIME_PM(dev))
7190 return;
7191
7192 if (!intel_enable_rc6(dev))
7193 return;
7194
7195 /* Make sure we're not suspended first. */
7196 pm_runtime_get_sync(device);
7197 pm_runtime_disable(device);
7198 }
7199
7200 /* Set up chip specific power management-related functions */
7201 void intel_init_pm(struct drm_device *dev)
7202 {
7203 struct drm_i915_private *dev_priv = dev->dev_private;
7204
7205 if (HAS_FBC(dev)) {
7206 if (INTEL_INFO(dev)->gen >= 7) {
7207 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
7208 dev_priv->display.enable_fbc = gen7_enable_fbc;
7209 dev_priv->display.disable_fbc = ironlake_disable_fbc;
7210 } else if (INTEL_INFO(dev)->gen >= 5) {
7211 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
7212 dev_priv->display.enable_fbc = ironlake_enable_fbc;
7213 dev_priv->display.disable_fbc = ironlake_disable_fbc;
7214 } else if (IS_GM45(dev)) {
7215 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
7216 dev_priv->display.enable_fbc = g4x_enable_fbc;
7217 dev_priv->display.disable_fbc = g4x_disable_fbc;
7218 } else {
7219 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
7220 dev_priv->display.enable_fbc = i8xx_enable_fbc;
7221 dev_priv->display.disable_fbc = i8xx_disable_fbc;
7222
7223 /* This value was pulled out of someone's hat */
7224 I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);
7225 }
7226 }
7227
7228 /* For cxsr */
7229 if (IS_PINEVIEW(dev))
7230 i915_pineview_get_mem_freq(dev);
7231 else if (IS_GEN5(dev))
7232 i915_ironlake_get_mem_freq(dev);
7233
7234 /* For FIFO watermark updates */
7235 if (HAS_PCH_SPLIT(dev)) {
7236 ilk_setup_wm_latency(dev);
7237
7238 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
7239 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7240 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7241 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
7242 dev_priv->display.update_wm = ilk_update_wm;
7243 dev_priv->display.update_sprite_wm = ilk_update_sprite_wm;
7244 } else {
7245 DRM_DEBUG_KMS("Failed to read display plane latency. "
7246 "Disable CxSR\n");
7247 }
7248
7249 if (IS_GEN5(dev))
7250 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7251 else if (IS_GEN6(dev))
7252 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7253 else if (IS_IVYBRIDGE(dev))
7254 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7255 else if (IS_HASWELL(dev))
7256 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7257 else if (INTEL_INFO(dev)->gen == 8)
7258 dev_priv->display.init_clock_gating = gen8_init_clock_gating;
7259 } else if (IS_CHERRYVIEW(dev)) {
7260 dev_priv->display.update_wm = cherryview_update_wm;
7261 dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;
7262 dev_priv->display.init_clock_gating =
7263 cherryview_init_clock_gating;
7264 } else if (IS_VALLEYVIEW(dev)) {
7265 dev_priv->display.update_wm = valleyview_update_wm;
7266 dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;
7267 dev_priv->display.init_clock_gating =
7268 valleyview_init_clock_gating;
7269 } else if (IS_PINEVIEW(dev)) {
7270 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7271 dev_priv->is_ddr3,
7272 dev_priv->fsb_freq,
7273 dev_priv->mem_freq)) {
7274 DRM_INFO("failed to find known CxSR latency "
7275 "(found ddr%s fsb freq %d, mem freq %d), "
7276 "disabling CxSR\n",
7277 (dev_priv->is_ddr3 == 1) ? "3" : "2",
7278 dev_priv->fsb_freq, dev_priv->mem_freq);
7279 /* Disable CxSR and never update its watermark again */
7280 intel_set_memory_cxsr(dev_priv, false);
7281 dev_priv->display.update_wm = NULL;
7282 } else
7283 dev_priv->display.update_wm = pineview_update_wm;
7284 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7285 } else if (IS_G4X(dev)) {
7286 dev_priv->display.update_wm = g4x_update_wm;
7287 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7288 } else if (IS_GEN4(dev)) {
7289 dev_priv->display.update_wm = i965_update_wm;
7290 if (IS_CRESTLINE(dev))
7291 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7292 else if (IS_BROADWATER(dev))
7293 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7294 } else if (IS_GEN3(dev)) {
7295 dev_priv->display.update_wm = i9xx_update_wm;
7296 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7297 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7298 } else if (IS_GEN2(dev)) {
7299 if (INTEL_INFO(dev)->num_pipes == 1) {
7300 dev_priv->display.update_wm = i845_update_wm;
7301 dev_priv->display.get_fifo_size = i845_get_fifo_size;
7302 } else {
7303 dev_priv->display.update_wm = i9xx_update_wm;
7304 dev_priv->display.get_fifo_size = i830_get_fifo_size;
7305 }
7306
7307 if (IS_I85X(dev) || IS_I865G(dev))
7308 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7309 else
7310 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7311 } else {
7312 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
7313 }
7314 }
7315
7316 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
7317 {
7318 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7319
7320 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7321 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7322 return -EAGAIN;
7323 }
7324
7325 I915_WRITE(GEN6_PCODE_DATA, *val);
7326 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7327
7328 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7329 500)) {
7330 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7331 return -ETIMEDOUT;
7332 }
7333
7334 *val = I915_READ(GEN6_PCODE_DATA);
7335 I915_WRITE(GEN6_PCODE_DATA, 0);
7336
7337 return 0;
7338 }
7339
7340 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
7341 {
7342 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7343
7344 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7345 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7346 return -EAGAIN;
7347 }
7348
7349 I915_WRITE(GEN6_PCODE_DATA, val);
7350 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7351
7352 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7353 500)) {
7354 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7355 return -ETIMEDOUT;
7356 }
7357
7358 I915_WRITE(GEN6_PCODE_DATA, 0);
7359
7360 return 0;
7361 }
7362
7363 static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7364 {
7365 int div;
7366
7367 /* 4 x czclk */
7368 switch (dev_priv->mem_freq) {
7369 case 800:
7370 div = 10;
7371 break;
7372 case 1066:
7373 div = 12;
7374 break;
7375 case 1333:
7376 div = 16;
7377 break;
7378 default:
7379 return -1;
7380 }
7381
7382 return DIV_ROUND_CLOSEST(dev_priv->mem_freq * (val + 6 - 0xbd), 4 * div);
7383 }
7384
7385 static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
7386 {
7387 int mul;
7388
7389 /* 4 x czclk */
7390 switch (dev_priv->mem_freq) {
7391 case 800:
7392 mul = 10;
7393 break;
7394 case 1066:
7395 mul = 12;
7396 break;
7397 case 1333:
7398 mul = 16;
7399 break;
7400 default:
7401 return -1;
7402 }
7403
7404 return DIV_ROUND_CLOSEST(4 * mul * val, dev_priv->mem_freq) + 0xbd - 6;
7405 }
7406
7407 static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
7408 {
7409 int div, freq;
7410
7411 switch (dev_priv->rps.cz_freq) {
7412 case 200:
7413 div = 5;
7414 break;
7415 case 267:
7416 div = 6;
7417 break;
7418 case 320:
7419 case 333:
7420 case 400:
7421 div = 8;
7422 break;
7423 default:
7424 return -1;
7425 }
7426
7427 freq = (DIV_ROUND_CLOSEST((dev_priv->rps.cz_freq * val), 2 * div) / 2);
7428
7429 return freq;
7430 }
7431
7432 static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
7433 {
7434 int mul, opcode;
7435
7436 switch (dev_priv->rps.cz_freq) {
7437 case 200:
7438 mul = 5;
7439 break;
7440 case 267:
7441 mul = 6;
7442 break;
7443 case 320:
7444 case 333:
7445 case 400:
7446 mul = 8;
7447 break;
7448 default:
7449 return -1;
7450 }
7451
7452 opcode = (DIV_ROUND_CLOSEST((val * 2 * mul), dev_priv->rps.cz_freq) * 2);
7453
7454 return opcode;
7455 }
7456
7457 int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val)
7458 {
7459 int ret = -1;
7460
7461 if (IS_CHERRYVIEW(dev_priv->dev))
7462 ret = chv_gpu_freq(dev_priv, val);
7463 else if (IS_VALLEYVIEW(dev_priv->dev))
7464 ret = byt_gpu_freq(dev_priv, val);
7465
7466 return ret;
7467 }
7468
7469 int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val)
7470 {
7471 int ret = -1;
7472
7473 if (IS_CHERRYVIEW(dev_priv->dev))
7474 ret = chv_freq_opcode(dev_priv, val);
7475 else if (IS_VALLEYVIEW(dev_priv->dev))
7476 ret = byt_freq_opcode(dev_priv, val);
7477
7478 return ret;
7479 }
7480
7481 void intel_pm_setup(struct drm_device *dev)
7482 {
7483 struct drm_i915_private *dev_priv = dev->dev_private;
7484
7485 mutex_init(&dev_priv->rps.hw_lock);
7486
7487 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
7488 intel_gen6_powersave_work);
7489
7490 dev_priv->pm.suspended = false;
7491 dev_priv->pm._irqs_disabled = false;
7492 }
Linux kernel - Deliverables
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