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Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_pm.c
1 /*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28 #include <linux/cpufreq.h>
29 #include "i915_drv.h"
30 #include "intel_drv.h"
31 #include "../../../platform/x86/intel_ips.h"
32 #include <linux/module.h>
33 #include <linux/vgaarb.h>
34 #include <drm/i915_powerwell.h>
35 #include <linux/pm_runtime.h>
36
37 /**
38 * RC6 is a special power stage which allows the GPU to enter an very
39 * low-voltage mode when idle, using down to 0V while at this stage. This
40 * stage is entered automatically when the GPU is idle when RC6 support is
41 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
42 *
43 * There are different RC6 modes available in Intel GPU, which differentiate
44 * among each other with the latency required to enter and leave RC6 and
45 * voltage consumed by the GPU in different states.
46 *
47 * The combination of the following flags define which states GPU is allowed
48 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
49 * RC6pp is deepest RC6. Their support by hardware varies according to the
50 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
51 * which brings the most power savings; deeper states save more power, but
52 * require higher latency to switch to and wake up.
53 */
54 #define INTEL_RC6_ENABLE (1<<0)
55 #define INTEL_RC6p_ENABLE (1<<1)
56 #define INTEL_RC6pp_ENABLE (1<<2)
57
58 /* FBC, or Frame Buffer Compression, is a technique employed to compress the
59 * framebuffer contents in-memory, aiming at reducing the required bandwidth
60 * during in-memory transfers and, therefore, reduce the power packet.
61 *
62 * The benefits of FBC are mostly visible with solid backgrounds and
63 * variation-less patterns.
64 *
65 * FBC-related functionality can be enabled by the means of the
66 * i915.i915_enable_fbc parameter
67 */
68
69 static void i8xx_disable_fbc(struct drm_device *dev)
70 {
71 struct drm_i915_private *dev_priv = dev->dev_private;
72 u32 fbc_ctl;
73
74 /* Disable compression */
75 fbc_ctl = I915_READ(FBC_CONTROL);
76 if ((fbc_ctl & FBC_CTL_EN) == 0)
77 return;
78
79 fbc_ctl &= ~FBC_CTL_EN;
80 I915_WRITE(FBC_CONTROL, fbc_ctl);
81
82 /* Wait for compressing bit to clear */
83 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
84 DRM_DEBUG_KMS("FBC idle timed out\n");
85 return;
86 }
87
88 DRM_DEBUG_KMS("disabled FBC\n");
89 }
90
91 static void i8xx_enable_fbc(struct drm_crtc *crtc)
92 {
93 struct drm_device *dev = crtc->dev;
94 struct drm_i915_private *dev_priv = dev->dev_private;
95 struct drm_framebuffer *fb = crtc->fb;
96 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
97 struct drm_i915_gem_object *obj = intel_fb->obj;
98 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
99 int cfb_pitch;
100 int plane, i;
101 u32 fbc_ctl;
102
103 cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
104 if (fb->pitches[0] < cfb_pitch)
105 cfb_pitch = fb->pitches[0];
106
107 /* FBC_CTL wants 32B or 64B units */
108 if (IS_GEN2(dev))
109 cfb_pitch = (cfb_pitch / 32) - 1;
110 else
111 cfb_pitch = (cfb_pitch / 64) - 1;
112 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
113
114 /* Clear old tags */
115 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
116 I915_WRITE(FBC_TAG + (i * 4), 0);
117
118 if (IS_GEN4(dev)) {
119 u32 fbc_ctl2;
120
121 /* Set it up... */
122 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
123 fbc_ctl2 |= plane;
124 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
125 I915_WRITE(FBC_FENCE_OFF, crtc->y);
126 }
127
128 /* enable it... */
129 fbc_ctl = I915_READ(FBC_CONTROL);
130 fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT;
131 fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
132 if (IS_I945GM(dev))
133 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
134 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
135 fbc_ctl |= obj->fence_reg;
136 I915_WRITE(FBC_CONTROL, fbc_ctl);
137
138 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c, ",
139 cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
140 }
141
142 static bool i8xx_fbc_enabled(struct drm_device *dev)
143 {
144 struct drm_i915_private *dev_priv = dev->dev_private;
145
146 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
147 }
148
149 static void g4x_enable_fbc(struct drm_crtc *crtc)
150 {
151 struct drm_device *dev = crtc->dev;
152 struct drm_i915_private *dev_priv = dev->dev_private;
153 struct drm_framebuffer *fb = crtc->fb;
154 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
155 struct drm_i915_gem_object *obj = intel_fb->obj;
156 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
157 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
158 u32 dpfc_ctl;
159
160 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
161 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
162 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
163
164 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
165
166 /* enable it... */
167 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
168
169 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
170 }
171
172 static void g4x_disable_fbc(struct drm_device *dev)
173 {
174 struct drm_i915_private *dev_priv = dev->dev_private;
175 u32 dpfc_ctl;
176
177 /* Disable compression */
178 dpfc_ctl = I915_READ(DPFC_CONTROL);
179 if (dpfc_ctl & DPFC_CTL_EN) {
180 dpfc_ctl &= ~DPFC_CTL_EN;
181 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
182
183 DRM_DEBUG_KMS("disabled FBC\n");
184 }
185 }
186
187 static bool g4x_fbc_enabled(struct drm_device *dev)
188 {
189 struct drm_i915_private *dev_priv = dev->dev_private;
190
191 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
192 }
193
194 static void sandybridge_blit_fbc_update(struct drm_device *dev)
195 {
196 struct drm_i915_private *dev_priv = dev->dev_private;
197 u32 blt_ecoskpd;
198
199 /* Make sure blitter notifies FBC of writes */
200
201 /* Blitter is part of Media powerwell on VLV. No impact of
202 * his param in other platforms for now */
203 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_MEDIA);
204
205 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
206 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
207 GEN6_BLITTER_LOCK_SHIFT;
208 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
209 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
210 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
211 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
212 GEN6_BLITTER_LOCK_SHIFT);
213 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
214 POSTING_READ(GEN6_BLITTER_ECOSKPD);
215
216 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_MEDIA);
217 }
218
219 static void ironlake_enable_fbc(struct drm_crtc *crtc)
220 {
221 struct drm_device *dev = crtc->dev;
222 struct drm_i915_private *dev_priv = dev->dev_private;
223 struct drm_framebuffer *fb = crtc->fb;
224 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
225 struct drm_i915_gem_object *obj = intel_fb->obj;
226 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
227 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
228 u32 dpfc_ctl;
229
230 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
231 dpfc_ctl &= DPFC_RESERVED;
232 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
233 /* Set persistent mode for front-buffer rendering, ala X. */
234 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
235 dpfc_ctl |= DPFC_CTL_FENCE_EN;
236 if (IS_GEN5(dev))
237 dpfc_ctl |= obj->fence_reg;
238 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
239
240 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
241 I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
242 /* enable it... */
243 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
244
245 if (IS_GEN6(dev)) {
246 I915_WRITE(SNB_DPFC_CTL_SA,
247 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
248 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
249 sandybridge_blit_fbc_update(dev);
250 }
251
252 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
253 }
254
255 static void ironlake_disable_fbc(struct drm_device *dev)
256 {
257 struct drm_i915_private *dev_priv = dev->dev_private;
258 u32 dpfc_ctl;
259
260 /* Disable compression */
261 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
262 if (dpfc_ctl & DPFC_CTL_EN) {
263 dpfc_ctl &= ~DPFC_CTL_EN;
264 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
265
266 DRM_DEBUG_KMS("disabled FBC\n");
267 }
268 }
269
270 static bool ironlake_fbc_enabled(struct drm_device *dev)
271 {
272 struct drm_i915_private *dev_priv = dev->dev_private;
273
274 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
275 }
276
277 static void gen7_enable_fbc(struct drm_crtc *crtc)
278 {
279 struct drm_device *dev = crtc->dev;
280 struct drm_i915_private *dev_priv = dev->dev_private;
281 struct drm_framebuffer *fb = crtc->fb;
282 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
283 struct drm_i915_gem_object *obj = intel_fb->obj;
284 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
285
286 I915_WRITE(IVB_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj));
287
288 I915_WRITE(ILK_DPFC_CONTROL, DPFC_CTL_EN | DPFC_CTL_LIMIT_1X |
289 IVB_DPFC_CTL_FENCE_EN |
290 intel_crtc->plane << IVB_DPFC_CTL_PLANE_SHIFT);
291
292 if (IS_IVYBRIDGE(dev)) {
293 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
294 I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS);
295 } else {
296 /* WaFbcAsynchFlipDisableFbcQueue:hsw */
297 I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe),
298 HSW_BYPASS_FBC_QUEUE);
299 }
300
301 I915_WRITE(SNB_DPFC_CTL_SA,
302 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
303 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
304
305 sandybridge_blit_fbc_update(dev);
306
307 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
308 }
309
310 bool intel_fbc_enabled(struct drm_device *dev)
311 {
312 struct drm_i915_private *dev_priv = dev->dev_private;
313
314 if (!dev_priv->display.fbc_enabled)
315 return false;
316
317 return dev_priv->display.fbc_enabled(dev);
318 }
319
320 static void intel_fbc_work_fn(struct work_struct *__work)
321 {
322 struct intel_fbc_work *work =
323 container_of(to_delayed_work(__work),
324 struct intel_fbc_work, work);
325 struct drm_device *dev = work->crtc->dev;
326 struct drm_i915_private *dev_priv = dev->dev_private;
327
328 mutex_lock(&dev->struct_mutex);
329 if (work == dev_priv->fbc.fbc_work) {
330 /* Double check that we haven't switched fb without cancelling
331 * the prior work.
332 */
333 if (work->crtc->fb == work->fb) {
334 dev_priv->display.enable_fbc(work->crtc);
335
336 dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;
337 dev_priv->fbc.fb_id = work->crtc->fb->base.id;
338 dev_priv->fbc.y = work->crtc->y;
339 }
340
341 dev_priv->fbc.fbc_work = NULL;
342 }
343 mutex_unlock(&dev->struct_mutex);
344
345 kfree(work);
346 }
347
348 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
349 {
350 if (dev_priv->fbc.fbc_work == NULL)
351 return;
352
353 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
354
355 /* Synchronisation is provided by struct_mutex and checking of
356 * dev_priv->fbc.fbc_work, so we can perform the cancellation
357 * entirely asynchronously.
358 */
359 if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
360 /* tasklet was killed before being run, clean up */
361 kfree(dev_priv->fbc.fbc_work);
362
363 /* Mark the work as no longer wanted so that if it does
364 * wake-up (because the work was already running and waiting
365 * for our mutex), it will discover that is no longer
366 * necessary to run.
367 */
368 dev_priv->fbc.fbc_work = NULL;
369 }
370
371 static void intel_enable_fbc(struct drm_crtc *crtc)
372 {
373 struct intel_fbc_work *work;
374 struct drm_device *dev = crtc->dev;
375 struct drm_i915_private *dev_priv = dev->dev_private;
376
377 if (!dev_priv->display.enable_fbc)
378 return;
379
380 intel_cancel_fbc_work(dev_priv);
381
382 work = kzalloc(sizeof(*work), GFP_KERNEL);
383 if (work == NULL) {
384 DRM_ERROR("Failed to allocate FBC work structure\n");
385 dev_priv->display.enable_fbc(crtc);
386 return;
387 }
388
389 work->crtc = crtc;
390 work->fb = crtc->fb;
391 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
392
393 dev_priv->fbc.fbc_work = work;
394
395 /* Delay the actual enabling to let pageflipping cease and the
396 * display to settle before starting the compression. Note that
397 * this delay also serves a second purpose: it allows for a
398 * vblank to pass after disabling the FBC before we attempt
399 * to modify the control registers.
400 *
401 * A more complicated solution would involve tracking vblanks
402 * following the termination of the page-flipping sequence
403 * and indeed performing the enable as a co-routine and not
404 * waiting synchronously upon the vblank.
405 *
406 * WaFbcWaitForVBlankBeforeEnable:ilk,snb
407 */
408 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
409 }
410
411 void intel_disable_fbc(struct drm_device *dev)
412 {
413 struct drm_i915_private *dev_priv = dev->dev_private;
414
415 intel_cancel_fbc_work(dev_priv);
416
417 if (!dev_priv->display.disable_fbc)
418 return;
419
420 dev_priv->display.disable_fbc(dev);
421 dev_priv->fbc.plane = -1;
422 }
423
424 static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
425 enum no_fbc_reason reason)
426 {
427 if (dev_priv->fbc.no_fbc_reason == reason)
428 return false;
429
430 dev_priv->fbc.no_fbc_reason = reason;
431 return true;
432 }
433
434 /**
435 * intel_update_fbc - enable/disable FBC as needed
436 * @dev: the drm_device
437 *
438 * Set up the framebuffer compression hardware at mode set time. We
439 * enable it if possible:
440 * - plane A only (on pre-965)
441 * - no pixel mulitply/line duplication
442 * - no alpha buffer discard
443 * - no dual wide
444 * - framebuffer <= max_hdisplay in width, max_vdisplay in height
445 *
446 * We can't assume that any compression will take place (worst case),
447 * so the compressed buffer has to be the same size as the uncompressed
448 * one. It also must reside (along with the line length buffer) in
449 * stolen memory.
450 *
451 * We need to enable/disable FBC on a global basis.
452 */
453 void intel_update_fbc(struct drm_device *dev)
454 {
455 struct drm_i915_private *dev_priv = dev->dev_private;
456 struct drm_crtc *crtc = NULL, *tmp_crtc;
457 struct intel_crtc *intel_crtc;
458 struct drm_framebuffer *fb;
459 struct intel_framebuffer *intel_fb;
460 struct drm_i915_gem_object *obj;
461 const struct drm_display_mode *adjusted_mode;
462 unsigned int max_width, max_height;
463
464 if (!HAS_FBC(dev)) {
465 set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED);
466 return;
467 }
468
469 if (!i915_powersave) {
470 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
471 DRM_DEBUG_KMS("fbc disabled per module param\n");
472 return;
473 }
474
475 /*
476 * If FBC is already on, we just have to verify that we can
477 * keep it that way...
478 * Need to disable if:
479 * - more than one pipe is active
480 * - changing FBC params (stride, fence, mode)
481 * - new fb is too large to fit in compressed buffer
482 * - going to an unsupported config (interlace, pixel multiply, etc.)
483 */
484 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
485 if (intel_crtc_active(tmp_crtc) &&
486 to_intel_crtc(tmp_crtc)->primary_enabled) {
487 if (crtc) {
488 if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
489 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
490 goto out_disable;
491 }
492 crtc = tmp_crtc;
493 }
494 }
495
496 if (!crtc || crtc->fb == NULL) {
497 if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
498 DRM_DEBUG_KMS("no output, disabling\n");
499 goto out_disable;
500 }
501
502 intel_crtc = to_intel_crtc(crtc);
503 fb = crtc->fb;
504 intel_fb = to_intel_framebuffer(fb);
505 obj = intel_fb->obj;
506 adjusted_mode = &intel_crtc->config.adjusted_mode;
507
508 if (i915_enable_fbc < 0 &&
509 INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) {
510 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
511 DRM_DEBUG_KMS("disabled per chip default\n");
512 goto out_disable;
513 }
514 if (!i915_enable_fbc) {
515 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
516 DRM_DEBUG_KMS("fbc disabled per module param\n");
517 goto out_disable;
518 }
519 if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ||
520 (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
521 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
522 DRM_DEBUG_KMS("mode incompatible with compression, "
523 "disabling\n");
524 goto out_disable;
525 }
526
527 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
528 max_width = 4096;
529 max_height = 2048;
530 } else {
531 max_width = 2048;
532 max_height = 1536;
533 }
534 if (intel_crtc->config.pipe_src_w > max_width ||
535 intel_crtc->config.pipe_src_h > max_height) {
536 if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
537 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
538 goto out_disable;
539 }
540 if ((INTEL_INFO(dev)->gen < 4 || IS_HASWELL(dev)) &&
541 intel_crtc->plane != PLANE_A) {
542 if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
543 DRM_DEBUG_KMS("plane not A, disabling compression\n");
544 goto out_disable;
545 }
546
547 /* The use of a CPU fence is mandatory in order to detect writes
548 * by the CPU to the scanout and trigger updates to the FBC.
549 */
550 if (obj->tiling_mode != I915_TILING_X ||
551 obj->fence_reg == I915_FENCE_REG_NONE) {
552 if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED))
553 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
554 goto out_disable;
555 }
556
557 /* If the kernel debugger is active, always disable compression */
558 if (in_dbg_master())
559 goto out_disable;
560
561 if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) {
562 if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL))
563 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
564 goto out_disable;
565 }
566
567 /* If the scanout has not changed, don't modify the FBC settings.
568 * Note that we make the fundamental assumption that the fb->obj
569 * cannot be unpinned (and have its GTT offset and fence revoked)
570 * without first being decoupled from the scanout and FBC disabled.
571 */
572 if (dev_priv->fbc.plane == intel_crtc->plane &&
573 dev_priv->fbc.fb_id == fb->base.id &&
574 dev_priv->fbc.y == crtc->y)
575 return;
576
577 if (intel_fbc_enabled(dev)) {
578 /* We update FBC along two paths, after changing fb/crtc
579 * configuration (modeswitching) and after page-flipping
580 * finishes. For the latter, we know that not only did
581 * we disable the FBC at the start of the page-flip
582 * sequence, but also more than one vblank has passed.
583 *
584 * For the former case of modeswitching, it is possible
585 * to switch between two FBC valid configurations
586 * instantaneously so we do need to disable the FBC
587 * before we can modify its control registers. We also
588 * have to wait for the next vblank for that to take
589 * effect. However, since we delay enabling FBC we can
590 * assume that a vblank has passed since disabling and
591 * that we can safely alter the registers in the deferred
592 * callback.
593 *
594 * In the scenario that we go from a valid to invalid
595 * and then back to valid FBC configuration we have
596 * no strict enforcement that a vblank occurred since
597 * disabling the FBC. However, along all current pipe
598 * disabling paths we do need to wait for a vblank at
599 * some point. And we wait before enabling FBC anyway.
600 */
601 DRM_DEBUG_KMS("disabling active FBC for update\n");
602 intel_disable_fbc(dev);
603 }
604
605 intel_enable_fbc(crtc);
606 dev_priv->fbc.no_fbc_reason = FBC_OK;
607 return;
608
609 out_disable:
610 /* Multiple disables should be harmless */
611 if (intel_fbc_enabled(dev)) {
612 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
613 intel_disable_fbc(dev);
614 }
615 i915_gem_stolen_cleanup_compression(dev);
616 }
617
618 static void i915_pineview_get_mem_freq(struct drm_device *dev)
619 {
620 drm_i915_private_t *dev_priv = dev->dev_private;
621 u32 tmp;
622
623 tmp = I915_READ(CLKCFG);
624
625 switch (tmp & CLKCFG_FSB_MASK) {
626 case CLKCFG_FSB_533:
627 dev_priv->fsb_freq = 533; /* 133*4 */
628 break;
629 case CLKCFG_FSB_800:
630 dev_priv->fsb_freq = 800; /* 200*4 */
631 break;
632 case CLKCFG_FSB_667:
633 dev_priv->fsb_freq = 667; /* 167*4 */
634 break;
635 case CLKCFG_FSB_400:
636 dev_priv->fsb_freq = 400; /* 100*4 */
637 break;
638 }
639
640 switch (tmp & CLKCFG_MEM_MASK) {
641 case CLKCFG_MEM_533:
642 dev_priv->mem_freq = 533;
643 break;
644 case CLKCFG_MEM_667:
645 dev_priv->mem_freq = 667;
646 break;
647 case CLKCFG_MEM_800:
648 dev_priv->mem_freq = 800;
649 break;
650 }
651
652 /* detect pineview DDR3 setting */
653 tmp = I915_READ(CSHRDDR3CTL);
654 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
655 }
656
657 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
658 {
659 drm_i915_private_t *dev_priv = dev->dev_private;
660 u16 ddrpll, csipll;
661
662 ddrpll = I915_READ16(DDRMPLL1);
663 csipll = I915_READ16(CSIPLL0);
664
665 switch (ddrpll & 0xff) {
666 case 0xc:
667 dev_priv->mem_freq = 800;
668 break;
669 case 0x10:
670 dev_priv->mem_freq = 1066;
671 break;
672 case 0x14:
673 dev_priv->mem_freq = 1333;
674 break;
675 case 0x18:
676 dev_priv->mem_freq = 1600;
677 break;
678 default:
679 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
680 ddrpll & 0xff);
681 dev_priv->mem_freq = 0;
682 break;
683 }
684
685 dev_priv->ips.r_t = dev_priv->mem_freq;
686
687 switch (csipll & 0x3ff) {
688 case 0x00c:
689 dev_priv->fsb_freq = 3200;
690 break;
691 case 0x00e:
692 dev_priv->fsb_freq = 3733;
693 break;
694 case 0x010:
695 dev_priv->fsb_freq = 4266;
696 break;
697 case 0x012:
698 dev_priv->fsb_freq = 4800;
699 break;
700 case 0x014:
701 dev_priv->fsb_freq = 5333;
702 break;
703 case 0x016:
704 dev_priv->fsb_freq = 5866;
705 break;
706 case 0x018:
707 dev_priv->fsb_freq = 6400;
708 break;
709 default:
710 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
711 csipll & 0x3ff);
712 dev_priv->fsb_freq = 0;
713 break;
714 }
715
716 if (dev_priv->fsb_freq == 3200) {
717 dev_priv->ips.c_m = 0;
718 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
719 dev_priv->ips.c_m = 1;
720 } else {
721 dev_priv->ips.c_m = 2;
722 }
723 }
724
725 static const struct cxsr_latency cxsr_latency_table[] = {
726 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
727 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
728 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
729 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
730 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
731
732 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
733 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
734 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
735 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
736 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
737
738 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
739 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
740 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
741 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
742 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
743
744 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
745 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
746 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
747 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
748 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
749
750 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
751 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
752 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
753 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
754 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
755
756 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
757 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
758 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
759 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
760 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
761 };
762
763 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
764 int is_ddr3,
765 int fsb,
766 int mem)
767 {
768 const struct cxsr_latency *latency;
769 int i;
770
771 if (fsb == 0 || mem == 0)
772 return NULL;
773
774 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
775 latency = &cxsr_latency_table[i];
776 if (is_desktop == latency->is_desktop &&
777 is_ddr3 == latency->is_ddr3 &&
778 fsb == latency->fsb_freq && mem == latency->mem_freq)
779 return latency;
780 }
781
782 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
783
784 return NULL;
785 }
786
787 static void pineview_disable_cxsr(struct drm_device *dev)
788 {
789 struct drm_i915_private *dev_priv = dev->dev_private;
790
791 /* deactivate cxsr */
792 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
793 }
794
795 /*
796 * Latency for FIFO fetches is dependent on several factors:
797 * - memory configuration (speed, channels)
798 * - chipset
799 * - current MCH state
800 * It can be fairly high in some situations, so here we assume a fairly
801 * pessimal value. It's a tradeoff between extra memory fetches (if we
802 * set this value too high, the FIFO will fetch frequently to stay full)
803 * and power consumption (set it too low to save power and we might see
804 * FIFO underruns and display "flicker").
805 *
806 * A value of 5us seems to be a good balance; safe for very low end
807 * platforms but not overly aggressive on lower latency configs.
808 */
809 static const int latency_ns = 5000;
810
811 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
812 {
813 struct drm_i915_private *dev_priv = dev->dev_private;
814 uint32_t dsparb = I915_READ(DSPARB);
815 int size;
816
817 size = dsparb & 0x7f;
818 if (plane)
819 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
820
821 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
822 plane ? "B" : "A", size);
823
824 return size;
825 }
826
827 static int i830_get_fifo_size(struct drm_device *dev, int plane)
828 {
829 struct drm_i915_private *dev_priv = dev->dev_private;
830 uint32_t dsparb = I915_READ(DSPARB);
831 int size;
832
833 size = dsparb & 0x1ff;
834 if (plane)
835 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
836 size >>= 1; /* Convert to cachelines */
837
838 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
839 plane ? "B" : "A", size);
840
841 return size;
842 }
843
844 static int i845_get_fifo_size(struct drm_device *dev, int plane)
845 {
846 struct drm_i915_private *dev_priv = dev->dev_private;
847 uint32_t dsparb = I915_READ(DSPARB);
848 int size;
849
850 size = dsparb & 0x7f;
851 size >>= 2; /* Convert to cachelines */
852
853 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
854 plane ? "B" : "A",
855 size);
856
857 return size;
858 }
859
860 /* Pineview has different values for various configs */
861 static const struct intel_watermark_params pineview_display_wm = {
862 PINEVIEW_DISPLAY_FIFO,
863 PINEVIEW_MAX_WM,
864 PINEVIEW_DFT_WM,
865 PINEVIEW_GUARD_WM,
866 PINEVIEW_FIFO_LINE_SIZE
867 };
868 static const struct intel_watermark_params pineview_display_hplloff_wm = {
869 PINEVIEW_DISPLAY_FIFO,
870 PINEVIEW_MAX_WM,
871 PINEVIEW_DFT_HPLLOFF_WM,
872 PINEVIEW_GUARD_WM,
873 PINEVIEW_FIFO_LINE_SIZE
874 };
875 static const struct intel_watermark_params pineview_cursor_wm = {
876 PINEVIEW_CURSOR_FIFO,
877 PINEVIEW_CURSOR_MAX_WM,
878 PINEVIEW_CURSOR_DFT_WM,
879 PINEVIEW_CURSOR_GUARD_WM,
880 PINEVIEW_FIFO_LINE_SIZE,
881 };
882 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
883 PINEVIEW_CURSOR_FIFO,
884 PINEVIEW_CURSOR_MAX_WM,
885 PINEVIEW_CURSOR_DFT_WM,
886 PINEVIEW_CURSOR_GUARD_WM,
887 PINEVIEW_FIFO_LINE_SIZE
888 };
889 static const struct intel_watermark_params g4x_wm_info = {
890 G4X_FIFO_SIZE,
891 G4X_MAX_WM,
892 G4X_MAX_WM,
893 2,
894 G4X_FIFO_LINE_SIZE,
895 };
896 static const struct intel_watermark_params g4x_cursor_wm_info = {
897 I965_CURSOR_FIFO,
898 I965_CURSOR_MAX_WM,
899 I965_CURSOR_DFT_WM,
900 2,
901 G4X_FIFO_LINE_SIZE,
902 };
903 static const struct intel_watermark_params valleyview_wm_info = {
904 VALLEYVIEW_FIFO_SIZE,
905 VALLEYVIEW_MAX_WM,
906 VALLEYVIEW_MAX_WM,
907 2,
908 G4X_FIFO_LINE_SIZE,
909 };
910 static const struct intel_watermark_params valleyview_cursor_wm_info = {
911 I965_CURSOR_FIFO,
912 VALLEYVIEW_CURSOR_MAX_WM,
913 I965_CURSOR_DFT_WM,
914 2,
915 G4X_FIFO_LINE_SIZE,
916 };
917 static const struct intel_watermark_params i965_cursor_wm_info = {
918 I965_CURSOR_FIFO,
919 I965_CURSOR_MAX_WM,
920 I965_CURSOR_DFT_WM,
921 2,
922 I915_FIFO_LINE_SIZE,
923 };
924 static const struct intel_watermark_params i945_wm_info = {
925 I945_FIFO_SIZE,
926 I915_MAX_WM,
927 1,
928 2,
929 I915_FIFO_LINE_SIZE
930 };
931 static const struct intel_watermark_params i915_wm_info = {
932 I915_FIFO_SIZE,
933 I915_MAX_WM,
934 1,
935 2,
936 I915_FIFO_LINE_SIZE
937 };
938 static const struct intel_watermark_params i830_wm_info = {
939 I855GM_FIFO_SIZE,
940 I915_MAX_WM,
941 1,
942 2,
943 I830_FIFO_LINE_SIZE
944 };
945 static const struct intel_watermark_params i845_wm_info = {
946 I830_FIFO_SIZE,
947 I915_MAX_WM,
948 1,
949 2,
950 I830_FIFO_LINE_SIZE
951 };
952
953 /**
954 * intel_calculate_wm - calculate watermark level
955 * @clock_in_khz: pixel clock
956 * @wm: chip FIFO params
957 * @pixel_size: display pixel size
958 * @latency_ns: memory latency for the platform
959 *
960 * Calculate the watermark level (the level at which the display plane will
961 * start fetching from memory again). Each chip has a different display
962 * FIFO size and allocation, so the caller needs to figure that out and pass
963 * in the correct intel_watermark_params structure.
964 *
965 * As the pixel clock runs, the FIFO will be drained at a rate that depends
966 * on the pixel size. When it reaches the watermark level, it'll start
967 * fetching FIFO line sized based chunks from memory until the FIFO fills
968 * past the watermark point. If the FIFO drains completely, a FIFO underrun
969 * will occur, and a display engine hang could result.
970 */
971 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
972 const struct intel_watermark_params *wm,
973 int fifo_size,
974 int pixel_size,
975 unsigned long latency_ns)
976 {
977 long entries_required, wm_size;
978
979 /*
980 * Note: we need to make sure we don't overflow for various clock &
981 * latency values.
982 * clocks go from a few thousand to several hundred thousand.
983 * latency is usually a few thousand
984 */
985 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
986 1000;
987 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
988
989 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
990
991 wm_size = fifo_size - (entries_required + wm->guard_size);
992
993 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
994
995 /* Don't promote wm_size to unsigned... */
996 if (wm_size > (long)wm->max_wm)
997 wm_size = wm->max_wm;
998 if (wm_size <= 0)
999 wm_size = wm->default_wm;
1000 return wm_size;
1001 }
1002
1003 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1004 {
1005 struct drm_crtc *crtc, *enabled = NULL;
1006
1007 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1008 if (intel_crtc_active(crtc)) {
1009 if (enabled)
1010 return NULL;
1011 enabled = crtc;
1012 }
1013 }
1014
1015 return enabled;
1016 }
1017
1018 static void pineview_update_wm(struct drm_crtc *unused_crtc)
1019 {
1020 struct drm_device *dev = unused_crtc->dev;
1021 struct drm_i915_private *dev_priv = dev->dev_private;
1022 struct drm_crtc *crtc;
1023 const struct cxsr_latency *latency;
1024 u32 reg;
1025 unsigned long wm;
1026
1027 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1028 dev_priv->fsb_freq, dev_priv->mem_freq);
1029 if (!latency) {
1030 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1031 pineview_disable_cxsr(dev);
1032 return;
1033 }
1034
1035 crtc = single_enabled_crtc(dev);
1036 if (crtc) {
1037 const struct drm_display_mode *adjusted_mode;
1038 int pixel_size = crtc->fb->bits_per_pixel / 8;
1039 int clock;
1040
1041 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1042 clock = adjusted_mode->crtc_clock;
1043
1044 /* Display SR */
1045 wm = intel_calculate_wm(clock, &pineview_display_wm,
1046 pineview_display_wm.fifo_size,
1047 pixel_size, latency->display_sr);
1048 reg = I915_READ(DSPFW1);
1049 reg &= ~DSPFW_SR_MASK;
1050 reg |= wm << DSPFW_SR_SHIFT;
1051 I915_WRITE(DSPFW1, reg);
1052 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1053
1054 /* cursor SR */
1055 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1056 pineview_display_wm.fifo_size,
1057 pixel_size, latency->cursor_sr);
1058 reg = I915_READ(DSPFW3);
1059 reg &= ~DSPFW_CURSOR_SR_MASK;
1060 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1061 I915_WRITE(DSPFW3, reg);
1062
1063 /* Display HPLL off SR */
1064 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1065 pineview_display_hplloff_wm.fifo_size,
1066 pixel_size, latency->display_hpll_disable);
1067 reg = I915_READ(DSPFW3);
1068 reg &= ~DSPFW_HPLL_SR_MASK;
1069 reg |= wm & DSPFW_HPLL_SR_MASK;
1070 I915_WRITE(DSPFW3, reg);
1071
1072 /* cursor HPLL off SR */
1073 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1074 pineview_display_hplloff_wm.fifo_size,
1075 pixel_size, latency->cursor_hpll_disable);
1076 reg = I915_READ(DSPFW3);
1077 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1078 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1079 I915_WRITE(DSPFW3, reg);
1080 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1081
1082 /* activate cxsr */
1083 I915_WRITE(DSPFW3,
1084 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1085 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1086 } else {
1087 pineview_disable_cxsr(dev);
1088 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1089 }
1090 }
1091
1092 static bool g4x_compute_wm0(struct drm_device *dev,
1093 int plane,
1094 const struct intel_watermark_params *display,
1095 int display_latency_ns,
1096 const struct intel_watermark_params *cursor,
1097 int cursor_latency_ns,
1098 int *plane_wm,
1099 int *cursor_wm)
1100 {
1101 struct drm_crtc *crtc;
1102 const struct drm_display_mode *adjusted_mode;
1103 int htotal, hdisplay, clock, pixel_size;
1104 int line_time_us, line_count;
1105 int entries, tlb_miss;
1106
1107 crtc = intel_get_crtc_for_plane(dev, plane);
1108 if (!intel_crtc_active(crtc)) {
1109 *cursor_wm = cursor->guard_size;
1110 *plane_wm = display->guard_size;
1111 return false;
1112 }
1113
1114 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1115 clock = adjusted_mode->crtc_clock;
1116 htotal = adjusted_mode->crtc_htotal;
1117 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1118 pixel_size = crtc->fb->bits_per_pixel / 8;
1119
1120 /* Use the small buffer method to calculate plane watermark */
1121 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1122 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1123 if (tlb_miss > 0)
1124 entries += tlb_miss;
1125 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1126 *plane_wm = entries + display->guard_size;
1127 if (*plane_wm > (int)display->max_wm)
1128 *plane_wm = display->max_wm;
1129
1130 /* Use the large buffer method to calculate cursor watermark */
1131 line_time_us = ((htotal * 1000) / clock);
1132 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1133 entries = line_count * 64 * pixel_size;
1134 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1135 if (tlb_miss > 0)
1136 entries += tlb_miss;
1137 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1138 *cursor_wm = entries + cursor->guard_size;
1139 if (*cursor_wm > (int)cursor->max_wm)
1140 *cursor_wm = (int)cursor->max_wm;
1141
1142 return true;
1143 }
1144
1145 /*
1146 * Check the wm result.
1147 *
1148 * If any calculated watermark values is larger than the maximum value that
1149 * can be programmed into the associated watermark register, that watermark
1150 * must be disabled.
1151 */
1152 static bool g4x_check_srwm(struct drm_device *dev,
1153 int display_wm, int cursor_wm,
1154 const struct intel_watermark_params *display,
1155 const struct intel_watermark_params *cursor)
1156 {
1157 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1158 display_wm, cursor_wm);
1159
1160 if (display_wm > display->max_wm) {
1161 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1162 display_wm, display->max_wm);
1163 return false;
1164 }
1165
1166 if (cursor_wm > cursor->max_wm) {
1167 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1168 cursor_wm, cursor->max_wm);
1169 return false;
1170 }
1171
1172 if (!(display_wm || cursor_wm)) {
1173 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1174 return false;
1175 }
1176
1177 return true;
1178 }
1179
1180 static bool g4x_compute_srwm(struct drm_device *dev,
1181 int plane,
1182 int latency_ns,
1183 const struct intel_watermark_params *display,
1184 const struct intel_watermark_params *cursor,
1185 int *display_wm, int *cursor_wm)
1186 {
1187 struct drm_crtc *crtc;
1188 const struct drm_display_mode *adjusted_mode;
1189 int hdisplay, htotal, pixel_size, clock;
1190 unsigned long line_time_us;
1191 int line_count, line_size;
1192 int small, large;
1193 int entries;
1194
1195 if (!latency_ns) {
1196 *display_wm = *cursor_wm = 0;
1197 return false;
1198 }
1199
1200 crtc = intel_get_crtc_for_plane(dev, plane);
1201 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1202 clock = adjusted_mode->crtc_clock;
1203 htotal = adjusted_mode->crtc_htotal;
1204 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1205 pixel_size = crtc->fb->bits_per_pixel / 8;
1206
1207 line_time_us = (htotal * 1000) / clock;
1208 line_count = (latency_ns / line_time_us + 1000) / 1000;
1209 line_size = hdisplay * pixel_size;
1210
1211 /* Use the minimum of the small and large buffer method for primary */
1212 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1213 large = line_count * line_size;
1214
1215 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1216 *display_wm = entries + display->guard_size;
1217
1218 /* calculate the self-refresh watermark for display cursor */
1219 entries = line_count * pixel_size * 64;
1220 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1221 *cursor_wm = entries + cursor->guard_size;
1222
1223 return g4x_check_srwm(dev,
1224 *display_wm, *cursor_wm,
1225 display, cursor);
1226 }
1227
1228 static bool vlv_compute_drain_latency(struct drm_device *dev,
1229 int plane,
1230 int *plane_prec_mult,
1231 int *plane_dl,
1232 int *cursor_prec_mult,
1233 int *cursor_dl)
1234 {
1235 struct drm_crtc *crtc;
1236 int clock, pixel_size;
1237 int entries;
1238
1239 crtc = intel_get_crtc_for_plane(dev, plane);
1240 if (!intel_crtc_active(crtc))
1241 return false;
1242
1243 clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
1244 pixel_size = crtc->fb->bits_per_pixel / 8; /* BPP */
1245
1246 entries = (clock / 1000) * pixel_size;
1247 *plane_prec_mult = (entries > 256) ?
1248 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1249 *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1250 pixel_size);
1251
1252 entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */
1253 *cursor_prec_mult = (entries > 256) ?
1254 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1255 *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1256
1257 return true;
1258 }
1259
1260 /*
1261 * Update drain latency registers of memory arbiter
1262 *
1263 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1264 * to be programmed. Each plane has a drain latency multiplier and a drain
1265 * latency value.
1266 */
1267
1268 static void vlv_update_drain_latency(struct drm_device *dev)
1269 {
1270 struct drm_i915_private *dev_priv = dev->dev_private;
1271 int planea_prec, planea_dl, planeb_prec, planeb_dl;
1272 int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1273 int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1274 either 16 or 32 */
1275
1276 /* For plane A, Cursor A */
1277 if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1278 &cursor_prec_mult, &cursora_dl)) {
1279 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1280 DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1281 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1282 DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1283
1284 I915_WRITE(VLV_DDL1, cursora_prec |
1285 (cursora_dl << DDL_CURSORA_SHIFT) |
1286 planea_prec | planea_dl);
1287 }
1288
1289 /* For plane B, Cursor B */
1290 if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1291 &cursor_prec_mult, &cursorb_dl)) {
1292 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1293 DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1294 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1295 DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1296
1297 I915_WRITE(VLV_DDL2, cursorb_prec |
1298 (cursorb_dl << DDL_CURSORB_SHIFT) |
1299 planeb_prec | planeb_dl);
1300 }
1301 }
1302
1303 #define single_plane_enabled(mask) is_power_of_2(mask)
1304
1305 static void valleyview_update_wm(struct drm_crtc *crtc)
1306 {
1307 struct drm_device *dev = crtc->dev;
1308 static const int sr_latency_ns = 12000;
1309 struct drm_i915_private *dev_priv = dev->dev_private;
1310 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1311 int plane_sr, cursor_sr;
1312 int ignore_plane_sr, ignore_cursor_sr;
1313 unsigned int enabled = 0;
1314
1315 vlv_update_drain_latency(dev);
1316
1317 if (g4x_compute_wm0(dev, PIPE_A,
1318 &valleyview_wm_info, latency_ns,
1319 &valleyview_cursor_wm_info, latency_ns,
1320 &planea_wm, &cursora_wm))
1321 enabled |= 1 << PIPE_A;
1322
1323 if (g4x_compute_wm0(dev, PIPE_B,
1324 &valleyview_wm_info, latency_ns,
1325 &valleyview_cursor_wm_info, latency_ns,
1326 &planeb_wm, &cursorb_wm))
1327 enabled |= 1 << PIPE_B;
1328
1329 if (single_plane_enabled(enabled) &&
1330 g4x_compute_srwm(dev, ffs(enabled) - 1,
1331 sr_latency_ns,
1332 &valleyview_wm_info,
1333 &valleyview_cursor_wm_info,
1334 &plane_sr, &ignore_cursor_sr) &&
1335 g4x_compute_srwm(dev, ffs(enabled) - 1,
1336 2*sr_latency_ns,
1337 &valleyview_wm_info,
1338 &valleyview_cursor_wm_info,
1339 &ignore_plane_sr, &cursor_sr)) {
1340 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
1341 } else {
1342 I915_WRITE(FW_BLC_SELF_VLV,
1343 I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
1344 plane_sr = cursor_sr = 0;
1345 }
1346
1347 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1348 planea_wm, cursora_wm,
1349 planeb_wm, cursorb_wm,
1350 plane_sr, cursor_sr);
1351
1352 I915_WRITE(DSPFW1,
1353 (plane_sr << DSPFW_SR_SHIFT) |
1354 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1355 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1356 planea_wm);
1357 I915_WRITE(DSPFW2,
1358 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1359 (cursora_wm << DSPFW_CURSORA_SHIFT));
1360 I915_WRITE(DSPFW3,
1361 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1362 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1363 }
1364
1365 static void g4x_update_wm(struct drm_crtc *crtc)
1366 {
1367 struct drm_device *dev = crtc->dev;
1368 static const int sr_latency_ns = 12000;
1369 struct drm_i915_private *dev_priv = dev->dev_private;
1370 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1371 int plane_sr, cursor_sr;
1372 unsigned int enabled = 0;
1373
1374 if (g4x_compute_wm0(dev, PIPE_A,
1375 &g4x_wm_info, latency_ns,
1376 &g4x_cursor_wm_info, latency_ns,
1377 &planea_wm, &cursora_wm))
1378 enabled |= 1 << PIPE_A;
1379
1380 if (g4x_compute_wm0(dev, PIPE_B,
1381 &g4x_wm_info, latency_ns,
1382 &g4x_cursor_wm_info, latency_ns,
1383 &planeb_wm, &cursorb_wm))
1384 enabled |= 1 << PIPE_B;
1385
1386 if (single_plane_enabled(enabled) &&
1387 g4x_compute_srwm(dev, ffs(enabled) - 1,
1388 sr_latency_ns,
1389 &g4x_wm_info,
1390 &g4x_cursor_wm_info,
1391 &plane_sr, &cursor_sr)) {
1392 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1393 } else {
1394 I915_WRITE(FW_BLC_SELF,
1395 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
1396 plane_sr = cursor_sr = 0;
1397 }
1398
1399 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1400 planea_wm, cursora_wm,
1401 planeb_wm, cursorb_wm,
1402 plane_sr, cursor_sr);
1403
1404 I915_WRITE(DSPFW1,
1405 (plane_sr << DSPFW_SR_SHIFT) |
1406 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1407 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1408 planea_wm);
1409 I915_WRITE(DSPFW2,
1410 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1411 (cursora_wm << DSPFW_CURSORA_SHIFT));
1412 /* HPLL off in SR has some issues on G4x... disable it */
1413 I915_WRITE(DSPFW3,
1414 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1415 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1416 }
1417
1418 static void i965_update_wm(struct drm_crtc *unused_crtc)
1419 {
1420 struct drm_device *dev = unused_crtc->dev;
1421 struct drm_i915_private *dev_priv = dev->dev_private;
1422 struct drm_crtc *crtc;
1423 int srwm = 1;
1424 int cursor_sr = 16;
1425
1426 /* Calc sr entries for one plane configs */
1427 crtc = single_enabled_crtc(dev);
1428 if (crtc) {
1429 /* self-refresh has much higher latency */
1430 static const int sr_latency_ns = 12000;
1431 const struct drm_display_mode *adjusted_mode =
1432 &to_intel_crtc(crtc)->config.adjusted_mode;
1433 int clock = adjusted_mode->crtc_clock;
1434 int htotal = adjusted_mode->crtc_htotal;
1435 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1436 int pixel_size = crtc->fb->bits_per_pixel / 8;
1437 unsigned long line_time_us;
1438 int entries;
1439
1440 line_time_us = ((htotal * 1000) / clock);
1441
1442 /* Use ns/us then divide to preserve precision */
1443 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1444 pixel_size * hdisplay;
1445 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1446 srwm = I965_FIFO_SIZE - entries;
1447 if (srwm < 0)
1448 srwm = 1;
1449 srwm &= 0x1ff;
1450 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1451 entries, srwm);
1452
1453 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1454 pixel_size * 64;
1455 entries = DIV_ROUND_UP(entries,
1456 i965_cursor_wm_info.cacheline_size);
1457 cursor_sr = i965_cursor_wm_info.fifo_size -
1458 (entries + i965_cursor_wm_info.guard_size);
1459
1460 if (cursor_sr > i965_cursor_wm_info.max_wm)
1461 cursor_sr = i965_cursor_wm_info.max_wm;
1462
1463 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1464 "cursor %d\n", srwm, cursor_sr);
1465
1466 if (IS_CRESTLINE(dev))
1467 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1468 } else {
1469 /* Turn off self refresh if both pipes are enabled */
1470 if (IS_CRESTLINE(dev))
1471 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1472 & ~FW_BLC_SELF_EN);
1473 }
1474
1475 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1476 srwm);
1477
1478 /* 965 has limitations... */
1479 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1480 (8 << 16) | (8 << 8) | (8 << 0));
1481 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1482 /* update cursor SR watermark */
1483 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1484 }
1485
1486 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1487 {
1488 struct drm_device *dev = unused_crtc->dev;
1489 struct drm_i915_private *dev_priv = dev->dev_private;
1490 const struct intel_watermark_params *wm_info;
1491 uint32_t fwater_lo;
1492 uint32_t fwater_hi;
1493 int cwm, srwm = 1;
1494 int fifo_size;
1495 int planea_wm, planeb_wm;
1496 struct drm_crtc *crtc, *enabled = NULL;
1497
1498 if (IS_I945GM(dev))
1499 wm_info = &i945_wm_info;
1500 else if (!IS_GEN2(dev))
1501 wm_info = &i915_wm_info;
1502 else
1503 wm_info = &i830_wm_info;
1504
1505 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1506 crtc = intel_get_crtc_for_plane(dev, 0);
1507 if (intel_crtc_active(crtc)) {
1508 const struct drm_display_mode *adjusted_mode;
1509 int cpp = crtc->fb->bits_per_pixel / 8;
1510 if (IS_GEN2(dev))
1511 cpp = 4;
1512
1513 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1514 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1515 wm_info, fifo_size, cpp,
1516 latency_ns);
1517 enabled = crtc;
1518 } else
1519 planea_wm = fifo_size - wm_info->guard_size;
1520
1521 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1522 crtc = intel_get_crtc_for_plane(dev, 1);
1523 if (intel_crtc_active(crtc)) {
1524 const struct drm_display_mode *adjusted_mode;
1525 int cpp = crtc->fb->bits_per_pixel / 8;
1526 if (IS_GEN2(dev))
1527 cpp = 4;
1528
1529 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1530 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1531 wm_info, fifo_size, cpp,
1532 latency_ns);
1533 if (enabled == NULL)
1534 enabled = crtc;
1535 else
1536 enabled = NULL;
1537 } else
1538 planeb_wm = fifo_size - wm_info->guard_size;
1539
1540 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1541
1542 /*
1543 * Overlay gets an aggressive default since video jitter is bad.
1544 */
1545 cwm = 2;
1546
1547 /* Play safe and disable self-refresh before adjusting watermarks. */
1548 if (IS_I945G(dev) || IS_I945GM(dev))
1549 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1550 else if (IS_I915GM(dev))
1551 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_SELF_EN));
1552
1553 /* Calc sr entries for one plane configs */
1554 if (HAS_FW_BLC(dev) && enabled) {
1555 /* self-refresh has much higher latency */
1556 static const int sr_latency_ns = 6000;
1557 const struct drm_display_mode *adjusted_mode =
1558 &to_intel_crtc(enabled)->config.adjusted_mode;
1559 int clock = adjusted_mode->crtc_clock;
1560 int htotal = adjusted_mode->crtc_htotal;
1561 int hdisplay = to_intel_crtc(enabled)->config.pipe_src_w;
1562 int pixel_size = enabled->fb->bits_per_pixel / 8;
1563 unsigned long line_time_us;
1564 int entries;
1565
1566 line_time_us = (htotal * 1000) / clock;
1567
1568 /* Use ns/us then divide to preserve precision */
1569 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1570 pixel_size * hdisplay;
1571 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1572 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1573 srwm = wm_info->fifo_size - entries;
1574 if (srwm < 0)
1575 srwm = 1;
1576
1577 if (IS_I945G(dev) || IS_I945GM(dev))
1578 I915_WRITE(FW_BLC_SELF,
1579 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1580 else if (IS_I915GM(dev))
1581 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1582 }
1583
1584 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1585 planea_wm, planeb_wm, cwm, srwm);
1586
1587 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1588 fwater_hi = (cwm & 0x1f);
1589
1590 /* Set request length to 8 cachelines per fetch */
1591 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1592 fwater_hi = fwater_hi | (1 << 8);
1593
1594 I915_WRITE(FW_BLC, fwater_lo);
1595 I915_WRITE(FW_BLC2, fwater_hi);
1596
1597 if (HAS_FW_BLC(dev)) {
1598 if (enabled) {
1599 if (IS_I945G(dev) || IS_I945GM(dev))
1600 I915_WRITE(FW_BLC_SELF,
1601 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1602 else if (IS_I915GM(dev))
1603 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_SELF_EN));
1604 DRM_DEBUG_KMS("memory self refresh enabled\n");
1605 } else
1606 DRM_DEBUG_KMS("memory self refresh disabled\n");
1607 }
1608 }
1609
1610 static void i845_update_wm(struct drm_crtc *unused_crtc)
1611 {
1612 struct drm_device *dev = unused_crtc->dev;
1613 struct drm_i915_private *dev_priv = dev->dev_private;
1614 struct drm_crtc *crtc;
1615 const struct drm_display_mode *adjusted_mode;
1616 uint32_t fwater_lo;
1617 int planea_wm;
1618
1619 crtc = single_enabled_crtc(dev);
1620 if (crtc == NULL)
1621 return;
1622
1623 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1624 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1625 &i845_wm_info,
1626 dev_priv->display.get_fifo_size(dev, 0),
1627 4, latency_ns);
1628 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1629 fwater_lo |= (3<<8) | planea_wm;
1630
1631 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1632
1633 I915_WRITE(FW_BLC, fwater_lo);
1634 }
1635
1636 static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
1637 struct drm_crtc *crtc)
1638 {
1639 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1640 uint32_t pixel_rate;
1641
1642 pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock;
1643
1644 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1645 * adjust the pixel_rate here. */
1646
1647 if (intel_crtc->config.pch_pfit.enabled) {
1648 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1649 uint32_t pfit_size = intel_crtc->config.pch_pfit.size;
1650
1651 pipe_w = intel_crtc->config.pipe_src_w;
1652 pipe_h = intel_crtc->config.pipe_src_h;
1653 pfit_w = (pfit_size >> 16) & 0xFFFF;
1654 pfit_h = pfit_size & 0xFFFF;
1655 if (pipe_w < pfit_w)
1656 pipe_w = pfit_w;
1657 if (pipe_h < pfit_h)
1658 pipe_h = pfit_h;
1659
1660 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1661 pfit_w * pfit_h);
1662 }
1663
1664 return pixel_rate;
1665 }
1666
1667 /* latency must be in 0.1us units. */
1668 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
1669 uint32_t latency)
1670 {
1671 uint64_t ret;
1672
1673 if (WARN(latency == 0, "Latency value missing\n"))
1674 return UINT_MAX;
1675
1676 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1677 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1678
1679 return ret;
1680 }
1681
1682 /* latency must be in 0.1us units. */
1683 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1684 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1685 uint32_t latency)
1686 {
1687 uint32_t ret;
1688
1689 if (WARN(latency == 0, "Latency value missing\n"))
1690 return UINT_MAX;
1691
1692 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1693 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1694 ret = DIV_ROUND_UP(ret, 64) + 2;
1695 return ret;
1696 }
1697
1698 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1699 uint8_t bytes_per_pixel)
1700 {
1701 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1702 }
1703
1704 struct ilk_pipe_wm_parameters {
1705 bool active;
1706 uint32_t pipe_htotal;
1707 uint32_t pixel_rate;
1708 struct intel_plane_wm_parameters pri;
1709 struct intel_plane_wm_parameters spr;
1710 struct intel_plane_wm_parameters cur;
1711 };
1712
1713 struct ilk_wm_maximums {
1714 uint16_t pri;
1715 uint16_t spr;
1716 uint16_t cur;
1717 uint16_t fbc;
1718 };
1719
1720 /* used in computing the new watermarks state */
1721 struct intel_wm_config {
1722 unsigned int num_pipes_active;
1723 bool sprites_enabled;
1724 bool sprites_scaled;
1725 };
1726
1727 /*
1728 * For both WM_PIPE and WM_LP.
1729 * mem_value must be in 0.1us units.
1730 */
1731 static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params,
1732 uint32_t mem_value,
1733 bool is_lp)
1734 {
1735 uint32_t method1, method2;
1736
1737 if (!params->active || !params->pri.enabled)
1738 return 0;
1739
1740 method1 = ilk_wm_method1(params->pixel_rate,
1741 params->pri.bytes_per_pixel,
1742 mem_value);
1743
1744 if (!is_lp)
1745 return method1;
1746
1747 method2 = ilk_wm_method2(params->pixel_rate,
1748 params->pipe_htotal,
1749 params->pri.horiz_pixels,
1750 params->pri.bytes_per_pixel,
1751 mem_value);
1752
1753 return min(method1, method2);
1754 }
1755
1756 /*
1757 * For both WM_PIPE and WM_LP.
1758 * mem_value must be in 0.1us units.
1759 */
1760 static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params,
1761 uint32_t mem_value)
1762 {
1763 uint32_t method1, method2;
1764
1765 if (!params->active || !params->spr.enabled)
1766 return 0;
1767
1768 method1 = ilk_wm_method1(params->pixel_rate,
1769 params->spr.bytes_per_pixel,
1770 mem_value);
1771 method2 = ilk_wm_method2(params->pixel_rate,
1772 params->pipe_htotal,
1773 params->spr.horiz_pixels,
1774 params->spr.bytes_per_pixel,
1775 mem_value);
1776 return min(method1, method2);
1777 }
1778
1779 /*
1780 * For both WM_PIPE and WM_LP.
1781 * mem_value must be in 0.1us units.
1782 */
1783 static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params,
1784 uint32_t mem_value)
1785 {
1786 if (!params->active || !params->cur.enabled)
1787 return 0;
1788
1789 return ilk_wm_method2(params->pixel_rate,
1790 params->pipe_htotal,
1791 params->cur.horiz_pixels,
1792 params->cur.bytes_per_pixel,
1793 mem_value);
1794 }
1795
1796 /* Only for WM_LP. */
1797 static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params,
1798 uint32_t pri_val)
1799 {
1800 if (!params->active || !params->pri.enabled)
1801 return 0;
1802
1803 return ilk_wm_fbc(pri_val,
1804 params->pri.horiz_pixels,
1805 params->pri.bytes_per_pixel);
1806 }
1807
1808 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1809 {
1810 if (INTEL_INFO(dev)->gen >= 8)
1811 return 3072;
1812 else if (INTEL_INFO(dev)->gen >= 7)
1813 return 768;
1814 else
1815 return 512;
1816 }
1817
1818 /* Calculate the maximum primary/sprite plane watermark */
1819 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1820 int level,
1821 const struct intel_wm_config *config,
1822 enum intel_ddb_partitioning ddb_partitioning,
1823 bool is_sprite)
1824 {
1825 unsigned int fifo_size = ilk_display_fifo_size(dev);
1826 unsigned int max;
1827
1828 /* if sprites aren't enabled, sprites get nothing */
1829 if (is_sprite && !config->sprites_enabled)
1830 return 0;
1831
1832 /* HSW allows LP1+ watermarks even with multiple pipes */
1833 if (level == 0 || config->num_pipes_active > 1) {
1834 fifo_size /= INTEL_INFO(dev)->num_pipes;
1835
1836 /*
1837 * For some reason the non self refresh
1838 * FIFO size is only half of the self
1839 * refresh FIFO size on ILK/SNB.
1840 */
1841 if (INTEL_INFO(dev)->gen <= 6)
1842 fifo_size /= 2;
1843 }
1844
1845 if (config->sprites_enabled) {
1846 /* level 0 is always calculated with 1:1 split */
1847 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1848 if (is_sprite)
1849 fifo_size *= 5;
1850 fifo_size /= 6;
1851 } else {
1852 fifo_size /= 2;
1853 }
1854 }
1855
1856 /* clamp to max that the registers can hold */
1857 if (INTEL_INFO(dev)->gen >= 8)
1858 max = level == 0 ? 255 : 2047;
1859 else if (INTEL_INFO(dev)->gen >= 7)
1860 /* IVB/HSW primary/sprite plane watermarks */
1861 max = level == 0 ? 127 : 1023;
1862 else if (!is_sprite)
1863 /* ILK/SNB primary plane watermarks */
1864 max = level == 0 ? 127 : 511;
1865 else
1866 /* ILK/SNB sprite plane watermarks */
1867 max = level == 0 ? 63 : 255;
1868
1869 return min(fifo_size, max);
1870 }
1871
1872 /* Calculate the maximum cursor plane watermark */
1873 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
1874 int level,
1875 const struct intel_wm_config *config)
1876 {
1877 /* HSW LP1+ watermarks w/ multiple pipes */
1878 if (level > 0 && config->num_pipes_active > 1)
1879 return 64;
1880
1881 /* otherwise just report max that registers can hold */
1882 if (INTEL_INFO(dev)->gen >= 7)
1883 return level == 0 ? 63 : 255;
1884 else
1885 return level == 0 ? 31 : 63;
1886 }
1887
1888 /* Calculate the maximum FBC watermark */
1889 static unsigned int ilk_fbc_wm_max(struct drm_device *dev)
1890 {
1891 /* max that registers can hold */
1892 if (INTEL_INFO(dev)->gen >= 8)
1893 return 31;
1894 else
1895 return 15;
1896 }
1897
1898 static void ilk_compute_wm_maximums(struct drm_device *dev,
1899 int level,
1900 const struct intel_wm_config *config,
1901 enum intel_ddb_partitioning ddb_partitioning,
1902 struct ilk_wm_maximums *max)
1903 {
1904 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1905 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1906 max->cur = ilk_cursor_wm_max(dev, level, config);
1907 max->fbc = ilk_fbc_wm_max(dev);
1908 }
1909
1910 static bool ilk_validate_wm_level(int level,
1911 const struct ilk_wm_maximums *max,
1912 struct intel_wm_level *result)
1913 {
1914 bool ret;
1915
1916 /* already determined to be invalid? */
1917 if (!result->enable)
1918 return false;
1919
1920 result->enable = result->pri_val <= max->pri &&
1921 result->spr_val <= max->spr &&
1922 result->cur_val <= max->cur;
1923
1924 ret = result->enable;
1925
1926 /*
1927 * HACK until we can pre-compute everything,
1928 * and thus fail gracefully if LP0 watermarks
1929 * are exceeded...
1930 */
1931 if (level == 0 && !result->enable) {
1932 if (result->pri_val > max->pri)
1933 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1934 level, result->pri_val, max->pri);
1935 if (result->spr_val > max->spr)
1936 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1937 level, result->spr_val, max->spr);
1938 if (result->cur_val > max->cur)
1939 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1940 level, result->cur_val, max->cur);
1941
1942 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
1943 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
1944 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
1945 result->enable = true;
1946 }
1947
1948 return ret;
1949 }
1950
1951 static void ilk_compute_wm_level(struct drm_i915_private *dev_priv,
1952 int level,
1953 const struct ilk_pipe_wm_parameters *p,
1954 struct intel_wm_level *result)
1955 {
1956 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
1957 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
1958 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
1959
1960 /* WM1+ latency values stored in 0.5us units */
1961 if (level > 0) {
1962 pri_latency *= 5;
1963 spr_latency *= 5;
1964 cur_latency *= 5;
1965 }
1966
1967 result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
1968 result->spr_val = ilk_compute_spr_wm(p, spr_latency);
1969 result->cur_val = ilk_compute_cur_wm(p, cur_latency);
1970 result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
1971 result->enable = true;
1972 }
1973
1974 static uint32_t
1975 hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
1976 {
1977 struct drm_i915_private *dev_priv = dev->dev_private;
1978 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1979 struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
1980 u32 linetime, ips_linetime;
1981
1982 if (!intel_crtc_active(crtc))
1983 return 0;
1984
1985 /* The WM are computed with base on how long it takes to fill a single
1986 * row at the given clock rate, multiplied by 8.
1987 * */
1988 linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
1989 mode->crtc_clock);
1990 ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
1991 intel_ddi_get_cdclk_freq(dev_priv));
1992
1993 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
1994 PIPE_WM_LINETIME_TIME(linetime);
1995 }
1996
1997 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5])
1998 {
1999 struct drm_i915_private *dev_priv = dev->dev_private;
2000
2001 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2002 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2003
2004 wm[0] = (sskpd >> 56) & 0xFF;
2005 if (wm[0] == 0)
2006 wm[0] = sskpd & 0xF;
2007 wm[1] = (sskpd >> 4) & 0xFF;
2008 wm[2] = (sskpd >> 12) & 0xFF;
2009 wm[3] = (sskpd >> 20) & 0x1FF;
2010 wm[4] = (sskpd >> 32) & 0x1FF;
2011 } else if (INTEL_INFO(dev)->gen >= 6) {
2012 uint32_t sskpd = I915_READ(MCH_SSKPD);
2013
2014 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2015 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2016 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2017 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2018 } else if (INTEL_INFO(dev)->gen >= 5) {
2019 uint32_t mltr = I915_READ(MLTR_ILK);
2020
2021 /* ILK primary LP0 latency is 700 ns */
2022 wm[0] = 7;
2023 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2024 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2025 }
2026 }
2027
2028 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2029 {
2030 /* ILK sprite LP0 latency is 1300 ns */
2031 if (INTEL_INFO(dev)->gen == 5)
2032 wm[0] = 13;
2033 }
2034
2035 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2036 {
2037 /* ILK cursor LP0 latency is 1300 ns */
2038 if (INTEL_INFO(dev)->gen == 5)
2039 wm[0] = 13;
2040
2041 /* WaDoubleCursorLP3Latency:ivb */
2042 if (IS_IVYBRIDGE(dev))
2043 wm[3] *= 2;
2044 }
2045
2046 static int ilk_wm_max_level(const struct drm_device *dev)
2047 {
2048 /* how many WM levels are we expecting */
2049 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2050 return 4;
2051 else if (INTEL_INFO(dev)->gen >= 6)
2052 return 3;
2053 else
2054 return 2;
2055 }
2056
2057 static void intel_print_wm_latency(struct drm_device *dev,
2058 const char *name,
2059 const uint16_t wm[5])
2060 {
2061 int level, max_level = ilk_wm_max_level(dev);
2062
2063 for (level = 0; level <= max_level; level++) {
2064 unsigned int latency = wm[level];
2065
2066 if (latency == 0) {
2067 DRM_ERROR("%s WM%d latency not provided\n",
2068 name, level);
2069 continue;
2070 }
2071
2072 /* WM1+ latency values in 0.5us units */
2073 if (level > 0)
2074 latency *= 5;
2075
2076 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2077 name, level, wm[level],
2078 latency / 10, latency % 10);
2079 }
2080 }
2081
2082 static void intel_setup_wm_latency(struct drm_device *dev)
2083 {
2084 struct drm_i915_private *dev_priv = dev->dev_private;
2085
2086 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2087
2088 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2089 sizeof(dev_priv->wm.pri_latency));
2090 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2091 sizeof(dev_priv->wm.pri_latency));
2092
2093 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2094 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2095
2096 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2097 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2098 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2099 }
2100
2101 static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
2102 struct ilk_pipe_wm_parameters *p,
2103 struct intel_wm_config *config)
2104 {
2105 struct drm_device *dev = crtc->dev;
2106 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2107 enum pipe pipe = intel_crtc->pipe;
2108 struct drm_plane *plane;
2109
2110 p->active = intel_crtc_active(crtc);
2111 if (p->active) {
2112 p->pipe_htotal = intel_crtc->config.adjusted_mode.crtc_htotal;
2113 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
2114 p->pri.bytes_per_pixel = crtc->fb->bits_per_pixel / 8;
2115 p->cur.bytes_per_pixel = 4;
2116 p->pri.horiz_pixels = intel_crtc->config.pipe_src_w;
2117 p->cur.horiz_pixels = 64;
2118 /* TODO: for now, assume primary and cursor planes are always enabled. */
2119 p->pri.enabled = true;
2120 p->cur.enabled = true;
2121 }
2122
2123 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
2124 config->num_pipes_active += intel_crtc_active(crtc);
2125
2126 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2127 struct intel_plane *intel_plane = to_intel_plane(plane);
2128
2129 if (intel_plane->pipe == pipe)
2130 p->spr = intel_plane->wm;
2131
2132 config->sprites_enabled |= intel_plane->wm.enabled;
2133 config->sprites_scaled |= intel_plane->wm.scaled;
2134 }
2135 }
2136
2137 /* Compute new watermarks for the pipe */
2138 static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
2139 const struct ilk_pipe_wm_parameters *params,
2140 struct intel_pipe_wm *pipe_wm)
2141 {
2142 struct drm_device *dev = crtc->dev;
2143 struct drm_i915_private *dev_priv = dev->dev_private;
2144 int level, max_level = ilk_wm_max_level(dev);
2145 /* LP0 watermark maximums depend on this pipe alone */
2146 struct intel_wm_config config = {
2147 .num_pipes_active = 1,
2148 .sprites_enabled = params->spr.enabled,
2149 .sprites_scaled = params->spr.scaled,
2150 };
2151 struct ilk_wm_maximums max;
2152
2153 /* LP0 watermarks always use 1/2 DDB partitioning */
2154 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2155
2156 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2157 if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled)
2158 max_level = 1;
2159
2160 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2161 if (params->spr.scaled)
2162 max_level = 0;
2163
2164 for (level = 0; level <= max_level; level++)
2165 ilk_compute_wm_level(dev_priv, level, params,
2166 &pipe_wm->wm[level]);
2167
2168 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2169 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
2170
2171 /* At least LP0 must be valid */
2172 return ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]);
2173 }
2174
2175 /*
2176 * Merge the watermarks from all active pipes for a specific level.
2177 */
2178 static void ilk_merge_wm_level(struct drm_device *dev,
2179 int level,
2180 struct intel_wm_level *ret_wm)
2181 {
2182 const struct intel_crtc *intel_crtc;
2183
2184 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) {
2185 const struct intel_wm_level *wm =
2186 &intel_crtc->wm.active.wm[level];
2187
2188 if (!wm->enable)
2189 return;
2190
2191 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2192 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2193 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2194 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2195 }
2196
2197 ret_wm->enable = true;
2198 }
2199
2200 /*
2201 * Merge all low power watermarks for all active pipes.
2202 */
2203 static void ilk_wm_merge(struct drm_device *dev,
2204 const struct intel_wm_config *config,
2205 const struct ilk_wm_maximums *max,
2206 struct intel_pipe_wm *merged)
2207 {
2208 int level, max_level = ilk_wm_max_level(dev);
2209
2210 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2211 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2212 config->num_pipes_active > 1)
2213 return;
2214
2215 /* ILK: FBC WM must be disabled always */
2216 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
2217
2218 /* merge each WM1+ level */
2219 for (level = 1; level <= max_level; level++) {
2220 struct intel_wm_level *wm = &merged->wm[level];
2221
2222 ilk_merge_wm_level(dev, level, wm);
2223
2224 if (!ilk_validate_wm_level(level, max, wm))
2225 break;
2226
2227 /*
2228 * The spec says it is preferred to disable
2229 * FBC WMs instead of disabling a WM level.
2230 */
2231 if (wm->fbc_val > max->fbc) {
2232 merged->fbc_wm_enabled = false;
2233 wm->fbc_val = 0;
2234 }
2235 }
2236
2237 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2238 /*
2239 * FIXME this is racy. FBC might get enabled later.
2240 * What we should check here is whether FBC can be
2241 * enabled sometime later.
2242 */
2243 if (IS_GEN5(dev) && !merged->fbc_wm_enabled && intel_fbc_enabled(dev)) {
2244 for (level = 2; level <= max_level; level++) {
2245 struct intel_wm_level *wm = &merged->wm[level];
2246
2247 wm->enable = false;
2248 }
2249 }
2250 }
2251
2252 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2253 {
2254 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2255 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2256 }
2257
2258 /* The value we need to program into the WM_LPx latency field */
2259 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2260 {
2261 struct drm_i915_private *dev_priv = dev->dev_private;
2262
2263 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2264 return 2 * level;
2265 else
2266 return dev_priv->wm.pri_latency[level];
2267 }
2268
2269 static void ilk_compute_wm_results(struct drm_device *dev,
2270 const struct intel_pipe_wm *merged,
2271 enum intel_ddb_partitioning partitioning,
2272 struct ilk_wm_values *results)
2273 {
2274 struct intel_crtc *intel_crtc;
2275 int level, wm_lp;
2276
2277 results->enable_fbc_wm = merged->fbc_wm_enabled;
2278 results->partitioning = partitioning;
2279
2280 /* LP1+ register values */
2281 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2282 const struct intel_wm_level *r;
2283
2284 level = ilk_wm_lp_to_level(wm_lp, merged);
2285
2286 r = &merged->wm[level];
2287 if (!r->enable)
2288 break;
2289
2290 results->wm_lp[wm_lp - 1] = WM3_LP_EN |
2291 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2292 (r->pri_val << WM1_LP_SR_SHIFT) |
2293 r->cur_val;
2294
2295 if (INTEL_INFO(dev)->gen >= 8)
2296 results->wm_lp[wm_lp - 1] |=
2297 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2298 else
2299 results->wm_lp[wm_lp - 1] |=
2300 r->fbc_val << WM1_LP_FBC_SHIFT;
2301
2302 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2303 WARN_ON(wm_lp != 1);
2304 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2305 } else
2306 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2307 }
2308
2309 /* LP0 register values */
2310 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) {
2311 enum pipe pipe = intel_crtc->pipe;
2312 const struct intel_wm_level *r =
2313 &intel_crtc->wm.active.wm[0];
2314
2315 if (WARN_ON(!r->enable))
2316 continue;
2317
2318 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
2319
2320 results->wm_pipe[pipe] =
2321 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2322 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2323 r->cur_val;
2324 }
2325 }
2326
2327 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2328 * case both are at the same level. Prefer r1 in case they're the same. */
2329 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2330 struct intel_pipe_wm *r1,
2331 struct intel_pipe_wm *r2)
2332 {
2333 int level, max_level = ilk_wm_max_level(dev);
2334 int level1 = 0, level2 = 0;
2335
2336 for (level = 1; level <= max_level; level++) {
2337 if (r1->wm[level].enable)
2338 level1 = level;
2339 if (r2->wm[level].enable)
2340 level2 = level;
2341 }
2342
2343 if (level1 == level2) {
2344 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2345 return r2;
2346 else
2347 return r1;
2348 } else if (level1 > level2) {
2349 return r1;
2350 } else {
2351 return r2;
2352 }
2353 }
2354
2355 /* dirty bits used to track which watermarks need changes */
2356 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2357 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2358 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2359 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2360 #define WM_DIRTY_FBC (1 << 24)
2361 #define WM_DIRTY_DDB (1 << 25)
2362
2363 static unsigned int ilk_compute_wm_dirty(struct drm_device *dev,
2364 const struct ilk_wm_values *old,
2365 const struct ilk_wm_values *new)
2366 {
2367 unsigned int dirty = 0;
2368 enum pipe pipe;
2369 int wm_lp;
2370
2371 for_each_pipe(pipe) {
2372 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2373 dirty |= WM_DIRTY_LINETIME(pipe);
2374 /* Must disable LP1+ watermarks too */
2375 dirty |= WM_DIRTY_LP_ALL;
2376 }
2377
2378 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2379 dirty |= WM_DIRTY_PIPE(pipe);
2380 /* Must disable LP1+ watermarks too */
2381 dirty |= WM_DIRTY_LP_ALL;
2382 }
2383 }
2384
2385 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2386 dirty |= WM_DIRTY_FBC;
2387 /* Must disable LP1+ watermarks too */
2388 dirty |= WM_DIRTY_LP_ALL;
2389 }
2390
2391 if (old->partitioning != new->partitioning) {
2392 dirty |= WM_DIRTY_DDB;
2393 /* Must disable LP1+ watermarks too */
2394 dirty |= WM_DIRTY_LP_ALL;
2395 }
2396
2397 /* LP1+ watermarks already deemed dirty, no need to continue */
2398 if (dirty & WM_DIRTY_LP_ALL)
2399 return dirty;
2400
2401 /* Find the lowest numbered LP1+ watermark in need of an update... */
2402 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2403 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2404 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2405 break;
2406 }
2407
2408 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2409 for (; wm_lp <= 3; wm_lp++)
2410 dirty |= WM_DIRTY_LP(wm_lp);
2411
2412 return dirty;
2413 }
2414
2415 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2416 unsigned int dirty)
2417 {
2418 struct ilk_wm_values *previous = &dev_priv->wm.hw;
2419 bool changed = false;
2420
2421 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2422 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2423 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2424 changed = true;
2425 }
2426 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2427 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2428 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2429 changed = true;
2430 }
2431 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2432 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2433 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2434 changed = true;
2435 }
2436
2437 /*
2438 * Don't touch WM1S_LP_EN here.
2439 * Doing so could cause underruns.
2440 */
2441
2442 return changed;
2443 }
2444
2445 /*
2446 * The spec says we shouldn't write when we don't need, because every write
2447 * causes WMs to be re-evaluated, expending some power.
2448 */
2449 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2450 struct ilk_wm_values *results)
2451 {
2452 struct drm_device *dev = dev_priv->dev;
2453 struct ilk_wm_values *previous = &dev_priv->wm.hw;
2454 unsigned int dirty;
2455 uint32_t val;
2456
2457 dirty = ilk_compute_wm_dirty(dev, previous, results);
2458 if (!dirty)
2459 return;
2460
2461 _ilk_disable_lp_wm(dev_priv, dirty);
2462
2463 if (dirty & WM_DIRTY_PIPE(PIPE_A))
2464 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2465 if (dirty & WM_DIRTY_PIPE(PIPE_B))
2466 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2467 if (dirty & WM_DIRTY_PIPE(PIPE_C))
2468 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2469
2470 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2471 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2472 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2473 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2474 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2475 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2476
2477 if (dirty & WM_DIRTY_DDB) {
2478 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2479 val = I915_READ(WM_MISC);
2480 if (results->partitioning == INTEL_DDB_PART_1_2)
2481 val &= ~WM_MISC_DATA_PARTITION_5_6;
2482 else
2483 val |= WM_MISC_DATA_PARTITION_5_6;
2484 I915_WRITE(WM_MISC, val);
2485 } else {
2486 val = I915_READ(DISP_ARB_CTL2);
2487 if (results->partitioning == INTEL_DDB_PART_1_2)
2488 val &= ~DISP_DATA_PARTITION_5_6;
2489 else
2490 val |= DISP_DATA_PARTITION_5_6;
2491 I915_WRITE(DISP_ARB_CTL2, val);
2492 }
2493 }
2494
2495 if (dirty & WM_DIRTY_FBC) {
2496 val = I915_READ(DISP_ARB_CTL);
2497 if (results->enable_fbc_wm)
2498 val &= ~DISP_FBC_WM_DIS;
2499 else
2500 val |= DISP_FBC_WM_DIS;
2501 I915_WRITE(DISP_ARB_CTL, val);
2502 }
2503
2504 if (dirty & WM_DIRTY_LP(1) &&
2505 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2506 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2507
2508 if (INTEL_INFO(dev)->gen >= 7) {
2509 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2510 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2511 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2512 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2513 }
2514
2515 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2516 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2517 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2518 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2519 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2520 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2521
2522 dev_priv->wm.hw = *results;
2523 }
2524
2525 static bool ilk_disable_lp_wm(struct drm_device *dev)
2526 {
2527 struct drm_i915_private *dev_priv = dev->dev_private;
2528
2529 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2530 }
2531
2532 static void ilk_update_wm(struct drm_crtc *crtc)
2533 {
2534 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2535 struct drm_device *dev = crtc->dev;
2536 struct drm_i915_private *dev_priv = dev->dev_private;
2537 struct ilk_wm_maximums max;
2538 struct ilk_pipe_wm_parameters params = {};
2539 struct ilk_wm_values results = {};
2540 enum intel_ddb_partitioning partitioning;
2541 struct intel_pipe_wm pipe_wm = {};
2542 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
2543 struct intel_wm_config config = {};
2544
2545 ilk_compute_wm_parameters(crtc, &params, &config);
2546
2547 intel_compute_pipe_wm(crtc, &params, &pipe_wm);
2548
2549 if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
2550 return;
2551
2552 intel_crtc->wm.active = pipe_wm;
2553
2554 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
2555 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
2556
2557 /* 5/6 split only in single pipe config on IVB+ */
2558 if (INTEL_INFO(dev)->gen >= 7 &&
2559 config.num_pipes_active == 1 && config.sprites_enabled) {
2560 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
2561 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
2562
2563 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
2564 } else {
2565 best_lp_wm = &lp_wm_1_2;
2566 }
2567
2568 partitioning = (best_lp_wm == &lp_wm_1_2) ?
2569 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
2570
2571 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
2572
2573 ilk_write_wm_values(dev_priv, &results);
2574 }
2575
2576 static void ilk_update_sprite_wm(struct drm_plane *plane,
2577 struct drm_crtc *crtc,
2578 uint32_t sprite_width, int pixel_size,
2579 bool enabled, bool scaled)
2580 {
2581 struct drm_device *dev = plane->dev;
2582 struct intel_plane *intel_plane = to_intel_plane(plane);
2583
2584 intel_plane->wm.enabled = enabled;
2585 intel_plane->wm.scaled = scaled;
2586 intel_plane->wm.horiz_pixels = sprite_width;
2587 intel_plane->wm.bytes_per_pixel = pixel_size;
2588
2589 /*
2590 * IVB workaround: must disable low power watermarks for at least
2591 * one frame before enabling scaling. LP watermarks can be re-enabled
2592 * when scaling is disabled.
2593 *
2594 * WaCxSRDisabledForSpriteScaling:ivb
2595 */
2596 if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev))
2597 intel_wait_for_vblank(dev, intel_plane->pipe);
2598
2599 ilk_update_wm(crtc);
2600 }
2601
2602 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
2603 {
2604 struct drm_device *dev = crtc->dev;
2605 struct drm_i915_private *dev_priv = dev->dev_private;
2606 struct ilk_wm_values *hw = &dev_priv->wm.hw;
2607 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2608 struct intel_pipe_wm *active = &intel_crtc->wm.active;
2609 enum pipe pipe = intel_crtc->pipe;
2610 static const unsigned int wm0_pipe_reg[] = {
2611 [PIPE_A] = WM0_PIPEA_ILK,
2612 [PIPE_B] = WM0_PIPEB_ILK,
2613 [PIPE_C] = WM0_PIPEC_IVB,
2614 };
2615
2616 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
2617 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2618 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
2619
2620 if (intel_crtc_active(crtc)) {
2621 u32 tmp = hw->wm_pipe[pipe];
2622
2623 /*
2624 * For active pipes LP0 watermark is marked as
2625 * enabled, and LP1+ watermaks as disabled since
2626 * we can't really reverse compute them in case
2627 * multiple pipes are active.
2628 */
2629 active->wm[0].enable = true;
2630 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
2631 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
2632 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
2633 active->linetime = hw->wm_linetime[pipe];
2634 } else {
2635 int level, max_level = ilk_wm_max_level(dev);
2636
2637 /*
2638 * For inactive pipes, all watermark levels
2639 * should be marked as enabled but zeroed,
2640 * which is what we'd compute them to.
2641 */
2642 for (level = 0; level <= max_level; level++)
2643 active->wm[level].enable = true;
2644 }
2645 }
2646
2647 void ilk_wm_get_hw_state(struct drm_device *dev)
2648 {
2649 struct drm_i915_private *dev_priv = dev->dev_private;
2650 struct ilk_wm_values *hw = &dev_priv->wm.hw;
2651 struct drm_crtc *crtc;
2652
2653 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
2654 ilk_pipe_wm_get_hw_state(crtc);
2655
2656 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
2657 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
2658 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
2659
2660 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
2661 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
2662 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
2663
2664 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2665 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
2666 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
2667 else if (IS_IVYBRIDGE(dev))
2668 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
2669 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
2670
2671 hw->enable_fbc_wm =
2672 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
2673 }
2674
2675 /**
2676 * intel_update_watermarks - update FIFO watermark values based on current modes
2677 *
2678 * Calculate watermark values for the various WM regs based on current mode
2679 * and plane configuration.
2680 *
2681 * There are several cases to deal with here:
2682 * - normal (i.e. non-self-refresh)
2683 * - self-refresh (SR) mode
2684 * - lines are large relative to FIFO size (buffer can hold up to 2)
2685 * - lines are small relative to FIFO size (buffer can hold more than 2
2686 * lines), so need to account for TLB latency
2687 *
2688 * The normal calculation is:
2689 * watermark = dotclock * bytes per pixel * latency
2690 * where latency is platform & configuration dependent (we assume pessimal
2691 * values here).
2692 *
2693 * The SR calculation is:
2694 * watermark = (trunc(latency/line time)+1) * surface width *
2695 * bytes per pixel
2696 * where
2697 * line time = htotal / dotclock
2698 * surface width = hdisplay for normal plane and 64 for cursor
2699 * and latency is assumed to be high, as above.
2700 *
2701 * The final value programmed to the register should always be rounded up,
2702 * and include an extra 2 entries to account for clock crossings.
2703 *
2704 * We don't use the sprite, so we can ignore that. And on Crestline we have
2705 * to set the non-SR watermarks to 8.
2706 */
2707 void intel_update_watermarks(struct drm_crtc *crtc)
2708 {
2709 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
2710
2711 if (dev_priv->display.update_wm)
2712 dev_priv->display.update_wm(crtc);
2713 }
2714
2715 void intel_update_sprite_watermarks(struct drm_plane *plane,
2716 struct drm_crtc *crtc,
2717 uint32_t sprite_width, int pixel_size,
2718 bool enabled, bool scaled)
2719 {
2720 struct drm_i915_private *dev_priv = plane->dev->dev_private;
2721
2722 if (dev_priv->display.update_sprite_wm)
2723 dev_priv->display.update_sprite_wm(plane, crtc, sprite_width,
2724 pixel_size, enabled, scaled);
2725 }
2726
2727 static struct drm_i915_gem_object *
2728 intel_alloc_context_page(struct drm_device *dev)
2729 {
2730 struct drm_i915_gem_object *ctx;
2731 int ret;
2732
2733 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2734
2735 ctx = i915_gem_alloc_object(dev, 4096);
2736 if (!ctx) {
2737 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
2738 return NULL;
2739 }
2740
2741 ret = i915_gem_obj_ggtt_pin(ctx, 4096, true, false);
2742 if (ret) {
2743 DRM_ERROR("failed to pin power context: %d\n", ret);
2744 goto err_unref;
2745 }
2746
2747 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
2748 if (ret) {
2749 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
2750 goto err_unpin;
2751 }
2752
2753 return ctx;
2754
2755 err_unpin:
2756 i915_gem_object_unpin(ctx);
2757 err_unref:
2758 drm_gem_object_unreference(&ctx->base);
2759 return NULL;
2760 }
2761
2762 /**
2763 * Lock protecting IPS related data structures
2764 */
2765 DEFINE_SPINLOCK(mchdev_lock);
2766
2767 /* Global for IPS driver to get at the current i915 device. Protected by
2768 * mchdev_lock. */
2769 static struct drm_i915_private *i915_mch_dev;
2770
2771 bool ironlake_set_drps(struct drm_device *dev, u8 val)
2772 {
2773 struct drm_i915_private *dev_priv = dev->dev_private;
2774 u16 rgvswctl;
2775
2776 assert_spin_locked(&mchdev_lock);
2777
2778 rgvswctl = I915_READ16(MEMSWCTL);
2779 if (rgvswctl & MEMCTL_CMD_STS) {
2780 DRM_DEBUG("gpu busy, RCS change rejected\n");
2781 return false; /* still busy with another command */
2782 }
2783
2784 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
2785 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
2786 I915_WRITE16(MEMSWCTL, rgvswctl);
2787 POSTING_READ16(MEMSWCTL);
2788
2789 rgvswctl |= MEMCTL_CMD_STS;
2790 I915_WRITE16(MEMSWCTL, rgvswctl);
2791
2792 return true;
2793 }
2794
2795 static void ironlake_enable_drps(struct drm_device *dev)
2796 {
2797 struct drm_i915_private *dev_priv = dev->dev_private;
2798 u32 rgvmodectl = I915_READ(MEMMODECTL);
2799 u8 fmax, fmin, fstart, vstart;
2800
2801 spin_lock_irq(&mchdev_lock);
2802
2803 /* Enable temp reporting */
2804 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
2805 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
2806
2807 /* 100ms RC evaluation intervals */
2808 I915_WRITE(RCUPEI, 100000);
2809 I915_WRITE(RCDNEI, 100000);
2810
2811 /* Set max/min thresholds to 90ms and 80ms respectively */
2812 I915_WRITE(RCBMAXAVG, 90000);
2813 I915_WRITE(RCBMINAVG, 80000);
2814
2815 I915_WRITE(MEMIHYST, 1);
2816
2817 /* Set up min, max, and cur for interrupt handling */
2818 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
2819 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
2820 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
2821 MEMMODE_FSTART_SHIFT;
2822
2823 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
2824 PXVFREQ_PX_SHIFT;
2825
2826 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
2827 dev_priv->ips.fstart = fstart;
2828
2829 dev_priv->ips.max_delay = fstart;
2830 dev_priv->ips.min_delay = fmin;
2831 dev_priv->ips.cur_delay = fstart;
2832
2833 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
2834 fmax, fmin, fstart);
2835
2836 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
2837
2838 /*
2839 * Interrupts will be enabled in ironlake_irq_postinstall
2840 */
2841
2842 I915_WRITE(VIDSTART, vstart);
2843 POSTING_READ(VIDSTART);
2844
2845 rgvmodectl |= MEMMODE_SWMODE_EN;
2846 I915_WRITE(MEMMODECTL, rgvmodectl);
2847
2848 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2849 DRM_ERROR("stuck trying to change perf mode\n");
2850 mdelay(1);
2851
2852 ironlake_set_drps(dev, fstart);
2853
2854 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2855 I915_READ(0x112e0);
2856 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
2857 dev_priv->ips.last_count2 = I915_READ(0x112f4);
2858 getrawmonotonic(&dev_priv->ips.last_time2);
2859
2860 spin_unlock_irq(&mchdev_lock);
2861 }
2862
2863 static void ironlake_disable_drps(struct drm_device *dev)
2864 {
2865 struct drm_i915_private *dev_priv = dev->dev_private;
2866 u16 rgvswctl;
2867
2868 spin_lock_irq(&mchdev_lock);
2869
2870 rgvswctl = I915_READ16(MEMSWCTL);
2871
2872 /* Ack interrupts, disable EFC interrupt */
2873 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
2874 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
2875 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
2876 I915_WRITE(DEIIR, DE_PCU_EVENT);
2877 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
2878
2879 /* Go back to the starting frequency */
2880 ironlake_set_drps(dev, dev_priv->ips.fstart);
2881 mdelay(1);
2882 rgvswctl |= MEMCTL_CMD_STS;
2883 I915_WRITE(MEMSWCTL, rgvswctl);
2884 mdelay(1);
2885
2886 spin_unlock_irq(&mchdev_lock);
2887 }
2888
2889 /* There's a funny hw issue where the hw returns all 0 when reading from
2890 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
2891 * ourselves, instead of doing a rmw cycle (which might result in us clearing
2892 * all limits and the gpu stuck at whatever frequency it is at atm).
2893 */
2894 static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2895 {
2896 u32 limits;
2897
2898 /* Only set the down limit when we've reached the lowest level to avoid
2899 * getting more interrupts, otherwise leave this clear. This prevents a
2900 * race in the hw when coming out of rc6: There's a tiny window where
2901 * the hw runs at the minimal clock before selecting the desired
2902 * frequency, if the down threshold expires in that window we will not
2903 * receive a down interrupt. */
2904 limits = dev_priv->rps.max_delay << 24;
2905 if (val <= dev_priv->rps.min_delay)
2906 limits |= dev_priv->rps.min_delay << 16;
2907
2908 return limits;
2909 }
2910
2911 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
2912 {
2913 int new_power;
2914
2915 new_power = dev_priv->rps.power;
2916 switch (dev_priv->rps.power) {
2917 case LOW_POWER:
2918 if (val > dev_priv->rps.rpe_delay + 1 && val > dev_priv->rps.cur_delay)
2919 new_power = BETWEEN;
2920 break;
2921
2922 case BETWEEN:
2923 if (val <= dev_priv->rps.rpe_delay && val < dev_priv->rps.cur_delay)
2924 new_power = LOW_POWER;
2925 else if (val >= dev_priv->rps.rp0_delay && val > dev_priv->rps.cur_delay)
2926 new_power = HIGH_POWER;
2927 break;
2928
2929 case HIGH_POWER:
2930 if (val < (dev_priv->rps.rp1_delay + dev_priv->rps.rp0_delay) >> 1 && val < dev_priv->rps.cur_delay)
2931 new_power = BETWEEN;
2932 break;
2933 }
2934 /* Max/min bins are special */
2935 if (val == dev_priv->rps.min_delay)
2936 new_power = LOW_POWER;
2937 if (val == dev_priv->rps.max_delay)
2938 new_power = HIGH_POWER;
2939 if (new_power == dev_priv->rps.power)
2940 return;
2941
2942 /* Note the units here are not exactly 1us, but 1280ns. */
2943 switch (new_power) {
2944 case LOW_POWER:
2945 /* Upclock if more than 95% busy over 16ms */
2946 I915_WRITE(GEN6_RP_UP_EI, 12500);
2947 I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800);
2948
2949 /* Downclock if less than 85% busy over 32ms */
2950 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
2951 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250);
2952
2953 I915_WRITE(GEN6_RP_CONTROL,
2954 GEN6_RP_MEDIA_TURBO |
2955 GEN6_RP_MEDIA_HW_NORMAL_MODE |
2956 GEN6_RP_MEDIA_IS_GFX |
2957 GEN6_RP_ENABLE |
2958 GEN6_RP_UP_BUSY_AVG |
2959 GEN6_RP_DOWN_IDLE_AVG);
2960 break;
2961
2962 case BETWEEN:
2963 /* Upclock if more than 90% busy over 13ms */
2964 I915_WRITE(GEN6_RP_UP_EI, 10250);
2965 I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225);
2966
2967 /* Downclock if less than 75% busy over 32ms */
2968 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
2969 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750);
2970
2971 I915_WRITE(GEN6_RP_CONTROL,
2972 GEN6_RP_MEDIA_TURBO |
2973 GEN6_RP_MEDIA_HW_NORMAL_MODE |
2974 GEN6_RP_MEDIA_IS_GFX |
2975 GEN6_RP_ENABLE |
2976 GEN6_RP_UP_BUSY_AVG |
2977 GEN6_RP_DOWN_IDLE_AVG);
2978 break;
2979
2980 case HIGH_POWER:
2981 /* Upclock if more than 85% busy over 10ms */
2982 I915_WRITE(GEN6_RP_UP_EI, 8000);
2983 I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800);
2984
2985 /* Downclock if less than 60% busy over 32ms */
2986 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
2987 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000);
2988
2989 I915_WRITE(GEN6_RP_CONTROL,
2990 GEN6_RP_MEDIA_TURBO |
2991 GEN6_RP_MEDIA_HW_NORMAL_MODE |
2992 GEN6_RP_MEDIA_IS_GFX |
2993 GEN6_RP_ENABLE |
2994 GEN6_RP_UP_BUSY_AVG |
2995 GEN6_RP_DOWN_IDLE_AVG);
2996 break;
2997 }
2998
2999 dev_priv->rps.power = new_power;
3000 dev_priv->rps.last_adj = 0;
3001 }
3002
3003 void gen6_set_rps(struct drm_device *dev, u8 val)
3004 {
3005 struct drm_i915_private *dev_priv = dev->dev_private;
3006
3007 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3008 WARN_ON(val > dev_priv->rps.max_delay);
3009 WARN_ON(val < dev_priv->rps.min_delay);
3010
3011 if (val == dev_priv->rps.cur_delay)
3012 return;
3013
3014 gen6_set_rps_thresholds(dev_priv, val);
3015
3016 if (IS_HASWELL(dev))
3017 I915_WRITE(GEN6_RPNSWREQ,
3018 HSW_FREQUENCY(val));
3019 else
3020 I915_WRITE(GEN6_RPNSWREQ,
3021 GEN6_FREQUENCY(val) |
3022 GEN6_OFFSET(0) |
3023 GEN6_AGGRESSIVE_TURBO);
3024
3025 /* Make sure we continue to get interrupts
3026 * until we hit the minimum or maximum frequencies.
3027 */
3028 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
3029 gen6_rps_limits(dev_priv, val));
3030
3031 POSTING_READ(GEN6_RPNSWREQ);
3032
3033 dev_priv->rps.cur_delay = val;
3034
3035 trace_intel_gpu_freq_change(val * 50);
3036 }
3037
3038 void gen6_rps_idle(struct drm_i915_private *dev_priv)
3039 {
3040 struct drm_device *dev = dev_priv->dev;
3041
3042 mutex_lock(&dev_priv->rps.hw_lock);
3043 if (dev_priv->rps.enabled) {
3044 if (IS_VALLEYVIEW(dev))
3045 valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
3046 else
3047 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
3048 dev_priv->rps.last_adj = 0;
3049 }
3050 mutex_unlock(&dev_priv->rps.hw_lock);
3051 }
3052
3053 void gen6_rps_boost(struct drm_i915_private *dev_priv)
3054 {
3055 struct drm_device *dev = dev_priv->dev;
3056
3057 mutex_lock(&dev_priv->rps.hw_lock);
3058 if (dev_priv->rps.enabled) {
3059 if (IS_VALLEYVIEW(dev))
3060 valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_delay);
3061 else
3062 gen6_set_rps(dev_priv->dev, dev_priv->rps.max_delay);
3063 dev_priv->rps.last_adj = 0;
3064 }
3065 mutex_unlock(&dev_priv->rps.hw_lock);
3066 }
3067
3068 void valleyview_set_rps(struct drm_device *dev, u8 val)
3069 {
3070 struct drm_i915_private *dev_priv = dev->dev_private;
3071
3072 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3073 WARN_ON(val > dev_priv->rps.max_delay);
3074 WARN_ON(val < dev_priv->rps.min_delay);
3075
3076 DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
3077 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_delay),
3078 dev_priv->rps.cur_delay,
3079 vlv_gpu_freq(dev_priv, val), val);
3080
3081 if (val == dev_priv->rps.cur_delay)
3082 return;
3083
3084 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
3085
3086 dev_priv->rps.cur_delay = val;
3087
3088 trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val));
3089 }
3090
3091 static void gen6_disable_rps_interrupts(struct drm_device *dev)
3092 {
3093 struct drm_i915_private *dev_priv = dev->dev_private;
3094
3095 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3096 I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) & ~GEN6_PM_RPS_EVENTS);
3097 /* Complete PM interrupt masking here doesn't race with the rps work
3098 * item again unmasking PM interrupts because that is using a different
3099 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3100 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3101
3102 spin_lock_irq(&dev_priv->irq_lock);
3103 dev_priv->rps.pm_iir = 0;
3104 spin_unlock_irq(&dev_priv->irq_lock);
3105
3106 I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
3107 }
3108
3109 static void gen6_disable_rps(struct drm_device *dev)
3110 {
3111 struct drm_i915_private *dev_priv = dev->dev_private;
3112
3113 I915_WRITE(GEN6_RC_CONTROL, 0);
3114 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
3115
3116 gen6_disable_rps_interrupts(dev);
3117 }
3118
3119 static void valleyview_disable_rps(struct drm_device *dev)
3120 {
3121 struct drm_i915_private *dev_priv = dev->dev_private;
3122
3123 I915_WRITE(GEN6_RC_CONTROL, 0);
3124
3125 gen6_disable_rps_interrupts(dev);
3126
3127 if (dev_priv->vlv_pctx) {
3128 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
3129 dev_priv->vlv_pctx = NULL;
3130 }
3131 }
3132
3133 static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
3134 {
3135 if (IS_GEN6(dev))
3136 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
3137
3138 if (IS_HASWELL(dev))
3139 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
3140
3141 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
3142 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3143 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3144 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
3145 }
3146
3147 int intel_enable_rc6(const struct drm_device *dev)
3148 {
3149 /* No RC6 before Ironlake */
3150 if (INTEL_INFO(dev)->gen < 5)
3151 return 0;
3152
3153 /* Respect the kernel parameter if it is set */
3154 if (i915_enable_rc6 >= 0)
3155 return i915_enable_rc6;
3156
3157 /* Disable RC6 on Ironlake */
3158 if (INTEL_INFO(dev)->gen == 5)
3159 return 0;
3160
3161 if (IS_HASWELL(dev))
3162 return INTEL_RC6_ENABLE;
3163
3164 /* snb/ivb have more than one rc6 state. */
3165 if (INTEL_INFO(dev)->gen == 6)
3166 return INTEL_RC6_ENABLE;
3167
3168 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
3169 }
3170
3171 static void gen6_enable_rps_interrupts(struct drm_device *dev)
3172 {
3173 struct drm_i915_private *dev_priv = dev->dev_private;
3174 u32 enabled_intrs;
3175
3176 spin_lock_irq(&dev_priv->irq_lock);
3177 WARN_ON(dev_priv->rps.pm_iir);
3178 snb_enable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS);
3179 I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
3180 spin_unlock_irq(&dev_priv->irq_lock);
3181
3182 /* only unmask PM interrupts we need. Mask all others. */
3183 enabled_intrs = GEN6_PM_RPS_EVENTS;
3184
3185 /* IVB and SNB hard hangs on looping batchbuffer
3186 * if GEN6_PM_UP_EI_EXPIRED is masked.
3187 */
3188 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
3189 enabled_intrs |= GEN6_PM_RP_UP_EI_EXPIRED;
3190
3191 I915_WRITE(GEN6_PMINTRMSK, ~enabled_intrs);
3192 }
3193
3194 static void gen8_enable_rps(struct drm_device *dev)
3195 {
3196 struct drm_i915_private *dev_priv = dev->dev_private;
3197 struct intel_ring_buffer *ring;
3198 uint32_t rc6_mask = 0, rp_state_cap;
3199 int unused;
3200
3201 /* 1a: Software RC state - RC0 */
3202 I915_WRITE(GEN6_RC_STATE, 0);
3203
3204 /* 1c & 1d: Get forcewake during program sequence. Although the driver
3205 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
3206 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3207
3208 /* 2a: Disable RC states. */
3209 I915_WRITE(GEN6_RC_CONTROL, 0);
3210
3211 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3212
3213 /* 2b: Program RC6 thresholds.*/
3214 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
3215 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
3216 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
3217 for_each_ring(ring, dev_priv, unused)
3218 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3219 I915_WRITE(GEN6_RC_SLEEP, 0);
3220 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
3221
3222 /* 3: Enable RC6 */
3223 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
3224 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
3225 DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off");
3226 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
3227 GEN6_RC_CTL_EI_MODE(1) |
3228 rc6_mask);
3229
3230 /* 4 Program defaults and thresholds for RPS*/
3231 I915_WRITE(GEN6_RPNSWREQ, HSW_FREQUENCY(10)); /* Request 500 MHz */
3232 I915_WRITE(GEN6_RC_VIDEO_FREQ, HSW_FREQUENCY(12)); /* Request 600 MHz */
3233 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
3234 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
3235
3236 /* Docs recommend 900MHz, and 300 MHz respectively */
3237 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
3238 dev_priv->rps.max_delay << 24 |
3239 dev_priv->rps.min_delay << 16);
3240
3241 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
3242 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
3243 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
3244 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
3245
3246 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3247
3248 /* 5: Enable RPS */
3249 I915_WRITE(GEN6_RP_CONTROL,
3250 GEN6_RP_MEDIA_TURBO |
3251 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3252 GEN6_RP_MEDIA_IS_GFX |
3253 GEN6_RP_ENABLE |
3254 GEN6_RP_UP_BUSY_AVG |
3255 GEN6_RP_DOWN_IDLE_AVG);
3256
3257 /* 6: Ring frequency + overclocking (our driver does this later */
3258
3259 gen6_set_rps(dev, (I915_READ(GEN6_GT_PERF_STATUS) & 0xff00) >> 8);
3260
3261 gen6_enable_rps_interrupts(dev);
3262
3263 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3264 }
3265
3266 static void gen6_enable_rps(struct drm_device *dev)
3267 {
3268 struct drm_i915_private *dev_priv = dev->dev_private;
3269 struct intel_ring_buffer *ring;
3270 u32 rp_state_cap;
3271 u32 gt_perf_status;
3272 u32 rc6vids, pcu_mbox, rc6_mask = 0;
3273 u32 gtfifodbg;
3274 int rc6_mode;
3275 int i, ret;
3276
3277 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3278
3279 /* Here begins a magic sequence of register writes to enable
3280 * auto-downclocking.
3281 *
3282 * Perhaps there might be some value in exposing these to
3283 * userspace...
3284 */
3285 I915_WRITE(GEN6_RC_STATE, 0);
3286
3287 /* Clear the DBG now so we don't confuse earlier errors */
3288 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3289 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3290 I915_WRITE(GTFIFODBG, gtfifodbg);
3291 }
3292
3293 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3294
3295 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3296 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
3297
3298 /* In units of 50MHz */
3299 dev_priv->rps.hw_max = dev_priv->rps.max_delay = rp_state_cap & 0xff;
3300 dev_priv->rps.min_delay = (rp_state_cap >> 16) & 0xff;
3301 dev_priv->rps.rp1_delay = (rp_state_cap >> 8) & 0xff;
3302 dev_priv->rps.rp0_delay = (rp_state_cap >> 0) & 0xff;
3303 dev_priv->rps.rpe_delay = dev_priv->rps.rp1_delay;
3304 dev_priv->rps.cur_delay = 0;
3305
3306 /* disable the counters and set deterministic thresholds */
3307 I915_WRITE(GEN6_RC_CONTROL, 0);
3308
3309 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
3310 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
3311 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
3312 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3313 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3314
3315 for_each_ring(ring, dev_priv, i)
3316 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3317
3318 I915_WRITE(GEN6_RC_SLEEP, 0);
3319 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
3320 if (IS_IVYBRIDGE(dev))
3321 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
3322 else
3323 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
3324 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
3325 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
3326
3327 /* Check if we are enabling RC6 */
3328 rc6_mode = intel_enable_rc6(dev_priv->dev);
3329 if (rc6_mode & INTEL_RC6_ENABLE)
3330 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
3331
3332 /* We don't use those on Haswell */
3333 if (!IS_HASWELL(dev)) {
3334 if (rc6_mode & INTEL_RC6p_ENABLE)
3335 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
3336
3337 if (rc6_mode & INTEL_RC6pp_ENABLE)
3338 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
3339 }
3340
3341 intel_print_rc6_info(dev, rc6_mask);
3342
3343 I915_WRITE(GEN6_RC_CONTROL,
3344 rc6_mask |
3345 GEN6_RC_CTL_EI_MODE(1) |
3346 GEN6_RC_CTL_HW_ENABLE);
3347
3348 /* Power down if completely idle for over 50ms */
3349 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
3350 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3351
3352 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
3353 if (!ret) {
3354 pcu_mbox = 0;
3355 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
3356 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
3357 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
3358 (dev_priv->rps.max_delay & 0xff) * 50,
3359 (pcu_mbox & 0xff) * 50);
3360 dev_priv->rps.hw_max = pcu_mbox & 0xff;
3361 }
3362 } else {
3363 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
3364 }
3365
3366 dev_priv->rps.power = HIGH_POWER; /* force a reset */
3367 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
3368
3369 gen6_enable_rps_interrupts(dev);
3370
3371 rc6vids = 0;
3372 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
3373 if (IS_GEN6(dev) && ret) {
3374 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
3375 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
3376 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
3377 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
3378 rc6vids &= 0xffff00;
3379 rc6vids |= GEN6_ENCODE_RC6_VID(450);
3380 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
3381 if (ret)
3382 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
3383 }
3384
3385 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3386 }
3387
3388 void gen6_update_ring_freq(struct drm_device *dev)
3389 {
3390 struct drm_i915_private *dev_priv = dev->dev_private;
3391 int min_freq = 15;
3392 unsigned int gpu_freq;
3393 unsigned int max_ia_freq, min_ring_freq;
3394 int scaling_factor = 180;
3395 struct cpufreq_policy *policy;
3396
3397 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3398
3399 policy = cpufreq_cpu_get(0);
3400 if (policy) {
3401 max_ia_freq = policy->cpuinfo.max_freq;
3402 cpufreq_cpu_put(policy);
3403 } else {
3404 /*
3405 * Default to measured freq if none found, PCU will ensure we
3406 * don't go over
3407 */
3408 max_ia_freq = tsc_khz;
3409 }
3410
3411 /* Convert from kHz to MHz */
3412 max_ia_freq /= 1000;
3413
3414 min_ring_freq = I915_READ(DCLK) & 0xf;
3415 /* convert DDR frequency from units of 266.6MHz to bandwidth */
3416 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3417
3418 /*
3419 * For each potential GPU frequency, load a ring frequency we'd like
3420 * to use for memory access. We do this by specifying the IA frequency
3421 * the PCU should use as a reference to determine the ring frequency.
3422 */
3423 for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay;
3424 gpu_freq--) {
3425 int diff = dev_priv->rps.max_delay - gpu_freq;
3426 unsigned int ia_freq = 0, ring_freq = 0;
3427
3428 if (INTEL_INFO(dev)->gen >= 8) {
3429 /* max(2 * GT, DDR). NB: GT is 50MHz units */
3430 ring_freq = max(min_ring_freq, gpu_freq);
3431 } else if (IS_HASWELL(dev)) {
3432 ring_freq = mult_frac(gpu_freq, 5, 4);
3433 ring_freq = max(min_ring_freq, ring_freq);
3434 /* leave ia_freq as the default, chosen by cpufreq */
3435 } else {
3436 /* On older processors, there is no separate ring
3437 * clock domain, so in order to boost the bandwidth
3438 * of the ring, we need to upclock the CPU (ia_freq).
3439 *
3440 * For GPU frequencies less than 750MHz,
3441 * just use the lowest ring freq.
3442 */
3443 if (gpu_freq < min_freq)
3444 ia_freq = 800;
3445 else
3446 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
3447 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
3448 }
3449
3450 sandybridge_pcode_write(dev_priv,
3451 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3452 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
3453 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
3454 gpu_freq);
3455 }
3456 }
3457
3458 int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
3459 {
3460 u32 val, rp0;
3461
3462 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
3463
3464 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
3465 /* Clamp to max */
3466 rp0 = min_t(u32, rp0, 0xea);
3467
3468 return rp0;
3469 }
3470
3471 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
3472 {
3473 u32 val, rpe;
3474
3475 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
3476 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
3477 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
3478 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
3479
3480 return rpe;
3481 }
3482
3483 int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
3484 {
3485 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
3486 }
3487
3488 static void valleyview_setup_pctx(struct drm_device *dev)
3489 {
3490 struct drm_i915_private *dev_priv = dev->dev_private;
3491 struct drm_i915_gem_object *pctx;
3492 unsigned long pctx_paddr;
3493 u32 pcbr;
3494 int pctx_size = 24*1024;
3495
3496 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3497
3498 pcbr = I915_READ(VLV_PCBR);
3499 if (pcbr) {
3500 /* BIOS set it up already, grab the pre-alloc'd space */
3501 int pcbr_offset;
3502
3503 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
3504 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
3505 pcbr_offset,
3506 I915_GTT_OFFSET_NONE,
3507 pctx_size);
3508 goto out;
3509 }
3510
3511 /*
3512 * From the Gunit register HAS:
3513 * The Gfx driver is expected to program this register and ensure
3514 * proper allocation within Gfx stolen memory. For example, this
3515 * register should be programmed such than the PCBR range does not
3516 * overlap with other ranges, such as the frame buffer, protected
3517 * memory, or any other relevant ranges.
3518 */
3519 pctx = i915_gem_object_create_stolen(dev, pctx_size);
3520 if (!pctx) {
3521 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
3522 return;
3523 }
3524
3525 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
3526 I915_WRITE(VLV_PCBR, pctx_paddr);
3527
3528 out:
3529 dev_priv->vlv_pctx = pctx;
3530 }
3531
3532 static void valleyview_enable_rps(struct drm_device *dev)
3533 {
3534 struct drm_i915_private *dev_priv = dev->dev_private;
3535 struct intel_ring_buffer *ring;
3536 u32 gtfifodbg, val, rc6_mode = 0;
3537 int i;
3538
3539 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3540
3541 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3542 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
3543 gtfifodbg);
3544 I915_WRITE(GTFIFODBG, gtfifodbg);
3545 }
3546
3547 /* If VLV, Forcewake all wells, else re-direct to regular path */
3548 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3549
3550 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
3551 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
3552 I915_WRITE(GEN6_RP_UP_EI, 66000);
3553 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
3554
3555 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3556
3557 I915_WRITE(GEN6_RP_CONTROL,
3558 GEN6_RP_MEDIA_TURBO |
3559 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3560 GEN6_RP_MEDIA_IS_GFX |
3561 GEN6_RP_ENABLE |
3562 GEN6_RP_UP_BUSY_AVG |
3563 GEN6_RP_DOWN_IDLE_CONT);
3564
3565 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
3566 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3567 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3568
3569 for_each_ring(ring, dev_priv, i)
3570 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3571
3572 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
3573
3574 /* allows RC6 residency counter to work */
3575 I915_WRITE(VLV_COUNTER_CONTROL,
3576 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
3577 VLV_MEDIA_RC6_COUNT_EN |
3578 VLV_RENDER_RC6_COUNT_EN));
3579 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
3580 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
3581
3582 intel_print_rc6_info(dev, rc6_mode);
3583
3584 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
3585
3586 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
3587
3588 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
3589 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
3590
3591 dev_priv->rps.cur_delay = (val >> 8) & 0xff;
3592 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
3593 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_delay),
3594 dev_priv->rps.cur_delay);
3595
3596 dev_priv->rps.max_delay = valleyview_rps_max_freq(dev_priv);
3597 dev_priv->rps.hw_max = dev_priv->rps.max_delay;
3598 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
3599 vlv_gpu_freq(dev_priv, dev_priv->rps.max_delay),
3600 dev_priv->rps.max_delay);
3601
3602 dev_priv->rps.rpe_delay = valleyview_rps_rpe_freq(dev_priv);
3603 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
3604 vlv_gpu_freq(dev_priv, dev_priv->rps.rpe_delay),
3605 dev_priv->rps.rpe_delay);
3606
3607 dev_priv->rps.min_delay = valleyview_rps_min_freq(dev_priv);
3608 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
3609 vlv_gpu_freq(dev_priv, dev_priv->rps.min_delay),
3610 dev_priv->rps.min_delay);
3611
3612 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
3613 vlv_gpu_freq(dev_priv, dev_priv->rps.rpe_delay),
3614 dev_priv->rps.rpe_delay);
3615
3616 valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
3617
3618 gen6_enable_rps_interrupts(dev);
3619
3620 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3621 }
3622
3623 void ironlake_teardown_rc6(struct drm_device *dev)
3624 {
3625 struct drm_i915_private *dev_priv = dev->dev_private;
3626
3627 if (dev_priv->ips.renderctx) {
3628 i915_gem_object_unpin(dev_priv->ips.renderctx);
3629 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
3630 dev_priv->ips.renderctx = NULL;
3631 }
3632
3633 if (dev_priv->ips.pwrctx) {
3634 i915_gem_object_unpin(dev_priv->ips.pwrctx);
3635 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
3636 dev_priv->ips.pwrctx = NULL;
3637 }
3638 }
3639
3640 static void ironlake_disable_rc6(struct drm_device *dev)
3641 {
3642 struct drm_i915_private *dev_priv = dev->dev_private;
3643
3644 if (I915_READ(PWRCTXA)) {
3645 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
3646 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
3647 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
3648 50);
3649
3650 I915_WRITE(PWRCTXA, 0);
3651 POSTING_READ(PWRCTXA);
3652
3653 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
3654 POSTING_READ(RSTDBYCTL);
3655 }
3656 }
3657
3658 static int ironlake_setup_rc6(struct drm_device *dev)
3659 {
3660 struct drm_i915_private *dev_priv = dev->dev_private;
3661
3662 if (dev_priv->ips.renderctx == NULL)
3663 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
3664 if (!dev_priv->ips.renderctx)
3665 return -ENOMEM;
3666
3667 if (dev_priv->ips.pwrctx == NULL)
3668 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
3669 if (!dev_priv->ips.pwrctx) {
3670 ironlake_teardown_rc6(dev);
3671 return -ENOMEM;
3672 }
3673
3674 return 0;
3675 }
3676
3677 static void ironlake_enable_rc6(struct drm_device *dev)
3678 {
3679 struct drm_i915_private *dev_priv = dev->dev_private;
3680 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
3681 bool was_interruptible;
3682 int ret;
3683
3684 /* rc6 disabled by default due to repeated reports of hanging during
3685 * boot and resume.
3686 */
3687 if (!intel_enable_rc6(dev))
3688 return;
3689
3690 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3691
3692 ret = ironlake_setup_rc6(dev);
3693 if (ret)
3694 return;
3695
3696 was_interruptible = dev_priv->mm.interruptible;
3697 dev_priv->mm.interruptible = false;
3698
3699 /*
3700 * GPU can automatically power down the render unit if given a page
3701 * to save state.
3702 */
3703 ret = intel_ring_begin(ring, 6);
3704 if (ret) {
3705 ironlake_teardown_rc6(dev);
3706 dev_priv->mm.interruptible = was_interruptible;
3707 return;
3708 }
3709
3710 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
3711 intel_ring_emit(ring, MI_SET_CONTEXT);
3712 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) |
3713 MI_MM_SPACE_GTT |
3714 MI_SAVE_EXT_STATE_EN |
3715 MI_RESTORE_EXT_STATE_EN |
3716 MI_RESTORE_INHIBIT);
3717 intel_ring_emit(ring, MI_SUSPEND_FLUSH);
3718 intel_ring_emit(ring, MI_NOOP);
3719 intel_ring_emit(ring, MI_FLUSH);
3720 intel_ring_advance(ring);
3721
3722 /*
3723 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
3724 * does an implicit flush, combined with MI_FLUSH above, it should be
3725 * safe to assume that renderctx is valid
3726 */
3727 ret = intel_ring_idle(ring);
3728 dev_priv->mm.interruptible = was_interruptible;
3729 if (ret) {
3730 DRM_ERROR("failed to enable ironlake power savings\n");
3731 ironlake_teardown_rc6(dev);
3732 return;
3733 }
3734
3735 I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN);
3736 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
3737
3738 intel_print_rc6_info(dev, INTEL_RC6_ENABLE);
3739 }
3740
3741 static unsigned long intel_pxfreq(u32 vidfreq)
3742 {
3743 unsigned long freq;
3744 int div = (vidfreq & 0x3f0000) >> 16;
3745 int post = (vidfreq & 0x3000) >> 12;
3746 int pre = (vidfreq & 0x7);
3747
3748 if (!pre)
3749 return 0;
3750
3751 freq = ((div * 133333) / ((1<<post) * pre));
3752
3753 return freq;
3754 }
3755
3756 static const struct cparams {
3757 u16 i;
3758 u16 t;
3759 u16 m;
3760 u16 c;
3761 } cparams[] = {
3762 { 1, 1333, 301, 28664 },
3763 { 1, 1066, 294, 24460 },
3764 { 1, 800, 294, 25192 },
3765 { 0, 1333, 276, 27605 },
3766 { 0, 1066, 276, 27605 },
3767 { 0, 800, 231, 23784 },
3768 };
3769
3770 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
3771 {
3772 u64 total_count, diff, ret;
3773 u32 count1, count2, count3, m = 0, c = 0;
3774 unsigned long now = jiffies_to_msecs(jiffies), diff1;
3775 int i;
3776
3777 assert_spin_locked(&mchdev_lock);
3778
3779 diff1 = now - dev_priv->ips.last_time1;
3780
3781 /* Prevent division-by-zero if we are asking too fast.
3782 * Also, we don't get interesting results if we are polling
3783 * faster than once in 10ms, so just return the saved value
3784 * in such cases.
3785 */
3786 if (diff1 <= 10)
3787 return dev_priv->ips.chipset_power;
3788
3789 count1 = I915_READ(DMIEC);
3790 count2 = I915_READ(DDREC);
3791 count3 = I915_READ(CSIEC);
3792
3793 total_count = count1 + count2 + count3;
3794
3795 /* FIXME: handle per-counter overflow */
3796 if (total_count < dev_priv->ips.last_count1) {
3797 diff = ~0UL - dev_priv->ips.last_count1;
3798 diff += total_count;
3799 } else {
3800 diff = total_count - dev_priv->ips.last_count1;
3801 }
3802
3803 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
3804 if (cparams[i].i == dev_priv->ips.c_m &&
3805 cparams[i].t == dev_priv->ips.r_t) {
3806 m = cparams[i].m;
3807 c = cparams[i].c;
3808 break;
3809 }
3810 }
3811
3812 diff = div_u64(diff, diff1);
3813 ret = ((m * diff) + c);
3814 ret = div_u64(ret, 10);
3815
3816 dev_priv->ips.last_count1 = total_count;
3817 dev_priv->ips.last_time1 = now;
3818
3819 dev_priv->ips.chipset_power = ret;
3820
3821 return ret;
3822 }
3823
3824 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
3825 {
3826 unsigned long val;
3827
3828 if (dev_priv->info->gen != 5)
3829 return 0;
3830
3831 spin_lock_irq(&mchdev_lock);
3832
3833 val = __i915_chipset_val(dev_priv);
3834
3835 spin_unlock_irq(&mchdev_lock);
3836
3837 return val;
3838 }
3839
3840 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
3841 {
3842 unsigned long m, x, b;
3843 u32 tsfs;
3844
3845 tsfs = I915_READ(TSFS);
3846
3847 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
3848 x = I915_READ8(TR1);
3849
3850 b = tsfs & TSFS_INTR_MASK;
3851
3852 return ((m * x) / 127) - b;
3853 }
3854
3855 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
3856 {
3857 static const struct v_table {
3858 u16 vd; /* in .1 mil */
3859 u16 vm; /* in .1 mil */
3860 } v_table[] = {
3861 { 0, 0, },
3862 { 375, 0, },
3863 { 500, 0, },
3864 { 625, 0, },
3865 { 750, 0, },
3866 { 875, 0, },
3867 { 1000, 0, },
3868 { 1125, 0, },
3869 { 4125, 3000, },
3870 { 4125, 3000, },
3871 { 4125, 3000, },
3872 { 4125, 3000, },
3873 { 4125, 3000, },
3874 { 4125, 3000, },
3875 { 4125, 3000, },
3876 { 4125, 3000, },
3877 { 4125, 3000, },
3878 { 4125, 3000, },
3879 { 4125, 3000, },
3880 { 4125, 3000, },
3881 { 4125, 3000, },
3882 { 4125, 3000, },
3883 { 4125, 3000, },
3884 { 4125, 3000, },
3885 { 4125, 3000, },
3886 { 4125, 3000, },
3887 { 4125, 3000, },
3888 { 4125, 3000, },
3889 { 4125, 3000, },
3890 { 4125, 3000, },
3891 { 4125, 3000, },
3892 { 4125, 3000, },
3893 { 4250, 3125, },
3894 { 4375, 3250, },
3895 { 4500, 3375, },
3896 { 4625, 3500, },
3897 { 4750, 3625, },
3898 { 4875, 3750, },
3899 { 5000, 3875, },
3900 { 5125, 4000, },
3901 { 5250, 4125, },
3902 { 5375, 4250, },
3903 { 5500, 4375, },
3904 { 5625, 4500, },
3905 { 5750, 4625, },
3906 { 5875, 4750, },
3907 { 6000, 4875, },
3908 { 6125, 5000, },
3909 { 6250, 5125, },
3910 { 6375, 5250, },
3911 { 6500, 5375, },
3912 { 6625, 5500, },
3913 { 6750, 5625, },
3914 { 6875, 5750, },
3915 { 7000, 5875, },
3916 { 7125, 6000, },
3917 { 7250, 6125, },
3918 { 7375, 6250, },
3919 { 7500, 6375, },
3920 { 7625, 6500, },
3921 { 7750, 6625, },
3922 { 7875, 6750, },
3923 { 8000, 6875, },
3924 { 8125, 7000, },
3925 { 8250, 7125, },
3926 { 8375, 7250, },
3927 { 8500, 7375, },
3928 { 8625, 7500, },
3929 { 8750, 7625, },
3930 { 8875, 7750, },
3931 { 9000, 7875, },
3932 { 9125, 8000, },
3933 { 9250, 8125, },
3934 { 9375, 8250, },
3935 { 9500, 8375, },
3936 { 9625, 8500, },
3937 { 9750, 8625, },
3938 { 9875, 8750, },
3939 { 10000, 8875, },
3940 { 10125, 9000, },
3941 { 10250, 9125, },
3942 { 10375, 9250, },
3943 { 10500, 9375, },
3944 { 10625, 9500, },
3945 { 10750, 9625, },
3946 { 10875, 9750, },
3947 { 11000, 9875, },
3948 { 11125, 10000, },
3949 { 11250, 10125, },
3950 { 11375, 10250, },
3951 { 11500, 10375, },
3952 { 11625, 10500, },
3953 { 11750, 10625, },
3954 { 11875, 10750, },
3955 { 12000, 10875, },
3956 { 12125, 11000, },
3957 { 12250, 11125, },
3958 { 12375, 11250, },
3959 { 12500, 11375, },
3960 { 12625, 11500, },
3961 { 12750, 11625, },
3962 { 12875, 11750, },
3963 { 13000, 11875, },
3964 { 13125, 12000, },
3965 { 13250, 12125, },
3966 { 13375, 12250, },
3967 { 13500, 12375, },
3968 { 13625, 12500, },
3969 { 13750, 12625, },
3970 { 13875, 12750, },
3971 { 14000, 12875, },
3972 { 14125, 13000, },
3973 { 14250, 13125, },
3974 { 14375, 13250, },
3975 { 14500, 13375, },
3976 { 14625, 13500, },
3977 { 14750, 13625, },
3978 { 14875, 13750, },
3979 { 15000, 13875, },
3980 { 15125, 14000, },
3981 { 15250, 14125, },
3982 { 15375, 14250, },
3983 { 15500, 14375, },
3984 { 15625, 14500, },
3985 { 15750, 14625, },
3986 { 15875, 14750, },
3987 { 16000, 14875, },
3988 { 16125, 15000, },
3989 };
3990 if (dev_priv->info->is_mobile)
3991 return v_table[pxvid].vm;
3992 else
3993 return v_table[pxvid].vd;
3994 }
3995
3996 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
3997 {
3998 struct timespec now, diff1;
3999 u64 diff;
4000 unsigned long diffms;
4001 u32 count;
4002
4003 assert_spin_locked(&mchdev_lock);
4004
4005 getrawmonotonic(&now);
4006 diff1 = timespec_sub(now, dev_priv->ips.last_time2);
4007
4008 /* Don't divide by 0 */
4009 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
4010 if (!diffms)
4011 return;
4012
4013 count = I915_READ(GFXEC);
4014
4015 if (count < dev_priv->ips.last_count2) {
4016 diff = ~0UL - dev_priv->ips.last_count2;
4017 diff += count;
4018 } else {
4019 diff = count - dev_priv->ips.last_count2;
4020 }
4021
4022 dev_priv->ips.last_count2 = count;
4023 dev_priv->ips.last_time2 = now;
4024
4025 /* More magic constants... */
4026 diff = diff * 1181;
4027 diff = div_u64(diff, diffms * 10);
4028 dev_priv->ips.gfx_power = diff;
4029 }
4030
4031 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
4032 {
4033 if (dev_priv->info->gen != 5)
4034 return;
4035
4036 spin_lock_irq(&mchdev_lock);
4037
4038 __i915_update_gfx_val(dev_priv);
4039
4040 spin_unlock_irq(&mchdev_lock);
4041 }
4042
4043 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
4044 {
4045 unsigned long t, corr, state1, corr2, state2;
4046 u32 pxvid, ext_v;
4047
4048 assert_spin_locked(&mchdev_lock);
4049
4050 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4));
4051 pxvid = (pxvid >> 24) & 0x7f;
4052 ext_v = pvid_to_extvid(dev_priv, pxvid);
4053
4054 state1 = ext_v;
4055
4056 t = i915_mch_val(dev_priv);
4057
4058 /* Revel in the empirically derived constants */
4059
4060 /* Correction factor in 1/100000 units */
4061 if (t > 80)
4062 corr = ((t * 2349) + 135940);
4063 else if (t >= 50)
4064 corr = ((t * 964) + 29317);
4065 else /* < 50 */
4066 corr = ((t * 301) + 1004);
4067
4068 corr = corr * ((150142 * state1) / 10000 - 78642);
4069 corr /= 100000;
4070 corr2 = (corr * dev_priv->ips.corr);
4071
4072 state2 = (corr2 * state1) / 10000;
4073 state2 /= 100; /* convert to mW */
4074
4075 __i915_update_gfx_val(dev_priv);
4076
4077 return dev_priv->ips.gfx_power + state2;
4078 }
4079
4080 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
4081 {
4082 unsigned long val;
4083
4084 if (dev_priv->info->gen != 5)
4085 return 0;
4086
4087 spin_lock_irq(&mchdev_lock);
4088
4089 val = __i915_gfx_val(dev_priv);
4090
4091 spin_unlock_irq(&mchdev_lock);
4092
4093 return val;
4094 }
4095
4096 /**
4097 * i915_read_mch_val - return value for IPS use
4098 *
4099 * Calculate and return a value for the IPS driver to use when deciding whether
4100 * we have thermal and power headroom to increase CPU or GPU power budget.
4101 */
4102 unsigned long i915_read_mch_val(void)
4103 {
4104 struct drm_i915_private *dev_priv;
4105 unsigned long chipset_val, graphics_val, ret = 0;
4106
4107 spin_lock_irq(&mchdev_lock);
4108 if (!i915_mch_dev)
4109 goto out_unlock;
4110 dev_priv = i915_mch_dev;
4111
4112 chipset_val = __i915_chipset_val(dev_priv);
4113 graphics_val = __i915_gfx_val(dev_priv);
4114
4115 ret = chipset_val + graphics_val;
4116
4117 out_unlock:
4118 spin_unlock_irq(&mchdev_lock);
4119
4120 return ret;
4121 }
4122 EXPORT_SYMBOL_GPL(i915_read_mch_val);
4123
4124 /**
4125 * i915_gpu_raise - raise GPU frequency limit
4126 *
4127 * Raise the limit; IPS indicates we have thermal headroom.
4128 */
4129 bool i915_gpu_raise(void)
4130 {
4131 struct drm_i915_private *dev_priv;
4132 bool ret = true;
4133
4134 spin_lock_irq(&mchdev_lock);
4135 if (!i915_mch_dev) {
4136 ret = false;
4137 goto out_unlock;
4138 }
4139 dev_priv = i915_mch_dev;
4140
4141 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
4142 dev_priv->ips.max_delay--;
4143
4144 out_unlock:
4145 spin_unlock_irq(&mchdev_lock);
4146
4147 return ret;
4148 }
4149 EXPORT_SYMBOL_GPL(i915_gpu_raise);
4150
4151 /**
4152 * i915_gpu_lower - lower GPU frequency limit
4153 *
4154 * IPS indicates we're close to a thermal limit, so throttle back the GPU
4155 * frequency maximum.
4156 */
4157 bool i915_gpu_lower(void)
4158 {
4159 struct drm_i915_private *dev_priv;
4160 bool ret = true;
4161
4162 spin_lock_irq(&mchdev_lock);
4163 if (!i915_mch_dev) {
4164 ret = false;
4165 goto out_unlock;
4166 }
4167 dev_priv = i915_mch_dev;
4168
4169 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
4170 dev_priv->ips.max_delay++;
4171
4172 out_unlock:
4173 spin_unlock_irq(&mchdev_lock);
4174
4175 return ret;
4176 }
4177 EXPORT_SYMBOL_GPL(i915_gpu_lower);
4178
4179 /**
4180 * i915_gpu_busy - indicate GPU business to IPS
4181 *
4182 * Tell the IPS driver whether or not the GPU is busy.
4183 */
4184 bool i915_gpu_busy(void)
4185 {
4186 struct drm_i915_private *dev_priv;
4187 struct intel_ring_buffer *ring;
4188 bool ret = false;
4189 int i;
4190
4191 spin_lock_irq(&mchdev_lock);
4192 if (!i915_mch_dev)
4193 goto out_unlock;
4194 dev_priv = i915_mch_dev;
4195
4196 for_each_ring(ring, dev_priv, i)
4197 ret |= !list_empty(&ring->request_list);
4198
4199 out_unlock:
4200 spin_unlock_irq(&mchdev_lock);
4201
4202 return ret;
4203 }
4204 EXPORT_SYMBOL_GPL(i915_gpu_busy);
4205
4206 /**
4207 * i915_gpu_turbo_disable - disable graphics turbo
4208 *
4209 * Disable graphics turbo by resetting the max frequency and setting the
4210 * current frequency to the default.
4211 */
4212 bool i915_gpu_turbo_disable(void)
4213 {
4214 struct drm_i915_private *dev_priv;
4215 bool ret = true;
4216
4217 spin_lock_irq(&mchdev_lock);
4218 if (!i915_mch_dev) {
4219 ret = false;
4220 goto out_unlock;
4221 }
4222 dev_priv = i915_mch_dev;
4223
4224 dev_priv->ips.max_delay = dev_priv->ips.fstart;
4225
4226 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
4227 ret = false;
4228
4229 out_unlock:
4230 spin_unlock_irq(&mchdev_lock);
4231
4232 return ret;
4233 }
4234 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
4235
4236 /**
4237 * Tells the intel_ips driver that the i915 driver is now loaded, if
4238 * IPS got loaded first.
4239 *
4240 * This awkward dance is so that neither module has to depend on the
4241 * other in order for IPS to do the appropriate communication of
4242 * GPU turbo limits to i915.
4243 */
4244 static void
4245 ips_ping_for_i915_load(void)
4246 {
4247 void (*link)(void);
4248
4249 link = symbol_get(ips_link_to_i915_driver);
4250 if (link) {
4251 link();
4252 symbol_put(ips_link_to_i915_driver);
4253 }
4254 }
4255
4256 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
4257 {
4258 /* We only register the i915 ips part with intel-ips once everything is
4259 * set up, to avoid intel-ips sneaking in and reading bogus values. */
4260 spin_lock_irq(&mchdev_lock);
4261 i915_mch_dev = dev_priv;
4262 spin_unlock_irq(&mchdev_lock);
4263
4264 ips_ping_for_i915_load();
4265 }
4266
4267 void intel_gpu_ips_teardown(void)
4268 {
4269 spin_lock_irq(&mchdev_lock);
4270 i915_mch_dev = NULL;
4271 spin_unlock_irq(&mchdev_lock);
4272 }
4273 static void intel_init_emon(struct drm_device *dev)
4274 {
4275 struct drm_i915_private *dev_priv = dev->dev_private;
4276 u32 lcfuse;
4277 u8 pxw[16];
4278 int i;
4279
4280 /* Disable to program */
4281 I915_WRITE(ECR, 0);
4282 POSTING_READ(ECR);
4283
4284 /* Program energy weights for various events */
4285 I915_WRITE(SDEW, 0x15040d00);
4286 I915_WRITE(CSIEW0, 0x007f0000);
4287 I915_WRITE(CSIEW1, 0x1e220004);
4288 I915_WRITE(CSIEW2, 0x04000004);
4289
4290 for (i = 0; i < 5; i++)
4291 I915_WRITE(PEW + (i * 4), 0);
4292 for (i = 0; i < 3; i++)
4293 I915_WRITE(DEW + (i * 4), 0);
4294
4295 /* Program P-state weights to account for frequency power adjustment */
4296 for (i = 0; i < 16; i++) {
4297 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
4298 unsigned long freq = intel_pxfreq(pxvidfreq);
4299 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
4300 PXVFREQ_PX_SHIFT;
4301 unsigned long val;
4302
4303 val = vid * vid;
4304 val *= (freq / 1000);
4305 val *= 255;
4306 val /= (127*127*900);
4307 if (val > 0xff)
4308 DRM_ERROR("bad pxval: %ld\n", val);
4309 pxw[i] = val;
4310 }
4311 /* Render standby states get 0 weight */
4312 pxw[14] = 0;
4313 pxw[15] = 0;
4314
4315 for (i = 0; i < 4; i++) {
4316 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
4317 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
4318 I915_WRITE(PXW + (i * 4), val);
4319 }
4320
4321 /* Adjust magic regs to magic values (more experimental results) */
4322 I915_WRITE(OGW0, 0);
4323 I915_WRITE(OGW1, 0);
4324 I915_WRITE(EG0, 0x00007f00);
4325 I915_WRITE(EG1, 0x0000000e);
4326 I915_WRITE(EG2, 0x000e0000);
4327 I915_WRITE(EG3, 0x68000300);
4328 I915_WRITE(EG4, 0x42000000);
4329 I915_WRITE(EG5, 0x00140031);
4330 I915_WRITE(EG6, 0);
4331 I915_WRITE(EG7, 0);
4332
4333 for (i = 0; i < 8; i++)
4334 I915_WRITE(PXWL + (i * 4), 0);
4335
4336 /* Enable PMON + select events */
4337 I915_WRITE(ECR, 0x80000019);
4338
4339 lcfuse = I915_READ(LCFUSE02);
4340
4341 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
4342 }
4343
4344 void intel_disable_gt_powersave(struct drm_device *dev)
4345 {
4346 struct drm_i915_private *dev_priv = dev->dev_private;
4347
4348 /* Interrupts should be disabled already to avoid re-arming. */
4349 WARN_ON(dev->irq_enabled);
4350
4351 if (IS_IRONLAKE_M(dev)) {
4352 ironlake_disable_drps(dev);
4353 ironlake_disable_rc6(dev);
4354 } else if (INTEL_INFO(dev)->gen >= 6) {
4355 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
4356 cancel_work_sync(&dev_priv->rps.work);
4357 mutex_lock(&dev_priv->rps.hw_lock);
4358 if (IS_VALLEYVIEW(dev))
4359 valleyview_disable_rps(dev);
4360 else
4361 gen6_disable_rps(dev);
4362 dev_priv->rps.enabled = false;
4363 mutex_unlock(&dev_priv->rps.hw_lock);
4364 }
4365 }
4366
4367 static void intel_gen6_powersave_work(struct work_struct *work)
4368 {
4369 struct drm_i915_private *dev_priv =
4370 container_of(work, struct drm_i915_private,
4371 rps.delayed_resume_work.work);
4372 struct drm_device *dev = dev_priv->dev;
4373
4374 mutex_lock(&dev_priv->rps.hw_lock);
4375
4376 if (IS_VALLEYVIEW(dev)) {
4377 valleyview_enable_rps(dev);
4378 } else if (IS_BROADWELL(dev)) {
4379 gen8_enable_rps(dev);
4380 gen6_update_ring_freq(dev);
4381 } else {
4382 gen6_enable_rps(dev);
4383 gen6_update_ring_freq(dev);
4384 }
4385 dev_priv->rps.enabled = true;
4386 mutex_unlock(&dev_priv->rps.hw_lock);
4387 }
4388
4389 void intel_enable_gt_powersave(struct drm_device *dev)
4390 {
4391 struct drm_i915_private *dev_priv = dev->dev_private;
4392
4393 if (IS_IRONLAKE_M(dev)) {
4394 ironlake_enable_drps(dev);
4395 ironlake_enable_rc6(dev);
4396 intel_init_emon(dev);
4397 } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
4398 if (IS_VALLEYVIEW(dev))
4399 valleyview_setup_pctx(dev);
4400 /*
4401 * PCU communication is slow and this doesn't need to be
4402 * done at any specific time, so do this out of our fast path
4403 * to make resume and init faster.
4404 */
4405 schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
4406 round_jiffies_up_relative(HZ));
4407 }
4408 }
4409
4410 static void ibx_init_clock_gating(struct drm_device *dev)
4411 {
4412 struct drm_i915_private *dev_priv = dev->dev_private;
4413
4414 /*
4415 * On Ibex Peak and Cougar Point, we need to disable clock
4416 * gating for the panel power sequencer or it will fail to
4417 * start up when no ports are active.
4418 */
4419 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
4420 }
4421
4422 static void g4x_disable_trickle_feed(struct drm_device *dev)
4423 {
4424 struct drm_i915_private *dev_priv = dev->dev_private;
4425 int pipe;
4426
4427 for_each_pipe(pipe) {
4428 I915_WRITE(DSPCNTR(pipe),
4429 I915_READ(DSPCNTR(pipe)) |
4430 DISPPLANE_TRICKLE_FEED_DISABLE);
4431 intel_flush_primary_plane(dev_priv, pipe);
4432 }
4433 }
4434
4435 static void ilk_init_lp_watermarks(struct drm_device *dev)
4436 {
4437 struct drm_i915_private *dev_priv = dev->dev_private;
4438
4439 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
4440 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
4441 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
4442
4443 /*
4444 * Don't touch WM1S_LP_EN here.
4445 * Doing so could cause underruns.
4446 */
4447 }
4448
4449 static void ironlake_init_clock_gating(struct drm_device *dev)
4450 {
4451 struct drm_i915_private *dev_priv = dev->dev_private;
4452 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
4453
4454 /*
4455 * Required for FBC
4456 * WaFbcDisableDpfcClockGating:ilk
4457 */
4458 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
4459 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
4460 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
4461
4462 I915_WRITE(PCH_3DCGDIS0,
4463 MARIUNIT_CLOCK_GATE_DISABLE |
4464 SVSMUNIT_CLOCK_GATE_DISABLE);
4465 I915_WRITE(PCH_3DCGDIS1,
4466 VFMUNIT_CLOCK_GATE_DISABLE);
4467
4468 /*
4469 * According to the spec the following bits should be set in
4470 * order to enable memory self-refresh
4471 * The bit 22/21 of 0x42004
4472 * The bit 5 of 0x42020
4473 * The bit 15 of 0x45000
4474 */
4475 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4476 (I915_READ(ILK_DISPLAY_CHICKEN2) |
4477 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4478 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
4479 I915_WRITE(DISP_ARB_CTL,
4480 (I915_READ(DISP_ARB_CTL) |
4481 DISP_FBC_WM_DIS));
4482
4483 ilk_init_lp_watermarks(dev);
4484
4485 /*
4486 * Based on the document from hardware guys the following bits
4487 * should be set unconditionally in order to enable FBC.
4488 * The bit 22 of 0x42000
4489 * The bit 22 of 0x42004
4490 * The bit 7,8,9 of 0x42020.
4491 */
4492 if (IS_IRONLAKE_M(dev)) {
4493 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
4494 I915_WRITE(ILK_DISPLAY_CHICKEN1,
4495 I915_READ(ILK_DISPLAY_CHICKEN1) |
4496 ILK_FBCQ_DIS);
4497 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4498 I915_READ(ILK_DISPLAY_CHICKEN2) |
4499 ILK_DPARB_GATE);
4500 }
4501
4502 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
4503
4504 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4505 I915_READ(ILK_DISPLAY_CHICKEN2) |
4506 ILK_ELPIN_409_SELECT);
4507 I915_WRITE(_3D_CHICKEN2,
4508 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
4509 _3D_CHICKEN2_WM_READ_PIPELINED);
4510
4511 /* WaDisableRenderCachePipelinedFlush:ilk */
4512 I915_WRITE(CACHE_MODE_0,
4513 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
4514
4515 g4x_disable_trickle_feed(dev);
4516
4517 ibx_init_clock_gating(dev);
4518 }
4519
4520 static void cpt_init_clock_gating(struct drm_device *dev)
4521 {
4522 struct drm_i915_private *dev_priv = dev->dev_private;
4523 int pipe;
4524 uint32_t val;
4525
4526 /*
4527 * On Ibex Peak and Cougar Point, we need to disable clock
4528 * gating for the panel power sequencer or it will fail to
4529 * start up when no ports are active.
4530 */
4531 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
4532 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
4533 PCH_CPUNIT_CLOCK_GATE_DISABLE);
4534 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
4535 DPLS_EDP_PPS_FIX_DIS);
4536 /* The below fixes the weird display corruption, a few pixels shifted
4537 * downward, on (only) LVDS of some HP laptops with IVY.
4538 */
4539 for_each_pipe(pipe) {
4540 val = I915_READ(TRANS_CHICKEN2(pipe));
4541 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
4542 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
4543 if (dev_priv->vbt.fdi_rx_polarity_inverted)
4544 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
4545 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
4546 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
4547 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
4548 I915_WRITE(TRANS_CHICKEN2(pipe), val);
4549 }
4550 /* WADP0ClockGatingDisable */
4551 for_each_pipe(pipe) {
4552 I915_WRITE(TRANS_CHICKEN1(pipe),
4553 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
4554 }
4555 }
4556
4557 static void gen6_check_mch_setup(struct drm_device *dev)
4558 {
4559 struct drm_i915_private *dev_priv = dev->dev_private;
4560 uint32_t tmp;
4561
4562 tmp = I915_READ(MCH_SSKPD);
4563 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) {
4564 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp);
4565 DRM_INFO("This can cause pipe underruns and display issues.\n");
4566 DRM_INFO("Please upgrade your BIOS to fix this.\n");
4567 }
4568 }
4569
4570 static void gen6_init_clock_gating(struct drm_device *dev)
4571 {
4572 struct drm_i915_private *dev_priv = dev->dev_private;
4573 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
4574
4575 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
4576
4577 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4578 I915_READ(ILK_DISPLAY_CHICKEN2) |
4579 ILK_ELPIN_409_SELECT);
4580
4581 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4582 I915_WRITE(_3D_CHICKEN,
4583 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
4584
4585 /* WaSetupGtModeTdRowDispatch:snb */
4586 if (IS_SNB_GT1(dev))
4587 I915_WRITE(GEN6_GT_MODE,
4588 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
4589
4590 ilk_init_lp_watermarks(dev);
4591
4592 I915_WRITE(CACHE_MODE_0,
4593 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
4594
4595 I915_WRITE(GEN6_UCGCTL1,
4596 I915_READ(GEN6_UCGCTL1) |
4597 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
4598 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
4599
4600 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4601 * gating disable must be set. Failure to set it results in
4602 * flickering pixels due to Z write ordering failures after
4603 * some amount of runtime in the Mesa "fire" demo, and Unigine
4604 * Sanctuary and Tropics, and apparently anything else with
4605 * alpha test or pixel discard.
4606 *
4607 * According to the spec, bit 11 (RCCUNIT) must also be set,
4608 * but we didn't debug actual testcases to find it out.
4609 *
4610 * Also apply WaDisableVDSUnitClockGating:snb and
4611 * WaDisableRCPBUnitClockGating:snb.
4612 */
4613 I915_WRITE(GEN6_UCGCTL2,
4614 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
4615 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
4616 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4617
4618 /* Bspec says we need to always set all mask bits. */
4619 I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) |
4620 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL);
4621
4622 /*
4623 * According to the spec the following bits should be
4624 * set in order to enable memory self-refresh and fbc:
4625 * The bit21 and bit22 of 0x42000
4626 * The bit21 and bit22 of 0x42004
4627 * The bit5 and bit7 of 0x42020
4628 * The bit14 of 0x70180
4629 * The bit14 of 0x71180
4630 *
4631 * WaFbcAsynchFlipDisableFbcQueue:snb
4632 */
4633 I915_WRITE(ILK_DISPLAY_CHICKEN1,
4634 I915_READ(ILK_DISPLAY_CHICKEN1) |
4635 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
4636 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4637 I915_READ(ILK_DISPLAY_CHICKEN2) |
4638 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
4639 I915_WRITE(ILK_DSPCLK_GATE_D,
4640 I915_READ(ILK_DSPCLK_GATE_D) |
4641 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
4642 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
4643
4644 g4x_disable_trickle_feed(dev);
4645
4646 /* The default value should be 0x200 according to docs, but the two
4647 * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
4648 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff));
4649 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
4650
4651 cpt_init_clock_gating(dev);
4652
4653 gen6_check_mch_setup(dev);
4654 }
4655
4656 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
4657 {
4658 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
4659
4660 reg &= ~GEN7_FF_SCHED_MASK;
4661 reg |= GEN7_FF_TS_SCHED_HW;
4662 reg |= GEN7_FF_VS_SCHED_HW;
4663 reg |= GEN7_FF_DS_SCHED_HW;
4664
4665 if (IS_HASWELL(dev_priv->dev))
4666 reg &= ~GEN7_FF_VS_REF_CNT_FFME;
4667
4668 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
4669 }
4670
4671 static void lpt_init_clock_gating(struct drm_device *dev)
4672 {
4673 struct drm_i915_private *dev_priv = dev->dev_private;
4674
4675 /*
4676 * TODO: this bit should only be enabled when really needed, then
4677 * disabled when not needed anymore in order to save power.
4678 */
4679 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
4680 I915_WRITE(SOUTH_DSPCLK_GATE_D,
4681 I915_READ(SOUTH_DSPCLK_GATE_D) |
4682 PCH_LP_PARTITION_LEVEL_DISABLE);
4683
4684 /* WADPOClockGatingDisable:hsw */
4685 I915_WRITE(_TRANSA_CHICKEN1,
4686 I915_READ(_TRANSA_CHICKEN1) |
4687 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
4688 }
4689
4690 static void lpt_suspend_hw(struct drm_device *dev)
4691 {
4692 struct drm_i915_private *dev_priv = dev->dev_private;
4693
4694 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
4695 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
4696
4697 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
4698 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
4699 }
4700 }
4701
4702 static void gen8_init_clock_gating(struct drm_device *dev)
4703 {
4704 struct drm_i915_private *dev_priv = dev->dev_private;
4705 enum pipe i;
4706
4707 I915_WRITE(WM3_LP_ILK, 0);
4708 I915_WRITE(WM2_LP_ILK, 0);
4709 I915_WRITE(WM1_LP_ILK, 0);
4710
4711 /* FIXME(BDW): Check all the w/a, some might only apply to
4712 * pre-production hw. */
4713
4714 WARN(!i915_preliminary_hw_support,
4715 "GEN8_CENTROID_PIXEL_OPT_DIS not be needed for production\n");
4716 I915_WRITE(HALF_SLICE_CHICKEN3,
4717 _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS));
4718 I915_WRITE(HALF_SLICE_CHICKEN3,
4719 _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
4720 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE));
4721
4722 I915_WRITE(_3D_CHICKEN3,
4723 _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2));
4724
4725 I915_WRITE(COMMON_SLICE_CHICKEN2,
4726 _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE));
4727
4728 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
4729 _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE));
4730
4731 /* WaSwitchSolVfFArbitrationPriority:bdw */
4732 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
4733
4734 /* WaPsrDPAMaskVBlankInSRD:bdw */
4735 I915_WRITE(CHICKEN_PAR1_1,
4736 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
4737
4738 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
4739 for_each_pipe(i) {
4740 I915_WRITE(CHICKEN_PIPESL_1(i),
4741 I915_READ(CHICKEN_PIPESL_1(i) |
4742 DPRS_MASK_VBLANK_SRD));
4743 }
4744
4745 /* Use Force Non-Coherent whenever executing a 3D context. This is a
4746 * workaround for for a possible hang in the unlikely event a TLB
4747 * invalidation occurs during a PSD flush.
4748 */
4749 I915_WRITE(HDC_CHICKEN0,
4750 I915_READ(HDC_CHICKEN0) |
4751 _MASKED_BIT_ENABLE(HDC_FORCE_NON_COHERENT));
4752
4753 /* WaVSRefCountFullforceMissDisable:bdw */
4754 /* WaDSRefCountFullforceMissDisable:bdw */
4755 I915_WRITE(GEN7_FF_THREAD_MODE,
4756 I915_READ(GEN7_FF_THREAD_MODE) &
4757 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
4758 }
4759
4760 static void haswell_init_clock_gating(struct drm_device *dev)
4761 {
4762 struct drm_i915_private *dev_priv = dev->dev_private;
4763
4764 ilk_init_lp_watermarks(dev);
4765
4766 /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
4767 * This implements the WaDisableRCZUnitClockGating:hsw workaround.
4768 */
4769 I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
4770
4771 /* Apply the WaDisableRHWOOptimizationForRenderHang:hsw workaround. */
4772 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4773 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4774
4775 /* WaApplyL3ControlAndL3ChickenMode:hsw */
4776 I915_WRITE(GEN7_L3CNTLREG1,
4777 GEN7_WA_FOR_GEN7_L3_CONTROL);
4778 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
4779 GEN7_WA_L3_CHICKEN_MODE);
4780
4781 /* L3 caching of data atomics doesn't work -- disable it. */
4782 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
4783 I915_WRITE(HSW_ROW_CHICKEN3,
4784 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
4785
4786 /* This is required by WaCatErrorRejectionIssue:hsw */
4787 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4788 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4789 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4790
4791 /* WaVSRefCountFullforceMissDisable:hsw */
4792 gen7_setup_fixed_func_scheduler(dev_priv);
4793
4794 /* WaDisable4x2SubspanOptimization:hsw */
4795 I915_WRITE(CACHE_MODE_1,
4796 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
4797
4798 /* WaSwitchSolVfFArbitrationPriority:hsw */
4799 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
4800
4801 /* WaRsPkgCStateDisplayPMReq:hsw */
4802 I915_WRITE(CHICKEN_PAR1_1,
4803 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
4804
4805 lpt_init_clock_gating(dev);
4806 }
4807
4808 static void ivybridge_init_clock_gating(struct drm_device *dev)
4809 {
4810 struct drm_i915_private *dev_priv = dev->dev_private;
4811 uint32_t snpcr;
4812
4813 ilk_init_lp_watermarks(dev);
4814
4815 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
4816
4817 /* WaDisableEarlyCull:ivb */
4818 I915_WRITE(_3D_CHICKEN3,
4819 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
4820
4821 /* WaDisableBackToBackFlipFix:ivb */
4822 I915_WRITE(IVB_CHICKEN3,
4823 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
4824 CHICKEN3_DGMG_DONE_FIX_DISABLE);
4825
4826 /* WaDisablePSDDualDispatchEnable:ivb */
4827 if (IS_IVB_GT1(dev))
4828 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
4829 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
4830 else
4831 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
4832 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
4833
4834 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
4835 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4836 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4837
4838 /* WaApplyL3ControlAndL3ChickenMode:ivb */
4839 I915_WRITE(GEN7_L3CNTLREG1,
4840 GEN7_WA_FOR_GEN7_L3_CONTROL);
4841 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
4842 GEN7_WA_L3_CHICKEN_MODE);
4843 if (IS_IVB_GT1(dev))
4844 I915_WRITE(GEN7_ROW_CHICKEN2,
4845 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4846 else
4847 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
4848 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4849
4850
4851 /* WaForceL3Serialization:ivb */
4852 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
4853 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
4854
4855 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4856 * gating disable must be set. Failure to set it results in
4857 * flickering pixels due to Z write ordering failures after
4858 * some amount of runtime in the Mesa "fire" demo, and Unigine
4859 * Sanctuary and Tropics, and apparently anything else with
4860 * alpha test or pixel discard.
4861 *
4862 * According to the spec, bit 11 (RCCUNIT) must also be set,
4863 * but we didn't debug actual testcases to find it out.
4864 *
4865 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
4866 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
4867 */
4868 I915_WRITE(GEN6_UCGCTL2,
4869 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
4870 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4871
4872 /* This is required by WaCatErrorRejectionIssue:ivb */
4873 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4874 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4875 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4876
4877 g4x_disable_trickle_feed(dev);
4878
4879 /* WaVSRefCountFullforceMissDisable:ivb */
4880 gen7_setup_fixed_func_scheduler(dev_priv);
4881
4882 /* WaDisable4x2SubspanOptimization:ivb */
4883 I915_WRITE(CACHE_MODE_1,
4884 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
4885
4886 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4887 snpcr &= ~GEN6_MBC_SNPCR_MASK;
4888 snpcr |= GEN6_MBC_SNPCR_MED;
4889 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
4890
4891 if (!HAS_PCH_NOP(dev))
4892 cpt_init_clock_gating(dev);
4893
4894 gen6_check_mch_setup(dev);
4895 }
4896
4897 static void valleyview_init_clock_gating(struct drm_device *dev)
4898 {
4899 struct drm_i915_private *dev_priv = dev->dev_private;
4900 u32 val;
4901
4902 mutex_lock(&dev_priv->rps.hw_lock);
4903 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4904 mutex_unlock(&dev_priv->rps.hw_lock);
4905 switch ((val >> 6) & 3) {
4906 case 0:
4907 dev_priv->mem_freq = 800;
4908 break;
4909 case 1:
4910 dev_priv->mem_freq = 1066;
4911 break;
4912 case 2:
4913 dev_priv->mem_freq = 1333;
4914 break;
4915 case 3:
4916 dev_priv->mem_freq = 1333;
4917 break;
4918 }
4919 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
4920
4921 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
4922
4923 /* WaDisableEarlyCull:vlv */
4924 I915_WRITE(_3D_CHICKEN3,
4925 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
4926
4927 /* WaDisableBackToBackFlipFix:vlv */
4928 I915_WRITE(IVB_CHICKEN3,
4929 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
4930 CHICKEN3_DGMG_DONE_FIX_DISABLE);
4931
4932 /* WaDisablePSDDualDispatchEnable:vlv */
4933 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
4934 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
4935 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
4936
4937 /* Apply the WaDisableRHWOOptimizationForRenderHang:vlv workaround. */
4938 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4939 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4940
4941 /* WaApplyL3ControlAndL3ChickenMode:vlv */
4942 I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
4943 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
4944
4945 /* WaForceL3Serialization:vlv */
4946 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
4947 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
4948
4949 /* WaDisableDopClockGating:vlv */
4950 I915_WRITE(GEN7_ROW_CHICKEN2,
4951 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4952
4953 /* This is required by WaCatErrorRejectionIssue:vlv */
4954 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4955 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4956 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4957
4958 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4959 * gating disable must be set. Failure to set it results in
4960 * flickering pixels due to Z write ordering failures after
4961 * some amount of runtime in the Mesa "fire" demo, and Unigine
4962 * Sanctuary and Tropics, and apparently anything else with
4963 * alpha test or pixel discard.
4964 *
4965 * According to the spec, bit 11 (RCCUNIT) must also be set,
4966 * but we didn't debug actual testcases to find it out.
4967 *
4968 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
4969 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
4970 *
4971 * Also apply WaDisableVDSUnitClockGating:vlv and
4972 * WaDisableRCPBUnitClockGating:vlv.
4973 */
4974 I915_WRITE(GEN6_UCGCTL2,
4975 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
4976 GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
4977 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
4978 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
4979 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4980
4981 I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
4982
4983 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
4984
4985 I915_WRITE(CACHE_MODE_1,
4986 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
4987
4988 /*
4989 * WaDisableVLVClockGating_VBIIssue:vlv
4990 * Disable clock gating on th GCFG unit to prevent a delay
4991 * in the reporting of vblank events.
4992 */
4993 I915_WRITE(VLV_GUNIT_CLOCK_GATE, 0xffffffff);
4994
4995 /* Conservative clock gating settings for now */
4996 I915_WRITE(0x9400, 0xffffffff);
4997 I915_WRITE(0x9404, 0xffffffff);
4998 I915_WRITE(0x9408, 0xffffffff);
4999 I915_WRITE(0x940c, 0xffffffff);
5000 I915_WRITE(0x9410, 0xffffffff);
5001 I915_WRITE(0x9414, 0xffffffff);
5002 I915_WRITE(0x9418, 0xffffffff);
5003 }
5004
5005 static void g4x_init_clock_gating(struct drm_device *dev)
5006 {
5007 struct drm_i915_private *dev_priv = dev->dev_private;
5008 uint32_t dspclk_gate;
5009
5010 I915_WRITE(RENCLK_GATE_D1, 0);
5011 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5012 GS_UNIT_CLOCK_GATE_DISABLE |
5013 CL_UNIT_CLOCK_GATE_DISABLE);
5014 I915_WRITE(RAMCLK_GATE_D, 0);
5015 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5016 OVRUNIT_CLOCK_GATE_DISABLE |
5017 OVCUNIT_CLOCK_GATE_DISABLE;
5018 if (IS_GM45(dev))
5019 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5020 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5021
5022 /* WaDisableRenderCachePipelinedFlush */
5023 I915_WRITE(CACHE_MODE_0,
5024 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
5025
5026 g4x_disable_trickle_feed(dev);
5027 }
5028
5029 static void crestline_init_clock_gating(struct drm_device *dev)
5030 {
5031 struct drm_i915_private *dev_priv = dev->dev_private;
5032
5033 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5034 I915_WRITE(RENCLK_GATE_D2, 0);
5035 I915_WRITE(DSPCLK_GATE_D, 0);
5036 I915_WRITE(RAMCLK_GATE_D, 0);
5037 I915_WRITE16(DEUC, 0);
5038 I915_WRITE(MI_ARB_STATE,
5039 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
5040 }
5041
5042 static void broadwater_init_clock_gating(struct drm_device *dev)
5043 {
5044 struct drm_i915_private *dev_priv = dev->dev_private;
5045
5046 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5047 I965_RCC_CLOCK_GATE_DISABLE |
5048 I965_RCPB_CLOCK_GATE_DISABLE |
5049 I965_ISC_CLOCK_GATE_DISABLE |
5050 I965_FBC_CLOCK_GATE_DISABLE);
5051 I915_WRITE(RENCLK_GATE_D2, 0);
5052 I915_WRITE(MI_ARB_STATE,
5053 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
5054 }
5055
5056 static void gen3_init_clock_gating(struct drm_device *dev)
5057 {
5058 struct drm_i915_private *dev_priv = dev->dev_private;
5059 u32 dstate = I915_READ(D_STATE);
5060
5061 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5062 DSTATE_DOT_CLOCK_GATING;
5063 I915_WRITE(D_STATE, dstate);
5064
5065 if (IS_PINEVIEW(dev))
5066 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
5067
5068 /* IIR "flip pending" means done if this bit is set */
5069 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
5070 }
5071
5072 static void i85x_init_clock_gating(struct drm_device *dev)
5073 {
5074 struct drm_i915_private *dev_priv = dev->dev_private;
5075
5076 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5077 }
5078
5079 static void i830_init_clock_gating(struct drm_device *dev)
5080 {
5081 struct drm_i915_private *dev_priv = dev->dev_private;
5082
5083 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5084 }
5085
5086 void intel_init_clock_gating(struct drm_device *dev)
5087 {
5088 struct drm_i915_private *dev_priv = dev->dev_private;
5089
5090 dev_priv->display.init_clock_gating(dev);
5091 }
5092
5093 void intel_suspend_hw(struct drm_device *dev)
5094 {
5095 if (HAS_PCH_LPT(dev))
5096 lpt_suspend_hw(dev);
5097 }
5098
5099 #define for_each_power_well(i, power_well, domain_mask, power_domains) \
5100 for (i = 0; \
5101 i < (power_domains)->power_well_count && \
5102 ((power_well) = &(power_domains)->power_wells[i]); \
5103 i++) \
5104 if ((power_well)->domains & (domain_mask))
5105
5106 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
5107 for (i = (power_domains)->power_well_count - 1; \
5108 i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
5109 i--) \
5110 if ((power_well)->domains & (domain_mask))
5111
5112 /**
5113 * We should only use the power well if we explicitly asked the hardware to
5114 * enable it, so check if it's enabled and also check if we've requested it to
5115 * be enabled.
5116 */
5117 static bool hsw_power_well_enabled(struct drm_device *dev,
5118 struct i915_power_well *power_well)
5119 {
5120 struct drm_i915_private *dev_priv = dev->dev_private;
5121
5122 return I915_READ(HSW_PWR_WELL_DRIVER) ==
5123 (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
5124 }
5125
5126 bool intel_display_power_enabled_sw(struct drm_device *dev,
5127 enum intel_display_power_domain domain)
5128 {
5129 struct drm_i915_private *dev_priv = dev->dev_private;
5130 struct i915_power_domains *power_domains;
5131
5132 power_domains = &dev_priv->power_domains;
5133
5134 return power_domains->domain_use_count[domain];
5135 }
5136
5137 bool intel_display_power_enabled(struct drm_device *dev,
5138 enum intel_display_power_domain domain)
5139 {
5140 struct drm_i915_private *dev_priv = dev->dev_private;
5141 struct i915_power_domains *power_domains;
5142 struct i915_power_well *power_well;
5143 bool is_enabled;
5144 int i;
5145
5146 power_domains = &dev_priv->power_domains;
5147
5148 is_enabled = true;
5149
5150 mutex_lock(&power_domains->lock);
5151 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
5152 if (power_well->always_on)
5153 continue;
5154
5155 if (!power_well->is_enabled(dev, power_well)) {
5156 is_enabled = false;
5157 break;
5158 }
5159 }
5160 mutex_unlock(&power_domains->lock);
5161
5162 return is_enabled;
5163 }
5164
5165 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
5166 {
5167 struct drm_device *dev = dev_priv->dev;
5168 unsigned long irqflags;
5169
5170 /*
5171 * After we re-enable the power well, if we touch VGA register 0x3d5
5172 * we'll get unclaimed register interrupts. This stops after we write
5173 * anything to the VGA MSR register. The vgacon module uses this
5174 * register all the time, so if we unbind our driver and, as a
5175 * consequence, bind vgacon, we'll get stuck in an infinite loop at
5176 * console_unlock(). So make here we touch the VGA MSR register, making
5177 * sure vgacon can keep working normally without triggering interrupts
5178 * and error messages.
5179 */
5180 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
5181 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
5182 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
5183
5184 if (IS_BROADWELL(dev)) {
5185 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
5186 I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_B),
5187 dev_priv->de_irq_mask[PIPE_B]);
5188 I915_WRITE(GEN8_DE_PIPE_IER(PIPE_B),
5189 ~dev_priv->de_irq_mask[PIPE_B] |
5190 GEN8_PIPE_VBLANK);
5191 I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_C),
5192 dev_priv->de_irq_mask[PIPE_C]);
5193 I915_WRITE(GEN8_DE_PIPE_IER(PIPE_C),
5194 ~dev_priv->de_irq_mask[PIPE_C] |
5195 GEN8_PIPE_VBLANK);
5196 POSTING_READ(GEN8_DE_PIPE_IER(PIPE_C));
5197 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
5198 }
5199 }
5200
5201 static void hsw_power_well_post_disable(struct drm_i915_private *dev_priv)
5202 {
5203 struct drm_device *dev = dev_priv->dev;
5204 enum pipe p;
5205 unsigned long irqflags;
5206
5207 /*
5208 * After this, the registers on the pipes that are part of the power
5209 * well will become zero, so we have to adjust our counters according to
5210 * that.
5211 *
5212 * FIXME: Should we do this in general in drm_vblank_post_modeset?
5213 */
5214 spin_lock_irqsave(&dev->vbl_lock, irqflags);
5215 for_each_pipe(p)
5216 if (p != PIPE_A)
5217 dev->vblank[p].last = 0;
5218 spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
5219 }
5220
5221 static void hsw_set_power_well(struct drm_device *dev,
5222 struct i915_power_well *power_well, bool enable)
5223 {
5224 struct drm_i915_private *dev_priv = dev->dev_private;
5225 bool is_enabled, enable_requested;
5226 uint32_t tmp;
5227
5228 WARN_ON(dev_priv->pc8.enabled);
5229
5230 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
5231 is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
5232 enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
5233
5234 if (enable) {
5235 if (!enable_requested)
5236 I915_WRITE(HSW_PWR_WELL_DRIVER,
5237 HSW_PWR_WELL_ENABLE_REQUEST);
5238
5239 if (!is_enabled) {
5240 DRM_DEBUG_KMS("Enabling power well\n");
5241 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
5242 HSW_PWR_WELL_STATE_ENABLED), 20))
5243 DRM_ERROR("Timeout enabling power well\n");
5244 }
5245
5246 hsw_power_well_post_enable(dev_priv);
5247 } else {
5248 if (enable_requested) {
5249 I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
5250 POSTING_READ(HSW_PWR_WELL_DRIVER);
5251 DRM_DEBUG_KMS("Requesting to disable the power well\n");
5252
5253 hsw_power_well_post_disable(dev_priv);
5254 }
5255 }
5256 }
5257
5258 static void __intel_power_well_get(struct drm_device *dev,
5259 struct i915_power_well *power_well)
5260 {
5261 struct drm_i915_private *dev_priv = dev->dev_private;
5262
5263 if (!power_well->count++ && power_well->set) {
5264 hsw_disable_package_c8(dev_priv);
5265 power_well->set(dev, power_well, true);
5266 }
5267 }
5268
5269 static void __intel_power_well_put(struct drm_device *dev,
5270 struct i915_power_well *power_well)
5271 {
5272 struct drm_i915_private *dev_priv = dev->dev_private;
5273
5274 WARN_ON(!power_well->count);
5275
5276 if (!--power_well->count && power_well->set &&
5277 i915_disable_power_well) {
5278 power_well->set(dev, power_well, false);
5279 hsw_enable_package_c8(dev_priv);
5280 }
5281 }
5282
5283 void intel_display_power_get(struct drm_device *dev,
5284 enum intel_display_power_domain domain)
5285 {
5286 struct drm_i915_private *dev_priv = dev->dev_private;
5287 struct i915_power_domains *power_domains;
5288 struct i915_power_well *power_well;
5289 int i;
5290
5291 power_domains = &dev_priv->power_domains;
5292
5293 mutex_lock(&power_domains->lock);
5294
5295 for_each_power_well(i, power_well, BIT(domain), power_domains)
5296 __intel_power_well_get(dev, power_well);
5297
5298 power_domains->domain_use_count[domain]++;
5299
5300 mutex_unlock(&power_domains->lock);
5301 }
5302
5303 void intel_display_power_put(struct drm_device *dev,
5304 enum intel_display_power_domain domain)
5305 {
5306 struct drm_i915_private *dev_priv = dev->dev_private;
5307 struct i915_power_domains *power_domains;
5308 struct i915_power_well *power_well;
5309 int i;
5310
5311 power_domains = &dev_priv->power_domains;
5312
5313 mutex_lock(&power_domains->lock);
5314
5315 WARN_ON(!power_domains->domain_use_count[domain]);
5316 power_domains->domain_use_count[domain]--;
5317
5318 for_each_power_well_rev(i, power_well, BIT(domain), power_domains)
5319 __intel_power_well_put(dev, power_well);
5320
5321 mutex_unlock(&power_domains->lock);
5322 }
5323
5324 static struct i915_power_domains *hsw_pwr;
5325
5326 /* Display audio driver power well request */
5327 void i915_request_power_well(void)
5328 {
5329 struct drm_i915_private *dev_priv;
5330
5331 if (WARN_ON(!hsw_pwr))
5332 return;
5333
5334 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
5335 power_domains);
5336 intel_display_power_get(dev_priv->dev, POWER_DOMAIN_AUDIO);
5337 }
5338 EXPORT_SYMBOL_GPL(i915_request_power_well);
5339
5340 /* Display audio driver power well release */
5341 void i915_release_power_well(void)
5342 {
5343 struct drm_i915_private *dev_priv;
5344
5345 if (WARN_ON(!hsw_pwr))
5346 return;
5347
5348 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
5349 power_domains);
5350 intel_display_power_put(dev_priv->dev, POWER_DOMAIN_AUDIO);
5351 }
5352 EXPORT_SYMBOL_GPL(i915_release_power_well);
5353
5354 static struct i915_power_well i9xx_always_on_power_well[] = {
5355 {
5356 .name = "always-on",
5357 .always_on = 1,
5358 .domains = POWER_DOMAIN_MASK,
5359 },
5360 };
5361
5362 static struct i915_power_well hsw_power_wells[] = {
5363 {
5364 .name = "always-on",
5365 .always_on = 1,
5366 .domains = HSW_ALWAYS_ON_POWER_DOMAINS,
5367 },
5368 {
5369 .name = "display",
5370 .domains = POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS,
5371 .is_enabled = hsw_power_well_enabled,
5372 .set = hsw_set_power_well,
5373 },
5374 };
5375
5376 static struct i915_power_well bdw_power_wells[] = {
5377 {
5378 .name = "always-on",
5379 .always_on = 1,
5380 .domains = BDW_ALWAYS_ON_POWER_DOMAINS,
5381 },
5382 {
5383 .name = "display",
5384 .domains = POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS,
5385 .is_enabled = hsw_power_well_enabled,
5386 .set = hsw_set_power_well,
5387 },
5388 };
5389
5390 #define set_power_wells(power_domains, __power_wells) ({ \
5391 (power_domains)->power_wells = (__power_wells); \
5392 (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \
5393 })
5394
5395 int intel_power_domains_init(struct drm_device *dev)
5396 {
5397 struct drm_i915_private *dev_priv = dev->dev_private;
5398 struct i915_power_domains *power_domains = &dev_priv->power_domains;
5399
5400 mutex_init(&power_domains->lock);
5401
5402 /*
5403 * The enabling order will be from lower to higher indexed wells,
5404 * the disabling order is reversed.
5405 */
5406 if (IS_HASWELL(dev)) {
5407 set_power_wells(power_domains, hsw_power_wells);
5408 hsw_pwr = power_domains;
5409 } else if (IS_BROADWELL(dev)) {
5410 set_power_wells(power_domains, bdw_power_wells);
5411 hsw_pwr = power_domains;
5412 } else {
5413 set_power_wells(power_domains, i9xx_always_on_power_well);
5414 }
5415
5416 return 0;
5417 }
5418
5419 void intel_power_domains_remove(struct drm_device *dev)
5420 {
5421 hsw_pwr = NULL;
5422 }
5423
5424 static void intel_power_domains_resume(struct drm_device *dev)
5425 {
5426 struct drm_i915_private *dev_priv = dev->dev_private;
5427 struct i915_power_domains *power_domains = &dev_priv->power_domains;
5428 struct i915_power_well *power_well;
5429 int i;
5430
5431 mutex_lock(&power_domains->lock);
5432 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
5433 if (power_well->set)
5434 power_well->set(dev, power_well, power_well->count > 0);
5435 }
5436 mutex_unlock(&power_domains->lock);
5437 }
5438
5439 /*
5440 * Starting with Haswell, we have a "Power Down Well" that can be turned off
5441 * when not needed anymore. We have 4 registers that can request the power well
5442 * to be enabled, and it will only be disabled if none of the registers is
5443 * requesting it to be enabled.
5444 */
5445 void intel_power_domains_init_hw(struct drm_device *dev)
5446 {
5447 struct drm_i915_private *dev_priv = dev->dev_private;
5448
5449 /* For now, we need the power well to be always enabled. */
5450 intel_display_set_init_power(dev, true);
5451 intel_power_domains_resume(dev);
5452
5453 if (!(IS_HASWELL(dev) || IS_BROADWELL(dev)))
5454 return;
5455
5456 /* We're taking over the BIOS, so clear any requests made by it since
5457 * the driver is in charge now. */
5458 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
5459 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
5460 }
5461
5462 /* Disables PC8 so we can use the GMBUS and DP AUX interrupts. */
5463 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)
5464 {
5465 hsw_disable_package_c8(dev_priv);
5466 }
5467
5468 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)
5469 {
5470 hsw_enable_package_c8(dev_priv);
5471 }
5472
5473 void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
5474 {
5475 struct drm_device *dev = dev_priv->dev;
5476 struct device *device = &dev->pdev->dev;
5477
5478 if (!HAS_RUNTIME_PM(dev))
5479 return;
5480
5481 pm_runtime_get_sync(device);
5482 WARN(dev_priv->pm.suspended, "Device still suspended.\n");
5483 }
5484
5485 void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
5486 {
5487 struct drm_device *dev = dev_priv->dev;
5488 struct device *device = &dev->pdev->dev;
5489
5490 if (!HAS_RUNTIME_PM(dev))
5491 return;
5492
5493 pm_runtime_mark_last_busy(device);
5494 pm_runtime_put_autosuspend(device);
5495 }
5496
5497 void intel_init_runtime_pm(struct drm_i915_private *dev_priv)
5498 {
5499 struct drm_device *dev = dev_priv->dev;
5500 struct device *device = &dev->pdev->dev;
5501
5502 dev_priv->pm.suspended = false;
5503
5504 if (!HAS_RUNTIME_PM(dev))
5505 return;
5506
5507 pm_runtime_set_active(device);
5508
5509 pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
5510 pm_runtime_mark_last_busy(device);
5511 pm_runtime_use_autosuspend(device);
5512 }
5513
5514 void intel_fini_runtime_pm(struct drm_i915_private *dev_priv)
5515 {
5516 struct drm_device *dev = dev_priv->dev;
5517 struct device *device = &dev->pdev->dev;
5518
5519 if (!HAS_RUNTIME_PM(dev))
5520 return;
5521
5522 /* Make sure we're not suspended first. */
5523 pm_runtime_get_sync(device);
5524 pm_runtime_disable(device);
5525 }
5526
5527 /* Set up chip specific power management-related functions */
5528 void intel_init_pm(struct drm_device *dev)
5529 {
5530 struct drm_i915_private *dev_priv = dev->dev_private;
5531
5532 if (HAS_FBC(dev)) {
5533 if (INTEL_INFO(dev)->gen >= 7) {
5534 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
5535 dev_priv->display.enable_fbc = gen7_enable_fbc;
5536 dev_priv->display.disable_fbc = ironlake_disable_fbc;
5537 } else if (INTEL_INFO(dev)->gen >= 5) {
5538 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
5539 dev_priv->display.enable_fbc = ironlake_enable_fbc;
5540 dev_priv->display.disable_fbc = ironlake_disable_fbc;
5541 } else if (IS_GM45(dev)) {
5542 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5543 dev_priv->display.enable_fbc = g4x_enable_fbc;
5544 dev_priv->display.disable_fbc = g4x_disable_fbc;
5545 } else {
5546 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5547 dev_priv->display.enable_fbc = i8xx_enable_fbc;
5548 dev_priv->display.disable_fbc = i8xx_disable_fbc;
5549
5550 /* This value was pulled out of someone's hat */
5551 I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);
5552 }
5553 }
5554
5555 /* For cxsr */
5556 if (IS_PINEVIEW(dev))
5557 i915_pineview_get_mem_freq(dev);
5558 else if (IS_GEN5(dev))
5559 i915_ironlake_get_mem_freq(dev);
5560
5561 /* For FIFO watermark updates */
5562 if (HAS_PCH_SPLIT(dev)) {
5563 intel_setup_wm_latency(dev);
5564
5565 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
5566 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
5567 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
5568 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
5569 dev_priv->display.update_wm = ilk_update_wm;
5570 dev_priv->display.update_sprite_wm = ilk_update_sprite_wm;
5571 } else {
5572 DRM_DEBUG_KMS("Failed to read display plane latency. "
5573 "Disable CxSR\n");
5574 }
5575
5576 if (IS_GEN5(dev))
5577 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
5578 else if (IS_GEN6(dev))
5579 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
5580 else if (IS_IVYBRIDGE(dev))
5581 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
5582 else if (IS_HASWELL(dev))
5583 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
5584 else if (INTEL_INFO(dev)->gen == 8)
5585 dev_priv->display.init_clock_gating = gen8_init_clock_gating;
5586 } else if (IS_VALLEYVIEW(dev)) {
5587 dev_priv->display.update_wm = valleyview_update_wm;
5588 dev_priv->display.init_clock_gating =
5589 valleyview_init_clock_gating;
5590 } else if (IS_PINEVIEW(dev)) {
5591 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5592 dev_priv->is_ddr3,
5593 dev_priv->fsb_freq,
5594 dev_priv->mem_freq)) {
5595 DRM_INFO("failed to find known CxSR latency "
5596 "(found ddr%s fsb freq %d, mem freq %d), "
5597 "disabling CxSR\n",
5598 (dev_priv->is_ddr3 == 1) ? "3" : "2",
5599 dev_priv->fsb_freq, dev_priv->mem_freq);
5600 /* Disable CxSR and never update its watermark again */
5601 pineview_disable_cxsr(dev);
5602 dev_priv->display.update_wm = NULL;
5603 } else
5604 dev_priv->display.update_wm = pineview_update_wm;
5605 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
5606 } else if (IS_G4X(dev)) {
5607 dev_priv->display.update_wm = g4x_update_wm;
5608 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
5609 } else if (IS_GEN4(dev)) {
5610 dev_priv->display.update_wm = i965_update_wm;
5611 if (IS_CRESTLINE(dev))
5612 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
5613 else if (IS_BROADWATER(dev))
5614 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
5615 } else if (IS_GEN3(dev)) {
5616 dev_priv->display.update_wm = i9xx_update_wm;
5617 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5618 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
5619 } else if (IS_GEN2(dev)) {
5620 if (INTEL_INFO(dev)->num_pipes == 1) {
5621 dev_priv->display.update_wm = i845_update_wm;
5622 dev_priv->display.get_fifo_size = i845_get_fifo_size;
5623 } else {
5624 dev_priv->display.update_wm = i9xx_update_wm;
5625 dev_priv->display.get_fifo_size = i830_get_fifo_size;
5626 }
5627
5628 if (IS_I85X(dev) || IS_I865G(dev))
5629 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
5630 else
5631 dev_priv->display.init_clock_gating = i830_init_clock_gating;
5632 } else {
5633 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
5634 }
5635 }
5636
5637 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
5638 {
5639 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5640
5641 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
5642 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
5643 return -EAGAIN;
5644 }
5645
5646 I915_WRITE(GEN6_PCODE_DATA, *val);
5647 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
5648
5649 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
5650 500)) {
5651 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
5652 return -ETIMEDOUT;
5653 }
5654
5655 *val = I915_READ(GEN6_PCODE_DATA);
5656 I915_WRITE(GEN6_PCODE_DATA, 0);
5657
5658 return 0;
5659 }
5660
5661 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
5662 {
5663 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5664
5665 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
5666 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
5667 return -EAGAIN;
5668 }
5669
5670 I915_WRITE(GEN6_PCODE_DATA, val);
5671 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
5672
5673 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
5674 500)) {
5675 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
5676 return -ETIMEDOUT;
5677 }
5678
5679 I915_WRITE(GEN6_PCODE_DATA, 0);
5680
5681 return 0;
5682 }
5683
5684 int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val)
5685 {
5686 int div;
5687
5688 /* 4 x czclk */
5689 switch (dev_priv->mem_freq) {
5690 case 800:
5691 div = 10;
5692 break;
5693 case 1066:
5694 div = 12;
5695 break;
5696 case 1333:
5697 div = 16;
5698 break;
5699 default:
5700 return -1;
5701 }
5702
5703 return DIV_ROUND_CLOSEST(dev_priv->mem_freq * (val + 6 - 0xbd), 4 * div);
5704 }
5705
5706 int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val)
5707 {
5708 int mul;
5709
5710 /* 4 x czclk */
5711 switch (dev_priv->mem_freq) {
5712 case 800:
5713 mul = 10;
5714 break;
5715 case 1066:
5716 mul = 12;
5717 break;
5718 case 1333:
5719 mul = 16;
5720 break;
5721 default:
5722 return -1;
5723 }
5724
5725 return DIV_ROUND_CLOSEST(4 * mul * val, dev_priv->mem_freq) + 0xbd - 6;
5726 }
5727
5728 void intel_pm_setup(struct drm_device *dev)
5729 {
5730 struct drm_i915_private *dev_priv = dev->dev_private;
5731
5732 mutex_init(&dev_priv->rps.hw_lock);
5733
5734 mutex_init(&dev_priv->pc8.lock);
5735 dev_priv->pc8.requirements_met = false;
5736 dev_priv->pc8.gpu_idle = false;
5737 dev_priv->pc8.irqs_disabled = false;
5738 dev_priv->pc8.enabled = false;
5739 dev_priv->pc8.disable_count = 2; /* requirements_met + gpu_idle */
5740 INIT_DELAYED_WORK(&dev_priv->pc8.enable_work, hsw_enable_pc8_work);
5741 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
5742 intel_gen6_powersave_work);
5743 }
Linux kernel - Deliverables
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