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Merge tag 'mvebu-fixes-4.5-2' of git://git.infradead.org/linux-mvebu into fixes
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_pm.c
1 /*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28 #include <linux/cpufreq.h>
29 #include "i915_drv.h"
30 #include "intel_drv.h"
31 #include "../../../platform/x86/intel_ips.h"
32 #include <linux/module.h>
33
34 /**
35 * RC6 is a special power stage which allows the GPU to enter an very
36 * low-voltage mode when idle, using down to 0V while at this stage. This
37 * stage is entered automatically when the GPU is idle when RC6 support is
38 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
39 *
40 * There are different RC6 modes available in Intel GPU, which differentiate
41 * among each other with the latency required to enter and leave RC6 and
42 * voltage consumed by the GPU in different states.
43 *
44 * The combination of the following flags define which states GPU is allowed
45 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
46 * RC6pp is deepest RC6. Their support by hardware varies according to the
47 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
48 * which brings the most power savings; deeper states save more power, but
49 * require higher latency to switch to and wake up.
50 */
51 #define INTEL_RC6_ENABLE (1<<0)
52 #define INTEL_RC6p_ENABLE (1<<1)
53 #define INTEL_RC6pp_ENABLE (1<<2)
54
55 static void bxt_init_clock_gating(struct drm_device *dev)
56 {
57 struct drm_i915_private *dev_priv = dev->dev_private;
58
59 /* WaDisableSDEUnitClockGating:bxt */
60 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
61 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
62
63 /*
64 * FIXME:
65 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
66 */
67 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
68 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
69
70 /*
71 * Wa: Backlight PWM may stop in the asserted state, causing backlight
72 * to stay fully on.
73 */
74 if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
75 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
76 PWM1_GATING_DIS | PWM2_GATING_DIS);
77 }
78
79 static void i915_pineview_get_mem_freq(struct drm_device *dev)
80 {
81 struct drm_i915_private *dev_priv = dev->dev_private;
82 u32 tmp;
83
84 tmp = I915_READ(CLKCFG);
85
86 switch (tmp & CLKCFG_FSB_MASK) {
87 case CLKCFG_FSB_533:
88 dev_priv->fsb_freq = 533; /* 133*4 */
89 break;
90 case CLKCFG_FSB_800:
91 dev_priv->fsb_freq = 800; /* 200*4 */
92 break;
93 case CLKCFG_FSB_667:
94 dev_priv->fsb_freq = 667; /* 167*4 */
95 break;
96 case CLKCFG_FSB_400:
97 dev_priv->fsb_freq = 400; /* 100*4 */
98 break;
99 }
100
101 switch (tmp & CLKCFG_MEM_MASK) {
102 case CLKCFG_MEM_533:
103 dev_priv->mem_freq = 533;
104 break;
105 case CLKCFG_MEM_667:
106 dev_priv->mem_freq = 667;
107 break;
108 case CLKCFG_MEM_800:
109 dev_priv->mem_freq = 800;
110 break;
111 }
112
113 /* detect pineview DDR3 setting */
114 tmp = I915_READ(CSHRDDR3CTL);
115 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
116 }
117
118 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
119 {
120 struct drm_i915_private *dev_priv = dev->dev_private;
121 u16 ddrpll, csipll;
122
123 ddrpll = I915_READ16(DDRMPLL1);
124 csipll = I915_READ16(CSIPLL0);
125
126 switch (ddrpll & 0xff) {
127 case 0xc:
128 dev_priv->mem_freq = 800;
129 break;
130 case 0x10:
131 dev_priv->mem_freq = 1066;
132 break;
133 case 0x14:
134 dev_priv->mem_freq = 1333;
135 break;
136 case 0x18:
137 dev_priv->mem_freq = 1600;
138 break;
139 default:
140 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
141 ddrpll & 0xff);
142 dev_priv->mem_freq = 0;
143 break;
144 }
145
146 dev_priv->ips.r_t = dev_priv->mem_freq;
147
148 switch (csipll & 0x3ff) {
149 case 0x00c:
150 dev_priv->fsb_freq = 3200;
151 break;
152 case 0x00e:
153 dev_priv->fsb_freq = 3733;
154 break;
155 case 0x010:
156 dev_priv->fsb_freq = 4266;
157 break;
158 case 0x012:
159 dev_priv->fsb_freq = 4800;
160 break;
161 case 0x014:
162 dev_priv->fsb_freq = 5333;
163 break;
164 case 0x016:
165 dev_priv->fsb_freq = 5866;
166 break;
167 case 0x018:
168 dev_priv->fsb_freq = 6400;
169 break;
170 default:
171 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
172 csipll & 0x3ff);
173 dev_priv->fsb_freq = 0;
174 break;
175 }
176
177 if (dev_priv->fsb_freq == 3200) {
178 dev_priv->ips.c_m = 0;
179 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
180 dev_priv->ips.c_m = 1;
181 } else {
182 dev_priv->ips.c_m = 2;
183 }
184 }
185
186 static const struct cxsr_latency cxsr_latency_table[] = {
187 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
188 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
189 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
190 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
191 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
192
193 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
194 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
195 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
196 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
197 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
198
199 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
200 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
201 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
202 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
203 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
204
205 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
206 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
207 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
208 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
209 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
210
211 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
212 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
213 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
214 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
215 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
216
217 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
218 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
219 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
220 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
221 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
222 };
223
224 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
225 int is_ddr3,
226 int fsb,
227 int mem)
228 {
229 const struct cxsr_latency *latency;
230 int i;
231
232 if (fsb == 0 || mem == 0)
233 return NULL;
234
235 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
236 latency = &cxsr_latency_table[i];
237 if (is_desktop == latency->is_desktop &&
238 is_ddr3 == latency->is_ddr3 &&
239 fsb == latency->fsb_freq && mem == latency->mem_freq)
240 return latency;
241 }
242
243 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
244
245 return NULL;
246 }
247
248 static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
249 {
250 u32 val;
251
252 mutex_lock(&dev_priv->rps.hw_lock);
253
254 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
255 if (enable)
256 val &= ~FORCE_DDR_HIGH_FREQ;
257 else
258 val |= FORCE_DDR_HIGH_FREQ;
259 val &= ~FORCE_DDR_LOW_FREQ;
260 val |= FORCE_DDR_FREQ_REQ_ACK;
261 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
262
263 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
264 FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
265 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
266
267 mutex_unlock(&dev_priv->rps.hw_lock);
268 }
269
270 static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
271 {
272 u32 val;
273
274 mutex_lock(&dev_priv->rps.hw_lock);
275
276 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
277 if (enable)
278 val |= DSP_MAXFIFO_PM5_ENABLE;
279 else
280 val &= ~DSP_MAXFIFO_PM5_ENABLE;
281 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
282
283 mutex_unlock(&dev_priv->rps.hw_lock);
284 }
285
286 #define FW_WM(value, plane) \
287 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
288
289 void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
290 {
291 struct drm_device *dev = dev_priv->dev;
292 u32 val;
293
294 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
295 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
296 POSTING_READ(FW_BLC_SELF_VLV);
297 dev_priv->wm.vlv.cxsr = enable;
298 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
299 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
300 POSTING_READ(FW_BLC_SELF);
301 } else if (IS_PINEVIEW(dev)) {
302 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
303 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
304 I915_WRITE(DSPFW3, val);
305 POSTING_READ(DSPFW3);
306 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
307 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
308 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
309 I915_WRITE(FW_BLC_SELF, val);
310 POSTING_READ(FW_BLC_SELF);
311 } else if (IS_I915GM(dev)) {
312 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
313 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
314 I915_WRITE(INSTPM, val);
315 POSTING_READ(INSTPM);
316 } else {
317 return;
318 }
319
320 DRM_DEBUG_KMS("memory self-refresh is %s\n",
321 enable ? "enabled" : "disabled");
322 }
323
324
325 /*
326 * Latency for FIFO fetches is dependent on several factors:
327 * - memory configuration (speed, channels)
328 * - chipset
329 * - current MCH state
330 * It can be fairly high in some situations, so here we assume a fairly
331 * pessimal value. It's a tradeoff between extra memory fetches (if we
332 * set this value too high, the FIFO will fetch frequently to stay full)
333 * and power consumption (set it too low to save power and we might see
334 * FIFO underruns and display "flicker").
335 *
336 * A value of 5us seems to be a good balance; safe for very low end
337 * platforms but not overly aggressive on lower latency configs.
338 */
339 static const int pessimal_latency_ns = 5000;
340
341 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
342 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
343
344 static int vlv_get_fifo_size(struct drm_device *dev,
345 enum pipe pipe, int plane)
346 {
347 struct drm_i915_private *dev_priv = dev->dev_private;
348 int sprite0_start, sprite1_start, size;
349
350 switch (pipe) {
351 uint32_t dsparb, dsparb2, dsparb3;
352 case PIPE_A:
353 dsparb = I915_READ(DSPARB);
354 dsparb2 = I915_READ(DSPARB2);
355 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
356 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
357 break;
358 case PIPE_B:
359 dsparb = I915_READ(DSPARB);
360 dsparb2 = I915_READ(DSPARB2);
361 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
362 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
363 break;
364 case PIPE_C:
365 dsparb2 = I915_READ(DSPARB2);
366 dsparb3 = I915_READ(DSPARB3);
367 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
368 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
369 break;
370 default:
371 return 0;
372 }
373
374 switch (plane) {
375 case 0:
376 size = sprite0_start;
377 break;
378 case 1:
379 size = sprite1_start - sprite0_start;
380 break;
381 case 2:
382 size = 512 - 1 - sprite1_start;
383 break;
384 default:
385 return 0;
386 }
387
388 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
389 pipe_name(pipe), plane == 0 ? "primary" : "sprite",
390 plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
391 size);
392
393 return size;
394 }
395
396 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
397 {
398 struct drm_i915_private *dev_priv = dev->dev_private;
399 uint32_t dsparb = I915_READ(DSPARB);
400 int size;
401
402 size = dsparb & 0x7f;
403 if (plane)
404 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
405
406 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
407 plane ? "B" : "A", size);
408
409 return size;
410 }
411
412 static int i830_get_fifo_size(struct drm_device *dev, int plane)
413 {
414 struct drm_i915_private *dev_priv = dev->dev_private;
415 uint32_t dsparb = I915_READ(DSPARB);
416 int size;
417
418 size = dsparb & 0x1ff;
419 if (plane)
420 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
421 size >>= 1; /* Convert to cachelines */
422
423 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
424 plane ? "B" : "A", size);
425
426 return size;
427 }
428
429 static int i845_get_fifo_size(struct drm_device *dev, int plane)
430 {
431 struct drm_i915_private *dev_priv = dev->dev_private;
432 uint32_t dsparb = I915_READ(DSPARB);
433 int size;
434
435 size = dsparb & 0x7f;
436 size >>= 2; /* Convert to cachelines */
437
438 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
439 plane ? "B" : "A",
440 size);
441
442 return size;
443 }
444
445 /* Pineview has different values for various configs */
446 static const struct intel_watermark_params pineview_display_wm = {
447 .fifo_size = PINEVIEW_DISPLAY_FIFO,
448 .max_wm = PINEVIEW_MAX_WM,
449 .default_wm = PINEVIEW_DFT_WM,
450 .guard_size = PINEVIEW_GUARD_WM,
451 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
452 };
453 static const struct intel_watermark_params pineview_display_hplloff_wm = {
454 .fifo_size = PINEVIEW_DISPLAY_FIFO,
455 .max_wm = PINEVIEW_MAX_WM,
456 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
457 .guard_size = PINEVIEW_GUARD_WM,
458 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
459 };
460 static const struct intel_watermark_params pineview_cursor_wm = {
461 .fifo_size = PINEVIEW_CURSOR_FIFO,
462 .max_wm = PINEVIEW_CURSOR_MAX_WM,
463 .default_wm = PINEVIEW_CURSOR_DFT_WM,
464 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
465 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
466 };
467 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
468 .fifo_size = PINEVIEW_CURSOR_FIFO,
469 .max_wm = PINEVIEW_CURSOR_MAX_WM,
470 .default_wm = PINEVIEW_CURSOR_DFT_WM,
471 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
472 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
473 };
474 static const struct intel_watermark_params g4x_wm_info = {
475 .fifo_size = G4X_FIFO_SIZE,
476 .max_wm = G4X_MAX_WM,
477 .default_wm = G4X_MAX_WM,
478 .guard_size = 2,
479 .cacheline_size = G4X_FIFO_LINE_SIZE,
480 };
481 static const struct intel_watermark_params g4x_cursor_wm_info = {
482 .fifo_size = I965_CURSOR_FIFO,
483 .max_wm = I965_CURSOR_MAX_WM,
484 .default_wm = I965_CURSOR_DFT_WM,
485 .guard_size = 2,
486 .cacheline_size = G4X_FIFO_LINE_SIZE,
487 };
488 static const struct intel_watermark_params valleyview_wm_info = {
489 .fifo_size = VALLEYVIEW_FIFO_SIZE,
490 .max_wm = VALLEYVIEW_MAX_WM,
491 .default_wm = VALLEYVIEW_MAX_WM,
492 .guard_size = 2,
493 .cacheline_size = G4X_FIFO_LINE_SIZE,
494 };
495 static const struct intel_watermark_params valleyview_cursor_wm_info = {
496 .fifo_size = I965_CURSOR_FIFO,
497 .max_wm = VALLEYVIEW_CURSOR_MAX_WM,
498 .default_wm = I965_CURSOR_DFT_WM,
499 .guard_size = 2,
500 .cacheline_size = G4X_FIFO_LINE_SIZE,
501 };
502 static const struct intel_watermark_params i965_cursor_wm_info = {
503 .fifo_size = I965_CURSOR_FIFO,
504 .max_wm = I965_CURSOR_MAX_WM,
505 .default_wm = I965_CURSOR_DFT_WM,
506 .guard_size = 2,
507 .cacheline_size = I915_FIFO_LINE_SIZE,
508 };
509 static const struct intel_watermark_params i945_wm_info = {
510 .fifo_size = I945_FIFO_SIZE,
511 .max_wm = I915_MAX_WM,
512 .default_wm = 1,
513 .guard_size = 2,
514 .cacheline_size = I915_FIFO_LINE_SIZE,
515 };
516 static const struct intel_watermark_params i915_wm_info = {
517 .fifo_size = I915_FIFO_SIZE,
518 .max_wm = I915_MAX_WM,
519 .default_wm = 1,
520 .guard_size = 2,
521 .cacheline_size = I915_FIFO_LINE_SIZE,
522 };
523 static const struct intel_watermark_params i830_a_wm_info = {
524 .fifo_size = I855GM_FIFO_SIZE,
525 .max_wm = I915_MAX_WM,
526 .default_wm = 1,
527 .guard_size = 2,
528 .cacheline_size = I830_FIFO_LINE_SIZE,
529 };
530 static const struct intel_watermark_params i830_bc_wm_info = {
531 .fifo_size = I855GM_FIFO_SIZE,
532 .max_wm = I915_MAX_WM/2,
533 .default_wm = 1,
534 .guard_size = 2,
535 .cacheline_size = I830_FIFO_LINE_SIZE,
536 };
537 static const struct intel_watermark_params i845_wm_info = {
538 .fifo_size = I830_FIFO_SIZE,
539 .max_wm = I915_MAX_WM,
540 .default_wm = 1,
541 .guard_size = 2,
542 .cacheline_size = I830_FIFO_LINE_SIZE,
543 };
544
545 /**
546 * intel_calculate_wm - calculate watermark level
547 * @clock_in_khz: pixel clock
548 * @wm: chip FIFO params
549 * @pixel_size: display pixel size
550 * @latency_ns: memory latency for the platform
551 *
552 * Calculate the watermark level (the level at which the display plane will
553 * start fetching from memory again). Each chip has a different display
554 * FIFO size and allocation, so the caller needs to figure that out and pass
555 * in the correct intel_watermark_params structure.
556 *
557 * As the pixel clock runs, the FIFO will be drained at a rate that depends
558 * on the pixel size. When it reaches the watermark level, it'll start
559 * fetching FIFO line sized based chunks from memory until the FIFO fills
560 * past the watermark point. If the FIFO drains completely, a FIFO underrun
561 * will occur, and a display engine hang could result.
562 */
563 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
564 const struct intel_watermark_params *wm,
565 int fifo_size,
566 int pixel_size,
567 unsigned long latency_ns)
568 {
569 long entries_required, wm_size;
570
571 /*
572 * Note: we need to make sure we don't overflow for various clock &
573 * latency values.
574 * clocks go from a few thousand to several hundred thousand.
575 * latency is usually a few thousand
576 */
577 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
578 1000;
579 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
580
581 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
582
583 wm_size = fifo_size - (entries_required + wm->guard_size);
584
585 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
586
587 /* Don't promote wm_size to unsigned... */
588 if (wm_size > (long)wm->max_wm)
589 wm_size = wm->max_wm;
590 if (wm_size <= 0)
591 wm_size = wm->default_wm;
592
593 /*
594 * Bspec seems to indicate that the value shouldn't be lower than
595 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
596 * Lets go for 8 which is the burst size since certain platforms
597 * already use a hardcoded 8 (which is what the spec says should be
598 * done).
599 */
600 if (wm_size <= 8)
601 wm_size = 8;
602
603 return wm_size;
604 }
605
606 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
607 {
608 struct drm_crtc *crtc, *enabled = NULL;
609
610 for_each_crtc(dev, crtc) {
611 if (intel_crtc_active(crtc)) {
612 if (enabled)
613 return NULL;
614 enabled = crtc;
615 }
616 }
617
618 return enabled;
619 }
620
621 static void pineview_update_wm(struct drm_crtc *unused_crtc)
622 {
623 struct drm_device *dev = unused_crtc->dev;
624 struct drm_i915_private *dev_priv = dev->dev_private;
625 struct drm_crtc *crtc;
626 const struct cxsr_latency *latency;
627 u32 reg;
628 unsigned long wm;
629
630 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
631 dev_priv->fsb_freq, dev_priv->mem_freq);
632 if (!latency) {
633 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
634 intel_set_memory_cxsr(dev_priv, false);
635 return;
636 }
637
638 crtc = single_enabled_crtc(dev);
639 if (crtc) {
640 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
641 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
642 int clock = adjusted_mode->crtc_clock;
643
644 /* Display SR */
645 wm = intel_calculate_wm(clock, &pineview_display_wm,
646 pineview_display_wm.fifo_size,
647 pixel_size, latency->display_sr);
648 reg = I915_READ(DSPFW1);
649 reg &= ~DSPFW_SR_MASK;
650 reg |= FW_WM(wm, SR);
651 I915_WRITE(DSPFW1, reg);
652 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
653
654 /* cursor SR */
655 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
656 pineview_display_wm.fifo_size,
657 pixel_size, latency->cursor_sr);
658 reg = I915_READ(DSPFW3);
659 reg &= ~DSPFW_CURSOR_SR_MASK;
660 reg |= FW_WM(wm, CURSOR_SR);
661 I915_WRITE(DSPFW3, reg);
662
663 /* Display HPLL off SR */
664 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
665 pineview_display_hplloff_wm.fifo_size,
666 pixel_size, latency->display_hpll_disable);
667 reg = I915_READ(DSPFW3);
668 reg &= ~DSPFW_HPLL_SR_MASK;
669 reg |= FW_WM(wm, HPLL_SR);
670 I915_WRITE(DSPFW3, reg);
671
672 /* cursor HPLL off SR */
673 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
674 pineview_display_hplloff_wm.fifo_size,
675 pixel_size, latency->cursor_hpll_disable);
676 reg = I915_READ(DSPFW3);
677 reg &= ~DSPFW_HPLL_CURSOR_MASK;
678 reg |= FW_WM(wm, HPLL_CURSOR);
679 I915_WRITE(DSPFW3, reg);
680 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
681
682 intel_set_memory_cxsr(dev_priv, true);
683 } else {
684 intel_set_memory_cxsr(dev_priv, false);
685 }
686 }
687
688 static bool g4x_compute_wm0(struct drm_device *dev,
689 int plane,
690 const struct intel_watermark_params *display,
691 int display_latency_ns,
692 const struct intel_watermark_params *cursor,
693 int cursor_latency_ns,
694 int *plane_wm,
695 int *cursor_wm)
696 {
697 struct drm_crtc *crtc;
698 const struct drm_display_mode *adjusted_mode;
699 int htotal, hdisplay, clock, pixel_size;
700 int line_time_us, line_count;
701 int entries, tlb_miss;
702
703 crtc = intel_get_crtc_for_plane(dev, plane);
704 if (!intel_crtc_active(crtc)) {
705 *cursor_wm = cursor->guard_size;
706 *plane_wm = display->guard_size;
707 return false;
708 }
709
710 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
711 clock = adjusted_mode->crtc_clock;
712 htotal = adjusted_mode->crtc_htotal;
713 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
714 pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
715
716 /* Use the small buffer method to calculate plane watermark */
717 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
718 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
719 if (tlb_miss > 0)
720 entries += tlb_miss;
721 entries = DIV_ROUND_UP(entries, display->cacheline_size);
722 *plane_wm = entries + display->guard_size;
723 if (*plane_wm > (int)display->max_wm)
724 *plane_wm = display->max_wm;
725
726 /* Use the large buffer method to calculate cursor watermark */
727 line_time_us = max(htotal * 1000 / clock, 1);
728 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
729 entries = line_count * crtc->cursor->state->crtc_w * pixel_size;
730 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
731 if (tlb_miss > 0)
732 entries += tlb_miss;
733 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
734 *cursor_wm = entries + cursor->guard_size;
735 if (*cursor_wm > (int)cursor->max_wm)
736 *cursor_wm = (int)cursor->max_wm;
737
738 return true;
739 }
740
741 /*
742 * Check the wm result.
743 *
744 * If any calculated watermark values is larger than the maximum value that
745 * can be programmed into the associated watermark register, that watermark
746 * must be disabled.
747 */
748 static bool g4x_check_srwm(struct drm_device *dev,
749 int display_wm, int cursor_wm,
750 const struct intel_watermark_params *display,
751 const struct intel_watermark_params *cursor)
752 {
753 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
754 display_wm, cursor_wm);
755
756 if (display_wm > display->max_wm) {
757 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
758 display_wm, display->max_wm);
759 return false;
760 }
761
762 if (cursor_wm > cursor->max_wm) {
763 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
764 cursor_wm, cursor->max_wm);
765 return false;
766 }
767
768 if (!(display_wm || cursor_wm)) {
769 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
770 return false;
771 }
772
773 return true;
774 }
775
776 static bool g4x_compute_srwm(struct drm_device *dev,
777 int plane,
778 int latency_ns,
779 const struct intel_watermark_params *display,
780 const struct intel_watermark_params *cursor,
781 int *display_wm, int *cursor_wm)
782 {
783 struct drm_crtc *crtc;
784 const struct drm_display_mode *adjusted_mode;
785 int hdisplay, htotal, pixel_size, clock;
786 unsigned long line_time_us;
787 int line_count, line_size;
788 int small, large;
789 int entries;
790
791 if (!latency_ns) {
792 *display_wm = *cursor_wm = 0;
793 return false;
794 }
795
796 crtc = intel_get_crtc_for_plane(dev, plane);
797 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
798 clock = adjusted_mode->crtc_clock;
799 htotal = adjusted_mode->crtc_htotal;
800 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
801 pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
802
803 line_time_us = max(htotal * 1000 / clock, 1);
804 line_count = (latency_ns / line_time_us + 1000) / 1000;
805 line_size = hdisplay * pixel_size;
806
807 /* Use the minimum of the small and large buffer method for primary */
808 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
809 large = line_count * line_size;
810
811 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
812 *display_wm = entries + display->guard_size;
813
814 /* calculate the self-refresh watermark for display cursor */
815 entries = line_count * pixel_size * crtc->cursor->state->crtc_w;
816 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
817 *cursor_wm = entries + cursor->guard_size;
818
819 return g4x_check_srwm(dev,
820 *display_wm, *cursor_wm,
821 display, cursor);
822 }
823
824 #define FW_WM_VLV(value, plane) \
825 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
826
827 static void vlv_write_wm_values(struct intel_crtc *crtc,
828 const struct vlv_wm_values *wm)
829 {
830 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
831 enum pipe pipe = crtc->pipe;
832
833 I915_WRITE(VLV_DDL(pipe),
834 (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
835 (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
836 (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
837 (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
838
839 I915_WRITE(DSPFW1,
840 FW_WM(wm->sr.plane, SR) |
841 FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
842 FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
843 FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
844 I915_WRITE(DSPFW2,
845 FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
846 FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
847 FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
848 I915_WRITE(DSPFW3,
849 FW_WM(wm->sr.cursor, CURSOR_SR));
850
851 if (IS_CHERRYVIEW(dev_priv)) {
852 I915_WRITE(DSPFW7_CHV,
853 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
854 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
855 I915_WRITE(DSPFW8_CHV,
856 FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
857 FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
858 I915_WRITE(DSPFW9_CHV,
859 FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
860 FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
861 I915_WRITE(DSPHOWM,
862 FW_WM(wm->sr.plane >> 9, SR_HI) |
863 FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
864 FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
865 FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
866 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
867 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
868 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
869 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
870 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
871 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
872 } else {
873 I915_WRITE(DSPFW7,
874 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
875 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
876 I915_WRITE(DSPHOWM,
877 FW_WM(wm->sr.plane >> 9, SR_HI) |
878 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
879 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
880 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
881 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
882 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
883 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
884 }
885
886 /* zero (unused) WM1 watermarks */
887 I915_WRITE(DSPFW4, 0);
888 I915_WRITE(DSPFW5, 0);
889 I915_WRITE(DSPFW6, 0);
890 I915_WRITE(DSPHOWM1, 0);
891
892 POSTING_READ(DSPFW1);
893 }
894
895 #undef FW_WM_VLV
896
897 enum vlv_wm_level {
898 VLV_WM_LEVEL_PM2,
899 VLV_WM_LEVEL_PM5,
900 VLV_WM_LEVEL_DDR_DVFS,
901 };
902
903 /* latency must be in 0.1us units. */
904 static unsigned int vlv_wm_method2(unsigned int pixel_rate,
905 unsigned int pipe_htotal,
906 unsigned int horiz_pixels,
907 unsigned int bytes_per_pixel,
908 unsigned int latency)
909 {
910 unsigned int ret;
911
912 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
913 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
914 ret = DIV_ROUND_UP(ret, 64);
915
916 return ret;
917 }
918
919 static void vlv_setup_wm_latency(struct drm_device *dev)
920 {
921 struct drm_i915_private *dev_priv = dev->dev_private;
922
923 /* all latencies in usec */
924 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
925
926 dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
927
928 if (IS_CHERRYVIEW(dev_priv)) {
929 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
930 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
931
932 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
933 }
934 }
935
936 static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
937 struct intel_crtc *crtc,
938 const struct intel_plane_state *state,
939 int level)
940 {
941 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
942 int clock, htotal, pixel_size, width, wm;
943
944 if (dev_priv->wm.pri_latency[level] == 0)
945 return USHRT_MAX;
946
947 if (!state->visible)
948 return 0;
949
950 pixel_size = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
951 clock = crtc->config->base.adjusted_mode.crtc_clock;
952 htotal = crtc->config->base.adjusted_mode.crtc_htotal;
953 width = crtc->config->pipe_src_w;
954 if (WARN_ON(htotal == 0))
955 htotal = 1;
956
957 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
958 /*
959 * FIXME the formula gives values that are
960 * too big for the cursor FIFO, and hence we
961 * would never be able to use cursors. For
962 * now just hardcode the watermark.
963 */
964 wm = 63;
965 } else {
966 wm = vlv_wm_method2(clock, htotal, width, pixel_size,
967 dev_priv->wm.pri_latency[level] * 10);
968 }
969
970 return min_t(int, wm, USHRT_MAX);
971 }
972
973 static void vlv_compute_fifo(struct intel_crtc *crtc)
974 {
975 struct drm_device *dev = crtc->base.dev;
976 struct vlv_wm_state *wm_state = &crtc->wm_state;
977 struct intel_plane *plane;
978 unsigned int total_rate = 0;
979 const int fifo_size = 512 - 1;
980 int fifo_extra, fifo_left = fifo_size;
981
982 for_each_intel_plane_on_crtc(dev, crtc, plane) {
983 struct intel_plane_state *state =
984 to_intel_plane_state(plane->base.state);
985
986 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
987 continue;
988
989 if (state->visible) {
990 wm_state->num_active_planes++;
991 total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
992 }
993 }
994
995 for_each_intel_plane_on_crtc(dev, crtc, plane) {
996 struct intel_plane_state *state =
997 to_intel_plane_state(plane->base.state);
998 unsigned int rate;
999
1000 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1001 plane->wm.fifo_size = 63;
1002 continue;
1003 }
1004
1005 if (!state->visible) {
1006 plane->wm.fifo_size = 0;
1007 continue;
1008 }
1009
1010 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1011 plane->wm.fifo_size = fifo_size * rate / total_rate;
1012 fifo_left -= plane->wm.fifo_size;
1013 }
1014
1015 fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1016
1017 /* spread the remainder evenly */
1018 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1019 int plane_extra;
1020
1021 if (fifo_left == 0)
1022 break;
1023
1024 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1025 continue;
1026
1027 /* give it all to the first plane if none are active */
1028 if (plane->wm.fifo_size == 0 &&
1029 wm_state->num_active_planes)
1030 continue;
1031
1032 plane_extra = min(fifo_extra, fifo_left);
1033 plane->wm.fifo_size += plane_extra;
1034 fifo_left -= plane_extra;
1035 }
1036
1037 WARN_ON(fifo_left != 0);
1038 }
1039
1040 static void vlv_invert_wms(struct intel_crtc *crtc)
1041 {
1042 struct vlv_wm_state *wm_state = &crtc->wm_state;
1043 int level;
1044
1045 for (level = 0; level < wm_state->num_levels; level++) {
1046 struct drm_device *dev = crtc->base.dev;
1047 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1048 struct intel_plane *plane;
1049
1050 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1051 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1052
1053 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1054 switch (plane->base.type) {
1055 int sprite;
1056 case DRM_PLANE_TYPE_CURSOR:
1057 wm_state->wm[level].cursor = plane->wm.fifo_size -
1058 wm_state->wm[level].cursor;
1059 break;
1060 case DRM_PLANE_TYPE_PRIMARY:
1061 wm_state->wm[level].primary = plane->wm.fifo_size -
1062 wm_state->wm[level].primary;
1063 break;
1064 case DRM_PLANE_TYPE_OVERLAY:
1065 sprite = plane->plane;
1066 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1067 wm_state->wm[level].sprite[sprite];
1068 break;
1069 }
1070 }
1071 }
1072 }
1073
1074 static void vlv_compute_wm(struct intel_crtc *crtc)
1075 {
1076 struct drm_device *dev = crtc->base.dev;
1077 struct vlv_wm_state *wm_state = &crtc->wm_state;
1078 struct intel_plane *plane;
1079 int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1080 int level;
1081
1082 memset(wm_state, 0, sizeof(*wm_state));
1083
1084 wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
1085 wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
1086
1087 wm_state->num_active_planes = 0;
1088
1089 vlv_compute_fifo(crtc);
1090
1091 if (wm_state->num_active_planes != 1)
1092 wm_state->cxsr = false;
1093
1094 if (wm_state->cxsr) {
1095 for (level = 0; level < wm_state->num_levels; level++) {
1096 wm_state->sr[level].plane = sr_fifo_size;
1097 wm_state->sr[level].cursor = 63;
1098 }
1099 }
1100
1101 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1102 struct intel_plane_state *state =
1103 to_intel_plane_state(plane->base.state);
1104
1105 if (!state->visible)
1106 continue;
1107
1108 /* normal watermarks */
1109 for (level = 0; level < wm_state->num_levels; level++) {
1110 int wm = vlv_compute_wm_level(plane, crtc, state, level);
1111 int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1112
1113 /* hack */
1114 if (WARN_ON(level == 0 && wm > max_wm))
1115 wm = max_wm;
1116
1117 if (wm > plane->wm.fifo_size)
1118 break;
1119
1120 switch (plane->base.type) {
1121 int sprite;
1122 case DRM_PLANE_TYPE_CURSOR:
1123 wm_state->wm[level].cursor = wm;
1124 break;
1125 case DRM_PLANE_TYPE_PRIMARY:
1126 wm_state->wm[level].primary = wm;
1127 break;
1128 case DRM_PLANE_TYPE_OVERLAY:
1129 sprite = plane->plane;
1130 wm_state->wm[level].sprite[sprite] = wm;
1131 break;
1132 }
1133 }
1134
1135 wm_state->num_levels = level;
1136
1137 if (!wm_state->cxsr)
1138 continue;
1139
1140 /* maxfifo watermarks */
1141 switch (plane->base.type) {
1142 int sprite, level;
1143 case DRM_PLANE_TYPE_CURSOR:
1144 for (level = 0; level < wm_state->num_levels; level++)
1145 wm_state->sr[level].cursor =
1146 wm_state->wm[level].cursor;
1147 break;
1148 case DRM_PLANE_TYPE_PRIMARY:
1149 for (level = 0; level < wm_state->num_levels; level++)
1150 wm_state->sr[level].plane =
1151 min(wm_state->sr[level].plane,
1152 wm_state->wm[level].primary);
1153 break;
1154 case DRM_PLANE_TYPE_OVERLAY:
1155 sprite = plane->plane;
1156 for (level = 0; level < wm_state->num_levels; level++)
1157 wm_state->sr[level].plane =
1158 min(wm_state->sr[level].plane,
1159 wm_state->wm[level].sprite[sprite]);
1160 break;
1161 }
1162 }
1163
1164 /* clear any (partially) filled invalid levels */
1165 for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
1166 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1167 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1168 }
1169
1170 vlv_invert_wms(crtc);
1171 }
1172
1173 #define VLV_FIFO(plane, value) \
1174 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1175
1176 static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1177 {
1178 struct drm_device *dev = crtc->base.dev;
1179 struct drm_i915_private *dev_priv = to_i915(dev);
1180 struct intel_plane *plane;
1181 int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1182
1183 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1184 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1185 WARN_ON(plane->wm.fifo_size != 63);
1186 continue;
1187 }
1188
1189 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1190 sprite0_start = plane->wm.fifo_size;
1191 else if (plane->plane == 0)
1192 sprite1_start = sprite0_start + plane->wm.fifo_size;
1193 else
1194 fifo_size = sprite1_start + plane->wm.fifo_size;
1195 }
1196
1197 WARN_ON(fifo_size != 512 - 1);
1198
1199 DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1200 pipe_name(crtc->pipe), sprite0_start,
1201 sprite1_start, fifo_size);
1202
1203 switch (crtc->pipe) {
1204 uint32_t dsparb, dsparb2, dsparb3;
1205 case PIPE_A:
1206 dsparb = I915_READ(DSPARB);
1207 dsparb2 = I915_READ(DSPARB2);
1208
1209 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1210 VLV_FIFO(SPRITEB, 0xff));
1211 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1212 VLV_FIFO(SPRITEB, sprite1_start));
1213
1214 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1215 VLV_FIFO(SPRITEB_HI, 0x1));
1216 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1217 VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1218
1219 I915_WRITE(DSPARB, dsparb);
1220 I915_WRITE(DSPARB2, dsparb2);
1221 break;
1222 case PIPE_B:
1223 dsparb = I915_READ(DSPARB);
1224 dsparb2 = I915_READ(DSPARB2);
1225
1226 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1227 VLV_FIFO(SPRITED, 0xff));
1228 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1229 VLV_FIFO(SPRITED, sprite1_start));
1230
1231 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1232 VLV_FIFO(SPRITED_HI, 0xff));
1233 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1234 VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1235
1236 I915_WRITE(DSPARB, dsparb);
1237 I915_WRITE(DSPARB2, dsparb2);
1238 break;
1239 case PIPE_C:
1240 dsparb3 = I915_READ(DSPARB3);
1241 dsparb2 = I915_READ(DSPARB2);
1242
1243 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1244 VLV_FIFO(SPRITEF, 0xff));
1245 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1246 VLV_FIFO(SPRITEF, sprite1_start));
1247
1248 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1249 VLV_FIFO(SPRITEF_HI, 0xff));
1250 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1251 VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1252
1253 I915_WRITE(DSPARB3, dsparb3);
1254 I915_WRITE(DSPARB2, dsparb2);
1255 break;
1256 default:
1257 break;
1258 }
1259 }
1260
1261 #undef VLV_FIFO
1262
1263 static void vlv_merge_wm(struct drm_device *dev,
1264 struct vlv_wm_values *wm)
1265 {
1266 struct intel_crtc *crtc;
1267 int num_active_crtcs = 0;
1268
1269 wm->level = to_i915(dev)->wm.max_level;
1270 wm->cxsr = true;
1271
1272 for_each_intel_crtc(dev, crtc) {
1273 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1274
1275 if (!crtc->active)
1276 continue;
1277
1278 if (!wm_state->cxsr)
1279 wm->cxsr = false;
1280
1281 num_active_crtcs++;
1282 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1283 }
1284
1285 if (num_active_crtcs != 1)
1286 wm->cxsr = false;
1287
1288 if (num_active_crtcs > 1)
1289 wm->level = VLV_WM_LEVEL_PM2;
1290
1291 for_each_intel_crtc(dev, crtc) {
1292 struct vlv_wm_state *wm_state = &crtc->wm_state;
1293 enum pipe pipe = crtc->pipe;
1294
1295 if (!crtc->active)
1296 continue;
1297
1298 wm->pipe[pipe] = wm_state->wm[wm->level];
1299 if (wm->cxsr)
1300 wm->sr = wm_state->sr[wm->level];
1301
1302 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1303 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1304 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1305 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1306 }
1307 }
1308
1309 static void vlv_update_wm(struct drm_crtc *crtc)
1310 {
1311 struct drm_device *dev = crtc->dev;
1312 struct drm_i915_private *dev_priv = dev->dev_private;
1313 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1314 enum pipe pipe = intel_crtc->pipe;
1315 struct vlv_wm_values wm = {};
1316
1317 vlv_compute_wm(intel_crtc);
1318 vlv_merge_wm(dev, &wm);
1319
1320 if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1321 /* FIXME should be part of crtc atomic commit */
1322 vlv_pipe_set_fifo_size(intel_crtc);
1323 return;
1324 }
1325
1326 if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1327 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1328 chv_set_memory_dvfs(dev_priv, false);
1329
1330 if (wm.level < VLV_WM_LEVEL_PM5 &&
1331 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1332 chv_set_memory_pm5(dev_priv, false);
1333
1334 if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
1335 intel_set_memory_cxsr(dev_priv, false);
1336
1337 /* FIXME should be part of crtc atomic commit */
1338 vlv_pipe_set_fifo_size(intel_crtc);
1339
1340 vlv_write_wm_values(intel_crtc, &wm);
1341
1342 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1343 "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1344 pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1345 wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1346 wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1347
1348 if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
1349 intel_set_memory_cxsr(dev_priv, true);
1350
1351 if (wm.level >= VLV_WM_LEVEL_PM5 &&
1352 dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1353 chv_set_memory_pm5(dev_priv, true);
1354
1355 if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1356 dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1357 chv_set_memory_dvfs(dev_priv, true);
1358
1359 dev_priv->wm.vlv = wm;
1360 }
1361
1362 #define single_plane_enabled(mask) is_power_of_2(mask)
1363
1364 static void g4x_update_wm(struct drm_crtc *crtc)
1365 {
1366 struct drm_device *dev = crtc->dev;
1367 static const int sr_latency_ns = 12000;
1368 struct drm_i915_private *dev_priv = dev->dev_private;
1369 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1370 int plane_sr, cursor_sr;
1371 unsigned int enabled = 0;
1372 bool cxsr_enabled;
1373
1374 if (g4x_compute_wm0(dev, PIPE_A,
1375 &g4x_wm_info, pessimal_latency_ns,
1376 &g4x_cursor_wm_info, pessimal_latency_ns,
1377 &planea_wm, &cursora_wm))
1378 enabled |= 1 << PIPE_A;
1379
1380 if (g4x_compute_wm0(dev, PIPE_B,
1381 &g4x_wm_info, pessimal_latency_ns,
1382 &g4x_cursor_wm_info, pessimal_latency_ns,
1383 &planeb_wm, &cursorb_wm))
1384 enabled |= 1 << PIPE_B;
1385
1386 if (single_plane_enabled(enabled) &&
1387 g4x_compute_srwm(dev, ffs(enabled) - 1,
1388 sr_latency_ns,
1389 &g4x_wm_info,
1390 &g4x_cursor_wm_info,
1391 &plane_sr, &cursor_sr)) {
1392 cxsr_enabled = true;
1393 } else {
1394 cxsr_enabled = false;
1395 intel_set_memory_cxsr(dev_priv, false);
1396 plane_sr = cursor_sr = 0;
1397 }
1398
1399 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1400 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1401 planea_wm, cursora_wm,
1402 planeb_wm, cursorb_wm,
1403 plane_sr, cursor_sr);
1404
1405 I915_WRITE(DSPFW1,
1406 FW_WM(plane_sr, SR) |
1407 FW_WM(cursorb_wm, CURSORB) |
1408 FW_WM(planeb_wm, PLANEB) |
1409 FW_WM(planea_wm, PLANEA));
1410 I915_WRITE(DSPFW2,
1411 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1412 FW_WM(cursora_wm, CURSORA));
1413 /* HPLL off in SR has some issues on G4x... disable it */
1414 I915_WRITE(DSPFW3,
1415 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1416 FW_WM(cursor_sr, CURSOR_SR));
1417
1418 if (cxsr_enabled)
1419 intel_set_memory_cxsr(dev_priv, true);
1420 }
1421
1422 static void i965_update_wm(struct drm_crtc *unused_crtc)
1423 {
1424 struct drm_device *dev = unused_crtc->dev;
1425 struct drm_i915_private *dev_priv = dev->dev_private;
1426 struct drm_crtc *crtc;
1427 int srwm = 1;
1428 int cursor_sr = 16;
1429 bool cxsr_enabled;
1430
1431 /* Calc sr entries for one plane configs */
1432 crtc = single_enabled_crtc(dev);
1433 if (crtc) {
1434 /* self-refresh has much higher latency */
1435 static const int sr_latency_ns = 12000;
1436 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1437 int clock = adjusted_mode->crtc_clock;
1438 int htotal = adjusted_mode->crtc_htotal;
1439 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
1440 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
1441 unsigned long line_time_us;
1442 int entries;
1443
1444 line_time_us = max(htotal * 1000 / clock, 1);
1445
1446 /* Use ns/us then divide to preserve precision */
1447 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1448 pixel_size * hdisplay;
1449 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1450 srwm = I965_FIFO_SIZE - entries;
1451 if (srwm < 0)
1452 srwm = 1;
1453 srwm &= 0x1ff;
1454 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1455 entries, srwm);
1456
1457 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1458 pixel_size * crtc->cursor->state->crtc_w;
1459 entries = DIV_ROUND_UP(entries,
1460 i965_cursor_wm_info.cacheline_size);
1461 cursor_sr = i965_cursor_wm_info.fifo_size -
1462 (entries + i965_cursor_wm_info.guard_size);
1463
1464 if (cursor_sr > i965_cursor_wm_info.max_wm)
1465 cursor_sr = i965_cursor_wm_info.max_wm;
1466
1467 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1468 "cursor %d\n", srwm, cursor_sr);
1469
1470 cxsr_enabled = true;
1471 } else {
1472 cxsr_enabled = false;
1473 /* Turn off self refresh if both pipes are enabled */
1474 intel_set_memory_cxsr(dev_priv, false);
1475 }
1476
1477 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1478 srwm);
1479
1480 /* 965 has limitations... */
1481 I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1482 FW_WM(8, CURSORB) |
1483 FW_WM(8, PLANEB) |
1484 FW_WM(8, PLANEA));
1485 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1486 FW_WM(8, PLANEC_OLD));
1487 /* update cursor SR watermark */
1488 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
1489
1490 if (cxsr_enabled)
1491 intel_set_memory_cxsr(dev_priv, true);
1492 }
1493
1494 #undef FW_WM
1495
1496 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1497 {
1498 struct drm_device *dev = unused_crtc->dev;
1499 struct drm_i915_private *dev_priv = dev->dev_private;
1500 const struct intel_watermark_params *wm_info;
1501 uint32_t fwater_lo;
1502 uint32_t fwater_hi;
1503 int cwm, srwm = 1;
1504 int fifo_size;
1505 int planea_wm, planeb_wm;
1506 struct drm_crtc *crtc, *enabled = NULL;
1507
1508 if (IS_I945GM(dev))
1509 wm_info = &i945_wm_info;
1510 else if (!IS_GEN2(dev))
1511 wm_info = &i915_wm_info;
1512 else
1513 wm_info = &i830_a_wm_info;
1514
1515 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1516 crtc = intel_get_crtc_for_plane(dev, 0);
1517 if (intel_crtc_active(crtc)) {
1518 const struct drm_display_mode *adjusted_mode;
1519 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
1520 if (IS_GEN2(dev))
1521 cpp = 4;
1522
1523 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1524 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1525 wm_info, fifo_size, cpp,
1526 pessimal_latency_ns);
1527 enabled = crtc;
1528 } else {
1529 planea_wm = fifo_size - wm_info->guard_size;
1530 if (planea_wm > (long)wm_info->max_wm)
1531 planea_wm = wm_info->max_wm;
1532 }
1533
1534 if (IS_GEN2(dev))
1535 wm_info = &i830_bc_wm_info;
1536
1537 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1538 crtc = intel_get_crtc_for_plane(dev, 1);
1539 if (intel_crtc_active(crtc)) {
1540 const struct drm_display_mode *adjusted_mode;
1541 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
1542 if (IS_GEN2(dev))
1543 cpp = 4;
1544
1545 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1546 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1547 wm_info, fifo_size, cpp,
1548 pessimal_latency_ns);
1549 if (enabled == NULL)
1550 enabled = crtc;
1551 else
1552 enabled = NULL;
1553 } else {
1554 planeb_wm = fifo_size - wm_info->guard_size;
1555 if (planeb_wm > (long)wm_info->max_wm)
1556 planeb_wm = wm_info->max_wm;
1557 }
1558
1559 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1560
1561 if (IS_I915GM(dev) && enabled) {
1562 struct drm_i915_gem_object *obj;
1563
1564 obj = intel_fb_obj(enabled->primary->state->fb);
1565
1566 /* self-refresh seems busted with untiled */
1567 if (obj->tiling_mode == I915_TILING_NONE)
1568 enabled = NULL;
1569 }
1570
1571 /*
1572 * Overlay gets an aggressive default since video jitter is bad.
1573 */
1574 cwm = 2;
1575
1576 /* Play safe and disable self-refresh before adjusting watermarks. */
1577 intel_set_memory_cxsr(dev_priv, false);
1578
1579 /* Calc sr entries for one plane configs */
1580 if (HAS_FW_BLC(dev) && enabled) {
1581 /* self-refresh has much higher latency */
1582 static const int sr_latency_ns = 6000;
1583 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode;
1584 int clock = adjusted_mode->crtc_clock;
1585 int htotal = adjusted_mode->crtc_htotal;
1586 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
1587 int pixel_size = enabled->primary->state->fb->bits_per_pixel / 8;
1588 unsigned long line_time_us;
1589 int entries;
1590
1591 line_time_us = max(htotal * 1000 / clock, 1);
1592
1593 /* Use ns/us then divide to preserve precision */
1594 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1595 pixel_size * hdisplay;
1596 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1597 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1598 srwm = wm_info->fifo_size - entries;
1599 if (srwm < 0)
1600 srwm = 1;
1601
1602 if (IS_I945G(dev) || IS_I945GM(dev))
1603 I915_WRITE(FW_BLC_SELF,
1604 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1605 else if (IS_I915GM(dev))
1606 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1607 }
1608
1609 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1610 planea_wm, planeb_wm, cwm, srwm);
1611
1612 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1613 fwater_hi = (cwm & 0x1f);
1614
1615 /* Set request length to 8 cachelines per fetch */
1616 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1617 fwater_hi = fwater_hi | (1 << 8);
1618
1619 I915_WRITE(FW_BLC, fwater_lo);
1620 I915_WRITE(FW_BLC2, fwater_hi);
1621
1622 if (enabled)
1623 intel_set_memory_cxsr(dev_priv, true);
1624 }
1625
1626 static void i845_update_wm(struct drm_crtc *unused_crtc)
1627 {
1628 struct drm_device *dev = unused_crtc->dev;
1629 struct drm_i915_private *dev_priv = dev->dev_private;
1630 struct drm_crtc *crtc;
1631 const struct drm_display_mode *adjusted_mode;
1632 uint32_t fwater_lo;
1633 int planea_wm;
1634
1635 crtc = single_enabled_crtc(dev);
1636 if (crtc == NULL)
1637 return;
1638
1639 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1640 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1641 &i845_wm_info,
1642 dev_priv->display.get_fifo_size(dev, 0),
1643 4, pessimal_latency_ns);
1644 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1645 fwater_lo |= (3<<8) | planea_wm;
1646
1647 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1648
1649 I915_WRITE(FW_BLC, fwater_lo);
1650 }
1651
1652 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
1653 {
1654 uint32_t pixel_rate;
1655
1656 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
1657
1658 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1659 * adjust the pixel_rate here. */
1660
1661 if (pipe_config->pch_pfit.enabled) {
1662 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1663 uint32_t pfit_size = pipe_config->pch_pfit.size;
1664
1665 pipe_w = pipe_config->pipe_src_w;
1666 pipe_h = pipe_config->pipe_src_h;
1667
1668 pfit_w = (pfit_size >> 16) & 0xFFFF;
1669 pfit_h = pfit_size & 0xFFFF;
1670 if (pipe_w < pfit_w)
1671 pipe_w = pfit_w;
1672 if (pipe_h < pfit_h)
1673 pipe_h = pfit_h;
1674
1675 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1676 pfit_w * pfit_h);
1677 }
1678
1679 return pixel_rate;
1680 }
1681
1682 /* latency must be in 0.1us units. */
1683 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
1684 uint32_t latency)
1685 {
1686 uint64_t ret;
1687
1688 if (WARN(latency == 0, "Latency value missing\n"))
1689 return UINT_MAX;
1690
1691 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1692 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1693
1694 return ret;
1695 }
1696
1697 /* latency must be in 0.1us units. */
1698 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1699 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1700 uint32_t latency)
1701 {
1702 uint32_t ret;
1703
1704 if (WARN(latency == 0, "Latency value missing\n"))
1705 return UINT_MAX;
1706
1707 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1708 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1709 ret = DIV_ROUND_UP(ret, 64) + 2;
1710 return ret;
1711 }
1712
1713 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1714 uint8_t bytes_per_pixel)
1715 {
1716 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1717 }
1718
1719 struct ilk_wm_maximums {
1720 uint16_t pri;
1721 uint16_t spr;
1722 uint16_t cur;
1723 uint16_t fbc;
1724 };
1725
1726 /*
1727 * For both WM_PIPE and WM_LP.
1728 * mem_value must be in 0.1us units.
1729 */
1730 static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
1731 const struct intel_plane_state *pstate,
1732 uint32_t mem_value,
1733 bool is_lp)
1734 {
1735 int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
1736 uint32_t method1, method2;
1737
1738 if (!cstate->base.active || !pstate->visible)
1739 return 0;
1740
1741 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), bpp, mem_value);
1742
1743 if (!is_lp)
1744 return method1;
1745
1746 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1747 cstate->base.adjusted_mode.crtc_htotal,
1748 drm_rect_width(&pstate->dst),
1749 bpp,
1750 mem_value);
1751
1752 return min(method1, method2);
1753 }
1754
1755 /*
1756 * For both WM_PIPE and WM_LP.
1757 * mem_value must be in 0.1us units.
1758 */
1759 static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
1760 const struct intel_plane_state *pstate,
1761 uint32_t mem_value)
1762 {
1763 int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
1764 uint32_t method1, method2;
1765
1766 if (!cstate->base.active || !pstate->visible)
1767 return 0;
1768
1769 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), bpp, mem_value);
1770 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1771 cstate->base.adjusted_mode.crtc_htotal,
1772 drm_rect_width(&pstate->dst),
1773 bpp,
1774 mem_value);
1775 return min(method1, method2);
1776 }
1777
1778 /*
1779 * For both WM_PIPE and WM_LP.
1780 * mem_value must be in 0.1us units.
1781 */
1782 static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
1783 const struct intel_plane_state *pstate,
1784 uint32_t mem_value)
1785 {
1786 /*
1787 * We treat the cursor plane as always-on for the purposes of watermark
1788 * calculation. Until we have two-stage watermark programming merged,
1789 * this is necessary to avoid flickering.
1790 */
1791 int cpp = 4;
1792 int width = pstate->visible ? pstate->base.crtc_w : 64;
1793
1794 if (!cstate->base.active)
1795 return 0;
1796
1797 return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1798 cstate->base.adjusted_mode.crtc_htotal,
1799 width, cpp, mem_value);
1800 }
1801
1802 /* Only for WM_LP. */
1803 static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
1804 const struct intel_plane_state *pstate,
1805 uint32_t pri_val)
1806 {
1807 int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
1808
1809 if (!cstate->base.active || !pstate->visible)
1810 return 0;
1811
1812 return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->dst), bpp);
1813 }
1814
1815 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1816 {
1817 if (INTEL_INFO(dev)->gen >= 8)
1818 return 3072;
1819 else if (INTEL_INFO(dev)->gen >= 7)
1820 return 768;
1821 else
1822 return 512;
1823 }
1824
1825 static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1826 int level, bool is_sprite)
1827 {
1828 if (INTEL_INFO(dev)->gen >= 8)
1829 /* BDW primary/sprite plane watermarks */
1830 return level == 0 ? 255 : 2047;
1831 else if (INTEL_INFO(dev)->gen >= 7)
1832 /* IVB/HSW primary/sprite plane watermarks */
1833 return level == 0 ? 127 : 1023;
1834 else if (!is_sprite)
1835 /* ILK/SNB primary plane watermarks */
1836 return level == 0 ? 127 : 511;
1837 else
1838 /* ILK/SNB sprite plane watermarks */
1839 return level == 0 ? 63 : 255;
1840 }
1841
1842 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1843 int level)
1844 {
1845 if (INTEL_INFO(dev)->gen >= 7)
1846 return level == 0 ? 63 : 255;
1847 else
1848 return level == 0 ? 31 : 63;
1849 }
1850
1851 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1852 {
1853 if (INTEL_INFO(dev)->gen >= 8)
1854 return 31;
1855 else
1856 return 15;
1857 }
1858
1859 /* Calculate the maximum primary/sprite plane watermark */
1860 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1861 int level,
1862 const struct intel_wm_config *config,
1863 enum intel_ddb_partitioning ddb_partitioning,
1864 bool is_sprite)
1865 {
1866 unsigned int fifo_size = ilk_display_fifo_size(dev);
1867
1868 /* if sprites aren't enabled, sprites get nothing */
1869 if (is_sprite && !config->sprites_enabled)
1870 return 0;
1871
1872 /* HSW allows LP1+ watermarks even with multiple pipes */
1873 if (level == 0 || config->num_pipes_active > 1) {
1874 fifo_size /= INTEL_INFO(dev)->num_pipes;
1875
1876 /*
1877 * For some reason the non self refresh
1878 * FIFO size is only half of the self
1879 * refresh FIFO size on ILK/SNB.
1880 */
1881 if (INTEL_INFO(dev)->gen <= 6)
1882 fifo_size /= 2;
1883 }
1884
1885 if (config->sprites_enabled) {
1886 /* level 0 is always calculated with 1:1 split */
1887 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1888 if (is_sprite)
1889 fifo_size *= 5;
1890 fifo_size /= 6;
1891 } else {
1892 fifo_size /= 2;
1893 }
1894 }
1895
1896 /* clamp to max that the registers can hold */
1897 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
1898 }
1899
1900 /* Calculate the maximum cursor plane watermark */
1901 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
1902 int level,
1903 const struct intel_wm_config *config)
1904 {
1905 /* HSW LP1+ watermarks w/ multiple pipes */
1906 if (level > 0 && config->num_pipes_active > 1)
1907 return 64;
1908
1909 /* otherwise just report max that registers can hold */
1910 return ilk_cursor_wm_reg_max(dev, level);
1911 }
1912
1913 static void ilk_compute_wm_maximums(const struct drm_device *dev,
1914 int level,
1915 const struct intel_wm_config *config,
1916 enum intel_ddb_partitioning ddb_partitioning,
1917 struct ilk_wm_maximums *max)
1918 {
1919 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1920 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1921 max->cur = ilk_cursor_wm_max(dev, level, config);
1922 max->fbc = ilk_fbc_wm_reg_max(dev);
1923 }
1924
1925 static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1926 int level,
1927 struct ilk_wm_maximums *max)
1928 {
1929 max->pri = ilk_plane_wm_reg_max(dev, level, false);
1930 max->spr = ilk_plane_wm_reg_max(dev, level, true);
1931 max->cur = ilk_cursor_wm_reg_max(dev, level);
1932 max->fbc = ilk_fbc_wm_reg_max(dev);
1933 }
1934
1935 static bool ilk_validate_wm_level(int level,
1936 const struct ilk_wm_maximums *max,
1937 struct intel_wm_level *result)
1938 {
1939 bool ret;
1940
1941 /* already determined to be invalid? */
1942 if (!result->enable)
1943 return false;
1944
1945 result->enable = result->pri_val <= max->pri &&
1946 result->spr_val <= max->spr &&
1947 result->cur_val <= max->cur;
1948
1949 ret = result->enable;
1950
1951 /*
1952 * HACK until we can pre-compute everything,
1953 * and thus fail gracefully if LP0 watermarks
1954 * are exceeded...
1955 */
1956 if (level == 0 && !result->enable) {
1957 if (result->pri_val > max->pri)
1958 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1959 level, result->pri_val, max->pri);
1960 if (result->spr_val > max->spr)
1961 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1962 level, result->spr_val, max->spr);
1963 if (result->cur_val > max->cur)
1964 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1965 level, result->cur_val, max->cur);
1966
1967 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
1968 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
1969 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
1970 result->enable = true;
1971 }
1972
1973 return ret;
1974 }
1975
1976 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
1977 const struct intel_crtc *intel_crtc,
1978 int level,
1979 struct intel_crtc_state *cstate,
1980 struct intel_plane_state *pristate,
1981 struct intel_plane_state *sprstate,
1982 struct intel_plane_state *curstate,
1983 struct intel_wm_level *result)
1984 {
1985 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
1986 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
1987 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
1988
1989 /* WM1+ latency values stored in 0.5us units */
1990 if (level > 0) {
1991 pri_latency *= 5;
1992 spr_latency *= 5;
1993 cur_latency *= 5;
1994 }
1995
1996 result->pri_val = ilk_compute_pri_wm(cstate, pristate,
1997 pri_latency, level);
1998 result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
1999 result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
2000 result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
2001 result->enable = true;
2002 }
2003
2004 static uint32_t
2005 hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
2006 {
2007 struct drm_i915_private *dev_priv = dev->dev_private;
2008 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2009 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
2010 u32 linetime, ips_linetime;
2011
2012 if (!intel_crtc->active)
2013 return 0;
2014
2015 /* The WM are computed with base on how long it takes to fill a single
2016 * row at the given clock rate, multiplied by 8.
2017 * */
2018 linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2019 adjusted_mode->crtc_clock);
2020 ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2021 dev_priv->cdclk_freq);
2022
2023 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2024 PIPE_WM_LINETIME_TIME(linetime);
2025 }
2026
2027 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
2028 {
2029 struct drm_i915_private *dev_priv = dev->dev_private;
2030
2031 if (IS_GEN9(dev)) {
2032 uint32_t val;
2033 int ret, i;
2034 int level, max_level = ilk_wm_max_level(dev);
2035
2036 /* read the first set of memory latencies[0:3] */
2037 val = 0; /* data0 to be programmed to 0 for first set */
2038 mutex_lock(&dev_priv->rps.hw_lock);
2039 ret = sandybridge_pcode_read(dev_priv,
2040 GEN9_PCODE_READ_MEM_LATENCY,
2041 &val);
2042 mutex_unlock(&dev_priv->rps.hw_lock);
2043
2044 if (ret) {
2045 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2046 return;
2047 }
2048
2049 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2050 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2051 GEN9_MEM_LATENCY_LEVEL_MASK;
2052 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2053 GEN9_MEM_LATENCY_LEVEL_MASK;
2054 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2055 GEN9_MEM_LATENCY_LEVEL_MASK;
2056
2057 /* read the second set of memory latencies[4:7] */
2058 val = 1; /* data0 to be programmed to 1 for second set */
2059 mutex_lock(&dev_priv->rps.hw_lock);
2060 ret = sandybridge_pcode_read(dev_priv,
2061 GEN9_PCODE_READ_MEM_LATENCY,
2062 &val);
2063 mutex_unlock(&dev_priv->rps.hw_lock);
2064 if (ret) {
2065 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2066 return;
2067 }
2068
2069 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2070 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2071 GEN9_MEM_LATENCY_LEVEL_MASK;
2072 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2073 GEN9_MEM_LATENCY_LEVEL_MASK;
2074 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2075 GEN9_MEM_LATENCY_LEVEL_MASK;
2076
2077 /*
2078 * WaWmMemoryReadLatency:skl
2079 *
2080 * punit doesn't take into account the read latency so we need
2081 * to add 2us to the various latency levels we retrieve from
2082 * the punit.
2083 * - W0 is a bit special in that it's the only level that
2084 * can't be disabled if we want to have display working, so
2085 * we always add 2us there.
2086 * - For levels >=1, punit returns 0us latency when they are
2087 * disabled, so we respect that and don't add 2us then
2088 *
2089 * Additionally, if a level n (n > 1) has a 0us latency, all
2090 * levels m (m >= n) need to be disabled. We make sure to
2091 * sanitize the values out of the punit to satisfy this
2092 * requirement.
2093 */
2094 wm[0] += 2;
2095 for (level = 1; level <= max_level; level++)
2096 if (wm[level] != 0)
2097 wm[level] += 2;
2098 else {
2099 for (i = level + 1; i <= max_level; i++)
2100 wm[i] = 0;
2101
2102 break;
2103 }
2104 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2105 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2106
2107 wm[0] = (sskpd >> 56) & 0xFF;
2108 if (wm[0] == 0)
2109 wm[0] = sskpd & 0xF;
2110 wm[1] = (sskpd >> 4) & 0xFF;
2111 wm[2] = (sskpd >> 12) & 0xFF;
2112 wm[3] = (sskpd >> 20) & 0x1FF;
2113 wm[4] = (sskpd >> 32) & 0x1FF;
2114 } else if (INTEL_INFO(dev)->gen >= 6) {
2115 uint32_t sskpd = I915_READ(MCH_SSKPD);
2116
2117 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2118 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2119 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2120 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2121 } else if (INTEL_INFO(dev)->gen >= 5) {
2122 uint32_t mltr = I915_READ(MLTR_ILK);
2123
2124 /* ILK primary LP0 latency is 700 ns */
2125 wm[0] = 7;
2126 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2127 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2128 }
2129 }
2130
2131 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2132 {
2133 /* ILK sprite LP0 latency is 1300 ns */
2134 if (INTEL_INFO(dev)->gen == 5)
2135 wm[0] = 13;
2136 }
2137
2138 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2139 {
2140 /* ILK cursor LP0 latency is 1300 ns */
2141 if (INTEL_INFO(dev)->gen == 5)
2142 wm[0] = 13;
2143
2144 /* WaDoubleCursorLP3Latency:ivb */
2145 if (IS_IVYBRIDGE(dev))
2146 wm[3] *= 2;
2147 }
2148
2149 int ilk_wm_max_level(const struct drm_device *dev)
2150 {
2151 /* how many WM levels are we expecting */
2152 if (INTEL_INFO(dev)->gen >= 9)
2153 return 7;
2154 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2155 return 4;
2156 else if (INTEL_INFO(dev)->gen >= 6)
2157 return 3;
2158 else
2159 return 2;
2160 }
2161
2162 static void intel_print_wm_latency(struct drm_device *dev,
2163 const char *name,
2164 const uint16_t wm[8])
2165 {
2166 int level, max_level = ilk_wm_max_level(dev);
2167
2168 for (level = 0; level <= max_level; level++) {
2169 unsigned int latency = wm[level];
2170
2171 if (latency == 0) {
2172 DRM_ERROR("%s WM%d latency not provided\n",
2173 name, level);
2174 continue;
2175 }
2176
2177 /*
2178 * - latencies are in us on gen9.
2179 * - before then, WM1+ latency values are in 0.5us units
2180 */
2181 if (IS_GEN9(dev))
2182 latency *= 10;
2183 else if (level > 0)
2184 latency *= 5;
2185
2186 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2187 name, level, wm[level],
2188 latency / 10, latency % 10);
2189 }
2190 }
2191
2192 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2193 uint16_t wm[5], uint16_t min)
2194 {
2195 int level, max_level = ilk_wm_max_level(dev_priv->dev);
2196
2197 if (wm[0] >= min)
2198 return false;
2199
2200 wm[0] = max(wm[0], min);
2201 for (level = 1; level <= max_level; level++)
2202 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2203
2204 return true;
2205 }
2206
2207 static void snb_wm_latency_quirk(struct drm_device *dev)
2208 {
2209 struct drm_i915_private *dev_priv = dev->dev_private;
2210 bool changed;
2211
2212 /*
2213 * The BIOS provided WM memory latency values are often
2214 * inadequate for high resolution displays. Adjust them.
2215 */
2216 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2217 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2218 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2219
2220 if (!changed)
2221 return;
2222
2223 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2224 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2225 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2226 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2227 }
2228
2229 static void ilk_setup_wm_latency(struct drm_device *dev)
2230 {
2231 struct drm_i915_private *dev_priv = dev->dev_private;
2232
2233 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2234
2235 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2236 sizeof(dev_priv->wm.pri_latency));
2237 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2238 sizeof(dev_priv->wm.pri_latency));
2239
2240 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2241 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2242
2243 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2244 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2245 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2246
2247 if (IS_GEN6(dev))
2248 snb_wm_latency_quirk(dev);
2249 }
2250
2251 static void skl_setup_wm_latency(struct drm_device *dev)
2252 {
2253 struct drm_i915_private *dev_priv = dev->dev_private;
2254
2255 intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2256 intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2257 }
2258
2259 /* Compute new watermarks for the pipe */
2260 static int ilk_compute_pipe_wm(struct intel_crtc *intel_crtc,
2261 struct drm_atomic_state *state)
2262 {
2263 struct intel_pipe_wm *pipe_wm;
2264 struct drm_device *dev = intel_crtc->base.dev;
2265 const struct drm_i915_private *dev_priv = dev->dev_private;
2266 struct intel_crtc_state *cstate = NULL;
2267 struct intel_plane *intel_plane;
2268 struct drm_plane_state *ps;
2269 struct intel_plane_state *pristate = NULL;
2270 struct intel_plane_state *sprstate = NULL;
2271 struct intel_plane_state *curstate = NULL;
2272 int level, max_level = ilk_wm_max_level(dev);
2273 /* LP0 watermark maximums depend on this pipe alone */
2274 struct intel_wm_config config = {
2275 .num_pipes_active = 1,
2276 };
2277 struct ilk_wm_maximums max;
2278
2279 cstate = intel_atomic_get_crtc_state(state, intel_crtc);
2280 if (IS_ERR(cstate))
2281 return PTR_ERR(cstate);
2282
2283 pipe_wm = &cstate->wm.optimal.ilk;
2284
2285 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2286 ps = drm_atomic_get_plane_state(state,
2287 &intel_plane->base);
2288 if (IS_ERR(ps))
2289 return PTR_ERR(ps);
2290
2291 if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
2292 pristate = to_intel_plane_state(ps);
2293 else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
2294 sprstate = to_intel_plane_state(ps);
2295 else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
2296 curstate = to_intel_plane_state(ps);
2297 }
2298
2299 config.sprites_enabled = sprstate->visible;
2300 config.sprites_scaled = sprstate->visible &&
2301 (drm_rect_width(&sprstate->dst) != drm_rect_width(&sprstate->src) >> 16 ||
2302 drm_rect_height(&sprstate->dst) != drm_rect_height(&sprstate->src) >> 16);
2303
2304 pipe_wm->pipe_enabled = cstate->base.active;
2305 pipe_wm->sprites_enabled = config.sprites_enabled;
2306 pipe_wm->sprites_scaled = config.sprites_scaled;
2307
2308 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2309 if (INTEL_INFO(dev)->gen <= 6 && sprstate->visible)
2310 max_level = 1;
2311
2312 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2313 if (config.sprites_scaled)
2314 max_level = 0;
2315
2316 ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
2317 pristate, sprstate, curstate, &pipe_wm->wm[0]);
2318
2319 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2320 pipe_wm->linetime = hsw_compute_linetime_wm(dev,
2321 &intel_crtc->base);
2322
2323 /* LP0 watermarks always use 1/2 DDB partitioning */
2324 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2325
2326 /* At least LP0 must be valid */
2327 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
2328 return -EINVAL;
2329
2330 ilk_compute_wm_reg_maximums(dev, 1, &max);
2331
2332 for (level = 1; level <= max_level; level++) {
2333 struct intel_wm_level wm = {};
2334
2335 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
2336 pristate, sprstate, curstate, &wm);
2337
2338 /*
2339 * Disable any watermark level that exceeds the
2340 * register maximums since such watermarks are
2341 * always invalid.
2342 */
2343 if (!ilk_validate_wm_level(level, &max, &wm))
2344 break;
2345
2346 pipe_wm->wm[level] = wm;
2347 }
2348
2349 return 0;
2350 }
2351
2352 /*
2353 * Merge the watermarks from all active pipes for a specific level.
2354 */
2355 static void ilk_merge_wm_level(struct drm_device *dev,
2356 int level,
2357 struct intel_wm_level *ret_wm)
2358 {
2359 const struct intel_crtc *intel_crtc;
2360
2361 ret_wm->enable = true;
2362
2363 for_each_intel_crtc(dev, intel_crtc) {
2364 const struct intel_crtc_state *cstate =
2365 to_intel_crtc_state(intel_crtc->base.state);
2366 const struct intel_pipe_wm *active = &cstate->wm.optimal.ilk;
2367 const struct intel_wm_level *wm = &active->wm[level];
2368
2369 if (!active->pipe_enabled)
2370 continue;
2371
2372 /*
2373 * The watermark values may have been used in the past,
2374 * so we must maintain them in the registers for some
2375 * time even if the level is now disabled.
2376 */
2377 if (!wm->enable)
2378 ret_wm->enable = false;
2379
2380 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2381 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2382 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2383 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2384 }
2385 }
2386
2387 /*
2388 * Merge all low power watermarks for all active pipes.
2389 */
2390 static void ilk_wm_merge(struct drm_device *dev,
2391 const struct intel_wm_config *config,
2392 const struct ilk_wm_maximums *max,
2393 struct intel_pipe_wm *merged)
2394 {
2395 struct drm_i915_private *dev_priv = dev->dev_private;
2396 int level, max_level = ilk_wm_max_level(dev);
2397 int last_enabled_level = max_level;
2398
2399 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2400 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2401 config->num_pipes_active > 1)
2402 return;
2403
2404 /* ILK: FBC WM must be disabled always */
2405 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
2406
2407 /* merge each WM1+ level */
2408 for (level = 1; level <= max_level; level++) {
2409 struct intel_wm_level *wm = &merged->wm[level];
2410
2411 ilk_merge_wm_level(dev, level, wm);
2412
2413 if (level > last_enabled_level)
2414 wm->enable = false;
2415 else if (!ilk_validate_wm_level(level, max, wm))
2416 /* make sure all following levels get disabled */
2417 last_enabled_level = level - 1;
2418
2419 /*
2420 * The spec says it is preferred to disable
2421 * FBC WMs instead of disabling a WM level.
2422 */
2423 if (wm->fbc_val > max->fbc) {
2424 if (wm->enable)
2425 merged->fbc_wm_enabled = false;
2426 wm->fbc_val = 0;
2427 }
2428 }
2429
2430 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2431 /*
2432 * FIXME this is racy. FBC might get enabled later.
2433 * What we should check here is whether FBC can be
2434 * enabled sometime later.
2435 */
2436 if (IS_GEN5(dev) && !merged->fbc_wm_enabled &&
2437 intel_fbc_is_active(dev_priv)) {
2438 for (level = 2; level <= max_level; level++) {
2439 struct intel_wm_level *wm = &merged->wm[level];
2440
2441 wm->enable = false;
2442 }
2443 }
2444 }
2445
2446 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2447 {
2448 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2449 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2450 }
2451
2452 /* The value we need to program into the WM_LPx latency field */
2453 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2454 {
2455 struct drm_i915_private *dev_priv = dev->dev_private;
2456
2457 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2458 return 2 * level;
2459 else
2460 return dev_priv->wm.pri_latency[level];
2461 }
2462
2463 static void ilk_compute_wm_results(struct drm_device *dev,
2464 const struct intel_pipe_wm *merged,
2465 enum intel_ddb_partitioning partitioning,
2466 struct ilk_wm_values *results)
2467 {
2468 struct intel_crtc *intel_crtc;
2469 int level, wm_lp;
2470
2471 results->enable_fbc_wm = merged->fbc_wm_enabled;
2472 results->partitioning = partitioning;
2473
2474 /* LP1+ register values */
2475 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2476 const struct intel_wm_level *r;
2477
2478 level = ilk_wm_lp_to_level(wm_lp, merged);
2479
2480 r = &merged->wm[level];
2481
2482 /*
2483 * Maintain the watermark values even if the level is
2484 * disabled. Doing otherwise could cause underruns.
2485 */
2486 results->wm_lp[wm_lp - 1] =
2487 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2488 (r->pri_val << WM1_LP_SR_SHIFT) |
2489 r->cur_val;
2490
2491 if (r->enable)
2492 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2493
2494 if (INTEL_INFO(dev)->gen >= 8)
2495 results->wm_lp[wm_lp - 1] |=
2496 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2497 else
2498 results->wm_lp[wm_lp - 1] |=
2499 r->fbc_val << WM1_LP_FBC_SHIFT;
2500
2501 /*
2502 * Always set WM1S_LP_EN when spr_val != 0, even if the
2503 * level is disabled. Doing otherwise could cause underruns.
2504 */
2505 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2506 WARN_ON(wm_lp != 1);
2507 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2508 } else
2509 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2510 }
2511
2512 /* LP0 register values */
2513 for_each_intel_crtc(dev, intel_crtc) {
2514 const struct intel_crtc_state *cstate =
2515 to_intel_crtc_state(intel_crtc->base.state);
2516 enum pipe pipe = intel_crtc->pipe;
2517 const struct intel_wm_level *r = &cstate->wm.optimal.ilk.wm[0];
2518
2519 if (WARN_ON(!r->enable))
2520 continue;
2521
2522 results->wm_linetime[pipe] = cstate->wm.optimal.ilk.linetime;
2523
2524 results->wm_pipe[pipe] =
2525 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2526 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2527 r->cur_val;
2528 }
2529 }
2530
2531 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2532 * case both are at the same level. Prefer r1 in case they're the same. */
2533 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2534 struct intel_pipe_wm *r1,
2535 struct intel_pipe_wm *r2)
2536 {
2537 int level, max_level = ilk_wm_max_level(dev);
2538 int level1 = 0, level2 = 0;
2539
2540 for (level = 1; level <= max_level; level++) {
2541 if (r1->wm[level].enable)
2542 level1 = level;
2543 if (r2->wm[level].enable)
2544 level2 = level;
2545 }
2546
2547 if (level1 == level2) {
2548 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2549 return r2;
2550 else
2551 return r1;
2552 } else if (level1 > level2) {
2553 return r1;
2554 } else {
2555 return r2;
2556 }
2557 }
2558
2559 /* dirty bits used to track which watermarks need changes */
2560 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2561 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2562 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2563 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2564 #define WM_DIRTY_FBC (1 << 24)
2565 #define WM_DIRTY_DDB (1 << 25)
2566
2567 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
2568 const struct ilk_wm_values *old,
2569 const struct ilk_wm_values *new)
2570 {
2571 unsigned int dirty = 0;
2572 enum pipe pipe;
2573 int wm_lp;
2574
2575 for_each_pipe(dev_priv, pipe) {
2576 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2577 dirty |= WM_DIRTY_LINETIME(pipe);
2578 /* Must disable LP1+ watermarks too */
2579 dirty |= WM_DIRTY_LP_ALL;
2580 }
2581
2582 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2583 dirty |= WM_DIRTY_PIPE(pipe);
2584 /* Must disable LP1+ watermarks too */
2585 dirty |= WM_DIRTY_LP_ALL;
2586 }
2587 }
2588
2589 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2590 dirty |= WM_DIRTY_FBC;
2591 /* Must disable LP1+ watermarks too */
2592 dirty |= WM_DIRTY_LP_ALL;
2593 }
2594
2595 if (old->partitioning != new->partitioning) {
2596 dirty |= WM_DIRTY_DDB;
2597 /* Must disable LP1+ watermarks too */
2598 dirty |= WM_DIRTY_LP_ALL;
2599 }
2600
2601 /* LP1+ watermarks already deemed dirty, no need to continue */
2602 if (dirty & WM_DIRTY_LP_ALL)
2603 return dirty;
2604
2605 /* Find the lowest numbered LP1+ watermark in need of an update... */
2606 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2607 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2608 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2609 break;
2610 }
2611
2612 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2613 for (; wm_lp <= 3; wm_lp++)
2614 dirty |= WM_DIRTY_LP(wm_lp);
2615
2616 return dirty;
2617 }
2618
2619 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2620 unsigned int dirty)
2621 {
2622 struct ilk_wm_values *previous = &dev_priv->wm.hw;
2623 bool changed = false;
2624
2625 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2626 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2627 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2628 changed = true;
2629 }
2630 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2631 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2632 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2633 changed = true;
2634 }
2635 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2636 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2637 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2638 changed = true;
2639 }
2640
2641 /*
2642 * Don't touch WM1S_LP_EN here.
2643 * Doing so could cause underruns.
2644 */
2645
2646 return changed;
2647 }
2648
2649 /*
2650 * The spec says we shouldn't write when we don't need, because every write
2651 * causes WMs to be re-evaluated, expending some power.
2652 */
2653 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2654 struct ilk_wm_values *results)
2655 {
2656 struct drm_device *dev = dev_priv->dev;
2657 struct ilk_wm_values *previous = &dev_priv->wm.hw;
2658 unsigned int dirty;
2659 uint32_t val;
2660
2661 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
2662 if (!dirty)
2663 return;
2664
2665 _ilk_disable_lp_wm(dev_priv, dirty);
2666
2667 if (dirty & WM_DIRTY_PIPE(PIPE_A))
2668 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2669 if (dirty & WM_DIRTY_PIPE(PIPE_B))
2670 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2671 if (dirty & WM_DIRTY_PIPE(PIPE_C))
2672 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2673
2674 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2675 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2676 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2677 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2678 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2679 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2680
2681 if (dirty & WM_DIRTY_DDB) {
2682 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2683 val = I915_READ(WM_MISC);
2684 if (results->partitioning == INTEL_DDB_PART_1_2)
2685 val &= ~WM_MISC_DATA_PARTITION_5_6;
2686 else
2687 val |= WM_MISC_DATA_PARTITION_5_6;
2688 I915_WRITE(WM_MISC, val);
2689 } else {
2690 val = I915_READ(DISP_ARB_CTL2);
2691 if (results->partitioning == INTEL_DDB_PART_1_2)
2692 val &= ~DISP_DATA_PARTITION_5_6;
2693 else
2694 val |= DISP_DATA_PARTITION_5_6;
2695 I915_WRITE(DISP_ARB_CTL2, val);
2696 }
2697 }
2698
2699 if (dirty & WM_DIRTY_FBC) {
2700 val = I915_READ(DISP_ARB_CTL);
2701 if (results->enable_fbc_wm)
2702 val &= ~DISP_FBC_WM_DIS;
2703 else
2704 val |= DISP_FBC_WM_DIS;
2705 I915_WRITE(DISP_ARB_CTL, val);
2706 }
2707
2708 if (dirty & WM_DIRTY_LP(1) &&
2709 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2710 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2711
2712 if (INTEL_INFO(dev)->gen >= 7) {
2713 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2714 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2715 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2716 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2717 }
2718
2719 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2720 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2721 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2722 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2723 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2724 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2725
2726 dev_priv->wm.hw = *results;
2727 }
2728
2729 static bool ilk_disable_lp_wm(struct drm_device *dev)
2730 {
2731 struct drm_i915_private *dev_priv = dev->dev_private;
2732
2733 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2734 }
2735
2736 /*
2737 * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2738 * different active planes.
2739 */
2740
2741 #define SKL_DDB_SIZE 896 /* in blocks */
2742 #define BXT_DDB_SIZE 512
2743
2744 /*
2745 * Return the index of a plane in the SKL DDB and wm result arrays. Primary
2746 * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
2747 * other universal planes are in indices 1..n. Note that this may leave unused
2748 * indices between the top "sprite" plane and the cursor.
2749 */
2750 static int
2751 skl_wm_plane_id(const struct intel_plane *plane)
2752 {
2753 switch (plane->base.type) {
2754 case DRM_PLANE_TYPE_PRIMARY:
2755 return 0;
2756 case DRM_PLANE_TYPE_CURSOR:
2757 return PLANE_CURSOR;
2758 case DRM_PLANE_TYPE_OVERLAY:
2759 return plane->plane + 1;
2760 default:
2761 MISSING_CASE(plane->base.type);
2762 return plane->plane;
2763 }
2764 }
2765
2766 static void
2767 skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
2768 const struct intel_crtc_state *cstate,
2769 const struct intel_wm_config *config,
2770 struct skl_ddb_entry *alloc /* out */)
2771 {
2772 struct drm_crtc *for_crtc = cstate->base.crtc;
2773 struct drm_crtc *crtc;
2774 unsigned int pipe_size, ddb_size;
2775 int nth_active_pipe;
2776
2777 if (!cstate->base.active) {
2778 alloc->start = 0;
2779 alloc->end = 0;
2780 return;
2781 }
2782
2783 if (IS_BROXTON(dev))
2784 ddb_size = BXT_DDB_SIZE;
2785 else
2786 ddb_size = SKL_DDB_SIZE;
2787
2788 ddb_size -= 4; /* 4 blocks for bypass path allocation */
2789
2790 nth_active_pipe = 0;
2791 for_each_crtc(dev, crtc) {
2792 if (!to_intel_crtc(crtc)->active)
2793 continue;
2794
2795 if (crtc == for_crtc)
2796 break;
2797
2798 nth_active_pipe++;
2799 }
2800
2801 pipe_size = ddb_size / config->num_pipes_active;
2802 alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active;
2803 alloc->end = alloc->start + pipe_size;
2804 }
2805
2806 static unsigned int skl_cursor_allocation(const struct intel_wm_config *config)
2807 {
2808 if (config->num_pipes_active == 1)
2809 return 32;
2810
2811 return 8;
2812 }
2813
2814 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
2815 {
2816 entry->start = reg & 0x3ff;
2817 entry->end = (reg >> 16) & 0x3ff;
2818 if (entry->end)
2819 entry->end += 1;
2820 }
2821
2822 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2823 struct skl_ddb_allocation *ddb /* out */)
2824 {
2825 enum pipe pipe;
2826 int plane;
2827 u32 val;
2828
2829 memset(ddb, 0, sizeof(*ddb));
2830
2831 for_each_pipe(dev_priv, pipe) {
2832 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe)))
2833 continue;
2834
2835 for_each_plane(dev_priv, pipe, plane) {
2836 val = I915_READ(PLANE_BUF_CFG(pipe, plane));
2837 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
2838 val);
2839 }
2840
2841 val = I915_READ(CUR_BUF_CFG(pipe));
2842 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
2843 val);
2844 }
2845 }
2846
2847 static unsigned int
2848 skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
2849 const struct drm_plane_state *pstate,
2850 int y)
2851 {
2852 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
2853 struct drm_framebuffer *fb = pstate->fb;
2854
2855 /* for planar format */
2856 if (fb->pixel_format == DRM_FORMAT_NV12) {
2857 if (y) /* y-plane data rate */
2858 return intel_crtc->config->pipe_src_w *
2859 intel_crtc->config->pipe_src_h *
2860 drm_format_plane_cpp(fb->pixel_format, 0);
2861 else /* uv-plane data rate */
2862 return (intel_crtc->config->pipe_src_w/2) *
2863 (intel_crtc->config->pipe_src_h/2) *
2864 drm_format_plane_cpp(fb->pixel_format, 1);
2865 }
2866
2867 /* for packed formats */
2868 return intel_crtc->config->pipe_src_w *
2869 intel_crtc->config->pipe_src_h *
2870 drm_format_plane_cpp(fb->pixel_format, 0);
2871 }
2872
2873 /*
2874 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
2875 * a 8192x4096@32bpp framebuffer:
2876 * 3 * 4096 * 8192 * 4 < 2^32
2877 */
2878 static unsigned int
2879 skl_get_total_relative_data_rate(const struct intel_crtc_state *cstate)
2880 {
2881 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
2882 struct drm_device *dev = intel_crtc->base.dev;
2883 const struct intel_plane *intel_plane;
2884 unsigned int total_data_rate = 0;
2885
2886 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2887 const struct drm_plane_state *pstate = intel_plane->base.state;
2888
2889 if (pstate->fb == NULL)
2890 continue;
2891
2892 if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
2893 continue;
2894
2895 /* packed/uv */
2896 total_data_rate += skl_plane_relative_data_rate(cstate,
2897 pstate,
2898 0);
2899
2900 if (pstate->fb->pixel_format == DRM_FORMAT_NV12)
2901 /* y-plane */
2902 total_data_rate += skl_plane_relative_data_rate(cstate,
2903 pstate,
2904 1);
2905 }
2906
2907 return total_data_rate;
2908 }
2909
2910 static void
2911 skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
2912 struct skl_ddb_allocation *ddb /* out */)
2913 {
2914 struct drm_crtc *crtc = cstate->base.crtc;
2915 struct drm_device *dev = crtc->dev;
2916 struct drm_i915_private *dev_priv = to_i915(dev);
2917 struct intel_wm_config *config = &dev_priv->wm.config;
2918 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2919 struct intel_plane *intel_plane;
2920 enum pipe pipe = intel_crtc->pipe;
2921 struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
2922 uint16_t alloc_size, start, cursor_blocks;
2923 uint16_t minimum[I915_MAX_PLANES];
2924 uint16_t y_minimum[I915_MAX_PLANES];
2925 unsigned int total_data_rate;
2926
2927 skl_ddb_get_pipe_allocation_limits(dev, cstate, config, alloc);
2928 alloc_size = skl_ddb_entry_size(alloc);
2929 if (alloc_size == 0) {
2930 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
2931 memset(&ddb->plane[pipe][PLANE_CURSOR], 0,
2932 sizeof(ddb->plane[pipe][PLANE_CURSOR]));
2933 return;
2934 }
2935
2936 cursor_blocks = skl_cursor_allocation(config);
2937 ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks;
2938 ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
2939
2940 alloc_size -= cursor_blocks;
2941 alloc->end -= cursor_blocks;
2942
2943 /* 1. Allocate the mininum required blocks for each active plane */
2944 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2945 struct drm_plane *plane = &intel_plane->base;
2946 struct drm_framebuffer *fb = plane->state->fb;
2947 int id = skl_wm_plane_id(intel_plane);
2948
2949 if (fb == NULL)
2950 continue;
2951 if (plane->type == DRM_PLANE_TYPE_CURSOR)
2952 continue;
2953
2954 minimum[id] = 8;
2955 alloc_size -= minimum[id];
2956 y_minimum[id] = (fb->pixel_format == DRM_FORMAT_NV12) ? 8 : 0;
2957 alloc_size -= y_minimum[id];
2958 }
2959
2960 /*
2961 * 2. Distribute the remaining space in proportion to the amount of
2962 * data each plane needs to fetch from memory.
2963 *
2964 * FIXME: we may not allocate every single block here.
2965 */
2966 total_data_rate = skl_get_total_relative_data_rate(cstate);
2967
2968 start = alloc->start;
2969 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2970 struct drm_plane *plane = &intel_plane->base;
2971 struct drm_plane_state *pstate = intel_plane->base.state;
2972 unsigned int data_rate, y_data_rate;
2973 uint16_t plane_blocks, y_plane_blocks = 0;
2974 int id = skl_wm_plane_id(intel_plane);
2975
2976 if (pstate->fb == NULL)
2977 continue;
2978 if (plane->type == DRM_PLANE_TYPE_CURSOR)
2979 continue;
2980
2981 data_rate = skl_plane_relative_data_rate(cstate, pstate, 0);
2982
2983 /*
2984 * allocation for (packed formats) or (uv-plane part of planar format):
2985 * promote the expression to 64 bits to avoid overflowing, the
2986 * result is < available as data_rate / total_data_rate < 1
2987 */
2988 plane_blocks = minimum[id];
2989 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
2990 total_data_rate);
2991
2992 ddb->plane[pipe][id].start = start;
2993 ddb->plane[pipe][id].end = start + plane_blocks;
2994
2995 start += plane_blocks;
2996
2997 /*
2998 * allocation for y_plane part of planar format:
2999 */
3000 if (pstate->fb->pixel_format == DRM_FORMAT_NV12) {
3001 y_data_rate = skl_plane_relative_data_rate(cstate,
3002 pstate,
3003 1);
3004 y_plane_blocks = y_minimum[id];
3005 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3006 total_data_rate);
3007
3008 ddb->y_plane[pipe][id].start = start;
3009 ddb->y_plane[pipe][id].end = start + y_plane_blocks;
3010
3011 start += y_plane_blocks;
3012 }
3013
3014 }
3015
3016 }
3017
3018 static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
3019 {
3020 /* TODO: Take into account the scalers once we support them */
3021 return config->base.adjusted_mode.crtc_clock;
3022 }
3023
3024 /*
3025 * The max latency should be 257 (max the punit can code is 255 and we add 2us
3026 * for the read latency) and bytes_per_pixel should always be <= 8, so that
3027 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3028 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3029 */
3030 static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
3031 uint32_t latency)
3032 {
3033 uint32_t wm_intermediate_val, ret;
3034
3035 if (latency == 0)
3036 return UINT_MAX;
3037
3038 wm_intermediate_val = latency * pixel_rate * bytes_per_pixel / 512;
3039 ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3040
3041 return ret;
3042 }
3043
3044 static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
3045 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
3046 uint64_t tiling, uint32_t latency)
3047 {
3048 uint32_t ret;
3049 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3050 uint32_t wm_intermediate_val;
3051
3052 if (latency == 0)
3053 return UINT_MAX;
3054
3055 plane_bytes_per_line = horiz_pixels * bytes_per_pixel;
3056
3057 if (tiling == I915_FORMAT_MOD_Y_TILED ||
3058 tiling == I915_FORMAT_MOD_Yf_TILED) {
3059 plane_bytes_per_line *= 4;
3060 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3061 plane_blocks_per_line /= 4;
3062 } else {
3063 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3064 }
3065
3066 wm_intermediate_val = latency * pixel_rate;
3067 ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
3068 plane_blocks_per_line;
3069
3070 return ret;
3071 }
3072
3073 static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb,
3074 const struct intel_crtc *intel_crtc)
3075 {
3076 struct drm_device *dev = intel_crtc->base.dev;
3077 struct drm_i915_private *dev_priv = dev->dev_private;
3078 const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
3079
3080 /*
3081 * If ddb allocation of pipes changed, it may require recalculation of
3082 * watermarks
3083 */
3084 if (memcmp(new_ddb->pipe, cur_ddb->pipe, sizeof(new_ddb->pipe)))
3085 return true;
3086
3087 return false;
3088 }
3089
3090 static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3091 struct intel_crtc_state *cstate,
3092 struct intel_plane *intel_plane,
3093 uint16_t ddb_allocation,
3094 int level,
3095 uint16_t *out_blocks, /* out */
3096 uint8_t *out_lines /* out */)
3097 {
3098 struct drm_plane *plane = &intel_plane->base;
3099 struct drm_framebuffer *fb = plane->state->fb;
3100 uint32_t latency = dev_priv->wm.skl_latency[level];
3101 uint32_t method1, method2;
3102 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3103 uint32_t res_blocks, res_lines;
3104 uint32_t selected_result;
3105 uint8_t bytes_per_pixel;
3106
3107 if (latency == 0 || !cstate->base.active || !fb)
3108 return false;
3109
3110 bytes_per_pixel = drm_format_plane_cpp(fb->pixel_format, 0);
3111 method1 = skl_wm_method1(skl_pipe_pixel_rate(cstate),
3112 bytes_per_pixel,
3113 latency);
3114 method2 = skl_wm_method2(skl_pipe_pixel_rate(cstate),
3115 cstate->base.adjusted_mode.crtc_htotal,
3116 cstate->pipe_src_w,
3117 bytes_per_pixel,
3118 fb->modifier[0],
3119 latency);
3120
3121 plane_bytes_per_line = cstate->pipe_src_w * bytes_per_pixel;
3122 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3123
3124 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3125 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
3126 uint32_t min_scanlines = 4;
3127 uint32_t y_tile_minimum;
3128 if (intel_rotation_90_or_270(plane->state->rotation)) {
3129 int bpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
3130 drm_format_plane_cpp(fb->pixel_format, 1) :
3131 drm_format_plane_cpp(fb->pixel_format, 0);
3132
3133 switch (bpp) {
3134 case 1:
3135 min_scanlines = 16;
3136 break;
3137 case 2:
3138 min_scanlines = 8;
3139 break;
3140 case 8:
3141 WARN(1, "Unsupported pixel depth for rotation");
3142 }
3143 }
3144 y_tile_minimum = plane_blocks_per_line * min_scanlines;
3145 selected_result = max(method2, y_tile_minimum);
3146 } else {
3147 if ((ddb_allocation / plane_blocks_per_line) >= 1)
3148 selected_result = min(method1, method2);
3149 else
3150 selected_result = method1;
3151 }
3152
3153 res_blocks = selected_result + 1;
3154 res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
3155
3156 if (level >= 1 && level <= 7) {
3157 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3158 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED)
3159 res_lines += 4;
3160 else
3161 res_blocks++;
3162 }
3163
3164 if (res_blocks >= ddb_allocation || res_lines > 31)
3165 return false;
3166
3167 *out_blocks = res_blocks;
3168 *out_lines = res_lines;
3169
3170 return true;
3171 }
3172
3173 static void skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3174 struct skl_ddb_allocation *ddb,
3175 struct intel_crtc_state *cstate,
3176 int level,
3177 struct skl_wm_level *result)
3178 {
3179 struct drm_device *dev = dev_priv->dev;
3180 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
3181 struct intel_plane *intel_plane;
3182 uint16_t ddb_blocks;
3183 enum pipe pipe = intel_crtc->pipe;
3184
3185 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3186 int i = skl_wm_plane_id(intel_plane);
3187
3188 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3189
3190 result->plane_en[i] = skl_compute_plane_wm(dev_priv,
3191 cstate,
3192 intel_plane,
3193 ddb_blocks,
3194 level,
3195 &result->plane_res_b[i],
3196 &result->plane_res_l[i]);
3197 }
3198 }
3199
3200 static uint32_t
3201 skl_compute_linetime_wm(struct intel_crtc_state *cstate)
3202 {
3203 if (!cstate->base.active)
3204 return 0;
3205
3206 if (WARN_ON(skl_pipe_pixel_rate(cstate) == 0))
3207 return 0;
3208
3209 return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
3210 skl_pipe_pixel_rate(cstate));
3211 }
3212
3213 static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
3214 struct skl_wm_level *trans_wm /* out */)
3215 {
3216 struct drm_crtc *crtc = cstate->base.crtc;
3217 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3218 struct intel_plane *intel_plane;
3219
3220 if (!cstate->base.active)
3221 return;
3222
3223 /* Until we know more, just disable transition WMs */
3224 for_each_intel_plane_on_crtc(crtc->dev, intel_crtc, intel_plane) {
3225 int i = skl_wm_plane_id(intel_plane);
3226
3227 trans_wm->plane_en[i] = false;
3228 }
3229 }
3230
3231 static void skl_compute_pipe_wm(struct intel_crtc_state *cstate,
3232 struct skl_ddb_allocation *ddb,
3233 struct skl_pipe_wm *pipe_wm)
3234 {
3235 struct drm_device *dev = cstate->base.crtc->dev;
3236 const struct drm_i915_private *dev_priv = dev->dev_private;
3237 int level, max_level = ilk_wm_max_level(dev);
3238
3239 for (level = 0; level <= max_level; level++) {
3240 skl_compute_wm_level(dev_priv, ddb, cstate,
3241 level, &pipe_wm->wm[level]);
3242 }
3243 pipe_wm->linetime = skl_compute_linetime_wm(cstate);
3244
3245 skl_compute_transition_wm(cstate, &pipe_wm->trans_wm);
3246 }
3247
3248 static void skl_compute_wm_results(struct drm_device *dev,
3249 struct skl_pipe_wm *p_wm,
3250 struct skl_wm_values *r,
3251 struct intel_crtc *intel_crtc)
3252 {
3253 int level, max_level = ilk_wm_max_level(dev);
3254 enum pipe pipe = intel_crtc->pipe;
3255 uint32_t temp;
3256 int i;
3257
3258 for (level = 0; level <= max_level; level++) {
3259 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3260 temp = 0;
3261
3262 temp |= p_wm->wm[level].plane_res_l[i] <<
3263 PLANE_WM_LINES_SHIFT;
3264 temp |= p_wm->wm[level].plane_res_b[i];
3265 if (p_wm->wm[level].plane_en[i])
3266 temp |= PLANE_WM_EN;
3267
3268 r->plane[pipe][i][level] = temp;
3269 }
3270
3271 temp = 0;
3272
3273 temp |= p_wm->wm[level].plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3274 temp |= p_wm->wm[level].plane_res_b[PLANE_CURSOR];
3275
3276 if (p_wm->wm[level].plane_en[PLANE_CURSOR])
3277 temp |= PLANE_WM_EN;
3278
3279 r->plane[pipe][PLANE_CURSOR][level] = temp;
3280
3281 }
3282
3283 /* transition WMs */
3284 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3285 temp = 0;
3286 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3287 temp |= p_wm->trans_wm.plane_res_b[i];
3288 if (p_wm->trans_wm.plane_en[i])
3289 temp |= PLANE_WM_EN;
3290
3291 r->plane_trans[pipe][i] = temp;
3292 }
3293
3294 temp = 0;
3295 temp |= p_wm->trans_wm.plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3296 temp |= p_wm->trans_wm.plane_res_b[PLANE_CURSOR];
3297 if (p_wm->trans_wm.plane_en[PLANE_CURSOR])
3298 temp |= PLANE_WM_EN;
3299
3300 r->plane_trans[pipe][PLANE_CURSOR] = temp;
3301
3302 r->wm_linetime[pipe] = p_wm->linetime;
3303 }
3304
3305 static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
3306 i915_reg_t reg,
3307 const struct skl_ddb_entry *entry)
3308 {
3309 if (entry->end)
3310 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3311 else
3312 I915_WRITE(reg, 0);
3313 }
3314
3315 static void skl_write_wm_values(struct drm_i915_private *dev_priv,
3316 const struct skl_wm_values *new)
3317 {
3318 struct drm_device *dev = dev_priv->dev;
3319 struct intel_crtc *crtc;
3320
3321 for_each_intel_crtc(dev, crtc) {
3322 int i, level, max_level = ilk_wm_max_level(dev);
3323 enum pipe pipe = crtc->pipe;
3324
3325 if (!new->dirty[pipe])
3326 continue;
3327
3328 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]);
3329
3330 for (level = 0; level <= max_level; level++) {
3331 for (i = 0; i < intel_num_planes(crtc); i++)
3332 I915_WRITE(PLANE_WM(pipe, i, level),
3333 new->plane[pipe][i][level]);
3334 I915_WRITE(CUR_WM(pipe, level),
3335 new->plane[pipe][PLANE_CURSOR][level]);
3336 }
3337 for (i = 0; i < intel_num_planes(crtc); i++)
3338 I915_WRITE(PLANE_WM_TRANS(pipe, i),
3339 new->plane_trans[pipe][i]);
3340 I915_WRITE(CUR_WM_TRANS(pipe),
3341 new->plane_trans[pipe][PLANE_CURSOR]);
3342
3343 for (i = 0; i < intel_num_planes(crtc); i++) {
3344 skl_ddb_entry_write(dev_priv,
3345 PLANE_BUF_CFG(pipe, i),
3346 &new->ddb.plane[pipe][i]);
3347 skl_ddb_entry_write(dev_priv,
3348 PLANE_NV12_BUF_CFG(pipe, i),
3349 &new->ddb.y_plane[pipe][i]);
3350 }
3351
3352 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3353 &new->ddb.plane[pipe][PLANE_CURSOR]);
3354 }
3355 }
3356
3357 /*
3358 * When setting up a new DDB allocation arrangement, we need to correctly
3359 * sequence the times at which the new allocations for the pipes are taken into
3360 * account or we'll have pipes fetching from space previously allocated to
3361 * another pipe.
3362 *
3363 * Roughly the sequence looks like:
3364 * 1. re-allocate the pipe(s) with the allocation being reduced and not
3365 * overlapping with a previous light-up pipe (another way to put it is:
3366 * pipes with their new allocation strickly included into their old ones).
3367 * 2. re-allocate the other pipes that get their allocation reduced
3368 * 3. allocate the pipes having their allocation increased
3369 *
3370 * Steps 1. and 2. are here to take care of the following case:
3371 * - Initially DDB looks like this:
3372 * | B | C |
3373 * - enable pipe A.
3374 * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
3375 * allocation
3376 * | A | B | C |
3377 *
3378 * We need to sequence the re-allocation: C, B, A (and not B, C, A).
3379 */
3380
3381 static void
3382 skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass)
3383 {
3384 int plane;
3385
3386 DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);
3387
3388 for_each_plane(dev_priv, pipe, plane) {
3389 I915_WRITE(PLANE_SURF(pipe, plane),
3390 I915_READ(PLANE_SURF(pipe, plane)));
3391 }
3392 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3393 }
3394
3395 static bool
3396 skl_ddb_allocation_included(const struct skl_ddb_allocation *old,
3397 const struct skl_ddb_allocation *new,
3398 enum pipe pipe)
3399 {
3400 uint16_t old_size, new_size;
3401
3402 old_size = skl_ddb_entry_size(&old->pipe[pipe]);
3403 new_size = skl_ddb_entry_size(&new->pipe[pipe]);
3404
3405 return old_size != new_size &&
3406 new->pipe[pipe].start >= old->pipe[pipe].start &&
3407 new->pipe[pipe].end <= old->pipe[pipe].end;
3408 }
3409
3410 static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
3411 struct skl_wm_values *new_values)
3412 {
3413 struct drm_device *dev = dev_priv->dev;
3414 struct skl_ddb_allocation *cur_ddb, *new_ddb;
3415 bool reallocated[I915_MAX_PIPES] = {};
3416 struct intel_crtc *crtc;
3417 enum pipe pipe;
3418
3419 new_ddb = &new_values->ddb;
3420 cur_ddb = &dev_priv->wm.skl_hw.ddb;
3421
3422 /*
3423 * First pass: flush the pipes with the new allocation contained into
3424 * the old space.
3425 *
3426 * We'll wait for the vblank on those pipes to ensure we can safely
3427 * re-allocate the freed space without this pipe fetching from it.
3428 */
3429 for_each_intel_crtc(dev, crtc) {
3430 if (!crtc->active)
3431 continue;
3432
3433 pipe = crtc->pipe;
3434
3435 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))
3436 continue;
3437
3438 skl_wm_flush_pipe(dev_priv, pipe, 1);
3439 intel_wait_for_vblank(dev, pipe);
3440
3441 reallocated[pipe] = true;
3442 }
3443
3444
3445 /*
3446 * Second pass: flush the pipes that are having their allocation
3447 * reduced, but overlapping with a previous allocation.
3448 *
3449 * Here as well we need to wait for the vblank to make sure the freed
3450 * space is not used anymore.
3451 */
3452 for_each_intel_crtc(dev, crtc) {
3453 if (!crtc->active)
3454 continue;
3455
3456 pipe = crtc->pipe;
3457
3458 if (reallocated[pipe])
3459 continue;
3460
3461 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <
3462 skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
3463 skl_wm_flush_pipe(dev_priv, pipe, 2);
3464 intel_wait_for_vblank(dev, pipe);
3465 reallocated[pipe] = true;
3466 }
3467 }
3468
3469 /*
3470 * Third pass: flush the pipes that got more space allocated.
3471 *
3472 * We don't need to actively wait for the update here, next vblank
3473 * will just get more DDB space with the correct WM values.
3474 */
3475 for_each_intel_crtc(dev, crtc) {
3476 if (!crtc->active)
3477 continue;
3478
3479 pipe = crtc->pipe;
3480
3481 /*
3482 * At this point, only the pipes more space than before are
3483 * left to re-allocate.
3484 */
3485 if (reallocated[pipe])
3486 continue;
3487
3488 skl_wm_flush_pipe(dev_priv, pipe, 3);
3489 }
3490 }
3491
3492 static bool skl_update_pipe_wm(struct drm_crtc *crtc,
3493 struct skl_ddb_allocation *ddb, /* out */
3494 struct skl_pipe_wm *pipe_wm /* out */)
3495 {
3496 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3497 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3498
3499 skl_allocate_pipe_ddb(cstate, ddb);
3500 skl_compute_pipe_wm(cstate, ddb, pipe_wm);
3501
3502 if (!memcmp(&intel_crtc->wm.active.skl, pipe_wm, sizeof(*pipe_wm)))
3503 return false;
3504
3505 intel_crtc->wm.active.skl = *pipe_wm;
3506
3507 return true;
3508 }
3509
3510 static void skl_update_other_pipe_wm(struct drm_device *dev,
3511 struct drm_crtc *crtc,
3512 struct skl_wm_values *r)
3513 {
3514 struct intel_crtc *intel_crtc;
3515 struct intel_crtc *this_crtc = to_intel_crtc(crtc);
3516
3517 /*
3518 * If the WM update hasn't changed the allocation for this_crtc (the
3519 * crtc we are currently computing the new WM values for), other
3520 * enabled crtcs will keep the same allocation and we don't need to
3521 * recompute anything for them.
3522 */
3523 if (!skl_ddb_allocation_changed(&r->ddb, this_crtc))
3524 return;
3525
3526 /*
3527 * Otherwise, because of this_crtc being freshly enabled/disabled, the
3528 * other active pipes need new DDB allocation and WM values.
3529 */
3530 for_each_intel_crtc(dev, intel_crtc) {
3531 struct skl_pipe_wm pipe_wm = {};
3532 bool wm_changed;
3533
3534 if (this_crtc->pipe == intel_crtc->pipe)
3535 continue;
3536
3537 if (!intel_crtc->active)
3538 continue;
3539
3540 wm_changed = skl_update_pipe_wm(&intel_crtc->base,
3541 &r->ddb, &pipe_wm);
3542
3543 /*
3544 * If we end up re-computing the other pipe WM values, it's
3545 * because it was really needed, so we expect the WM values to
3546 * be different.
3547 */
3548 WARN_ON(!wm_changed);
3549
3550 skl_compute_wm_results(dev, &pipe_wm, r, intel_crtc);
3551 r->dirty[intel_crtc->pipe] = true;
3552 }
3553 }
3554
3555 static void skl_clear_wm(struct skl_wm_values *watermarks, enum pipe pipe)
3556 {
3557 watermarks->wm_linetime[pipe] = 0;
3558 memset(watermarks->plane[pipe], 0,
3559 sizeof(uint32_t) * 8 * I915_MAX_PLANES);
3560 memset(watermarks->plane_trans[pipe],
3561 0, sizeof(uint32_t) * I915_MAX_PLANES);
3562 watermarks->plane_trans[pipe][PLANE_CURSOR] = 0;
3563
3564 /* Clear ddb entries for pipe */
3565 memset(&watermarks->ddb.pipe[pipe], 0, sizeof(struct skl_ddb_entry));
3566 memset(&watermarks->ddb.plane[pipe], 0,
3567 sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
3568 memset(&watermarks->ddb.y_plane[pipe], 0,
3569 sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
3570 memset(&watermarks->ddb.plane[pipe][PLANE_CURSOR], 0,
3571 sizeof(struct skl_ddb_entry));
3572
3573 }
3574
3575 static void skl_update_wm(struct drm_crtc *crtc)
3576 {
3577 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3578 struct drm_device *dev = crtc->dev;
3579 struct drm_i915_private *dev_priv = dev->dev_private;
3580 struct skl_wm_values *results = &dev_priv->wm.skl_results;
3581 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3582 struct skl_pipe_wm *pipe_wm = &cstate->wm.optimal.skl;
3583
3584
3585 /* Clear all dirty flags */
3586 memset(results->dirty, 0, sizeof(bool) * I915_MAX_PIPES);
3587
3588 skl_clear_wm(results, intel_crtc->pipe);
3589
3590 if (!skl_update_pipe_wm(crtc, &results->ddb, pipe_wm))
3591 return;
3592
3593 skl_compute_wm_results(dev, pipe_wm, results, intel_crtc);
3594 results->dirty[intel_crtc->pipe] = true;
3595
3596 skl_update_other_pipe_wm(dev, crtc, results);
3597 skl_write_wm_values(dev_priv, results);
3598 skl_flush_wm_values(dev_priv, results);
3599
3600 /* store the new configuration */
3601 dev_priv->wm.skl_hw = *results;
3602 }
3603
3604 static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
3605 {
3606 struct drm_device *dev = dev_priv->dev;
3607 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
3608 struct ilk_wm_maximums max;
3609 struct intel_wm_config *config = &dev_priv->wm.config;
3610 struct ilk_wm_values results = {};
3611 enum intel_ddb_partitioning partitioning;
3612
3613 ilk_compute_wm_maximums(dev, 1, config, INTEL_DDB_PART_1_2, &max);
3614 ilk_wm_merge(dev, config, &max, &lp_wm_1_2);
3615
3616 /* 5/6 split only in single pipe config on IVB+ */
3617 if (INTEL_INFO(dev)->gen >= 7 &&
3618 config->num_pipes_active == 1 && config->sprites_enabled) {
3619 ilk_compute_wm_maximums(dev, 1, config, INTEL_DDB_PART_5_6, &max);
3620 ilk_wm_merge(dev, config, &max, &lp_wm_5_6);
3621
3622 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
3623 } else {
3624 best_lp_wm = &lp_wm_1_2;
3625 }
3626
3627 partitioning = (best_lp_wm == &lp_wm_1_2) ?
3628 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
3629
3630 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
3631
3632 ilk_write_wm_values(dev_priv, &results);
3633 }
3634
3635 static void ilk_update_wm(struct drm_crtc *crtc)
3636 {
3637 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
3638 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3639 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3640
3641 WARN_ON(cstate->base.active != intel_crtc->active);
3642
3643 /*
3644 * IVB workaround: must disable low power watermarks for at least
3645 * one frame before enabling scaling. LP watermarks can be re-enabled
3646 * when scaling is disabled.
3647 *
3648 * WaCxSRDisabledForSpriteScaling:ivb
3649 */
3650 if (cstate->disable_lp_wm) {
3651 ilk_disable_lp_wm(crtc->dev);
3652 intel_wait_for_vblank(crtc->dev, intel_crtc->pipe);
3653 }
3654
3655 intel_crtc->wm.active.ilk = cstate->wm.optimal.ilk;
3656
3657 ilk_program_watermarks(dev_priv);
3658 }
3659
3660 static void skl_pipe_wm_active_state(uint32_t val,
3661 struct skl_pipe_wm *active,
3662 bool is_transwm,
3663 bool is_cursor,
3664 int i,
3665 int level)
3666 {
3667 bool is_enabled = (val & PLANE_WM_EN) != 0;
3668
3669 if (!is_transwm) {
3670 if (!is_cursor) {
3671 active->wm[level].plane_en[i] = is_enabled;
3672 active->wm[level].plane_res_b[i] =
3673 val & PLANE_WM_BLOCKS_MASK;
3674 active->wm[level].plane_res_l[i] =
3675 (val >> PLANE_WM_LINES_SHIFT) &
3676 PLANE_WM_LINES_MASK;
3677 } else {
3678 active->wm[level].plane_en[PLANE_CURSOR] = is_enabled;
3679 active->wm[level].plane_res_b[PLANE_CURSOR] =
3680 val & PLANE_WM_BLOCKS_MASK;
3681 active->wm[level].plane_res_l[PLANE_CURSOR] =
3682 (val >> PLANE_WM_LINES_SHIFT) &
3683 PLANE_WM_LINES_MASK;
3684 }
3685 } else {
3686 if (!is_cursor) {
3687 active->trans_wm.plane_en[i] = is_enabled;
3688 active->trans_wm.plane_res_b[i] =
3689 val & PLANE_WM_BLOCKS_MASK;
3690 active->trans_wm.plane_res_l[i] =
3691 (val >> PLANE_WM_LINES_SHIFT) &
3692 PLANE_WM_LINES_MASK;
3693 } else {
3694 active->trans_wm.plane_en[PLANE_CURSOR] = is_enabled;
3695 active->trans_wm.plane_res_b[PLANE_CURSOR] =
3696 val & PLANE_WM_BLOCKS_MASK;
3697 active->trans_wm.plane_res_l[PLANE_CURSOR] =
3698 (val >> PLANE_WM_LINES_SHIFT) &
3699 PLANE_WM_LINES_MASK;
3700 }
3701 }
3702 }
3703
3704 static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3705 {
3706 struct drm_device *dev = crtc->dev;
3707 struct drm_i915_private *dev_priv = dev->dev_private;
3708 struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
3709 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3710 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3711 struct skl_pipe_wm *active = &cstate->wm.optimal.skl;
3712 enum pipe pipe = intel_crtc->pipe;
3713 int level, i, max_level;
3714 uint32_t temp;
3715
3716 max_level = ilk_wm_max_level(dev);
3717
3718 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3719
3720 for (level = 0; level <= max_level; level++) {
3721 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3722 hw->plane[pipe][i][level] =
3723 I915_READ(PLANE_WM(pipe, i, level));
3724 hw->plane[pipe][PLANE_CURSOR][level] = I915_READ(CUR_WM(pipe, level));
3725 }
3726
3727 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3728 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
3729 hw->plane_trans[pipe][PLANE_CURSOR] = I915_READ(CUR_WM_TRANS(pipe));
3730
3731 if (!intel_crtc->active)
3732 return;
3733
3734 hw->dirty[pipe] = true;
3735
3736 active->linetime = hw->wm_linetime[pipe];
3737
3738 for (level = 0; level <= max_level; level++) {
3739 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3740 temp = hw->plane[pipe][i][level];
3741 skl_pipe_wm_active_state(temp, active, false,
3742 false, i, level);
3743 }
3744 temp = hw->plane[pipe][PLANE_CURSOR][level];
3745 skl_pipe_wm_active_state(temp, active, false, true, i, level);
3746 }
3747
3748 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3749 temp = hw->plane_trans[pipe][i];
3750 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
3751 }
3752
3753 temp = hw->plane_trans[pipe][PLANE_CURSOR];
3754 skl_pipe_wm_active_state(temp, active, true, true, i, 0);
3755
3756 intel_crtc->wm.active.skl = *active;
3757 }
3758
3759 void skl_wm_get_hw_state(struct drm_device *dev)
3760 {
3761 struct drm_i915_private *dev_priv = dev->dev_private;
3762 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3763 struct drm_crtc *crtc;
3764
3765 skl_ddb_get_hw_state(dev_priv, ddb);
3766 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3767 skl_pipe_wm_get_hw_state(crtc);
3768 }
3769
3770 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3771 {
3772 struct drm_device *dev = crtc->dev;
3773 struct drm_i915_private *dev_priv = dev->dev_private;
3774 struct ilk_wm_values *hw = &dev_priv->wm.hw;
3775 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3776 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3777 struct intel_pipe_wm *active = &cstate->wm.optimal.ilk;
3778 enum pipe pipe = intel_crtc->pipe;
3779 static const i915_reg_t wm0_pipe_reg[] = {
3780 [PIPE_A] = WM0_PIPEA_ILK,
3781 [PIPE_B] = WM0_PIPEB_ILK,
3782 [PIPE_C] = WM0_PIPEC_IVB,
3783 };
3784
3785 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
3786 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3787 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3788
3789 active->pipe_enabled = intel_crtc->active;
3790
3791 if (active->pipe_enabled) {
3792 u32 tmp = hw->wm_pipe[pipe];
3793
3794 /*
3795 * For active pipes LP0 watermark is marked as
3796 * enabled, and LP1+ watermaks as disabled since
3797 * we can't really reverse compute them in case
3798 * multiple pipes are active.
3799 */
3800 active->wm[0].enable = true;
3801 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3802 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3803 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3804 active->linetime = hw->wm_linetime[pipe];
3805 } else {
3806 int level, max_level = ilk_wm_max_level(dev);
3807
3808 /*
3809 * For inactive pipes, all watermark levels
3810 * should be marked as enabled but zeroed,
3811 * which is what we'd compute them to.
3812 */
3813 for (level = 0; level <= max_level; level++)
3814 active->wm[level].enable = true;
3815 }
3816
3817 intel_crtc->wm.active.ilk = *active;
3818 }
3819
3820 #define _FW_WM(value, plane) \
3821 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
3822 #define _FW_WM_VLV(value, plane) \
3823 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
3824
3825 static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
3826 struct vlv_wm_values *wm)
3827 {
3828 enum pipe pipe;
3829 uint32_t tmp;
3830
3831 for_each_pipe(dev_priv, pipe) {
3832 tmp = I915_READ(VLV_DDL(pipe));
3833
3834 wm->ddl[pipe].primary =
3835 (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3836 wm->ddl[pipe].cursor =
3837 (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3838 wm->ddl[pipe].sprite[0] =
3839 (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3840 wm->ddl[pipe].sprite[1] =
3841 (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3842 }
3843
3844 tmp = I915_READ(DSPFW1);
3845 wm->sr.plane = _FW_WM(tmp, SR);
3846 wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
3847 wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
3848 wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
3849
3850 tmp = I915_READ(DSPFW2);
3851 wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
3852 wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
3853 wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
3854
3855 tmp = I915_READ(DSPFW3);
3856 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
3857
3858 if (IS_CHERRYVIEW(dev_priv)) {
3859 tmp = I915_READ(DSPFW7_CHV);
3860 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
3861 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
3862
3863 tmp = I915_READ(DSPFW8_CHV);
3864 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
3865 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
3866
3867 tmp = I915_READ(DSPFW9_CHV);
3868 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
3869 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
3870
3871 tmp = I915_READ(DSPHOWM);
3872 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
3873 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
3874 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
3875 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
3876 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
3877 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
3878 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
3879 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
3880 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
3881 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
3882 } else {
3883 tmp = I915_READ(DSPFW7);
3884 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
3885 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
3886
3887 tmp = I915_READ(DSPHOWM);
3888 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
3889 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
3890 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
3891 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
3892 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
3893 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
3894 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
3895 }
3896 }
3897
3898 #undef _FW_WM
3899 #undef _FW_WM_VLV
3900
3901 void vlv_wm_get_hw_state(struct drm_device *dev)
3902 {
3903 struct drm_i915_private *dev_priv = to_i915(dev);
3904 struct vlv_wm_values *wm = &dev_priv->wm.vlv;
3905 struct intel_plane *plane;
3906 enum pipe pipe;
3907 u32 val;
3908
3909 vlv_read_wm_values(dev_priv, wm);
3910
3911 for_each_intel_plane(dev, plane) {
3912 switch (plane->base.type) {
3913 int sprite;
3914 case DRM_PLANE_TYPE_CURSOR:
3915 plane->wm.fifo_size = 63;
3916 break;
3917 case DRM_PLANE_TYPE_PRIMARY:
3918 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
3919 break;
3920 case DRM_PLANE_TYPE_OVERLAY:
3921 sprite = plane->plane;
3922 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
3923 break;
3924 }
3925 }
3926
3927 wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
3928 wm->level = VLV_WM_LEVEL_PM2;
3929
3930 if (IS_CHERRYVIEW(dev_priv)) {
3931 mutex_lock(&dev_priv->rps.hw_lock);
3932
3933 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
3934 if (val & DSP_MAXFIFO_PM5_ENABLE)
3935 wm->level = VLV_WM_LEVEL_PM5;
3936
3937 /*
3938 * If DDR DVFS is disabled in the BIOS, Punit
3939 * will never ack the request. So if that happens
3940 * assume we don't have to enable/disable DDR DVFS
3941 * dynamically. To test that just set the REQ_ACK
3942 * bit to poke the Punit, but don't change the
3943 * HIGH/LOW bits so that we don't actually change
3944 * the current state.
3945 */
3946 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
3947 val |= FORCE_DDR_FREQ_REQ_ACK;
3948 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
3949
3950 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
3951 FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
3952 DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
3953 "assuming DDR DVFS is disabled\n");
3954 dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
3955 } else {
3956 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
3957 if ((val & FORCE_DDR_HIGH_FREQ) == 0)
3958 wm->level = VLV_WM_LEVEL_DDR_DVFS;
3959 }
3960
3961 mutex_unlock(&dev_priv->rps.hw_lock);
3962 }
3963
3964 for_each_pipe(dev_priv, pipe)
3965 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
3966 pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
3967 wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
3968
3969 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
3970 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
3971 }
3972
3973 void ilk_wm_get_hw_state(struct drm_device *dev)
3974 {
3975 struct drm_i915_private *dev_priv = dev->dev_private;
3976 struct ilk_wm_values *hw = &dev_priv->wm.hw;
3977 struct drm_crtc *crtc;
3978
3979 for_each_crtc(dev, crtc)
3980 ilk_pipe_wm_get_hw_state(crtc);
3981
3982 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
3983 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
3984 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
3985
3986 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
3987 if (INTEL_INFO(dev)->gen >= 7) {
3988 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
3989 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
3990 }
3991
3992 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3993 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
3994 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
3995 else if (IS_IVYBRIDGE(dev))
3996 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
3997 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
3998
3999 hw->enable_fbc_wm =
4000 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4001 }
4002
4003 /**
4004 * intel_update_watermarks - update FIFO watermark values based on current modes
4005 *
4006 * Calculate watermark values for the various WM regs based on current mode
4007 * and plane configuration.
4008 *
4009 * There are several cases to deal with here:
4010 * - normal (i.e. non-self-refresh)
4011 * - self-refresh (SR) mode
4012 * - lines are large relative to FIFO size (buffer can hold up to 2)
4013 * - lines are small relative to FIFO size (buffer can hold more than 2
4014 * lines), so need to account for TLB latency
4015 *
4016 * The normal calculation is:
4017 * watermark = dotclock * bytes per pixel * latency
4018 * where latency is platform & configuration dependent (we assume pessimal
4019 * values here).
4020 *
4021 * The SR calculation is:
4022 * watermark = (trunc(latency/line time)+1) * surface width *
4023 * bytes per pixel
4024 * where
4025 * line time = htotal / dotclock
4026 * surface width = hdisplay for normal plane and 64 for cursor
4027 * and latency is assumed to be high, as above.
4028 *
4029 * The final value programmed to the register should always be rounded up,
4030 * and include an extra 2 entries to account for clock crossings.
4031 *
4032 * We don't use the sprite, so we can ignore that. And on Crestline we have
4033 * to set the non-SR watermarks to 8.
4034 */
4035 void intel_update_watermarks(struct drm_crtc *crtc)
4036 {
4037 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4038
4039 if (dev_priv->display.update_wm)
4040 dev_priv->display.update_wm(crtc);
4041 }
4042
4043 /**
4044 * Lock protecting IPS related data structures
4045 */
4046 DEFINE_SPINLOCK(mchdev_lock);
4047
4048 /* Global for IPS driver to get at the current i915 device. Protected by
4049 * mchdev_lock. */
4050 static struct drm_i915_private *i915_mch_dev;
4051
4052 bool ironlake_set_drps(struct drm_device *dev, u8 val)
4053 {
4054 struct drm_i915_private *dev_priv = dev->dev_private;
4055 u16 rgvswctl;
4056
4057 assert_spin_locked(&mchdev_lock);
4058
4059 rgvswctl = I915_READ16(MEMSWCTL);
4060 if (rgvswctl & MEMCTL_CMD_STS) {
4061 DRM_DEBUG("gpu busy, RCS change rejected\n");
4062 return false; /* still busy with another command */
4063 }
4064
4065 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4066 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4067 I915_WRITE16(MEMSWCTL, rgvswctl);
4068 POSTING_READ16(MEMSWCTL);
4069
4070 rgvswctl |= MEMCTL_CMD_STS;
4071 I915_WRITE16(MEMSWCTL, rgvswctl);
4072
4073 return true;
4074 }
4075
4076 static void ironlake_enable_drps(struct drm_device *dev)
4077 {
4078 struct drm_i915_private *dev_priv = dev->dev_private;
4079 u32 rgvmodectl = I915_READ(MEMMODECTL);
4080 u8 fmax, fmin, fstart, vstart;
4081
4082 spin_lock_irq(&mchdev_lock);
4083
4084 /* Enable temp reporting */
4085 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4086 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4087
4088 /* 100ms RC evaluation intervals */
4089 I915_WRITE(RCUPEI, 100000);
4090 I915_WRITE(RCDNEI, 100000);
4091
4092 /* Set max/min thresholds to 90ms and 80ms respectively */
4093 I915_WRITE(RCBMAXAVG, 90000);
4094 I915_WRITE(RCBMINAVG, 80000);
4095
4096 I915_WRITE(MEMIHYST, 1);
4097
4098 /* Set up min, max, and cur for interrupt handling */
4099 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4100 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4101 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4102 MEMMODE_FSTART_SHIFT;
4103
4104 vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
4105 PXVFREQ_PX_SHIFT;
4106
4107 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4108 dev_priv->ips.fstart = fstart;
4109
4110 dev_priv->ips.max_delay = fstart;
4111 dev_priv->ips.min_delay = fmin;
4112 dev_priv->ips.cur_delay = fstart;
4113
4114 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4115 fmax, fmin, fstart);
4116
4117 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4118
4119 /*
4120 * Interrupts will be enabled in ironlake_irq_postinstall
4121 */
4122
4123 I915_WRITE(VIDSTART, vstart);
4124 POSTING_READ(VIDSTART);
4125
4126 rgvmodectl |= MEMMODE_SWMODE_EN;
4127 I915_WRITE(MEMMODECTL, rgvmodectl);
4128
4129 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
4130 DRM_ERROR("stuck trying to change perf mode\n");
4131 mdelay(1);
4132
4133 ironlake_set_drps(dev, fstart);
4134
4135 dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4136 I915_READ(DDREC) + I915_READ(CSIEC);
4137 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
4138 dev_priv->ips.last_count2 = I915_READ(GFXEC);
4139 dev_priv->ips.last_time2 = ktime_get_raw_ns();
4140
4141 spin_unlock_irq(&mchdev_lock);
4142 }
4143
4144 static void ironlake_disable_drps(struct drm_device *dev)
4145 {
4146 struct drm_i915_private *dev_priv = dev->dev_private;
4147 u16 rgvswctl;
4148
4149 spin_lock_irq(&mchdev_lock);
4150
4151 rgvswctl = I915_READ16(MEMSWCTL);
4152
4153 /* Ack interrupts, disable EFC interrupt */
4154 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4155 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4156 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4157 I915_WRITE(DEIIR, DE_PCU_EVENT);
4158 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4159
4160 /* Go back to the starting frequency */
4161 ironlake_set_drps(dev, dev_priv->ips.fstart);
4162 mdelay(1);
4163 rgvswctl |= MEMCTL_CMD_STS;
4164 I915_WRITE(MEMSWCTL, rgvswctl);
4165 mdelay(1);
4166
4167 spin_unlock_irq(&mchdev_lock);
4168 }
4169
4170 /* There's a funny hw issue where the hw returns all 0 when reading from
4171 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4172 * ourselves, instead of doing a rmw cycle (which might result in us clearing
4173 * all limits and the gpu stuck at whatever frequency it is at atm).
4174 */
4175 static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
4176 {
4177 u32 limits;
4178
4179 /* Only set the down limit when we've reached the lowest level to avoid
4180 * getting more interrupts, otherwise leave this clear. This prevents a
4181 * race in the hw when coming out of rc6: There's a tiny window where
4182 * the hw runs at the minimal clock before selecting the desired
4183 * frequency, if the down threshold expires in that window we will not
4184 * receive a down interrupt. */
4185 if (IS_GEN9(dev_priv->dev)) {
4186 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4187 if (val <= dev_priv->rps.min_freq_softlimit)
4188 limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4189 } else {
4190 limits = dev_priv->rps.max_freq_softlimit << 24;
4191 if (val <= dev_priv->rps.min_freq_softlimit)
4192 limits |= dev_priv->rps.min_freq_softlimit << 16;
4193 }
4194
4195 return limits;
4196 }
4197
4198 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4199 {
4200 int new_power;
4201 u32 threshold_up = 0, threshold_down = 0; /* in % */
4202 u32 ei_up = 0, ei_down = 0;
4203
4204 new_power = dev_priv->rps.power;
4205 switch (dev_priv->rps.power) {
4206 case LOW_POWER:
4207 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
4208 new_power = BETWEEN;
4209 break;
4210
4211 case BETWEEN:
4212 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
4213 new_power = LOW_POWER;
4214 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
4215 new_power = HIGH_POWER;
4216 break;
4217
4218 case HIGH_POWER:
4219 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
4220 new_power = BETWEEN;
4221 break;
4222 }
4223 /* Max/min bins are special */
4224 if (val <= dev_priv->rps.min_freq_softlimit)
4225 new_power = LOW_POWER;
4226 if (val >= dev_priv->rps.max_freq_softlimit)
4227 new_power = HIGH_POWER;
4228 if (new_power == dev_priv->rps.power)
4229 return;
4230
4231 /* Note the units here are not exactly 1us, but 1280ns. */
4232 switch (new_power) {
4233 case LOW_POWER:
4234 /* Upclock if more than 95% busy over 16ms */
4235 ei_up = 16000;
4236 threshold_up = 95;
4237
4238 /* Downclock if less than 85% busy over 32ms */
4239 ei_down = 32000;
4240 threshold_down = 85;
4241 break;
4242
4243 case BETWEEN:
4244 /* Upclock if more than 90% busy over 13ms */
4245 ei_up = 13000;
4246 threshold_up = 90;
4247
4248 /* Downclock if less than 75% busy over 32ms */
4249 ei_down = 32000;
4250 threshold_down = 75;
4251 break;
4252
4253 case HIGH_POWER:
4254 /* Upclock if more than 85% busy over 10ms */
4255 ei_up = 10000;
4256 threshold_up = 85;
4257
4258 /* Downclock if less than 60% busy over 32ms */
4259 ei_down = 32000;
4260 threshold_down = 60;
4261 break;
4262 }
4263
4264 I915_WRITE(GEN6_RP_UP_EI,
4265 GT_INTERVAL_FROM_US(dev_priv, ei_up));
4266 I915_WRITE(GEN6_RP_UP_THRESHOLD,
4267 GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100)));
4268
4269 I915_WRITE(GEN6_RP_DOWN_EI,
4270 GT_INTERVAL_FROM_US(dev_priv, ei_down));
4271 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4272 GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100)));
4273
4274 I915_WRITE(GEN6_RP_CONTROL,
4275 GEN6_RP_MEDIA_TURBO |
4276 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4277 GEN6_RP_MEDIA_IS_GFX |
4278 GEN6_RP_ENABLE |
4279 GEN6_RP_UP_BUSY_AVG |
4280 GEN6_RP_DOWN_IDLE_AVG);
4281
4282 dev_priv->rps.power = new_power;
4283 dev_priv->rps.up_threshold = threshold_up;
4284 dev_priv->rps.down_threshold = threshold_down;
4285 dev_priv->rps.last_adj = 0;
4286 }
4287
4288 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4289 {
4290 u32 mask = 0;
4291
4292 if (val > dev_priv->rps.min_freq_softlimit)
4293 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
4294 if (val < dev_priv->rps.max_freq_softlimit)
4295 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
4296
4297 mask &= dev_priv->pm_rps_events;
4298
4299 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
4300 }
4301
4302 /* gen6_set_rps is called to update the frequency request, but should also be
4303 * called when the range (min_delay and max_delay) is modified so that we can
4304 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
4305 static void gen6_set_rps(struct drm_device *dev, u8 val)
4306 {
4307 struct drm_i915_private *dev_priv = dev->dev_private;
4308
4309 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4310 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
4311 return;
4312
4313 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4314 WARN_ON(val > dev_priv->rps.max_freq);
4315 WARN_ON(val < dev_priv->rps.min_freq);
4316
4317 /* min/max delay may still have been modified so be sure to
4318 * write the limits value.
4319 */
4320 if (val != dev_priv->rps.cur_freq) {
4321 gen6_set_rps_thresholds(dev_priv, val);
4322
4323 if (IS_GEN9(dev))
4324 I915_WRITE(GEN6_RPNSWREQ,
4325 GEN9_FREQUENCY(val));
4326 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4327 I915_WRITE(GEN6_RPNSWREQ,
4328 HSW_FREQUENCY(val));
4329 else
4330 I915_WRITE(GEN6_RPNSWREQ,
4331 GEN6_FREQUENCY(val) |
4332 GEN6_OFFSET(0) |
4333 GEN6_AGGRESSIVE_TURBO);
4334 }
4335
4336 /* Make sure we continue to get interrupts
4337 * until we hit the minimum or maximum frequencies.
4338 */
4339 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
4340 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4341
4342 POSTING_READ(GEN6_RPNSWREQ);
4343
4344 dev_priv->rps.cur_freq = val;
4345 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4346 }
4347
4348 static void valleyview_set_rps(struct drm_device *dev, u8 val)
4349 {
4350 struct drm_i915_private *dev_priv = dev->dev_private;
4351
4352 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4353 WARN_ON(val > dev_priv->rps.max_freq);
4354 WARN_ON(val < dev_priv->rps.min_freq);
4355
4356 if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1),
4357 "Odd GPU freq value\n"))
4358 val &= ~1;
4359
4360 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4361
4362 if (val != dev_priv->rps.cur_freq) {
4363 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
4364 if (!IS_CHERRYVIEW(dev_priv))
4365 gen6_set_rps_thresholds(dev_priv, val);
4366 }
4367
4368 dev_priv->rps.cur_freq = val;
4369 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4370 }
4371
4372 /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
4373 *
4374 * * If Gfx is Idle, then
4375 * 1. Forcewake Media well.
4376 * 2. Request idle freq.
4377 * 3. Release Forcewake of Media well.
4378 */
4379 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4380 {
4381 u32 val = dev_priv->rps.idle_freq;
4382
4383 if (dev_priv->rps.cur_freq <= val)
4384 return;
4385
4386 /* Wake up the media well, as that takes a lot less
4387 * power than the Render well. */
4388 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
4389 valleyview_set_rps(dev_priv->dev, val);
4390 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
4391 }
4392
4393 void gen6_rps_busy(struct drm_i915_private *dev_priv)
4394 {
4395 mutex_lock(&dev_priv->rps.hw_lock);
4396 if (dev_priv->rps.enabled) {
4397 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
4398 gen6_rps_reset_ei(dev_priv);
4399 I915_WRITE(GEN6_PMINTRMSK,
4400 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
4401 }
4402 mutex_unlock(&dev_priv->rps.hw_lock);
4403 }
4404
4405 void gen6_rps_idle(struct drm_i915_private *dev_priv)
4406 {
4407 struct drm_device *dev = dev_priv->dev;
4408
4409 mutex_lock(&dev_priv->rps.hw_lock);
4410 if (dev_priv->rps.enabled) {
4411 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
4412 vlv_set_rps_idle(dev_priv);
4413 else
4414 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
4415 dev_priv->rps.last_adj = 0;
4416 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
4417 }
4418 mutex_unlock(&dev_priv->rps.hw_lock);
4419
4420 spin_lock(&dev_priv->rps.client_lock);
4421 while (!list_empty(&dev_priv->rps.clients))
4422 list_del_init(dev_priv->rps.clients.next);
4423 spin_unlock(&dev_priv->rps.client_lock);
4424 }
4425
4426 void gen6_rps_boost(struct drm_i915_private *dev_priv,
4427 struct intel_rps_client *rps,
4428 unsigned long submitted)
4429 {
4430 /* This is intentionally racy! We peek at the state here, then
4431 * validate inside the RPS worker.
4432 */
4433 if (!(dev_priv->mm.busy &&
4434 dev_priv->rps.enabled &&
4435 dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit))
4436 return;
4437
4438 /* Force a RPS boost (and don't count it against the client) if
4439 * the GPU is severely congested.
4440 */
4441 if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
4442 rps = NULL;
4443
4444 spin_lock(&dev_priv->rps.client_lock);
4445 if (rps == NULL || list_empty(&rps->link)) {
4446 spin_lock_irq(&dev_priv->irq_lock);
4447 if (dev_priv->rps.interrupts_enabled) {
4448 dev_priv->rps.client_boost = true;
4449 queue_work(dev_priv->wq, &dev_priv->rps.work);
4450 }
4451 spin_unlock_irq(&dev_priv->irq_lock);
4452
4453 if (rps != NULL) {
4454 list_add(&rps->link, &dev_priv->rps.clients);
4455 rps->boosts++;
4456 } else
4457 dev_priv->rps.boosts++;
4458 }
4459 spin_unlock(&dev_priv->rps.client_lock);
4460 }
4461
4462 void intel_set_rps(struct drm_device *dev, u8 val)
4463 {
4464 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
4465 valleyview_set_rps(dev, val);
4466 else
4467 gen6_set_rps(dev, val);
4468 }
4469
4470 static void gen9_disable_rps(struct drm_device *dev)
4471 {
4472 struct drm_i915_private *dev_priv = dev->dev_private;
4473
4474 I915_WRITE(GEN6_RC_CONTROL, 0);
4475 I915_WRITE(GEN9_PG_ENABLE, 0);
4476 }
4477
4478 static void gen6_disable_rps(struct drm_device *dev)
4479 {
4480 struct drm_i915_private *dev_priv = dev->dev_private;
4481
4482 I915_WRITE(GEN6_RC_CONTROL, 0);
4483 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
4484 }
4485
4486 static void cherryview_disable_rps(struct drm_device *dev)
4487 {
4488 struct drm_i915_private *dev_priv = dev->dev_private;
4489
4490 I915_WRITE(GEN6_RC_CONTROL, 0);
4491 }
4492
4493 static void valleyview_disable_rps(struct drm_device *dev)
4494 {
4495 struct drm_i915_private *dev_priv = dev->dev_private;
4496
4497 /* we're doing forcewake before Disabling RC6,
4498 * This what the BIOS expects when going into suspend */
4499 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4500
4501 I915_WRITE(GEN6_RC_CONTROL, 0);
4502
4503 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4504 }
4505
4506 static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
4507 {
4508 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
4509 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
4510 mode = GEN6_RC_CTL_RC6_ENABLE;
4511 else
4512 mode = 0;
4513 }
4514 if (HAS_RC6p(dev))
4515 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
4516 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
4517 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
4518 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
4519
4520 else
4521 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
4522 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off");
4523 }
4524
4525 static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
4526 {
4527 /* No RC6 before Ironlake and code is gone for ilk. */
4528 if (INTEL_INFO(dev)->gen < 6)
4529 return 0;
4530
4531 /* Respect the kernel parameter if it is set */
4532 if (enable_rc6 >= 0) {
4533 int mask;
4534
4535 if (HAS_RC6p(dev))
4536 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
4537 INTEL_RC6pp_ENABLE;
4538 else
4539 mask = INTEL_RC6_ENABLE;
4540
4541 if ((enable_rc6 & mask) != enable_rc6)
4542 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
4543 enable_rc6 & mask, enable_rc6, mask);
4544
4545 return enable_rc6 & mask;
4546 }
4547
4548 if (IS_IVYBRIDGE(dev))
4549 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
4550
4551 return INTEL_RC6_ENABLE;
4552 }
4553
4554 int intel_enable_rc6(const struct drm_device *dev)
4555 {
4556 return i915.enable_rc6;
4557 }
4558
4559 static void gen6_init_rps_frequencies(struct drm_device *dev)
4560 {
4561 struct drm_i915_private *dev_priv = dev->dev_private;
4562 uint32_t rp_state_cap;
4563 u32 ddcc_status = 0;
4564 int ret;
4565
4566 /* All of these values are in units of 50MHz */
4567 dev_priv->rps.cur_freq = 0;
4568 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
4569 if (IS_BROXTON(dev)) {
4570 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
4571 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
4572 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
4573 dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff;
4574 } else {
4575 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
4576 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
4577 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
4578 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
4579 }
4580
4581 /* hw_max = RP0 until we check for overclocking */
4582 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
4583
4584 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
4585 if (IS_HASWELL(dev) || IS_BROADWELL(dev) ||
4586 IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
4587 ret = sandybridge_pcode_read(dev_priv,
4588 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
4589 &ddcc_status);
4590 if (0 == ret)
4591 dev_priv->rps.efficient_freq =
4592 clamp_t(u8,
4593 ((ddcc_status >> 8) & 0xff),
4594 dev_priv->rps.min_freq,
4595 dev_priv->rps.max_freq);
4596 }
4597
4598 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
4599 /* Store the frequency values in 16.66 MHZ units, which is
4600 the natural hardware unit for SKL */
4601 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
4602 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
4603 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
4604 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
4605 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
4606 }
4607
4608 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
4609
4610 /* Preserve min/max settings in case of re-init */
4611 if (dev_priv->rps.max_freq_softlimit == 0)
4612 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4613
4614 if (dev_priv->rps.min_freq_softlimit == 0) {
4615 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4616 dev_priv->rps.min_freq_softlimit =
4617 max_t(int, dev_priv->rps.efficient_freq,
4618 intel_freq_opcode(dev_priv, 450));
4619 else
4620 dev_priv->rps.min_freq_softlimit =
4621 dev_priv->rps.min_freq;
4622 }
4623 }
4624
4625 /* See the Gen9_GT_PM_Programming_Guide doc for the below */
4626 static void gen9_enable_rps(struct drm_device *dev)
4627 {
4628 struct drm_i915_private *dev_priv = dev->dev_private;
4629
4630 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4631
4632 gen6_init_rps_frequencies(dev);
4633
4634 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4635 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
4636 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4637 return;
4638 }
4639
4640 /* Program defaults and thresholds for RPS*/
4641 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4642 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
4643
4644 /* 1 second timeout*/
4645 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
4646 GT_INTERVAL_FROM_US(dev_priv, 1000000));
4647
4648 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
4649
4650 /* Leaning on the below call to gen6_set_rps to program/setup the
4651 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
4652 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
4653 dev_priv->rps.power = HIGH_POWER; /* force a reset */
4654 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
4655
4656 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4657 }
4658
4659 static void gen9_enable_rc6(struct drm_device *dev)
4660 {
4661 struct drm_i915_private *dev_priv = dev->dev_private;
4662 struct intel_engine_cs *ring;
4663 uint32_t rc6_mask = 0;
4664 int unused;
4665
4666 /* 1a: Software RC state - RC0 */
4667 I915_WRITE(GEN6_RC_STATE, 0);
4668
4669 /* 1b: Get forcewake during program sequence. Although the driver
4670 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4671 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4672
4673 /* 2a: Disable RC states. */
4674 I915_WRITE(GEN6_RC_CONTROL, 0);
4675
4676 /* 2b: Program RC6 thresholds.*/
4677
4678 /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
4679 if (IS_SKYLAKE(dev))
4680 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
4681 else
4682 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
4683 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4684 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4685 for_each_ring(ring, dev_priv, unused)
4686 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4687
4688 if (HAS_GUC_UCODE(dev))
4689 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
4690
4691 I915_WRITE(GEN6_RC_SLEEP, 0);
4692
4693 /* 2c: Program Coarse Power Gating Policies. */
4694 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
4695 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
4696
4697 /* 3a: Enable RC6 */
4698 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4699 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4700 DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4701 "on" : "off");
4702 /* WaRsUseTimeoutMode */
4703 if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) ||
4704 IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
4705 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
4706 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4707 GEN7_RC_CTL_TO_MODE |
4708 rc6_mask);
4709 } else {
4710 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
4711 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4712 GEN6_RC_CTL_EI_MODE(1) |
4713 rc6_mask);
4714 }
4715
4716 /*
4717 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
4718 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
4719 */
4720 if ((IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) ||
4721 ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && (INTEL_REVID(dev) <= SKL_REVID_F0)))
4722 I915_WRITE(GEN9_PG_ENABLE, 0);
4723 else
4724 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4725 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
4726
4727 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4728
4729 }
4730
4731 static void gen8_enable_rps(struct drm_device *dev)
4732 {
4733 struct drm_i915_private *dev_priv = dev->dev_private;
4734 struct intel_engine_cs *ring;
4735 uint32_t rc6_mask = 0;
4736 int unused;
4737
4738 /* 1a: Software RC state - RC0 */
4739 I915_WRITE(GEN6_RC_STATE, 0);
4740
4741 /* 1c & 1d: Get forcewake during program sequence. Although the driver
4742 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4743 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4744
4745 /* 2a: Disable RC states. */
4746 I915_WRITE(GEN6_RC_CONTROL, 0);
4747
4748 /* Initialize rps frequencies */
4749 gen6_init_rps_frequencies(dev);
4750
4751 /* 2b: Program RC6 thresholds.*/
4752 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4753 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4754 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4755 for_each_ring(ring, dev_priv, unused)
4756 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4757 I915_WRITE(GEN6_RC_SLEEP, 0);
4758 if (IS_BROADWELL(dev))
4759 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
4760 else
4761 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
4762
4763 /* 3: Enable RC6 */
4764 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4765 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4766 intel_print_rc6_info(dev, rc6_mask);
4767 if (IS_BROADWELL(dev))
4768 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4769 GEN7_RC_CTL_TO_MODE |
4770 rc6_mask);
4771 else
4772 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4773 GEN6_RC_CTL_EI_MODE(1) |
4774 rc6_mask);
4775
4776 /* 4 Program defaults and thresholds for RPS*/
4777 I915_WRITE(GEN6_RPNSWREQ,
4778 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4779 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4780 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4781 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
4782 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
4783
4784 /* Docs recommend 900MHz, and 300 MHz respectively */
4785 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
4786 dev_priv->rps.max_freq_softlimit << 24 |
4787 dev_priv->rps.min_freq_softlimit << 16);
4788
4789 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
4790 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
4791 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
4792 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
4793
4794 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4795
4796 /* 5: Enable RPS */
4797 I915_WRITE(GEN6_RP_CONTROL,
4798 GEN6_RP_MEDIA_TURBO |
4799 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4800 GEN6_RP_MEDIA_IS_GFX |
4801 GEN6_RP_ENABLE |
4802 GEN6_RP_UP_BUSY_AVG |
4803 GEN6_RP_DOWN_IDLE_AVG);
4804
4805 /* 6: Ring frequency + overclocking (our driver does this later */
4806
4807 dev_priv->rps.power = HIGH_POWER; /* force a reset */
4808 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
4809
4810 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4811 }
4812
4813 static void gen6_enable_rps(struct drm_device *dev)
4814 {
4815 struct drm_i915_private *dev_priv = dev->dev_private;
4816 struct intel_engine_cs *ring;
4817 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
4818 u32 gtfifodbg;
4819 int rc6_mode;
4820 int i, ret;
4821
4822 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4823
4824 /* Here begins a magic sequence of register writes to enable
4825 * auto-downclocking.
4826 *
4827 * Perhaps there might be some value in exposing these to
4828 * userspace...
4829 */
4830 I915_WRITE(GEN6_RC_STATE, 0);
4831
4832 /* Clear the DBG now so we don't confuse earlier errors */
4833 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
4834 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
4835 I915_WRITE(GTFIFODBG, gtfifodbg);
4836 }
4837
4838 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4839
4840 /* Initialize rps frequencies */
4841 gen6_init_rps_frequencies(dev);
4842
4843 /* disable the counters and set deterministic thresholds */
4844 I915_WRITE(GEN6_RC_CONTROL, 0);
4845
4846 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
4847 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
4848 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
4849 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4850 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4851
4852 for_each_ring(ring, dev_priv, i)
4853 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4854
4855 I915_WRITE(GEN6_RC_SLEEP, 0);
4856 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
4857 if (IS_IVYBRIDGE(dev))
4858 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
4859 else
4860 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
4861 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
4862 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
4863
4864 /* Check if we are enabling RC6 */
4865 rc6_mode = intel_enable_rc6(dev_priv->dev);
4866 if (rc6_mode & INTEL_RC6_ENABLE)
4867 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
4868
4869 /* We don't use those on Haswell */
4870 if (!IS_HASWELL(dev)) {
4871 if (rc6_mode & INTEL_RC6p_ENABLE)
4872 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
4873
4874 if (rc6_mode & INTEL_RC6pp_ENABLE)
4875 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
4876 }
4877
4878 intel_print_rc6_info(dev, rc6_mask);
4879
4880 I915_WRITE(GEN6_RC_CONTROL,
4881 rc6_mask |
4882 GEN6_RC_CTL_EI_MODE(1) |
4883 GEN6_RC_CTL_HW_ENABLE);
4884
4885 /* Power down if completely idle for over 50ms */
4886 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
4887 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4888
4889 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
4890 if (ret)
4891 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
4892
4893 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
4894 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
4895 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
4896 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
4897 (pcu_mbox & 0xff) * 50);
4898 dev_priv->rps.max_freq = pcu_mbox & 0xff;
4899 }
4900
4901 dev_priv->rps.power = HIGH_POWER; /* force a reset */
4902 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
4903
4904 rc6vids = 0;
4905 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
4906 if (IS_GEN6(dev) && ret) {
4907 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
4908 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
4909 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
4910 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
4911 rc6vids &= 0xffff00;
4912 rc6vids |= GEN6_ENCODE_RC6_VID(450);
4913 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
4914 if (ret)
4915 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
4916 }
4917
4918 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4919 }
4920
4921 static void __gen6_update_ring_freq(struct drm_device *dev)
4922 {
4923 struct drm_i915_private *dev_priv = dev->dev_private;
4924 int min_freq = 15;
4925 unsigned int gpu_freq;
4926 unsigned int max_ia_freq, min_ring_freq;
4927 unsigned int max_gpu_freq, min_gpu_freq;
4928 int scaling_factor = 180;
4929 struct cpufreq_policy *policy;
4930
4931 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4932
4933 policy = cpufreq_cpu_get(0);
4934 if (policy) {
4935 max_ia_freq = policy->cpuinfo.max_freq;
4936 cpufreq_cpu_put(policy);
4937 } else {
4938 /*
4939 * Default to measured freq if none found, PCU will ensure we
4940 * don't go over
4941 */
4942 max_ia_freq = tsc_khz;
4943 }
4944
4945 /* Convert from kHz to MHz */
4946 max_ia_freq /= 1000;
4947
4948 min_ring_freq = I915_READ(DCLK) & 0xf;
4949 /* convert DDR frequency from units of 266.6MHz to bandwidth */
4950 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
4951
4952 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
4953 /* Convert GT frequency to 50 HZ units */
4954 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
4955 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
4956 } else {
4957 min_gpu_freq = dev_priv->rps.min_freq;
4958 max_gpu_freq = dev_priv->rps.max_freq;
4959 }
4960
4961 /*
4962 * For each potential GPU frequency, load a ring frequency we'd like
4963 * to use for memory access. We do this by specifying the IA frequency
4964 * the PCU should use as a reference to determine the ring frequency.
4965 */
4966 for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
4967 int diff = max_gpu_freq - gpu_freq;
4968 unsigned int ia_freq = 0, ring_freq = 0;
4969
4970 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
4971 /*
4972 * ring_freq = 2 * GT. ring_freq is in 100MHz units
4973 * No floor required for ring frequency on SKL.
4974 */
4975 ring_freq = gpu_freq;
4976 } else if (INTEL_INFO(dev)->gen >= 8) {
4977 /* max(2 * GT, DDR). NB: GT is 50MHz units */
4978 ring_freq = max(min_ring_freq, gpu_freq);
4979 } else if (IS_HASWELL(dev)) {
4980 ring_freq = mult_frac(gpu_freq, 5, 4);
4981 ring_freq = max(min_ring_freq, ring_freq);
4982 /* leave ia_freq as the default, chosen by cpufreq */
4983 } else {
4984 /* On older processors, there is no separate ring
4985 * clock domain, so in order to boost the bandwidth
4986 * of the ring, we need to upclock the CPU (ia_freq).
4987 *
4988 * For GPU frequencies less than 750MHz,
4989 * just use the lowest ring freq.
4990 */
4991 if (gpu_freq < min_freq)
4992 ia_freq = 800;
4993 else
4994 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
4995 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
4996 }
4997
4998 sandybridge_pcode_write(dev_priv,
4999 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
5000 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5001 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5002 gpu_freq);
5003 }
5004 }
5005
5006 void gen6_update_ring_freq(struct drm_device *dev)
5007 {
5008 struct drm_i915_private *dev_priv = dev->dev_private;
5009
5010 if (!HAS_CORE_RING_FREQ(dev))
5011 return;
5012
5013 mutex_lock(&dev_priv->rps.hw_lock);
5014 __gen6_update_ring_freq(dev);
5015 mutex_unlock(&dev_priv->rps.hw_lock);
5016 }
5017
5018 static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
5019 {
5020 struct drm_device *dev = dev_priv->dev;
5021 u32 val, rp0;
5022
5023 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5024
5025 switch (INTEL_INFO(dev)->eu_total) {
5026 case 8:
5027 /* (2 * 4) config */
5028 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5029 break;
5030 case 12:
5031 /* (2 * 6) config */
5032 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5033 break;
5034 case 16:
5035 /* (2 * 8) config */
5036 default:
5037 /* Setting (2 * 8) Min RP0 for any other combination */
5038 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5039 break;
5040 }
5041
5042 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5043
5044 return rp0;
5045 }
5046
5047 static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5048 {
5049 u32 val, rpe;
5050
5051 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5052 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5053
5054 return rpe;
5055 }
5056
5057 static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5058 {
5059 u32 val, rp1;
5060
5061 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5062 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5063
5064 return rp1;
5065 }
5066
5067 static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5068 {
5069 u32 val, rp1;
5070
5071 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5072
5073 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5074
5075 return rp1;
5076 }
5077
5078 static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
5079 {
5080 u32 val, rp0;
5081
5082 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5083
5084 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5085 /* Clamp to max */
5086 rp0 = min_t(u32, rp0, 0xea);
5087
5088 return rp0;
5089 }
5090
5091 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5092 {
5093 u32 val, rpe;
5094
5095 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
5096 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
5097 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
5098 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5099
5100 return rpe;
5101 }
5102
5103 static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
5104 {
5105 u32 val;
5106
5107 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5108 /*
5109 * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
5110 * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
5111 * a BYT-M B0 the above register contains 0xbf. Moreover when setting
5112 * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
5113 * to make sure it matches what Punit accepts.
5114 */
5115 return max_t(u32, val, 0xc0);
5116 }
5117
5118 /* Check that the pctx buffer wasn't move under us. */
5119 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5120 {
5121 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5122
5123 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5124 dev_priv->vlv_pctx->stolen->start);
5125 }
5126
5127
5128 /* Check that the pcbr address is not empty. */
5129 static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5130 {
5131 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5132
5133 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5134 }
5135
5136 static void cherryview_setup_pctx(struct drm_device *dev)
5137 {
5138 struct drm_i915_private *dev_priv = dev->dev_private;
5139 unsigned long pctx_paddr, paddr;
5140 struct i915_gtt *gtt = &dev_priv->gtt;
5141 u32 pcbr;
5142 int pctx_size = 32*1024;
5143
5144 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
5145
5146 pcbr = I915_READ(VLV_PCBR);
5147 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
5148 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5149 paddr = (dev_priv->mm.stolen_base +
5150 (gtt->stolen_size - pctx_size));
5151
5152 pctx_paddr = (paddr & (~4095));
5153 I915_WRITE(VLV_PCBR, pctx_paddr);
5154 }
5155
5156 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5157 }
5158
5159 static void valleyview_setup_pctx(struct drm_device *dev)
5160 {
5161 struct drm_i915_private *dev_priv = dev->dev_private;
5162 struct drm_i915_gem_object *pctx;
5163 unsigned long pctx_paddr;
5164 u32 pcbr;
5165 int pctx_size = 24*1024;
5166
5167 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
5168
5169 pcbr = I915_READ(VLV_PCBR);
5170 if (pcbr) {
5171 /* BIOS set it up already, grab the pre-alloc'd space */
5172 int pcbr_offset;
5173
5174 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
5175 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
5176 pcbr_offset,
5177 I915_GTT_OFFSET_NONE,
5178 pctx_size);
5179 goto out;
5180 }
5181
5182 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5183
5184 /*
5185 * From the Gunit register HAS:
5186 * The Gfx driver is expected to program this register and ensure
5187 * proper allocation within Gfx stolen memory. For example, this
5188 * register should be programmed such than the PCBR range does not
5189 * overlap with other ranges, such as the frame buffer, protected
5190 * memory, or any other relevant ranges.
5191 */
5192 pctx = i915_gem_object_create_stolen(dev, pctx_size);
5193 if (!pctx) {
5194 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
5195 return;
5196 }
5197
5198 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5199 I915_WRITE(VLV_PCBR, pctx_paddr);
5200
5201 out:
5202 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5203 dev_priv->vlv_pctx = pctx;
5204 }
5205
5206 static void valleyview_cleanup_pctx(struct drm_device *dev)
5207 {
5208 struct drm_i915_private *dev_priv = dev->dev_private;
5209
5210 if (WARN_ON(!dev_priv->vlv_pctx))
5211 return;
5212
5213 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
5214 dev_priv->vlv_pctx = NULL;
5215 }
5216
5217 static void valleyview_init_gt_powersave(struct drm_device *dev)
5218 {
5219 struct drm_i915_private *dev_priv = dev->dev_private;
5220 u32 val;
5221
5222 valleyview_setup_pctx(dev);
5223
5224 mutex_lock(&dev_priv->rps.hw_lock);
5225
5226 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5227 switch ((val >> 6) & 3) {
5228 case 0:
5229 case 1:
5230 dev_priv->mem_freq = 800;
5231 break;
5232 case 2:
5233 dev_priv->mem_freq = 1066;
5234 break;
5235 case 3:
5236 dev_priv->mem_freq = 1333;
5237 break;
5238 }
5239 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5240
5241 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5242 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5243 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5244 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5245 dev_priv->rps.max_freq);
5246
5247 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5248 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5249 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5250 dev_priv->rps.efficient_freq);
5251
5252 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5253 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
5254 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5255 dev_priv->rps.rp1_freq);
5256
5257 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5258 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5259 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5260 dev_priv->rps.min_freq);
5261
5262 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5263
5264 /* Preserve min/max settings in case of re-init */
5265 if (dev_priv->rps.max_freq_softlimit == 0)
5266 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5267
5268 if (dev_priv->rps.min_freq_softlimit == 0)
5269 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5270
5271 mutex_unlock(&dev_priv->rps.hw_lock);
5272 }
5273
5274 static void cherryview_init_gt_powersave(struct drm_device *dev)
5275 {
5276 struct drm_i915_private *dev_priv = dev->dev_private;
5277 u32 val;
5278
5279 cherryview_setup_pctx(dev);
5280
5281 mutex_lock(&dev_priv->rps.hw_lock);
5282
5283 mutex_lock(&dev_priv->sb_lock);
5284 val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
5285 mutex_unlock(&dev_priv->sb_lock);
5286
5287 switch ((val >> 2) & 0x7) {
5288 case 3:
5289 dev_priv->mem_freq = 2000;
5290 break;
5291 default:
5292 dev_priv->mem_freq = 1600;
5293 break;
5294 }
5295 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5296
5297 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5298 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5299 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5300 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5301 dev_priv->rps.max_freq);
5302
5303 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5304 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5305 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5306 dev_priv->rps.efficient_freq);
5307
5308 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5309 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
5310 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5311 dev_priv->rps.rp1_freq);
5312
5313 /* PUnit validated range is only [RPe, RP0] */
5314 dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
5315 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5316 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5317 dev_priv->rps.min_freq);
5318
5319 WARN_ONCE((dev_priv->rps.max_freq |
5320 dev_priv->rps.efficient_freq |
5321 dev_priv->rps.rp1_freq |
5322 dev_priv->rps.min_freq) & 1,
5323 "Odd GPU freq values\n");
5324
5325 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5326
5327 /* Preserve min/max settings in case of re-init */
5328 if (dev_priv->rps.max_freq_softlimit == 0)
5329 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5330
5331 if (dev_priv->rps.min_freq_softlimit == 0)
5332 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5333
5334 mutex_unlock(&dev_priv->rps.hw_lock);
5335 }
5336
5337 static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
5338 {
5339 valleyview_cleanup_pctx(dev);
5340 }
5341
5342 static void cherryview_enable_rps(struct drm_device *dev)
5343 {
5344 struct drm_i915_private *dev_priv = dev->dev_private;
5345 struct intel_engine_cs *ring;
5346 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
5347 int i;
5348
5349 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5350
5351 gtfifodbg = I915_READ(GTFIFODBG);
5352 if (gtfifodbg) {
5353 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5354 gtfifodbg);
5355 I915_WRITE(GTFIFODBG, gtfifodbg);
5356 }
5357
5358 cherryview_check_pctx(dev_priv);
5359
5360 /* 1a & 1b: Get forcewake during program sequence. Although the driver
5361 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5362 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5363
5364 /* Disable RC states. */
5365 I915_WRITE(GEN6_RC_CONTROL, 0);
5366
5367 /* 2a: Program RC6 thresholds.*/
5368 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5369 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5370 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5371
5372 for_each_ring(ring, dev_priv, i)
5373 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5374 I915_WRITE(GEN6_RC_SLEEP, 0);
5375
5376 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
5377 I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
5378
5379 /* allows RC6 residency counter to work */
5380 I915_WRITE(VLV_COUNTER_CONTROL,
5381 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
5382 VLV_MEDIA_RC6_COUNT_EN |
5383 VLV_RENDER_RC6_COUNT_EN));
5384
5385 /* For now we assume BIOS is allocating and populating the PCBR */
5386 pcbr = I915_READ(VLV_PCBR);
5387
5388 /* 3: Enable RC6 */
5389 if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
5390 (pcbr >> VLV_PCBR_ADDR_SHIFT))
5391 rc6_mode = GEN7_RC_CTL_TO_MODE;
5392
5393 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5394
5395 /* 4 Program defaults and thresholds for RPS*/
5396 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
5397 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5398 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5399 I915_WRITE(GEN6_RP_UP_EI, 66000);
5400 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5401
5402 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5403
5404 /* 5: Enable RPS */
5405 I915_WRITE(GEN6_RP_CONTROL,
5406 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5407 GEN6_RP_MEDIA_IS_GFX |
5408 GEN6_RP_ENABLE |
5409 GEN6_RP_UP_BUSY_AVG |
5410 GEN6_RP_DOWN_IDLE_AVG);
5411
5412 /* Setting Fixed Bias */
5413 val = VLV_OVERRIDE_EN |
5414 VLV_SOC_TDP_EN |
5415 CHV_BIAS_CPU_50_SOC_50;
5416 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5417
5418 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5419
5420 /* RPS code assumes GPLL is used */
5421 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5422
5423 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
5424 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5425
5426 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5427 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5428 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
5429 dev_priv->rps.cur_freq);
5430
5431 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5432 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5433 dev_priv->rps.efficient_freq);
5434
5435 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5436
5437 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5438 }
5439
5440 static void valleyview_enable_rps(struct drm_device *dev)
5441 {
5442 struct drm_i915_private *dev_priv = dev->dev_private;
5443 struct intel_engine_cs *ring;
5444 u32 gtfifodbg, val, rc6_mode = 0;
5445 int i;
5446
5447 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5448
5449 valleyview_check_pctx(dev_priv);
5450
5451 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
5452 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5453 gtfifodbg);
5454 I915_WRITE(GTFIFODBG, gtfifodbg);
5455 }
5456
5457 /* If VLV, Forcewake all wells, else re-direct to regular path */
5458 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5459
5460 /* Disable RC states. */
5461 I915_WRITE(GEN6_RC_CONTROL, 0);
5462
5463 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
5464 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5465 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5466 I915_WRITE(GEN6_RP_UP_EI, 66000);
5467 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5468
5469 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5470
5471 I915_WRITE(GEN6_RP_CONTROL,
5472 GEN6_RP_MEDIA_TURBO |
5473 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5474 GEN6_RP_MEDIA_IS_GFX |
5475 GEN6_RP_ENABLE |
5476 GEN6_RP_UP_BUSY_AVG |
5477 GEN6_RP_DOWN_IDLE_CONT);
5478
5479 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
5480 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5481 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5482
5483 for_each_ring(ring, dev_priv, i)
5484 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5485
5486 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
5487
5488 /* allows RC6 residency counter to work */
5489 I915_WRITE(VLV_COUNTER_CONTROL,
5490 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
5491 VLV_RENDER_RC0_COUNT_EN |
5492 VLV_MEDIA_RC6_COUNT_EN |
5493 VLV_RENDER_RC6_COUNT_EN));
5494
5495 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
5496 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
5497
5498 intel_print_rc6_info(dev, rc6_mode);
5499
5500 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5501
5502 /* Setting Fixed Bias */
5503 val = VLV_OVERRIDE_EN |
5504 VLV_SOC_TDP_EN |
5505 VLV_BIAS_CPU_125_SOC_875;
5506 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5507
5508 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5509
5510 /* RPS code assumes GPLL is used */
5511 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5512
5513 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
5514 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5515
5516 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5517 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5518 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
5519 dev_priv->rps.cur_freq);
5520
5521 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5522 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5523 dev_priv->rps.efficient_freq);
5524
5525 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5526
5527 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5528 }
5529
5530 static unsigned long intel_pxfreq(u32 vidfreq)
5531 {
5532 unsigned long freq;
5533 int div = (vidfreq & 0x3f0000) >> 16;
5534 int post = (vidfreq & 0x3000) >> 12;
5535 int pre = (vidfreq & 0x7);
5536
5537 if (!pre)
5538 return 0;
5539
5540 freq = ((div * 133333) / ((1<<post) * pre));
5541
5542 return freq;
5543 }
5544
5545 static const struct cparams {
5546 u16 i;
5547 u16 t;
5548 u16 m;
5549 u16 c;
5550 } cparams[] = {
5551 { 1, 1333, 301, 28664 },
5552 { 1, 1066, 294, 24460 },
5553 { 1, 800, 294, 25192 },
5554 { 0, 1333, 276, 27605 },
5555 { 0, 1066, 276, 27605 },
5556 { 0, 800, 231, 23784 },
5557 };
5558
5559 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
5560 {
5561 u64 total_count, diff, ret;
5562 u32 count1, count2, count3, m = 0, c = 0;
5563 unsigned long now = jiffies_to_msecs(jiffies), diff1;
5564 int i;
5565
5566 assert_spin_locked(&mchdev_lock);
5567
5568 diff1 = now - dev_priv->ips.last_time1;
5569
5570 /* Prevent division-by-zero if we are asking too fast.
5571 * Also, we don't get interesting results if we are polling
5572 * faster than once in 10ms, so just return the saved value
5573 * in such cases.
5574 */
5575 if (diff1 <= 10)
5576 return dev_priv->ips.chipset_power;
5577
5578 count1 = I915_READ(DMIEC);
5579 count2 = I915_READ(DDREC);
5580 count3 = I915_READ(CSIEC);
5581
5582 total_count = count1 + count2 + count3;
5583
5584 /* FIXME: handle per-counter overflow */
5585 if (total_count < dev_priv->ips.last_count1) {
5586 diff = ~0UL - dev_priv->ips.last_count1;
5587 diff += total_count;
5588 } else {
5589 diff = total_count - dev_priv->ips.last_count1;
5590 }
5591
5592 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
5593 if (cparams[i].i == dev_priv->ips.c_m &&
5594 cparams[i].t == dev_priv->ips.r_t) {
5595 m = cparams[i].m;
5596 c = cparams[i].c;
5597 break;
5598 }
5599 }
5600
5601 diff = div_u64(diff, diff1);
5602 ret = ((m * diff) + c);
5603 ret = div_u64(ret, 10);
5604
5605 dev_priv->ips.last_count1 = total_count;
5606 dev_priv->ips.last_time1 = now;
5607
5608 dev_priv->ips.chipset_power = ret;
5609
5610 return ret;
5611 }
5612
5613 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
5614 {
5615 struct drm_device *dev = dev_priv->dev;
5616 unsigned long val;
5617
5618 if (INTEL_INFO(dev)->gen != 5)
5619 return 0;
5620
5621 spin_lock_irq(&mchdev_lock);
5622
5623 val = __i915_chipset_val(dev_priv);
5624
5625 spin_unlock_irq(&mchdev_lock);
5626
5627 return val;
5628 }
5629
5630 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
5631 {
5632 unsigned long m, x, b;
5633 u32 tsfs;
5634
5635 tsfs = I915_READ(TSFS);
5636
5637 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
5638 x = I915_READ8(TR1);
5639
5640 b = tsfs & TSFS_INTR_MASK;
5641
5642 return ((m * x) / 127) - b;
5643 }
5644
5645 static int _pxvid_to_vd(u8 pxvid)
5646 {
5647 if (pxvid == 0)
5648 return 0;
5649
5650 if (pxvid >= 8 && pxvid < 31)
5651 pxvid = 31;
5652
5653 return (pxvid + 2) * 125;
5654 }
5655
5656 static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
5657 {
5658 struct drm_device *dev = dev_priv->dev;
5659 const int vd = _pxvid_to_vd(pxvid);
5660 const int vm = vd - 1125;
5661
5662 if (INTEL_INFO(dev)->is_mobile)
5663 return vm > 0 ? vm : 0;
5664
5665 return vd;
5666 }
5667
5668 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
5669 {
5670 u64 now, diff, diffms;
5671 u32 count;
5672
5673 assert_spin_locked(&mchdev_lock);
5674
5675 now = ktime_get_raw_ns();
5676 diffms = now - dev_priv->ips.last_time2;
5677 do_div(diffms, NSEC_PER_MSEC);
5678
5679 /* Don't divide by 0 */
5680 if (!diffms)
5681 return;
5682
5683 count = I915_READ(GFXEC);
5684
5685 if (count < dev_priv->ips.last_count2) {
5686 diff = ~0UL - dev_priv->ips.last_count2;
5687 diff += count;
5688 } else {
5689 diff = count - dev_priv->ips.last_count2;
5690 }
5691
5692 dev_priv->ips.last_count2 = count;
5693 dev_priv->ips.last_time2 = now;
5694
5695 /* More magic constants... */
5696 diff = diff * 1181;
5697 diff = div_u64(diff, diffms * 10);
5698 dev_priv->ips.gfx_power = diff;
5699 }
5700
5701 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
5702 {
5703 struct drm_device *dev = dev_priv->dev;
5704
5705 if (INTEL_INFO(dev)->gen != 5)
5706 return;
5707
5708 spin_lock_irq(&mchdev_lock);
5709
5710 __i915_update_gfx_val(dev_priv);
5711
5712 spin_unlock_irq(&mchdev_lock);
5713 }
5714
5715 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
5716 {
5717 unsigned long t, corr, state1, corr2, state2;
5718 u32 pxvid, ext_v;
5719
5720 assert_spin_locked(&mchdev_lock);
5721
5722 pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
5723 pxvid = (pxvid >> 24) & 0x7f;
5724 ext_v = pvid_to_extvid(dev_priv, pxvid);
5725
5726 state1 = ext_v;
5727
5728 t = i915_mch_val(dev_priv);
5729
5730 /* Revel in the empirically derived constants */
5731
5732 /* Correction factor in 1/100000 units */
5733 if (t > 80)
5734 corr = ((t * 2349) + 135940);
5735 else if (t >= 50)
5736 corr = ((t * 964) + 29317);
5737 else /* < 50 */
5738 corr = ((t * 301) + 1004);
5739
5740 corr = corr * ((150142 * state1) / 10000 - 78642);
5741 corr /= 100000;
5742 corr2 = (corr * dev_priv->ips.corr);
5743
5744 state2 = (corr2 * state1) / 10000;
5745 state2 /= 100; /* convert to mW */
5746
5747 __i915_update_gfx_val(dev_priv);
5748
5749 return dev_priv->ips.gfx_power + state2;
5750 }
5751
5752 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
5753 {
5754 struct drm_device *dev = dev_priv->dev;
5755 unsigned long val;
5756
5757 if (INTEL_INFO(dev)->gen != 5)
5758 return 0;
5759
5760 spin_lock_irq(&mchdev_lock);
5761
5762 val = __i915_gfx_val(dev_priv);
5763
5764 spin_unlock_irq(&mchdev_lock);
5765
5766 return val;
5767 }
5768
5769 /**
5770 * i915_read_mch_val - return value for IPS use
5771 *
5772 * Calculate and return a value for the IPS driver to use when deciding whether
5773 * we have thermal and power headroom to increase CPU or GPU power budget.
5774 */
5775 unsigned long i915_read_mch_val(void)
5776 {
5777 struct drm_i915_private *dev_priv;
5778 unsigned long chipset_val, graphics_val, ret = 0;
5779
5780 spin_lock_irq(&mchdev_lock);
5781 if (!i915_mch_dev)
5782 goto out_unlock;
5783 dev_priv = i915_mch_dev;
5784
5785 chipset_val = __i915_chipset_val(dev_priv);
5786 graphics_val = __i915_gfx_val(dev_priv);
5787
5788 ret = chipset_val + graphics_val;
5789
5790 out_unlock:
5791 spin_unlock_irq(&mchdev_lock);
5792
5793 return ret;
5794 }
5795 EXPORT_SYMBOL_GPL(i915_read_mch_val);
5796
5797 /**
5798 * i915_gpu_raise - raise GPU frequency limit
5799 *
5800 * Raise the limit; IPS indicates we have thermal headroom.
5801 */
5802 bool i915_gpu_raise(void)
5803 {
5804 struct drm_i915_private *dev_priv;
5805 bool ret = true;
5806
5807 spin_lock_irq(&mchdev_lock);
5808 if (!i915_mch_dev) {
5809 ret = false;
5810 goto out_unlock;
5811 }
5812 dev_priv = i915_mch_dev;
5813
5814 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
5815 dev_priv->ips.max_delay--;
5816
5817 out_unlock:
5818 spin_unlock_irq(&mchdev_lock);
5819
5820 return ret;
5821 }
5822 EXPORT_SYMBOL_GPL(i915_gpu_raise);
5823
5824 /**
5825 * i915_gpu_lower - lower GPU frequency limit
5826 *
5827 * IPS indicates we're close to a thermal limit, so throttle back the GPU
5828 * frequency maximum.
5829 */
5830 bool i915_gpu_lower(void)
5831 {
5832 struct drm_i915_private *dev_priv;
5833 bool ret = true;
5834
5835 spin_lock_irq(&mchdev_lock);
5836 if (!i915_mch_dev) {
5837 ret = false;
5838 goto out_unlock;
5839 }
5840 dev_priv = i915_mch_dev;
5841
5842 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
5843 dev_priv->ips.max_delay++;
5844
5845 out_unlock:
5846 spin_unlock_irq(&mchdev_lock);
5847
5848 return ret;
5849 }
5850 EXPORT_SYMBOL_GPL(i915_gpu_lower);
5851
5852 /**
5853 * i915_gpu_busy - indicate GPU business to IPS
5854 *
5855 * Tell the IPS driver whether or not the GPU is busy.
5856 */
5857 bool i915_gpu_busy(void)
5858 {
5859 struct drm_i915_private *dev_priv;
5860 struct intel_engine_cs *ring;
5861 bool ret = false;
5862 int i;
5863
5864 spin_lock_irq(&mchdev_lock);
5865 if (!i915_mch_dev)
5866 goto out_unlock;
5867 dev_priv = i915_mch_dev;
5868
5869 for_each_ring(ring, dev_priv, i)
5870 ret |= !list_empty(&ring->request_list);
5871
5872 out_unlock:
5873 spin_unlock_irq(&mchdev_lock);
5874
5875 return ret;
5876 }
5877 EXPORT_SYMBOL_GPL(i915_gpu_busy);
5878
5879 /**
5880 * i915_gpu_turbo_disable - disable graphics turbo
5881 *
5882 * Disable graphics turbo by resetting the max frequency and setting the
5883 * current frequency to the default.
5884 */
5885 bool i915_gpu_turbo_disable(void)
5886 {
5887 struct drm_i915_private *dev_priv;
5888 bool ret = true;
5889
5890 spin_lock_irq(&mchdev_lock);
5891 if (!i915_mch_dev) {
5892 ret = false;
5893 goto out_unlock;
5894 }
5895 dev_priv = i915_mch_dev;
5896
5897 dev_priv->ips.max_delay = dev_priv->ips.fstart;
5898
5899 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
5900 ret = false;
5901
5902 out_unlock:
5903 spin_unlock_irq(&mchdev_lock);
5904
5905 return ret;
5906 }
5907 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
5908
5909 /**
5910 * Tells the intel_ips driver that the i915 driver is now loaded, if
5911 * IPS got loaded first.
5912 *
5913 * This awkward dance is so that neither module has to depend on the
5914 * other in order for IPS to do the appropriate communication of
5915 * GPU turbo limits to i915.
5916 */
5917 static void
5918 ips_ping_for_i915_load(void)
5919 {
5920 void (*link)(void);
5921
5922 link = symbol_get(ips_link_to_i915_driver);
5923 if (link) {
5924 link();
5925 symbol_put(ips_link_to_i915_driver);
5926 }
5927 }
5928
5929 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
5930 {
5931 /* We only register the i915 ips part with intel-ips once everything is
5932 * set up, to avoid intel-ips sneaking in and reading bogus values. */
5933 spin_lock_irq(&mchdev_lock);
5934 i915_mch_dev = dev_priv;
5935 spin_unlock_irq(&mchdev_lock);
5936
5937 ips_ping_for_i915_load();
5938 }
5939
5940 void intel_gpu_ips_teardown(void)
5941 {
5942 spin_lock_irq(&mchdev_lock);
5943 i915_mch_dev = NULL;
5944 spin_unlock_irq(&mchdev_lock);
5945 }
5946
5947 static void intel_init_emon(struct drm_device *dev)
5948 {
5949 struct drm_i915_private *dev_priv = dev->dev_private;
5950 u32 lcfuse;
5951 u8 pxw[16];
5952 int i;
5953
5954 /* Disable to program */
5955 I915_WRITE(ECR, 0);
5956 POSTING_READ(ECR);
5957
5958 /* Program energy weights for various events */
5959 I915_WRITE(SDEW, 0x15040d00);
5960 I915_WRITE(CSIEW0, 0x007f0000);
5961 I915_WRITE(CSIEW1, 0x1e220004);
5962 I915_WRITE(CSIEW2, 0x04000004);
5963
5964 for (i = 0; i < 5; i++)
5965 I915_WRITE(PEW(i), 0);
5966 for (i = 0; i < 3; i++)
5967 I915_WRITE(DEW(i), 0);
5968
5969 /* Program P-state weights to account for frequency power adjustment */
5970 for (i = 0; i < 16; i++) {
5971 u32 pxvidfreq = I915_READ(PXVFREQ(i));
5972 unsigned long freq = intel_pxfreq(pxvidfreq);
5973 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5974 PXVFREQ_PX_SHIFT;
5975 unsigned long val;
5976
5977 val = vid * vid;
5978 val *= (freq / 1000);
5979 val *= 255;
5980 val /= (127*127*900);
5981 if (val > 0xff)
5982 DRM_ERROR("bad pxval: %ld\n", val);
5983 pxw[i] = val;
5984 }
5985 /* Render standby states get 0 weight */
5986 pxw[14] = 0;
5987 pxw[15] = 0;
5988
5989 for (i = 0; i < 4; i++) {
5990 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5991 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
5992 I915_WRITE(PXW(i), val);
5993 }
5994
5995 /* Adjust magic regs to magic values (more experimental results) */
5996 I915_WRITE(OGW0, 0);
5997 I915_WRITE(OGW1, 0);
5998 I915_WRITE(EG0, 0x00007f00);
5999 I915_WRITE(EG1, 0x0000000e);
6000 I915_WRITE(EG2, 0x000e0000);
6001 I915_WRITE(EG3, 0x68000300);
6002 I915_WRITE(EG4, 0x42000000);
6003 I915_WRITE(EG5, 0x00140031);
6004 I915_WRITE(EG6, 0);
6005 I915_WRITE(EG7, 0);
6006
6007 for (i = 0; i < 8; i++)
6008 I915_WRITE(PXWL(i), 0);
6009
6010 /* Enable PMON + select events */
6011 I915_WRITE(ECR, 0x80000019);
6012
6013 lcfuse = I915_READ(LCFUSE02);
6014
6015 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
6016 }
6017
6018 void intel_init_gt_powersave(struct drm_device *dev)
6019 {
6020 struct drm_i915_private *dev_priv = dev->dev_private;
6021
6022 i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
6023 /*
6024 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6025 * requirement.
6026 */
6027 if (!i915.enable_rc6) {
6028 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6029 intel_runtime_pm_get(dev_priv);
6030 }
6031
6032 if (IS_CHERRYVIEW(dev))
6033 cherryview_init_gt_powersave(dev);
6034 else if (IS_VALLEYVIEW(dev))
6035 valleyview_init_gt_powersave(dev);
6036 }
6037
6038 void intel_cleanup_gt_powersave(struct drm_device *dev)
6039 {
6040 struct drm_i915_private *dev_priv = dev->dev_private;
6041
6042 if (IS_CHERRYVIEW(dev))
6043 return;
6044 else if (IS_VALLEYVIEW(dev))
6045 valleyview_cleanup_gt_powersave(dev);
6046
6047 if (!i915.enable_rc6)
6048 intel_runtime_pm_put(dev_priv);
6049 }
6050
6051 static void gen6_suspend_rps(struct drm_device *dev)
6052 {
6053 struct drm_i915_private *dev_priv = dev->dev_private;
6054
6055 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
6056
6057 gen6_disable_rps_interrupts(dev);
6058 }
6059
6060 /**
6061 * intel_suspend_gt_powersave - suspend PM work and helper threads
6062 * @dev: drm device
6063 *
6064 * We don't want to disable RC6 or other features here, we just want
6065 * to make sure any work we've queued has finished and won't bother
6066 * us while we're suspended.
6067 */
6068 void intel_suspend_gt_powersave(struct drm_device *dev)
6069 {
6070 struct drm_i915_private *dev_priv = dev->dev_private;
6071
6072 if (INTEL_INFO(dev)->gen < 6)
6073 return;
6074
6075 gen6_suspend_rps(dev);
6076
6077 /* Force GPU to min freq during suspend */
6078 gen6_rps_idle(dev_priv);
6079 }
6080
6081 void intel_disable_gt_powersave(struct drm_device *dev)
6082 {
6083 struct drm_i915_private *dev_priv = dev->dev_private;
6084
6085 if (IS_IRONLAKE_M(dev)) {
6086 ironlake_disable_drps(dev);
6087 } else if (INTEL_INFO(dev)->gen >= 6) {
6088 intel_suspend_gt_powersave(dev);
6089
6090 mutex_lock(&dev_priv->rps.hw_lock);
6091 if (INTEL_INFO(dev)->gen >= 9)
6092 gen9_disable_rps(dev);
6093 else if (IS_CHERRYVIEW(dev))
6094 cherryview_disable_rps(dev);
6095 else if (IS_VALLEYVIEW(dev))
6096 valleyview_disable_rps(dev);
6097 else
6098 gen6_disable_rps(dev);
6099
6100 dev_priv->rps.enabled = false;
6101 mutex_unlock(&dev_priv->rps.hw_lock);
6102 }
6103 }
6104
6105 static void intel_gen6_powersave_work(struct work_struct *work)
6106 {
6107 struct drm_i915_private *dev_priv =
6108 container_of(work, struct drm_i915_private,
6109 rps.delayed_resume_work.work);
6110 struct drm_device *dev = dev_priv->dev;
6111
6112 mutex_lock(&dev_priv->rps.hw_lock);
6113
6114 gen6_reset_rps_interrupts(dev);
6115
6116 if (IS_CHERRYVIEW(dev)) {
6117 cherryview_enable_rps(dev);
6118 } else if (IS_VALLEYVIEW(dev)) {
6119 valleyview_enable_rps(dev);
6120 } else if (INTEL_INFO(dev)->gen >= 9) {
6121 gen9_enable_rc6(dev);
6122 gen9_enable_rps(dev);
6123 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
6124 __gen6_update_ring_freq(dev);
6125 } else if (IS_BROADWELL(dev)) {
6126 gen8_enable_rps(dev);
6127 __gen6_update_ring_freq(dev);
6128 } else {
6129 gen6_enable_rps(dev);
6130 __gen6_update_ring_freq(dev);
6131 }
6132
6133 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6134 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6135
6136 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6137 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6138
6139 dev_priv->rps.enabled = true;
6140
6141 gen6_enable_rps_interrupts(dev);
6142
6143 mutex_unlock(&dev_priv->rps.hw_lock);
6144
6145 intel_runtime_pm_put(dev_priv);
6146 }
6147
6148 void intel_enable_gt_powersave(struct drm_device *dev)
6149 {
6150 struct drm_i915_private *dev_priv = dev->dev_private;
6151
6152 /* Powersaving is controlled by the host when inside a VM */
6153 if (intel_vgpu_active(dev))
6154 return;
6155
6156 if (IS_IRONLAKE_M(dev)) {
6157 mutex_lock(&dev->struct_mutex);
6158 ironlake_enable_drps(dev);
6159 intel_init_emon(dev);
6160 mutex_unlock(&dev->struct_mutex);
6161 } else if (INTEL_INFO(dev)->gen >= 6) {
6162 /*
6163 * PCU communication is slow and this doesn't need to be
6164 * done at any specific time, so do this out of our fast path
6165 * to make resume and init faster.
6166 *
6167 * We depend on the HW RC6 power context save/restore
6168 * mechanism when entering D3 through runtime PM suspend. So
6169 * disable RPM until RPS/RC6 is properly setup. We can only
6170 * get here via the driver load/system resume/runtime resume
6171 * paths, so the _noresume version is enough (and in case of
6172 * runtime resume it's necessary).
6173 */
6174 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
6175 round_jiffies_up_relative(HZ)))
6176 intel_runtime_pm_get_noresume(dev_priv);
6177 }
6178 }
6179
6180 void intel_reset_gt_powersave(struct drm_device *dev)
6181 {
6182 struct drm_i915_private *dev_priv = dev->dev_private;
6183
6184 if (INTEL_INFO(dev)->gen < 6)
6185 return;
6186
6187 gen6_suspend_rps(dev);
6188 dev_priv->rps.enabled = false;
6189 }
6190
6191 static void ibx_init_clock_gating(struct drm_device *dev)
6192 {
6193 struct drm_i915_private *dev_priv = dev->dev_private;
6194
6195 /*
6196 * On Ibex Peak and Cougar Point, we need to disable clock
6197 * gating for the panel power sequencer or it will fail to
6198 * start up when no ports are active.
6199 */
6200 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6201 }
6202
6203 static void g4x_disable_trickle_feed(struct drm_device *dev)
6204 {
6205 struct drm_i915_private *dev_priv = dev->dev_private;
6206 enum pipe pipe;
6207
6208 for_each_pipe(dev_priv, pipe) {
6209 I915_WRITE(DSPCNTR(pipe),
6210 I915_READ(DSPCNTR(pipe)) |
6211 DISPPLANE_TRICKLE_FEED_DISABLE);
6212
6213 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6214 POSTING_READ(DSPSURF(pipe));
6215 }
6216 }
6217
6218 static void ilk_init_lp_watermarks(struct drm_device *dev)
6219 {
6220 struct drm_i915_private *dev_priv = dev->dev_private;
6221
6222 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6223 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6224 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6225
6226 /*
6227 * Don't touch WM1S_LP_EN here.
6228 * Doing so could cause underruns.
6229 */
6230 }
6231
6232 static void ironlake_init_clock_gating(struct drm_device *dev)
6233 {
6234 struct drm_i915_private *dev_priv = dev->dev_private;
6235 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6236
6237 /*
6238 * Required for FBC
6239 * WaFbcDisableDpfcClockGating:ilk
6240 */
6241 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6242 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6243 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6244
6245 I915_WRITE(PCH_3DCGDIS0,
6246 MARIUNIT_CLOCK_GATE_DISABLE |
6247 SVSMUNIT_CLOCK_GATE_DISABLE);
6248 I915_WRITE(PCH_3DCGDIS1,
6249 VFMUNIT_CLOCK_GATE_DISABLE);
6250
6251 /*
6252 * According to the spec the following bits should be set in
6253 * order to enable memory self-refresh
6254 * The bit 22/21 of 0x42004
6255 * The bit 5 of 0x42020
6256 * The bit 15 of 0x45000
6257 */
6258 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6259 (I915_READ(ILK_DISPLAY_CHICKEN2) |
6260 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
6261 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6262 I915_WRITE(DISP_ARB_CTL,
6263 (I915_READ(DISP_ARB_CTL) |
6264 DISP_FBC_WM_DIS));
6265
6266 ilk_init_lp_watermarks(dev);
6267
6268 /*
6269 * Based on the document from hardware guys the following bits
6270 * should be set unconditionally in order to enable FBC.
6271 * The bit 22 of 0x42000
6272 * The bit 22 of 0x42004
6273 * The bit 7,8,9 of 0x42020.
6274 */
6275 if (IS_IRONLAKE_M(dev)) {
6276 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6277 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6278 I915_READ(ILK_DISPLAY_CHICKEN1) |
6279 ILK_FBCQ_DIS);
6280 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6281 I915_READ(ILK_DISPLAY_CHICKEN2) |
6282 ILK_DPARB_GATE);
6283 }
6284
6285 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6286
6287 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6288 I915_READ(ILK_DISPLAY_CHICKEN2) |
6289 ILK_ELPIN_409_SELECT);
6290 I915_WRITE(_3D_CHICKEN2,
6291 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6292 _3D_CHICKEN2_WM_READ_PIPELINED);
6293
6294 /* WaDisableRenderCachePipelinedFlush:ilk */
6295 I915_WRITE(CACHE_MODE_0,
6296 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6297
6298 /* WaDisable_RenderCache_OperationalFlush:ilk */
6299 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6300
6301 g4x_disable_trickle_feed(dev);
6302
6303 ibx_init_clock_gating(dev);
6304 }
6305
6306 static void cpt_init_clock_gating(struct drm_device *dev)
6307 {
6308 struct drm_i915_private *dev_priv = dev->dev_private;
6309 int pipe;
6310 uint32_t val;
6311
6312 /*
6313 * On Ibex Peak and Cougar Point, we need to disable clock
6314 * gating for the panel power sequencer or it will fail to
6315 * start up when no ports are active.
6316 */
6317 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6318 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6319 PCH_CPUNIT_CLOCK_GATE_DISABLE);
6320 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6321 DPLS_EDP_PPS_FIX_DIS);
6322 /* The below fixes the weird display corruption, a few pixels shifted
6323 * downward, on (only) LVDS of some HP laptops with IVY.
6324 */
6325 for_each_pipe(dev_priv, pipe) {
6326 val = I915_READ(TRANS_CHICKEN2(pipe));
6327 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6328 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6329 if (dev_priv->vbt.fdi_rx_polarity_inverted)
6330 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6331 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6332 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6333 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
6334 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6335 }
6336 /* WADP0ClockGatingDisable */
6337 for_each_pipe(dev_priv, pipe) {
6338 I915_WRITE(TRANS_CHICKEN1(pipe),
6339 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6340 }
6341 }
6342
6343 static void gen6_check_mch_setup(struct drm_device *dev)
6344 {
6345 struct drm_i915_private *dev_priv = dev->dev_private;
6346 uint32_t tmp;
6347
6348 tmp = I915_READ(MCH_SSKPD);
6349 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6350 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6351 tmp);
6352 }
6353
6354 static void gen6_init_clock_gating(struct drm_device *dev)
6355 {
6356 struct drm_i915_private *dev_priv = dev->dev_private;
6357 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6358
6359 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6360
6361 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6362 I915_READ(ILK_DISPLAY_CHICKEN2) |
6363 ILK_ELPIN_409_SELECT);
6364
6365 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
6366 I915_WRITE(_3D_CHICKEN,
6367 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
6368
6369 /* WaDisable_RenderCache_OperationalFlush:snb */
6370 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6371
6372 /*
6373 * BSpec recoomends 8x4 when MSAA is used,
6374 * however in practice 16x4 seems fastest.
6375 *
6376 * Note that PS/WM thread counts depend on the WIZ hashing
6377 * disable bit, which we don't touch here, but it's good
6378 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6379 */
6380 I915_WRITE(GEN6_GT_MODE,
6381 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6382
6383 ilk_init_lp_watermarks(dev);
6384
6385 I915_WRITE(CACHE_MODE_0,
6386 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6387
6388 I915_WRITE(GEN6_UCGCTL1,
6389 I915_READ(GEN6_UCGCTL1) |
6390 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
6391 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6392
6393 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
6394 * gating disable must be set. Failure to set it results in
6395 * flickering pixels due to Z write ordering failures after
6396 * some amount of runtime in the Mesa "fire" demo, and Unigine
6397 * Sanctuary and Tropics, and apparently anything else with
6398 * alpha test or pixel discard.
6399 *
6400 * According to the spec, bit 11 (RCCUNIT) must also be set,
6401 * but we didn't debug actual testcases to find it out.
6402 *
6403 * WaDisableRCCUnitClockGating:snb
6404 * WaDisableRCPBUnitClockGating:snb
6405 */
6406 I915_WRITE(GEN6_UCGCTL2,
6407 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
6408 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
6409
6410 /* WaStripsFansDisableFastClipPerformanceFix:snb */
6411 I915_WRITE(_3D_CHICKEN3,
6412 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6413
6414 /*
6415 * Bspec says:
6416 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
6417 * 3DSTATE_SF number of SF output attributes is more than 16."
6418 */
6419 I915_WRITE(_3D_CHICKEN3,
6420 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
6421
6422 /*
6423 * According to the spec the following bits should be
6424 * set in order to enable memory self-refresh and fbc:
6425 * The bit21 and bit22 of 0x42000
6426 * The bit21 and bit22 of 0x42004
6427 * The bit5 and bit7 of 0x42020
6428 * The bit14 of 0x70180
6429 * The bit14 of 0x71180
6430 *
6431 * WaFbcAsynchFlipDisableFbcQueue:snb
6432 */
6433 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6434 I915_READ(ILK_DISPLAY_CHICKEN1) |
6435 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6436 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6437 I915_READ(ILK_DISPLAY_CHICKEN2) |
6438 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
6439 I915_WRITE(ILK_DSPCLK_GATE_D,
6440 I915_READ(ILK_DSPCLK_GATE_D) |
6441 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
6442 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6443
6444 g4x_disable_trickle_feed(dev);
6445
6446 cpt_init_clock_gating(dev);
6447
6448 gen6_check_mch_setup(dev);
6449 }
6450
6451 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
6452 {
6453 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
6454
6455 /*
6456 * WaVSThreadDispatchOverride:ivb,vlv
6457 *
6458 * This actually overrides the dispatch
6459 * mode for all thread types.
6460 */
6461 reg &= ~GEN7_FF_SCHED_MASK;
6462 reg |= GEN7_FF_TS_SCHED_HW;
6463 reg |= GEN7_FF_VS_SCHED_HW;
6464 reg |= GEN7_FF_DS_SCHED_HW;
6465
6466 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
6467 }
6468
6469 static void lpt_init_clock_gating(struct drm_device *dev)
6470 {
6471 struct drm_i915_private *dev_priv = dev->dev_private;
6472
6473 /*
6474 * TODO: this bit should only be enabled when really needed, then
6475 * disabled when not needed anymore in order to save power.
6476 */
6477 if (HAS_PCH_LPT_LP(dev))
6478 I915_WRITE(SOUTH_DSPCLK_GATE_D,
6479 I915_READ(SOUTH_DSPCLK_GATE_D) |
6480 PCH_LP_PARTITION_LEVEL_DISABLE);
6481
6482 /* WADPOClockGatingDisable:hsw */
6483 I915_WRITE(TRANS_CHICKEN1(PIPE_A),
6484 I915_READ(TRANS_CHICKEN1(PIPE_A)) |
6485 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6486 }
6487
6488 static void lpt_suspend_hw(struct drm_device *dev)
6489 {
6490 struct drm_i915_private *dev_priv = dev->dev_private;
6491
6492 if (HAS_PCH_LPT_LP(dev)) {
6493 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
6494
6495 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6496 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6497 }
6498 }
6499
6500 static void broadwell_init_clock_gating(struct drm_device *dev)
6501 {
6502 struct drm_i915_private *dev_priv = dev->dev_private;
6503 enum pipe pipe;
6504 uint32_t misccpctl;
6505
6506 ilk_init_lp_watermarks(dev);
6507
6508 /* WaSwitchSolVfFArbitrationPriority:bdw */
6509 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6510
6511 /* WaPsrDPAMaskVBlankInSRD:bdw */
6512 I915_WRITE(CHICKEN_PAR1_1,
6513 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
6514
6515 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
6516 for_each_pipe(dev_priv, pipe) {
6517 I915_WRITE(CHICKEN_PIPESL_1(pipe),
6518 I915_READ(CHICKEN_PIPESL_1(pipe)) |
6519 BDW_DPRS_MASK_VBLANK_SRD);
6520 }
6521
6522 /* WaVSRefCountFullforceMissDisable:bdw */
6523 /* WaDSRefCountFullforceMissDisable:bdw */
6524 I915_WRITE(GEN7_FF_THREAD_MODE,
6525 I915_READ(GEN7_FF_THREAD_MODE) &
6526 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
6527
6528 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6529 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
6530
6531 /* WaDisableSDEUnitClockGating:bdw */
6532 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6533 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6534
6535 /*
6536 * WaProgramL3SqcReg1Default:bdw
6537 * WaTempDisableDOPClkGating:bdw
6538 */
6539 misccpctl = I915_READ(GEN7_MISCCPCTL);
6540 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
6541 I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
6542 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
6543
6544 /*
6545 * WaGttCachingOffByDefault:bdw
6546 * GTT cache may not work with big pages, so if those
6547 * are ever enabled GTT cache may need to be disabled.
6548 */
6549 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
6550
6551 lpt_init_clock_gating(dev);
6552 }
6553
6554 static void haswell_init_clock_gating(struct drm_device *dev)
6555 {
6556 struct drm_i915_private *dev_priv = dev->dev_private;
6557
6558 ilk_init_lp_watermarks(dev);
6559
6560 /* L3 caching of data atomics doesn't work -- disable it. */
6561 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
6562 I915_WRITE(HSW_ROW_CHICKEN3,
6563 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
6564
6565 /* This is required by WaCatErrorRejectionIssue:hsw */
6566 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6567 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6568 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6569
6570 /* WaVSRefCountFullforceMissDisable:hsw */
6571 I915_WRITE(GEN7_FF_THREAD_MODE,
6572 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
6573
6574 /* WaDisable_RenderCache_OperationalFlush:hsw */
6575 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6576
6577 /* enable HiZ Raw Stall Optimization */
6578 I915_WRITE(CACHE_MODE_0_GEN7,
6579 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6580
6581 /* WaDisable4x2SubspanOptimization:hsw */
6582 I915_WRITE(CACHE_MODE_1,
6583 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6584
6585 /*
6586 * BSpec recommends 8x4 when MSAA is used,
6587 * however in practice 16x4 seems fastest.
6588 *
6589 * Note that PS/WM thread counts depend on the WIZ hashing
6590 * disable bit, which we don't touch here, but it's good
6591 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6592 */
6593 I915_WRITE(GEN7_GT_MODE,
6594 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6595
6596 /* WaSampleCChickenBitEnable:hsw */
6597 I915_WRITE(HALF_SLICE_CHICKEN3,
6598 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
6599
6600 /* WaSwitchSolVfFArbitrationPriority:hsw */
6601 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6602
6603 /* WaRsPkgCStateDisplayPMReq:hsw */
6604 I915_WRITE(CHICKEN_PAR1_1,
6605 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
6606
6607 lpt_init_clock_gating(dev);
6608 }
6609
6610 static void ivybridge_init_clock_gating(struct drm_device *dev)
6611 {
6612 struct drm_i915_private *dev_priv = dev->dev_private;
6613 uint32_t snpcr;
6614
6615 ilk_init_lp_watermarks(dev);
6616
6617 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6618
6619 /* WaDisableEarlyCull:ivb */
6620 I915_WRITE(_3D_CHICKEN3,
6621 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6622
6623 /* WaDisableBackToBackFlipFix:ivb */
6624 I915_WRITE(IVB_CHICKEN3,
6625 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6626 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6627
6628 /* WaDisablePSDDualDispatchEnable:ivb */
6629 if (IS_IVB_GT1(dev))
6630 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6631 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
6632
6633 /* WaDisable_RenderCache_OperationalFlush:ivb */
6634 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6635
6636 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6637 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
6638 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
6639
6640 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6641 I915_WRITE(GEN7_L3CNTLREG1,
6642 GEN7_WA_FOR_GEN7_L3_CONTROL);
6643 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
6644 GEN7_WA_L3_CHICKEN_MODE);
6645 if (IS_IVB_GT1(dev))
6646 I915_WRITE(GEN7_ROW_CHICKEN2,
6647 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6648 else {
6649 /* must write both registers */
6650 I915_WRITE(GEN7_ROW_CHICKEN2,
6651 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6652 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
6653 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6654 }
6655
6656 /* WaForceL3Serialization:ivb */
6657 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6658 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6659
6660 /*
6661 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6662 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
6663 */
6664 I915_WRITE(GEN6_UCGCTL2,
6665 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
6666
6667 /* This is required by WaCatErrorRejectionIssue:ivb */
6668 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6669 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6670 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6671
6672 g4x_disable_trickle_feed(dev);
6673
6674 gen7_setup_fixed_func_scheduler(dev_priv);
6675
6676 if (0) { /* causes HiZ corruption on ivb:gt1 */
6677 /* enable HiZ Raw Stall Optimization */
6678 I915_WRITE(CACHE_MODE_0_GEN7,
6679 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6680 }
6681
6682 /* WaDisable4x2SubspanOptimization:ivb */
6683 I915_WRITE(CACHE_MODE_1,
6684 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6685
6686 /*
6687 * BSpec recommends 8x4 when MSAA is used,
6688 * however in practice 16x4 seems fastest.
6689 *
6690 * Note that PS/WM thread counts depend on the WIZ hashing
6691 * disable bit, which we don't touch here, but it's good
6692 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6693 */
6694 I915_WRITE(GEN7_GT_MODE,
6695 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6696
6697 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
6698 snpcr &= ~GEN6_MBC_SNPCR_MASK;
6699 snpcr |= GEN6_MBC_SNPCR_MED;
6700 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
6701
6702 if (!HAS_PCH_NOP(dev))
6703 cpt_init_clock_gating(dev);
6704
6705 gen6_check_mch_setup(dev);
6706 }
6707
6708 static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
6709 {
6710 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6711
6712 /*
6713 * Disable trickle feed and enable pnd deadline calculation
6714 */
6715 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6716 I915_WRITE(CBR1_VLV, 0);
6717 }
6718
6719 static void valleyview_init_clock_gating(struct drm_device *dev)
6720 {
6721 struct drm_i915_private *dev_priv = dev->dev_private;
6722
6723 vlv_init_display_clock_gating(dev_priv);
6724
6725 /* WaDisableEarlyCull:vlv */
6726 I915_WRITE(_3D_CHICKEN3,
6727 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6728
6729 /* WaDisableBackToBackFlipFix:vlv */
6730 I915_WRITE(IVB_CHICKEN3,
6731 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6732 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6733
6734 /* WaPsdDispatchEnable:vlv */
6735 /* WaDisablePSDDualDispatchEnable:vlv */
6736 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6737 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
6738 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
6739
6740 /* WaDisable_RenderCache_OperationalFlush:vlv */
6741 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6742
6743 /* WaForceL3Serialization:vlv */
6744 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6745 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6746
6747 /* WaDisableDopClockGating:vlv */
6748 I915_WRITE(GEN7_ROW_CHICKEN2,
6749 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6750
6751 /* This is required by WaCatErrorRejectionIssue:vlv */
6752 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6753 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6754 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6755
6756 gen7_setup_fixed_func_scheduler(dev_priv);
6757
6758 /*
6759 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6760 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
6761 */
6762 I915_WRITE(GEN6_UCGCTL2,
6763 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
6764
6765 /* WaDisableL3Bank2xClockGate:vlv
6766 * Disabling L3 clock gating- MMIO 940c[25] = 1
6767 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
6768 I915_WRITE(GEN7_UCGCTL4,
6769 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
6770
6771 /*
6772 * BSpec says this must be set, even though
6773 * WaDisable4x2SubspanOptimization isn't listed for VLV.
6774 */
6775 I915_WRITE(CACHE_MODE_1,
6776 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6777
6778 /*
6779 * BSpec recommends 8x4 when MSAA is used,
6780 * however in practice 16x4 seems fastest.
6781 *
6782 * Note that PS/WM thread counts depend on the WIZ hashing
6783 * disable bit, which we don't touch here, but it's good
6784 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6785 */
6786 I915_WRITE(GEN7_GT_MODE,
6787 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6788
6789 /*
6790 * WaIncreaseL3CreditsForVLVB0:vlv
6791 * This is the hardware default actually.
6792 */
6793 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
6794
6795 /*
6796 * WaDisableVLVClockGating_VBIIssue:vlv
6797 * Disable clock gating on th GCFG unit to prevent a delay
6798 * in the reporting of vblank events.
6799 */
6800 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6801 }
6802
6803 static void cherryview_init_clock_gating(struct drm_device *dev)
6804 {
6805 struct drm_i915_private *dev_priv = dev->dev_private;
6806
6807 vlv_init_display_clock_gating(dev_priv);
6808
6809 /* WaVSRefCountFullforceMissDisable:chv */
6810 /* WaDSRefCountFullforceMissDisable:chv */
6811 I915_WRITE(GEN7_FF_THREAD_MODE,
6812 I915_READ(GEN7_FF_THREAD_MODE) &
6813 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
6814
6815 /* WaDisableSemaphoreAndSyncFlipWait:chv */
6816 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6817 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
6818
6819 /* WaDisableCSUnitClockGating:chv */
6820 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
6821 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6822
6823 /* WaDisableSDEUnitClockGating:chv */
6824 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6825 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6826
6827 /*
6828 * GTT cache may not work with big pages, so if those
6829 * are ever enabled GTT cache may need to be disabled.
6830 */
6831 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
6832 }
6833
6834 static void g4x_init_clock_gating(struct drm_device *dev)
6835 {
6836 struct drm_i915_private *dev_priv = dev->dev_private;
6837 uint32_t dspclk_gate;
6838
6839 I915_WRITE(RENCLK_GATE_D1, 0);
6840 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
6841 GS_UNIT_CLOCK_GATE_DISABLE |
6842 CL_UNIT_CLOCK_GATE_DISABLE);
6843 I915_WRITE(RAMCLK_GATE_D, 0);
6844 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
6845 OVRUNIT_CLOCK_GATE_DISABLE |
6846 OVCUNIT_CLOCK_GATE_DISABLE;
6847 if (IS_GM45(dev))
6848 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
6849 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
6850
6851 /* WaDisableRenderCachePipelinedFlush */
6852 I915_WRITE(CACHE_MODE_0,
6853 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6854
6855 /* WaDisable_RenderCache_OperationalFlush:g4x */
6856 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6857
6858 g4x_disable_trickle_feed(dev);
6859 }
6860
6861 static void crestline_init_clock_gating(struct drm_device *dev)
6862 {
6863 struct drm_i915_private *dev_priv = dev->dev_private;
6864
6865 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
6866 I915_WRITE(RENCLK_GATE_D2, 0);
6867 I915_WRITE(DSPCLK_GATE_D, 0);
6868 I915_WRITE(RAMCLK_GATE_D, 0);
6869 I915_WRITE16(DEUC, 0);
6870 I915_WRITE(MI_ARB_STATE,
6871 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6872
6873 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6874 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6875 }
6876
6877 static void broadwater_init_clock_gating(struct drm_device *dev)
6878 {
6879 struct drm_i915_private *dev_priv = dev->dev_private;
6880
6881 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
6882 I965_RCC_CLOCK_GATE_DISABLE |
6883 I965_RCPB_CLOCK_GATE_DISABLE |
6884 I965_ISC_CLOCK_GATE_DISABLE |
6885 I965_FBC_CLOCK_GATE_DISABLE);
6886 I915_WRITE(RENCLK_GATE_D2, 0);
6887 I915_WRITE(MI_ARB_STATE,
6888 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6889
6890 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6891 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6892 }
6893
6894 static void gen3_init_clock_gating(struct drm_device *dev)
6895 {
6896 struct drm_i915_private *dev_priv = dev->dev_private;
6897 u32 dstate = I915_READ(D_STATE);
6898
6899 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
6900 DSTATE_DOT_CLOCK_GATING;
6901 I915_WRITE(D_STATE, dstate);
6902
6903 if (IS_PINEVIEW(dev))
6904 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
6905
6906 /* IIR "flip pending" means done if this bit is set */
6907 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
6908
6909 /* interrupts should cause a wake up from C3 */
6910 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
6911
6912 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
6913 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
6914
6915 I915_WRITE(MI_ARB_STATE,
6916 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6917 }
6918
6919 static void i85x_init_clock_gating(struct drm_device *dev)
6920 {
6921 struct drm_i915_private *dev_priv = dev->dev_private;
6922
6923 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
6924
6925 /* interrupts should cause a wake up from C3 */
6926 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
6927 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
6928
6929 I915_WRITE(MEM_MODE,
6930 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
6931 }
6932
6933 static void i830_init_clock_gating(struct drm_device *dev)
6934 {
6935 struct drm_i915_private *dev_priv = dev->dev_private;
6936
6937 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
6938
6939 I915_WRITE(MEM_MODE,
6940 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
6941 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
6942 }
6943
6944 void intel_init_clock_gating(struct drm_device *dev)
6945 {
6946 struct drm_i915_private *dev_priv = dev->dev_private;
6947
6948 if (dev_priv->display.init_clock_gating)
6949 dev_priv->display.init_clock_gating(dev);
6950 }
6951
6952 void intel_suspend_hw(struct drm_device *dev)
6953 {
6954 if (HAS_PCH_LPT(dev))
6955 lpt_suspend_hw(dev);
6956 }
6957
6958 /* Set up chip specific power management-related functions */
6959 void intel_init_pm(struct drm_device *dev)
6960 {
6961 struct drm_i915_private *dev_priv = dev->dev_private;
6962
6963 intel_fbc_init(dev_priv);
6964
6965 /* For cxsr */
6966 if (IS_PINEVIEW(dev))
6967 i915_pineview_get_mem_freq(dev);
6968 else if (IS_GEN5(dev))
6969 i915_ironlake_get_mem_freq(dev);
6970
6971 /* For FIFO watermark updates */
6972 if (INTEL_INFO(dev)->gen >= 9) {
6973 skl_setup_wm_latency(dev);
6974
6975 if (IS_BROXTON(dev))
6976 dev_priv->display.init_clock_gating =
6977 bxt_init_clock_gating;
6978 dev_priv->display.update_wm = skl_update_wm;
6979 } else if (HAS_PCH_SPLIT(dev)) {
6980 ilk_setup_wm_latency(dev);
6981
6982 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
6983 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
6984 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
6985 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
6986 dev_priv->display.update_wm = ilk_update_wm;
6987 dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
6988 } else {
6989 DRM_DEBUG_KMS("Failed to read display plane latency. "
6990 "Disable CxSR\n");
6991 }
6992
6993 if (IS_GEN5(dev))
6994 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
6995 else if (IS_GEN6(dev))
6996 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
6997 else if (IS_IVYBRIDGE(dev))
6998 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
6999 else if (IS_HASWELL(dev))
7000 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7001 else if (INTEL_INFO(dev)->gen == 8)
7002 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7003 } else if (IS_CHERRYVIEW(dev)) {
7004 vlv_setup_wm_latency(dev);
7005
7006 dev_priv->display.update_wm = vlv_update_wm;
7007 dev_priv->display.init_clock_gating =
7008 cherryview_init_clock_gating;
7009 } else if (IS_VALLEYVIEW(dev)) {
7010 vlv_setup_wm_latency(dev);
7011
7012 dev_priv->display.update_wm = vlv_update_wm;
7013 dev_priv->display.init_clock_gating =
7014 valleyview_init_clock_gating;
7015 } else if (IS_PINEVIEW(dev)) {
7016 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7017 dev_priv->is_ddr3,
7018 dev_priv->fsb_freq,
7019 dev_priv->mem_freq)) {
7020 DRM_INFO("failed to find known CxSR latency "
7021 "(found ddr%s fsb freq %d, mem freq %d), "
7022 "disabling CxSR\n",
7023 (dev_priv->is_ddr3 == 1) ? "3" : "2",
7024 dev_priv->fsb_freq, dev_priv->mem_freq);
7025 /* Disable CxSR and never update its watermark again */
7026 intel_set_memory_cxsr(dev_priv, false);
7027 dev_priv->display.update_wm = NULL;
7028 } else
7029 dev_priv->display.update_wm = pineview_update_wm;
7030 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7031 } else if (IS_G4X(dev)) {
7032 dev_priv->display.update_wm = g4x_update_wm;
7033 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7034 } else if (IS_GEN4(dev)) {
7035 dev_priv->display.update_wm = i965_update_wm;
7036 if (IS_CRESTLINE(dev))
7037 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7038 else if (IS_BROADWATER(dev))
7039 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7040 } else if (IS_GEN3(dev)) {
7041 dev_priv->display.update_wm = i9xx_update_wm;
7042 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7043 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7044 } else if (IS_GEN2(dev)) {
7045 if (INTEL_INFO(dev)->num_pipes == 1) {
7046 dev_priv->display.update_wm = i845_update_wm;
7047 dev_priv->display.get_fifo_size = i845_get_fifo_size;
7048 } else {
7049 dev_priv->display.update_wm = i9xx_update_wm;
7050 dev_priv->display.get_fifo_size = i830_get_fifo_size;
7051 }
7052
7053 if (IS_I85X(dev) || IS_I865G(dev))
7054 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7055 else
7056 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7057 } else {
7058 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
7059 }
7060 }
7061
7062 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
7063 {
7064 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7065
7066 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7067 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7068 return -EAGAIN;
7069 }
7070
7071 I915_WRITE(GEN6_PCODE_DATA, *val);
7072 I915_WRITE(GEN6_PCODE_DATA1, 0);
7073 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7074
7075 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7076 500)) {
7077 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7078 return -ETIMEDOUT;
7079 }
7080
7081 *val = I915_READ(GEN6_PCODE_DATA);
7082 I915_WRITE(GEN6_PCODE_DATA, 0);
7083
7084 return 0;
7085 }
7086
7087 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val)
7088 {
7089 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7090
7091 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7092 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7093 return -EAGAIN;
7094 }
7095
7096 I915_WRITE(GEN6_PCODE_DATA, val);
7097 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7098
7099 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7100 500)) {
7101 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7102 return -ETIMEDOUT;
7103 }
7104
7105 I915_WRITE(GEN6_PCODE_DATA, 0);
7106
7107 return 0;
7108 }
7109
7110 static int vlv_gpu_freq_div(unsigned int czclk_freq)
7111 {
7112 switch (czclk_freq) {
7113 case 200:
7114 return 10;
7115 case 267:
7116 return 12;
7117 case 320:
7118 case 333:
7119 return 16;
7120 case 400:
7121 return 20;
7122 default:
7123 return -1;
7124 }
7125 }
7126
7127 static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7128 {
7129 int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
7130
7131 div = vlv_gpu_freq_div(czclk_freq);
7132 if (div < 0)
7133 return div;
7134
7135 return DIV_ROUND_CLOSEST(czclk_freq * (val + 6 - 0xbd), div);
7136 }
7137
7138 static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
7139 {
7140 int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
7141
7142 mul = vlv_gpu_freq_div(czclk_freq);
7143 if (mul < 0)
7144 return mul;
7145
7146 return DIV_ROUND_CLOSEST(mul * val, czclk_freq) + 0xbd - 6;
7147 }
7148
7149 static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
7150 {
7151 int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
7152
7153 div = vlv_gpu_freq_div(czclk_freq) / 2;
7154 if (div < 0)
7155 return div;
7156
7157 return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2;
7158 }
7159
7160 static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
7161 {
7162 int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
7163
7164 mul = vlv_gpu_freq_div(czclk_freq) / 2;
7165 if (mul < 0)
7166 return mul;
7167
7168 /* CHV needs even values */
7169 return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2;
7170 }
7171
7172 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
7173 {
7174 if (IS_GEN9(dev_priv->dev))
7175 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
7176 GEN9_FREQ_SCALER);
7177 else if (IS_CHERRYVIEW(dev_priv->dev))
7178 return chv_gpu_freq(dev_priv, val);
7179 else if (IS_VALLEYVIEW(dev_priv->dev))
7180 return byt_gpu_freq(dev_priv, val);
7181 else
7182 return val * GT_FREQUENCY_MULTIPLIER;
7183 }
7184
7185 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7186 {
7187 if (IS_GEN9(dev_priv->dev))
7188 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
7189 GT_FREQUENCY_MULTIPLIER);
7190 else if (IS_CHERRYVIEW(dev_priv->dev))
7191 return chv_freq_opcode(dev_priv, val);
7192 else if (IS_VALLEYVIEW(dev_priv->dev))
7193 return byt_freq_opcode(dev_priv, val);
7194 else
7195 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
7196 }
7197
7198 struct request_boost {
7199 struct work_struct work;
7200 struct drm_i915_gem_request *req;
7201 };
7202
7203 static void __intel_rps_boost_work(struct work_struct *work)
7204 {
7205 struct request_boost *boost = container_of(work, struct request_boost, work);
7206 struct drm_i915_gem_request *req = boost->req;
7207
7208 if (!i915_gem_request_completed(req, true))
7209 gen6_rps_boost(to_i915(req->ring->dev), NULL,
7210 req->emitted_jiffies);
7211
7212 i915_gem_request_unreference__unlocked(req);
7213 kfree(boost);
7214 }
7215
7216 void intel_queue_rps_boost_for_request(struct drm_device *dev,
7217 struct drm_i915_gem_request *req)
7218 {
7219 struct request_boost *boost;
7220
7221 if (req == NULL || INTEL_INFO(dev)->gen < 6)
7222 return;
7223
7224 if (i915_gem_request_completed(req, true))
7225 return;
7226
7227 boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
7228 if (boost == NULL)
7229 return;
7230
7231 i915_gem_request_reference(req);
7232 boost->req = req;
7233
7234 INIT_WORK(&boost->work, __intel_rps_boost_work);
7235 queue_work(to_i915(dev)->wq, &boost->work);
7236 }
7237
7238 void intel_pm_setup(struct drm_device *dev)
7239 {
7240 struct drm_i915_private *dev_priv = dev->dev_private;
7241
7242 mutex_init(&dev_priv->rps.hw_lock);
7243 spin_lock_init(&dev_priv->rps.client_lock);
7244
7245 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
7246 intel_gen6_powersave_work);
7247 INIT_LIST_HEAD(&dev_priv->rps.clients);
7248 INIT_LIST_HEAD(&dev_priv->rps.semaphores.link);
7249 INIT_LIST_HEAD(&dev_priv->rps.mmioflips.link);
7250
7251 dev_priv->pm.suspended = false;
7252 atomic_set(&dev_priv->pm.wakeref_count, 0);
7253 atomic_set(&dev_priv->pm.atomic_seq, 0);
7254 }
Linux kernel - Deliverables
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