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drm/i915: s/9/intel_freq_opcode(450)/
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_pm.c
1 /*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28 #include <linux/cpufreq.h>
29 #include "i915_drv.h"
30 #include "intel_drv.h"
31 #include "../../../platform/x86/intel_ips.h"
32 #include <linux/module.h>
33
34 /**
35 * RC6 is a special power stage which allows the GPU to enter an very
36 * low-voltage mode when idle, using down to 0V while at this stage. This
37 * stage is entered automatically when the GPU is idle when RC6 support is
38 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
39 *
40 * There are different RC6 modes available in Intel GPU, which differentiate
41 * among each other with the latency required to enter and leave RC6 and
42 * voltage consumed by the GPU in different states.
43 *
44 * The combination of the following flags define which states GPU is allowed
45 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
46 * RC6pp is deepest RC6. Their support by hardware varies according to the
47 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
48 * which brings the most power savings; deeper states save more power, but
49 * require higher latency to switch to and wake up.
50 */
51 #define INTEL_RC6_ENABLE (1<<0)
52 #define INTEL_RC6p_ENABLE (1<<1)
53 #define INTEL_RC6pp_ENABLE (1<<2)
54
55 static void gen9_init_clock_gating(struct drm_device *dev)
56 {
57 struct drm_i915_private *dev_priv = dev->dev_private;
58
59 /* WaEnableLbsSlaRetryTimerDecrement:skl */
60 I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
61 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
62 }
63
64 static void skl_init_clock_gating(struct drm_device *dev)
65 {
66 struct drm_i915_private *dev_priv = dev->dev_private;
67
68 gen9_init_clock_gating(dev);
69
70 if (INTEL_REVID(dev) <= SKL_REVID_B0) {
71 /*
72 * WaDisableSDEUnitClockGating:skl
73 * WaSetGAPSunitClckGateDisable:skl
74 */
75 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
76 GEN8_GAPSUNIT_CLOCK_GATE_DISABLE |
77 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
78
79 /* WaDisableVFUnitClockGating:skl */
80 I915_WRITE(GEN6_UCGCTL2, I915_READ(GEN6_UCGCTL2) |
81 GEN6_VFUNIT_CLOCK_GATE_DISABLE);
82 }
83
84 if (INTEL_REVID(dev) <= SKL_REVID_D0) {
85 /* WaDisableHDCInvalidation:skl */
86 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
87 BDW_DISABLE_HDC_INVALIDATION);
88
89 /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
90 I915_WRITE(FF_SLICE_CS_CHICKEN2,
91 I915_READ(FF_SLICE_CS_CHICKEN2) |
92 GEN9_TSG_BARRIER_ACK_DISABLE);
93 }
94
95 if (INTEL_REVID(dev) <= SKL_REVID_E0)
96 /* WaDisableLSQCROPERFforOCL:skl */
97 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
98 GEN8_LQSC_RO_PERF_DIS);
99 }
100
101 static void bxt_init_clock_gating(struct drm_device *dev)
102 {
103 struct drm_i915_private *dev_priv = dev->dev_private;
104
105 gen9_init_clock_gating(dev);
106
107 /*
108 * FIXME:
109 * GEN8_SDEUNIT_CLOCK_GATE_DISABLE applies on A0 only.
110 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
111 */
112 /* WaDisableSDEUnitClockGating:bxt */
113 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
114 GEN8_SDEUNIT_CLOCK_GATE_DISABLE |
115 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
116
117 /* FIXME: apply on A0 only */
118 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
119 }
120
121 static void i915_pineview_get_mem_freq(struct drm_device *dev)
122 {
123 struct drm_i915_private *dev_priv = dev->dev_private;
124 u32 tmp;
125
126 tmp = I915_READ(CLKCFG);
127
128 switch (tmp & CLKCFG_FSB_MASK) {
129 case CLKCFG_FSB_533:
130 dev_priv->fsb_freq = 533; /* 133*4 */
131 break;
132 case CLKCFG_FSB_800:
133 dev_priv->fsb_freq = 800; /* 200*4 */
134 break;
135 case CLKCFG_FSB_667:
136 dev_priv->fsb_freq = 667; /* 167*4 */
137 break;
138 case CLKCFG_FSB_400:
139 dev_priv->fsb_freq = 400; /* 100*4 */
140 break;
141 }
142
143 switch (tmp & CLKCFG_MEM_MASK) {
144 case CLKCFG_MEM_533:
145 dev_priv->mem_freq = 533;
146 break;
147 case CLKCFG_MEM_667:
148 dev_priv->mem_freq = 667;
149 break;
150 case CLKCFG_MEM_800:
151 dev_priv->mem_freq = 800;
152 break;
153 }
154
155 /* detect pineview DDR3 setting */
156 tmp = I915_READ(CSHRDDR3CTL);
157 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
158 }
159
160 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
161 {
162 struct drm_i915_private *dev_priv = dev->dev_private;
163 u16 ddrpll, csipll;
164
165 ddrpll = I915_READ16(DDRMPLL1);
166 csipll = I915_READ16(CSIPLL0);
167
168 switch (ddrpll & 0xff) {
169 case 0xc:
170 dev_priv->mem_freq = 800;
171 break;
172 case 0x10:
173 dev_priv->mem_freq = 1066;
174 break;
175 case 0x14:
176 dev_priv->mem_freq = 1333;
177 break;
178 case 0x18:
179 dev_priv->mem_freq = 1600;
180 break;
181 default:
182 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
183 ddrpll & 0xff);
184 dev_priv->mem_freq = 0;
185 break;
186 }
187
188 dev_priv->ips.r_t = dev_priv->mem_freq;
189
190 switch (csipll & 0x3ff) {
191 case 0x00c:
192 dev_priv->fsb_freq = 3200;
193 break;
194 case 0x00e:
195 dev_priv->fsb_freq = 3733;
196 break;
197 case 0x010:
198 dev_priv->fsb_freq = 4266;
199 break;
200 case 0x012:
201 dev_priv->fsb_freq = 4800;
202 break;
203 case 0x014:
204 dev_priv->fsb_freq = 5333;
205 break;
206 case 0x016:
207 dev_priv->fsb_freq = 5866;
208 break;
209 case 0x018:
210 dev_priv->fsb_freq = 6400;
211 break;
212 default:
213 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
214 csipll & 0x3ff);
215 dev_priv->fsb_freq = 0;
216 break;
217 }
218
219 if (dev_priv->fsb_freq == 3200) {
220 dev_priv->ips.c_m = 0;
221 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
222 dev_priv->ips.c_m = 1;
223 } else {
224 dev_priv->ips.c_m = 2;
225 }
226 }
227
228 static const struct cxsr_latency cxsr_latency_table[] = {
229 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
230 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
231 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
232 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
233 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
234
235 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
236 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
237 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
238 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
239 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
240
241 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
242 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
243 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
244 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
245 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
246
247 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
248 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
249 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
250 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
251 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
252
253 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
254 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
255 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
256 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
257 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
258
259 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
260 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
261 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
262 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
263 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
264 };
265
266 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
267 int is_ddr3,
268 int fsb,
269 int mem)
270 {
271 const struct cxsr_latency *latency;
272 int i;
273
274 if (fsb == 0 || mem == 0)
275 return NULL;
276
277 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
278 latency = &cxsr_latency_table[i];
279 if (is_desktop == latency->is_desktop &&
280 is_ddr3 == latency->is_ddr3 &&
281 fsb == latency->fsb_freq && mem == latency->mem_freq)
282 return latency;
283 }
284
285 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
286
287 return NULL;
288 }
289
290 static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
291 {
292 u32 val;
293
294 mutex_lock(&dev_priv->rps.hw_lock);
295
296 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
297 if (enable)
298 val &= ~FORCE_DDR_HIGH_FREQ;
299 else
300 val |= FORCE_DDR_HIGH_FREQ;
301 val &= ~FORCE_DDR_LOW_FREQ;
302 val |= FORCE_DDR_FREQ_REQ_ACK;
303 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
304
305 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
306 FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
307 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
308
309 mutex_unlock(&dev_priv->rps.hw_lock);
310 }
311
312 static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
313 {
314 u32 val;
315
316 mutex_lock(&dev_priv->rps.hw_lock);
317
318 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
319 if (enable)
320 val |= DSP_MAXFIFO_PM5_ENABLE;
321 else
322 val &= ~DSP_MAXFIFO_PM5_ENABLE;
323 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
324
325 mutex_unlock(&dev_priv->rps.hw_lock);
326 }
327
328 #define FW_WM(value, plane) \
329 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
330
331 void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
332 {
333 struct drm_device *dev = dev_priv->dev;
334 u32 val;
335
336 if (IS_VALLEYVIEW(dev)) {
337 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
338 if (IS_CHERRYVIEW(dev))
339 chv_set_memory_pm5(dev_priv, enable);
340 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
341 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
342 } else if (IS_PINEVIEW(dev)) {
343 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
344 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
345 I915_WRITE(DSPFW3, val);
346 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
347 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
348 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
349 I915_WRITE(FW_BLC_SELF, val);
350 } else if (IS_I915GM(dev)) {
351 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
352 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
353 I915_WRITE(INSTPM, val);
354 } else {
355 return;
356 }
357
358 DRM_DEBUG_KMS("memory self-refresh is %s\n",
359 enable ? "enabled" : "disabled");
360 }
361
362
363 /*
364 * Latency for FIFO fetches is dependent on several factors:
365 * - memory configuration (speed, channels)
366 * - chipset
367 * - current MCH state
368 * It can be fairly high in some situations, so here we assume a fairly
369 * pessimal value. It's a tradeoff between extra memory fetches (if we
370 * set this value too high, the FIFO will fetch frequently to stay full)
371 * and power consumption (set it too low to save power and we might see
372 * FIFO underruns and display "flicker").
373 *
374 * A value of 5us seems to be a good balance; safe for very low end
375 * platforms but not overly aggressive on lower latency configs.
376 */
377 static const int pessimal_latency_ns = 5000;
378
379 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
380 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
381
382 static int vlv_get_fifo_size(struct drm_device *dev,
383 enum pipe pipe, int plane)
384 {
385 struct drm_i915_private *dev_priv = dev->dev_private;
386 int sprite0_start, sprite1_start, size;
387
388 switch (pipe) {
389 uint32_t dsparb, dsparb2, dsparb3;
390 case PIPE_A:
391 dsparb = I915_READ(DSPARB);
392 dsparb2 = I915_READ(DSPARB2);
393 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
394 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
395 break;
396 case PIPE_B:
397 dsparb = I915_READ(DSPARB);
398 dsparb2 = I915_READ(DSPARB2);
399 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
400 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
401 break;
402 case PIPE_C:
403 dsparb2 = I915_READ(DSPARB2);
404 dsparb3 = I915_READ(DSPARB3);
405 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
406 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
407 break;
408 default:
409 return 0;
410 }
411
412 switch (plane) {
413 case 0:
414 size = sprite0_start;
415 break;
416 case 1:
417 size = sprite1_start - sprite0_start;
418 break;
419 case 2:
420 size = 512 - 1 - sprite1_start;
421 break;
422 default:
423 return 0;
424 }
425
426 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
427 pipe_name(pipe), plane == 0 ? "primary" : "sprite",
428 plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
429 size);
430
431 return size;
432 }
433
434 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
435 {
436 struct drm_i915_private *dev_priv = dev->dev_private;
437 uint32_t dsparb = I915_READ(DSPARB);
438 int size;
439
440 size = dsparb & 0x7f;
441 if (plane)
442 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
443
444 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
445 plane ? "B" : "A", size);
446
447 return size;
448 }
449
450 static int i830_get_fifo_size(struct drm_device *dev, int plane)
451 {
452 struct drm_i915_private *dev_priv = dev->dev_private;
453 uint32_t dsparb = I915_READ(DSPARB);
454 int size;
455
456 size = dsparb & 0x1ff;
457 if (plane)
458 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
459 size >>= 1; /* Convert to cachelines */
460
461 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
462 plane ? "B" : "A", size);
463
464 return size;
465 }
466
467 static int i845_get_fifo_size(struct drm_device *dev, int plane)
468 {
469 struct drm_i915_private *dev_priv = dev->dev_private;
470 uint32_t dsparb = I915_READ(DSPARB);
471 int size;
472
473 size = dsparb & 0x7f;
474 size >>= 2; /* Convert to cachelines */
475
476 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
477 plane ? "B" : "A",
478 size);
479
480 return size;
481 }
482
483 /* Pineview has different values for various configs */
484 static const struct intel_watermark_params pineview_display_wm = {
485 .fifo_size = PINEVIEW_DISPLAY_FIFO,
486 .max_wm = PINEVIEW_MAX_WM,
487 .default_wm = PINEVIEW_DFT_WM,
488 .guard_size = PINEVIEW_GUARD_WM,
489 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
490 };
491 static const struct intel_watermark_params pineview_display_hplloff_wm = {
492 .fifo_size = PINEVIEW_DISPLAY_FIFO,
493 .max_wm = PINEVIEW_MAX_WM,
494 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
495 .guard_size = PINEVIEW_GUARD_WM,
496 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
497 };
498 static const struct intel_watermark_params pineview_cursor_wm = {
499 .fifo_size = PINEVIEW_CURSOR_FIFO,
500 .max_wm = PINEVIEW_CURSOR_MAX_WM,
501 .default_wm = PINEVIEW_CURSOR_DFT_WM,
502 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
503 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
504 };
505 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
506 .fifo_size = PINEVIEW_CURSOR_FIFO,
507 .max_wm = PINEVIEW_CURSOR_MAX_WM,
508 .default_wm = PINEVIEW_CURSOR_DFT_WM,
509 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
510 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
511 };
512 static const struct intel_watermark_params g4x_wm_info = {
513 .fifo_size = G4X_FIFO_SIZE,
514 .max_wm = G4X_MAX_WM,
515 .default_wm = G4X_MAX_WM,
516 .guard_size = 2,
517 .cacheline_size = G4X_FIFO_LINE_SIZE,
518 };
519 static const struct intel_watermark_params g4x_cursor_wm_info = {
520 .fifo_size = I965_CURSOR_FIFO,
521 .max_wm = I965_CURSOR_MAX_WM,
522 .default_wm = I965_CURSOR_DFT_WM,
523 .guard_size = 2,
524 .cacheline_size = G4X_FIFO_LINE_SIZE,
525 };
526 static const struct intel_watermark_params valleyview_wm_info = {
527 .fifo_size = VALLEYVIEW_FIFO_SIZE,
528 .max_wm = VALLEYVIEW_MAX_WM,
529 .default_wm = VALLEYVIEW_MAX_WM,
530 .guard_size = 2,
531 .cacheline_size = G4X_FIFO_LINE_SIZE,
532 };
533 static const struct intel_watermark_params valleyview_cursor_wm_info = {
534 .fifo_size = I965_CURSOR_FIFO,
535 .max_wm = VALLEYVIEW_CURSOR_MAX_WM,
536 .default_wm = I965_CURSOR_DFT_WM,
537 .guard_size = 2,
538 .cacheline_size = G4X_FIFO_LINE_SIZE,
539 };
540 static const struct intel_watermark_params i965_cursor_wm_info = {
541 .fifo_size = I965_CURSOR_FIFO,
542 .max_wm = I965_CURSOR_MAX_WM,
543 .default_wm = I965_CURSOR_DFT_WM,
544 .guard_size = 2,
545 .cacheline_size = I915_FIFO_LINE_SIZE,
546 };
547 static const struct intel_watermark_params i945_wm_info = {
548 .fifo_size = I945_FIFO_SIZE,
549 .max_wm = I915_MAX_WM,
550 .default_wm = 1,
551 .guard_size = 2,
552 .cacheline_size = I915_FIFO_LINE_SIZE,
553 };
554 static const struct intel_watermark_params i915_wm_info = {
555 .fifo_size = I915_FIFO_SIZE,
556 .max_wm = I915_MAX_WM,
557 .default_wm = 1,
558 .guard_size = 2,
559 .cacheline_size = I915_FIFO_LINE_SIZE,
560 };
561 static const struct intel_watermark_params i830_a_wm_info = {
562 .fifo_size = I855GM_FIFO_SIZE,
563 .max_wm = I915_MAX_WM,
564 .default_wm = 1,
565 .guard_size = 2,
566 .cacheline_size = I830_FIFO_LINE_SIZE,
567 };
568 static const struct intel_watermark_params i830_bc_wm_info = {
569 .fifo_size = I855GM_FIFO_SIZE,
570 .max_wm = I915_MAX_WM/2,
571 .default_wm = 1,
572 .guard_size = 2,
573 .cacheline_size = I830_FIFO_LINE_SIZE,
574 };
575 static const struct intel_watermark_params i845_wm_info = {
576 .fifo_size = I830_FIFO_SIZE,
577 .max_wm = I915_MAX_WM,
578 .default_wm = 1,
579 .guard_size = 2,
580 .cacheline_size = I830_FIFO_LINE_SIZE,
581 };
582
583 /**
584 * intel_calculate_wm - calculate watermark level
585 * @clock_in_khz: pixel clock
586 * @wm: chip FIFO params
587 * @pixel_size: display pixel size
588 * @latency_ns: memory latency for the platform
589 *
590 * Calculate the watermark level (the level at which the display plane will
591 * start fetching from memory again). Each chip has a different display
592 * FIFO size and allocation, so the caller needs to figure that out and pass
593 * in the correct intel_watermark_params structure.
594 *
595 * As the pixel clock runs, the FIFO will be drained at a rate that depends
596 * on the pixel size. When it reaches the watermark level, it'll start
597 * fetching FIFO line sized based chunks from memory until the FIFO fills
598 * past the watermark point. If the FIFO drains completely, a FIFO underrun
599 * will occur, and a display engine hang could result.
600 */
601 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
602 const struct intel_watermark_params *wm,
603 int fifo_size,
604 int pixel_size,
605 unsigned long latency_ns)
606 {
607 long entries_required, wm_size;
608
609 /*
610 * Note: we need to make sure we don't overflow for various clock &
611 * latency values.
612 * clocks go from a few thousand to several hundred thousand.
613 * latency is usually a few thousand
614 */
615 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
616 1000;
617 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
618
619 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
620
621 wm_size = fifo_size - (entries_required + wm->guard_size);
622
623 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
624
625 /* Don't promote wm_size to unsigned... */
626 if (wm_size > (long)wm->max_wm)
627 wm_size = wm->max_wm;
628 if (wm_size <= 0)
629 wm_size = wm->default_wm;
630
631 /*
632 * Bspec seems to indicate that the value shouldn't be lower than
633 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
634 * Lets go for 8 which is the burst size since certain platforms
635 * already use a hardcoded 8 (which is what the spec says should be
636 * done).
637 */
638 if (wm_size <= 8)
639 wm_size = 8;
640
641 return wm_size;
642 }
643
644 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
645 {
646 struct drm_crtc *crtc, *enabled = NULL;
647
648 for_each_crtc(dev, crtc) {
649 if (intel_crtc_active(crtc)) {
650 if (enabled)
651 return NULL;
652 enabled = crtc;
653 }
654 }
655
656 return enabled;
657 }
658
659 static void pineview_update_wm(struct drm_crtc *unused_crtc)
660 {
661 struct drm_device *dev = unused_crtc->dev;
662 struct drm_i915_private *dev_priv = dev->dev_private;
663 struct drm_crtc *crtc;
664 const struct cxsr_latency *latency;
665 u32 reg;
666 unsigned long wm;
667
668 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
669 dev_priv->fsb_freq, dev_priv->mem_freq);
670 if (!latency) {
671 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
672 intel_set_memory_cxsr(dev_priv, false);
673 return;
674 }
675
676 crtc = single_enabled_crtc(dev);
677 if (crtc) {
678 const struct drm_display_mode *adjusted_mode;
679 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
680 int clock;
681
682 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
683 clock = adjusted_mode->crtc_clock;
684
685 /* Display SR */
686 wm = intel_calculate_wm(clock, &pineview_display_wm,
687 pineview_display_wm.fifo_size,
688 pixel_size, latency->display_sr);
689 reg = I915_READ(DSPFW1);
690 reg &= ~DSPFW_SR_MASK;
691 reg |= FW_WM(wm, SR);
692 I915_WRITE(DSPFW1, reg);
693 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
694
695 /* cursor SR */
696 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
697 pineview_display_wm.fifo_size,
698 pixel_size, latency->cursor_sr);
699 reg = I915_READ(DSPFW3);
700 reg &= ~DSPFW_CURSOR_SR_MASK;
701 reg |= FW_WM(wm, CURSOR_SR);
702 I915_WRITE(DSPFW3, reg);
703
704 /* Display HPLL off SR */
705 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
706 pineview_display_hplloff_wm.fifo_size,
707 pixel_size, latency->display_hpll_disable);
708 reg = I915_READ(DSPFW3);
709 reg &= ~DSPFW_HPLL_SR_MASK;
710 reg |= FW_WM(wm, HPLL_SR);
711 I915_WRITE(DSPFW3, reg);
712
713 /* cursor HPLL off SR */
714 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
715 pineview_display_hplloff_wm.fifo_size,
716 pixel_size, latency->cursor_hpll_disable);
717 reg = I915_READ(DSPFW3);
718 reg &= ~DSPFW_HPLL_CURSOR_MASK;
719 reg |= FW_WM(wm, HPLL_CURSOR);
720 I915_WRITE(DSPFW3, reg);
721 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
722
723 intel_set_memory_cxsr(dev_priv, true);
724 } else {
725 intel_set_memory_cxsr(dev_priv, false);
726 }
727 }
728
729 static bool g4x_compute_wm0(struct drm_device *dev,
730 int plane,
731 const struct intel_watermark_params *display,
732 int display_latency_ns,
733 const struct intel_watermark_params *cursor,
734 int cursor_latency_ns,
735 int *plane_wm,
736 int *cursor_wm)
737 {
738 struct drm_crtc *crtc;
739 const struct drm_display_mode *adjusted_mode;
740 int htotal, hdisplay, clock, pixel_size;
741 int line_time_us, line_count;
742 int entries, tlb_miss;
743
744 crtc = intel_get_crtc_for_plane(dev, plane);
745 if (!intel_crtc_active(crtc)) {
746 *cursor_wm = cursor->guard_size;
747 *plane_wm = display->guard_size;
748 return false;
749 }
750
751 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
752 clock = adjusted_mode->crtc_clock;
753 htotal = adjusted_mode->crtc_htotal;
754 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
755 pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
756
757 /* Use the small buffer method to calculate plane watermark */
758 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
759 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
760 if (tlb_miss > 0)
761 entries += tlb_miss;
762 entries = DIV_ROUND_UP(entries, display->cacheline_size);
763 *plane_wm = entries + display->guard_size;
764 if (*plane_wm > (int)display->max_wm)
765 *plane_wm = display->max_wm;
766
767 /* Use the large buffer method to calculate cursor watermark */
768 line_time_us = max(htotal * 1000 / clock, 1);
769 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
770 entries = line_count * crtc->cursor->state->crtc_w * pixel_size;
771 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
772 if (tlb_miss > 0)
773 entries += tlb_miss;
774 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
775 *cursor_wm = entries + cursor->guard_size;
776 if (*cursor_wm > (int)cursor->max_wm)
777 *cursor_wm = (int)cursor->max_wm;
778
779 return true;
780 }
781
782 /*
783 * Check the wm result.
784 *
785 * If any calculated watermark values is larger than the maximum value that
786 * can be programmed into the associated watermark register, that watermark
787 * must be disabled.
788 */
789 static bool g4x_check_srwm(struct drm_device *dev,
790 int display_wm, int cursor_wm,
791 const struct intel_watermark_params *display,
792 const struct intel_watermark_params *cursor)
793 {
794 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
795 display_wm, cursor_wm);
796
797 if (display_wm > display->max_wm) {
798 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
799 display_wm, display->max_wm);
800 return false;
801 }
802
803 if (cursor_wm > cursor->max_wm) {
804 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
805 cursor_wm, cursor->max_wm);
806 return false;
807 }
808
809 if (!(display_wm || cursor_wm)) {
810 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
811 return false;
812 }
813
814 return true;
815 }
816
817 static bool g4x_compute_srwm(struct drm_device *dev,
818 int plane,
819 int latency_ns,
820 const struct intel_watermark_params *display,
821 const struct intel_watermark_params *cursor,
822 int *display_wm, int *cursor_wm)
823 {
824 struct drm_crtc *crtc;
825 const struct drm_display_mode *adjusted_mode;
826 int hdisplay, htotal, pixel_size, clock;
827 unsigned long line_time_us;
828 int line_count, line_size;
829 int small, large;
830 int entries;
831
832 if (!latency_ns) {
833 *display_wm = *cursor_wm = 0;
834 return false;
835 }
836
837 crtc = intel_get_crtc_for_plane(dev, plane);
838 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
839 clock = adjusted_mode->crtc_clock;
840 htotal = adjusted_mode->crtc_htotal;
841 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
842 pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
843
844 line_time_us = max(htotal * 1000 / clock, 1);
845 line_count = (latency_ns / line_time_us + 1000) / 1000;
846 line_size = hdisplay * pixel_size;
847
848 /* Use the minimum of the small and large buffer method for primary */
849 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
850 large = line_count * line_size;
851
852 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
853 *display_wm = entries + display->guard_size;
854
855 /* calculate the self-refresh watermark for display cursor */
856 entries = line_count * pixel_size * crtc->cursor->state->crtc_w;
857 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
858 *cursor_wm = entries + cursor->guard_size;
859
860 return g4x_check_srwm(dev,
861 *display_wm, *cursor_wm,
862 display, cursor);
863 }
864
865 #define FW_WM_VLV(value, plane) \
866 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
867
868 static void vlv_write_wm_values(struct intel_crtc *crtc,
869 const struct vlv_wm_values *wm)
870 {
871 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
872 enum pipe pipe = crtc->pipe;
873
874 I915_WRITE(VLV_DDL(pipe),
875 (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
876 (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
877 (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
878 (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
879
880 I915_WRITE(DSPFW1,
881 FW_WM(wm->sr.plane, SR) |
882 FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
883 FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
884 FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
885 I915_WRITE(DSPFW2,
886 FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
887 FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
888 FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
889 I915_WRITE(DSPFW3,
890 FW_WM(wm->sr.cursor, CURSOR_SR));
891
892 if (IS_CHERRYVIEW(dev_priv)) {
893 I915_WRITE(DSPFW7_CHV,
894 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
895 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
896 I915_WRITE(DSPFW8_CHV,
897 FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
898 FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
899 I915_WRITE(DSPFW9_CHV,
900 FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
901 FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
902 I915_WRITE(DSPHOWM,
903 FW_WM(wm->sr.plane >> 9, SR_HI) |
904 FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
905 FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
906 FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
907 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
908 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
909 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
910 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
911 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
912 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
913 } else {
914 I915_WRITE(DSPFW7,
915 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
916 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
917 I915_WRITE(DSPHOWM,
918 FW_WM(wm->sr.plane >> 9, SR_HI) |
919 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
920 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
921 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
922 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
923 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
924 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
925 }
926
927 POSTING_READ(DSPFW1);
928
929 dev_priv->wm.vlv = *wm;
930 }
931
932 #undef FW_WM_VLV
933
934 static uint8_t vlv_compute_drain_latency(struct drm_crtc *crtc,
935 struct drm_plane *plane)
936 {
937 struct drm_device *dev = crtc->dev;
938 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
939 int entries, prec_mult, drain_latency, pixel_size;
940 int clock = intel_crtc->config->base.adjusted_mode.crtc_clock;
941 const int high_precision = IS_CHERRYVIEW(dev) ? 16 : 64;
942
943 /*
944 * FIXME the plane might have an fb
945 * but be invisible (eg. due to clipping)
946 */
947 if (!intel_crtc->active || !plane->state->fb)
948 return 0;
949
950 if (WARN(clock == 0, "Pixel clock is zero!\n"))
951 return 0;
952
953 pixel_size = drm_format_plane_cpp(plane->state->fb->pixel_format, 0);
954
955 if (WARN(pixel_size == 0, "Pixel size is zero!\n"))
956 return 0;
957
958 entries = DIV_ROUND_UP(clock, 1000) * pixel_size;
959
960 prec_mult = high_precision;
961 drain_latency = 64 * prec_mult * 4 / entries;
962
963 if (drain_latency > DRAIN_LATENCY_MASK) {
964 prec_mult /= 2;
965 drain_latency = 64 * prec_mult * 4 / entries;
966 }
967
968 if (drain_latency > DRAIN_LATENCY_MASK)
969 drain_latency = DRAIN_LATENCY_MASK;
970
971 return drain_latency | (prec_mult == high_precision ?
972 DDL_PRECISION_HIGH : DDL_PRECISION_LOW);
973 }
974
975 static int vlv_compute_wm(struct intel_crtc *crtc,
976 struct intel_plane *plane,
977 int fifo_size)
978 {
979 int clock, entries, pixel_size;
980
981 /*
982 * FIXME the plane might have an fb
983 * but be invisible (eg. due to clipping)
984 */
985 if (!crtc->active || !plane->base.state->fb)
986 return 0;
987
988 pixel_size = drm_format_plane_cpp(plane->base.state->fb->pixel_format, 0);
989 clock = crtc->config->base.adjusted_mode.crtc_clock;
990
991 entries = DIV_ROUND_UP(clock, 1000) * pixel_size;
992
993 /*
994 * Set up the watermark such that we don't start issuing memory
995 * requests until we are within PND's max deadline value (256us).
996 * Idea being to be idle as long as possible while still taking
997 * advatange of PND's deadline scheduling. The limit of 8
998 * cachelines (used when the FIFO will anyway drain in less time
999 * than 256us) should match what we would be done if trickle
1000 * feed were enabled.
1001 */
1002 return fifo_size - clamp(DIV_ROUND_UP(256 * entries, 64), 0, fifo_size - 8);
1003 }
1004
1005 static bool vlv_compute_sr_wm(struct drm_device *dev,
1006 struct vlv_wm_values *wm)
1007 {
1008 struct drm_i915_private *dev_priv = to_i915(dev);
1009 struct drm_crtc *crtc;
1010 enum pipe pipe = INVALID_PIPE;
1011 int num_planes = 0;
1012 int fifo_size = 0;
1013 struct intel_plane *plane;
1014
1015 wm->sr.cursor = wm->sr.plane = 0;
1016
1017 crtc = single_enabled_crtc(dev);
1018 /* maxfifo not supported on pipe C */
1019 if (crtc && to_intel_crtc(crtc)->pipe != PIPE_C) {
1020 pipe = to_intel_crtc(crtc)->pipe;
1021 num_planes = !!wm->pipe[pipe].primary +
1022 !!wm->pipe[pipe].sprite[0] +
1023 !!wm->pipe[pipe].sprite[1];
1024 fifo_size = INTEL_INFO(dev_priv)->num_pipes * 512 - 1;
1025 }
1026
1027 if (fifo_size == 0 || num_planes > 1)
1028 return false;
1029
1030 wm->sr.cursor = vlv_compute_wm(to_intel_crtc(crtc),
1031 to_intel_plane(crtc->cursor), 0x3f);
1032
1033 list_for_each_entry(plane, &dev->mode_config.plane_list, base.head) {
1034 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1035 continue;
1036
1037 if (plane->pipe != pipe)
1038 continue;
1039
1040 wm->sr.plane = vlv_compute_wm(to_intel_crtc(crtc),
1041 plane, fifo_size);
1042 if (wm->sr.plane != 0)
1043 break;
1044 }
1045
1046 return true;
1047 }
1048
1049 static void valleyview_update_wm(struct drm_crtc *crtc)
1050 {
1051 struct drm_device *dev = crtc->dev;
1052 struct drm_i915_private *dev_priv = dev->dev_private;
1053 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1054 enum pipe pipe = intel_crtc->pipe;
1055 bool cxsr_enabled;
1056 struct vlv_wm_values wm = dev_priv->wm.vlv;
1057
1058 wm.ddl[pipe].primary = vlv_compute_drain_latency(crtc, crtc->primary);
1059 wm.pipe[pipe].primary = vlv_compute_wm(intel_crtc,
1060 to_intel_plane(crtc->primary),
1061 vlv_get_fifo_size(dev, pipe, 0));
1062
1063 wm.ddl[pipe].cursor = vlv_compute_drain_latency(crtc, crtc->cursor);
1064 wm.pipe[pipe].cursor = vlv_compute_wm(intel_crtc,
1065 to_intel_plane(crtc->cursor),
1066 0x3f);
1067
1068 cxsr_enabled = vlv_compute_sr_wm(dev, &wm);
1069
1070 if (memcmp(&wm, &dev_priv->wm.vlv, sizeof(wm)) == 0)
1071 return;
1072
1073 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1074 "SR: plane=%d, cursor=%d\n", pipe_name(pipe),
1075 wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1076 wm.sr.plane, wm.sr.cursor);
1077
1078 /*
1079 * FIXME DDR DVFS introduces massive memory latencies which
1080 * are not known to system agent so any deadline specified
1081 * by the display may not be respected. To support DDR DVFS
1082 * the watermark code needs to be rewritten to essentially
1083 * bypass deadline mechanism and rely solely on the
1084 * watermarks. For now disable DDR DVFS.
1085 */
1086 if (IS_CHERRYVIEW(dev_priv))
1087 chv_set_memory_dvfs(dev_priv, false);
1088
1089 if (!cxsr_enabled)
1090 intel_set_memory_cxsr(dev_priv, false);
1091
1092 vlv_write_wm_values(intel_crtc, &wm);
1093
1094 if (cxsr_enabled)
1095 intel_set_memory_cxsr(dev_priv, true);
1096 }
1097
1098 static void valleyview_update_sprite_wm(struct drm_plane *plane,
1099 struct drm_crtc *crtc,
1100 uint32_t sprite_width,
1101 uint32_t sprite_height,
1102 int pixel_size,
1103 bool enabled, bool scaled)
1104 {
1105 struct drm_device *dev = crtc->dev;
1106 struct drm_i915_private *dev_priv = dev->dev_private;
1107 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1108 enum pipe pipe = intel_crtc->pipe;
1109 int sprite = to_intel_plane(plane)->plane;
1110 bool cxsr_enabled;
1111 struct vlv_wm_values wm = dev_priv->wm.vlv;
1112
1113 if (enabled) {
1114 wm.ddl[pipe].sprite[sprite] =
1115 vlv_compute_drain_latency(crtc, plane);
1116
1117 wm.pipe[pipe].sprite[sprite] =
1118 vlv_compute_wm(intel_crtc,
1119 to_intel_plane(plane),
1120 vlv_get_fifo_size(dev, pipe, sprite+1));
1121 } else {
1122 wm.ddl[pipe].sprite[sprite] = 0;
1123 wm.pipe[pipe].sprite[sprite] = 0;
1124 }
1125
1126 cxsr_enabled = vlv_compute_sr_wm(dev, &wm);
1127
1128 if (memcmp(&wm, &dev_priv->wm.vlv, sizeof(wm)) == 0)
1129 return;
1130
1131 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: sprite %c=%d, "
1132 "SR: plane=%d, cursor=%d\n", pipe_name(pipe),
1133 sprite_name(pipe, sprite),
1134 wm.pipe[pipe].sprite[sprite],
1135 wm.sr.plane, wm.sr.cursor);
1136
1137 if (!cxsr_enabled)
1138 intel_set_memory_cxsr(dev_priv, false);
1139
1140 vlv_write_wm_values(intel_crtc, &wm);
1141
1142 if (cxsr_enabled)
1143 intel_set_memory_cxsr(dev_priv, true);
1144 }
1145
1146 #define single_plane_enabled(mask) is_power_of_2(mask)
1147
1148 static void g4x_update_wm(struct drm_crtc *crtc)
1149 {
1150 struct drm_device *dev = crtc->dev;
1151 static const int sr_latency_ns = 12000;
1152 struct drm_i915_private *dev_priv = dev->dev_private;
1153 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1154 int plane_sr, cursor_sr;
1155 unsigned int enabled = 0;
1156 bool cxsr_enabled;
1157
1158 if (g4x_compute_wm0(dev, PIPE_A,
1159 &g4x_wm_info, pessimal_latency_ns,
1160 &g4x_cursor_wm_info, pessimal_latency_ns,
1161 &planea_wm, &cursora_wm))
1162 enabled |= 1 << PIPE_A;
1163
1164 if (g4x_compute_wm0(dev, PIPE_B,
1165 &g4x_wm_info, pessimal_latency_ns,
1166 &g4x_cursor_wm_info, pessimal_latency_ns,
1167 &planeb_wm, &cursorb_wm))
1168 enabled |= 1 << PIPE_B;
1169
1170 if (single_plane_enabled(enabled) &&
1171 g4x_compute_srwm(dev, ffs(enabled) - 1,
1172 sr_latency_ns,
1173 &g4x_wm_info,
1174 &g4x_cursor_wm_info,
1175 &plane_sr, &cursor_sr)) {
1176 cxsr_enabled = true;
1177 } else {
1178 cxsr_enabled = false;
1179 intel_set_memory_cxsr(dev_priv, false);
1180 plane_sr = cursor_sr = 0;
1181 }
1182
1183 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1184 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1185 planea_wm, cursora_wm,
1186 planeb_wm, cursorb_wm,
1187 plane_sr, cursor_sr);
1188
1189 I915_WRITE(DSPFW1,
1190 FW_WM(plane_sr, SR) |
1191 FW_WM(cursorb_wm, CURSORB) |
1192 FW_WM(planeb_wm, PLANEB) |
1193 FW_WM(planea_wm, PLANEA));
1194 I915_WRITE(DSPFW2,
1195 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1196 FW_WM(cursora_wm, CURSORA));
1197 /* HPLL off in SR has some issues on G4x... disable it */
1198 I915_WRITE(DSPFW3,
1199 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1200 FW_WM(cursor_sr, CURSOR_SR));
1201
1202 if (cxsr_enabled)
1203 intel_set_memory_cxsr(dev_priv, true);
1204 }
1205
1206 static void i965_update_wm(struct drm_crtc *unused_crtc)
1207 {
1208 struct drm_device *dev = unused_crtc->dev;
1209 struct drm_i915_private *dev_priv = dev->dev_private;
1210 struct drm_crtc *crtc;
1211 int srwm = 1;
1212 int cursor_sr = 16;
1213 bool cxsr_enabled;
1214
1215 /* Calc sr entries for one plane configs */
1216 crtc = single_enabled_crtc(dev);
1217 if (crtc) {
1218 /* self-refresh has much higher latency */
1219 static const int sr_latency_ns = 12000;
1220 const struct drm_display_mode *adjusted_mode =
1221 &to_intel_crtc(crtc)->config->base.adjusted_mode;
1222 int clock = adjusted_mode->crtc_clock;
1223 int htotal = adjusted_mode->crtc_htotal;
1224 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
1225 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
1226 unsigned long line_time_us;
1227 int entries;
1228
1229 line_time_us = max(htotal * 1000 / clock, 1);
1230
1231 /* Use ns/us then divide to preserve precision */
1232 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1233 pixel_size * hdisplay;
1234 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1235 srwm = I965_FIFO_SIZE - entries;
1236 if (srwm < 0)
1237 srwm = 1;
1238 srwm &= 0x1ff;
1239 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1240 entries, srwm);
1241
1242 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1243 pixel_size * crtc->cursor->state->crtc_w;
1244 entries = DIV_ROUND_UP(entries,
1245 i965_cursor_wm_info.cacheline_size);
1246 cursor_sr = i965_cursor_wm_info.fifo_size -
1247 (entries + i965_cursor_wm_info.guard_size);
1248
1249 if (cursor_sr > i965_cursor_wm_info.max_wm)
1250 cursor_sr = i965_cursor_wm_info.max_wm;
1251
1252 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1253 "cursor %d\n", srwm, cursor_sr);
1254
1255 cxsr_enabled = true;
1256 } else {
1257 cxsr_enabled = false;
1258 /* Turn off self refresh if both pipes are enabled */
1259 intel_set_memory_cxsr(dev_priv, false);
1260 }
1261
1262 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1263 srwm);
1264
1265 /* 965 has limitations... */
1266 I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1267 FW_WM(8, CURSORB) |
1268 FW_WM(8, PLANEB) |
1269 FW_WM(8, PLANEA));
1270 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1271 FW_WM(8, PLANEC_OLD));
1272 /* update cursor SR watermark */
1273 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
1274
1275 if (cxsr_enabled)
1276 intel_set_memory_cxsr(dev_priv, true);
1277 }
1278
1279 #undef FW_WM
1280
1281 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1282 {
1283 struct drm_device *dev = unused_crtc->dev;
1284 struct drm_i915_private *dev_priv = dev->dev_private;
1285 const struct intel_watermark_params *wm_info;
1286 uint32_t fwater_lo;
1287 uint32_t fwater_hi;
1288 int cwm, srwm = 1;
1289 int fifo_size;
1290 int planea_wm, planeb_wm;
1291 struct drm_crtc *crtc, *enabled = NULL;
1292
1293 if (IS_I945GM(dev))
1294 wm_info = &i945_wm_info;
1295 else if (!IS_GEN2(dev))
1296 wm_info = &i915_wm_info;
1297 else
1298 wm_info = &i830_a_wm_info;
1299
1300 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1301 crtc = intel_get_crtc_for_plane(dev, 0);
1302 if (intel_crtc_active(crtc)) {
1303 const struct drm_display_mode *adjusted_mode;
1304 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
1305 if (IS_GEN2(dev))
1306 cpp = 4;
1307
1308 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1309 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1310 wm_info, fifo_size, cpp,
1311 pessimal_latency_ns);
1312 enabled = crtc;
1313 } else {
1314 planea_wm = fifo_size - wm_info->guard_size;
1315 if (planea_wm > (long)wm_info->max_wm)
1316 planea_wm = wm_info->max_wm;
1317 }
1318
1319 if (IS_GEN2(dev))
1320 wm_info = &i830_bc_wm_info;
1321
1322 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1323 crtc = intel_get_crtc_for_plane(dev, 1);
1324 if (intel_crtc_active(crtc)) {
1325 const struct drm_display_mode *adjusted_mode;
1326 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
1327 if (IS_GEN2(dev))
1328 cpp = 4;
1329
1330 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1331 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1332 wm_info, fifo_size, cpp,
1333 pessimal_latency_ns);
1334 if (enabled == NULL)
1335 enabled = crtc;
1336 else
1337 enabled = NULL;
1338 } else {
1339 planeb_wm = fifo_size - wm_info->guard_size;
1340 if (planeb_wm > (long)wm_info->max_wm)
1341 planeb_wm = wm_info->max_wm;
1342 }
1343
1344 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1345
1346 if (IS_I915GM(dev) && enabled) {
1347 struct drm_i915_gem_object *obj;
1348
1349 obj = intel_fb_obj(enabled->primary->state->fb);
1350
1351 /* self-refresh seems busted with untiled */
1352 if (obj->tiling_mode == I915_TILING_NONE)
1353 enabled = NULL;
1354 }
1355
1356 /*
1357 * Overlay gets an aggressive default since video jitter is bad.
1358 */
1359 cwm = 2;
1360
1361 /* Play safe and disable self-refresh before adjusting watermarks. */
1362 intel_set_memory_cxsr(dev_priv, false);
1363
1364 /* Calc sr entries for one plane configs */
1365 if (HAS_FW_BLC(dev) && enabled) {
1366 /* self-refresh has much higher latency */
1367 static const int sr_latency_ns = 6000;
1368 const struct drm_display_mode *adjusted_mode =
1369 &to_intel_crtc(enabled)->config->base.adjusted_mode;
1370 int clock = adjusted_mode->crtc_clock;
1371 int htotal = adjusted_mode->crtc_htotal;
1372 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
1373 int pixel_size = enabled->primary->state->fb->bits_per_pixel / 8;
1374 unsigned long line_time_us;
1375 int entries;
1376
1377 line_time_us = max(htotal * 1000 / clock, 1);
1378
1379 /* Use ns/us then divide to preserve precision */
1380 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1381 pixel_size * hdisplay;
1382 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1383 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1384 srwm = wm_info->fifo_size - entries;
1385 if (srwm < 0)
1386 srwm = 1;
1387
1388 if (IS_I945G(dev) || IS_I945GM(dev))
1389 I915_WRITE(FW_BLC_SELF,
1390 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1391 else if (IS_I915GM(dev))
1392 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1393 }
1394
1395 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1396 planea_wm, planeb_wm, cwm, srwm);
1397
1398 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1399 fwater_hi = (cwm & 0x1f);
1400
1401 /* Set request length to 8 cachelines per fetch */
1402 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1403 fwater_hi = fwater_hi | (1 << 8);
1404
1405 I915_WRITE(FW_BLC, fwater_lo);
1406 I915_WRITE(FW_BLC2, fwater_hi);
1407
1408 if (enabled)
1409 intel_set_memory_cxsr(dev_priv, true);
1410 }
1411
1412 static void i845_update_wm(struct drm_crtc *unused_crtc)
1413 {
1414 struct drm_device *dev = unused_crtc->dev;
1415 struct drm_i915_private *dev_priv = dev->dev_private;
1416 struct drm_crtc *crtc;
1417 const struct drm_display_mode *adjusted_mode;
1418 uint32_t fwater_lo;
1419 int planea_wm;
1420
1421 crtc = single_enabled_crtc(dev);
1422 if (crtc == NULL)
1423 return;
1424
1425 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1426 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1427 &i845_wm_info,
1428 dev_priv->display.get_fifo_size(dev, 0),
1429 4, pessimal_latency_ns);
1430 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1431 fwater_lo |= (3<<8) | planea_wm;
1432
1433 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1434
1435 I915_WRITE(FW_BLC, fwater_lo);
1436 }
1437
1438 static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
1439 struct drm_crtc *crtc)
1440 {
1441 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1442 uint32_t pixel_rate;
1443
1444 pixel_rate = intel_crtc->config->base.adjusted_mode.crtc_clock;
1445
1446 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1447 * adjust the pixel_rate here. */
1448
1449 if (intel_crtc->config->pch_pfit.enabled) {
1450 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1451 uint32_t pfit_size = intel_crtc->config->pch_pfit.size;
1452
1453 pipe_w = intel_crtc->config->pipe_src_w;
1454 pipe_h = intel_crtc->config->pipe_src_h;
1455 pfit_w = (pfit_size >> 16) & 0xFFFF;
1456 pfit_h = pfit_size & 0xFFFF;
1457 if (pipe_w < pfit_w)
1458 pipe_w = pfit_w;
1459 if (pipe_h < pfit_h)
1460 pipe_h = pfit_h;
1461
1462 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1463 pfit_w * pfit_h);
1464 }
1465
1466 return pixel_rate;
1467 }
1468
1469 /* latency must be in 0.1us units. */
1470 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
1471 uint32_t latency)
1472 {
1473 uint64_t ret;
1474
1475 if (WARN(latency == 0, "Latency value missing\n"))
1476 return UINT_MAX;
1477
1478 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1479 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1480
1481 return ret;
1482 }
1483
1484 /* latency must be in 0.1us units. */
1485 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1486 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1487 uint32_t latency)
1488 {
1489 uint32_t ret;
1490
1491 if (WARN(latency == 0, "Latency value missing\n"))
1492 return UINT_MAX;
1493
1494 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1495 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1496 ret = DIV_ROUND_UP(ret, 64) + 2;
1497 return ret;
1498 }
1499
1500 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1501 uint8_t bytes_per_pixel)
1502 {
1503 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1504 }
1505
1506 struct skl_pipe_wm_parameters {
1507 bool active;
1508 uint32_t pipe_htotal;
1509 uint32_t pixel_rate; /* in KHz */
1510 struct intel_plane_wm_parameters plane[I915_MAX_PLANES];
1511 struct intel_plane_wm_parameters cursor;
1512 };
1513
1514 struct ilk_pipe_wm_parameters {
1515 bool active;
1516 uint32_t pipe_htotal;
1517 uint32_t pixel_rate;
1518 struct intel_plane_wm_parameters pri;
1519 struct intel_plane_wm_parameters spr;
1520 struct intel_plane_wm_parameters cur;
1521 };
1522
1523 struct ilk_wm_maximums {
1524 uint16_t pri;
1525 uint16_t spr;
1526 uint16_t cur;
1527 uint16_t fbc;
1528 };
1529
1530 /* used in computing the new watermarks state */
1531 struct intel_wm_config {
1532 unsigned int num_pipes_active;
1533 bool sprites_enabled;
1534 bool sprites_scaled;
1535 };
1536
1537 /*
1538 * For both WM_PIPE and WM_LP.
1539 * mem_value must be in 0.1us units.
1540 */
1541 static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params,
1542 uint32_t mem_value,
1543 bool is_lp)
1544 {
1545 uint32_t method1, method2;
1546
1547 if (!params->active || !params->pri.enabled)
1548 return 0;
1549
1550 method1 = ilk_wm_method1(params->pixel_rate,
1551 params->pri.bytes_per_pixel,
1552 mem_value);
1553
1554 if (!is_lp)
1555 return method1;
1556
1557 method2 = ilk_wm_method2(params->pixel_rate,
1558 params->pipe_htotal,
1559 params->pri.horiz_pixels,
1560 params->pri.bytes_per_pixel,
1561 mem_value);
1562
1563 return min(method1, method2);
1564 }
1565
1566 /*
1567 * For both WM_PIPE and WM_LP.
1568 * mem_value must be in 0.1us units.
1569 */
1570 static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params,
1571 uint32_t mem_value)
1572 {
1573 uint32_t method1, method2;
1574
1575 if (!params->active || !params->spr.enabled)
1576 return 0;
1577
1578 method1 = ilk_wm_method1(params->pixel_rate,
1579 params->spr.bytes_per_pixel,
1580 mem_value);
1581 method2 = ilk_wm_method2(params->pixel_rate,
1582 params->pipe_htotal,
1583 params->spr.horiz_pixels,
1584 params->spr.bytes_per_pixel,
1585 mem_value);
1586 return min(method1, method2);
1587 }
1588
1589 /*
1590 * For both WM_PIPE and WM_LP.
1591 * mem_value must be in 0.1us units.
1592 */
1593 static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params,
1594 uint32_t mem_value)
1595 {
1596 if (!params->active || !params->cur.enabled)
1597 return 0;
1598
1599 return ilk_wm_method2(params->pixel_rate,
1600 params->pipe_htotal,
1601 params->cur.horiz_pixels,
1602 params->cur.bytes_per_pixel,
1603 mem_value);
1604 }
1605
1606 /* Only for WM_LP. */
1607 static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params,
1608 uint32_t pri_val)
1609 {
1610 if (!params->active || !params->pri.enabled)
1611 return 0;
1612
1613 return ilk_wm_fbc(pri_val,
1614 params->pri.horiz_pixels,
1615 params->pri.bytes_per_pixel);
1616 }
1617
1618 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1619 {
1620 if (INTEL_INFO(dev)->gen >= 8)
1621 return 3072;
1622 else if (INTEL_INFO(dev)->gen >= 7)
1623 return 768;
1624 else
1625 return 512;
1626 }
1627
1628 static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1629 int level, bool is_sprite)
1630 {
1631 if (INTEL_INFO(dev)->gen >= 8)
1632 /* BDW primary/sprite plane watermarks */
1633 return level == 0 ? 255 : 2047;
1634 else if (INTEL_INFO(dev)->gen >= 7)
1635 /* IVB/HSW primary/sprite plane watermarks */
1636 return level == 0 ? 127 : 1023;
1637 else if (!is_sprite)
1638 /* ILK/SNB primary plane watermarks */
1639 return level == 0 ? 127 : 511;
1640 else
1641 /* ILK/SNB sprite plane watermarks */
1642 return level == 0 ? 63 : 255;
1643 }
1644
1645 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1646 int level)
1647 {
1648 if (INTEL_INFO(dev)->gen >= 7)
1649 return level == 0 ? 63 : 255;
1650 else
1651 return level == 0 ? 31 : 63;
1652 }
1653
1654 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1655 {
1656 if (INTEL_INFO(dev)->gen >= 8)
1657 return 31;
1658 else
1659 return 15;
1660 }
1661
1662 /* Calculate the maximum primary/sprite plane watermark */
1663 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1664 int level,
1665 const struct intel_wm_config *config,
1666 enum intel_ddb_partitioning ddb_partitioning,
1667 bool is_sprite)
1668 {
1669 unsigned int fifo_size = ilk_display_fifo_size(dev);
1670
1671 /* if sprites aren't enabled, sprites get nothing */
1672 if (is_sprite && !config->sprites_enabled)
1673 return 0;
1674
1675 /* HSW allows LP1+ watermarks even with multiple pipes */
1676 if (level == 0 || config->num_pipes_active > 1) {
1677 fifo_size /= INTEL_INFO(dev)->num_pipes;
1678
1679 /*
1680 * For some reason the non self refresh
1681 * FIFO size is only half of the self
1682 * refresh FIFO size on ILK/SNB.
1683 */
1684 if (INTEL_INFO(dev)->gen <= 6)
1685 fifo_size /= 2;
1686 }
1687
1688 if (config->sprites_enabled) {
1689 /* level 0 is always calculated with 1:1 split */
1690 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1691 if (is_sprite)
1692 fifo_size *= 5;
1693 fifo_size /= 6;
1694 } else {
1695 fifo_size /= 2;
1696 }
1697 }
1698
1699 /* clamp to max that the registers can hold */
1700 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
1701 }
1702
1703 /* Calculate the maximum cursor plane watermark */
1704 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
1705 int level,
1706 const struct intel_wm_config *config)
1707 {
1708 /* HSW LP1+ watermarks w/ multiple pipes */
1709 if (level > 0 && config->num_pipes_active > 1)
1710 return 64;
1711
1712 /* otherwise just report max that registers can hold */
1713 return ilk_cursor_wm_reg_max(dev, level);
1714 }
1715
1716 static void ilk_compute_wm_maximums(const struct drm_device *dev,
1717 int level,
1718 const struct intel_wm_config *config,
1719 enum intel_ddb_partitioning ddb_partitioning,
1720 struct ilk_wm_maximums *max)
1721 {
1722 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1723 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1724 max->cur = ilk_cursor_wm_max(dev, level, config);
1725 max->fbc = ilk_fbc_wm_reg_max(dev);
1726 }
1727
1728 static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1729 int level,
1730 struct ilk_wm_maximums *max)
1731 {
1732 max->pri = ilk_plane_wm_reg_max(dev, level, false);
1733 max->spr = ilk_plane_wm_reg_max(dev, level, true);
1734 max->cur = ilk_cursor_wm_reg_max(dev, level);
1735 max->fbc = ilk_fbc_wm_reg_max(dev);
1736 }
1737
1738 static bool ilk_validate_wm_level(int level,
1739 const struct ilk_wm_maximums *max,
1740 struct intel_wm_level *result)
1741 {
1742 bool ret;
1743
1744 /* already determined to be invalid? */
1745 if (!result->enable)
1746 return false;
1747
1748 result->enable = result->pri_val <= max->pri &&
1749 result->spr_val <= max->spr &&
1750 result->cur_val <= max->cur;
1751
1752 ret = result->enable;
1753
1754 /*
1755 * HACK until we can pre-compute everything,
1756 * and thus fail gracefully if LP0 watermarks
1757 * are exceeded...
1758 */
1759 if (level == 0 && !result->enable) {
1760 if (result->pri_val > max->pri)
1761 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1762 level, result->pri_val, max->pri);
1763 if (result->spr_val > max->spr)
1764 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1765 level, result->spr_val, max->spr);
1766 if (result->cur_val > max->cur)
1767 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1768 level, result->cur_val, max->cur);
1769
1770 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
1771 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
1772 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
1773 result->enable = true;
1774 }
1775
1776 return ret;
1777 }
1778
1779 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
1780 int level,
1781 const struct ilk_pipe_wm_parameters *p,
1782 struct intel_wm_level *result)
1783 {
1784 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
1785 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
1786 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
1787
1788 /* WM1+ latency values stored in 0.5us units */
1789 if (level > 0) {
1790 pri_latency *= 5;
1791 spr_latency *= 5;
1792 cur_latency *= 5;
1793 }
1794
1795 result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
1796 result->spr_val = ilk_compute_spr_wm(p, spr_latency);
1797 result->cur_val = ilk_compute_cur_wm(p, cur_latency);
1798 result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
1799 result->enable = true;
1800 }
1801
1802 static uint32_t
1803 hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
1804 {
1805 struct drm_i915_private *dev_priv = dev->dev_private;
1806 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1807 struct drm_display_mode *mode = &intel_crtc->config->base.adjusted_mode;
1808 u32 linetime, ips_linetime;
1809
1810 if (!intel_crtc->active)
1811 return 0;
1812
1813 /* The WM are computed with base on how long it takes to fill a single
1814 * row at the given clock rate, multiplied by 8.
1815 * */
1816 linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
1817 mode->crtc_clock);
1818 ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
1819 dev_priv->display.get_display_clock_speed(dev_priv->dev));
1820
1821 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
1822 PIPE_WM_LINETIME_TIME(linetime);
1823 }
1824
1825 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
1826 {
1827 struct drm_i915_private *dev_priv = dev->dev_private;
1828
1829 if (IS_GEN9(dev)) {
1830 uint32_t val;
1831 int ret, i;
1832 int level, max_level = ilk_wm_max_level(dev);
1833
1834 /* read the first set of memory latencies[0:3] */
1835 val = 0; /* data0 to be programmed to 0 for first set */
1836 mutex_lock(&dev_priv->rps.hw_lock);
1837 ret = sandybridge_pcode_read(dev_priv,
1838 GEN9_PCODE_READ_MEM_LATENCY,
1839 &val);
1840 mutex_unlock(&dev_priv->rps.hw_lock);
1841
1842 if (ret) {
1843 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
1844 return;
1845 }
1846
1847 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
1848 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
1849 GEN9_MEM_LATENCY_LEVEL_MASK;
1850 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
1851 GEN9_MEM_LATENCY_LEVEL_MASK;
1852 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
1853 GEN9_MEM_LATENCY_LEVEL_MASK;
1854
1855 /* read the second set of memory latencies[4:7] */
1856 val = 1; /* data0 to be programmed to 1 for second set */
1857 mutex_lock(&dev_priv->rps.hw_lock);
1858 ret = sandybridge_pcode_read(dev_priv,
1859 GEN9_PCODE_READ_MEM_LATENCY,
1860 &val);
1861 mutex_unlock(&dev_priv->rps.hw_lock);
1862 if (ret) {
1863 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
1864 return;
1865 }
1866
1867 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
1868 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
1869 GEN9_MEM_LATENCY_LEVEL_MASK;
1870 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
1871 GEN9_MEM_LATENCY_LEVEL_MASK;
1872 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
1873 GEN9_MEM_LATENCY_LEVEL_MASK;
1874
1875 /*
1876 * WaWmMemoryReadLatency:skl
1877 *
1878 * punit doesn't take into account the read latency so we need
1879 * to add 2us to the various latency levels we retrieve from
1880 * the punit.
1881 * - W0 is a bit special in that it's the only level that
1882 * can't be disabled if we want to have display working, so
1883 * we always add 2us there.
1884 * - For levels >=1, punit returns 0us latency when they are
1885 * disabled, so we respect that and don't add 2us then
1886 *
1887 * Additionally, if a level n (n > 1) has a 0us latency, all
1888 * levels m (m >= n) need to be disabled. We make sure to
1889 * sanitize the values out of the punit to satisfy this
1890 * requirement.
1891 */
1892 wm[0] += 2;
1893 for (level = 1; level <= max_level; level++)
1894 if (wm[level] != 0)
1895 wm[level] += 2;
1896 else {
1897 for (i = level + 1; i <= max_level; i++)
1898 wm[i] = 0;
1899
1900 break;
1901 }
1902 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1903 uint64_t sskpd = I915_READ64(MCH_SSKPD);
1904
1905 wm[0] = (sskpd >> 56) & 0xFF;
1906 if (wm[0] == 0)
1907 wm[0] = sskpd & 0xF;
1908 wm[1] = (sskpd >> 4) & 0xFF;
1909 wm[2] = (sskpd >> 12) & 0xFF;
1910 wm[3] = (sskpd >> 20) & 0x1FF;
1911 wm[4] = (sskpd >> 32) & 0x1FF;
1912 } else if (INTEL_INFO(dev)->gen >= 6) {
1913 uint32_t sskpd = I915_READ(MCH_SSKPD);
1914
1915 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
1916 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
1917 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
1918 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
1919 } else if (INTEL_INFO(dev)->gen >= 5) {
1920 uint32_t mltr = I915_READ(MLTR_ILK);
1921
1922 /* ILK primary LP0 latency is 700 ns */
1923 wm[0] = 7;
1924 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
1925 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
1926 }
1927 }
1928
1929 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
1930 {
1931 /* ILK sprite LP0 latency is 1300 ns */
1932 if (INTEL_INFO(dev)->gen == 5)
1933 wm[0] = 13;
1934 }
1935
1936 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
1937 {
1938 /* ILK cursor LP0 latency is 1300 ns */
1939 if (INTEL_INFO(dev)->gen == 5)
1940 wm[0] = 13;
1941
1942 /* WaDoubleCursorLP3Latency:ivb */
1943 if (IS_IVYBRIDGE(dev))
1944 wm[3] *= 2;
1945 }
1946
1947 int ilk_wm_max_level(const struct drm_device *dev)
1948 {
1949 /* how many WM levels are we expecting */
1950 if (IS_GEN9(dev))
1951 return 7;
1952 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1953 return 4;
1954 else if (INTEL_INFO(dev)->gen >= 6)
1955 return 3;
1956 else
1957 return 2;
1958 }
1959
1960 static void intel_print_wm_latency(struct drm_device *dev,
1961 const char *name,
1962 const uint16_t wm[8])
1963 {
1964 int level, max_level = ilk_wm_max_level(dev);
1965
1966 for (level = 0; level <= max_level; level++) {
1967 unsigned int latency = wm[level];
1968
1969 if (latency == 0) {
1970 DRM_ERROR("%s WM%d latency not provided\n",
1971 name, level);
1972 continue;
1973 }
1974
1975 /*
1976 * - latencies are in us on gen9.
1977 * - before then, WM1+ latency values are in 0.5us units
1978 */
1979 if (IS_GEN9(dev))
1980 latency *= 10;
1981 else if (level > 0)
1982 latency *= 5;
1983
1984 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
1985 name, level, wm[level],
1986 latency / 10, latency % 10);
1987 }
1988 }
1989
1990 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
1991 uint16_t wm[5], uint16_t min)
1992 {
1993 int level, max_level = ilk_wm_max_level(dev_priv->dev);
1994
1995 if (wm[0] >= min)
1996 return false;
1997
1998 wm[0] = max(wm[0], min);
1999 for (level = 1; level <= max_level; level++)
2000 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2001
2002 return true;
2003 }
2004
2005 static void snb_wm_latency_quirk(struct drm_device *dev)
2006 {
2007 struct drm_i915_private *dev_priv = dev->dev_private;
2008 bool changed;
2009
2010 /*
2011 * The BIOS provided WM memory latency values are often
2012 * inadequate for high resolution displays. Adjust them.
2013 */
2014 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2015 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2016 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2017
2018 if (!changed)
2019 return;
2020
2021 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2022 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2023 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2024 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2025 }
2026
2027 static void ilk_setup_wm_latency(struct drm_device *dev)
2028 {
2029 struct drm_i915_private *dev_priv = dev->dev_private;
2030
2031 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2032
2033 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2034 sizeof(dev_priv->wm.pri_latency));
2035 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2036 sizeof(dev_priv->wm.pri_latency));
2037
2038 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2039 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2040
2041 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2042 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2043 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2044
2045 if (IS_GEN6(dev))
2046 snb_wm_latency_quirk(dev);
2047 }
2048
2049 static void skl_setup_wm_latency(struct drm_device *dev)
2050 {
2051 struct drm_i915_private *dev_priv = dev->dev_private;
2052
2053 intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2054 intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2055 }
2056
2057 static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
2058 struct ilk_pipe_wm_parameters *p)
2059 {
2060 struct drm_device *dev = crtc->dev;
2061 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2062 enum pipe pipe = intel_crtc->pipe;
2063 struct drm_plane *plane;
2064
2065 if (!intel_crtc->active)
2066 return;
2067
2068 p->active = true;
2069 p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;
2070 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
2071
2072 if (crtc->primary->state->fb) {
2073 p->pri.enabled = true;
2074 p->pri.bytes_per_pixel =
2075 crtc->primary->state->fb->bits_per_pixel / 8;
2076 } else {
2077 p->pri.enabled = false;
2078 p->pri.bytes_per_pixel = 0;
2079 }
2080
2081 if (crtc->cursor->state->fb) {
2082 p->cur.enabled = true;
2083 p->cur.bytes_per_pixel = 4;
2084 } else {
2085 p->cur.enabled = false;
2086 p->cur.bytes_per_pixel = 0;
2087 }
2088 p->pri.horiz_pixels = intel_crtc->config->pipe_src_w;
2089 p->cur.horiz_pixels = intel_crtc->base.cursor->state->crtc_w;
2090
2091 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
2092 struct intel_plane *intel_plane = to_intel_plane(plane);
2093
2094 if (intel_plane->pipe == pipe) {
2095 p->spr = intel_plane->wm;
2096 break;
2097 }
2098 }
2099 }
2100
2101 static void ilk_compute_wm_config(struct drm_device *dev,
2102 struct intel_wm_config *config)
2103 {
2104 struct intel_crtc *intel_crtc;
2105
2106 /* Compute the currently _active_ config */
2107 for_each_intel_crtc(dev, intel_crtc) {
2108 const struct intel_pipe_wm *wm = &intel_crtc->wm.active;
2109
2110 if (!wm->pipe_enabled)
2111 continue;
2112
2113 config->sprites_enabled |= wm->sprites_enabled;
2114 config->sprites_scaled |= wm->sprites_scaled;
2115 config->num_pipes_active++;
2116 }
2117 }
2118
2119 /* Compute new watermarks for the pipe */
2120 static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
2121 const struct ilk_pipe_wm_parameters *params,
2122 struct intel_pipe_wm *pipe_wm)
2123 {
2124 struct drm_device *dev = crtc->dev;
2125 const struct drm_i915_private *dev_priv = dev->dev_private;
2126 int level, max_level = ilk_wm_max_level(dev);
2127 /* LP0 watermark maximums depend on this pipe alone */
2128 struct intel_wm_config config = {
2129 .num_pipes_active = 1,
2130 .sprites_enabled = params->spr.enabled,
2131 .sprites_scaled = params->spr.scaled,
2132 };
2133 struct ilk_wm_maximums max;
2134
2135 pipe_wm->pipe_enabled = params->active;
2136 pipe_wm->sprites_enabled = params->spr.enabled;
2137 pipe_wm->sprites_scaled = params->spr.scaled;
2138
2139 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2140 if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled)
2141 max_level = 1;
2142
2143 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2144 if (params->spr.scaled)
2145 max_level = 0;
2146
2147 ilk_compute_wm_level(dev_priv, 0, params, &pipe_wm->wm[0]);
2148
2149 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2150 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
2151
2152 /* LP0 watermarks always use 1/2 DDB partitioning */
2153 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2154
2155 /* At least LP0 must be valid */
2156 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
2157 return false;
2158
2159 ilk_compute_wm_reg_maximums(dev, 1, &max);
2160
2161 for (level = 1; level <= max_level; level++) {
2162 struct intel_wm_level wm = {};
2163
2164 ilk_compute_wm_level(dev_priv, level, params, &wm);
2165
2166 /*
2167 * Disable any watermark level that exceeds the
2168 * register maximums since such watermarks are
2169 * always invalid.
2170 */
2171 if (!ilk_validate_wm_level(level, &max, &wm))
2172 break;
2173
2174 pipe_wm->wm[level] = wm;
2175 }
2176
2177 return true;
2178 }
2179
2180 /*
2181 * Merge the watermarks from all active pipes for a specific level.
2182 */
2183 static void ilk_merge_wm_level(struct drm_device *dev,
2184 int level,
2185 struct intel_wm_level *ret_wm)
2186 {
2187 const struct intel_crtc *intel_crtc;
2188
2189 ret_wm->enable = true;
2190
2191 for_each_intel_crtc(dev, intel_crtc) {
2192 const struct intel_pipe_wm *active = &intel_crtc->wm.active;
2193 const struct intel_wm_level *wm = &active->wm[level];
2194
2195 if (!active->pipe_enabled)
2196 continue;
2197
2198 /*
2199 * The watermark values may have been used in the past,
2200 * so we must maintain them in the registers for some
2201 * time even if the level is now disabled.
2202 */
2203 if (!wm->enable)
2204 ret_wm->enable = false;
2205
2206 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2207 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2208 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2209 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2210 }
2211 }
2212
2213 /*
2214 * Merge all low power watermarks for all active pipes.
2215 */
2216 static void ilk_wm_merge(struct drm_device *dev,
2217 const struct intel_wm_config *config,
2218 const struct ilk_wm_maximums *max,
2219 struct intel_pipe_wm *merged)
2220 {
2221 int level, max_level = ilk_wm_max_level(dev);
2222 int last_enabled_level = max_level;
2223
2224 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2225 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2226 config->num_pipes_active > 1)
2227 return;
2228
2229 /* ILK: FBC WM must be disabled always */
2230 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
2231
2232 /* merge each WM1+ level */
2233 for (level = 1; level <= max_level; level++) {
2234 struct intel_wm_level *wm = &merged->wm[level];
2235
2236 ilk_merge_wm_level(dev, level, wm);
2237
2238 if (level > last_enabled_level)
2239 wm->enable = false;
2240 else if (!ilk_validate_wm_level(level, max, wm))
2241 /* make sure all following levels get disabled */
2242 last_enabled_level = level - 1;
2243
2244 /*
2245 * The spec says it is preferred to disable
2246 * FBC WMs instead of disabling a WM level.
2247 */
2248 if (wm->fbc_val > max->fbc) {
2249 if (wm->enable)
2250 merged->fbc_wm_enabled = false;
2251 wm->fbc_val = 0;
2252 }
2253 }
2254
2255 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2256 /*
2257 * FIXME this is racy. FBC might get enabled later.
2258 * What we should check here is whether FBC can be
2259 * enabled sometime later.
2260 */
2261 if (IS_GEN5(dev) && !merged->fbc_wm_enabled && intel_fbc_enabled(dev)) {
2262 for (level = 2; level <= max_level; level++) {
2263 struct intel_wm_level *wm = &merged->wm[level];
2264
2265 wm->enable = false;
2266 }
2267 }
2268 }
2269
2270 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2271 {
2272 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2273 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2274 }
2275
2276 /* The value we need to program into the WM_LPx latency field */
2277 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2278 {
2279 struct drm_i915_private *dev_priv = dev->dev_private;
2280
2281 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2282 return 2 * level;
2283 else
2284 return dev_priv->wm.pri_latency[level];
2285 }
2286
2287 static void ilk_compute_wm_results(struct drm_device *dev,
2288 const struct intel_pipe_wm *merged,
2289 enum intel_ddb_partitioning partitioning,
2290 struct ilk_wm_values *results)
2291 {
2292 struct intel_crtc *intel_crtc;
2293 int level, wm_lp;
2294
2295 results->enable_fbc_wm = merged->fbc_wm_enabled;
2296 results->partitioning = partitioning;
2297
2298 /* LP1+ register values */
2299 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2300 const struct intel_wm_level *r;
2301
2302 level = ilk_wm_lp_to_level(wm_lp, merged);
2303
2304 r = &merged->wm[level];
2305
2306 /*
2307 * Maintain the watermark values even if the level is
2308 * disabled. Doing otherwise could cause underruns.
2309 */
2310 results->wm_lp[wm_lp - 1] =
2311 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2312 (r->pri_val << WM1_LP_SR_SHIFT) |
2313 r->cur_val;
2314
2315 if (r->enable)
2316 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2317
2318 if (INTEL_INFO(dev)->gen >= 8)
2319 results->wm_lp[wm_lp - 1] |=
2320 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2321 else
2322 results->wm_lp[wm_lp - 1] |=
2323 r->fbc_val << WM1_LP_FBC_SHIFT;
2324
2325 /*
2326 * Always set WM1S_LP_EN when spr_val != 0, even if the
2327 * level is disabled. Doing otherwise could cause underruns.
2328 */
2329 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2330 WARN_ON(wm_lp != 1);
2331 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2332 } else
2333 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2334 }
2335
2336 /* LP0 register values */
2337 for_each_intel_crtc(dev, intel_crtc) {
2338 enum pipe pipe = intel_crtc->pipe;
2339 const struct intel_wm_level *r =
2340 &intel_crtc->wm.active.wm[0];
2341
2342 if (WARN_ON(!r->enable))
2343 continue;
2344
2345 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
2346
2347 results->wm_pipe[pipe] =
2348 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2349 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2350 r->cur_val;
2351 }
2352 }
2353
2354 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2355 * case both are at the same level. Prefer r1 in case they're the same. */
2356 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2357 struct intel_pipe_wm *r1,
2358 struct intel_pipe_wm *r2)
2359 {
2360 int level, max_level = ilk_wm_max_level(dev);
2361 int level1 = 0, level2 = 0;
2362
2363 for (level = 1; level <= max_level; level++) {
2364 if (r1->wm[level].enable)
2365 level1 = level;
2366 if (r2->wm[level].enable)
2367 level2 = level;
2368 }
2369
2370 if (level1 == level2) {
2371 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2372 return r2;
2373 else
2374 return r1;
2375 } else if (level1 > level2) {
2376 return r1;
2377 } else {
2378 return r2;
2379 }
2380 }
2381
2382 /* dirty bits used to track which watermarks need changes */
2383 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2384 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2385 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2386 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2387 #define WM_DIRTY_FBC (1 << 24)
2388 #define WM_DIRTY_DDB (1 << 25)
2389
2390 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
2391 const struct ilk_wm_values *old,
2392 const struct ilk_wm_values *new)
2393 {
2394 unsigned int dirty = 0;
2395 enum pipe pipe;
2396 int wm_lp;
2397
2398 for_each_pipe(dev_priv, pipe) {
2399 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2400 dirty |= WM_DIRTY_LINETIME(pipe);
2401 /* Must disable LP1+ watermarks too */
2402 dirty |= WM_DIRTY_LP_ALL;
2403 }
2404
2405 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2406 dirty |= WM_DIRTY_PIPE(pipe);
2407 /* Must disable LP1+ watermarks too */
2408 dirty |= WM_DIRTY_LP_ALL;
2409 }
2410 }
2411
2412 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2413 dirty |= WM_DIRTY_FBC;
2414 /* Must disable LP1+ watermarks too */
2415 dirty |= WM_DIRTY_LP_ALL;
2416 }
2417
2418 if (old->partitioning != new->partitioning) {
2419 dirty |= WM_DIRTY_DDB;
2420 /* Must disable LP1+ watermarks too */
2421 dirty |= WM_DIRTY_LP_ALL;
2422 }
2423
2424 /* LP1+ watermarks already deemed dirty, no need to continue */
2425 if (dirty & WM_DIRTY_LP_ALL)
2426 return dirty;
2427
2428 /* Find the lowest numbered LP1+ watermark in need of an update... */
2429 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2430 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2431 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2432 break;
2433 }
2434
2435 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2436 for (; wm_lp <= 3; wm_lp++)
2437 dirty |= WM_DIRTY_LP(wm_lp);
2438
2439 return dirty;
2440 }
2441
2442 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2443 unsigned int dirty)
2444 {
2445 struct ilk_wm_values *previous = &dev_priv->wm.hw;
2446 bool changed = false;
2447
2448 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2449 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2450 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2451 changed = true;
2452 }
2453 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2454 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2455 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2456 changed = true;
2457 }
2458 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2459 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2460 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2461 changed = true;
2462 }
2463
2464 /*
2465 * Don't touch WM1S_LP_EN here.
2466 * Doing so could cause underruns.
2467 */
2468
2469 return changed;
2470 }
2471
2472 /*
2473 * The spec says we shouldn't write when we don't need, because every write
2474 * causes WMs to be re-evaluated, expending some power.
2475 */
2476 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2477 struct ilk_wm_values *results)
2478 {
2479 struct drm_device *dev = dev_priv->dev;
2480 struct ilk_wm_values *previous = &dev_priv->wm.hw;
2481 unsigned int dirty;
2482 uint32_t val;
2483
2484 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
2485 if (!dirty)
2486 return;
2487
2488 _ilk_disable_lp_wm(dev_priv, dirty);
2489
2490 if (dirty & WM_DIRTY_PIPE(PIPE_A))
2491 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2492 if (dirty & WM_DIRTY_PIPE(PIPE_B))
2493 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2494 if (dirty & WM_DIRTY_PIPE(PIPE_C))
2495 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2496
2497 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2498 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2499 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2500 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2501 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2502 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2503
2504 if (dirty & WM_DIRTY_DDB) {
2505 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2506 val = I915_READ(WM_MISC);
2507 if (results->partitioning == INTEL_DDB_PART_1_2)
2508 val &= ~WM_MISC_DATA_PARTITION_5_6;
2509 else
2510 val |= WM_MISC_DATA_PARTITION_5_6;
2511 I915_WRITE(WM_MISC, val);
2512 } else {
2513 val = I915_READ(DISP_ARB_CTL2);
2514 if (results->partitioning == INTEL_DDB_PART_1_2)
2515 val &= ~DISP_DATA_PARTITION_5_6;
2516 else
2517 val |= DISP_DATA_PARTITION_5_6;
2518 I915_WRITE(DISP_ARB_CTL2, val);
2519 }
2520 }
2521
2522 if (dirty & WM_DIRTY_FBC) {
2523 val = I915_READ(DISP_ARB_CTL);
2524 if (results->enable_fbc_wm)
2525 val &= ~DISP_FBC_WM_DIS;
2526 else
2527 val |= DISP_FBC_WM_DIS;
2528 I915_WRITE(DISP_ARB_CTL, val);
2529 }
2530
2531 if (dirty & WM_DIRTY_LP(1) &&
2532 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2533 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2534
2535 if (INTEL_INFO(dev)->gen >= 7) {
2536 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2537 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2538 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2539 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2540 }
2541
2542 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2543 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2544 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2545 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2546 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2547 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2548
2549 dev_priv->wm.hw = *results;
2550 }
2551
2552 static bool ilk_disable_lp_wm(struct drm_device *dev)
2553 {
2554 struct drm_i915_private *dev_priv = dev->dev_private;
2555
2556 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2557 }
2558
2559 /*
2560 * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2561 * different active planes.
2562 */
2563
2564 #define SKL_DDB_SIZE 896 /* in blocks */
2565 #define BXT_DDB_SIZE 512
2566
2567 static void
2568 skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
2569 struct drm_crtc *for_crtc,
2570 const struct intel_wm_config *config,
2571 const struct skl_pipe_wm_parameters *params,
2572 struct skl_ddb_entry *alloc /* out */)
2573 {
2574 struct drm_crtc *crtc;
2575 unsigned int pipe_size, ddb_size;
2576 int nth_active_pipe;
2577
2578 if (!params->active) {
2579 alloc->start = 0;
2580 alloc->end = 0;
2581 return;
2582 }
2583
2584 if (IS_BROXTON(dev))
2585 ddb_size = BXT_DDB_SIZE;
2586 else
2587 ddb_size = SKL_DDB_SIZE;
2588
2589 ddb_size -= 4; /* 4 blocks for bypass path allocation */
2590
2591 nth_active_pipe = 0;
2592 for_each_crtc(dev, crtc) {
2593 if (!to_intel_crtc(crtc)->active)
2594 continue;
2595
2596 if (crtc == for_crtc)
2597 break;
2598
2599 nth_active_pipe++;
2600 }
2601
2602 pipe_size = ddb_size / config->num_pipes_active;
2603 alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active;
2604 alloc->end = alloc->start + pipe_size;
2605 }
2606
2607 static unsigned int skl_cursor_allocation(const struct intel_wm_config *config)
2608 {
2609 if (config->num_pipes_active == 1)
2610 return 32;
2611
2612 return 8;
2613 }
2614
2615 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
2616 {
2617 entry->start = reg & 0x3ff;
2618 entry->end = (reg >> 16) & 0x3ff;
2619 if (entry->end)
2620 entry->end += 1;
2621 }
2622
2623 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2624 struct skl_ddb_allocation *ddb /* out */)
2625 {
2626 enum pipe pipe;
2627 int plane;
2628 u32 val;
2629
2630 for_each_pipe(dev_priv, pipe) {
2631 for_each_plane(dev_priv, pipe, plane) {
2632 val = I915_READ(PLANE_BUF_CFG(pipe, plane));
2633 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
2634 val);
2635 }
2636
2637 val = I915_READ(CUR_BUF_CFG(pipe));
2638 skl_ddb_entry_init_from_hw(&ddb->cursor[pipe], val);
2639 }
2640 }
2641
2642 static unsigned int
2643 skl_plane_relative_data_rate(const struct intel_plane_wm_parameters *p)
2644 {
2645 return p->horiz_pixels * p->vert_pixels * p->bytes_per_pixel;
2646 }
2647
2648 /*
2649 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
2650 * a 8192x4096@32bpp framebuffer:
2651 * 3 * 4096 * 8192 * 4 < 2^32
2652 */
2653 static unsigned int
2654 skl_get_total_relative_data_rate(struct intel_crtc *intel_crtc,
2655 const struct skl_pipe_wm_parameters *params)
2656 {
2657 unsigned int total_data_rate = 0;
2658 int plane;
2659
2660 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
2661 const struct intel_plane_wm_parameters *p;
2662
2663 p = &params->plane[plane];
2664 if (!p->enabled)
2665 continue;
2666
2667 total_data_rate += skl_plane_relative_data_rate(p);
2668 }
2669
2670 return total_data_rate;
2671 }
2672
2673 static void
2674 skl_allocate_pipe_ddb(struct drm_crtc *crtc,
2675 const struct intel_wm_config *config,
2676 const struct skl_pipe_wm_parameters *params,
2677 struct skl_ddb_allocation *ddb /* out */)
2678 {
2679 struct drm_device *dev = crtc->dev;
2680 struct drm_i915_private *dev_priv = dev->dev_private;
2681 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2682 enum pipe pipe = intel_crtc->pipe;
2683 struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
2684 uint16_t alloc_size, start, cursor_blocks;
2685 uint16_t minimum[I915_MAX_PLANES];
2686 unsigned int total_data_rate;
2687 int plane;
2688
2689 skl_ddb_get_pipe_allocation_limits(dev, crtc, config, params, alloc);
2690 alloc_size = skl_ddb_entry_size(alloc);
2691 if (alloc_size == 0) {
2692 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
2693 memset(&ddb->cursor[pipe], 0, sizeof(ddb->cursor[pipe]));
2694 return;
2695 }
2696
2697 cursor_blocks = skl_cursor_allocation(config);
2698 ddb->cursor[pipe].start = alloc->end - cursor_blocks;
2699 ddb->cursor[pipe].end = alloc->end;
2700
2701 alloc_size -= cursor_blocks;
2702 alloc->end -= cursor_blocks;
2703
2704 /* 1. Allocate the mininum required blocks for each active plane */
2705 for_each_plane(dev_priv, pipe, plane) {
2706 const struct intel_plane_wm_parameters *p;
2707
2708 p = &params->plane[plane];
2709 if (!p->enabled)
2710 continue;
2711
2712 minimum[plane] = 8;
2713 alloc_size -= minimum[plane];
2714 }
2715
2716 /*
2717 * 2. Distribute the remaining space in proportion to the amount of
2718 * data each plane needs to fetch from memory.
2719 *
2720 * FIXME: we may not allocate every single block here.
2721 */
2722 total_data_rate = skl_get_total_relative_data_rate(intel_crtc, params);
2723
2724 start = alloc->start;
2725 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
2726 const struct intel_plane_wm_parameters *p;
2727 unsigned int data_rate;
2728 uint16_t plane_blocks;
2729
2730 p = &params->plane[plane];
2731 if (!p->enabled)
2732 continue;
2733
2734 data_rate = skl_plane_relative_data_rate(p);
2735
2736 /*
2737 * promote the expression to 64 bits to avoid overflowing, the
2738 * result is < available as data_rate / total_data_rate < 1
2739 */
2740 plane_blocks = minimum[plane];
2741 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
2742 total_data_rate);
2743
2744 ddb->plane[pipe][plane].start = start;
2745 ddb->plane[pipe][plane].end = start + plane_blocks;
2746
2747 start += plane_blocks;
2748 }
2749
2750 }
2751
2752 static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
2753 {
2754 /* TODO: Take into account the scalers once we support them */
2755 return config->base.adjusted_mode.crtc_clock;
2756 }
2757
2758 /*
2759 * The max latency should be 257 (max the punit can code is 255 and we add 2us
2760 * for the read latency) and bytes_per_pixel should always be <= 8, so that
2761 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
2762 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
2763 */
2764 static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
2765 uint32_t latency)
2766 {
2767 uint32_t wm_intermediate_val, ret;
2768
2769 if (latency == 0)
2770 return UINT_MAX;
2771
2772 wm_intermediate_val = latency * pixel_rate * bytes_per_pixel / 512;
2773 ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
2774
2775 return ret;
2776 }
2777
2778 static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
2779 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
2780 uint64_t tiling, uint32_t latency)
2781 {
2782 uint32_t ret;
2783 uint32_t plane_bytes_per_line, plane_blocks_per_line;
2784 uint32_t wm_intermediate_val;
2785
2786 if (latency == 0)
2787 return UINT_MAX;
2788
2789 plane_bytes_per_line = horiz_pixels * bytes_per_pixel;
2790
2791 if (tiling == I915_FORMAT_MOD_Y_TILED ||
2792 tiling == I915_FORMAT_MOD_Yf_TILED) {
2793 plane_bytes_per_line *= 4;
2794 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
2795 plane_blocks_per_line /= 4;
2796 } else {
2797 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
2798 }
2799
2800 wm_intermediate_val = latency * pixel_rate;
2801 ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
2802 plane_blocks_per_line;
2803
2804 return ret;
2805 }
2806
2807 static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb,
2808 const struct intel_crtc *intel_crtc)
2809 {
2810 struct drm_device *dev = intel_crtc->base.dev;
2811 struct drm_i915_private *dev_priv = dev->dev_private;
2812 const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
2813 enum pipe pipe = intel_crtc->pipe;
2814
2815 if (memcmp(new_ddb->plane[pipe], cur_ddb->plane[pipe],
2816 sizeof(new_ddb->plane[pipe])))
2817 return true;
2818
2819 if (memcmp(&new_ddb->cursor[pipe], &cur_ddb->cursor[pipe],
2820 sizeof(new_ddb->cursor[pipe])))
2821 return true;
2822
2823 return false;
2824 }
2825
2826 static void skl_compute_wm_global_parameters(struct drm_device *dev,
2827 struct intel_wm_config *config)
2828 {
2829 struct drm_crtc *crtc;
2830 struct drm_plane *plane;
2831
2832 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
2833 config->num_pipes_active += to_intel_crtc(crtc)->active;
2834
2835 /* FIXME: I don't think we need those two global parameters on SKL */
2836 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2837 struct intel_plane *intel_plane = to_intel_plane(plane);
2838
2839 config->sprites_enabled |= intel_plane->wm.enabled;
2840 config->sprites_scaled |= intel_plane->wm.scaled;
2841 }
2842 }
2843
2844 static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,
2845 struct skl_pipe_wm_parameters *p)
2846 {
2847 struct drm_device *dev = crtc->dev;
2848 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2849 enum pipe pipe = intel_crtc->pipe;
2850 struct drm_plane *plane;
2851 struct drm_framebuffer *fb;
2852 int i = 1; /* Index for sprite planes start */
2853
2854 p->active = intel_crtc->active;
2855 if (p->active) {
2856 p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;
2857 p->pixel_rate = skl_pipe_pixel_rate(intel_crtc->config);
2858
2859 fb = crtc->primary->state->fb;
2860 if (fb) {
2861 p->plane[0].enabled = true;
2862 p->plane[0].bytes_per_pixel = fb->bits_per_pixel / 8;
2863 p->plane[0].tiling = fb->modifier[0];
2864 } else {
2865 p->plane[0].enabled = false;
2866 p->plane[0].bytes_per_pixel = 0;
2867 p->plane[0].tiling = DRM_FORMAT_MOD_NONE;
2868 }
2869 p->plane[0].horiz_pixels = intel_crtc->config->pipe_src_w;
2870 p->plane[0].vert_pixels = intel_crtc->config->pipe_src_h;
2871 p->plane[0].rotation = crtc->primary->state->rotation;
2872
2873 fb = crtc->cursor->state->fb;
2874 if (fb) {
2875 p->cursor.enabled = true;
2876 p->cursor.bytes_per_pixel = fb->bits_per_pixel / 8;
2877 p->cursor.horiz_pixels = crtc->cursor->state->crtc_w;
2878 p->cursor.vert_pixels = crtc->cursor->state->crtc_h;
2879 } else {
2880 p->cursor.enabled = false;
2881 p->cursor.bytes_per_pixel = 0;
2882 p->cursor.horiz_pixels = 64;
2883 p->cursor.vert_pixels = 64;
2884 }
2885 }
2886
2887 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2888 struct intel_plane *intel_plane = to_intel_plane(plane);
2889
2890 if (intel_plane->pipe == pipe &&
2891 plane->type == DRM_PLANE_TYPE_OVERLAY)
2892 p->plane[i++] = intel_plane->wm;
2893 }
2894 }
2895
2896 static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
2897 struct skl_pipe_wm_parameters *p,
2898 struct intel_plane_wm_parameters *p_params,
2899 uint16_t ddb_allocation,
2900 int level,
2901 uint16_t *out_blocks, /* out */
2902 uint8_t *out_lines /* out */)
2903 {
2904 uint32_t latency = dev_priv->wm.skl_latency[level];
2905 uint32_t method1, method2;
2906 uint32_t plane_bytes_per_line, plane_blocks_per_line;
2907 uint32_t res_blocks, res_lines;
2908 uint32_t selected_result;
2909
2910 if (latency == 0 || !p->active || !p_params->enabled)
2911 return false;
2912
2913 method1 = skl_wm_method1(p->pixel_rate,
2914 p_params->bytes_per_pixel,
2915 latency);
2916 method2 = skl_wm_method2(p->pixel_rate,
2917 p->pipe_htotal,
2918 p_params->horiz_pixels,
2919 p_params->bytes_per_pixel,
2920 p_params->tiling,
2921 latency);
2922
2923 plane_bytes_per_line = p_params->horiz_pixels *
2924 p_params->bytes_per_pixel;
2925 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
2926
2927 if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
2928 p_params->tiling == I915_FORMAT_MOD_Yf_TILED) {
2929 uint32_t min_scanlines = 4;
2930 uint32_t y_tile_minimum;
2931 if (intel_rotation_90_or_270(p_params->rotation)) {
2932 switch (p_params->bytes_per_pixel) {
2933 case 1:
2934 min_scanlines = 16;
2935 break;
2936 case 2:
2937 min_scanlines = 8;
2938 break;
2939 case 8:
2940 WARN(1, "Unsupported pixel depth for rotation");
2941 }
2942 }
2943 y_tile_minimum = plane_blocks_per_line * min_scanlines;
2944 selected_result = max(method2, y_tile_minimum);
2945 } else {
2946 if ((ddb_allocation / plane_blocks_per_line) >= 1)
2947 selected_result = min(method1, method2);
2948 else
2949 selected_result = method1;
2950 }
2951
2952 res_blocks = selected_result + 1;
2953 res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
2954
2955 if (level >= 1 && level <= 7) {
2956 if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
2957 p_params->tiling == I915_FORMAT_MOD_Yf_TILED)
2958 res_lines += 4;
2959 else
2960 res_blocks++;
2961 }
2962
2963 if (res_blocks >= ddb_allocation || res_lines > 31)
2964 return false;
2965
2966 *out_blocks = res_blocks;
2967 *out_lines = res_lines;
2968
2969 return true;
2970 }
2971
2972 static void skl_compute_wm_level(const struct drm_i915_private *dev_priv,
2973 struct skl_ddb_allocation *ddb,
2974 struct skl_pipe_wm_parameters *p,
2975 enum pipe pipe,
2976 int level,
2977 int num_planes,
2978 struct skl_wm_level *result)
2979 {
2980 uint16_t ddb_blocks;
2981 int i;
2982
2983 for (i = 0; i < num_planes; i++) {
2984 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
2985
2986 result->plane_en[i] = skl_compute_plane_wm(dev_priv,
2987 p, &p->plane[i],
2988 ddb_blocks,
2989 level,
2990 &result->plane_res_b[i],
2991 &result->plane_res_l[i]);
2992 }
2993
2994 ddb_blocks = skl_ddb_entry_size(&ddb->cursor[pipe]);
2995 result->cursor_en = skl_compute_plane_wm(dev_priv, p, &p->cursor,
2996 ddb_blocks, level,
2997 &result->cursor_res_b,
2998 &result->cursor_res_l);
2999 }
3000
3001 static uint32_t
3002 skl_compute_linetime_wm(struct drm_crtc *crtc, struct skl_pipe_wm_parameters *p)
3003 {
3004 if (!to_intel_crtc(crtc)->active)
3005 return 0;
3006
3007 return DIV_ROUND_UP(8 * p->pipe_htotal * 1000, p->pixel_rate);
3008
3009 }
3010
3011 static void skl_compute_transition_wm(struct drm_crtc *crtc,
3012 struct skl_pipe_wm_parameters *params,
3013 struct skl_wm_level *trans_wm /* out */)
3014 {
3015 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3016 int i;
3017
3018 if (!params->active)
3019 return;
3020
3021 /* Until we know more, just disable transition WMs */
3022 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3023 trans_wm->plane_en[i] = false;
3024 trans_wm->cursor_en = false;
3025 }
3026
3027 static void skl_compute_pipe_wm(struct drm_crtc *crtc,
3028 struct skl_ddb_allocation *ddb,
3029 struct skl_pipe_wm_parameters *params,
3030 struct skl_pipe_wm *pipe_wm)
3031 {
3032 struct drm_device *dev = crtc->dev;
3033 const struct drm_i915_private *dev_priv = dev->dev_private;
3034 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3035 int level, max_level = ilk_wm_max_level(dev);
3036
3037 for (level = 0; level <= max_level; level++) {
3038 skl_compute_wm_level(dev_priv, ddb, params, intel_crtc->pipe,
3039 level, intel_num_planes(intel_crtc),
3040 &pipe_wm->wm[level]);
3041 }
3042 pipe_wm->linetime = skl_compute_linetime_wm(crtc, params);
3043
3044 skl_compute_transition_wm(crtc, params, &pipe_wm->trans_wm);
3045 }
3046
3047 static void skl_compute_wm_results(struct drm_device *dev,
3048 struct skl_pipe_wm_parameters *p,
3049 struct skl_pipe_wm *p_wm,
3050 struct skl_wm_values *r,
3051 struct intel_crtc *intel_crtc)
3052 {
3053 int level, max_level = ilk_wm_max_level(dev);
3054 enum pipe pipe = intel_crtc->pipe;
3055 uint32_t temp;
3056 int i;
3057
3058 for (level = 0; level <= max_level; level++) {
3059 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3060 temp = 0;
3061
3062 temp |= p_wm->wm[level].plane_res_l[i] <<
3063 PLANE_WM_LINES_SHIFT;
3064 temp |= p_wm->wm[level].plane_res_b[i];
3065 if (p_wm->wm[level].plane_en[i])
3066 temp |= PLANE_WM_EN;
3067
3068 r->plane[pipe][i][level] = temp;
3069 }
3070
3071 temp = 0;
3072
3073 temp |= p_wm->wm[level].cursor_res_l << PLANE_WM_LINES_SHIFT;
3074 temp |= p_wm->wm[level].cursor_res_b;
3075
3076 if (p_wm->wm[level].cursor_en)
3077 temp |= PLANE_WM_EN;
3078
3079 r->cursor[pipe][level] = temp;
3080
3081 }
3082
3083 /* transition WMs */
3084 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3085 temp = 0;
3086 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3087 temp |= p_wm->trans_wm.plane_res_b[i];
3088 if (p_wm->trans_wm.plane_en[i])
3089 temp |= PLANE_WM_EN;
3090
3091 r->plane_trans[pipe][i] = temp;
3092 }
3093
3094 temp = 0;
3095 temp |= p_wm->trans_wm.cursor_res_l << PLANE_WM_LINES_SHIFT;
3096 temp |= p_wm->trans_wm.cursor_res_b;
3097 if (p_wm->trans_wm.cursor_en)
3098 temp |= PLANE_WM_EN;
3099
3100 r->cursor_trans[pipe] = temp;
3101
3102 r->wm_linetime[pipe] = p_wm->linetime;
3103 }
3104
3105 static void skl_ddb_entry_write(struct drm_i915_private *dev_priv, uint32_t reg,
3106 const struct skl_ddb_entry *entry)
3107 {
3108 if (entry->end)
3109 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3110 else
3111 I915_WRITE(reg, 0);
3112 }
3113
3114 static void skl_write_wm_values(struct drm_i915_private *dev_priv,
3115 const struct skl_wm_values *new)
3116 {
3117 struct drm_device *dev = dev_priv->dev;
3118 struct intel_crtc *crtc;
3119
3120 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
3121 int i, level, max_level = ilk_wm_max_level(dev);
3122 enum pipe pipe = crtc->pipe;
3123
3124 if (!new->dirty[pipe])
3125 continue;
3126
3127 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]);
3128
3129 for (level = 0; level <= max_level; level++) {
3130 for (i = 0; i < intel_num_planes(crtc); i++)
3131 I915_WRITE(PLANE_WM(pipe, i, level),
3132 new->plane[pipe][i][level]);
3133 I915_WRITE(CUR_WM(pipe, level),
3134 new->cursor[pipe][level]);
3135 }
3136 for (i = 0; i < intel_num_planes(crtc); i++)
3137 I915_WRITE(PLANE_WM_TRANS(pipe, i),
3138 new->plane_trans[pipe][i]);
3139 I915_WRITE(CUR_WM_TRANS(pipe), new->cursor_trans[pipe]);
3140
3141 for (i = 0; i < intel_num_planes(crtc); i++)
3142 skl_ddb_entry_write(dev_priv,
3143 PLANE_BUF_CFG(pipe, i),
3144 &new->ddb.plane[pipe][i]);
3145
3146 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3147 &new->ddb.cursor[pipe]);
3148 }
3149 }
3150
3151 /*
3152 * When setting up a new DDB allocation arrangement, we need to correctly
3153 * sequence the times at which the new allocations for the pipes are taken into
3154 * account or we'll have pipes fetching from space previously allocated to
3155 * another pipe.
3156 *
3157 * Roughly the sequence looks like:
3158 * 1. re-allocate the pipe(s) with the allocation being reduced and not
3159 * overlapping with a previous light-up pipe (another way to put it is:
3160 * pipes with their new allocation strickly included into their old ones).
3161 * 2. re-allocate the other pipes that get their allocation reduced
3162 * 3. allocate the pipes having their allocation increased
3163 *
3164 * Steps 1. and 2. are here to take care of the following case:
3165 * - Initially DDB looks like this:
3166 * | B | C |
3167 * - enable pipe A.
3168 * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
3169 * allocation
3170 * | A | B | C |
3171 *
3172 * We need to sequence the re-allocation: C, B, A (and not B, C, A).
3173 */
3174
3175 static void
3176 skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass)
3177 {
3178 int plane;
3179
3180 DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);
3181
3182 for_each_plane(dev_priv, pipe, plane) {
3183 I915_WRITE(PLANE_SURF(pipe, plane),
3184 I915_READ(PLANE_SURF(pipe, plane)));
3185 }
3186 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3187 }
3188
3189 static bool
3190 skl_ddb_allocation_included(const struct skl_ddb_allocation *old,
3191 const struct skl_ddb_allocation *new,
3192 enum pipe pipe)
3193 {
3194 uint16_t old_size, new_size;
3195
3196 old_size = skl_ddb_entry_size(&old->pipe[pipe]);
3197 new_size = skl_ddb_entry_size(&new->pipe[pipe]);
3198
3199 return old_size != new_size &&
3200 new->pipe[pipe].start >= old->pipe[pipe].start &&
3201 new->pipe[pipe].end <= old->pipe[pipe].end;
3202 }
3203
3204 static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
3205 struct skl_wm_values *new_values)
3206 {
3207 struct drm_device *dev = dev_priv->dev;
3208 struct skl_ddb_allocation *cur_ddb, *new_ddb;
3209 bool reallocated[I915_MAX_PIPES] = {};
3210 struct intel_crtc *crtc;
3211 enum pipe pipe;
3212
3213 new_ddb = &new_values->ddb;
3214 cur_ddb = &dev_priv->wm.skl_hw.ddb;
3215
3216 /*
3217 * First pass: flush the pipes with the new allocation contained into
3218 * the old space.
3219 *
3220 * We'll wait for the vblank on those pipes to ensure we can safely
3221 * re-allocate the freed space without this pipe fetching from it.
3222 */
3223 for_each_intel_crtc(dev, crtc) {
3224 if (!crtc->active)
3225 continue;
3226
3227 pipe = crtc->pipe;
3228
3229 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))
3230 continue;
3231
3232 skl_wm_flush_pipe(dev_priv, pipe, 1);
3233 intel_wait_for_vblank(dev, pipe);
3234
3235 reallocated[pipe] = true;
3236 }
3237
3238
3239 /*
3240 * Second pass: flush the pipes that are having their allocation
3241 * reduced, but overlapping with a previous allocation.
3242 *
3243 * Here as well we need to wait for the vblank to make sure the freed
3244 * space is not used anymore.
3245 */
3246 for_each_intel_crtc(dev, crtc) {
3247 if (!crtc->active)
3248 continue;
3249
3250 pipe = crtc->pipe;
3251
3252 if (reallocated[pipe])
3253 continue;
3254
3255 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <
3256 skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
3257 skl_wm_flush_pipe(dev_priv, pipe, 2);
3258 intel_wait_for_vblank(dev, pipe);
3259 reallocated[pipe] = true;
3260 }
3261 }
3262
3263 /*
3264 * Third pass: flush the pipes that got more space allocated.
3265 *
3266 * We don't need to actively wait for the update here, next vblank
3267 * will just get more DDB space with the correct WM values.
3268 */
3269 for_each_intel_crtc(dev, crtc) {
3270 if (!crtc->active)
3271 continue;
3272
3273 pipe = crtc->pipe;
3274
3275 /*
3276 * At this point, only the pipes more space than before are
3277 * left to re-allocate.
3278 */
3279 if (reallocated[pipe])
3280 continue;
3281
3282 skl_wm_flush_pipe(dev_priv, pipe, 3);
3283 }
3284 }
3285
3286 static bool skl_update_pipe_wm(struct drm_crtc *crtc,
3287 struct skl_pipe_wm_parameters *params,
3288 struct intel_wm_config *config,
3289 struct skl_ddb_allocation *ddb, /* out */
3290 struct skl_pipe_wm *pipe_wm /* out */)
3291 {
3292 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3293
3294 skl_compute_wm_pipe_parameters(crtc, params);
3295 skl_allocate_pipe_ddb(crtc, config, params, ddb);
3296 skl_compute_pipe_wm(crtc, ddb, params, pipe_wm);
3297
3298 if (!memcmp(&intel_crtc->wm.skl_active, pipe_wm, sizeof(*pipe_wm)))
3299 return false;
3300
3301 intel_crtc->wm.skl_active = *pipe_wm;
3302 return true;
3303 }
3304
3305 static void skl_update_other_pipe_wm(struct drm_device *dev,
3306 struct drm_crtc *crtc,
3307 struct intel_wm_config *config,
3308 struct skl_wm_values *r)
3309 {
3310 struct intel_crtc *intel_crtc;
3311 struct intel_crtc *this_crtc = to_intel_crtc(crtc);
3312
3313 /*
3314 * If the WM update hasn't changed the allocation for this_crtc (the
3315 * crtc we are currently computing the new WM values for), other
3316 * enabled crtcs will keep the same allocation and we don't need to
3317 * recompute anything for them.
3318 */
3319 if (!skl_ddb_allocation_changed(&r->ddb, this_crtc))
3320 return;
3321
3322 /*
3323 * Otherwise, because of this_crtc being freshly enabled/disabled, the
3324 * other active pipes need new DDB allocation and WM values.
3325 */
3326 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
3327 base.head) {
3328 struct skl_pipe_wm_parameters params = {};
3329 struct skl_pipe_wm pipe_wm = {};
3330 bool wm_changed;
3331
3332 if (this_crtc->pipe == intel_crtc->pipe)
3333 continue;
3334
3335 if (!intel_crtc->active)
3336 continue;
3337
3338 wm_changed = skl_update_pipe_wm(&intel_crtc->base,
3339 &params, config,
3340 &r->ddb, &pipe_wm);
3341
3342 /*
3343 * If we end up re-computing the other pipe WM values, it's
3344 * because it was really needed, so we expect the WM values to
3345 * be different.
3346 */
3347 WARN_ON(!wm_changed);
3348
3349 skl_compute_wm_results(dev, &params, &pipe_wm, r, intel_crtc);
3350 r->dirty[intel_crtc->pipe] = true;
3351 }
3352 }
3353
3354 static void skl_update_wm(struct drm_crtc *crtc)
3355 {
3356 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3357 struct drm_device *dev = crtc->dev;
3358 struct drm_i915_private *dev_priv = dev->dev_private;
3359 struct skl_pipe_wm_parameters params = {};
3360 struct skl_wm_values *results = &dev_priv->wm.skl_results;
3361 struct skl_pipe_wm pipe_wm = {};
3362 struct intel_wm_config config = {};
3363
3364 memset(results, 0, sizeof(*results));
3365
3366 skl_compute_wm_global_parameters(dev, &config);
3367
3368 if (!skl_update_pipe_wm(crtc, &params, &config,
3369 &results->ddb, &pipe_wm))
3370 return;
3371
3372 skl_compute_wm_results(dev, &params, &pipe_wm, results, intel_crtc);
3373 results->dirty[intel_crtc->pipe] = true;
3374
3375 skl_update_other_pipe_wm(dev, crtc, &config, results);
3376 skl_write_wm_values(dev_priv, results);
3377 skl_flush_wm_values(dev_priv, results);
3378
3379 /* store the new configuration */
3380 dev_priv->wm.skl_hw = *results;
3381 }
3382
3383 static void
3384 skl_update_sprite_wm(struct drm_plane *plane, struct drm_crtc *crtc,
3385 uint32_t sprite_width, uint32_t sprite_height,
3386 int pixel_size, bool enabled, bool scaled)
3387 {
3388 struct intel_plane *intel_plane = to_intel_plane(plane);
3389 struct drm_framebuffer *fb = plane->state->fb;
3390
3391 intel_plane->wm.enabled = enabled;
3392 intel_plane->wm.scaled = scaled;
3393 intel_plane->wm.horiz_pixels = sprite_width;
3394 intel_plane->wm.vert_pixels = sprite_height;
3395 intel_plane->wm.bytes_per_pixel = pixel_size;
3396 intel_plane->wm.tiling = DRM_FORMAT_MOD_NONE;
3397 /*
3398 * Framebuffer can be NULL on plane disable, but it does not
3399 * matter for watermarks if we assume no tiling in that case.
3400 */
3401 if (fb)
3402 intel_plane->wm.tiling = fb->modifier[0];
3403 intel_plane->wm.rotation = plane->state->rotation;
3404
3405 skl_update_wm(crtc);
3406 }
3407
3408 static void ilk_update_wm(struct drm_crtc *crtc)
3409 {
3410 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3411 struct drm_device *dev = crtc->dev;
3412 struct drm_i915_private *dev_priv = dev->dev_private;
3413 struct ilk_wm_maximums max;
3414 struct ilk_pipe_wm_parameters params = {};
3415 struct ilk_wm_values results = {};
3416 enum intel_ddb_partitioning partitioning;
3417 struct intel_pipe_wm pipe_wm = {};
3418 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
3419 struct intel_wm_config config = {};
3420
3421 ilk_compute_wm_parameters(crtc, &params);
3422
3423 intel_compute_pipe_wm(crtc, &params, &pipe_wm);
3424
3425 if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
3426 return;
3427
3428 intel_crtc->wm.active = pipe_wm;
3429
3430 ilk_compute_wm_config(dev, &config);
3431
3432 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
3433 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
3434
3435 /* 5/6 split only in single pipe config on IVB+ */
3436 if (INTEL_INFO(dev)->gen >= 7 &&
3437 config.num_pipes_active == 1 && config.sprites_enabled) {
3438 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
3439 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
3440
3441 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
3442 } else {
3443 best_lp_wm = &lp_wm_1_2;
3444 }
3445
3446 partitioning = (best_lp_wm == &lp_wm_1_2) ?
3447 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
3448
3449 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
3450
3451 ilk_write_wm_values(dev_priv, &results);
3452 }
3453
3454 static void
3455 ilk_update_sprite_wm(struct drm_plane *plane,
3456 struct drm_crtc *crtc,
3457 uint32_t sprite_width, uint32_t sprite_height,
3458 int pixel_size, bool enabled, bool scaled)
3459 {
3460 struct drm_device *dev = plane->dev;
3461 struct intel_plane *intel_plane = to_intel_plane(plane);
3462
3463 intel_plane->wm.enabled = enabled;
3464 intel_plane->wm.scaled = scaled;
3465 intel_plane->wm.horiz_pixels = sprite_width;
3466 intel_plane->wm.vert_pixels = sprite_width;
3467 intel_plane->wm.bytes_per_pixel = pixel_size;
3468
3469 /*
3470 * IVB workaround: must disable low power watermarks for at least
3471 * one frame before enabling scaling. LP watermarks can be re-enabled
3472 * when scaling is disabled.
3473 *
3474 * WaCxSRDisabledForSpriteScaling:ivb
3475 */
3476 if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev))
3477 intel_wait_for_vblank(dev, intel_plane->pipe);
3478
3479 ilk_update_wm(crtc);
3480 }
3481
3482 static void skl_pipe_wm_active_state(uint32_t val,
3483 struct skl_pipe_wm *active,
3484 bool is_transwm,
3485 bool is_cursor,
3486 int i,
3487 int level)
3488 {
3489 bool is_enabled = (val & PLANE_WM_EN) != 0;
3490
3491 if (!is_transwm) {
3492 if (!is_cursor) {
3493 active->wm[level].plane_en[i] = is_enabled;
3494 active->wm[level].plane_res_b[i] =
3495 val & PLANE_WM_BLOCKS_MASK;
3496 active->wm[level].plane_res_l[i] =
3497 (val >> PLANE_WM_LINES_SHIFT) &
3498 PLANE_WM_LINES_MASK;
3499 } else {
3500 active->wm[level].cursor_en = is_enabled;
3501 active->wm[level].cursor_res_b =
3502 val & PLANE_WM_BLOCKS_MASK;
3503 active->wm[level].cursor_res_l =
3504 (val >> PLANE_WM_LINES_SHIFT) &
3505 PLANE_WM_LINES_MASK;
3506 }
3507 } else {
3508 if (!is_cursor) {
3509 active->trans_wm.plane_en[i] = is_enabled;
3510 active->trans_wm.plane_res_b[i] =
3511 val & PLANE_WM_BLOCKS_MASK;
3512 active->trans_wm.plane_res_l[i] =
3513 (val >> PLANE_WM_LINES_SHIFT) &
3514 PLANE_WM_LINES_MASK;
3515 } else {
3516 active->trans_wm.cursor_en = is_enabled;
3517 active->trans_wm.cursor_res_b =
3518 val & PLANE_WM_BLOCKS_MASK;
3519 active->trans_wm.cursor_res_l =
3520 (val >> PLANE_WM_LINES_SHIFT) &
3521 PLANE_WM_LINES_MASK;
3522 }
3523 }
3524 }
3525
3526 static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3527 {
3528 struct drm_device *dev = crtc->dev;
3529 struct drm_i915_private *dev_priv = dev->dev_private;
3530 struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
3531 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3532 struct skl_pipe_wm *active = &intel_crtc->wm.skl_active;
3533 enum pipe pipe = intel_crtc->pipe;
3534 int level, i, max_level;
3535 uint32_t temp;
3536
3537 max_level = ilk_wm_max_level(dev);
3538
3539 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3540
3541 for (level = 0; level <= max_level; level++) {
3542 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3543 hw->plane[pipe][i][level] =
3544 I915_READ(PLANE_WM(pipe, i, level));
3545 hw->cursor[pipe][level] = I915_READ(CUR_WM(pipe, level));
3546 }
3547
3548 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3549 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
3550 hw->cursor_trans[pipe] = I915_READ(CUR_WM_TRANS(pipe));
3551
3552 if (!intel_crtc->active)
3553 return;
3554
3555 hw->dirty[pipe] = true;
3556
3557 active->linetime = hw->wm_linetime[pipe];
3558
3559 for (level = 0; level <= max_level; level++) {
3560 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3561 temp = hw->plane[pipe][i][level];
3562 skl_pipe_wm_active_state(temp, active, false,
3563 false, i, level);
3564 }
3565 temp = hw->cursor[pipe][level];
3566 skl_pipe_wm_active_state(temp, active, false, true, i, level);
3567 }
3568
3569 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3570 temp = hw->plane_trans[pipe][i];
3571 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
3572 }
3573
3574 temp = hw->cursor_trans[pipe];
3575 skl_pipe_wm_active_state(temp, active, true, true, i, 0);
3576 }
3577
3578 void skl_wm_get_hw_state(struct drm_device *dev)
3579 {
3580 struct drm_i915_private *dev_priv = dev->dev_private;
3581 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3582 struct drm_crtc *crtc;
3583
3584 skl_ddb_get_hw_state(dev_priv, ddb);
3585 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3586 skl_pipe_wm_get_hw_state(crtc);
3587 }
3588
3589 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3590 {
3591 struct drm_device *dev = crtc->dev;
3592 struct drm_i915_private *dev_priv = dev->dev_private;
3593 struct ilk_wm_values *hw = &dev_priv->wm.hw;
3594 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3595 struct intel_pipe_wm *active = &intel_crtc->wm.active;
3596 enum pipe pipe = intel_crtc->pipe;
3597 static const unsigned int wm0_pipe_reg[] = {
3598 [PIPE_A] = WM0_PIPEA_ILK,
3599 [PIPE_B] = WM0_PIPEB_ILK,
3600 [PIPE_C] = WM0_PIPEC_IVB,
3601 };
3602
3603 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
3604 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3605 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3606
3607 active->pipe_enabled = intel_crtc->active;
3608
3609 if (active->pipe_enabled) {
3610 u32 tmp = hw->wm_pipe[pipe];
3611
3612 /*
3613 * For active pipes LP0 watermark is marked as
3614 * enabled, and LP1+ watermaks as disabled since
3615 * we can't really reverse compute them in case
3616 * multiple pipes are active.
3617 */
3618 active->wm[0].enable = true;
3619 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3620 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3621 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3622 active->linetime = hw->wm_linetime[pipe];
3623 } else {
3624 int level, max_level = ilk_wm_max_level(dev);
3625
3626 /*
3627 * For inactive pipes, all watermark levels
3628 * should be marked as enabled but zeroed,
3629 * which is what we'd compute them to.
3630 */
3631 for (level = 0; level <= max_level; level++)
3632 active->wm[level].enable = true;
3633 }
3634 }
3635
3636 void ilk_wm_get_hw_state(struct drm_device *dev)
3637 {
3638 struct drm_i915_private *dev_priv = dev->dev_private;
3639 struct ilk_wm_values *hw = &dev_priv->wm.hw;
3640 struct drm_crtc *crtc;
3641
3642 for_each_crtc(dev, crtc)
3643 ilk_pipe_wm_get_hw_state(crtc);
3644
3645 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
3646 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
3647 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
3648
3649 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
3650 if (INTEL_INFO(dev)->gen >= 7) {
3651 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
3652 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
3653 }
3654
3655 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3656 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
3657 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
3658 else if (IS_IVYBRIDGE(dev))
3659 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
3660 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
3661
3662 hw->enable_fbc_wm =
3663 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
3664 }
3665
3666 /**
3667 * intel_update_watermarks - update FIFO watermark values based on current modes
3668 *
3669 * Calculate watermark values for the various WM regs based on current mode
3670 * and plane configuration.
3671 *
3672 * There are several cases to deal with here:
3673 * - normal (i.e. non-self-refresh)
3674 * - self-refresh (SR) mode
3675 * - lines are large relative to FIFO size (buffer can hold up to 2)
3676 * - lines are small relative to FIFO size (buffer can hold more than 2
3677 * lines), so need to account for TLB latency
3678 *
3679 * The normal calculation is:
3680 * watermark = dotclock * bytes per pixel * latency
3681 * where latency is platform & configuration dependent (we assume pessimal
3682 * values here).
3683 *
3684 * The SR calculation is:
3685 * watermark = (trunc(latency/line time)+1) * surface width *
3686 * bytes per pixel
3687 * where
3688 * line time = htotal / dotclock
3689 * surface width = hdisplay for normal plane and 64 for cursor
3690 * and latency is assumed to be high, as above.
3691 *
3692 * The final value programmed to the register should always be rounded up,
3693 * and include an extra 2 entries to account for clock crossings.
3694 *
3695 * We don't use the sprite, so we can ignore that. And on Crestline we have
3696 * to set the non-SR watermarks to 8.
3697 */
3698 void intel_update_watermarks(struct drm_crtc *crtc)
3699 {
3700 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
3701
3702 if (dev_priv->display.update_wm)
3703 dev_priv->display.update_wm(crtc);
3704 }
3705
3706 void intel_update_sprite_watermarks(struct drm_plane *plane,
3707 struct drm_crtc *crtc,
3708 uint32_t sprite_width,
3709 uint32_t sprite_height,
3710 int pixel_size,
3711 bool enabled, bool scaled)
3712 {
3713 struct drm_i915_private *dev_priv = plane->dev->dev_private;
3714
3715 if (dev_priv->display.update_sprite_wm)
3716 dev_priv->display.update_sprite_wm(plane, crtc,
3717 sprite_width, sprite_height,
3718 pixel_size, enabled, scaled);
3719 }
3720
3721 /**
3722 * Lock protecting IPS related data structures
3723 */
3724 DEFINE_SPINLOCK(mchdev_lock);
3725
3726 /* Global for IPS driver to get at the current i915 device. Protected by
3727 * mchdev_lock. */
3728 static struct drm_i915_private *i915_mch_dev;
3729
3730 bool ironlake_set_drps(struct drm_device *dev, u8 val)
3731 {
3732 struct drm_i915_private *dev_priv = dev->dev_private;
3733 u16 rgvswctl;
3734
3735 assert_spin_locked(&mchdev_lock);
3736
3737 rgvswctl = I915_READ16(MEMSWCTL);
3738 if (rgvswctl & MEMCTL_CMD_STS) {
3739 DRM_DEBUG("gpu busy, RCS change rejected\n");
3740 return false; /* still busy with another command */
3741 }
3742
3743 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
3744 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
3745 I915_WRITE16(MEMSWCTL, rgvswctl);
3746 POSTING_READ16(MEMSWCTL);
3747
3748 rgvswctl |= MEMCTL_CMD_STS;
3749 I915_WRITE16(MEMSWCTL, rgvswctl);
3750
3751 return true;
3752 }
3753
3754 static void ironlake_enable_drps(struct drm_device *dev)
3755 {
3756 struct drm_i915_private *dev_priv = dev->dev_private;
3757 u32 rgvmodectl = I915_READ(MEMMODECTL);
3758 u8 fmax, fmin, fstart, vstart;
3759
3760 spin_lock_irq(&mchdev_lock);
3761
3762 /* Enable temp reporting */
3763 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
3764 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
3765
3766 /* 100ms RC evaluation intervals */
3767 I915_WRITE(RCUPEI, 100000);
3768 I915_WRITE(RCDNEI, 100000);
3769
3770 /* Set max/min thresholds to 90ms and 80ms respectively */
3771 I915_WRITE(RCBMAXAVG, 90000);
3772 I915_WRITE(RCBMINAVG, 80000);
3773
3774 I915_WRITE(MEMIHYST, 1);
3775
3776 /* Set up min, max, and cur for interrupt handling */
3777 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
3778 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
3779 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
3780 MEMMODE_FSTART_SHIFT;
3781
3782 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
3783 PXVFREQ_PX_SHIFT;
3784
3785 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
3786 dev_priv->ips.fstart = fstart;
3787
3788 dev_priv->ips.max_delay = fstart;
3789 dev_priv->ips.min_delay = fmin;
3790 dev_priv->ips.cur_delay = fstart;
3791
3792 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
3793 fmax, fmin, fstart);
3794
3795 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
3796
3797 /*
3798 * Interrupts will be enabled in ironlake_irq_postinstall
3799 */
3800
3801 I915_WRITE(VIDSTART, vstart);
3802 POSTING_READ(VIDSTART);
3803
3804 rgvmodectl |= MEMMODE_SWMODE_EN;
3805 I915_WRITE(MEMMODECTL, rgvmodectl);
3806
3807 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
3808 DRM_ERROR("stuck trying to change perf mode\n");
3809 mdelay(1);
3810
3811 ironlake_set_drps(dev, fstart);
3812
3813 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
3814 I915_READ(0x112e0);
3815 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
3816 dev_priv->ips.last_count2 = I915_READ(0x112f4);
3817 dev_priv->ips.last_time2 = ktime_get_raw_ns();
3818
3819 spin_unlock_irq(&mchdev_lock);
3820 }
3821
3822 static void ironlake_disable_drps(struct drm_device *dev)
3823 {
3824 struct drm_i915_private *dev_priv = dev->dev_private;
3825 u16 rgvswctl;
3826
3827 spin_lock_irq(&mchdev_lock);
3828
3829 rgvswctl = I915_READ16(MEMSWCTL);
3830
3831 /* Ack interrupts, disable EFC interrupt */
3832 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
3833 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
3834 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
3835 I915_WRITE(DEIIR, DE_PCU_EVENT);
3836 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
3837
3838 /* Go back to the starting frequency */
3839 ironlake_set_drps(dev, dev_priv->ips.fstart);
3840 mdelay(1);
3841 rgvswctl |= MEMCTL_CMD_STS;
3842 I915_WRITE(MEMSWCTL, rgvswctl);
3843 mdelay(1);
3844
3845 spin_unlock_irq(&mchdev_lock);
3846 }
3847
3848 /* There's a funny hw issue where the hw returns all 0 when reading from
3849 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3850 * ourselves, instead of doing a rmw cycle (which might result in us clearing
3851 * all limits and the gpu stuck at whatever frequency it is at atm).
3852 */
3853 static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
3854 {
3855 u32 limits;
3856
3857 /* Only set the down limit when we've reached the lowest level to avoid
3858 * getting more interrupts, otherwise leave this clear. This prevents a
3859 * race in the hw when coming out of rc6: There's a tiny window where
3860 * the hw runs at the minimal clock before selecting the desired
3861 * frequency, if the down threshold expires in that window we will not
3862 * receive a down interrupt. */
3863 if (IS_GEN9(dev_priv->dev)) {
3864 limits = (dev_priv->rps.max_freq_softlimit) << 23;
3865 if (val <= dev_priv->rps.min_freq_softlimit)
3866 limits |= (dev_priv->rps.min_freq_softlimit) << 14;
3867 } else {
3868 limits = dev_priv->rps.max_freq_softlimit << 24;
3869 if (val <= dev_priv->rps.min_freq_softlimit)
3870 limits |= dev_priv->rps.min_freq_softlimit << 16;
3871 }
3872
3873 return limits;
3874 }
3875
3876 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
3877 {
3878 int new_power;
3879 u32 threshold_up = 0, threshold_down = 0; /* in % */
3880 u32 ei_up = 0, ei_down = 0;
3881
3882 new_power = dev_priv->rps.power;
3883 switch (dev_priv->rps.power) {
3884 case LOW_POWER:
3885 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
3886 new_power = BETWEEN;
3887 break;
3888
3889 case BETWEEN:
3890 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
3891 new_power = LOW_POWER;
3892 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
3893 new_power = HIGH_POWER;
3894 break;
3895
3896 case HIGH_POWER:
3897 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
3898 new_power = BETWEEN;
3899 break;
3900 }
3901 /* Max/min bins are special */
3902 if (val <= dev_priv->rps.min_freq_softlimit)
3903 new_power = LOW_POWER;
3904 if (val >= dev_priv->rps.max_freq_softlimit)
3905 new_power = HIGH_POWER;
3906 if (new_power == dev_priv->rps.power)
3907 return;
3908
3909 /* Note the units here are not exactly 1us, but 1280ns. */
3910 switch (new_power) {
3911 case LOW_POWER:
3912 /* Upclock if more than 95% busy over 16ms */
3913 ei_up = 16000;
3914 threshold_up = 95;
3915
3916 /* Downclock if less than 85% busy over 32ms */
3917 ei_down = 32000;
3918 threshold_down = 85;
3919 break;
3920
3921 case BETWEEN:
3922 /* Upclock if more than 90% busy over 13ms */
3923 ei_up = 13000;
3924 threshold_up = 90;
3925
3926 /* Downclock if less than 75% busy over 32ms */
3927 ei_down = 32000;
3928 threshold_down = 75;
3929 break;
3930
3931 case HIGH_POWER:
3932 /* Upclock if more than 85% busy over 10ms */
3933 ei_up = 10000;
3934 threshold_up = 85;
3935
3936 /* Downclock if less than 60% busy over 32ms */
3937 ei_down = 32000;
3938 threshold_down = 60;
3939 break;
3940 }
3941
3942 I915_WRITE(GEN6_RP_UP_EI,
3943 GT_INTERVAL_FROM_US(dev_priv, ei_up));
3944 I915_WRITE(GEN6_RP_UP_THRESHOLD,
3945 GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100)));
3946
3947 I915_WRITE(GEN6_RP_DOWN_EI,
3948 GT_INTERVAL_FROM_US(dev_priv, ei_down));
3949 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
3950 GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100)));
3951
3952 I915_WRITE(GEN6_RP_CONTROL,
3953 GEN6_RP_MEDIA_TURBO |
3954 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3955 GEN6_RP_MEDIA_IS_GFX |
3956 GEN6_RP_ENABLE |
3957 GEN6_RP_UP_BUSY_AVG |
3958 GEN6_RP_DOWN_IDLE_AVG);
3959
3960 dev_priv->rps.power = new_power;
3961 dev_priv->rps.up_threshold = threshold_up;
3962 dev_priv->rps.down_threshold = threshold_down;
3963 dev_priv->rps.last_adj = 0;
3964 }
3965
3966 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
3967 {
3968 u32 mask = 0;
3969
3970 if (val > dev_priv->rps.min_freq_softlimit)
3971 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
3972 if (val < dev_priv->rps.max_freq_softlimit)
3973 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
3974
3975 mask &= dev_priv->pm_rps_events;
3976
3977 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
3978 }
3979
3980 /* gen6_set_rps is called to update the frequency request, but should also be
3981 * called when the range (min_delay and max_delay) is modified so that we can
3982 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
3983 static void gen6_set_rps(struct drm_device *dev, u8 val)
3984 {
3985 struct drm_i915_private *dev_priv = dev->dev_private;
3986
3987 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3988 WARN_ON(val > dev_priv->rps.max_freq);
3989 WARN_ON(val < dev_priv->rps.min_freq);
3990
3991 /* min/max delay may still have been modified so be sure to
3992 * write the limits value.
3993 */
3994 if (val != dev_priv->rps.cur_freq) {
3995 gen6_set_rps_thresholds(dev_priv, val);
3996
3997 if (IS_GEN9(dev))
3998 I915_WRITE(GEN6_RPNSWREQ,
3999 GEN9_FREQUENCY(val));
4000 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4001 I915_WRITE(GEN6_RPNSWREQ,
4002 HSW_FREQUENCY(val));
4003 else
4004 I915_WRITE(GEN6_RPNSWREQ,
4005 GEN6_FREQUENCY(val) |
4006 GEN6_OFFSET(0) |
4007 GEN6_AGGRESSIVE_TURBO);
4008 }
4009
4010 /* Make sure we continue to get interrupts
4011 * until we hit the minimum or maximum frequencies.
4012 */
4013 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
4014 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4015
4016 POSTING_READ(GEN6_RPNSWREQ);
4017
4018 dev_priv->rps.cur_freq = val;
4019 trace_intel_gpu_freq_change(val * 50);
4020 }
4021
4022 static void valleyview_set_rps(struct drm_device *dev, u8 val)
4023 {
4024 struct drm_i915_private *dev_priv = dev->dev_private;
4025
4026 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4027 WARN_ON(val > dev_priv->rps.max_freq);
4028 WARN_ON(val < dev_priv->rps.min_freq);
4029
4030 if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1),
4031 "Odd GPU freq value\n"))
4032 val &= ~1;
4033
4034 if (val != dev_priv->rps.cur_freq) {
4035 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
4036 if (!IS_CHERRYVIEW(dev_priv))
4037 gen6_set_rps_thresholds(dev_priv, val);
4038 }
4039
4040 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4041
4042 dev_priv->rps.cur_freq = val;
4043 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4044 }
4045
4046 /* vlv_set_rps_idle: Set the frequency to Rpn if Gfx clocks are down
4047 *
4048 * * If Gfx is Idle, then
4049 * 1. Mask Turbo interrupts
4050 * 2. Bring up Gfx clock
4051 * 3. Change the freq to Rpn and wait till P-Unit updates freq
4052 * 4. Clear the Force GFX CLK ON bit so that Gfx can down
4053 * 5. Unmask Turbo interrupts
4054 */
4055 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4056 {
4057 struct drm_device *dev = dev_priv->dev;
4058 u32 val = dev_priv->rps.idle_freq;
4059
4060 /* CHV and latest VLV don't need to force the gfx clock */
4061 if (IS_CHERRYVIEW(dev) || dev->pdev->revision >= 0xd) {
4062 valleyview_set_rps(dev_priv->dev, val);
4063 return;
4064 }
4065
4066 /*
4067 * When we are idle. Drop to min voltage state.
4068 */
4069
4070 if (dev_priv->rps.cur_freq <= val)
4071 return;
4072
4073 /* Mask turbo interrupt so that they will not come in between */
4074 I915_WRITE(GEN6_PMINTRMSK,
4075 gen6_sanitize_rps_pm_mask(dev_priv, ~0));
4076
4077 vlv_force_gfx_clock(dev_priv, true);
4078
4079 dev_priv->rps.cur_freq = val;
4080
4081 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
4082
4083 if (wait_for(((vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS))
4084 & GENFREQSTATUS) == 0, 100))
4085 DRM_ERROR("timed out waiting for Punit\n");
4086
4087 gen6_set_rps_thresholds(dev_priv, val);
4088 vlv_force_gfx_clock(dev_priv, false);
4089
4090 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4091 }
4092
4093 void gen6_rps_busy(struct drm_i915_private *dev_priv)
4094 {
4095 mutex_lock(&dev_priv->rps.hw_lock);
4096 if (dev_priv->rps.enabled) {
4097 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
4098 gen6_rps_reset_ei(dev_priv);
4099 I915_WRITE(GEN6_PMINTRMSK,
4100 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
4101 }
4102 mutex_unlock(&dev_priv->rps.hw_lock);
4103 }
4104
4105 void gen6_rps_idle(struct drm_i915_private *dev_priv)
4106 {
4107 struct drm_device *dev = dev_priv->dev;
4108
4109 mutex_lock(&dev_priv->rps.hw_lock);
4110 if (dev_priv->rps.enabled) {
4111 if (IS_VALLEYVIEW(dev))
4112 vlv_set_rps_idle(dev_priv);
4113 else
4114 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
4115 dev_priv->rps.last_adj = 0;
4116 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
4117 }
4118
4119 while (!list_empty(&dev_priv->rps.clients))
4120 list_del_init(dev_priv->rps.clients.next);
4121 mutex_unlock(&dev_priv->rps.hw_lock);
4122 }
4123
4124 void gen6_rps_boost(struct drm_i915_private *dev_priv,
4125 struct drm_i915_file_private *file_priv)
4126 {
4127 u32 val;
4128
4129 mutex_lock(&dev_priv->rps.hw_lock);
4130 val = dev_priv->rps.max_freq_softlimit;
4131 if (dev_priv->rps.enabled &&
4132 dev_priv->mm.busy &&
4133 dev_priv->rps.cur_freq < val &&
4134 (file_priv == NULL || list_empty(&file_priv->rps_boost))) {
4135 intel_set_rps(dev_priv->dev, val);
4136 dev_priv->rps.last_adj = 0;
4137
4138 if (file_priv != NULL) {
4139 list_add(&file_priv->rps_boost, &dev_priv->rps.clients);
4140 file_priv->rps_boosts++;
4141 } else
4142 dev_priv->rps.boosts++;
4143 }
4144 mutex_unlock(&dev_priv->rps.hw_lock);
4145 }
4146
4147 void intel_set_rps(struct drm_device *dev, u8 val)
4148 {
4149 if (IS_VALLEYVIEW(dev))
4150 valleyview_set_rps(dev, val);
4151 else
4152 gen6_set_rps(dev, val);
4153 }
4154
4155 static void gen9_disable_rps(struct drm_device *dev)
4156 {
4157 struct drm_i915_private *dev_priv = dev->dev_private;
4158
4159 I915_WRITE(GEN6_RC_CONTROL, 0);
4160 I915_WRITE(GEN9_PG_ENABLE, 0);
4161 }
4162
4163 static void gen6_disable_rps(struct drm_device *dev)
4164 {
4165 struct drm_i915_private *dev_priv = dev->dev_private;
4166
4167 I915_WRITE(GEN6_RC_CONTROL, 0);
4168 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
4169 }
4170
4171 static void cherryview_disable_rps(struct drm_device *dev)
4172 {
4173 struct drm_i915_private *dev_priv = dev->dev_private;
4174
4175 I915_WRITE(GEN6_RC_CONTROL, 0);
4176 }
4177
4178 static void valleyview_disable_rps(struct drm_device *dev)
4179 {
4180 struct drm_i915_private *dev_priv = dev->dev_private;
4181
4182 /* we're doing forcewake before Disabling RC6,
4183 * This what the BIOS expects when going into suspend */
4184 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4185
4186 I915_WRITE(GEN6_RC_CONTROL, 0);
4187
4188 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4189 }
4190
4191 static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
4192 {
4193 if (IS_VALLEYVIEW(dev)) {
4194 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
4195 mode = GEN6_RC_CTL_RC6_ENABLE;
4196 else
4197 mode = 0;
4198 }
4199 if (HAS_RC6p(dev))
4200 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
4201 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
4202 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
4203 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
4204
4205 else
4206 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
4207 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off");
4208 }
4209
4210 static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
4211 {
4212 /* No RC6 before Ironlake */
4213 if (INTEL_INFO(dev)->gen < 5)
4214 return 0;
4215
4216 /* RC6 is only on Ironlake mobile not on desktop */
4217 if (INTEL_INFO(dev)->gen == 5 && !IS_IRONLAKE_M(dev))
4218 return 0;
4219
4220 /* Respect the kernel parameter if it is set */
4221 if (enable_rc6 >= 0) {
4222 int mask;
4223
4224 if (HAS_RC6p(dev))
4225 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
4226 INTEL_RC6pp_ENABLE;
4227 else
4228 mask = INTEL_RC6_ENABLE;
4229
4230 if ((enable_rc6 & mask) != enable_rc6)
4231 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
4232 enable_rc6 & mask, enable_rc6, mask);
4233
4234 return enable_rc6 & mask;
4235 }
4236
4237 /* Disable RC6 on Ironlake */
4238 if (INTEL_INFO(dev)->gen == 5)
4239 return 0;
4240
4241 if (IS_IVYBRIDGE(dev))
4242 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
4243
4244 return INTEL_RC6_ENABLE;
4245 }
4246
4247 int intel_enable_rc6(const struct drm_device *dev)
4248 {
4249 return i915.enable_rc6;
4250 }
4251
4252 static void gen6_init_rps_frequencies(struct drm_device *dev)
4253 {
4254 struct drm_i915_private *dev_priv = dev->dev_private;
4255 uint32_t rp_state_cap;
4256 u32 ddcc_status = 0;
4257 int ret;
4258
4259 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
4260 /* All of these values are in units of 50MHz */
4261 dev_priv->rps.cur_freq = 0;
4262 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
4263 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
4264 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
4265 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
4266 if (IS_SKYLAKE(dev)) {
4267 /* Store the frequency values in 16.66 MHZ units, which is
4268 the natural hardware unit for SKL */
4269 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
4270 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
4271 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
4272 }
4273 /* hw_max = RP0 until we check for overclocking */
4274 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
4275
4276 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
4277 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
4278 ret = sandybridge_pcode_read(dev_priv,
4279 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
4280 &ddcc_status);
4281 if (0 == ret)
4282 dev_priv->rps.efficient_freq =
4283 clamp_t(u8,
4284 ((ddcc_status >> 8) & 0xff),
4285 dev_priv->rps.min_freq,
4286 dev_priv->rps.max_freq);
4287 }
4288
4289 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
4290
4291 /* Preserve min/max settings in case of re-init */
4292 if (dev_priv->rps.max_freq_softlimit == 0)
4293 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4294
4295 if (dev_priv->rps.min_freq_softlimit == 0) {
4296 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4297 dev_priv->rps.min_freq_softlimit =
4298 max_t(int, dev_priv->rps.efficient_freq,
4299 intel_freq_opcode(dev_priv, 450));
4300 else
4301 dev_priv->rps.min_freq_softlimit =
4302 dev_priv->rps.min_freq;
4303 }
4304 }
4305
4306 /* See the Gen9_GT_PM_Programming_Guide doc for the below */
4307 static void gen9_enable_rps(struct drm_device *dev)
4308 {
4309 struct drm_i915_private *dev_priv = dev->dev_private;
4310
4311 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4312
4313 gen6_init_rps_frequencies(dev);
4314
4315 /* Program defaults and thresholds for RPS*/
4316 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4317 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
4318
4319 /* 1 second timeout*/
4320 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
4321 GT_INTERVAL_FROM_US(dev_priv, 1000000));
4322
4323 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
4324
4325 /* Leaning on the below call to gen6_set_rps to program/setup the
4326 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
4327 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
4328 dev_priv->rps.power = HIGH_POWER; /* force a reset */
4329 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
4330
4331 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4332 }
4333
4334 static void gen9_enable_rc6(struct drm_device *dev)
4335 {
4336 struct drm_i915_private *dev_priv = dev->dev_private;
4337 struct intel_engine_cs *ring;
4338 uint32_t rc6_mask = 0;
4339 int unused;
4340
4341 /* 1a: Software RC state - RC0 */
4342 I915_WRITE(GEN6_RC_STATE, 0);
4343
4344 /* 1b: Get forcewake during program sequence. Although the driver
4345 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4346 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4347
4348 /* 2a: Disable RC states. */
4349 I915_WRITE(GEN6_RC_CONTROL, 0);
4350
4351 /* 2b: Program RC6 thresholds.*/
4352 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
4353 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4354 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4355 for_each_ring(ring, dev_priv, unused)
4356 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4357 I915_WRITE(GEN6_RC_SLEEP, 0);
4358 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
4359
4360 /* 2c: Program Coarse Power Gating Policies. */
4361 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
4362 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
4363
4364 /* 3a: Enable RC6 */
4365 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4366 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4367 DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4368 "on" : "off");
4369 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4370 GEN6_RC_CTL_EI_MODE(1) |
4371 rc6_mask);
4372
4373 /*
4374 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
4375 * WaDisableRenderPowerGating:skl,bxt - Render PG need to be disabled with RC6.
4376 */
4377 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4378 GEN9_MEDIA_PG_ENABLE : 0);
4379
4380
4381 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4382
4383 }
4384
4385 static void gen8_enable_rps(struct drm_device *dev)
4386 {
4387 struct drm_i915_private *dev_priv = dev->dev_private;
4388 struct intel_engine_cs *ring;
4389 uint32_t rc6_mask = 0;
4390 int unused;
4391
4392 /* 1a: Software RC state - RC0 */
4393 I915_WRITE(GEN6_RC_STATE, 0);
4394
4395 /* 1c & 1d: Get forcewake during program sequence. Although the driver
4396 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4397 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4398
4399 /* 2a: Disable RC states. */
4400 I915_WRITE(GEN6_RC_CONTROL, 0);
4401
4402 /* Initialize rps frequencies */
4403 gen6_init_rps_frequencies(dev);
4404
4405 /* 2b: Program RC6 thresholds.*/
4406 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4407 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4408 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4409 for_each_ring(ring, dev_priv, unused)
4410 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4411 I915_WRITE(GEN6_RC_SLEEP, 0);
4412 if (IS_BROADWELL(dev))
4413 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
4414 else
4415 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
4416
4417 /* 3: Enable RC6 */
4418 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4419 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4420 intel_print_rc6_info(dev, rc6_mask);
4421 if (IS_BROADWELL(dev))
4422 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4423 GEN7_RC_CTL_TO_MODE |
4424 rc6_mask);
4425 else
4426 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4427 GEN6_RC_CTL_EI_MODE(1) |
4428 rc6_mask);
4429
4430 /* 4 Program defaults and thresholds for RPS*/
4431 I915_WRITE(GEN6_RPNSWREQ,
4432 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4433 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4434 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4435 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
4436 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
4437
4438 /* Docs recommend 900MHz, and 300 MHz respectively */
4439 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
4440 dev_priv->rps.max_freq_softlimit << 24 |
4441 dev_priv->rps.min_freq_softlimit << 16);
4442
4443 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
4444 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
4445 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
4446 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
4447
4448 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4449
4450 /* 5: Enable RPS */
4451 I915_WRITE(GEN6_RP_CONTROL,
4452 GEN6_RP_MEDIA_TURBO |
4453 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4454 GEN6_RP_MEDIA_IS_GFX |
4455 GEN6_RP_ENABLE |
4456 GEN6_RP_UP_BUSY_AVG |
4457 GEN6_RP_DOWN_IDLE_AVG);
4458
4459 /* 6: Ring frequency + overclocking (our driver does this later */
4460
4461 dev_priv->rps.power = HIGH_POWER; /* force a reset */
4462 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
4463
4464 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4465 }
4466
4467 static void gen6_enable_rps(struct drm_device *dev)
4468 {
4469 struct drm_i915_private *dev_priv = dev->dev_private;
4470 struct intel_engine_cs *ring;
4471 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
4472 u32 gtfifodbg;
4473 int rc6_mode;
4474 int i, ret;
4475
4476 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4477
4478 /* Here begins a magic sequence of register writes to enable
4479 * auto-downclocking.
4480 *
4481 * Perhaps there might be some value in exposing these to
4482 * userspace...
4483 */
4484 I915_WRITE(GEN6_RC_STATE, 0);
4485
4486 /* Clear the DBG now so we don't confuse earlier errors */
4487 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
4488 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
4489 I915_WRITE(GTFIFODBG, gtfifodbg);
4490 }
4491
4492 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4493
4494 /* Initialize rps frequencies */
4495 gen6_init_rps_frequencies(dev);
4496
4497 /* disable the counters and set deterministic thresholds */
4498 I915_WRITE(GEN6_RC_CONTROL, 0);
4499
4500 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
4501 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
4502 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
4503 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4504 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4505
4506 for_each_ring(ring, dev_priv, i)
4507 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4508
4509 I915_WRITE(GEN6_RC_SLEEP, 0);
4510 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
4511 if (IS_IVYBRIDGE(dev))
4512 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
4513 else
4514 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
4515 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
4516 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
4517
4518 /* Check if we are enabling RC6 */
4519 rc6_mode = intel_enable_rc6(dev_priv->dev);
4520 if (rc6_mode & INTEL_RC6_ENABLE)
4521 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
4522
4523 /* We don't use those on Haswell */
4524 if (!IS_HASWELL(dev)) {
4525 if (rc6_mode & INTEL_RC6p_ENABLE)
4526 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
4527
4528 if (rc6_mode & INTEL_RC6pp_ENABLE)
4529 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
4530 }
4531
4532 intel_print_rc6_info(dev, rc6_mask);
4533
4534 I915_WRITE(GEN6_RC_CONTROL,
4535 rc6_mask |
4536 GEN6_RC_CTL_EI_MODE(1) |
4537 GEN6_RC_CTL_HW_ENABLE);
4538
4539 /* Power down if completely idle for over 50ms */
4540 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
4541 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4542
4543 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
4544 if (ret)
4545 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
4546
4547 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
4548 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
4549 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
4550 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
4551 (pcu_mbox & 0xff) * 50);
4552 dev_priv->rps.max_freq = pcu_mbox & 0xff;
4553 }
4554
4555 dev_priv->rps.power = HIGH_POWER; /* force a reset */
4556 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
4557
4558 rc6vids = 0;
4559 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
4560 if (IS_GEN6(dev) && ret) {
4561 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
4562 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
4563 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
4564 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
4565 rc6vids &= 0xffff00;
4566 rc6vids |= GEN6_ENCODE_RC6_VID(450);
4567 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
4568 if (ret)
4569 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
4570 }
4571
4572 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4573 }
4574
4575 static void __gen6_update_ring_freq(struct drm_device *dev)
4576 {
4577 struct drm_i915_private *dev_priv = dev->dev_private;
4578 int min_freq = 15;
4579 unsigned int gpu_freq;
4580 unsigned int max_ia_freq, min_ring_freq;
4581 int scaling_factor = 180;
4582 struct cpufreq_policy *policy;
4583
4584 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4585
4586 policy = cpufreq_cpu_get(0);
4587 if (policy) {
4588 max_ia_freq = policy->cpuinfo.max_freq;
4589 cpufreq_cpu_put(policy);
4590 } else {
4591 /*
4592 * Default to measured freq if none found, PCU will ensure we
4593 * don't go over
4594 */
4595 max_ia_freq = tsc_khz;
4596 }
4597
4598 /* Convert from kHz to MHz */
4599 max_ia_freq /= 1000;
4600
4601 min_ring_freq = I915_READ(DCLK) & 0xf;
4602 /* convert DDR frequency from units of 266.6MHz to bandwidth */
4603 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
4604
4605 /*
4606 * For each potential GPU frequency, load a ring frequency we'd like
4607 * to use for memory access. We do this by specifying the IA frequency
4608 * the PCU should use as a reference to determine the ring frequency.
4609 */
4610 for (gpu_freq = dev_priv->rps.max_freq; gpu_freq >= dev_priv->rps.min_freq;
4611 gpu_freq--) {
4612 int diff = dev_priv->rps.max_freq - gpu_freq;
4613 unsigned int ia_freq = 0, ring_freq = 0;
4614
4615 if (INTEL_INFO(dev)->gen >= 8) {
4616 /* max(2 * GT, DDR). NB: GT is 50MHz units */
4617 ring_freq = max(min_ring_freq, gpu_freq);
4618 } else if (IS_HASWELL(dev)) {
4619 ring_freq = mult_frac(gpu_freq, 5, 4);
4620 ring_freq = max(min_ring_freq, ring_freq);
4621 /* leave ia_freq as the default, chosen by cpufreq */
4622 } else {
4623 /* On older processors, there is no separate ring
4624 * clock domain, so in order to boost the bandwidth
4625 * of the ring, we need to upclock the CPU (ia_freq).
4626 *
4627 * For GPU frequencies less than 750MHz,
4628 * just use the lowest ring freq.
4629 */
4630 if (gpu_freq < min_freq)
4631 ia_freq = 800;
4632 else
4633 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
4634 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
4635 }
4636
4637 sandybridge_pcode_write(dev_priv,
4638 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
4639 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
4640 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
4641 gpu_freq);
4642 }
4643 }
4644
4645 void gen6_update_ring_freq(struct drm_device *dev)
4646 {
4647 struct drm_i915_private *dev_priv = dev->dev_private;
4648
4649 if (INTEL_INFO(dev)->gen < 6 || IS_VALLEYVIEW(dev))
4650 return;
4651
4652 mutex_lock(&dev_priv->rps.hw_lock);
4653 __gen6_update_ring_freq(dev);
4654 mutex_unlock(&dev_priv->rps.hw_lock);
4655 }
4656
4657 static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
4658 {
4659 struct drm_device *dev = dev_priv->dev;
4660 u32 val, rp0;
4661
4662 if (dev->pdev->revision >= 0x20) {
4663 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
4664
4665 switch (INTEL_INFO(dev)->eu_total) {
4666 case 8:
4667 /* (2 * 4) config */
4668 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
4669 break;
4670 case 12:
4671 /* (2 * 6) config */
4672 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
4673 break;
4674 case 16:
4675 /* (2 * 8) config */
4676 default:
4677 /* Setting (2 * 8) Min RP0 for any other combination */
4678 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
4679 break;
4680 }
4681 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
4682 } else {
4683 /* For pre-production hardware */
4684 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
4685 rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
4686 PUNIT_GPU_STATUS_MAX_FREQ_MASK;
4687 }
4688 return rp0;
4689 }
4690
4691 static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
4692 {
4693 u32 val, rpe;
4694
4695 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
4696 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
4697
4698 return rpe;
4699 }
4700
4701 static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
4702 {
4703 struct drm_device *dev = dev_priv->dev;
4704 u32 val, rp1;
4705
4706 if (dev->pdev->revision >= 0x20) {
4707 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
4708 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
4709 } else {
4710 /* For pre-production hardware */
4711 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4712 rp1 = ((val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
4713 PUNIT_GPU_STATUS_MAX_FREQ_MASK);
4714 }
4715 return rp1;
4716 }
4717
4718 static int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
4719 {
4720 struct drm_device *dev = dev_priv->dev;
4721 u32 val, rpn;
4722
4723 if (dev->pdev->revision >= 0x20) {
4724 val = vlv_punit_read(dev_priv, FB_GFX_FMIN_AT_VMIN_FUSE);
4725 rpn = ((val >> FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT) &
4726 FB_GFX_FREQ_FUSE_MASK);
4727 } else { /* For pre-production hardware */
4728 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
4729 rpn = ((val >> PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT) &
4730 PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK);
4731 }
4732
4733 return rpn;
4734 }
4735
4736 static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
4737 {
4738 u32 val, rp1;
4739
4740 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
4741
4742 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
4743
4744 return rp1;
4745 }
4746
4747 static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
4748 {
4749 u32 val, rp0;
4750
4751 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
4752
4753 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
4754 /* Clamp to max */
4755 rp0 = min_t(u32, rp0, 0xea);
4756
4757 return rp0;
4758 }
4759
4760 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
4761 {
4762 u32 val, rpe;
4763
4764 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
4765 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
4766 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
4767 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
4768
4769 return rpe;
4770 }
4771
4772 static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
4773 {
4774 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
4775 }
4776
4777 /* Check that the pctx buffer wasn't move under us. */
4778 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
4779 {
4780 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
4781
4782 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
4783 dev_priv->vlv_pctx->stolen->start);
4784 }
4785
4786
4787 /* Check that the pcbr address is not empty. */
4788 static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
4789 {
4790 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
4791
4792 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
4793 }
4794
4795 static void cherryview_setup_pctx(struct drm_device *dev)
4796 {
4797 struct drm_i915_private *dev_priv = dev->dev_private;
4798 unsigned long pctx_paddr, paddr;
4799 struct i915_gtt *gtt = &dev_priv->gtt;
4800 u32 pcbr;
4801 int pctx_size = 32*1024;
4802
4803 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4804
4805 pcbr = I915_READ(VLV_PCBR);
4806 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
4807 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
4808 paddr = (dev_priv->mm.stolen_base +
4809 (gtt->stolen_size - pctx_size));
4810
4811 pctx_paddr = (paddr & (~4095));
4812 I915_WRITE(VLV_PCBR, pctx_paddr);
4813 }
4814
4815 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
4816 }
4817
4818 static void valleyview_setup_pctx(struct drm_device *dev)
4819 {
4820 struct drm_i915_private *dev_priv = dev->dev_private;
4821 struct drm_i915_gem_object *pctx;
4822 unsigned long pctx_paddr;
4823 u32 pcbr;
4824 int pctx_size = 24*1024;
4825
4826 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4827
4828 pcbr = I915_READ(VLV_PCBR);
4829 if (pcbr) {
4830 /* BIOS set it up already, grab the pre-alloc'd space */
4831 int pcbr_offset;
4832
4833 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
4834 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
4835 pcbr_offset,
4836 I915_GTT_OFFSET_NONE,
4837 pctx_size);
4838 goto out;
4839 }
4840
4841 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
4842
4843 /*
4844 * From the Gunit register HAS:
4845 * The Gfx driver is expected to program this register and ensure
4846 * proper allocation within Gfx stolen memory. For example, this
4847 * register should be programmed such than the PCBR range does not
4848 * overlap with other ranges, such as the frame buffer, protected
4849 * memory, or any other relevant ranges.
4850 */
4851 pctx = i915_gem_object_create_stolen(dev, pctx_size);
4852 if (!pctx) {
4853 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
4854 return;
4855 }
4856
4857 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
4858 I915_WRITE(VLV_PCBR, pctx_paddr);
4859
4860 out:
4861 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
4862 dev_priv->vlv_pctx = pctx;
4863 }
4864
4865 static void valleyview_cleanup_pctx(struct drm_device *dev)
4866 {
4867 struct drm_i915_private *dev_priv = dev->dev_private;
4868
4869 if (WARN_ON(!dev_priv->vlv_pctx))
4870 return;
4871
4872 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
4873 dev_priv->vlv_pctx = NULL;
4874 }
4875
4876 static void valleyview_init_gt_powersave(struct drm_device *dev)
4877 {
4878 struct drm_i915_private *dev_priv = dev->dev_private;
4879 u32 val;
4880
4881 valleyview_setup_pctx(dev);
4882
4883 mutex_lock(&dev_priv->rps.hw_lock);
4884
4885 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4886 switch ((val >> 6) & 3) {
4887 case 0:
4888 case 1:
4889 dev_priv->mem_freq = 800;
4890 break;
4891 case 2:
4892 dev_priv->mem_freq = 1066;
4893 break;
4894 case 3:
4895 dev_priv->mem_freq = 1333;
4896 break;
4897 }
4898 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
4899
4900 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
4901 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
4902 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
4903 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4904 dev_priv->rps.max_freq);
4905
4906 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
4907 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
4908 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4909 dev_priv->rps.efficient_freq);
4910
4911 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
4912 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
4913 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
4914 dev_priv->rps.rp1_freq);
4915
4916 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
4917 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
4918 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4919 dev_priv->rps.min_freq);
4920
4921 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
4922
4923 /* Preserve min/max settings in case of re-init */
4924 if (dev_priv->rps.max_freq_softlimit == 0)
4925 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4926
4927 if (dev_priv->rps.min_freq_softlimit == 0)
4928 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
4929
4930 mutex_unlock(&dev_priv->rps.hw_lock);
4931 }
4932
4933 static void cherryview_init_gt_powersave(struct drm_device *dev)
4934 {
4935 struct drm_i915_private *dev_priv = dev->dev_private;
4936 u32 val;
4937
4938 cherryview_setup_pctx(dev);
4939
4940 mutex_lock(&dev_priv->rps.hw_lock);
4941
4942 mutex_lock(&dev_priv->dpio_lock);
4943 val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
4944 mutex_unlock(&dev_priv->dpio_lock);
4945
4946 switch ((val >> 2) & 0x7) {
4947 case 0:
4948 case 1:
4949 dev_priv->rps.cz_freq = 200;
4950 dev_priv->mem_freq = 1600;
4951 break;
4952 case 2:
4953 dev_priv->rps.cz_freq = 267;
4954 dev_priv->mem_freq = 1600;
4955 break;
4956 case 3:
4957 dev_priv->rps.cz_freq = 333;
4958 dev_priv->mem_freq = 2000;
4959 break;
4960 case 4:
4961 dev_priv->rps.cz_freq = 320;
4962 dev_priv->mem_freq = 1600;
4963 break;
4964 case 5:
4965 dev_priv->rps.cz_freq = 400;
4966 dev_priv->mem_freq = 1600;
4967 break;
4968 }
4969 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
4970
4971 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
4972 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
4973 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
4974 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4975 dev_priv->rps.max_freq);
4976
4977 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
4978 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
4979 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4980 dev_priv->rps.efficient_freq);
4981
4982 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
4983 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
4984 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
4985 dev_priv->rps.rp1_freq);
4986
4987 dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv);
4988 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
4989 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4990 dev_priv->rps.min_freq);
4991
4992 WARN_ONCE((dev_priv->rps.max_freq |
4993 dev_priv->rps.efficient_freq |
4994 dev_priv->rps.rp1_freq |
4995 dev_priv->rps.min_freq) & 1,
4996 "Odd GPU freq values\n");
4997
4998 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
4999
5000 /* Preserve min/max settings in case of re-init */
5001 if (dev_priv->rps.max_freq_softlimit == 0)
5002 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5003
5004 if (dev_priv->rps.min_freq_softlimit == 0)
5005 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5006
5007 mutex_unlock(&dev_priv->rps.hw_lock);
5008 }
5009
5010 static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
5011 {
5012 valleyview_cleanup_pctx(dev);
5013 }
5014
5015 static void cherryview_enable_rps(struct drm_device *dev)
5016 {
5017 struct drm_i915_private *dev_priv = dev->dev_private;
5018 struct intel_engine_cs *ring;
5019 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
5020 int i;
5021
5022 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5023
5024 gtfifodbg = I915_READ(GTFIFODBG);
5025 if (gtfifodbg) {
5026 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5027 gtfifodbg);
5028 I915_WRITE(GTFIFODBG, gtfifodbg);
5029 }
5030
5031 cherryview_check_pctx(dev_priv);
5032
5033 /* 1a & 1b: Get forcewake during program sequence. Although the driver
5034 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5035 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5036
5037 /* Disable RC states. */
5038 I915_WRITE(GEN6_RC_CONTROL, 0);
5039
5040 /* 2a: Program RC6 thresholds.*/
5041 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5042 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5043 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5044
5045 for_each_ring(ring, dev_priv, i)
5046 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5047 I915_WRITE(GEN6_RC_SLEEP, 0);
5048
5049 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
5050 I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
5051
5052 /* allows RC6 residency counter to work */
5053 I915_WRITE(VLV_COUNTER_CONTROL,
5054 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
5055 VLV_MEDIA_RC6_COUNT_EN |
5056 VLV_RENDER_RC6_COUNT_EN));
5057
5058 /* For now we assume BIOS is allocating and populating the PCBR */
5059 pcbr = I915_READ(VLV_PCBR);
5060
5061 /* 3: Enable RC6 */
5062 if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
5063 (pcbr >> VLV_PCBR_ADDR_SHIFT))
5064 rc6_mode = GEN7_RC_CTL_TO_MODE;
5065
5066 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5067
5068 /* 4 Program defaults and thresholds for RPS*/
5069 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
5070 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5071 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5072 I915_WRITE(GEN6_RP_UP_EI, 66000);
5073 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5074
5075 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5076
5077 /* 5: Enable RPS */
5078 I915_WRITE(GEN6_RP_CONTROL,
5079 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5080 GEN6_RP_MEDIA_IS_GFX |
5081 GEN6_RP_ENABLE |
5082 GEN6_RP_UP_BUSY_AVG |
5083 GEN6_RP_DOWN_IDLE_AVG);
5084
5085 /* Setting Fixed Bias */
5086 val = VLV_OVERRIDE_EN |
5087 VLV_SOC_TDP_EN |
5088 CHV_BIAS_CPU_50_SOC_50;
5089 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5090
5091 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5092
5093 /* RPS code assumes GPLL is used */
5094 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5095
5096 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & GPLLENABLE ? "yes" : "no");
5097 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5098
5099 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5100 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5101 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
5102 dev_priv->rps.cur_freq);
5103
5104 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5105 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5106 dev_priv->rps.efficient_freq);
5107
5108 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5109
5110 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5111 }
5112
5113 static void valleyview_enable_rps(struct drm_device *dev)
5114 {
5115 struct drm_i915_private *dev_priv = dev->dev_private;
5116 struct intel_engine_cs *ring;
5117 u32 gtfifodbg, val, rc6_mode = 0;
5118 int i;
5119
5120 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5121
5122 valleyview_check_pctx(dev_priv);
5123
5124 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
5125 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5126 gtfifodbg);
5127 I915_WRITE(GTFIFODBG, gtfifodbg);
5128 }
5129
5130 /* If VLV, Forcewake all wells, else re-direct to regular path */
5131 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5132
5133 /* Disable RC states. */
5134 I915_WRITE(GEN6_RC_CONTROL, 0);
5135
5136 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
5137 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5138 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5139 I915_WRITE(GEN6_RP_UP_EI, 66000);
5140 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5141
5142 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5143
5144 I915_WRITE(GEN6_RP_CONTROL,
5145 GEN6_RP_MEDIA_TURBO |
5146 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5147 GEN6_RP_MEDIA_IS_GFX |
5148 GEN6_RP_ENABLE |
5149 GEN6_RP_UP_BUSY_AVG |
5150 GEN6_RP_DOWN_IDLE_CONT);
5151
5152 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
5153 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5154 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5155
5156 for_each_ring(ring, dev_priv, i)
5157 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5158
5159 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
5160
5161 /* allows RC6 residency counter to work */
5162 I915_WRITE(VLV_COUNTER_CONTROL,
5163 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
5164 VLV_RENDER_RC0_COUNT_EN |
5165 VLV_MEDIA_RC6_COUNT_EN |
5166 VLV_RENDER_RC6_COUNT_EN));
5167
5168 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
5169 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
5170
5171 intel_print_rc6_info(dev, rc6_mode);
5172
5173 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5174
5175 /* Setting Fixed Bias */
5176 val = VLV_OVERRIDE_EN |
5177 VLV_SOC_TDP_EN |
5178 VLV_BIAS_CPU_125_SOC_875;
5179 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5180
5181 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5182
5183 /* RPS code assumes GPLL is used */
5184 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5185
5186 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & GPLLENABLE ? "yes" : "no");
5187 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5188
5189 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5190 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5191 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
5192 dev_priv->rps.cur_freq);
5193
5194 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5195 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5196 dev_priv->rps.efficient_freq);
5197
5198 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5199
5200 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5201 }
5202
5203 static unsigned long intel_pxfreq(u32 vidfreq)
5204 {
5205 unsigned long freq;
5206 int div = (vidfreq & 0x3f0000) >> 16;
5207 int post = (vidfreq & 0x3000) >> 12;
5208 int pre = (vidfreq & 0x7);
5209
5210 if (!pre)
5211 return 0;
5212
5213 freq = ((div * 133333) / ((1<<post) * pre));
5214
5215 return freq;
5216 }
5217
5218 static const struct cparams {
5219 u16 i;
5220 u16 t;
5221 u16 m;
5222 u16 c;
5223 } cparams[] = {
5224 { 1, 1333, 301, 28664 },
5225 { 1, 1066, 294, 24460 },
5226 { 1, 800, 294, 25192 },
5227 { 0, 1333, 276, 27605 },
5228 { 0, 1066, 276, 27605 },
5229 { 0, 800, 231, 23784 },
5230 };
5231
5232 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
5233 {
5234 u64 total_count, diff, ret;
5235 u32 count1, count2, count3, m = 0, c = 0;
5236 unsigned long now = jiffies_to_msecs(jiffies), diff1;
5237 int i;
5238
5239 assert_spin_locked(&mchdev_lock);
5240
5241 diff1 = now - dev_priv->ips.last_time1;
5242
5243 /* Prevent division-by-zero if we are asking too fast.
5244 * Also, we don't get interesting results if we are polling
5245 * faster than once in 10ms, so just return the saved value
5246 * in such cases.
5247 */
5248 if (diff1 <= 10)
5249 return dev_priv->ips.chipset_power;
5250
5251 count1 = I915_READ(DMIEC);
5252 count2 = I915_READ(DDREC);
5253 count3 = I915_READ(CSIEC);
5254
5255 total_count = count1 + count2 + count3;
5256
5257 /* FIXME: handle per-counter overflow */
5258 if (total_count < dev_priv->ips.last_count1) {
5259 diff = ~0UL - dev_priv->ips.last_count1;
5260 diff += total_count;
5261 } else {
5262 diff = total_count - dev_priv->ips.last_count1;
5263 }
5264
5265 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
5266 if (cparams[i].i == dev_priv->ips.c_m &&
5267 cparams[i].t == dev_priv->ips.r_t) {
5268 m = cparams[i].m;
5269 c = cparams[i].c;
5270 break;
5271 }
5272 }
5273
5274 diff = div_u64(diff, diff1);
5275 ret = ((m * diff) + c);
5276 ret = div_u64(ret, 10);
5277
5278 dev_priv->ips.last_count1 = total_count;
5279 dev_priv->ips.last_time1 = now;
5280
5281 dev_priv->ips.chipset_power = ret;
5282
5283 return ret;
5284 }
5285
5286 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
5287 {
5288 struct drm_device *dev = dev_priv->dev;
5289 unsigned long val;
5290
5291 if (INTEL_INFO(dev)->gen != 5)
5292 return 0;
5293
5294 spin_lock_irq(&mchdev_lock);
5295
5296 val = __i915_chipset_val(dev_priv);
5297
5298 spin_unlock_irq(&mchdev_lock);
5299
5300 return val;
5301 }
5302
5303 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
5304 {
5305 unsigned long m, x, b;
5306 u32 tsfs;
5307
5308 tsfs = I915_READ(TSFS);
5309
5310 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
5311 x = I915_READ8(TR1);
5312
5313 b = tsfs & TSFS_INTR_MASK;
5314
5315 return ((m * x) / 127) - b;
5316 }
5317
5318 static int _pxvid_to_vd(u8 pxvid)
5319 {
5320 if (pxvid == 0)
5321 return 0;
5322
5323 if (pxvid >= 8 && pxvid < 31)
5324 pxvid = 31;
5325
5326 return (pxvid + 2) * 125;
5327 }
5328
5329 static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
5330 {
5331 struct drm_device *dev = dev_priv->dev;
5332 const int vd = _pxvid_to_vd(pxvid);
5333 const int vm = vd - 1125;
5334
5335 if (INTEL_INFO(dev)->is_mobile)
5336 return vm > 0 ? vm : 0;
5337
5338 return vd;
5339 }
5340
5341 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
5342 {
5343 u64 now, diff, diffms;
5344 u32 count;
5345
5346 assert_spin_locked(&mchdev_lock);
5347
5348 now = ktime_get_raw_ns();
5349 diffms = now - dev_priv->ips.last_time2;
5350 do_div(diffms, NSEC_PER_MSEC);
5351
5352 /* Don't divide by 0 */
5353 if (!diffms)
5354 return;
5355
5356 count = I915_READ(GFXEC);
5357
5358 if (count < dev_priv->ips.last_count2) {
5359 diff = ~0UL - dev_priv->ips.last_count2;
5360 diff += count;
5361 } else {
5362 diff = count - dev_priv->ips.last_count2;
5363 }
5364
5365 dev_priv->ips.last_count2 = count;
5366 dev_priv->ips.last_time2 = now;
5367
5368 /* More magic constants... */
5369 diff = diff * 1181;
5370 diff = div_u64(diff, diffms * 10);
5371 dev_priv->ips.gfx_power = diff;
5372 }
5373
5374 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
5375 {
5376 struct drm_device *dev = dev_priv->dev;
5377
5378 if (INTEL_INFO(dev)->gen != 5)
5379 return;
5380
5381 spin_lock_irq(&mchdev_lock);
5382
5383 __i915_update_gfx_val(dev_priv);
5384
5385 spin_unlock_irq(&mchdev_lock);
5386 }
5387
5388 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
5389 {
5390 unsigned long t, corr, state1, corr2, state2;
5391 u32 pxvid, ext_v;
5392
5393 assert_spin_locked(&mchdev_lock);
5394
5395 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_freq * 4));
5396 pxvid = (pxvid >> 24) & 0x7f;
5397 ext_v = pvid_to_extvid(dev_priv, pxvid);
5398
5399 state1 = ext_v;
5400
5401 t = i915_mch_val(dev_priv);
5402
5403 /* Revel in the empirically derived constants */
5404
5405 /* Correction factor in 1/100000 units */
5406 if (t > 80)
5407 corr = ((t * 2349) + 135940);
5408 else if (t >= 50)
5409 corr = ((t * 964) + 29317);
5410 else /* < 50 */
5411 corr = ((t * 301) + 1004);
5412
5413 corr = corr * ((150142 * state1) / 10000 - 78642);
5414 corr /= 100000;
5415 corr2 = (corr * dev_priv->ips.corr);
5416
5417 state2 = (corr2 * state1) / 10000;
5418 state2 /= 100; /* convert to mW */
5419
5420 __i915_update_gfx_val(dev_priv);
5421
5422 return dev_priv->ips.gfx_power + state2;
5423 }
5424
5425 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
5426 {
5427 struct drm_device *dev = dev_priv->dev;
5428 unsigned long val;
5429
5430 if (INTEL_INFO(dev)->gen != 5)
5431 return 0;
5432
5433 spin_lock_irq(&mchdev_lock);
5434
5435 val = __i915_gfx_val(dev_priv);
5436
5437 spin_unlock_irq(&mchdev_lock);
5438
5439 return val;
5440 }
5441
5442 /**
5443 * i915_read_mch_val - return value for IPS use
5444 *
5445 * Calculate and return a value for the IPS driver to use when deciding whether
5446 * we have thermal and power headroom to increase CPU or GPU power budget.
5447 */
5448 unsigned long i915_read_mch_val(void)
5449 {
5450 struct drm_i915_private *dev_priv;
5451 unsigned long chipset_val, graphics_val, ret = 0;
5452
5453 spin_lock_irq(&mchdev_lock);
5454 if (!i915_mch_dev)
5455 goto out_unlock;
5456 dev_priv = i915_mch_dev;
5457
5458 chipset_val = __i915_chipset_val(dev_priv);
5459 graphics_val = __i915_gfx_val(dev_priv);
5460
5461 ret = chipset_val + graphics_val;
5462
5463 out_unlock:
5464 spin_unlock_irq(&mchdev_lock);
5465
5466 return ret;
5467 }
5468 EXPORT_SYMBOL_GPL(i915_read_mch_val);
5469
5470 /**
5471 * i915_gpu_raise - raise GPU frequency limit
5472 *
5473 * Raise the limit; IPS indicates we have thermal headroom.
5474 */
5475 bool i915_gpu_raise(void)
5476 {
5477 struct drm_i915_private *dev_priv;
5478 bool ret = true;
5479
5480 spin_lock_irq(&mchdev_lock);
5481 if (!i915_mch_dev) {
5482 ret = false;
5483 goto out_unlock;
5484 }
5485 dev_priv = i915_mch_dev;
5486
5487 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
5488 dev_priv->ips.max_delay--;
5489
5490 out_unlock:
5491 spin_unlock_irq(&mchdev_lock);
5492
5493 return ret;
5494 }
5495 EXPORT_SYMBOL_GPL(i915_gpu_raise);
5496
5497 /**
5498 * i915_gpu_lower - lower GPU frequency limit
5499 *
5500 * IPS indicates we're close to a thermal limit, so throttle back the GPU
5501 * frequency maximum.
5502 */
5503 bool i915_gpu_lower(void)
5504 {
5505 struct drm_i915_private *dev_priv;
5506 bool ret = true;
5507
5508 spin_lock_irq(&mchdev_lock);
5509 if (!i915_mch_dev) {
5510 ret = false;
5511 goto out_unlock;
5512 }
5513 dev_priv = i915_mch_dev;
5514
5515 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
5516 dev_priv->ips.max_delay++;
5517
5518 out_unlock:
5519 spin_unlock_irq(&mchdev_lock);
5520
5521 return ret;
5522 }
5523 EXPORT_SYMBOL_GPL(i915_gpu_lower);
5524
5525 /**
5526 * i915_gpu_busy - indicate GPU business to IPS
5527 *
5528 * Tell the IPS driver whether or not the GPU is busy.
5529 */
5530 bool i915_gpu_busy(void)
5531 {
5532 struct drm_i915_private *dev_priv;
5533 struct intel_engine_cs *ring;
5534 bool ret = false;
5535 int i;
5536
5537 spin_lock_irq(&mchdev_lock);
5538 if (!i915_mch_dev)
5539 goto out_unlock;
5540 dev_priv = i915_mch_dev;
5541
5542 for_each_ring(ring, dev_priv, i)
5543 ret |= !list_empty(&ring->request_list);
5544
5545 out_unlock:
5546 spin_unlock_irq(&mchdev_lock);
5547
5548 return ret;
5549 }
5550 EXPORT_SYMBOL_GPL(i915_gpu_busy);
5551
5552 /**
5553 * i915_gpu_turbo_disable - disable graphics turbo
5554 *
5555 * Disable graphics turbo by resetting the max frequency and setting the
5556 * current frequency to the default.
5557 */
5558 bool i915_gpu_turbo_disable(void)
5559 {
5560 struct drm_i915_private *dev_priv;
5561 bool ret = true;
5562
5563 spin_lock_irq(&mchdev_lock);
5564 if (!i915_mch_dev) {
5565 ret = false;
5566 goto out_unlock;
5567 }
5568 dev_priv = i915_mch_dev;
5569
5570 dev_priv->ips.max_delay = dev_priv->ips.fstart;
5571
5572 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
5573 ret = false;
5574
5575 out_unlock:
5576 spin_unlock_irq(&mchdev_lock);
5577
5578 return ret;
5579 }
5580 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
5581
5582 /**
5583 * Tells the intel_ips driver that the i915 driver is now loaded, if
5584 * IPS got loaded first.
5585 *
5586 * This awkward dance is so that neither module has to depend on the
5587 * other in order for IPS to do the appropriate communication of
5588 * GPU turbo limits to i915.
5589 */
5590 static void
5591 ips_ping_for_i915_load(void)
5592 {
5593 void (*link)(void);
5594
5595 link = symbol_get(ips_link_to_i915_driver);
5596 if (link) {
5597 link();
5598 symbol_put(ips_link_to_i915_driver);
5599 }
5600 }
5601
5602 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
5603 {
5604 /* We only register the i915 ips part with intel-ips once everything is
5605 * set up, to avoid intel-ips sneaking in and reading bogus values. */
5606 spin_lock_irq(&mchdev_lock);
5607 i915_mch_dev = dev_priv;
5608 spin_unlock_irq(&mchdev_lock);
5609
5610 ips_ping_for_i915_load();
5611 }
5612
5613 void intel_gpu_ips_teardown(void)
5614 {
5615 spin_lock_irq(&mchdev_lock);
5616 i915_mch_dev = NULL;
5617 spin_unlock_irq(&mchdev_lock);
5618 }
5619
5620 static void intel_init_emon(struct drm_device *dev)
5621 {
5622 struct drm_i915_private *dev_priv = dev->dev_private;
5623 u32 lcfuse;
5624 u8 pxw[16];
5625 int i;
5626
5627 /* Disable to program */
5628 I915_WRITE(ECR, 0);
5629 POSTING_READ(ECR);
5630
5631 /* Program energy weights for various events */
5632 I915_WRITE(SDEW, 0x15040d00);
5633 I915_WRITE(CSIEW0, 0x007f0000);
5634 I915_WRITE(CSIEW1, 0x1e220004);
5635 I915_WRITE(CSIEW2, 0x04000004);
5636
5637 for (i = 0; i < 5; i++)
5638 I915_WRITE(PEW + (i * 4), 0);
5639 for (i = 0; i < 3; i++)
5640 I915_WRITE(DEW + (i * 4), 0);
5641
5642 /* Program P-state weights to account for frequency power adjustment */
5643 for (i = 0; i < 16; i++) {
5644 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
5645 unsigned long freq = intel_pxfreq(pxvidfreq);
5646 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5647 PXVFREQ_PX_SHIFT;
5648 unsigned long val;
5649
5650 val = vid * vid;
5651 val *= (freq / 1000);
5652 val *= 255;
5653 val /= (127*127*900);
5654 if (val > 0xff)
5655 DRM_ERROR("bad pxval: %ld\n", val);
5656 pxw[i] = val;
5657 }
5658 /* Render standby states get 0 weight */
5659 pxw[14] = 0;
5660 pxw[15] = 0;
5661
5662 for (i = 0; i < 4; i++) {
5663 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5664 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
5665 I915_WRITE(PXW + (i * 4), val);
5666 }
5667
5668 /* Adjust magic regs to magic values (more experimental results) */
5669 I915_WRITE(OGW0, 0);
5670 I915_WRITE(OGW1, 0);
5671 I915_WRITE(EG0, 0x00007f00);
5672 I915_WRITE(EG1, 0x0000000e);
5673 I915_WRITE(EG2, 0x000e0000);
5674 I915_WRITE(EG3, 0x68000300);
5675 I915_WRITE(EG4, 0x42000000);
5676 I915_WRITE(EG5, 0x00140031);
5677 I915_WRITE(EG6, 0);
5678 I915_WRITE(EG7, 0);
5679
5680 for (i = 0; i < 8; i++)
5681 I915_WRITE(PXWL + (i * 4), 0);
5682
5683 /* Enable PMON + select events */
5684 I915_WRITE(ECR, 0x80000019);
5685
5686 lcfuse = I915_READ(LCFUSE02);
5687
5688 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
5689 }
5690
5691 void intel_init_gt_powersave(struct drm_device *dev)
5692 {
5693 i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
5694
5695 if (IS_CHERRYVIEW(dev))
5696 cherryview_init_gt_powersave(dev);
5697 else if (IS_VALLEYVIEW(dev))
5698 valleyview_init_gt_powersave(dev);
5699 }
5700
5701 void intel_cleanup_gt_powersave(struct drm_device *dev)
5702 {
5703 if (IS_CHERRYVIEW(dev))
5704 return;
5705 else if (IS_VALLEYVIEW(dev))
5706 valleyview_cleanup_gt_powersave(dev);
5707 }
5708
5709 static void gen6_suspend_rps(struct drm_device *dev)
5710 {
5711 struct drm_i915_private *dev_priv = dev->dev_private;
5712
5713 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
5714
5715 gen6_disable_rps_interrupts(dev);
5716 }
5717
5718 /**
5719 * intel_suspend_gt_powersave - suspend PM work and helper threads
5720 * @dev: drm device
5721 *
5722 * We don't want to disable RC6 or other features here, we just want
5723 * to make sure any work we've queued has finished and won't bother
5724 * us while we're suspended.
5725 */
5726 void intel_suspend_gt_powersave(struct drm_device *dev)
5727 {
5728 struct drm_i915_private *dev_priv = dev->dev_private;
5729
5730 if (INTEL_INFO(dev)->gen < 6)
5731 return;
5732
5733 gen6_suspend_rps(dev);
5734
5735 /* Force GPU to min freq during suspend */
5736 gen6_rps_idle(dev_priv);
5737 }
5738
5739 void intel_disable_gt_powersave(struct drm_device *dev)
5740 {
5741 struct drm_i915_private *dev_priv = dev->dev_private;
5742
5743 if (IS_IRONLAKE_M(dev)) {
5744 ironlake_disable_drps(dev);
5745 } else if (INTEL_INFO(dev)->gen >= 6) {
5746 intel_suspend_gt_powersave(dev);
5747
5748 mutex_lock(&dev_priv->rps.hw_lock);
5749 if (INTEL_INFO(dev)->gen >= 9)
5750 gen9_disable_rps(dev);
5751 else if (IS_CHERRYVIEW(dev))
5752 cherryview_disable_rps(dev);
5753 else if (IS_VALLEYVIEW(dev))
5754 valleyview_disable_rps(dev);
5755 else
5756 gen6_disable_rps(dev);
5757
5758 dev_priv->rps.enabled = false;
5759 mutex_unlock(&dev_priv->rps.hw_lock);
5760 }
5761 }
5762
5763 static void intel_gen6_powersave_work(struct work_struct *work)
5764 {
5765 struct drm_i915_private *dev_priv =
5766 container_of(work, struct drm_i915_private,
5767 rps.delayed_resume_work.work);
5768 struct drm_device *dev = dev_priv->dev;
5769
5770 mutex_lock(&dev_priv->rps.hw_lock);
5771
5772 gen6_reset_rps_interrupts(dev);
5773
5774 if (IS_CHERRYVIEW(dev)) {
5775 cherryview_enable_rps(dev);
5776 } else if (IS_VALLEYVIEW(dev)) {
5777 valleyview_enable_rps(dev);
5778 } else if (INTEL_INFO(dev)->gen >= 9) {
5779 gen9_enable_rc6(dev);
5780 gen9_enable_rps(dev);
5781 __gen6_update_ring_freq(dev);
5782 } else if (IS_BROADWELL(dev)) {
5783 gen8_enable_rps(dev);
5784 __gen6_update_ring_freq(dev);
5785 } else {
5786 gen6_enable_rps(dev);
5787 __gen6_update_ring_freq(dev);
5788 }
5789
5790 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
5791 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
5792
5793 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
5794 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
5795
5796 dev_priv->rps.enabled = true;
5797
5798 gen6_enable_rps_interrupts(dev);
5799
5800 mutex_unlock(&dev_priv->rps.hw_lock);
5801
5802 intel_runtime_pm_put(dev_priv);
5803 }
5804
5805 void intel_enable_gt_powersave(struct drm_device *dev)
5806 {
5807 struct drm_i915_private *dev_priv = dev->dev_private;
5808
5809 /* Powersaving is controlled by the host when inside a VM */
5810 if (intel_vgpu_active(dev))
5811 return;
5812
5813 if (IS_IRONLAKE_M(dev)) {
5814 mutex_lock(&dev->struct_mutex);
5815 ironlake_enable_drps(dev);
5816 intel_init_emon(dev);
5817 mutex_unlock(&dev->struct_mutex);
5818 } else if (INTEL_INFO(dev)->gen >= 6) {
5819 /*
5820 * PCU communication is slow and this doesn't need to be
5821 * done at any specific time, so do this out of our fast path
5822 * to make resume and init faster.
5823 *
5824 * We depend on the HW RC6 power context save/restore
5825 * mechanism when entering D3 through runtime PM suspend. So
5826 * disable RPM until RPS/RC6 is properly setup. We can only
5827 * get here via the driver load/system resume/runtime resume
5828 * paths, so the _noresume version is enough (and in case of
5829 * runtime resume it's necessary).
5830 */
5831 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
5832 round_jiffies_up_relative(HZ)))
5833 intel_runtime_pm_get_noresume(dev_priv);
5834 }
5835 }
5836
5837 void intel_reset_gt_powersave(struct drm_device *dev)
5838 {
5839 struct drm_i915_private *dev_priv = dev->dev_private;
5840
5841 if (INTEL_INFO(dev)->gen < 6)
5842 return;
5843
5844 gen6_suspend_rps(dev);
5845 dev_priv->rps.enabled = false;
5846 }
5847
5848 static void ibx_init_clock_gating(struct drm_device *dev)
5849 {
5850 struct drm_i915_private *dev_priv = dev->dev_private;
5851
5852 /*
5853 * On Ibex Peak and Cougar Point, we need to disable clock
5854 * gating for the panel power sequencer or it will fail to
5855 * start up when no ports are active.
5856 */
5857 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
5858 }
5859
5860 static void g4x_disable_trickle_feed(struct drm_device *dev)
5861 {
5862 struct drm_i915_private *dev_priv = dev->dev_private;
5863 int pipe;
5864
5865 for_each_pipe(dev_priv, pipe) {
5866 I915_WRITE(DSPCNTR(pipe),
5867 I915_READ(DSPCNTR(pipe)) |
5868 DISPPLANE_TRICKLE_FEED_DISABLE);
5869 intel_flush_primary_plane(dev_priv, pipe);
5870 }
5871 }
5872
5873 static void ilk_init_lp_watermarks(struct drm_device *dev)
5874 {
5875 struct drm_i915_private *dev_priv = dev->dev_private;
5876
5877 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
5878 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
5879 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
5880
5881 /*
5882 * Don't touch WM1S_LP_EN here.
5883 * Doing so could cause underruns.
5884 */
5885 }
5886
5887 static void ironlake_init_clock_gating(struct drm_device *dev)
5888 {
5889 struct drm_i915_private *dev_priv = dev->dev_private;
5890 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
5891
5892 /*
5893 * Required for FBC
5894 * WaFbcDisableDpfcClockGating:ilk
5895 */
5896 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
5897 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
5898 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
5899
5900 I915_WRITE(PCH_3DCGDIS0,
5901 MARIUNIT_CLOCK_GATE_DISABLE |
5902 SVSMUNIT_CLOCK_GATE_DISABLE);
5903 I915_WRITE(PCH_3DCGDIS1,
5904 VFMUNIT_CLOCK_GATE_DISABLE);
5905
5906 /*
5907 * According to the spec the following bits should be set in
5908 * order to enable memory self-refresh
5909 * The bit 22/21 of 0x42004
5910 * The bit 5 of 0x42020
5911 * The bit 15 of 0x45000
5912 */
5913 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5914 (I915_READ(ILK_DISPLAY_CHICKEN2) |
5915 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
5916 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
5917 I915_WRITE(DISP_ARB_CTL,
5918 (I915_READ(DISP_ARB_CTL) |
5919 DISP_FBC_WM_DIS));
5920
5921 ilk_init_lp_watermarks(dev);
5922
5923 /*
5924 * Based on the document from hardware guys the following bits
5925 * should be set unconditionally in order to enable FBC.
5926 * The bit 22 of 0x42000
5927 * The bit 22 of 0x42004
5928 * The bit 7,8,9 of 0x42020.
5929 */
5930 if (IS_IRONLAKE_M(dev)) {
5931 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
5932 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5933 I915_READ(ILK_DISPLAY_CHICKEN1) |
5934 ILK_FBCQ_DIS);
5935 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5936 I915_READ(ILK_DISPLAY_CHICKEN2) |
5937 ILK_DPARB_GATE);
5938 }
5939
5940 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
5941
5942 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5943 I915_READ(ILK_DISPLAY_CHICKEN2) |
5944 ILK_ELPIN_409_SELECT);
5945 I915_WRITE(_3D_CHICKEN2,
5946 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
5947 _3D_CHICKEN2_WM_READ_PIPELINED);
5948
5949 /* WaDisableRenderCachePipelinedFlush:ilk */
5950 I915_WRITE(CACHE_MODE_0,
5951 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
5952
5953 /* WaDisable_RenderCache_OperationalFlush:ilk */
5954 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5955
5956 g4x_disable_trickle_feed(dev);
5957
5958 ibx_init_clock_gating(dev);
5959 }
5960
5961 static void cpt_init_clock_gating(struct drm_device *dev)
5962 {
5963 struct drm_i915_private *dev_priv = dev->dev_private;
5964 int pipe;
5965 uint32_t val;
5966
5967 /*
5968 * On Ibex Peak and Cougar Point, we need to disable clock
5969 * gating for the panel power sequencer or it will fail to
5970 * start up when no ports are active.
5971 */
5972 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
5973 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
5974 PCH_CPUNIT_CLOCK_GATE_DISABLE);
5975 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
5976 DPLS_EDP_PPS_FIX_DIS);
5977 /* The below fixes the weird display corruption, a few pixels shifted
5978 * downward, on (only) LVDS of some HP laptops with IVY.
5979 */
5980 for_each_pipe(dev_priv, pipe) {
5981 val = I915_READ(TRANS_CHICKEN2(pipe));
5982 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
5983 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
5984 if (dev_priv->vbt.fdi_rx_polarity_inverted)
5985 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
5986 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
5987 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
5988 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
5989 I915_WRITE(TRANS_CHICKEN2(pipe), val);
5990 }
5991 /* WADP0ClockGatingDisable */
5992 for_each_pipe(dev_priv, pipe) {
5993 I915_WRITE(TRANS_CHICKEN1(pipe),
5994 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
5995 }
5996 }
5997
5998 static void gen6_check_mch_setup(struct drm_device *dev)
5999 {
6000 struct drm_i915_private *dev_priv = dev->dev_private;
6001 uint32_t tmp;
6002
6003 tmp = I915_READ(MCH_SSKPD);
6004 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6005 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6006 tmp);
6007 }
6008
6009 static void gen6_init_clock_gating(struct drm_device *dev)
6010 {
6011 struct drm_i915_private *dev_priv = dev->dev_private;
6012 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6013
6014 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6015
6016 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6017 I915_READ(ILK_DISPLAY_CHICKEN2) |
6018 ILK_ELPIN_409_SELECT);
6019
6020 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
6021 I915_WRITE(_3D_CHICKEN,
6022 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
6023
6024 /* WaDisable_RenderCache_OperationalFlush:snb */
6025 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6026
6027 /*
6028 * BSpec recoomends 8x4 when MSAA is used,
6029 * however in practice 16x4 seems fastest.
6030 *
6031 * Note that PS/WM thread counts depend on the WIZ hashing
6032 * disable bit, which we don't touch here, but it's good
6033 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6034 */
6035 I915_WRITE(GEN6_GT_MODE,
6036 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6037
6038 ilk_init_lp_watermarks(dev);
6039
6040 I915_WRITE(CACHE_MODE_0,
6041 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6042
6043 I915_WRITE(GEN6_UCGCTL1,
6044 I915_READ(GEN6_UCGCTL1) |
6045 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
6046 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6047
6048 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
6049 * gating disable must be set. Failure to set it results in
6050 * flickering pixels due to Z write ordering failures after
6051 * some amount of runtime in the Mesa "fire" demo, and Unigine
6052 * Sanctuary and Tropics, and apparently anything else with
6053 * alpha test or pixel discard.
6054 *
6055 * According to the spec, bit 11 (RCCUNIT) must also be set,
6056 * but we didn't debug actual testcases to find it out.
6057 *
6058 * WaDisableRCCUnitClockGating:snb
6059 * WaDisableRCPBUnitClockGating:snb
6060 */
6061 I915_WRITE(GEN6_UCGCTL2,
6062 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
6063 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
6064
6065 /* WaStripsFansDisableFastClipPerformanceFix:snb */
6066 I915_WRITE(_3D_CHICKEN3,
6067 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6068
6069 /*
6070 * Bspec says:
6071 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
6072 * 3DSTATE_SF number of SF output attributes is more than 16."
6073 */
6074 I915_WRITE(_3D_CHICKEN3,
6075 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
6076
6077 /*
6078 * According to the spec the following bits should be
6079 * set in order to enable memory self-refresh and fbc:
6080 * The bit21 and bit22 of 0x42000
6081 * The bit21 and bit22 of 0x42004
6082 * The bit5 and bit7 of 0x42020
6083 * The bit14 of 0x70180
6084 * The bit14 of 0x71180
6085 *
6086 * WaFbcAsynchFlipDisableFbcQueue:snb
6087 */
6088 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6089 I915_READ(ILK_DISPLAY_CHICKEN1) |
6090 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6091 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6092 I915_READ(ILK_DISPLAY_CHICKEN2) |
6093 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
6094 I915_WRITE(ILK_DSPCLK_GATE_D,
6095 I915_READ(ILK_DSPCLK_GATE_D) |
6096 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
6097 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6098
6099 g4x_disable_trickle_feed(dev);
6100
6101 cpt_init_clock_gating(dev);
6102
6103 gen6_check_mch_setup(dev);
6104 }
6105
6106 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
6107 {
6108 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
6109
6110 /*
6111 * WaVSThreadDispatchOverride:ivb,vlv
6112 *
6113 * This actually overrides the dispatch
6114 * mode for all thread types.
6115 */
6116 reg &= ~GEN7_FF_SCHED_MASK;
6117 reg |= GEN7_FF_TS_SCHED_HW;
6118 reg |= GEN7_FF_VS_SCHED_HW;
6119 reg |= GEN7_FF_DS_SCHED_HW;
6120
6121 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
6122 }
6123
6124 static void lpt_init_clock_gating(struct drm_device *dev)
6125 {
6126 struct drm_i915_private *dev_priv = dev->dev_private;
6127
6128 /*
6129 * TODO: this bit should only be enabled when really needed, then
6130 * disabled when not needed anymore in order to save power.
6131 */
6132 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
6133 I915_WRITE(SOUTH_DSPCLK_GATE_D,
6134 I915_READ(SOUTH_DSPCLK_GATE_D) |
6135 PCH_LP_PARTITION_LEVEL_DISABLE);
6136
6137 /* WADPOClockGatingDisable:hsw */
6138 I915_WRITE(_TRANSA_CHICKEN1,
6139 I915_READ(_TRANSA_CHICKEN1) |
6140 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6141 }
6142
6143 static void lpt_suspend_hw(struct drm_device *dev)
6144 {
6145 struct drm_i915_private *dev_priv = dev->dev_private;
6146
6147 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6148 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
6149
6150 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6151 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6152 }
6153 }
6154
6155 static void broadwell_init_clock_gating(struct drm_device *dev)
6156 {
6157 struct drm_i915_private *dev_priv = dev->dev_private;
6158 enum pipe pipe;
6159
6160 I915_WRITE(WM3_LP_ILK, 0);
6161 I915_WRITE(WM2_LP_ILK, 0);
6162 I915_WRITE(WM1_LP_ILK, 0);
6163
6164 /* WaSwitchSolVfFArbitrationPriority:bdw */
6165 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6166
6167 /* WaPsrDPAMaskVBlankInSRD:bdw */
6168 I915_WRITE(CHICKEN_PAR1_1,
6169 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
6170
6171 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
6172 for_each_pipe(dev_priv, pipe) {
6173 I915_WRITE(CHICKEN_PIPESL_1(pipe),
6174 I915_READ(CHICKEN_PIPESL_1(pipe)) |
6175 BDW_DPRS_MASK_VBLANK_SRD);
6176 }
6177
6178 /* WaVSRefCountFullforceMissDisable:bdw */
6179 /* WaDSRefCountFullforceMissDisable:bdw */
6180 I915_WRITE(GEN7_FF_THREAD_MODE,
6181 I915_READ(GEN7_FF_THREAD_MODE) &
6182 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
6183
6184 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6185 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
6186
6187 /* WaDisableSDEUnitClockGating:bdw */
6188 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6189 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6190
6191 lpt_init_clock_gating(dev);
6192 }
6193
6194 static void haswell_init_clock_gating(struct drm_device *dev)
6195 {
6196 struct drm_i915_private *dev_priv = dev->dev_private;
6197
6198 ilk_init_lp_watermarks(dev);
6199
6200 /* L3 caching of data atomics doesn't work -- disable it. */
6201 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
6202 I915_WRITE(HSW_ROW_CHICKEN3,
6203 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
6204
6205 /* This is required by WaCatErrorRejectionIssue:hsw */
6206 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6207 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6208 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6209
6210 /* WaVSRefCountFullforceMissDisable:hsw */
6211 I915_WRITE(GEN7_FF_THREAD_MODE,
6212 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
6213
6214 /* WaDisable_RenderCache_OperationalFlush:hsw */
6215 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6216
6217 /* enable HiZ Raw Stall Optimization */
6218 I915_WRITE(CACHE_MODE_0_GEN7,
6219 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6220
6221 /* WaDisable4x2SubspanOptimization:hsw */
6222 I915_WRITE(CACHE_MODE_1,
6223 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6224
6225 /*
6226 * BSpec recommends 8x4 when MSAA is used,
6227 * however in practice 16x4 seems fastest.
6228 *
6229 * Note that PS/WM thread counts depend on the WIZ hashing
6230 * disable bit, which we don't touch here, but it's good
6231 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6232 */
6233 I915_WRITE(GEN7_GT_MODE,
6234 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6235
6236 /* WaSampleCChickenBitEnable:hsw */
6237 I915_WRITE(HALF_SLICE_CHICKEN3,
6238 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
6239
6240 /* WaSwitchSolVfFArbitrationPriority:hsw */
6241 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6242
6243 /* WaRsPkgCStateDisplayPMReq:hsw */
6244 I915_WRITE(CHICKEN_PAR1_1,
6245 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
6246
6247 lpt_init_clock_gating(dev);
6248 }
6249
6250 static void ivybridge_init_clock_gating(struct drm_device *dev)
6251 {
6252 struct drm_i915_private *dev_priv = dev->dev_private;
6253 uint32_t snpcr;
6254
6255 ilk_init_lp_watermarks(dev);
6256
6257 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6258
6259 /* WaDisableEarlyCull:ivb */
6260 I915_WRITE(_3D_CHICKEN3,
6261 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6262
6263 /* WaDisableBackToBackFlipFix:ivb */
6264 I915_WRITE(IVB_CHICKEN3,
6265 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6266 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6267
6268 /* WaDisablePSDDualDispatchEnable:ivb */
6269 if (IS_IVB_GT1(dev))
6270 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6271 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
6272
6273 /* WaDisable_RenderCache_OperationalFlush:ivb */
6274 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6275
6276 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6277 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
6278 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
6279
6280 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6281 I915_WRITE(GEN7_L3CNTLREG1,
6282 GEN7_WA_FOR_GEN7_L3_CONTROL);
6283 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
6284 GEN7_WA_L3_CHICKEN_MODE);
6285 if (IS_IVB_GT1(dev))
6286 I915_WRITE(GEN7_ROW_CHICKEN2,
6287 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6288 else {
6289 /* must write both registers */
6290 I915_WRITE(GEN7_ROW_CHICKEN2,
6291 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6292 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
6293 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6294 }
6295
6296 /* WaForceL3Serialization:ivb */
6297 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6298 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6299
6300 /*
6301 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6302 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
6303 */
6304 I915_WRITE(GEN6_UCGCTL2,
6305 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
6306
6307 /* This is required by WaCatErrorRejectionIssue:ivb */
6308 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6309 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6310 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6311
6312 g4x_disable_trickle_feed(dev);
6313
6314 gen7_setup_fixed_func_scheduler(dev_priv);
6315
6316 if (0) { /* causes HiZ corruption on ivb:gt1 */
6317 /* enable HiZ Raw Stall Optimization */
6318 I915_WRITE(CACHE_MODE_0_GEN7,
6319 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6320 }
6321
6322 /* WaDisable4x2SubspanOptimization:ivb */
6323 I915_WRITE(CACHE_MODE_1,
6324 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6325
6326 /*
6327 * BSpec recommends 8x4 when MSAA is used,
6328 * however in practice 16x4 seems fastest.
6329 *
6330 * Note that PS/WM thread counts depend on the WIZ hashing
6331 * disable bit, which we don't touch here, but it's good
6332 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6333 */
6334 I915_WRITE(GEN7_GT_MODE,
6335 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6336
6337 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
6338 snpcr &= ~GEN6_MBC_SNPCR_MASK;
6339 snpcr |= GEN6_MBC_SNPCR_MED;
6340 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
6341
6342 if (!HAS_PCH_NOP(dev))
6343 cpt_init_clock_gating(dev);
6344
6345 gen6_check_mch_setup(dev);
6346 }
6347
6348 static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
6349 {
6350 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6351
6352 /*
6353 * Disable trickle feed and enable pnd deadline calculation
6354 */
6355 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6356 I915_WRITE(CBR1_VLV, 0);
6357 }
6358
6359 static void valleyview_init_clock_gating(struct drm_device *dev)
6360 {
6361 struct drm_i915_private *dev_priv = dev->dev_private;
6362
6363 vlv_init_display_clock_gating(dev_priv);
6364
6365 /* WaDisableEarlyCull:vlv */
6366 I915_WRITE(_3D_CHICKEN3,
6367 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6368
6369 /* WaDisableBackToBackFlipFix:vlv */
6370 I915_WRITE(IVB_CHICKEN3,
6371 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6372 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6373
6374 /* WaPsdDispatchEnable:vlv */
6375 /* WaDisablePSDDualDispatchEnable:vlv */
6376 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6377 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
6378 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
6379
6380 /* WaDisable_RenderCache_OperationalFlush:vlv */
6381 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6382
6383 /* WaForceL3Serialization:vlv */
6384 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6385 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6386
6387 /* WaDisableDopClockGating:vlv */
6388 I915_WRITE(GEN7_ROW_CHICKEN2,
6389 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6390
6391 /* This is required by WaCatErrorRejectionIssue:vlv */
6392 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6393 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6394 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6395
6396 gen7_setup_fixed_func_scheduler(dev_priv);
6397
6398 /*
6399 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6400 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
6401 */
6402 I915_WRITE(GEN6_UCGCTL2,
6403 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
6404
6405 /* WaDisableL3Bank2xClockGate:vlv
6406 * Disabling L3 clock gating- MMIO 940c[25] = 1
6407 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
6408 I915_WRITE(GEN7_UCGCTL4,
6409 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
6410
6411 /*
6412 * BSpec says this must be set, even though
6413 * WaDisable4x2SubspanOptimization isn't listed for VLV.
6414 */
6415 I915_WRITE(CACHE_MODE_1,
6416 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6417
6418 /*
6419 * BSpec recommends 8x4 when MSAA is used,
6420 * however in practice 16x4 seems fastest.
6421 *
6422 * Note that PS/WM thread counts depend on the WIZ hashing
6423 * disable bit, which we don't touch here, but it's good
6424 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6425 */
6426 I915_WRITE(GEN7_GT_MODE,
6427 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6428
6429 /*
6430 * WaIncreaseL3CreditsForVLVB0:vlv
6431 * This is the hardware default actually.
6432 */
6433 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
6434
6435 /*
6436 * WaDisableVLVClockGating_VBIIssue:vlv
6437 * Disable clock gating on th GCFG unit to prevent a delay
6438 * in the reporting of vblank events.
6439 */
6440 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6441 }
6442
6443 static void cherryview_init_clock_gating(struct drm_device *dev)
6444 {
6445 struct drm_i915_private *dev_priv = dev->dev_private;
6446
6447 vlv_init_display_clock_gating(dev_priv);
6448
6449 /* WaVSRefCountFullforceMissDisable:chv */
6450 /* WaDSRefCountFullforceMissDisable:chv */
6451 I915_WRITE(GEN7_FF_THREAD_MODE,
6452 I915_READ(GEN7_FF_THREAD_MODE) &
6453 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
6454
6455 /* WaDisableSemaphoreAndSyncFlipWait:chv */
6456 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6457 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
6458
6459 /* WaDisableCSUnitClockGating:chv */
6460 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
6461 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6462
6463 /* WaDisableSDEUnitClockGating:chv */
6464 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6465 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6466 }
6467
6468 static void g4x_init_clock_gating(struct drm_device *dev)
6469 {
6470 struct drm_i915_private *dev_priv = dev->dev_private;
6471 uint32_t dspclk_gate;
6472
6473 I915_WRITE(RENCLK_GATE_D1, 0);
6474 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
6475 GS_UNIT_CLOCK_GATE_DISABLE |
6476 CL_UNIT_CLOCK_GATE_DISABLE);
6477 I915_WRITE(RAMCLK_GATE_D, 0);
6478 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
6479 OVRUNIT_CLOCK_GATE_DISABLE |
6480 OVCUNIT_CLOCK_GATE_DISABLE;
6481 if (IS_GM45(dev))
6482 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
6483 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
6484
6485 /* WaDisableRenderCachePipelinedFlush */
6486 I915_WRITE(CACHE_MODE_0,
6487 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6488
6489 /* WaDisable_RenderCache_OperationalFlush:g4x */
6490 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6491
6492 g4x_disable_trickle_feed(dev);
6493 }
6494
6495 static void crestline_init_clock_gating(struct drm_device *dev)
6496 {
6497 struct drm_i915_private *dev_priv = dev->dev_private;
6498
6499 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
6500 I915_WRITE(RENCLK_GATE_D2, 0);
6501 I915_WRITE(DSPCLK_GATE_D, 0);
6502 I915_WRITE(RAMCLK_GATE_D, 0);
6503 I915_WRITE16(DEUC, 0);
6504 I915_WRITE(MI_ARB_STATE,
6505 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6506
6507 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6508 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6509 }
6510
6511 static void broadwater_init_clock_gating(struct drm_device *dev)
6512 {
6513 struct drm_i915_private *dev_priv = dev->dev_private;
6514
6515 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
6516 I965_RCC_CLOCK_GATE_DISABLE |
6517 I965_RCPB_CLOCK_GATE_DISABLE |
6518 I965_ISC_CLOCK_GATE_DISABLE |
6519 I965_FBC_CLOCK_GATE_DISABLE);
6520 I915_WRITE(RENCLK_GATE_D2, 0);
6521 I915_WRITE(MI_ARB_STATE,
6522 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6523
6524 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6525 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6526 }
6527
6528 static void gen3_init_clock_gating(struct drm_device *dev)
6529 {
6530 struct drm_i915_private *dev_priv = dev->dev_private;
6531 u32 dstate = I915_READ(D_STATE);
6532
6533 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
6534 DSTATE_DOT_CLOCK_GATING;
6535 I915_WRITE(D_STATE, dstate);
6536
6537 if (IS_PINEVIEW(dev))
6538 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
6539
6540 /* IIR "flip pending" means done if this bit is set */
6541 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
6542
6543 /* interrupts should cause a wake up from C3 */
6544 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
6545
6546 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
6547 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
6548
6549 I915_WRITE(MI_ARB_STATE,
6550 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6551 }
6552
6553 static void i85x_init_clock_gating(struct drm_device *dev)
6554 {
6555 struct drm_i915_private *dev_priv = dev->dev_private;
6556
6557 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
6558
6559 /* interrupts should cause a wake up from C3 */
6560 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
6561 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
6562
6563 I915_WRITE(MEM_MODE,
6564 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
6565 }
6566
6567 static void i830_init_clock_gating(struct drm_device *dev)
6568 {
6569 struct drm_i915_private *dev_priv = dev->dev_private;
6570
6571 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
6572
6573 I915_WRITE(MEM_MODE,
6574 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
6575 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
6576 }
6577
6578 void intel_init_clock_gating(struct drm_device *dev)
6579 {
6580 struct drm_i915_private *dev_priv = dev->dev_private;
6581
6582 if (dev_priv->display.init_clock_gating)
6583 dev_priv->display.init_clock_gating(dev);
6584 }
6585
6586 void intel_suspend_hw(struct drm_device *dev)
6587 {
6588 if (HAS_PCH_LPT(dev))
6589 lpt_suspend_hw(dev);
6590 }
6591
6592 /* Set up chip specific power management-related functions */
6593 void intel_init_pm(struct drm_device *dev)
6594 {
6595 struct drm_i915_private *dev_priv = dev->dev_private;
6596
6597 intel_fbc_init(dev_priv);
6598
6599 /* For cxsr */
6600 if (IS_PINEVIEW(dev))
6601 i915_pineview_get_mem_freq(dev);
6602 else if (IS_GEN5(dev))
6603 i915_ironlake_get_mem_freq(dev);
6604
6605 /* For FIFO watermark updates */
6606 if (INTEL_INFO(dev)->gen >= 9) {
6607 skl_setup_wm_latency(dev);
6608
6609 if (IS_BROXTON(dev))
6610 dev_priv->display.init_clock_gating =
6611 bxt_init_clock_gating;
6612 else if (IS_SKYLAKE(dev))
6613 dev_priv->display.init_clock_gating =
6614 skl_init_clock_gating;
6615 dev_priv->display.update_wm = skl_update_wm;
6616 dev_priv->display.update_sprite_wm = skl_update_sprite_wm;
6617 } else if (HAS_PCH_SPLIT(dev)) {
6618 ilk_setup_wm_latency(dev);
6619
6620 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
6621 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
6622 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
6623 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
6624 dev_priv->display.update_wm = ilk_update_wm;
6625 dev_priv->display.update_sprite_wm = ilk_update_sprite_wm;
6626 } else {
6627 DRM_DEBUG_KMS("Failed to read display plane latency. "
6628 "Disable CxSR\n");
6629 }
6630
6631 if (IS_GEN5(dev))
6632 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
6633 else if (IS_GEN6(dev))
6634 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
6635 else if (IS_IVYBRIDGE(dev))
6636 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
6637 else if (IS_HASWELL(dev))
6638 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
6639 else if (INTEL_INFO(dev)->gen == 8)
6640 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
6641 } else if (IS_CHERRYVIEW(dev)) {
6642 dev_priv->display.update_wm = valleyview_update_wm;
6643 dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;
6644 dev_priv->display.init_clock_gating =
6645 cherryview_init_clock_gating;
6646 } else if (IS_VALLEYVIEW(dev)) {
6647 dev_priv->display.update_wm = valleyview_update_wm;
6648 dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;
6649 dev_priv->display.init_clock_gating =
6650 valleyview_init_clock_gating;
6651 } else if (IS_PINEVIEW(dev)) {
6652 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
6653 dev_priv->is_ddr3,
6654 dev_priv->fsb_freq,
6655 dev_priv->mem_freq)) {
6656 DRM_INFO("failed to find known CxSR latency "
6657 "(found ddr%s fsb freq %d, mem freq %d), "
6658 "disabling CxSR\n",
6659 (dev_priv->is_ddr3 == 1) ? "3" : "2",
6660 dev_priv->fsb_freq, dev_priv->mem_freq);
6661 /* Disable CxSR and never update its watermark again */
6662 intel_set_memory_cxsr(dev_priv, false);
6663 dev_priv->display.update_wm = NULL;
6664 } else
6665 dev_priv->display.update_wm = pineview_update_wm;
6666 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6667 } else if (IS_G4X(dev)) {
6668 dev_priv->display.update_wm = g4x_update_wm;
6669 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
6670 } else if (IS_GEN4(dev)) {
6671 dev_priv->display.update_wm = i965_update_wm;
6672 if (IS_CRESTLINE(dev))
6673 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
6674 else if (IS_BROADWATER(dev))
6675 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
6676 } else if (IS_GEN3(dev)) {
6677 dev_priv->display.update_wm = i9xx_update_wm;
6678 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6679 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6680 } else if (IS_GEN2(dev)) {
6681 if (INTEL_INFO(dev)->num_pipes == 1) {
6682 dev_priv->display.update_wm = i845_update_wm;
6683 dev_priv->display.get_fifo_size = i845_get_fifo_size;
6684 } else {
6685 dev_priv->display.update_wm = i9xx_update_wm;
6686 dev_priv->display.get_fifo_size = i830_get_fifo_size;
6687 }
6688
6689 if (IS_I85X(dev) || IS_I865G(dev))
6690 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
6691 else
6692 dev_priv->display.init_clock_gating = i830_init_clock_gating;
6693 } else {
6694 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
6695 }
6696 }
6697
6698 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
6699 {
6700 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6701
6702 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6703 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
6704 return -EAGAIN;
6705 }
6706
6707 I915_WRITE(GEN6_PCODE_DATA, *val);
6708 I915_WRITE(GEN6_PCODE_DATA1, 0);
6709 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6710
6711 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6712 500)) {
6713 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
6714 return -ETIMEDOUT;
6715 }
6716
6717 *val = I915_READ(GEN6_PCODE_DATA);
6718 I915_WRITE(GEN6_PCODE_DATA, 0);
6719
6720 return 0;
6721 }
6722
6723 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val)
6724 {
6725 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6726
6727 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6728 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
6729 return -EAGAIN;
6730 }
6731
6732 I915_WRITE(GEN6_PCODE_DATA, val);
6733 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6734
6735 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6736 500)) {
6737 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
6738 return -ETIMEDOUT;
6739 }
6740
6741 I915_WRITE(GEN6_PCODE_DATA, 0);
6742
6743 return 0;
6744 }
6745
6746 static int vlv_gpu_freq_div(unsigned int czclk_freq)
6747 {
6748 switch (czclk_freq) {
6749 case 200:
6750 return 10;
6751 case 267:
6752 return 12;
6753 case 320:
6754 case 333:
6755 return 16;
6756 case 400:
6757 return 20;
6758 default:
6759 return -1;
6760 }
6761 }
6762
6763 static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
6764 {
6765 int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->mem_freq, 4);
6766
6767 div = vlv_gpu_freq_div(czclk_freq);
6768 if (div < 0)
6769 return div;
6770
6771 return DIV_ROUND_CLOSEST(czclk_freq * (val + 6 - 0xbd), div);
6772 }
6773
6774 static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
6775 {
6776 int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->mem_freq, 4);
6777
6778 mul = vlv_gpu_freq_div(czclk_freq);
6779 if (mul < 0)
6780 return mul;
6781
6782 return DIV_ROUND_CLOSEST(mul * val, czclk_freq) + 0xbd - 6;
6783 }
6784
6785 static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
6786 {
6787 int div, czclk_freq = dev_priv->rps.cz_freq;
6788
6789 div = vlv_gpu_freq_div(czclk_freq) / 2;
6790 if (div < 0)
6791 return div;
6792
6793 return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2;
6794 }
6795
6796 static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
6797 {
6798 int mul, czclk_freq = dev_priv->rps.cz_freq;
6799
6800 mul = vlv_gpu_freq_div(czclk_freq) / 2;
6801 if (mul < 0)
6802 return mul;
6803
6804 /* CHV needs even values */
6805 return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2;
6806 }
6807
6808 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
6809 {
6810 if (IS_GEN9(dev_priv->dev))
6811 return (val * GT_FREQUENCY_MULTIPLIER) / GEN9_FREQ_SCALER;
6812 else if (IS_CHERRYVIEW(dev_priv->dev))
6813 return chv_gpu_freq(dev_priv, val);
6814 else if (IS_VALLEYVIEW(dev_priv->dev))
6815 return byt_gpu_freq(dev_priv, val);
6816 else
6817 return val * GT_FREQUENCY_MULTIPLIER;
6818 }
6819
6820 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
6821 {
6822 if (IS_GEN9(dev_priv->dev))
6823 return (val * GEN9_FREQ_SCALER) / GT_FREQUENCY_MULTIPLIER;
6824 else if (IS_CHERRYVIEW(dev_priv->dev))
6825 return chv_freq_opcode(dev_priv, val);
6826 else if (IS_VALLEYVIEW(dev_priv->dev))
6827 return byt_freq_opcode(dev_priv, val);
6828 else
6829 return val / GT_FREQUENCY_MULTIPLIER;
6830 }
6831
6832 struct request_boost {
6833 struct work_struct work;
6834 struct drm_i915_gem_request *rq;
6835 };
6836
6837 static void __intel_rps_boost_work(struct work_struct *work)
6838 {
6839 struct request_boost *boost = container_of(work, struct request_boost, work);
6840
6841 if (!i915_gem_request_completed(boost->rq, true))
6842 gen6_rps_boost(to_i915(boost->rq->ring->dev), NULL);
6843
6844 i915_gem_request_unreference__unlocked(boost->rq);
6845 kfree(boost);
6846 }
6847
6848 void intel_queue_rps_boost_for_request(struct drm_device *dev,
6849 struct drm_i915_gem_request *rq)
6850 {
6851 struct request_boost *boost;
6852
6853 if (rq == NULL || INTEL_INFO(dev)->gen < 6)
6854 return;
6855
6856 boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
6857 if (boost == NULL)
6858 return;
6859
6860 i915_gem_request_reference(rq);
6861 boost->rq = rq;
6862
6863 INIT_WORK(&boost->work, __intel_rps_boost_work);
6864 queue_work(to_i915(dev)->wq, &boost->work);
6865 }
6866
6867 void intel_pm_setup(struct drm_device *dev)
6868 {
6869 struct drm_i915_private *dev_priv = dev->dev_private;
6870
6871 mutex_init(&dev_priv->rps.hw_lock);
6872
6873 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
6874 intel_gen6_powersave_work);
6875 INIT_LIST_HEAD(&dev_priv->rps.clients);
6876
6877 dev_priv->pm.suspended = false;
6878 }
Linux kernel - Deliverables
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