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drm/i915/skl: Implement Wa4x4STCOptimizationDisable:skl
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_pm.c
1 /*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28 #include <linux/cpufreq.h>
29 #include "i915_drv.h"
30 #include "intel_drv.h"
31 #include "../../../platform/x86/intel_ips.h"
32 #include <linux/module.h>
33 #include <linux/vgaarb.h>
34 #include <drm/i915_powerwell.h>
35 #include <linux/pm_runtime.h>
36
37 /**
38 * RC6 is a special power stage which allows the GPU to enter an very
39 * low-voltage mode when idle, using down to 0V while at this stage. This
40 * stage is entered automatically when the GPU is idle when RC6 support is
41 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
42 *
43 * There are different RC6 modes available in Intel GPU, which differentiate
44 * among each other with the latency required to enter and leave RC6 and
45 * voltage consumed by the GPU in different states.
46 *
47 * The combination of the following flags define which states GPU is allowed
48 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
49 * RC6pp is deepest RC6. Their support by hardware varies according to the
50 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
51 * which brings the most power savings; deeper states save more power, but
52 * require higher latency to switch to and wake up.
53 */
54 #define INTEL_RC6_ENABLE (1<<0)
55 #define INTEL_RC6p_ENABLE (1<<1)
56 #define INTEL_RC6pp_ENABLE (1<<2)
57
58 /* FBC, or Frame Buffer Compression, is a technique employed to compress the
59 * framebuffer contents in-memory, aiming at reducing the required bandwidth
60 * during in-memory transfers and, therefore, reduce the power packet.
61 *
62 * The benefits of FBC are mostly visible with solid backgrounds and
63 * variation-less patterns.
64 *
65 * FBC-related functionality can be enabled by the means of the
66 * i915.i915_enable_fbc parameter
67 */
68
69 static void gen9_init_clock_gating(struct drm_device *dev)
70 {
71 struct drm_i915_private *dev_priv = dev->dev_private;
72
73 /*
74 * WaDisableSDEUnitClockGating:skl
75 * This seems to be a pre-production w/a.
76 */
77 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
78 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
79
80 /* Wa4x4STCOptimizationDisable:skl */
81 I915_WRITE(CACHE_MODE_1,
82 _MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE));
83 }
84
85 static void i8xx_disable_fbc(struct drm_device *dev)
86 {
87 struct drm_i915_private *dev_priv = dev->dev_private;
88 u32 fbc_ctl;
89
90 /* Disable compression */
91 fbc_ctl = I915_READ(FBC_CONTROL);
92 if ((fbc_ctl & FBC_CTL_EN) == 0)
93 return;
94
95 fbc_ctl &= ~FBC_CTL_EN;
96 I915_WRITE(FBC_CONTROL, fbc_ctl);
97
98 /* Wait for compressing bit to clear */
99 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
100 DRM_DEBUG_KMS("FBC idle timed out\n");
101 return;
102 }
103
104 DRM_DEBUG_KMS("disabled FBC\n");
105 }
106
107 static void i8xx_enable_fbc(struct drm_crtc *crtc)
108 {
109 struct drm_device *dev = crtc->dev;
110 struct drm_i915_private *dev_priv = dev->dev_private;
111 struct drm_framebuffer *fb = crtc->primary->fb;
112 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
113 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
114 int cfb_pitch;
115 int i;
116 u32 fbc_ctl;
117
118 cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
119 if (fb->pitches[0] < cfb_pitch)
120 cfb_pitch = fb->pitches[0];
121
122 /* FBC_CTL wants 32B or 64B units */
123 if (IS_GEN2(dev))
124 cfb_pitch = (cfb_pitch / 32) - 1;
125 else
126 cfb_pitch = (cfb_pitch / 64) - 1;
127
128 /* Clear old tags */
129 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
130 I915_WRITE(FBC_TAG + (i * 4), 0);
131
132 if (IS_GEN4(dev)) {
133 u32 fbc_ctl2;
134
135 /* Set it up... */
136 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
137 fbc_ctl2 |= FBC_CTL_PLANE(intel_crtc->plane);
138 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
139 I915_WRITE(FBC_FENCE_OFF, crtc->y);
140 }
141
142 /* enable it... */
143 fbc_ctl = I915_READ(FBC_CONTROL);
144 fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT;
145 fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
146 if (IS_I945GM(dev))
147 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
148 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
149 fbc_ctl |= obj->fence_reg;
150 I915_WRITE(FBC_CONTROL, fbc_ctl);
151
152 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c\n",
153 cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
154 }
155
156 static bool i8xx_fbc_enabled(struct drm_device *dev)
157 {
158 struct drm_i915_private *dev_priv = dev->dev_private;
159
160 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
161 }
162
163 static void g4x_enable_fbc(struct drm_crtc *crtc)
164 {
165 struct drm_device *dev = crtc->dev;
166 struct drm_i915_private *dev_priv = dev->dev_private;
167 struct drm_framebuffer *fb = crtc->primary->fb;
168 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
169 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
170 u32 dpfc_ctl;
171
172 dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane) | DPFC_SR_EN;
173 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
174 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
175 else
176 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
177 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
178
179 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
180
181 /* enable it... */
182 I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
183
184 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
185 }
186
187 static void g4x_disable_fbc(struct drm_device *dev)
188 {
189 struct drm_i915_private *dev_priv = dev->dev_private;
190 u32 dpfc_ctl;
191
192 /* Disable compression */
193 dpfc_ctl = I915_READ(DPFC_CONTROL);
194 if (dpfc_ctl & DPFC_CTL_EN) {
195 dpfc_ctl &= ~DPFC_CTL_EN;
196 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
197
198 DRM_DEBUG_KMS("disabled FBC\n");
199 }
200 }
201
202 static bool g4x_fbc_enabled(struct drm_device *dev)
203 {
204 struct drm_i915_private *dev_priv = dev->dev_private;
205
206 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
207 }
208
209 static void sandybridge_blit_fbc_update(struct drm_device *dev)
210 {
211 struct drm_i915_private *dev_priv = dev->dev_private;
212 u32 blt_ecoskpd;
213
214 /* Make sure blitter notifies FBC of writes */
215
216 /* Blitter is part of Media powerwell on VLV. No impact of
217 * his param in other platforms for now */
218 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_MEDIA);
219
220 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
221 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
222 GEN6_BLITTER_LOCK_SHIFT;
223 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
224 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
225 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
226 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
227 GEN6_BLITTER_LOCK_SHIFT);
228 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
229 POSTING_READ(GEN6_BLITTER_ECOSKPD);
230
231 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_MEDIA);
232 }
233
234 static void ironlake_enable_fbc(struct drm_crtc *crtc)
235 {
236 struct drm_device *dev = crtc->dev;
237 struct drm_i915_private *dev_priv = dev->dev_private;
238 struct drm_framebuffer *fb = crtc->primary->fb;
239 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
240 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
241 u32 dpfc_ctl;
242
243 dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane);
244 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
245 dev_priv->fbc.threshold++;
246
247 switch (dev_priv->fbc.threshold) {
248 case 4:
249 case 3:
250 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
251 break;
252 case 2:
253 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
254 break;
255 case 1:
256 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
257 break;
258 }
259 dpfc_ctl |= DPFC_CTL_FENCE_EN;
260 if (IS_GEN5(dev))
261 dpfc_ctl |= obj->fence_reg;
262
263 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
264 I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
265 /* enable it... */
266 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
267
268 if (IS_GEN6(dev)) {
269 I915_WRITE(SNB_DPFC_CTL_SA,
270 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
271 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
272 sandybridge_blit_fbc_update(dev);
273 }
274
275 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
276 }
277
278 static void ironlake_disable_fbc(struct drm_device *dev)
279 {
280 struct drm_i915_private *dev_priv = dev->dev_private;
281 u32 dpfc_ctl;
282
283 /* Disable compression */
284 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
285 if (dpfc_ctl & DPFC_CTL_EN) {
286 dpfc_ctl &= ~DPFC_CTL_EN;
287 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
288
289 DRM_DEBUG_KMS("disabled FBC\n");
290 }
291 }
292
293 static bool ironlake_fbc_enabled(struct drm_device *dev)
294 {
295 struct drm_i915_private *dev_priv = dev->dev_private;
296
297 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
298 }
299
300 static void gen7_enable_fbc(struct drm_crtc *crtc)
301 {
302 struct drm_device *dev = crtc->dev;
303 struct drm_i915_private *dev_priv = dev->dev_private;
304 struct drm_framebuffer *fb = crtc->primary->fb;
305 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
306 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
307 u32 dpfc_ctl;
308
309 dpfc_ctl = IVB_DPFC_CTL_PLANE(intel_crtc->plane);
310 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
311 dev_priv->fbc.threshold++;
312
313 switch (dev_priv->fbc.threshold) {
314 case 4:
315 case 3:
316 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
317 break;
318 case 2:
319 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
320 break;
321 case 1:
322 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
323 break;
324 }
325
326 dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
327
328 if (dev_priv->fbc.false_color)
329 dpfc_ctl |= FBC_CTL_FALSE_COLOR;
330
331 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
332
333 if (IS_IVYBRIDGE(dev)) {
334 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
335 I915_WRITE(ILK_DISPLAY_CHICKEN1,
336 I915_READ(ILK_DISPLAY_CHICKEN1) |
337 ILK_FBCQ_DIS);
338 } else {
339 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
340 I915_WRITE(CHICKEN_PIPESL_1(intel_crtc->pipe),
341 I915_READ(CHICKEN_PIPESL_1(intel_crtc->pipe)) |
342 HSW_FBCQ_DIS);
343 }
344
345 I915_WRITE(SNB_DPFC_CTL_SA,
346 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
347 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
348
349 sandybridge_blit_fbc_update(dev);
350
351 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
352 }
353
354 bool intel_fbc_enabled(struct drm_device *dev)
355 {
356 struct drm_i915_private *dev_priv = dev->dev_private;
357
358 if (!dev_priv->display.fbc_enabled)
359 return false;
360
361 return dev_priv->display.fbc_enabled(dev);
362 }
363
364 void gen8_fbc_sw_flush(struct drm_device *dev, u32 value)
365 {
366 struct drm_i915_private *dev_priv = dev->dev_private;
367
368 if (!IS_GEN8(dev))
369 return;
370
371 I915_WRITE(MSG_FBC_REND_STATE, value);
372 }
373
374 static void intel_fbc_work_fn(struct work_struct *__work)
375 {
376 struct intel_fbc_work *work =
377 container_of(to_delayed_work(__work),
378 struct intel_fbc_work, work);
379 struct drm_device *dev = work->crtc->dev;
380 struct drm_i915_private *dev_priv = dev->dev_private;
381
382 mutex_lock(&dev->struct_mutex);
383 if (work == dev_priv->fbc.fbc_work) {
384 /* Double check that we haven't switched fb without cancelling
385 * the prior work.
386 */
387 if (work->crtc->primary->fb == work->fb) {
388 dev_priv->display.enable_fbc(work->crtc);
389
390 dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;
391 dev_priv->fbc.fb_id = work->crtc->primary->fb->base.id;
392 dev_priv->fbc.y = work->crtc->y;
393 }
394
395 dev_priv->fbc.fbc_work = NULL;
396 }
397 mutex_unlock(&dev->struct_mutex);
398
399 kfree(work);
400 }
401
402 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
403 {
404 if (dev_priv->fbc.fbc_work == NULL)
405 return;
406
407 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
408
409 /* Synchronisation is provided by struct_mutex and checking of
410 * dev_priv->fbc.fbc_work, so we can perform the cancellation
411 * entirely asynchronously.
412 */
413 if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
414 /* tasklet was killed before being run, clean up */
415 kfree(dev_priv->fbc.fbc_work);
416
417 /* Mark the work as no longer wanted so that if it does
418 * wake-up (because the work was already running and waiting
419 * for our mutex), it will discover that is no longer
420 * necessary to run.
421 */
422 dev_priv->fbc.fbc_work = NULL;
423 }
424
425 static void intel_enable_fbc(struct drm_crtc *crtc)
426 {
427 struct intel_fbc_work *work;
428 struct drm_device *dev = crtc->dev;
429 struct drm_i915_private *dev_priv = dev->dev_private;
430
431 if (!dev_priv->display.enable_fbc)
432 return;
433
434 intel_cancel_fbc_work(dev_priv);
435
436 work = kzalloc(sizeof(*work), GFP_KERNEL);
437 if (work == NULL) {
438 DRM_ERROR("Failed to allocate FBC work structure\n");
439 dev_priv->display.enable_fbc(crtc);
440 return;
441 }
442
443 work->crtc = crtc;
444 work->fb = crtc->primary->fb;
445 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
446
447 dev_priv->fbc.fbc_work = work;
448
449 /* Delay the actual enabling to let pageflipping cease and the
450 * display to settle before starting the compression. Note that
451 * this delay also serves a second purpose: it allows for a
452 * vblank to pass after disabling the FBC before we attempt
453 * to modify the control registers.
454 *
455 * A more complicated solution would involve tracking vblanks
456 * following the termination of the page-flipping sequence
457 * and indeed performing the enable as a co-routine and not
458 * waiting synchronously upon the vblank.
459 *
460 * WaFbcWaitForVBlankBeforeEnable:ilk,snb
461 */
462 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
463 }
464
465 void intel_disable_fbc(struct drm_device *dev)
466 {
467 struct drm_i915_private *dev_priv = dev->dev_private;
468
469 intel_cancel_fbc_work(dev_priv);
470
471 if (!dev_priv->display.disable_fbc)
472 return;
473
474 dev_priv->display.disable_fbc(dev);
475 dev_priv->fbc.plane = -1;
476 }
477
478 static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
479 enum no_fbc_reason reason)
480 {
481 if (dev_priv->fbc.no_fbc_reason == reason)
482 return false;
483
484 dev_priv->fbc.no_fbc_reason = reason;
485 return true;
486 }
487
488 /**
489 * intel_update_fbc - enable/disable FBC as needed
490 * @dev: the drm_device
491 *
492 * Set up the framebuffer compression hardware at mode set time. We
493 * enable it if possible:
494 * - plane A only (on pre-965)
495 * - no pixel mulitply/line duplication
496 * - no alpha buffer discard
497 * - no dual wide
498 * - framebuffer <= max_hdisplay in width, max_vdisplay in height
499 *
500 * We can't assume that any compression will take place (worst case),
501 * so the compressed buffer has to be the same size as the uncompressed
502 * one. It also must reside (along with the line length buffer) in
503 * stolen memory.
504 *
505 * We need to enable/disable FBC on a global basis.
506 */
507 void intel_update_fbc(struct drm_device *dev)
508 {
509 struct drm_i915_private *dev_priv = dev->dev_private;
510 struct drm_crtc *crtc = NULL, *tmp_crtc;
511 struct intel_crtc *intel_crtc;
512 struct drm_framebuffer *fb;
513 struct drm_i915_gem_object *obj;
514 const struct drm_display_mode *adjusted_mode;
515 unsigned int max_width, max_height;
516
517 if (!HAS_FBC(dev)) {
518 set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED);
519 return;
520 }
521
522 if (!i915.powersave) {
523 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
524 DRM_DEBUG_KMS("fbc disabled per module param\n");
525 return;
526 }
527
528 /*
529 * If FBC is already on, we just have to verify that we can
530 * keep it that way...
531 * Need to disable if:
532 * - more than one pipe is active
533 * - changing FBC params (stride, fence, mode)
534 * - new fb is too large to fit in compressed buffer
535 * - going to an unsupported config (interlace, pixel multiply, etc.)
536 */
537 for_each_crtc(dev, tmp_crtc) {
538 if (intel_crtc_active(tmp_crtc) &&
539 to_intel_crtc(tmp_crtc)->primary_enabled) {
540 if (crtc) {
541 if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
542 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
543 goto out_disable;
544 }
545 crtc = tmp_crtc;
546 }
547 }
548
549 if (!crtc || crtc->primary->fb == NULL) {
550 if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
551 DRM_DEBUG_KMS("no output, disabling\n");
552 goto out_disable;
553 }
554
555 intel_crtc = to_intel_crtc(crtc);
556 fb = crtc->primary->fb;
557 obj = intel_fb_obj(fb);
558 adjusted_mode = &intel_crtc->config.adjusted_mode;
559
560 if (i915.enable_fbc < 0) {
561 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
562 DRM_DEBUG_KMS("disabled per chip default\n");
563 goto out_disable;
564 }
565 if (!i915.enable_fbc) {
566 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
567 DRM_DEBUG_KMS("fbc disabled per module param\n");
568 goto out_disable;
569 }
570 if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ||
571 (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
572 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
573 DRM_DEBUG_KMS("mode incompatible with compression, "
574 "disabling\n");
575 goto out_disable;
576 }
577
578 if (INTEL_INFO(dev)->gen >= 8 || IS_HASWELL(dev)) {
579 max_width = 4096;
580 max_height = 4096;
581 } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
582 max_width = 4096;
583 max_height = 2048;
584 } else {
585 max_width = 2048;
586 max_height = 1536;
587 }
588 if (intel_crtc->config.pipe_src_w > max_width ||
589 intel_crtc->config.pipe_src_h > max_height) {
590 if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
591 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
592 goto out_disable;
593 }
594 if ((INTEL_INFO(dev)->gen < 4 || HAS_DDI(dev)) &&
595 intel_crtc->plane != PLANE_A) {
596 if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
597 DRM_DEBUG_KMS("plane not A, disabling compression\n");
598 goto out_disable;
599 }
600
601 /* The use of a CPU fence is mandatory in order to detect writes
602 * by the CPU to the scanout and trigger updates to the FBC.
603 */
604 if (obj->tiling_mode != I915_TILING_X ||
605 obj->fence_reg == I915_FENCE_REG_NONE) {
606 if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED))
607 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
608 goto out_disable;
609 }
610 if (INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
611 to_intel_plane(crtc->primary)->rotation != BIT(DRM_ROTATE_0)) {
612 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
613 DRM_DEBUG_KMS("Rotation unsupported, disabling\n");
614 goto out_disable;
615 }
616
617 /* If the kernel debugger is active, always disable compression */
618 if (in_dbg_master())
619 goto out_disable;
620
621 if (i915_gem_stolen_setup_compression(dev, obj->base.size,
622 drm_format_plane_cpp(fb->pixel_format, 0))) {
623 if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL))
624 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
625 goto out_disable;
626 }
627
628 /* If the scanout has not changed, don't modify the FBC settings.
629 * Note that we make the fundamental assumption that the fb->obj
630 * cannot be unpinned (and have its GTT offset and fence revoked)
631 * without first being decoupled from the scanout and FBC disabled.
632 */
633 if (dev_priv->fbc.plane == intel_crtc->plane &&
634 dev_priv->fbc.fb_id == fb->base.id &&
635 dev_priv->fbc.y == crtc->y)
636 return;
637
638 if (intel_fbc_enabled(dev)) {
639 /* We update FBC along two paths, after changing fb/crtc
640 * configuration (modeswitching) and after page-flipping
641 * finishes. For the latter, we know that not only did
642 * we disable the FBC at the start of the page-flip
643 * sequence, but also more than one vblank has passed.
644 *
645 * For the former case of modeswitching, it is possible
646 * to switch between two FBC valid configurations
647 * instantaneously so we do need to disable the FBC
648 * before we can modify its control registers. We also
649 * have to wait for the next vblank for that to take
650 * effect. However, since we delay enabling FBC we can
651 * assume that a vblank has passed since disabling and
652 * that we can safely alter the registers in the deferred
653 * callback.
654 *
655 * In the scenario that we go from a valid to invalid
656 * and then back to valid FBC configuration we have
657 * no strict enforcement that a vblank occurred since
658 * disabling the FBC. However, along all current pipe
659 * disabling paths we do need to wait for a vblank at
660 * some point. And we wait before enabling FBC anyway.
661 */
662 DRM_DEBUG_KMS("disabling active FBC for update\n");
663 intel_disable_fbc(dev);
664 }
665
666 intel_enable_fbc(crtc);
667 dev_priv->fbc.no_fbc_reason = FBC_OK;
668 return;
669
670 out_disable:
671 /* Multiple disables should be harmless */
672 if (intel_fbc_enabled(dev)) {
673 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
674 intel_disable_fbc(dev);
675 }
676 i915_gem_stolen_cleanup_compression(dev);
677 }
678
679 static void i915_pineview_get_mem_freq(struct drm_device *dev)
680 {
681 struct drm_i915_private *dev_priv = dev->dev_private;
682 u32 tmp;
683
684 tmp = I915_READ(CLKCFG);
685
686 switch (tmp & CLKCFG_FSB_MASK) {
687 case CLKCFG_FSB_533:
688 dev_priv->fsb_freq = 533; /* 133*4 */
689 break;
690 case CLKCFG_FSB_800:
691 dev_priv->fsb_freq = 800; /* 200*4 */
692 break;
693 case CLKCFG_FSB_667:
694 dev_priv->fsb_freq = 667; /* 167*4 */
695 break;
696 case CLKCFG_FSB_400:
697 dev_priv->fsb_freq = 400; /* 100*4 */
698 break;
699 }
700
701 switch (tmp & CLKCFG_MEM_MASK) {
702 case CLKCFG_MEM_533:
703 dev_priv->mem_freq = 533;
704 break;
705 case CLKCFG_MEM_667:
706 dev_priv->mem_freq = 667;
707 break;
708 case CLKCFG_MEM_800:
709 dev_priv->mem_freq = 800;
710 break;
711 }
712
713 /* detect pineview DDR3 setting */
714 tmp = I915_READ(CSHRDDR3CTL);
715 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
716 }
717
718 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
719 {
720 struct drm_i915_private *dev_priv = dev->dev_private;
721 u16 ddrpll, csipll;
722
723 ddrpll = I915_READ16(DDRMPLL1);
724 csipll = I915_READ16(CSIPLL0);
725
726 switch (ddrpll & 0xff) {
727 case 0xc:
728 dev_priv->mem_freq = 800;
729 break;
730 case 0x10:
731 dev_priv->mem_freq = 1066;
732 break;
733 case 0x14:
734 dev_priv->mem_freq = 1333;
735 break;
736 case 0x18:
737 dev_priv->mem_freq = 1600;
738 break;
739 default:
740 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
741 ddrpll & 0xff);
742 dev_priv->mem_freq = 0;
743 break;
744 }
745
746 dev_priv->ips.r_t = dev_priv->mem_freq;
747
748 switch (csipll & 0x3ff) {
749 case 0x00c:
750 dev_priv->fsb_freq = 3200;
751 break;
752 case 0x00e:
753 dev_priv->fsb_freq = 3733;
754 break;
755 case 0x010:
756 dev_priv->fsb_freq = 4266;
757 break;
758 case 0x012:
759 dev_priv->fsb_freq = 4800;
760 break;
761 case 0x014:
762 dev_priv->fsb_freq = 5333;
763 break;
764 case 0x016:
765 dev_priv->fsb_freq = 5866;
766 break;
767 case 0x018:
768 dev_priv->fsb_freq = 6400;
769 break;
770 default:
771 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
772 csipll & 0x3ff);
773 dev_priv->fsb_freq = 0;
774 break;
775 }
776
777 if (dev_priv->fsb_freq == 3200) {
778 dev_priv->ips.c_m = 0;
779 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
780 dev_priv->ips.c_m = 1;
781 } else {
782 dev_priv->ips.c_m = 2;
783 }
784 }
785
786 static const struct cxsr_latency cxsr_latency_table[] = {
787 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
788 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
789 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
790 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
791 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
792
793 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
794 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
795 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
796 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
797 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
798
799 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
800 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
801 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
802 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
803 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
804
805 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
806 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
807 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
808 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
809 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
810
811 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
812 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
813 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
814 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
815 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
816
817 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
818 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
819 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
820 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
821 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
822 };
823
824 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
825 int is_ddr3,
826 int fsb,
827 int mem)
828 {
829 const struct cxsr_latency *latency;
830 int i;
831
832 if (fsb == 0 || mem == 0)
833 return NULL;
834
835 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
836 latency = &cxsr_latency_table[i];
837 if (is_desktop == latency->is_desktop &&
838 is_ddr3 == latency->is_ddr3 &&
839 fsb == latency->fsb_freq && mem == latency->mem_freq)
840 return latency;
841 }
842
843 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
844
845 return NULL;
846 }
847
848 void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
849 {
850 struct drm_device *dev = dev_priv->dev;
851 u32 val;
852
853 if (IS_VALLEYVIEW(dev)) {
854 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
855 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
856 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
857 } else if (IS_PINEVIEW(dev)) {
858 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
859 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
860 I915_WRITE(DSPFW3, val);
861 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
862 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
863 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
864 I915_WRITE(FW_BLC_SELF, val);
865 } else if (IS_I915GM(dev)) {
866 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
867 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
868 I915_WRITE(INSTPM, val);
869 } else {
870 return;
871 }
872
873 DRM_DEBUG_KMS("memory self-refresh is %s\n",
874 enable ? "enabled" : "disabled");
875 }
876
877 /*
878 * Latency for FIFO fetches is dependent on several factors:
879 * - memory configuration (speed, channels)
880 * - chipset
881 * - current MCH state
882 * It can be fairly high in some situations, so here we assume a fairly
883 * pessimal value. It's a tradeoff between extra memory fetches (if we
884 * set this value too high, the FIFO will fetch frequently to stay full)
885 * and power consumption (set it too low to save power and we might see
886 * FIFO underruns and display "flicker").
887 *
888 * A value of 5us seems to be a good balance; safe for very low end
889 * platforms but not overly aggressive on lower latency configs.
890 */
891 static const int pessimal_latency_ns = 5000;
892
893 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
894 {
895 struct drm_i915_private *dev_priv = dev->dev_private;
896 uint32_t dsparb = I915_READ(DSPARB);
897 int size;
898
899 size = dsparb & 0x7f;
900 if (plane)
901 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
902
903 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
904 plane ? "B" : "A", size);
905
906 return size;
907 }
908
909 static int i830_get_fifo_size(struct drm_device *dev, int plane)
910 {
911 struct drm_i915_private *dev_priv = dev->dev_private;
912 uint32_t dsparb = I915_READ(DSPARB);
913 int size;
914
915 size = dsparb & 0x1ff;
916 if (plane)
917 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
918 size >>= 1; /* Convert to cachelines */
919
920 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
921 plane ? "B" : "A", size);
922
923 return size;
924 }
925
926 static int i845_get_fifo_size(struct drm_device *dev, int plane)
927 {
928 struct drm_i915_private *dev_priv = dev->dev_private;
929 uint32_t dsparb = I915_READ(DSPARB);
930 int size;
931
932 size = dsparb & 0x7f;
933 size >>= 2; /* Convert to cachelines */
934
935 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
936 plane ? "B" : "A",
937 size);
938
939 return size;
940 }
941
942 /* Pineview has different values for various configs */
943 static const struct intel_watermark_params pineview_display_wm = {
944 .fifo_size = PINEVIEW_DISPLAY_FIFO,
945 .max_wm = PINEVIEW_MAX_WM,
946 .default_wm = PINEVIEW_DFT_WM,
947 .guard_size = PINEVIEW_GUARD_WM,
948 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
949 };
950 static const struct intel_watermark_params pineview_display_hplloff_wm = {
951 .fifo_size = PINEVIEW_DISPLAY_FIFO,
952 .max_wm = PINEVIEW_MAX_WM,
953 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
954 .guard_size = PINEVIEW_GUARD_WM,
955 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
956 };
957 static const struct intel_watermark_params pineview_cursor_wm = {
958 .fifo_size = PINEVIEW_CURSOR_FIFO,
959 .max_wm = PINEVIEW_CURSOR_MAX_WM,
960 .default_wm = PINEVIEW_CURSOR_DFT_WM,
961 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
962 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
963 };
964 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
965 .fifo_size = PINEVIEW_CURSOR_FIFO,
966 .max_wm = PINEVIEW_CURSOR_MAX_WM,
967 .default_wm = PINEVIEW_CURSOR_DFT_WM,
968 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
969 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
970 };
971 static const struct intel_watermark_params g4x_wm_info = {
972 .fifo_size = G4X_FIFO_SIZE,
973 .max_wm = G4X_MAX_WM,
974 .default_wm = G4X_MAX_WM,
975 .guard_size = 2,
976 .cacheline_size = G4X_FIFO_LINE_SIZE,
977 };
978 static const struct intel_watermark_params g4x_cursor_wm_info = {
979 .fifo_size = I965_CURSOR_FIFO,
980 .max_wm = I965_CURSOR_MAX_WM,
981 .default_wm = I965_CURSOR_DFT_WM,
982 .guard_size = 2,
983 .cacheline_size = G4X_FIFO_LINE_SIZE,
984 };
985 static const struct intel_watermark_params valleyview_wm_info = {
986 .fifo_size = VALLEYVIEW_FIFO_SIZE,
987 .max_wm = VALLEYVIEW_MAX_WM,
988 .default_wm = VALLEYVIEW_MAX_WM,
989 .guard_size = 2,
990 .cacheline_size = G4X_FIFO_LINE_SIZE,
991 };
992 static const struct intel_watermark_params valleyview_cursor_wm_info = {
993 .fifo_size = I965_CURSOR_FIFO,
994 .max_wm = VALLEYVIEW_CURSOR_MAX_WM,
995 .default_wm = I965_CURSOR_DFT_WM,
996 .guard_size = 2,
997 .cacheline_size = G4X_FIFO_LINE_SIZE,
998 };
999 static const struct intel_watermark_params i965_cursor_wm_info = {
1000 .fifo_size = I965_CURSOR_FIFO,
1001 .max_wm = I965_CURSOR_MAX_WM,
1002 .default_wm = I965_CURSOR_DFT_WM,
1003 .guard_size = 2,
1004 .cacheline_size = I915_FIFO_LINE_SIZE,
1005 };
1006 static const struct intel_watermark_params i945_wm_info = {
1007 .fifo_size = I945_FIFO_SIZE,
1008 .max_wm = I915_MAX_WM,
1009 .default_wm = 1,
1010 .guard_size = 2,
1011 .cacheline_size = I915_FIFO_LINE_SIZE,
1012 };
1013 static const struct intel_watermark_params i915_wm_info = {
1014 .fifo_size = I915_FIFO_SIZE,
1015 .max_wm = I915_MAX_WM,
1016 .default_wm = 1,
1017 .guard_size = 2,
1018 .cacheline_size = I915_FIFO_LINE_SIZE,
1019 };
1020 static const struct intel_watermark_params i830_a_wm_info = {
1021 .fifo_size = I855GM_FIFO_SIZE,
1022 .max_wm = I915_MAX_WM,
1023 .default_wm = 1,
1024 .guard_size = 2,
1025 .cacheline_size = I830_FIFO_LINE_SIZE,
1026 };
1027 static const struct intel_watermark_params i830_bc_wm_info = {
1028 .fifo_size = I855GM_FIFO_SIZE,
1029 .max_wm = I915_MAX_WM/2,
1030 .default_wm = 1,
1031 .guard_size = 2,
1032 .cacheline_size = I830_FIFO_LINE_SIZE,
1033 };
1034 static const struct intel_watermark_params i845_wm_info = {
1035 .fifo_size = I830_FIFO_SIZE,
1036 .max_wm = I915_MAX_WM,
1037 .default_wm = 1,
1038 .guard_size = 2,
1039 .cacheline_size = I830_FIFO_LINE_SIZE,
1040 };
1041
1042 /**
1043 * intel_calculate_wm - calculate watermark level
1044 * @clock_in_khz: pixel clock
1045 * @wm: chip FIFO params
1046 * @pixel_size: display pixel size
1047 * @latency_ns: memory latency for the platform
1048 *
1049 * Calculate the watermark level (the level at which the display plane will
1050 * start fetching from memory again). Each chip has a different display
1051 * FIFO size and allocation, so the caller needs to figure that out and pass
1052 * in the correct intel_watermark_params structure.
1053 *
1054 * As the pixel clock runs, the FIFO will be drained at a rate that depends
1055 * on the pixel size. When it reaches the watermark level, it'll start
1056 * fetching FIFO line sized based chunks from memory until the FIFO fills
1057 * past the watermark point. If the FIFO drains completely, a FIFO underrun
1058 * will occur, and a display engine hang could result.
1059 */
1060 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
1061 const struct intel_watermark_params *wm,
1062 int fifo_size,
1063 int pixel_size,
1064 unsigned long latency_ns)
1065 {
1066 long entries_required, wm_size;
1067
1068 /*
1069 * Note: we need to make sure we don't overflow for various clock &
1070 * latency values.
1071 * clocks go from a few thousand to several hundred thousand.
1072 * latency is usually a few thousand
1073 */
1074 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
1075 1000;
1076 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
1077
1078 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
1079
1080 wm_size = fifo_size - (entries_required + wm->guard_size);
1081
1082 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
1083
1084 /* Don't promote wm_size to unsigned... */
1085 if (wm_size > (long)wm->max_wm)
1086 wm_size = wm->max_wm;
1087 if (wm_size <= 0)
1088 wm_size = wm->default_wm;
1089 return wm_size;
1090 }
1091
1092 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1093 {
1094 struct drm_crtc *crtc, *enabled = NULL;
1095
1096 for_each_crtc(dev, crtc) {
1097 if (intel_crtc_active(crtc)) {
1098 if (enabled)
1099 return NULL;
1100 enabled = crtc;
1101 }
1102 }
1103
1104 return enabled;
1105 }
1106
1107 static void pineview_update_wm(struct drm_crtc *unused_crtc)
1108 {
1109 struct drm_device *dev = unused_crtc->dev;
1110 struct drm_i915_private *dev_priv = dev->dev_private;
1111 struct drm_crtc *crtc;
1112 const struct cxsr_latency *latency;
1113 u32 reg;
1114 unsigned long wm;
1115
1116 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1117 dev_priv->fsb_freq, dev_priv->mem_freq);
1118 if (!latency) {
1119 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1120 intel_set_memory_cxsr(dev_priv, false);
1121 return;
1122 }
1123
1124 crtc = single_enabled_crtc(dev);
1125 if (crtc) {
1126 const struct drm_display_mode *adjusted_mode;
1127 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1128 int clock;
1129
1130 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1131 clock = adjusted_mode->crtc_clock;
1132
1133 /* Display SR */
1134 wm = intel_calculate_wm(clock, &pineview_display_wm,
1135 pineview_display_wm.fifo_size,
1136 pixel_size, latency->display_sr);
1137 reg = I915_READ(DSPFW1);
1138 reg &= ~DSPFW_SR_MASK;
1139 reg |= wm << DSPFW_SR_SHIFT;
1140 I915_WRITE(DSPFW1, reg);
1141 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1142
1143 /* cursor SR */
1144 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1145 pineview_display_wm.fifo_size,
1146 pixel_size, latency->cursor_sr);
1147 reg = I915_READ(DSPFW3);
1148 reg &= ~DSPFW_CURSOR_SR_MASK;
1149 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1150 I915_WRITE(DSPFW3, reg);
1151
1152 /* Display HPLL off SR */
1153 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1154 pineview_display_hplloff_wm.fifo_size,
1155 pixel_size, latency->display_hpll_disable);
1156 reg = I915_READ(DSPFW3);
1157 reg &= ~DSPFW_HPLL_SR_MASK;
1158 reg |= wm & DSPFW_HPLL_SR_MASK;
1159 I915_WRITE(DSPFW3, reg);
1160
1161 /* cursor HPLL off SR */
1162 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1163 pineview_display_hplloff_wm.fifo_size,
1164 pixel_size, latency->cursor_hpll_disable);
1165 reg = I915_READ(DSPFW3);
1166 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1167 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1168 I915_WRITE(DSPFW3, reg);
1169 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1170
1171 intel_set_memory_cxsr(dev_priv, true);
1172 } else {
1173 intel_set_memory_cxsr(dev_priv, false);
1174 }
1175 }
1176
1177 static bool g4x_compute_wm0(struct drm_device *dev,
1178 int plane,
1179 const struct intel_watermark_params *display,
1180 int display_latency_ns,
1181 const struct intel_watermark_params *cursor,
1182 int cursor_latency_ns,
1183 int *plane_wm,
1184 int *cursor_wm)
1185 {
1186 struct drm_crtc *crtc;
1187 const struct drm_display_mode *adjusted_mode;
1188 int htotal, hdisplay, clock, pixel_size;
1189 int line_time_us, line_count;
1190 int entries, tlb_miss;
1191
1192 crtc = intel_get_crtc_for_plane(dev, plane);
1193 if (!intel_crtc_active(crtc)) {
1194 *cursor_wm = cursor->guard_size;
1195 *plane_wm = display->guard_size;
1196 return false;
1197 }
1198
1199 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1200 clock = adjusted_mode->crtc_clock;
1201 htotal = adjusted_mode->crtc_htotal;
1202 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1203 pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1204
1205 /* Use the small buffer method to calculate plane watermark */
1206 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1207 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1208 if (tlb_miss > 0)
1209 entries += tlb_miss;
1210 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1211 *plane_wm = entries + display->guard_size;
1212 if (*plane_wm > (int)display->max_wm)
1213 *plane_wm = display->max_wm;
1214
1215 /* Use the large buffer method to calculate cursor watermark */
1216 line_time_us = max(htotal * 1000 / clock, 1);
1217 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1218 entries = line_count * to_intel_crtc(crtc)->cursor_width * pixel_size;
1219 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1220 if (tlb_miss > 0)
1221 entries += tlb_miss;
1222 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1223 *cursor_wm = entries + cursor->guard_size;
1224 if (*cursor_wm > (int)cursor->max_wm)
1225 *cursor_wm = (int)cursor->max_wm;
1226
1227 return true;
1228 }
1229
1230 /*
1231 * Check the wm result.
1232 *
1233 * If any calculated watermark values is larger than the maximum value that
1234 * can be programmed into the associated watermark register, that watermark
1235 * must be disabled.
1236 */
1237 static bool g4x_check_srwm(struct drm_device *dev,
1238 int display_wm, int cursor_wm,
1239 const struct intel_watermark_params *display,
1240 const struct intel_watermark_params *cursor)
1241 {
1242 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1243 display_wm, cursor_wm);
1244
1245 if (display_wm > display->max_wm) {
1246 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1247 display_wm, display->max_wm);
1248 return false;
1249 }
1250
1251 if (cursor_wm > cursor->max_wm) {
1252 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1253 cursor_wm, cursor->max_wm);
1254 return false;
1255 }
1256
1257 if (!(display_wm || cursor_wm)) {
1258 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1259 return false;
1260 }
1261
1262 return true;
1263 }
1264
1265 static bool g4x_compute_srwm(struct drm_device *dev,
1266 int plane,
1267 int latency_ns,
1268 const struct intel_watermark_params *display,
1269 const struct intel_watermark_params *cursor,
1270 int *display_wm, int *cursor_wm)
1271 {
1272 struct drm_crtc *crtc;
1273 const struct drm_display_mode *adjusted_mode;
1274 int hdisplay, htotal, pixel_size, clock;
1275 unsigned long line_time_us;
1276 int line_count, line_size;
1277 int small, large;
1278 int entries;
1279
1280 if (!latency_ns) {
1281 *display_wm = *cursor_wm = 0;
1282 return false;
1283 }
1284
1285 crtc = intel_get_crtc_for_plane(dev, plane);
1286 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1287 clock = adjusted_mode->crtc_clock;
1288 htotal = adjusted_mode->crtc_htotal;
1289 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1290 pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1291
1292 line_time_us = max(htotal * 1000 / clock, 1);
1293 line_count = (latency_ns / line_time_us + 1000) / 1000;
1294 line_size = hdisplay * pixel_size;
1295
1296 /* Use the minimum of the small and large buffer method for primary */
1297 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1298 large = line_count * line_size;
1299
1300 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1301 *display_wm = entries + display->guard_size;
1302
1303 /* calculate the self-refresh watermark for display cursor */
1304 entries = line_count * pixel_size * to_intel_crtc(crtc)->cursor_width;
1305 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1306 *cursor_wm = entries + cursor->guard_size;
1307
1308 return g4x_check_srwm(dev,
1309 *display_wm, *cursor_wm,
1310 display, cursor);
1311 }
1312
1313 static bool vlv_compute_drain_latency(struct drm_crtc *crtc,
1314 int pixel_size,
1315 int *prec_mult,
1316 int *drain_latency)
1317 {
1318 int entries;
1319 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
1320
1321 if (WARN(clock == 0, "Pixel clock is zero!\n"))
1322 return false;
1323
1324 if (WARN(pixel_size == 0, "Pixel size is zero!\n"))
1325 return false;
1326
1327 entries = DIV_ROUND_UP(clock, 1000) * pixel_size;
1328 *prec_mult = (entries > 128) ? DRAIN_LATENCY_PRECISION_64 :
1329 DRAIN_LATENCY_PRECISION_32;
1330 *drain_latency = (64 * (*prec_mult) * 4) / entries;
1331
1332 if (*drain_latency > DRAIN_LATENCY_MASK)
1333 *drain_latency = DRAIN_LATENCY_MASK;
1334
1335 return true;
1336 }
1337
1338 /*
1339 * Update drain latency registers of memory arbiter
1340 *
1341 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1342 * to be programmed. Each plane has a drain latency multiplier and a drain
1343 * latency value.
1344 */
1345
1346 static void vlv_update_drain_latency(struct drm_crtc *crtc)
1347 {
1348 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1349 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1350 int pixel_size;
1351 int drain_latency;
1352 enum pipe pipe = intel_crtc->pipe;
1353 int plane_prec, prec_mult, plane_dl;
1354
1355 plane_dl = I915_READ(VLV_DDL(pipe)) & ~(DDL_PLANE_PRECISION_64 |
1356 DRAIN_LATENCY_MASK | DDL_CURSOR_PRECISION_64 |
1357 (DRAIN_LATENCY_MASK << DDL_CURSOR_SHIFT));
1358
1359 if (!intel_crtc_active(crtc)) {
1360 I915_WRITE(VLV_DDL(pipe), plane_dl);
1361 return;
1362 }
1363
1364 /* Primary plane Drain Latency */
1365 pixel_size = crtc->primary->fb->bits_per_pixel / 8; /* BPP */
1366 if (vlv_compute_drain_latency(crtc, pixel_size, &prec_mult, &drain_latency)) {
1367 plane_prec = (prec_mult == DRAIN_LATENCY_PRECISION_64) ?
1368 DDL_PLANE_PRECISION_64 :
1369 DDL_PLANE_PRECISION_32;
1370 plane_dl |= plane_prec | drain_latency;
1371 }
1372
1373 /* Cursor Drain Latency
1374 * BPP is always 4 for cursor
1375 */
1376 pixel_size = 4;
1377
1378 /* Program cursor DL only if it is enabled */
1379 if (intel_crtc->cursor_base &&
1380 vlv_compute_drain_latency(crtc, pixel_size, &prec_mult, &drain_latency)) {
1381 plane_prec = (prec_mult == DRAIN_LATENCY_PRECISION_64) ?
1382 DDL_CURSOR_PRECISION_64 :
1383 DDL_CURSOR_PRECISION_32;
1384 plane_dl |= plane_prec | (drain_latency << DDL_CURSOR_SHIFT);
1385 }
1386
1387 I915_WRITE(VLV_DDL(pipe), plane_dl);
1388 }
1389
1390 #define single_plane_enabled(mask) is_power_of_2(mask)
1391
1392 static void valleyview_update_wm(struct drm_crtc *crtc)
1393 {
1394 struct drm_device *dev = crtc->dev;
1395 static const int sr_latency_ns = 12000;
1396 struct drm_i915_private *dev_priv = dev->dev_private;
1397 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1398 int plane_sr, cursor_sr;
1399 int ignore_plane_sr, ignore_cursor_sr;
1400 unsigned int enabled = 0;
1401 bool cxsr_enabled;
1402
1403 vlv_update_drain_latency(crtc);
1404
1405 if (g4x_compute_wm0(dev, PIPE_A,
1406 &valleyview_wm_info, pessimal_latency_ns,
1407 &valleyview_cursor_wm_info, pessimal_latency_ns,
1408 &planea_wm, &cursora_wm))
1409 enabled |= 1 << PIPE_A;
1410
1411 if (g4x_compute_wm0(dev, PIPE_B,
1412 &valleyview_wm_info, pessimal_latency_ns,
1413 &valleyview_cursor_wm_info, pessimal_latency_ns,
1414 &planeb_wm, &cursorb_wm))
1415 enabled |= 1 << PIPE_B;
1416
1417 if (single_plane_enabled(enabled) &&
1418 g4x_compute_srwm(dev, ffs(enabled) - 1,
1419 sr_latency_ns,
1420 &valleyview_wm_info,
1421 &valleyview_cursor_wm_info,
1422 &plane_sr, &ignore_cursor_sr) &&
1423 g4x_compute_srwm(dev, ffs(enabled) - 1,
1424 2*sr_latency_ns,
1425 &valleyview_wm_info,
1426 &valleyview_cursor_wm_info,
1427 &ignore_plane_sr, &cursor_sr)) {
1428 cxsr_enabled = true;
1429 } else {
1430 cxsr_enabled = false;
1431 intel_set_memory_cxsr(dev_priv, false);
1432 plane_sr = cursor_sr = 0;
1433 }
1434
1435 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1436 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1437 planea_wm, cursora_wm,
1438 planeb_wm, cursorb_wm,
1439 plane_sr, cursor_sr);
1440
1441 I915_WRITE(DSPFW1,
1442 (plane_sr << DSPFW_SR_SHIFT) |
1443 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1444 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1445 (planea_wm << DSPFW_PLANEA_SHIFT));
1446 I915_WRITE(DSPFW2,
1447 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1448 (cursora_wm << DSPFW_CURSORA_SHIFT));
1449 I915_WRITE(DSPFW3,
1450 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1451 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1452
1453 if (cxsr_enabled)
1454 intel_set_memory_cxsr(dev_priv, true);
1455 }
1456
1457 static void cherryview_update_wm(struct drm_crtc *crtc)
1458 {
1459 struct drm_device *dev = crtc->dev;
1460 static const int sr_latency_ns = 12000;
1461 struct drm_i915_private *dev_priv = dev->dev_private;
1462 int planea_wm, planeb_wm, planec_wm;
1463 int cursora_wm, cursorb_wm, cursorc_wm;
1464 int plane_sr, cursor_sr;
1465 int ignore_plane_sr, ignore_cursor_sr;
1466 unsigned int enabled = 0;
1467 bool cxsr_enabled;
1468
1469 vlv_update_drain_latency(crtc);
1470
1471 if (g4x_compute_wm0(dev, PIPE_A,
1472 &valleyview_wm_info, pessimal_latency_ns,
1473 &valleyview_cursor_wm_info, pessimal_latency_ns,
1474 &planea_wm, &cursora_wm))
1475 enabled |= 1 << PIPE_A;
1476
1477 if (g4x_compute_wm0(dev, PIPE_B,
1478 &valleyview_wm_info, pessimal_latency_ns,
1479 &valleyview_cursor_wm_info, pessimal_latency_ns,
1480 &planeb_wm, &cursorb_wm))
1481 enabled |= 1 << PIPE_B;
1482
1483 if (g4x_compute_wm0(dev, PIPE_C,
1484 &valleyview_wm_info, pessimal_latency_ns,
1485 &valleyview_cursor_wm_info, pessimal_latency_ns,
1486 &planec_wm, &cursorc_wm))
1487 enabled |= 1 << PIPE_C;
1488
1489 if (single_plane_enabled(enabled) &&
1490 g4x_compute_srwm(dev, ffs(enabled) - 1,
1491 sr_latency_ns,
1492 &valleyview_wm_info,
1493 &valleyview_cursor_wm_info,
1494 &plane_sr, &ignore_cursor_sr) &&
1495 g4x_compute_srwm(dev, ffs(enabled) - 1,
1496 2*sr_latency_ns,
1497 &valleyview_wm_info,
1498 &valleyview_cursor_wm_info,
1499 &ignore_plane_sr, &cursor_sr)) {
1500 cxsr_enabled = true;
1501 } else {
1502 cxsr_enabled = false;
1503 intel_set_memory_cxsr(dev_priv, false);
1504 plane_sr = cursor_sr = 0;
1505 }
1506
1507 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1508 "B: plane=%d, cursor=%d, C: plane=%d, cursor=%d, "
1509 "SR: plane=%d, cursor=%d\n",
1510 planea_wm, cursora_wm,
1511 planeb_wm, cursorb_wm,
1512 planec_wm, cursorc_wm,
1513 plane_sr, cursor_sr);
1514
1515 I915_WRITE(DSPFW1,
1516 (plane_sr << DSPFW_SR_SHIFT) |
1517 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1518 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1519 (planea_wm << DSPFW_PLANEA_SHIFT));
1520 I915_WRITE(DSPFW2,
1521 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1522 (cursora_wm << DSPFW_CURSORA_SHIFT));
1523 I915_WRITE(DSPFW3,
1524 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1525 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1526 I915_WRITE(DSPFW9_CHV,
1527 (I915_READ(DSPFW9_CHV) & ~(DSPFW_PLANEC_MASK |
1528 DSPFW_CURSORC_MASK)) |
1529 (planec_wm << DSPFW_PLANEC_SHIFT) |
1530 (cursorc_wm << DSPFW_CURSORC_SHIFT));
1531
1532 if (cxsr_enabled)
1533 intel_set_memory_cxsr(dev_priv, true);
1534 }
1535
1536 static void valleyview_update_sprite_wm(struct drm_plane *plane,
1537 struct drm_crtc *crtc,
1538 uint32_t sprite_width,
1539 uint32_t sprite_height,
1540 int pixel_size,
1541 bool enabled, bool scaled)
1542 {
1543 struct drm_device *dev = crtc->dev;
1544 struct drm_i915_private *dev_priv = dev->dev_private;
1545 int pipe = to_intel_plane(plane)->pipe;
1546 int sprite = to_intel_plane(plane)->plane;
1547 int drain_latency;
1548 int plane_prec;
1549 int sprite_dl;
1550 int prec_mult;
1551
1552 sprite_dl = I915_READ(VLV_DDL(pipe)) & ~(DDL_SPRITE_PRECISION_64(sprite) |
1553 (DRAIN_LATENCY_MASK << DDL_SPRITE_SHIFT(sprite)));
1554
1555 if (enabled && vlv_compute_drain_latency(crtc, pixel_size, &prec_mult,
1556 &drain_latency)) {
1557 plane_prec = (prec_mult == DRAIN_LATENCY_PRECISION_64) ?
1558 DDL_SPRITE_PRECISION_64(sprite) :
1559 DDL_SPRITE_PRECISION_32(sprite);
1560 sprite_dl |= plane_prec |
1561 (drain_latency << DDL_SPRITE_SHIFT(sprite));
1562 }
1563
1564 I915_WRITE(VLV_DDL(pipe), sprite_dl);
1565 }
1566
1567 static void g4x_update_wm(struct drm_crtc *crtc)
1568 {
1569 struct drm_device *dev = crtc->dev;
1570 static const int sr_latency_ns = 12000;
1571 struct drm_i915_private *dev_priv = dev->dev_private;
1572 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1573 int plane_sr, cursor_sr;
1574 unsigned int enabled = 0;
1575 bool cxsr_enabled;
1576
1577 if (g4x_compute_wm0(dev, PIPE_A,
1578 &g4x_wm_info, pessimal_latency_ns,
1579 &g4x_cursor_wm_info, pessimal_latency_ns,
1580 &planea_wm, &cursora_wm))
1581 enabled |= 1 << PIPE_A;
1582
1583 if (g4x_compute_wm0(dev, PIPE_B,
1584 &g4x_wm_info, pessimal_latency_ns,
1585 &g4x_cursor_wm_info, pessimal_latency_ns,
1586 &planeb_wm, &cursorb_wm))
1587 enabled |= 1 << PIPE_B;
1588
1589 if (single_plane_enabled(enabled) &&
1590 g4x_compute_srwm(dev, ffs(enabled) - 1,
1591 sr_latency_ns,
1592 &g4x_wm_info,
1593 &g4x_cursor_wm_info,
1594 &plane_sr, &cursor_sr)) {
1595 cxsr_enabled = true;
1596 } else {
1597 cxsr_enabled = false;
1598 intel_set_memory_cxsr(dev_priv, false);
1599 plane_sr = cursor_sr = 0;
1600 }
1601
1602 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1603 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1604 planea_wm, cursora_wm,
1605 planeb_wm, cursorb_wm,
1606 plane_sr, cursor_sr);
1607
1608 I915_WRITE(DSPFW1,
1609 (plane_sr << DSPFW_SR_SHIFT) |
1610 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1611 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1612 (planea_wm << DSPFW_PLANEA_SHIFT));
1613 I915_WRITE(DSPFW2,
1614 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1615 (cursora_wm << DSPFW_CURSORA_SHIFT));
1616 /* HPLL off in SR has some issues on G4x... disable it */
1617 I915_WRITE(DSPFW3,
1618 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1619 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1620
1621 if (cxsr_enabled)
1622 intel_set_memory_cxsr(dev_priv, true);
1623 }
1624
1625 static void i965_update_wm(struct drm_crtc *unused_crtc)
1626 {
1627 struct drm_device *dev = unused_crtc->dev;
1628 struct drm_i915_private *dev_priv = dev->dev_private;
1629 struct drm_crtc *crtc;
1630 int srwm = 1;
1631 int cursor_sr = 16;
1632 bool cxsr_enabled;
1633
1634 /* Calc sr entries for one plane configs */
1635 crtc = single_enabled_crtc(dev);
1636 if (crtc) {
1637 /* self-refresh has much higher latency */
1638 static const int sr_latency_ns = 12000;
1639 const struct drm_display_mode *adjusted_mode =
1640 &to_intel_crtc(crtc)->config.adjusted_mode;
1641 int clock = adjusted_mode->crtc_clock;
1642 int htotal = adjusted_mode->crtc_htotal;
1643 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1644 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1645 unsigned long line_time_us;
1646 int entries;
1647
1648 line_time_us = max(htotal * 1000 / clock, 1);
1649
1650 /* Use ns/us then divide to preserve precision */
1651 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1652 pixel_size * hdisplay;
1653 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1654 srwm = I965_FIFO_SIZE - entries;
1655 if (srwm < 0)
1656 srwm = 1;
1657 srwm &= 0x1ff;
1658 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1659 entries, srwm);
1660
1661 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1662 pixel_size * to_intel_crtc(crtc)->cursor_width;
1663 entries = DIV_ROUND_UP(entries,
1664 i965_cursor_wm_info.cacheline_size);
1665 cursor_sr = i965_cursor_wm_info.fifo_size -
1666 (entries + i965_cursor_wm_info.guard_size);
1667
1668 if (cursor_sr > i965_cursor_wm_info.max_wm)
1669 cursor_sr = i965_cursor_wm_info.max_wm;
1670
1671 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1672 "cursor %d\n", srwm, cursor_sr);
1673
1674 cxsr_enabled = true;
1675 } else {
1676 cxsr_enabled = false;
1677 /* Turn off self refresh if both pipes are enabled */
1678 intel_set_memory_cxsr(dev_priv, false);
1679 }
1680
1681 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1682 srwm);
1683
1684 /* 965 has limitations... */
1685 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1686 (8 << DSPFW_CURSORB_SHIFT) |
1687 (8 << DSPFW_PLANEB_SHIFT) |
1688 (8 << DSPFW_PLANEA_SHIFT));
1689 I915_WRITE(DSPFW2, (8 << DSPFW_CURSORA_SHIFT) |
1690 (8 << DSPFW_PLANEC_SHIFT_OLD));
1691 /* update cursor SR watermark */
1692 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1693
1694 if (cxsr_enabled)
1695 intel_set_memory_cxsr(dev_priv, true);
1696 }
1697
1698 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1699 {
1700 struct drm_device *dev = unused_crtc->dev;
1701 struct drm_i915_private *dev_priv = dev->dev_private;
1702 const struct intel_watermark_params *wm_info;
1703 uint32_t fwater_lo;
1704 uint32_t fwater_hi;
1705 int cwm, srwm = 1;
1706 int fifo_size;
1707 int planea_wm, planeb_wm;
1708 struct drm_crtc *crtc, *enabled = NULL;
1709
1710 if (IS_I945GM(dev))
1711 wm_info = &i945_wm_info;
1712 else if (!IS_GEN2(dev))
1713 wm_info = &i915_wm_info;
1714 else
1715 wm_info = &i830_a_wm_info;
1716
1717 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1718 crtc = intel_get_crtc_for_plane(dev, 0);
1719 if (intel_crtc_active(crtc)) {
1720 const struct drm_display_mode *adjusted_mode;
1721 int cpp = crtc->primary->fb->bits_per_pixel / 8;
1722 if (IS_GEN2(dev))
1723 cpp = 4;
1724
1725 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1726 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1727 wm_info, fifo_size, cpp,
1728 pessimal_latency_ns);
1729 enabled = crtc;
1730 } else {
1731 planea_wm = fifo_size - wm_info->guard_size;
1732 if (planea_wm > (long)wm_info->max_wm)
1733 planea_wm = wm_info->max_wm;
1734 }
1735
1736 if (IS_GEN2(dev))
1737 wm_info = &i830_bc_wm_info;
1738
1739 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1740 crtc = intel_get_crtc_for_plane(dev, 1);
1741 if (intel_crtc_active(crtc)) {
1742 const struct drm_display_mode *adjusted_mode;
1743 int cpp = crtc->primary->fb->bits_per_pixel / 8;
1744 if (IS_GEN2(dev))
1745 cpp = 4;
1746
1747 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1748 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1749 wm_info, fifo_size, cpp,
1750 pessimal_latency_ns);
1751 if (enabled == NULL)
1752 enabled = crtc;
1753 else
1754 enabled = NULL;
1755 } else {
1756 planeb_wm = fifo_size - wm_info->guard_size;
1757 if (planeb_wm > (long)wm_info->max_wm)
1758 planeb_wm = wm_info->max_wm;
1759 }
1760
1761 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1762
1763 if (IS_I915GM(dev) && enabled) {
1764 struct drm_i915_gem_object *obj;
1765
1766 obj = intel_fb_obj(enabled->primary->fb);
1767
1768 /* self-refresh seems busted with untiled */
1769 if (obj->tiling_mode == I915_TILING_NONE)
1770 enabled = NULL;
1771 }
1772
1773 /*
1774 * Overlay gets an aggressive default since video jitter is bad.
1775 */
1776 cwm = 2;
1777
1778 /* Play safe and disable self-refresh before adjusting watermarks. */
1779 intel_set_memory_cxsr(dev_priv, false);
1780
1781 /* Calc sr entries for one plane configs */
1782 if (HAS_FW_BLC(dev) && enabled) {
1783 /* self-refresh has much higher latency */
1784 static const int sr_latency_ns = 6000;
1785 const struct drm_display_mode *adjusted_mode =
1786 &to_intel_crtc(enabled)->config.adjusted_mode;
1787 int clock = adjusted_mode->crtc_clock;
1788 int htotal = adjusted_mode->crtc_htotal;
1789 int hdisplay = to_intel_crtc(enabled)->config.pipe_src_w;
1790 int pixel_size = enabled->primary->fb->bits_per_pixel / 8;
1791 unsigned long line_time_us;
1792 int entries;
1793
1794 line_time_us = max(htotal * 1000 / clock, 1);
1795
1796 /* Use ns/us then divide to preserve precision */
1797 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1798 pixel_size * hdisplay;
1799 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1800 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1801 srwm = wm_info->fifo_size - entries;
1802 if (srwm < 0)
1803 srwm = 1;
1804
1805 if (IS_I945G(dev) || IS_I945GM(dev))
1806 I915_WRITE(FW_BLC_SELF,
1807 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1808 else if (IS_I915GM(dev))
1809 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1810 }
1811
1812 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1813 planea_wm, planeb_wm, cwm, srwm);
1814
1815 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1816 fwater_hi = (cwm & 0x1f);
1817
1818 /* Set request length to 8 cachelines per fetch */
1819 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1820 fwater_hi = fwater_hi | (1 << 8);
1821
1822 I915_WRITE(FW_BLC, fwater_lo);
1823 I915_WRITE(FW_BLC2, fwater_hi);
1824
1825 if (enabled)
1826 intel_set_memory_cxsr(dev_priv, true);
1827 }
1828
1829 static void i845_update_wm(struct drm_crtc *unused_crtc)
1830 {
1831 struct drm_device *dev = unused_crtc->dev;
1832 struct drm_i915_private *dev_priv = dev->dev_private;
1833 struct drm_crtc *crtc;
1834 const struct drm_display_mode *adjusted_mode;
1835 uint32_t fwater_lo;
1836 int planea_wm;
1837
1838 crtc = single_enabled_crtc(dev);
1839 if (crtc == NULL)
1840 return;
1841
1842 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1843 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1844 &i845_wm_info,
1845 dev_priv->display.get_fifo_size(dev, 0),
1846 4, pessimal_latency_ns);
1847 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1848 fwater_lo |= (3<<8) | planea_wm;
1849
1850 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1851
1852 I915_WRITE(FW_BLC, fwater_lo);
1853 }
1854
1855 static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
1856 struct drm_crtc *crtc)
1857 {
1858 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1859 uint32_t pixel_rate;
1860
1861 pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock;
1862
1863 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1864 * adjust the pixel_rate here. */
1865
1866 if (intel_crtc->config.pch_pfit.enabled) {
1867 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1868 uint32_t pfit_size = intel_crtc->config.pch_pfit.size;
1869
1870 pipe_w = intel_crtc->config.pipe_src_w;
1871 pipe_h = intel_crtc->config.pipe_src_h;
1872 pfit_w = (pfit_size >> 16) & 0xFFFF;
1873 pfit_h = pfit_size & 0xFFFF;
1874 if (pipe_w < pfit_w)
1875 pipe_w = pfit_w;
1876 if (pipe_h < pfit_h)
1877 pipe_h = pfit_h;
1878
1879 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1880 pfit_w * pfit_h);
1881 }
1882
1883 return pixel_rate;
1884 }
1885
1886 /* latency must be in 0.1us units. */
1887 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
1888 uint32_t latency)
1889 {
1890 uint64_t ret;
1891
1892 if (WARN(latency == 0, "Latency value missing\n"))
1893 return UINT_MAX;
1894
1895 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1896 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1897
1898 return ret;
1899 }
1900
1901 /* latency must be in 0.1us units. */
1902 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1903 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1904 uint32_t latency)
1905 {
1906 uint32_t ret;
1907
1908 if (WARN(latency == 0, "Latency value missing\n"))
1909 return UINT_MAX;
1910
1911 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1912 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1913 ret = DIV_ROUND_UP(ret, 64) + 2;
1914 return ret;
1915 }
1916
1917 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1918 uint8_t bytes_per_pixel)
1919 {
1920 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1921 }
1922
1923 struct ilk_pipe_wm_parameters {
1924 bool active;
1925 uint32_t pipe_htotal;
1926 uint32_t pixel_rate;
1927 struct intel_plane_wm_parameters pri;
1928 struct intel_plane_wm_parameters spr;
1929 struct intel_plane_wm_parameters cur;
1930 };
1931
1932 struct ilk_wm_maximums {
1933 uint16_t pri;
1934 uint16_t spr;
1935 uint16_t cur;
1936 uint16_t fbc;
1937 };
1938
1939 /* used in computing the new watermarks state */
1940 struct intel_wm_config {
1941 unsigned int num_pipes_active;
1942 bool sprites_enabled;
1943 bool sprites_scaled;
1944 };
1945
1946 /*
1947 * For both WM_PIPE and WM_LP.
1948 * mem_value must be in 0.1us units.
1949 */
1950 static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params,
1951 uint32_t mem_value,
1952 bool is_lp)
1953 {
1954 uint32_t method1, method2;
1955
1956 if (!params->active || !params->pri.enabled)
1957 return 0;
1958
1959 method1 = ilk_wm_method1(params->pixel_rate,
1960 params->pri.bytes_per_pixel,
1961 mem_value);
1962
1963 if (!is_lp)
1964 return method1;
1965
1966 method2 = ilk_wm_method2(params->pixel_rate,
1967 params->pipe_htotal,
1968 params->pri.horiz_pixels,
1969 params->pri.bytes_per_pixel,
1970 mem_value);
1971
1972 return min(method1, method2);
1973 }
1974
1975 /*
1976 * For both WM_PIPE and WM_LP.
1977 * mem_value must be in 0.1us units.
1978 */
1979 static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params,
1980 uint32_t mem_value)
1981 {
1982 uint32_t method1, method2;
1983
1984 if (!params->active || !params->spr.enabled)
1985 return 0;
1986
1987 method1 = ilk_wm_method1(params->pixel_rate,
1988 params->spr.bytes_per_pixel,
1989 mem_value);
1990 method2 = ilk_wm_method2(params->pixel_rate,
1991 params->pipe_htotal,
1992 params->spr.horiz_pixels,
1993 params->spr.bytes_per_pixel,
1994 mem_value);
1995 return min(method1, method2);
1996 }
1997
1998 /*
1999 * For both WM_PIPE and WM_LP.
2000 * mem_value must be in 0.1us units.
2001 */
2002 static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params,
2003 uint32_t mem_value)
2004 {
2005 if (!params->active || !params->cur.enabled)
2006 return 0;
2007
2008 return ilk_wm_method2(params->pixel_rate,
2009 params->pipe_htotal,
2010 params->cur.horiz_pixels,
2011 params->cur.bytes_per_pixel,
2012 mem_value);
2013 }
2014
2015 /* Only for WM_LP. */
2016 static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params,
2017 uint32_t pri_val)
2018 {
2019 if (!params->active || !params->pri.enabled)
2020 return 0;
2021
2022 return ilk_wm_fbc(pri_val,
2023 params->pri.horiz_pixels,
2024 params->pri.bytes_per_pixel);
2025 }
2026
2027 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
2028 {
2029 if (INTEL_INFO(dev)->gen >= 8)
2030 return 3072;
2031 else if (INTEL_INFO(dev)->gen >= 7)
2032 return 768;
2033 else
2034 return 512;
2035 }
2036
2037 static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
2038 int level, bool is_sprite)
2039 {
2040 if (INTEL_INFO(dev)->gen >= 8)
2041 /* BDW primary/sprite plane watermarks */
2042 return level == 0 ? 255 : 2047;
2043 else if (INTEL_INFO(dev)->gen >= 7)
2044 /* IVB/HSW primary/sprite plane watermarks */
2045 return level == 0 ? 127 : 1023;
2046 else if (!is_sprite)
2047 /* ILK/SNB primary plane watermarks */
2048 return level == 0 ? 127 : 511;
2049 else
2050 /* ILK/SNB sprite plane watermarks */
2051 return level == 0 ? 63 : 255;
2052 }
2053
2054 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
2055 int level)
2056 {
2057 if (INTEL_INFO(dev)->gen >= 7)
2058 return level == 0 ? 63 : 255;
2059 else
2060 return level == 0 ? 31 : 63;
2061 }
2062
2063 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
2064 {
2065 if (INTEL_INFO(dev)->gen >= 8)
2066 return 31;
2067 else
2068 return 15;
2069 }
2070
2071 /* Calculate the maximum primary/sprite plane watermark */
2072 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
2073 int level,
2074 const struct intel_wm_config *config,
2075 enum intel_ddb_partitioning ddb_partitioning,
2076 bool is_sprite)
2077 {
2078 unsigned int fifo_size = ilk_display_fifo_size(dev);
2079
2080 /* if sprites aren't enabled, sprites get nothing */
2081 if (is_sprite && !config->sprites_enabled)
2082 return 0;
2083
2084 /* HSW allows LP1+ watermarks even with multiple pipes */
2085 if (level == 0 || config->num_pipes_active > 1) {
2086 fifo_size /= INTEL_INFO(dev)->num_pipes;
2087
2088 /*
2089 * For some reason the non self refresh
2090 * FIFO size is only half of the self
2091 * refresh FIFO size on ILK/SNB.
2092 */
2093 if (INTEL_INFO(dev)->gen <= 6)
2094 fifo_size /= 2;
2095 }
2096
2097 if (config->sprites_enabled) {
2098 /* level 0 is always calculated with 1:1 split */
2099 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
2100 if (is_sprite)
2101 fifo_size *= 5;
2102 fifo_size /= 6;
2103 } else {
2104 fifo_size /= 2;
2105 }
2106 }
2107
2108 /* clamp to max that the registers can hold */
2109 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
2110 }
2111
2112 /* Calculate the maximum cursor plane watermark */
2113 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
2114 int level,
2115 const struct intel_wm_config *config)
2116 {
2117 /* HSW LP1+ watermarks w/ multiple pipes */
2118 if (level > 0 && config->num_pipes_active > 1)
2119 return 64;
2120
2121 /* otherwise just report max that registers can hold */
2122 return ilk_cursor_wm_reg_max(dev, level);
2123 }
2124
2125 static void ilk_compute_wm_maximums(const struct drm_device *dev,
2126 int level,
2127 const struct intel_wm_config *config,
2128 enum intel_ddb_partitioning ddb_partitioning,
2129 struct ilk_wm_maximums *max)
2130 {
2131 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
2132 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
2133 max->cur = ilk_cursor_wm_max(dev, level, config);
2134 max->fbc = ilk_fbc_wm_reg_max(dev);
2135 }
2136
2137 static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
2138 int level,
2139 struct ilk_wm_maximums *max)
2140 {
2141 max->pri = ilk_plane_wm_reg_max(dev, level, false);
2142 max->spr = ilk_plane_wm_reg_max(dev, level, true);
2143 max->cur = ilk_cursor_wm_reg_max(dev, level);
2144 max->fbc = ilk_fbc_wm_reg_max(dev);
2145 }
2146
2147 static bool ilk_validate_wm_level(int level,
2148 const struct ilk_wm_maximums *max,
2149 struct intel_wm_level *result)
2150 {
2151 bool ret;
2152
2153 /* already determined to be invalid? */
2154 if (!result->enable)
2155 return false;
2156
2157 result->enable = result->pri_val <= max->pri &&
2158 result->spr_val <= max->spr &&
2159 result->cur_val <= max->cur;
2160
2161 ret = result->enable;
2162
2163 /*
2164 * HACK until we can pre-compute everything,
2165 * and thus fail gracefully if LP0 watermarks
2166 * are exceeded...
2167 */
2168 if (level == 0 && !result->enable) {
2169 if (result->pri_val > max->pri)
2170 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2171 level, result->pri_val, max->pri);
2172 if (result->spr_val > max->spr)
2173 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2174 level, result->spr_val, max->spr);
2175 if (result->cur_val > max->cur)
2176 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2177 level, result->cur_val, max->cur);
2178
2179 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2180 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2181 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2182 result->enable = true;
2183 }
2184
2185 return ret;
2186 }
2187
2188 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
2189 int level,
2190 const struct ilk_pipe_wm_parameters *p,
2191 struct intel_wm_level *result)
2192 {
2193 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2194 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2195 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2196
2197 /* WM1+ latency values stored in 0.5us units */
2198 if (level > 0) {
2199 pri_latency *= 5;
2200 spr_latency *= 5;
2201 cur_latency *= 5;
2202 }
2203
2204 result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
2205 result->spr_val = ilk_compute_spr_wm(p, spr_latency);
2206 result->cur_val = ilk_compute_cur_wm(p, cur_latency);
2207 result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
2208 result->enable = true;
2209 }
2210
2211 static uint32_t
2212 hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
2213 {
2214 struct drm_i915_private *dev_priv = dev->dev_private;
2215 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2216 struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
2217 u32 linetime, ips_linetime;
2218
2219 if (!intel_crtc_active(crtc))
2220 return 0;
2221
2222 /* The WM are computed with base on how long it takes to fill a single
2223 * row at the given clock rate, multiplied by 8.
2224 * */
2225 linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
2226 mode->crtc_clock);
2227 ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
2228 intel_ddi_get_cdclk_freq(dev_priv));
2229
2230 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2231 PIPE_WM_LINETIME_TIME(linetime);
2232 }
2233
2234 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5])
2235 {
2236 struct drm_i915_private *dev_priv = dev->dev_private;
2237
2238 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2239 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2240
2241 wm[0] = (sskpd >> 56) & 0xFF;
2242 if (wm[0] == 0)
2243 wm[0] = sskpd & 0xF;
2244 wm[1] = (sskpd >> 4) & 0xFF;
2245 wm[2] = (sskpd >> 12) & 0xFF;
2246 wm[3] = (sskpd >> 20) & 0x1FF;
2247 wm[4] = (sskpd >> 32) & 0x1FF;
2248 } else if (INTEL_INFO(dev)->gen >= 6) {
2249 uint32_t sskpd = I915_READ(MCH_SSKPD);
2250
2251 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2252 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2253 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2254 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2255 } else if (INTEL_INFO(dev)->gen >= 5) {
2256 uint32_t mltr = I915_READ(MLTR_ILK);
2257
2258 /* ILK primary LP0 latency is 700 ns */
2259 wm[0] = 7;
2260 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2261 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2262 }
2263 }
2264
2265 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2266 {
2267 /* ILK sprite LP0 latency is 1300 ns */
2268 if (INTEL_INFO(dev)->gen == 5)
2269 wm[0] = 13;
2270 }
2271
2272 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2273 {
2274 /* ILK cursor LP0 latency is 1300 ns */
2275 if (INTEL_INFO(dev)->gen == 5)
2276 wm[0] = 13;
2277
2278 /* WaDoubleCursorLP3Latency:ivb */
2279 if (IS_IVYBRIDGE(dev))
2280 wm[3] *= 2;
2281 }
2282
2283 int ilk_wm_max_level(const struct drm_device *dev)
2284 {
2285 /* how many WM levels are we expecting */
2286 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2287 return 4;
2288 else if (INTEL_INFO(dev)->gen >= 6)
2289 return 3;
2290 else
2291 return 2;
2292 }
2293 static void intel_print_wm_latency(struct drm_device *dev,
2294 const char *name,
2295 const uint16_t wm[5])
2296 {
2297 int level, max_level = ilk_wm_max_level(dev);
2298
2299 for (level = 0; level <= max_level; level++) {
2300 unsigned int latency = wm[level];
2301
2302 if (latency == 0) {
2303 DRM_ERROR("%s WM%d latency not provided\n",
2304 name, level);
2305 continue;
2306 }
2307
2308 /* WM1+ latency values in 0.5us units */
2309 if (level > 0)
2310 latency *= 5;
2311
2312 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2313 name, level, wm[level],
2314 latency / 10, latency % 10);
2315 }
2316 }
2317
2318 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2319 uint16_t wm[5], uint16_t min)
2320 {
2321 int level, max_level = ilk_wm_max_level(dev_priv->dev);
2322
2323 if (wm[0] >= min)
2324 return false;
2325
2326 wm[0] = max(wm[0], min);
2327 for (level = 1; level <= max_level; level++)
2328 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2329
2330 return true;
2331 }
2332
2333 static void snb_wm_latency_quirk(struct drm_device *dev)
2334 {
2335 struct drm_i915_private *dev_priv = dev->dev_private;
2336 bool changed;
2337
2338 /*
2339 * The BIOS provided WM memory latency values are often
2340 * inadequate for high resolution displays. Adjust them.
2341 */
2342 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2343 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2344 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2345
2346 if (!changed)
2347 return;
2348
2349 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2350 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2351 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2352 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2353 }
2354
2355 static void ilk_setup_wm_latency(struct drm_device *dev)
2356 {
2357 struct drm_i915_private *dev_priv = dev->dev_private;
2358
2359 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2360
2361 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2362 sizeof(dev_priv->wm.pri_latency));
2363 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2364 sizeof(dev_priv->wm.pri_latency));
2365
2366 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2367 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2368
2369 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2370 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2371 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2372
2373 if (IS_GEN6(dev))
2374 snb_wm_latency_quirk(dev);
2375 }
2376
2377 static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
2378 struct ilk_pipe_wm_parameters *p)
2379 {
2380 struct drm_device *dev = crtc->dev;
2381 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2382 enum pipe pipe = intel_crtc->pipe;
2383 struct drm_plane *plane;
2384
2385 if (!intel_crtc_active(crtc))
2386 return;
2387
2388 p->active = true;
2389 p->pipe_htotal = intel_crtc->config.adjusted_mode.crtc_htotal;
2390 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
2391 p->pri.bytes_per_pixel = crtc->primary->fb->bits_per_pixel / 8;
2392 p->cur.bytes_per_pixel = 4;
2393 p->pri.horiz_pixels = intel_crtc->config.pipe_src_w;
2394 p->cur.horiz_pixels = intel_crtc->cursor_width;
2395 /* TODO: for now, assume primary and cursor planes are always enabled. */
2396 p->pri.enabled = true;
2397 p->cur.enabled = true;
2398
2399 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
2400 struct intel_plane *intel_plane = to_intel_plane(plane);
2401
2402 if (intel_plane->pipe == pipe) {
2403 p->spr = intel_plane->wm;
2404 break;
2405 }
2406 }
2407 }
2408
2409 static void ilk_compute_wm_config(struct drm_device *dev,
2410 struct intel_wm_config *config)
2411 {
2412 struct intel_crtc *intel_crtc;
2413
2414 /* Compute the currently _active_ config */
2415 for_each_intel_crtc(dev, intel_crtc) {
2416 const struct intel_pipe_wm *wm = &intel_crtc->wm.active;
2417
2418 if (!wm->pipe_enabled)
2419 continue;
2420
2421 config->sprites_enabled |= wm->sprites_enabled;
2422 config->sprites_scaled |= wm->sprites_scaled;
2423 config->num_pipes_active++;
2424 }
2425 }
2426
2427 /* Compute new watermarks for the pipe */
2428 static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
2429 const struct ilk_pipe_wm_parameters *params,
2430 struct intel_pipe_wm *pipe_wm)
2431 {
2432 struct drm_device *dev = crtc->dev;
2433 const struct drm_i915_private *dev_priv = dev->dev_private;
2434 int level, max_level = ilk_wm_max_level(dev);
2435 /* LP0 watermark maximums depend on this pipe alone */
2436 struct intel_wm_config config = {
2437 .num_pipes_active = 1,
2438 .sprites_enabled = params->spr.enabled,
2439 .sprites_scaled = params->spr.scaled,
2440 };
2441 struct ilk_wm_maximums max;
2442
2443 pipe_wm->pipe_enabled = params->active;
2444 pipe_wm->sprites_enabled = params->spr.enabled;
2445 pipe_wm->sprites_scaled = params->spr.scaled;
2446
2447 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2448 if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled)
2449 max_level = 1;
2450
2451 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2452 if (params->spr.scaled)
2453 max_level = 0;
2454
2455 ilk_compute_wm_level(dev_priv, 0, params, &pipe_wm->wm[0]);
2456
2457 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2458 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
2459
2460 /* LP0 watermarks always use 1/2 DDB partitioning */
2461 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2462
2463 /* At least LP0 must be valid */
2464 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
2465 return false;
2466
2467 ilk_compute_wm_reg_maximums(dev, 1, &max);
2468
2469 for (level = 1; level <= max_level; level++) {
2470 struct intel_wm_level wm = {};
2471
2472 ilk_compute_wm_level(dev_priv, level, params, &wm);
2473
2474 /*
2475 * Disable any watermark level that exceeds the
2476 * register maximums since such watermarks are
2477 * always invalid.
2478 */
2479 if (!ilk_validate_wm_level(level, &max, &wm))
2480 break;
2481
2482 pipe_wm->wm[level] = wm;
2483 }
2484
2485 return true;
2486 }
2487
2488 /*
2489 * Merge the watermarks from all active pipes for a specific level.
2490 */
2491 static void ilk_merge_wm_level(struct drm_device *dev,
2492 int level,
2493 struct intel_wm_level *ret_wm)
2494 {
2495 const struct intel_crtc *intel_crtc;
2496
2497 ret_wm->enable = true;
2498
2499 for_each_intel_crtc(dev, intel_crtc) {
2500 const struct intel_pipe_wm *active = &intel_crtc->wm.active;
2501 const struct intel_wm_level *wm = &active->wm[level];
2502
2503 if (!active->pipe_enabled)
2504 continue;
2505
2506 /*
2507 * The watermark values may have been used in the past,
2508 * so we must maintain them in the registers for some
2509 * time even if the level is now disabled.
2510 */
2511 if (!wm->enable)
2512 ret_wm->enable = false;
2513
2514 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2515 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2516 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2517 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2518 }
2519 }
2520
2521 /*
2522 * Merge all low power watermarks for all active pipes.
2523 */
2524 static void ilk_wm_merge(struct drm_device *dev,
2525 const struct intel_wm_config *config,
2526 const struct ilk_wm_maximums *max,
2527 struct intel_pipe_wm *merged)
2528 {
2529 int level, max_level = ilk_wm_max_level(dev);
2530 int last_enabled_level = max_level;
2531
2532 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2533 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2534 config->num_pipes_active > 1)
2535 return;
2536
2537 /* ILK: FBC WM must be disabled always */
2538 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
2539
2540 /* merge each WM1+ level */
2541 for (level = 1; level <= max_level; level++) {
2542 struct intel_wm_level *wm = &merged->wm[level];
2543
2544 ilk_merge_wm_level(dev, level, wm);
2545
2546 if (level > last_enabled_level)
2547 wm->enable = false;
2548 else if (!ilk_validate_wm_level(level, max, wm))
2549 /* make sure all following levels get disabled */
2550 last_enabled_level = level - 1;
2551
2552 /*
2553 * The spec says it is preferred to disable
2554 * FBC WMs instead of disabling a WM level.
2555 */
2556 if (wm->fbc_val > max->fbc) {
2557 if (wm->enable)
2558 merged->fbc_wm_enabled = false;
2559 wm->fbc_val = 0;
2560 }
2561 }
2562
2563 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2564 /*
2565 * FIXME this is racy. FBC might get enabled later.
2566 * What we should check here is whether FBC can be
2567 * enabled sometime later.
2568 */
2569 if (IS_GEN5(dev) && !merged->fbc_wm_enabled && intel_fbc_enabled(dev)) {
2570 for (level = 2; level <= max_level; level++) {
2571 struct intel_wm_level *wm = &merged->wm[level];
2572
2573 wm->enable = false;
2574 }
2575 }
2576 }
2577
2578 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2579 {
2580 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2581 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2582 }
2583
2584 /* The value we need to program into the WM_LPx latency field */
2585 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2586 {
2587 struct drm_i915_private *dev_priv = dev->dev_private;
2588
2589 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2590 return 2 * level;
2591 else
2592 return dev_priv->wm.pri_latency[level];
2593 }
2594
2595 static void ilk_compute_wm_results(struct drm_device *dev,
2596 const struct intel_pipe_wm *merged,
2597 enum intel_ddb_partitioning partitioning,
2598 struct ilk_wm_values *results)
2599 {
2600 struct intel_crtc *intel_crtc;
2601 int level, wm_lp;
2602
2603 results->enable_fbc_wm = merged->fbc_wm_enabled;
2604 results->partitioning = partitioning;
2605
2606 /* LP1+ register values */
2607 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2608 const struct intel_wm_level *r;
2609
2610 level = ilk_wm_lp_to_level(wm_lp, merged);
2611
2612 r = &merged->wm[level];
2613
2614 /*
2615 * Maintain the watermark values even if the level is
2616 * disabled. Doing otherwise could cause underruns.
2617 */
2618 results->wm_lp[wm_lp - 1] =
2619 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2620 (r->pri_val << WM1_LP_SR_SHIFT) |
2621 r->cur_val;
2622
2623 if (r->enable)
2624 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2625
2626 if (INTEL_INFO(dev)->gen >= 8)
2627 results->wm_lp[wm_lp - 1] |=
2628 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2629 else
2630 results->wm_lp[wm_lp - 1] |=
2631 r->fbc_val << WM1_LP_FBC_SHIFT;
2632
2633 /*
2634 * Always set WM1S_LP_EN when spr_val != 0, even if the
2635 * level is disabled. Doing otherwise could cause underruns.
2636 */
2637 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2638 WARN_ON(wm_lp != 1);
2639 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2640 } else
2641 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2642 }
2643
2644 /* LP0 register values */
2645 for_each_intel_crtc(dev, intel_crtc) {
2646 enum pipe pipe = intel_crtc->pipe;
2647 const struct intel_wm_level *r =
2648 &intel_crtc->wm.active.wm[0];
2649
2650 if (WARN_ON(!r->enable))
2651 continue;
2652
2653 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
2654
2655 results->wm_pipe[pipe] =
2656 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2657 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2658 r->cur_val;
2659 }
2660 }
2661
2662 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2663 * case both are at the same level. Prefer r1 in case they're the same. */
2664 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2665 struct intel_pipe_wm *r1,
2666 struct intel_pipe_wm *r2)
2667 {
2668 int level, max_level = ilk_wm_max_level(dev);
2669 int level1 = 0, level2 = 0;
2670
2671 for (level = 1; level <= max_level; level++) {
2672 if (r1->wm[level].enable)
2673 level1 = level;
2674 if (r2->wm[level].enable)
2675 level2 = level;
2676 }
2677
2678 if (level1 == level2) {
2679 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2680 return r2;
2681 else
2682 return r1;
2683 } else if (level1 > level2) {
2684 return r1;
2685 } else {
2686 return r2;
2687 }
2688 }
2689
2690 /* dirty bits used to track which watermarks need changes */
2691 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2692 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2693 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2694 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2695 #define WM_DIRTY_FBC (1 << 24)
2696 #define WM_DIRTY_DDB (1 << 25)
2697
2698 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
2699 const struct ilk_wm_values *old,
2700 const struct ilk_wm_values *new)
2701 {
2702 unsigned int dirty = 0;
2703 enum pipe pipe;
2704 int wm_lp;
2705
2706 for_each_pipe(dev_priv, pipe) {
2707 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2708 dirty |= WM_DIRTY_LINETIME(pipe);
2709 /* Must disable LP1+ watermarks too */
2710 dirty |= WM_DIRTY_LP_ALL;
2711 }
2712
2713 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2714 dirty |= WM_DIRTY_PIPE(pipe);
2715 /* Must disable LP1+ watermarks too */
2716 dirty |= WM_DIRTY_LP_ALL;
2717 }
2718 }
2719
2720 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2721 dirty |= WM_DIRTY_FBC;
2722 /* Must disable LP1+ watermarks too */
2723 dirty |= WM_DIRTY_LP_ALL;
2724 }
2725
2726 if (old->partitioning != new->partitioning) {
2727 dirty |= WM_DIRTY_DDB;
2728 /* Must disable LP1+ watermarks too */
2729 dirty |= WM_DIRTY_LP_ALL;
2730 }
2731
2732 /* LP1+ watermarks already deemed dirty, no need to continue */
2733 if (dirty & WM_DIRTY_LP_ALL)
2734 return dirty;
2735
2736 /* Find the lowest numbered LP1+ watermark in need of an update... */
2737 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2738 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2739 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2740 break;
2741 }
2742
2743 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2744 for (; wm_lp <= 3; wm_lp++)
2745 dirty |= WM_DIRTY_LP(wm_lp);
2746
2747 return dirty;
2748 }
2749
2750 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2751 unsigned int dirty)
2752 {
2753 struct ilk_wm_values *previous = &dev_priv->wm.hw;
2754 bool changed = false;
2755
2756 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2757 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2758 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2759 changed = true;
2760 }
2761 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2762 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2763 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2764 changed = true;
2765 }
2766 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2767 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2768 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2769 changed = true;
2770 }
2771
2772 /*
2773 * Don't touch WM1S_LP_EN here.
2774 * Doing so could cause underruns.
2775 */
2776
2777 return changed;
2778 }
2779
2780 /*
2781 * The spec says we shouldn't write when we don't need, because every write
2782 * causes WMs to be re-evaluated, expending some power.
2783 */
2784 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2785 struct ilk_wm_values *results)
2786 {
2787 struct drm_device *dev = dev_priv->dev;
2788 struct ilk_wm_values *previous = &dev_priv->wm.hw;
2789 unsigned int dirty;
2790 uint32_t val;
2791
2792 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
2793 if (!dirty)
2794 return;
2795
2796 _ilk_disable_lp_wm(dev_priv, dirty);
2797
2798 if (dirty & WM_DIRTY_PIPE(PIPE_A))
2799 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2800 if (dirty & WM_DIRTY_PIPE(PIPE_B))
2801 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2802 if (dirty & WM_DIRTY_PIPE(PIPE_C))
2803 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2804
2805 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2806 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2807 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2808 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2809 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2810 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2811
2812 if (dirty & WM_DIRTY_DDB) {
2813 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2814 val = I915_READ(WM_MISC);
2815 if (results->partitioning == INTEL_DDB_PART_1_2)
2816 val &= ~WM_MISC_DATA_PARTITION_5_6;
2817 else
2818 val |= WM_MISC_DATA_PARTITION_5_6;
2819 I915_WRITE(WM_MISC, val);
2820 } else {
2821 val = I915_READ(DISP_ARB_CTL2);
2822 if (results->partitioning == INTEL_DDB_PART_1_2)
2823 val &= ~DISP_DATA_PARTITION_5_6;
2824 else
2825 val |= DISP_DATA_PARTITION_5_6;
2826 I915_WRITE(DISP_ARB_CTL2, val);
2827 }
2828 }
2829
2830 if (dirty & WM_DIRTY_FBC) {
2831 val = I915_READ(DISP_ARB_CTL);
2832 if (results->enable_fbc_wm)
2833 val &= ~DISP_FBC_WM_DIS;
2834 else
2835 val |= DISP_FBC_WM_DIS;
2836 I915_WRITE(DISP_ARB_CTL, val);
2837 }
2838
2839 if (dirty & WM_DIRTY_LP(1) &&
2840 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2841 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2842
2843 if (INTEL_INFO(dev)->gen >= 7) {
2844 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2845 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2846 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2847 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2848 }
2849
2850 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2851 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2852 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2853 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2854 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2855 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2856
2857 dev_priv->wm.hw = *results;
2858 }
2859
2860 static bool ilk_disable_lp_wm(struct drm_device *dev)
2861 {
2862 struct drm_i915_private *dev_priv = dev->dev_private;
2863
2864 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2865 }
2866
2867 static void ilk_update_wm(struct drm_crtc *crtc)
2868 {
2869 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2870 struct drm_device *dev = crtc->dev;
2871 struct drm_i915_private *dev_priv = dev->dev_private;
2872 struct ilk_wm_maximums max;
2873 struct ilk_pipe_wm_parameters params = {};
2874 struct ilk_wm_values results = {};
2875 enum intel_ddb_partitioning partitioning;
2876 struct intel_pipe_wm pipe_wm = {};
2877 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
2878 struct intel_wm_config config = {};
2879
2880 ilk_compute_wm_parameters(crtc, &params);
2881
2882 intel_compute_pipe_wm(crtc, &params, &pipe_wm);
2883
2884 if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
2885 return;
2886
2887 intel_crtc->wm.active = pipe_wm;
2888
2889 ilk_compute_wm_config(dev, &config);
2890
2891 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
2892 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
2893
2894 /* 5/6 split only in single pipe config on IVB+ */
2895 if (INTEL_INFO(dev)->gen >= 7 &&
2896 config.num_pipes_active == 1 && config.sprites_enabled) {
2897 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
2898 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
2899
2900 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
2901 } else {
2902 best_lp_wm = &lp_wm_1_2;
2903 }
2904
2905 partitioning = (best_lp_wm == &lp_wm_1_2) ?
2906 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
2907
2908 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
2909
2910 ilk_write_wm_values(dev_priv, &results);
2911 }
2912
2913 static void
2914 ilk_update_sprite_wm(struct drm_plane *plane,
2915 struct drm_crtc *crtc,
2916 uint32_t sprite_width, uint32_t sprite_height,
2917 int pixel_size, bool enabled, bool scaled)
2918 {
2919 struct drm_device *dev = plane->dev;
2920 struct intel_plane *intel_plane = to_intel_plane(plane);
2921
2922 intel_plane->wm.enabled = enabled;
2923 intel_plane->wm.scaled = scaled;
2924 intel_plane->wm.horiz_pixels = sprite_width;
2925 intel_plane->wm.vert_pixels = sprite_width;
2926 intel_plane->wm.bytes_per_pixel = pixel_size;
2927
2928 /*
2929 * IVB workaround: must disable low power watermarks for at least
2930 * one frame before enabling scaling. LP watermarks can be re-enabled
2931 * when scaling is disabled.
2932 *
2933 * WaCxSRDisabledForSpriteScaling:ivb
2934 */
2935 if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev))
2936 intel_wait_for_vblank(dev, intel_plane->pipe);
2937
2938 ilk_update_wm(crtc);
2939 }
2940
2941 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
2942 {
2943 struct drm_device *dev = crtc->dev;
2944 struct drm_i915_private *dev_priv = dev->dev_private;
2945 struct ilk_wm_values *hw = &dev_priv->wm.hw;
2946 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2947 struct intel_pipe_wm *active = &intel_crtc->wm.active;
2948 enum pipe pipe = intel_crtc->pipe;
2949 static const unsigned int wm0_pipe_reg[] = {
2950 [PIPE_A] = WM0_PIPEA_ILK,
2951 [PIPE_B] = WM0_PIPEB_ILK,
2952 [PIPE_C] = WM0_PIPEC_IVB,
2953 };
2954
2955 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
2956 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2957 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
2958
2959 active->pipe_enabled = intel_crtc_active(crtc);
2960
2961 if (active->pipe_enabled) {
2962 u32 tmp = hw->wm_pipe[pipe];
2963
2964 /*
2965 * For active pipes LP0 watermark is marked as
2966 * enabled, and LP1+ watermaks as disabled since
2967 * we can't really reverse compute them in case
2968 * multiple pipes are active.
2969 */
2970 active->wm[0].enable = true;
2971 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
2972 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
2973 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
2974 active->linetime = hw->wm_linetime[pipe];
2975 } else {
2976 int level, max_level = ilk_wm_max_level(dev);
2977
2978 /*
2979 * For inactive pipes, all watermark levels
2980 * should be marked as enabled but zeroed,
2981 * which is what we'd compute them to.
2982 */
2983 for (level = 0; level <= max_level; level++)
2984 active->wm[level].enable = true;
2985 }
2986 }
2987
2988 void ilk_wm_get_hw_state(struct drm_device *dev)
2989 {
2990 struct drm_i915_private *dev_priv = dev->dev_private;
2991 struct ilk_wm_values *hw = &dev_priv->wm.hw;
2992 struct drm_crtc *crtc;
2993
2994 for_each_crtc(dev, crtc)
2995 ilk_pipe_wm_get_hw_state(crtc);
2996
2997 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
2998 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
2999 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
3000
3001 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
3002 if (INTEL_INFO(dev)->gen >= 7) {
3003 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
3004 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
3005 }
3006
3007 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3008 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
3009 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
3010 else if (IS_IVYBRIDGE(dev))
3011 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
3012 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
3013
3014 hw->enable_fbc_wm =
3015 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
3016 }
3017
3018 /**
3019 * intel_update_watermarks - update FIFO watermark values based on current modes
3020 *
3021 * Calculate watermark values for the various WM regs based on current mode
3022 * and plane configuration.
3023 *
3024 * There are several cases to deal with here:
3025 * - normal (i.e. non-self-refresh)
3026 * - self-refresh (SR) mode
3027 * - lines are large relative to FIFO size (buffer can hold up to 2)
3028 * - lines are small relative to FIFO size (buffer can hold more than 2
3029 * lines), so need to account for TLB latency
3030 *
3031 * The normal calculation is:
3032 * watermark = dotclock * bytes per pixel * latency
3033 * where latency is platform & configuration dependent (we assume pessimal
3034 * values here).
3035 *
3036 * The SR calculation is:
3037 * watermark = (trunc(latency/line time)+1) * surface width *
3038 * bytes per pixel
3039 * where
3040 * line time = htotal / dotclock
3041 * surface width = hdisplay for normal plane and 64 for cursor
3042 * and latency is assumed to be high, as above.
3043 *
3044 * The final value programmed to the register should always be rounded up,
3045 * and include an extra 2 entries to account for clock crossings.
3046 *
3047 * We don't use the sprite, so we can ignore that. And on Crestline we have
3048 * to set the non-SR watermarks to 8.
3049 */
3050 void intel_update_watermarks(struct drm_crtc *crtc)
3051 {
3052 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
3053
3054 if (dev_priv->display.update_wm)
3055 dev_priv->display.update_wm(crtc);
3056 }
3057
3058 void intel_update_sprite_watermarks(struct drm_plane *plane,
3059 struct drm_crtc *crtc,
3060 uint32_t sprite_width,
3061 uint32_t sprite_height,
3062 int pixel_size,
3063 bool enabled, bool scaled)
3064 {
3065 struct drm_i915_private *dev_priv = plane->dev->dev_private;
3066
3067 if (dev_priv->display.update_sprite_wm)
3068 dev_priv->display.update_sprite_wm(plane, crtc,
3069 sprite_width, sprite_height,
3070 pixel_size, enabled, scaled);
3071 }
3072
3073 static struct drm_i915_gem_object *
3074 intel_alloc_context_page(struct drm_device *dev)
3075 {
3076 struct drm_i915_gem_object *ctx;
3077 int ret;
3078
3079 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3080
3081 ctx = i915_gem_alloc_object(dev, 4096);
3082 if (!ctx) {
3083 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
3084 return NULL;
3085 }
3086
3087 ret = i915_gem_obj_ggtt_pin(ctx, 4096, 0);
3088 if (ret) {
3089 DRM_ERROR("failed to pin power context: %d\n", ret);
3090 goto err_unref;
3091 }
3092
3093 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
3094 if (ret) {
3095 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
3096 goto err_unpin;
3097 }
3098
3099 return ctx;
3100
3101 err_unpin:
3102 i915_gem_object_ggtt_unpin(ctx);
3103 err_unref:
3104 drm_gem_object_unreference(&ctx->base);
3105 return NULL;
3106 }
3107
3108 /**
3109 * Lock protecting IPS related data structures
3110 */
3111 DEFINE_SPINLOCK(mchdev_lock);
3112
3113 /* Global for IPS driver to get at the current i915 device. Protected by
3114 * mchdev_lock. */
3115 static struct drm_i915_private *i915_mch_dev;
3116
3117 bool ironlake_set_drps(struct drm_device *dev, u8 val)
3118 {
3119 struct drm_i915_private *dev_priv = dev->dev_private;
3120 u16 rgvswctl;
3121
3122 assert_spin_locked(&mchdev_lock);
3123
3124 rgvswctl = I915_READ16(MEMSWCTL);
3125 if (rgvswctl & MEMCTL_CMD_STS) {
3126 DRM_DEBUG("gpu busy, RCS change rejected\n");
3127 return false; /* still busy with another command */
3128 }
3129
3130 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
3131 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
3132 I915_WRITE16(MEMSWCTL, rgvswctl);
3133 POSTING_READ16(MEMSWCTL);
3134
3135 rgvswctl |= MEMCTL_CMD_STS;
3136 I915_WRITE16(MEMSWCTL, rgvswctl);
3137
3138 return true;
3139 }
3140
3141 static void ironlake_enable_drps(struct drm_device *dev)
3142 {
3143 struct drm_i915_private *dev_priv = dev->dev_private;
3144 u32 rgvmodectl = I915_READ(MEMMODECTL);
3145 u8 fmax, fmin, fstart, vstart;
3146
3147 spin_lock_irq(&mchdev_lock);
3148
3149 /* Enable temp reporting */
3150 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
3151 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
3152
3153 /* 100ms RC evaluation intervals */
3154 I915_WRITE(RCUPEI, 100000);
3155 I915_WRITE(RCDNEI, 100000);
3156
3157 /* Set max/min thresholds to 90ms and 80ms respectively */
3158 I915_WRITE(RCBMAXAVG, 90000);
3159 I915_WRITE(RCBMINAVG, 80000);
3160
3161 I915_WRITE(MEMIHYST, 1);
3162
3163 /* Set up min, max, and cur for interrupt handling */
3164 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
3165 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
3166 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
3167 MEMMODE_FSTART_SHIFT;
3168
3169 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
3170 PXVFREQ_PX_SHIFT;
3171
3172 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
3173 dev_priv->ips.fstart = fstart;
3174
3175 dev_priv->ips.max_delay = fstart;
3176 dev_priv->ips.min_delay = fmin;
3177 dev_priv->ips.cur_delay = fstart;
3178
3179 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
3180 fmax, fmin, fstart);
3181
3182 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
3183
3184 /*
3185 * Interrupts will be enabled in ironlake_irq_postinstall
3186 */
3187
3188 I915_WRITE(VIDSTART, vstart);
3189 POSTING_READ(VIDSTART);
3190
3191 rgvmodectl |= MEMMODE_SWMODE_EN;
3192 I915_WRITE(MEMMODECTL, rgvmodectl);
3193
3194 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
3195 DRM_ERROR("stuck trying to change perf mode\n");
3196 mdelay(1);
3197
3198 ironlake_set_drps(dev, fstart);
3199
3200 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
3201 I915_READ(0x112e0);
3202 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
3203 dev_priv->ips.last_count2 = I915_READ(0x112f4);
3204 dev_priv->ips.last_time2 = ktime_get_raw_ns();
3205
3206 spin_unlock_irq(&mchdev_lock);
3207 }
3208
3209 static void ironlake_disable_drps(struct drm_device *dev)
3210 {
3211 struct drm_i915_private *dev_priv = dev->dev_private;
3212 u16 rgvswctl;
3213
3214 spin_lock_irq(&mchdev_lock);
3215
3216 rgvswctl = I915_READ16(MEMSWCTL);
3217
3218 /* Ack interrupts, disable EFC interrupt */
3219 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
3220 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
3221 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
3222 I915_WRITE(DEIIR, DE_PCU_EVENT);
3223 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
3224
3225 /* Go back to the starting frequency */
3226 ironlake_set_drps(dev, dev_priv->ips.fstart);
3227 mdelay(1);
3228 rgvswctl |= MEMCTL_CMD_STS;
3229 I915_WRITE(MEMSWCTL, rgvswctl);
3230 mdelay(1);
3231
3232 spin_unlock_irq(&mchdev_lock);
3233 }
3234
3235 /* There's a funny hw issue where the hw returns all 0 when reading from
3236 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3237 * ourselves, instead of doing a rmw cycle (which might result in us clearing
3238 * all limits and the gpu stuck at whatever frequency it is at atm).
3239 */
3240 static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)
3241 {
3242 u32 limits;
3243
3244 /* Only set the down limit when we've reached the lowest level to avoid
3245 * getting more interrupts, otherwise leave this clear. This prevents a
3246 * race in the hw when coming out of rc6: There's a tiny window where
3247 * the hw runs at the minimal clock before selecting the desired
3248 * frequency, if the down threshold expires in that window we will not
3249 * receive a down interrupt. */
3250 limits = dev_priv->rps.max_freq_softlimit << 24;
3251 if (val <= dev_priv->rps.min_freq_softlimit)
3252 limits |= dev_priv->rps.min_freq_softlimit << 16;
3253
3254 return limits;
3255 }
3256
3257 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
3258 {
3259 int new_power;
3260
3261 if (dev_priv->rps.is_bdw_sw_turbo)
3262 return;
3263
3264 new_power = dev_priv->rps.power;
3265 switch (dev_priv->rps.power) {
3266 case LOW_POWER:
3267 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
3268 new_power = BETWEEN;
3269 break;
3270
3271 case BETWEEN:
3272 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
3273 new_power = LOW_POWER;
3274 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
3275 new_power = HIGH_POWER;
3276 break;
3277
3278 case HIGH_POWER:
3279 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
3280 new_power = BETWEEN;
3281 break;
3282 }
3283 /* Max/min bins are special */
3284 if (val == dev_priv->rps.min_freq_softlimit)
3285 new_power = LOW_POWER;
3286 if (val == dev_priv->rps.max_freq_softlimit)
3287 new_power = HIGH_POWER;
3288 if (new_power == dev_priv->rps.power)
3289 return;
3290
3291 /* Note the units here are not exactly 1us, but 1280ns. */
3292 switch (new_power) {
3293 case LOW_POWER:
3294 /* Upclock if more than 95% busy over 16ms */
3295 I915_WRITE(GEN6_RP_UP_EI, 12500);
3296 I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800);
3297
3298 /* Downclock if less than 85% busy over 32ms */
3299 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3300 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250);
3301
3302 I915_WRITE(GEN6_RP_CONTROL,
3303 GEN6_RP_MEDIA_TURBO |
3304 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3305 GEN6_RP_MEDIA_IS_GFX |
3306 GEN6_RP_ENABLE |
3307 GEN6_RP_UP_BUSY_AVG |
3308 GEN6_RP_DOWN_IDLE_AVG);
3309 break;
3310
3311 case BETWEEN:
3312 /* Upclock if more than 90% busy over 13ms */
3313 I915_WRITE(GEN6_RP_UP_EI, 10250);
3314 I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225);
3315
3316 /* Downclock if less than 75% busy over 32ms */
3317 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3318 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750);
3319
3320 I915_WRITE(GEN6_RP_CONTROL,
3321 GEN6_RP_MEDIA_TURBO |
3322 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3323 GEN6_RP_MEDIA_IS_GFX |
3324 GEN6_RP_ENABLE |
3325 GEN6_RP_UP_BUSY_AVG |
3326 GEN6_RP_DOWN_IDLE_AVG);
3327 break;
3328
3329 case HIGH_POWER:
3330 /* Upclock if more than 85% busy over 10ms */
3331 I915_WRITE(GEN6_RP_UP_EI, 8000);
3332 I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800);
3333
3334 /* Downclock if less than 60% busy over 32ms */
3335 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3336 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000);
3337
3338 I915_WRITE(GEN6_RP_CONTROL,
3339 GEN6_RP_MEDIA_TURBO |
3340 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3341 GEN6_RP_MEDIA_IS_GFX |
3342 GEN6_RP_ENABLE |
3343 GEN6_RP_UP_BUSY_AVG |
3344 GEN6_RP_DOWN_IDLE_AVG);
3345 break;
3346 }
3347
3348 dev_priv->rps.power = new_power;
3349 dev_priv->rps.last_adj = 0;
3350 }
3351
3352 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
3353 {
3354 u32 mask = 0;
3355
3356 if (val > dev_priv->rps.min_freq_softlimit)
3357 mask |= GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
3358 if (val < dev_priv->rps.max_freq_softlimit)
3359 mask |= GEN6_PM_RP_UP_THRESHOLD;
3360
3361 mask |= dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED);
3362 mask &= dev_priv->pm_rps_events;
3363
3364 /* IVB and SNB hard hangs on looping batchbuffer
3365 * if GEN6_PM_UP_EI_EXPIRED is masked.
3366 */
3367 if (INTEL_INFO(dev_priv->dev)->gen <= 7 && !IS_HASWELL(dev_priv->dev))
3368 mask |= GEN6_PM_RP_UP_EI_EXPIRED;
3369
3370 if (IS_GEN8(dev_priv->dev))
3371 mask |= GEN8_PMINTR_REDIRECT_TO_NON_DISP;
3372
3373 return ~mask;
3374 }
3375
3376 /* gen6_set_rps is called to update the frequency request, but should also be
3377 * called when the range (min_delay and max_delay) is modified so that we can
3378 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
3379 void gen6_set_rps(struct drm_device *dev, u8 val)
3380 {
3381 struct drm_i915_private *dev_priv = dev->dev_private;
3382
3383 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3384 WARN_ON(val > dev_priv->rps.max_freq_softlimit);
3385 WARN_ON(val < dev_priv->rps.min_freq_softlimit);
3386
3387 /* min/max delay may still have been modified so be sure to
3388 * write the limits value.
3389 */
3390 if (val != dev_priv->rps.cur_freq) {
3391 gen6_set_rps_thresholds(dev_priv, val);
3392
3393 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3394 I915_WRITE(GEN6_RPNSWREQ,
3395 HSW_FREQUENCY(val));
3396 else
3397 I915_WRITE(GEN6_RPNSWREQ,
3398 GEN6_FREQUENCY(val) |
3399 GEN6_OFFSET(0) |
3400 GEN6_AGGRESSIVE_TURBO);
3401 }
3402
3403 /* Make sure we continue to get interrupts
3404 * until we hit the minimum or maximum frequencies.
3405 */
3406 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, gen6_rps_limits(dev_priv, val));
3407 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
3408
3409 POSTING_READ(GEN6_RPNSWREQ);
3410
3411 dev_priv->rps.cur_freq = val;
3412 trace_intel_gpu_freq_change(val * 50);
3413 }
3414
3415 /* vlv_set_rps_idle: Set the frequency to Rpn if Gfx clocks are down
3416 *
3417 * * If Gfx is Idle, then
3418 * 1. Mask Turbo interrupts
3419 * 2. Bring up Gfx clock
3420 * 3. Change the freq to Rpn and wait till P-Unit updates freq
3421 * 4. Clear the Force GFX CLK ON bit so that Gfx can down
3422 * 5. Unmask Turbo interrupts
3423 */
3424 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
3425 {
3426 struct drm_device *dev = dev_priv->dev;
3427
3428 /* Latest VLV doesn't need to force the gfx clock */
3429 if (dev->pdev->revision >= 0xd) {
3430 valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3431 return;
3432 }
3433
3434 /*
3435 * When we are idle. Drop to min voltage state.
3436 */
3437
3438 if (dev_priv->rps.cur_freq <= dev_priv->rps.min_freq_softlimit)
3439 return;
3440
3441 /* Mask turbo interrupt so that they will not come in between */
3442 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3443
3444 vlv_force_gfx_clock(dev_priv, true);
3445
3446 dev_priv->rps.cur_freq = dev_priv->rps.min_freq_softlimit;
3447
3448 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ,
3449 dev_priv->rps.min_freq_softlimit);
3450
3451 if (wait_for(((vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS))
3452 & GENFREQSTATUS) == 0, 5))
3453 DRM_ERROR("timed out waiting for Punit\n");
3454
3455 vlv_force_gfx_clock(dev_priv, false);
3456
3457 I915_WRITE(GEN6_PMINTRMSK,
3458 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
3459 }
3460
3461 void gen6_rps_idle(struct drm_i915_private *dev_priv)
3462 {
3463 struct drm_device *dev = dev_priv->dev;
3464
3465 mutex_lock(&dev_priv->rps.hw_lock);
3466 if (dev_priv->rps.enabled) {
3467 if (IS_CHERRYVIEW(dev))
3468 valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3469 else if (IS_VALLEYVIEW(dev))
3470 vlv_set_rps_idle(dev_priv);
3471 else if (!dev_priv->rps.is_bdw_sw_turbo
3472 || atomic_read(&dev_priv->rps.sw_turbo.flip_received)){
3473 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3474 }
3475
3476 dev_priv->rps.last_adj = 0;
3477 }
3478 mutex_unlock(&dev_priv->rps.hw_lock);
3479 }
3480
3481 void gen6_rps_boost(struct drm_i915_private *dev_priv)
3482 {
3483 struct drm_device *dev = dev_priv->dev;
3484
3485 mutex_lock(&dev_priv->rps.hw_lock);
3486 if (dev_priv->rps.enabled) {
3487 if (IS_VALLEYVIEW(dev))
3488 valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
3489 else if (!dev_priv->rps.is_bdw_sw_turbo
3490 || atomic_read(&dev_priv->rps.sw_turbo.flip_received)){
3491 gen6_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
3492 }
3493
3494 dev_priv->rps.last_adj = 0;
3495 }
3496 mutex_unlock(&dev_priv->rps.hw_lock);
3497 }
3498
3499 void valleyview_set_rps(struct drm_device *dev, u8 val)
3500 {
3501 struct drm_i915_private *dev_priv = dev->dev_private;
3502
3503 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3504 WARN_ON(val > dev_priv->rps.max_freq_softlimit);
3505 WARN_ON(val < dev_priv->rps.min_freq_softlimit);
3506
3507 DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
3508 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
3509 dev_priv->rps.cur_freq,
3510 vlv_gpu_freq(dev_priv, val), val);
3511
3512 if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1),
3513 "Odd GPU freq value\n"))
3514 val &= ~1;
3515
3516 if (val != dev_priv->rps.cur_freq)
3517 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
3518
3519 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
3520
3521 dev_priv->rps.cur_freq = val;
3522 trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val));
3523 }
3524
3525 static void gen8_disable_rps_interrupts(struct drm_device *dev)
3526 {
3527 struct drm_i915_private *dev_priv = dev->dev_private;
3528 if (IS_BROADWELL(dev) && dev_priv->rps.is_bdw_sw_turbo){
3529 if (atomic_read(&dev_priv->rps.sw_turbo.flip_received))
3530 del_timer(&dev_priv->rps.sw_turbo.flip_timer);
3531 dev_priv-> rps.is_bdw_sw_turbo = false;
3532 } else {
3533 I915_WRITE(GEN6_PMINTRMSK, ~GEN8_PMINTR_REDIRECT_TO_NON_DISP);
3534 I915_WRITE(GEN8_GT_IER(2), I915_READ(GEN8_GT_IER(2)) &
3535 ~dev_priv->pm_rps_events);
3536 /* Complete PM interrupt masking here doesn't race with the rps work
3537 * item again unmasking PM interrupts because that is using a different
3538 * register (GEN8_GT_IMR(2)) to mask PM interrupts. The only risk is in
3539 * leaving stale bits in GEN8_GT_IIR(2) and GEN8_GT_IMR(2) which
3540 * gen8_enable_rps will clean up. */
3541
3542 spin_lock_irq(&dev_priv->irq_lock);
3543 dev_priv->rps.pm_iir = 0;
3544 spin_unlock_irq(&dev_priv->irq_lock);
3545
3546 I915_WRITE(GEN8_GT_IIR(2), dev_priv->pm_rps_events);
3547 }
3548 }
3549
3550 static void gen6_disable_rps_interrupts(struct drm_device *dev)
3551 {
3552 struct drm_i915_private *dev_priv = dev->dev_private;
3553
3554 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3555 I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) &
3556 ~dev_priv->pm_rps_events);
3557 /* Complete PM interrupt masking here doesn't race with the rps work
3558 * item again unmasking PM interrupts because that is using a different
3559 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3560 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3561
3562 spin_lock_irq(&dev_priv->irq_lock);
3563 dev_priv->rps.pm_iir = 0;
3564 spin_unlock_irq(&dev_priv->irq_lock);
3565
3566 I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events);
3567 }
3568
3569 static void gen6_disable_rps(struct drm_device *dev)
3570 {
3571 struct drm_i915_private *dev_priv = dev->dev_private;
3572
3573 I915_WRITE(GEN6_RC_CONTROL, 0);
3574 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
3575
3576 if (IS_BROADWELL(dev))
3577 gen8_disable_rps_interrupts(dev);
3578 else
3579 gen6_disable_rps_interrupts(dev);
3580 }
3581
3582 static void cherryview_disable_rps(struct drm_device *dev)
3583 {
3584 struct drm_i915_private *dev_priv = dev->dev_private;
3585
3586 I915_WRITE(GEN6_RC_CONTROL, 0);
3587
3588 gen8_disable_rps_interrupts(dev);
3589 }
3590
3591 static void valleyview_disable_rps(struct drm_device *dev)
3592 {
3593 struct drm_i915_private *dev_priv = dev->dev_private;
3594
3595 /* we're doing forcewake before Disabling RC6,
3596 * This what the BIOS expects when going into suspend */
3597 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3598
3599 I915_WRITE(GEN6_RC_CONTROL, 0);
3600
3601 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3602
3603 gen6_disable_rps_interrupts(dev);
3604 }
3605
3606 static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
3607 {
3608 if (IS_VALLEYVIEW(dev)) {
3609 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
3610 mode = GEN6_RC_CTL_RC6_ENABLE;
3611 else
3612 mode = 0;
3613 }
3614 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
3615 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3616 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3617 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
3618 }
3619
3620 static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
3621 {
3622 /* No RC6 before Ironlake */
3623 if (INTEL_INFO(dev)->gen < 5)
3624 return 0;
3625
3626 /* RC6 is only on Ironlake mobile not on desktop */
3627 if (INTEL_INFO(dev)->gen == 5 && !IS_IRONLAKE_M(dev))
3628 return 0;
3629
3630 /* Respect the kernel parameter if it is set */
3631 if (enable_rc6 >= 0) {
3632 int mask;
3633
3634 if (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
3635 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
3636 INTEL_RC6pp_ENABLE;
3637 else
3638 mask = INTEL_RC6_ENABLE;
3639
3640 if ((enable_rc6 & mask) != enable_rc6)
3641 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
3642 enable_rc6 & mask, enable_rc6, mask);
3643
3644 return enable_rc6 & mask;
3645 }
3646
3647 /* Disable RC6 on Ironlake */
3648 if (INTEL_INFO(dev)->gen == 5)
3649 return 0;
3650
3651 if (IS_IVYBRIDGE(dev))
3652 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
3653
3654 return INTEL_RC6_ENABLE;
3655 }
3656
3657 int intel_enable_rc6(const struct drm_device *dev)
3658 {
3659 return i915.enable_rc6;
3660 }
3661
3662 static void gen8_enable_rps_interrupts(struct drm_device *dev)
3663 {
3664 struct drm_i915_private *dev_priv = dev->dev_private;
3665
3666 spin_lock_irq(&dev_priv->irq_lock);
3667 WARN_ON(dev_priv->rps.pm_iir);
3668 gen8_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
3669 I915_WRITE(GEN8_GT_IIR(2), dev_priv->pm_rps_events);
3670 spin_unlock_irq(&dev_priv->irq_lock);
3671 }
3672
3673 static void gen6_enable_rps_interrupts(struct drm_device *dev)
3674 {
3675 struct drm_i915_private *dev_priv = dev->dev_private;
3676
3677 spin_lock_irq(&dev_priv->irq_lock);
3678 WARN_ON(dev_priv->rps.pm_iir);
3679 gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
3680 I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events);
3681 spin_unlock_irq(&dev_priv->irq_lock);
3682 }
3683
3684 static void parse_rp_state_cap(struct drm_i915_private *dev_priv, u32 rp_state_cap)
3685 {
3686 /* All of these values are in units of 50MHz */
3687 dev_priv->rps.cur_freq = 0;
3688 /* static values from HW: RP0 < RPe < RP1 < RPn (min_freq) */
3689 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
3690 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
3691 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
3692 /* XXX: only BYT has a special efficient freq */
3693 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
3694 /* hw_max = RP0 until we check for overclocking */
3695 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
3696
3697 /* Preserve min/max settings in case of re-init */
3698 if (dev_priv->rps.max_freq_softlimit == 0)
3699 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
3700
3701 if (dev_priv->rps.min_freq_softlimit == 0)
3702 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
3703 }
3704
3705 static void bdw_sw_calculate_freq(struct drm_device *dev,
3706 struct intel_rps_bdw_cal *c, u32 *cur_time, u32 *c0)
3707 {
3708 struct drm_i915_private *dev_priv = dev->dev_private;
3709 u64 busy = 0;
3710 u32 busyness_pct = 0;
3711 u32 elapsed_time = 0;
3712 u16 new_freq = 0;
3713
3714 if (!c || !cur_time || !c0)
3715 return;
3716
3717 if (0 == c->last_c0)
3718 goto out;
3719
3720 /* Check Evaluation interval */
3721 elapsed_time = *cur_time - c->last_ts;
3722 if (elapsed_time < c->eval_interval)
3723 return;
3724
3725 mutex_lock(&dev_priv->rps.hw_lock);
3726
3727 /*
3728 * c0 unit in 32*1.28 usec, elapsed_time unit in 1 usec.
3729 * Whole busyness_pct calculation should be
3730 * busy = ((u64)(*c0 - c->last_c0) << 5 << 7) / 100;
3731 * busyness_pct = (u32)(busy * 100 / elapsed_time);
3732 * The final formula is to simplify CPU calculation
3733 */
3734 busy = (u64)(*c0 - c->last_c0) << 12;
3735 do_div(busy, elapsed_time);
3736 busyness_pct = (u32)busy;
3737
3738 if (c->is_up && busyness_pct >= c->it_threshold_pct)
3739 new_freq = (u16)dev_priv->rps.cur_freq + 3;
3740 if (!c->is_up && busyness_pct <= c->it_threshold_pct)
3741 new_freq = (u16)dev_priv->rps.cur_freq - 1;
3742
3743 /* Adjust to new frequency busyness and compare with threshold */
3744 if (0 != new_freq) {
3745 if (new_freq > dev_priv->rps.max_freq_softlimit)
3746 new_freq = dev_priv->rps.max_freq_softlimit;
3747 else if (new_freq < dev_priv->rps.min_freq_softlimit)
3748 new_freq = dev_priv->rps.min_freq_softlimit;
3749
3750 gen6_set_rps(dev, new_freq);
3751 }
3752
3753 mutex_unlock(&dev_priv->rps.hw_lock);
3754
3755 out:
3756 c->last_c0 = *c0;
3757 c->last_ts = *cur_time;
3758 }
3759
3760 static void gen8_set_frequency_RP0(struct work_struct *work)
3761 {
3762 struct intel_rps_bdw_turbo *p_bdw_turbo =
3763 container_of(work, struct intel_rps_bdw_turbo, work_max_freq);
3764 struct intel_gen6_power_mgmt *p_power_mgmt =
3765 container_of(p_bdw_turbo, struct intel_gen6_power_mgmt, sw_turbo);
3766 struct drm_i915_private *dev_priv =
3767 container_of(p_power_mgmt, struct drm_i915_private, rps);
3768
3769 mutex_lock(&dev_priv->rps.hw_lock);
3770 gen6_set_rps(dev_priv->dev, dev_priv->rps.rp0_freq);
3771 mutex_unlock(&dev_priv->rps.hw_lock);
3772 }
3773
3774 static void flip_active_timeout_handler(unsigned long var)
3775 {
3776 struct drm_i915_private *dev_priv = (struct drm_i915_private *) var;
3777
3778 del_timer(&dev_priv->rps.sw_turbo.flip_timer);
3779 atomic_set(&dev_priv->rps.sw_turbo.flip_received, false);
3780
3781 queue_work(dev_priv->wq, &dev_priv->rps.sw_turbo.work_max_freq);
3782 }
3783
3784 void bdw_software_turbo(struct drm_device *dev)
3785 {
3786 struct drm_i915_private *dev_priv = dev->dev_private;
3787
3788 u32 current_time = I915_READ(TIMESTAMP_CTR); /* unit in usec */
3789 u32 current_c0 = I915_READ(MCHBAR_PCU_C0); /* unit in 32*1.28 usec */
3790
3791 bdw_sw_calculate_freq(dev, &dev_priv->rps.sw_turbo.up,
3792 &current_time, &current_c0);
3793 bdw_sw_calculate_freq(dev, &dev_priv->rps.sw_turbo.down,
3794 &current_time, &current_c0);
3795 }
3796
3797 static void gen8_enable_rps(struct drm_device *dev)
3798 {
3799 struct drm_i915_private *dev_priv = dev->dev_private;
3800 struct intel_engine_cs *ring;
3801 uint32_t rc6_mask = 0, rp_state_cap;
3802 uint32_t threshold_up_pct, threshold_down_pct;
3803 uint32_t ei_up, ei_down; /* up and down evaluation interval */
3804 u32 rp_ctl_flag;
3805 int unused;
3806
3807 /* Use software Turbo for BDW */
3808 dev_priv->rps.is_bdw_sw_turbo = IS_BROADWELL(dev);
3809
3810 /* 1a: Software RC state - RC0 */
3811 I915_WRITE(GEN6_RC_STATE, 0);
3812
3813 /* 1c & 1d: Get forcewake during program sequence. Although the driver
3814 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
3815 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3816
3817 /* 2a: Disable RC states. */
3818 I915_WRITE(GEN6_RC_CONTROL, 0);
3819
3820 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3821 parse_rp_state_cap(dev_priv, rp_state_cap);
3822
3823 /* 2b: Program RC6 thresholds.*/
3824 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
3825 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
3826 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
3827 for_each_ring(ring, dev_priv, unused)
3828 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3829 I915_WRITE(GEN6_RC_SLEEP, 0);
3830 if (IS_BROADWELL(dev))
3831 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
3832 else
3833 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
3834
3835 /* 3: Enable RC6 */
3836 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
3837 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
3838 intel_print_rc6_info(dev, rc6_mask);
3839 if (IS_BROADWELL(dev))
3840 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
3841 GEN7_RC_CTL_TO_MODE |
3842 rc6_mask);
3843 else
3844 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
3845 GEN6_RC_CTL_EI_MODE(1) |
3846 rc6_mask);
3847
3848 /* 4 Program defaults and thresholds for RPS*/
3849 I915_WRITE(GEN6_RPNSWREQ,
3850 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
3851 I915_WRITE(GEN6_RC_VIDEO_FREQ,
3852 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
3853 ei_up = 84480; /* 84.48ms */
3854 ei_down = 448000;
3855 threshold_up_pct = 90; /* x percent busy */
3856 threshold_down_pct = 70;
3857
3858 if (dev_priv->rps.is_bdw_sw_turbo) {
3859 dev_priv->rps.sw_turbo.up.it_threshold_pct = threshold_up_pct;
3860 dev_priv->rps.sw_turbo.up.eval_interval = ei_up;
3861 dev_priv->rps.sw_turbo.up.is_up = true;
3862 dev_priv->rps.sw_turbo.up.last_ts = 0;
3863 dev_priv->rps.sw_turbo.up.last_c0 = 0;
3864
3865 dev_priv->rps.sw_turbo.down.it_threshold_pct = threshold_down_pct;
3866 dev_priv->rps.sw_turbo.down.eval_interval = ei_down;
3867 dev_priv->rps.sw_turbo.down.is_up = false;
3868 dev_priv->rps.sw_turbo.down.last_ts = 0;
3869 dev_priv->rps.sw_turbo.down.last_c0 = 0;
3870
3871 /* Start the timer to track if flip comes*/
3872 dev_priv->rps.sw_turbo.timeout = 200*1000; /* in us */
3873
3874 init_timer(&dev_priv->rps.sw_turbo.flip_timer);
3875 dev_priv->rps.sw_turbo.flip_timer.function = flip_active_timeout_handler;
3876 dev_priv->rps.sw_turbo.flip_timer.data = (unsigned long) dev_priv;
3877 dev_priv->rps.sw_turbo.flip_timer.expires =
3878 usecs_to_jiffies(dev_priv->rps.sw_turbo.timeout) + jiffies;
3879 add_timer(&dev_priv->rps.sw_turbo.flip_timer);
3880 INIT_WORK(&dev_priv->rps.sw_turbo.work_max_freq, gen8_set_frequency_RP0);
3881
3882 atomic_set(&dev_priv->rps.sw_turbo.flip_received, true);
3883 } else {
3884 /* NB: Docs say 1s, and 1000000 - which aren't equivalent
3885 * 1 second timeout*/
3886 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, FREQ_1_28_US(1000000));
3887
3888 /* Docs recommend 900MHz, and 300 MHz respectively */
3889 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
3890 dev_priv->rps.max_freq_softlimit << 24 |
3891 dev_priv->rps.min_freq_softlimit << 16);
3892
3893 I915_WRITE(GEN6_RP_UP_THRESHOLD,
3894 FREQ_1_28_US(ei_up * threshold_up_pct / 100));
3895 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
3896 FREQ_1_28_US(ei_down * threshold_down_pct / 100));
3897 I915_WRITE(GEN6_RP_UP_EI,
3898 FREQ_1_28_US(ei_up));
3899 I915_WRITE(GEN6_RP_DOWN_EI,
3900 FREQ_1_28_US(ei_down));
3901
3902 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3903 }
3904
3905 /* 5: Enable RPS */
3906 rp_ctl_flag = GEN6_RP_MEDIA_TURBO |
3907 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3908 GEN6_RP_MEDIA_IS_GFX |
3909 GEN6_RP_UP_BUSY_AVG |
3910 GEN6_RP_DOWN_IDLE_AVG;
3911 if (!dev_priv->rps.is_bdw_sw_turbo)
3912 rp_ctl_flag |= GEN6_RP_ENABLE;
3913
3914 I915_WRITE(GEN6_RP_CONTROL, rp_ctl_flag);
3915
3916 /* 6: Ring frequency + overclocking
3917 * (our driver does this later */
3918 gen6_set_rps(dev, (I915_READ(GEN6_GT_PERF_STATUS) & 0xff00) >> 8);
3919 if (!dev_priv->rps.is_bdw_sw_turbo)
3920 gen8_enable_rps_interrupts(dev);
3921
3922 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3923 }
3924
3925 static void gen6_enable_rps(struct drm_device *dev)
3926 {
3927 struct drm_i915_private *dev_priv = dev->dev_private;
3928 struct intel_engine_cs *ring;
3929 u32 rp_state_cap;
3930 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
3931 u32 gtfifodbg;
3932 int rc6_mode;
3933 int i, ret;
3934
3935 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3936
3937 /* Here begins a magic sequence of register writes to enable
3938 * auto-downclocking.
3939 *
3940 * Perhaps there might be some value in exposing these to
3941 * userspace...
3942 */
3943 I915_WRITE(GEN6_RC_STATE, 0);
3944
3945 /* Clear the DBG now so we don't confuse earlier errors */
3946 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3947 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3948 I915_WRITE(GTFIFODBG, gtfifodbg);
3949 }
3950
3951 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3952
3953 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3954
3955 parse_rp_state_cap(dev_priv, rp_state_cap);
3956
3957 /* disable the counters and set deterministic thresholds */
3958 I915_WRITE(GEN6_RC_CONTROL, 0);
3959
3960 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
3961 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
3962 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
3963 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3964 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3965
3966 for_each_ring(ring, dev_priv, i)
3967 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3968
3969 I915_WRITE(GEN6_RC_SLEEP, 0);
3970 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
3971 if (IS_IVYBRIDGE(dev))
3972 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
3973 else
3974 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
3975 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
3976 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
3977
3978 /* Check if we are enabling RC6 */
3979 rc6_mode = intel_enable_rc6(dev_priv->dev);
3980 if (rc6_mode & INTEL_RC6_ENABLE)
3981 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
3982
3983 /* We don't use those on Haswell */
3984 if (!IS_HASWELL(dev)) {
3985 if (rc6_mode & INTEL_RC6p_ENABLE)
3986 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
3987
3988 if (rc6_mode & INTEL_RC6pp_ENABLE)
3989 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
3990 }
3991
3992 intel_print_rc6_info(dev, rc6_mask);
3993
3994 I915_WRITE(GEN6_RC_CONTROL,
3995 rc6_mask |
3996 GEN6_RC_CTL_EI_MODE(1) |
3997 GEN6_RC_CTL_HW_ENABLE);
3998
3999 /* Power down if completely idle for over 50ms */
4000 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
4001 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4002
4003 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
4004 if (ret)
4005 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
4006
4007 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
4008 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
4009 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
4010 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
4011 (pcu_mbox & 0xff) * 50);
4012 dev_priv->rps.max_freq = pcu_mbox & 0xff;
4013 }
4014
4015 dev_priv->rps.power = HIGH_POWER; /* force a reset */
4016 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
4017
4018 gen6_enable_rps_interrupts(dev);
4019
4020 rc6vids = 0;
4021 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
4022 if (IS_GEN6(dev) && ret) {
4023 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
4024 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
4025 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
4026 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
4027 rc6vids &= 0xffff00;
4028 rc6vids |= GEN6_ENCODE_RC6_VID(450);
4029 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
4030 if (ret)
4031 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
4032 }
4033
4034 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
4035 }
4036
4037 static void __gen6_update_ring_freq(struct drm_device *dev)
4038 {
4039 struct drm_i915_private *dev_priv = dev->dev_private;
4040 int min_freq = 15;
4041 unsigned int gpu_freq;
4042 unsigned int max_ia_freq, min_ring_freq;
4043 int scaling_factor = 180;
4044 struct cpufreq_policy *policy;
4045
4046 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4047
4048 policy = cpufreq_cpu_get(0);
4049 if (policy) {
4050 max_ia_freq = policy->cpuinfo.max_freq;
4051 cpufreq_cpu_put(policy);
4052 } else {
4053 /*
4054 * Default to measured freq if none found, PCU will ensure we
4055 * don't go over
4056 */
4057 max_ia_freq = tsc_khz;
4058 }
4059
4060 /* Convert from kHz to MHz */
4061 max_ia_freq /= 1000;
4062
4063 min_ring_freq = I915_READ(DCLK) & 0xf;
4064 /* convert DDR frequency from units of 266.6MHz to bandwidth */
4065 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
4066
4067 /*
4068 * For each potential GPU frequency, load a ring frequency we'd like
4069 * to use for memory access. We do this by specifying the IA frequency
4070 * the PCU should use as a reference to determine the ring frequency.
4071 */
4072 for (gpu_freq = dev_priv->rps.max_freq_softlimit; gpu_freq >= dev_priv->rps.min_freq_softlimit;
4073 gpu_freq--) {
4074 int diff = dev_priv->rps.max_freq_softlimit - gpu_freq;
4075 unsigned int ia_freq = 0, ring_freq = 0;
4076
4077 if (INTEL_INFO(dev)->gen >= 8) {
4078 /* max(2 * GT, DDR). NB: GT is 50MHz units */
4079 ring_freq = max(min_ring_freq, gpu_freq);
4080 } else if (IS_HASWELL(dev)) {
4081 ring_freq = mult_frac(gpu_freq, 5, 4);
4082 ring_freq = max(min_ring_freq, ring_freq);
4083 /* leave ia_freq as the default, chosen by cpufreq */
4084 } else {
4085 /* On older processors, there is no separate ring
4086 * clock domain, so in order to boost the bandwidth
4087 * of the ring, we need to upclock the CPU (ia_freq).
4088 *
4089 * For GPU frequencies less than 750MHz,
4090 * just use the lowest ring freq.
4091 */
4092 if (gpu_freq < min_freq)
4093 ia_freq = 800;
4094 else
4095 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
4096 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
4097 }
4098
4099 sandybridge_pcode_write(dev_priv,
4100 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
4101 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
4102 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
4103 gpu_freq);
4104 }
4105 }
4106
4107 void gen6_update_ring_freq(struct drm_device *dev)
4108 {
4109 struct drm_i915_private *dev_priv = dev->dev_private;
4110
4111 if (INTEL_INFO(dev)->gen < 6 || IS_VALLEYVIEW(dev))
4112 return;
4113
4114 mutex_lock(&dev_priv->rps.hw_lock);
4115 __gen6_update_ring_freq(dev);
4116 mutex_unlock(&dev_priv->rps.hw_lock);
4117 }
4118
4119 static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
4120 {
4121 u32 val, rp0;
4122
4123 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
4124 rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & PUNIT_GPU_STATUS_MAX_FREQ_MASK;
4125
4126 return rp0;
4127 }
4128
4129 static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
4130 {
4131 u32 val, rpe;
4132
4133 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
4134 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
4135
4136 return rpe;
4137 }
4138
4139 static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
4140 {
4141 u32 val, rp1;
4142
4143 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4144 rp1 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & PUNIT_GPU_STATUS_MAX_FREQ_MASK;
4145
4146 return rp1;
4147 }
4148
4149 static int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
4150 {
4151 u32 val, rpn;
4152
4153 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
4154 rpn = (val >> PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT) & PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK;
4155 return rpn;
4156 }
4157
4158 static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
4159 {
4160 u32 val, rp1;
4161
4162 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
4163
4164 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
4165
4166 return rp1;
4167 }
4168
4169 static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
4170 {
4171 u32 val, rp0;
4172
4173 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
4174
4175 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
4176 /* Clamp to max */
4177 rp0 = min_t(u32, rp0, 0xea);
4178
4179 return rp0;
4180 }
4181
4182 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
4183 {
4184 u32 val, rpe;
4185
4186 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
4187 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
4188 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
4189 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
4190
4191 return rpe;
4192 }
4193
4194 static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
4195 {
4196 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
4197 }
4198
4199 /* Check that the pctx buffer wasn't move under us. */
4200 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
4201 {
4202 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
4203
4204 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
4205 dev_priv->vlv_pctx->stolen->start);
4206 }
4207
4208
4209 /* Check that the pcbr address is not empty. */
4210 static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
4211 {
4212 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
4213
4214 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
4215 }
4216
4217 static void cherryview_setup_pctx(struct drm_device *dev)
4218 {
4219 struct drm_i915_private *dev_priv = dev->dev_private;
4220 unsigned long pctx_paddr, paddr;
4221 struct i915_gtt *gtt = &dev_priv->gtt;
4222 u32 pcbr;
4223 int pctx_size = 32*1024;
4224
4225 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4226
4227 pcbr = I915_READ(VLV_PCBR);
4228 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
4229 paddr = (dev_priv->mm.stolen_base +
4230 (gtt->stolen_size - pctx_size));
4231
4232 pctx_paddr = (paddr & (~4095));
4233 I915_WRITE(VLV_PCBR, pctx_paddr);
4234 }
4235 }
4236
4237 static void valleyview_setup_pctx(struct drm_device *dev)
4238 {
4239 struct drm_i915_private *dev_priv = dev->dev_private;
4240 struct drm_i915_gem_object *pctx;
4241 unsigned long pctx_paddr;
4242 u32 pcbr;
4243 int pctx_size = 24*1024;
4244
4245 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4246
4247 pcbr = I915_READ(VLV_PCBR);
4248 if (pcbr) {
4249 /* BIOS set it up already, grab the pre-alloc'd space */
4250 int pcbr_offset;
4251
4252 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
4253 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
4254 pcbr_offset,
4255 I915_GTT_OFFSET_NONE,
4256 pctx_size);
4257 goto out;
4258 }
4259
4260 /*
4261 * From the Gunit register HAS:
4262 * The Gfx driver is expected to program this register and ensure
4263 * proper allocation within Gfx stolen memory. For example, this
4264 * register should be programmed such than the PCBR range does not
4265 * overlap with other ranges, such as the frame buffer, protected
4266 * memory, or any other relevant ranges.
4267 */
4268 pctx = i915_gem_object_create_stolen(dev, pctx_size);
4269 if (!pctx) {
4270 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
4271 return;
4272 }
4273
4274 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
4275 I915_WRITE(VLV_PCBR, pctx_paddr);
4276
4277 out:
4278 dev_priv->vlv_pctx = pctx;
4279 }
4280
4281 static void valleyview_cleanup_pctx(struct drm_device *dev)
4282 {
4283 struct drm_i915_private *dev_priv = dev->dev_private;
4284
4285 if (WARN_ON(!dev_priv->vlv_pctx))
4286 return;
4287
4288 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
4289 dev_priv->vlv_pctx = NULL;
4290 }
4291
4292 static void valleyview_init_gt_powersave(struct drm_device *dev)
4293 {
4294 struct drm_i915_private *dev_priv = dev->dev_private;
4295 u32 val;
4296
4297 valleyview_setup_pctx(dev);
4298
4299 mutex_lock(&dev_priv->rps.hw_lock);
4300
4301 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4302 switch ((val >> 6) & 3) {
4303 case 0:
4304 case 1:
4305 dev_priv->mem_freq = 800;
4306 break;
4307 case 2:
4308 dev_priv->mem_freq = 1066;
4309 break;
4310 case 3:
4311 dev_priv->mem_freq = 1333;
4312 break;
4313 }
4314 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
4315
4316 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
4317 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
4318 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
4319 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4320 dev_priv->rps.max_freq);
4321
4322 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
4323 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
4324 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4325 dev_priv->rps.efficient_freq);
4326
4327 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
4328 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
4329 vlv_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
4330 dev_priv->rps.rp1_freq);
4331
4332 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
4333 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
4334 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4335 dev_priv->rps.min_freq);
4336
4337 /* Preserve min/max settings in case of re-init */
4338 if (dev_priv->rps.max_freq_softlimit == 0)
4339 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4340
4341 if (dev_priv->rps.min_freq_softlimit == 0)
4342 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
4343
4344 mutex_unlock(&dev_priv->rps.hw_lock);
4345 }
4346
4347 static void cherryview_init_gt_powersave(struct drm_device *dev)
4348 {
4349 struct drm_i915_private *dev_priv = dev->dev_private;
4350 u32 val;
4351
4352 cherryview_setup_pctx(dev);
4353
4354 mutex_lock(&dev_priv->rps.hw_lock);
4355
4356 val = vlv_punit_read(dev_priv, CCK_FUSE_REG);
4357 switch ((val >> 2) & 0x7) {
4358 case 0:
4359 case 1:
4360 dev_priv->rps.cz_freq = 200;
4361 dev_priv->mem_freq = 1600;
4362 break;
4363 case 2:
4364 dev_priv->rps.cz_freq = 267;
4365 dev_priv->mem_freq = 1600;
4366 break;
4367 case 3:
4368 dev_priv->rps.cz_freq = 333;
4369 dev_priv->mem_freq = 2000;
4370 break;
4371 case 4:
4372 dev_priv->rps.cz_freq = 320;
4373 dev_priv->mem_freq = 1600;
4374 break;
4375 case 5:
4376 dev_priv->rps.cz_freq = 400;
4377 dev_priv->mem_freq = 1600;
4378 break;
4379 }
4380 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
4381
4382 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
4383 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
4384 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
4385 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4386 dev_priv->rps.max_freq);
4387
4388 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
4389 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
4390 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4391 dev_priv->rps.efficient_freq);
4392
4393 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
4394 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
4395 vlv_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
4396 dev_priv->rps.rp1_freq);
4397
4398 dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv);
4399 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
4400 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4401 dev_priv->rps.min_freq);
4402
4403 WARN_ONCE((dev_priv->rps.max_freq |
4404 dev_priv->rps.efficient_freq |
4405 dev_priv->rps.rp1_freq |
4406 dev_priv->rps.min_freq) & 1,
4407 "Odd GPU freq values\n");
4408
4409 /* Preserve min/max settings in case of re-init */
4410 if (dev_priv->rps.max_freq_softlimit == 0)
4411 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4412
4413 if (dev_priv->rps.min_freq_softlimit == 0)
4414 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
4415
4416 mutex_unlock(&dev_priv->rps.hw_lock);
4417 }
4418
4419 static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
4420 {
4421 valleyview_cleanup_pctx(dev);
4422 }
4423
4424 static void cherryview_enable_rps(struct drm_device *dev)
4425 {
4426 struct drm_i915_private *dev_priv = dev->dev_private;
4427 struct intel_engine_cs *ring;
4428 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
4429 int i;
4430
4431 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4432
4433 gtfifodbg = I915_READ(GTFIFODBG);
4434 if (gtfifodbg) {
4435 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4436 gtfifodbg);
4437 I915_WRITE(GTFIFODBG, gtfifodbg);
4438 }
4439
4440 cherryview_check_pctx(dev_priv);
4441
4442 /* 1a & 1b: Get forcewake during program sequence. Although the driver
4443 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4444 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
4445
4446 /* 2a: Program RC6 thresholds.*/
4447 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4448 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4449 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4450
4451 for_each_ring(ring, dev_priv, i)
4452 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4453 I915_WRITE(GEN6_RC_SLEEP, 0);
4454
4455 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
4456
4457 /* allows RC6 residency counter to work */
4458 I915_WRITE(VLV_COUNTER_CONTROL,
4459 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
4460 VLV_MEDIA_RC6_COUNT_EN |
4461 VLV_RENDER_RC6_COUNT_EN));
4462
4463 /* For now we assume BIOS is allocating and populating the PCBR */
4464 pcbr = I915_READ(VLV_PCBR);
4465
4466 DRM_DEBUG_DRIVER("PCBR offset : 0x%x\n", pcbr);
4467
4468 /* 3: Enable RC6 */
4469 if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
4470 (pcbr >> VLV_PCBR_ADDR_SHIFT))
4471 rc6_mode = GEN6_RC_CTL_EI_MODE(1);
4472
4473 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
4474
4475 /* 4 Program defaults and thresholds for RPS*/
4476 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
4477 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
4478 I915_WRITE(GEN6_RP_UP_EI, 66000);
4479 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
4480
4481 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4482
4483 /* WaDisablePwrmtrEvent:chv (pre-production hw) */
4484 I915_WRITE(0xA80C, I915_READ(0xA80C) & 0x00ffffff);
4485 I915_WRITE(0xA810, I915_READ(0xA810) & 0xffffff00);
4486
4487 /* 5: Enable RPS */
4488 I915_WRITE(GEN6_RP_CONTROL,
4489 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4490 GEN6_RP_MEDIA_IS_GFX | /* WaSetMaskForGfxBusyness:chv (pre-production hw ?) */
4491 GEN6_RP_ENABLE |
4492 GEN6_RP_UP_BUSY_AVG |
4493 GEN6_RP_DOWN_IDLE_AVG);
4494
4495 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4496
4497 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
4498 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
4499
4500 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
4501 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
4502 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
4503 dev_priv->rps.cur_freq);
4504
4505 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
4506 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4507 dev_priv->rps.efficient_freq);
4508
4509 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
4510
4511 gen8_enable_rps_interrupts(dev);
4512
4513 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
4514 }
4515
4516 static void valleyview_enable_rps(struct drm_device *dev)
4517 {
4518 struct drm_i915_private *dev_priv = dev->dev_private;
4519 struct intel_engine_cs *ring;
4520 u32 gtfifodbg, val, rc6_mode = 0;
4521 int i;
4522
4523 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4524
4525 valleyview_check_pctx(dev_priv);
4526
4527 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
4528 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4529 gtfifodbg);
4530 I915_WRITE(GTFIFODBG, gtfifodbg);
4531 }
4532
4533 /* If VLV, Forcewake all wells, else re-direct to regular path */
4534 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
4535
4536 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
4537 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
4538 I915_WRITE(GEN6_RP_UP_EI, 66000);
4539 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
4540
4541 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4542 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 0xf4240);
4543
4544 I915_WRITE(GEN6_RP_CONTROL,
4545 GEN6_RP_MEDIA_TURBO |
4546 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4547 GEN6_RP_MEDIA_IS_GFX |
4548 GEN6_RP_ENABLE |
4549 GEN6_RP_UP_BUSY_AVG |
4550 GEN6_RP_DOWN_IDLE_CONT);
4551
4552 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
4553 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4554 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4555
4556 for_each_ring(ring, dev_priv, i)
4557 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4558
4559 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
4560
4561 /* allows RC6 residency counter to work */
4562 I915_WRITE(VLV_COUNTER_CONTROL,
4563 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
4564 VLV_RENDER_RC0_COUNT_EN |
4565 VLV_MEDIA_RC6_COUNT_EN |
4566 VLV_RENDER_RC6_COUNT_EN));
4567
4568 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4569 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
4570
4571 intel_print_rc6_info(dev, rc6_mode);
4572
4573 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
4574
4575 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4576
4577 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
4578 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
4579
4580 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
4581 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
4582 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
4583 dev_priv->rps.cur_freq);
4584
4585 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
4586 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4587 dev_priv->rps.efficient_freq);
4588
4589 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
4590
4591 gen6_enable_rps_interrupts(dev);
4592
4593 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
4594 }
4595
4596 void ironlake_teardown_rc6(struct drm_device *dev)
4597 {
4598 struct drm_i915_private *dev_priv = dev->dev_private;
4599
4600 if (dev_priv->ips.renderctx) {
4601 i915_gem_object_ggtt_unpin(dev_priv->ips.renderctx);
4602 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
4603 dev_priv->ips.renderctx = NULL;
4604 }
4605
4606 if (dev_priv->ips.pwrctx) {
4607 i915_gem_object_ggtt_unpin(dev_priv->ips.pwrctx);
4608 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
4609 dev_priv->ips.pwrctx = NULL;
4610 }
4611 }
4612
4613 static void ironlake_disable_rc6(struct drm_device *dev)
4614 {
4615 struct drm_i915_private *dev_priv = dev->dev_private;
4616
4617 if (I915_READ(PWRCTXA)) {
4618 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
4619 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
4620 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
4621 50);
4622
4623 I915_WRITE(PWRCTXA, 0);
4624 POSTING_READ(PWRCTXA);
4625
4626 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
4627 POSTING_READ(RSTDBYCTL);
4628 }
4629 }
4630
4631 static int ironlake_setup_rc6(struct drm_device *dev)
4632 {
4633 struct drm_i915_private *dev_priv = dev->dev_private;
4634
4635 if (dev_priv->ips.renderctx == NULL)
4636 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
4637 if (!dev_priv->ips.renderctx)
4638 return -ENOMEM;
4639
4640 if (dev_priv->ips.pwrctx == NULL)
4641 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
4642 if (!dev_priv->ips.pwrctx) {
4643 ironlake_teardown_rc6(dev);
4644 return -ENOMEM;
4645 }
4646
4647 return 0;
4648 }
4649
4650 static void ironlake_enable_rc6(struct drm_device *dev)
4651 {
4652 struct drm_i915_private *dev_priv = dev->dev_private;
4653 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
4654 bool was_interruptible;
4655 int ret;
4656
4657 /* rc6 disabled by default due to repeated reports of hanging during
4658 * boot and resume.
4659 */
4660 if (!intel_enable_rc6(dev))
4661 return;
4662
4663 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4664
4665 ret = ironlake_setup_rc6(dev);
4666 if (ret)
4667 return;
4668
4669 was_interruptible = dev_priv->mm.interruptible;
4670 dev_priv->mm.interruptible = false;
4671
4672 /*
4673 * GPU can automatically power down the render unit if given a page
4674 * to save state.
4675 */
4676 ret = intel_ring_begin(ring, 6);
4677 if (ret) {
4678 ironlake_teardown_rc6(dev);
4679 dev_priv->mm.interruptible = was_interruptible;
4680 return;
4681 }
4682
4683 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
4684 intel_ring_emit(ring, MI_SET_CONTEXT);
4685 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) |
4686 MI_MM_SPACE_GTT |
4687 MI_SAVE_EXT_STATE_EN |
4688 MI_RESTORE_EXT_STATE_EN |
4689 MI_RESTORE_INHIBIT);
4690 intel_ring_emit(ring, MI_SUSPEND_FLUSH);
4691 intel_ring_emit(ring, MI_NOOP);
4692 intel_ring_emit(ring, MI_FLUSH);
4693 intel_ring_advance(ring);
4694
4695 /*
4696 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
4697 * does an implicit flush, combined with MI_FLUSH above, it should be
4698 * safe to assume that renderctx is valid
4699 */
4700 ret = intel_ring_idle(ring);
4701 dev_priv->mm.interruptible = was_interruptible;
4702 if (ret) {
4703 DRM_ERROR("failed to enable ironlake power savings\n");
4704 ironlake_teardown_rc6(dev);
4705 return;
4706 }
4707
4708 I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN);
4709 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
4710
4711 intel_print_rc6_info(dev, GEN6_RC_CTL_RC6_ENABLE);
4712 }
4713
4714 static unsigned long intel_pxfreq(u32 vidfreq)
4715 {
4716 unsigned long freq;
4717 int div = (vidfreq & 0x3f0000) >> 16;
4718 int post = (vidfreq & 0x3000) >> 12;
4719 int pre = (vidfreq & 0x7);
4720
4721 if (!pre)
4722 return 0;
4723
4724 freq = ((div * 133333) / ((1<<post) * pre));
4725
4726 return freq;
4727 }
4728
4729 static const struct cparams {
4730 u16 i;
4731 u16 t;
4732 u16 m;
4733 u16 c;
4734 } cparams[] = {
4735 { 1, 1333, 301, 28664 },
4736 { 1, 1066, 294, 24460 },
4737 { 1, 800, 294, 25192 },
4738 { 0, 1333, 276, 27605 },
4739 { 0, 1066, 276, 27605 },
4740 { 0, 800, 231, 23784 },
4741 };
4742
4743 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
4744 {
4745 u64 total_count, diff, ret;
4746 u32 count1, count2, count3, m = 0, c = 0;
4747 unsigned long now = jiffies_to_msecs(jiffies), diff1;
4748 int i;
4749
4750 assert_spin_locked(&mchdev_lock);
4751
4752 diff1 = now - dev_priv->ips.last_time1;
4753
4754 /* Prevent division-by-zero if we are asking too fast.
4755 * Also, we don't get interesting results if we are polling
4756 * faster than once in 10ms, so just return the saved value
4757 * in such cases.
4758 */
4759 if (diff1 <= 10)
4760 return dev_priv->ips.chipset_power;
4761
4762 count1 = I915_READ(DMIEC);
4763 count2 = I915_READ(DDREC);
4764 count3 = I915_READ(CSIEC);
4765
4766 total_count = count1 + count2 + count3;
4767
4768 /* FIXME: handle per-counter overflow */
4769 if (total_count < dev_priv->ips.last_count1) {
4770 diff = ~0UL - dev_priv->ips.last_count1;
4771 diff += total_count;
4772 } else {
4773 diff = total_count - dev_priv->ips.last_count1;
4774 }
4775
4776 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
4777 if (cparams[i].i == dev_priv->ips.c_m &&
4778 cparams[i].t == dev_priv->ips.r_t) {
4779 m = cparams[i].m;
4780 c = cparams[i].c;
4781 break;
4782 }
4783 }
4784
4785 diff = div_u64(diff, diff1);
4786 ret = ((m * diff) + c);
4787 ret = div_u64(ret, 10);
4788
4789 dev_priv->ips.last_count1 = total_count;
4790 dev_priv->ips.last_time1 = now;
4791
4792 dev_priv->ips.chipset_power = ret;
4793
4794 return ret;
4795 }
4796
4797 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
4798 {
4799 struct drm_device *dev = dev_priv->dev;
4800 unsigned long val;
4801
4802 if (INTEL_INFO(dev)->gen != 5)
4803 return 0;
4804
4805 spin_lock_irq(&mchdev_lock);
4806
4807 val = __i915_chipset_val(dev_priv);
4808
4809 spin_unlock_irq(&mchdev_lock);
4810
4811 return val;
4812 }
4813
4814 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
4815 {
4816 unsigned long m, x, b;
4817 u32 tsfs;
4818
4819 tsfs = I915_READ(TSFS);
4820
4821 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
4822 x = I915_READ8(TR1);
4823
4824 b = tsfs & TSFS_INTR_MASK;
4825
4826 return ((m * x) / 127) - b;
4827 }
4828
4829 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
4830 {
4831 struct drm_device *dev = dev_priv->dev;
4832 static const struct v_table {
4833 u16 vd; /* in .1 mil */
4834 u16 vm; /* in .1 mil */
4835 } v_table[] = {
4836 { 0, 0, },
4837 { 375, 0, },
4838 { 500, 0, },
4839 { 625, 0, },
4840 { 750, 0, },
4841 { 875, 0, },
4842 { 1000, 0, },
4843 { 1125, 0, },
4844 { 4125, 3000, },
4845 { 4125, 3000, },
4846 { 4125, 3000, },
4847 { 4125, 3000, },
4848 { 4125, 3000, },
4849 { 4125, 3000, },
4850 { 4125, 3000, },
4851 { 4125, 3000, },
4852 { 4125, 3000, },
4853 { 4125, 3000, },
4854 { 4125, 3000, },
4855 { 4125, 3000, },
4856 { 4125, 3000, },
4857 { 4125, 3000, },
4858 { 4125, 3000, },
4859 { 4125, 3000, },
4860 { 4125, 3000, },
4861 { 4125, 3000, },
4862 { 4125, 3000, },
4863 { 4125, 3000, },
4864 { 4125, 3000, },
4865 { 4125, 3000, },
4866 { 4125, 3000, },
4867 { 4125, 3000, },
4868 { 4250, 3125, },
4869 { 4375, 3250, },
4870 { 4500, 3375, },
4871 { 4625, 3500, },
4872 { 4750, 3625, },
4873 { 4875, 3750, },
4874 { 5000, 3875, },
4875 { 5125, 4000, },
4876 { 5250, 4125, },
4877 { 5375, 4250, },
4878 { 5500, 4375, },
4879 { 5625, 4500, },
4880 { 5750, 4625, },
4881 { 5875, 4750, },
4882 { 6000, 4875, },
4883 { 6125, 5000, },
4884 { 6250, 5125, },
4885 { 6375, 5250, },
4886 { 6500, 5375, },
4887 { 6625, 5500, },
4888 { 6750, 5625, },
4889 { 6875, 5750, },
4890 { 7000, 5875, },
4891 { 7125, 6000, },
4892 { 7250, 6125, },
4893 { 7375, 6250, },
4894 { 7500, 6375, },
4895 { 7625, 6500, },
4896 { 7750, 6625, },
4897 { 7875, 6750, },
4898 { 8000, 6875, },
4899 { 8125, 7000, },
4900 { 8250, 7125, },
4901 { 8375, 7250, },
4902 { 8500, 7375, },
4903 { 8625, 7500, },
4904 { 8750, 7625, },
4905 { 8875, 7750, },
4906 { 9000, 7875, },
4907 { 9125, 8000, },
4908 { 9250, 8125, },
4909 { 9375, 8250, },
4910 { 9500, 8375, },
4911 { 9625, 8500, },
4912 { 9750, 8625, },
4913 { 9875, 8750, },
4914 { 10000, 8875, },
4915 { 10125, 9000, },
4916 { 10250, 9125, },
4917 { 10375, 9250, },
4918 { 10500, 9375, },
4919 { 10625, 9500, },
4920 { 10750, 9625, },
4921 { 10875, 9750, },
4922 { 11000, 9875, },
4923 { 11125, 10000, },
4924 { 11250, 10125, },
4925 { 11375, 10250, },
4926 { 11500, 10375, },
4927 { 11625, 10500, },
4928 { 11750, 10625, },
4929 { 11875, 10750, },
4930 { 12000, 10875, },
4931 { 12125, 11000, },
4932 { 12250, 11125, },
4933 { 12375, 11250, },
4934 { 12500, 11375, },
4935 { 12625, 11500, },
4936 { 12750, 11625, },
4937 { 12875, 11750, },
4938 { 13000, 11875, },
4939 { 13125, 12000, },
4940 { 13250, 12125, },
4941 { 13375, 12250, },
4942 { 13500, 12375, },
4943 { 13625, 12500, },
4944 { 13750, 12625, },
4945 { 13875, 12750, },
4946 { 14000, 12875, },
4947 { 14125, 13000, },
4948 { 14250, 13125, },
4949 { 14375, 13250, },
4950 { 14500, 13375, },
4951 { 14625, 13500, },
4952 { 14750, 13625, },
4953 { 14875, 13750, },
4954 { 15000, 13875, },
4955 { 15125, 14000, },
4956 { 15250, 14125, },
4957 { 15375, 14250, },
4958 { 15500, 14375, },
4959 { 15625, 14500, },
4960 { 15750, 14625, },
4961 { 15875, 14750, },
4962 { 16000, 14875, },
4963 { 16125, 15000, },
4964 };
4965 if (INTEL_INFO(dev)->is_mobile)
4966 return v_table[pxvid].vm;
4967 else
4968 return v_table[pxvid].vd;
4969 }
4970
4971 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
4972 {
4973 u64 now, diff, diffms;
4974 u32 count;
4975
4976 assert_spin_locked(&mchdev_lock);
4977
4978 now = ktime_get_raw_ns();
4979 diffms = now - dev_priv->ips.last_time2;
4980 do_div(diffms, NSEC_PER_MSEC);
4981
4982 /* Don't divide by 0 */
4983 if (!diffms)
4984 return;
4985
4986 count = I915_READ(GFXEC);
4987
4988 if (count < dev_priv->ips.last_count2) {
4989 diff = ~0UL - dev_priv->ips.last_count2;
4990 diff += count;
4991 } else {
4992 diff = count - dev_priv->ips.last_count2;
4993 }
4994
4995 dev_priv->ips.last_count2 = count;
4996 dev_priv->ips.last_time2 = now;
4997
4998 /* More magic constants... */
4999 diff = diff * 1181;
5000 diff = div_u64(diff, diffms * 10);
5001 dev_priv->ips.gfx_power = diff;
5002 }
5003
5004 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
5005 {
5006 struct drm_device *dev = dev_priv->dev;
5007
5008 if (INTEL_INFO(dev)->gen != 5)
5009 return;
5010
5011 spin_lock_irq(&mchdev_lock);
5012
5013 __i915_update_gfx_val(dev_priv);
5014
5015 spin_unlock_irq(&mchdev_lock);
5016 }
5017
5018 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
5019 {
5020 unsigned long t, corr, state1, corr2, state2;
5021 u32 pxvid, ext_v;
5022
5023 assert_spin_locked(&mchdev_lock);
5024
5025 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_freq * 4));
5026 pxvid = (pxvid >> 24) & 0x7f;
5027 ext_v = pvid_to_extvid(dev_priv, pxvid);
5028
5029 state1 = ext_v;
5030
5031 t = i915_mch_val(dev_priv);
5032
5033 /* Revel in the empirically derived constants */
5034
5035 /* Correction factor in 1/100000 units */
5036 if (t > 80)
5037 corr = ((t * 2349) + 135940);
5038 else if (t >= 50)
5039 corr = ((t * 964) + 29317);
5040 else /* < 50 */
5041 corr = ((t * 301) + 1004);
5042
5043 corr = corr * ((150142 * state1) / 10000 - 78642);
5044 corr /= 100000;
5045 corr2 = (corr * dev_priv->ips.corr);
5046
5047 state2 = (corr2 * state1) / 10000;
5048 state2 /= 100; /* convert to mW */
5049
5050 __i915_update_gfx_val(dev_priv);
5051
5052 return dev_priv->ips.gfx_power + state2;
5053 }
5054
5055 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
5056 {
5057 struct drm_device *dev = dev_priv->dev;
5058 unsigned long val;
5059
5060 if (INTEL_INFO(dev)->gen != 5)
5061 return 0;
5062
5063 spin_lock_irq(&mchdev_lock);
5064
5065 val = __i915_gfx_val(dev_priv);
5066
5067 spin_unlock_irq(&mchdev_lock);
5068
5069 return val;
5070 }
5071
5072 /**
5073 * i915_read_mch_val - return value for IPS use
5074 *
5075 * Calculate and return a value for the IPS driver to use when deciding whether
5076 * we have thermal and power headroom to increase CPU or GPU power budget.
5077 */
5078 unsigned long i915_read_mch_val(void)
5079 {
5080 struct drm_i915_private *dev_priv;
5081 unsigned long chipset_val, graphics_val, ret = 0;
5082
5083 spin_lock_irq(&mchdev_lock);
5084 if (!i915_mch_dev)
5085 goto out_unlock;
5086 dev_priv = i915_mch_dev;
5087
5088 chipset_val = __i915_chipset_val(dev_priv);
5089 graphics_val = __i915_gfx_val(dev_priv);
5090
5091 ret = chipset_val + graphics_val;
5092
5093 out_unlock:
5094 spin_unlock_irq(&mchdev_lock);
5095
5096 return ret;
5097 }
5098 EXPORT_SYMBOL_GPL(i915_read_mch_val);
5099
5100 /**
5101 * i915_gpu_raise - raise GPU frequency limit
5102 *
5103 * Raise the limit; IPS indicates we have thermal headroom.
5104 */
5105 bool i915_gpu_raise(void)
5106 {
5107 struct drm_i915_private *dev_priv;
5108 bool ret = true;
5109
5110 spin_lock_irq(&mchdev_lock);
5111 if (!i915_mch_dev) {
5112 ret = false;
5113 goto out_unlock;
5114 }
5115 dev_priv = i915_mch_dev;
5116
5117 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
5118 dev_priv->ips.max_delay--;
5119
5120 out_unlock:
5121 spin_unlock_irq(&mchdev_lock);
5122
5123 return ret;
5124 }
5125 EXPORT_SYMBOL_GPL(i915_gpu_raise);
5126
5127 /**
5128 * i915_gpu_lower - lower GPU frequency limit
5129 *
5130 * IPS indicates we're close to a thermal limit, so throttle back the GPU
5131 * frequency maximum.
5132 */
5133 bool i915_gpu_lower(void)
5134 {
5135 struct drm_i915_private *dev_priv;
5136 bool ret = true;
5137
5138 spin_lock_irq(&mchdev_lock);
5139 if (!i915_mch_dev) {
5140 ret = false;
5141 goto out_unlock;
5142 }
5143 dev_priv = i915_mch_dev;
5144
5145 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
5146 dev_priv->ips.max_delay++;
5147
5148 out_unlock:
5149 spin_unlock_irq(&mchdev_lock);
5150
5151 return ret;
5152 }
5153 EXPORT_SYMBOL_GPL(i915_gpu_lower);
5154
5155 /**
5156 * i915_gpu_busy - indicate GPU business to IPS
5157 *
5158 * Tell the IPS driver whether or not the GPU is busy.
5159 */
5160 bool i915_gpu_busy(void)
5161 {
5162 struct drm_i915_private *dev_priv;
5163 struct intel_engine_cs *ring;
5164 bool ret = false;
5165 int i;
5166
5167 spin_lock_irq(&mchdev_lock);
5168 if (!i915_mch_dev)
5169 goto out_unlock;
5170 dev_priv = i915_mch_dev;
5171
5172 for_each_ring(ring, dev_priv, i)
5173 ret |= !list_empty(&ring->request_list);
5174
5175 out_unlock:
5176 spin_unlock_irq(&mchdev_lock);
5177
5178 return ret;
5179 }
5180 EXPORT_SYMBOL_GPL(i915_gpu_busy);
5181
5182 /**
5183 * i915_gpu_turbo_disable - disable graphics turbo
5184 *
5185 * Disable graphics turbo by resetting the max frequency and setting the
5186 * current frequency to the default.
5187 */
5188 bool i915_gpu_turbo_disable(void)
5189 {
5190 struct drm_i915_private *dev_priv;
5191 bool ret = true;
5192
5193 spin_lock_irq(&mchdev_lock);
5194 if (!i915_mch_dev) {
5195 ret = false;
5196 goto out_unlock;
5197 }
5198 dev_priv = i915_mch_dev;
5199
5200 dev_priv->ips.max_delay = dev_priv->ips.fstart;
5201
5202 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
5203 ret = false;
5204
5205 out_unlock:
5206 spin_unlock_irq(&mchdev_lock);
5207
5208 return ret;
5209 }
5210 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
5211
5212 /**
5213 * Tells the intel_ips driver that the i915 driver is now loaded, if
5214 * IPS got loaded first.
5215 *
5216 * This awkward dance is so that neither module has to depend on the
5217 * other in order for IPS to do the appropriate communication of
5218 * GPU turbo limits to i915.
5219 */
5220 static void
5221 ips_ping_for_i915_load(void)
5222 {
5223 void (*link)(void);
5224
5225 link = symbol_get(ips_link_to_i915_driver);
5226 if (link) {
5227 link();
5228 symbol_put(ips_link_to_i915_driver);
5229 }
5230 }
5231
5232 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
5233 {
5234 /* We only register the i915 ips part with intel-ips once everything is
5235 * set up, to avoid intel-ips sneaking in and reading bogus values. */
5236 spin_lock_irq(&mchdev_lock);
5237 i915_mch_dev = dev_priv;
5238 spin_unlock_irq(&mchdev_lock);
5239
5240 ips_ping_for_i915_load();
5241 }
5242
5243 void intel_gpu_ips_teardown(void)
5244 {
5245 spin_lock_irq(&mchdev_lock);
5246 i915_mch_dev = NULL;
5247 spin_unlock_irq(&mchdev_lock);
5248 }
5249
5250 static void intel_init_emon(struct drm_device *dev)
5251 {
5252 struct drm_i915_private *dev_priv = dev->dev_private;
5253 u32 lcfuse;
5254 u8 pxw[16];
5255 int i;
5256
5257 /* Disable to program */
5258 I915_WRITE(ECR, 0);
5259 POSTING_READ(ECR);
5260
5261 /* Program energy weights for various events */
5262 I915_WRITE(SDEW, 0x15040d00);
5263 I915_WRITE(CSIEW0, 0x007f0000);
5264 I915_WRITE(CSIEW1, 0x1e220004);
5265 I915_WRITE(CSIEW2, 0x04000004);
5266
5267 for (i = 0; i < 5; i++)
5268 I915_WRITE(PEW + (i * 4), 0);
5269 for (i = 0; i < 3; i++)
5270 I915_WRITE(DEW + (i * 4), 0);
5271
5272 /* Program P-state weights to account for frequency power adjustment */
5273 for (i = 0; i < 16; i++) {
5274 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
5275 unsigned long freq = intel_pxfreq(pxvidfreq);
5276 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5277 PXVFREQ_PX_SHIFT;
5278 unsigned long val;
5279
5280 val = vid * vid;
5281 val *= (freq / 1000);
5282 val *= 255;
5283 val /= (127*127*900);
5284 if (val > 0xff)
5285 DRM_ERROR("bad pxval: %ld\n", val);
5286 pxw[i] = val;
5287 }
5288 /* Render standby states get 0 weight */
5289 pxw[14] = 0;
5290 pxw[15] = 0;
5291
5292 for (i = 0; i < 4; i++) {
5293 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5294 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
5295 I915_WRITE(PXW + (i * 4), val);
5296 }
5297
5298 /* Adjust magic regs to magic values (more experimental results) */
5299 I915_WRITE(OGW0, 0);
5300 I915_WRITE(OGW1, 0);
5301 I915_WRITE(EG0, 0x00007f00);
5302 I915_WRITE(EG1, 0x0000000e);
5303 I915_WRITE(EG2, 0x000e0000);
5304 I915_WRITE(EG3, 0x68000300);
5305 I915_WRITE(EG4, 0x42000000);
5306 I915_WRITE(EG5, 0x00140031);
5307 I915_WRITE(EG6, 0);
5308 I915_WRITE(EG7, 0);
5309
5310 for (i = 0; i < 8; i++)
5311 I915_WRITE(PXWL + (i * 4), 0);
5312
5313 /* Enable PMON + select events */
5314 I915_WRITE(ECR, 0x80000019);
5315
5316 lcfuse = I915_READ(LCFUSE02);
5317
5318 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
5319 }
5320
5321 void intel_init_gt_powersave(struct drm_device *dev)
5322 {
5323 i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
5324
5325 if (IS_CHERRYVIEW(dev))
5326 cherryview_init_gt_powersave(dev);
5327 else if (IS_VALLEYVIEW(dev))
5328 valleyview_init_gt_powersave(dev);
5329 }
5330
5331 void intel_cleanup_gt_powersave(struct drm_device *dev)
5332 {
5333 if (IS_CHERRYVIEW(dev))
5334 return;
5335 else if (IS_VALLEYVIEW(dev))
5336 valleyview_cleanup_gt_powersave(dev);
5337 }
5338
5339 /**
5340 * intel_suspend_gt_powersave - suspend PM work and helper threads
5341 * @dev: drm device
5342 *
5343 * We don't want to disable RC6 or other features here, we just want
5344 * to make sure any work we've queued has finished and won't bother
5345 * us while we're suspended.
5346 */
5347 void intel_suspend_gt_powersave(struct drm_device *dev)
5348 {
5349 struct drm_i915_private *dev_priv = dev->dev_private;
5350
5351 /* Interrupts should be disabled already to avoid re-arming. */
5352 WARN_ON(intel_irqs_enabled(dev_priv));
5353
5354 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
5355
5356 cancel_work_sync(&dev_priv->rps.work);
5357
5358 /* Force GPU to min freq during suspend */
5359 gen6_rps_idle(dev_priv);
5360 }
5361
5362 void intel_disable_gt_powersave(struct drm_device *dev)
5363 {
5364 struct drm_i915_private *dev_priv = dev->dev_private;
5365
5366 /* Interrupts should be disabled already to avoid re-arming. */
5367 WARN_ON(intel_irqs_enabled(dev_priv));
5368
5369 if (IS_IRONLAKE_M(dev)) {
5370 ironlake_disable_drps(dev);
5371 ironlake_disable_rc6(dev);
5372 } else if (INTEL_INFO(dev)->gen >= 6) {
5373 intel_suspend_gt_powersave(dev);
5374
5375 mutex_lock(&dev_priv->rps.hw_lock);
5376 if (IS_CHERRYVIEW(dev))
5377 cherryview_disable_rps(dev);
5378 else if (IS_VALLEYVIEW(dev))
5379 valleyview_disable_rps(dev);
5380 else
5381 gen6_disable_rps(dev);
5382 dev_priv->rps.enabled = false;
5383 mutex_unlock(&dev_priv->rps.hw_lock);
5384 }
5385 }
5386
5387 static void intel_gen6_powersave_work(struct work_struct *work)
5388 {
5389 struct drm_i915_private *dev_priv =
5390 container_of(work, struct drm_i915_private,
5391 rps.delayed_resume_work.work);
5392 struct drm_device *dev = dev_priv->dev;
5393
5394 dev_priv->rps.is_bdw_sw_turbo = false;
5395
5396 mutex_lock(&dev_priv->rps.hw_lock);
5397
5398 if (IS_CHERRYVIEW(dev)) {
5399 cherryview_enable_rps(dev);
5400 } else if (IS_VALLEYVIEW(dev)) {
5401 valleyview_enable_rps(dev);
5402 } else if (IS_BROADWELL(dev)) {
5403 gen8_enable_rps(dev);
5404 __gen6_update_ring_freq(dev);
5405 } else {
5406 gen6_enable_rps(dev);
5407 __gen6_update_ring_freq(dev);
5408 }
5409 dev_priv->rps.enabled = true;
5410 mutex_unlock(&dev_priv->rps.hw_lock);
5411
5412 intel_runtime_pm_put(dev_priv);
5413 }
5414
5415 void intel_enable_gt_powersave(struct drm_device *dev)
5416 {
5417 struct drm_i915_private *dev_priv = dev->dev_private;
5418
5419 if (IS_IRONLAKE_M(dev)) {
5420 mutex_lock(&dev->struct_mutex);
5421 ironlake_enable_drps(dev);
5422 ironlake_enable_rc6(dev);
5423 intel_init_emon(dev);
5424 mutex_unlock(&dev->struct_mutex);
5425 } else if (INTEL_INFO(dev)->gen >= 6) {
5426 /*
5427 * PCU communication is slow and this doesn't need to be
5428 * done at any specific time, so do this out of our fast path
5429 * to make resume and init faster.
5430 *
5431 * We depend on the HW RC6 power context save/restore
5432 * mechanism when entering D3 through runtime PM suspend. So
5433 * disable RPM until RPS/RC6 is properly setup. We can only
5434 * get here via the driver load/system resume/runtime resume
5435 * paths, so the _noresume version is enough (and in case of
5436 * runtime resume it's necessary).
5437 */
5438 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
5439 round_jiffies_up_relative(HZ)))
5440 intel_runtime_pm_get_noresume(dev_priv);
5441 }
5442 }
5443
5444 void intel_reset_gt_powersave(struct drm_device *dev)
5445 {
5446 struct drm_i915_private *dev_priv = dev->dev_private;
5447
5448 dev_priv->rps.enabled = false;
5449 intel_enable_gt_powersave(dev);
5450 }
5451
5452 static void ibx_init_clock_gating(struct drm_device *dev)
5453 {
5454 struct drm_i915_private *dev_priv = dev->dev_private;
5455
5456 /*
5457 * On Ibex Peak and Cougar Point, we need to disable clock
5458 * gating for the panel power sequencer or it will fail to
5459 * start up when no ports are active.
5460 */
5461 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
5462 }
5463
5464 static void g4x_disable_trickle_feed(struct drm_device *dev)
5465 {
5466 struct drm_i915_private *dev_priv = dev->dev_private;
5467 int pipe;
5468
5469 for_each_pipe(dev_priv, pipe) {
5470 I915_WRITE(DSPCNTR(pipe),
5471 I915_READ(DSPCNTR(pipe)) |
5472 DISPPLANE_TRICKLE_FEED_DISABLE);
5473 intel_flush_primary_plane(dev_priv, pipe);
5474 }
5475 }
5476
5477 static void ilk_init_lp_watermarks(struct drm_device *dev)
5478 {
5479 struct drm_i915_private *dev_priv = dev->dev_private;
5480
5481 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
5482 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
5483 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
5484
5485 /*
5486 * Don't touch WM1S_LP_EN here.
5487 * Doing so could cause underruns.
5488 */
5489 }
5490
5491 static void ironlake_init_clock_gating(struct drm_device *dev)
5492 {
5493 struct drm_i915_private *dev_priv = dev->dev_private;
5494 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
5495
5496 /*
5497 * Required for FBC
5498 * WaFbcDisableDpfcClockGating:ilk
5499 */
5500 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
5501 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
5502 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
5503
5504 I915_WRITE(PCH_3DCGDIS0,
5505 MARIUNIT_CLOCK_GATE_DISABLE |
5506 SVSMUNIT_CLOCK_GATE_DISABLE);
5507 I915_WRITE(PCH_3DCGDIS1,
5508 VFMUNIT_CLOCK_GATE_DISABLE);
5509
5510 /*
5511 * According to the spec the following bits should be set in
5512 * order to enable memory self-refresh
5513 * The bit 22/21 of 0x42004
5514 * The bit 5 of 0x42020
5515 * The bit 15 of 0x45000
5516 */
5517 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5518 (I915_READ(ILK_DISPLAY_CHICKEN2) |
5519 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
5520 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
5521 I915_WRITE(DISP_ARB_CTL,
5522 (I915_READ(DISP_ARB_CTL) |
5523 DISP_FBC_WM_DIS));
5524
5525 ilk_init_lp_watermarks(dev);
5526
5527 /*
5528 * Based on the document from hardware guys the following bits
5529 * should be set unconditionally in order to enable FBC.
5530 * The bit 22 of 0x42000
5531 * The bit 22 of 0x42004
5532 * The bit 7,8,9 of 0x42020.
5533 */
5534 if (IS_IRONLAKE_M(dev)) {
5535 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
5536 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5537 I915_READ(ILK_DISPLAY_CHICKEN1) |
5538 ILK_FBCQ_DIS);
5539 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5540 I915_READ(ILK_DISPLAY_CHICKEN2) |
5541 ILK_DPARB_GATE);
5542 }
5543
5544 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
5545
5546 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5547 I915_READ(ILK_DISPLAY_CHICKEN2) |
5548 ILK_ELPIN_409_SELECT);
5549 I915_WRITE(_3D_CHICKEN2,
5550 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
5551 _3D_CHICKEN2_WM_READ_PIPELINED);
5552
5553 /* WaDisableRenderCachePipelinedFlush:ilk */
5554 I915_WRITE(CACHE_MODE_0,
5555 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
5556
5557 /* WaDisable_RenderCache_OperationalFlush:ilk */
5558 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5559
5560 g4x_disable_trickle_feed(dev);
5561
5562 ibx_init_clock_gating(dev);
5563 }
5564
5565 static void cpt_init_clock_gating(struct drm_device *dev)
5566 {
5567 struct drm_i915_private *dev_priv = dev->dev_private;
5568 int pipe;
5569 uint32_t val;
5570
5571 /*
5572 * On Ibex Peak and Cougar Point, we need to disable clock
5573 * gating for the panel power sequencer or it will fail to
5574 * start up when no ports are active.
5575 */
5576 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
5577 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
5578 PCH_CPUNIT_CLOCK_GATE_DISABLE);
5579 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
5580 DPLS_EDP_PPS_FIX_DIS);
5581 /* The below fixes the weird display corruption, a few pixels shifted
5582 * downward, on (only) LVDS of some HP laptops with IVY.
5583 */
5584 for_each_pipe(dev_priv, pipe) {
5585 val = I915_READ(TRANS_CHICKEN2(pipe));
5586 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
5587 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
5588 if (dev_priv->vbt.fdi_rx_polarity_inverted)
5589 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
5590 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
5591 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
5592 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
5593 I915_WRITE(TRANS_CHICKEN2(pipe), val);
5594 }
5595 /* WADP0ClockGatingDisable */
5596 for_each_pipe(dev_priv, pipe) {
5597 I915_WRITE(TRANS_CHICKEN1(pipe),
5598 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
5599 }
5600 }
5601
5602 static void gen6_check_mch_setup(struct drm_device *dev)
5603 {
5604 struct drm_i915_private *dev_priv = dev->dev_private;
5605 uint32_t tmp;
5606
5607 tmp = I915_READ(MCH_SSKPD);
5608 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
5609 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
5610 tmp);
5611 }
5612
5613 static void gen6_init_clock_gating(struct drm_device *dev)
5614 {
5615 struct drm_i915_private *dev_priv = dev->dev_private;
5616 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
5617
5618 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
5619
5620 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5621 I915_READ(ILK_DISPLAY_CHICKEN2) |
5622 ILK_ELPIN_409_SELECT);
5623
5624 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
5625 I915_WRITE(_3D_CHICKEN,
5626 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
5627
5628 /* WaSetupGtModeTdRowDispatch:snb */
5629 if (IS_SNB_GT1(dev))
5630 I915_WRITE(GEN6_GT_MODE,
5631 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
5632
5633 /* WaDisable_RenderCache_OperationalFlush:snb */
5634 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5635
5636 /*
5637 * BSpec recoomends 8x4 when MSAA is used,
5638 * however in practice 16x4 seems fastest.
5639 *
5640 * Note that PS/WM thread counts depend on the WIZ hashing
5641 * disable bit, which we don't touch here, but it's good
5642 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5643 */
5644 I915_WRITE(GEN6_GT_MODE,
5645 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5646
5647 ilk_init_lp_watermarks(dev);
5648
5649 I915_WRITE(CACHE_MODE_0,
5650 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
5651
5652 I915_WRITE(GEN6_UCGCTL1,
5653 I915_READ(GEN6_UCGCTL1) |
5654 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
5655 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
5656
5657 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5658 * gating disable must be set. Failure to set it results in
5659 * flickering pixels due to Z write ordering failures after
5660 * some amount of runtime in the Mesa "fire" demo, and Unigine
5661 * Sanctuary and Tropics, and apparently anything else with
5662 * alpha test or pixel discard.
5663 *
5664 * According to the spec, bit 11 (RCCUNIT) must also be set,
5665 * but we didn't debug actual testcases to find it out.
5666 *
5667 * WaDisableRCCUnitClockGating:snb
5668 * WaDisableRCPBUnitClockGating:snb
5669 */
5670 I915_WRITE(GEN6_UCGCTL2,
5671 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
5672 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5673
5674 /* WaStripsFansDisableFastClipPerformanceFix:snb */
5675 I915_WRITE(_3D_CHICKEN3,
5676 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
5677
5678 /*
5679 * Bspec says:
5680 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
5681 * 3DSTATE_SF number of SF output attributes is more than 16."
5682 */
5683 I915_WRITE(_3D_CHICKEN3,
5684 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
5685
5686 /*
5687 * According to the spec the following bits should be
5688 * set in order to enable memory self-refresh and fbc:
5689 * The bit21 and bit22 of 0x42000
5690 * The bit21 and bit22 of 0x42004
5691 * The bit5 and bit7 of 0x42020
5692 * The bit14 of 0x70180
5693 * The bit14 of 0x71180
5694 *
5695 * WaFbcAsynchFlipDisableFbcQueue:snb
5696 */
5697 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5698 I915_READ(ILK_DISPLAY_CHICKEN1) |
5699 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
5700 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5701 I915_READ(ILK_DISPLAY_CHICKEN2) |
5702 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
5703 I915_WRITE(ILK_DSPCLK_GATE_D,
5704 I915_READ(ILK_DSPCLK_GATE_D) |
5705 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
5706 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
5707
5708 g4x_disable_trickle_feed(dev);
5709
5710 cpt_init_clock_gating(dev);
5711
5712 gen6_check_mch_setup(dev);
5713 }
5714
5715 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
5716 {
5717 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
5718
5719 /*
5720 * WaVSThreadDispatchOverride:ivb,vlv
5721 *
5722 * This actually overrides the dispatch
5723 * mode for all thread types.
5724 */
5725 reg &= ~GEN7_FF_SCHED_MASK;
5726 reg |= GEN7_FF_TS_SCHED_HW;
5727 reg |= GEN7_FF_VS_SCHED_HW;
5728 reg |= GEN7_FF_DS_SCHED_HW;
5729
5730 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
5731 }
5732
5733 static void lpt_init_clock_gating(struct drm_device *dev)
5734 {
5735 struct drm_i915_private *dev_priv = dev->dev_private;
5736
5737 /*
5738 * TODO: this bit should only be enabled when really needed, then
5739 * disabled when not needed anymore in order to save power.
5740 */
5741 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
5742 I915_WRITE(SOUTH_DSPCLK_GATE_D,
5743 I915_READ(SOUTH_DSPCLK_GATE_D) |
5744 PCH_LP_PARTITION_LEVEL_DISABLE);
5745
5746 /* WADPOClockGatingDisable:hsw */
5747 I915_WRITE(_TRANSA_CHICKEN1,
5748 I915_READ(_TRANSA_CHICKEN1) |
5749 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
5750 }
5751
5752 static void lpt_suspend_hw(struct drm_device *dev)
5753 {
5754 struct drm_i915_private *dev_priv = dev->dev_private;
5755
5756 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
5757 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
5758
5759 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
5760 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
5761 }
5762 }
5763
5764 static void broadwell_init_clock_gating(struct drm_device *dev)
5765 {
5766 struct drm_i915_private *dev_priv = dev->dev_private;
5767 enum pipe pipe;
5768
5769 I915_WRITE(WM3_LP_ILK, 0);
5770 I915_WRITE(WM2_LP_ILK, 0);
5771 I915_WRITE(WM1_LP_ILK, 0);
5772
5773 /* FIXME(BDW): Check all the w/a, some might only apply to
5774 * pre-production hw. */
5775
5776
5777 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE));
5778
5779 I915_WRITE(_3D_CHICKEN3,
5780 _MASKED_BIT_ENABLE(_3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2)));
5781
5782
5783 /* WaSwitchSolVfFArbitrationPriority:bdw */
5784 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
5785
5786 /* WaPsrDPAMaskVBlankInSRD:bdw */
5787 I915_WRITE(CHICKEN_PAR1_1,
5788 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
5789
5790 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
5791 for_each_pipe(dev_priv, pipe) {
5792 I915_WRITE(CHICKEN_PIPESL_1(pipe),
5793 I915_READ(CHICKEN_PIPESL_1(pipe)) |
5794 BDW_DPRS_MASK_VBLANK_SRD);
5795 }
5796
5797 /* WaVSRefCountFullforceMissDisable:bdw */
5798 /* WaDSRefCountFullforceMissDisable:bdw */
5799 I915_WRITE(GEN7_FF_THREAD_MODE,
5800 I915_READ(GEN7_FF_THREAD_MODE) &
5801 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
5802
5803 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
5804 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
5805
5806 /* WaDisableSDEUnitClockGating:bdw */
5807 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
5808 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5809
5810 lpt_init_clock_gating(dev);
5811 }
5812
5813 static void haswell_init_clock_gating(struct drm_device *dev)
5814 {
5815 struct drm_i915_private *dev_priv = dev->dev_private;
5816
5817 ilk_init_lp_watermarks(dev);
5818
5819 /* L3 caching of data atomics doesn't work -- disable it. */
5820 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
5821 I915_WRITE(HSW_ROW_CHICKEN3,
5822 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
5823
5824 /* This is required by WaCatErrorRejectionIssue:hsw */
5825 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5826 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5827 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5828
5829 /* WaVSRefCountFullforceMissDisable:hsw */
5830 I915_WRITE(GEN7_FF_THREAD_MODE,
5831 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
5832
5833 /* WaDisable_RenderCache_OperationalFlush:hsw */
5834 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5835
5836 /* enable HiZ Raw Stall Optimization */
5837 I915_WRITE(CACHE_MODE_0_GEN7,
5838 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
5839
5840 /* WaDisable4x2SubspanOptimization:hsw */
5841 I915_WRITE(CACHE_MODE_1,
5842 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5843
5844 /*
5845 * BSpec recommends 8x4 when MSAA is used,
5846 * however in practice 16x4 seems fastest.
5847 *
5848 * Note that PS/WM thread counts depend on the WIZ hashing
5849 * disable bit, which we don't touch here, but it's good
5850 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5851 */
5852 I915_WRITE(GEN7_GT_MODE,
5853 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5854
5855 /* WaSwitchSolVfFArbitrationPriority:hsw */
5856 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
5857
5858 /* WaRsPkgCStateDisplayPMReq:hsw */
5859 I915_WRITE(CHICKEN_PAR1_1,
5860 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
5861
5862 lpt_init_clock_gating(dev);
5863 }
5864
5865 static void ivybridge_init_clock_gating(struct drm_device *dev)
5866 {
5867 struct drm_i915_private *dev_priv = dev->dev_private;
5868 uint32_t snpcr;
5869
5870 ilk_init_lp_watermarks(dev);
5871
5872 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
5873
5874 /* WaDisableEarlyCull:ivb */
5875 I915_WRITE(_3D_CHICKEN3,
5876 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5877
5878 /* WaDisableBackToBackFlipFix:ivb */
5879 I915_WRITE(IVB_CHICKEN3,
5880 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5881 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5882
5883 /* WaDisablePSDDualDispatchEnable:ivb */
5884 if (IS_IVB_GT1(dev))
5885 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5886 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5887
5888 /* WaDisable_RenderCache_OperationalFlush:ivb */
5889 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5890
5891 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
5892 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5893 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5894
5895 /* WaApplyL3ControlAndL3ChickenMode:ivb */
5896 I915_WRITE(GEN7_L3CNTLREG1,
5897 GEN7_WA_FOR_GEN7_L3_CONTROL);
5898 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
5899 GEN7_WA_L3_CHICKEN_MODE);
5900 if (IS_IVB_GT1(dev))
5901 I915_WRITE(GEN7_ROW_CHICKEN2,
5902 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5903 else {
5904 /* must write both registers */
5905 I915_WRITE(GEN7_ROW_CHICKEN2,
5906 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5907 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
5908 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5909 }
5910
5911 /* WaForceL3Serialization:ivb */
5912 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5913 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5914
5915 /*
5916 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5917 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
5918 */
5919 I915_WRITE(GEN6_UCGCTL2,
5920 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
5921
5922 /* This is required by WaCatErrorRejectionIssue:ivb */
5923 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5924 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5925 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5926
5927 g4x_disable_trickle_feed(dev);
5928
5929 gen7_setup_fixed_func_scheduler(dev_priv);
5930
5931 if (0) { /* causes HiZ corruption on ivb:gt1 */
5932 /* enable HiZ Raw Stall Optimization */
5933 I915_WRITE(CACHE_MODE_0_GEN7,
5934 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
5935 }
5936
5937 /* WaDisable4x2SubspanOptimization:ivb */
5938 I915_WRITE(CACHE_MODE_1,
5939 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5940
5941 /*
5942 * BSpec recommends 8x4 when MSAA is used,
5943 * however in practice 16x4 seems fastest.
5944 *
5945 * Note that PS/WM thread counts depend on the WIZ hashing
5946 * disable bit, which we don't touch here, but it's good
5947 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5948 */
5949 I915_WRITE(GEN7_GT_MODE,
5950 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5951
5952 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5953 snpcr &= ~GEN6_MBC_SNPCR_MASK;
5954 snpcr |= GEN6_MBC_SNPCR_MED;
5955 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5956
5957 if (!HAS_PCH_NOP(dev))
5958 cpt_init_clock_gating(dev);
5959
5960 gen6_check_mch_setup(dev);
5961 }
5962
5963 static void valleyview_init_clock_gating(struct drm_device *dev)
5964 {
5965 struct drm_i915_private *dev_priv = dev->dev_private;
5966
5967 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
5968
5969 /* WaDisableEarlyCull:vlv */
5970 I915_WRITE(_3D_CHICKEN3,
5971 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5972
5973 /* WaDisableBackToBackFlipFix:vlv */
5974 I915_WRITE(IVB_CHICKEN3,
5975 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5976 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5977
5978 /* WaPsdDispatchEnable:vlv */
5979 /* WaDisablePSDDualDispatchEnable:vlv */
5980 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5981 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
5982 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5983
5984 /* WaDisable_RenderCache_OperationalFlush:vlv */
5985 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5986
5987 /* WaForceL3Serialization:vlv */
5988 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5989 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5990
5991 /* WaDisableDopClockGating:vlv */
5992 I915_WRITE(GEN7_ROW_CHICKEN2,
5993 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5994
5995 /* This is required by WaCatErrorRejectionIssue:vlv */
5996 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5997 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5998 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5999
6000 gen7_setup_fixed_func_scheduler(dev_priv);
6001
6002 /*
6003 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6004 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
6005 */
6006 I915_WRITE(GEN6_UCGCTL2,
6007 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
6008
6009 /* WaDisableL3Bank2xClockGate:vlv
6010 * Disabling L3 clock gating- MMIO 940c[25] = 1
6011 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
6012 I915_WRITE(GEN7_UCGCTL4,
6013 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
6014
6015 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6016
6017 /*
6018 * BSpec says this must be set, even though
6019 * WaDisable4x2SubspanOptimization isn't listed for VLV.
6020 */
6021 I915_WRITE(CACHE_MODE_1,
6022 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6023
6024 /*
6025 * WaIncreaseL3CreditsForVLVB0:vlv
6026 * This is the hardware default actually.
6027 */
6028 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
6029
6030 /*
6031 * WaDisableVLVClockGating_VBIIssue:vlv
6032 * Disable clock gating on th GCFG unit to prevent a delay
6033 * in the reporting of vblank events.
6034 */
6035 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6036 }
6037
6038 static void cherryview_init_clock_gating(struct drm_device *dev)
6039 {
6040 struct drm_i915_private *dev_priv = dev->dev_private;
6041
6042 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6043
6044 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6045
6046 /* WaVSRefCountFullforceMissDisable:chv */
6047 /* WaDSRefCountFullforceMissDisable:chv */
6048 I915_WRITE(GEN7_FF_THREAD_MODE,
6049 I915_READ(GEN7_FF_THREAD_MODE) &
6050 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
6051
6052 /* WaDisableSemaphoreAndSyncFlipWait:chv */
6053 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6054 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
6055
6056 /* WaDisableCSUnitClockGating:chv */
6057 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
6058 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6059
6060 /* WaDisableSDEUnitClockGating:chv */
6061 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6062 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6063
6064 /* WaDisableGunitClockGating:chv (pre-production hw) */
6065 I915_WRITE(VLV_GUNIT_CLOCK_GATE, I915_READ(VLV_GUNIT_CLOCK_GATE) |
6066 GINT_DIS);
6067
6068 /* WaDisableFfDopClockGating:chv (pre-production hw) */
6069 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6070 _MASKED_BIT_ENABLE(GEN8_FF_DOP_CLOCK_GATE_DISABLE));
6071
6072 /* WaDisableDopClockGating:chv (pre-production hw) */
6073 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
6074 GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
6075 }
6076
6077 static void g4x_init_clock_gating(struct drm_device *dev)
6078 {
6079 struct drm_i915_private *dev_priv = dev->dev_private;
6080 uint32_t dspclk_gate;
6081
6082 I915_WRITE(RENCLK_GATE_D1, 0);
6083 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
6084 GS_UNIT_CLOCK_GATE_DISABLE |
6085 CL_UNIT_CLOCK_GATE_DISABLE);
6086 I915_WRITE(RAMCLK_GATE_D, 0);
6087 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
6088 OVRUNIT_CLOCK_GATE_DISABLE |
6089 OVCUNIT_CLOCK_GATE_DISABLE;
6090 if (IS_GM45(dev))
6091 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
6092 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
6093
6094 /* WaDisableRenderCachePipelinedFlush */
6095 I915_WRITE(CACHE_MODE_0,
6096 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6097
6098 /* WaDisable_RenderCache_OperationalFlush:g4x */
6099 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6100
6101 g4x_disable_trickle_feed(dev);
6102 }
6103
6104 static void crestline_init_clock_gating(struct drm_device *dev)
6105 {
6106 struct drm_i915_private *dev_priv = dev->dev_private;
6107
6108 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
6109 I915_WRITE(RENCLK_GATE_D2, 0);
6110 I915_WRITE(DSPCLK_GATE_D, 0);
6111 I915_WRITE(RAMCLK_GATE_D, 0);
6112 I915_WRITE16(DEUC, 0);
6113 I915_WRITE(MI_ARB_STATE,
6114 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6115
6116 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6117 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6118 }
6119
6120 static void broadwater_init_clock_gating(struct drm_device *dev)
6121 {
6122 struct drm_i915_private *dev_priv = dev->dev_private;
6123
6124 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
6125 I965_RCC_CLOCK_GATE_DISABLE |
6126 I965_RCPB_CLOCK_GATE_DISABLE |
6127 I965_ISC_CLOCK_GATE_DISABLE |
6128 I965_FBC_CLOCK_GATE_DISABLE);
6129 I915_WRITE(RENCLK_GATE_D2, 0);
6130 I915_WRITE(MI_ARB_STATE,
6131 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6132
6133 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6134 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6135 }
6136
6137 static void gen3_init_clock_gating(struct drm_device *dev)
6138 {
6139 struct drm_i915_private *dev_priv = dev->dev_private;
6140 u32 dstate = I915_READ(D_STATE);
6141
6142 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
6143 DSTATE_DOT_CLOCK_GATING;
6144 I915_WRITE(D_STATE, dstate);
6145
6146 if (IS_PINEVIEW(dev))
6147 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
6148
6149 /* IIR "flip pending" means done if this bit is set */
6150 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
6151
6152 /* interrupts should cause a wake up from C3 */
6153 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
6154
6155 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
6156 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
6157
6158 I915_WRITE(MI_ARB_STATE,
6159 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6160 }
6161
6162 static void i85x_init_clock_gating(struct drm_device *dev)
6163 {
6164 struct drm_i915_private *dev_priv = dev->dev_private;
6165
6166 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
6167
6168 /* interrupts should cause a wake up from C3 */
6169 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
6170 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
6171
6172 I915_WRITE(MEM_MODE,
6173 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
6174 }
6175
6176 static void i830_init_clock_gating(struct drm_device *dev)
6177 {
6178 struct drm_i915_private *dev_priv = dev->dev_private;
6179
6180 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
6181
6182 I915_WRITE(MEM_MODE,
6183 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
6184 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
6185 }
6186
6187 void intel_init_clock_gating(struct drm_device *dev)
6188 {
6189 struct drm_i915_private *dev_priv = dev->dev_private;
6190
6191 dev_priv->display.init_clock_gating(dev);
6192 }
6193
6194 void intel_suspend_hw(struct drm_device *dev)
6195 {
6196 if (HAS_PCH_LPT(dev))
6197 lpt_suspend_hw(dev);
6198 }
6199
6200 #define for_each_power_well(i, power_well, domain_mask, power_domains) \
6201 for (i = 0; \
6202 i < (power_domains)->power_well_count && \
6203 ((power_well) = &(power_domains)->power_wells[i]); \
6204 i++) \
6205 if ((power_well)->domains & (domain_mask))
6206
6207 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
6208 for (i = (power_domains)->power_well_count - 1; \
6209 i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
6210 i--) \
6211 if ((power_well)->domains & (domain_mask))
6212
6213 /**
6214 * We should only use the power well if we explicitly asked the hardware to
6215 * enable it, so check if it's enabled and also check if we've requested it to
6216 * be enabled.
6217 */
6218 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
6219 struct i915_power_well *power_well)
6220 {
6221 return I915_READ(HSW_PWR_WELL_DRIVER) ==
6222 (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
6223 }
6224
6225 bool intel_display_power_enabled_unlocked(struct drm_i915_private *dev_priv,
6226 enum intel_display_power_domain domain)
6227 {
6228 struct i915_power_domains *power_domains;
6229 struct i915_power_well *power_well;
6230 bool is_enabled;
6231 int i;
6232
6233 if (dev_priv->pm.suspended)
6234 return false;
6235
6236 power_domains = &dev_priv->power_domains;
6237
6238 is_enabled = true;
6239
6240 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
6241 if (power_well->always_on)
6242 continue;
6243
6244 if (!power_well->hw_enabled) {
6245 is_enabled = false;
6246 break;
6247 }
6248 }
6249
6250 return is_enabled;
6251 }
6252
6253 bool intel_display_power_enabled(struct drm_i915_private *dev_priv,
6254 enum intel_display_power_domain domain)
6255 {
6256 struct i915_power_domains *power_domains;
6257 bool ret;
6258
6259 power_domains = &dev_priv->power_domains;
6260
6261 mutex_lock(&power_domains->lock);
6262 ret = intel_display_power_enabled_unlocked(dev_priv, domain);
6263 mutex_unlock(&power_domains->lock);
6264
6265 return ret;
6266 }
6267
6268 /*
6269 * Starting with Haswell, we have a "Power Down Well" that can be turned off
6270 * when not needed anymore. We have 4 registers that can request the power well
6271 * to be enabled, and it will only be disabled if none of the registers is
6272 * requesting it to be enabled.
6273 */
6274 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
6275 {
6276 struct drm_device *dev = dev_priv->dev;
6277
6278 /*
6279 * After we re-enable the power well, if we touch VGA register 0x3d5
6280 * we'll get unclaimed register interrupts. This stops after we write
6281 * anything to the VGA MSR register. The vgacon module uses this
6282 * register all the time, so if we unbind our driver and, as a
6283 * consequence, bind vgacon, we'll get stuck in an infinite loop at
6284 * console_unlock(). So make here we touch the VGA MSR register, making
6285 * sure vgacon can keep working normally without triggering interrupts
6286 * and error messages.
6287 */
6288 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
6289 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
6290 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
6291
6292 if (IS_BROADWELL(dev) || (INTEL_INFO(dev)->gen >= 9))
6293 gen8_irq_power_well_post_enable(dev_priv);
6294 }
6295
6296 static void hsw_set_power_well(struct drm_i915_private *dev_priv,
6297 struct i915_power_well *power_well, bool enable)
6298 {
6299 bool is_enabled, enable_requested;
6300 uint32_t tmp;
6301
6302 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
6303 is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
6304 enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
6305
6306 if (enable) {
6307 if (!enable_requested)
6308 I915_WRITE(HSW_PWR_WELL_DRIVER,
6309 HSW_PWR_WELL_ENABLE_REQUEST);
6310
6311 if (!is_enabled) {
6312 DRM_DEBUG_KMS("Enabling power well\n");
6313 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
6314 HSW_PWR_WELL_STATE_ENABLED), 20))
6315 DRM_ERROR("Timeout enabling power well\n");
6316 }
6317
6318 hsw_power_well_post_enable(dev_priv);
6319 } else {
6320 if (enable_requested) {
6321 I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
6322 POSTING_READ(HSW_PWR_WELL_DRIVER);
6323 DRM_DEBUG_KMS("Requesting to disable the power well\n");
6324 }
6325 }
6326 }
6327
6328 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
6329 struct i915_power_well *power_well)
6330 {
6331 hsw_set_power_well(dev_priv, power_well, power_well->count > 0);
6332
6333 /*
6334 * We're taking over the BIOS, so clear any requests made by it since
6335 * the driver is in charge now.
6336 */
6337 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
6338 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
6339 }
6340
6341 static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
6342 struct i915_power_well *power_well)
6343 {
6344 hsw_set_power_well(dev_priv, power_well, true);
6345 }
6346
6347 static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
6348 struct i915_power_well *power_well)
6349 {
6350 hsw_set_power_well(dev_priv, power_well, false);
6351 }
6352
6353 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
6354 struct i915_power_well *power_well)
6355 {
6356 }
6357
6358 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
6359 struct i915_power_well *power_well)
6360 {
6361 return true;
6362 }
6363
6364 static void vlv_set_power_well(struct drm_i915_private *dev_priv,
6365 struct i915_power_well *power_well, bool enable)
6366 {
6367 enum punit_power_well power_well_id = power_well->data;
6368 u32 mask;
6369 u32 state;
6370 u32 ctrl;
6371
6372 mask = PUNIT_PWRGT_MASK(power_well_id);
6373 state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) :
6374 PUNIT_PWRGT_PWR_GATE(power_well_id);
6375
6376 mutex_lock(&dev_priv->rps.hw_lock);
6377
6378 #define COND \
6379 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
6380
6381 if (COND)
6382 goto out;
6383
6384 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
6385 ctrl &= ~mask;
6386 ctrl |= state;
6387 vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
6388
6389 if (wait_for(COND, 100))
6390 DRM_ERROR("timout setting power well state %08x (%08x)\n",
6391 state,
6392 vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
6393
6394 #undef COND
6395
6396 out:
6397 mutex_unlock(&dev_priv->rps.hw_lock);
6398 }
6399
6400 static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv,
6401 struct i915_power_well *power_well)
6402 {
6403 vlv_set_power_well(dev_priv, power_well, power_well->count > 0);
6404 }
6405
6406 static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
6407 struct i915_power_well *power_well)
6408 {
6409 vlv_set_power_well(dev_priv, power_well, true);
6410 }
6411
6412 static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
6413 struct i915_power_well *power_well)
6414 {
6415 vlv_set_power_well(dev_priv, power_well, false);
6416 }
6417
6418 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
6419 struct i915_power_well *power_well)
6420 {
6421 int power_well_id = power_well->data;
6422 bool enabled = false;
6423 u32 mask;
6424 u32 state;
6425 u32 ctrl;
6426
6427 mask = PUNIT_PWRGT_MASK(power_well_id);
6428 ctrl = PUNIT_PWRGT_PWR_ON(power_well_id);
6429
6430 mutex_lock(&dev_priv->rps.hw_lock);
6431
6432 state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
6433 /*
6434 * We only ever set the power-on and power-gate states, anything
6435 * else is unexpected.
6436 */
6437 WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) &&
6438 state != PUNIT_PWRGT_PWR_GATE(power_well_id));
6439 if (state == ctrl)
6440 enabled = true;
6441
6442 /*
6443 * A transient state at this point would mean some unexpected party
6444 * is poking at the power controls too.
6445 */
6446 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
6447 WARN_ON(ctrl != state);
6448
6449 mutex_unlock(&dev_priv->rps.hw_lock);
6450
6451 return enabled;
6452 }
6453
6454 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
6455 struct i915_power_well *power_well)
6456 {
6457 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
6458
6459 vlv_set_power_well(dev_priv, power_well, true);
6460
6461 spin_lock_irq(&dev_priv->irq_lock);
6462 valleyview_enable_display_irqs(dev_priv);
6463 spin_unlock_irq(&dev_priv->irq_lock);
6464
6465 /*
6466 * During driver initialization/resume we can avoid restoring the
6467 * part of the HW/SW state that will be inited anyway explicitly.
6468 */
6469 if (dev_priv->power_domains.initializing)
6470 return;
6471
6472 intel_hpd_init(dev_priv->dev);
6473
6474 i915_redisable_vga_power_on(dev_priv->dev);
6475 }
6476
6477 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
6478 struct i915_power_well *power_well)
6479 {
6480 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
6481
6482 spin_lock_irq(&dev_priv->irq_lock);
6483 valleyview_disable_display_irqs(dev_priv);
6484 spin_unlock_irq(&dev_priv->irq_lock);
6485
6486 vlv_set_power_well(dev_priv, power_well, false);
6487
6488 vlv_power_sequencer_reset(dev_priv);
6489 }
6490
6491 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
6492 struct i915_power_well *power_well)
6493 {
6494 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
6495
6496 /*
6497 * Enable the CRI clock source so we can get at the
6498 * display and the reference clock for VGA
6499 * hotplug / manual detection.
6500 */
6501 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
6502 DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
6503 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
6504
6505 vlv_set_power_well(dev_priv, power_well, true);
6506
6507 /*
6508 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
6509 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
6510 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
6511 * b. The other bits such as sfr settings / modesel may all
6512 * be set to 0.
6513 *
6514 * This should only be done on init and resume from S3 with
6515 * both PLLs disabled, or we risk losing DPIO and PLL
6516 * synchronization.
6517 */
6518 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
6519 }
6520
6521 static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
6522 struct i915_power_well *power_well)
6523 {
6524 enum pipe pipe;
6525
6526 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
6527
6528 for_each_pipe(dev_priv, pipe)
6529 assert_pll_disabled(dev_priv, pipe);
6530
6531 /* Assert common reset */
6532 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST);
6533
6534 vlv_set_power_well(dev_priv, power_well, false);
6535 }
6536
6537 static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
6538 struct i915_power_well *power_well)
6539 {
6540 enum dpio_phy phy;
6541
6542 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
6543 power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
6544
6545 /*
6546 * Enable the CRI clock source so we can get at the
6547 * display and the reference clock for VGA
6548 * hotplug / manual detection.
6549 */
6550 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
6551 phy = DPIO_PHY0;
6552 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
6553 DPLL_REFA_CLK_ENABLE_VLV);
6554 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
6555 DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
6556 } else {
6557 phy = DPIO_PHY1;
6558 I915_WRITE(DPLL(PIPE_C), I915_READ(DPLL(PIPE_C)) |
6559 DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
6560 }
6561 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
6562 vlv_set_power_well(dev_priv, power_well, true);
6563
6564 /* Poll for phypwrgood signal */
6565 if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1))
6566 DRM_ERROR("Display PHY %d is not power up\n", phy);
6567
6568 I915_WRITE(DISPLAY_PHY_CONTROL, I915_READ(DISPLAY_PHY_CONTROL) |
6569 PHY_COM_LANE_RESET_DEASSERT(phy));
6570 }
6571
6572 static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
6573 struct i915_power_well *power_well)
6574 {
6575 enum dpio_phy phy;
6576
6577 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
6578 power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
6579
6580 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
6581 phy = DPIO_PHY0;
6582 assert_pll_disabled(dev_priv, PIPE_A);
6583 assert_pll_disabled(dev_priv, PIPE_B);
6584 } else {
6585 phy = DPIO_PHY1;
6586 assert_pll_disabled(dev_priv, PIPE_C);
6587 }
6588
6589 I915_WRITE(DISPLAY_PHY_CONTROL, I915_READ(DISPLAY_PHY_CONTROL) &
6590 ~PHY_COM_LANE_RESET_DEASSERT(phy));
6591
6592 vlv_set_power_well(dev_priv, power_well, false);
6593 }
6594
6595 static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,
6596 struct i915_power_well *power_well)
6597 {
6598 enum pipe pipe = power_well->data;
6599 bool enabled;
6600 u32 state, ctrl;
6601
6602 mutex_lock(&dev_priv->rps.hw_lock);
6603
6604 state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe);
6605 /*
6606 * We only ever set the power-on and power-gate states, anything
6607 * else is unexpected.
6608 */
6609 WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe));
6610 enabled = state == DP_SSS_PWR_ON(pipe);
6611
6612 /*
6613 * A transient state at this point would mean some unexpected party
6614 * is poking at the power controls too.
6615 */
6616 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe);
6617 WARN_ON(ctrl << 16 != state);
6618
6619 mutex_unlock(&dev_priv->rps.hw_lock);
6620
6621 return enabled;
6622 }
6623
6624 static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
6625 struct i915_power_well *power_well,
6626 bool enable)
6627 {
6628 enum pipe pipe = power_well->data;
6629 u32 state;
6630 u32 ctrl;
6631
6632 state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe);
6633
6634 mutex_lock(&dev_priv->rps.hw_lock);
6635
6636 #define COND \
6637 ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state)
6638
6639 if (COND)
6640 goto out;
6641
6642 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
6643 ctrl &= ~DP_SSC_MASK(pipe);
6644 ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe);
6645 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl);
6646
6647 if (wait_for(COND, 100))
6648 DRM_ERROR("timout setting power well state %08x (%08x)\n",
6649 state,
6650 vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ));
6651
6652 #undef COND
6653
6654 out:
6655 mutex_unlock(&dev_priv->rps.hw_lock);
6656 }
6657
6658 static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv,
6659 struct i915_power_well *power_well)
6660 {
6661 chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0);
6662 }
6663
6664 static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
6665 struct i915_power_well *power_well)
6666 {
6667 WARN_ON_ONCE(power_well->data != PIPE_A &&
6668 power_well->data != PIPE_B &&
6669 power_well->data != PIPE_C);
6670
6671 chv_set_pipe_power_well(dev_priv, power_well, true);
6672 }
6673
6674 static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
6675 struct i915_power_well *power_well)
6676 {
6677 WARN_ON_ONCE(power_well->data != PIPE_A &&
6678 power_well->data != PIPE_B &&
6679 power_well->data != PIPE_C);
6680
6681 chv_set_pipe_power_well(dev_priv, power_well, false);
6682 }
6683
6684 static void check_power_well_state(struct drm_i915_private *dev_priv,
6685 struct i915_power_well *power_well)
6686 {
6687 bool enabled = power_well->ops->is_enabled(dev_priv, power_well);
6688
6689 if (power_well->always_on || !i915.disable_power_well) {
6690 if (!enabled)
6691 goto mismatch;
6692
6693 return;
6694 }
6695
6696 if (enabled != (power_well->count > 0))
6697 goto mismatch;
6698
6699 return;
6700
6701 mismatch:
6702 WARN(1, "state mismatch for '%s' (always_on %d hw state %d use-count %d disable_power_well %d\n",
6703 power_well->name, power_well->always_on, enabled,
6704 power_well->count, i915.disable_power_well);
6705 }
6706
6707 void intel_display_power_get(struct drm_i915_private *dev_priv,
6708 enum intel_display_power_domain domain)
6709 {
6710 struct i915_power_domains *power_domains;
6711 struct i915_power_well *power_well;
6712 int i;
6713
6714 intel_runtime_pm_get(dev_priv);
6715
6716 power_domains = &dev_priv->power_domains;
6717
6718 mutex_lock(&power_domains->lock);
6719
6720 for_each_power_well(i, power_well, BIT(domain), power_domains) {
6721 if (!power_well->count++) {
6722 DRM_DEBUG_KMS("enabling %s\n", power_well->name);
6723 power_well->ops->enable(dev_priv, power_well);
6724 power_well->hw_enabled = true;
6725 }
6726
6727 check_power_well_state(dev_priv, power_well);
6728 }
6729
6730 power_domains->domain_use_count[domain]++;
6731
6732 mutex_unlock(&power_domains->lock);
6733 }
6734
6735 void intel_display_power_put(struct drm_i915_private *dev_priv,
6736 enum intel_display_power_domain domain)
6737 {
6738 struct i915_power_domains *power_domains;
6739 struct i915_power_well *power_well;
6740 int i;
6741
6742 power_domains = &dev_priv->power_domains;
6743
6744 mutex_lock(&power_domains->lock);
6745
6746 WARN_ON(!power_domains->domain_use_count[domain]);
6747 power_domains->domain_use_count[domain]--;
6748
6749 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
6750 WARN_ON(!power_well->count);
6751
6752 if (!--power_well->count && i915.disable_power_well) {
6753 DRM_DEBUG_KMS("disabling %s\n", power_well->name);
6754 power_well->hw_enabled = false;
6755 power_well->ops->disable(dev_priv, power_well);
6756 }
6757
6758 check_power_well_state(dev_priv, power_well);
6759 }
6760
6761 mutex_unlock(&power_domains->lock);
6762
6763 intel_runtime_pm_put(dev_priv);
6764 }
6765
6766 static struct i915_power_domains *hsw_pwr;
6767
6768 /* Display audio driver power well request */
6769 int i915_request_power_well(void)
6770 {
6771 struct drm_i915_private *dev_priv;
6772
6773 if (!hsw_pwr)
6774 return -ENODEV;
6775
6776 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
6777 power_domains);
6778 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
6779 return 0;
6780 }
6781 EXPORT_SYMBOL_GPL(i915_request_power_well);
6782
6783 /* Display audio driver power well release */
6784 int i915_release_power_well(void)
6785 {
6786 struct drm_i915_private *dev_priv;
6787
6788 if (!hsw_pwr)
6789 return -ENODEV;
6790
6791 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
6792 power_domains);
6793 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
6794 return 0;
6795 }
6796 EXPORT_SYMBOL_GPL(i915_release_power_well);
6797
6798 /*
6799 * Private interface for the audio driver to get CDCLK in kHz.
6800 *
6801 * Caller must request power well using i915_request_power_well() prior to
6802 * making the call.
6803 */
6804 int i915_get_cdclk_freq(void)
6805 {
6806 struct drm_i915_private *dev_priv;
6807
6808 if (!hsw_pwr)
6809 return -ENODEV;
6810
6811 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
6812 power_domains);
6813
6814 return intel_ddi_get_cdclk_freq(dev_priv);
6815 }
6816 EXPORT_SYMBOL_GPL(i915_get_cdclk_freq);
6817
6818
6819 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
6820
6821 #define HSW_ALWAYS_ON_POWER_DOMAINS ( \
6822 BIT(POWER_DOMAIN_PIPE_A) | \
6823 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
6824 BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
6825 BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
6826 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6827 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6828 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6829 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6830 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
6831 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
6832 BIT(POWER_DOMAIN_PORT_CRT) | \
6833 BIT(POWER_DOMAIN_PLLS) | \
6834 BIT(POWER_DOMAIN_INIT))
6835 #define HSW_DISPLAY_POWER_DOMAINS ( \
6836 (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \
6837 BIT(POWER_DOMAIN_INIT))
6838
6839 #define BDW_ALWAYS_ON_POWER_DOMAINS ( \
6840 HSW_ALWAYS_ON_POWER_DOMAINS | \
6841 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
6842 #define BDW_DISPLAY_POWER_DOMAINS ( \
6843 (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) | \
6844 BIT(POWER_DOMAIN_INIT))
6845
6846 #define VLV_ALWAYS_ON_POWER_DOMAINS BIT(POWER_DOMAIN_INIT)
6847 #define VLV_DISPLAY_POWER_DOMAINS POWER_DOMAIN_MASK
6848
6849 #define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \
6850 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6851 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6852 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6853 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6854 BIT(POWER_DOMAIN_PORT_CRT) | \
6855 BIT(POWER_DOMAIN_INIT))
6856
6857 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \
6858 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6859 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6860 BIT(POWER_DOMAIN_INIT))
6861
6862 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \
6863 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6864 BIT(POWER_DOMAIN_INIT))
6865
6866 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \
6867 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6868 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6869 BIT(POWER_DOMAIN_INIT))
6870
6871 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \
6872 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6873 BIT(POWER_DOMAIN_INIT))
6874
6875 #define CHV_PIPE_A_POWER_DOMAINS ( \
6876 BIT(POWER_DOMAIN_PIPE_A) | \
6877 BIT(POWER_DOMAIN_INIT))
6878
6879 #define CHV_PIPE_B_POWER_DOMAINS ( \
6880 BIT(POWER_DOMAIN_PIPE_B) | \
6881 BIT(POWER_DOMAIN_INIT))
6882
6883 #define CHV_PIPE_C_POWER_DOMAINS ( \
6884 BIT(POWER_DOMAIN_PIPE_C) | \
6885 BIT(POWER_DOMAIN_INIT))
6886
6887 #define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \
6888 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6889 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6890 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6891 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6892 BIT(POWER_DOMAIN_INIT))
6893
6894 #define CHV_DPIO_CMN_D_POWER_DOMAINS ( \
6895 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
6896 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
6897 BIT(POWER_DOMAIN_INIT))
6898
6899 #define CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS ( \
6900 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
6901 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
6902 BIT(POWER_DOMAIN_INIT))
6903
6904 #define CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS ( \
6905 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
6906 BIT(POWER_DOMAIN_INIT))
6907
6908 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
6909 .sync_hw = i9xx_always_on_power_well_noop,
6910 .enable = i9xx_always_on_power_well_noop,
6911 .disable = i9xx_always_on_power_well_noop,
6912 .is_enabled = i9xx_always_on_power_well_enabled,
6913 };
6914
6915 static const struct i915_power_well_ops chv_pipe_power_well_ops = {
6916 .sync_hw = chv_pipe_power_well_sync_hw,
6917 .enable = chv_pipe_power_well_enable,
6918 .disable = chv_pipe_power_well_disable,
6919 .is_enabled = chv_pipe_power_well_enabled,
6920 };
6921
6922 static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = {
6923 .sync_hw = vlv_power_well_sync_hw,
6924 .enable = chv_dpio_cmn_power_well_enable,
6925 .disable = chv_dpio_cmn_power_well_disable,
6926 .is_enabled = vlv_power_well_enabled,
6927 };
6928
6929 static struct i915_power_well i9xx_always_on_power_well[] = {
6930 {
6931 .name = "always-on",
6932 .always_on = 1,
6933 .domains = POWER_DOMAIN_MASK,
6934 .ops = &i9xx_always_on_power_well_ops,
6935 },
6936 };
6937
6938 static const struct i915_power_well_ops hsw_power_well_ops = {
6939 .sync_hw = hsw_power_well_sync_hw,
6940 .enable = hsw_power_well_enable,
6941 .disable = hsw_power_well_disable,
6942 .is_enabled = hsw_power_well_enabled,
6943 };
6944
6945 static struct i915_power_well hsw_power_wells[] = {
6946 {
6947 .name = "always-on",
6948 .always_on = 1,
6949 .domains = HSW_ALWAYS_ON_POWER_DOMAINS,
6950 .ops = &i9xx_always_on_power_well_ops,
6951 },
6952 {
6953 .name = "display",
6954 .domains = HSW_DISPLAY_POWER_DOMAINS,
6955 .ops = &hsw_power_well_ops,
6956 },
6957 };
6958
6959 static struct i915_power_well bdw_power_wells[] = {
6960 {
6961 .name = "always-on",
6962 .always_on = 1,
6963 .domains = BDW_ALWAYS_ON_POWER_DOMAINS,
6964 .ops = &i9xx_always_on_power_well_ops,
6965 },
6966 {
6967 .name = "display",
6968 .domains = BDW_DISPLAY_POWER_DOMAINS,
6969 .ops = &hsw_power_well_ops,
6970 },
6971 };
6972
6973 static const struct i915_power_well_ops vlv_display_power_well_ops = {
6974 .sync_hw = vlv_power_well_sync_hw,
6975 .enable = vlv_display_power_well_enable,
6976 .disable = vlv_display_power_well_disable,
6977 .is_enabled = vlv_power_well_enabled,
6978 };
6979
6980 static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = {
6981 .sync_hw = vlv_power_well_sync_hw,
6982 .enable = vlv_dpio_cmn_power_well_enable,
6983 .disable = vlv_dpio_cmn_power_well_disable,
6984 .is_enabled = vlv_power_well_enabled,
6985 };
6986
6987 static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
6988 .sync_hw = vlv_power_well_sync_hw,
6989 .enable = vlv_power_well_enable,
6990 .disable = vlv_power_well_disable,
6991 .is_enabled = vlv_power_well_enabled,
6992 };
6993
6994 static struct i915_power_well vlv_power_wells[] = {
6995 {
6996 .name = "always-on",
6997 .always_on = 1,
6998 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
6999 .ops = &i9xx_always_on_power_well_ops,
7000 },
7001 {
7002 .name = "display",
7003 .domains = VLV_DISPLAY_POWER_DOMAINS,
7004 .data = PUNIT_POWER_WELL_DISP2D,
7005 .ops = &vlv_display_power_well_ops,
7006 },
7007 {
7008 .name = "dpio-tx-b-01",
7009 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
7010 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
7011 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
7012 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
7013 .ops = &vlv_dpio_power_well_ops,
7014 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
7015 },
7016 {
7017 .name = "dpio-tx-b-23",
7018 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
7019 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
7020 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
7021 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
7022 .ops = &vlv_dpio_power_well_ops,
7023 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
7024 },
7025 {
7026 .name = "dpio-tx-c-01",
7027 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
7028 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
7029 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
7030 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
7031 .ops = &vlv_dpio_power_well_ops,
7032 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
7033 },
7034 {
7035 .name = "dpio-tx-c-23",
7036 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
7037 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
7038 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
7039 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
7040 .ops = &vlv_dpio_power_well_ops,
7041 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
7042 },
7043 {
7044 .name = "dpio-common",
7045 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
7046 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
7047 .ops = &vlv_dpio_cmn_power_well_ops,
7048 },
7049 };
7050
7051 static struct i915_power_well chv_power_wells[] = {
7052 {
7053 .name = "always-on",
7054 .always_on = 1,
7055 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
7056 .ops = &i9xx_always_on_power_well_ops,
7057 },
7058 #if 0
7059 {
7060 .name = "display",
7061 .domains = VLV_DISPLAY_POWER_DOMAINS,
7062 .data = PUNIT_POWER_WELL_DISP2D,
7063 .ops = &vlv_display_power_well_ops,
7064 },
7065 {
7066 .name = "pipe-a",
7067 .domains = CHV_PIPE_A_POWER_DOMAINS,
7068 .data = PIPE_A,
7069 .ops = &chv_pipe_power_well_ops,
7070 },
7071 {
7072 .name = "pipe-b",
7073 .domains = CHV_PIPE_B_POWER_DOMAINS,
7074 .data = PIPE_B,
7075 .ops = &chv_pipe_power_well_ops,
7076 },
7077 {
7078 .name = "pipe-c",
7079 .domains = CHV_PIPE_C_POWER_DOMAINS,
7080 .data = PIPE_C,
7081 .ops = &chv_pipe_power_well_ops,
7082 },
7083 #endif
7084 {
7085 .name = "dpio-common-bc",
7086 /*
7087 * XXX: cmnreset for one PHY seems to disturb the other.
7088 * As a workaround keep both powered on at the same
7089 * time for now.
7090 */
7091 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS | CHV_DPIO_CMN_D_POWER_DOMAINS,
7092 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
7093 .ops = &chv_dpio_cmn_power_well_ops,
7094 },
7095 {
7096 .name = "dpio-common-d",
7097 /*
7098 * XXX: cmnreset for one PHY seems to disturb the other.
7099 * As a workaround keep both powered on at the same
7100 * time for now.
7101 */
7102 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS | CHV_DPIO_CMN_D_POWER_DOMAINS,
7103 .data = PUNIT_POWER_WELL_DPIO_CMN_D,
7104 .ops = &chv_dpio_cmn_power_well_ops,
7105 },
7106 #if 0
7107 {
7108 .name = "dpio-tx-b-01",
7109 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
7110 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS,
7111 .ops = &vlv_dpio_power_well_ops,
7112 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
7113 },
7114 {
7115 .name = "dpio-tx-b-23",
7116 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
7117 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS,
7118 .ops = &vlv_dpio_power_well_ops,
7119 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
7120 },
7121 {
7122 .name = "dpio-tx-c-01",
7123 .domains = VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
7124 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
7125 .ops = &vlv_dpio_power_well_ops,
7126 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
7127 },
7128 {
7129 .name = "dpio-tx-c-23",
7130 .domains = VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
7131 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
7132 .ops = &vlv_dpio_power_well_ops,
7133 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
7134 },
7135 {
7136 .name = "dpio-tx-d-01",
7137 .domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS |
7138 CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS,
7139 .ops = &vlv_dpio_power_well_ops,
7140 .data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_01,
7141 },
7142 {
7143 .name = "dpio-tx-d-23",
7144 .domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS |
7145 CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS,
7146 .ops = &vlv_dpio_power_well_ops,
7147 .data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_23,
7148 },
7149 #endif
7150 };
7151
7152 static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv,
7153 enum punit_power_well power_well_id)
7154 {
7155 struct i915_power_domains *power_domains = &dev_priv->power_domains;
7156 struct i915_power_well *power_well;
7157 int i;
7158
7159 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
7160 if (power_well->data == power_well_id)
7161 return power_well;
7162 }
7163
7164 return NULL;
7165 }
7166
7167 #define set_power_wells(power_domains, __power_wells) ({ \
7168 (power_domains)->power_wells = (__power_wells); \
7169 (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \
7170 })
7171
7172 int intel_power_domains_init(struct drm_i915_private *dev_priv)
7173 {
7174 struct i915_power_domains *power_domains = &dev_priv->power_domains;
7175
7176 mutex_init(&power_domains->lock);
7177
7178 /*
7179 * The enabling order will be from lower to higher indexed wells,
7180 * the disabling order is reversed.
7181 */
7182 if (IS_HASWELL(dev_priv->dev)) {
7183 set_power_wells(power_domains, hsw_power_wells);
7184 hsw_pwr = power_domains;
7185 } else if (IS_BROADWELL(dev_priv->dev)) {
7186 set_power_wells(power_domains, bdw_power_wells);
7187 hsw_pwr = power_domains;
7188 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
7189 set_power_wells(power_domains, chv_power_wells);
7190 } else if (IS_VALLEYVIEW(dev_priv->dev)) {
7191 set_power_wells(power_domains, vlv_power_wells);
7192 } else {
7193 set_power_wells(power_domains, i9xx_always_on_power_well);
7194 }
7195
7196 return 0;
7197 }
7198
7199 void intel_power_domains_remove(struct drm_i915_private *dev_priv)
7200 {
7201 hsw_pwr = NULL;
7202 }
7203
7204 static void intel_power_domains_resume(struct drm_i915_private *dev_priv)
7205 {
7206 struct i915_power_domains *power_domains = &dev_priv->power_domains;
7207 struct i915_power_well *power_well;
7208 int i;
7209
7210 mutex_lock(&power_domains->lock);
7211 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
7212 power_well->ops->sync_hw(dev_priv, power_well);
7213 power_well->hw_enabled = power_well->ops->is_enabled(dev_priv,
7214 power_well);
7215 }
7216 mutex_unlock(&power_domains->lock);
7217 }
7218
7219 static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
7220 {
7221 struct i915_power_well *cmn =
7222 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
7223 struct i915_power_well *disp2d =
7224 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D);
7225
7226 /* nothing to do if common lane is already off */
7227 if (!cmn->ops->is_enabled(dev_priv, cmn))
7228 return;
7229
7230 /* If the display might be already active skip this */
7231 if (disp2d->ops->is_enabled(dev_priv, disp2d) &&
7232 I915_READ(DPIO_CTL) & DPIO_CMNRST)
7233 return;
7234
7235 DRM_DEBUG_KMS("toggling display PHY side reset\n");
7236
7237 /* cmnlane needs DPLL registers */
7238 disp2d->ops->enable(dev_priv, disp2d);
7239
7240 /*
7241 * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
7242 * Need to assert and de-assert PHY SB reset by gating the
7243 * common lane power, then un-gating it.
7244 * Simply ungating isn't enough to reset the PHY enough to get
7245 * ports and lanes running.
7246 */
7247 cmn->ops->disable(dev_priv, cmn);
7248 }
7249
7250 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv)
7251 {
7252 struct drm_device *dev = dev_priv->dev;
7253 struct i915_power_domains *power_domains = &dev_priv->power_domains;
7254
7255 power_domains->initializing = true;
7256
7257 if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
7258 mutex_lock(&power_domains->lock);
7259 vlv_cmnlane_wa(dev_priv);
7260 mutex_unlock(&power_domains->lock);
7261 }
7262
7263 /* For now, we need the power well to be always enabled. */
7264 intel_display_set_init_power(dev_priv, true);
7265 intel_power_domains_resume(dev_priv);
7266 power_domains->initializing = false;
7267 }
7268
7269 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)
7270 {
7271 intel_runtime_pm_get(dev_priv);
7272 }
7273
7274 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)
7275 {
7276 intel_runtime_pm_put(dev_priv);
7277 }
7278
7279 void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
7280 {
7281 struct drm_device *dev = dev_priv->dev;
7282 struct device *device = &dev->pdev->dev;
7283
7284 if (!HAS_RUNTIME_PM(dev))
7285 return;
7286
7287 pm_runtime_get_sync(device);
7288 WARN(dev_priv->pm.suspended, "Device still suspended.\n");
7289 }
7290
7291 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv)
7292 {
7293 struct drm_device *dev = dev_priv->dev;
7294 struct device *device = &dev->pdev->dev;
7295
7296 if (!HAS_RUNTIME_PM(dev))
7297 return;
7298
7299 WARN(dev_priv->pm.suspended, "Getting nosync-ref while suspended.\n");
7300 pm_runtime_get_noresume(device);
7301 }
7302
7303 void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
7304 {
7305 struct drm_device *dev = dev_priv->dev;
7306 struct device *device = &dev->pdev->dev;
7307
7308 if (!HAS_RUNTIME_PM(dev))
7309 return;
7310
7311 pm_runtime_mark_last_busy(device);
7312 pm_runtime_put_autosuspend(device);
7313 }
7314
7315 void intel_init_runtime_pm(struct drm_i915_private *dev_priv)
7316 {
7317 struct drm_device *dev = dev_priv->dev;
7318 struct device *device = &dev->pdev->dev;
7319
7320 if (!HAS_RUNTIME_PM(dev))
7321 return;
7322
7323 pm_runtime_set_active(device);
7324
7325 /*
7326 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
7327 * requirement.
7328 */
7329 if (!intel_enable_rc6(dev)) {
7330 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
7331 return;
7332 }
7333
7334 pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
7335 pm_runtime_mark_last_busy(device);
7336 pm_runtime_use_autosuspend(device);
7337
7338 pm_runtime_put_autosuspend(device);
7339 }
7340
7341 void intel_fini_runtime_pm(struct drm_i915_private *dev_priv)
7342 {
7343 struct drm_device *dev = dev_priv->dev;
7344 struct device *device = &dev->pdev->dev;
7345
7346 if (!HAS_RUNTIME_PM(dev))
7347 return;
7348
7349 if (!intel_enable_rc6(dev))
7350 return;
7351
7352 /* Make sure we're not suspended first. */
7353 pm_runtime_get_sync(device);
7354 pm_runtime_disable(device);
7355 }
7356
7357 /* Set up chip specific power management-related functions */
7358 void intel_init_pm(struct drm_device *dev)
7359 {
7360 struct drm_i915_private *dev_priv = dev->dev_private;
7361
7362 if (HAS_FBC(dev)) {
7363 if (INTEL_INFO(dev)->gen >= 7) {
7364 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
7365 dev_priv->display.enable_fbc = gen7_enable_fbc;
7366 dev_priv->display.disable_fbc = ironlake_disable_fbc;
7367 } else if (INTEL_INFO(dev)->gen >= 5) {
7368 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
7369 dev_priv->display.enable_fbc = ironlake_enable_fbc;
7370 dev_priv->display.disable_fbc = ironlake_disable_fbc;
7371 } else if (IS_GM45(dev)) {
7372 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
7373 dev_priv->display.enable_fbc = g4x_enable_fbc;
7374 dev_priv->display.disable_fbc = g4x_disable_fbc;
7375 } else {
7376 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
7377 dev_priv->display.enable_fbc = i8xx_enable_fbc;
7378 dev_priv->display.disable_fbc = i8xx_disable_fbc;
7379
7380 /* This value was pulled out of someone's hat */
7381 I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);
7382 }
7383 }
7384
7385 /* For cxsr */
7386 if (IS_PINEVIEW(dev))
7387 i915_pineview_get_mem_freq(dev);
7388 else if (IS_GEN5(dev))
7389 i915_ironlake_get_mem_freq(dev);
7390
7391 /* For FIFO watermark updates */
7392 if (HAS_PCH_SPLIT(dev)) {
7393 ilk_setup_wm_latency(dev);
7394
7395 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
7396 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7397 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7398 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
7399 dev_priv->display.update_wm = ilk_update_wm;
7400 dev_priv->display.update_sprite_wm = ilk_update_sprite_wm;
7401 } else {
7402 DRM_DEBUG_KMS("Failed to read display plane latency. "
7403 "Disable CxSR\n");
7404 }
7405
7406 if (IS_GEN5(dev))
7407 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7408 else if (IS_GEN6(dev))
7409 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7410 else if (IS_IVYBRIDGE(dev))
7411 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7412 else if (IS_HASWELL(dev))
7413 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7414 else if (INTEL_INFO(dev)->gen == 8)
7415 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7416 else if (INTEL_INFO(dev)->gen == 9)
7417 dev_priv->display.init_clock_gating = gen9_init_clock_gating;
7418 } else if (IS_CHERRYVIEW(dev)) {
7419 dev_priv->display.update_wm = cherryview_update_wm;
7420 dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;
7421 dev_priv->display.init_clock_gating =
7422 cherryview_init_clock_gating;
7423 } else if (IS_VALLEYVIEW(dev)) {
7424 dev_priv->display.update_wm = valleyview_update_wm;
7425 dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;
7426 dev_priv->display.init_clock_gating =
7427 valleyview_init_clock_gating;
7428 } else if (IS_PINEVIEW(dev)) {
7429 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7430 dev_priv->is_ddr3,
7431 dev_priv->fsb_freq,
7432 dev_priv->mem_freq)) {
7433 DRM_INFO("failed to find known CxSR latency "
7434 "(found ddr%s fsb freq %d, mem freq %d), "
7435 "disabling CxSR\n",
7436 (dev_priv->is_ddr3 == 1) ? "3" : "2",
7437 dev_priv->fsb_freq, dev_priv->mem_freq);
7438 /* Disable CxSR and never update its watermark again */
7439 intel_set_memory_cxsr(dev_priv, false);
7440 dev_priv->display.update_wm = NULL;
7441 } else
7442 dev_priv->display.update_wm = pineview_update_wm;
7443 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7444 } else if (IS_G4X(dev)) {
7445 dev_priv->display.update_wm = g4x_update_wm;
7446 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7447 } else if (IS_GEN4(dev)) {
7448 dev_priv->display.update_wm = i965_update_wm;
7449 if (IS_CRESTLINE(dev))
7450 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7451 else if (IS_BROADWATER(dev))
7452 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7453 } else if (IS_GEN3(dev)) {
7454 dev_priv->display.update_wm = i9xx_update_wm;
7455 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7456 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7457 } else if (IS_GEN2(dev)) {
7458 if (INTEL_INFO(dev)->num_pipes == 1) {
7459 dev_priv->display.update_wm = i845_update_wm;
7460 dev_priv->display.get_fifo_size = i845_get_fifo_size;
7461 } else {
7462 dev_priv->display.update_wm = i9xx_update_wm;
7463 dev_priv->display.get_fifo_size = i830_get_fifo_size;
7464 }
7465
7466 if (IS_I85X(dev) || IS_I865G(dev))
7467 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7468 else
7469 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7470 } else {
7471 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
7472 }
7473 }
7474
7475 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
7476 {
7477 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7478
7479 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7480 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7481 return -EAGAIN;
7482 }
7483
7484 I915_WRITE(GEN6_PCODE_DATA, *val);
7485 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7486
7487 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7488 500)) {
7489 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7490 return -ETIMEDOUT;
7491 }
7492
7493 *val = I915_READ(GEN6_PCODE_DATA);
7494 I915_WRITE(GEN6_PCODE_DATA, 0);
7495
7496 return 0;
7497 }
7498
7499 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
7500 {
7501 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7502
7503 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7504 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7505 return -EAGAIN;
7506 }
7507
7508 I915_WRITE(GEN6_PCODE_DATA, val);
7509 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7510
7511 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7512 500)) {
7513 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7514 return -ETIMEDOUT;
7515 }
7516
7517 I915_WRITE(GEN6_PCODE_DATA, 0);
7518
7519 return 0;
7520 }
7521
7522 static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7523 {
7524 int div;
7525
7526 /* 4 x czclk */
7527 switch (dev_priv->mem_freq) {
7528 case 800:
7529 div = 10;
7530 break;
7531 case 1066:
7532 div = 12;
7533 break;
7534 case 1333:
7535 div = 16;
7536 break;
7537 default:
7538 return -1;
7539 }
7540
7541 return DIV_ROUND_CLOSEST(dev_priv->mem_freq * (val + 6 - 0xbd), 4 * div);
7542 }
7543
7544 static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
7545 {
7546 int mul;
7547
7548 /* 4 x czclk */
7549 switch (dev_priv->mem_freq) {
7550 case 800:
7551 mul = 10;
7552 break;
7553 case 1066:
7554 mul = 12;
7555 break;
7556 case 1333:
7557 mul = 16;
7558 break;
7559 default:
7560 return -1;
7561 }
7562
7563 return DIV_ROUND_CLOSEST(4 * mul * val, dev_priv->mem_freq) + 0xbd - 6;
7564 }
7565
7566 static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
7567 {
7568 int div, freq;
7569
7570 switch (dev_priv->rps.cz_freq) {
7571 case 200:
7572 div = 5;
7573 break;
7574 case 267:
7575 div = 6;
7576 break;
7577 case 320:
7578 case 333:
7579 case 400:
7580 div = 8;
7581 break;
7582 default:
7583 return -1;
7584 }
7585
7586 freq = (DIV_ROUND_CLOSEST((dev_priv->rps.cz_freq * val), 2 * div) / 2);
7587
7588 return freq;
7589 }
7590
7591 static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
7592 {
7593 int mul, opcode;
7594
7595 switch (dev_priv->rps.cz_freq) {
7596 case 200:
7597 mul = 5;
7598 break;
7599 case 267:
7600 mul = 6;
7601 break;
7602 case 320:
7603 case 333:
7604 case 400:
7605 mul = 8;
7606 break;
7607 default:
7608 return -1;
7609 }
7610
7611 /* CHV needs even values */
7612 opcode = (DIV_ROUND_CLOSEST((val * 2 * mul), dev_priv->rps.cz_freq) * 2);
7613
7614 return opcode;
7615 }
7616
7617 int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val)
7618 {
7619 int ret = -1;
7620
7621 if (IS_CHERRYVIEW(dev_priv->dev))
7622 ret = chv_gpu_freq(dev_priv, val);
7623 else if (IS_VALLEYVIEW(dev_priv->dev))
7624 ret = byt_gpu_freq(dev_priv, val);
7625
7626 return ret;
7627 }
7628
7629 int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val)
7630 {
7631 int ret = -1;
7632
7633 if (IS_CHERRYVIEW(dev_priv->dev))
7634 ret = chv_freq_opcode(dev_priv, val);
7635 else if (IS_VALLEYVIEW(dev_priv->dev))
7636 ret = byt_freq_opcode(dev_priv, val);
7637
7638 return ret;
7639 }
7640
7641 void intel_pm_setup(struct drm_device *dev)
7642 {
7643 struct drm_i915_private *dev_priv = dev->dev_private;
7644
7645 mutex_init(&dev_priv->rps.hw_lock);
7646
7647 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
7648 intel_gen6_powersave_work);
7649
7650 dev_priv->pm.suspended = false;
7651 dev_priv->pm._irqs_disabled = false;
7652 }
Linux kernel - Deliverables
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