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drm/i915: add SW tracking to FBC enabling
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_pm.c
1 /*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28 #include <linux/cpufreq.h>
29 #include "i915_drv.h"
30 #include "intel_drv.h"
31 #include "../../../platform/x86/intel_ips.h"
32 #include <linux/module.h>
33 #include <linux/vgaarb.h>
34 #include <drm/i915_powerwell.h>
35 #include <linux/pm_runtime.h>
36
37 /**
38 * RC6 is a special power stage which allows the GPU to enter an very
39 * low-voltage mode when idle, using down to 0V while at this stage. This
40 * stage is entered automatically when the GPU is idle when RC6 support is
41 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
42 *
43 * There are different RC6 modes available in Intel GPU, which differentiate
44 * among each other with the latency required to enter and leave RC6 and
45 * voltage consumed by the GPU in different states.
46 *
47 * The combination of the following flags define which states GPU is allowed
48 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
49 * RC6pp is deepest RC6. Their support by hardware varies according to the
50 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
51 * which brings the most power savings; deeper states save more power, but
52 * require higher latency to switch to and wake up.
53 */
54 #define INTEL_RC6_ENABLE (1<<0)
55 #define INTEL_RC6p_ENABLE (1<<1)
56 #define INTEL_RC6pp_ENABLE (1<<2)
57
58 /* FBC, or Frame Buffer Compression, is a technique employed to compress the
59 * framebuffer contents in-memory, aiming at reducing the required bandwidth
60 * during in-memory transfers and, therefore, reduce the power packet.
61 *
62 * The benefits of FBC are mostly visible with solid backgrounds and
63 * variation-less patterns.
64 *
65 * FBC-related functionality can be enabled by the means of the
66 * i915.i915_enable_fbc parameter
67 */
68
69 static void i8xx_disable_fbc(struct drm_device *dev)
70 {
71 struct drm_i915_private *dev_priv = dev->dev_private;
72 u32 fbc_ctl;
73
74 dev_priv->fbc.enabled = false;
75
76 /* Disable compression */
77 fbc_ctl = I915_READ(FBC_CONTROL);
78 if ((fbc_ctl & FBC_CTL_EN) == 0)
79 return;
80
81 fbc_ctl &= ~FBC_CTL_EN;
82 I915_WRITE(FBC_CONTROL, fbc_ctl);
83
84 /* Wait for compressing bit to clear */
85 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
86 DRM_DEBUG_KMS("FBC idle timed out\n");
87 return;
88 }
89
90 DRM_DEBUG_KMS("disabled FBC\n");
91 }
92
93 static void i8xx_enable_fbc(struct drm_crtc *crtc)
94 {
95 struct drm_device *dev = crtc->dev;
96 struct drm_i915_private *dev_priv = dev->dev_private;
97 struct drm_framebuffer *fb = crtc->primary->fb;
98 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
99 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
100 int cfb_pitch;
101 int i;
102 u32 fbc_ctl;
103
104 dev_priv->fbc.enabled = true;
105
106 cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
107 if (fb->pitches[0] < cfb_pitch)
108 cfb_pitch = fb->pitches[0];
109
110 /* FBC_CTL wants 32B or 64B units */
111 if (IS_GEN2(dev))
112 cfb_pitch = (cfb_pitch / 32) - 1;
113 else
114 cfb_pitch = (cfb_pitch / 64) - 1;
115
116 /* Clear old tags */
117 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
118 I915_WRITE(FBC_TAG + (i * 4), 0);
119
120 if (IS_GEN4(dev)) {
121 u32 fbc_ctl2;
122
123 /* Set it up... */
124 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
125 fbc_ctl2 |= FBC_CTL_PLANE(intel_crtc->plane);
126 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
127 I915_WRITE(FBC_FENCE_OFF, crtc->y);
128 }
129
130 /* enable it... */
131 fbc_ctl = I915_READ(FBC_CONTROL);
132 fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT;
133 fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
134 if (IS_I945GM(dev))
135 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
136 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
137 fbc_ctl |= obj->fence_reg;
138 I915_WRITE(FBC_CONTROL, fbc_ctl);
139
140 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c\n",
141 cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
142 }
143
144 static bool i8xx_fbc_enabled(struct drm_device *dev)
145 {
146 struct drm_i915_private *dev_priv = dev->dev_private;
147
148 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
149 }
150
151 static void g4x_enable_fbc(struct drm_crtc *crtc)
152 {
153 struct drm_device *dev = crtc->dev;
154 struct drm_i915_private *dev_priv = dev->dev_private;
155 struct drm_framebuffer *fb = crtc->primary->fb;
156 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
157 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
158 u32 dpfc_ctl;
159
160 dev_priv->fbc.enabled = true;
161
162 dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane) | DPFC_SR_EN;
163 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
164 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
165 else
166 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
167 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
168
169 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
170
171 /* enable it... */
172 I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
173
174 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
175 }
176
177 static void g4x_disable_fbc(struct drm_device *dev)
178 {
179 struct drm_i915_private *dev_priv = dev->dev_private;
180 u32 dpfc_ctl;
181
182 dev_priv->fbc.enabled = false;
183
184 /* Disable compression */
185 dpfc_ctl = I915_READ(DPFC_CONTROL);
186 if (dpfc_ctl & DPFC_CTL_EN) {
187 dpfc_ctl &= ~DPFC_CTL_EN;
188 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
189
190 DRM_DEBUG_KMS("disabled FBC\n");
191 }
192 }
193
194 static bool g4x_fbc_enabled(struct drm_device *dev)
195 {
196 struct drm_i915_private *dev_priv = dev->dev_private;
197
198 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
199 }
200
201 static void sandybridge_blit_fbc_update(struct drm_device *dev)
202 {
203 struct drm_i915_private *dev_priv = dev->dev_private;
204 u32 blt_ecoskpd;
205
206 /* Make sure blitter notifies FBC of writes */
207
208 /* Blitter is part of Media powerwell on VLV. No impact of
209 * his param in other platforms for now */
210 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_MEDIA);
211
212 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
213 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
214 GEN6_BLITTER_LOCK_SHIFT;
215 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
216 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
217 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
218 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
219 GEN6_BLITTER_LOCK_SHIFT);
220 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
221 POSTING_READ(GEN6_BLITTER_ECOSKPD);
222
223 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_MEDIA);
224 }
225
226 static void ironlake_enable_fbc(struct drm_crtc *crtc)
227 {
228 struct drm_device *dev = crtc->dev;
229 struct drm_i915_private *dev_priv = dev->dev_private;
230 struct drm_framebuffer *fb = crtc->primary->fb;
231 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
232 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
233 u32 dpfc_ctl;
234
235 dev_priv->fbc.enabled = true;
236
237 dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane);
238 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
239 dev_priv->fbc.threshold++;
240
241 switch (dev_priv->fbc.threshold) {
242 case 4:
243 case 3:
244 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
245 break;
246 case 2:
247 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
248 break;
249 case 1:
250 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
251 break;
252 }
253 dpfc_ctl |= DPFC_CTL_FENCE_EN;
254 if (IS_GEN5(dev))
255 dpfc_ctl |= obj->fence_reg;
256
257 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
258 I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
259 /* enable it... */
260 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
261
262 if (IS_GEN6(dev)) {
263 I915_WRITE(SNB_DPFC_CTL_SA,
264 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
265 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
266 sandybridge_blit_fbc_update(dev);
267 }
268
269 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
270 }
271
272 static void ironlake_disable_fbc(struct drm_device *dev)
273 {
274 struct drm_i915_private *dev_priv = dev->dev_private;
275 u32 dpfc_ctl;
276
277 dev_priv->fbc.enabled = false;
278
279 /* Disable compression */
280 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
281 if (dpfc_ctl & DPFC_CTL_EN) {
282 dpfc_ctl &= ~DPFC_CTL_EN;
283 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
284
285 DRM_DEBUG_KMS("disabled FBC\n");
286 }
287 }
288
289 static bool ironlake_fbc_enabled(struct drm_device *dev)
290 {
291 struct drm_i915_private *dev_priv = dev->dev_private;
292
293 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
294 }
295
296 static void gen7_enable_fbc(struct drm_crtc *crtc)
297 {
298 struct drm_device *dev = crtc->dev;
299 struct drm_i915_private *dev_priv = dev->dev_private;
300 struct drm_framebuffer *fb = crtc->primary->fb;
301 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
302 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
303 u32 dpfc_ctl;
304
305 dev_priv->fbc.enabled = true;
306
307 dpfc_ctl = IVB_DPFC_CTL_PLANE(intel_crtc->plane);
308 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
309 dev_priv->fbc.threshold++;
310
311 switch (dev_priv->fbc.threshold) {
312 case 4:
313 case 3:
314 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
315 break;
316 case 2:
317 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
318 break;
319 case 1:
320 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
321 break;
322 }
323
324 dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
325
326 if (dev_priv->fbc.false_color)
327 dpfc_ctl |= FBC_CTL_FALSE_COLOR;
328
329 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
330
331 if (IS_IVYBRIDGE(dev)) {
332 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
333 I915_WRITE(ILK_DISPLAY_CHICKEN1,
334 I915_READ(ILK_DISPLAY_CHICKEN1) |
335 ILK_FBCQ_DIS);
336 } else {
337 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
338 I915_WRITE(CHICKEN_PIPESL_1(intel_crtc->pipe),
339 I915_READ(CHICKEN_PIPESL_1(intel_crtc->pipe)) |
340 HSW_FBCQ_DIS);
341 }
342
343 I915_WRITE(SNB_DPFC_CTL_SA,
344 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
345 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
346
347 sandybridge_blit_fbc_update(dev);
348
349 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
350 }
351
352 bool intel_fbc_enabled(struct drm_device *dev)
353 {
354 struct drm_i915_private *dev_priv = dev->dev_private;
355
356 return dev_priv->fbc.enabled;
357 }
358
359 void gen8_fbc_sw_flush(struct drm_device *dev, u32 value)
360 {
361 struct drm_i915_private *dev_priv = dev->dev_private;
362
363 if (!IS_GEN8(dev))
364 return;
365
366 if (!intel_fbc_enabled(dev))
367 return;
368
369 I915_WRITE(MSG_FBC_REND_STATE, value);
370 }
371
372 static void intel_fbc_work_fn(struct work_struct *__work)
373 {
374 struct intel_fbc_work *work =
375 container_of(to_delayed_work(__work),
376 struct intel_fbc_work, work);
377 struct drm_device *dev = work->crtc->dev;
378 struct drm_i915_private *dev_priv = dev->dev_private;
379
380 mutex_lock(&dev->struct_mutex);
381 if (work == dev_priv->fbc.fbc_work) {
382 /* Double check that we haven't switched fb without cancelling
383 * the prior work.
384 */
385 if (work->crtc->primary->fb == work->fb) {
386 dev_priv->display.enable_fbc(work->crtc);
387
388 dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;
389 dev_priv->fbc.fb_id = work->crtc->primary->fb->base.id;
390 dev_priv->fbc.y = work->crtc->y;
391 }
392
393 dev_priv->fbc.fbc_work = NULL;
394 }
395 mutex_unlock(&dev->struct_mutex);
396
397 kfree(work);
398 }
399
400 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
401 {
402 if (dev_priv->fbc.fbc_work == NULL)
403 return;
404
405 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
406
407 /* Synchronisation is provided by struct_mutex and checking of
408 * dev_priv->fbc.fbc_work, so we can perform the cancellation
409 * entirely asynchronously.
410 */
411 if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
412 /* tasklet was killed before being run, clean up */
413 kfree(dev_priv->fbc.fbc_work);
414
415 /* Mark the work as no longer wanted so that if it does
416 * wake-up (because the work was already running and waiting
417 * for our mutex), it will discover that is no longer
418 * necessary to run.
419 */
420 dev_priv->fbc.fbc_work = NULL;
421 }
422
423 static void intel_enable_fbc(struct drm_crtc *crtc)
424 {
425 struct intel_fbc_work *work;
426 struct drm_device *dev = crtc->dev;
427 struct drm_i915_private *dev_priv = dev->dev_private;
428
429 if (!dev_priv->display.enable_fbc)
430 return;
431
432 intel_cancel_fbc_work(dev_priv);
433
434 work = kzalloc(sizeof(*work), GFP_KERNEL);
435 if (work == NULL) {
436 DRM_ERROR("Failed to allocate FBC work structure\n");
437 dev_priv->display.enable_fbc(crtc);
438 return;
439 }
440
441 work->crtc = crtc;
442 work->fb = crtc->primary->fb;
443 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
444
445 dev_priv->fbc.fbc_work = work;
446
447 /* Delay the actual enabling to let pageflipping cease and the
448 * display to settle before starting the compression. Note that
449 * this delay also serves a second purpose: it allows for a
450 * vblank to pass after disabling the FBC before we attempt
451 * to modify the control registers.
452 *
453 * A more complicated solution would involve tracking vblanks
454 * following the termination of the page-flipping sequence
455 * and indeed performing the enable as a co-routine and not
456 * waiting synchronously upon the vblank.
457 *
458 * WaFbcWaitForVBlankBeforeEnable:ilk,snb
459 */
460 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
461 }
462
463 void intel_disable_fbc(struct drm_device *dev)
464 {
465 struct drm_i915_private *dev_priv = dev->dev_private;
466
467 intel_cancel_fbc_work(dev_priv);
468
469 if (!dev_priv->display.disable_fbc)
470 return;
471
472 dev_priv->display.disable_fbc(dev);
473 dev_priv->fbc.plane = -1;
474 }
475
476 static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
477 enum no_fbc_reason reason)
478 {
479 if (dev_priv->fbc.no_fbc_reason == reason)
480 return false;
481
482 dev_priv->fbc.no_fbc_reason = reason;
483 return true;
484 }
485
486 /**
487 * intel_update_fbc - enable/disable FBC as needed
488 * @dev: the drm_device
489 *
490 * Set up the framebuffer compression hardware at mode set time. We
491 * enable it if possible:
492 * - plane A only (on pre-965)
493 * - no pixel mulitply/line duplication
494 * - no alpha buffer discard
495 * - no dual wide
496 * - framebuffer <= max_hdisplay in width, max_vdisplay in height
497 *
498 * We can't assume that any compression will take place (worst case),
499 * so the compressed buffer has to be the same size as the uncompressed
500 * one. It also must reside (along with the line length buffer) in
501 * stolen memory.
502 *
503 * We need to enable/disable FBC on a global basis.
504 */
505 void intel_update_fbc(struct drm_device *dev)
506 {
507 struct drm_i915_private *dev_priv = dev->dev_private;
508 struct drm_crtc *crtc = NULL, *tmp_crtc;
509 struct intel_crtc *intel_crtc;
510 struct drm_framebuffer *fb;
511 struct drm_i915_gem_object *obj;
512 const struct drm_display_mode *adjusted_mode;
513 unsigned int max_width, max_height;
514
515 if (!HAS_FBC(dev)) {
516 set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED);
517 return;
518 }
519
520 if (!i915.powersave) {
521 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
522 DRM_DEBUG_KMS("fbc disabled per module param\n");
523 return;
524 }
525
526 /*
527 * If FBC is already on, we just have to verify that we can
528 * keep it that way...
529 * Need to disable if:
530 * - more than one pipe is active
531 * - changing FBC params (stride, fence, mode)
532 * - new fb is too large to fit in compressed buffer
533 * - going to an unsupported config (interlace, pixel multiply, etc.)
534 */
535 for_each_crtc(dev, tmp_crtc) {
536 if (intel_crtc_active(tmp_crtc) &&
537 to_intel_crtc(tmp_crtc)->primary_enabled) {
538 if (crtc) {
539 if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
540 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
541 goto out_disable;
542 }
543 crtc = tmp_crtc;
544 }
545 }
546
547 if (!crtc || crtc->primary->fb == NULL) {
548 if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
549 DRM_DEBUG_KMS("no output, disabling\n");
550 goto out_disable;
551 }
552
553 intel_crtc = to_intel_crtc(crtc);
554 fb = crtc->primary->fb;
555 obj = intel_fb_obj(fb);
556 adjusted_mode = &intel_crtc->config.adjusted_mode;
557
558 if (i915.enable_fbc < 0) {
559 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
560 DRM_DEBUG_KMS("disabled per chip default\n");
561 goto out_disable;
562 }
563 if (!i915.enable_fbc) {
564 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
565 DRM_DEBUG_KMS("fbc disabled per module param\n");
566 goto out_disable;
567 }
568 if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ||
569 (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
570 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
571 DRM_DEBUG_KMS("mode incompatible with compression, "
572 "disabling\n");
573 goto out_disable;
574 }
575
576 if (INTEL_INFO(dev)->gen >= 8 || IS_HASWELL(dev)) {
577 max_width = 4096;
578 max_height = 4096;
579 } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
580 max_width = 4096;
581 max_height = 2048;
582 } else {
583 max_width = 2048;
584 max_height = 1536;
585 }
586 if (intel_crtc->config.pipe_src_w > max_width ||
587 intel_crtc->config.pipe_src_h > max_height) {
588 if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
589 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
590 goto out_disable;
591 }
592 if ((INTEL_INFO(dev)->gen < 4 || HAS_DDI(dev)) &&
593 intel_crtc->plane != PLANE_A) {
594 if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
595 DRM_DEBUG_KMS("plane not A, disabling compression\n");
596 goto out_disable;
597 }
598
599 /* The use of a CPU fence is mandatory in order to detect writes
600 * by the CPU to the scanout and trigger updates to the FBC.
601 */
602 if (obj->tiling_mode != I915_TILING_X ||
603 obj->fence_reg == I915_FENCE_REG_NONE) {
604 if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED))
605 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
606 goto out_disable;
607 }
608 if (INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
609 to_intel_plane(crtc->primary)->rotation != BIT(DRM_ROTATE_0)) {
610 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
611 DRM_DEBUG_KMS("Rotation unsupported, disabling\n");
612 goto out_disable;
613 }
614
615 /* If the kernel debugger is active, always disable compression */
616 if (in_dbg_master())
617 goto out_disable;
618
619 if (i915_gem_stolen_setup_compression(dev, obj->base.size,
620 drm_format_plane_cpp(fb->pixel_format, 0))) {
621 if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL))
622 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
623 goto out_disable;
624 }
625
626 /* If the scanout has not changed, don't modify the FBC settings.
627 * Note that we make the fundamental assumption that the fb->obj
628 * cannot be unpinned (and have its GTT offset and fence revoked)
629 * without first being decoupled from the scanout and FBC disabled.
630 */
631 if (dev_priv->fbc.plane == intel_crtc->plane &&
632 dev_priv->fbc.fb_id == fb->base.id &&
633 dev_priv->fbc.y == crtc->y)
634 return;
635
636 if (intel_fbc_enabled(dev)) {
637 /* We update FBC along two paths, after changing fb/crtc
638 * configuration (modeswitching) and after page-flipping
639 * finishes. For the latter, we know that not only did
640 * we disable the FBC at the start of the page-flip
641 * sequence, but also more than one vblank has passed.
642 *
643 * For the former case of modeswitching, it is possible
644 * to switch between two FBC valid configurations
645 * instantaneously so we do need to disable the FBC
646 * before we can modify its control registers. We also
647 * have to wait for the next vblank for that to take
648 * effect. However, since we delay enabling FBC we can
649 * assume that a vblank has passed since disabling and
650 * that we can safely alter the registers in the deferred
651 * callback.
652 *
653 * In the scenario that we go from a valid to invalid
654 * and then back to valid FBC configuration we have
655 * no strict enforcement that a vblank occurred since
656 * disabling the FBC. However, along all current pipe
657 * disabling paths we do need to wait for a vblank at
658 * some point. And we wait before enabling FBC anyway.
659 */
660 DRM_DEBUG_KMS("disabling active FBC for update\n");
661 intel_disable_fbc(dev);
662 }
663
664 intel_enable_fbc(crtc);
665 dev_priv->fbc.no_fbc_reason = FBC_OK;
666 return;
667
668 out_disable:
669 /* Multiple disables should be harmless */
670 if (intel_fbc_enabled(dev)) {
671 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
672 intel_disable_fbc(dev);
673 }
674 i915_gem_stolen_cleanup_compression(dev);
675 }
676
677 static void i915_pineview_get_mem_freq(struct drm_device *dev)
678 {
679 struct drm_i915_private *dev_priv = dev->dev_private;
680 u32 tmp;
681
682 tmp = I915_READ(CLKCFG);
683
684 switch (tmp & CLKCFG_FSB_MASK) {
685 case CLKCFG_FSB_533:
686 dev_priv->fsb_freq = 533; /* 133*4 */
687 break;
688 case CLKCFG_FSB_800:
689 dev_priv->fsb_freq = 800; /* 200*4 */
690 break;
691 case CLKCFG_FSB_667:
692 dev_priv->fsb_freq = 667; /* 167*4 */
693 break;
694 case CLKCFG_FSB_400:
695 dev_priv->fsb_freq = 400; /* 100*4 */
696 break;
697 }
698
699 switch (tmp & CLKCFG_MEM_MASK) {
700 case CLKCFG_MEM_533:
701 dev_priv->mem_freq = 533;
702 break;
703 case CLKCFG_MEM_667:
704 dev_priv->mem_freq = 667;
705 break;
706 case CLKCFG_MEM_800:
707 dev_priv->mem_freq = 800;
708 break;
709 }
710
711 /* detect pineview DDR3 setting */
712 tmp = I915_READ(CSHRDDR3CTL);
713 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
714 }
715
716 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
717 {
718 struct drm_i915_private *dev_priv = dev->dev_private;
719 u16 ddrpll, csipll;
720
721 ddrpll = I915_READ16(DDRMPLL1);
722 csipll = I915_READ16(CSIPLL0);
723
724 switch (ddrpll & 0xff) {
725 case 0xc:
726 dev_priv->mem_freq = 800;
727 break;
728 case 0x10:
729 dev_priv->mem_freq = 1066;
730 break;
731 case 0x14:
732 dev_priv->mem_freq = 1333;
733 break;
734 case 0x18:
735 dev_priv->mem_freq = 1600;
736 break;
737 default:
738 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
739 ddrpll & 0xff);
740 dev_priv->mem_freq = 0;
741 break;
742 }
743
744 dev_priv->ips.r_t = dev_priv->mem_freq;
745
746 switch (csipll & 0x3ff) {
747 case 0x00c:
748 dev_priv->fsb_freq = 3200;
749 break;
750 case 0x00e:
751 dev_priv->fsb_freq = 3733;
752 break;
753 case 0x010:
754 dev_priv->fsb_freq = 4266;
755 break;
756 case 0x012:
757 dev_priv->fsb_freq = 4800;
758 break;
759 case 0x014:
760 dev_priv->fsb_freq = 5333;
761 break;
762 case 0x016:
763 dev_priv->fsb_freq = 5866;
764 break;
765 case 0x018:
766 dev_priv->fsb_freq = 6400;
767 break;
768 default:
769 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
770 csipll & 0x3ff);
771 dev_priv->fsb_freq = 0;
772 break;
773 }
774
775 if (dev_priv->fsb_freq == 3200) {
776 dev_priv->ips.c_m = 0;
777 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
778 dev_priv->ips.c_m = 1;
779 } else {
780 dev_priv->ips.c_m = 2;
781 }
782 }
783
784 static const struct cxsr_latency cxsr_latency_table[] = {
785 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
786 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
787 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
788 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
789 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
790
791 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
792 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
793 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
794 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
795 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
796
797 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
798 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
799 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
800 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
801 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
802
803 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
804 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
805 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
806 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
807 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
808
809 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
810 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
811 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
812 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
813 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
814
815 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
816 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
817 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
818 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
819 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
820 };
821
822 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
823 int is_ddr3,
824 int fsb,
825 int mem)
826 {
827 const struct cxsr_latency *latency;
828 int i;
829
830 if (fsb == 0 || mem == 0)
831 return NULL;
832
833 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
834 latency = &cxsr_latency_table[i];
835 if (is_desktop == latency->is_desktop &&
836 is_ddr3 == latency->is_ddr3 &&
837 fsb == latency->fsb_freq && mem == latency->mem_freq)
838 return latency;
839 }
840
841 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
842
843 return NULL;
844 }
845
846 void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
847 {
848 struct drm_device *dev = dev_priv->dev;
849 u32 val;
850
851 if (IS_VALLEYVIEW(dev)) {
852 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
853 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
854 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
855 } else if (IS_PINEVIEW(dev)) {
856 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
857 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
858 I915_WRITE(DSPFW3, val);
859 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
860 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
861 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
862 I915_WRITE(FW_BLC_SELF, val);
863 } else if (IS_I915GM(dev)) {
864 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
865 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
866 I915_WRITE(INSTPM, val);
867 } else {
868 return;
869 }
870
871 DRM_DEBUG_KMS("memory self-refresh is %s\n",
872 enable ? "enabled" : "disabled");
873 }
874
875 /*
876 * Latency for FIFO fetches is dependent on several factors:
877 * - memory configuration (speed, channels)
878 * - chipset
879 * - current MCH state
880 * It can be fairly high in some situations, so here we assume a fairly
881 * pessimal value. It's a tradeoff between extra memory fetches (if we
882 * set this value too high, the FIFO will fetch frequently to stay full)
883 * and power consumption (set it too low to save power and we might see
884 * FIFO underruns and display "flicker").
885 *
886 * A value of 5us seems to be a good balance; safe for very low end
887 * platforms but not overly aggressive on lower latency configs.
888 */
889 static const int pessimal_latency_ns = 5000;
890
891 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
892 {
893 struct drm_i915_private *dev_priv = dev->dev_private;
894 uint32_t dsparb = I915_READ(DSPARB);
895 int size;
896
897 size = dsparb & 0x7f;
898 if (plane)
899 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
900
901 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
902 plane ? "B" : "A", size);
903
904 return size;
905 }
906
907 static int i830_get_fifo_size(struct drm_device *dev, int plane)
908 {
909 struct drm_i915_private *dev_priv = dev->dev_private;
910 uint32_t dsparb = I915_READ(DSPARB);
911 int size;
912
913 size = dsparb & 0x1ff;
914 if (plane)
915 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
916 size >>= 1; /* Convert to cachelines */
917
918 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
919 plane ? "B" : "A", size);
920
921 return size;
922 }
923
924 static int i845_get_fifo_size(struct drm_device *dev, int plane)
925 {
926 struct drm_i915_private *dev_priv = dev->dev_private;
927 uint32_t dsparb = I915_READ(DSPARB);
928 int size;
929
930 size = dsparb & 0x7f;
931 size >>= 2; /* Convert to cachelines */
932
933 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
934 plane ? "B" : "A",
935 size);
936
937 return size;
938 }
939
940 /* Pineview has different values for various configs */
941 static const struct intel_watermark_params pineview_display_wm = {
942 .fifo_size = PINEVIEW_DISPLAY_FIFO,
943 .max_wm = PINEVIEW_MAX_WM,
944 .default_wm = PINEVIEW_DFT_WM,
945 .guard_size = PINEVIEW_GUARD_WM,
946 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
947 };
948 static const struct intel_watermark_params pineview_display_hplloff_wm = {
949 .fifo_size = PINEVIEW_DISPLAY_FIFO,
950 .max_wm = PINEVIEW_MAX_WM,
951 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
952 .guard_size = PINEVIEW_GUARD_WM,
953 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
954 };
955 static const struct intel_watermark_params pineview_cursor_wm = {
956 .fifo_size = PINEVIEW_CURSOR_FIFO,
957 .max_wm = PINEVIEW_CURSOR_MAX_WM,
958 .default_wm = PINEVIEW_CURSOR_DFT_WM,
959 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
960 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
961 };
962 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
963 .fifo_size = PINEVIEW_CURSOR_FIFO,
964 .max_wm = PINEVIEW_CURSOR_MAX_WM,
965 .default_wm = PINEVIEW_CURSOR_DFT_WM,
966 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
967 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
968 };
969 static const struct intel_watermark_params g4x_wm_info = {
970 .fifo_size = G4X_FIFO_SIZE,
971 .max_wm = G4X_MAX_WM,
972 .default_wm = G4X_MAX_WM,
973 .guard_size = 2,
974 .cacheline_size = G4X_FIFO_LINE_SIZE,
975 };
976 static const struct intel_watermark_params g4x_cursor_wm_info = {
977 .fifo_size = I965_CURSOR_FIFO,
978 .max_wm = I965_CURSOR_MAX_WM,
979 .default_wm = I965_CURSOR_DFT_WM,
980 .guard_size = 2,
981 .cacheline_size = G4X_FIFO_LINE_SIZE,
982 };
983 static const struct intel_watermark_params valleyview_wm_info = {
984 .fifo_size = VALLEYVIEW_FIFO_SIZE,
985 .max_wm = VALLEYVIEW_MAX_WM,
986 .default_wm = VALLEYVIEW_MAX_WM,
987 .guard_size = 2,
988 .cacheline_size = G4X_FIFO_LINE_SIZE,
989 };
990 static const struct intel_watermark_params valleyview_cursor_wm_info = {
991 .fifo_size = I965_CURSOR_FIFO,
992 .max_wm = VALLEYVIEW_CURSOR_MAX_WM,
993 .default_wm = I965_CURSOR_DFT_WM,
994 .guard_size = 2,
995 .cacheline_size = G4X_FIFO_LINE_SIZE,
996 };
997 static const struct intel_watermark_params i965_cursor_wm_info = {
998 .fifo_size = I965_CURSOR_FIFO,
999 .max_wm = I965_CURSOR_MAX_WM,
1000 .default_wm = I965_CURSOR_DFT_WM,
1001 .guard_size = 2,
1002 .cacheline_size = I915_FIFO_LINE_SIZE,
1003 };
1004 static const struct intel_watermark_params i945_wm_info = {
1005 .fifo_size = I945_FIFO_SIZE,
1006 .max_wm = I915_MAX_WM,
1007 .default_wm = 1,
1008 .guard_size = 2,
1009 .cacheline_size = I915_FIFO_LINE_SIZE,
1010 };
1011 static const struct intel_watermark_params i915_wm_info = {
1012 .fifo_size = I915_FIFO_SIZE,
1013 .max_wm = I915_MAX_WM,
1014 .default_wm = 1,
1015 .guard_size = 2,
1016 .cacheline_size = I915_FIFO_LINE_SIZE,
1017 };
1018 static const struct intel_watermark_params i830_a_wm_info = {
1019 .fifo_size = I855GM_FIFO_SIZE,
1020 .max_wm = I915_MAX_WM,
1021 .default_wm = 1,
1022 .guard_size = 2,
1023 .cacheline_size = I830_FIFO_LINE_SIZE,
1024 };
1025 static const struct intel_watermark_params i830_bc_wm_info = {
1026 .fifo_size = I855GM_FIFO_SIZE,
1027 .max_wm = I915_MAX_WM/2,
1028 .default_wm = 1,
1029 .guard_size = 2,
1030 .cacheline_size = I830_FIFO_LINE_SIZE,
1031 };
1032 static const struct intel_watermark_params i845_wm_info = {
1033 .fifo_size = I830_FIFO_SIZE,
1034 .max_wm = I915_MAX_WM,
1035 .default_wm = 1,
1036 .guard_size = 2,
1037 .cacheline_size = I830_FIFO_LINE_SIZE,
1038 };
1039
1040 /**
1041 * intel_calculate_wm - calculate watermark level
1042 * @clock_in_khz: pixel clock
1043 * @wm: chip FIFO params
1044 * @pixel_size: display pixel size
1045 * @latency_ns: memory latency for the platform
1046 *
1047 * Calculate the watermark level (the level at which the display plane will
1048 * start fetching from memory again). Each chip has a different display
1049 * FIFO size and allocation, so the caller needs to figure that out and pass
1050 * in the correct intel_watermark_params structure.
1051 *
1052 * As the pixel clock runs, the FIFO will be drained at a rate that depends
1053 * on the pixel size. When it reaches the watermark level, it'll start
1054 * fetching FIFO line sized based chunks from memory until the FIFO fills
1055 * past the watermark point. If the FIFO drains completely, a FIFO underrun
1056 * will occur, and a display engine hang could result.
1057 */
1058 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
1059 const struct intel_watermark_params *wm,
1060 int fifo_size,
1061 int pixel_size,
1062 unsigned long latency_ns)
1063 {
1064 long entries_required, wm_size;
1065
1066 /*
1067 * Note: we need to make sure we don't overflow for various clock &
1068 * latency values.
1069 * clocks go from a few thousand to several hundred thousand.
1070 * latency is usually a few thousand
1071 */
1072 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
1073 1000;
1074 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
1075
1076 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
1077
1078 wm_size = fifo_size - (entries_required + wm->guard_size);
1079
1080 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
1081
1082 /* Don't promote wm_size to unsigned... */
1083 if (wm_size > (long)wm->max_wm)
1084 wm_size = wm->max_wm;
1085 if (wm_size <= 0)
1086 wm_size = wm->default_wm;
1087
1088 /*
1089 * Bspec seems to indicate that the value shouldn't be lower than
1090 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
1091 * Lets go for 8 which is the burst size since certain platforms
1092 * already use a hardcoded 8 (which is what the spec says should be
1093 * done).
1094 */
1095 if (wm_size <= 8)
1096 wm_size = 8;
1097
1098 return wm_size;
1099 }
1100
1101 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1102 {
1103 struct drm_crtc *crtc, *enabled = NULL;
1104
1105 for_each_crtc(dev, crtc) {
1106 if (intel_crtc_active(crtc)) {
1107 if (enabled)
1108 return NULL;
1109 enabled = crtc;
1110 }
1111 }
1112
1113 return enabled;
1114 }
1115
1116 static void pineview_update_wm(struct drm_crtc *unused_crtc)
1117 {
1118 struct drm_device *dev = unused_crtc->dev;
1119 struct drm_i915_private *dev_priv = dev->dev_private;
1120 struct drm_crtc *crtc;
1121 const struct cxsr_latency *latency;
1122 u32 reg;
1123 unsigned long wm;
1124
1125 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1126 dev_priv->fsb_freq, dev_priv->mem_freq);
1127 if (!latency) {
1128 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1129 intel_set_memory_cxsr(dev_priv, false);
1130 return;
1131 }
1132
1133 crtc = single_enabled_crtc(dev);
1134 if (crtc) {
1135 const struct drm_display_mode *adjusted_mode;
1136 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1137 int clock;
1138
1139 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1140 clock = adjusted_mode->crtc_clock;
1141
1142 /* Display SR */
1143 wm = intel_calculate_wm(clock, &pineview_display_wm,
1144 pineview_display_wm.fifo_size,
1145 pixel_size, latency->display_sr);
1146 reg = I915_READ(DSPFW1);
1147 reg &= ~DSPFW_SR_MASK;
1148 reg |= wm << DSPFW_SR_SHIFT;
1149 I915_WRITE(DSPFW1, reg);
1150 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1151
1152 /* cursor SR */
1153 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1154 pineview_display_wm.fifo_size,
1155 pixel_size, latency->cursor_sr);
1156 reg = I915_READ(DSPFW3);
1157 reg &= ~DSPFW_CURSOR_SR_MASK;
1158 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1159 I915_WRITE(DSPFW3, reg);
1160
1161 /* Display HPLL off SR */
1162 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1163 pineview_display_hplloff_wm.fifo_size,
1164 pixel_size, latency->display_hpll_disable);
1165 reg = I915_READ(DSPFW3);
1166 reg &= ~DSPFW_HPLL_SR_MASK;
1167 reg |= wm & DSPFW_HPLL_SR_MASK;
1168 I915_WRITE(DSPFW3, reg);
1169
1170 /* cursor HPLL off SR */
1171 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1172 pineview_display_hplloff_wm.fifo_size,
1173 pixel_size, latency->cursor_hpll_disable);
1174 reg = I915_READ(DSPFW3);
1175 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1176 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1177 I915_WRITE(DSPFW3, reg);
1178 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1179
1180 intel_set_memory_cxsr(dev_priv, true);
1181 } else {
1182 intel_set_memory_cxsr(dev_priv, false);
1183 }
1184 }
1185
1186 static bool g4x_compute_wm0(struct drm_device *dev,
1187 int plane,
1188 const struct intel_watermark_params *display,
1189 int display_latency_ns,
1190 const struct intel_watermark_params *cursor,
1191 int cursor_latency_ns,
1192 int *plane_wm,
1193 int *cursor_wm)
1194 {
1195 struct drm_crtc *crtc;
1196 const struct drm_display_mode *adjusted_mode;
1197 int htotal, hdisplay, clock, pixel_size;
1198 int line_time_us, line_count;
1199 int entries, tlb_miss;
1200
1201 crtc = intel_get_crtc_for_plane(dev, plane);
1202 if (!intel_crtc_active(crtc)) {
1203 *cursor_wm = cursor->guard_size;
1204 *plane_wm = display->guard_size;
1205 return false;
1206 }
1207
1208 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1209 clock = adjusted_mode->crtc_clock;
1210 htotal = adjusted_mode->crtc_htotal;
1211 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1212 pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1213
1214 /* Use the small buffer method to calculate plane watermark */
1215 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1216 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1217 if (tlb_miss > 0)
1218 entries += tlb_miss;
1219 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1220 *plane_wm = entries + display->guard_size;
1221 if (*plane_wm > (int)display->max_wm)
1222 *plane_wm = display->max_wm;
1223
1224 /* Use the large buffer method to calculate cursor watermark */
1225 line_time_us = max(htotal * 1000 / clock, 1);
1226 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1227 entries = line_count * to_intel_crtc(crtc)->cursor_width * pixel_size;
1228 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1229 if (tlb_miss > 0)
1230 entries += tlb_miss;
1231 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1232 *cursor_wm = entries + cursor->guard_size;
1233 if (*cursor_wm > (int)cursor->max_wm)
1234 *cursor_wm = (int)cursor->max_wm;
1235
1236 return true;
1237 }
1238
1239 /*
1240 * Check the wm result.
1241 *
1242 * If any calculated watermark values is larger than the maximum value that
1243 * can be programmed into the associated watermark register, that watermark
1244 * must be disabled.
1245 */
1246 static bool g4x_check_srwm(struct drm_device *dev,
1247 int display_wm, int cursor_wm,
1248 const struct intel_watermark_params *display,
1249 const struct intel_watermark_params *cursor)
1250 {
1251 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1252 display_wm, cursor_wm);
1253
1254 if (display_wm > display->max_wm) {
1255 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1256 display_wm, display->max_wm);
1257 return false;
1258 }
1259
1260 if (cursor_wm > cursor->max_wm) {
1261 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1262 cursor_wm, cursor->max_wm);
1263 return false;
1264 }
1265
1266 if (!(display_wm || cursor_wm)) {
1267 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1268 return false;
1269 }
1270
1271 return true;
1272 }
1273
1274 static bool g4x_compute_srwm(struct drm_device *dev,
1275 int plane,
1276 int latency_ns,
1277 const struct intel_watermark_params *display,
1278 const struct intel_watermark_params *cursor,
1279 int *display_wm, int *cursor_wm)
1280 {
1281 struct drm_crtc *crtc;
1282 const struct drm_display_mode *adjusted_mode;
1283 int hdisplay, htotal, pixel_size, clock;
1284 unsigned long line_time_us;
1285 int line_count, line_size;
1286 int small, large;
1287 int entries;
1288
1289 if (!latency_ns) {
1290 *display_wm = *cursor_wm = 0;
1291 return false;
1292 }
1293
1294 crtc = intel_get_crtc_for_plane(dev, plane);
1295 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1296 clock = adjusted_mode->crtc_clock;
1297 htotal = adjusted_mode->crtc_htotal;
1298 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1299 pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1300
1301 line_time_us = max(htotal * 1000 / clock, 1);
1302 line_count = (latency_ns / line_time_us + 1000) / 1000;
1303 line_size = hdisplay * pixel_size;
1304
1305 /* Use the minimum of the small and large buffer method for primary */
1306 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1307 large = line_count * line_size;
1308
1309 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1310 *display_wm = entries + display->guard_size;
1311
1312 /* calculate the self-refresh watermark for display cursor */
1313 entries = line_count * pixel_size * to_intel_crtc(crtc)->cursor_width;
1314 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1315 *cursor_wm = entries + cursor->guard_size;
1316
1317 return g4x_check_srwm(dev,
1318 *display_wm, *cursor_wm,
1319 display, cursor);
1320 }
1321
1322 static bool vlv_compute_drain_latency(struct drm_crtc *crtc,
1323 int pixel_size,
1324 int *prec_mult,
1325 int *drain_latency)
1326 {
1327 int entries;
1328 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
1329
1330 if (WARN(clock == 0, "Pixel clock is zero!\n"))
1331 return false;
1332
1333 if (WARN(pixel_size == 0, "Pixel size is zero!\n"))
1334 return false;
1335
1336 entries = DIV_ROUND_UP(clock, 1000) * pixel_size;
1337 *prec_mult = (entries > 128) ? DRAIN_LATENCY_PRECISION_64 :
1338 DRAIN_LATENCY_PRECISION_32;
1339 *drain_latency = (64 * (*prec_mult) * 4) / entries;
1340
1341 if (*drain_latency > DRAIN_LATENCY_MASK)
1342 *drain_latency = DRAIN_LATENCY_MASK;
1343
1344 return true;
1345 }
1346
1347 /*
1348 * Update drain latency registers of memory arbiter
1349 *
1350 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1351 * to be programmed. Each plane has a drain latency multiplier and a drain
1352 * latency value.
1353 */
1354
1355 static void vlv_update_drain_latency(struct drm_crtc *crtc)
1356 {
1357 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1358 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1359 int pixel_size;
1360 int drain_latency;
1361 enum pipe pipe = intel_crtc->pipe;
1362 int plane_prec, prec_mult, plane_dl;
1363
1364 plane_dl = I915_READ(VLV_DDL(pipe)) & ~(DDL_PLANE_PRECISION_64 |
1365 DRAIN_LATENCY_MASK | DDL_CURSOR_PRECISION_64 |
1366 (DRAIN_LATENCY_MASK << DDL_CURSOR_SHIFT));
1367
1368 if (!intel_crtc_active(crtc)) {
1369 I915_WRITE(VLV_DDL(pipe), plane_dl);
1370 return;
1371 }
1372
1373 /* Primary plane Drain Latency */
1374 pixel_size = crtc->primary->fb->bits_per_pixel / 8; /* BPP */
1375 if (vlv_compute_drain_latency(crtc, pixel_size, &prec_mult, &drain_latency)) {
1376 plane_prec = (prec_mult == DRAIN_LATENCY_PRECISION_64) ?
1377 DDL_PLANE_PRECISION_64 :
1378 DDL_PLANE_PRECISION_32;
1379 plane_dl |= plane_prec | drain_latency;
1380 }
1381
1382 /* Cursor Drain Latency
1383 * BPP is always 4 for cursor
1384 */
1385 pixel_size = 4;
1386
1387 /* Program cursor DL only if it is enabled */
1388 if (intel_crtc->cursor_base &&
1389 vlv_compute_drain_latency(crtc, pixel_size, &prec_mult, &drain_latency)) {
1390 plane_prec = (prec_mult == DRAIN_LATENCY_PRECISION_64) ?
1391 DDL_CURSOR_PRECISION_64 :
1392 DDL_CURSOR_PRECISION_32;
1393 plane_dl |= plane_prec | (drain_latency << DDL_CURSOR_SHIFT);
1394 }
1395
1396 I915_WRITE(VLV_DDL(pipe), plane_dl);
1397 }
1398
1399 #define single_plane_enabled(mask) is_power_of_2(mask)
1400
1401 static void valleyview_update_wm(struct drm_crtc *crtc)
1402 {
1403 struct drm_device *dev = crtc->dev;
1404 static const int sr_latency_ns = 12000;
1405 struct drm_i915_private *dev_priv = dev->dev_private;
1406 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1407 int plane_sr, cursor_sr;
1408 int ignore_plane_sr, ignore_cursor_sr;
1409 unsigned int enabled = 0;
1410 bool cxsr_enabled;
1411
1412 vlv_update_drain_latency(crtc);
1413
1414 if (g4x_compute_wm0(dev, PIPE_A,
1415 &valleyview_wm_info, pessimal_latency_ns,
1416 &valleyview_cursor_wm_info, pessimal_latency_ns,
1417 &planea_wm, &cursora_wm))
1418 enabled |= 1 << PIPE_A;
1419
1420 if (g4x_compute_wm0(dev, PIPE_B,
1421 &valleyview_wm_info, pessimal_latency_ns,
1422 &valleyview_cursor_wm_info, pessimal_latency_ns,
1423 &planeb_wm, &cursorb_wm))
1424 enabled |= 1 << PIPE_B;
1425
1426 if (single_plane_enabled(enabled) &&
1427 g4x_compute_srwm(dev, ffs(enabled) - 1,
1428 sr_latency_ns,
1429 &valleyview_wm_info,
1430 &valleyview_cursor_wm_info,
1431 &plane_sr, &ignore_cursor_sr) &&
1432 g4x_compute_srwm(dev, ffs(enabled) - 1,
1433 2*sr_latency_ns,
1434 &valleyview_wm_info,
1435 &valleyview_cursor_wm_info,
1436 &ignore_plane_sr, &cursor_sr)) {
1437 cxsr_enabled = true;
1438 } else {
1439 cxsr_enabled = false;
1440 intel_set_memory_cxsr(dev_priv, false);
1441 plane_sr = cursor_sr = 0;
1442 }
1443
1444 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1445 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1446 planea_wm, cursora_wm,
1447 planeb_wm, cursorb_wm,
1448 plane_sr, cursor_sr);
1449
1450 I915_WRITE(DSPFW1,
1451 (plane_sr << DSPFW_SR_SHIFT) |
1452 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1453 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1454 (planea_wm << DSPFW_PLANEA_SHIFT));
1455 I915_WRITE(DSPFW2,
1456 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1457 (cursora_wm << DSPFW_CURSORA_SHIFT));
1458 I915_WRITE(DSPFW3,
1459 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1460 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1461
1462 if (cxsr_enabled)
1463 intel_set_memory_cxsr(dev_priv, true);
1464 }
1465
1466 static void cherryview_update_wm(struct drm_crtc *crtc)
1467 {
1468 struct drm_device *dev = crtc->dev;
1469 static const int sr_latency_ns = 12000;
1470 struct drm_i915_private *dev_priv = dev->dev_private;
1471 int planea_wm, planeb_wm, planec_wm;
1472 int cursora_wm, cursorb_wm, cursorc_wm;
1473 int plane_sr, cursor_sr;
1474 int ignore_plane_sr, ignore_cursor_sr;
1475 unsigned int enabled = 0;
1476 bool cxsr_enabled;
1477
1478 vlv_update_drain_latency(crtc);
1479
1480 if (g4x_compute_wm0(dev, PIPE_A,
1481 &valleyview_wm_info, pessimal_latency_ns,
1482 &valleyview_cursor_wm_info, pessimal_latency_ns,
1483 &planea_wm, &cursora_wm))
1484 enabled |= 1 << PIPE_A;
1485
1486 if (g4x_compute_wm0(dev, PIPE_B,
1487 &valleyview_wm_info, pessimal_latency_ns,
1488 &valleyview_cursor_wm_info, pessimal_latency_ns,
1489 &planeb_wm, &cursorb_wm))
1490 enabled |= 1 << PIPE_B;
1491
1492 if (g4x_compute_wm0(dev, PIPE_C,
1493 &valleyview_wm_info, pessimal_latency_ns,
1494 &valleyview_cursor_wm_info, pessimal_latency_ns,
1495 &planec_wm, &cursorc_wm))
1496 enabled |= 1 << PIPE_C;
1497
1498 if (single_plane_enabled(enabled) &&
1499 g4x_compute_srwm(dev, ffs(enabled) - 1,
1500 sr_latency_ns,
1501 &valleyview_wm_info,
1502 &valleyview_cursor_wm_info,
1503 &plane_sr, &ignore_cursor_sr) &&
1504 g4x_compute_srwm(dev, ffs(enabled) - 1,
1505 2*sr_latency_ns,
1506 &valleyview_wm_info,
1507 &valleyview_cursor_wm_info,
1508 &ignore_plane_sr, &cursor_sr)) {
1509 cxsr_enabled = true;
1510 } else {
1511 cxsr_enabled = false;
1512 intel_set_memory_cxsr(dev_priv, false);
1513 plane_sr = cursor_sr = 0;
1514 }
1515
1516 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1517 "B: plane=%d, cursor=%d, C: plane=%d, cursor=%d, "
1518 "SR: plane=%d, cursor=%d\n",
1519 planea_wm, cursora_wm,
1520 planeb_wm, cursorb_wm,
1521 planec_wm, cursorc_wm,
1522 plane_sr, cursor_sr);
1523
1524 I915_WRITE(DSPFW1,
1525 (plane_sr << DSPFW_SR_SHIFT) |
1526 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1527 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1528 (planea_wm << DSPFW_PLANEA_SHIFT));
1529 I915_WRITE(DSPFW2,
1530 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1531 (cursora_wm << DSPFW_CURSORA_SHIFT));
1532 I915_WRITE(DSPFW3,
1533 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1534 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1535 I915_WRITE(DSPFW9_CHV,
1536 (I915_READ(DSPFW9_CHV) & ~(DSPFW_PLANEC_MASK |
1537 DSPFW_CURSORC_MASK)) |
1538 (planec_wm << DSPFW_PLANEC_SHIFT) |
1539 (cursorc_wm << DSPFW_CURSORC_SHIFT));
1540
1541 if (cxsr_enabled)
1542 intel_set_memory_cxsr(dev_priv, true);
1543 }
1544
1545 static void valleyview_update_sprite_wm(struct drm_plane *plane,
1546 struct drm_crtc *crtc,
1547 uint32_t sprite_width,
1548 uint32_t sprite_height,
1549 int pixel_size,
1550 bool enabled, bool scaled)
1551 {
1552 struct drm_device *dev = crtc->dev;
1553 struct drm_i915_private *dev_priv = dev->dev_private;
1554 int pipe = to_intel_plane(plane)->pipe;
1555 int sprite = to_intel_plane(plane)->plane;
1556 int drain_latency;
1557 int plane_prec;
1558 int sprite_dl;
1559 int prec_mult;
1560
1561 sprite_dl = I915_READ(VLV_DDL(pipe)) & ~(DDL_SPRITE_PRECISION_64(sprite) |
1562 (DRAIN_LATENCY_MASK << DDL_SPRITE_SHIFT(sprite)));
1563
1564 if (enabled && vlv_compute_drain_latency(crtc, pixel_size, &prec_mult,
1565 &drain_latency)) {
1566 plane_prec = (prec_mult == DRAIN_LATENCY_PRECISION_64) ?
1567 DDL_SPRITE_PRECISION_64(sprite) :
1568 DDL_SPRITE_PRECISION_32(sprite);
1569 sprite_dl |= plane_prec |
1570 (drain_latency << DDL_SPRITE_SHIFT(sprite));
1571 }
1572
1573 I915_WRITE(VLV_DDL(pipe), sprite_dl);
1574 }
1575
1576 static void g4x_update_wm(struct drm_crtc *crtc)
1577 {
1578 struct drm_device *dev = crtc->dev;
1579 static const int sr_latency_ns = 12000;
1580 struct drm_i915_private *dev_priv = dev->dev_private;
1581 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1582 int plane_sr, cursor_sr;
1583 unsigned int enabled = 0;
1584 bool cxsr_enabled;
1585
1586 if (g4x_compute_wm0(dev, PIPE_A,
1587 &g4x_wm_info, pessimal_latency_ns,
1588 &g4x_cursor_wm_info, pessimal_latency_ns,
1589 &planea_wm, &cursora_wm))
1590 enabled |= 1 << PIPE_A;
1591
1592 if (g4x_compute_wm0(dev, PIPE_B,
1593 &g4x_wm_info, pessimal_latency_ns,
1594 &g4x_cursor_wm_info, pessimal_latency_ns,
1595 &planeb_wm, &cursorb_wm))
1596 enabled |= 1 << PIPE_B;
1597
1598 if (single_plane_enabled(enabled) &&
1599 g4x_compute_srwm(dev, ffs(enabled) - 1,
1600 sr_latency_ns,
1601 &g4x_wm_info,
1602 &g4x_cursor_wm_info,
1603 &plane_sr, &cursor_sr)) {
1604 cxsr_enabled = true;
1605 } else {
1606 cxsr_enabled = false;
1607 intel_set_memory_cxsr(dev_priv, false);
1608 plane_sr = cursor_sr = 0;
1609 }
1610
1611 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1612 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1613 planea_wm, cursora_wm,
1614 planeb_wm, cursorb_wm,
1615 plane_sr, cursor_sr);
1616
1617 I915_WRITE(DSPFW1,
1618 (plane_sr << DSPFW_SR_SHIFT) |
1619 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1620 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1621 (planea_wm << DSPFW_PLANEA_SHIFT));
1622 I915_WRITE(DSPFW2,
1623 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1624 (cursora_wm << DSPFW_CURSORA_SHIFT));
1625 /* HPLL off in SR has some issues on G4x... disable it */
1626 I915_WRITE(DSPFW3,
1627 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1628 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1629
1630 if (cxsr_enabled)
1631 intel_set_memory_cxsr(dev_priv, true);
1632 }
1633
1634 static void i965_update_wm(struct drm_crtc *unused_crtc)
1635 {
1636 struct drm_device *dev = unused_crtc->dev;
1637 struct drm_i915_private *dev_priv = dev->dev_private;
1638 struct drm_crtc *crtc;
1639 int srwm = 1;
1640 int cursor_sr = 16;
1641 bool cxsr_enabled;
1642
1643 /* Calc sr entries for one plane configs */
1644 crtc = single_enabled_crtc(dev);
1645 if (crtc) {
1646 /* self-refresh has much higher latency */
1647 static const int sr_latency_ns = 12000;
1648 const struct drm_display_mode *adjusted_mode =
1649 &to_intel_crtc(crtc)->config.adjusted_mode;
1650 int clock = adjusted_mode->crtc_clock;
1651 int htotal = adjusted_mode->crtc_htotal;
1652 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1653 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1654 unsigned long line_time_us;
1655 int entries;
1656
1657 line_time_us = max(htotal * 1000 / clock, 1);
1658
1659 /* Use ns/us then divide to preserve precision */
1660 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1661 pixel_size * hdisplay;
1662 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1663 srwm = I965_FIFO_SIZE - entries;
1664 if (srwm < 0)
1665 srwm = 1;
1666 srwm &= 0x1ff;
1667 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1668 entries, srwm);
1669
1670 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1671 pixel_size * to_intel_crtc(crtc)->cursor_width;
1672 entries = DIV_ROUND_UP(entries,
1673 i965_cursor_wm_info.cacheline_size);
1674 cursor_sr = i965_cursor_wm_info.fifo_size -
1675 (entries + i965_cursor_wm_info.guard_size);
1676
1677 if (cursor_sr > i965_cursor_wm_info.max_wm)
1678 cursor_sr = i965_cursor_wm_info.max_wm;
1679
1680 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1681 "cursor %d\n", srwm, cursor_sr);
1682
1683 cxsr_enabled = true;
1684 } else {
1685 cxsr_enabled = false;
1686 /* Turn off self refresh if both pipes are enabled */
1687 intel_set_memory_cxsr(dev_priv, false);
1688 }
1689
1690 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1691 srwm);
1692
1693 /* 965 has limitations... */
1694 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1695 (8 << DSPFW_CURSORB_SHIFT) |
1696 (8 << DSPFW_PLANEB_SHIFT) |
1697 (8 << DSPFW_PLANEA_SHIFT));
1698 I915_WRITE(DSPFW2, (8 << DSPFW_CURSORA_SHIFT) |
1699 (8 << DSPFW_PLANEC_SHIFT_OLD));
1700 /* update cursor SR watermark */
1701 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1702
1703 if (cxsr_enabled)
1704 intel_set_memory_cxsr(dev_priv, true);
1705 }
1706
1707 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1708 {
1709 struct drm_device *dev = unused_crtc->dev;
1710 struct drm_i915_private *dev_priv = dev->dev_private;
1711 const struct intel_watermark_params *wm_info;
1712 uint32_t fwater_lo;
1713 uint32_t fwater_hi;
1714 int cwm, srwm = 1;
1715 int fifo_size;
1716 int planea_wm, planeb_wm;
1717 struct drm_crtc *crtc, *enabled = NULL;
1718
1719 if (IS_I945GM(dev))
1720 wm_info = &i945_wm_info;
1721 else if (!IS_GEN2(dev))
1722 wm_info = &i915_wm_info;
1723 else
1724 wm_info = &i830_a_wm_info;
1725
1726 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1727 crtc = intel_get_crtc_for_plane(dev, 0);
1728 if (intel_crtc_active(crtc)) {
1729 const struct drm_display_mode *adjusted_mode;
1730 int cpp = crtc->primary->fb->bits_per_pixel / 8;
1731 if (IS_GEN2(dev))
1732 cpp = 4;
1733
1734 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1735 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1736 wm_info, fifo_size, cpp,
1737 pessimal_latency_ns);
1738 enabled = crtc;
1739 } else {
1740 planea_wm = fifo_size - wm_info->guard_size;
1741 if (planea_wm > (long)wm_info->max_wm)
1742 planea_wm = wm_info->max_wm;
1743 }
1744
1745 if (IS_GEN2(dev))
1746 wm_info = &i830_bc_wm_info;
1747
1748 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1749 crtc = intel_get_crtc_for_plane(dev, 1);
1750 if (intel_crtc_active(crtc)) {
1751 const struct drm_display_mode *adjusted_mode;
1752 int cpp = crtc->primary->fb->bits_per_pixel / 8;
1753 if (IS_GEN2(dev))
1754 cpp = 4;
1755
1756 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1757 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1758 wm_info, fifo_size, cpp,
1759 pessimal_latency_ns);
1760 if (enabled == NULL)
1761 enabled = crtc;
1762 else
1763 enabled = NULL;
1764 } else {
1765 planeb_wm = fifo_size - wm_info->guard_size;
1766 if (planeb_wm > (long)wm_info->max_wm)
1767 planeb_wm = wm_info->max_wm;
1768 }
1769
1770 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1771
1772 if (IS_I915GM(dev) && enabled) {
1773 struct drm_i915_gem_object *obj;
1774
1775 obj = intel_fb_obj(enabled->primary->fb);
1776
1777 /* self-refresh seems busted with untiled */
1778 if (obj->tiling_mode == I915_TILING_NONE)
1779 enabled = NULL;
1780 }
1781
1782 /*
1783 * Overlay gets an aggressive default since video jitter is bad.
1784 */
1785 cwm = 2;
1786
1787 /* Play safe and disable self-refresh before adjusting watermarks. */
1788 intel_set_memory_cxsr(dev_priv, false);
1789
1790 /* Calc sr entries for one plane configs */
1791 if (HAS_FW_BLC(dev) && enabled) {
1792 /* self-refresh has much higher latency */
1793 static const int sr_latency_ns = 6000;
1794 const struct drm_display_mode *adjusted_mode =
1795 &to_intel_crtc(enabled)->config.adjusted_mode;
1796 int clock = adjusted_mode->crtc_clock;
1797 int htotal = adjusted_mode->crtc_htotal;
1798 int hdisplay = to_intel_crtc(enabled)->config.pipe_src_w;
1799 int pixel_size = enabled->primary->fb->bits_per_pixel / 8;
1800 unsigned long line_time_us;
1801 int entries;
1802
1803 line_time_us = max(htotal * 1000 / clock, 1);
1804
1805 /* Use ns/us then divide to preserve precision */
1806 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1807 pixel_size * hdisplay;
1808 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1809 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1810 srwm = wm_info->fifo_size - entries;
1811 if (srwm < 0)
1812 srwm = 1;
1813
1814 if (IS_I945G(dev) || IS_I945GM(dev))
1815 I915_WRITE(FW_BLC_SELF,
1816 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1817 else if (IS_I915GM(dev))
1818 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1819 }
1820
1821 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1822 planea_wm, planeb_wm, cwm, srwm);
1823
1824 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1825 fwater_hi = (cwm & 0x1f);
1826
1827 /* Set request length to 8 cachelines per fetch */
1828 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1829 fwater_hi = fwater_hi | (1 << 8);
1830
1831 I915_WRITE(FW_BLC, fwater_lo);
1832 I915_WRITE(FW_BLC2, fwater_hi);
1833
1834 if (enabled)
1835 intel_set_memory_cxsr(dev_priv, true);
1836 }
1837
1838 static void i845_update_wm(struct drm_crtc *unused_crtc)
1839 {
1840 struct drm_device *dev = unused_crtc->dev;
1841 struct drm_i915_private *dev_priv = dev->dev_private;
1842 struct drm_crtc *crtc;
1843 const struct drm_display_mode *adjusted_mode;
1844 uint32_t fwater_lo;
1845 int planea_wm;
1846
1847 crtc = single_enabled_crtc(dev);
1848 if (crtc == NULL)
1849 return;
1850
1851 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1852 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1853 &i845_wm_info,
1854 dev_priv->display.get_fifo_size(dev, 0),
1855 4, pessimal_latency_ns);
1856 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1857 fwater_lo |= (3<<8) | planea_wm;
1858
1859 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1860
1861 I915_WRITE(FW_BLC, fwater_lo);
1862 }
1863
1864 static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
1865 struct drm_crtc *crtc)
1866 {
1867 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1868 uint32_t pixel_rate;
1869
1870 pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock;
1871
1872 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1873 * adjust the pixel_rate here. */
1874
1875 if (intel_crtc->config.pch_pfit.enabled) {
1876 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1877 uint32_t pfit_size = intel_crtc->config.pch_pfit.size;
1878
1879 pipe_w = intel_crtc->config.pipe_src_w;
1880 pipe_h = intel_crtc->config.pipe_src_h;
1881 pfit_w = (pfit_size >> 16) & 0xFFFF;
1882 pfit_h = pfit_size & 0xFFFF;
1883 if (pipe_w < pfit_w)
1884 pipe_w = pfit_w;
1885 if (pipe_h < pfit_h)
1886 pipe_h = pfit_h;
1887
1888 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1889 pfit_w * pfit_h);
1890 }
1891
1892 return pixel_rate;
1893 }
1894
1895 /* latency must be in 0.1us units. */
1896 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
1897 uint32_t latency)
1898 {
1899 uint64_t ret;
1900
1901 if (WARN(latency == 0, "Latency value missing\n"))
1902 return UINT_MAX;
1903
1904 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1905 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1906
1907 return ret;
1908 }
1909
1910 /* latency must be in 0.1us units. */
1911 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1912 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1913 uint32_t latency)
1914 {
1915 uint32_t ret;
1916
1917 if (WARN(latency == 0, "Latency value missing\n"))
1918 return UINT_MAX;
1919
1920 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1921 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1922 ret = DIV_ROUND_UP(ret, 64) + 2;
1923 return ret;
1924 }
1925
1926 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1927 uint8_t bytes_per_pixel)
1928 {
1929 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1930 }
1931
1932 struct ilk_pipe_wm_parameters {
1933 bool active;
1934 uint32_t pipe_htotal;
1935 uint32_t pixel_rate;
1936 struct intel_plane_wm_parameters pri;
1937 struct intel_plane_wm_parameters spr;
1938 struct intel_plane_wm_parameters cur;
1939 };
1940
1941 struct ilk_wm_maximums {
1942 uint16_t pri;
1943 uint16_t spr;
1944 uint16_t cur;
1945 uint16_t fbc;
1946 };
1947
1948 /* used in computing the new watermarks state */
1949 struct intel_wm_config {
1950 unsigned int num_pipes_active;
1951 bool sprites_enabled;
1952 bool sprites_scaled;
1953 };
1954
1955 /*
1956 * For both WM_PIPE and WM_LP.
1957 * mem_value must be in 0.1us units.
1958 */
1959 static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params,
1960 uint32_t mem_value,
1961 bool is_lp)
1962 {
1963 uint32_t method1, method2;
1964
1965 if (!params->active || !params->pri.enabled)
1966 return 0;
1967
1968 method1 = ilk_wm_method1(params->pixel_rate,
1969 params->pri.bytes_per_pixel,
1970 mem_value);
1971
1972 if (!is_lp)
1973 return method1;
1974
1975 method2 = ilk_wm_method2(params->pixel_rate,
1976 params->pipe_htotal,
1977 params->pri.horiz_pixels,
1978 params->pri.bytes_per_pixel,
1979 mem_value);
1980
1981 return min(method1, method2);
1982 }
1983
1984 /*
1985 * For both WM_PIPE and WM_LP.
1986 * mem_value must be in 0.1us units.
1987 */
1988 static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params,
1989 uint32_t mem_value)
1990 {
1991 uint32_t method1, method2;
1992
1993 if (!params->active || !params->spr.enabled)
1994 return 0;
1995
1996 method1 = ilk_wm_method1(params->pixel_rate,
1997 params->spr.bytes_per_pixel,
1998 mem_value);
1999 method2 = ilk_wm_method2(params->pixel_rate,
2000 params->pipe_htotal,
2001 params->spr.horiz_pixels,
2002 params->spr.bytes_per_pixel,
2003 mem_value);
2004 return min(method1, method2);
2005 }
2006
2007 /*
2008 * For both WM_PIPE and WM_LP.
2009 * mem_value must be in 0.1us units.
2010 */
2011 static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params,
2012 uint32_t mem_value)
2013 {
2014 if (!params->active || !params->cur.enabled)
2015 return 0;
2016
2017 return ilk_wm_method2(params->pixel_rate,
2018 params->pipe_htotal,
2019 params->cur.horiz_pixels,
2020 params->cur.bytes_per_pixel,
2021 mem_value);
2022 }
2023
2024 /* Only for WM_LP. */
2025 static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params,
2026 uint32_t pri_val)
2027 {
2028 if (!params->active || !params->pri.enabled)
2029 return 0;
2030
2031 return ilk_wm_fbc(pri_val,
2032 params->pri.horiz_pixels,
2033 params->pri.bytes_per_pixel);
2034 }
2035
2036 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
2037 {
2038 if (INTEL_INFO(dev)->gen >= 8)
2039 return 3072;
2040 else if (INTEL_INFO(dev)->gen >= 7)
2041 return 768;
2042 else
2043 return 512;
2044 }
2045
2046 static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
2047 int level, bool is_sprite)
2048 {
2049 if (INTEL_INFO(dev)->gen >= 8)
2050 /* BDW primary/sprite plane watermarks */
2051 return level == 0 ? 255 : 2047;
2052 else if (INTEL_INFO(dev)->gen >= 7)
2053 /* IVB/HSW primary/sprite plane watermarks */
2054 return level == 0 ? 127 : 1023;
2055 else if (!is_sprite)
2056 /* ILK/SNB primary plane watermarks */
2057 return level == 0 ? 127 : 511;
2058 else
2059 /* ILK/SNB sprite plane watermarks */
2060 return level == 0 ? 63 : 255;
2061 }
2062
2063 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
2064 int level)
2065 {
2066 if (INTEL_INFO(dev)->gen >= 7)
2067 return level == 0 ? 63 : 255;
2068 else
2069 return level == 0 ? 31 : 63;
2070 }
2071
2072 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
2073 {
2074 if (INTEL_INFO(dev)->gen >= 8)
2075 return 31;
2076 else
2077 return 15;
2078 }
2079
2080 /* Calculate the maximum primary/sprite plane watermark */
2081 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
2082 int level,
2083 const struct intel_wm_config *config,
2084 enum intel_ddb_partitioning ddb_partitioning,
2085 bool is_sprite)
2086 {
2087 unsigned int fifo_size = ilk_display_fifo_size(dev);
2088
2089 /* if sprites aren't enabled, sprites get nothing */
2090 if (is_sprite && !config->sprites_enabled)
2091 return 0;
2092
2093 /* HSW allows LP1+ watermarks even with multiple pipes */
2094 if (level == 0 || config->num_pipes_active > 1) {
2095 fifo_size /= INTEL_INFO(dev)->num_pipes;
2096
2097 /*
2098 * For some reason the non self refresh
2099 * FIFO size is only half of the self
2100 * refresh FIFO size on ILK/SNB.
2101 */
2102 if (INTEL_INFO(dev)->gen <= 6)
2103 fifo_size /= 2;
2104 }
2105
2106 if (config->sprites_enabled) {
2107 /* level 0 is always calculated with 1:1 split */
2108 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
2109 if (is_sprite)
2110 fifo_size *= 5;
2111 fifo_size /= 6;
2112 } else {
2113 fifo_size /= 2;
2114 }
2115 }
2116
2117 /* clamp to max that the registers can hold */
2118 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
2119 }
2120
2121 /* Calculate the maximum cursor plane watermark */
2122 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
2123 int level,
2124 const struct intel_wm_config *config)
2125 {
2126 /* HSW LP1+ watermarks w/ multiple pipes */
2127 if (level > 0 && config->num_pipes_active > 1)
2128 return 64;
2129
2130 /* otherwise just report max that registers can hold */
2131 return ilk_cursor_wm_reg_max(dev, level);
2132 }
2133
2134 static void ilk_compute_wm_maximums(const struct drm_device *dev,
2135 int level,
2136 const struct intel_wm_config *config,
2137 enum intel_ddb_partitioning ddb_partitioning,
2138 struct ilk_wm_maximums *max)
2139 {
2140 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
2141 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
2142 max->cur = ilk_cursor_wm_max(dev, level, config);
2143 max->fbc = ilk_fbc_wm_reg_max(dev);
2144 }
2145
2146 static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
2147 int level,
2148 struct ilk_wm_maximums *max)
2149 {
2150 max->pri = ilk_plane_wm_reg_max(dev, level, false);
2151 max->spr = ilk_plane_wm_reg_max(dev, level, true);
2152 max->cur = ilk_cursor_wm_reg_max(dev, level);
2153 max->fbc = ilk_fbc_wm_reg_max(dev);
2154 }
2155
2156 static bool ilk_validate_wm_level(int level,
2157 const struct ilk_wm_maximums *max,
2158 struct intel_wm_level *result)
2159 {
2160 bool ret;
2161
2162 /* already determined to be invalid? */
2163 if (!result->enable)
2164 return false;
2165
2166 result->enable = result->pri_val <= max->pri &&
2167 result->spr_val <= max->spr &&
2168 result->cur_val <= max->cur;
2169
2170 ret = result->enable;
2171
2172 /*
2173 * HACK until we can pre-compute everything,
2174 * and thus fail gracefully if LP0 watermarks
2175 * are exceeded...
2176 */
2177 if (level == 0 && !result->enable) {
2178 if (result->pri_val > max->pri)
2179 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2180 level, result->pri_val, max->pri);
2181 if (result->spr_val > max->spr)
2182 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2183 level, result->spr_val, max->spr);
2184 if (result->cur_val > max->cur)
2185 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2186 level, result->cur_val, max->cur);
2187
2188 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2189 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2190 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2191 result->enable = true;
2192 }
2193
2194 return ret;
2195 }
2196
2197 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
2198 int level,
2199 const struct ilk_pipe_wm_parameters *p,
2200 struct intel_wm_level *result)
2201 {
2202 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2203 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2204 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2205
2206 /* WM1+ latency values stored in 0.5us units */
2207 if (level > 0) {
2208 pri_latency *= 5;
2209 spr_latency *= 5;
2210 cur_latency *= 5;
2211 }
2212
2213 result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
2214 result->spr_val = ilk_compute_spr_wm(p, spr_latency);
2215 result->cur_val = ilk_compute_cur_wm(p, cur_latency);
2216 result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
2217 result->enable = true;
2218 }
2219
2220 static uint32_t
2221 hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
2222 {
2223 struct drm_i915_private *dev_priv = dev->dev_private;
2224 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2225 struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
2226 u32 linetime, ips_linetime;
2227
2228 if (!intel_crtc_active(crtc))
2229 return 0;
2230
2231 /* The WM are computed with base on how long it takes to fill a single
2232 * row at the given clock rate, multiplied by 8.
2233 * */
2234 linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
2235 mode->crtc_clock);
2236 ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
2237 intel_ddi_get_cdclk_freq(dev_priv));
2238
2239 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2240 PIPE_WM_LINETIME_TIME(linetime);
2241 }
2242
2243 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5])
2244 {
2245 struct drm_i915_private *dev_priv = dev->dev_private;
2246
2247 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2248 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2249
2250 wm[0] = (sskpd >> 56) & 0xFF;
2251 if (wm[0] == 0)
2252 wm[0] = sskpd & 0xF;
2253 wm[1] = (sskpd >> 4) & 0xFF;
2254 wm[2] = (sskpd >> 12) & 0xFF;
2255 wm[3] = (sskpd >> 20) & 0x1FF;
2256 wm[4] = (sskpd >> 32) & 0x1FF;
2257 } else if (INTEL_INFO(dev)->gen >= 6) {
2258 uint32_t sskpd = I915_READ(MCH_SSKPD);
2259
2260 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2261 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2262 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2263 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2264 } else if (INTEL_INFO(dev)->gen >= 5) {
2265 uint32_t mltr = I915_READ(MLTR_ILK);
2266
2267 /* ILK primary LP0 latency is 700 ns */
2268 wm[0] = 7;
2269 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2270 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2271 }
2272 }
2273
2274 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2275 {
2276 /* ILK sprite LP0 latency is 1300 ns */
2277 if (INTEL_INFO(dev)->gen == 5)
2278 wm[0] = 13;
2279 }
2280
2281 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2282 {
2283 /* ILK cursor LP0 latency is 1300 ns */
2284 if (INTEL_INFO(dev)->gen == 5)
2285 wm[0] = 13;
2286
2287 /* WaDoubleCursorLP3Latency:ivb */
2288 if (IS_IVYBRIDGE(dev))
2289 wm[3] *= 2;
2290 }
2291
2292 int ilk_wm_max_level(const struct drm_device *dev)
2293 {
2294 /* how many WM levels are we expecting */
2295 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2296 return 4;
2297 else if (INTEL_INFO(dev)->gen >= 6)
2298 return 3;
2299 else
2300 return 2;
2301 }
2302 static void intel_print_wm_latency(struct drm_device *dev,
2303 const char *name,
2304 const uint16_t wm[5])
2305 {
2306 int level, max_level = ilk_wm_max_level(dev);
2307
2308 for (level = 0; level <= max_level; level++) {
2309 unsigned int latency = wm[level];
2310
2311 if (latency == 0) {
2312 DRM_ERROR("%s WM%d latency not provided\n",
2313 name, level);
2314 continue;
2315 }
2316
2317 /* WM1+ latency values in 0.5us units */
2318 if (level > 0)
2319 latency *= 5;
2320
2321 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2322 name, level, wm[level],
2323 latency / 10, latency % 10);
2324 }
2325 }
2326
2327 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2328 uint16_t wm[5], uint16_t min)
2329 {
2330 int level, max_level = ilk_wm_max_level(dev_priv->dev);
2331
2332 if (wm[0] >= min)
2333 return false;
2334
2335 wm[0] = max(wm[0], min);
2336 for (level = 1; level <= max_level; level++)
2337 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2338
2339 return true;
2340 }
2341
2342 static void snb_wm_latency_quirk(struct drm_device *dev)
2343 {
2344 struct drm_i915_private *dev_priv = dev->dev_private;
2345 bool changed;
2346
2347 /*
2348 * The BIOS provided WM memory latency values are often
2349 * inadequate for high resolution displays. Adjust them.
2350 */
2351 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2352 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2353 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2354
2355 if (!changed)
2356 return;
2357
2358 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2359 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2360 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2361 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2362 }
2363
2364 static void ilk_setup_wm_latency(struct drm_device *dev)
2365 {
2366 struct drm_i915_private *dev_priv = dev->dev_private;
2367
2368 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2369
2370 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2371 sizeof(dev_priv->wm.pri_latency));
2372 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2373 sizeof(dev_priv->wm.pri_latency));
2374
2375 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2376 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2377
2378 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2379 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2380 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2381
2382 if (IS_GEN6(dev))
2383 snb_wm_latency_quirk(dev);
2384 }
2385
2386 static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
2387 struct ilk_pipe_wm_parameters *p)
2388 {
2389 struct drm_device *dev = crtc->dev;
2390 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2391 enum pipe pipe = intel_crtc->pipe;
2392 struct drm_plane *plane;
2393
2394 if (!intel_crtc_active(crtc))
2395 return;
2396
2397 p->active = true;
2398 p->pipe_htotal = intel_crtc->config.adjusted_mode.crtc_htotal;
2399 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
2400 p->pri.bytes_per_pixel = crtc->primary->fb->bits_per_pixel / 8;
2401 p->cur.bytes_per_pixel = 4;
2402 p->pri.horiz_pixels = intel_crtc->config.pipe_src_w;
2403 p->cur.horiz_pixels = intel_crtc->cursor_width;
2404 /* TODO: for now, assume primary and cursor planes are always enabled. */
2405 p->pri.enabled = true;
2406 p->cur.enabled = true;
2407
2408 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
2409 struct intel_plane *intel_plane = to_intel_plane(plane);
2410
2411 if (intel_plane->pipe == pipe) {
2412 p->spr = intel_plane->wm;
2413 break;
2414 }
2415 }
2416 }
2417
2418 static void ilk_compute_wm_config(struct drm_device *dev,
2419 struct intel_wm_config *config)
2420 {
2421 struct intel_crtc *intel_crtc;
2422
2423 /* Compute the currently _active_ config */
2424 for_each_intel_crtc(dev, intel_crtc) {
2425 const struct intel_pipe_wm *wm = &intel_crtc->wm.active;
2426
2427 if (!wm->pipe_enabled)
2428 continue;
2429
2430 config->sprites_enabled |= wm->sprites_enabled;
2431 config->sprites_scaled |= wm->sprites_scaled;
2432 config->num_pipes_active++;
2433 }
2434 }
2435
2436 /* Compute new watermarks for the pipe */
2437 static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
2438 const struct ilk_pipe_wm_parameters *params,
2439 struct intel_pipe_wm *pipe_wm)
2440 {
2441 struct drm_device *dev = crtc->dev;
2442 const struct drm_i915_private *dev_priv = dev->dev_private;
2443 int level, max_level = ilk_wm_max_level(dev);
2444 /* LP0 watermark maximums depend on this pipe alone */
2445 struct intel_wm_config config = {
2446 .num_pipes_active = 1,
2447 .sprites_enabled = params->spr.enabled,
2448 .sprites_scaled = params->spr.scaled,
2449 };
2450 struct ilk_wm_maximums max;
2451
2452 pipe_wm->pipe_enabled = params->active;
2453 pipe_wm->sprites_enabled = params->spr.enabled;
2454 pipe_wm->sprites_scaled = params->spr.scaled;
2455
2456 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2457 if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled)
2458 max_level = 1;
2459
2460 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2461 if (params->spr.scaled)
2462 max_level = 0;
2463
2464 ilk_compute_wm_level(dev_priv, 0, params, &pipe_wm->wm[0]);
2465
2466 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2467 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
2468
2469 /* LP0 watermarks always use 1/2 DDB partitioning */
2470 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2471
2472 /* At least LP0 must be valid */
2473 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
2474 return false;
2475
2476 ilk_compute_wm_reg_maximums(dev, 1, &max);
2477
2478 for (level = 1; level <= max_level; level++) {
2479 struct intel_wm_level wm = {};
2480
2481 ilk_compute_wm_level(dev_priv, level, params, &wm);
2482
2483 /*
2484 * Disable any watermark level that exceeds the
2485 * register maximums since such watermarks are
2486 * always invalid.
2487 */
2488 if (!ilk_validate_wm_level(level, &max, &wm))
2489 break;
2490
2491 pipe_wm->wm[level] = wm;
2492 }
2493
2494 return true;
2495 }
2496
2497 /*
2498 * Merge the watermarks from all active pipes for a specific level.
2499 */
2500 static void ilk_merge_wm_level(struct drm_device *dev,
2501 int level,
2502 struct intel_wm_level *ret_wm)
2503 {
2504 const struct intel_crtc *intel_crtc;
2505
2506 ret_wm->enable = true;
2507
2508 for_each_intel_crtc(dev, intel_crtc) {
2509 const struct intel_pipe_wm *active = &intel_crtc->wm.active;
2510 const struct intel_wm_level *wm = &active->wm[level];
2511
2512 if (!active->pipe_enabled)
2513 continue;
2514
2515 /*
2516 * The watermark values may have been used in the past,
2517 * so we must maintain them in the registers for some
2518 * time even if the level is now disabled.
2519 */
2520 if (!wm->enable)
2521 ret_wm->enable = false;
2522
2523 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2524 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2525 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2526 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2527 }
2528 }
2529
2530 /*
2531 * Merge all low power watermarks for all active pipes.
2532 */
2533 static void ilk_wm_merge(struct drm_device *dev,
2534 const struct intel_wm_config *config,
2535 const struct ilk_wm_maximums *max,
2536 struct intel_pipe_wm *merged)
2537 {
2538 int level, max_level = ilk_wm_max_level(dev);
2539 int last_enabled_level = max_level;
2540
2541 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2542 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2543 config->num_pipes_active > 1)
2544 return;
2545
2546 /* ILK: FBC WM must be disabled always */
2547 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
2548
2549 /* merge each WM1+ level */
2550 for (level = 1; level <= max_level; level++) {
2551 struct intel_wm_level *wm = &merged->wm[level];
2552
2553 ilk_merge_wm_level(dev, level, wm);
2554
2555 if (level > last_enabled_level)
2556 wm->enable = false;
2557 else if (!ilk_validate_wm_level(level, max, wm))
2558 /* make sure all following levels get disabled */
2559 last_enabled_level = level - 1;
2560
2561 /*
2562 * The spec says it is preferred to disable
2563 * FBC WMs instead of disabling a WM level.
2564 */
2565 if (wm->fbc_val > max->fbc) {
2566 if (wm->enable)
2567 merged->fbc_wm_enabled = false;
2568 wm->fbc_val = 0;
2569 }
2570 }
2571
2572 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2573 /*
2574 * FIXME this is racy. FBC might get enabled later.
2575 * What we should check here is whether FBC can be
2576 * enabled sometime later.
2577 */
2578 if (IS_GEN5(dev) && !merged->fbc_wm_enabled && intel_fbc_enabled(dev)) {
2579 for (level = 2; level <= max_level; level++) {
2580 struct intel_wm_level *wm = &merged->wm[level];
2581
2582 wm->enable = false;
2583 }
2584 }
2585 }
2586
2587 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2588 {
2589 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2590 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2591 }
2592
2593 /* The value we need to program into the WM_LPx latency field */
2594 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2595 {
2596 struct drm_i915_private *dev_priv = dev->dev_private;
2597
2598 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2599 return 2 * level;
2600 else
2601 return dev_priv->wm.pri_latency[level];
2602 }
2603
2604 static void ilk_compute_wm_results(struct drm_device *dev,
2605 const struct intel_pipe_wm *merged,
2606 enum intel_ddb_partitioning partitioning,
2607 struct ilk_wm_values *results)
2608 {
2609 struct intel_crtc *intel_crtc;
2610 int level, wm_lp;
2611
2612 results->enable_fbc_wm = merged->fbc_wm_enabled;
2613 results->partitioning = partitioning;
2614
2615 /* LP1+ register values */
2616 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2617 const struct intel_wm_level *r;
2618
2619 level = ilk_wm_lp_to_level(wm_lp, merged);
2620
2621 r = &merged->wm[level];
2622
2623 /*
2624 * Maintain the watermark values even if the level is
2625 * disabled. Doing otherwise could cause underruns.
2626 */
2627 results->wm_lp[wm_lp - 1] =
2628 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2629 (r->pri_val << WM1_LP_SR_SHIFT) |
2630 r->cur_val;
2631
2632 if (r->enable)
2633 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2634
2635 if (INTEL_INFO(dev)->gen >= 8)
2636 results->wm_lp[wm_lp - 1] |=
2637 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2638 else
2639 results->wm_lp[wm_lp - 1] |=
2640 r->fbc_val << WM1_LP_FBC_SHIFT;
2641
2642 /*
2643 * Always set WM1S_LP_EN when spr_val != 0, even if the
2644 * level is disabled. Doing otherwise could cause underruns.
2645 */
2646 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2647 WARN_ON(wm_lp != 1);
2648 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2649 } else
2650 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2651 }
2652
2653 /* LP0 register values */
2654 for_each_intel_crtc(dev, intel_crtc) {
2655 enum pipe pipe = intel_crtc->pipe;
2656 const struct intel_wm_level *r =
2657 &intel_crtc->wm.active.wm[0];
2658
2659 if (WARN_ON(!r->enable))
2660 continue;
2661
2662 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
2663
2664 results->wm_pipe[pipe] =
2665 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2666 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2667 r->cur_val;
2668 }
2669 }
2670
2671 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2672 * case both are at the same level. Prefer r1 in case they're the same. */
2673 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2674 struct intel_pipe_wm *r1,
2675 struct intel_pipe_wm *r2)
2676 {
2677 int level, max_level = ilk_wm_max_level(dev);
2678 int level1 = 0, level2 = 0;
2679
2680 for (level = 1; level <= max_level; level++) {
2681 if (r1->wm[level].enable)
2682 level1 = level;
2683 if (r2->wm[level].enable)
2684 level2 = level;
2685 }
2686
2687 if (level1 == level2) {
2688 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2689 return r2;
2690 else
2691 return r1;
2692 } else if (level1 > level2) {
2693 return r1;
2694 } else {
2695 return r2;
2696 }
2697 }
2698
2699 /* dirty bits used to track which watermarks need changes */
2700 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2701 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2702 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2703 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2704 #define WM_DIRTY_FBC (1 << 24)
2705 #define WM_DIRTY_DDB (1 << 25)
2706
2707 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
2708 const struct ilk_wm_values *old,
2709 const struct ilk_wm_values *new)
2710 {
2711 unsigned int dirty = 0;
2712 enum pipe pipe;
2713 int wm_lp;
2714
2715 for_each_pipe(dev_priv, pipe) {
2716 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2717 dirty |= WM_DIRTY_LINETIME(pipe);
2718 /* Must disable LP1+ watermarks too */
2719 dirty |= WM_DIRTY_LP_ALL;
2720 }
2721
2722 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2723 dirty |= WM_DIRTY_PIPE(pipe);
2724 /* Must disable LP1+ watermarks too */
2725 dirty |= WM_DIRTY_LP_ALL;
2726 }
2727 }
2728
2729 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2730 dirty |= WM_DIRTY_FBC;
2731 /* Must disable LP1+ watermarks too */
2732 dirty |= WM_DIRTY_LP_ALL;
2733 }
2734
2735 if (old->partitioning != new->partitioning) {
2736 dirty |= WM_DIRTY_DDB;
2737 /* Must disable LP1+ watermarks too */
2738 dirty |= WM_DIRTY_LP_ALL;
2739 }
2740
2741 /* LP1+ watermarks already deemed dirty, no need to continue */
2742 if (dirty & WM_DIRTY_LP_ALL)
2743 return dirty;
2744
2745 /* Find the lowest numbered LP1+ watermark in need of an update... */
2746 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2747 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2748 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2749 break;
2750 }
2751
2752 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2753 for (; wm_lp <= 3; wm_lp++)
2754 dirty |= WM_DIRTY_LP(wm_lp);
2755
2756 return dirty;
2757 }
2758
2759 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2760 unsigned int dirty)
2761 {
2762 struct ilk_wm_values *previous = &dev_priv->wm.hw;
2763 bool changed = false;
2764
2765 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2766 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2767 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2768 changed = true;
2769 }
2770 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2771 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2772 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2773 changed = true;
2774 }
2775 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2776 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2777 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2778 changed = true;
2779 }
2780
2781 /*
2782 * Don't touch WM1S_LP_EN here.
2783 * Doing so could cause underruns.
2784 */
2785
2786 return changed;
2787 }
2788
2789 /*
2790 * The spec says we shouldn't write when we don't need, because every write
2791 * causes WMs to be re-evaluated, expending some power.
2792 */
2793 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2794 struct ilk_wm_values *results)
2795 {
2796 struct drm_device *dev = dev_priv->dev;
2797 struct ilk_wm_values *previous = &dev_priv->wm.hw;
2798 unsigned int dirty;
2799 uint32_t val;
2800
2801 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
2802 if (!dirty)
2803 return;
2804
2805 _ilk_disable_lp_wm(dev_priv, dirty);
2806
2807 if (dirty & WM_DIRTY_PIPE(PIPE_A))
2808 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2809 if (dirty & WM_DIRTY_PIPE(PIPE_B))
2810 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2811 if (dirty & WM_DIRTY_PIPE(PIPE_C))
2812 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2813
2814 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2815 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2816 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2817 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2818 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2819 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2820
2821 if (dirty & WM_DIRTY_DDB) {
2822 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2823 val = I915_READ(WM_MISC);
2824 if (results->partitioning == INTEL_DDB_PART_1_2)
2825 val &= ~WM_MISC_DATA_PARTITION_5_6;
2826 else
2827 val |= WM_MISC_DATA_PARTITION_5_6;
2828 I915_WRITE(WM_MISC, val);
2829 } else {
2830 val = I915_READ(DISP_ARB_CTL2);
2831 if (results->partitioning == INTEL_DDB_PART_1_2)
2832 val &= ~DISP_DATA_PARTITION_5_6;
2833 else
2834 val |= DISP_DATA_PARTITION_5_6;
2835 I915_WRITE(DISP_ARB_CTL2, val);
2836 }
2837 }
2838
2839 if (dirty & WM_DIRTY_FBC) {
2840 val = I915_READ(DISP_ARB_CTL);
2841 if (results->enable_fbc_wm)
2842 val &= ~DISP_FBC_WM_DIS;
2843 else
2844 val |= DISP_FBC_WM_DIS;
2845 I915_WRITE(DISP_ARB_CTL, val);
2846 }
2847
2848 if (dirty & WM_DIRTY_LP(1) &&
2849 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2850 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2851
2852 if (INTEL_INFO(dev)->gen >= 7) {
2853 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2854 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2855 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2856 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2857 }
2858
2859 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2860 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2861 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2862 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2863 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2864 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2865
2866 dev_priv->wm.hw = *results;
2867 }
2868
2869 static bool ilk_disable_lp_wm(struct drm_device *dev)
2870 {
2871 struct drm_i915_private *dev_priv = dev->dev_private;
2872
2873 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2874 }
2875
2876 static void ilk_update_wm(struct drm_crtc *crtc)
2877 {
2878 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2879 struct drm_device *dev = crtc->dev;
2880 struct drm_i915_private *dev_priv = dev->dev_private;
2881 struct ilk_wm_maximums max;
2882 struct ilk_pipe_wm_parameters params = {};
2883 struct ilk_wm_values results = {};
2884 enum intel_ddb_partitioning partitioning;
2885 struct intel_pipe_wm pipe_wm = {};
2886 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
2887 struct intel_wm_config config = {};
2888
2889 ilk_compute_wm_parameters(crtc, &params);
2890
2891 intel_compute_pipe_wm(crtc, &params, &pipe_wm);
2892
2893 if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
2894 return;
2895
2896 intel_crtc->wm.active = pipe_wm;
2897
2898 ilk_compute_wm_config(dev, &config);
2899
2900 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
2901 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
2902
2903 /* 5/6 split only in single pipe config on IVB+ */
2904 if (INTEL_INFO(dev)->gen >= 7 &&
2905 config.num_pipes_active == 1 && config.sprites_enabled) {
2906 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
2907 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
2908
2909 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
2910 } else {
2911 best_lp_wm = &lp_wm_1_2;
2912 }
2913
2914 partitioning = (best_lp_wm == &lp_wm_1_2) ?
2915 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
2916
2917 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
2918
2919 ilk_write_wm_values(dev_priv, &results);
2920 }
2921
2922 static void
2923 ilk_update_sprite_wm(struct drm_plane *plane,
2924 struct drm_crtc *crtc,
2925 uint32_t sprite_width, uint32_t sprite_height,
2926 int pixel_size, bool enabled, bool scaled)
2927 {
2928 struct drm_device *dev = plane->dev;
2929 struct intel_plane *intel_plane = to_intel_plane(plane);
2930
2931 intel_plane->wm.enabled = enabled;
2932 intel_plane->wm.scaled = scaled;
2933 intel_plane->wm.horiz_pixels = sprite_width;
2934 intel_plane->wm.vert_pixels = sprite_width;
2935 intel_plane->wm.bytes_per_pixel = pixel_size;
2936
2937 /*
2938 * IVB workaround: must disable low power watermarks for at least
2939 * one frame before enabling scaling. LP watermarks can be re-enabled
2940 * when scaling is disabled.
2941 *
2942 * WaCxSRDisabledForSpriteScaling:ivb
2943 */
2944 if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev))
2945 intel_wait_for_vblank(dev, intel_plane->pipe);
2946
2947 ilk_update_wm(crtc);
2948 }
2949
2950 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
2951 {
2952 struct drm_device *dev = crtc->dev;
2953 struct drm_i915_private *dev_priv = dev->dev_private;
2954 struct ilk_wm_values *hw = &dev_priv->wm.hw;
2955 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2956 struct intel_pipe_wm *active = &intel_crtc->wm.active;
2957 enum pipe pipe = intel_crtc->pipe;
2958 static const unsigned int wm0_pipe_reg[] = {
2959 [PIPE_A] = WM0_PIPEA_ILK,
2960 [PIPE_B] = WM0_PIPEB_ILK,
2961 [PIPE_C] = WM0_PIPEC_IVB,
2962 };
2963
2964 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
2965 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2966 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
2967
2968 active->pipe_enabled = intel_crtc_active(crtc);
2969
2970 if (active->pipe_enabled) {
2971 u32 tmp = hw->wm_pipe[pipe];
2972
2973 /*
2974 * For active pipes LP0 watermark is marked as
2975 * enabled, and LP1+ watermaks as disabled since
2976 * we can't really reverse compute them in case
2977 * multiple pipes are active.
2978 */
2979 active->wm[0].enable = true;
2980 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
2981 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
2982 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
2983 active->linetime = hw->wm_linetime[pipe];
2984 } else {
2985 int level, max_level = ilk_wm_max_level(dev);
2986
2987 /*
2988 * For inactive pipes, all watermark levels
2989 * should be marked as enabled but zeroed,
2990 * which is what we'd compute them to.
2991 */
2992 for (level = 0; level <= max_level; level++)
2993 active->wm[level].enable = true;
2994 }
2995 }
2996
2997 void ilk_wm_get_hw_state(struct drm_device *dev)
2998 {
2999 struct drm_i915_private *dev_priv = dev->dev_private;
3000 struct ilk_wm_values *hw = &dev_priv->wm.hw;
3001 struct drm_crtc *crtc;
3002
3003 for_each_crtc(dev, crtc)
3004 ilk_pipe_wm_get_hw_state(crtc);
3005
3006 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
3007 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
3008 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
3009
3010 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
3011 if (INTEL_INFO(dev)->gen >= 7) {
3012 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
3013 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
3014 }
3015
3016 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3017 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
3018 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
3019 else if (IS_IVYBRIDGE(dev))
3020 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
3021 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
3022
3023 hw->enable_fbc_wm =
3024 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
3025 }
3026
3027 /**
3028 * intel_update_watermarks - update FIFO watermark values based on current modes
3029 *
3030 * Calculate watermark values for the various WM regs based on current mode
3031 * and plane configuration.
3032 *
3033 * There are several cases to deal with here:
3034 * - normal (i.e. non-self-refresh)
3035 * - self-refresh (SR) mode
3036 * - lines are large relative to FIFO size (buffer can hold up to 2)
3037 * - lines are small relative to FIFO size (buffer can hold more than 2
3038 * lines), so need to account for TLB latency
3039 *
3040 * The normal calculation is:
3041 * watermark = dotclock * bytes per pixel * latency
3042 * where latency is platform & configuration dependent (we assume pessimal
3043 * values here).
3044 *
3045 * The SR calculation is:
3046 * watermark = (trunc(latency/line time)+1) * surface width *
3047 * bytes per pixel
3048 * where
3049 * line time = htotal / dotclock
3050 * surface width = hdisplay for normal plane and 64 for cursor
3051 * and latency is assumed to be high, as above.
3052 *
3053 * The final value programmed to the register should always be rounded up,
3054 * and include an extra 2 entries to account for clock crossings.
3055 *
3056 * We don't use the sprite, so we can ignore that. And on Crestline we have
3057 * to set the non-SR watermarks to 8.
3058 */
3059 void intel_update_watermarks(struct drm_crtc *crtc)
3060 {
3061 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
3062
3063 if (dev_priv->display.update_wm)
3064 dev_priv->display.update_wm(crtc);
3065 }
3066
3067 void intel_update_sprite_watermarks(struct drm_plane *plane,
3068 struct drm_crtc *crtc,
3069 uint32_t sprite_width,
3070 uint32_t sprite_height,
3071 int pixel_size,
3072 bool enabled, bool scaled)
3073 {
3074 struct drm_i915_private *dev_priv = plane->dev->dev_private;
3075
3076 if (dev_priv->display.update_sprite_wm)
3077 dev_priv->display.update_sprite_wm(plane, crtc,
3078 sprite_width, sprite_height,
3079 pixel_size, enabled, scaled);
3080 }
3081
3082 static struct drm_i915_gem_object *
3083 intel_alloc_context_page(struct drm_device *dev)
3084 {
3085 struct drm_i915_gem_object *ctx;
3086 int ret;
3087
3088 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3089
3090 ctx = i915_gem_alloc_object(dev, 4096);
3091 if (!ctx) {
3092 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
3093 return NULL;
3094 }
3095
3096 ret = i915_gem_obj_ggtt_pin(ctx, 4096, 0);
3097 if (ret) {
3098 DRM_ERROR("failed to pin power context: %d\n", ret);
3099 goto err_unref;
3100 }
3101
3102 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
3103 if (ret) {
3104 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
3105 goto err_unpin;
3106 }
3107
3108 return ctx;
3109
3110 err_unpin:
3111 i915_gem_object_ggtt_unpin(ctx);
3112 err_unref:
3113 drm_gem_object_unreference(&ctx->base);
3114 return NULL;
3115 }
3116
3117 /**
3118 * Lock protecting IPS related data structures
3119 */
3120 DEFINE_SPINLOCK(mchdev_lock);
3121
3122 /* Global for IPS driver to get at the current i915 device. Protected by
3123 * mchdev_lock. */
3124 static struct drm_i915_private *i915_mch_dev;
3125
3126 bool ironlake_set_drps(struct drm_device *dev, u8 val)
3127 {
3128 struct drm_i915_private *dev_priv = dev->dev_private;
3129 u16 rgvswctl;
3130
3131 assert_spin_locked(&mchdev_lock);
3132
3133 rgvswctl = I915_READ16(MEMSWCTL);
3134 if (rgvswctl & MEMCTL_CMD_STS) {
3135 DRM_DEBUG("gpu busy, RCS change rejected\n");
3136 return false; /* still busy with another command */
3137 }
3138
3139 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
3140 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
3141 I915_WRITE16(MEMSWCTL, rgvswctl);
3142 POSTING_READ16(MEMSWCTL);
3143
3144 rgvswctl |= MEMCTL_CMD_STS;
3145 I915_WRITE16(MEMSWCTL, rgvswctl);
3146
3147 return true;
3148 }
3149
3150 static void ironlake_enable_drps(struct drm_device *dev)
3151 {
3152 struct drm_i915_private *dev_priv = dev->dev_private;
3153 u32 rgvmodectl = I915_READ(MEMMODECTL);
3154 u8 fmax, fmin, fstart, vstart;
3155
3156 spin_lock_irq(&mchdev_lock);
3157
3158 /* Enable temp reporting */
3159 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
3160 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
3161
3162 /* 100ms RC evaluation intervals */
3163 I915_WRITE(RCUPEI, 100000);
3164 I915_WRITE(RCDNEI, 100000);
3165
3166 /* Set max/min thresholds to 90ms and 80ms respectively */
3167 I915_WRITE(RCBMAXAVG, 90000);
3168 I915_WRITE(RCBMINAVG, 80000);
3169
3170 I915_WRITE(MEMIHYST, 1);
3171
3172 /* Set up min, max, and cur for interrupt handling */
3173 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
3174 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
3175 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
3176 MEMMODE_FSTART_SHIFT;
3177
3178 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
3179 PXVFREQ_PX_SHIFT;
3180
3181 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
3182 dev_priv->ips.fstart = fstart;
3183
3184 dev_priv->ips.max_delay = fstart;
3185 dev_priv->ips.min_delay = fmin;
3186 dev_priv->ips.cur_delay = fstart;
3187
3188 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
3189 fmax, fmin, fstart);
3190
3191 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
3192
3193 /*
3194 * Interrupts will be enabled in ironlake_irq_postinstall
3195 */
3196
3197 I915_WRITE(VIDSTART, vstart);
3198 POSTING_READ(VIDSTART);
3199
3200 rgvmodectl |= MEMMODE_SWMODE_EN;
3201 I915_WRITE(MEMMODECTL, rgvmodectl);
3202
3203 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
3204 DRM_ERROR("stuck trying to change perf mode\n");
3205 mdelay(1);
3206
3207 ironlake_set_drps(dev, fstart);
3208
3209 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
3210 I915_READ(0x112e0);
3211 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
3212 dev_priv->ips.last_count2 = I915_READ(0x112f4);
3213 dev_priv->ips.last_time2 = ktime_get_raw_ns();
3214
3215 spin_unlock_irq(&mchdev_lock);
3216 }
3217
3218 static void ironlake_disable_drps(struct drm_device *dev)
3219 {
3220 struct drm_i915_private *dev_priv = dev->dev_private;
3221 u16 rgvswctl;
3222
3223 spin_lock_irq(&mchdev_lock);
3224
3225 rgvswctl = I915_READ16(MEMSWCTL);
3226
3227 /* Ack interrupts, disable EFC interrupt */
3228 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
3229 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
3230 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
3231 I915_WRITE(DEIIR, DE_PCU_EVENT);
3232 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
3233
3234 /* Go back to the starting frequency */
3235 ironlake_set_drps(dev, dev_priv->ips.fstart);
3236 mdelay(1);
3237 rgvswctl |= MEMCTL_CMD_STS;
3238 I915_WRITE(MEMSWCTL, rgvswctl);
3239 mdelay(1);
3240
3241 spin_unlock_irq(&mchdev_lock);
3242 }
3243
3244 /* There's a funny hw issue where the hw returns all 0 when reading from
3245 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3246 * ourselves, instead of doing a rmw cycle (which might result in us clearing
3247 * all limits and the gpu stuck at whatever frequency it is at atm).
3248 */
3249 static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)
3250 {
3251 u32 limits;
3252
3253 /* Only set the down limit when we've reached the lowest level to avoid
3254 * getting more interrupts, otherwise leave this clear. This prevents a
3255 * race in the hw when coming out of rc6: There's a tiny window where
3256 * the hw runs at the minimal clock before selecting the desired
3257 * frequency, if the down threshold expires in that window we will not
3258 * receive a down interrupt. */
3259 limits = dev_priv->rps.max_freq_softlimit << 24;
3260 if (val <= dev_priv->rps.min_freq_softlimit)
3261 limits |= dev_priv->rps.min_freq_softlimit << 16;
3262
3263 return limits;
3264 }
3265
3266 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
3267 {
3268 int new_power;
3269
3270 if (dev_priv->rps.is_bdw_sw_turbo)
3271 return;
3272
3273 new_power = dev_priv->rps.power;
3274 switch (dev_priv->rps.power) {
3275 case LOW_POWER:
3276 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
3277 new_power = BETWEEN;
3278 break;
3279
3280 case BETWEEN:
3281 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
3282 new_power = LOW_POWER;
3283 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
3284 new_power = HIGH_POWER;
3285 break;
3286
3287 case HIGH_POWER:
3288 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
3289 new_power = BETWEEN;
3290 break;
3291 }
3292 /* Max/min bins are special */
3293 if (val == dev_priv->rps.min_freq_softlimit)
3294 new_power = LOW_POWER;
3295 if (val == dev_priv->rps.max_freq_softlimit)
3296 new_power = HIGH_POWER;
3297 if (new_power == dev_priv->rps.power)
3298 return;
3299
3300 /* Note the units here are not exactly 1us, but 1280ns. */
3301 switch (new_power) {
3302 case LOW_POWER:
3303 /* Upclock if more than 95% busy over 16ms */
3304 I915_WRITE(GEN6_RP_UP_EI, 12500);
3305 I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800);
3306
3307 /* Downclock if less than 85% busy over 32ms */
3308 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3309 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250);
3310
3311 I915_WRITE(GEN6_RP_CONTROL,
3312 GEN6_RP_MEDIA_TURBO |
3313 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3314 GEN6_RP_MEDIA_IS_GFX |
3315 GEN6_RP_ENABLE |
3316 GEN6_RP_UP_BUSY_AVG |
3317 GEN6_RP_DOWN_IDLE_AVG);
3318 break;
3319
3320 case BETWEEN:
3321 /* Upclock if more than 90% busy over 13ms */
3322 I915_WRITE(GEN6_RP_UP_EI, 10250);
3323 I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225);
3324
3325 /* Downclock if less than 75% busy over 32ms */
3326 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3327 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750);
3328
3329 I915_WRITE(GEN6_RP_CONTROL,
3330 GEN6_RP_MEDIA_TURBO |
3331 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3332 GEN6_RP_MEDIA_IS_GFX |
3333 GEN6_RP_ENABLE |
3334 GEN6_RP_UP_BUSY_AVG |
3335 GEN6_RP_DOWN_IDLE_AVG);
3336 break;
3337
3338 case HIGH_POWER:
3339 /* Upclock if more than 85% busy over 10ms */
3340 I915_WRITE(GEN6_RP_UP_EI, 8000);
3341 I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800);
3342
3343 /* Downclock if less than 60% busy over 32ms */
3344 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3345 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000);
3346
3347 I915_WRITE(GEN6_RP_CONTROL,
3348 GEN6_RP_MEDIA_TURBO |
3349 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3350 GEN6_RP_MEDIA_IS_GFX |
3351 GEN6_RP_ENABLE |
3352 GEN6_RP_UP_BUSY_AVG |
3353 GEN6_RP_DOWN_IDLE_AVG);
3354 break;
3355 }
3356
3357 dev_priv->rps.power = new_power;
3358 dev_priv->rps.last_adj = 0;
3359 }
3360
3361 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
3362 {
3363 u32 mask = 0;
3364
3365 if (val > dev_priv->rps.min_freq_softlimit)
3366 mask |= GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
3367 if (val < dev_priv->rps.max_freq_softlimit)
3368 mask |= GEN6_PM_RP_UP_THRESHOLD;
3369
3370 mask |= dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED);
3371 mask &= dev_priv->pm_rps_events;
3372
3373 /* IVB and SNB hard hangs on looping batchbuffer
3374 * if GEN6_PM_UP_EI_EXPIRED is masked.
3375 */
3376 if (INTEL_INFO(dev_priv->dev)->gen <= 7 && !IS_HASWELL(dev_priv->dev))
3377 mask |= GEN6_PM_RP_UP_EI_EXPIRED;
3378
3379 if (IS_GEN8(dev_priv->dev))
3380 mask |= GEN8_PMINTR_REDIRECT_TO_NON_DISP;
3381
3382 return ~mask;
3383 }
3384
3385 /* gen6_set_rps is called to update the frequency request, but should also be
3386 * called when the range (min_delay and max_delay) is modified so that we can
3387 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
3388 void gen6_set_rps(struct drm_device *dev, u8 val)
3389 {
3390 struct drm_i915_private *dev_priv = dev->dev_private;
3391
3392 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3393 WARN_ON(val > dev_priv->rps.max_freq_softlimit);
3394 WARN_ON(val < dev_priv->rps.min_freq_softlimit);
3395
3396 /* min/max delay may still have been modified so be sure to
3397 * write the limits value.
3398 */
3399 if (val != dev_priv->rps.cur_freq) {
3400 gen6_set_rps_thresholds(dev_priv, val);
3401
3402 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3403 I915_WRITE(GEN6_RPNSWREQ,
3404 HSW_FREQUENCY(val));
3405 else
3406 I915_WRITE(GEN6_RPNSWREQ,
3407 GEN6_FREQUENCY(val) |
3408 GEN6_OFFSET(0) |
3409 GEN6_AGGRESSIVE_TURBO);
3410 }
3411
3412 /* Make sure we continue to get interrupts
3413 * until we hit the minimum or maximum frequencies.
3414 */
3415 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, gen6_rps_limits(dev_priv, val));
3416 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
3417
3418 POSTING_READ(GEN6_RPNSWREQ);
3419
3420 dev_priv->rps.cur_freq = val;
3421 trace_intel_gpu_freq_change(val * 50);
3422 }
3423
3424 /* vlv_set_rps_idle: Set the frequency to Rpn if Gfx clocks are down
3425 *
3426 * * If Gfx is Idle, then
3427 * 1. Mask Turbo interrupts
3428 * 2. Bring up Gfx clock
3429 * 3. Change the freq to Rpn and wait till P-Unit updates freq
3430 * 4. Clear the Force GFX CLK ON bit so that Gfx can down
3431 * 5. Unmask Turbo interrupts
3432 */
3433 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
3434 {
3435 struct drm_device *dev = dev_priv->dev;
3436
3437 /* Latest VLV doesn't need to force the gfx clock */
3438 if (dev->pdev->revision >= 0xd) {
3439 valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3440 return;
3441 }
3442
3443 /*
3444 * When we are idle. Drop to min voltage state.
3445 */
3446
3447 if (dev_priv->rps.cur_freq <= dev_priv->rps.min_freq_softlimit)
3448 return;
3449
3450 /* Mask turbo interrupt so that they will not come in between */
3451 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3452
3453 vlv_force_gfx_clock(dev_priv, true);
3454
3455 dev_priv->rps.cur_freq = dev_priv->rps.min_freq_softlimit;
3456
3457 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ,
3458 dev_priv->rps.min_freq_softlimit);
3459
3460 if (wait_for(((vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS))
3461 & GENFREQSTATUS) == 0, 5))
3462 DRM_ERROR("timed out waiting for Punit\n");
3463
3464 vlv_force_gfx_clock(dev_priv, false);
3465
3466 I915_WRITE(GEN6_PMINTRMSK,
3467 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
3468 }
3469
3470 void gen6_rps_idle(struct drm_i915_private *dev_priv)
3471 {
3472 struct drm_device *dev = dev_priv->dev;
3473
3474 mutex_lock(&dev_priv->rps.hw_lock);
3475 if (dev_priv->rps.enabled) {
3476 if (IS_CHERRYVIEW(dev))
3477 valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3478 else if (IS_VALLEYVIEW(dev))
3479 vlv_set_rps_idle(dev_priv);
3480 else if (!dev_priv->rps.is_bdw_sw_turbo
3481 || atomic_read(&dev_priv->rps.sw_turbo.flip_received)){
3482 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3483 }
3484
3485 dev_priv->rps.last_adj = 0;
3486 }
3487 mutex_unlock(&dev_priv->rps.hw_lock);
3488 }
3489
3490 void gen6_rps_boost(struct drm_i915_private *dev_priv)
3491 {
3492 struct drm_device *dev = dev_priv->dev;
3493
3494 mutex_lock(&dev_priv->rps.hw_lock);
3495 if (dev_priv->rps.enabled) {
3496 if (IS_VALLEYVIEW(dev))
3497 valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
3498 else if (!dev_priv->rps.is_bdw_sw_turbo
3499 || atomic_read(&dev_priv->rps.sw_turbo.flip_received)){
3500 gen6_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
3501 }
3502
3503 dev_priv->rps.last_adj = 0;
3504 }
3505 mutex_unlock(&dev_priv->rps.hw_lock);
3506 }
3507
3508 void valleyview_set_rps(struct drm_device *dev, u8 val)
3509 {
3510 struct drm_i915_private *dev_priv = dev->dev_private;
3511
3512 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3513 WARN_ON(val > dev_priv->rps.max_freq_softlimit);
3514 WARN_ON(val < dev_priv->rps.min_freq_softlimit);
3515
3516 DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
3517 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
3518 dev_priv->rps.cur_freq,
3519 vlv_gpu_freq(dev_priv, val), val);
3520
3521 if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1),
3522 "Odd GPU freq value\n"))
3523 val &= ~1;
3524
3525 if (val != dev_priv->rps.cur_freq)
3526 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
3527
3528 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
3529
3530 dev_priv->rps.cur_freq = val;
3531 trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val));
3532 }
3533
3534 static void gen8_disable_rps_interrupts(struct drm_device *dev)
3535 {
3536 struct drm_i915_private *dev_priv = dev->dev_private;
3537 if (IS_BROADWELL(dev) && dev_priv->rps.is_bdw_sw_turbo){
3538 if (atomic_read(&dev_priv->rps.sw_turbo.flip_received))
3539 del_timer(&dev_priv->rps.sw_turbo.flip_timer);
3540 dev_priv-> rps.is_bdw_sw_turbo = false;
3541 } else {
3542 I915_WRITE(GEN6_PMINTRMSK, ~GEN8_PMINTR_REDIRECT_TO_NON_DISP);
3543 I915_WRITE(GEN8_GT_IER(2), I915_READ(GEN8_GT_IER(2)) &
3544 ~dev_priv->pm_rps_events);
3545 /* Complete PM interrupt masking here doesn't race with the rps work
3546 * item again unmasking PM interrupts because that is using a different
3547 * register (GEN8_GT_IMR(2)) to mask PM interrupts. The only risk is in
3548 * leaving stale bits in GEN8_GT_IIR(2) and GEN8_GT_IMR(2) which
3549 * gen8_enable_rps will clean up. */
3550
3551 spin_lock_irq(&dev_priv->irq_lock);
3552 dev_priv->rps.pm_iir = 0;
3553 spin_unlock_irq(&dev_priv->irq_lock);
3554
3555 I915_WRITE(GEN8_GT_IIR(2), dev_priv->pm_rps_events);
3556 }
3557 }
3558
3559 static void gen6_disable_rps_interrupts(struct drm_device *dev)
3560 {
3561 struct drm_i915_private *dev_priv = dev->dev_private;
3562
3563 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3564 I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) &
3565 ~dev_priv->pm_rps_events);
3566 /* Complete PM interrupt masking here doesn't race with the rps work
3567 * item again unmasking PM interrupts because that is using a different
3568 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3569 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3570
3571 spin_lock_irq(&dev_priv->irq_lock);
3572 dev_priv->rps.pm_iir = 0;
3573 spin_unlock_irq(&dev_priv->irq_lock);
3574
3575 I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events);
3576 }
3577
3578 static void gen6_disable_rps(struct drm_device *dev)
3579 {
3580 struct drm_i915_private *dev_priv = dev->dev_private;
3581
3582 I915_WRITE(GEN6_RC_CONTROL, 0);
3583 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
3584
3585 if (IS_BROADWELL(dev))
3586 gen8_disable_rps_interrupts(dev);
3587 else
3588 gen6_disable_rps_interrupts(dev);
3589 }
3590
3591 static void cherryview_disable_rps(struct drm_device *dev)
3592 {
3593 struct drm_i915_private *dev_priv = dev->dev_private;
3594
3595 I915_WRITE(GEN6_RC_CONTROL, 0);
3596
3597 gen8_disable_rps_interrupts(dev);
3598 }
3599
3600 static void valleyview_disable_rps(struct drm_device *dev)
3601 {
3602 struct drm_i915_private *dev_priv = dev->dev_private;
3603
3604 /* we're doing forcewake before Disabling RC6,
3605 * This what the BIOS expects when going into suspend */
3606 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3607
3608 I915_WRITE(GEN6_RC_CONTROL, 0);
3609
3610 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3611
3612 gen6_disable_rps_interrupts(dev);
3613 }
3614
3615 static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
3616 {
3617 if (IS_VALLEYVIEW(dev)) {
3618 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
3619 mode = GEN6_RC_CTL_RC6_ENABLE;
3620 else
3621 mode = 0;
3622 }
3623 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
3624 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3625 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3626 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
3627 }
3628
3629 static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
3630 {
3631 /* No RC6 before Ironlake */
3632 if (INTEL_INFO(dev)->gen < 5)
3633 return 0;
3634
3635 /* RC6 is only on Ironlake mobile not on desktop */
3636 if (INTEL_INFO(dev)->gen == 5 && !IS_IRONLAKE_M(dev))
3637 return 0;
3638
3639 /* Respect the kernel parameter if it is set */
3640 if (enable_rc6 >= 0) {
3641 int mask;
3642
3643 if (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
3644 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
3645 INTEL_RC6pp_ENABLE;
3646 else
3647 mask = INTEL_RC6_ENABLE;
3648
3649 if ((enable_rc6 & mask) != enable_rc6)
3650 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
3651 enable_rc6 & mask, enable_rc6, mask);
3652
3653 return enable_rc6 & mask;
3654 }
3655
3656 /* Disable RC6 on Ironlake */
3657 if (INTEL_INFO(dev)->gen == 5)
3658 return 0;
3659
3660 if (IS_IVYBRIDGE(dev))
3661 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
3662
3663 return INTEL_RC6_ENABLE;
3664 }
3665
3666 int intel_enable_rc6(const struct drm_device *dev)
3667 {
3668 return i915.enable_rc6;
3669 }
3670
3671 static void gen8_enable_rps_interrupts(struct drm_device *dev)
3672 {
3673 struct drm_i915_private *dev_priv = dev->dev_private;
3674
3675 spin_lock_irq(&dev_priv->irq_lock);
3676 WARN_ON(dev_priv->rps.pm_iir);
3677 gen8_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
3678 I915_WRITE(GEN8_GT_IIR(2), dev_priv->pm_rps_events);
3679 spin_unlock_irq(&dev_priv->irq_lock);
3680 }
3681
3682 static void gen6_enable_rps_interrupts(struct drm_device *dev)
3683 {
3684 struct drm_i915_private *dev_priv = dev->dev_private;
3685
3686 spin_lock_irq(&dev_priv->irq_lock);
3687 WARN_ON(dev_priv->rps.pm_iir);
3688 gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
3689 I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events);
3690 spin_unlock_irq(&dev_priv->irq_lock);
3691 }
3692
3693 static void parse_rp_state_cap(struct drm_i915_private *dev_priv, u32 rp_state_cap)
3694 {
3695 /* All of these values are in units of 50MHz */
3696 dev_priv->rps.cur_freq = 0;
3697 /* static values from HW: RP0 < RPe < RP1 < RPn (min_freq) */
3698 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
3699 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
3700 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
3701 /* XXX: only BYT has a special efficient freq */
3702 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
3703 /* hw_max = RP0 until we check for overclocking */
3704 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
3705
3706 /* Preserve min/max settings in case of re-init */
3707 if (dev_priv->rps.max_freq_softlimit == 0)
3708 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
3709
3710 if (dev_priv->rps.min_freq_softlimit == 0)
3711 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
3712 }
3713
3714 static void bdw_sw_calculate_freq(struct drm_device *dev,
3715 struct intel_rps_bdw_cal *c, u32 *cur_time, u32 *c0)
3716 {
3717 struct drm_i915_private *dev_priv = dev->dev_private;
3718 u64 busy = 0;
3719 u32 busyness_pct = 0;
3720 u32 elapsed_time = 0;
3721 u16 new_freq = 0;
3722
3723 if (!c || !cur_time || !c0)
3724 return;
3725
3726 if (0 == c->last_c0)
3727 goto out;
3728
3729 /* Check Evaluation interval */
3730 elapsed_time = *cur_time - c->last_ts;
3731 if (elapsed_time < c->eval_interval)
3732 return;
3733
3734 mutex_lock(&dev_priv->rps.hw_lock);
3735
3736 /*
3737 * c0 unit in 32*1.28 usec, elapsed_time unit in 1 usec.
3738 * Whole busyness_pct calculation should be
3739 * busy = ((u64)(*c0 - c->last_c0) << 5 << 7) / 100;
3740 * busyness_pct = (u32)(busy * 100 / elapsed_time);
3741 * The final formula is to simplify CPU calculation
3742 */
3743 busy = (u64)(*c0 - c->last_c0) << 12;
3744 do_div(busy, elapsed_time);
3745 busyness_pct = (u32)busy;
3746
3747 if (c->is_up && busyness_pct >= c->it_threshold_pct)
3748 new_freq = (u16)dev_priv->rps.cur_freq + 3;
3749 if (!c->is_up && busyness_pct <= c->it_threshold_pct)
3750 new_freq = (u16)dev_priv->rps.cur_freq - 1;
3751
3752 /* Adjust to new frequency busyness and compare with threshold */
3753 if (0 != new_freq) {
3754 if (new_freq > dev_priv->rps.max_freq_softlimit)
3755 new_freq = dev_priv->rps.max_freq_softlimit;
3756 else if (new_freq < dev_priv->rps.min_freq_softlimit)
3757 new_freq = dev_priv->rps.min_freq_softlimit;
3758
3759 gen6_set_rps(dev, new_freq);
3760 }
3761
3762 mutex_unlock(&dev_priv->rps.hw_lock);
3763
3764 out:
3765 c->last_c0 = *c0;
3766 c->last_ts = *cur_time;
3767 }
3768
3769 static void gen8_set_frequency_RP0(struct work_struct *work)
3770 {
3771 struct intel_rps_bdw_turbo *p_bdw_turbo =
3772 container_of(work, struct intel_rps_bdw_turbo, work_max_freq);
3773 struct intel_gen6_power_mgmt *p_power_mgmt =
3774 container_of(p_bdw_turbo, struct intel_gen6_power_mgmt, sw_turbo);
3775 struct drm_i915_private *dev_priv =
3776 container_of(p_power_mgmt, struct drm_i915_private, rps);
3777
3778 mutex_lock(&dev_priv->rps.hw_lock);
3779 gen6_set_rps(dev_priv->dev, dev_priv->rps.rp0_freq);
3780 mutex_unlock(&dev_priv->rps.hw_lock);
3781 }
3782
3783 static void flip_active_timeout_handler(unsigned long var)
3784 {
3785 struct drm_i915_private *dev_priv = (struct drm_i915_private *) var;
3786
3787 del_timer(&dev_priv->rps.sw_turbo.flip_timer);
3788 atomic_set(&dev_priv->rps.sw_turbo.flip_received, false);
3789
3790 queue_work(dev_priv->wq, &dev_priv->rps.sw_turbo.work_max_freq);
3791 }
3792
3793 void bdw_software_turbo(struct drm_device *dev)
3794 {
3795 struct drm_i915_private *dev_priv = dev->dev_private;
3796
3797 u32 current_time = I915_READ(TIMESTAMP_CTR); /* unit in usec */
3798 u32 current_c0 = I915_READ(MCHBAR_PCU_C0); /* unit in 32*1.28 usec */
3799
3800 bdw_sw_calculate_freq(dev, &dev_priv->rps.sw_turbo.up,
3801 &current_time, &current_c0);
3802 bdw_sw_calculate_freq(dev, &dev_priv->rps.sw_turbo.down,
3803 &current_time, &current_c0);
3804 }
3805
3806 static void gen8_enable_rps(struct drm_device *dev)
3807 {
3808 struct drm_i915_private *dev_priv = dev->dev_private;
3809 struct intel_engine_cs *ring;
3810 uint32_t rc6_mask = 0, rp_state_cap;
3811 uint32_t threshold_up_pct, threshold_down_pct;
3812 uint32_t ei_up, ei_down; /* up and down evaluation interval */
3813 u32 rp_ctl_flag;
3814 int unused;
3815
3816 /* Use software Turbo for BDW */
3817 dev_priv->rps.is_bdw_sw_turbo = IS_BROADWELL(dev);
3818
3819 /* 1a: Software RC state - RC0 */
3820 I915_WRITE(GEN6_RC_STATE, 0);
3821
3822 /* 1c & 1d: Get forcewake during program sequence. Although the driver
3823 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
3824 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3825
3826 /* 2a: Disable RC states. */
3827 I915_WRITE(GEN6_RC_CONTROL, 0);
3828
3829 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3830 parse_rp_state_cap(dev_priv, rp_state_cap);
3831
3832 /* 2b: Program RC6 thresholds.*/
3833 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
3834 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
3835 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
3836 for_each_ring(ring, dev_priv, unused)
3837 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3838 I915_WRITE(GEN6_RC_SLEEP, 0);
3839 if (IS_BROADWELL(dev))
3840 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
3841 else
3842 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
3843
3844 /* 3: Enable RC6 */
3845 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
3846 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
3847 intel_print_rc6_info(dev, rc6_mask);
3848 if (IS_BROADWELL(dev))
3849 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
3850 GEN7_RC_CTL_TO_MODE |
3851 rc6_mask);
3852 else
3853 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
3854 GEN6_RC_CTL_EI_MODE(1) |
3855 rc6_mask);
3856
3857 /* 4 Program defaults and thresholds for RPS*/
3858 I915_WRITE(GEN6_RPNSWREQ,
3859 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
3860 I915_WRITE(GEN6_RC_VIDEO_FREQ,
3861 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
3862 ei_up = 84480; /* 84.48ms */
3863 ei_down = 448000;
3864 threshold_up_pct = 90; /* x percent busy */
3865 threshold_down_pct = 70;
3866
3867 if (dev_priv->rps.is_bdw_sw_turbo) {
3868 dev_priv->rps.sw_turbo.up.it_threshold_pct = threshold_up_pct;
3869 dev_priv->rps.sw_turbo.up.eval_interval = ei_up;
3870 dev_priv->rps.sw_turbo.up.is_up = true;
3871 dev_priv->rps.sw_turbo.up.last_ts = 0;
3872 dev_priv->rps.sw_turbo.up.last_c0 = 0;
3873
3874 dev_priv->rps.sw_turbo.down.it_threshold_pct = threshold_down_pct;
3875 dev_priv->rps.sw_turbo.down.eval_interval = ei_down;
3876 dev_priv->rps.sw_turbo.down.is_up = false;
3877 dev_priv->rps.sw_turbo.down.last_ts = 0;
3878 dev_priv->rps.sw_turbo.down.last_c0 = 0;
3879
3880 /* Start the timer to track if flip comes*/
3881 dev_priv->rps.sw_turbo.timeout = 200*1000; /* in us */
3882
3883 init_timer(&dev_priv->rps.sw_turbo.flip_timer);
3884 dev_priv->rps.sw_turbo.flip_timer.function = flip_active_timeout_handler;
3885 dev_priv->rps.sw_turbo.flip_timer.data = (unsigned long) dev_priv;
3886 dev_priv->rps.sw_turbo.flip_timer.expires =
3887 usecs_to_jiffies(dev_priv->rps.sw_turbo.timeout) + jiffies;
3888 add_timer(&dev_priv->rps.sw_turbo.flip_timer);
3889 INIT_WORK(&dev_priv->rps.sw_turbo.work_max_freq, gen8_set_frequency_RP0);
3890
3891 atomic_set(&dev_priv->rps.sw_turbo.flip_received, true);
3892 } else {
3893 /* NB: Docs say 1s, and 1000000 - which aren't equivalent
3894 * 1 second timeout*/
3895 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, FREQ_1_28_US(1000000));
3896
3897 /* Docs recommend 900MHz, and 300 MHz respectively */
3898 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
3899 dev_priv->rps.max_freq_softlimit << 24 |
3900 dev_priv->rps.min_freq_softlimit << 16);
3901
3902 I915_WRITE(GEN6_RP_UP_THRESHOLD,
3903 FREQ_1_28_US(ei_up * threshold_up_pct / 100));
3904 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
3905 FREQ_1_28_US(ei_down * threshold_down_pct / 100));
3906 I915_WRITE(GEN6_RP_UP_EI,
3907 FREQ_1_28_US(ei_up));
3908 I915_WRITE(GEN6_RP_DOWN_EI,
3909 FREQ_1_28_US(ei_down));
3910
3911 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3912 }
3913
3914 /* 5: Enable RPS */
3915 rp_ctl_flag = GEN6_RP_MEDIA_TURBO |
3916 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3917 GEN6_RP_MEDIA_IS_GFX |
3918 GEN6_RP_UP_BUSY_AVG |
3919 GEN6_RP_DOWN_IDLE_AVG;
3920 if (!dev_priv->rps.is_bdw_sw_turbo)
3921 rp_ctl_flag |= GEN6_RP_ENABLE;
3922
3923 I915_WRITE(GEN6_RP_CONTROL, rp_ctl_flag);
3924
3925 /* 6: Ring frequency + overclocking
3926 * (our driver does this later */
3927 gen6_set_rps(dev, (I915_READ(GEN6_GT_PERF_STATUS) & 0xff00) >> 8);
3928 if (!dev_priv->rps.is_bdw_sw_turbo)
3929 gen8_enable_rps_interrupts(dev);
3930
3931 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3932 }
3933
3934 static void gen6_enable_rps(struct drm_device *dev)
3935 {
3936 struct drm_i915_private *dev_priv = dev->dev_private;
3937 struct intel_engine_cs *ring;
3938 u32 rp_state_cap;
3939 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
3940 u32 gtfifodbg;
3941 int rc6_mode;
3942 int i, ret;
3943
3944 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3945
3946 /* Here begins a magic sequence of register writes to enable
3947 * auto-downclocking.
3948 *
3949 * Perhaps there might be some value in exposing these to
3950 * userspace...
3951 */
3952 I915_WRITE(GEN6_RC_STATE, 0);
3953
3954 /* Clear the DBG now so we don't confuse earlier errors */
3955 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3956 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3957 I915_WRITE(GTFIFODBG, gtfifodbg);
3958 }
3959
3960 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3961
3962 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3963
3964 parse_rp_state_cap(dev_priv, rp_state_cap);
3965
3966 /* disable the counters and set deterministic thresholds */
3967 I915_WRITE(GEN6_RC_CONTROL, 0);
3968
3969 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
3970 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
3971 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
3972 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3973 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3974
3975 for_each_ring(ring, dev_priv, i)
3976 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3977
3978 I915_WRITE(GEN6_RC_SLEEP, 0);
3979 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
3980 if (IS_IVYBRIDGE(dev))
3981 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
3982 else
3983 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
3984 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
3985 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
3986
3987 /* Check if we are enabling RC6 */
3988 rc6_mode = intel_enable_rc6(dev_priv->dev);
3989 if (rc6_mode & INTEL_RC6_ENABLE)
3990 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
3991
3992 /* We don't use those on Haswell */
3993 if (!IS_HASWELL(dev)) {
3994 if (rc6_mode & INTEL_RC6p_ENABLE)
3995 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
3996
3997 if (rc6_mode & INTEL_RC6pp_ENABLE)
3998 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
3999 }
4000
4001 intel_print_rc6_info(dev, rc6_mask);
4002
4003 I915_WRITE(GEN6_RC_CONTROL,
4004 rc6_mask |
4005 GEN6_RC_CTL_EI_MODE(1) |
4006 GEN6_RC_CTL_HW_ENABLE);
4007
4008 /* Power down if completely idle for over 50ms */
4009 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
4010 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4011
4012 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
4013 if (ret)
4014 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
4015
4016 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
4017 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
4018 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
4019 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
4020 (pcu_mbox & 0xff) * 50);
4021 dev_priv->rps.max_freq = pcu_mbox & 0xff;
4022 }
4023
4024 dev_priv->rps.power = HIGH_POWER; /* force a reset */
4025 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
4026
4027 gen6_enable_rps_interrupts(dev);
4028
4029 rc6vids = 0;
4030 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
4031 if (IS_GEN6(dev) && ret) {
4032 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
4033 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
4034 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
4035 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
4036 rc6vids &= 0xffff00;
4037 rc6vids |= GEN6_ENCODE_RC6_VID(450);
4038 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
4039 if (ret)
4040 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
4041 }
4042
4043 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
4044 }
4045
4046 static void __gen6_update_ring_freq(struct drm_device *dev)
4047 {
4048 struct drm_i915_private *dev_priv = dev->dev_private;
4049 int min_freq = 15;
4050 unsigned int gpu_freq;
4051 unsigned int max_ia_freq, min_ring_freq;
4052 int scaling_factor = 180;
4053 struct cpufreq_policy *policy;
4054
4055 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4056
4057 policy = cpufreq_cpu_get(0);
4058 if (policy) {
4059 max_ia_freq = policy->cpuinfo.max_freq;
4060 cpufreq_cpu_put(policy);
4061 } else {
4062 /*
4063 * Default to measured freq if none found, PCU will ensure we
4064 * don't go over
4065 */
4066 max_ia_freq = tsc_khz;
4067 }
4068
4069 /* Convert from kHz to MHz */
4070 max_ia_freq /= 1000;
4071
4072 min_ring_freq = I915_READ(DCLK) & 0xf;
4073 /* convert DDR frequency from units of 266.6MHz to bandwidth */
4074 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
4075
4076 /*
4077 * For each potential GPU frequency, load a ring frequency we'd like
4078 * to use for memory access. We do this by specifying the IA frequency
4079 * the PCU should use as a reference to determine the ring frequency.
4080 */
4081 for (gpu_freq = dev_priv->rps.max_freq_softlimit; gpu_freq >= dev_priv->rps.min_freq_softlimit;
4082 gpu_freq--) {
4083 int diff = dev_priv->rps.max_freq_softlimit - gpu_freq;
4084 unsigned int ia_freq = 0, ring_freq = 0;
4085
4086 if (INTEL_INFO(dev)->gen >= 8) {
4087 /* max(2 * GT, DDR). NB: GT is 50MHz units */
4088 ring_freq = max(min_ring_freq, gpu_freq);
4089 } else if (IS_HASWELL(dev)) {
4090 ring_freq = mult_frac(gpu_freq, 5, 4);
4091 ring_freq = max(min_ring_freq, ring_freq);
4092 /* leave ia_freq as the default, chosen by cpufreq */
4093 } else {
4094 /* On older processors, there is no separate ring
4095 * clock domain, so in order to boost the bandwidth
4096 * of the ring, we need to upclock the CPU (ia_freq).
4097 *
4098 * For GPU frequencies less than 750MHz,
4099 * just use the lowest ring freq.
4100 */
4101 if (gpu_freq < min_freq)
4102 ia_freq = 800;
4103 else
4104 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
4105 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
4106 }
4107
4108 sandybridge_pcode_write(dev_priv,
4109 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
4110 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
4111 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
4112 gpu_freq);
4113 }
4114 }
4115
4116 void gen6_update_ring_freq(struct drm_device *dev)
4117 {
4118 struct drm_i915_private *dev_priv = dev->dev_private;
4119
4120 if (INTEL_INFO(dev)->gen < 6 || IS_VALLEYVIEW(dev))
4121 return;
4122
4123 mutex_lock(&dev_priv->rps.hw_lock);
4124 __gen6_update_ring_freq(dev);
4125 mutex_unlock(&dev_priv->rps.hw_lock);
4126 }
4127
4128 static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
4129 {
4130 u32 val, rp0;
4131
4132 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
4133 rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & PUNIT_GPU_STATUS_MAX_FREQ_MASK;
4134
4135 return rp0;
4136 }
4137
4138 static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
4139 {
4140 u32 val, rpe;
4141
4142 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
4143 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
4144
4145 return rpe;
4146 }
4147
4148 static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
4149 {
4150 u32 val, rp1;
4151
4152 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4153 rp1 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & PUNIT_GPU_STATUS_MAX_FREQ_MASK;
4154
4155 return rp1;
4156 }
4157
4158 static int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
4159 {
4160 u32 val, rpn;
4161
4162 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
4163 rpn = (val >> PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT) & PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK;
4164 return rpn;
4165 }
4166
4167 static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
4168 {
4169 u32 val, rp1;
4170
4171 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
4172
4173 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
4174
4175 return rp1;
4176 }
4177
4178 static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
4179 {
4180 u32 val, rp0;
4181
4182 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
4183
4184 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
4185 /* Clamp to max */
4186 rp0 = min_t(u32, rp0, 0xea);
4187
4188 return rp0;
4189 }
4190
4191 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
4192 {
4193 u32 val, rpe;
4194
4195 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
4196 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
4197 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
4198 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
4199
4200 return rpe;
4201 }
4202
4203 static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
4204 {
4205 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
4206 }
4207
4208 /* Check that the pctx buffer wasn't move under us. */
4209 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
4210 {
4211 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
4212
4213 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
4214 dev_priv->vlv_pctx->stolen->start);
4215 }
4216
4217
4218 /* Check that the pcbr address is not empty. */
4219 static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
4220 {
4221 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
4222
4223 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
4224 }
4225
4226 static void cherryview_setup_pctx(struct drm_device *dev)
4227 {
4228 struct drm_i915_private *dev_priv = dev->dev_private;
4229 unsigned long pctx_paddr, paddr;
4230 struct i915_gtt *gtt = &dev_priv->gtt;
4231 u32 pcbr;
4232 int pctx_size = 32*1024;
4233
4234 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4235
4236 pcbr = I915_READ(VLV_PCBR);
4237 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
4238 paddr = (dev_priv->mm.stolen_base +
4239 (gtt->stolen_size - pctx_size));
4240
4241 pctx_paddr = (paddr & (~4095));
4242 I915_WRITE(VLV_PCBR, pctx_paddr);
4243 }
4244 }
4245
4246 static void valleyview_setup_pctx(struct drm_device *dev)
4247 {
4248 struct drm_i915_private *dev_priv = dev->dev_private;
4249 struct drm_i915_gem_object *pctx;
4250 unsigned long pctx_paddr;
4251 u32 pcbr;
4252 int pctx_size = 24*1024;
4253
4254 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4255
4256 pcbr = I915_READ(VLV_PCBR);
4257 if (pcbr) {
4258 /* BIOS set it up already, grab the pre-alloc'd space */
4259 int pcbr_offset;
4260
4261 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
4262 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
4263 pcbr_offset,
4264 I915_GTT_OFFSET_NONE,
4265 pctx_size);
4266 goto out;
4267 }
4268
4269 /*
4270 * From the Gunit register HAS:
4271 * The Gfx driver is expected to program this register and ensure
4272 * proper allocation within Gfx stolen memory. For example, this
4273 * register should be programmed such than the PCBR range does not
4274 * overlap with other ranges, such as the frame buffer, protected
4275 * memory, or any other relevant ranges.
4276 */
4277 pctx = i915_gem_object_create_stolen(dev, pctx_size);
4278 if (!pctx) {
4279 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
4280 return;
4281 }
4282
4283 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
4284 I915_WRITE(VLV_PCBR, pctx_paddr);
4285
4286 out:
4287 dev_priv->vlv_pctx = pctx;
4288 }
4289
4290 static void valleyview_cleanup_pctx(struct drm_device *dev)
4291 {
4292 struct drm_i915_private *dev_priv = dev->dev_private;
4293
4294 if (WARN_ON(!dev_priv->vlv_pctx))
4295 return;
4296
4297 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
4298 dev_priv->vlv_pctx = NULL;
4299 }
4300
4301 static void valleyview_init_gt_powersave(struct drm_device *dev)
4302 {
4303 struct drm_i915_private *dev_priv = dev->dev_private;
4304 u32 val;
4305
4306 valleyview_setup_pctx(dev);
4307
4308 mutex_lock(&dev_priv->rps.hw_lock);
4309
4310 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4311 switch ((val >> 6) & 3) {
4312 case 0:
4313 case 1:
4314 dev_priv->mem_freq = 800;
4315 break;
4316 case 2:
4317 dev_priv->mem_freq = 1066;
4318 break;
4319 case 3:
4320 dev_priv->mem_freq = 1333;
4321 break;
4322 }
4323 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
4324
4325 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
4326 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
4327 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
4328 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4329 dev_priv->rps.max_freq);
4330
4331 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
4332 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
4333 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4334 dev_priv->rps.efficient_freq);
4335
4336 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
4337 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
4338 vlv_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
4339 dev_priv->rps.rp1_freq);
4340
4341 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
4342 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
4343 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4344 dev_priv->rps.min_freq);
4345
4346 /* Preserve min/max settings in case of re-init */
4347 if (dev_priv->rps.max_freq_softlimit == 0)
4348 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4349
4350 if (dev_priv->rps.min_freq_softlimit == 0)
4351 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
4352
4353 mutex_unlock(&dev_priv->rps.hw_lock);
4354 }
4355
4356 static void cherryview_init_gt_powersave(struct drm_device *dev)
4357 {
4358 struct drm_i915_private *dev_priv = dev->dev_private;
4359 u32 val;
4360
4361 cherryview_setup_pctx(dev);
4362
4363 mutex_lock(&dev_priv->rps.hw_lock);
4364
4365 val = vlv_punit_read(dev_priv, CCK_FUSE_REG);
4366 switch ((val >> 2) & 0x7) {
4367 case 0:
4368 case 1:
4369 dev_priv->rps.cz_freq = 200;
4370 dev_priv->mem_freq = 1600;
4371 break;
4372 case 2:
4373 dev_priv->rps.cz_freq = 267;
4374 dev_priv->mem_freq = 1600;
4375 break;
4376 case 3:
4377 dev_priv->rps.cz_freq = 333;
4378 dev_priv->mem_freq = 2000;
4379 break;
4380 case 4:
4381 dev_priv->rps.cz_freq = 320;
4382 dev_priv->mem_freq = 1600;
4383 break;
4384 case 5:
4385 dev_priv->rps.cz_freq = 400;
4386 dev_priv->mem_freq = 1600;
4387 break;
4388 }
4389 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
4390
4391 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
4392 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
4393 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
4394 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4395 dev_priv->rps.max_freq);
4396
4397 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
4398 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
4399 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4400 dev_priv->rps.efficient_freq);
4401
4402 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
4403 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
4404 vlv_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
4405 dev_priv->rps.rp1_freq);
4406
4407 dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv);
4408 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
4409 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4410 dev_priv->rps.min_freq);
4411
4412 WARN_ONCE((dev_priv->rps.max_freq |
4413 dev_priv->rps.efficient_freq |
4414 dev_priv->rps.rp1_freq |
4415 dev_priv->rps.min_freq) & 1,
4416 "Odd GPU freq values\n");
4417
4418 /* Preserve min/max settings in case of re-init */
4419 if (dev_priv->rps.max_freq_softlimit == 0)
4420 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4421
4422 if (dev_priv->rps.min_freq_softlimit == 0)
4423 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
4424
4425 mutex_unlock(&dev_priv->rps.hw_lock);
4426 }
4427
4428 static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
4429 {
4430 valleyview_cleanup_pctx(dev);
4431 }
4432
4433 static void cherryview_enable_rps(struct drm_device *dev)
4434 {
4435 struct drm_i915_private *dev_priv = dev->dev_private;
4436 struct intel_engine_cs *ring;
4437 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
4438 int i;
4439
4440 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4441
4442 gtfifodbg = I915_READ(GTFIFODBG);
4443 if (gtfifodbg) {
4444 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4445 gtfifodbg);
4446 I915_WRITE(GTFIFODBG, gtfifodbg);
4447 }
4448
4449 cherryview_check_pctx(dev_priv);
4450
4451 /* 1a & 1b: Get forcewake during program sequence. Although the driver
4452 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4453 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
4454
4455 /* 2a: Program RC6 thresholds.*/
4456 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4457 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4458 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4459
4460 for_each_ring(ring, dev_priv, i)
4461 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4462 I915_WRITE(GEN6_RC_SLEEP, 0);
4463
4464 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
4465
4466 /* allows RC6 residency counter to work */
4467 I915_WRITE(VLV_COUNTER_CONTROL,
4468 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
4469 VLV_MEDIA_RC6_COUNT_EN |
4470 VLV_RENDER_RC6_COUNT_EN));
4471
4472 /* For now we assume BIOS is allocating and populating the PCBR */
4473 pcbr = I915_READ(VLV_PCBR);
4474
4475 DRM_DEBUG_DRIVER("PCBR offset : 0x%x\n", pcbr);
4476
4477 /* 3: Enable RC6 */
4478 if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
4479 (pcbr >> VLV_PCBR_ADDR_SHIFT))
4480 rc6_mode = GEN6_RC_CTL_EI_MODE(1);
4481
4482 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
4483
4484 /* 4 Program defaults and thresholds for RPS*/
4485 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
4486 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
4487 I915_WRITE(GEN6_RP_UP_EI, 66000);
4488 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
4489
4490 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4491
4492 /* WaDisablePwrmtrEvent:chv (pre-production hw) */
4493 I915_WRITE(0xA80C, I915_READ(0xA80C) & 0x00ffffff);
4494 I915_WRITE(0xA810, I915_READ(0xA810) & 0xffffff00);
4495
4496 /* 5: Enable RPS */
4497 I915_WRITE(GEN6_RP_CONTROL,
4498 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4499 GEN6_RP_MEDIA_IS_GFX | /* WaSetMaskForGfxBusyness:chv (pre-production hw ?) */
4500 GEN6_RP_ENABLE |
4501 GEN6_RP_UP_BUSY_AVG |
4502 GEN6_RP_DOWN_IDLE_AVG);
4503
4504 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4505
4506 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
4507 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
4508
4509 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
4510 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
4511 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
4512 dev_priv->rps.cur_freq);
4513
4514 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
4515 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4516 dev_priv->rps.efficient_freq);
4517
4518 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
4519
4520 gen8_enable_rps_interrupts(dev);
4521
4522 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
4523 }
4524
4525 static void valleyview_enable_rps(struct drm_device *dev)
4526 {
4527 struct drm_i915_private *dev_priv = dev->dev_private;
4528 struct intel_engine_cs *ring;
4529 u32 gtfifodbg, val, rc6_mode = 0;
4530 int i;
4531
4532 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4533
4534 valleyview_check_pctx(dev_priv);
4535
4536 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
4537 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4538 gtfifodbg);
4539 I915_WRITE(GTFIFODBG, gtfifodbg);
4540 }
4541
4542 /* If VLV, Forcewake all wells, else re-direct to regular path */
4543 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
4544
4545 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
4546 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
4547 I915_WRITE(GEN6_RP_UP_EI, 66000);
4548 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
4549
4550 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4551 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 0xf4240);
4552
4553 I915_WRITE(GEN6_RP_CONTROL,
4554 GEN6_RP_MEDIA_TURBO |
4555 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4556 GEN6_RP_MEDIA_IS_GFX |
4557 GEN6_RP_ENABLE |
4558 GEN6_RP_UP_BUSY_AVG |
4559 GEN6_RP_DOWN_IDLE_CONT);
4560
4561 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
4562 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4563 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4564
4565 for_each_ring(ring, dev_priv, i)
4566 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4567
4568 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
4569
4570 /* allows RC6 residency counter to work */
4571 I915_WRITE(VLV_COUNTER_CONTROL,
4572 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
4573 VLV_RENDER_RC0_COUNT_EN |
4574 VLV_MEDIA_RC6_COUNT_EN |
4575 VLV_RENDER_RC6_COUNT_EN));
4576
4577 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4578 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
4579
4580 intel_print_rc6_info(dev, rc6_mode);
4581
4582 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
4583
4584 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4585
4586 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
4587 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
4588
4589 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
4590 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
4591 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
4592 dev_priv->rps.cur_freq);
4593
4594 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
4595 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4596 dev_priv->rps.efficient_freq);
4597
4598 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
4599
4600 gen6_enable_rps_interrupts(dev);
4601
4602 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
4603 }
4604
4605 void ironlake_teardown_rc6(struct drm_device *dev)
4606 {
4607 struct drm_i915_private *dev_priv = dev->dev_private;
4608
4609 if (dev_priv->ips.renderctx) {
4610 i915_gem_object_ggtt_unpin(dev_priv->ips.renderctx);
4611 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
4612 dev_priv->ips.renderctx = NULL;
4613 }
4614
4615 if (dev_priv->ips.pwrctx) {
4616 i915_gem_object_ggtt_unpin(dev_priv->ips.pwrctx);
4617 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
4618 dev_priv->ips.pwrctx = NULL;
4619 }
4620 }
4621
4622 static void ironlake_disable_rc6(struct drm_device *dev)
4623 {
4624 struct drm_i915_private *dev_priv = dev->dev_private;
4625
4626 if (I915_READ(PWRCTXA)) {
4627 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
4628 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
4629 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
4630 50);
4631
4632 I915_WRITE(PWRCTXA, 0);
4633 POSTING_READ(PWRCTXA);
4634
4635 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
4636 POSTING_READ(RSTDBYCTL);
4637 }
4638 }
4639
4640 static int ironlake_setup_rc6(struct drm_device *dev)
4641 {
4642 struct drm_i915_private *dev_priv = dev->dev_private;
4643
4644 if (dev_priv->ips.renderctx == NULL)
4645 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
4646 if (!dev_priv->ips.renderctx)
4647 return -ENOMEM;
4648
4649 if (dev_priv->ips.pwrctx == NULL)
4650 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
4651 if (!dev_priv->ips.pwrctx) {
4652 ironlake_teardown_rc6(dev);
4653 return -ENOMEM;
4654 }
4655
4656 return 0;
4657 }
4658
4659 static void ironlake_enable_rc6(struct drm_device *dev)
4660 {
4661 struct drm_i915_private *dev_priv = dev->dev_private;
4662 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
4663 bool was_interruptible;
4664 int ret;
4665
4666 /* rc6 disabled by default due to repeated reports of hanging during
4667 * boot and resume.
4668 */
4669 if (!intel_enable_rc6(dev))
4670 return;
4671
4672 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4673
4674 ret = ironlake_setup_rc6(dev);
4675 if (ret)
4676 return;
4677
4678 was_interruptible = dev_priv->mm.interruptible;
4679 dev_priv->mm.interruptible = false;
4680
4681 /*
4682 * GPU can automatically power down the render unit if given a page
4683 * to save state.
4684 */
4685 ret = intel_ring_begin(ring, 6);
4686 if (ret) {
4687 ironlake_teardown_rc6(dev);
4688 dev_priv->mm.interruptible = was_interruptible;
4689 return;
4690 }
4691
4692 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
4693 intel_ring_emit(ring, MI_SET_CONTEXT);
4694 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) |
4695 MI_MM_SPACE_GTT |
4696 MI_SAVE_EXT_STATE_EN |
4697 MI_RESTORE_EXT_STATE_EN |
4698 MI_RESTORE_INHIBIT);
4699 intel_ring_emit(ring, MI_SUSPEND_FLUSH);
4700 intel_ring_emit(ring, MI_NOOP);
4701 intel_ring_emit(ring, MI_FLUSH);
4702 intel_ring_advance(ring);
4703
4704 /*
4705 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
4706 * does an implicit flush, combined with MI_FLUSH above, it should be
4707 * safe to assume that renderctx is valid
4708 */
4709 ret = intel_ring_idle(ring);
4710 dev_priv->mm.interruptible = was_interruptible;
4711 if (ret) {
4712 DRM_ERROR("failed to enable ironlake power savings\n");
4713 ironlake_teardown_rc6(dev);
4714 return;
4715 }
4716
4717 I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN);
4718 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
4719
4720 intel_print_rc6_info(dev, GEN6_RC_CTL_RC6_ENABLE);
4721 }
4722
4723 static unsigned long intel_pxfreq(u32 vidfreq)
4724 {
4725 unsigned long freq;
4726 int div = (vidfreq & 0x3f0000) >> 16;
4727 int post = (vidfreq & 0x3000) >> 12;
4728 int pre = (vidfreq & 0x7);
4729
4730 if (!pre)
4731 return 0;
4732
4733 freq = ((div * 133333) / ((1<<post) * pre));
4734
4735 return freq;
4736 }
4737
4738 static const struct cparams {
4739 u16 i;
4740 u16 t;
4741 u16 m;
4742 u16 c;
4743 } cparams[] = {
4744 { 1, 1333, 301, 28664 },
4745 { 1, 1066, 294, 24460 },
4746 { 1, 800, 294, 25192 },
4747 { 0, 1333, 276, 27605 },
4748 { 0, 1066, 276, 27605 },
4749 { 0, 800, 231, 23784 },
4750 };
4751
4752 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
4753 {
4754 u64 total_count, diff, ret;
4755 u32 count1, count2, count3, m = 0, c = 0;
4756 unsigned long now = jiffies_to_msecs(jiffies), diff1;
4757 int i;
4758
4759 assert_spin_locked(&mchdev_lock);
4760
4761 diff1 = now - dev_priv->ips.last_time1;
4762
4763 /* Prevent division-by-zero if we are asking too fast.
4764 * Also, we don't get interesting results if we are polling
4765 * faster than once in 10ms, so just return the saved value
4766 * in such cases.
4767 */
4768 if (diff1 <= 10)
4769 return dev_priv->ips.chipset_power;
4770
4771 count1 = I915_READ(DMIEC);
4772 count2 = I915_READ(DDREC);
4773 count3 = I915_READ(CSIEC);
4774
4775 total_count = count1 + count2 + count3;
4776
4777 /* FIXME: handle per-counter overflow */
4778 if (total_count < dev_priv->ips.last_count1) {
4779 diff = ~0UL - dev_priv->ips.last_count1;
4780 diff += total_count;
4781 } else {
4782 diff = total_count - dev_priv->ips.last_count1;
4783 }
4784
4785 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
4786 if (cparams[i].i == dev_priv->ips.c_m &&
4787 cparams[i].t == dev_priv->ips.r_t) {
4788 m = cparams[i].m;
4789 c = cparams[i].c;
4790 break;
4791 }
4792 }
4793
4794 diff = div_u64(diff, diff1);
4795 ret = ((m * diff) + c);
4796 ret = div_u64(ret, 10);
4797
4798 dev_priv->ips.last_count1 = total_count;
4799 dev_priv->ips.last_time1 = now;
4800
4801 dev_priv->ips.chipset_power = ret;
4802
4803 return ret;
4804 }
4805
4806 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
4807 {
4808 struct drm_device *dev = dev_priv->dev;
4809 unsigned long val;
4810
4811 if (INTEL_INFO(dev)->gen != 5)
4812 return 0;
4813
4814 spin_lock_irq(&mchdev_lock);
4815
4816 val = __i915_chipset_val(dev_priv);
4817
4818 spin_unlock_irq(&mchdev_lock);
4819
4820 return val;
4821 }
4822
4823 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
4824 {
4825 unsigned long m, x, b;
4826 u32 tsfs;
4827
4828 tsfs = I915_READ(TSFS);
4829
4830 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
4831 x = I915_READ8(TR1);
4832
4833 b = tsfs & TSFS_INTR_MASK;
4834
4835 return ((m * x) / 127) - b;
4836 }
4837
4838 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
4839 {
4840 struct drm_device *dev = dev_priv->dev;
4841 static const struct v_table {
4842 u16 vd; /* in .1 mil */
4843 u16 vm; /* in .1 mil */
4844 } v_table[] = {
4845 { 0, 0, },
4846 { 375, 0, },
4847 { 500, 0, },
4848 { 625, 0, },
4849 { 750, 0, },
4850 { 875, 0, },
4851 { 1000, 0, },
4852 { 1125, 0, },
4853 { 4125, 3000, },
4854 { 4125, 3000, },
4855 { 4125, 3000, },
4856 { 4125, 3000, },
4857 { 4125, 3000, },
4858 { 4125, 3000, },
4859 { 4125, 3000, },
4860 { 4125, 3000, },
4861 { 4125, 3000, },
4862 { 4125, 3000, },
4863 { 4125, 3000, },
4864 { 4125, 3000, },
4865 { 4125, 3000, },
4866 { 4125, 3000, },
4867 { 4125, 3000, },
4868 { 4125, 3000, },
4869 { 4125, 3000, },
4870 { 4125, 3000, },
4871 { 4125, 3000, },
4872 { 4125, 3000, },
4873 { 4125, 3000, },
4874 { 4125, 3000, },
4875 { 4125, 3000, },
4876 { 4125, 3000, },
4877 { 4250, 3125, },
4878 { 4375, 3250, },
4879 { 4500, 3375, },
4880 { 4625, 3500, },
4881 { 4750, 3625, },
4882 { 4875, 3750, },
4883 { 5000, 3875, },
4884 { 5125, 4000, },
4885 { 5250, 4125, },
4886 { 5375, 4250, },
4887 { 5500, 4375, },
4888 { 5625, 4500, },
4889 { 5750, 4625, },
4890 { 5875, 4750, },
4891 { 6000, 4875, },
4892 { 6125, 5000, },
4893 { 6250, 5125, },
4894 { 6375, 5250, },
4895 { 6500, 5375, },
4896 { 6625, 5500, },
4897 { 6750, 5625, },
4898 { 6875, 5750, },
4899 { 7000, 5875, },
4900 { 7125, 6000, },
4901 { 7250, 6125, },
4902 { 7375, 6250, },
4903 { 7500, 6375, },
4904 { 7625, 6500, },
4905 { 7750, 6625, },
4906 { 7875, 6750, },
4907 { 8000, 6875, },
4908 { 8125, 7000, },
4909 { 8250, 7125, },
4910 { 8375, 7250, },
4911 { 8500, 7375, },
4912 { 8625, 7500, },
4913 { 8750, 7625, },
4914 { 8875, 7750, },
4915 { 9000, 7875, },
4916 { 9125, 8000, },
4917 { 9250, 8125, },
4918 { 9375, 8250, },
4919 { 9500, 8375, },
4920 { 9625, 8500, },
4921 { 9750, 8625, },
4922 { 9875, 8750, },
4923 { 10000, 8875, },
4924 { 10125, 9000, },
4925 { 10250, 9125, },
4926 { 10375, 9250, },
4927 { 10500, 9375, },
4928 { 10625, 9500, },
4929 { 10750, 9625, },
4930 { 10875, 9750, },
4931 { 11000, 9875, },
4932 { 11125, 10000, },
4933 { 11250, 10125, },
4934 { 11375, 10250, },
4935 { 11500, 10375, },
4936 { 11625, 10500, },
4937 { 11750, 10625, },
4938 { 11875, 10750, },
4939 { 12000, 10875, },
4940 { 12125, 11000, },
4941 { 12250, 11125, },
4942 { 12375, 11250, },
4943 { 12500, 11375, },
4944 { 12625, 11500, },
4945 { 12750, 11625, },
4946 { 12875, 11750, },
4947 { 13000, 11875, },
4948 { 13125, 12000, },
4949 { 13250, 12125, },
4950 { 13375, 12250, },
4951 { 13500, 12375, },
4952 { 13625, 12500, },
4953 { 13750, 12625, },
4954 { 13875, 12750, },
4955 { 14000, 12875, },
4956 { 14125, 13000, },
4957 { 14250, 13125, },
4958 { 14375, 13250, },
4959 { 14500, 13375, },
4960 { 14625, 13500, },
4961 { 14750, 13625, },
4962 { 14875, 13750, },
4963 { 15000, 13875, },
4964 { 15125, 14000, },
4965 { 15250, 14125, },
4966 { 15375, 14250, },
4967 { 15500, 14375, },
4968 { 15625, 14500, },
4969 { 15750, 14625, },
4970 { 15875, 14750, },
4971 { 16000, 14875, },
4972 { 16125, 15000, },
4973 };
4974 if (INTEL_INFO(dev)->is_mobile)
4975 return v_table[pxvid].vm;
4976 else
4977 return v_table[pxvid].vd;
4978 }
4979
4980 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
4981 {
4982 u64 now, diff, diffms;
4983 u32 count;
4984
4985 assert_spin_locked(&mchdev_lock);
4986
4987 now = ktime_get_raw_ns();
4988 diffms = now - dev_priv->ips.last_time2;
4989 do_div(diffms, NSEC_PER_MSEC);
4990
4991 /* Don't divide by 0 */
4992 if (!diffms)
4993 return;
4994
4995 count = I915_READ(GFXEC);
4996
4997 if (count < dev_priv->ips.last_count2) {
4998 diff = ~0UL - dev_priv->ips.last_count2;
4999 diff += count;
5000 } else {
5001 diff = count - dev_priv->ips.last_count2;
5002 }
5003
5004 dev_priv->ips.last_count2 = count;
5005 dev_priv->ips.last_time2 = now;
5006
5007 /* More magic constants... */
5008 diff = diff * 1181;
5009 diff = div_u64(diff, diffms * 10);
5010 dev_priv->ips.gfx_power = diff;
5011 }
5012
5013 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
5014 {
5015 struct drm_device *dev = dev_priv->dev;
5016
5017 if (INTEL_INFO(dev)->gen != 5)
5018 return;
5019
5020 spin_lock_irq(&mchdev_lock);
5021
5022 __i915_update_gfx_val(dev_priv);
5023
5024 spin_unlock_irq(&mchdev_lock);
5025 }
5026
5027 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
5028 {
5029 unsigned long t, corr, state1, corr2, state2;
5030 u32 pxvid, ext_v;
5031
5032 assert_spin_locked(&mchdev_lock);
5033
5034 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_freq * 4));
5035 pxvid = (pxvid >> 24) & 0x7f;
5036 ext_v = pvid_to_extvid(dev_priv, pxvid);
5037
5038 state1 = ext_v;
5039
5040 t = i915_mch_val(dev_priv);
5041
5042 /* Revel in the empirically derived constants */
5043
5044 /* Correction factor in 1/100000 units */
5045 if (t > 80)
5046 corr = ((t * 2349) + 135940);
5047 else if (t >= 50)
5048 corr = ((t * 964) + 29317);
5049 else /* < 50 */
5050 corr = ((t * 301) + 1004);
5051
5052 corr = corr * ((150142 * state1) / 10000 - 78642);
5053 corr /= 100000;
5054 corr2 = (corr * dev_priv->ips.corr);
5055
5056 state2 = (corr2 * state1) / 10000;
5057 state2 /= 100; /* convert to mW */
5058
5059 __i915_update_gfx_val(dev_priv);
5060
5061 return dev_priv->ips.gfx_power + state2;
5062 }
5063
5064 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
5065 {
5066 struct drm_device *dev = dev_priv->dev;
5067 unsigned long val;
5068
5069 if (INTEL_INFO(dev)->gen != 5)
5070 return 0;
5071
5072 spin_lock_irq(&mchdev_lock);
5073
5074 val = __i915_gfx_val(dev_priv);
5075
5076 spin_unlock_irq(&mchdev_lock);
5077
5078 return val;
5079 }
5080
5081 /**
5082 * i915_read_mch_val - return value for IPS use
5083 *
5084 * Calculate and return a value for the IPS driver to use when deciding whether
5085 * we have thermal and power headroom to increase CPU or GPU power budget.
5086 */
5087 unsigned long i915_read_mch_val(void)
5088 {
5089 struct drm_i915_private *dev_priv;
5090 unsigned long chipset_val, graphics_val, ret = 0;
5091
5092 spin_lock_irq(&mchdev_lock);
5093 if (!i915_mch_dev)
5094 goto out_unlock;
5095 dev_priv = i915_mch_dev;
5096
5097 chipset_val = __i915_chipset_val(dev_priv);
5098 graphics_val = __i915_gfx_val(dev_priv);
5099
5100 ret = chipset_val + graphics_val;
5101
5102 out_unlock:
5103 spin_unlock_irq(&mchdev_lock);
5104
5105 return ret;
5106 }
5107 EXPORT_SYMBOL_GPL(i915_read_mch_val);
5108
5109 /**
5110 * i915_gpu_raise - raise GPU frequency limit
5111 *
5112 * Raise the limit; IPS indicates we have thermal headroom.
5113 */
5114 bool i915_gpu_raise(void)
5115 {
5116 struct drm_i915_private *dev_priv;
5117 bool ret = true;
5118
5119 spin_lock_irq(&mchdev_lock);
5120 if (!i915_mch_dev) {
5121 ret = false;
5122 goto out_unlock;
5123 }
5124 dev_priv = i915_mch_dev;
5125
5126 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
5127 dev_priv->ips.max_delay--;
5128
5129 out_unlock:
5130 spin_unlock_irq(&mchdev_lock);
5131
5132 return ret;
5133 }
5134 EXPORT_SYMBOL_GPL(i915_gpu_raise);
5135
5136 /**
5137 * i915_gpu_lower - lower GPU frequency limit
5138 *
5139 * IPS indicates we're close to a thermal limit, so throttle back the GPU
5140 * frequency maximum.
5141 */
5142 bool i915_gpu_lower(void)
5143 {
5144 struct drm_i915_private *dev_priv;
5145 bool ret = true;
5146
5147 spin_lock_irq(&mchdev_lock);
5148 if (!i915_mch_dev) {
5149 ret = false;
5150 goto out_unlock;
5151 }
5152 dev_priv = i915_mch_dev;
5153
5154 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
5155 dev_priv->ips.max_delay++;
5156
5157 out_unlock:
5158 spin_unlock_irq(&mchdev_lock);
5159
5160 return ret;
5161 }
5162 EXPORT_SYMBOL_GPL(i915_gpu_lower);
5163
5164 /**
5165 * i915_gpu_busy - indicate GPU business to IPS
5166 *
5167 * Tell the IPS driver whether or not the GPU is busy.
5168 */
5169 bool i915_gpu_busy(void)
5170 {
5171 struct drm_i915_private *dev_priv;
5172 struct intel_engine_cs *ring;
5173 bool ret = false;
5174 int i;
5175
5176 spin_lock_irq(&mchdev_lock);
5177 if (!i915_mch_dev)
5178 goto out_unlock;
5179 dev_priv = i915_mch_dev;
5180
5181 for_each_ring(ring, dev_priv, i)
5182 ret |= !list_empty(&ring->request_list);
5183
5184 out_unlock:
5185 spin_unlock_irq(&mchdev_lock);
5186
5187 return ret;
5188 }
5189 EXPORT_SYMBOL_GPL(i915_gpu_busy);
5190
5191 /**
5192 * i915_gpu_turbo_disable - disable graphics turbo
5193 *
5194 * Disable graphics turbo by resetting the max frequency and setting the
5195 * current frequency to the default.
5196 */
5197 bool i915_gpu_turbo_disable(void)
5198 {
5199 struct drm_i915_private *dev_priv;
5200 bool ret = true;
5201
5202 spin_lock_irq(&mchdev_lock);
5203 if (!i915_mch_dev) {
5204 ret = false;
5205 goto out_unlock;
5206 }
5207 dev_priv = i915_mch_dev;
5208
5209 dev_priv->ips.max_delay = dev_priv->ips.fstart;
5210
5211 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
5212 ret = false;
5213
5214 out_unlock:
5215 spin_unlock_irq(&mchdev_lock);
5216
5217 return ret;
5218 }
5219 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
5220
5221 /**
5222 * Tells the intel_ips driver that the i915 driver is now loaded, if
5223 * IPS got loaded first.
5224 *
5225 * This awkward dance is so that neither module has to depend on the
5226 * other in order for IPS to do the appropriate communication of
5227 * GPU turbo limits to i915.
5228 */
5229 static void
5230 ips_ping_for_i915_load(void)
5231 {
5232 void (*link)(void);
5233
5234 link = symbol_get(ips_link_to_i915_driver);
5235 if (link) {
5236 link();
5237 symbol_put(ips_link_to_i915_driver);
5238 }
5239 }
5240
5241 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
5242 {
5243 /* We only register the i915 ips part with intel-ips once everything is
5244 * set up, to avoid intel-ips sneaking in and reading bogus values. */
5245 spin_lock_irq(&mchdev_lock);
5246 i915_mch_dev = dev_priv;
5247 spin_unlock_irq(&mchdev_lock);
5248
5249 ips_ping_for_i915_load();
5250 }
5251
5252 void intel_gpu_ips_teardown(void)
5253 {
5254 spin_lock_irq(&mchdev_lock);
5255 i915_mch_dev = NULL;
5256 spin_unlock_irq(&mchdev_lock);
5257 }
5258
5259 static void intel_init_emon(struct drm_device *dev)
5260 {
5261 struct drm_i915_private *dev_priv = dev->dev_private;
5262 u32 lcfuse;
5263 u8 pxw[16];
5264 int i;
5265
5266 /* Disable to program */
5267 I915_WRITE(ECR, 0);
5268 POSTING_READ(ECR);
5269
5270 /* Program energy weights for various events */
5271 I915_WRITE(SDEW, 0x15040d00);
5272 I915_WRITE(CSIEW0, 0x007f0000);
5273 I915_WRITE(CSIEW1, 0x1e220004);
5274 I915_WRITE(CSIEW2, 0x04000004);
5275
5276 for (i = 0; i < 5; i++)
5277 I915_WRITE(PEW + (i * 4), 0);
5278 for (i = 0; i < 3; i++)
5279 I915_WRITE(DEW + (i * 4), 0);
5280
5281 /* Program P-state weights to account for frequency power adjustment */
5282 for (i = 0; i < 16; i++) {
5283 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
5284 unsigned long freq = intel_pxfreq(pxvidfreq);
5285 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5286 PXVFREQ_PX_SHIFT;
5287 unsigned long val;
5288
5289 val = vid * vid;
5290 val *= (freq / 1000);
5291 val *= 255;
5292 val /= (127*127*900);
5293 if (val > 0xff)
5294 DRM_ERROR("bad pxval: %ld\n", val);
5295 pxw[i] = val;
5296 }
5297 /* Render standby states get 0 weight */
5298 pxw[14] = 0;
5299 pxw[15] = 0;
5300
5301 for (i = 0; i < 4; i++) {
5302 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5303 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
5304 I915_WRITE(PXW + (i * 4), val);
5305 }
5306
5307 /* Adjust magic regs to magic values (more experimental results) */
5308 I915_WRITE(OGW0, 0);
5309 I915_WRITE(OGW1, 0);
5310 I915_WRITE(EG0, 0x00007f00);
5311 I915_WRITE(EG1, 0x0000000e);
5312 I915_WRITE(EG2, 0x000e0000);
5313 I915_WRITE(EG3, 0x68000300);
5314 I915_WRITE(EG4, 0x42000000);
5315 I915_WRITE(EG5, 0x00140031);
5316 I915_WRITE(EG6, 0);
5317 I915_WRITE(EG7, 0);
5318
5319 for (i = 0; i < 8; i++)
5320 I915_WRITE(PXWL + (i * 4), 0);
5321
5322 /* Enable PMON + select events */
5323 I915_WRITE(ECR, 0x80000019);
5324
5325 lcfuse = I915_READ(LCFUSE02);
5326
5327 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
5328 }
5329
5330 void intel_init_gt_powersave(struct drm_device *dev)
5331 {
5332 i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
5333
5334 if (IS_CHERRYVIEW(dev))
5335 cherryview_init_gt_powersave(dev);
5336 else if (IS_VALLEYVIEW(dev))
5337 valleyview_init_gt_powersave(dev);
5338 }
5339
5340 void intel_cleanup_gt_powersave(struct drm_device *dev)
5341 {
5342 if (IS_CHERRYVIEW(dev))
5343 return;
5344 else if (IS_VALLEYVIEW(dev))
5345 valleyview_cleanup_gt_powersave(dev);
5346 }
5347
5348 /**
5349 * intel_suspend_gt_powersave - suspend PM work and helper threads
5350 * @dev: drm device
5351 *
5352 * We don't want to disable RC6 or other features here, we just want
5353 * to make sure any work we've queued has finished and won't bother
5354 * us while we're suspended.
5355 */
5356 void intel_suspend_gt_powersave(struct drm_device *dev)
5357 {
5358 struct drm_i915_private *dev_priv = dev->dev_private;
5359
5360 /* Interrupts should be disabled already to avoid re-arming. */
5361 WARN_ON(intel_irqs_enabled(dev_priv));
5362
5363 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
5364
5365 cancel_work_sync(&dev_priv->rps.work);
5366
5367 /* Force GPU to min freq during suspend */
5368 gen6_rps_idle(dev_priv);
5369 }
5370
5371 void intel_disable_gt_powersave(struct drm_device *dev)
5372 {
5373 struct drm_i915_private *dev_priv = dev->dev_private;
5374
5375 /* Interrupts should be disabled already to avoid re-arming. */
5376 WARN_ON(intel_irqs_enabled(dev_priv));
5377
5378 if (IS_IRONLAKE_M(dev)) {
5379 ironlake_disable_drps(dev);
5380 ironlake_disable_rc6(dev);
5381 } else if (INTEL_INFO(dev)->gen >= 6) {
5382 intel_suspend_gt_powersave(dev);
5383
5384 mutex_lock(&dev_priv->rps.hw_lock);
5385 if (IS_CHERRYVIEW(dev))
5386 cherryview_disable_rps(dev);
5387 else if (IS_VALLEYVIEW(dev))
5388 valleyview_disable_rps(dev);
5389 else
5390 gen6_disable_rps(dev);
5391 dev_priv->rps.enabled = false;
5392 mutex_unlock(&dev_priv->rps.hw_lock);
5393 }
5394 }
5395
5396 static void intel_gen6_powersave_work(struct work_struct *work)
5397 {
5398 struct drm_i915_private *dev_priv =
5399 container_of(work, struct drm_i915_private,
5400 rps.delayed_resume_work.work);
5401 struct drm_device *dev = dev_priv->dev;
5402
5403 dev_priv->rps.is_bdw_sw_turbo = false;
5404
5405 mutex_lock(&dev_priv->rps.hw_lock);
5406
5407 if (IS_CHERRYVIEW(dev)) {
5408 cherryview_enable_rps(dev);
5409 } else if (IS_VALLEYVIEW(dev)) {
5410 valleyview_enable_rps(dev);
5411 } else if (IS_BROADWELL(dev)) {
5412 gen8_enable_rps(dev);
5413 __gen6_update_ring_freq(dev);
5414 } else {
5415 gen6_enable_rps(dev);
5416 __gen6_update_ring_freq(dev);
5417 }
5418 dev_priv->rps.enabled = true;
5419 mutex_unlock(&dev_priv->rps.hw_lock);
5420
5421 intel_runtime_pm_put(dev_priv);
5422 }
5423
5424 void intel_enable_gt_powersave(struct drm_device *dev)
5425 {
5426 struct drm_i915_private *dev_priv = dev->dev_private;
5427
5428 if (IS_IRONLAKE_M(dev)) {
5429 mutex_lock(&dev->struct_mutex);
5430 ironlake_enable_drps(dev);
5431 ironlake_enable_rc6(dev);
5432 intel_init_emon(dev);
5433 mutex_unlock(&dev->struct_mutex);
5434 } else if (INTEL_INFO(dev)->gen >= 6) {
5435 /*
5436 * PCU communication is slow and this doesn't need to be
5437 * done at any specific time, so do this out of our fast path
5438 * to make resume and init faster.
5439 *
5440 * We depend on the HW RC6 power context save/restore
5441 * mechanism when entering D3 through runtime PM suspend. So
5442 * disable RPM until RPS/RC6 is properly setup. We can only
5443 * get here via the driver load/system resume/runtime resume
5444 * paths, so the _noresume version is enough (and in case of
5445 * runtime resume it's necessary).
5446 */
5447 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
5448 round_jiffies_up_relative(HZ)))
5449 intel_runtime_pm_get_noresume(dev_priv);
5450 }
5451 }
5452
5453 void intel_reset_gt_powersave(struct drm_device *dev)
5454 {
5455 struct drm_i915_private *dev_priv = dev->dev_private;
5456
5457 dev_priv->rps.enabled = false;
5458 intel_enable_gt_powersave(dev);
5459 }
5460
5461 static void ibx_init_clock_gating(struct drm_device *dev)
5462 {
5463 struct drm_i915_private *dev_priv = dev->dev_private;
5464
5465 /*
5466 * On Ibex Peak and Cougar Point, we need to disable clock
5467 * gating for the panel power sequencer or it will fail to
5468 * start up when no ports are active.
5469 */
5470 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
5471 }
5472
5473 static void g4x_disable_trickle_feed(struct drm_device *dev)
5474 {
5475 struct drm_i915_private *dev_priv = dev->dev_private;
5476 int pipe;
5477
5478 for_each_pipe(dev_priv, pipe) {
5479 I915_WRITE(DSPCNTR(pipe),
5480 I915_READ(DSPCNTR(pipe)) |
5481 DISPPLANE_TRICKLE_FEED_DISABLE);
5482 intel_flush_primary_plane(dev_priv, pipe);
5483 }
5484 }
5485
5486 static void ilk_init_lp_watermarks(struct drm_device *dev)
5487 {
5488 struct drm_i915_private *dev_priv = dev->dev_private;
5489
5490 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
5491 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
5492 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
5493
5494 /*
5495 * Don't touch WM1S_LP_EN here.
5496 * Doing so could cause underruns.
5497 */
5498 }
5499
5500 static void ironlake_init_clock_gating(struct drm_device *dev)
5501 {
5502 struct drm_i915_private *dev_priv = dev->dev_private;
5503 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
5504
5505 /*
5506 * Required for FBC
5507 * WaFbcDisableDpfcClockGating:ilk
5508 */
5509 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
5510 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
5511 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
5512
5513 I915_WRITE(PCH_3DCGDIS0,
5514 MARIUNIT_CLOCK_GATE_DISABLE |
5515 SVSMUNIT_CLOCK_GATE_DISABLE);
5516 I915_WRITE(PCH_3DCGDIS1,
5517 VFMUNIT_CLOCK_GATE_DISABLE);
5518
5519 /*
5520 * According to the spec the following bits should be set in
5521 * order to enable memory self-refresh
5522 * The bit 22/21 of 0x42004
5523 * The bit 5 of 0x42020
5524 * The bit 15 of 0x45000
5525 */
5526 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5527 (I915_READ(ILK_DISPLAY_CHICKEN2) |
5528 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
5529 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
5530 I915_WRITE(DISP_ARB_CTL,
5531 (I915_READ(DISP_ARB_CTL) |
5532 DISP_FBC_WM_DIS));
5533
5534 ilk_init_lp_watermarks(dev);
5535
5536 /*
5537 * Based on the document from hardware guys the following bits
5538 * should be set unconditionally in order to enable FBC.
5539 * The bit 22 of 0x42000
5540 * The bit 22 of 0x42004
5541 * The bit 7,8,9 of 0x42020.
5542 */
5543 if (IS_IRONLAKE_M(dev)) {
5544 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
5545 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5546 I915_READ(ILK_DISPLAY_CHICKEN1) |
5547 ILK_FBCQ_DIS);
5548 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5549 I915_READ(ILK_DISPLAY_CHICKEN2) |
5550 ILK_DPARB_GATE);
5551 }
5552
5553 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
5554
5555 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5556 I915_READ(ILK_DISPLAY_CHICKEN2) |
5557 ILK_ELPIN_409_SELECT);
5558 I915_WRITE(_3D_CHICKEN2,
5559 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
5560 _3D_CHICKEN2_WM_READ_PIPELINED);
5561
5562 /* WaDisableRenderCachePipelinedFlush:ilk */
5563 I915_WRITE(CACHE_MODE_0,
5564 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
5565
5566 /* WaDisable_RenderCache_OperationalFlush:ilk */
5567 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5568
5569 g4x_disable_trickle_feed(dev);
5570
5571 ibx_init_clock_gating(dev);
5572 }
5573
5574 static void cpt_init_clock_gating(struct drm_device *dev)
5575 {
5576 struct drm_i915_private *dev_priv = dev->dev_private;
5577 int pipe;
5578 uint32_t val;
5579
5580 /*
5581 * On Ibex Peak and Cougar Point, we need to disable clock
5582 * gating for the panel power sequencer or it will fail to
5583 * start up when no ports are active.
5584 */
5585 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
5586 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
5587 PCH_CPUNIT_CLOCK_GATE_DISABLE);
5588 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
5589 DPLS_EDP_PPS_FIX_DIS);
5590 /* The below fixes the weird display corruption, a few pixels shifted
5591 * downward, on (only) LVDS of some HP laptops with IVY.
5592 */
5593 for_each_pipe(dev_priv, pipe) {
5594 val = I915_READ(TRANS_CHICKEN2(pipe));
5595 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
5596 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
5597 if (dev_priv->vbt.fdi_rx_polarity_inverted)
5598 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
5599 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
5600 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
5601 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
5602 I915_WRITE(TRANS_CHICKEN2(pipe), val);
5603 }
5604 /* WADP0ClockGatingDisable */
5605 for_each_pipe(dev_priv, pipe) {
5606 I915_WRITE(TRANS_CHICKEN1(pipe),
5607 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
5608 }
5609 }
5610
5611 static void gen6_check_mch_setup(struct drm_device *dev)
5612 {
5613 struct drm_i915_private *dev_priv = dev->dev_private;
5614 uint32_t tmp;
5615
5616 tmp = I915_READ(MCH_SSKPD);
5617 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
5618 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
5619 tmp);
5620 }
5621
5622 static void gen6_init_clock_gating(struct drm_device *dev)
5623 {
5624 struct drm_i915_private *dev_priv = dev->dev_private;
5625 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
5626
5627 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
5628
5629 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5630 I915_READ(ILK_DISPLAY_CHICKEN2) |
5631 ILK_ELPIN_409_SELECT);
5632
5633 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
5634 I915_WRITE(_3D_CHICKEN,
5635 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
5636
5637 /* WaSetupGtModeTdRowDispatch:snb */
5638 if (IS_SNB_GT1(dev))
5639 I915_WRITE(GEN6_GT_MODE,
5640 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
5641
5642 /* WaDisable_RenderCache_OperationalFlush:snb */
5643 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5644
5645 /*
5646 * BSpec recoomends 8x4 when MSAA is used,
5647 * however in practice 16x4 seems fastest.
5648 *
5649 * Note that PS/WM thread counts depend on the WIZ hashing
5650 * disable bit, which we don't touch here, but it's good
5651 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5652 */
5653 I915_WRITE(GEN6_GT_MODE,
5654 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5655
5656 ilk_init_lp_watermarks(dev);
5657
5658 I915_WRITE(CACHE_MODE_0,
5659 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
5660
5661 I915_WRITE(GEN6_UCGCTL1,
5662 I915_READ(GEN6_UCGCTL1) |
5663 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
5664 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
5665
5666 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5667 * gating disable must be set. Failure to set it results in
5668 * flickering pixels due to Z write ordering failures after
5669 * some amount of runtime in the Mesa "fire" demo, and Unigine
5670 * Sanctuary and Tropics, and apparently anything else with
5671 * alpha test or pixel discard.
5672 *
5673 * According to the spec, bit 11 (RCCUNIT) must also be set,
5674 * but we didn't debug actual testcases to find it out.
5675 *
5676 * WaDisableRCCUnitClockGating:snb
5677 * WaDisableRCPBUnitClockGating:snb
5678 */
5679 I915_WRITE(GEN6_UCGCTL2,
5680 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
5681 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5682
5683 /* WaStripsFansDisableFastClipPerformanceFix:snb */
5684 I915_WRITE(_3D_CHICKEN3,
5685 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
5686
5687 /*
5688 * Bspec says:
5689 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
5690 * 3DSTATE_SF number of SF output attributes is more than 16."
5691 */
5692 I915_WRITE(_3D_CHICKEN3,
5693 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
5694
5695 /*
5696 * According to the spec the following bits should be
5697 * set in order to enable memory self-refresh and fbc:
5698 * The bit21 and bit22 of 0x42000
5699 * The bit21 and bit22 of 0x42004
5700 * The bit5 and bit7 of 0x42020
5701 * The bit14 of 0x70180
5702 * The bit14 of 0x71180
5703 *
5704 * WaFbcAsynchFlipDisableFbcQueue:snb
5705 */
5706 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5707 I915_READ(ILK_DISPLAY_CHICKEN1) |
5708 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
5709 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5710 I915_READ(ILK_DISPLAY_CHICKEN2) |
5711 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
5712 I915_WRITE(ILK_DSPCLK_GATE_D,
5713 I915_READ(ILK_DSPCLK_GATE_D) |
5714 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
5715 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
5716
5717 g4x_disable_trickle_feed(dev);
5718
5719 cpt_init_clock_gating(dev);
5720
5721 gen6_check_mch_setup(dev);
5722 }
5723
5724 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
5725 {
5726 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
5727
5728 /*
5729 * WaVSThreadDispatchOverride:ivb,vlv
5730 *
5731 * This actually overrides the dispatch
5732 * mode for all thread types.
5733 */
5734 reg &= ~GEN7_FF_SCHED_MASK;
5735 reg |= GEN7_FF_TS_SCHED_HW;
5736 reg |= GEN7_FF_VS_SCHED_HW;
5737 reg |= GEN7_FF_DS_SCHED_HW;
5738
5739 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
5740 }
5741
5742 static void lpt_init_clock_gating(struct drm_device *dev)
5743 {
5744 struct drm_i915_private *dev_priv = dev->dev_private;
5745
5746 /*
5747 * TODO: this bit should only be enabled when really needed, then
5748 * disabled when not needed anymore in order to save power.
5749 */
5750 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
5751 I915_WRITE(SOUTH_DSPCLK_GATE_D,
5752 I915_READ(SOUTH_DSPCLK_GATE_D) |
5753 PCH_LP_PARTITION_LEVEL_DISABLE);
5754
5755 /* WADPOClockGatingDisable:hsw */
5756 I915_WRITE(_TRANSA_CHICKEN1,
5757 I915_READ(_TRANSA_CHICKEN1) |
5758 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
5759 }
5760
5761 static void lpt_suspend_hw(struct drm_device *dev)
5762 {
5763 struct drm_i915_private *dev_priv = dev->dev_private;
5764
5765 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
5766 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
5767
5768 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
5769 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
5770 }
5771 }
5772
5773 static void broadwell_init_clock_gating(struct drm_device *dev)
5774 {
5775 struct drm_i915_private *dev_priv = dev->dev_private;
5776 enum pipe pipe;
5777
5778 I915_WRITE(WM3_LP_ILK, 0);
5779 I915_WRITE(WM2_LP_ILK, 0);
5780 I915_WRITE(WM1_LP_ILK, 0);
5781
5782 /* FIXME(BDW): Check all the w/a, some might only apply to
5783 * pre-production hw. */
5784
5785
5786 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE));
5787
5788 I915_WRITE(_3D_CHICKEN3,
5789 _MASKED_BIT_ENABLE(_3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2)));
5790
5791
5792 /* WaSwitchSolVfFArbitrationPriority:bdw */
5793 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
5794
5795 /* WaPsrDPAMaskVBlankInSRD:bdw */
5796 I915_WRITE(CHICKEN_PAR1_1,
5797 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
5798
5799 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
5800 for_each_pipe(dev_priv, pipe) {
5801 I915_WRITE(CHICKEN_PIPESL_1(pipe),
5802 I915_READ(CHICKEN_PIPESL_1(pipe)) |
5803 BDW_DPRS_MASK_VBLANK_SRD);
5804 }
5805
5806 /* WaVSRefCountFullforceMissDisable:bdw */
5807 /* WaDSRefCountFullforceMissDisable:bdw */
5808 I915_WRITE(GEN7_FF_THREAD_MODE,
5809 I915_READ(GEN7_FF_THREAD_MODE) &
5810 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
5811
5812 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
5813 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
5814
5815 /* WaDisableSDEUnitClockGating:bdw */
5816 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
5817 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5818
5819 lpt_init_clock_gating(dev);
5820 }
5821
5822 static void haswell_init_clock_gating(struct drm_device *dev)
5823 {
5824 struct drm_i915_private *dev_priv = dev->dev_private;
5825
5826 ilk_init_lp_watermarks(dev);
5827
5828 /* L3 caching of data atomics doesn't work -- disable it. */
5829 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
5830 I915_WRITE(HSW_ROW_CHICKEN3,
5831 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
5832
5833 /* This is required by WaCatErrorRejectionIssue:hsw */
5834 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5835 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5836 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5837
5838 /* WaVSRefCountFullforceMissDisable:hsw */
5839 I915_WRITE(GEN7_FF_THREAD_MODE,
5840 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
5841
5842 /* WaDisable_RenderCache_OperationalFlush:hsw */
5843 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5844
5845 /* enable HiZ Raw Stall Optimization */
5846 I915_WRITE(CACHE_MODE_0_GEN7,
5847 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
5848
5849 /* WaDisable4x2SubspanOptimization:hsw */
5850 I915_WRITE(CACHE_MODE_1,
5851 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5852
5853 /*
5854 * BSpec recommends 8x4 when MSAA is used,
5855 * however in practice 16x4 seems fastest.
5856 *
5857 * Note that PS/WM thread counts depend on the WIZ hashing
5858 * disable bit, which we don't touch here, but it's good
5859 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5860 */
5861 I915_WRITE(GEN7_GT_MODE,
5862 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5863
5864 /* WaSwitchSolVfFArbitrationPriority:hsw */
5865 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
5866
5867 /* WaRsPkgCStateDisplayPMReq:hsw */
5868 I915_WRITE(CHICKEN_PAR1_1,
5869 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
5870
5871 lpt_init_clock_gating(dev);
5872 }
5873
5874 static void ivybridge_init_clock_gating(struct drm_device *dev)
5875 {
5876 struct drm_i915_private *dev_priv = dev->dev_private;
5877 uint32_t snpcr;
5878
5879 ilk_init_lp_watermarks(dev);
5880
5881 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
5882
5883 /* WaDisableEarlyCull:ivb */
5884 I915_WRITE(_3D_CHICKEN3,
5885 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5886
5887 /* WaDisableBackToBackFlipFix:ivb */
5888 I915_WRITE(IVB_CHICKEN3,
5889 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5890 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5891
5892 /* WaDisablePSDDualDispatchEnable:ivb */
5893 if (IS_IVB_GT1(dev))
5894 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5895 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5896
5897 /* WaDisable_RenderCache_OperationalFlush:ivb */
5898 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5899
5900 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
5901 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5902 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5903
5904 /* WaApplyL3ControlAndL3ChickenMode:ivb */
5905 I915_WRITE(GEN7_L3CNTLREG1,
5906 GEN7_WA_FOR_GEN7_L3_CONTROL);
5907 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
5908 GEN7_WA_L3_CHICKEN_MODE);
5909 if (IS_IVB_GT1(dev))
5910 I915_WRITE(GEN7_ROW_CHICKEN2,
5911 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5912 else {
5913 /* must write both registers */
5914 I915_WRITE(GEN7_ROW_CHICKEN2,
5915 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5916 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
5917 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5918 }
5919
5920 /* WaForceL3Serialization:ivb */
5921 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5922 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5923
5924 /*
5925 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5926 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
5927 */
5928 I915_WRITE(GEN6_UCGCTL2,
5929 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
5930
5931 /* This is required by WaCatErrorRejectionIssue:ivb */
5932 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5933 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5934 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5935
5936 g4x_disable_trickle_feed(dev);
5937
5938 gen7_setup_fixed_func_scheduler(dev_priv);
5939
5940 if (0) { /* causes HiZ corruption on ivb:gt1 */
5941 /* enable HiZ Raw Stall Optimization */
5942 I915_WRITE(CACHE_MODE_0_GEN7,
5943 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
5944 }
5945
5946 /* WaDisable4x2SubspanOptimization:ivb */
5947 I915_WRITE(CACHE_MODE_1,
5948 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5949
5950 /*
5951 * BSpec recommends 8x4 when MSAA is used,
5952 * however in practice 16x4 seems fastest.
5953 *
5954 * Note that PS/WM thread counts depend on the WIZ hashing
5955 * disable bit, which we don't touch here, but it's good
5956 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5957 */
5958 I915_WRITE(GEN7_GT_MODE,
5959 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5960
5961 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5962 snpcr &= ~GEN6_MBC_SNPCR_MASK;
5963 snpcr |= GEN6_MBC_SNPCR_MED;
5964 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5965
5966 if (!HAS_PCH_NOP(dev))
5967 cpt_init_clock_gating(dev);
5968
5969 gen6_check_mch_setup(dev);
5970 }
5971
5972 static void valleyview_init_clock_gating(struct drm_device *dev)
5973 {
5974 struct drm_i915_private *dev_priv = dev->dev_private;
5975
5976 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
5977
5978 /* WaDisableEarlyCull:vlv */
5979 I915_WRITE(_3D_CHICKEN3,
5980 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5981
5982 /* WaDisableBackToBackFlipFix:vlv */
5983 I915_WRITE(IVB_CHICKEN3,
5984 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5985 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5986
5987 /* WaPsdDispatchEnable:vlv */
5988 /* WaDisablePSDDualDispatchEnable:vlv */
5989 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5990 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
5991 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5992
5993 /* WaDisable_RenderCache_OperationalFlush:vlv */
5994 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5995
5996 /* WaForceL3Serialization:vlv */
5997 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5998 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5999
6000 /* WaDisableDopClockGating:vlv */
6001 I915_WRITE(GEN7_ROW_CHICKEN2,
6002 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6003
6004 /* This is required by WaCatErrorRejectionIssue:vlv */
6005 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6006 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6007 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6008
6009 gen7_setup_fixed_func_scheduler(dev_priv);
6010
6011 /*
6012 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6013 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
6014 */
6015 I915_WRITE(GEN6_UCGCTL2,
6016 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
6017
6018 /* WaDisableL3Bank2xClockGate:vlv
6019 * Disabling L3 clock gating- MMIO 940c[25] = 1
6020 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
6021 I915_WRITE(GEN7_UCGCTL4,
6022 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
6023
6024 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6025
6026 /*
6027 * BSpec says this must be set, even though
6028 * WaDisable4x2SubspanOptimization isn't listed for VLV.
6029 */
6030 I915_WRITE(CACHE_MODE_1,
6031 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6032
6033 /*
6034 * WaIncreaseL3CreditsForVLVB0:vlv
6035 * This is the hardware default actually.
6036 */
6037 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
6038
6039 /*
6040 * WaDisableVLVClockGating_VBIIssue:vlv
6041 * Disable clock gating on th GCFG unit to prevent a delay
6042 * in the reporting of vblank events.
6043 */
6044 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6045 }
6046
6047 static void cherryview_init_clock_gating(struct drm_device *dev)
6048 {
6049 struct drm_i915_private *dev_priv = dev->dev_private;
6050
6051 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6052
6053 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6054
6055 /* WaVSRefCountFullforceMissDisable:chv */
6056 /* WaDSRefCountFullforceMissDisable:chv */
6057 I915_WRITE(GEN7_FF_THREAD_MODE,
6058 I915_READ(GEN7_FF_THREAD_MODE) &
6059 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
6060
6061 /* WaDisableSemaphoreAndSyncFlipWait:chv */
6062 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6063 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
6064
6065 /* WaDisableCSUnitClockGating:chv */
6066 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
6067 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6068
6069 /* WaDisableSDEUnitClockGating:chv */
6070 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6071 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6072
6073 /* WaDisableGunitClockGating:chv (pre-production hw) */
6074 I915_WRITE(VLV_GUNIT_CLOCK_GATE, I915_READ(VLV_GUNIT_CLOCK_GATE) |
6075 GINT_DIS);
6076
6077 /* WaDisableFfDopClockGating:chv (pre-production hw) */
6078 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6079 _MASKED_BIT_ENABLE(GEN8_FF_DOP_CLOCK_GATE_DISABLE));
6080
6081 /* WaDisableDopClockGating:chv (pre-production hw) */
6082 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
6083 GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
6084 }
6085
6086 static void g4x_init_clock_gating(struct drm_device *dev)
6087 {
6088 struct drm_i915_private *dev_priv = dev->dev_private;
6089 uint32_t dspclk_gate;
6090
6091 I915_WRITE(RENCLK_GATE_D1, 0);
6092 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
6093 GS_UNIT_CLOCK_GATE_DISABLE |
6094 CL_UNIT_CLOCK_GATE_DISABLE);
6095 I915_WRITE(RAMCLK_GATE_D, 0);
6096 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
6097 OVRUNIT_CLOCK_GATE_DISABLE |
6098 OVCUNIT_CLOCK_GATE_DISABLE;
6099 if (IS_GM45(dev))
6100 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
6101 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
6102
6103 /* WaDisableRenderCachePipelinedFlush */
6104 I915_WRITE(CACHE_MODE_0,
6105 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6106
6107 /* WaDisable_RenderCache_OperationalFlush:g4x */
6108 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6109
6110 g4x_disable_trickle_feed(dev);
6111 }
6112
6113 static void crestline_init_clock_gating(struct drm_device *dev)
6114 {
6115 struct drm_i915_private *dev_priv = dev->dev_private;
6116
6117 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
6118 I915_WRITE(RENCLK_GATE_D2, 0);
6119 I915_WRITE(DSPCLK_GATE_D, 0);
6120 I915_WRITE(RAMCLK_GATE_D, 0);
6121 I915_WRITE16(DEUC, 0);
6122 I915_WRITE(MI_ARB_STATE,
6123 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6124
6125 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6126 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6127 }
6128
6129 static void broadwater_init_clock_gating(struct drm_device *dev)
6130 {
6131 struct drm_i915_private *dev_priv = dev->dev_private;
6132
6133 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
6134 I965_RCC_CLOCK_GATE_DISABLE |
6135 I965_RCPB_CLOCK_GATE_DISABLE |
6136 I965_ISC_CLOCK_GATE_DISABLE |
6137 I965_FBC_CLOCK_GATE_DISABLE);
6138 I915_WRITE(RENCLK_GATE_D2, 0);
6139 I915_WRITE(MI_ARB_STATE,
6140 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6141
6142 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6143 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6144 }
6145
6146 static void gen3_init_clock_gating(struct drm_device *dev)
6147 {
6148 struct drm_i915_private *dev_priv = dev->dev_private;
6149 u32 dstate = I915_READ(D_STATE);
6150
6151 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
6152 DSTATE_DOT_CLOCK_GATING;
6153 I915_WRITE(D_STATE, dstate);
6154
6155 if (IS_PINEVIEW(dev))
6156 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
6157
6158 /* IIR "flip pending" means done if this bit is set */
6159 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
6160
6161 /* interrupts should cause a wake up from C3 */
6162 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
6163
6164 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
6165 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
6166
6167 I915_WRITE(MI_ARB_STATE,
6168 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6169 }
6170
6171 static void i85x_init_clock_gating(struct drm_device *dev)
6172 {
6173 struct drm_i915_private *dev_priv = dev->dev_private;
6174
6175 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
6176
6177 /* interrupts should cause a wake up from C3 */
6178 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
6179 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
6180
6181 I915_WRITE(MEM_MODE,
6182 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
6183 }
6184
6185 static void i830_init_clock_gating(struct drm_device *dev)
6186 {
6187 struct drm_i915_private *dev_priv = dev->dev_private;
6188
6189 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
6190
6191 I915_WRITE(MEM_MODE,
6192 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
6193 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
6194 }
6195
6196 void intel_init_clock_gating(struct drm_device *dev)
6197 {
6198 struct drm_i915_private *dev_priv = dev->dev_private;
6199
6200 dev_priv->display.init_clock_gating(dev);
6201 }
6202
6203 void intel_suspend_hw(struct drm_device *dev)
6204 {
6205 if (HAS_PCH_LPT(dev))
6206 lpt_suspend_hw(dev);
6207 }
6208
6209 #define for_each_power_well(i, power_well, domain_mask, power_domains) \
6210 for (i = 0; \
6211 i < (power_domains)->power_well_count && \
6212 ((power_well) = &(power_domains)->power_wells[i]); \
6213 i++) \
6214 if ((power_well)->domains & (domain_mask))
6215
6216 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
6217 for (i = (power_domains)->power_well_count - 1; \
6218 i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
6219 i--) \
6220 if ((power_well)->domains & (domain_mask))
6221
6222 /**
6223 * We should only use the power well if we explicitly asked the hardware to
6224 * enable it, so check if it's enabled and also check if we've requested it to
6225 * be enabled.
6226 */
6227 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
6228 struct i915_power_well *power_well)
6229 {
6230 return I915_READ(HSW_PWR_WELL_DRIVER) ==
6231 (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
6232 }
6233
6234 bool intel_display_power_enabled_unlocked(struct drm_i915_private *dev_priv,
6235 enum intel_display_power_domain domain)
6236 {
6237 struct i915_power_domains *power_domains;
6238 struct i915_power_well *power_well;
6239 bool is_enabled;
6240 int i;
6241
6242 if (dev_priv->pm.suspended)
6243 return false;
6244
6245 power_domains = &dev_priv->power_domains;
6246
6247 is_enabled = true;
6248
6249 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
6250 if (power_well->always_on)
6251 continue;
6252
6253 if (!power_well->hw_enabled) {
6254 is_enabled = false;
6255 break;
6256 }
6257 }
6258
6259 return is_enabled;
6260 }
6261
6262 bool intel_display_power_enabled(struct drm_i915_private *dev_priv,
6263 enum intel_display_power_domain domain)
6264 {
6265 struct i915_power_domains *power_domains;
6266 bool ret;
6267
6268 power_domains = &dev_priv->power_domains;
6269
6270 mutex_lock(&power_domains->lock);
6271 ret = intel_display_power_enabled_unlocked(dev_priv, domain);
6272 mutex_unlock(&power_domains->lock);
6273
6274 return ret;
6275 }
6276
6277 /*
6278 * Starting with Haswell, we have a "Power Down Well" that can be turned off
6279 * when not needed anymore. We have 4 registers that can request the power well
6280 * to be enabled, and it will only be disabled if none of the registers is
6281 * requesting it to be enabled.
6282 */
6283 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
6284 {
6285 struct drm_device *dev = dev_priv->dev;
6286
6287 /*
6288 * After we re-enable the power well, if we touch VGA register 0x3d5
6289 * we'll get unclaimed register interrupts. This stops after we write
6290 * anything to the VGA MSR register. The vgacon module uses this
6291 * register all the time, so if we unbind our driver and, as a
6292 * consequence, bind vgacon, we'll get stuck in an infinite loop at
6293 * console_unlock(). So make here we touch the VGA MSR register, making
6294 * sure vgacon can keep working normally without triggering interrupts
6295 * and error messages.
6296 */
6297 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
6298 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
6299 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
6300
6301 if (IS_BROADWELL(dev))
6302 gen8_irq_power_well_post_enable(dev_priv);
6303 }
6304
6305 static void hsw_set_power_well(struct drm_i915_private *dev_priv,
6306 struct i915_power_well *power_well, bool enable)
6307 {
6308 bool is_enabled, enable_requested;
6309 uint32_t tmp;
6310
6311 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
6312 is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
6313 enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
6314
6315 if (enable) {
6316 if (!enable_requested)
6317 I915_WRITE(HSW_PWR_WELL_DRIVER,
6318 HSW_PWR_WELL_ENABLE_REQUEST);
6319
6320 if (!is_enabled) {
6321 DRM_DEBUG_KMS("Enabling power well\n");
6322 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
6323 HSW_PWR_WELL_STATE_ENABLED), 20))
6324 DRM_ERROR("Timeout enabling power well\n");
6325 }
6326
6327 hsw_power_well_post_enable(dev_priv);
6328 } else {
6329 if (enable_requested) {
6330 I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
6331 POSTING_READ(HSW_PWR_WELL_DRIVER);
6332 DRM_DEBUG_KMS("Requesting to disable the power well\n");
6333 }
6334 }
6335 }
6336
6337 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
6338 struct i915_power_well *power_well)
6339 {
6340 hsw_set_power_well(dev_priv, power_well, power_well->count > 0);
6341
6342 /*
6343 * We're taking over the BIOS, so clear any requests made by it since
6344 * the driver is in charge now.
6345 */
6346 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
6347 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
6348 }
6349
6350 static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
6351 struct i915_power_well *power_well)
6352 {
6353 hsw_set_power_well(dev_priv, power_well, true);
6354 }
6355
6356 static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
6357 struct i915_power_well *power_well)
6358 {
6359 hsw_set_power_well(dev_priv, power_well, false);
6360 }
6361
6362 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
6363 struct i915_power_well *power_well)
6364 {
6365 }
6366
6367 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
6368 struct i915_power_well *power_well)
6369 {
6370 return true;
6371 }
6372
6373 static void vlv_set_power_well(struct drm_i915_private *dev_priv,
6374 struct i915_power_well *power_well, bool enable)
6375 {
6376 enum punit_power_well power_well_id = power_well->data;
6377 u32 mask;
6378 u32 state;
6379 u32 ctrl;
6380
6381 mask = PUNIT_PWRGT_MASK(power_well_id);
6382 state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) :
6383 PUNIT_PWRGT_PWR_GATE(power_well_id);
6384
6385 mutex_lock(&dev_priv->rps.hw_lock);
6386
6387 #define COND \
6388 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
6389
6390 if (COND)
6391 goto out;
6392
6393 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
6394 ctrl &= ~mask;
6395 ctrl |= state;
6396 vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
6397
6398 if (wait_for(COND, 100))
6399 DRM_ERROR("timout setting power well state %08x (%08x)\n",
6400 state,
6401 vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
6402
6403 #undef COND
6404
6405 out:
6406 mutex_unlock(&dev_priv->rps.hw_lock);
6407 }
6408
6409 static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv,
6410 struct i915_power_well *power_well)
6411 {
6412 vlv_set_power_well(dev_priv, power_well, power_well->count > 0);
6413 }
6414
6415 static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
6416 struct i915_power_well *power_well)
6417 {
6418 vlv_set_power_well(dev_priv, power_well, true);
6419 }
6420
6421 static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
6422 struct i915_power_well *power_well)
6423 {
6424 vlv_set_power_well(dev_priv, power_well, false);
6425 }
6426
6427 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
6428 struct i915_power_well *power_well)
6429 {
6430 int power_well_id = power_well->data;
6431 bool enabled = false;
6432 u32 mask;
6433 u32 state;
6434 u32 ctrl;
6435
6436 mask = PUNIT_PWRGT_MASK(power_well_id);
6437 ctrl = PUNIT_PWRGT_PWR_ON(power_well_id);
6438
6439 mutex_lock(&dev_priv->rps.hw_lock);
6440
6441 state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
6442 /*
6443 * We only ever set the power-on and power-gate states, anything
6444 * else is unexpected.
6445 */
6446 WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) &&
6447 state != PUNIT_PWRGT_PWR_GATE(power_well_id));
6448 if (state == ctrl)
6449 enabled = true;
6450
6451 /*
6452 * A transient state at this point would mean some unexpected party
6453 * is poking at the power controls too.
6454 */
6455 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
6456 WARN_ON(ctrl != state);
6457
6458 mutex_unlock(&dev_priv->rps.hw_lock);
6459
6460 return enabled;
6461 }
6462
6463 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
6464 struct i915_power_well *power_well)
6465 {
6466 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
6467
6468 vlv_set_power_well(dev_priv, power_well, true);
6469
6470 spin_lock_irq(&dev_priv->irq_lock);
6471 valleyview_enable_display_irqs(dev_priv);
6472 spin_unlock_irq(&dev_priv->irq_lock);
6473
6474 /*
6475 * During driver initialization/resume we can avoid restoring the
6476 * part of the HW/SW state that will be inited anyway explicitly.
6477 */
6478 if (dev_priv->power_domains.initializing)
6479 return;
6480
6481 intel_hpd_init(dev_priv->dev);
6482
6483 i915_redisable_vga_power_on(dev_priv->dev);
6484 }
6485
6486 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
6487 struct i915_power_well *power_well)
6488 {
6489 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
6490
6491 spin_lock_irq(&dev_priv->irq_lock);
6492 valleyview_disable_display_irqs(dev_priv);
6493 spin_unlock_irq(&dev_priv->irq_lock);
6494
6495 vlv_set_power_well(dev_priv, power_well, false);
6496
6497 vlv_power_sequencer_reset(dev_priv);
6498 }
6499
6500 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
6501 struct i915_power_well *power_well)
6502 {
6503 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
6504
6505 /*
6506 * Enable the CRI clock source so we can get at the
6507 * display and the reference clock for VGA
6508 * hotplug / manual detection.
6509 */
6510 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
6511 DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
6512 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
6513
6514 vlv_set_power_well(dev_priv, power_well, true);
6515
6516 /*
6517 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
6518 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
6519 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
6520 * b. The other bits such as sfr settings / modesel may all
6521 * be set to 0.
6522 *
6523 * This should only be done on init and resume from S3 with
6524 * both PLLs disabled, or we risk losing DPIO and PLL
6525 * synchronization.
6526 */
6527 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
6528 }
6529
6530 static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
6531 struct i915_power_well *power_well)
6532 {
6533 enum pipe pipe;
6534
6535 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
6536
6537 for_each_pipe(dev_priv, pipe)
6538 assert_pll_disabled(dev_priv, pipe);
6539
6540 /* Assert common reset */
6541 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST);
6542
6543 vlv_set_power_well(dev_priv, power_well, false);
6544 }
6545
6546 static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
6547 struct i915_power_well *power_well)
6548 {
6549 enum dpio_phy phy;
6550
6551 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
6552 power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
6553
6554 /*
6555 * Enable the CRI clock source so we can get at the
6556 * display and the reference clock for VGA
6557 * hotplug / manual detection.
6558 */
6559 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
6560 phy = DPIO_PHY0;
6561 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
6562 DPLL_REFA_CLK_ENABLE_VLV);
6563 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
6564 DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
6565 } else {
6566 phy = DPIO_PHY1;
6567 I915_WRITE(DPLL(PIPE_C), I915_READ(DPLL(PIPE_C)) |
6568 DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
6569 }
6570 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
6571 vlv_set_power_well(dev_priv, power_well, true);
6572
6573 /* Poll for phypwrgood signal */
6574 if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1))
6575 DRM_ERROR("Display PHY %d is not power up\n", phy);
6576
6577 I915_WRITE(DISPLAY_PHY_CONTROL, I915_READ(DISPLAY_PHY_CONTROL) |
6578 PHY_COM_LANE_RESET_DEASSERT(phy));
6579 }
6580
6581 static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
6582 struct i915_power_well *power_well)
6583 {
6584 enum dpio_phy phy;
6585
6586 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
6587 power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
6588
6589 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
6590 phy = DPIO_PHY0;
6591 assert_pll_disabled(dev_priv, PIPE_A);
6592 assert_pll_disabled(dev_priv, PIPE_B);
6593 } else {
6594 phy = DPIO_PHY1;
6595 assert_pll_disabled(dev_priv, PIPE_C);
6596 }
6597
6598 I915_WRITE(DISPLAY_PHY_CONTROL, I915_READ(DISPLAY_PHY_CONTROL) &
6599 ~PHY_COM_LANE_RESET_DEASSERT(phy));
6600
6601 vlv_set_power_well(dev_priv, power_well, false);
6602 }
6603
6604 static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,
6605 struct i915_power_well *power_well)
6606 {
6607 enum pipe pipe = power_well->data;
6608 bool enabled;
6609 u32 state, ctrl;
6610
6611 mutex_lock(&dev_priv->rps.hw_lock);
6612
6613 state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe);
6614 /*
6615 * We only ever set the power-on and power-gate states, anything
6616 * else is unexpected.
6617 */
6618 WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe));
6619 enabled = state == DP_SSS_PWR_ON(pipe);
6620
6621 /*
6622 * A transient state at this point would mean some unexpected party
6623 * is poking at the power controls too.
6624 */
6625 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe);
6626 WARN_ON(ctrl << 16 != state);
6627
6628 mutex_unlock(&dev_priv->rps.hw_lock);
6629
6630 return enabled;
6631 }
6632
6633 static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
6634 struct i915_power_well *power_well,
6635 bool enable)
6636 {
6637 enum pipe pipe = power_well->data;
6638 u32 state;
6639 u32 ctrl;
6640
6641 state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe);
6642
6643 mutex_lock(&dev_priv->rps.hw_lock);
6644
6645 #define COND \
6646 ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state)
6647
6648 if (COND)
6649 goto out;
6650
6651 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
6652 ctrl &= ~DP_SSC_MASK(pipe);
6653 ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe);
6654 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl);
6655
6656 if (wait_for(COND, 100))
6657 DRM_ERROR("timout setting power well state %08x (%08x)\n",
6658 state,
6659 vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ));
6660
6661 #undef COND
6662
6663 out:
6664 mutex_unlock(&dev_priv->rps.hw_lock);
6665 }
6666
6667 static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv,
6668 struct i915_power_well *power_well)
6669 {
6670 chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0);
6671 }
6672
6673 static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
6674 struct i915_power_well *power_well)
6675 {
6676 WARN_ON_ONCE(power_well->data != PIPE_A &&
6677 power_well->data != PIPE_B &&
6678 power_well->data != PIPE_C);
6679
6680 chv_set_pipe_power_well(dev_priv, power_well, true);
6681 }
6682
6683 static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
6684 struct i915_power_well *power_well)
6685 {
6686 WARN_ON_ONCE(power_well->data != PIPE_A &&
6687 power_well->data != PIPE_B &&
6688 power_well->data != PIPE_C);
6689
6690 chv_set_pipe_power_well(dev_priv, power_well, false);
6691 }
6692
6693 static void check_power_well_state(struct drm_i915_private *dev_priv,
6694 struct i915_power_well *power_well)
6695 {
6696 bool enabled = power_well->ops->is_enabled(dev_priv, power_well);
6697
6698 if (power_well->always_on || !i915.disable_power_well) {
6699 if (!enabled)
6700 goto mismatch;
6701
6702 return;
6703 }
6704
6705 if (enabled != (power_well->count > 0))
6706 goto mismatch;
6707
6708 return;
6709
6710 mismatch:
6711 WARN(1, "state mismatch for '%s' (always_on %d hw state %d use-count %d disable_power_well %d\n",
6712 power_well->name, power_well->always_on, enabled,
6713 power_well->count, i915.disable_power_well);
6714 }
6715
6716 void intel_display_power_get(struct drm_i915_private *dev_priv,
6717 enum intel_display_power_domain domain)
6718 {
6719 struct i915_power_domains *power_domains;
6720 struct i915_power_well *power_well;
6721 int i;
6722
6723 intel_runtime_pm_get(dev_priv);
6724
6725 power_domains = &dev_priv->power_domains;
6726
6727 mutex_lock(&power_domains->lock);
6728
6729 for_each_power_well(i, power_well, BIT(domain), power_domains) {
6730 if (!power_well->count++) {
6731 DRM_DEBUG_KMS("enabling %s\n", power_well->name);
6732 power_well->ops->enable(dev_priv, power_well);
6733 power_well->hw_enabled = true;
6734 }
6735
6736 check_power_well_state(dev_priv, power_well);
6737 }
6738
6739 power_domains->domain_use_count[domain]++;
6740
6741 mutex_unlock(&power_domains->lock);
6742 }
6743
6744 void intel_display_power_put(struct drm_i915_private *dev_priv,
6745 enum intel_display_power_domain domain)
6746 {
6747 struct i915_power_domains *power_domains;
6748 struct i915_power_well *power_well;
6749 int i;
6750
6751 power_domains = &dev_priv->power_domains;
6752
6753 mutex_lock(&power_domains->lock);
6754
6755 WARN_ON(!power_domains->domain_use_count[domain]);
6756 power_domains->domain_use_count[domain]--;
6757
6758 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
6759 WARN_ON(!power_well->count);
6760
6761 if (!--power_well->count && i915.disable_power_well) {
6762 DRM_DEBUG_KMS("disabling %s\n", power_well->name);
6763 power_well->hw_enabled = false;
6764 power_well->ops->disable(dev_priv, power_well);
6765 }
6766
6767 check_power_well_state(dev_priv, power_well);
6768 }
6769
6770 mutex_unlock(&power_domains->lock);
6771
6772 intel_runtime_pm_put(dev_priv);
6773 }
6774
6775 static struct i915_power_domains *hsw_pwr;
6776
6777 /* Display audio driver power well request */
6778 int i915_request_power_well(void)
6779 {
6780 struct drm_i915_private *dev_priv;
6781
6782 if (!hsw_pwr)
6783 return -ENODEV;
6784
6785 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
6786 power_domains);
6787 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
6788 return 0;
6789 }
6790 EXPORT_SYMBOL_GPL(i915_request_power_well);
6791
6792 /* Display audio driver power well release */
6793 int i915_release_power_well(void)
6794 {
6795 struct drm_i915_private *dev_priv;
6796
6797 if (!hsw_pwr)
6798 return -ENODEV;
6799
6800 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
6801 power_domains);
6802 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
6803 return 0;
6804 }
6805 EXPORT_SYMBOL_GPL(i915_release_power_well);
6806
6807 /*
6808 * Private interface for the audio driver to get CDCLK in kHz.
6809 *
6810 * Caller must request power well using i915_request_power_well() prior to
6811 * making the call.
6812 */
6813 int i915_get_cdclk_freq(void)
6814 {
6815 struct drm_i915_private *dev_priv;
6816
6817 if (!hsw_pwr)
6818 return -ENODEV;
6819
6820 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
6821 power_domains);
6822
6823 return intel_ddi_get_cdclk_freq(dev_priv);
6824 }
6825 EXPORT_SYMBOL_GPL(i915_get_cdclk_freq);
6826
6827
6828 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
6829
6830 #define HSW_ALWAYS_ON_POWER_DOMAINS ( \
6831 BIT(POWER_DOMAIN_PIPE_A) | \
6832 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
6833 BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
6834 BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
6835 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6836 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6837 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6838 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6839 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
6840 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
6841 BIT(POWER_DOMAIN_PORT_CRT) | \
6842 BIT(POWER_DOMAIN_PLLS) | \
6843 BIT(POWER_DOMAIN_INIT))
6844 #define HSW_DISPLAY_POWER_DOMAINS ( \
6845 (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \
6846 BIT(POWER_DOMAIN_INIT))
6847
6848 #define BDW_ALWAYS_ON_POWER_DOMAINS ( \
6849 HSW_ALWAYS_ON_POWER_DOMAINS | \
6850 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
6851 #define BDW_DISPLAY_POWER_DOMAINS ( \
6852 (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) | \
6853 BIT(POWER_DOMAIN_INIT))
6854
6855 #define VLV_ALWAYS_ON_POWER_DOMAINS BIT(POWER_DOMAIN_INIT)
6856 #define VLV_DISPLAY_POWER_DOMAINS POWER_DOMAIN_MASK
6857
6858 #define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \
6859 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6860 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6861 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6862 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6863 BIT(POWER_DOMAIN_PORT_CRT) | \
6864 BIT(POWER_DOMAIN_INIT))
6865
6866 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \
6867 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6868 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6869 BIT(POWER_DOMAIN_INIT))
6870
6871 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \
6872 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6873 BIT(POWER_DOMAIN_INIT))
6874
6875 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \
6876 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6877 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6878 BIT(POWER_DOMAIN_INIT))
6879
6880 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \
6881 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6882 BIT(POWER_DOMAIN_INIT))
6883
6884 #define CHV_PIPE_A_POWER_DOMAINS ( \
6885 BIT(POWER_DOMAIN_PIPE_A) | \
6886 BIT(POWER_DOMAIN_INIT))
6887
6888 #define CHV_PIPE_B_POWER_DOMAINS ( \
6889 BIT(POWER_DOMAIN_PIPE_B) | \
6890 BIT(POWER_DOMAIN_INIT))
6891
6892 #define CHV_PIPE_C_POWER_DOMAINS ( \
6893 BIT(POWER_DOMAIN_PIPE_C) | \
6894 BIT(POWER_DOMAIN_INIT))
6895
6896 #define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \
6897 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6898 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6899 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6900 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6901 BIT(POWER_DOMAIN_INIT))
6902
6903 #define CHV_DPIO_CMN_D_POWER_DOMAINS ( \
6904 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
6905 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
6906 BIT(POWER_DOMAIN_INIT))
6907
6908 #define CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS ( \
6909 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
6910 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
6911 BIT(POWER_DOMAIN_INIT))
6912
6913 #define CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS ( \
6914 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
6915 BIT(POWER_DOMAIN_INIT))
6916
6917 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
6918 .sync_hw = i9xx_always_on_power_well_noop,
6919 .enable = i9xx_always_on_power_well_noop,
6920 .disable = i9xx_always_on_power_well_noop,
6921 .is_enabled = i9xx_always_on_power_well_enabled,
6922 };
6923
6924 static const struct i915_power_well_ops chv_pipe_power_well_ops = {
6925 .sync_hw = chv_pipe_power_well_sync_hw,
6926 .enable = chv_pipe_power_well_enable,
6927 .disable = chv_pipe_power_well_disable,
6928 .is_enabled = chv_pipe_power_well_enabled,
6929 };
6930
6931 static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = {
6932 .sync_hw = vlv_power_well_sync_hw,
6933 .enable = chv_dpio_cmn_power_well_enable,
6934 .disable = chv_dpio_cmn_power_well_disable,
6935 .is_enabled = vlv_power_well_enabled,
6936 };
6937
6938 static struct i915_power_well i9xx_always_on_power_well[] = {
6939 {
6940 .name = "always-on",
6941 .always_on = 1,
6942 .domains = POWER_DOMAIN_MASK,
6943 .ops = &i9xx_always_on_power_well_ops,
6944 },
6945 };
6946
6947 static const struct i915_power_well_ops hsw_power_well_ops = {
6948 .sync_hw = hsw_power_well_sync_hw,
6949 .enable = hsw_power_well_enable,
6950 .disable = hsw_power_well_disable,
6951 .is_enabled = hsw_power_well_enabled,
6952 };
6953
6954 static struct i915_power_well hsw_power_wells[] = {
6955 {
6956 .name = "always-on",
6957 .always_on = 1,
6958 .domains = HSW_ALWAYS_ON_POWER_DOMAINS,
6959 .ops = &i9xx_always_on_power_well_ops,
6960 },
6961 {
6962 .name = "display",
6963 .domains = HSW_DISPLAY_POWER_DOMAINS,
6964 .ops = &hsw_power_well_ops,
6965 },
6966 };
6967
6968 static struct i915_power_well bdw_power_wells[] = {
6969 {
6970 .name = "always-on",
6971 .always_on = 1,
6972 .domains = BDW_ALWAYS_ON_POWER_DOMAINS,
6973 .ops = &i9xx_always_on_power_well_ops,
6974 },
6975 {
6976 .name = "display",
6977 .domains = BDW_DISPLAY_POWER_DOMAINS,
6978 .ops = &hsw_power_well_ops,
6979 },
6980 };
6981
6982 static const struct i915_power_well_ops vlv_display_power_well_ops = {
6983 .sync_hw = vlv_power_well_sync_hw,
6984 .enable = vlv_display_power_well_enable,
6985 .disable = vlv_display_power_well_disable,
6986 .is_enabled = vlv_power_well_enabled,
6987 };
6988
6989 static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = {
6990 .sync_hw = vlv_power_well_sync_hw,
6991 .enable = vlv_dpio_cmn_power_well_enable,
6992 .disable = vlv_dpio_cmn_power_well_disable,
6993 .is_enabled = vlv_power_well_enabled,
6994 };
6995
6996 static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
6997 .sync_hw = vlv_power_well_sync_hw,
6998 .enable = vlv_power_well_enable,
6999 .disable = vlv_power_well_disable,
7000 .is_enabled = vlv_power_well_enabled,
7001 };
7002
7003 static struct i915_power_well vlv_power_wells[] = {
7004 {
7005 .name = "always-on",
7006 .always_on = 1,
7007 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
7008 .ops = &i9xx_always_on_power_well_ops,
7009 },
7010 {
7011 .name = "display",
7012 .domains = VLV_DISPLAY_POWER_DOMAINS,
7013 .data = PUNIT_POWER_WELL_DISP2D,
7014 .ops = &vlv_display_power_well_ops,
7015 },
7016 {
7017 .name = "dpio-tx-b-01",
7018 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
7019 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
7020 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
7021 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
7022 .ops = &vlv_dpio_power_well_ops,
7023 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
7024 },
7025 {
7026 .name = "dpio-tx-b-23",
7027 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
7028 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
7029 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
7030 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
7031 .ops = &vlv_dpio_power_well_ops,
7032 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
7033 },
7034 {
7035 .name = "dpio-tx-c-01",
7036 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
7037 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
7038 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
7039 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
7040 .ops = &vlv_dpio_power_well_ops,
7041 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
7042 },
7043 {
7044 .name = "dpio-tx-c-23",
7045 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
7046 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
7047 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
7048 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
7049 .ops = &vlv_dpio_power_well_ops,
7050 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
7051 },
7052 {
7053 .name = "dpio-common",
7054 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
7055 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
7056 .ops = &vlv_dpio_cmn_power_well_ops,
7057 },
7058 };
7059
7060 static struct i915_power_well chv_power_wells[] = {
7061 {
7062 .name = "always-on",
7063 .always_on = 1,
7064 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
7065 .ops = &i9xx_always_on_power_well_ops,
7066 },
7067 #if 0
7068 {
7069 .name = "display",
7070 .domains = VLV_DISPLAY_POWER_DOMAINS,
7071 .data = PUNIT_POWER_WELL_DISP2D,
7072 .ops = &vlv_display_power_well_ops,
7073 },
7074 {
7075 .name = "pipe-a",
7076 .domains = CHV_PIPE_A_POWER_DOMAINS,
7077 .data = PIPE_A,
7078 .ops = &chv_pipe_power_well_ops,
7079 },
7080 {
7081 .name = "pipe-b",
7082 .domains = CHV_PIPE_B_POWER_DOMAINS,
7083 .data = PIPE_B,
7084 .ops = &chv_pipe_power_well_ops,
7085 },
7086 {
7087 .name = "pipe-c",
7088 .domains = CHV_PIPE_C_POWER_DOMAINS,
7089 .data = PIPE_C,
7090 .ops = &chv_pipe_power_well_ops,
7091 },
7092 #endif
7093 {
7094 .name = "dpio-common-bc",
7095 /*
7096 * XXX: cmnreset for one PHY seems to disturb the other.
7097 * As a workaround keep both powered on at the same
7098 * time for now.
7099 */
7100 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS | CHV_DPIO_CMN_D_POWER_DOMAINS,
7101 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
7102 .ops = &chv_dpio_cmn_power_well_ops,
7103 },
7104 {
7105 .name = "dpio-common-d",
7106 /*
7107 * XXX: cmnreset for one PHY seems to disturb the other.
7108 * As a workaround keep both powered on at the same
7109 * time for now.
7110 */
7111 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS | CHV_DPIO_CMN_D_POWER_DOMAINS,
7112 .data = PUNIT_POWER_WELL_DPIO_CMN_D,
7113 .ops = &chv_dpio_cmn_power_well_ops,
7114 },
7115 #if 0
7116 {
7117 .name = "dpio-tx-b-01",
7118 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
7119 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS,
7120 .ops = &vlv_dpio_power_well_ops,
7121 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
7122 },
7123 {
7124 .name = "dpio-tx-b-23",
7125 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
7126 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS,
7127 .ops = &vlv_dpio_power_well_ops,
7128 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
7129 },
7130 {
7131 .name = "dpio-tx-c-01",
7132 .domains = VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
7133 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
7134 .ops = &vlv_dpio_power_well_ops,
7135 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
7136 },
7137 {
7138 .name = "dpio-tx-c-23",
7139 .domains = VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
7140 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
7141 .ops = &vlv_dpio_power_well_ops,
7142 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
7143 },
7144 {
7145 .name = "dpio-tx-d-01",
7146 .domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS |
7147 CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS,
7148 .ops = &vlv_dpio_power_well_ops,
7149 .data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_01,
7150 },
7151 {
7152 .name = "dpio-tx-d-23",
7153 .domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS |
7154 CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS,
7155 .ops = &vlv_dpio_power_well_ops,
7156 .data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_23,
7157 },
7158 #endif
7159 };
7160
7161 static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv,
7162 enum punit_power_well power_well_id)
7163 {
7164 struct i915_power_domains *power_domains = &dev_priv->power_domains;
7165 struct i915_power_well *power_well;
7166 int i;
7167
7168 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
7169 if (power_well->data == power_well_id)
7170 return power_well;
7171 }
7172
7173 return NULL;
7174 }
7175
7176 #define set_power_wells(power_domains, __power_wells) ({ \
7177 (power_domains)->power_wells = (__power_wells); \
7178 (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \
7179 })
7180
7181 int intel_power_domains_init(struct drm_i915_private *dev_priv)
7182 {
7183 struct i915_power_domains *power_domains = &dev_priv->power_domains;
7184
7185 mutex_init(&power_domains->lock);
7186
7187 /*
7188 * The enabling order will be from lower to higher indexed wells,
7189 * the disabling order is reversed.
7190 */
7191 if (IS_HASWELL(dev_priv->dev)) {
7192 set_power_wells(power_domains, hsw_power_wells);
7193 hsw_pwr = power_domains;
7194 } else if (IS_BROADWELL(dev_priv->dev)) {
7195 set_power_wells(power_domains, bdw_power_wells);
7196 hsw_pwr = power_domains;
7197 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
7198 set_power_wells(power_domains, chv_power_wells);
7199 } else if (IS_VALLEYVIEW(dev_priv->dev)) {
7200 set_power_wells(power_domains, vlv_power_wells);
7201 } else {
7202 set_power_wells(power_domains, i9xx_always_on_power_well);
7203 }
7204
7205 return 0;
7206 }
7207
7208 void intel_power_domains_remove(struct drm_i915_private *dev_priv)
7209 {
7210 hsw_pwr = NULL;
7211 }
7212
7213 static void intel_power_domains_resume(struct drm_i915_private *dev_priv)
7214 {
7215 struct i915_power_domains *power_domains = &dev_priv->power_domains;
7216 struct i915_power_well *power_well;
7217 int i;
7218
7219 mutex_lock(&power_domains->lock);
7220 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
7221 power_well->ops->sync_hw(dev_priv, power_well);
7222 power_well->hw_enabled = power_well->ops->is_enabled(dev_priv,
7223 power_well);
7224 }
7225 mutex_unlock(&power_domains->lock);
7226 }
7227
7228 static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
7229 {
7230 struct i915_power_well *cmn =
7231 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
7232 struct i915_power_well *disp2d =
7233 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D);
7234
7235 /* nothing to do if common lane is already off */
7236 if (!cmn->ops->is_enabled(dev_priv, cmn))
7237 return;
7238
7239 /* If the display might be already active skip this */
7240 if (disp2d->ops->is_enabled(dev_priv, disp2d) &&
7241 I915_READ(DPIO_CTL) & DPIO_CMNRST)
7242 return;
7243
7244 DRM_DEBUG_KMS("toggling display PHY side reset\n");
7245
7246 /* cmnlane needs DPLL registers */
7247 disp2d->ops->enable(dev_priv, disp2d);
7248
7249 /*
7250 * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
7251 * Need to assert and de-assert PHY SB reset by gating the
7252 * common lane power, then un-gating it.
7253 * Simply ungating isn't enough to reset the PHY enough to get
7254 * ports and lanes running.
7255 */
7256 cmn->ops->disable(dev_priv, cmn);
7257 }
7258
7259 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv)
7260 {
7261 struct drm_device *dev = dev_priv->dev;
7262 struct i915_power_domains *power_domains = &dev_priv->power_domains;
7263
7264 power_domains->initializing = true;
7265
7266 if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
7267 mutex_lock(&power_domains->lock);
7268 vlv_cmnlane_wa(dev_priv);
7269 mutex_unlock(&power_domains->lock);
7270 }
7271
7272 /* For now, we need the power well to be always enabled. */
7273 intel_display_set_init_power(dev_priv, true);
7274 intel_power_domains_resume(dev_priv);
7275 power_domains->initializing = false;
7276 }
7277
7278 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)
7279 {
7280 intel_runtime_pm_get(dev_priv);
7281 }
7282
7283 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)
7284 {
7285 intel_runtime_pm_put(dev_priv);
7286 }
7287
7288 void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
7289 {
7290 struct drm_device *dev = dev_priv->dev;
7291 struct device *device = &dev->pdev->dev;
7292
7293 if (!HAS_RUNTIME_PM(dev))
7294 return;
7295
7296 pm_runtime_get_sync(device);
7297 WARN(dev_priv->pm.suspended, "Device still suspended.\n");
7298 }
7299
7300 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv)
7301 {
7302 struct drm_device *dev = dev_priv->dev;
7303 struct device *device = &dev->pdev->dev;
7304
7305 if (!HAS_RUNTIME_PM(dev))
7306 return;
7307
7308 WARN(dev_priv->pm.suspended, "Getting nosync-ref while suspended.\n");
7309 pm_runtime_get_noresume(device);
7310 }
7311
7312 void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
7313 {
7314 struct drm_device *dev = dev_priv->dev;
7315 struct device *device = &dev->pdev->dev;
7316
7317 if (!HAS_RUNTIME_PM(dev))
7318 return;
7319
7320 pm_runtime_mark_last_busy(device);
7321 pm_runtime_put_autosuspend(device);
7322 }
7323
7324 void intel_init_runtime_pm(struct drm_i915_private *dev_priv)
7325 {
7326 struct drm_device *dev = dev_priv->dev;
7327 struct device *device = &dev->pdev->dev;
7328
7329 if (!HAS_RUNTIME_PM(dev))
7330 return;
7331
7332 pm_runtime_set_active(device);
7333
7334 /*
7335 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
7336 * requirement.
7337 */
7338 if (!intel_enable_rc6(dev)) {
7339 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
7340 return;
7341 }
7342
7343 pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
7344 pm_runtime_mark_last_busy(device);
7345 pm_runtime_use_autosuspend(device);
7346
7347 pm_runtime_put_autosuspend(device);
7348 }
7349
7350 void intel_fini_runtime_pm(struct drm_i915_private *dev_priv)
7351 {
7352 struct drm_device *dev = dev_priv->dev;
7353 struct device *device = &dev->pdev->dev;
7354
7355 if (!HAS_RUNTIME_PM(dev))
7356 return;
7357
7358 if (!intel_enable_rc6(dev))
7359 return;
7360
7361 /* Make sure we're not suspended first. */
7362 pm_runtime_get_sync(device);
7363 pm_runtime_disable(device);
7364 }
7365
7366 static void intel_init_fbc(struct drm_i915_private *dev_priv)
7367 {
7368 if (!HAS_FBC(dev_priv)) {
7369 dev_priv->fbc.enabled = false;
7370 return;
7371 }
7372
7373 if (INTEL_INFO(dev_priv)->gen >= 7) {
7374 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
7375 dev_priv->display.enable_fbc = gen7_enable_fbc;
7376 dev_priv->display.disable_fbc = ironlake_disable_fbc;
7377 } else if (INTEL_INFO(dev_priv)->gen >= 5) {
7378 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
7379 dev_priv->display.enable_fbc = ironlake_enable_fbc;
7380 dev_priv->display.disable_fbc = ironlake_disable_fbc;
7381 } else if (IS_GM45(dev_priv)) {
7382 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
7383 dev_priv->display.enable_fbc = g4x_enable_fbc;
7384 dev_priv->display.disable_fbc = g4x_disable_fbc;
7385 } else {
7386 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
7387 dev_priv->display.enable_fbc = i8xx_enable_fbc;
7388 dev_priv->display.disable_fbc = i8xx_disable_fbc;
7389
7390 /* This value was pulled out of someone's hat */
7391 I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);
7392 }
7393
7394 dev_priv->fbc.enabled = dev_priv->display.fbc_enabled(dev_priv->dev);
7395 }
7396
7397 /* Set up chip specific power management-related functions */
7398 void intel_init_pm(struct drm_device *dev)
7399 {
7400 struct drm_i915_private *dev_priv = dev->dev_private;
7401
7402 intel_init_fbc(dev_priv);
7403
7404 /* For cxsr */
7405 if (IS_PINEVIEW(dev))
7406 i915_pineview_get_mem_freq(dev);
7407 else if (IS_GEN5(dev))
7408 i915_ironlake_get_mem_freq(dev);
7409
7410 /* For FIFO watermark updates */
7411 if (HAS_PCH_SPLIT(dev)) {
7412 ilk_setup_wm_latency(dev);
7413
7414 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
7415 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7416 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7417 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
7418 dev_priv->display.update_wm = ilk_update_wm;
7419 dev_priv->display.update_sprite_wm = ilk_update_sprite_wm;
7420 } else {
7421 DRM_DEBUG_KMS("Failed to read display plane latency. "
7422 "Disable CxSR\n");
7423 }
7424
7425 if (IS_GEN5(dev))
7426 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7427 else if (IS_GEN6(dev))
7428 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7429 else if (IS_IVYBRIDGE(dev))
7430 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7431 else if (IS_HASWELL(dev))
7432 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7433 else if (INTEL_INFO(dev)->gen == 8)
7434 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7435 } else if (IS_CHERRYVIEW(dev)) {
7436 dev_priv->display.update_wm = cherryview_update_wm;
7437 dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;
7438 dev_priv->display.init_clock_gating =
7439 cherryview_init_clock_gating;
7440 } else if (IS_VALLEYVIEW(dev)) {
7441 dev_priv->display.update_wm = valleyview_update_wm;
7442 dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;
7443 dev_priv->display.init_clock_gating =
7444 valleyview_init_clock_gating;
7445 } else if (IS_PINEVIEW(dev)) {
7446 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7447 dev_priv->is_ddr3,
7448 dev_priv->fsb_freq,
7449 dev_priv->mem_freq)) {
7450 DRM_INFO("failed to find known CxSR latency "
7451 "(found ddr%s fsb freq %d, mem freq %d), "
7452 "disabling CxSR\n",
7453 (dev_priv->is_ddr3 == 1) ? "3" : "2",
7454 dev_priv->fsb_freq, dev_priv->mem_freq);
7455 /* Disable CxSR and never update its watermark again */
7456 intel_set_memory_cxsr(dev_priv, false);
7457 dev_priv->display.update_wm = NULL;
7458 } else
7459 dev_priv->display.update_wm = pineview_update_wm;
7460 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7461 } else if (IS_G4X(dev)) {
7462 dev_priv->display.update_wm = g4x_update_wm;
7463 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7464 } else if (IS_GEN4(dev)) {
7465 dev_priv->display.update_wm = i965_update_wm;
7466 if (IS_CRESTLINE(dev))
7467 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7468 else if (IS_BROADWATER(dev))
7469 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7470 } else if (IS_GEN3(dev)) {
7471 dev_priv->display.update_wm = i9xx_update_wm;
7472 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7473 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7474 } else if (IS_GEN2(dev)) {
7475 if (INTEL_INFO(dev)->num_pipes == 1) {
7476 dev_priv->display.update_wm = i845_update_wm;
7477 dev_priv->display.get_fifo_size = i845_get_fifo_size;
7478 } else {
7479 dev_priv->display.update_wm = i9xx_update_wm;
7480 dev_priv->display.get_fifo_size = i830_get_fifo_size;
7481 }
7482
7483 if (IS_I85X(dev) || IS_I865G(dev))
7484 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7485 else
7486 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7487 } else {
7488 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
7489 }
7490 }
7491
7492 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
7493 {
7494 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7495
7496 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7497 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7498 return -EAGAIN;
7499 }
7500
7501 I915_WRITE(GEN6_PCODE_DATA, *val);
7502 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7503
7504 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7505 500)) {
7506 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7507 return -ETIMEDOUT;
7508 }
7509
7510 *val = I915_READ(GEN6_PCODE_DATA);
7511 I915_WRITE(GEN6_PCODE_DATA, 0);
7512
7513 return 0;
7514 }
7515
7516 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
7517 {
7518 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7519
7520 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7521 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7522 return -EAGAIN;
7523 }
7524
7525 I915_WRITE(GEN6_PCODE_DATA, val);
7526 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7527
7528 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7529 500)) {
7530 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7531 return -ETIMEDOUT;
7532 }
7533
7534 I915_WRITE(GEN6_PCODE_DATA, 0);
7535
7536 return 0;
7537 }
7538
7539 static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7540 {
7541 int div;
7542
7543 /* 4 x czclk */
7544 switch (dev_priv->mem_freq) {
7545 case 800:
7546 div = 10;
7547 break;
7548 case 1066:
7549 div = 12;
7550 break;
7551 case 1333:
7552 div = 16;
7553 break;
7554 default:
7555 return -1;
7556 }
7557
7558 return DIV_ROUND_CLOSEST(dev_priv->mem_freq * (val + 6 - 0xbd), 4 * div);
7559 }
7560
7561 static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
7562 {
7563 int mul;
7564
7565 /* 4 x czclk */
7566 switch (dev_priv->mem_freq) {
7567 case 800:
7568 mul = 10;
7569 break;
7570 case 1066:
7571 mul = 12;
7572 break;
7573 case 1333:
7574 mul = 16;
7575 break;
7576 default:
7577 return -1;
7578 }
7579
7580 return DIV_ROUND_CLOSEST(4 * mul * val, dev_priv->mem_freq) + 0xbd - 6;
7581 }
7582
7583 static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
7584 {
7585 int div, freq;
7586
7587 switch (dev_priv->rps.cz_freq) {
7588 case 200:
7589 div = 5;
7590 break;
7591 case 267:
7592 div = 6;
7593 break;
7594 case 320:
7595 case 333:
7596 case 400:
7597 div = 8;
7598 break;
7599 default:
7600 return -1;
7601 }
7602
7603 freq = (DIV_ROUND_CLOSEST((dev_priv->rps.cz_freq * val), 2 * div) / 2);
7604
7605 return freq;
7606 }
7607
7608 static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
7609 {
7610 int mul, opcode;
7611
7612 switch (dev_priv->rps.cz_freq) {
7613 case 200:
7614 mul = 5;
7615 break;
7616 case 267:
7617 mul = 6;
7618 break;
7619 case 320:
7620 case 333:
7621 case 400:
7622 mul = 8;
7623 break;
7624 default:
7625 return -1;
7626 }
7627
7628 /* CHV needs even values */
7629 opcode = (DIV_ROUND_CLOSEST((val * 2 * mul), dev_priv->rps.cz_freq) * 2);
7630
7631 return opcode;
7632 }
7633
7634 int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val)
7635 {
7636 int ret = -1;
7637
7638 if (IS_CHERRYVIEW(dev_priv->dev))
7639 ret = chv_gpu_freq(dev_priv, val);
7640 else if (IS_VALLEYVIEW(dev_priv->dev))
7641 ret = byt_gpu_freq(dev_priv, val);
7642
7643 return ret;
7644 }
7645
7646 int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val)
7647 {
7648 int ret = -1;
7649
7650 if (IS_CHERRYVIEW(dev_priv->dev))
7651 ret = chv_freq_opcode(dev_priv, val);
7652 else if (IS_VALLEYVIEW(dev_priv->dev))
7653 ret = byt_freq_opcode(dev_priv, val);
7654
7655 return ret;
7656 }
7657
7658 void intel_pm_setup(struct drm_device *dev)
7659 {
7660 struct drm_i915_private *dev_priv = dev->dev_private;
7661
7662 mutex_init(&dev_priv->rps.hw_lock);
7663
7664 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
7665 intel_gen6_powersave_work);
7666
7667 dev_priv->pm.suspended = false;
7668 dev_priv->pm._irqs_disabled = false;
7669 }
Linux kernel - Deliverables
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