2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
28 #include <linux/cpufreq.h>
30 #include "intel_drv.h"
31 #include "../../../platform/x86/intel_ips.h"
32 #include <linux/module.h>
35 * RC6 is a special power stage which allows the GPU to enter an very
36 * low-voltage mode when idle, using down to 0V while at this stage. This
37 * stage is entered automatically when the GPU is idle when RC6 support is
38 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
40 * There are different RC6 modes available in Intel GPU, which differentiate
41 * among each other with the latency required to enter and leave RC6 and
42 * voltage consumed by the GPU in different states.
44 * The combination of the following flags define which states GPU is allowed
45 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
46 * RC6pp is deepest RC6. Their support by hardware varies according to the
47 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
48 * which brings the most power savings; deeper states save more power, but
49 * require higher latency to switch to and wake up.
51 #define INTEL_RC6_ENABLE (1<<0)
52 #define INTEL_RC6p_ENABLE (1<<1)
53 #define INTEL_RC6pp_ENABLE (1<<2)
55 static void bxt_init_clock_gating(struct drm_device
*dev
)
57 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
59 /* WaDisableSDEUnitClockGating:bxt */
60 I915_WRITE(GEN8_UCGCTL6
, I915_READ(GEN8_UCGCTL6
) |
61 GEN8_SDEUNIT_CLOCK_GATE_DISABLE
);
65 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
67 I915_WRITE(GEN8_UCGCTL6
, I915_READ(GEN8_UCGCTL6
) |
68 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ
);
71 * Wa: Backlight PWM may stop in the asserted state, causing backlight
74 if (IS_BXT_REVID(dev_priv
, BXT_REVID_B0
, REVID_FOREVER
))
75 I915_WRITE(GEN9_CLKGATE_DIS_0
, I915_READ(GEN9_CLKGATE_DIS_0
) |
76 PWM1_GATING_DIS
| PWM2_GATING_DIS
);
79 static void i915_pineview_get_mem_freq(struct drm_device
*dev
)
81 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
84 tmp
= I915_READ(CLKCFG
);
86 switch (tmp
& CLKCFG_FSB_MASK
) {
88 dev_priv
->fsb_freq
= 533; /* 133*4 */
91 dev_priv
->fsb_freq
= 800; /* 200*4 */
94 dev_priv
->fsb_freq
= 667; /* 167*4 */
97 dev_priv
->fsb_freq
= 400; /* 100*4 */
101 switch (tmp
& CLKCFG_MEM_MASK
) {
103 dev_priv
->mem_freq
= 533;
106 dev_priv
->mem_freq
= 667;
109 dev_priv
->mem_freq
= 800;
113 /* detect pineview DDR3 setting */
114 tmp
= I915_READ(CSHRDDR3CTL
);
115 dev_priv
->is_ddr3
= (tmp
& CSHRDDR3CTL_DDR3
) ? 1 : 0;
118 static void i915_ironlake_get_mem_freq(struct drm_device
*dev
)
120 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
123 ddrpll
= I915_READ16(DDRMPLL1
);
124 csipll
= I915_READ16(CSIPLL0
);
126 switch (ddrpll
& 0xff) {
128 dev_priv
->mem_freq
= 800;
131 dev_priv
->mem_freq
= 1066;
134 dev_priv
->mem_freq
= 1333;
137 dev_priv
->mem_freq
= 1600;
140 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
142 dev_priv
->mem_freq
= 0;
146 dev_priv
->ips
.r_t
= dev_priv
->mem_freq
;
148 switch (csipll
& 0x3ff) {
150 dev_priv
->fsb_freq
= 3200;
153 dev_priv
->fsb_freq
= 3733;
156 dev_priv
->fsb_freq
= 4266;
159 dev_priv
->fsb_freq
= 4800;
162 dev_priv
->fsb_freq
= 5333;
165 dev_priv
->fsb_freq
= 5866;
168 dev_priv
->fsb_freq
= 6400;
171 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
173 dev_priv
->fsb_freq
= 0;
177 if (dev_priv
->fsb_freq
== 3200) {
178 dev_priv
->ips
.c_m
= 0;
179 } else if (dev_priv
->fsb_freq
> 3200 && dev_priv
->fsb_freq
<= 4800) {
180 dev_priv
->ips
.c_m
= 1;
182 dev_priv
->ips
.c_m
= 2;
186 static const struct cxsr_latency cxsr_latency_table
[] = {
187 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
188 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
189 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
190 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
191 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
193 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
194 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
195 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
196 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
197 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
199 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
200 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
201 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
202 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
203 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
205 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
206 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
207 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
208 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
209 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
211 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
212 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
213 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
214 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
215 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
217 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
218 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
219 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
220 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
221 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
224 static const struct cxsr_latency
*intel_get_cxsr_latency(int is_desktop
,
229 const struct cxsr_latency
*latency
;
232 if (fsb
== 0 || mem
== 0)
235 for (i
= 0; i
< ARRAY_SIZE(cxsr_latency_table
); i
++) {
236 latency
= &cxsr_latency_table
[i
];
237 if (is_desktop
== latency
->is_desktop
&&
238 is_ddr3
== latency
->is_ddr3
&&
239 fsb
== latency
->fsb_freq
&& mem
== latency
->mem_freq
)
243 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
248 static void chv_set_memory_dvfs(struct drm_i915_private
*dev_priv
, bool enable
)
252 mutex_lock(&dev_priv
->rps
.hw_lock
);
254 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DDR_SETUP2
);
256 val
&= ~FORCE_DDR_HIGH_FREQ
;
258 val
|= FORCE_DDR_HIGH_FREQ
;
259 val
&= ~FORCE_DDR_LOW_FREQ
;
260 val
|= FORCE_DDR_FREQ_REQ_ACK
;
261 vlv_punit_write(dev_priv
, PUNIT_REG_DDR_SETUP2
, val
);
263 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DDR_SETUP2
) &
264 FORCE_DDR_FREQ_REQ_ACK
) == 0, 3))
265 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
267 mutex_unlock(&dev_priv
->rps
.hw_lock
);
270 static void chv_set_memory_pm5(struct drm_i915_private
*dev_priv
, bool enable
)
274 mutex_lock(&dev_priv
->rps
.hw_lock
);
276 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
278 val
|= DSP_MAXFIFO_PM5_ENABLE
;
280 val
&= ~DSP_MAXFIFO_PM5_ENABLE
;
281 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
283 mutex_unlock(&dev_priv
->rps
.hw_lock
);
286 #define FW_WM(value, plane) \
287 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
289 void intel_set_memory_cxsr(struct drm_i915_private
*dev_priv
, bool enable
)
291 struct drm_device
*dev
= dev_priv
->dev
;
294 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
295 I915_WRITE(FW_BLC_SELF_VLV
, enable
? FW_CSPWRDWNEN
: 0);
296 POSTING_READ(FW_BLC_SELF_VLV
);
297 dev_priv
->wm
.vlv
.cxsr
= enable
;
298 } else if (IS_G4X(dev
) || IS_CRESTLINE(dev
)) {
299 I915_WRITE(FW_BLC_SELF
, enable
? FW_BLC_SELF_EN
: 0);
300 POSTING_READ(FW_BLC_SELF
);
301 } else if (IS_PINEVIEW(dev
)) {
302 val
= I915_READ(DSPFW3
) & ~PINEVIEW_SELF_REFRESH_EN
;
303 val
|= enable
? PINEVIEW_SELF_REFRESH_EN
: 0;
304 I915_WRITE(DSPFW3
, val
);
305 POSTING_READ(DSPFW3
);
306 } else if (IS_I945G(dev
) || IS_I945GM(dev
)) {
307 val
= enable
? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN
) :
308 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN
);
309 I915_WRITE(FW_BLC_SELF
, val
);
310 POSTING_READ(FW_BLC_SELF
);
311 } else if (IS_I915GM(dev
)) {
312 val
= enable
? _MASKED_BIT_ENABLE(INSTPM_SELF_EN
) :
313 _MASKED_BIT_DISABLE(INSTPM_SELF_EN
);
314 I915_WRITE(INSTPM
, val
);
315 POSTING_READ(INSTPM
);
320 DRM_DEBUG_KMS("memory self-refresh is %s\n",
321 enable
? "enabled" : "disabled");
326 * Latency for FIFO fetches is dependent on several factors:
327 * - memory configuration (speed, channels)
329 * - current MCH state
330 * It can be fairly high in some situations, so here we assume a fairly
331 * pessimal value. It's a tradeoff between extra memory fetches (if we
332 * set this value too high, the FIFO will fetch frequently to stay full)
333 * and power consumption (set it too low to save power and we might see
334 * FIFO underruns and display "flicker").
336 * A value of 5us seems to be a good balance; safe for very low end
337 * platforms but not overly aggressive on lower latency configs.
339 static const int pessimal_latency_ns
= 5000;
341 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
342 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
344 static int vlv_get_fifo_size(struct drm_device
*dev
,
345 enum pipe pipe
, int plane
)
347 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
348 int sprite0_start
, sprite1_start
, size
;
351 uint32_t dsparb
, dsparb2
, dsparb3
;
353 dsparb
= I915_READ(DSPARB
);
354 dsparb2
= I915_READ(DSPARB2
);
355 sprite0_start
= VLV_FIFO_START(dsparb
, dsparb2
, 0, 0);
356 sprite1_start
= VLV_FIFO_START(dsparb
, dsparb2
, 8, 4);
359 dsparb
= I915_READ(DSPARB
);
360 dsparb2
= I915_READ(DSPARB2
);
361 sprite0_start
= VLV_FIFO_START(dsparb
, dsparb2
, 16, 8);
362 sprite1_start
= VLV_FIFO_START(dsparb
, dsparb2
, 24, 12);
365 dsparb2
= I915_READ(DSPARB2
);
366 dsparb3
= I915_READ(DSPARB3
);
367 sprite0_start
= VLV_FIFO_START(dsparb3
, dsparb2
, 0, 16);
368 sprite1_start
= VLV_FIFO_START(dsparb3
, dsparb2
, 8, 20);
376 size
= sprite0_start
;
379 size
= sprite1_start
- sprite0_start
;
382 size
= 512 - 1 - sprite1_start
;
388 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
389 pipe_name(pipe
), plane
== 0 ? "primary" : "sprite",
390 plane
== 0 ? plane_name(pipe
) : sprite_name(pipe
, plane
- 1),
396 static int i9xx_get_fifo_size(struct drm_device
*dev
, int plane
)
398 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
399 uint32_t dsparb
= I915_READ(DSPARB
);
402 size
= dsparb
& 0x7f;
404 size
= ((dsparb
>> DSPARB_CSTART_SHIFT
) & 0x7f) - size
;
406 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
407 plane
? "B" : "A", size
);
412 static int i830_get_fifo_size(struct drm_device
*dev
, int plane
)
414 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
415 uint32_t dsparb
= I915_READ(DSPARB
);
418 size
= dsparb
& 0x1ff;
420 size
= ((dsparb
>> DSPARB_BEND_SHIFT
) & 0x1ff) - size
;
421 size
>>= 1; /* Convert to cachelines */
423 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
424 plane
? "B" : "A", size
);
429 static int i845_get_fifo_size(struct drm_device
*dev
, int plane
)
431 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
432 uint32_t dsparb
= I915_READ(DSPARB
);
435 size
= dsparb
& 0x7f;
436 size
>>= 2; /* Convert to cachelines */
438 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
445 /* Pineview has different values for various configs */
446 static const struct intel_watermark_params pineview_display_wm
= {
447 .fifo_size
= PINEVIEW_DISPLAY_FIFO
,
448 .max_wm
= PINEVIEW_MAX_WM
,
449 .default_wm
= PINEVIEW_DFT_WM
,
450 .guard_size
= PINEVIEW_GUARD_WM
,
451 .cacheline_size
= PINEVIEW_FIFO_LINE_SIZE
,
453 static const struct intel_watermark_params pineview_display_hplloff_wm
= {
454 .fifo_size
= PINEVIEW_DISPLAY_FIFO
,
455 .max_wm
= PINEVIEW_MAX_WM
,
456 .default_wm
= PINEVIEW_DFT_HPLLOFF_WM
,
457 .guard_size
= PINEVIEW_GUARD_WM
,
458 .cacheline_size
= PINEVIEW_FIFO_LINE_SIZE
,
460 static const struct intel_watermark_params pineview_cursor_wm
= {
461 .fifo_size
= PINEVIEW_CURSOR_FIFO
,
462 .max_wm
= PINEVIEW_CURSOR_MAX_WM
,
463 .default_wm
= PINEVIEW_CURSOR_DFT_WM
,
464 .guard_size
= PINEVIEW_CURSOR_GUARD_WM
,
465 .cacheline_size
= PINEVIEW_FIFO_LINE_SIZE
,
467 static const struct intel_watermark_params pineview_cursor_hplloff_wm
= {
468 .fifo_size
= PINEVIEW_CURSOR_FIFO
,
469 .max_wm
= PINEVIEW_CURSOR_MAX_WM
,
470 .default_wm
= PINEVIEW_CURSOR_DFT_WM
,
471 .guard_size
= PINEVIEW_CURSOR_GUARD_WM
,
472 .cacheline_size
= PINEVIEW_FIFO_LINE_SIZE
,
474 static const struct intel_watermark_params g4x_wm_info
= {
475 .fifo_size
= G4X_FIFO_SIZE
,
476 .max_wm
= G4X_MAX_WM
,
477 .default_wm
= G4X_MAX_WM
,
479 .cacheline_size
= G4X_FIFO_LINE_SIZE
,
481 static const struct intel_watermark_params g4x_cursor_wm_info
= {
482 .fifo_size
= I965_CURSOR_FIFO
,
483 .max_wm
= I965_CURSOR_MAX_WM
,
484 .default_wm
= I965_CURSOR_DFT_WM
,
486 .cacheline_size
= G4X_FIFO_LINE_SIZE
,
488 static const struct intel_watermark_params valleyview_wm_info
= {
489 .fifo_size
= VALLEYVIEW_FIFO_SIZE
,
490 .max_wm
= VALLEYVIEW_MAX_WM
,
491 .default_wm
= VALLEYVIEW_MAX_WM
,
493 .cacheline_size
= G4X_FIFO_LINE_SIZE
,
495 static const struct intel_watermark_params valleyview_cursor_wm_info
= {
496 .fifo_size
= I965_CURSOR_FIFO
,
497 .max_wm
= VALLEYVIEW_CURSOR_MAX_WM
,
498 .default_wm
= I965_CURSOR_DFT_WM
,
500 .cacheline_size
= G4X_FIFO_LINE_SIZE
,
502 static const struct intel_watermark_params i965_cursor_wm_info
= {
503 .fifo_size
= I965_CURSOR_FIFO
,
504 .max_wm
= I965_CURSOR_MAX_WM
,
505 .default_wm
= I965_CURSOR_DFT_WM
,
507 .cacheline_size
= I915_FIFO_LINE_SIZE
,
509 static const struct intel_watermark_params i945_wm_info
= {
510 .fifo_size
= I945_FIFO_SIZE
,
511 .max_wm
= I915_MAX_WM
,
514 .cacheline_size
= I915_FIFO_LINE_SIZE
,
516 static const struct intel_watermark_params i915_wm_info
= {
517 .fifo_size
= I915_FIFO_SIZE
,
518 .max_wm
= I915_MAX_WM
,
521 .cacheline_size
= I915_FIFO_LINE_SIZE
,
523 static const struct intel_watermark_params i830_a_wm_info
= {
524 .fifo_size
= I855GM_FIFO_SIZE
,
525 .max_wm
= I915_MAX_WM
,
528 .cacheline_size
= I830_FIFO_LINE_SIZE
,
530 static const struct intel_watermark_params i830_bc_wm_info
= {
531 .fifo_size
= I855GM_FIFO_SIZE
,
532 .max_wm
= I915_MAX_WM
/2,
535 .cacheline_size
= I830_FIFO_LINE_SIZE
,
537 static const struct intel_watermark_params i845_wm_info
= {
538 .fifo_size
= I830_FIFO_SIZE
,
539 .max_wm
= I915_MAX_WM
,
542 .cacheline_size
= I830_FIFO_LINE_SIZE
,
546 * intel_calculate_wm - calculate watermark level
547 * @clock_in_khz: pixel clock
548 * @wm: chip FIFO params
549 * @pixel_size: display pixel size
550 * @latency_ns: memory latency for the platform
552 * Calculate the watermark level (the level at which the display plane will
553 * start fetching from memory again). Each chip has a different display
554 * FIFO size and allocation, so the caller needs to figure that out and pass
555 * in the correct intel_watermark_params structure.
557 * As the pixel clock runs, the FIFO will be drained at a rate that depends
558 * on the pixel size. When it reaches the watermark level, it'll start
559 * fetching FIFO line sized based chunks from memory until the FIFO fills
560 * past the watermark point. If the FIFO drains completely, a FIFO underrun
561 * will occur, and a display engine hang could result.
563 static unsigned long intel_calculate_wm(unsigned long clock_in_khz
,
564 const struct intel_watermark_params
*wm
,
567 unsigned long latency_ns
)
569 long entries_required
, wm_size
;
572 * Note: we need to make sure we don't overflow for various clock &
574 * clocks go from a few thousand to several hundred thousand.
575 * latency is usually a few thousand
577 entries_required
= ((clock_in_khz
/ 1000) * pixel_size
* latency_ns
) /
579 entries_required
= DIV_ROUND_UP(entries_required
, wm
->cacheline_size
);
581 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required
);
583 wm_size
= fifo_size
- (entries_required
+ wm
->guard_size
);
585 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size
);
587 /* Don't promote wm_size to unsigned... */
588 if (wm_size
> (long)wm
->max_wm
)
589 wm_size
= wm
->max_wm
;
591 wm_size
= wm
->default_wm
;
594 * Bspec seems to indicate that the value shouldn't be lower than
595 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
596 * Lets go for 8 which is the burst size since certain platforms
597 * already use a hardcoded 8 (which is what the spec says should be
606 static struct drm_crtc
*single_enabled_crtc(struct drm_device
*dev
)
608 struct drm_crtc
*crtc
, *enabled
= NULL
;
610 for_each_crtc(dev
, crtc
) {
611 if (intel_crtc_active(crtc
)) {
621 static void pineview_update_wm(struct drm_crtc
*unused_crtc
)
623 struct drm_device
*dev
= unused_crtc
->dev
;
624 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
625 struct drm_crtc
*crtc
;
626 const struct cxsr_latency
*latency
;
630 latency
= intel_get_cxsr_latency(IS_PINEVIEW_G(dev
), dev_priv
->is_ddr3
,
631 dev_priv
->fsb_freq
, dev_priv
->mem_freq
);
633 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
634 intel_set_memory_cxsr(dev_priv
, false);
638 crtc
= single_enabled_crtc(dev
);
640 const struct drm_display_mode
*adjusted_mode
= &to_intel_crtc(crtc
)->config
->base
.adjusted_mode
;
641 int pixel_size
= crtc
->primary
->state
->fb
->bits_per_pixel
/ 8;
642 int clock
= adjusted_mode
->crtc_clock
;
645 wm
= intel_calculate_wm(clock
, &pineview_display_wm
,
646 pineview_display_wm
.fifo_size
,
647 pixel_size
, latency
->display_sr
);
648 reg
= I915_READ(DSPFW1
);
649 reg
&= ~DSPFW_SR_MASK
;
650 reg
|= FW_WM(wm
, SR
);
651 I915_WRITE(DSPFW1
, reg
);
652 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg
);
655 wm
= intel_calculate_wm(clock
, &pineview_cursor_wm
,
656 pineview_display_wm
.fifo_size
,
657 pixel_size
, latency
->cursor_sr
);
658 reg
= I915_READ(DSPFW3
);
659 reg
&= ~DSPFW_CURSOR_SR_MASK
;
660 reg
|= FW_WM(wm
, CURSOR_SR
);
661 I915_WRITE(DSPFW3
, reg
);
663 /* Display HPLL off SR */
664 wm
= intel_calculate_wm(clock
, &pineview_display_hplloff_wm
,
665 pineview_display_hplloff_wm
.fifo_size
,
666 pixel_size
, latency
->display_hpll_disable
);
667 reg
= I915_READ(DSPFW3
);
668 reg
&= ~DSPFW_HPLL_SR_MASK
;
669 reg
|= FW_WM(wm
, HPLL_SR
);
670 I915_WRITE(DSPFW3
, reg
);
672 /* cursor HPLL off SR */
673 wm
= intel_calculate_wm(clock
, &pineview_cursor_hplloff_wm
,
674 pineview_display_hplloff_wm
.fifo_size
,
675 pixel_size
, latency
->cursor_hpll_disable
);
676 reg
= I915_READ(DSPFW3
);
677 reg
&= ~DSPFW_HPLL_CURSOR_MASK
;
678 reg
|= FW_WM(wm
, HPLL_CURSOR
);
679 I915_WRITE(DSPFW3
, reg
);
680 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg
);
682 intel_set_memory_cxsr(dev_priv
, true);
684 intel_set_memory_cxsr(dev_priv
, false);
688 static bool g4x_compute_wm0(struct drm_device
*dev
,
690 const struct intel_watermark_params
*display
,
691 int display_latency_ns
,
692 const struct intel_watermark_params
*cursor
,
693 int cursor_latency_ns
,
697 struct drm_crtc
*crtc
;
698 const struct drm_display_mode
*adjusted_mode
;
699 int htotal
, hdisplay
, clock
, pixel_size
;
700 int line_time_us
, line_count
;
701 int entries
, tlb_miss
;
703 crtc
= intel_get_crtc_for_plane(dev
, plane
);
704 if (!intel_crtc_active(crtc
)) {
705 *cursor_wm
= cursor
->guard_size
;
706 *plane_wm
= display
->guard_size
;
710 adjusted_mode
= &to_intel_crtc(crtc
)->config
->base
.adjusted_mode
;
711 clock
= adjusted_mode
->crtc_clock
;
712 htotal
= adjusted_mode
->crtc_htotal
;
713 hdisplay
= to_intel_crtc(crtc
)->config
->pipe_src_w
;
714 pixel_size
= crtc
->primary
->state
->fb
->bits_per_pixel
/ 8;
716 /* Use the small buffer method to calculate plane watermark */
717 entries
= ((clock
* pixel_size
/ 1000) * display_latency_ns
) / 1000;
718 tlb_miss
= display
->fifo_size
*display
->cacheline_size
- hdisplay
* 8;
721 entries
= DIV_ROUND_UP(entries
, display
->cacheline_size
);
722 *plane_wm
= entries
+ display
->guard_size
;
723 if (*plane_wm
> (int)display
->max_wm
)
724 *plane_wm
= display
->max_wm
;
726 /* Use the large buffer method to calculate cursor watermark */
727 line_time_us
= max(htotal
* 1000 / clock
, 1);
728 line_count
= (cursor_latency_ns
/ line_time_us
+ 1000) / 1000;
729 entries
= line_count
* crtc
->cursor
->state
->crtc_w
* pixel_size
;
730 tlb_miss
= cursor
->fifo_size
*cursor
->cacheline_size
- hdisplay
* 8;
733 entries
= DIV_ROUND_UP(entries
, cursor
->cacheline_size
);
734 *cursor_wm
= entries
+ cursor
->guard_size
;
735 if (*cursor_wm
> (int)cursor
->max_wm
)
736 *cursor_wm
= (int)cursor
->max_wm
;
742 * Check the wm result.
744 * If any calculated watermark values is larger than the maximum value that
745 * can be programmed into the associated watermark register, that watermark
748 static bool g4x_check_srwm(struct drm_device
*dev
,
749 int display_wm
, int cursor_wm
,
750 const struct intel_watermark_params
*display
,
751 const struct intel_watermark_params
*cursor
)
753 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
754 display_wm
, cursor_wm
);
756 if (display_wm
> display
->max_wm
) {
757 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
758 display_wm
, display
->max_wm
);
762 if (cursor_wm
> cursor
->max_wm
) {
763 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
764 cursor_wm
, cursor
->max_wm
);
768 if (!(display_wm
|| cursor_wm
)) {
769 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
776 static bool g4x_compute_srwm(struct drm_device
*dev
,
779 const struct intel_watermark_params
*display
,
780 const struct intel_watermark_params
*cursor
,
781 int *display_wm
, int *cursor_wm
)
783 struct drm_crtc
*crtc
;
784 const struct drm_display_mode
*adjusted_mode
;
785 int hdisplay
, htotal
, pixel_size
, clock
;
786 unsigned long line_time_us
;
787 int line_count
, line_size
;
792 *display_wm
= *cursor_wm
= 0;
796 crtc
= intel_get_crtc_for_plane(dev
, plane
);
797 adjusted_mode
= &to_intel_crtc(crtc
)->config
->base
.adjusted_mode
;
798 clock
= adjusted_mode
->crtc_clock
;
799 htotal
= adjusted_mode
->crtc_htotal
;
800 hdisplay
= to_intel_crtc(crtc
)->config
->pipe_src_w
;
801 pixel_size
= crtc
->primary
->state
->fb
->bits_per_pixel
/ 8;
803 line_time_us
= max(htotal
* 1000 / clock
, 1);
804 line_count
= (latency_ns
/ line_time_us
+ 1000) / 1000;
805 line_size
= hdisplay
* pixel_size
;
807 /* Use the minimum of the small and large buffer method for primary */
808 small
= ((clock
* pixel_size
/ 1000) * latency_ns
) / 1000;
809 large
= line_count
* line_size
;
811 entries
= DIV_ROUND_UP(min(small
, large
), display
->cacheline_size
);
812 *display_wm
= entries
+ display
->guard_size
;
814 /* calculate the self-refresh watermark for display cursor */
815 entries
= line_count
* pixel_size
* crtc
->cursor
->state
->crtc_w
;
816 entries
= DIV_ROUND_UP(entries
, cursor
->cacheline_size
);
817 *cursor_wm
= entries
+ cursor
->guard_size
;
819 return g4x_check_srwm(dev
,
820 *display_wm
, *cursor_wm
,
824 #define FW_WM_VLV(value, plane) \
825 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
827 static void vlv_write_wm_values(struct intel_crtc
*crtc
,
828 const struct vlv_wm_values
*wm
)
830 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
831 enum pipe pipe
= crtc
->pipe
;
833 I915_WRITE(VLV_DDL(pipe
),
834 (wm
->ddl
[pipe
].cursor
<< DDL_CURSOR_SHIFT
) |
835 (wm
->ddl
[pipe
].sprite
[1] << DDL_SPRITE_SHIFT(1)) |
836 (wm
->ddl
[pipe
].sprite
[0] << DDL_SPRITE_SHIFT(0)) |
837 (wm
->ddl
[pipe
].primary
<< DDL_PLANE_SHIFT
));
840 FW_WM(wm
->sr
.plane
, SR
) |
841 FW_WM(wm
->pipe
[PIPE_B
].cursor
, CURSORB
) |
842 FW_WM_VLV(wm
->pipe
[PIPE_B
].primary
, PLANEB
) |
843 FW_WM_VLV(wm
->pipe
[PIPE_A
].primary
, PLANEA
));
845 FW_WM_VLV(wm
->pipe
[PIPE_A
].sprite
[1], SPRITEB
) |
846 FW_WM(wm
->pipe
[PIPE_A
].cursor
, CURSORA
) |
847 FW_WM_VLV(wm
->pipe
[PIPE_A
].sprite
[0], SPRITEA
));
849 FW_WM(wm
->sr
.cursor
, CURSOR_SR
));
851 if (IS_CHERRYVIEW(dev_priv
)) {
852 I915_WRITE(DSPFW7_CHV
,
853 FW_WM_VLV(wm
->pipe
[PIPE_B
].sprite
[1], SPRITED
) |
854 FW_WM_VLV(wm
->pipe
[PIPE_B
].sprite
[0], SPRITEC
));
855 I915_WRITE(DSPFW8_CHV
,
856 FW_WM_VLV(wm
->pipe
[PIPE_C
].sprite
[1], SPRITEF
) |
857 FW_WM_VLV(wm
->pipe
[PIPE_C
].sprite
[0], SPRITEE
));
858 I915_WRITE(DSPFW9_CHV
,
859 FW_WM_VLV(wm
->pipe
[PIPE_C
].primary
, PLANEC
) |
860 FW_WM(wm
->pipe
[PIPE_C
].cursor
, CURSORC
));
862 FW_WM(wm
->sr
.plane
>> 9, SR_HI
) |
863 FW_WM(wm
->pipe
[PIPE_C
].sprite
[1] >> 8, SPRITEF_HI
) |
864 FW_WM(wm
->pipe
[PIPE_C
].sprite
[0] >> 8, SPRITEE_HI
) |
865 FW_WM(wm
->pipe
[PIPE_C
].primary
>> 8, PLANEC_HI
) |
866 FW_WM(wm
->pipe
[PIPE_B
].sprite
[1] >> 8, SPRITED_HI
) |
867 FW_WM(wm
->pipe
[PIPE_B
].sprite
[0] >> 8, SPRITEC_HI
) |
868 FW_WM(wm
->pipe
[PIPE_B
].primary
>> 8, PLANEB_HI
) |
869 FW_WM(wm
->pipe
[PIPE_A
].sprite
[1] >> 8, SPRITEB_HI
) |
870 FW_WM(wm
->pipe
[PIPE_A
].sprite
[0] >> 8, SPRITEA_HI
) |
871 FW_WM(wm
->pipe
[PIPE_A
].primary
>> 8, PLANEA_HI
));
874 FW_WM_VLV(wm
->pipe
[PIPE_B
].sprite
[1], SPRITED
) |
875 FW_WM_VLV(wm
->pipe
[PIPE_B
].sprite
[0], SPRITEC
));
877 FW_WM(wm
->sr
.plane
>> 9, SR_HI
) |
878 FW_WM(wm
->pipe
[PIPE_B
].sprite
[1] >> 8, SPRITED_HI
) |
879 FW_WM(wm
->pipe
[PIPE_B
].sprite
[0] >> 8, SPRITEC_HI
) |
880 FW_WM(wm
->pipe
[PIPE_B
].primary
>> 8, PLANEB_HI
) |
881 FW_WM(wm
->pipe
[PIPE_A
].sprite
[1] >> 8, SPRITEB_HI
) |
882 FW_WM(wm
->pipe
[PIPE_A
].sprite
[0] >> 8, SPRITEA_HI
) |
883 FW_WM(wm
->pipe
[PIPE_A
].primary
>> 8, PLANEA_HI
));
886 /* zero (unused) WM1 watermarks */
887 I915_WRITE(DSPFW4
, 0);
888 I915_WRITE(DSPFW5
, 0);
889 I915_WRITE(DSPFW6
, 0);
890 I915_WRITE(DSPHOWM1
, 0);
892 POSTING_READ(DSPFW1
);
900 VLV_WM_LEVEL_DDR_DVFS
,
903 /* latency must be in 0.1us units. */
904 static unsigned int vlv_wm_method2(unsigned int pixel_rate
,
905 unsigned int pipe_htotal
,
906 unsigned int horiz_pixels
,
907 unsigned int bytes_per_pixel
,
908 unsigned int latency
)
912 ret
= (latency
* pixel_rate
) / (pipe_htotal
* 10000);
913 ret
= (ret
+ 1) * horiz_pixels
* bytes_per_pixel
;
914 ret
= DIV_ROUND_UP(ret
, 64);
919 static void vlv_setup_wm_latency(struct drm_device
*dev
)
921 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
923 /* all latencies in usec */
924 dev_priv
->wm
.pri_latency
[VLV_WM_LEVEL_PM2
] = 3;
926 dev_priv
->wm
.max_level
= VLV_WM_LEVEL_PM2
;
928 if (IS_CHERRYVIEW(dev_priv
)) {
929 dev_priv
->wm
.pri_latency
[VLV_WM_LEVEL_PM5
] = 12;
930 dev_priv
->wm
.pri_latency
[VLV_WM_LEVEL_DDR_DVFS
] = 33;
932 dev_priv
->wm
.max_level
= VLV_WM_LEVEL_DDR_DVFS
;
936 static uint16_t vlv_compute_wm_level(struct intel_plane
*plane
,
937 struct intel_crtc
*crtc
,
938 const struct intel_plane_state
*state
,
941 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
942 int clock
, htotal
, pixel_size
, width
, wm
;
944 if (dev_priv
->wm
.pri_latency
[level
] == 0)
950 pixel_size
= drm_format_plane_cpp(state
->base
.fb
->pixel_format
, 0);
951 clock
= crtc
->config
->base
.adjusted_mode
.crtc_clock
;
952 htotal
= crtc
->config
->base
.adjusted_mode
.crtc_htotal
;
953 width
= crtc
->config
->pipe_src_w
;
954 if (WARN_ON(htotal
== 0))
957 if (plane
->base
.type
== DRM_PLANE_TYPE_CURSOR
) {
959 * FIXME the formula gives values that are
960 * too big for the cursor FIFO, and hence we
961 * would never be able to use cursors. For
962 * now just hardcode the watermark.
966 wm
= vlv_wm_method2(clock
, htotal
, width
, pixel_size
,
967 dev_priv
->wm
.pri_latency
[level
] * 10);
970 return min_t(int, wm
, USHRT_MAX
);
973 static void vlv_compute_fifo(struct intel_crtc
*crtc
)
975 struct drm_device
*dev
= crtc
->base
.dev
;
976 struct vlv_wm_state
*wm_state
= &crtc
->wm_state
;
977 struct intel_plane
*plane
;
978 unsigned int total_rate
= 0;
979 const int fifo_size
= 512 - 1;
980 int fifo_extra
, fifo_left
= fifo_size
;
982 for_each_intel_plane_on_crtc(dev
, crtc
, plane
) {
983 struct intel_plane_state
*state
=
984 to_intel_plane_state(plane
->base
.state
);
986 if (plane
->base
.type
== DRM_PLANE_TYPE_CURSOR
)
989 if (state
->visible
) {
990 wm_state
->num_active_planes
++;
991 total_rate
+= drm_format_plane_cpp(state
->base
.fb
->pixel_format
, 0);
995 for_each_intel_plane_on_crtc(dev
, crtc
, plane
) {
996 struct intel_plane_state
*state
=
997 to_intel_plane_state(plane
->base
.state
);
1000 if (plane
->base
.type
== DRM_PLANE_TYPE_CURSOR
) {
1001 plane
->wm
.fifo_size
= 63;
1005 if (!state
->visible
) {
1006 plane
->wm
.fifo_size
= 0;
1010 rate
= drm_format_plane_cpp(state
->base
.fb
->pixel_format
, 0);
1011 plane
->wm
.fifo_size
= fifo_size
* rate
/ total_rate
;
1012 fifo_left
-= plane
->wm
.fifo_size
;
1015 fifo_extra
= DIV_ROUND_UP(fifo_left
, wm_state
->num_active_planes
?: 1);
1017 /* spread the remainder evenly */
1018 for_each_intel_plane_on_crtc(dev
, crtc
, plane
) {
1024 if (plane
->base
.type
== DRM_PLANE_TYPE_CURSOR
)
1027 /* give it all to the first plane if none are active */
1028 if (plane
->wm
.fifo_size
== 0 &&
1029 wm_state
->num_active_planes
)
1032 plane_extra
= min(fifo_extra
, fifo_left
);
1033 plane
->wm
.fifo_size
+= plane_extra
;
1034 fifo_left
-= plane_extra
;
1037 WARN_ON(fifo_left
!= 0);
1040 static void vlv_invert_wms(struct intel_crtc
*crtc
)
1042 struct vlv_wm_state
*wm_state
= &crtc
->wm_state
;
1045 for (level
= 0; level
< wm_state
->num_levels
; level
++) {
1046 struct drm_device
*dev
= crtc
->base
.dev
;
1047 const int sr_fifo_size
= INTEL_INFO(dev
)->num_pipes
* 512 - 1;
1048 struct intel_plane
*plane
;
1050 wm_state
->sr
[level
].plane
= sr_fifo_size
- wm_state
->sr
[level
].plane
;
1051 wm_state
->sr
[level
].cursor
= 63 - wm_state
->sr
[level
].cursor
;
1053 for_each_intel_plane_on_crtc(dev
, crtc
, plane
) {
1054 switch (plane
->base
.type
) {
1056 case DRM_PLANE_TYPE_CURSOR
:
1057 wm_state
->wm
[level
].cursor
= plane
->wm
.fifo_size
-
1058 wm_state
->wm
[level
].cursor
;
1060 case DRM_PLANE_TYPE_PRIMARY
:
1061 wm_state
->wm
[level
].primary
= plane
->wm
.fifo_size
-
1062 wm_state
->wm
[level
].primary
;
1064 case DRM_PLANE_TYPE_OVERLAY
:
1065 sprite
= plane
->plane
;
1066 wm_state
->wm
[level
].sprite
[sprite
] = plane
->wm
.fifo_size
-
1067 wm_state
->wm
[level
].sprite
[sprite
];
1074 static void vlv_compute_wm(struct intel_crtc
*crtc
)
1076 struct drm_device
*dev
= crtc
->base
.dev
;
1077 struct vlv_wm_state
*wm_state
= &crtc
->wm_state
;
1078 struct intel_plane
*plane
;
1079 int sr_fifo_size
= INTEL_INFO(dev
)->num_pipes
* 512 - 1;
1082 memset(wm_state
, 0, sizeof(*wm_state
));
1084 wm_state
->cxsr
= crtc
->pipe
!= PIPE_C
&& crtc
->wm
.cxsr_allowed
;
1085 wm_state
->num_levels
= to_i915(dev
)->wm
.max_level
+ 1;
1087 wm_state
->num_active_planes
= 0;
1089 vlv_compute_fifo(crtc
);
1091 if (wm_state
->num_active_planes
!= 1)
1092 wm_state
->cxsr
= false;
1094 if (wm_state
->cxsr
) {
1095 for (level
= 0; level
< wm_state
->num_levels
; level
++) {
1096 wm_state
->sr
[level
].plane
= sr_fifo_size
;
1097 wm_state
->sr
[level
].cursor
= 63;
1101 for_each_intel_plane_on_crtc(dev
, crtc
, plane
) {
1102 struct intel_plane_state
*state
=
1103 to_intel_plane_state(plane
->base
.state
);
1105 if (!state
->visible
)
1108 /* normal watermarks */
1109 for (level
= 0; level
< wm_state
->num_levels
; level
++) {
1110 int wm
= vlv_compute_wm_level(plane
, crtc
, state
, level
);
1111 int max_wm
= plane
->base
.type
== DRM_PLANE_TYPE_CURSOR
? 63 : 511;
1114 if (WARN_ON(level
== 0 && wm
> max_wm
))
1117 if (wm
> plane
->wm
.fifo_size
)
1120 switch (plane
->base
.type
) {
1122 case DRM_PLANE_TYPE_CURSOR
:
1123 wm_state
->wm
[level
].cursor
= wm
;
1125 case DRM_PLANE_TYPE_PRIMARY
:
1126 wm_state
->wm
[level
].primary
= wm
;
1128 case DRM_PLANE_TYPE_OVERLAY
:
1129 sprite
= plane
->plane
;
1130 wm_state
->wm
[level
].sprite
[sprite
] = wm
;
1135 wm_state
->num_levels
= level
;
1137 if (!wm_state
->cxsr
)
1140 /* maxfifo watermarks */
1141 switch (plane
->base
.type
) {
1143 case DRM_PLANE_TYPE_CURSOR
:
1144 for (level
= 0; level
< wm_state
->num_levels
; level
++)
1145 wm_state
->sr
[level
].cursor
=
1146 wm_state
->wm
[level
].cursor
;
1148 case DRM_PLANE_TYPE_PRIMARY
:
1149 for (level
= 0; level
< wm_state
->num_levels
; level
++)
1150 wm_state
->sr
[level
].plane
=
1151 min(wm_state
->sr
[level
].plane
,
1152 wm_state
->wm
[level
].primary
);
1154 case DRM_PLANE_TYPE_OVERLAY
:
1155 sprite
= plane
->plane
;
1156 for (level
= 0; level
< wm_state
->num_levels
; level
++)
1157 wm_state
->sr
[level
].plane
=
1158 min(wm_state
->sr
[level
].plane
,
1159 wm_state
->wm
[level
].sprite
[sprite
]);
1164 /* clear any (partially) filled invalid levels */
1165 for (level
= wm_state
->num_levels
; level
< to_i915(dev
)->wm
.max_level
+ 1; level
++) {
1166 memset(&wm_state
->wm
[level
], 0, sizeof(wm_state
->wm
[level
]));
1167 memset(&wm_state
->sr
[level
], 0, sizeof(wm_state
->sr
[level
]));
1170 vlv_invert_wms(crtc
);
1173 #define VLV_FIFO(plane, value) \
1174 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1176 static void vlv_pipe_set_fifo_size(struct intel_crtc
*crtc
)
1178 struct drm_device
*dev
= crtc
->base
.dev
;
1179 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1180 struct intel_plane
*plane
;
1181 int sprite0_start
= 0, sprite1_start
= 0, fifo_size
= 0;
1183 for_each_intel_plane_on_crtc(dev
, crtc
, plane
) {
1184 if (plane
->base
.type
== DRM_PLANE_TYPE_CURSOR
) {
1185 WARN_ON(plane
->wm
.fifo_size
!= 63);
1189 if (plane
->base
.type
== DRM_PLANE_TYPE_PRIMARY
)
1190 sprite0_start
= plane
->wm
.fifo_size
;
1191 else if (plane
->plane
== 0)
1192 sprite1_start
= sprite0_start
+ plane
->wm
.fifo_size
;
1194 fifo_size
= sprite1_start
+ plane
->wm
.fifo_size
;
1197 WARN_ON(fifo_size
!= 512 - 1);
1199 DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1200 pipe_name(crtc
->pipe
), sprite0_start
,
1201 sprite1_start
, fifo_size
);
1203 switch (crtc
->pipe
) {
1204 uint32_t dsparb
, dsparb2
, dsparb3
;
1206 dsparb
= I915_READ(DSPARB
);
1207 dsparb2
= I915_READ(DSPARB2
);
1209 dsparb
&= ~(VLV_FIFO(SPRITEA
, 0xff) |
1210 VLV_FIFO(SPRITEB
, 0xff));
1211 dsparb
|= (VLV_FIFO(SPRITEA
, sprite0_start
) |
1212 VLV_FIFO(SPRITEB
, sprite1_start
));
1214 dsparb2
&= ~(VLV_FIFO(SPRITEA_HI
, 0x1) |
1215 VLV_FIFO(SPRITEB_HI
, 0x1));
1216 dsparb2
|= (VLV_FIFO(SPRITEA_HI
, sprite0_start
>> 8) |
1217 VLV_FIFO(SPRITEB_HI
, sprite1_start
>> 8));
1219 I915_WRITE(DSPARB
, dsparb
);
1220 I915_WRITE(DSPARB2
, dsparb2
);
1223 dsparb
= I915_READ(DSPARB
);
1224 dsparb2
= I915_READ(DSPARB2
);
1226 dsparb
&= ~(VLV_FIFO(SPRITEC
, 0xff) |
1227 VLV_FIFO(SPRITED
, 0xff));
1228 dsparb
|= (VLV_FIFO(SPRITEC
, sprite0_start
) |
1229 VLV_FIFO(SPRITED
, sprite1_start
));
1231 dsparb2
&= ~(VLV_FIFO(SPRITEC_HI
, 0xff) |
1232 VLV_FIFO(SPRITED_HI
, 0xff));
1233 dsparb2
|= (VLV_FIFO(SPRITEC_HI
, sprite0_start
>> 8) |
1234 VLV_FIFO(SPRITED_HI
, sprite1_start
>> 8));
1236 I915_WRITE(DSPARB
, dsparb
);
1237 I915_WRITE(DSPARB2
, dsparb2
);
1240 dsparb3
= I915_READ(DSPARB3
);
1241 dsparb2
= I915_READ(DSPARB2
);
1243 dsparb3
&= ~(VLV_FIFO(SPRITEE
, 0xff) |
1244 VLV_FIFO(SPRITEF
, 0xff));
1245 dsparb3
|= (VLV_FIFO(SPRITEE
, sprite0_start
) |
1246 VLV_FIFO(SPRITEF
, sprite1_start
));
1248 dsparb2
&= ~(VLV_FIFO(SPRITEE_HI
, 0xff) |
1249 VLV_FIFO(SPRITEF_HI
, 0xff));
1250 dsparb2
|= (VLV_FIFO(SPRITEE_HI
, sprite0_start
>> 8) |
1251 VLV_FIFO(SPRITEF_HI
, sprite1_start
>> 8));
1253 I915_WRITE(DSPARB3
, dsparb3
);
1254 I915_WRITE(DSPARB2
, dsparb2
);
1263 static void vlv_merge_wm(struct drm_device
*dev
,
1264 struct vlv_wm_values
*wm
)
1266 struct intel_crtc
*crtc
;
1267 int num_active_crtcs
= 0;
1269 wm
->level
= to_i915(dev
)->wm
.max_level
;
1272 for_each_intel_crtc(dev
, crtc
) {
1273 const struct vlv_wm_state
*wm_state
= &crtc
->wm_state
;
1278 if (!wm_state
->cxsr
)
1282 wm
->level
= min_t(int, wm
->level
, wm_state
->num_levels
- 1);
1285 if (num_active_crtcs
!= 1)
1288 if (num_active_crtcs
> 1)
1289 wm
->level
= VLV_WM_LEVEL_PM2
;
1291 for_each_intel_crtc(dev
, crtc
) {
1292 struct vlv_wm_state
*wm_state
= &crtc
->wm_state
;
1293 enum pipe pipe
= crtc
->pipe
;
1298 wm
->pipe
[pipe
] = wm_state
->wm
[wm
->level
];
1300 wm
->sr
= wm_state
->sr
[wm
->level
];
1302 wm
->ddl
[pipe
].primary
= DDL_PRECISION_HIGH
| 2;
1303 wm
->ddl
[pipe
].sprite
[0] = DDL_PRECISION_HIGH
| 2;
1304 wm
->ddl
[pipe
].sprite
[1] = DDL_PRECISION_HIGH
| 2;
1305 wm
->ddl
[pipe
].cursor
= DDL_PRECISION_HIGH
| 2;
1309 static void vlv_update_wm(struct drm_crtc
*crtc
)
1311 struct drm_device
*dev
= crtc
->dev
;
1312 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1313 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1314 enum pipe pipe
= intel_crtc
->pipe
;
1315 struct vlv_wm_values wm
= {};
1317 vlv_compute_wm(intel_crtc
);
1318 vlv_merge_wm(dev
, &wm
);
1320 if (memcmp(&dev_priv
->wm
.vlv
, &wm
, sizeof(wm
)) == 0) {
1321 /* FIXME should be part of crtc atomic commit */
1322 vlv_pipe_set_fifo_size(intel_crtc
);
1326 if (wm
.level
< VLV_WM_LEVEL_DDR_DVFS
&&
1327 dev_priv
->wm
.vlv
.level
>= VLV_WM_LEVEL_DDR_DVFS
)
1328 chv_set_memory_dvfs(dev_priv
, false);
1330 if (wm
.level
< VLV_WM_LEVEL_PM5
&&
1331 dev_priv
->wm
.vlv
.level
>= VLV_WM_LEVEL_PM5
)
1332 chv_set_memory_pm5(dev_priv
, false);
1334 if (!wm
.cxsr
&& dev_priv
->wm
.vlv
.cxsr
)
1335 intel_set_memory_cxsr(dev_priv
, false);
1337 /* FIXME should be part of crtc atomic commit */
1338 vlv_pipe_set_fifo_size(intel_crtc
);
1340 vlv_write_wm_values(intel_crtc
, &wm
);
1342 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1343 "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1344 pipe_name(pipe
), wm
.pipe
[pipe
].primary
, wm
.pipe
[pipe
].cursor
,
1345 wm
.pipe
[pipe
].sprite
[0], wm
.pipe
[pipe
].sprite
[1],
1346 wm
.sr
.plane
, wm
.sr
.cursor
, wm
.level
, wm
.cxsr
);
1348 if (wm
.cxsr
&& !dev_priv
->wm
.vlv
.cxsr
)
1349 intel_set_memory_cxsr(dev_priv
, true);
1351 if (wm
.level
>= VLV_WM_LEVEL_PM5
&&
1352 dev_priv
->wm
.vlv
.level
< VLV_WM_LEVEL_PM5
)
1353 chv_set_memory_pm5(dev_priv
, true);
1355 if (wm
.level
>= VLV_WM_LEVEL_DDR_DVFS
&&
1356 dev_priv
->wm
.vlv
.level
< VLV_WM_LEVEL_DDR_DVFS
)
1357 chv_set_memory_dvfs(dev_priv
, true);
1359 dev_priv
->wm
.vlv
= wm
;
1362 #define single_plane_enabled(mask) is_power_of_2(mask)
1364 static void g4x_update_wm(struct drm_crtc
*crtc
)
1366 struct drm_device
*dev
= crtc
->dev
;
1367 static const int sr_latency_ns
= 12000;
1368 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1369 int planea_wm
, planeb_wm
, cursora_wm
, cursorb_wm
;
1370 int plane_sr
, cursor_sr
;
1371 unsigned int enabled
= 0;
1374 if (g4x_compute_wm0(dev
, PIPE_A
,
1375 &g4x_wm_info
, pessimal_latency_ns
,
1376 &g4x_cursor_wm_info
, pessimal_latency_ns
,
1377 &planea_wm
, &cursora_wm
))
1378 enabled
|= 1 << PIPE_A
;
1380 if (g4x_compute_wm0(dev
, PIPE_B
,
1381 &g4x_wm_info
, pessimal_latency_ns
,
1382 &g4x_cursor_wm_info
, pessimal_latency_ns
,
1383 &planeb_wm
, &cursorb_wm
))
1384 enabled
|= 1 << PIPE_B
;
1386 if (single_plane_enabled(enabled
) &&
1387 g4x_compute_srwm(dev
, ffs(enabled
) - 1,
1390 &g4x_cursor_wm_info
,
1391 &plane_sr
, &cursor_sr
)) {
1392 cxsr_enabled
= true;
1394 cxsr_enabled
= false;
1395 intel_set_memory_cxsr(dev_priv
, false);
1396 plane_sr
= cursor_sr
= 0;
1399 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1400 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1401 planea_wm
, cursora_wm
,
1402 planeb_wm
, cursorb_wm
,
1403 plane_sr
, cursor_sr
);
1406 FW_WM(plane_sr
, SR
) |
1407 FW_WM(cursorb_wm
, CURSORB
) |
1408 FW_WM(planeb_wm
, PLANEB
) |
1409 FW_WM(planea_wm
, PLANEA
));
1411 (I915_READ(DSPFW2
) & ~DSPFW_CURSORA_MASK
) |
1412 FW_WM(cursora_wm
, CURSORA
));
1413 /* HPLL off in SR has some issues on G4x... disable it */
1415 (I915_READ(DSPFW3
) & ~(DSPFW_HPLL_SR_EN
| DSPFW_CURSOR_SR_MASK
)) |
1416 FW_WM(cursor_sr
, CURSOR_SR
));
1419 intel_set_memory_cxsr(dev_priv
, true);
1422 static void i965_update_wm(struct drm_crtc
*unused_crtc
)
1424 struct drm_device
*dev
= unused_crtc
->dev
;
1425 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1426 struct drm_crtc
*crtc
;
1431 /* Calc sr entries for one plane configs */
1432 crtc
= single_enabled_crtc(dev
);
1434 /* self-refresh has much higher latency */
1435 static const int sr_latency_ns
= 12000;
1436 const struct drm_display_mode
*adjusted_mode
= &to_intel_crtc(crtc
)->config
->base
.adjusted_mode
;
1437 int clock
= adjusted_mode
->crtc_clock
;
1438 int htotal
= adjusted_mode
->crtc_htotal
;
1439 int hdisplay
= to_intel_crtc(crtc
)->config
->pipe_src_w
;
1440 int pixel_size
= crtc
->primary
->state
->fb
->bits_per_pixel
/ 8;
1441 unsigned long line_time_us
;
1444 line_time_us
= max(htotal
* 1000 / clock
, 1);
1446 /* Use ns/us then divide to preserve precision */
1447 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
1448 pixel_size
* hdisplay
;
1449 entries
= DIV_ROUND_UP(entries
, I915_FIFO_LINE_SIZE
);
1450 srwm
= I965_FIFO_SIZE
- entries
;
1454 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1457 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
1458 pixel_size
* crtc
->cursor
->state
->crtc_w
;
1459 entries
= DIV_ROUND_UP(entries
,
1460 i965_cursor_wm_info
.cacheline_size
);
1461 cursor_sr
= i965_cursor_wm_info
.fifo_size
-
1462 (entries
+ i965_cursor_wm_info
.guard_size
);
1464 if (cursor_sr
> i965_cursor_wm_info
.max_wm
)
1465 cursor_sr
= i965_cursor_wm_info
.max_wm
;
1467 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1468 "cursor %d\n", srwm
, cursor_sr
);
1470 cxsr_enabled
= true;
1472 cxsr_enabled
= false;
1473 /* Turn off self refresh if both pipes are enabled */
1474 intel_set_memory_cxsr(dev_priv
, false);
1477 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1480 /* 965 has limitations... */
1481 I915_WRITE(DSPFW1
, FW_WM(srwm
, SR
) |
1485 I915_WRITE(DSPFW2
, FW_WM(8, CURSORA
) |
1486 FW_WM(8, PLANEC_OLD
));
1487 /* update cursor SR watermark */
1488 I915_WRITE(DSPFW3
, FW_WM(cursor_sr
, CURSOR_SR
));
1491 intel_set_memory_cxsr(dev_priv
, true);
1496 static void i9xx_update_wm(struct drm_crtc
*unused_crtc
)
1498 struct drm_device
*dev
= unused_crtc
->dev
;
1499 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1500 const struct intel_watermark_params
*wm_info
;
1505 int planea_wm
, planeb_wm
;
1506 struct drm_crtc
*crtc
, *enabled
= NULL
;
1509 wm_info
= &i945_wm_info
;
1510 else if (!IS_GEN2(dev
))
1511 wm_info
= &i915_wm_info
;
1513 wm_info
= &i830_a_wm_info
;
1515 fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 0);
1516 crtc
= intel_get_crtc_for_plane(dev
, 0);
1517 if (intel_crtc_active(crtc
)) {
1518 const struct drm_display_mode
*adjusted_mode
;
1519 int cpp
= crtc
->primary
->state
->fb
->bits_per_pixel
/ 8;
1523 adjusted_mode
= &to_intel_crtc(crtc
)->config
->base
.adjusted_mode
;
1524 planea_wm
= intel_calculate_wm(adjusted_mode
->crtc_clock
,
1525 wm_info
, fifo_size
, cpp
,
1526 pessimal_latency_ns
);
1529 planea_wm
= fifo_size
- wm_info
->guard_size
;
1530 if (planea_wm
> (long)wm_info
->max_wm
)
1531 planea_wm
= wm_info
->max_wm
;
1535 wm_info
= &i830_bc_wm_info
;
1537 fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 1);
1538 crtc
= intel_get_crtc_for_plane(dev
, 1);
1539 if (intel_crtc_active(crtc
)) {
1540 const struct drm_display_mode
*adjusted_mode
;
1541 int cpp
= crtc
->primary
->state
->fb
->bits_per_pixel
/ 8;
1545 adjusted_mode
= &to_intel_crtc(crtc
)->config
->base
.adjusted_mode
;
1546 planeb_wm
= intel_calculate_wm(adjusted_mode
->crtc_clock
,
1547 wm_info
, fifo_size
, cpp
,
1548 pessimal_latency_ns
);
1549 if (enabled
== NULL
)
1554 planeb_wm
= fifo_size
- wm_info
->guard_size
;
1555 if (planeb_wm
> (long)wm_info
->max_wm
)
1556 planeb_wm
= wm_info
->max_wm
;
1559 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm
, planeb_wm
);
1561 if (IS_I915GM(dev
) && enabled
) {
1562 struct drm_i915_gem_object
*obj
;
1564 obj
= intel_fb_obj(enabled
->primary
->state
->fb
);
1566 /* self-refresh seems busted with untiled */
1567 if (obj
->tiling_mode
== I915_TILING_NONE
)
1572 * Overlay gets an aggressive default since video jitter is bad.
1576 /* Play safe and disable self-refresh before adjusting watermarks. */
1577 intel_set_memory_cxsr(dev_priv
, false);
1579 /* Calc sr entries for one plane configs */
1580 if (HAS_FW_BLC(dev
) && enabled
) {
1581 /* self-refresh has much higher latency */
1582 static const int sr_latency_ns
= 6000;
1583 const struct drm_display_mode
*adjusted_mode
= &to_intel_crtc(enabled
)->config
->base
.adjusted_mode
;
1584 int clock
= adjusted_mode
->crtc_clock
;
1585 int htotal
= adjusted_mode
->crtc_htotal
;
1586 int hdisplay
= to_intel_crtc(enabled
)->config
->pipe_src_w
;
1587 int pixel_size
= enabled
->primary
->state
->fb
->bits_per_pixel
/ 8;
1588 unsigned long line_time_us
;
1591 line_time_us
= max(htotal
* 1000 / clock
, 1);
1593 /* Use ns/us then divide to preserve precision */
1594 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
1595 pixel_size
* hdisplay
;
1596 entries
= DIV_ROUND_UP(entries
, wm_info
->cacheline_size
);
1597 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries
);
1598 srwm
= wm_info
->fifo_size
- entries
;
1602 if (IS_I945G(dev
) || IS_I945GM(dev
))
1603 I915_WRITE(FW_BLC_SELF
,
1604 FW_BLC_SELF_FIFO_MASK
| (srwm
& 0xff));
1605 else if (IS_I915GM(dev
))
1606 I915_WRITE(FW_BLC_SELF
, srwm
& 0x3f);
1609 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1610 planea_wm
, planeb_wm
, cwm
, srwm
);
1612 fwater_lo
= ((planeb_wm
& 0x3f) << 16) | (planea_wm
& 0x3f);
1613 fwater_hi
= (cwm
& 0x1f);
1615 /* Set request length to 8 cachelines per fetch */
1616 fwater_lo
= fwater_lo
| (1 << 24) | (1 << 8);
1617 fwater_hi
= fwater_hi
| (1 << 8);
1619 I915_WRITE(FW_BLC
, fwater_lo
);
1620 I915_WRITE(FW_BLC2
, fwater_hi
);
1623 intel_set_memory_cxsr(dev_priv
, true);
1626 static void i845_update_wm(struct drm_crtc
*unused_crtc
)
1628 struct drm_device
*dev
= unused_crtc
->dev
;
1629 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1630 struct drm_crtc
*crtc
;
1631 const struct drm_display_mode
*adjusted_mode
;
1635 crtc
= single_enabled_crtc(dev
);
1639 adjusted_mode
= &to_intel_crtc(crtc
)->config
->base
.adjusted_mode
;
1640 planea_wm
= intel_calculate_wm(adjusted_mode
->crtc_clock
,
1642 dev_priv
->display
.get_fifo_size(dev
, 0),
1643 4, pessimal_latency_ns
);
1644 fwater_lo
= I915_READ(FW_BLC
) & ~0xfff;
1645 fwater_lo
|= (3<<8) | planea_wm
;
1647 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm
);
1649 I915_WRITE(FW_BLC
, fwater_lo
);
1652 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state
*pipe_config
)
1654 uint32_t pixel_rate
;
1656 pixel_rate
= pipe_config
->base
.adjusted_mode
.crtc_clock
;
1658 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1659 * adjust the pixel_rate here. */
1661 if (pipe_config
->pch_pfit
.enabled
) {
1662 uint64_t pipe_w
, pipe_h
, pfit_w
, pfit_h
;
1663 uint32_t pfit_size
= pipe_config
->pch_pfit
.size
;
1665 pipe_w
= pipe_config
->pipe_src_w
;
1666 pipe_h
= pipe_config
->pipe_src_h
;
1668 pfit_w
= (pfit_size
>> 16) & 0xFFFF;
1669 pfit_h
= pfit_size
& 0xFFFF;
1670 if (pipe_w
< pfit_w
)
1672 if (pipe_h
< pfit_h
)
1675 pixel_rate
= div_u64((uint64_t) pixel_rate
* pipe_w
* pipe_h
,
1682 /* latency must be in 0.1us units. */
1683 static uint32_t ilk_wm_method1(uint32_t pixel_rate
, uint8_t bytes_per_pixel
,
1688 if (WARN(latency
== 0, "Latency value missing\n"))
1691 ret
= (uint64_t) pixel_rate
* bytes_per_pixel
* latency
;
1692 ret
= DIV_ROUND_UP_ULL(ret
, 64 * 10000) + 2;
1697 /* latency must be in 0.1us units. */
1698 static uint32_t ilk_wm_method2(uint32_t pixel_rate
, uint32_t pipe_htotal
,
1699 uint32_t horiz_pixels
, uint8_t bytes_per_pixel
,
1704 if (WARN(latency
== 0, "Latency value missing\n"))
1707 ret
= (latency
* pixel_rate
) / (pipe_htotal
* 10000);
1708 ret
= (ret
+ 1) * horiz_pixels
* bytes_per_pixel
;
1709 ret
= DIV_ROUND_UP(ret
, 64) + 2;
1713 static uint32_t ilk_wm_fbc(uint32_t pri_val
, uint32_t horiz_pixels
,
1714 uint8_t bytes_per_pixel
)
1716 return DIV_ROUND_UP(pri_val
* 64, horiz_pixels
* bytes_per_pixel
) + 2;
1719 struct ilk_wm_maximums
{
1727 * For both WM_PIPE and WM_LP.
1728 * mem_value must be in 0.1us units.
1730 static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state
*cstate
,
1731 const struct intel_plane_state
*pstate
,
1735 int bpp
= pstate
->base
.fb
? pstate
->base
.fb
->bits_per_pixel
/ 8 : 0;
1736 uint32_t method1
, method2
;
1738 if (!cstate
->base
.active
|| !pstate
->visible
)
1741 method1
= ilk_wm_method1(ilk_pipe_pixel_rate(cstate
), bpp
, mem_value
);
1746 method2
= ilk_wm_method2(ilk_pipe_pixel_rate(cstate
),
1747 cstate
->base
.adjusted_mode
.crtc_htotal
,
1748 drm_rect_width(&pstate
->dst
),
1752 return min(method1
, method2
);
1756 * For both WM_PIPE and WM_LP.
1757 * mem_value must be in 0.1us units.
1759 static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state
*cstate
,
1760 const struct intel_plane_state
*pstate
,
1763 int bpp
= pstate
->base
.fb
? pstate
->base
.fb
->bits_per_pixel
/ 8 : 0;
1764 uint32_t method1
, method2
;
1766 if (!cstate
->base
.active
|| !pstate
->visible
)
1769 method1
= ilk_wm_method1(ilk_pipe_pixel_rate(cstate
), bpp
, mem_value
);
1770 method2
= ilk_wm_method2(ilk_pipe_pixel_rate(cstate
),
1771 cstate
->base
.adjusted_mode
.crtc_htotal
,
1772 drm_rect_width(&pstate
->dst
),
1775 return min(method1
, method2
);
1779 * For both WM_PIPE and WM_LP.
1780 * mem_value must be in 0.1us units.
1782 static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state
*cstate
,
1783 const struct intel_plane_state
*pstate
,
1787 * We treat the cursor plane as always-on for the purposes of watermark
1788 * calculation. Until we have two-stage watermark programming merged,
1789 * this is necessary to avoid flickering.
1792 int width
= pstate
->visible
? pstate
->base
.crtc_w
: 64;
1794 if (!cstate
->base
.active
)
1797 return ilk_wm_method2(ilk_pipe_pixel_rate(cstate
),
1798 cstate
->base
.adjusted_mode
.crtc_htotal
,
1799 width
, cpp
, mem_value
);
1802 /* Only for WM_LP. */
1803 static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state
*cstate
,
1804 const struct intel_plane_state
*pstate
,
1807 int bpp
= pstate
->base
.fb
? pstate
->base
.fb
->bits_per_pixel
/ 8 : 0;
1809 if (!cstate
->base
.active
|| !pstate
->visible
)
1812 return ilk_wm_fbc(pri_val
, drm_rect_width(&pstate
->dst
), bpp
);
1815 static unsigned int ilk_display_fifo_size(const struct drm_device
*dev
)
1817 if (INTEL_INFO(dev
)->gen
>= 8)
1819 else if (INTEL_INFO(dev
)->gen
>= 7)
1825 static unsigned int ilk_plane_wm_reg_max(const struct drm_device
*dev
,
1826 int level
, bool is_sprite
)
1828 if (INTEL_INFO(dev
)->gen
>= 8)
1829 /* BDW primary/sprite plane watermarks */
1830 return level
== 0 ? 255 : 2047;
1831 else if (INTEL_INFO(dev
)->gen
>= 7)
1832 /* IVB/HSW primary/sprite plane watermarks */
1833 return level
== 0 ? 127 : 1023;
1834 else if (!is_sprite
)
1835 /* ILK/SNB primary plane watermarks */
1836 return level
== 0 ? 127 : 511;
1838 /* ILK/SNB sprite plane watermarks */
1839 return level
== 0 ? 63 : 255;
1842 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device
*dev
,
1845 if (INTEL_INFO(dev
)->gen
>= 7)
1846 return level
== 0 ? 63 : 255;
1848 return level
== 0 ? 31 : 63;
1851 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device
*dev
)
1853 if (INTEL_INFO(dev
)->gen
>= 8)
1859 /* Calculate the maximum primary/sprite plane watermark */
1860 static unsigned int ilk_plane_wm_max(const struct drm_device
*dev
,
1862 const struct intel_wm_config
*config
,
1863 enum intel_ddb_partitioning ddb_partitioning
,
1866 unsigned int fifo_size
= ilk_display_fifo_size(dev
);
1868 /* if sprites aren't enabled, sprites get nothing */
1869 if (is_sprite
&& !config
->sprites_enabled
)
1872 /* HSW allows LP1+ watermarks even with multiple pipes */
1873 if (level
== 0 || config
->num_pipes_active
> 1) {
1874 fifo_size
/= INTEL_INFO(dev
)->num_pipes
;
1877 * For some reason the non self refresh
1878 * FIFO size is only half of the self
1879 * refresh FIFO size on ILK/SNB.
1881 if (INTEL_INFO(dev
)->gen
<= 6)
1885 if (config
->sprites_enabled
) {
1886 /* level 0 is always calculated with 1:1 split */
1887 if (level
> 0 && ddb_partitioning
== INTEL_DDB_PART_5_6
) {
1896 /* clamp to max that the registers can hold */
1897 return min(fifo_size
, ilk_plane_wm_reg_max(dev
, level
, is_sprite
));
1900 /* Calculate the maximum cursor plane watermark */
1901 static unsigned int ilk_cursor_wm_max(const struct drm_device
*dev
,
1903 const struct intel_wm_config
*config
)
1905 /* HSW LP1+ watermarks w/ multiple pipes */
1906 if (level
> 0 && config
->num_pipes_active
> 1)
1909 /* otherwise just report max that registers can hold */
1910 return ilk_cursor_wm_reg_max(dev
, level
);
1913 static void ilk_compute_wm_maximums(const struct drm_device
*dev
,
1915 const struct intel_wm_config
*config
,
1916 enum intel_ddb_partitioning ddb_partitioning
,
1917 struct ilk_wm_maximums
*max
)
1919 max
->pri
= ilk_plane_wm_max(dev
, level
, config
, ddb_partitioning
, false);
1920 max
->spr
= ilk_plane_wm_max(dev
, level
, config
, ddb_partitioning
, true);
1921 max
->cur
= ilk_cursor_wm_max(dev
, level
, config
);
1922 max
->fbc
= ilk_fbc_wm_reg_max(dev
);
1925 static void ilk_compute_wm_reg_maximums(struct drm_device
*dev
,
1927 struct ilk_wm_maximums
*max
)
1929 max
->pri
= ilk_plane_wm_reg_max(dev
, level
, false);
1930 max
->spr
= ilk_plane_wm_reg_max(dev
, level
, true);
1931 max
->cur
= ilk_cursor_wm_reg_max(dev
, level
);
1932 max
->fbc
= ilk_fbc_wm_reg_max(dev
);
1935 static bool ilk_validate_wm_level(int level
,
1936 const struct ilk_wm_maximums
*max
,
1937 struct intel_wm_level
*result
)
1941 /* already determined to be invalid? */
1942 if (!result
->enable
)
1945 result
->enable
= result
->pri_val
<= max
->pri
&&
1946 result
->spr_val
<= max
->spr
&&
1947 result
->cur_val
<= max
->cur
;
1949 ret
= result
->enable
;
1952 * HACK until we can pre-compute everything,
1953 * and thus fail gracefully if LP0 watermarks
1956 if (level
== 0 && !result
->enable
) {
1957 if (result
->pri_val
> max
->pri
)
1958 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1959 level
, result
->pri_val
, max
->pri
);
1960 if (result
->spr_val
> max
->spr
)
1961 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1962 level
, result
->spr_val
, max
->spr
);
1963 if (result
->cur_val
> max
->cur
)
1964 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1965 level
, result
->cur_val
, max
->cur
);
1967 result
->pri_val
= min_t(uint32_t, result
->pri_val
, max
->pri
);
1968 result
->spr_val
= min_t(uint32_t, result
->spr_val
, max
->spr
);
1969 result
->cur_val
= min_t(uint32_t, result
->cur_val
, max
->cur
);
1970 result
->enable
= true;
1976 static void ilk_compute_wm_level(const struct drm_i915_private
*dev_priv
,
1977 const struct intel_crtc
*intel_crtc
,
1979 struct intel_crtc_state
*cstate
,
1980 struct intel_plane_state
*pristate
,
1981 struct intel_plane_state
*sprstate
,
1982 struct intel_plane_state
*curstate
,
1983 struct intel_wm_level
*result
)
1985 uint16_t pri_latency
= dev_priv
->wm
.pri_latency
[level
];
1986 uint16_t spr_latency
= dev_priv
->wm
.spr_latency
[level
];
1987 uint16_t cur_latency
= dev_priv
->wm
.cur_latency
[level
];
1989 /* WM1+ latency values stored in 0.5us units */
1996 result
->pri_val
= ilk_compute_pri_wm(cstate
, pristate
,
1997 pri_latency
, level
);
1998 result
->spr_val
= ilk_compute_spr_wm(cstate
, sprstate
, spr_latency
);
1999 result
->cur_val
= ilk_compute_cur_wm(cstate
, curstate
, cur_latency
);
2000 result
->fbc_val
= ilk_compute_fbc_wm(cstate
, pristate
, result
->pri_val
);
2001 result
->enable
= true;
2005 hsw_compute_linetime_wm(struct drm_device
*dev
, struct drm_crtc
*crtc
)
2007 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2008 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2009 const struct drm_display_mode
*adjusted_mode
= &intel_crtc
->config
->base
.adjusted_mode
;
2010 u32 linetime
, ips_linetime
;
2012 if (!intel_crtc
->active
)
2015 /* The WM are computed with base on how long it takes to fill a single
2016 * row at the given clock rate, multiplied by 8.
2018 linetime
= DIV_ROUND_CLOSEST(adjusted_mode
->crtc_htotal
* 1000 * 8,
2019 adjusted_mode
->crtc_clock
);
2020 ips_linetime
= DIV_ROUND_CLOSEST(adjusted_mode
->crtc_htotal
* 1000 * 8,
2021 dev_priv
->cdclk_freq
);
2023 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime
) |
2024 PIPE_WM_LINETIME_TIME(linetime
);
2027 static void intel_read_wm_latency(struct drm_device
*dev
, uint16_t wm
[8])
2029 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2034 int level
, max_level
= ilk_wm_max_level(dev
);
2036 /* read the first set of memory latencies[0:3] */
2037 val
= 0; /* data0 to be programmed to 0 for first set */
2038 mutex_lock(&dev_priv
->rps
.hw_lock
);
2039 ret
= sandybridge_pcode_read(dev_priv
,
2040 GEN9_PCODE_READ_MEM_LATENCY
,
2042 mutex_unlock(&dev_priv
->rps
.hw_lock
);
2045 DRM_ERROR("SKL Mailbox read error = %d\n", ret
);
2049 wm
[0] = val
& GEN9_MEM_LATENCY_LEVEL_MASK
;
2050 wm
[1] = (val
>> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT
) &
2051 GEN9_MEM_LATENCY_LEVEL_MASK
;
2052 wm
[2] = (val
>> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT
) &
2053 GEN9_MEM_LATENCY_LEVEL_MASK
;
2054 wm
[3] = (val
>> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT
) &
2055 GEN9_MEM_LATENCY_LEVEL_MASK
;
2057 /* read the second set of memory latencies[4:7] */
2058 val
= 1; /* data0 to be programmed to 1 for second set */
2059 mutex_lock(&dev_priv
->rps
.hw_lock
);
2060 ret
= sandybridge_pcode_read(dev_priv
,
2061 GEN9_PCODE_READ_MEM_LATENCY
,
2063 mutex_unlock(&dev_priv
->rps
.hw_lock
);
2065 DRM_ERROR("SKL Mailbox read error = %d\n", ret
);
2069 wm
[4] = val
& GEN9_MEM_LATENCY_LEVEL_MASK
;
2070 wm
[5] = (val
>> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT
) &
2071 GEN9_MEM_LATENCY_LEVEL_MASK
;
2072 wm
[6] = (val
>> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT
) &
2073 GEN9_MEM_LATENCY_LEVEL_MASK
;
2074 wm
[7] = (val
>> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT
) &
2075 GEN9_MEM_LATENCY_LEVEL_MASK
;
2078 * WaWmMemoryReadLatency:skl
2080 * punit doesn't take into account the read latency so we need
2081 * to add 2us to the various latency levels we retrieve from
2083 * - W0 is a bit special in that it's the only level that
2084 * can't be disabled if we want to have display working, so
2085 * we always add 2us there.
2086 * - For levels >=1, punit returns 0us latency when they are
2087 * disabled, so we respect that and don't add 2us then
2089 * Additionally, if a level n (n > 1) has a 0us latency, all
2090 * levels m (m >= n) need to be disabled. We make sure to
2091 * sanitize the values out of the punit to satisfy this
2095 for (level
= 1; level
<= max_level
; level
++)
2099 for (i
= level
+ 1; i
<= max_level
; i
++)
2104 } else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2105 uint64_t sskpd
= I915_READ64(MCH_SSKPD
);
2107 wm
[0] = (sskpd
>> 56) & 0xFF;
2109 wm
[0] = sskpd
& 0xF;
2110 wm
[1] = (sskpd
>> 4) & 0xFF;
2111 wm
[2] = (sskpd
>> 12) & 0xFF;
2112 wm
[3] = (sskpd
>> 20) & 0x1FF;
2113 wm
[4] = (sskpd
>> 32) & 0x1FF;
2114 } else if (INTEL_INFO(dev
)->gen
>= 6) {
2115 uint32_t sskpd
= I915_READ(MCH_SSKPD
);
2117 wm
[0] = (sskpd
>> SSKPD_WM0_SHIFT
) & SSKPD_WM_MASK
;
2118 wm
[1] = (sskpd
>> SSKPD_WM1_SHIFT
) & SSKPD_WM_MASK
;
2119 wm
[2] = (sskpd
>> SSKPD_WM2_SHIFT
) & SSKPD_WM_MASK
;
2120 wm
[3] = (sskpd
>> SSKPD_WM3_SHIFT
) & SSKPD_WM_MASK
;
2121 } else if (INTEL_INFO(dev
)->gen
>= 5) {
2122 uint32_t mltr
= I915_READ(MLTR_ILK
);
2124 /* ILK primary LP0 latency is 700 ns */
2126 wm
[1] = (mltr
>> MLTR_WM1_SHIFT
) & ILK_SRLT_MASK
;
2127 wm
[2] = (mltr
>> MLTR_WM2_SHIFT
) & ILK_SRLT_MASK
;
2131 static void intel_fixup_spr_wm_latency(struct drm_device
*dev
, uint16_t wm
[5])
2133 /* ILK sprite LP0 latency is 1300 ns */
2134 if (INTEL_INFO(dev
)->gen
== 5)
2138 static void intel_fixup_cur_wm_latency(struct drm_device
*dev
, uint16_t wm
[5])
2140 /* ILK cursor LP0 latency is 1300 ns */
2141 if (INTEL_INFO(dev
)->gen
== 5)
2144 /* WaDoubleCursorLP3Latency:ivb */
2145 if (IS_IVYBRIDGE(dev
))
2149 int ilk_wm_max_level(const struct drm_device
*dev
)
2151 /* how many WM levels are we expecting */
2152 if (INTEL_INFO(dev
)->gen
>= 9)
2154 else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2156 else if (INTEL_INFO(dev
)->gen
>= 6)
2162 static void intel_print_wm_latency(struct drm_device
*dev
,
2164 const uint16_t wm
[8])
2166 int level
, max_level
= ilk_wm_max_level(dev
);
2168 for (level
= 0; level
<= max_level
; level
++) {
2169 unsigned int latency
= wm
[level
];
2172 DRM_ERROR("%s WM%d latency not provided\n",
2178 * - latencies are in us on gen9.
2179 * - before then, WM1+ latency values are in 0.5us units
2186 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2187 name
, level
, wm
[level
],
2188 latency
/ 10, latency
% 10);
2192 static bool ilk_increase_wm_latency(struct drm_i915_private
*dev_priv
,
2193 uint16_t wm
[5], uint16_t min
)
2195 int level
, max_level
= ilk_wm_max_level(dev_priv
->dev
);
2200 wm
[0] = max(wm
[0], min
);
2201 for (level
= 1; level
<= max_level
; level
++)
2202 wm
[level
] = max_t(uint16_t, wm
[level
], DIV_ROUND_UP(min
, 5));
2207 static void snb_wm_latency_quirk(struct drm_device
*dev
)
2209 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2213 * The BIOS provided WM memory latency values are often
2214 * inadequate for high resolution displays. Adjust them.
2216 changed
= ilk_increase_wm_latency(dev_priv
, dev_priv
->wm
.pri_latency
, 12) |
2217 ilk_increase_wm_latency(dev_priv
, dev_priv
->wm
.spr_latency
, 12) |
2218 ilk_increase_wm_latency(dev_priv
, dev_priv
->wm
.cur_latency
, 12);
2223 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2224 intel_print_wm_latency(dev
, "Primary", dev_priv
->wm
.pri_latency
);
2225 intel_print_wm_latency(dev
, "Sprite", dev_priv
->wm
.spr_latency
);
2226 intel_print_wm_latency(dev
, "Cursor", dev_priv
->wm
.cur_latency
);
2229 static void ilk_setup_wm_latency(struct drm_device
*dev
)
2231 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2233 intel_read_wm_latency(dev
, dev_priv
->wm
.pri_latency
);
2235 memcpy(dev_priv
->wm
.spr_latency
, dev_priv
->wm
.pri_latency
,
2236 sizeof(dev_priv
->wm
.pri_latency
));
2237 memcpy(dev_priv
->wm
.cur_latency
, dev_priv
->wm
.pri_latency
,
2238 sizeof(dev_priv
->wm
.pri_latency
));
2240 intel_fixup_spr_wm_latency(dev
, dev_priv
->wm
.spr_latency
);
2241 intel_fixup_cur_wm_latency(dev
, dev_priv
->wm
.cur_latency
);
2243 intel_print_wm_latency(dev
, "Primary", dev_priv
->wm
.pri_latency
);
2244 intel_print_wm_latency(dev
, "Sprite", dev_priv
->wm
.spr_latency
);
2245 intel_print_wm_latency(dev
, "Cursor", dev_priv
->wm
.cur_latency
);
2248 snb_wm_latency_quirk(dev
);
2251 static void skl_setup_wm_latency(struct drm_device
*dev
)
2253 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2255 intel_read_wm_latency(dev
, dev_priv
->wm
.skl_latency
);
2256 intel_print_wm_latency(dev
, "Gen9 Plane", dev_priv
->wm
.skl_latency
);
2259 /* Compute new watermarks for the pipe */
2260 static int ilk_compute_pipe_wm(struct intel_crtc
*intel_crtc
,
2261 struct drm_atomic_state
*state
)
2263 struct intel_pipe_wm
*pipe_wm
;
2264 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2265 const struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2266 struct intel_crtc_state
*cstate
= NULL
;
2267 struct intel_plane
*intel_plane
;
2268 struct drm_plane_state
*ps
;
2269 struct intel_plane_state
*pristate
= NULL
;
2270 struct intel_plane_state
*sprstate
= NULL
;
2271 struct intel_plane_state
*curstate
= NULL
;
2272 int level
, max_level
= ilk_wm_max_level(dev
);
2273 /* LP0 watermark maximums depend on this pipe alone */
2274 struct intel_wm_config config
= {
2275 .num_pipes_active
= 1,
2277 struct ilk_wm_maximums max
;
2279 cstate
= intel_atomic_get_crtc_state(state
, intel_crtc
);
2281 return PTR_ERR(cstate
);
2283 pipe_wm
= &cstate
->wm
.optimal
.ilk
;
2285 for_each_intel_plane_on_crtc(dev
, intel_crtc
, intel_plane
) {
2286 ps
= drm_atomic_get_plane_state(state
,
2287 &intel_plane
->base
);
2291 if (intel_plane
->base
.type
== DRM_PLANE_TYPE_PRIMARY
)
2292 pristate
= to_intel_plane_state(ps
);
2293 else if (intel_plane
->base
.type
== DRM_PLANE_TYPE_OVERLAY
)
2294 sprstate
= to_intel_plane_state(ps
);
2295 else if (intel_plane
->base
.type
== DRM_PLANE_TYPE_CURSOR
)
2296 curstate
= to_intel_plane_state(ps
);
2299 config
.sprites_enabled
= sprstate
->visible
;
2300 config
.sprites_scaled
= sprstate
->visible
&&
2301 (drm_rect_width(&sprstate
->dst
) != drm_rect_width(&sprstate
->src
) >> 16 ||
2302 drm_rect_height(&sprstate
->dst
) != drm_rect_height(&sprstate
->src
) >> 16);
2304 pipe_wm
->pipe_enabled
= cstate
->base
.active
;
2305 pipe_wm
->sprites_enabled
= config
.sprites_enabled
;
2306 pipe_wm
->sprites_scaled
= config
.sprites_scaled
;
2308 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2309 if (INTEL_INFO(dev
)->gen
<= 6 && sprstate
->visible
)
2312 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2313 if (config
.sprites_scaled
)
2316 ilk_compute_wm_level(dev_priv
, intel_crtc
, 0, cstate
,
2317 pristate
, sprstate
, curstate
, &pipe_wm
->wm
[0]);
2319 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2320 pipe_wm
->linetime
= hsw_compute_linetime_wm(dev
,
2323 /* LP0 watermarks always use 1/2 DDB partitioning */
2324 ilk_compute_wm_maximums(dev
, 0, &config
, INTEL_DDB_PART_1_2
, &max
);
2326 /* At least LP0 must be valid */
2327 if (!ilk_validate_wm_level(0, &max
, &pipe_wm
->wm
[0]))
2330 ilk_compute_wm_reg_maximums(dev
, 1, &max
);
2332 for (level
= 1; level
<= max_level
; level
++) {
2333 struct intel_wm_level wm
= {};
2335 ilk_compute_wm_level(dev_priv
, intel_crtc
, level
, cstate
,
2336 pristate
, sprstate
, curstate
, &wm
);
2339 * Disable any watermark level that exceeds the
2340 * register maximums since such watermarks are
2343 if (!ilk_validate_wm_level(level
, &max
, &wm
))
2346 pipe_wm
->wm
[level
] = wm
;
2353 * Merge the watermarks from all active pipes for a specific level.
2355 static void ilk_merge_wm_level(struct drm_device
*dev
,
2357 struct intel_wm_level
*ret_wm
)
2359 const struct intel_crtc
*intel_crtc
;
2361 ret_wm
->enable
= true;
2363 for_each_intel_crtc(dev
, intel_crtc
) {
2364 const struct intel_crtc_state
*cstate
=
2365 to_intel_crtc_state(intel_crtc
->base
.state
);
2366 const struct intel_pipe_wm
*active
= &cstate
->wm
.optimal
.ilk
;
2367 const struct intel_wm_level
*wm
= &active
->wm
[level
];
2369 if (!active
->pipe_enabled
)
2373 * The watermark values may have been used in the past,
2374 * so we must maintain them in the registers for some
2375 * time even if the level is now disabled.
2378 ret_wm
->enable
= false;
2380 ret_wm
->pri_val
= max(ret_wm
->pri_val
, wm
->pri_val
);
2381 ret_wm
->spr_val
= max(ret_wm
->spr_val
, wm
->spr_val
);
2382 ret_wm
->cur_val
= max(ret_wm
->cur_val
, wm
->cur_val
);
2383 ret_wm
->fbc_val
= max(ret_wm
->fbc_val
, wm
->fbc_val
);
2388 * Merge all low power watermarks for all active pipes.
2390 static void ilk_wm_merge(struct drm_device
*dev
,
2391 const struct intel_wm_config
*config
,
2392 const struct ilk_wm_maximums
*max
,
2393 struct intel_pipe_wm
*merged
)
2395 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2396 int level
, max_level
= ilk_wm_max_level(dev
);
2397 int last_enabled_level
= max_level
;
2399 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2400 if ((INTEL_INFO(dev
)->gen
<= 6 || IS_IVYBRIDGE(dev
)) &&
2401 config
->num_pipes_active
> 1)
2404 /* ILK: FBC WM must be disabled always */
2405 merged
->fbc_wm_enabled
= INTEL_INFO(dev
)->gen
>= 6;
2407 /* merge each WM1+ level */
2408 for (level
= 1; level
<= max_level
; level
++) {
2409 struct intel_wm_level
*wm
= &merged
->wm
[level
];
2411 ilk_merge_wm_level(dev
, level
, wm
);
2413 if (level
> last_enabled_level
)
2415 else if (!ilk_validate_wm_level(level
, max
, wm
))
2416 /* make sure all following levels get disabled */
2417 last_enabled_level
= level
- 1;
2420 * The spec says it is preferred to disable
2421 * FBC WMs instead of disabling a WM level.
2423 if (wm
->fbc_val
> max
->fbc
) {
2425 merged
->fbc_wm_enabled
= false;
2430 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2432 * FIXME this is racy. FBC might get enabled later.
2433 * What we should check here is whether FBC can be
2434 * enabled sometime later.
2436 if (IS_GEN5(dev
) && !merged
->fbc_wm_enabled
&&
2437 intel_fbc_is_active(dev_priv
)) {
2438 for (level
= 2; level
<= max_level
; level
++) {
2439 struct intel_wm_level
*wm
= &merged
->wm
[level
];
2446 static int ilk_wm_lp_to_level(int wm_lp
, const struct intel_pipe_wm
*pipe_wm
)
2448 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2449 return wm_lp
+ (wm_lp
>= 2 && pipe_wm
->wm
[4].enable
);
2452 /* The value we need to program into the WM_LPx latency field */
2453 static unsigned int ilk_wm_lp_latency(struct drm_device
*dev
, int level
)
2455 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2457 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2460 return dev_priv
->wm
.pri_latency
[level
];
2463 static void ilk_compute_wm_results(struct drm_device
*dev
,
2464 const struct intel_pipe_wm
*merged
,
2465 enum intel_ddb_partitioning partitioning
,
2466 struct ilk_wm_values
*results
)
2468 struct intel_crtc
*intel_crtc
;
2471 results
->enable_fbc_wm
= merged
->fbc_wm_enabled
;
2472 results
->partitioning
= partitioning
;
2474 /* LP1+ register values */
2475 for (wm_lp
= 1; wm_lp
<= 3; wm_lp
++) {
2476 const struct intel_wm_level
*r
;
2478 level
= ilk_wm_lp_to_level(wm_lp
, merged
);
2480 r
= &merged
->wm
[level
];
2483 * Maintain the watermark values even if the level is
2484 * disabled. Doing otherwise could cause underruns.
2486 results
->wm_lp
[wm_lp
- 1] =
2487 (ilk_wm_lp_latency(dev
, level
) << WM1_LP_LATENCY_SHIFT
) |
2488 (r
->pri_val
<< WM1_LP_SR_SHIFT
) |
2492 results
->wm_lp
[wm_lp
- 1] |= WM1_LP_SR_EN
;
2494 if (INTEL_INFO(dev
)->gen
>= 8)
2495 results
->wm_lp
[wm_lp
- 1] |=
2496 r
->fbc_val
<< WM1_LP_FBC_SHIFT_BDW
;
2498 results
->wm_lp
[wm_lp
- 1] |=
2499 r
->fbc_val
<< WM1_LP_FBC_SHIFT
;
2502 * Always set WM1S_LP_EN when spr_val != 0, even if the
2503 * level is disabled. Doing otherwise could cause underruns.
2505 if (INTEL_INFO(dev
)->gen
<= 6 && r
->spr_val
) {
2506 WARN_ON(wm_lp
!= 1);
2507 results
->wm_lp_spr
[wm_lp
- 1] = WM1S_LP_EN
| r
->spr_val
;
2509 results
->wm_lp_spr
[wm_lp
- 1] = r
->spr_val
;
2512 /* LP0 register values */
2513 for_each_intel_crtc(dev
, intel_crtc
) {
2514 const struct intel_crtc_state
*cstate
=
2515 to_intel_crtc_state(intel_crtc
->base
.state
);
2516 enum pipe pipe
= intel_crtc
->pipe
;
2517 const struct intel_wm_level
*r
= &cstate
->wm
.optimal
.ilk
.wm
[0];
2519 if (WARN_ON(!r
->enable
))
2522 results
->wm_linetime
[pipe
] = cstate
->wm
.optimal
.ilk
.linetime
;
2524 results
->wm_pipe
[pipe
] =
2525 (r
->pri_val
<< WM0_PIPE_PLANE_SHIFT
) |
2526 (r
->spr_val
<< WM0_PIPE_SPRITE_SHIFT
) |
2531 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2532 * case both are at the same level. Prefer r1 in case they're the same. */
2533 static struct intel_pipe_wm
*ilk_find_best_result(struct drm_device
*dev
,
2534 struct intel_pipe_wm
*r1
,
2535 struct intel_pipe_wm
*r2
)
2537 int level
, max_level
= ilk_wm_max_level(dev
);
2538 int level1
= 0, level2
= 0;
2540 for (level
= 1; level
<= max_level
; level
++) {
2541 if (r1
->wm
[level
].enable
)
2543 if (r2
->wm
[level
].enable
)
2547 if (level1
== level2
) {
2548 if (r2
->fbc_wm_enabled
&& !r1
->fbc_wm_enabled
)
2552 } else if (level1
> level2
) {
2559 /* dirty bits used to track which watermarks need changes */
2560 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2561 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2562 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2563 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2564 #define WM_DIRTY_FBC (1 << 24)
2565 #define WM_DIRTY_DDB (1 << 25)
2567 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private
*dev_priv
,
2568 const struct ilk_wm_values
*old
,
2569 const struct ilk_wm_values
*new)
2571 unsigned int dirty
= 0;
2575 for_each_pipe(dev_priv
, pipe
) {
2576 if (old
->wm_linetime
[pipe
] != new->wm_linetime
[pipe
]) {
2577 dirty
|= WM_DIRTY_LINETIME(pipe
);
2578 /* Must disable LP1+ watermarks too */
2579 dirty
|= WM_DIRTY_LP_ALL
;
2582 if (old
->wm_pipe
[pipe
] != new->wm_pipe
[pipe
]) {
2583 dirty
|= WM_DIRTY_PIPE(pipe
);
2584 /* Must disable LP1+ watermarks too */
2585 dirty
|= WM_DIRTY_LP_ALL
;
2589 if (old
->enable_fbc_wm
!= new->enable_fbc_wm
) {
2590 dirty
|= WM_DIRTY_FBC
;
2591 /* Must disable LP1+ watermarks too */
2592 dirty
|= WM_DIRTY_LP_ALL
;
2595 if (old
->partitioning
!= new->partitioning
) {
2596 dirty
|= WM_DIRTY_DDB
;
2597 /* Must disable LP1+ watermarks too */
2598 dirty
|= WM_DIRTY_LP_ALL
;
2601 /* LP1+ watermarks already deemed dirty, no need to continue */
2602 if (dirty
& WM_DIRTY_LP_ALL
)
2605 /* Find the lowest numbered LP1+ watermark in need of an update... */
2606 for (wm_lp
= 1; wm_lp
<= 3; wm_lp
++) {
2607 if (old
->wm_lp
[wm_lp
- 1] != new->wm_lp
[wm_lp
- 1] ||
2608 old
->wm_lp_spr
[wm_lp
- 1] != new->wm_lp_spr
[wm_lp
- 1])
2612 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2613 for (; wm_lp
<= 3; wm_lp
++)
2614 dirty
|= WM_DIRTY_LP(wm_lp
);
2619 static bool _ilk_disable_lp_wm(struct drm_i915_private
*dev_priv
,
2622 struct ilk_wm_values
*previous
= &dev_priv
->wm
.hw
;
2623 bool changed
= false;
2625 if (dirty
& WM_DIRTY_LP(3) && previous
->wm_lp
[2] & WM1_LP_SR_EN
) {
2626 previous
->wm_lp
[2] &= ~WM1_LP_SR_EN
;
2627 I915_WRITE(WM3_LP_ILK
, previous
->wm_lp
[2]);
2630 if (dirty
& WM_DIRTY_LP(2) && previous
->wm_lp
[1] & WM1_LP_SR_EN
) {
2631 previous
->wm_lp
[1] &= ~WM1_LP_SR_EN
;
2632 I915_WRITE(WM2_LP_ILK
, previous
->wm_lp
[1]);
2635 if (dirty
& WM_DIRTY_LP(1) && previous
->wm_lp
[0] & WM1_LP_SR_EN
) {
2636 previous
->wm_lp
[0] &= ~WM1_LP_SR_EN
;
2637 I915_WRITE(WM1_LP_ILK
, previous
->wm_lp
[0]);
2642 * Don't touch WM1S_LP_EN here.
2643 * Doing so could cause underruns.
2650 * The spec says we shouldn't write when we don't need, because every write
2651 * causes WMs to be re-evaluated, expending some power.
2653 static void ilk_write_wm_values(struct drm_i915_private
*dev_priv
,
2654 struct ilk_wm_values
*results
)
2656 struct drm_device
*dev
= dev_priv
->dev
;
2657 struct ilk_wm_values
*previous
= &dev_priv
->wm
.hw
;
2661 dirty
= ilk_compute_wm_dirty(dev_priv
, previous
, results
);
2665 _ilk_disable_lp_wm(dev_priv
, dirty
);
2667 if (dirty
& WM_DIRTY_PIPE(PIPE_A
))
2668 I915_WRITE(WM0_PIPEA_ILK
, results
->wm_pipe
[0]);
2669 if (dirty
& WM_DIRTY_PIPE(PIPE_B
))
2670 I915_WRITE(WM0_PIPEB_ILK
, results
->wm_pipe
[1]);
2671 if (dirty
& WM_DIRTY_PIPE(PIPE_C
))
2672 I915_WRITE(WM0_PIPEC_IVB
, results
->wm_pipe
[2]);
2674 if (dirty
& WM_DIRTY_LINETIME(PIPE_A
))
2675 I915_WRITE(PIPE_WM_LINETIME(PIPE_A
), results
->wm_linetime
[0]);
2676 if (dirty
& WM_DIRTY_LINETIME(PIPE_B
))
2677 I915_WRITE(PIPE_WM_LINETIME(PIPE_B
), results
->wm_linetime
[1]);
2678 if (dirty
& WM_DIRTY_LINETIME(PIPE_C
))
2679 I915_WRITE(PIPE_WM_LINETIME(PIPE_C
), results
->wm_linetime
[2]);
2681 if (dirty
& WM_DIRTY_DDB
) {
2682 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2683 val
= I915_READ(WM_MISC
);
2684 if (results
->partitioning
== INTEL_DDB_PART_1_2
)
2685 val
&= ~WM_MISC_DATA_PARTITION_5_6
;
2687 val
|= WM_MISC_DATA_PARTITION_5_6
;
2688 I915_WRITE(WM_MISC
, val
);
2690 val
= I915_READ(DISP_ARB_CTL2
);
2691 if (results
->partitioning
== INTEL_DDB_PART_1_2
)
2692 val
&= ~DISP_DATA_PARTITION_5_6
;
2694 val
|= DISP_DATA_PARTITION_5_6
;
2695 I915_WRITE(DISP_ARB_CTL2
, val
);
2699 if (dirty
& WM_DIRTY_FBC
) {
2700 val
= I915_READ(DISP_ARB_CTL
);
2701 if (results
->enable_fbc_wm
)
2702 val
&= ~DISP_FBC_WM_DIS
;
2704 val
|= DISP_FBC_WM_DIS
;
2705 I915_WRITE(DISP_ARB_CTL
, val
);
2708 if (dirty
& WM_DIRTY_LP(1) &&
2709 previous
->wm_lp_spr
[0] != results
->wm_lp_spr
[0])
2710 I915_WRITE(WM1S_LP_ILK
, results
->wm_lp_spr
[0]);
2712 if (INTEL_INFO(dev
)->gen
>= 7) {
2713 if (dirty
& WM_DIRTY_LP(2) && previous
->wm_lp_spr
[1] != results
->wm_lp_spr
[1])
2714 I915_WRITE(WM2S_LP_IVB
, results
->wm_lp_spr
[1]);
2715 if (dirty
& WM_DIRTY_LP(3) && previous
->wm_lp_spr
[2] != results
->wm_lp_spr
[2])
2716 I915_WRITE(WM3S_LP_IVB
, results
->wm_lp_spr
[2]);
2719 if (dirty
& WM_DIRTY_LP(1) && previous
->wm_lp
[0] != results
->wm_lp
[0])
2720 I915_WRITE(WM1_LP_ILK
, results
->wm_lp
[0]);
2721 if (dirty
& WM_DIRTY_LP(2) && previous
->wm_lp
[1] != results
->wm_lp
[1])
2722 I915_WRITE(WM2_LP_ILK
, results
->wm_lp
[1]);
2723 if (dirty
& WM_DIRTY_LP(3) && previous
->wm_lp
[2] != results
->wm_lp
[2])
2724 I915_WRITE(WM3_LP_ILK
, results
->wm_lp
[2]);
2726 dev_priv
->wm
.hw
= *results
;
2729 static bool ilk_disable_lp_wm(struct drm_device
*dev
)
2731 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2733 return _ilk_disable_lp_wm(dev_priv
, WM_DIRTY_LP_ALL
);
2737 * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2738 * different active planes.
2741 #define SKL_DDB_SIZE 896 /* in blocks */
2742 #define BXT_DDB_SIZE 512
2745 * Return the index of a plane in the SKL DDB and wm result arrays. Primary
2746 * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
2747 * other universal planes are in indices 1..n. Note that this may leave unused
2748 * indices between the top "sprite" plane and the cursor.
2751 skl_wm_plane_id(const struct intel_plane
*plane
)
2753 switch (plane
->base
.type
) {
2754 case DRM_PLANE_TYPE_PRIMARY
:
2756 case DRM_PLANE_TYPE_CURSOR
:
2757 return PLANE_CURSOR
;
2758 case DRM_PLANE_TYPE_OVERLAY
:
2759 return plane
->plane
+ 1;
2761 MISSING_CASE(plane
->base
.type
);
2762 return plane
->plane
;
2767 skl_ddb_get_pipe_allocation_limits(struct drm_device
*dev
,
2768 const struct intel_crtc_state
*cstate
,
2769 const struct intel_wm_config
*config
,
2770 struct skl_ddb_entry
*alloc
/* out */)
2772 struct drm_crtc
*for_crtc
= cstate
->base
.crtc
;
2773 struct drm_crtc
*crtc
;
2774 unsigned int pipe_size
, ddb_size
;
2775 int nth_active_pipe
;
2777 if (!cstate
->base
.active
) {
2783 if (IS_BROXTON(dev
))
2784 ddb_size
= BXT_DDB_SIZE
;
2786 ddb_size
= SKL_DDB_SIZE
;
2788 ddb_size
-= 4; /* 4 blocks for bypass path allocation */
2790 nth_active_pipe
= 0;
2791 for_each_crtc(dev
, crtc
) {
2792 if (!to_intel_crtc(crtc
)->active
)
2795 if (crtc
== for_crtc
)
2801 pipe_size
= ddb_size
/ config
->num_pipes_active
;
2802 alloc
->start
= nth_active_pipe
* ddb_size
/ config
->num_pipes_active
;
2803 alloc
->end
= alloc
->start
+ pipe_size
;
2806 static unsigned int skl_cursor_allocation(const struct intel_wm_config
*config
)
2808 if (config
->num_pipes_active
== 1)
2814 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry
*entry
, u32 reg
)
2816 entry
->start
= reg
& 0x3ff;
2817 entry
->end
= (reg
>> 16) & 0x3ff;
2822 void skl_ddb_get_hw_state(struct drm_i915_private
*dev_priv
,
2823 struct skl_ddb_allocation
*ddb
/* out */)
2829 memset(ddb
, 0, sizeof(*ddb
));
2831 for_each_pipe(dev_priv
, pipe
) {
2832 enum intel_display_power_domain power_domain
;
2834 power_domain
= POWER_DOMAIN_PIPE(pipe
);
2835 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
))
2838 for_each_plane(dev_priv
, pipe
, plane
) {
2839 val
= I915_READ(PLANE_BUF_CFG(pipe
, plane
));
2840 skl_ddb_entry_init_from_hw(&ddb
->plane
[pipe
][plane
],
2844 val
= I915_READ(CUR_BUF_CFG(pipe
));
2845 skl_ddb_entry_init_from_hw(&ddb
->plane
[pipe
][PLANE_CURSOR
],
2848 intel_display_power_put(dev_priv
, power_domain
);
2853 skl_plane_relative_data_rate(const struct intel_crtc_state
*cstate
,
2854 const struct drm_plane_state
*pstate
,
2857 struct intel_crtc
*intel_crtc
= to_intel_crtc(cstate
->base
.crtc
);
2858 struct drm_framebuffer
*fb
= pstate
->fb
;
2860 /* for planar format */
2861 if (fb
->pixel_format
== DRM_FORMAT_NV12
) {
2862 if (y
) /* y-plane data rate */
2863 return intel_crtc
->config
->pipe_src_w
*
2864 intel_crtc
->config
->pipe_src_h
*
2865 drm_format_plane_cpp(fb
->pixel_format
, 0);
2866 else /* uv-plane data rate */
2867 return (intel_crtc
->config
->pipe_src_w
/2) *
2868 (intel_crtc
->config
->pipe_src_h
/2) *
2869 drm_format_plane_cpp(fb
->pixel_format
, 1);
2872 /* for packed formats */
2873 return intel_crtc
->config
->pipe_src_w
*
2874 intel_crtc
->config
->pipe_src_h
*
2875 drm_format_plane_cpp(fb
->pixel_format
, 0);
2879 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
2880 * a 8192x4096@32bpp framebuffer:
2881 * 3 * 4096 * 8192 * 4 < 2^32
2884 skl_get_total_relative_data_rate(const struct intel_crtc_state
*cstate
)
2886 struct intel_crtc
*intel_crtc
= to_intel_crtc(cstate
->base
.crtc
);
2887 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2888 const struct intel_plane
*intel_plane
;
2889 unsigned int total_data_rate
= 0;
2891 for_each_intel_plane_on_crtc(dev
, intel_crtc
, intel_plane
) {
2892 const struct drm_plane_state
*pstate
= intel_plane
->base
.state
;
2894 if (pstate
->fb
== NULL
)
2897 if (intel_plane
->base
.type
== DRM_PLANE_TYPE_CURSOR
)
2901 total_data_rate
+= skl_plane_relative_data_rate(cstate
,
2905 if (pstate
->fb
->pixel_format
== DRM_FORMAT_NV12
)
2907 total_data_rate
+= skl_plane_relative_data_rate(cstate
,
2912 return total_data_rate
;
2916 skl_allocate_pipe_ddb(struct intel_crtc_state
*cstate
,
2917 struct skl_ddb_allocation
*ddb
/* out */)
2919 struct drm_crtc
*crtc
= cstate
->base
.crtc
;
2920 struct drm_device
*dev
= crtc
->dev
;
2921 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2922 struct intel_wm_config
*config
= &dev_priv
->wm
.config
;
2923 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2924 struct intel_plane
*intel_plane
;
2925 enum pipe pipe
= intel_crtc
->pipe
;
2926 struct skl_ddb_entry
*alloc
= &ddb
->pipe
[pipe
];
2927 uint16_t alloc_size
, start
, cursor_blocks
;
2928 uint16_t minimum
[I915_MAX_PLANES
];
2929 uint16_t y_minimum
[I915_MAX_PLANES
];
2930 unsigned int total_data_rate
;
2932 skl_ddb_get_pipe_allocation_limits(dev
, cstate
, config
, alloc
);
2933 alloc_size
= skl_ddb_entry_size(alloc
);
2934 if (alloc_size
== 0) {
2935 memset(ddb
->plane
[pipe
], 0, sizeof(ddb
->plane
[pipe
]));
2936 memset(&ddb
->plane
[pipe
][PLANE_CURSOR
], 0,
2937 sizeof(ddb
->plane
[pipe
][PLANE_CURSOR
]));
2941 cursor_blocks
= skl_cursor_allocation(config
);
2942 ddb
->plane
[pipe
][PLANE_CURSOR
].start
= alloc
->end
- cursor_blocks
;
2943 ddb
->plane
[pipe
][PLANE_CURSOR
].end
= alloc
->end
;
2945 alloc_size
-= cursor_blocks
;
2946 alloc
->end
-= cursor_blocks
;
2948 /* 1. Allocate the mininum required blocks for each active plane */
2949 for_each_intel_plane_on_crtc(dev
, intel_crtc
, intel_plane
) {
2950 struct drm_plane
*plane
= &intel_plane
->base
;
2951 struct drm_framebuffer
*fb
= plane
->state
->fb
;
2952 int id
= skl_wm_plane_id(intel_plane
);
2956 if (plane
->type
== DRM_PLANE_TYPE_CURSOR
)
2960 alloc_size
-= minimum
[id
];
2961 y_minimum
[id
] = (fb
->pixel_format
== DRM_FORMAT_NV12
) ? 8 : 0;
2962 alloc_size
-= y_minimum
[id
];
2966 * 2. Distribute the remaining space in proportion to the amount of
2967 * data each plane needs to fetch from memory.
2969 * FIXME: we may not allocate every single block here.
2971 total_data_rate
= skl_get_total_relative_data_rate(cstate
);
2973 start
= alloc
->start
;
2974 for_each_intel_plane_on_crtc(dev
, intel_crtc
, intel_plane
) {
2975 struct drm_plane
*plane
= &intel_plane
->base
;
2976 struct drm_plane_state
*pstate
= intel_plane
->base
.state
;
2977 unsigned int data_rate
, y_data_rate
;
2978 uint16_t plane_blocks
, y_plane_blocks
= 0;
2979 int id
= skl_wm_plane_id(intel_plane
);
2981 if (pstate
->fb
== NULL
)
2983 if (plane
->type
== DRM_PLANE_TYPE_CURSOR
)
2986 data_rate
= skl_plane_relative_data_rate(cstate
, pstate
, 0);
2989 * allocation for (packed formats) or (uv-plane part of planar format):
2990 * promote the expression to 64 bits to avoid overflowing, the
2991 * result is < available as data_rate / total_data_rate < 1
2993 plane_blocks
= minimum
[id
];
2994 plane_blocks
+= div_u64((uint64_t)alloc_size
* data_rate
,
2997 ddb
->plane
[pipe
][id
].start
= start
;
2998 ddb
->plane
[pipe
][id
].end
= start
+ plane_blocks
;
3000 start
+= plane_blocks
;
3003 * allocation for y_plane part of planar format:
3005 if (pstate
->fb
->pixel_format
== DRM_FORMAT_NV12
) {
3006 y_data_rate
= skl_plane_relative_data_rate(cstate
,
3009 y_plane_blocks
= y_minimum
[id
];
3010 y_plane_blocks
+= div_u64((uint64_t)alloc_size
* y_data_rate
,
3013 ddb
->y_plane
[pipe
][id
].start
= start
;
3014 ddb
->y_plane
[pipe
][id
].end
= start
+ y_plane_blocks
;
3016 start
+= y_plane_blocks
;
3023 static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state
*config
)
3025 /* TODO: Take into account the scalers once we support them */
3026 return config
->base
.adjusted_mode
.crtc_clock
;
3030 * The max latency should be 257 (max the punit can code is 255 and we add 2us
3031 * for the read latency) and bytes_per_pixel should always be <= 8, so that
3032 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3033 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3035 static uint32_t skl_wm_method1(uint32_t pixel_rate
, uint8_t bytes_per_pixel
,
3038 uint32_t wm_intermediate_val
, ret
;
3043 wm_intermediate_val
= latency
* pixel_rate
* bytes_per_pixel
/ 512;
3044 ret
= DIV_ROUND_UP(wm_intermediate_val
, 1000);
3049 static uint32_t skl_wm_method2(uint32_t pixel_rate
, uint32_t pipe_htotal
,
3050 uint32_t horiz_pixels
, uint8_t bytes_per_pixel
,
3051 uint64_t tiling
, uint32_t latency
)
3054 uint32_t plane_bytes_per_line
, plane_blocks_per_line
;
3055 uint32_t wm_intermediate_val
;
3060 plane_bytes_per_line
= horiz_pixels
* bytes_per_pixel
;
3062 if (tiling
== I915_FORMAT_MOD_Y_TILED
||
3063 tiling
== I915_FORMAT_MOD_Yf_TILED
) {
3064 plane_bytes_per_line
*= 4;
3065 plane_blocks_per_line
= DIV_ROUND_UP(plane_bytes_per_line
, 512);
3066 plane_blocks_per_line
/= 4;
3068 plane_blocks_per_line
= DIV_ROUND_UP(plane_bytes_per_line
, 512);
3071 wm_intermediate_val
= latency
* pixel_rate
;
3072 ret
= DIV_ROUND_UP(wm_intermediate_val
, pipe_htotal
* 1000) *
3073 plane_blocks_per_line
;
3078 static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation
*new_ddb
,
3079 const struct intel_crtc
*intel_crtc
)
3081 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3082 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3083 const struct skl_ddb_allocation
*cur_ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
3086 * If ddb allocation of pipes changed, it may require recalculation of
3089 if (memcmp(new_ddb
->pipe
, cur_ddb
->pipe
, sizeof(new_ddb
->pipe
)))
3095 static bool skl_compute_plane_wm(const struct drm_i915_private
*dev_priv
,
3096 struct intel_crtc_state
*cstate
,
3097 struct intel_plane
*intel_plane
,
3098 uint16_t ddb_allocation
,
3100 uint16_t *out_blocks
, /* out */
3101 uint8_t *out_lines
/* out */)
3103 struct drm_plane
*plane
= &intel_plane
->base
;
3104 struct drm_framebuffer
*fb
= plane
->state
->fb
;
3105 uint32_t latency
= dev_priv
->wm
.skl_latency
[level
];
3106 uint32_t method1
, method2
;
3107 uint32_t plane_bytes_per_line
, plane_blocks_per_line
;
3108 uint32_t res_blocks
, res_lines
;
3109 uint32_t selected_result
;
3110 uint8_t bytes_per_pixel
;
3112 if (latency
== 0 || !cstate
->base
.active
|| !fb
)
3115 bytes_per_pixel
= drm_format_plane_cpp(fb
->pixel_format
, 0);
3116 method1
= skl_wm_method1(skl_pipe_pixel_rate(cstate
),
3119 method2
= skl_wm_method2(skl_pipe_pixel_rate(cstate
),
3120 cstate
->base
.adjusted_mode
.crtc_htotal
,
3126 plane_bytes_per_line
= cstate
->pipe_src_w
* bytes_per_pixel
;
3127 plane_blocks_per_line
= DIV_ROUND_UP(plane_bytes_per_line
, 512);
3129 if (fb
->modifier
[0] == I915_FORMAT_MOD_Y_TILED
||
3130 fb
->modifier
[0] == I915_FORMAT_MOD_Yf_TILED
) {
3131 uint32_t min_scanlines
= 4;
3132 uint32_t y_tile_minimum
;
3133 if (intel_rotation_90_or_270(plane
->state
->rotation
)) {
3134 int bpp
= (fb
->pixel_format
== DRM_FORMAT_NV12
) ?
3135 drm_format_plane_cpp(fb
->pixel_format
, 1) :
3136 drm_format_plane_cpp(fb
->pixel_format
, 0);
3146 WARN(1, "Unsupported pixel depth for rotation");
3149 y_tile_minimum
= plane_blocks_per_line
* min_scanlines
;
3150 selected_result
= max(method2
, y_tile_minimum
);
3152 if ((ddb_allocation
/ plane_blocks_per_line
) >= 1)
3153 selected_result
= min(method1
, method2
);
3155 selected_result
= method1
;
3158 res_blocks
= selected_result
+ 1;
3159 res_lines
= DIV_ROUND_UP(selected_result
, plane_blocks_per_line
);
3161 if (level
>= 1 && level
<= 7) {
3162 if (fb
->modifier
[0] == I915_FORMAT_MOD_Y_TILED
||
3163 fb
->modifier
[0] == I915_FORMAT_MOD_Yf_TILED
)
3169 if (res_blocks
>= ddb_allocation
|| res_lines
> 31)
3172 *out_blocks
= res_blocks
;
3173 *out_lines
= res_lines
;
3178 static void skl_compute_wm_level(const struct drm_i915_private
*dev_priv
,
3179 struct skl_ddb_allocation
*ddb
,
3180 struct intel_crtc_state
*cstate
,
3182 struct skl_wm_level
*result
)
3184 struct drm_device
*dev
= dev_priv
->dev
;
3185 struct intel_crtc
*intel_crtc
= to_intel_crtc(cstate
->base
.crtc
);
3186 struct intel_plane
*intel_plane
;
3187 uint16_t ddb_blocks
;
3188 enum pipe pipe
= intel_crtc
->pipe
;
3190 for_each_intel_plane_on_crtc(dev
, intel_crtc
, intel_plane
) {
3191 int i
= skl_wm_plane_id(intel_plane
);
3193 ddb_blocks
= skl_ddb_entry_size(&ddb
->plane
[pipe
][i
]);
3195 result
->plane_en
[i
] = skl_compute_plane_wm(dev_priv
,
3200 &result
->plane_res_b
[i
],
3201 &result
->plane_res_l
[i
]);
3206 skl_compute_linetime_wm(struct intel_crtc_state
*cstate
)
3208 if (!cstate
->base
.active
)
3211 if (WARN_ON(skl_pipe_pixel_rate(cstate
) == 0))
3214 return DIV_ROUND_UP(8 * cstate
->base
.adjusted_mode
.crtc_htotal
* 1000,
3215 skl_pipe_pixel_rate(cstate
));
3218 static void skl_compute_transition_wm(struct intel_crtc_state
*cstate
,
3219 struct skl_wm_level
*trans_wm
/* out */)
3221 struct drm_crtc
*crtc
= cstate
->base
.crtc
;
3222 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3223 struct intel_plane
*intel_plane
;
3225 if (!cstate
->base
.active
)
3228 /* Until we know more, just disable transition WMs */
3229 for_each_intel_plane_on_crtc(crtc
->dev
, intel_crtc
, intel_plane
) {
3230 int i
= skl_wm_plane_id(intel_plane
);
3232 trans_wm
->plane_en
[i
] = false;
3236 static void skl_compute_pipe_wm(struct intel_crtc_state
*cstate
,
3237 struct skl_ddb_allocation
*ddb
,
3238 struct skl_pipe_wm
*pipe_wm
)
3240 struct drm_device
*dev
= cstate
->base
.crtc
->dev
;
3241 const struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3242 int level
, max_level
= ilk_wm_max_level(dev
);
3244 for (level
= 0; level
<= max_level
; level
++) {
3245 skl_compute_wm_level(dev_priv
, ddb
, cstate
,
3246 level
, &pipe_wm
->wm
[level
]);
3248 pipe_wm
->linetime
= skl_compute_linetime_wm(cstate
);
3250 skl_compute_transition_wm(cstate
, &pipe_wm
->trans_wm
);
3253 static void skl_compute_wm_results(struct drm_device
*dev
,
3254 struct skl_pipe_wm
*p_wm
,
3255 struct skl_wm_values
*r
,
3256 struct intel_crtc
*intel_crtc
)
3258 int level
, max_level
= ilk_wm_max_level(dev
);
3259 enum pipe pipe
= intel_crtc
->pipe
;
3263 for (level
= 0; level
<= max_level
; level
++) {
3264 for (i
= 0; i
< intel_num_planes(intel_crtc
); i
++) {
3267 temp
|= p_wm
->wm
[level
].plane_res_l
[i
] <<
3268 PLANE_WM_LINES_SHIFT
;
3269 temp
|= p_wm
->wm
[level
].plane_res_b
[i
];
3270 if (p_wm
->wm
[level
].plane_en
[i
])
3271 temp
|= PLANE_WM_EN
;
3273 r
->plane
[pipe
][i
][level
] = temp
;
3278 temp
|= p_wm
->wm
[level
].plane_res_l
[PLANE_CURSOR
] << PLANE_WM_LINES_SHIFT
;
3279 temp
|= p_wm
->wm
[level
].plane_res_b
[PLANE_CURSOR
];
3281 if (p_wm
->wm
[level
].plane_en
[PLANE_CURSOR
])
3282 temp
|= PLANE_WM_EN
;
3284 r
->plane
[pipe
][PLANE_CURSOR
][level
] = temp
;
3288 /* transition WMs */
3289 for (i
= 0; i
< intel_num_planes(intel_crtc
); i
++) {
3291 temp
|= p_wm
->trans_wm
.plane_res_l
[i
] << PLANE_WM_LINES_SHIFT
;
3292 temp
|= p_wm
->trans_wm
.plane_res_b
[i
];
3293 if (p_wm
->trans_wm
.plane_en
[i
])
3294 temp
|= PLANE_WM_EN
;
3296 r
->plane_trans
[pipe
][i
] = temp
;
3300 temp
|= p_wm
->trans_wm
.plane_res_l
[PLANE_CURSOR
] << PLANE_WM_LINES_SHIFT
;
3301 temp
|= p_wm
->trans_wm
.plane_res_b
[PLANE_CURSOR
];
3302 if (p_wm
->trans_wm
.plane_en
[PLANE_CURSOR
])
3303 temp
|= PLANE_WM_EN
;
3305 r
->plane_trans
[pipe
][PLANE_CURSOR
] = temp
;
3307 r
->wm_linetime
[pipe
] = p_wm
->linetime
;
3310 static void skl_ddb_entry_write(struct drm_i915_private
*dev_priv
,
3312 const struct skl_ddb_entry
*entry
)
3315 I915_WRITE(reg
, (entry
->end
- 1) << 16 | entry
->start
);
3320 static void skl_write_wm_values(struct drm_i915_private
*dev_priv
,
3321 const struct skl_wm_values
*new)
3323 struct drm_device
*dev
= dev_priv
->dev
;
3324 struct intel_crtc
*crtc
;
3326 for_each_intel_crtc(dev
, crtc
) {
3327 int i
, level
, max_level
= ilk_wm_max_level(dev
);
3328 enum pipe pipe
= crtc
->pipe
;
3330 if (!new->dirty
[pipe
])
3333 I915_WRITE(PIPE_WM_LINETIME(pipe
), new->wm_linetime
[pipe
]);
3335 for (level
= 0; level
<= max_level
; level
++) {
3336 for (i
= 0; i
< intel_num_planes(crtc
); i
++)
3337 I915_WRITE(PLANE_WM(pipe
, i
, level
),
3338 new->plane
[pipe
][i
][level
]);
3339 I915_WRITE(CUR_WM(pipe
, level
),
3340 new->plane
[pipe
][PLANE_CURSOR
][level
]);
3342 for (i
= 0; i
< intel_num_planes(crtc
); i
++)
3343 I915_WRITE(PLANE_WM_TRANS(pipe
, i
),
3344 new->plane_trans
[pipe
][i
]);
3345 I915_WRITE(CUR_WM_TRANS(pipe
),
3346 new->plane_trans
[pipe
][PLANE_CURSOR
]);
3348 for (i
= 0; i
< intel_num_planes(crtc
); i
++) {
3349 skl_ddb_entry_write(dev_priv
,
3350 PLANE_BUF_CFG(pipe
, i
),
3351 &new->ddb
.plane
[pipe
][i
]);
3352 skl_ddb_entry_write(dev_priv
,
3353 PLANE_NV12_BUF_CFG(pipe
, i
),
3354 &new->ddb
.y_plane
[pipe
][i
]);
3357 skl_ddb_entry_write(dev_priv
, CUR_BUF_CFG(pipe
),
3358 &new->ddb
.plane
[pipe
][PLANE_CURSOR
]);
3363 * When setting up a new DDB allocation arrangement, we need to correctly
3364 * sequence the times at which the new allocations for the pipes are taken into
3365 * account or we'll have pipes fetching from space previously allocated to
3368 * Roughly the sequence looks like:
3369 * 1. re-allocate the pipe(s) with the allocation being reduced and not
3370 * overlapping with a previous light-up pipe (another way to put it is:
3371 * pipes with their new allocation strickly included into their old ones).
3372 * 2. re-allocate the other pipes that get their allocation reduced
3373 * 3. allocate the pipes having their allocation increased
3375 * Steps 1. and 2. are here to take care of the following case:
3376 * - Initially DDB looks like this:
3379 * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
3383 * We need to sequence the re-allocation: C, B, A (and not B, C, A).
3387 skl_wm_flush_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int pass
)
3391 DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe
), pass
);
3393 for_each_plane(dev_priv
, pipe
, plane
) {
3394 I915_WRITE(PLANE_SURF(pipe
, plane
),
3395 I915_READ(PLANE_SURF(pipe
, plane
)));
3397 I915_WRITE(CURBASE(pipe
), I915_READ(CURBASE(pipe
)));
3401 skl_ddb_allocation_included(const struct skl_ddb_allocation
*old
,
3402 const struct skl_ddb_allocation
*new,
3405 uint16_t old_size
, new_size
;
3407 old_size
= skl_ddb_entry_size(&old
->pipe
[pipe
]);
3408 new_size
= skl_ddb_entry_size(&new->pipe
[pipe
]);
3410 return old_size
!= new_size
&&
3411 new->pipe
[pipe
].start
>= old
->pipe
[pipe
].start
&&
3412 new->pipe
[pipe
].end
<= old
->pipe
[pipe
].end
;
3415 static void skl_flush_wm_values(struct drm_i915_private
*dev_priv
,
3416 struct skl_wm_values
*new_values
)
3418 struct drm_device
*dev
= dev_priv
->dev
;
3419 struct skl_ddb_allocation
*cur_ddb
, *new_ddb
;
3420 bool reallocated
[I915_MAX_PIPES
] = {};
3421 struct intel_crtc
*crtc
;
3424 new_ddb
= &new_values
->ddb
;
3425 cur_ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
3428 * First pass: flush the pipes with the new allocation contained into
3431 * We'll wait for the vblank on those pipes to ensure we can safely
3432 * re-allocate the freed space without this pipe fetching from it.
3434 for_each_intel_crtc(dev
, crtc
) {
3440 if (!skl_ddb_allocation_included(cur_ddb
, new_ddb
, pipe
))
3443 skl_wm_flush_pipe(dev_priv
, pipe
, 1);
3444 intel_wait_for_vblank(dev
, pipe
);
3446 reallocated
[pipe
] = true;
3451 * Second pass: flush the pipes that are having their allocation
3452 * reduced, but overlapping with a previous allocation.
3454 * Here as well we need to wait for the vblank to make sure the freed
3455 * space is not used anymore.
3457 for_each_intel_crtc(dev
, crtc
) {
3463 if (reallocated
[pipe
])
3466 if (skl_ddb_entry_size(&new_ddb
->pipe
[pipe
]) <
3467 skl_ddb_entry_size(&cur_ddb
->pipe
[pipe
])) {
3468 skl_wm_flush_pipe(dev_priv
, pipe
, 2);
3469 intel_wait_for_vblank(dev
, pipe
);
3470 reallocated
[pipe
] = true;
3475 * Third pass: flush the pipes that got more space allocated.
3477 * We don't need to actively wait for the update here, next vblank
3478 * will just get more DDB space with the correct WM values.
3480 for_each_intel_crtc(dev
, crtc
) {
3487 * At this point, only the pipes more space than before are
3488 * left to re-allocate.
3490 if (reallocated
[pipe
])
3493 skl_wm_flush_pipe(dev_priv
, pipe
, 3);
3497 static bool skl_update_pipe_wm(struct drm_crtc
*crtc
,
3498 struct skl_ddb_allocation
*ddb
, /* out */
3499 struct skl_pipe_wm
*pipe_wm
/* out */)
3501 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3502 struct intel_crtc_state
*cstate
= to_intel_crtc_state(crtc
->state
);
3504 skl_allocate_pipe_ddb(cstate
, ddb
);
3505 skl_compute_pipe_wm(cstate
, ddb
, pipe_wm
);
3507 if (!memcmp(&intel_crtc
->wm
.active
.skl
, pipe_wm
, sizeof(*pipe_wm
)))
3510 intel_crtc
->wm
.active
.skl
= *pipe_wm
;
3515 static void skl_update_other_pipe_wm(struct drm_device
*dev
,
3516 struct drm_crtc
*crtc
,
3517 struct skl_wm_values
*r
)
3519 struct intel_crtc
*intel_crtc
;
3520 struct intel_crtc
*this_crtc
= to_intel_crtc(crtc
);
3523 * If the WM update hasn't changed the allocation for this_crtc (the
3524 * crtc we are currently computing the new WM values for), other
3525 * enabled crtcs will keep the same allocation and we don't need to
3526 * recompute anything for them.
3528 if (!skl_ddb_allocation_changed(&r
->ddb
, this_crtc
))
3532 * Otherwise, because of this_crtc being freshly enabled/disabled, the
3533 * other active pipes need new DDB allocation and WM values.
3535 for_each_intel_crtc(dev
, intel_crtc
) {
3536 struct skl_pipe_wm pipe_wm
= {};
3539 if (this_crtc
->pipe
== intel_crtc
->pipe
)
3542 if (!intel_crtc
->active
)
3545 wm_changed
= skl_update_pipe_wm(&intel_crtc
->base
,
3549 * If we end up re-computing the other pipe WM values, it's
3550 * because it was really needed, so we expect the WM values to
3553 WARN_ON(!wm_changed
);
3555 skl_compute_wm_results(dev
, &pipe_wm
, r
, intel_crtc
);
3556 r
->dirty
[intel_crtc
->pipe
] = true;
3560 static void skl_clear_wm(struct skl_wm_values
*watermarks
, enum pipe pipe
)
3562 watermarks
->wm_linetime
[pipe
] = 0;
3563 memset(watermarks
->plane
[pipe
], 0,
3564 sizeof(uint32_t) * 8 * I915_MAX_PLANES
);
3565 memset(watermarks
->plane_trans
[pipe
],
3566 0, sizeof(uint32_t) * I915_MAX_PLANES
);
3567 watermarks
->plane_trans
[pipe
][PLANE_CURSOR
] = 0;
3569 /* Clear ddb entries for pipe */
3570 memset(&watermarks
->ddb
.pipe
[pipe
], 0, sizeof(struct skl_ddb_entry
));
3571 memset(&watermarks
->ddb
.plane
[pipe
], 0,
3572 sizeof(struct skl_ddb_entry
) * I915_MAX_PLANES
);
3573 memset(&watermarks
->ddb
.y_plane
[pipe
], 0,
3574 sizeof(struct skl_ddb_entry
) * I915_MAX_PLANES
);
3575 memset(&watermarks
->ddb
.plane
[pipe
][PLANE_CURSOR
], 0,
3576 sizeof(struct skl_ddb_entry
));
3580 static void skl_update_wm(struct drm_crtc
*crtc
)
3582 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3583 struct drm_device
*dev
= crtc
->dev
;
3584 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3585 struct skl_wm_values
*results
= &dev_priv
->wm
.skl_results
;
3586 struct intel_crtc_state
*cstate
= to_intel_crtc_state(crtc
->state
);
3587 struct skl_pipe_wm
*pipe_wm
= &cstate
->wm
.optimal
.skl
;
3590 /* Clear all dirty flags */
3591 memset(results
->dirty
, 0, sizeof(bool) * I915_MAX_PIPES
);
3593 skl_clear_wm(results
, intel_crtc
->pipe
);
3595 if (!skl_update_pipe_wm(crtc
, &results
->ddb
, pipe_wm
))
3598 skl_compute_wm_results(dev
, pipe_wm
, results
, intel_crtc
);
3599 results
->dirty
[intel_crtc
->pipe
] = true;
3601 skl_update_other_pipe_wm(dev
, crtc
, results
);
3602 skl_write_wm_values(dev_priv
, results
);
3603 skl_flush_wm_values(dev_priv
, results
);
3605 /* store the new configuration */
3606 dev_priv
->wm
.skl_hw
= *results
;
3609 static void ilk_program_watermarks(struct drm_i915_private
*dev_priv
)
3611 struct drm_device
*dev
= dev_priv
->dev
;
3612 struct intel_pipe_wm lp_wm_1_2
= {}, lp_wm_5_6
= {}, *best_lp_wm
;
3613 struct ilk_wm_maximums max
;
3614 struct intel_wm_config
*config
= &dev_priv
->wm
.config
;
3615 struct ilk_wm_values results
= {};
3616 enum intel_ddb_partitioning partitioning
;
3618 ilk_compute_wm_maximums(dev
, 1, config
, INTEL_DDB_PART_1_2
, &max
);
3619 ilk_wm_merge(dev
, config
, &max
, &lp_wm_1_2
);
3621 /* 5/6 split only in single pipe config on IVB+ */
3622 if (INTEL_INFO(dev
)->gen
>= 7 &&
3623 config
->num_pipes_active
== 1 && config
->sprites_enabled
) {
3624 ilk_compute_wm_maximums(dev
, 1, config
, INTEL_DDB_PART_5_6
, &max
);
3625 ilk_wm_merge(dev
, config
, &max
, &lp_wm_5_6
);
3627 best_lp_wm
= ilk_find_best_result(dev
, &lp_wm_1_2
, &lp_wm_5_6
);
3629 best_lp_wm
= &lp_wm_1_2
;
3632 partitioning
= (best_lp_wm
== &lp_wm_1_2
) ?
3633 INTEL_DDB_PART_1_2
: INTEL_DDB_PART_5_6
;
3635 ilk_compute_wm_results(dev
, best_lp_wm
, partitioning
, &results
);
3637 ilk_write_wm_values(dev_priv
, &results
);
3640 static void ilk_update_wm(struct drm_crtc
*crtc
)
3642 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
3643 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3644 struct intel_crtc_state
*cstate
= to_intel_crtc_state(crtc
->state
);
3646 WARN_ON(cstate
->base
.active
!= intel_crtc
->active
);
3649 * IVB workaround: must disable low power watermarks for at least
3650 * one frame before enabling scaling. LP watermarks can be re-enabled
3651 * when scaling is disabled.
3653 * WaCxSRDisabledForSpriteScaling:ivb
3655 if (cstate
->disable_lp_wm
) {
3656 ilk_disable_lp_wm(crtc
->dev
);
3657 intel_wait_for_vblank(crtc
->dev
, intel_crtc
->pipe
);
3660 intel_crtc
->wm
.active
.ilk
= cstate
->wm
.optimal
.ilk
;
3662 ilk_program_watermarks(dev_priv
);
3665 static void skl_pipe_wm_active_state(uint32_t val
,
3666 struct skl_pipe_wm
*active
,
3672 bool is_enabled
= (val
& PLANE_WM_EN
) != 0;
3676 active
->wm
[level
].plane_en
[i
] = is_enabled
;
3677 active
->wm
[level
].plane_res_b
[i
] =
3678 val
& PLANE_WM_BLOCKS_MASK
;
3679 active
->wm
[level
].plane_res_l
[i
] =
3680 (val
>> PLANE_WM_LINES_SHIFT
) &
3681 PLANE_WM_LINES_MASK
;
3683 active
->wm
[level
].plane_en
[PLANE_CURSOR
] = is_enabled
;
3684 active
->wm
[level
].plane_res_b
[PLANE_CURSOR
] =
3685 val
& PLANE_WM_BLOCKS_MASK
;
3686 active
->wm
[level
].plane_res_l
[PLANE_CURSOR
] =
3687 (val
>> PLANE_WM_LINES_SHIFT
) &
3688 PLANE_WM_LINES_MASK
;
3692 active
->trans_wm
.plane_en
[i
] = is_enabled
;
3693 active
->trans_wm
.plane_res_b
[i
] =
3694 val
& PLANE_WM_BLOCKS_MASK
;
3695 active
->trans_wm
.plane_res_l
[i
] =
3696 (val
>> PLANE_WM_LINES_SHIFT
) &
3697 PLANE_WM_LINES_MASK
;
3699 active
->trans_wm
.plane_en
[PLANE_CURSOR
] = is_enabled
;
3700 active
->trans_wm
.plane_res_b
[PLANE_CURSOR
] =
3701 val
& PLANE_WM_BLOCKS_MASK
;
3702 active
->trans_wm
.plane_res_l
[PLANE_CURSOR
] =
3703 (val
>> PLANE_WM_LINES_SHIFT
) &
3704 PLANE_WM_LINES_MASK
;
3709 static void skl_pipe_wm_get_hw_state(struct drm_crtc
*crtc
)
3711 struct drm_device
*dev
= crtc
->dev
;
3712 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3713 struct skl_wm_values
*hw
= &dev_priv
->wm
.skl_hw
;
3714 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3715 struct intel_crtc_state
*cstate
= to_intel_crtc_state(crtc
->state
);
3716 struct skl_pipe_wm
*active
= &cstate
->wm
.optimal
.skl
;
3717 enum pipe pipe
= intel_crtc
->pipe
;
3718 int level
, i
, max_level
;
3721 max_level
= ilk_wm_max_level(dev
);
3723 hw
->wm_linetime
[pipe
] = I915_READ(PIPE_WM_LINETIME(pipe
));
3725 for (level
= 0; level
<= max_level
; level
++) {
3726 for (i
= 0; i
< intel_num_planes(intel_crtc
); i
++)
3727 hw
->plane
[pipe
][i
][level
] =
3728 I915_READ(PLANE_WM(pipe
, i
, level
));
3729 hw
->plane
[pipe
][PLANE_CURSOR
][level
] = I915_READ(CUR_WM(pipe
, level
));
3732 for (i
= 0; i
< intel_num_planes(intel_crtc
); i
++)
3733 hw
->plane_trans
[pipe
][i
] = I915_READ(PLANE_WM_TRANS(pipe
, i
));
3734 hw
->plane_trans
[pipe
][PLANE_CURSOR
] = I915_READ(CUR_WM_TRANS(pipe
));
3736 if (!intel_crtc
->active
)
3739 hw
->dirty
[pipe
] = true;
3741 active
->linetime
= hw
->wm_linetime
[pipe
];
3743 for (level
= 0; level
<= max_level
; level
++) {
3744 for (i
= 0; i
< intel_num_planes(intel_crtc
); i
++) {
3745 temp
= hw
->plane
[pipe
][i
][level
];
3746 skl_pipe_wm_active_state(temp
, active
, false,
3749 temp
= hw
->plane
[pipe
][PLANE_CURSOR
][level
];
3750 skl_pipe_wm_active_state(temp
, active
, false, true, i
, level
);
3753 for (i
= 0; i
< intel_num_planes(intel_crtc
); i
++) {
3754 temp
= hw
->plane_trans
[pipe
][i
];
3755 skl_pipe_wm_active_state(temp
, active
, true, false, i
, 0);
3758 temp
= hw
->plane_trans
[pipe
][PLANE_CURSOR
];
3759 skl_pipe_wm_active_state(temp
, active
, true, true, i
, 0);
3761 intel_crtc
->wm
.active
.skl
= *active
;
3764 void skl_wm_get_hw_state(struct drm_device
*dev
)
3766 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3767 struct skl_ddb_allocation
*ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
3768 struct drm_crtc
*crtc
;
3770 skl_ddb_get_hw_state(dev_priv
, ddb
);
3771 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
)
3772 skl_pipe_wm_get_hw_state(crtc
);
3775 static void ilk_pipe_wm_get_hw_state(struct drm_crtc
*crtc
)
3777 struct drm_device
*dev
= crtc
->dev
;
3778 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3779 struct ilk_wm_values
*hw
= &dev_priv
->wm
.hw
;
3780 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3781 struct intel_crtc_state
*cstate
= to_intel_crtc_state(crtc
->state
);
3782 struct intel_pipe_wm
*active
= &cstate
->wm
.optimal
.ilk
;
3783 enum pipe pipe
= intel_crtc
->pipe
;
3784 static const i915_reg_t wm0_pipe_reg
[] = {
3785 [PIPE_A
] = WM0_PIPEA_ILK
,
3786 [PIPE_B
] = WM0_PIPEB_ILK
,
3787 [PIPE_C
] = WM0_PIPEC_IVB
,
3790 hw
->wm_pipe
[pipe
] = I915_READ(wm0_pipe_reg
[pipe
]);
3791 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
3792 hw
->wm_linetime
[pipe
] = I915_READ(PIPE_WM_LINETIME(pipe
));
3794 active
->pipe_enabled
= intel_crtc
->active
;
3796 if (active
->pipe_enabled
) {
3797 u32 tmp
= hw
->wm_pipe
[pipe
];
3800 * For active pipes LP0 watermark is marked as
3801 * enabled, and LP1+ watermaks as disabled since
3802 * we can't really reverse compute them in case
3803 * multiple pipes are active.
3805 active
->wm
[0].enable
= true;
3806 active
->wm
[0].pri_val
= (tmp
& WM0_PIPE_PLANE_MASK
) >> WM0_PIPE_PLANE_SHIFT
;
3807 active
->wm
[0].spr_val
= (tmp
& WM0_PIPE_SPRITE_MASK
) >> WM0_PIPE_SPRITE_SHIFT
;
3808 active
->wm
[0].cur_val
= tmp
& WM0_PIPE_CURSOR_MASK
;
3809 active
->linetime
= hw
->wm_linetime
[pipe
];
3811 int level
, max_level
= ilk_wm_max_level(dev
);
3814 * For inactive pipes, all watermark levels
3815 * should be marked as enabled but zeroed,
3816 * which is what we'd compute them to.
3818 for (level
= 0; level
<= max_level
; level
++)
3819 active
->wm
[level
].enable
= true;
3822 intel_crtc
->wm
.active
.ilk
= *active
;
3825 #define _FW_WM(value, plane) \
3826 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
3827 #define _FW_WM_VLV(value, plane) \
3828 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
3830 static void vlv_read_wm_values(struct drm_i915_private
*dev_priv
,
3831 struct vlv_wm_values
*wm
)
3836 for_each_pipe(dev_priv
, pipe
) {
3837 tmp
= I915_READ(VLV_DDL(pipe
));
3839 wm
->ddl
[pipe
].primary
=
3840 (tmp
>> DDL_PLANE_SHIFT
) & (DDL_PRECISION_HIGH
| DRAIN_LATENCY_MASK
);
3841 wm
->ddl
[pipe
].cursor
=
3842 (tmp
>> DDL_CURSOR_SHIFT
) & (DDL_PRECISION_HIGH
| DRAIN_LATENCY_MASK
);
3843 wm
->ddl
[pipe
].sprite
[0] =
3844 (tmp
>> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH
| DRAIN_LATENCY_MASK
);
3845 wm
->ddl
[pipe
].sprite
[1] =
3846 (tmp
>> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH
| DRAIN_LATENCY_MASK
);
3849 tmp
= I915_READ(DSPFW1
);
3850 wm
->sr
.plane
= _FW_WM(tmp
, SR
);
3851 wm
->pipe
[PIPE_B
].cursor
= _FW_WM(tmp
, CURSORB
);
3852 wm
->pipe
[PIPE_B
].primary
= _FW_WM_VLV(tmp
, PLANEB
);
3853 wm
->pipe
[PIPE_A
].primary
= _FW_WM_VLV(tmp
, PLANEA
);
3855 tmp
= I915_READ(DSPFW2
);
3856 wm
->pipe
[PIPE_A
].sprite
[1] = _FW_WM_VLV(tmp
, SPRITEB
);
3857 wm
->pipe
[PIPE_A
].cursor
= _FW_WM(tmp
, CURSORA
);
3858 wm
->pipe
[PIPE_A
].sprite
[0] = _FW_WM_VLV(tmp
, SPRITEA
);
3860 tmp
= I915_READ(DSPFW3
);
3861 wm
->sr
.cursor
= _FW_WM(tmp
, CURSOR_SR
);
3863 if (IS_CHERRYVIEW(dev_priv
)) {
3864 tmp
= I915_READ(DSPFW7_CHV
);
3865 wm
->pipe
[PIPE_B
].sprite
[1] = _FW_WM_VLV(tmp
, SPRITED
);
3866 wm
->pipe
[PIPE_B
].sprite
[0] = _FW_WM_VLV(tmp
, SPRITEC
);
3868 tmp
= I915_READ(DSPFW8_CHV
);
3869 wm
->pipe
[PIPE_C
].sprite
[1] = _FW_WM_VLV(tmp
, SPRITEF
);
3870 wm
->pipe
[PIPE_C
].sprite
[0] = _FW_WM_VLV(tmp
, SPRITEE
);
3872 tmp
= I915_READ(DSPFW9_CHV
);
3873 wm
->pipe
[PIPE_C
].primary
= _FW_WM_VLV(tmp
, PLANEC
);
3874 wm
->pipe
[PIPE_C
].cursor
= _FW_WM(tmp
, CURSORC
);
3876 tmp
= I915_READ(DSPHOWM
);
3877 wm
->sr
.plane
|= _FW_WM(tmp
, SR_HI
) << 9;
3878 wm
->pipe
[PIPE_C
].sprite
[1] |= _FW_WM(tmp
, SPRITEF_HI
) << 8;
3879 wm
->pipe
[PIPE_C
].sprite
[0] |= _FW_WM(tmp
, SPRITEE_HI
) << 8;
3880 wm
->pipe
[PIPE_C
].primary
|= _FW_WM(tmp
, PLANEC_HI
) << 8;
3881 wm
->pipe
[PIPE_B
].sprite
[1] |= _FW_WM(tmp
, SPRITED_HI
) << 8;
3882 wm
->pipe
[PIPE_B
].sprite
[0] |= _FW_WM(tmp
, SPRITEC_HI
) << 8;
3883 wm
->pipe
[PIPE_B
].primary
|= _FW_WM(tmp
, PLANEB_HI
) << 8;
3884 wm
->pipe
[PIPE_A
].sprite
[1] |= _FW_WM(tmp
, SPRITEB_HI
) << 8;
3885 wm
->pipe
[PIPE_A
].sprite
[0] |= _FW_WM(tmp
, SPRITEA_HI
) << 8;
3886 wm
->pipe
[PIPE_A
].primary
|= _FW_WM(tmp
, PLANEA_HI
) << 8;
3888 tmp
= I915_READ(DSPFW7
);
3889 wm
->pipe
[PIPE_B
].sprite
[1] = _FW_WM_VLV(tmp
, SPRITED
);
3890 wm
->pipe
[PIPE_B
].sprite
[0] = _FW_WM_VLV(tmp
, SPRITEC
);
3892 tmp
= I915_READ(DSPHOWM
);
3893 wm
->sr
.plane
|= _FW_WM(tmp
, SR_HI
) << 9;
3894 wm
->pipe
[PIPE_B
].sprite
[1] |= _FW_WM(tmp
, SPRITED_HI
) << 8;
3895 wm
->pipe
[PIPE_B
].sprite
[0] |= _FW_WM(tmp
, SPRITEC_HI
) << 8;
3896 wm
->pipe
[PIPE_B
].primary
|= _FW_WM(tmp
, PLANEB_HI
) << 8;
3897 wm
->pipe
[PIPE_A
].sprite
[1] |= _FW_WM(tmp
, SPRITEB_HI
) << 8;
3898 wm
->pipe
[PIPE_A
].sprite
[0] |= _FW_WM(tmp
, SPRITEA_HI
) << 8;
3899 wm
->pipe
[PIPE_A
].primary
|= _FW_WM(tmp
, PLANEA_HI
) << 8;
3906 void vlv_wm_get_hw_state(struct drm_device
*dev
)
3908 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3909 struct vlv_wm_values
*wm
= &dev_priv
->wm
.vlv
;
3910 struct intel_plane
*plane
;
3914 vlv_read_wm_values(dev_priv
, wm
);
3916 for_each_intel_plane(dev
, plane
) {
3917 switch (plane
->base
.type
) {
3919 case DRM_PLANE_TYPE_CURSOR
:
3920 plane
->wm
.fifo_size
= 63;
3922 case DRM_PLANE_TYPE_PRIMARY
:
3923 plane
->wm
.fifo_size
= vlv_get_fifo_size(dev
, plane
->pipe
, 0);
3925 case DRM_PLANE_TYPE_OVERLAY
:
3926 sprite
= plane
->plane
;
3927 plane
->wm
.fifo_size
= vlv_get_fifo_size(dev
, plane
->pipe
, sprite
+ 1);
3932 wm
->cxsr
= I915_READ(FW_BLC_SELF_VLV
) & FW_CSPWRDWNEN
;
3933 wm
->level
= VLV_WM_LEVEL_PM2
;
3935 if (IS_CHERRYVIEW(dev_priv
)) {
3936 mutex_lock(&dev_priv
->rps
.hw_lock
);
3938 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
3939 if (val
& DSP_MAXFIFO_PM5_ENABLE
)
3940 wm
->level
= VLV_WM_LEVEL_PM5
;
3943 * If DDR DVFS is disabled in the BIOS, Punit
3944 * will never ack the request. So if that happens
3945 * assume we don't have to enable/disable DDR DVFS
3946 * dynamically. To test that just set the REQ_ACK
3947 * bit to poke the Punit, but don't change the
3948 * HIGH/LOW bits so that we don't actually change
3949 * the current state.
3951 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DDR_SETUP2
);
3952 val
|= FORCE_DDR_FREQ_REQ_ACK
;
3953 vlv_punit_write(dev_priv
, PUNIT_REG_DDR_SETUP2
, val
);
3955 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DDR_SETUP2
) &
3956 FORCE_DDR_FREQ_REQ_ACK
) == 0, 3)) {
3957 DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
3958 "assuming DDR DVFS is disabled\n");
3959 dev_priv
->wm
.max_level
= VLV_WM_LEVEL_PM5
;
3961 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DDR_SETUP2
);
3962 if ((val
& FORCE_DDR_HIGH_FREQ
) == 0)
3963 wm
->level
= VLV_WM_LEVEL_DDR_DVFS
;
3966 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3969 for_each_pipe(dev_priv
, pipe
)
3970 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
3971 pipe_name(pipe
), wm
->pipe
[pipe
].primary
, wm
->pipe
[pipe
].cursor
,
3972 wm
->pipe
[pipe
].sprite
[0], wm
->pipe
[pipe
].sprite
[1]);
3974 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
3975 wm
->sr
.plane
, wm
->sr
.cursor
, wm
->level
, wm
->cxsr
);
3978 void ilk_wm_get_hw_state(struct drm_device
*dev
)
3980 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3981 struct ilk_wm_values
*hw
= &dev_priv
->wm
.hw
;
3982 struct drm_crtc
*crtc
;
3984 for_each_crtc(dev
, crtc
)
3985 ilk_pipe_wm_get_hw_state(crtc
);
3987 hw
->wm_lp
[0] = I915_READ(WM1_LP_ILK
);
3988 hw
->wm_lp
[1] = I915_READ(WM2_LP_ILK
);
3989 hw
->wm_lp
[2] = I915_READ(WM3_LP_ILK
);
3991 hw
->wm_lp_spr
[0] = I915_READ(WM1S_LP_ILK
);
3992 if (INTEL_INFO(dev
)->gen
>= 7) {
3993 hw
->wm_lp_spr
[1] = I915_READ(WM2S_LP_IVB
);
3994 hw
->wm_lp_spr
[2] = I915_READ(WM3S_LP_IVB
);
3997 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
3998 hw
->partitioning
= (I915_READ(WM_MISC
) & WM_MISC_DATA_PARTITION_5_6
) ?
3999 INTEL_DDB_PART_5_6
: INTEL_DDB_PART_1_2
;
4000 else if (IS_IVYBRIDGE(dev
))
4001 hw
->partitioning
= (I915_READ(DISP_ARB_CTL2
) & DISP_DATA_PARTITION_5_6
) ?
4002 INTEL_DDB_PART_5_6
: INTEL_DDB_PART_1_2
;
4005 !(I915_READ(DISP_ARB_CTL
) & DISP_FBC_WM_DIS
);
4009 * intel_update_watermarks - update FIFO watermark values based on current modes
4011 * Calculate watermark values for the various WM regs based on current mode
4012 * and plane configuration.
4014 * There are several cases to deal with here:
4015 * - normal (i.e. non-self-refresh)
4016 * - self-refresh (SR) mode
4017 * - lines are large relative to FIFO size (buffer can hold up to 2)
4018 * - lines are small relative to FIFO size (buffer can hold more than 2
4019 * lines), so need to account for TLB latency
4021 * The normal calculation is:
4022 * watermark = dotclock * bytes per pixel * latency
4023 * where latency is platform & configuration dependent (we assume pessimal
4026 * The SR calculation is:
4027 * watermark = (trunc(latency/line time)+1) * surface width *
4030 * line time = htotal / dotclock
4031 * surface width = hdisplay for normal plane and 64 for cursor
4032 * and latency is assumed to be high, as above.
4034 * The final value programmed to the register should always be rounded up,
4035 * and include an extra 2 entries to account for clock crossings.
4037 * We don't use the sprite, so we can ignore that. And on Crestline we have
4038 * to set the non-SR watermarks to 8.
4040 void intel_update_watermarks(struct drm_crtc
*crtc
)
4042 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
4044 if (dev_priv
->display
.update_wm
)
4045 dev_priv
->display
.update_wm(crtc
);
4049 * Lock protecting IPS related data structures
4051 DEFINE_SPINLOCK(mchdev_lock
);
4053 /* Global for IPS driver to get at the current i915 device. Protected by
4055 static struct drm_i915_private
*i915_mch_dev
;
4057 bool ironlake_set_drps(struct drm_device
*dev
, u8 val
)
4059 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4062 assert_spin_locked(&mchdev_lock
);
4064 rgvswctl
= I915_READ16(MEMSWCTL
);
4065 if (rgvswctl
& MEMCTL_CMD_STS
) {
4066 DRM_DEBUG("gpu busy, RCS change rejected\n");
4067 return false; /* still busy with another command */
4070 rgvswctl
= (MEMCTL_CMD_CHFREQ
<< MEMCTL_CMD_SHIFT
) |
4071 (val
<< MEMCTL_FREQ_SHIFT
) | MEMCTL_SFCAVM
;
4072 I915_WRITE16(MEMSWCTL
, rgvswctl
);
4073 POSTING_READ16(MEMSWCTL
);
4075 rgvswctl
|= MEMCTL_CMD_STS
;
4076 I915_WRITE16(MEMSWCTL
, rgvswctl
);
4081 static void ironlake_enable_drps(struct drm_device
*dev
)
4083 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4084 u32 rgvmodectl
= I915_READ(MEMMODECTL
);
4085 u8 fmax
, fmin
, fstart
, vstart
;
4087 spin_lock_irq(&mchdev_lock
);
4089 /* Enable temp reporting */
4090 I915_WRITE16(PMMISC
, I915_READ(PMMISC
) | MCPPCE_EN
);
4091 I915_WRITE16(TSC1
, I915_READ(TSC1
) | TSE
);
4093 /* 100ms RC evaluation intervals */
4094 I915_WRITE(RCUPEI
, 100000);
4095 I915_WRITE(RCDNEI
, 100000);
4097 /* Set max/min thresholds to 90ms and 80ms respectively */
4098 I915_WRITE(RCBMAXAVG
, 90000);
4099 I915_WRITE(RCBMINAVG
, 80000);
4101 I915_WRITE(MEMIHYST
, 1);
4103 /* Set up min, max, and cur for interrupt handling */
4104 fmax
= (rgvmodectl
& MEMMODE_FMAX_MASK
) >> MEMMODE_FMAX_SHIFT
;
4105 fmin
= (rgvmodectl
& MEMMODE_FMIN_MASK
);
4106 fstart
= (rgvmodectl
& MEMMODE_FSTART_MASK
) >>
4107 MEMMODE_FSTART_SHIFT
;
4109 vstart
= (I915_READ(PXVFREQ(fstart
)) & PXVFREQ_PX_MASK
) >>
4112 dev_priv
->ips
.fmax
= fmax
; /* IPS callback will increase this */
4113 dev_priv
->ips
.fstart
= fstart
;
4115 dev_priv
->ips
.max_delay
= fstart
;
4116 dev_priv
->ips
.min_delay
= fmin
;
4117 dev_priv
->ips
.cur_delay
= fstart
;
4119 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4120 fmax
, fmin
, fstart
);
4122 I915_WRITE(MEMINTREN
, MEMINT_CX_SUPR_EN
| MEMINT_EVAL_CHG_EN
);
4125 * Interrupts will be enabled in ironlake_irq_postinstall
4128 I915_WRITE(VIDSTART
, vstart
);
4129 POSTING_READ(VIDSTART
);
4131 rgvmodectl
|= MEMMODE_SWMODE_EN
;
4132 I915_WRITE(MEMMODECTL
, rgvmodectl
);
4134 if (wait_for_atomic((I915_READ(MEMSWCTL
) & MEMCTL_CMD_STS
) == 0, 10))
4135 DRM_ERROR("stuck trying to change perf mode\n");
4138 ironlake_set_drps(dev
, fstart
);
4140 dev_priv
->ips
.last_count1
= I915_READ(DMIEC
) +
4141 I915_READ(DDREC
) + I915_READ(CSIEC
);
4142 dev_priv
->ips
.last_time1
= jiffies_to_msecs(jiffies
);
4143 dev_priv
->ips
.last_count2
= I915_READ(GFXEC
);
4144 dev_priv
->ips
.last_time2
= ktime_get_raw_ns();
4146 spin_unlock_irq(&mchdev_lock
);
4149 static void ironlake_disable_drps(struct drm_device
*dev
)
4151 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4154 spin_lock_irq(&mchdev_lock
);
4156 rgvswctl
= I915_READ16(MEMSWCTL
);
4158 /* Ack interrupts, disable EFC interrupt */
4159 I915_WRITE(MEMINTREN
, I915_READ(MEMINTREN
) & ~MEMINT_EVAL_CHG_EN
);
4160 I915_WRITE(MEMINTRSTS
, MEMINT_EVAL_CHG
);
4161 I915_WRITE(DEIER
, I915_READ(DEIER
) & ~DE_PCU_EVENT
);
4162 I915_WRITE(DEIIR
, DE_PCU_EVENT
);
4163 I915_WRITE(DEIMR
, I915_READ(DEIMR
) | DE_PCU_EVENT
);
4165 /* Go back to the starting frequency */
4166 ironlake_set_drps(dev
, dev_priv
->ips
.fstart
);
4168 rgvswctl
|= MEMCTL_CMD_STS
;
4169 I915_WRITE(MEMSWCTL
, rgvswctl
);
4172 spin_unlock_irq(&mchdev_lock
);
4175 /* There's a funny hw issue where the hw returns all 0 when reading from
4176 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4177 * ourselves, instead of doing a rmw cycle (which might result in us clearing
4178 * all limits and the gpu stuck at whatever frequency it is at atm).
4180 static u32
intel_rps_limits(struct drm_i915_private
*dev_priv
, u8 val
)
4184 /* Only set the down limit when we've reached the lowest level to avoid
4185 * getting more interrupts, otherwise leave this clear. This prevents a
4186 * race in the hw when coming out of rc6: There's a tiny window where
4187 * the hw runs at the minimal clock before selecting the desired
4188 * frequency, if the down threshold expires in that window we will not
4189 * receive a down interrupt. */
4190 if (IS_GEN9(dev_priv
->dev
)) {
4191 limits
= (dev_priv
->rps
.max_freq_softlimit
) << 23;
4192 if (val
<= dev_priv
->rps
.min_freq_softlimit
)
4193 limits
|= (dev_priv
->rps
.min_freq_softlimit
) << 14;
4195 limits
= dev_priv
->rps
.max_freq_softlimit
<< 24;
4196 if (val
<= dev_priv
->rps
.min_freq_softlimit
)
4197 limits
|= dev_priv
->rps
.min_freq_softlimit
<< 16;
4203 static void gen6_set_rps_thresholds(struct drm_i915_private
*dev_priv
, u8 val
)
4206 u32 threshold_up
= 0, threshold_down
= 0; /* in % */
4207 u32 ei_up
= 0, ei_down
= 0;
4209 new_power
= dev_priv
->rps
.power
;
4210 switch (dev_priv
->rps
.power
) {
4212 if (val
> dev_priv
->rps
.efficient_freq
+ 1 && val
> dev_priv
->rps
.cur_freq
)
4213 new_power
= BETWEEN
;
4217 if (val
<= dev_priv
->rps
.efficient_freq
&& val
< dev_priv
->rps
.cur_freq
)
4218 new_power
= LOW_POWER
;
4219 else if (val
>= dev_priv
->rps
.rp0_freq
&& val
> dev_priv
->rps
.cur_freq
)
4220 new_power
= HIGH_POWER
;
4224 if (val
< (dev_priv
->rps
.rp1_freq
+ dev_priv
->rps
.rp0_freq
) >> 1 && val
< dev_priv
->rps
.cur_freq
)
4225 new_power
= BETWEEN
;
4228 /* Max/min bins are special */
4229 if (val
<= dev_priv
->rps
.min_freq_softlimit
)
4230 new_power
= LOW_POWER
;
4231 if (val
>= dev_priv
->rps
.max_freq_softlimit
)
4232 new_power
= HIGH_POWER
;
4233 if (new_power
== dev_priv
->rps
.power
)
4236 /* Note the units here are not exactly 1us, but 1280ns. */
4237 switch (new_power
) {
4239 /* Upclock if more than 95% busy over 16ms */
4243 /* Downclock if less than 85% busy over 32ms */
4245 threshold_down
= 85;
4249 /* Upclock if more than 90% busy over 13ms */
4253 /* Downclock if less than 75% busy over 32ms */
4255 threshold_down
= 75;
4259 /* Upclock if more than 85% busy over 10ms */
4263 /* Downclock if less than 60% busy over 32ms */
4265 threshold_down
= 60;
4269 I915_WRITE(GEN6_RP_UP_EI
,
4270 GT_INTERVAL_FROM_US(dev_priv
, ei_up
));
4271 I915_WRITE(GEN6_RP_UP_THRESHOLD
,
4272 GT_INTERVAL_FROM_US(dev_priv
, (ei_up
* threshold_up
/ 100)));
4274 I915_WRITE(GEN6_RP_DOWN_EI
,
4275 GT_INTERVAL_FROM_US(dev_priv
, ei_down
));
4276 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
,
4277 GT_INTERVAL_FROM_US(dev_priv
, (ei_down
* threshold_down
/ 100)));
4279 I915_WRITE(GEN6_RP_CONTROL
,
4280 GEN6_RP_MEDIA_TURBO
|
4281 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
4282 GEN6_RP_MEDIA_IS_GFX
|
4284 GEN6_RP_UP_BUSY_AVG
|
4285 GEN6_RP_DOWN_IDLE_AVG
);
4287 dev_priv
->rps
.power
= new_power
;
4288 dev_priv
->rps
.up_threshold
= threshold_up
;
4289 dev_priv
->rps
.down_threshold
= threshold_down
;
4290 dev_priv
->rps
.last_adj
= 0;
4293 static u32
gen6_rps_pm_mask(struct drm_i915_private
*dev_priv
, u8 val
)
4297 if (val
> dev_priv
->rps
.min_freq_softlimit
)
4298 mask
|= GEN6_PM_RP_DOWN_EI_EXPIRED
| GEN6_PM_RP_DOWN_THRESHOLD
| GEN6_PM_RP_DOWN_TIMEOUT
;
4299 if (val
< dev_priv
->rps
.max_freq_softlimit
)
4300 mask
|= GEN6_PM_RP_UP_EI_EXPIRED
| GEN6_PM_RP_UP_THRESHOLD
;
4302 mask
&= dev_priv
->pm_rps_events
;
4304 return gen6_sanitize_rps_pm_mask(dev_priv
, ~mask
);
4307 /* gen6_set_rps is called to update the frequency request, but should also be
4308 * called when the range (min_delay and max_delay) is modified so that we can
4309 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
4310 static void gen6_set_rps(struct drm_device
*dev
, u8 val
)
4312 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4314 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4315 if (IS_BXT_REVID(dev
, 0, BXT_REVID_A1
))
4318 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
4319 WARN_ON(val
> dev_priv
->rps
.max_freq
);
4320 WARN_ON(val
< dev_priv
->rps
.min_freq
);
4322 /* min/max delay may still have been modified so be sure to
4323 * write the limits value.
4325 if (val
!= dev_priv
->rps
.cur_freq
) {
4326 gen6_set_rps_thresholds(dev_priv
, val
);
4329 I915_WRITE(GEN6_RPNSWREQ
,
4330 GEN9_FREQUENCY(val
));
4331 else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
4332 I915_WRITE(GEN6_RPNSWREQ
,
4333 HSW_FREQUENCY(val
));
4335 I915_WRITE(GEN6_RPNSWREQ
,
4336 GEN6_FREQUENCY(val
) |
4338 GEN6_AGGRESSIVE_TURBO
);
4341 /* Make sure we continue to get interrupts
4342 * until we hit the minimum or maximum frequencies.
4344 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS
, intel_rps_limits(dev_priv
, val
));
4345 I915_WRITE(GEN6_PMINTRMSK
, gen6_rps_pm_mask(dev_priv
, val
));
4347 POSTING_READ(GEN6_RPNSWREQ
);
4349 dev_priv
->rps
.cur_freq
= val
;
4350 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv
, val
));
4353 static void valleyview_set_rps(struct drm_device
*dev
, u8 val
)
4355 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4357 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
4358 WARN_ON(val
> dev_priv
->rps
.max_freq
);
4359 WARN_ON(val
< dev_priv
->rps
.min_freq
);
4361 if (WARN_ONCE(IS_CHERRYVIEW(dev
) && (val
& 1),
4362 "Odd GPU freq value\n"))
4365 I915_WRITE(GEN6_PMINTRMSK
, gen6_rps_pm_mask(dev_priv
, val
));
4367 if (val
!= dev_priv
->rps
.cur_freq
) {
4368 vlv_punit_write(dev_priv
, PUNIT_REG_GPU_FREQ_REQ
, val
);
4369 if (!IS_CHERRYVIEW(dev_priv
))
4370 gen6_set_rps_thresholds(dev_priv
, val
);
4373 dev_priv
->rps
.cur_freq
= val
;
4374 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv
, val
));
4377 /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
4379 * * If Gfx is Idle, then
4380 * 1. Forcewake Media well.
4381 * 2. Request idle freq.
4382 * 3. Release Forcewake of Media well.
4384 static void vlv_set_rps_idle(struct drm_i915_private
*dev_priv
)
4386 u32 val
= dev_priv
->rps
.idle_freq
;
4388 if (dev_priv
->rps
.cur_freq
<= val
)
4391 /* Wake up the media well, as that takes a lot less
4392 * power than the Render well. */
4393 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_MEDIA
);
4394 valleyview_set_rps(dev_priv
->dev
, val
);
4395 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_MEDIA
);
4398 void gen6_rps_busy(struct drm_i915_private
*dev_priv
)
4400 mutex_lock(&dev_priv
->rps
.hw_lock
);
4401 if (dev_priv
->rps
.enabled
) {
4402 if (dev_priv
->pm_rps_events
& (GEN6_PM_RP_DOWN_EI_EXPIRED
| GEN6_PM_RP_UP_EI_EXPIRED
))
4403 gen6_rps_reset_ei(dev_priv
);
4404 I915_WRITE(GEN6_PMINTRMSK
,
4405 gen6_rps_pm_mask(dev_priv
, dev_priv
->rps
.cur_freq
));
4407 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4410 void gen6_rps_idle(struct drm_i915_private
*dev_priv
)
4412 struct drm_device
*dev
= dev_priv
->dev
;
4414 mutex_lock(&dev_priv
->rps
.hw_lock
);
4415 if (dev_priv
->rps
.enabled
) {
4416 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
4417 vlv_set_rps_idle(dev_priv
);
4419 gen6_set_rps(dev_priv
->dev
, dev_priv
->rps
.idle_freq
);
4420 dev_priv
->rps
.last_adj
= 0;
4421 I915_WRITE(GEN6_PMINTRMSK
, 0xffffffff);
4423 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4425 spin_lock(&dev_priv
->rps
.client_lock
);
4426 while (!list_empty(&dev_priv
->rps
.clients
))
4427 list_del_init(dev_priv
->rps
.clients
.next
);
4428 spin_unlock(&dev_priv
->rps
.client_lock
);
4431 void gen6_rps_boost(struct drm_i915_private
*dev_priv
,
4432 struct intel_rps_client
*rps
,
4433 unsigned long submitted
)
4435 /* This is intentionally racy! We peek at the state here, then
4436 * validate inside the RPS worker.
4438 if (!(dev_priv
->mm
.busy
&&
4439 dev_priv
->rps
.enabled
&&
4440 dev_priv
->rps
.cur_freq
< dev_priv
->rps
.max_freq_softlimit
))
4443 /* Force a RPS boost (and don't count it against the client) if
4444 * the GPU is severely congested.
4446 if (rps
&& time_after(jiffies
, submitted
+ DRM_I915_THROTTLE_JIFFIES
))
4449 spin_lock(&dev_priv
->rps
.client_lock
);
4450 if (rps
== NULL
|| list_empty(&rps
->link
)) {
4451 spin_lock_irq(&dev_priv
->irq_lock
);
4452 if (dev_priv
->rps
.interrupts_enabled
) {
4453 dev_priv
->rps
.client_boost
= true;
4454 queue_work(dev_priv
->wq
, &dev_priv
->rps
.work
);
4456 spin_unlock_irq(&dev_priv
->irq_lock
);
4459 list_add(&rps
->link
, &dev_priv
->rps
.clients
);
4462 dev_priv
->rps
.boosts
++;
4464 spin_unlock(&dev_priv
->rps
.client_lock
);
4467 void intel_set_rps(struct drm_device
*dev
, u8 val
)
4469 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
4470 valleyview_set_rps(dev
, val
);
4472 gen6_set_rps(dev
, val
);
4475 static void gen9_disable_rps(struct drm_device
*dev
)
4477 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4479 I915_WRITE(GEN6_RC_CONTROL
, 0);
4480 I915_WRITE(GEN9_PG_ENABLE
, 0);
4483 static void gen6_disable_rps(struct drm_device
*dev
)
4485 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4487 I915_WRITE(GEN6_RC_CONTROL
, 0);
4488 I915_WRITE(GEN6_RPNSWREQ
, 1 << 31);
4491 static void cherryview_disable_rps(struct drm_device
*dev
)
4493 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4495 I915_WRITE(GEN6_RC_CONTROL
, 0);
4498 static void valleyview_disable_rps(struct drm_device
*dev
)
4500 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4502 /* we're doing forcewake before Disabling RC6,
4503 * This what the BIOS expects when going into suspend */
4504 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
4506 I915_WRITE(GEN6_RC_CONTROL
, 0);
4508 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
4511 static void intel_print_rc6_info(struct drm_device
*dev
, u32 mode
)
4513 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
4514 if (mode
& (GEN7_RC_CTL_TO_MODE
| GEN6_RC_CTL_EI_MODE(1)))
4515 mode
= GEN6_RC_CTL_RC6_ENABLE
;
4520 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
4521 (mode
& GEN6_RC_CTL_RC6_ENABLE
) ? "on" : "off",
4522 (mode
& GEN6_RC_CTL_RC6p_ENABLE
) ? "on" : "off",
4523 (mode
& GEN6_RC_CTL_RC6pp_ENABLE
) ? "on" : "off");
4526 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
4527 (mode
& GEN6_RC_CTL_RC6_ENABLE
) ? "on" : "off");
4530 static int sanitize_rc6_option(const struct drm_device
*dev
, int enable_rc6
)
4532 /* No RC6 before Ironlake and code is gone for ilk. */
4533 if (INTEL_INFO(dev
)->gen
< 6)
4536 /* Respect the kernel parameter if it is set */
4537 if (enable_rc6
>= 0) {
4541 mask
= INTEL_RC6_ENABLE
| INTEL_RC6p_ENABLE
|
4544 mask
= INTEL_RC6_ENABLE
;
4546 if ((enable_rc6
& mask
) != enable_rc6
)
4547 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
4548 enable_rc6
& mask
, enable_rc6
, mask
);
4550 return enable_rc6
& mask
;
4553 if (IS_IVYBRIDGE(dev
))
4554 return (INTEL_RC6_ENABLE
| INTEL_RC6p_ENABLE
);
4556 return INTEL_RC6_ENABLE
;
4559 int intel_enable_rc6(const struct drm_device
*dev
)
4561 return i915
.enable_rc6
;
4564 static void gen6_init_rps_frequencies(struct drm_device
*dev
)
4566 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4567 uint32_t rp_state_cap
;
4568 u32 ddcc_status
= 0;
4571 /* All of these values are in units of 50MHz */
4572 dev_priv
->rps
.cur_freq
= 0;
4573 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
4574 if (IS_BROXTON(dev
)) {
4575 rp_state_cap
= I915_READ(BXT_RP_STATE_CAP
);
4576 dev_priv
->rps
.rp0_freq
= (rp_state_cap
>> 16) & 0xff;
4577 dev_priv
->rps
.rp1_freq
= (rp_state_cap
>> 8) & 0xff;
4578 dev_priv
->rps
.min_freq
= (rp_state_cap
>> 0) & 0xff;
4580 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
4581 dev_priv
->rps
.rp0_freq
= (rp_state_cap
>> 0) & 0xff;
4582 dev_priv
->rps
.rp1_freq
= (rp_state_cap
>> 8) & 0xff;
4583 dev_priv
->rps
.min_freq
= (rp_state_cap
>> 16) & 0xff;
4586 /* hw_max = RP0 until we check for overclocking */
4587 dev_priv
->rps
.max_freq
= dev_priv
->rps
.rp0_freq
;
4589 dev_priv
->rps
.efficient_freq
= dev_priv
->rps
.rp1_freq
;
4590 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
) ||
4591 IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
)) {
4592 ret
= sandybridge_pcode_read(dev_priv
,
4593 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL
,
4596 dev_priv
->rps
.efficient_freq
=
4598 ((ddcc_status
>> 8) & 0xff),
4599 dev_priv
->rps
.min_freq
,
4600 dev_priv
->rps
.max_freq
);
4603 if (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
)) {
4604 /* Store the frequency values in 16.66 MHZ units, which is
4605 the natural hardware unit for SKL */
4606 dev_priv
->rps
.rp0_freq
*= GEN9_FREQ_SCALER
;
4607 dev_priv
->rps
.rp1_freq
*= GEN9_FREQ_SCALER
;
4608 dev_priv
->rps
.min_freq
*= GEN9_FREQ_SCALER
;
4609 dev_priv
->rps
.max_freq
*= GEN9_FREQ_SCALER
;
4610 dev_priv
->rps
.efficient_freq
*= GEN9_FREQ_SCALER
;
4613 dev_priv
->rps
.idle_freq
= dev_priv
->rps
.min_freq
;
4615 /* Preserve min/max settings in case of re-init */
4616 if (dev_priv
->rps
.max_freq_softlimit
== 0)
4617 dev_priv
->rps
.max_freq_softlimit
= dev_priv
->rps
.max_freq
;
4619 if (dev_priv
->rps
.min_freq_softlimit
== 0) {
4620 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
4621 dev_priv
->rps
.min_freq_softlimit
=
4622 max_t(int, dev_priv
->rps
.efficient_freq
,
4623 intel_freq_opcode(dev_priv
, 450));
4625 dev_priv
->rps
.min_freq_softlimit
=
4626 dev_priv
->rps
.min_freq
;
4630 /* See the Gen9_GT_PM_Programming_Guide doc for the below */
4631 static void gen9_enable_rps(struct drm_device
*dev
)
4633 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4635 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
4637 gen6_init_rps_frequencies(dev
);
4639 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4640 if (IS_BXT_REVID(dev
, 0, BXT_REVID_A1
)) {
4641 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
4645 /* Program defaults and thresholds for RPS*/
4646 I915_WRITE(GEN6_RC_VIDEO_FREQ
,
4647 GEN9_FREQUENCY(dev_priv
->rps
.rp1_freq
));
4649 /* 1 second timeout*/
4650 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
,
4651 GT_INTERVAL_FROM_US(dev_priv
, 1000000));
4653 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 0xa);
4655 /* Leaning on the below call to gen6_set_rps to program/setup the
4656 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
4657 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
4658 dev_priv
->rps
.power
= HIGH_POWER
; /* force a reset */
4659 gen6_set_rps(dev_priv
->dev
, dev_priv
->rps
.min_freq_softlimit
);
4661 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
4664 static void gen9_enable_rc6(struct drm_device
*dev
)
4666 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4667 struct intel_engine_cs
*ring
;
4668 uint32_t rc6_mask
= 0;
4671 /* 1a: Software RC state - RC0 */
4672 I915_WRITE(GEN6_RC_STATE
, 0);
4674 /* 1b: Get forcewake during program sequence. Although the driver
4675 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4676 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
4678 /* 2a: Disable RC states. */
4679 I915_WRITE(GEN6_RC_CONTROL
, 0);
4681 /* 2b: Program RC6 thresholds.*/
4683 /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
4684 if (IS_SKYLAKE(dev
))
4685 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 108 << 16);
4687 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 54 << 16);
4688 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000); /* 12500 * 1280ns */
4689 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25); /* 25 * 1280ns */
4690 for_each_ring(ring
, dev_priv
, unused
)
4691 I915_WRITE(RING_MAX_IDLE(ring
->mmio_base
), 10);
4693 if (HAS_GUC_UCODE(dev
))
4694 I915_WRITE(GUC_MAX_IDLE_COUNT
, 0xA);
4696 I915_WRITE(GEN6_RC_SLEEP
, 0);
4698 /* 2c: Program Coarse Power Gating Policies. */
4699 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS
, 25);
4700 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS
, 25);
4702 /* 3a: Enable RC6 */
4703 if (intel_enable_rc6(dev
) & INTEL_RC6_ENABLE
)
4704 rc6_mask
= GEN6_RC_CTL_RC6_ENABLE
;
4705 DRM_INFO("RC6 %s\n", (rc6_mask
& GEN6_RC_CTL_RC6_ENABLE
) ?
4707 /* WaRsUseTimeoutMode */
4708 if (IS_SKL_REVID(dev
, 0, SKL_REVID_D0
) ||
4709 IS_BXT_REVID(dev
, 0, BXT_REVID_A1
)) {
4710 I915_WRITE(GEN6_RC6_THRESHOLD
, 625); /* 800us */
4711 I915_WRITE(GEN6_RC_CONTROL
, GEN6_RC_CTL_HW_ENABLE
|
4712 GEN7_RC_CTL_TO_MODE
|
4715 I915_WRITE(GEN6_RC6_THRESHOLD
, 37500); /* 37.5/125ms per EI */
4716 I915_WRITE(GEN6_RC_CONTROL
, GEN6_RC_CTL_HW_ENABLE
|
4717 GEN6_RC_CTL_EI_MODE(1) |
4722 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
4723 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
4725 if ((IS_BROXTON(dev
) && (INTEL_REVID(dev
) < BXT_REVID_B0
)) ||
4726 ((IS_SKL_GT3(dev
) || IS_SKL_GT4(dev
)) && (INTEL_REVID(dev
) <= SKL_REVID_F0
)))
4727 I915_WRITE(GEN9_PG_ENABLE
, 0);
4729 I915_WRITE(GEN9_PG_ENABLE
, (rc6_mask
& GEN6_RC_CTL_RC6_ENABLE
) ?
4730 (GEN9_RENDER_PG_ENABLE
| GEN9_MEDIA_PG_ENABLE
) : 0);
4732 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
4736 static void gen8_enable_rps(struct drm_device
*dev
)
4738 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4739 struct intel_engine_cs
*ring
;
4740 uint32_t rc6_mask
= 0;
4743 /* 1a: Software RC state - RC0 */
4744 I915_WRITE(GEN6_RC_STATE
, 0);
4746 /* 1c & 1d: Get forcewake during program sequence. Although the driver
4747 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4748 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
4750 /* 2a: Disable RC states. */
4751 I915_WRITE(GEN6_RC_CONTROL
, 0);
4753 /* Initialize rps frequencies */
4754 gen6_init_rps_frequencies(dev
);
4756 /* 2b: Program RC6 thresholds.*/
4757 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 40 << 16);
4758 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000); /* 12500 * 1280ns */
4759 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25); /* 25 * 1280ns */
4760 for_each_ring(ring
, dev_priv
, unused
)
4761 I915_WRITE(RING_MAX_IDLE(ring
->mmio_base
), 10);
4762 I915_WRITE(GEN6_RC_SLEEP
, 0);
4763 if (IS_BROADWELL(dev
))
4764 I915_WRITE(GEN6_RC6_THRESHOLD
, 625); /* 800us/1.28 for TO */
4766 I915_WRITE(GEN6_RC6_THRESHOLD
, 50000); /* 50/125ms per EI */
4769 if (intel_enable_rc6(dev
) & INTEL_RC6_ENABLE
)
4770 rc6_mask
= GEN6_RC_CTL_RC6_ENABLE
;
4771 intel_print_rc6_info(dev
, rc6_mask
);
4772 if (IS_BROADWELL(dev
))
4773 I915_WRITE(GEN6_RC_CONTROL
, GEN6_RC_CTL_HW_ENABLE
|
4774 GEN7_RC_CTL_TO_MODE
|
4777 I915_WRITE(GEN6_RC_CONTROL
, GEN6_RC_CTL_HW_ENABLE
|
4778 GEN6_RC_CTL_EI_MODE(1) |
4781 /* 4 Program defaults and thresholds for RPS*/
4782 I915_WRITE(GEN6_RPNSWREQ
,
4783 HSW_FREQUENCY(dev_priv
->rps
.rp1_freq
));
4784 I915_WRITE(GEN6_RC_VIDEO_FREQ
,
4785 HSW_FREQUENCY(dev_priv
->rps
.rp1_freq
));
4786 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
4787 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 100000000 / 128); /* 1 second timeout */
4789 /* Docs recommend 900MHz, and 300 MHz respectively */
4790 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS
,
4791 dev_priv
->rps
.max_freq_softlimit
<< 24 |
4792 dev_priv
->rps
.min_freq_softlimit
<< 16);
4794 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 7600000 / 128); /* 76ms busyness per EI, 90% */
4795 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 31300000 / 128); /* 313ms busyness per EI, 70%*/
4796 I915_WRITE(GEN6_RP_UP_EI
, 66000); /* 84.48ms, XXX: random? */
4797 I915_WRITE(GEN6_RP_DOWN_EI
, 350000); /* 448ms, XXX: random? */
4799 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
4802 I915_WRITE(GEN6_RP_CONTROL
,
4803 GEN6_RP_MEDIA_TURBO
|
4804 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
4805 GEN6_RP_MEDIA_IS_GFX
|
4807 GEN6_RP_UP_BUSY_AVG
|
4808 GEN6_RP_DOWN_IDLE_AVG
);
4810 /* 6: Ring frequency + overclocking (our driver does this later */
4812 dev_priv
->rps
.power
= HIGH_POWER
; /* force a reset */
4813 gen6_set_rps(dev_priv
->dev
, dev_priv
->rps
.idle_freq
);
4815 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
4818 static void gen6_enable_rps(struct drm_device
*dev
)
4820 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4821 struct intel_engine_cs
*ring
;
4822 u32 rc6vids
, pcu_mbox
= 0, rc6_mask
= 0;
4827 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
4829 /* Here begins a magic sequence of register writes to enable
4830 * auto-downclocking.
4832 * Perhaps there might be some value in exposing these to
4835 I915_WRITE(GEN6_RC_STATE
, 0);
4837 /* Clear the DBG now so we don't confuse earlier errors */
4838 if ((gtfifodbg
= I915_READ(GTFIFODBG
))) {
4839 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg
);
4840 I915_WRITE(GTFIFODBG
, gtfifodbg
);
4843 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
4845 /* Initialize rps frequencies */
4846 gen6_init_rps_frequencies(dev
);
4848 /* disable the counters and set deterministic thresholds */
4849 I915_WRITE(GEN6_RC_CONTROL
, 0);
4851 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT
, 1000 << 16);
4852 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 40 << 16 | 30);
4853 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT
, 30);
4854 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000);
4855 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25);
4857 for_each_ring(ring
, dev_priv
, i
)
4858 I915_WRITE(RING_MAX_IDLE(ring
->mmio_base
), 10);
4860 I915_WRITE(GEN6_RC_SLEEP
, 0);
4861 I915_WRITE(GEN6_RC1e_THRESHOLD
, 1000);
4862 if (IS_IVYBRIDGE(dev
))
4863 I915_WRITE(GEN6_RC6_THRESHOLD
, 125000);
4865 I915_WRITE(GEN6_RC6_THRESHOLD
, 50000);
4866 I915_WRITE(GEN6_RC6p_THRESHOLD
, 150000);
4867 I915_WRITE(GEN6_RC6pp_THRESHOLD
, 64000); /* unused */
4869 /* Check if we are enabling RC6 */
4870 rc6_mode
= intel_enable_rc6(dev_priv
->dev
);
4871 if (rc6_mode
& INTEL_RC6_ENABLE
)
4872 rc6_mask
|= GEN6_RC_CTL_RC6_ENABLE
;
4874 /* We don't use those on Haswell */
4875 if (!IS_HASWELL(dev
)) {
4876 if (rc6_mode
& INTEL_RC6p_ENABLE
)
4877 rc6_mask
|= GEN6_RC_CTL_RC6p_ENABLE
;
4879 if (rc6_mode
& INTEL_RC6pp_ENABLE
)
4880 rc6_mask
|= GEN6_RC_CTL_RC6pp_ENABLE
;
4883 intel_print_rc6_info(dev
, rc6_mask
);
4885 I915_WRITE(GEN6_RC_CONTROL
,
4887 GEN6_RC_CTL_EI_MODE(1) |
4888 GEN6_RC_CTL_HW_ENABLE
);
4890 /* Power down if completely idle for over 50ms */
4891 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 50000);
4892 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
4894 ret
= sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_MIN_FREQ_TABLE
, 0);
4896 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
4898 ret
= sandybridge_pcode_read(dev_priv
, GEN6_READ_OC_PARAMS
, &pcu_mbox
);
4899 if (!ret
&& (pcu_mbox
& (1<<31))) { /* OC supported */
4900 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
4901 (dev_priv
->rps
.max_freq_softlimit
& 0xff) * 50,
4902 (pcu_mbox
& 0xff) * 50);
4903 dev_priv
->rps
.max_freq
= pcu_mbox
& 0xff;
4906 dev_priv
->rps
.power
= HIGH_POWER
; /* force a reset */
4907 gen6_set_rps(dev_priv
->dev
, dev_priv
->rps
.idle_freq
);
4910 ret
= sandybridge_pcode_read(dev_priv
, GEN6_PCODE_READ_RC6VIDS
, &rc6vids
);
4911 if (IS_GEN6(dev
) && ret
) {
4912 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
4913 } else if (IS_GEN6(dev
) && (GEN6_DECODE_RC6_VID(rc6vids
& 0xff) < 450)) {
4914 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
4915 GEN6_DECODE_RC6_VID(rc6vids
& 0xff), 450);
4916 rc6vids
&= 0xffff00;
4917 rc6vids
|= GEN6_ENCODE_RC6_VID(450);
4918 ret
= sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_RC6VIDS
, rc6vids
);
4920 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
4923 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
4926 static void __gen6_update_ring_freq(struct drm_device
*dev
)
4928 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4930 unsigned int gpu_freq
;
4931 unsigned int max_ia_freq
, min_ring_freq
;
4932 unsigned int max_gpu_freq
, min_gpu_freq
;
4933 int scaling_factor
= 180;
4934 struct cpufreq_policy
*policy
;
4936 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
4938 policy
= cpufreq_cpu_get(0);
4940 max_ia_freq
= policy
->cpuinfo
.max_freq
;
4941 cpufreq_cpu_put(policy
);
4944 * Default to measured freq if none found, PCU will ensure we
4947 max_ia_freq
= tsc_khz
;
4950 /* Convert from kHz to MHz */
4951 max_ia_freq
/= 1000;
4953 min_ring_freq
= I915_READ(DCLK
) & 0xf;
4954 /* convert DDR frequency from units of 266.6MHz to bandwidth */
4955 min_ring_freq
= mult_frac(min_ring_freq
, 8, 3);
4957 if (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
)) {
4958 /* Convert GT frequency to 50 HZ units */
4959 min_gpu_freq
= dev_priv
->rps
.min_freq
/ GEN9_FREQ_SCALER
;
4960 max_gpu_freq
= dev_priv
->rps
.max_freq
/ GEN9_FREQ_SCALER
;
4962 min_gpu_freq
= dev_priv
->rps
.min_freq
;
4963 max_gpu_freq
= dev_priv
->rps
.max_freq
;
4967 * For each potential GPU frequency, load a ring frequency we'd like
4968 * to use for memory access. We do this by specifying the IA frequency
4969 * the PCU should use as a reference to determine the ring frequency.
4971 for (gpu_freq
= max_gpu_freq
; gpu_freq
>= min_gpu_freq
; gpu_freq
--) {
4972 int diff
= max_gpu_freq
- gpu_freq
;
4973 unsigned int ia_freq
= 0, ring_freq
= 0;
4975 if (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
)) {
4977 * ring_freq = 2 * GT. ring_freq is in 100MHz units
4978 * No floor required for ring frequency on SKL.
4980 ring_freq
= gpu_freq
;
4981 } else if (INTEL_INFO(dev
)->gen
>= 8) {
4982 /* max(2 * GT, DDR). NB: GT is 50MHz units */
4983 ring_freq
= max(min_ring_freq
, gpu_freq
);
4984 } else if (IS_HASWELL(dev
)) {
4985 ring_freq
= mult_frac(gpu_freq
, 5, 4);
4986 ring_freq
= max(min_ring_freq
, ring_freq
);
4987 /* leave ia_freq as the default, chosen by cpufreq */
4989 /* On older processors, there is no separate ring
4990 * clock domain, so in order to boost the bandwidth
4991 * of the ring, we need to upclock the CPU (ia_freq).
4993 * For GPU frequencies less than 750MHz,
4994 * just use the lowest ring freq.
4996 if (gpu_freq
< min_freq
)
4999 ia_freq
= max_ia_freq
- ((diff
* scaling_factor
) / 2);
5000 ia_freq
= DIV_ROUND_CLOSEST(ia_freq
, 100);
5003 sandybridge_pcode_write(dev_priv
,
5004 GEN6_PCODE_WRITE_MIN_FREQ_TABLE
,
5005 ia_freq
<< GEN6_PCODE_FREQ_IA_RATIO_SHIFT
|
5006 ring_freq
<< GEN6_PCODE_FREQ_RING_RATIO_SHIFT
|
5011 void gen6_update_ring_freq(struct drm_device
*dev
)
5013 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5015 if (!HAS_CORE_RING_FREQ(dev
))
5018 mutex_lock(&dev_priv
->rps
.hw_lock
);
5019 __gen6_update_ring_freq(dev
);
5020 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5023 static int cherryview_rps_max_freq(struct drm_i915_private
*dev_priv
)
5025 struct drm_device
*dev
= dev_priv
->dev
;
5028 val
= vlv_punit_read(dev_priv
, FB_GFX_FMAX_AT_VMAX_FUSE
);
5030 switch (INTEL_INFO(dev
)->eu_total
) {
5032 /* (2 * 4) config */
5033 rp0
= (val
>> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT
);
5036 /* (2 * 6) config */
5037 rp0
= (val
>> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT
);
5040 /* (2 * 8) config */
5042 /* Setting (2 * 8) Min RP0 for any other combination */
5043 rp0
= (val
>> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT
);
5047 rp0
= (rp0
& FB_GFX_FREQ_FUSE_MASK
);
5052 static int cherryview_rps_rpe_freq(struct drm_i915_private
*dev_priv
)
5056 val
= vlv_punit_read(dev_priv
, PUNIT_GPU_DUTYCYCLE_REG
);
5057 rpe
= (val
>> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT
) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK
;
5062 static int cherryview_rps_guar_freq(struct drm_i915_private
*dev_priv
)
5066 val
= vlv_punit_read(dev_priv
, FB_GFX_FMAX_AT_VMAX_FUSE
);
5067 rp1
= (val
& FB_GFX_FREQ_FUSE_MASK
);
5072 static int valleyview_rps_guar_freq(struct drm_i915_private
*dev_priv
)
5076 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FREQ_FUSE
);
5078 rp1
= (val
& FB_GFX_FGUARANTEED_FREQ_FUSE_MASK
) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT
;
5083 static int valleyview_rps_max_freq(struct drm_i915_private
*dev_priv
)
5087 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FREQ_FUSE
);
5089 rp0
= (val
& FB_GFX_MAX_FREQ_FUSE_MASK
) >> FB_GFX_MAX_FREQ_FUSE_SHIFT
;
5091 rp0
= min_t(u32
, rp0
, 0xea);
5096 static int valleyview_rps_rpe_freq(struct drm_i915_private
*dev_priv
)
5100 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FMAX_FUSE_LO
);
5101 rpe
= (val
& FB_FMAX_VMIN_FREQ_LO_MASK
) >> FB_FMAX_VMIN_FREQ_LO_SHIFT
;
5102 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FMAX_FUSE_HI
);
5103 rpe
|= (val
& FB_FMAX_VMIN_FREQ_HI_MASK
) << 5;
5108 static int valleyview_rps_min_freq(struct drm_i915_private
*dev_priv
)
5112 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_LFM
) & 0xff;
5114 * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
5115 * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
5116 * a BYT-M B0 the above register contains 0xbf. Moreover when setting
5117 * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
5118 * to make sure it matches what Punit accepts.
5120 return max_t(u32
, val
, 0xc0);
5123 /* Check that the pctx buffer wasn't move under us. */
5124 static void valleyview_check_pctx(struct drm_i915_private
*dev_priv
)
5126 unsigned long pctx_addr
= I915_READ(VLV_PCBR
) & ~4095;
5128 WARN_ON(pctx_addr
!= dev_priv
->mm
.stolen_base
+
5129 dev_priv
->vlv_pctx
->stolen
->start
);
5133 /* Check that the pcbr address is not empty. */
5134 static void cherryview_check_pctx(struct drm_i915_private
*dev_priv
)
5136 unsigned long pctx_addr
= I915_READ(VLV_PCBR
) & ~4095;
5138 WARN_ON((pctx_addr
>> VLV_PCBR_ADDR_SHIFT
) == 0);
5141 static void cherryview_setup_pctx(struct drm_device
*dev
)
5143 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5144 unsigned long pctx_paddr
, paddr
;
5145 struct i915_gtt
*gtt
= &dev_priv
->gtt
;
5147 int pctx_size
= 32*1024;
5149 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
5151 pcbr
= I915_READ(VLV_PCBR
);
5152 if ((pcbr
>> VLV_PCBR_ADDR_SHIFT
) == 0) {
5153 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5154 paddr
= (dev_priv
->mm
.stolen_base
+
5155 (gtt
->stolen_size
- pctx_size
));
5157 pctx_paddr
= (paddr
& (~4095));
5158 I915_WRITE(VLV_PCBR
, pctx_paddr
);
5161 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR
));
5164 static void valleyview_setup_pctx(struct drm_device
*dev
)
5166 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5167 struct drm_i915_gem_object
*pctx
;
5168 unsigned long pctx_paddr
;
5170 int pctx_size
= 24*1024;
5172 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
5174 pcbr
= I915_READ(VLV_PCBR
);
5176 /* BIOS set it up already, grab the pre-alloc'd space */
5179 pcbr_offset
= (pcbr
& (~4095)) - dev_priv
->mm
.stolen_base
;
5180 pctx
= i915_gem_object_create_stolen_for_preallocated(dev_priv
->dev
,
5182 I915_GTT_OFFSET_NONE
,
5187 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5190 * From the Gunit register HAS:
5191 * The Gfx driver is expected to program this register and ensure
5192 * proper allocation within Gfx stolen memory. For example, this
5193 * register should be programmed such than the PCBR range does not
5194 * overlap with other ranges, such as the frame buffer, protected
5195 * memory, or any other relevant ranges.
5197 pctx
= i915_gem_object_create_stolen(dev
, pctx_size
);
5199 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
5203 pctx_paddr
= dev_priv
->mm
.stolen_base
+ pctx
->stolen
->start
;
5204 I915_WRITE(VLV_PCBR
, pctx_paddr
);
5207 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR
));
5208 dev_priv
->vlv_pctx
= pctx
;
5211 static void valleyview_cleanup_pctx(struct drm_device
*dev
)
5213 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5215 if (WARN_ON(!dev_priv
->vlv_pctx
))
5218 drm_gem_object_unreference(&dev_priv
->vlv_pctx
->base
);
5219 dev_priv
->vlv_pctx
= NULL
;
5222 static void valleyview_init_gt_powersave(struct drm_device
*dev
)
5224 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5227 valleyview_setup_pctx(dev
);
5229 mutex_lock(&dev_priv
->rps
.hw_lock
);
5231 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
5232 switch ((val
>> 6) & 3) {
5235 dev_priv
->mem_freq
= 800;
5238 dev_priv
->mem_freq
= 1066;
5241 dev_priv
->mem_freq
= 1333;
5244 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv
->mem_freq
);
5246 dev_priv
->rps
.max_freq
= valleyview_rps_max_freq(dev_priv
);
5247 dev_priv
->rps
.rp0_freq
= dev_priv
->rps
.max_freq
;
5248 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5249 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
),
5250 dev_priv
->rps
.max_freq
);
5252 dev_priv
->rps
.efficient_freq
= valleyview_rps_rpe_freq(dev_priv
);
5253 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5254 intel_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
),
5255 dev_priv
->rps
.efficient_freq
);
5257 dev_priv
->rps
.rp1_freq
= valleyview_rps_guar_freq(dev_priv
);
5258 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
5259 intel_gpu_freq(dev_priv
, dev_priv
->rps
.rp1_freq
),
5260 dev_priv
->rps
.rp1_freq
);
5262 dev_priv
->rps
.min_freq
= valleyview_rps_min_freq(dev_priv
);
5263 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5264 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
),
5265 dev_priv
->rps
.min_freq
);
5267 dev_priv
->rps
.idle_freq
= dev_priv
->rps
.min_freq
;
5269 /* Preserve min/max settings in case of re-init */
5270 if (dev_priv
->rps
.max_freq_softlimit
== 0)
5271 dev_priv
->rps
.max_freq_softlimit
= dev_priv
->rps
.max_freq
;
5273 if (dev_priv
->rps
.min_freq_softlimit
== 0)
5274 dev_priv
->rps
.min_freq_softlimit
= dev_priv
->rps
.min_freq
;
5276 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5279 static void cherryview_init_gt_powersave(struct drm_device
*dev
)
5281 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5284 cherryview_setup_pctx(dev
);
5286 mutex_lock(&dev_priv
->rps
.hw_lock
);
5288 mutex_lock(&dev_priv
->sb_lock
);
5289 val
= vlv_cck_read(dev_priv
, CCK_FUSE_REG
);
5290 mutex_unlock(&dev_priv
->sb_lock
);
5292 switch ((val
>> 2) & 0x7) {
5294 dev_priv
->mem_freq
= 2000;
5297 dev_priv
->mem_freq
= 1600;
5300 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv
->mem_freq
);
5302 dev_priv
->rps
.max_freq
= cherryview_rps_max_freq(dev_priv
);
5303 dev_priv
->rps
.rp0_freq
= dev_priv
->rps
.max_freq
;
5304 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5305 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
),
5306 dev_priv
->rps
.max_freq
);
5308 dev_priv
->rps
.efficient_freq
= cherryview_rps_rpe_freq(dev_priv
);
5309 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5310 intel_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
),
5311 dev_priv
->rps
.efficient_freq
);
5313 dev_priv
->rps
.rp1_freq
= cherryview_rps_guar_freq(dev_priv
);
5314 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
5315 intel_gpu_freq(dev_priv
, dev_priv
->rps
.rp1_freq
),
5316 dev_priv
->rps
.rp1_freq
);
5318 /* PUnit validated range is only [RPe, RP0] */
5319 dev_priv
->rps
.min_freq
= dev_priv
->rps
.efficient_freq
;
5320 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5321 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
),
5322 dev_priv
->rps
.min_freq
);
5324 WARN_ONCE((dev_priv
->rps
.max_freq
|
5325 dev_priv
->rps
.efficient_freq
|
5326 dev_priv
->rps
.rp1_freq
|
5327 dev_priv
->rps
.min_freq
) & 1,
5328 "Odd GPU freq values\n");
5330 dev_priv
->rps
.idle_freq
= dev_priv
->rps
.min_freq
;
5332 /* Preserve min/max settings in case of re-init */
5333 if (dev_priv
->rps
.max_freq_softlimit
== 0)
5334 dev_priv
->rps
.max_freq_softlimit
= dev_priv
->rps
.max_freq
;
5336 if (dev_priv
->rps
.min_freq_softlimit
== 0)
5337 dev_priv
->rps
.min_freq_softlimit
= dev_priv
->rps
.min_freq
;
5339 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5342 static void valleyview_cleanup_gt_powersave(struct drm_device
*dev
)
5344 valleyview_cleanup_pctx(dev
);
5347 static void cherryview_enable_rps(struct drm_device
*dev
)
5349 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5350 struct intel_engine_cs
*ring
;
5351 u32 gtfifodbg
, val
, rc6_mode
= 0, pcbr
;
5354 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
5356 gtfifodbg
= I915_READ(GTFIFODBG
);
5358 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5360 I915_WRITE(GTFIFODBG
, gtfifodbg
);
5363 cherryview_check_pctx(dev_priv
);
5365 /* 1a & 1b: Get forcewake during program sequence. Although the driver
5366 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5367 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
5369 /* Disable RC states. */
5370 I915_WRITE(GEN6_RC_CONTROL
, 0);
5372 /* 2a: Program RC6 thresholds.*/
5373 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 40 << 16);
5374 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000); /* 12500 * 1280ns */
5375 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25); /* 25 * 1280ns */
5377 for_each_ring(ring
, dev_priv
, i
)
5378 I915_WRITE(RING_MAX_IDLE(ring
->mmio_base
), 10);
5379 I915_WRITE(GEN6_RC_SLEEP
, 0);
5381 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
5382 I915_WRITE(GEN6_RC6_THRESHOLD
, 0x186);
5384 /* allows RC6 residency counter to work */
5385 I915_WRITE(VLV_COUNTER_CONTROL
,
5386 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH
|
5387 VLV_MEDIA_RC6_COUNT_EN
|
5388 VLV_RENDER_RC6_COUNT_EN
));
5390 /* For now we assume BIOS is allocating and populating the PCBR */
5391 pcbr
= I915_READ(VLV_PCBR
);
5394 if ((intel_enable_rc6(dev
) & INTEL_RC6_ENABLE
) &&
5395 (pcbr
>> VLV_PCBR_ADDR_SHIFT
))
5396 rc6_mode
= GEN7_RC_CTL_TO_MODE
;
5398 I915_WRITE(GEN6_RC_CONTROL
, rc6_mode
);
5400 /* 4 Program defaults and thresholds for RPS*/
5401 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 1000000);
5402 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 59400);
5403 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 245000);
5404 I915_WRITE(GEN6_RP_UP_EI
, 66000);
5405 I915_WRITE(GEN6_RP_DOWN_EI
, 350000);
5407 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
5410 I915_WRITE(GEN6_RP_CONTROL
,
5411 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
5412 GEN6_RP_MEDIA_IS_GFX
|
5414 GEN6_RP_UP_BUSY_AVG
|
5415 GEN6_RP_DOWN_IDLE_AVG
);
5417 /* Setting Fixed Bias */
5418 val
= VLV_OVERRIDE_EN
|
5420 CHV_BIAS_CPU_50_SOC_50
;
5421 vlv_punit_write(dev_priv
, VLV_TURBO_SOC_OVERRIDE
, val
);
5423 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
5425 /* RPS code assumes GPLL is used */
5426 WARN_ONCE((val
& GPLLENABLE
) == 0, "GPLL not enabled\n");
5428 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val
& GPLLENABLE
));
5429 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val
);
5431 dev_priv
->rps
.cur_freq
= (val
>> 8) & 0xff;
5432 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5433 intel_gpu_freq(dev_priv
, dev_priv
->rps
.cur_freq
),
5434 dev_priv
->rps
.cur_freq
);
5436 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5437 intel_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
),
5438 dev_priv
->rps
.efficient_freq
);
5440 valleyview_set_rps(dev_priv
->dev
, dev_priv
->rps
.efficient_freq
);
5442 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
5445 static void valleyview_enable_rps(struct drm_device
*dev
)
5447 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5448 struct intel_engine_cs
*ring
;
5449 u32 gtfifodbg
, val
, rc6_mode
= 0;
5452 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
5454 valleyview_check_pctx(dev_priv
);
5456 if ((gtfifodbg
= I915_READ(GTFIFODBG
))) {
5457 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5459 I915_WRITE(GTFIFODBG
, gtfifodbg
);
5462 /* If VLV, Forcewake all wells, else re-direct to regular path */
5463 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
5465 /* Disable RC states. */
5466 I915_WRITE(GEN6_RC_CONTROL
, 0);
5468 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 1000000);
5469 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 59400);
5470 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 245000);
5471 I915_WRITE(GEN6_RP_UP_EI
, 66000);
5472 I915_WRITE(GEN6_RP_DOWN_EI
, 350000);
5474 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
5476 I915_WRITE(GEN6_RP_CONTROL
,
5477 GEN6_RP_MEDIA_TURBO
|
5478 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
5479 GEN6_RP_MEDIA_IS_GFX
|
5481 GEN6_RP_UP_BUSY_AVG
|
5482 GEN6_RP_DOWN_IDLE_CONT
);
5484 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 0x00280000);
5485 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000);
5486 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25);
5488 for_each_ring(ring
, dev_priv
, i
)
5489 I915_WRITE(RING_MAX_IDLE(ring
->mmio_base
), 10);
5491 I915_WRITE(GEN6_RC6_THRESHOLD
, 0x557);
5493 /* allows RC6 residency counter to work */
5494 I915_WRITE(VLV_COUNTER_CONTROL
,
5495 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN
|
5496 VLV_RENDER_RC0_COUNT_EN
|
5497 VLV_MEDIA_RC6_COUNT_EN
|
5498 VLV_RENDER_RC6_COUNT_EN
));
5500 if (intel_enable_rc6(dev
) & INTEL_RC6_ENABLE
)
5501 rc6_mode
= GEN7_RC_CTL_TO_MODE
| VLV_RC_CTL_CTX_RST_PARALLEL
;
5503 intel_print_rc6_info(dev
, rc6_mode
);
5505 I915_WRITE(GEN6_RC_CONTROL
, rc6_mode
);
5507 /* Setting Fixed Bias */
5508 val
= VLV_OVERRIDE_EN
|
5510 VLV_BIAS_CPU_125_SOC_875
;
5511 vlv_punit_write(dev_priv
, VLV_TURBO_SOC_OVERRIDE
, val
);
5513 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
5515 /* RPS code assumes GPLL is used */
5516 WARN_ONCE((val
& GPLLENABLE
) == 0, "GPLL not enabled\n");
5518 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val
& GPLLENABLE
));
5519 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val
);
5521 dev_priv
->rps
.cur_freq
= (val
>> 8) & 0xff;
5522 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5523 intel_gpu_freq(dev_priv
, dev_priv
->rps
.cur_freq
),
5524 dev_priv
->rps
.cur_freq
);
5526 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5527 intel_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
),
5528 dev_priv
->rps
.efficient_freq
);
5530 valleyview_set_rps(dev_priv
->dev
, dev_priv
->rps
.efficient_freq
);
5532 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
5535 static unsigned long intel_pxfreq(u32 vidfreq
)
5538 int div
= (vidfreq
& 0x3f0000) >> 16;
5539 int post
= (vidfreq
& 0x3000) >> 12;
5540 int pre
= (vidfreq
& 0x7);
5545 freq
= ((div
* 133333) / ((1<<post
) * pre
));
5550 static const struct cparams
{
5556 { 1, 1333, 301, 28664 },
5557 { 1, 1066, 294, 24460 },
5558 { 1, 800, 294, 25192 },
5559 { 0, 1333, 276, 27605 },
5560 { 0, 1066, 276, 27605 },
5561 { 0, 800, 231, 23784 },
5564 static unsigned long __i915_chipset_val(struct drm_i915_private
*dev_priv
)
5566 u64 total_count
, diff
, ret
;
5567 u32 count1
, count2
, count3
, m
= 0, c
= 0;
5568 unsigned long now
= jiffies_to_msecs(jiffies
), diff1
;
5571 assert_spin_locked(&mchdev_lock
);
5573 diff1
= now
- dev_priv
->ips
.last_time1
;
5575 /* Prevent division-by-zero if we are asking too fast.
5576 * Also, we don't get interesting results if we are polling
5577 * faster than once in 10ms, so just return the saved value
5581 return dev_priv
->ips
.chipset_power
;
5583 count1
= I915_READ(DMIEC
);
5584 count2
= I915_READ(DDREC
);
5585 count3
= I915_READ(CSIEC
);
5587 total_count
= count1
+ count2
+ count3
;
5589 /* FIXME: handle per-counter overflow */
5590 if (total_count
< dev_priv
->ips
.last_count1
) {
5591 diff
= ~0UL - dev_priv
->ips
.last_count1
;
5592 diff
+= total_count
;
5594 diff
= total_count
- dev_priv
->ips
.last_count1
;
5597 for (i
= 0; i
< ARRAY_SIZE(cparams
); i
++) {
5598 if (cparams
[i
].i
== dev_priv
->ips
.c_m
&&
5599 cparams
[i
].t
== dev_priv
->ips
.r_t
) {
5606 diff
= div_u64(diff
, diff1
);
5607 ret
= ((m
* diff
) + c
);
5608 ret
= div_u64(ret
, 10);
5610 dev_priv
->ips
.last_count1
= total_count
;
5611 dev_priv
->ips
.last_time1
= now
;
5613 dev_priv
->ips
.chipset_power
= ret
;
5618 unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
)
5620 struct drm_device
*dev
= dev_priv
->dev
;
5623 if (INTEL_INFO(dev
)->gen
!= 5)
5626 spin_lock_irq(&mchdev_lock
);
5628 val
= __i915_chipset_val(dev_priv
);
5630 spin_unlock_irq(&mchdev_lock
);
5635 unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
)
5637 unsigned long m
, x
, b
;
5640 tsfs
= I915_READ(TSFS
);
5642 m
= ((tsfs
& TSFS_SLOPE_MASK
) >> TSFS_SLOPE_SHIFT
);
5643 x
= I915_READ8(TR1
);
5645 b
= tsfs
& TSFS_INTR_MASK
;
5647 return ((m
* x
) / 127) - b
;
5650 static int _pxvid_to_vd(u8 pxvid
)
5655 if (pxvid
>= 8 && pxvid
< 31)
5658 return (pxvid
+ 2) * 125;
5661 static u32
pvid_to_extvid(struct drm_i915_private
*dev_priv
, u8 pxvid
)
5663 struct drm_device
*dev
= dev_priv
->dev
;
5664 const int vd
= _pxvid_to_vd(pxvid
);
5665 const int vm
= vd
- 1125;
5667 if (INTEL_INFO(dev
)->is_mobile
)
5668 return vm
> 0 ? vm
: 0;
5673 static void __i915_update_gfx_val(struct drm_i915_private
*dev_priv
)
5675 u64 now
, diff
, diffms
;
5678 assert_spin_locked(&mchdev_lock
);
5680 now
= ktime_get_raw_ns();
5681 diffms
= now
- dev_priv
->ips
.last_time2
;
5682 do_div(diffms
, NSEC_PER_MSEC
);
5684 /* Don't divide by 0 */
5688 count
= I915_READ(GFXEC
);
5690 if (count
< dev_priv
->ips
.last_count2
) {
5691 diff
= ~0UL - dev_priv
->ips
.last_count2
;
5694 diff
= count
- dev_priv
->ips
.last_count2
;
5697 dev_priv
->ips
.last_count2
= count
;
5698 dev_priv
->ips
.last_time2
= now
;
5700 /* More magic constants... */
5702 diff
= div_u64(diff
, diffms
* 10);
5703 dev_priv
->ips
.gfx_power
= diff
;
5706 void i915_update_gfx_val(struct drm_i915_private
*dev_priv
)
5708 struct drm_device
*dev
= dev_priv
->dev
;
5710 if (INTEL_INFO(dev
)->gen
!= 5)
5713 spin_lock_irq(&mchdev_lock
);
5715 __i915_update_gfx_val(dev_priv
);
5717 spin_unlock_irq(&mchdev_lock
);
5720 static unsigned long __i915_gfx_val(struct drm_i915_private
*dev_priv
)
5722 unsigned long t
, corr
, state1
, corr2
, state2
;
5725 assert_spin_locked(&mchdev_lock
);
5727 pxvid
= I915_READ(PXVFREQ(dev_priv
->rps
.cur_freq
));
5728 pxvid
= (pxvid
>> 24) & 0x7f;
5729 ext_v
= pvid_to_extvid(dev_priv
, pxvid
);
5733 t
= i915_mch_val(dev_priv
);
5735 /* Revel in the empirically derived constants */
5737 /* Correction factor in 1/100000 units */
5739 corr
= ((t
* 2349) + 135940);
5741 corr
= ((t
* 964) + 29317);
5743 corr
= ((t
* 301) + 1004);
5745 corr
= corr
* ((150142 * state1
) / 10000 - 78642);
5747 corr2
= (corr
* dev_priv
->ips
.corr
);
5749 state2
= (corr2
* state1
) / 10000;
5750 state2
/= 100; /* convert to mW */
5752 __i915_update_gfx_val(dev_priv
);
5754 return dev_priv
->ips
.gfx_power
+ state2
;
5757 unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
)
5759 struct drm_device
*dev
= dev_priv
->dev
;
5762 if (INTEL_INFO(dev
)->gen
!= 5)
5765 spin_lock_irq(&mchdev_lock
);
5767 val
= __i915_gfx_val(dev_priv
);
5769 spin_unlock_irq(&mchdev_lock
);
5775 * i915_read_mch_val - return value for IPS use
5777 * Calculate and return a value for the IPS driver to use when deciding whether
5778 * we have thermal and power headroom to increase CPU or GPU power budget.
5780 unsigned long i915_read_mch_val(void)
5782 struct drm_i915_private
*dev_priv
;
5783 unsigned long chipset_val
, graphics_val
, ret
= 0;
5785 spin_lock_irq(&mchdev_lock
);
5788 dev_priv
= i915_mch_dev
;
5790 chipset_val
= __i915_chipset_val(dev_priv
);
5791 graphics_val
= __i915_gfx_val(dev_priv
);
5793 ret
= chipset_val
+ graphics_val
;
5796 spin_unlock_irq(&mchdev_lock
);
5800 EXPORT_SYMBOL_GPL(i915_read_mch_val
);
5803 * i915_gpu_raise - raise GPU frequency limit
5805 * Raise the limit; IPS indicates we have thermal headroom.
5807 bool i915_gpu_raise(void)
5809 struct drm_i915_private
*dev_priv
;
5812 spin_lock_irq(&mchdev_lock
);
5813 if (!i915_mch_dev
) {
5817 dev_priv
= i915_mch_dev
;
5819 if (dev_priv
->ips
.max_delay
> dev_priv
->ips
.fmax
)
5820 dev_priv
->ips
.max_delay
--;
5823 spin_unlock_irq(&mchdev_lock
);
5827 EXPORT_SYMBOL_GPL(i915_gpu_raise
);
5830 * i915_gpu_lower - lower GPU frequency limit
5832 * IPS indicates we're close to a thermal limit, so throttle back the GPU
5833 * frequency maximum.
5835 bool i915_gpu_lower(void)
5837 struct drm_i915_private
*dev_priv
;
5840 spin_lock_irq(&mchdev_lock
);
5841 if (!i915_mch_dev
) {
5845 dev_priv
= i915_mch_dev
;
5847 if (dev_priv
->ips
.max_delay
< dev_priv
->ips
.min_delay
)
5848 dev_priv
->ips
.max_delay
++;
5851 spin_unlock_irq(&mchdev_lock
);
5855 EXPORT_SYMBOL_GPL(i915_gpu_lower
);
5858 * i915_gpu_busy - indicate GPU business to IPS
5860 * Tell the IPS driver whether or not the GPU is busy.
5862 bool i915_gpu_busy(void)
5864 struct drm_i915_private
*dev_priv
;
5865 struct intel_engine_cs
*ring
;
5869 spin_lock_irq(&mchdev_lock
);
5872 dev_priv
= i915_mch_dev
;
5874 for_each_ring(ring
, dev_priv
, i
)
5875 ret
|= !list_empty(&ring
->request_list
);
5878 spin_unlock_irq(&mchdev_lock
);
5882 EXPORT_SYMBOL_GPL(i915_gpu_busy
);
5885 * i915_gpu_turbo_disable - disable graphics turbo
5887 * Disable graphics turbo by resetting the max frequency and setting the
5888 * current frequency to the default.
5890 bool i915_gpu_turbo_disable(void)
5892 struct drm_i915_private
*dev_priv
;
5895 spin_lock_irq(&mchdev_lock
);
5896 if (!i915_mch_dev
) {
5900 dev_priv
= i915_mch_dev
;
5902 dev_priv
->ips
.max_delay
= dev_priv
->ips
.fstart
;
5904 if (!ironlake_set_drps(dev_priv
->dev
, dev_priv
->ips
.fstart
))
5908 spin_unlock_irq(&mchdev_lock
);
5912 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable
);
5915 * Tells the intel_ips driver that the i915 driver is now loaded, if
5916 * IPS got loaded first.
5918 * This awkward dance is so that neither module has to depend on the
5919 * other in order for IPS to do the appropriate communication of
5920 * GPU turbo limits to i915.
5923 ips_ping_for_i915_load(void)
5927 link
= symbol_get(ips_link_to_i915_driver
);
5930 symbol_put(ips_link_to_i915_driver
);
5934 void intel_gpu_ips_init(struct drm_i915_private
*dev_priv
)
5936 /* We only register the i915 ips part with intel-ips once everything is
5937 * set up, to avoid intel-ips sneaking in and reading bogus values. */
5938 spin_lock_irq(&mchdev_lock
);
5939 i915_mch_dev
= dev_priv
;
5940 spin_unlock_irq(&mchdev_lock
);
5942 ips_ping_for_i915_load();
5945 void intel_gpu_ips_teardown(void)
5947 spin_lock_irq(&mchdev_lock
);
5948 i915_mch_dev
= NULL
;
5949 spin_unlock_irq(&mchdev_lock
);
5952 static void intel_init_emon(struct drm_device
*dev
)
5954 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5959 /* Disable to program */
5963 /* Program energy weights for various events */
5964 I915_WRITE(SDEW
, 0x15040d00);
5965 I915_WRITE(CSIEW0
, 0x007f0000);
5966 I915_WRITE(CSIEW1
, 0x1e220004);
5967 I915_WRITE(CSIEW2
, 0x04000004);
5969 for (i
= 0; i
< 5; i
++)
5970 I915_WRITE(PEW(i
), 0);
5971 for (i
= 0; i
< 3; i
++)
5972 I915_WRITE(DEW(i
), 0);
5974 /* Program P-state weights to account for frequency power adjustment */
5975 for (i
= 0; i
< 16; i
++) {
5976 u32 pxvidfreq
= I915_READ(PXVFREQ(i
));
5977 unsigned long freq
= intel_pxfreq(pxvidfreq
);
5978 unsigned long vid
= (pxvidfreq
& PXVFREQ_PX_MASK
) >>
5983 val
*= (freq
/ 1000);
5985 val
/= (127*127*900);
5987 DRM_ERROR("bad pxval: %ld\n", val
);
5990 /* Render standby states get 0 weight */
5994 for (i
= 0; i
< 4; i
++) {
5995 u32 val
= (pxw
[i
*4] << 24) | (pxw
[(i
*4)+1] << 16) |
5996 (pxw
[(i
*4)+2] << 8) | (pxw
[(i
*4)+3]);
5997 I915_WRITE(PXW(i
), val
);
6000 /* Adjust magic regs to magic values (more experimental results) */
6001 I915_WRITE(OGW0
, 0);
6002 I915_WRITE(OGW1
, 0);
6003 I915_WRITE(EG0
, 0x00007f00);
6004 I915_WRITE(EG1
, 0x0000000e);
6005 I915_WRITE(EG2
, 0x000e0000);
6006 I915_WRITE(EG3
, 0x68000300);
6007 I915_WRITE(EG4
, 0x42000000);
6008 I915_WRITE(EG5
, 0x00140031);
6012 for (i
= 0; i
< 8; i
++)
6013 I915_WRITE(PXWL(i
), 0);
6015 /* Enable PMON + select events */
6016 I915_WRITE(ECR
, 0x80000019);
6018 lcfuse
= I915_READ(LCFUSE02
);
6020 dev_priv
->ips
.corr
= (lcfuse
& LCFUSE_HIV_MASK
);
6023 void intel_init_gt_powersave(struct drm_device
*dev
)
6025 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6027 i915
.enable_rc6
= sanitize_rc6_option(dev
, i915
.enable_rc6
);
6029 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6032 if (!i915
.enable_rc6
) {
6033 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6034 intel_runtime_pm_get(dev_priv
);
6037 if (IS_CHERRYVIEW(dev
))
6038 cherryview_init_gt_powersave(dev
);
6039 else if (IS_VALLEYVIEW(dev
))
6040 valleyview_init_gt_powersave(dev
);
6043 void intel_cleanup_gt_powersave(struct drm_device
*dev
)
6045 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6047 if (IS_CHERRYVIEW(dev
))
6049 else if (IS_VALLEYVIEW(dev
))
6050 valleyview_cleanup_gt_powersave(dev
);
6052 if (!i915
.enable_rc6
)
6053 intel_runtime_pm_put(dev_priv
);
6056 static void gen6_suspend_rps(struct drm_device
*dev
)
6058 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6060 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
6062 gen6_disable_rps_interrupts(dev
);
6066 * intel_suspend_gt_powersave - suspend PM work and helper threads
6069 * We don't want to disable RC6 or other features here, we just want
6070 * to make sure any work we've queued has finished and won't bother
6071 * us while we're suspended.
6073 void intel_suspend_gt_powersave(struct drm_device
*dev
)
6075 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6077 if (INTEL_INFO(dev
)->gen
< 6)
6080 gen6_suspend_rps(dev
);
6082 /* Force GPU to min freq during suspend */
6083 gen6_rps_idle(dev_priv
);
6086 void intel_disable_gt_powersave(struct drm_device
*dev
)
6088 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6090 if (IS_IRONLAKE_M(dev
)) {
6091 ironlake_disable_drps(dev
);
6092 } else if (INTEL_INFO(dev
)->gen
>= 6) {
6093 intel_suspend_gt_powersave(dev
);
6095 mutex_lock(&dev_priv
->rps
.hw_lock
);
6096 if (INTEL_INFO(dev
)->gen
>= 9)
6097 gen9_disable_rps(dev
);
6098 else if (IS_CHERRYVIEW(dev
))
6099 cherryview_disable_rps(dev
);
6100 else if (IS_VALLEYVIEW(dev
))
6101 valleyview_disable_rps(dev
);
6103 gen6_disable_rps(dev
);
6105 dev_priv
->rps
.enabled
= false;
6106 mutex_unlock(&dev_priv
->rps
.hw_lock
);
6110 static void intel_gen6_powersave_work(struct work_struct
*work
)
6112 struct drm_i915_private
*dev_priv
=
6113 container_of(work
, struct drm_i915_private
,
6114 rps
.delayed_resume_work
.work
);
6115 struct drm_device
*dev
= dev_priv
->dev
;
6117 mutex_lock(&dev_priv
->rps
.hw_lock
);
6119 gen6_reset_rps_interrupts(dev
);
6121 if (IS_CHERRYVIEW(dev
)) {
6122 cherryview_enable_rps(dev
);
6123 } else if (IS_VALLEYVIEW(dev
)) {
6124 valleyview_enable_rps(dev
);
6125 } else if (INTEL_INFO(dev
)->gen
>= 9) {
6126 gen9_enable_rc6(dev
);
6127 gen9_enable_rps(dev
);
6128 if (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
))
6129 __gen6_update_ring_freq(dev
);
6130 } else if (IS_BROADWELL(dev
)) {
6131 gen8_enable_rps(dev
);
6132 __gen6_update_ring_freq(dev
);
6134 gen6_enable_rps(dev
);
6135 __gen6_update_ring_freq(dev
);
6138 WARN_ON(dev_priv
->rps
.max_freq
< dev_priv
->rps
.min_freq
);
6139 WARN_ON(dev_priv
->rps
.idle_freq
> dev_priv
->rps
.max_freq
);
6141 WARN_ON(dev_priv
->rps
.efficient_freq
< dev_priv
->rps
.min_freq
);
6142 WARN_ON(dev_priv
->rps
.efficient_freq
> dev_priv
->rps
.max_freq
);
6144 dev_priv
->rps
.enabled
= true;
6146 gen6_enable_rps_interrupts(dev
);
6148 mutex_unlock(&dev_priv
->rps
.hw_lock
);
6150 intel_runtime_pm_put(dev_priv
);
6153 void intel_enable_gt_powersave(struct drm_device
*dev
)
6155 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6157 /* Powersaving is controlled by the host when inside a VM */
6158 if (intel_vgpu_active(dev
))
6161 if (IS_IRONLAKE_M(dev
)) {
6162 mutex_lock(&dev
->struct_mutex
);
6163 ironlake_enable_drps(dev
);
6164 intel_init_emon(dev
);
6165 mutex_unlock(&dev
->struct_mutex
);
6166 } else if (INTEL_INFO(dev
)->gen
>= 6) {
6168 * PCU communication is slow and this doesn't need to be
6169 * done at any specific time, so do this out of our fast path
6170 * to make resume and init faster.
6172 * We depend on the HW RC6 power context save/restore
6173 * mechanism when entering D3 through runtime PM suspend. So
6174 * disable RPM until RPS/RC6 is properly setup. We can only
6175 * get here via the driver load/system resume/runtime resume
6176 * paths, so the _noresume version is enough (and in case of
6177 * runtime resume it's necessary).
6179 if (schedule_delayed_work(&dev_priv
->rps
.delayed_resume_work
,
6180 round_jiffies_up_relative(HZ
)))
6181 intel_runtime_pm_get_noresume(dev_priv
);
6185 void intel_reset_gt_powersave(struct drm_device
*dev
)
6187 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6189 if (INTEL_INFO(dev
)->gen
< 6)
6192 gen6_suspend_rps(dev
);
6193 dev_priv
->rps
.enabled
= false;
6196 static void ibx_init_clock_gating(struct drm_device
*dev
)
6198 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6201 * On Ibex Peak and Cougar Point, we need to disable clock
6202 * gating for the panel power sequencer or it will fail to
6203 * start up when no ports are active.
6205 I915_WRITE(SOUTH_DSPCLK_GATE_D
, PCH_DPLSUNIT_CLOCK_GATE_DISABLE
);
6208 static void g4x_disable_trickle_feed(struct drm_device
*dev
)
6210 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6213 for_each_pipe(dev_priv
, pipe
) {
6214 I915_WRITE(DSPCNTR(pipe
),
6215 I915_READ(DSPCNTR(pipe
)) |
6216 DISPPLANE_TRICKLE_FEED_DISABLE
);
6218 I915_WRITE(DSPSURF(pipe
), I915_READ(DSPSURF(pipe
)));
6219 POSTING_READ(DSPSURF(pipe
));
6223 static void ilk_init_lp_watermarks(struct drm_device
*dev
)
6225 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6227 I915_WRITE(WM3_LP_ILK
, I915_READ(WM3_LP_ILK
) & ~WM1_LP_SR_EN
);
6228 I915_WRITE(WM2_LP_ILK
, I915_READ(WM2_LP_ILK
) & ~WM1_LP_SR_EN
);
6229 I915_WRITE(WM1_LP_ILK
, I915_READ(WM1_LP_ILK
) & ~WM1_LP_SR_EN
);
6232 * Don't touch WM1S_LP_EN here.
6233 * Doing so could cause underruns.
6237 static void ironlake_init_clock_gating(struct drm_device
*dev
)
6239 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6240 uint32_t dspclk_gate
= ILK_VRHUNIT_CLOCK_GATE_DISABLE
;
6244 * WaFbcDisableDpfcClockGating:ilk
6246 dspclk_gate
|= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE
|
6247 ILK_DPFCUNIT_CLOCK_GATE_DISABLE
|
6248 ILK_DPFDUNIT_CLOCK_GATE_ENABLE
;
6250 I915_WRITE(PCH_3DCGDIS0
,
6251 MARIUNIT_CLOCK_GATE_DISABLE
|
6252 SVSMUNIT_CLOCK_GATE_DISABLE
);
6253 I915_WRITE(PCH_3DCGDIS1
,
6254 VFMUNIT_CLOCK_GATE_DISABLE
);
6257 * According to the spec the following bits should be set in
6258 * order to enable memory self-refresh
6259 * The bit 22/21 of 0x42004
6260 * The bit 5 of 0x42020
6261 * The bit 15 of 0x45000
6263 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
6264 (I915_READ(ILK_DISPLAY_CHICKEN2
) |
6265 ILK_DPARB_GATE
| ILK_VSDPFD_FULL
));
6266 dspclk_gate
|= ILK_DPARBUNIT_CLOCK_GATE_ENABLE
;
6267 I915_WRITE(DISP_ARB_CTL
,
6268 (I915_READ(DISP_ARB_CTL
) |
6271 ilk_init_lp_watermarks(dev
);
6274 * Based on the document from hardware guys the following bits
6275 * should be set unconditionally in order to enable FBC.
6276 * The bit 22 of 0x42000
6277 * The bit 22 of 0x42004
6278 * The bit 7,8,9 of 0x42020.
6280 if (IS_IRONLAKE_M(dev
)) {
6281 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6282 I915_WRITE(ILK_DISPLAY_CHICKEN1
,
6283 I915_READ(ILK_DISPLAY_CHICKEN1
) |
6285 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
6286 I915_READ(ILK_DISPLAY_CHICKEN2
) |
6290 I915_WRITE(ILK_DSPCLK_GATE_D
, dspclk_gate
);
6292 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
6293 I915_READ(ILK_DISPLAY_CHICKEN2
) |
6294 ILK_ELPIN_409_SELECT
);
6295 I915_WRITE(_3D_CHICKEN2
,
6296 _3D_CHICKEN2_WM_READ_PIPELINED
<< 16 |
6297 _3D_CHICKEN2_WM_READ_PIPELINED
);
6299 /* WaDisableRenderCachePipelinedFlush:ilk */
6300 I915_WRITE(CACHE_MODE_0
,
6301 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE
));
6303 /* WaDisable_RenderCache_OperationalFlush:ilk */
6304 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
6306 g4x_disable_trickle_feed(dev
);
6308 ibx_init_clock_gating(dev
);
6311 static void cpt_init_clock_gating(struct drm_device
*dev
)
6313 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6318 * On Ibex Peak and Cougar Point, we need to disable clock
6319 * gating for the panel power sequencer or it will fail to
6320 * start up when no ports are active.
6322 I915_WRITE(SOUTH_DSPCLK_GATE_D
, PCH_DPLSUNIT_CLOCK_GATE_DISABLE
|
6323 PCH_DPLUNIT_CLOCK_GATE_DISABLE
|
6324 PCH_CPUNIT_CLOCK_GATE_DISABLE
);
6325 I915_WRITE(SOUTH_CHICKEN2
, I915_READ(SOUTH_CHICKEN2
) |
6326 DPLS_EDP_PPS_FIX_DIS
);
6327 /* The below fixes the weird display corruption, a few pixels shifted
6328 * downward, on (only) LVDS of some HP laptops with IVY.
6330 for_each_pipe(dev_priv
, pipe
) {
6331 val
= I915_READ(TRANS_CHICKEN2(pipe
));
6332 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
6333 val
&= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED
;
6334 if (dev_priv
->vbt
.fdi_rx_polarity_inverted
)
6335 val
|= TRANS_CHICKEN2_FDI_POLARITY_REVERSED
;
6336 val
&= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK
;
6337 val
&= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER
;
6338 val
&= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH
;
6339 I915_WRITE(TRANS_CHICKEN2(pipe
), val
);
6341 /* WADP0ClockGatingDisable */
6342 for_each_pipe(dev_priv
, pipe
) {
6343 I915_WRITE(TRANS_CHICKEN1(pipe
),
6344 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE
);
6348 static void gen6_check_mch_setup(struct drm_device
*dev
)
6350 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6353 tmp
= I915_READ(MCH_SSKPD
);
6354 if ((tmp
& MCH_SSKPD_WM0_MASK
) != MCH_SSKPD_WM0_VAL
)
6355 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6359 static void gen6_init_clock_gating(struct drm_device
*dev
)
6361 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6362 uint32_t dspclk_gate
= ILK_VRHUNIT_CLOCK_GATE_DISABLE
;
6364 I915_WRITE(ILK_DSPCLK_GATE_D
, dspclk_gate
);
6366 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
6367 I915_READ(ILK_DISPLAY_CHICKEN2
) |
6368 ILK_ELPIN_409_SELECT
);
6370 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
6371 I915_WRITE(_3D_CHICKEN
,
6372 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB
));
6374 /* WaDisable_RenderCache_OperationalFlush:snb */
6375 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
6378 * BSpec recoomends 8x4 when MSAA is used,
6379 * however in practice 16x4 seems fastest.
6381 * Note that PS/WM thread counts depend on the WIZ hashing
6382 * disable bit, which we don't touch here, but it's good
6383 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6385 I915_WRITE(GEN6_GT_MODE
,
6386 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK
, GEN6_WIZ_HASHING_16x4
));
6388 ilk_init_lp_watermarks(dev
);
6390 I915_WRITE(CACHE_MODE_0
,
6391 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB
));
6393 I915_WRITE(GEN6_UCGCTL1
,
6394 I915_READ(GEN6_UCGCTL1
) |
6395 GEN6_BLBUNIT_CLOCK_GATE_DISABLE
|
6396 GEN6_CSUNIT_CLOCK_GATE_DISABLE
);
6398 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
6399 * gating disable must be set. Failure to set it results in
6400 * flickering pixels due to Z write ordering failures after
6401 * some amount of runtime in the Mesa "fire" demo, and Unigine
6402 * Sanctuary and Tropics, and apparently anything else with
6403 * alpha test or pixel discard.
6405 * According to the spec, bit 11 (RCCUNIT) must also be set,
6406 * but we didn't debug actual testcases to find it out.
6408 * WaDisableRCCUnitClockGating:snb
6409 * WaDisableRCPBUnitClockGating:snb
6411 I915_WRITE(GEN6_UCGCTL2
,
6412 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE
|
6413 GEN6_RCCUNIT_CLOCK_GATE_DISABLE
);
6415 /* WaStripsFansDisableFastClipPerformanceFix:snb */
6416 I915_WRITE(_3D_CHICKEN3
,
6417 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL
));
6421 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
6422 * 3DSTATE_SF number of SF output attributes is more than 16."
6424 I915_WRITE(_3D_CHICKEN3
,
6425 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH
));
6428 * According to the spec the following bits should be
6429 * set in order to enable memory self-refresh and fbc:
6430 * The bit21 and bit22 of 0x42000
6431 * The bit21 and bit22 of 0x42004
6432 * The bit5 and bit7 of 0x42020
6433 * The bit14 of 0x70180
6434 * The bit14 of 0x71180
6436 * WaFbcAsynchFlipDisableFbcQueue:snb
6438 I915_WRITE(ILK_DISPLAY_CHICKEN1
,
6439 I915_READ(ILK_DISPLAY_CHICKEN1
) |
6440 ILK_FBCQ_DIS
| ILK_PABSTRETCH_DIS
);
6441 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
6442 I915_READ(ILK_DISPLAY_CHICKEN2
) |
6443 ILK_DPARB_GATE
| ILK_VSDPFD_FULL
);
6444 I915_WRITE(ILK_DSPCLK_GATE_D
,
6445 I915_READ(ILK_DSPCLK_GATE_D
) |
6446 ILK_DPARBUNIT_CLOCK_GATE_ENABLE
|
6447 ILK_DPFDUNIT_CLOCK_GATE_ENABLE
);
6449 g4x_disable_trickle_feed(dev
);
6451 cpt_init_clock_gating(dev
);
6453 gen6_check_mch_setup(dev
);
6456 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private
*dev_priv
)
6458 uint32_t reg
= I915_READ(GEN7_FF_THREAD_MODE
);
6461 * WaVSThreadDispatchOverride:ivb,vlv
6463 * This actually overrides the dispatch
6464 * mode for all thread types.
6466 reg
&= ~GEN7_FF_SCHED_MASK
;
6467 reg
|= GEN7_FF_TS_SCHED_HW
;
6468 reg
|= GEN7_FF_VS_SCHED_HW
;
6469 reg
|= GEN7_FF_DS_SCHED_HW
;
6471 I915_WRITE(GEN7_FF_THREAD_MODE
, reg
);
6474 static void lpt_init_clock_gating(struct drm_device
*dev
)
6476 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6479 * TODO: this bit should only be enabled when really needed, then
6480 * disabled when not needed anymore in order to save power.
6482 if (HAS_PCH_LPT_LP(dev
))
6483 I915_WRITE(SOUTH_DSPCLK_GATE_D
,
6484 I915_READ(SOUTH_DSPCLK_GATE_D
) |
6485 PCH_LP_PARTITION_LEVEL_DISABLE
);
6487 /* WADPOClockGatingDisable:hsw */
6488 I915_WRITE(TRANS_CHICKEN1(PIPE_A
),
6489 I915_READ(TRANS_CHICKEN1(PIPE_A
)) |
6490 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE
);
6493 static void lpt_suspend_hw(struct drm_device
*dev
)
6495 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6497 if (HAS_PCH_LPT_LP(dev
)) {
6498 uint32_t val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
6500 val
&= ~PCH_LP_PARTITION_LEVEL_DISABLE
;
6501 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
6505 static void broadwell_init_clock_gating(struct drm_device
*dev
)
6507 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6511 ilk_init_lp_watermarks(dev
);
6513 /* WaSwitchSolVfFArbitrationPriority:bdw */
6514 I915_WRITE(GAM_ECOCHK
, I915_READ(GAM_ECOCHK
) | HSW_ECOCHK_ARB_PRIO_SOL
);
6516 /* WaPsrDPAMaskVBlankInSRD:bdw */
6517 I915_WRITE(CHICKEN_PAR1_1
,
6518 I915_READ(CHICKEN_PAR1_1
) | DPA_MASK_VBLANK_SRD
);
6520 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
6521 for_each_pipe(dev_priv
, pipe
) {
6522 I915_WRITE(CHICKEN_PIPESL_1(pipe
),
6523 I915_READ(CHICKEN_PIPESL_1(pipe
)) |
6524 BDW_DPRS_MASK_VBLANK_SRD
);
6527 /* WaVSRefCountFullforceMissDisable:bdw */
6528 /* WaDSRefCountFullforceMissDisable:bdw */
6529 I915_WRITE(GEN7_FF_THREAD_MODE
,
6530 I915_READ(GEN7_FF_THREAD_MODE
) &
6531 ~(GEN8_FF_DS_REF_CNT_FFME
| GEN7_FF_VS_REF_CNT_FFME
));
6533 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL
,
6534 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE
));
6536 /* WaDisableSDEUnitClockGating:bdw */
6537 I915_WRITE(GEN8_UCGCTL6
, I915_READ(GEN8_UCGCTL6
) |
6538 GEN8_SDEUNIT_CLOCK_GATE_DISABLE
);
6541 * WaProgramL3SqcReg1Default:bdw
6542 * WaTempDisableDOPClkGating:bdw
6544 misccpctl
= I915_READ(GEN7_MISCCPCTL
);
6545 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
& ~GEN7_DOP_CLOCK_GATE_ENABLE
);
6546 I915_WRITE(GEN8_L3SQCREG1
, BDW_WA_L3SQCREG1_DEFAULT
);
6547 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
);
6550 * WaGttCachingOffByDefault:bdw
6551 * GTT cache may not work with big pages, so if those
6552 * are ever enabled GTT cache may need to be disabled.
6554 I915_WRITE(HSW_GTT_CACHE_EN
, GTT_CACHE_EN_ALL
);
6556 lpt_init_clock_gating(dev
);
6559 static void haswell_init_clock_gating(struct drm_device
*dev
)
6561 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6563 ilk_init_lp_watermarks(dev
);
6565 /* L3 caching of data atomics doesn't work -- disable it. */
6566 I915_WRITE(HSW_SCRATCH1
, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE
);
6567 I915_WRITE(HSW_ROW_CHICKEN3
,
6568 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE
));
6570 /* This is required by WaCatErrorRejectionIssue:hsw */
6571 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
6572 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
6573 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
6575 /* WaVSRefCountFullforceMissDisable:hsw */
6576 I915_WRITE(GEN7_FF_THREAD_MODE
,
6577 I915_READ(GEN7_FF_THREAD_MODE
) & ~GEN7_FF_VS_REF_CNT_FFME
);
6579 /* WaDisable_RenderCache_OperationalFlush:hsw */
6580 I915_WRITE(CACHE_MODE_0_GEN7
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
6582 /* enable HiZ Raw Stall Optimization */
6583 I915_WRITE(CACHE_MODE_0_GEN7
,
6584 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE
));
6586 /* WaDisable4x2SubspanOptimization:hsw */
6587 I915_WRITE(CACHE_MODE_1
,
6588 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
));
6591 * BSpec recommends 8x4 when MSAA is used,
6592 * however in practice 16x4 seems fastest.
6594 * Note that PS/WM thread counts depend on the WIZ hashing
6595 * disable bit, which we don't touch here, but it's good
6596 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6598 I915_WRITE(GEN7_GT_MODE
,
6599 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK
, GEN6_WIZ_HASHING_16x4
));
6601 /* WaSampleCChickenBitEnable:hsw */
6602 I915_WRITE(HALF_SLICE_CHICKEN3
,
6603 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE
));
6605 /* WaSwitchSolVfFArbitrationPriority:hsw */
6606 I915_WRITE(GAM_ECOCHK
, I915_READ(GAM_ECOCHK
) | HSW_ECOCHK_ARB_PRIO_SOL
);
6608 /* WaRsPkgCStateDisplayPMReq:hsw */
6609 I915_WRITE(CHICKEN_PAR1_1
,
6610 I915_READ(CHICKEN_PAR1_1
) | FORCE_ARB_IDLE_PLANES
);
6612 lpt_init_clock_gating(dev
);
6615 static void ivybridge_init_clock_gating(struct drm_device
*dev
)
6617 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6620 ilk_init_lp_watermarks(dev
);
6622 I915_WRITE(ILK_DSPCLK_GATE_D
, ILK_VRHUNIT_CLOCK_GATE_DISABLE
);
6624 /* WaDisableEarlyCull:ivb */
6625 I915_WRITE(_3D_CHICKEN3
,
6626 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL
));
6628 /* WaDisableBackToBackFlipFix:ivb */
6629 I915_WRITE(IVB_CHICKEN3
,
6630 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE
|
6631 CHICKEN3_DGMG_DONE_FIX_DISABLE
);
6633 /* WaDisablePSDDualDispatchEnable:ivb */
6634 if (IS_IVB_GT1(dev
))
6635 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1
,
6636 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE
));
6638 /* WaDisable_RenderCache_OperationalFlush:ivb */
6639 I915_WRITE(CACHE_MODE_0_GEN7
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
6641 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6642 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1
,
6643 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC
);
6645 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6646 I915_WRITE(GEN7_L3CNTLREG1
,
6647 GEN7_WA_FOR_GEN7_L3_CONTROL
);
6648 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER
,
6649 GEN7_WA_L3_CHICKEN_MODE
);
6650 if (IS_IVB_GT1(dev
))
6651 I915_WRITE(GEN7_ROW_CHICKEN2
,
6652 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
6654 /* must write both registers */
6655 I915_WRITE(GEN7_ROW_CHICKEN2
,
6656 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
6657 I915_WRITE(GEN7_ROW_CHICKEN2_GT2
,
6658 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
6661 /* WaForceL3Serialization:ivb */
6662 I915_WRITE(GEN7_L3SQCREG4
, I915_READ(GEN7_L3SQCREG4
) &
6663 ~L3SQ_URB_READ_CAM_MATCH_DISABLE
);
6666 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6667 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
6669 I915_WRITE(GEN6_UCGCTL2
,
6670 GEN6_RCZUNIT_CLOCK_GATE_DISABLE
);
6672 /* This is required by WaCatErrorRejectionIssue:ivb */
6673 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
6674 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
6675 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
6677 g4x_disable_trickle_feed(dev
);
6679 gen7_setup_fixed_func_scheduler(dev_priv
);
6681 if (0) { /* causes HiZ corruption on ivb:gt1 */
6682 /* enable HiZ Raw Stall Optimization */
6683 I915_WRITE(CACHE_MODE_0_GEN7
,
6684 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE
));
6687 /* WaDisable4x2SubspanOptimization:ivb */
6688 I915_WRITE(CACHE_MODE_1
,
6689 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
));
6692 * BSpec recommends 8x4 when MSAA is used,
6693 * however in practice 16x4 seems fastest.
6695 * Note that PS/WM thread counts depend on the WIZ hashing
6696 * disable bit, which we don't touch here, but it's good
6697 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6699 I915_WRITE(GEN7_GT_MODE
,
6700 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK
, GEN6_WIZ_HASHING_16x4
));
6702 snpcr
= I915_READ(GEN6_MBCUNIT_SNPCR
);
6703 snpcr
&= ~GEN6_MBC_SNPCR_MASK
;
6704 snpcr
|= GEN6_MBC_SNPCR_MED
;
6705 I915_WRITE(GEN6_MBCUNIT_SNPCR
, snpcr
);
6707 if (!HAS_PCH_NOP(dev
))
6708 cpt_init_clock_gating(dev
);
6710 gen6_check_mch_setup(dev
);
6713 static void vlv_init_display_clock_gating(struct drm_i915_private
*dev_priv
)
6715 I915_WRITE(DSPCLK_GATE_D
, VRHUNIT_CLOCK_GATE_DISABLE
);
6718 * Disable trickle feed and enable pnd deadline calculation
6720 I915_WRITE(MI_ARB_VLV
, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
);
6721 I915_WRITE(CBR1_VLV
, 0);
6724 static void valleyview_init_clock_gating(struct drm_device
*dev
)
6726 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6728 vlv_init_display_clock_gating(dev_priv
);
6730 /* WaDisableEarlyCull:vlv */
6731 I915_WRITE(_3D_CHICKEN3
,
6732 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL
));
6734 /* WaDisableBackToBackFlipFix:vlv */
6735 I915_WRITE(IVB_CHICKEN3
,
6736 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE
|
6737 CHICKEN3_DGMG_DONE_FIX_DISABLE
);
6739 /* WaPsdDispatchEnable:vlv */
6740 /* WaDisablePSDDualDispatchEnable:vlv */
6741 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1
,
6742 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP
|
6743 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE
));
6745 /* WaDisable_RenderCache_OperationalFlush:vlv */
6746 I915_WRITE(CACHE_MODE_0_GEN7
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
6748 /* WaForceL3Serialization:vlv */
6749 I915_WRITE(GEN7_L3SQCREG4
, I915_READ(GEN7_L3SQCREG4
) &
6750 ~L3SQ_URB_READ_CAM_MATCH_DISABLE
);
6752 /* WaDisableDopClockGating:vlv */
6753 I915_WRITE(GEN7_ROW_CHICKEN2
,
6754 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
6756 /* This is required by WaCatErrorRejectionIssue:vlv */
6757 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
6758 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
6759 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
6761 gen7_setup_fixed_func_scheduler(dev_priv
);
6764 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6765 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
6767 I915_WRITE(GEN6_UCGCTL2
,
6768 GEN6_RCZUNIT_CLOCK_GATE_DISABLE
);
6770 /* WaDisableL3Bank2xClockGate:vlv
6771 * Disabling L3 clock gating- MMIO 940c[25] = 1
6772 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
6773 I915_WRITE(GEN7_UCGCTL4
,
6774 I915_READ(GEN7_UCGCTL4
) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE
);
6777 * BSpec says this must be set, even though
6778 * WaDisable4x2SubspanOptimization isn't listed for VLV.
6780 I915_WRITE(CACHE_MODE_1
,
6781 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
));
6784 * BSpec recommends 8x4 when MSAA is used,
6785 * however in practice 16x4 seems fastest.
6787 * Note that PS/WM thread counts depend on the WIZ hashing
6788 * disable bit, which we don't touch here, but it's good
6789 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6791 I915_WRITE(GEN7_GT_MODE
,
6792 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK
, GEN6_WIZ_HASHING_16x4
));
6795 * WaIncreaseL3CreditsForVLVB0:vlv
6796 * This is the hardware default actually.
6798 I915_WRITE(GEN7_L3SQCREG1
, VLV_B0_WA_L3SQCREG1_VALUE
);
6801 * WaDisableVLVClockGating_VBIIssue:vlv
6802 * Disable clock gating on th GCFG unit to prevent a delay
6803 * in the reporting of vblank events.
6805 I915_WRITE(VLV_GUNIT_CLOCK_GATE
, GCFG_DIS
);
6808 static void cherryview_init_clock_gating(struct drm_device
*dev
)
6810 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6812 vlv_init_display_clock_gating(dev_priv
);
6814 /* WaVSRefCountFullforceMissDisable:chv */
6815 /* WaDSRefCountFullforceMissDisable:chv */
6816 I915_WRITE(GEN7_FF_THREAD_MODE
,
6817 I915_READ(GEN7_FF_THREAD_MODE
) &
6818 ~(GEN8_FF_DS_REF_CNT_FFME
| GEN7_FF_VS_REF_CNT_FFME
));
6820 /* WaDisableSemaphoreAndSyncFlipWait:chv */
6821 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL
,
6822 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE
));
6824 /* WaDisableCSUnitClockGating:chv */
6825 I915_WRITE(GEN6_UCGCTL1
, I915_READ(GEN6_UCGCTL1
) |
6826 GEN6_CSUNIT_CLOCK_GATE_DISABLE
);
6828 /* WaDisableSDEUnitClockGating:chv */
6829 I915_WRITE(GEN8_UCGCTL6
, I915_READ(GEN8_UCGCTL6
) |
6830 GEN8_SDEUNIT_CLOCK_GATE_DISABLE
);
6833 * GTT cache may not work with big pages, so if those
6834 * are ever enabled GTT cache may need to be disabled.
6836 I915_WRITE(HSW_GTT_CACHE_EN
, GTT_CACHE_EN_ALL
);
6839 static void g4x_init_clock_gating(struct drm_device
*dev
)
6841 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6842 uint32_t dspclk_gate
;
6844 I915_WRITE(RENCLK_GATE_D1
, 0);
6845 I915_WRITE(RENCLK_GATE_D2
, VF_UNIT_CLOCK_GATE_DISABLE
|
6846 GS_UNIT_CLOCK_GATE_DISABLE
|
6847 CL_UNIT_CLOCK_GATE_DISABLE
);
6848 I915_WRITE(RAMCLK_GATE_D
, 0);
6849 dspclk_gate
= VRHUNIT_CLOCK_GATE_DISABLE
|
6850 OVRUNIT_CLOCK_GATE_DISABLE
|
6851 OVCUNIT_CLOCK_GATE_DISABLE
;
6853 dspclk_gate
|= DSSUNIT_CLOCK_GATE_DISABLE
;
6854 I915_WRITE(DSPCLK_GATE_D
, dspclk_gate
);
6856 /* WaDisableRenderCachePipelinedFlush */
6857 I915_WRITE(CACHE_MODE_0
,
6858 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE
));
6860 /* WaDisable_RenderCache_OperationalFlush:g4x */
6861 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
6863 g4x_disable_trickle_feed(dev
);
6866 static void crestline_init_clock_gating(struct drm_device
*dev
)
6868 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6870 I915_WRITE(RENCLK_GATE_D1
, I965_RCC_CLOCK_GATE_DISABLE
);
6871 I915_WRITE(RENCLK_GATE_D2
, 0);
6872 I915_WRITE(DSPCLK_GATE_D
, 0);
6873 I915_WRITE(RAMCLK_GATE_D
, 0);
6874 I915_WRITE16(DEUC
, 0);
6875 I915_WRITE(MI_ARB_STATE
,
6876 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
));
6878 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6879 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
6882 static void broadwater_init_clock_gating(struct drm_device
*dev
)
6884 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6886 I915_WRITE(RENCLK_GATE_D1
, I965_RCZ_CLOCK_GATE_DISABLE
|
6887 I965_RCC_CLOCK_GATE_DISABLE
|
6888 I965_RCPB_CLOCK_GATE_DISABLE
|
6889 I965_ISC_CLOCK_GATE_DISABLE
|
6890 I965_FBC_CLOCK_GATE_DISABLE
);
6891 I915_WRITE(RENCLK_GATE_D2
, 0);
6892 I915_WRITE(MI_ARB_STATE
,
6893 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
));
6895 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6896 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
6899 static void gen3_init_clock_gating(struct drm_device
*dev
)
6901 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6902 u32 dstate
= I915_READ(D_STATE
);
6904 dstate
|= DSTATE_PLL_D3_OFF
| DSTATE_GFX_CLOCK_GATING
|
6905 DSTATE_DOT_CLOCK_GATING
;
6906 I915_WRITE(D_STATE
, dstate
);
6908 if (IS_PINEVIEW(dev
))
6909 I915_WRITE(ECOSKPD
, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY
));
6911 /* IIR "flip pending" means done if this bit is set */
6912 I915_WRITE(ECOSKPD
, _MASKED_BIT_DISABLE(ECO_FLIP_DONE
));
6914 /* interrupts should cause a wake up from C3 */
6915 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN
));
6917 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
6918 I915_WRITE(MI_ARB_STATE
, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE
));
6920 I915_WRITE(MI_ARB_STATE
,
6921 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
));
6924 static void i85x_init_clock_gating(struct drm_device
*dev
)
6926 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6928 I915_WRITE(RENCLK_GATE_D1
, SV_CLOCK_GATE_DISABLE
);
6930 /* interrupts should cause a wake up from C3 */
6931 I915_WRITE(MI_STATE
, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN
) |
6932 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE
));
6934 I915_WRITE(MEM_MODE
,
6935 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE
));
6938 static void i830_init_clock_gating(struct drm_device
*dev
)
6940 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6942 I915_WRITE(DSPCLK_GATE_D
, OVRUNIT_CLOCK_GATE_DISABLE
);
6944 I915_WRITE(MEM_MODE
,
6945 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE
) |
6946 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE
));
6949 void intel_init_clock_gating(struct drm_device
*dev
)
6951 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6953 if (dev_priv
->display
.init_clock_gating
)
6954 dev_priv
->display
.init_clock_gating(dev
);
6957 void intel_suspend_hw(struct drm_device
*dev
)
6959 if (HAS_PCH_LPT(dev
))
6960 lpt_suspend_hw(dev
);
6963 /* Set up chip specific power management-related functions */
6964 void intel_init_pm(struct drm_device
*dev
)
6966 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6968 intel_fbc_init(dev_priv
);
6971 if (IS_PINEVIEW(dev
))
6972 i915_pineview_get_mem_freq(dev
);
6973 else if (IS_GEN5(dev
))
6974 i915_ironlake_get_mem_freq(dev
);
6976 /* For FIFO watermark updates */
6977 if (INTEL_INFO(dev
)->gen
>= 9) {
6978 skl_setup_wm_latency(dev
);
6980 if (IS_BROXTON(dev
))
6981 dev_priv
->display
.init_clock_gating
=
6982 bxt_init_clock_gating
;
6983 dev_priv
->display
.update_wm
= skl_update_wm
;
6984 } else if (HAS_PCH_SPLIT(dev
)) {
6985 ilk_setup_wm_latency(dev
);
6987 if ((IS_GEN5(dev
) && dev_priv
->wm
.pri_latency
[1] &&
6988 dev_priv
->wm
.spr_latency
[1] && dev_priv
->wm
.cur_latency
[1]) ||
6989 (!IS_GEN5(dev
) && dev_priv
->wm
.pri_latency
[0] &&
6990 dev_priv
->wm
.spr_latency
[0] && dev_priv
->wm
.cur_latency
[0])) {
6991 dev_priv
->display
.update_wm
= ilk_update_wm
;
6992 dev_priv
->display
.compute_pipe_wm
= ilk_compute_pipe_wm
;
6994 DRM_DEBUG_KMS("Failed to read display plane latency. "
6999 dev_priv
->display
.init_clock_gating
= ironlake_init_clock_gating
;
7000 else if (IS_GEN6(dev
))
7001 dev_priv
->display
.init_clock_gating
= gen6_init_clock_gating
;
7002 else if (IS_IVYBRIDGE(dev
))
7003 dev_priv
->display
.init_clock_gating
= ivybridge_init_clock_gating
;
7004 else if (IS_HASWELL(dev
))
7005 dev_priv
->display
.init_clock_gating
= haswell_init_clock_gating
;
7006 else if (INTEL_INFO(dev
)->gen
== 8)
7007 dev_priv
->display
.init_clock_gating
= broadwell_init_clock_gating
;
7008 } else if (IS_CHERRYVIEW(dev
)) {
7009 vlv_setup_wm_latency(dev
);
7011 dev_priv
->display
.update_wm
= vlv_update_wm
;
7012 dev_priv
->display
.init_clock_gating
=
7013 cherryview_init_clock_gating
;
7014 } else if (IS_VALLEYVIEW(dev
)) {
7015 vlv_setup_wm_latency(dev
);
7017 dev_priv
->display
.update_wm
= vlv_update_wm
;
7018 dev_priv
->display
.init_clock_gating
=
7019 valleyview_init_clock_gating
;
7020 } else if (IS_PINEVIEW(dev
)) {
7021 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev
),
7024 dev_priv
->mem_freq
)) {
7025 DRM_INFO("failed to find known CxSR latency "
7026 "(found ddr%s fsb freq %d, mem freq %d), "
7028 (dev_priv
->is_ddr3
== 1) ? "3" : "2",
7029 dev_priv
->fsb_freq
, dev_priv
->mem_freq
);
7030 /* Disable CxSR and never update its watermark again */
7031 intel_set_memory_cxsr(dev_priv
, false);
7032 dev_priv
->display
.update_wm
= NULL
;
7034 dev_priv
->display
.update_wm
= pineview_update_wm
;
7035 dev_priv
->display
.init_clock_gating
= gen3_init_clock_gating
;
7036 } else if (IS_G4X(dev
)) {
7037 dev_priv
->display
.update_wm
= g4x_update_wm
;
7038 dev_priv
->display
.init_clock_gating
= g4x_init_clock_gating
;
7039 } else if (IS_GEN4(dev
)) {
7040 dev_priv
->display
.update_wm
= i965_update_wm
;
7041 if (IS_CRESTLINE(dev
))
7042 dev_priv
->display
.init_clock_gating
= crestline_init_clock_gating
;
7043 else if (IS_BROADWATER(dev
))
7044 dev_priv
->display
.init_clock_gating
= broadwater_init_clock_gating
;
7045 } else if (IS_GEN3(dev
)) {
7046 dev_priv
->display
.update_wm
= i9xx_update_wm
;
7047 dev_priv
->display
.get_fifo_size
= i9xx_get_fifo_size
;
7048 dev_priv
->display
.init_clock_gating
= gen3_init_clock_gating
;
7049 } else if (IS_GEN2(dev
)) {
7050 if (INTEL_INFO(dev
)->num_pipes
== 1) {
7051 dev_priv
->display
.update_wm
= i845_update_wm
;
7052 dev_priv
->display
.get_fifo_size
= i845_get_fifo_size
;
7054 dev_priv
->display
.update_wm
= i9xx_update_wm
;
7055 dev_priv
->display
.get_fifo_size
= i830_get_fifo_size
;
7058 if (IS_I85X(dev
) || IS_I865G(dev
))
7059 dev_priv
->display
.init_clock_gating
= i85x_init_clock_gating
;
7061 dev_priv
->display
.init_clock_gating
= i830_init_clock_gating
;
7063 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
7067 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u32 mbox
, u32
*val
)
7069 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
7071 if (I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) {
7072 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7076 I915_WRITE(GEN6_PCODE_DATA
, *val
);
7077 I915_WRITE(GEN6_PCODE_DATA1
, 0);
7078 I915_WRITE(GEN6_PCODE_MAILBOX
, GEN6_PCODE_READY
| mbox
);
7080 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) == 0,
7082 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox
);
7086 *val
= I915_READ(GEN6_PCODE_DATA
);
7087 I915_WRITE(GEN6_PCODE_DATA
, 0);
7092 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
, u32 mbox
, u32 val
)
7094 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
7096 if (I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) {
7097 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7101 I915_WRITE(GEN6_PCODE_DATA
, val
);
7102 I915_WRITE(GEN6_PCODE_MAILBOX
, GEN6_PCODE_READY
| mbox
);
7104 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) == 0,
7106 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox
);
7110 I915_WRITE(GEN6_PCODE_DATA
, 0);
7115 static int vlv_gpu_freq_div(unsigned int czclk_freq
)
7117 switch (czclk_freq
) {
7132 static int byt_gpu_freq(struct drm_i915_private
*dev_priv
, int val
)
7134 int div
, czclk_freq
= DIV_ROUND_CLOSEST(dev_priv
->czclk_freq
, 1000);
7136 div
= vlv_gpu_freq_div(czclk_freq
);
7140 return DIV_ROUND_CLOSEST(czclk_freq
* (val
+ 6 - 0xbd), div
);
7143 static int byt_freq_opcode(struct drm_i915_private
*dev_priv
, int val
)
7145 int mul
, czclk_freq
= DIV_ROUND_CLOSEST(dev_priv
->czclk_freq
, 1000);
7147 mul
= vlv_gpu_freq_div(czclk_freq
);
7151 return DIV_ROUND_CLOSEST(mul
* val
, czclk_freq
) + 0xbd - 6;
7154 static int chv_gpu_freq(struct drm_i915_private
*dev_priv
, int val
)
7156 int div
, czclk_freq
= DIV_ROUND_CLOSEST(dev_priv
->czclk_freq
, 1000);
7158 div
= vlv_gpu_freq_div(czclk_freq
) / 2;
7162 return DIV_ROUND_CLOSEST(czclk_freq
* val
, 2 * div
) / 2;
7165 static int chv_freq_opcode(struct drm_i915_private
*dev_priv
, int val
)
7167 int mul
, czclk_freq
= DIV_ROUND_CLOSEST(dev_priv
->czclk_freq
, 1000);
7169 mul
= vlv_gpu_freq_div(czclk_freq
) / 2;
7173 /* CHV needs even values */
7174 return DIV_ROUND_CLOSEST(val
* 2 * mul
, czclk_freq
) * 2;
7177 int intel_gpu_freq(struct drm_i915_private
*dev_priv
, int val
)
7179 if (IS_GEN9(dev_priv
->dev
))
7180 return DIV_ROUND_CLOSEST(val
* GT_FREQUENCY_MULTIPLIER
,
7182 else if (IS_CHERRYVIEW(dev_priv
->dev
))
7183 return chv_gpu_freq(dev_priv
, val
);
7184 else if (IS_VALLEYVIEW(dev_priv
->dev
))
7185 return byt_gpu_freq(dev_priv
, val
);
7187 return val
* GT_FREQUENCY_MULTIPLIER
;
7190 int intel_freq_opcode(struct drm_i915_private
*dev_priv
, int val
)
7192 if (IS_GEN9(dev_priv
->dev
))
7193 return DIV_ROUND_CLOSEST(val
* GEN9_FREQ_SCALER
,
7194 GT_FREQUENCY_MULTIPLIER
);
7195 else if (IS_CHERRYVIEW(dev_priv
->dev
))
7196 return chv_freq_opcode(dev_priv
, val
);
7197 else if (IS_VALLEYVIEW(dev_priv
->dev
))
7198 return byt_freq_opcode(dev_priv
, val
);
7200 return DIV_ROUND_CLOSEST(val
, GT_FREQUENCY_MULTIPLIER
);
7203 struct request_boost
{
7204 struct work_struct work
;
7205 struct drm_i915_gem_request
*req
;
7208 static void __intel_rps_boost_work(struct work_struct
*work
)
7210 struct request_boost
*boost
= container_of(work
, struct request_boost
, work
);
7211 struct drm_i915_gem_request
*req
= boost
->req
;
7213 if (!i915_gem_request_completed(req
, true))
7214 gen6_rps_boost(to_i915(req
->ring
->dev
), NULL
,
7215 req
->emitted_jiffies
);
7217 i915_gem_request_unreference__unlocked(req
);
7221 void intel_queue_rps_boost_for_request(struct drm_device
*dev
,
7222 struct drm_i915_gem_request
*req
)
7224 struct request_boost
*boost
;
7226 if (req
== NULL
|| INTEL_INFO(dev
)->gen
< 6)
7229 if (i915_gem_request_completed(req
, true))
7232 boost
= kmalloc(sizeof(*boost
), GFP_ATOMIC
);
7236 i915_gem_request_reference(req
);
7239 INIT_WORK(&boost
->work
, __intel_rps_boost_work
);
7240 queue_work(to_i915(dev
)->wq
, &boost
->work
);
7243 void intel_pm_setup(struct drm_device
*dev
)
7245 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7247 mutex_init(&dev_priv
->rps
.hw_lock
);
7248 spin_lock_init(&dev_priv
->rps
.client_lock
);
7250 INIT_DELAYED_WORK(&dev_priv
->rps
.delayed_resume_work
,
7251 intel_gen6_powersave_work
);
7252 INIT_LIST_HEAD(&dev_priv
->rps
.clients
);
7253 INIT_LIST_HEAD(&dev_priv
->rps
.semaphores
.link
);
7254 INIT_LIST_HEAD(&dev_priv
->rps
.mmioflips
.link
);
7256 dev_priv
->pm
.suspended
= false;
7257 atomic_set(&dev_priv
->pm
.wakeref_count
, 0);
7258 atomic_set(&dev_priv
->pm
.atomic_seq
, 0);