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drm/i915: FBC flush nuke for BDW
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_pm.c
1 /*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28 #include <linux/cpufreq.h>
29 #include "i915_drv.h"
30 #include "intel_drv.h"
31 #include "../../../platform/x86/intel_ips.h"
32 #include <linux/module.h>
33 #include <linux/vgaarb.h>
34 #include <drm/i915_powerwell.h>
35 #include <linux/pm_runtime.h>
36
37 /**
38 * RC6 is a special power stage which allows the GPU to enter an very
39 * low-voltage mode when idle, using down to 0V while at this stage. This
40 * stage is entered automatically when the GPU is idle when RC6 support is
41 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
42 *
43 * There are different RC6 modes available in Intel GPU, which differentiate
44 * among each other with the latency required to enter and leave RC6 and
45 * voltage consumed by the GPU in different states.
46 *
47 * The combination of the following flags define which states GPU is allowed
48 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
49 * RC6pp is deepest RC6. Their support by hardware varies according to the
50 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
51 * which brings the most power savings; deeper states save more power, but
52 * require higher latency to switch to and wake up.
53 */
54 #define INTEL_RC6_ENABLE (1<<0)
55 #define INTEL_RC6p_ENABLE (1<<1)
56 #define INTEL_RC6pp_ENABLE (1<<2)
57
58 /* FBC, or Frame Buffer Compression, is a technique employed to compress the
59 * framebuffer contents in-memory, aiming at reducing the required bandwidth
60 * during in-memory transfers and, therefore, reduce the power packet.
61 *
62 * The benefits of FBC are mostly visible with solid backgrounds and
63 * variation-less patterns.
64 *
65 * FBC-related functionality can be enabled by the means of the
66 * i915.i915_enable_fbc parameter
67 */
68
69 static void i8xx_disable_fbc(struct drm_device *dev)
70 {
71 struct drm_i915_private *dev_priv = dev->dev_private;
72 u32 fbc_ctl;
73
74 /* Disable compression */
75 fbc_ctl = I915_READ(FBC_CONTROL);
76 if ((fbc_ctl & FBC_CTL_EN) == 0)
77 return;
78
79 fbc_ctl &= ~FBC_CTL_EN;
80 I915_WRITE(FBC_CONTROL, fbc_ctl);
81
82 /* Wait for compressing bit to clear */
83 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
84 DRM_DEBUG_KMS("FBC idle timed out\n");
85 return;
86 }
87
88 DRM_DEBUG_KMS("disabled FBC\n");
89 }
90
91 static void i8xx_enable_fbc(struct drm_crtc *crtc)
92 {
93 struct drm_device *dev = crtc->dev;
94 struct drm_i915_private *dev_priv = dev->dev_private;
95 struct drm_framebuffer *fb = crtc->primary->fb;
96 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
97 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
98 int cfb_pitch;
99 int i;
100 u32 fbc_ctl;
101
102 cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
103 if (fb->pitches[0] < cfb_pitch)
104 cfb_pitch = fb->pitches[0];
105
106 /* FBC_CTL wants 32B or 64B units */
107 if (IS_GEN2(dev))
108 cfb_pitch = (cfb_pitch / 32) - 1;
109 else
110 cfb_pitch = (cfb_pitch / 64) - 1;
111
112 /* Clear old tags */
113 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
114 I915_WRITE(FBC_TAG + (i * 4), 0);
115
116 if (IS_GEN4(dev)) {
117 u32 fbc_ctl2;
118
119 /* Set it up... */
120 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
121 fbc_ctl2 |= FBC_CTL_PLANE(intel_crtc->plane);
122 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
123 I915_WRITE(FBC_FENCE_OFF, crtc->y);
124 }
125
126 /* enable it... */
127 fbc_ctl = I915_READ(FBC_CONTROL);
128 fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT;
129 fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
130 if (IS_I945GM(dev))
131 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
132 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
133 fbc_ctl |= obj->fence_reg;
134 I915_WRITE(FBC_CONTROL, fbc_ctl);
135
136 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c\n",
137 cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
138 }
139
140 static bool i8xx_fbc_enabled(struct drm_device *dev)
141 {
142 struct drm_i915_private *dev_priv = dev->dev_private;
143
144 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
145 }
146
147 static void g4x_enable_fbc(struct drm_crtc *crtc)
148 {
149 struct drm_device *dev = crtc->dev;
150 struct drm_i915_private *dev_priv = dev->dev_private;
151 struct drm_framebuffer *fb = crtc->primary->fb;
152 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
153 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
154 u32 dpfc_ctl;
155
156 dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane) | DPFC_SR_EN;
157 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
158 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
159 else
160 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
161 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
162
163 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
164
165 /* enable it... */
166 I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
167
168 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
169 }
170
171 static void g4x_disable_fbc(struct drm_device *dev)
172 {
173 struct drm_i915_private *dev_priv = dev->dev_private;
174 u32 dpfc_ctl;
175
176 /* Disable compression */
177 dpfc_ctl = I915_READ(DPFC_CONTROL);
178 if (dpfc_ctl & DPFC_CTL_EN) {
179 dpfc_ctl &= ~DPFC_CTL_EN;
180 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
181
182 DRM_DEBUG_KMS("disabled FBC\n");
183 }
184 }
185
186 static bool g4x_fbc_enabled(struct drm_device *dev)
187 {
188 struct drm_i915_private *dev_priv = dev->dev_private;
189
190 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
191 }
192
193 static void sandybridge_blit_fbc_update(struct drm_device *dev)
194 {
195 struct drm_i915_private *dev_priv = dev->dev_private;
196 u32 blt_ecoskpd;
197
198 /* Make sure blitter notifies FBC of writes */
199
200 /* Blitter is part of Media powerwell on VLV. No impact of
201 * his param in other platforms for now */
202 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_MEDIA);
203
204 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
205 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
206 GEN6_BLITTER_LOCK_SHIFT;
207 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
208 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
209 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
210 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
211 GEN6_BLITTER_LOCK_SHIFT);
212 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
213 POSTING_READ(GEN6_BLITTER_ECOSKPD);
214
215 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_MEDIA);
216 }
217
218 static void ironlake_enable_fbc(struct drm_crtc *crtc)
219 {
220 struct drm_device *dev = crtc->dev;
221 struct drm_i915_private *dev_priv = dev->dev_private;
222 struct drm_framebuffer *fb = crtc->primary->fb;
223 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
224 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
225 u32 dpfc_ctl;
226
227 dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane);
228 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
229 dev_priv->fbc.threshold++;
230
231 switch (dev_priv->fbc.threshold) {
232 case 4:
233 case 3:
234 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
235 break;
236 case 2:
237 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
238 break;
239 case 1:
240 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
241 break;
242 }
243 dpfc_ctl |= DPFC_CTL_FENCE_EN;
244 if (IS_GEN5(dev))
245 dpfc_ctl |= obj->fence_reg;
246
247 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
248 I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
249 /* enable it... */
250 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
251
252 if (IS_GEN6(dev)) {
253 I915_WRITE(SNB_DPFC_CTL_SA,
254 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
255 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
256 sandybridge_blit_fbc_update(dev);
257 }
258
259 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
260 }
261
262 static void ironlake_disable_fbc(struct drm_device *dev)
263 {
264 struct drm_i915_private *dev_priv = dev->dev_private;
265 u32 dpfc_ctl;
266
267 /* Disable compression */
268 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
269 if (dpfc_ctl & DPFC_CTL_EN) {
270 dpfc_ctl &= ~DPFC_CTL_EN;
271 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
272
273 DRM_DEBUG_KMS("disabled FBC\n");
274 }
275 }
276
277 static bool ironlake_fbc_enabled(struct drm_device *dev)
278 {
279 struct drm_i915_private *dev_priv = dev->dev_private;
280
281 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
282 }
283
284 static void gen7_enable_fbc(struct drm_crtc *crtc)
285 {
286 struct drm_device *dev = crtc->dev;
287 struct drm_i915_private *dev_priv = dev->dev_private;
288 struct drm_framebuffer *fb = crtc->primary->fb;
289 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
290 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
291 u32 dpfc_ctl;
292
293 dpfc_ctl = IVB_DPFC_CTL_PLANE(intel_crtc->plane);
294 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
295 dev_priv->fbc.threshold++;
296
297 switch (dev_priv->fbc.threshold) {
298 case 4:
299 case 3:
300 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
301 break;
302 case 2:
303 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
304 break;
305 case 1:
306 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
307 break;
308 }
309
310 dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
311
312 if (dev_priv->fbc.false_color)
313 dpfc_ctl |= FBC_CTL_FALSE_COLOR;
314
315 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
316
317 if (IS_IVYBRIDGE(dev)) {
318 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
319 I915_WRITE(ILK_DISPLAY_CHICKEN1,
320 I915_READ(ILK_DISPLAY_CHICKEN1) |
321 ILK_FBCQ_DIS);
322 } else {
323 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
324 I915_WRITE(CHICKEN_PIPESL_1(intel_crtc->pipe),
325 I915_READ(CHICKEN_PIPESL_1(intel_crtc->pipe)) |
326 HSW_FBCQ_DIS);
327 }
328
329 I915_WRITE(SNB_DPFC_CTL_SA,
330 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
331 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
332
333 sandybridge_blit_fbc_update(dev);
334
335 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
336 }
337
338 bool intel_fbc_enabled(struct drm_device *dev)
339 {
340 struct drm_i915_private *dev_priv = dev->dev_private;
341
342 if (!dev_priv->display.fbc_enabled)
343 return false;
344
345 return dev_priv->display.fbc_enabled(dev);
346 }
347
348 void gen8_fbc_sw_flush(struct drm_device *dev, u32 value)
349 {
350 struct drm_i915_private *dev_priv = dev->dev_private;
351
352 if (!IS_GEN8(dev))
353 return;
354
355 I915_WRITE(MSG_FBC_REND_STATE, value);
356 }
357
358 static void intel_fbc_work_fn(struct work_struct *__work)
359 {
360 struct intel_fbc_work *work =
361 container_of(to_delayed_work(__work),
362 struct intel_fbc_work, work);
363 struct drm_device *dev = work->crtc->dev;
364 struct drm_i915_private *dev_priv = dev->dev_private;
365
366 mutex_lock(&dev->struct_mutex);
367 if (work == dev_priv->fbc.fbc_work) {
368 /* Double check that we haven't switched fb without cancelling
369 * the prior work.
370 */
371 if (work->crtc->primary->fb == work->fb) {
372 dev_priv->display.enable_fbc(work->crtc);
373
374 dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;
375 dev_priv->fbc.fb_id = work->crtc->primary->fb->base.id;
376 dev_priv->fbc.y = work->crtc->y;
377 }
378
379 dev_priv->fbc.fbc_work = NULL;
380 }
381 mutex_unlock(&dev->struct_mutex);
382
383 kfree(work);
384 }
385
386 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
387 {
388 if (dev_priv->fbc.fbc_work == NULL)
389 return;
390
391 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
392
393 /* Synchronisation is provided by struct_mutex and checking of
394 * dev_priv->fbc.fbc_work, so we can perform the cancellation
395 * entirely asynchronously.
396 */
397 if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
398 /* tasklet was killed before being run, clean up */
399 kfree(dev_priv->fbc.fbc_work);
400
401 /* Mark the work as no longer wanted so that if it does
402 * wake-up (because the work was already running and waiting
403 * for our mutex), it will discover that is no longer
404 * necessary to run.
405 */
406 dev_priv->fbc.fbc_work = NULL;
407 }
408
409 static void intel_enable_fbc(struct drm_crtc *crtc)
410 {
411 struct intel_fbc_work *work;
412 struct drm_device *dev = crtc->dev;
413 struct drm_i915_private *dev_priv = dev->dev_private;
414
415 if (!dev_priv->display.enable_fbc)
416 return;
417
418 intel_cancel_fbc_work(dev_priv);
419
420 work = kzalloc(sizeof(*work), GFP_KERNEL);
421 if (work == NULL) {
422 DRM_ERROR("Failed to allocate FBC work structure\n");
423 dev_priv->display.enable_fbc(crtc);
424 return;
425 }
426
427 work->crtc = crtc;
428 work->fb = crtc->primary->fb;
429 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
430
431 dev_priv->fbc.fbc_work = work;
432
433 /* Delay the actual enabling to let pageflipping cease and the
434 * display to settle before starting the compression. Note that
435 * this delay also serves a second purpose: it allows for a
436 * vblank to pass after disabling the FBC before we attempt
437 * to modify the control registers.
438 *
439 * A more complicated solution would involve tracking vblanks
440 * following the termination of the page-flipping sequence
441 * and indeed performing the enable as a co-routine and not
442 * waiting synchronously upon the vblank.
443 *
444 * WaFbcWaitForVBlankBeforeEnable:ilk,snb
445 */
446 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
447 }
448
449 void intel_disable_fbc(struct drm_device *dev)
450 {
451 struct drm_i915_private *dev_priv = dev->dev_private;
452
453 intel_cancel_fbc_work(dev_priv);
454
455 if (!dev_priv->display.disable_fbc)
456 return;
457
458 dev_priv->display.disable_fbc(dev);
459 dev_priv->fbc.plane = -1;
460 }
461
462 static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
463 enum no_fbc_reason reason)
464 {
465 if (dev_priv->fbc.no_fbc_reason == reason)
466 return false;
467
468 dev_priv->fbc.no_fbc_reason = reason;
469 return true;
470 }
471
472 /**
473 * intel_update_fbc - enable/disable FBC as needed
474 * @dev: the drm_device
475 *
476 * Set up the framebuffer compression hardware at mode set time. We
477 * enable it if possible:
478 * - plane A only (on pre-965)
479 * - no pixel mulitply/line duplication
480 * - no alpha buffer discard
481 * - no dual wide
482 * - framebuffer <= max_hdisplay in width, max_vdisplay in height
483 *
484 * We can't assume that any compression will take place (worst case),
485 * so the compressed buffer has to be the same size as the uncompressed
486 * one. It also must reside (along with the line length buffer) in
487 * stolen memory.
488 *
489 * We need to enable/disable FBC on a global basis.
490 */
491 void intel_update_fbc(struct drm_device *dev)
492 {
493 struct drm_i915_private *dev_priv = dev->dev_private;
494 struct drm_crtc *crtc = NULL, *tmp_crtc;
495 struct intel_crtc *intel_crtc;
496 struct drm_framebuffer *fb;
497 struct drm_i915_gem_object *obj;
498 const struct drm_display_mode *adjusted_mode;
499 unsigned int max_width, max_height;
500
501 if (!HAS_FBC(dev)) {
502 set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED);
503 return;
504 }
505
506 if (!i915.powersave) {
507 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
508 DRM_DEBUG_KMS("fbc disabled per module param\n");
509 return;
510 }
511
512 /*
513 * If FBC is already on, we just have to verify that we can
514 * keep it that way...
515 * Need to disable if:
516 * - more than one pipe is active
517 * - changing FBC params (stride, fence, mode)
518 * - new fb is too large to fit in compressed buffer
519 * - going to an unsupported config (interlace, pixel multiply, etc.)
520 */
521 for_each_crtc(dev, tmp_crtc) {
522 if (intel_crtc_active(tmp_crtc) &&
523 to_intel_crtc(tmp_crtc)->primary_enabled) {
524 if (crtc) {
525 if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
526 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
527 goto out_disable;
528 }
529 crtc = tmp_crtc;
530 }
531 }
532
533 if (!crtc || crtc->primary->fb == NULL) {
534 if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
535 DRM_DEBUG_KMS("no output, disabling\n");
536 goto out_disable;
537 }
538
539 intel_crtc = to_intel_crtc(crtc);
540 fb = crtc->primary->fb;
541 obj = intel_fb_obj(fb);
542 adjusted_mode = &intel_crtc->config.adjusted_mode;
543
544 if (i915.enable_fbc < 0) {
545 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
546 DRM_DEBUG_KMS("disabled per chip default\n");
547 goto out_disable;
548 }
549 if (!i915.enable_fbc) {
550 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
551 DRM_DEBUG_KMS("fbc disabled per module param\n");
552 goto out_disable;
553 }
554 if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ||
555 (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
556 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
557 DRM_DEBUG_KMS("mode incompatible with compression, "
558 "disabling\n");
559 goto out_disable;
560 }
561
562 if (INTEL_INFO(dev)->gen >= 8 || IS_HASWELL(dev)) {
563 max_width = 4096;
564 max_height = 4096;
565 } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
566 max_width = 4096;
567 max_height = 2048;
568 } else {
569 max_width = 2048;
570 max_height = 1536;
571 }
572 if (intel_crtc->config.pipe_src_w > max_width ||
573 intel_crtc->config.pipe_src_h > max_height) {
574 if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
575 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
576 goto out_disable;
577 }
578 if ((INTEL_INFO(dev)->gen < 4 || HAS_DDI(dev)) &&
579 intel_crtc->plane != PLANE_A) {
580 if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
581 DRM_DEBUG_KMS("plane not A, disabling compression\n");
582 goto out_disable;
583 }
584
585 /* The use of a CPU fence is mandatory in order to detect writes
586 * by the CPU to the scanout and trigger updates to the FBC.
587 */
588 if (obj->tiling_mode != I915_TILING_X ||
589 obj->fence_reg == I915_FENCE_REG_NONE) {
590 if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED))
591 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
592 goto out_disable;
593 }
594 if (INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
595 to_intel_plane(crtc->primary)->rotation != BIT(DRM_ROTATE_0)) {
596 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
597 DRM_DEBUG_KMS("Rotation unsupported, disabling\n");
598 goto out_disable;
599 }
600
601 /* If the kernel debugger is active, always disable compression */
602 if (in_dbg_master())
603 goto out_disable;
604
605 if (i915_gem_stolen_setup_compression(dev, obj->base.size,
606 drm_format_plane_cpp(fb->pixel_format, 0))) {
607 if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL))
608 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
609 goto out_disable;
610 }
611
612 /* If the scanout has not changed, don't modify the FBC settings.
613 * Note that we make the fundamental assumption that the fb->obj
614 * cannot be unpinned (and have its GTT offset and fence revoked)
615 * without first being decoupled from the scanout and FBC disabled.
616 */
617 if (dev_priv->fbc.plane == intel_crtc->plane &&
618 dev_priv->fbc.fb_id == fb->base.id &&
619 dev_priv->fbc.y == crtc->y)
620 return;
621
622 if (intel_fbc_enabled(dev)) {
623 /* We update FBC along two paths, after changing fb/crtc
624 * configuration (modeswitching) and after page-flipping
625 * finishes. For the latter, we know that not only did
626 * we disable the FBC at the start of the page-flip
627 * sequence, but also more than one vblank has passed.
628 *
629 * For the former case of modeswitching, it is possible
630 * to switch between two FBC valid configurations
631 * instantaneously so we do need to disable the FBC
632 * before we can modify its control registers. We also
633 * have to wait for the next vblank for that to take
634 * effect. However, since we delay enabling FBC we can
635 * assume that a vblank has passed since disabling and
636 * that we can safely alter the registers in the deferred
637 * callback.
638 *
639 * In the scenario that we go from a valid to invalid
640 * and then back to valid FBC configuration we have
641 * no strict enforcement that a vblank occurred since
642 * disabling the FBC. However, along all current pipe
643 * disabling paths we do need to wait for a vblank at
644 * some point. And we wait before enabling FBC anyway.
645 */
646 DRM_DEBUG_KMS("disabling active FBC for update\n");
647 intel_disable_fbc(dev);
648 }
649
650 intel_enable_fbc(crtc);
651 dev_priv->fbc.no_fbc_reason = FBC_OK;
652 return;
653
654 out_disable:
655 /* Multiple disables should be harmless */
656 if (intel_fbc_enabled(dev)) {
657 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
658 intel_disable_fbc(dev);
659 }
660 i915_gem_stolen_cleanup_compression(dev);
661 }
662
663 static void i915_pineview_get_mem_freq(struct drm_device *dev)
664 {
665 struct drm_i915_private *dev_priv = dev->dev_private;
666 u32 tmp;
667
668 tmp = I915_READ(CLKCFG);
669
670 switch (tmp & CLKCFG_FSB_MASK) {
671 case CLKCFG_FSB_533:
672 dev_priv->fsb_freq = 533; /* 133*4 */
673 break;
674 case CLKCFG_FSB_800:
675 dev_priv->fsb_freq = 800; /* 200*4 */
676 break;
677 case CLKCFG_FSB_667:
678 dev_priv->fsb_freq = 667; /* 167*4 */
679 break;
680 case CLKCFG_FSB_400:
681 dev_priv->fsb_freq = 400; /* 100*4 */
682 break;
683 }
684
685 switch (tmp & CLKCFG_MEM_MASK) {
686 case CLKCFG_MEM_533:
687 dev_priv->mem_freq = 533;
688 break;
689 case CLKCFG_MEM_667:
690 dev_priv->mem_freq = 667;
691 break;
692 case CLKCFG_MEM_800:
693 dev_priv->mem_freq = 800;
694 break;
695 }
696
697 /* detect pineview DDR3 setting */
698 tmp = I915_READ(CSHRDDR3CTL);
699 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
700 }
701
702 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
703 {
704 struct drm_i915_private *dev_priv = dev->dev_private;
705 u16 ddrpll, csipll;
706
707 ddrpll = I915_READ16(DDRMPLL1);
708 csipll = I915_READ16(CSIPLL0);
709
710 switch (ddrpll & 0xff) {
711 case 0xc:
712 dev_priv->mem_freq = 800;
713 break;
714 case 0x10:
715 dev_priv->mem_freq = 1066;
716 break;
717 case 0x14:
718 dev_priv->mem_freq = 1333;
719 break;
720 case 0x18:
721 dev_priv->mem_freq = 1600;
722 break;
723 default:
724 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
725 ddrpll & 0xff);
726 dev_priv->mem_freq = 0;
727 break;
728 }
729
730 dev_priv->ips.r_t = dev_priv->mem_freq;
731
732 switch (csipll & 0x3ff) {
733 case 0x00c:
734 dev_priv->fsb_freq = 3200;
735 break;
736 case 0x00e:
737 dev_priv->fsb_freq = 3733;
738 break;
739 case 0x010:
740 dev_priv->fsb_freq = 4266;
741 break;
742 case 0x012:
743 dev_priv->fsb_freq = 4800;
744 break;
745 case 0x014:
746 dev_priv->fsb_freq = 5333;
747 break;
748 case 0x016:
749 dev_priv->fsb_freq = 5866;
750 break;
751 case 0x018:
752 dev_priv->fsb_freq = 6400;
753 break;
754 default:
755 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
756 csipll & 0x3ff);
757 dev_priv->fsb_freq = 0;
758 break;
759 }
760
761 if (dev_priv->fsb_freq == 3200) {
762 dev_priv->ips.c_m = 0;
763 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
764 dev_priv->ips.c_m = 1;
765 } else {
766 dev_priv->ips.c_m = 2;
767 }
768 }
769
770 static const struct cxsr_latency cxsr_latency_table[] = {
771 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
772 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
773 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
774 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
775 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
776
777 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
778 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
779 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
780 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
781 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
782
783 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
784 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
785 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
786 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
787 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
788
789 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
790 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
791 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
792 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
793 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
794
795 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
796 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
797 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
798 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
799 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
800
801 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
802 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
803 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
804 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
805 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
806 };
807
808 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
809 int is_ddr3,
810 int fsb,
811 int mem)
812 {
813 const struct cxsr_latency *latency;
814 int i;
815
816 if (fsb == 0 || mem == 0)
817 return NULL;
818
819 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
820 latency = &cxsr_latency_table[i];
821 if (is_desktop == latency->is_desktop &&
822 is_ddr3 == latency->is_ddr3 &&
823 fsb == latency->fsb_freq && mem == latency->mem_freq)
824 return latency;
825 }
826
827 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
828
829 return NULL;
830 }
831
832 void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
833 {
834 struct drm_device *dev = dev_priv->dev;
835 u32 val;
836
837 if (IS_VALLEYVIEW(dev)) {
838 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
839 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
840 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
841 } else if (IS_PINEVIEW(dev)) {
842 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
843 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
844 I915_WRITE(DSPFW3, val);
845 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
846 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
847 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
848 I915_WRITE(FW_BLC_SELF, val);
849 } else if (IS_I915GM(dev)) {
850 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
851 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
852 I915_WRITE(INSTPM, val);
853 } else {
854 return;
855 }
856
857 DRM_DEBUG_KMS("memory self-refresh is %s\n",
858 enable ? "enabled" : "disabled");
859 }
860
861 /*
862 * Latency for FIFO fetches is dependent on several factors:
863 * - memory configuration (speed, channels)
864 * - chipset
865 * - current MCH state
866 * It can be fairly high in some situations, so here we assume a fairly
867 * pessimal value. It's a tradeoff between extra memory fetches (if we
868 * set this value too high, the FIFO will fetch frequently to stay full)
869 * and power consumption (set it too low to save power and we might see
870 * FIFO underruns and display "flicker").
871 *
872 * A value of 5us seems to be a good balance; safe for very low end
873 * platforms but not overly aggressive on lower latency configs.
874 */
875 static const int latency_ns = 5000;
876
877 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
878 {
879 struct drm_i915_private *dev_priv = dev->dev_private;
880 uint32_t dsparb = I915_READ(DSPARB);
881 int size;
882
883 size = dsparb & 0x7f;
884 if (plane)
885 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
886
887 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
888 plane ? "B" : "A", size);
889
890 return size;
891 }
892
893 static int i830_get_fifo_size(struct drm_device *dev, int plane)
894 {
895 struct drm_i915_private *dev_priv = dev->dev_private;
896 uint32_t dsparb = I915_READ(DSPARB);
897 int size;
898
899 size = dsparb & 0x1ff;
900 if (plane)
901 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
902 size >>= 1; /* Convert to cachelines */
903
904 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
905 plane ? "B" : "A", size);
906
907 return size;
908 }
909
910 static int i845_get_fifo_size(struct drm_device *dev, int plane)
911 {
912 struct drm_i915_private *dev_priv = dev->dev_private;
913 uint32_t dsparb = I915_READ(DSPARB);
914 int size;
915
916 size = dsparb & 0x7f;
917 size >>= 2; /* Convert to cachelines */
918
919 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
920 plane ? "B" : "A",
921 size);
922
923 return size;
924 }
925
926 /* Pineview has different values for various configs */
927 static const struct intel_watermark_params pineview_display_wm = {
928 .fifo_size = PINEVIEW_DISPLAY_FIFO,
929 .max_wm = PINEVIEW_MAX_WM,
930 .default_wm = PINEVIEW_DFT_WM,
931 .guard_size = PINEVIEW_GUARD_WM,
932 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
933 };
934 static const struct intel_watermark_params pineview_display_hplloff_wm = {
935 .fifo_size = PINEVIEW_DISPLAY_FIFO,
936 .max_wm = PINEVIEW_MAX_WM,
937 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
938 .guard_size = PINEVIEW_GUARD_WM,
939 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
940 };
941 static const struct intel_watermark_params pineview_cursor_wm = {
942 .fifo_size = PINEVIEW_CURSOR_FIFO,
943 .max_wm = PINEVIEW_CURSOR_MAX_WM,
944 .default_wm = PINEVIEW_CURSOR_DFT_WM,
945 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
946 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
947 };
948 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
949 .fifo_size = PINEVIEW_CURSOR_FIFO,
950 .max_wm = PINEVIEW_CURSOR_MAX_WM,
951 .default_wm = PINEVIEW_CURSOR_DFT_WM,
952 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
953 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
954 };
955 static const struct intel_watermark_params g4x_wm_info = {
956 .fifo_size = G4X_FIFO_SIZE,
957 .max_wm = G4X_MAX_WM,
958 .default_wm = G4X_MAX_WM,
959 .guard_size = 2,
960 .cacheline_size = G4X_FIFO_LINE_SIZE,
961 };
962 static const struct intel_watermark_params g4x_cursor_wm_info = {
963 .fifo_size = I965_CURSOR_FIFO,
964 .max_wm = I965_CURSOR_MAX_WM,
965 .default_wm = I965_CURSOR_DFT_WM,
966 .guard_size = 2,
967 .cacheline_size = G4X_FIFO_LINE_SIZE,
968 };
969 static const struct intel_watermark_params valleyview_wm_info = {
970 .fifo_size = VALLEYVIEW_FIFO_SIZE,
971 .max_wm = VALLEYVIEW_MAX_WM,
972 .default_wm = VALLEYVIEW_MAX_WM,
973 .guard_size = 2,
974 .cacheline_size = G4X_FIFO_LINE_SIZE,
975 };
976 static const struct intel_watermark_params valleyview_cursor_wm_info = {
977 .fifo_size = I965_CURSOR_FIFO,
978 .max_wm = VALLEYVIEW_CURSOR_MAX_WM,
979 .default_wm = I965_CURSOR_DFT_WM,
980 .guard_size = 2,
981 .cacheline_size = G4X_FIFO_LINE_SIZE,
982 };
983 static const struct intel_watermark_params i965_cursor_wm_info = {
984 .fifo_size = I965_CURSOR_FIFO,
985 .max_wm = I965_CURSOR_MAX_WM,
986 .default_wm = I965_CURSOR_DFT_WM,
987 .guard_size = 2,
988 .cacheline_size = I915_FIFO_LINE_SIZE,
989 };
990 static const struct intel_watermark_params i945_wm_info = {
991 .fifo_size = I945_FIFO_SIZE,
992 .max_wm = I915_MAX_WM,
993 .default_wm = 1,
994 .guard_size = 2,
995 .cacheline_size = I915_FIFO_LINE_SIZE,
996 };
997 static const struct intel_watermark_params i915_wm_info = {
998 .fifo_size = I915_FIFO_SIZE,
999 .max_wm = I915_MAX_WM,
1000 .default_wm = 1,
1001 .guard_size = 2,
1002 .cacheline_size = I915_FIFO_LINE_SIZE,
1003 };
1004 static const struct intel_watermark_params i830_wm_info = {
1005 .fifo_size = I855GM_FIFO_SIZE,
1006 .max_wm = I915_MAX_WM,
1007 .default_wm = 1,
1008 .guard_size = 2,
1009 .cacheline_size = I830_FIFO_LINE_SIZE,
1010 };
1011 static const struct intel_watermark_params i845_wm_info = {
1012 .fifo_size = I830_FIFO_SIZE,
1013 .max_wm = I915_MAX_WM,
1014 .default_wm = 1,
1015 .guard_size = 2,
1016 .cacheline_size = I830_FIFO_LINE_SIZE,
1017 };
1018
1019 /**
1020 * intel_calculate_wm - calculate watermark level
1021 * @clock_in_khz: pixel clock
1022 * @wm: chip FIFO params
1023 * @pixel_size: display pixel size
1024 * @latency_ns: memory latency for the platform
1025 *
1026 * Calculate the watermark level (the level at which the display plane will
1027 * start fetching from memory again). Each chip has a different display
1028 * FIFO size and allocation, so the caller needs to figure that out and pass
1029 * in the correct intel_watermark_params structure.
1030 *
1031 * As the pixel clock runs, the FIFO will be drained at a rate that depends
1032 * on the pixel size. When it reaches the watermark level, it'll start
1033 * fetching FIFO line sized based chunks from memory until the FIFO fills
1034 * past the watermark point. If the FIFO drains completely, a FIFO underrun
1035 * will occur, and a display engine hang could result.
1036 */
1037 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
1038 const struct intel_watermark_params *wm,
1039 int fifo_size,
1040 int pixel_size,
1041 unsigned long latency_ns)
1042 {
1043 long entries_required, wm_size;
1044
1045 /*
1046 * Note: we need to make sure we don't overflow for various clock &
1047 * latency values.
1048 * clocks go from a few thousand to several hundred thousand.
1049 * latency is usually a few thousand
1050 */
1051 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
1052 1000;
1053 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
1054
1055 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
1056
1057 wm_size = fifo_size - (entries_required + wm->guard_size);
1058
1059 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
1060
1061 /* Don't promote wm_size to unsigned... */
1062 if (wm_size > (long)wm->max_wm)
1063 wm_size = wm->max_wm;
1064 if (wm_size <= 0)
1065 wm_size = wm->default_wm;
1066 return wm_size;
1067 }
1068
1069 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1070 {
1071 struct drm_crtc *crtc, *enabled = NULL;
1072
1073 for_each_crtc(dev, crtc) {
1074 if (intel_crtc_active(crtc)) {
1075 if (enabled)
1076 return NULL;
1077 enabled = crtc;
1078 }
1079 }
1080
1081 return enabled;
1082 }
1083
1084 static void pineview_update_wm(struct drm_crtc *unused_crtc)
1085 {
1086 struct drm_device *dev = unused_crtc->dev;
1087 struct drm_i915_private *dev_priv = dev->dev_private;
1088 struct drm_crtc *crtc;
1089 const struct cxsr_latency *latency;
1090 u32 reg;
1091 unsigned long wm;
1092
1093 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1094 dev_priv->fsb_freq, dev_priv->mem_freq);
1095 if (!latency) {
1096 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1097 intel_set_memory_cxsr(dev_priv, false);
1098 return;
1099 }
1100
1101 crtc = single_enabled_crtc(dev);
1102 if (crtc) {
1103 const struct drm_display_mode *adjusted_mode;
1104 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1105 int clock;
1106
1107 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1108 clock = adjusted_mode->crtc_clock;
1109
1110 /* Display SR */
1111 wm = intel_calculate_wm(clock, &pineview_display_wm,
1112 pineview_display_wm.fifo_size,
1113 pixel_size, latency->display_sr);
1114 reg = I915_READ(DSPFW1);
1115 reg &= ~DSPFW_SR_MASK;
1116 reg |= wm << DSPFW_SR_SHIFT;
1117 I915_WRITE(DSPFW1, reg);
1118 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1119
1120 /* cursor SR */
1121 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1122 pineview_display_wm.fifo_size,
1123 pixel_size, latency->cursor_sr);
1124 reg = I915_READ(DSPFW3);
1125 reg &= ~DSPFW_CURSOR_SR_MASK;
1126 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1127 I915_WRITE(DSPFW3, reg);
1128
1129 /* Display HPLL off SR */
1130 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1131 pineview_display_hplloff_wm.fifo_size,
1132 pixel_size, latency->display_hpll_disable);
1133 reg = I915_READ(DSPFW3);
1134 reg &= ~DSPFW_HPLL_SR_MASK;
1135 reg |= wm & DSPFW_HPLL_SR_MASK;
1136 I915_WRITE(DSPFW3, reg);
1137
1138 /* cursor HPLL off SR */
1139 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1140 pineview_display_hplloff_wm.fifo_size,
1141 pixel_size, latency->cursor_hpll_disable);
1142 reg = I915_READ(DSPFW3);
1143 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1144 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1145 I915_WRITE(DSPFW3, reg);
1146 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1147
1148 intel_set_memory_cxsr(dev_priv, true);
1149 } else {
1150 intel_set_memory_cxsr(dev_priv, false);
1151 }
1152 }
1153
1154 static bool g4x_compute_wm0(struct drm_device *dev,
1155 int plane,
1156 const struct intel_watermark_params *display,
1157 int display_latency_ns,
1158 const struct intel_watermark_params *cursor,
1159 int cursor_latency_ns,
1160 int *plane_wm,
1161 int *cursor_wm)
1162 {
1163 struct drm_crtc *crtc;
1164 const struct drm_display_mode *adjusted_mode;
1165 int htotal, hdisplay, clock, pixel_size;
1166 int line_time_us, line_count;
1167 int entries, tlb_miss;
1168
1169 crtc = intel_get_crtc_for_plane(dev, plane);
1170 if (!intel_crtc_active(crtc)) {
1171 *cursor_wm = cursor->guard_size;
1172 *plane_wm = display->guard_size;
1173 return false;
1174 }
1175
1176 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1177 clock = adjusted_mode->crtc_clock;
1178 htotal = adjusted_mode->crtc_htotal;
1179 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1180 pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1181
1182 /* Use the small buffer method to calculate plane watermark */
1183 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1184 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1185 if (tlb_miss > 0)
1186 entries += tlb_miss;
1187 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1188 *plane_wm = entries + display->guard_size;
1189 if (*plane_wm > (int)display->max_wm)
1190 *plane_wm = display->max_wm;
1191
1192 /* Use the large buffer method to calculate cursor watermark */
1193 line_time_us = max(htotal * 1000 / clock, 1);
1194 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1195 entries = line_count * to_intel_crtc(crtc)->cursor_width * pixel_size;
1196 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1197 if (tlb_miss > 0)
1198 entries += tlb_miss;
1199 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1200 *cursor_wm = entries + cursor->guard_size;
1201 if (*cursor_wm > (int)cursor->max_wm)
1202 *cursor_wm = (int)cursor->max_wm;
1203
1204 return true;
1205 }
1206
1207 /*
1208 * Check the wm result.
1209 *
1210 * If any calculated watermark values is larger than the maximum value that
1211 * can be programmed into the associated watermark register, that watermark
1212 * must be disabled.
1213 */
1214 static bool g4x_check_srwm(struct drm_device *dev,
1215 int display_wm, int cursor_wm,
1216 const struct intel_watermark_params *display,
1217 const struct intel_watermark_params *cursor)
1218 {
1219 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1220 display_wm, cursor_wm);
1221
1222 if (display_wm > display->max_wm) {
1223 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1224 display_wm, display->max_wm);
1225 return false;
1226 }
1227
1228 if (cursor_wm > cursor->max_wm) {
1229 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1230 cursor_wm, cursor->max_wm);
1231 return false;
1232 }
1233
1234 if (!(display_wm || cursor_wm)) {
1235 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1236 return false;
1237 }
1238
1239 return true;
1240 }
1241
1242 static bool g4x_compute_srwm(struct drm_device *dev,
1243 int plane,
1244 int latency_ns,
1245 const struct intel_watermark_params *display,
1246 const struct intel_watermark_params *cursor,
1247 int *display_wm, int *cursor_wm)
1248 {
1249 struct drm_crtc *crtc;
1250 const struct drm_display_mode *adjusted_mode;
1251 int hdisplay, htotal, pixel_size, clock;
1252 unsigned long line_time_us;
1253 int line_count, line_size;
1254 int small, large;
1255 int entries;
1256
1257 if (!latency_ns) {
1258 *display_wm = *cursor_wm = 0;
1259 return false;
1260 }
1261
1262 crtc = intel_get_crtc_for_plane(dev, plane);
1263 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1264 clock = adjusted_mode->crtc_clock;
1265 htotal = adjusted_mode->crtc_htotal;
1266 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1267 pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1268
1269 line_time_us = max(htotal * 1000 / clock, 1);
1270 line_count = (latency_ns / line_time_us + 1000) / 1000;
1271 line_size = hdisplay * pixel_size;
1272
1273 /* Use the minimum of the small and large buffer method for primary */
1274 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1275 large = line_count * line_size;
1276
1277 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1278 *display_wm = entries + display->guard_size;
1279
1280 /* calculate the self-refresh watermark for display cursor */
1281 entries = line_count * pixel_size * to_intel_crtc(crtc)->cursor_width;
1282 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1283 *cursor_wm = entries + cursor->guard_size;
1284
1285 return g4x_check_srwm(dev,
1286 *display_wm, *cursor_wm,
1287 display, cursor);
1288 }
1289
1290 static bool vlv_compute_drain_latency(struct drm_crtc *crtc,
1291 int pixel_size,
1292 int *prec_mult,
1293 int *drain_latency)
1294 {
1295 int entries;
1296 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
1297
1298 if (WARN(clock == 0, "Pixel clock is zero!\n"))
1299 return false;
1300
1301 if (WARN(pixel_size == 0, "Pixel size is zero!\n"))
1302 return false;
1303
1304 entries = DIV_ROUND_UP(clock, 1000) * pixel_size;
1305 *prec_mult = (entries > 128) ? DRAIN_LATENCY_PRECISION_64 :
1306 DRAIN_LATENCY_PRECISION_32;
1307 *drain_latency = (64 * (*prec_mult) * 4) / entries;
1308
1309 if (*drain_latency > DRAIN_LATENCY_MASK)
1310 *drain_latency = DRAIN_LATENCY_MASK;
1311
1312 return true;
1313 }
1314
1315 /*
1316 * Update drain latency registers of memory arbiter
1317 *
1318 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1319 * to be programmed. Each plane has a drain latency multiplier and a drain
1320 * latency value.
1321 */
1322
1323 static void vlv_update_drain_latency(struct drm_crtc *crtc)
1324 {
1325 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1326 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1327 int pixel_size;
1328 int drain_latency;
1329 enum pipe pipe = intel_crtc->pipe;
1330 int plane_prec, prec_mult, plane_dl;
1331
1332 plane_dl = I915_READ(VLV_DDL(pipe)) & ~(DDL_PLANE_PRECISION_64 |
1333 DRAIN_LATENCY_MASK | DDL_CURSOR_PRECISION_64 |
1334 (DRAIN_LATENCY_MASK << DDL_CURSOR_SHIFT));
1335
1336 if (!intel_crtc_active(crtc)) {
1337 I915_WRITE(VLV_DDL(pipe), plane_dl);
1338 return;
1339 }
1340
1341 /* Primary plane Drain Latency */
1342 pixel_size = crtc->primary->fb->bits_per_pixel / 8; /* BPP */
1343 if (vlv_compute_drain_latency(crtc, pixel_size, &prec_mult, &drain_latency)) {
1344 plane_prec = (prec_mult == DRAIN_LATENCY_PRECISION_64) ?
1345 DDL_PLANE_PRECISION_64 :
1346 DDL_PLANE_PRECISION_32;
1347 plane_dl |= plane_prec | drain_latency;
1348 }
1349
1350 /* Cursor Drain Latency
1351 * BPP is always 4 for cursor
1352 */
1353 pixel_size = 4;
1354
1355 /* Program cursor DL only if it is enabled */
1356 if (intel_crtc->cursor_base &&
1357 vlv_compute_drain_latency(crtc, pixel_size, &prec_mult, &drain_latency)) {
1358 plane_prec = (prec_mult == DRAIN_LATENCY_PRECISION_64) ?
1359 DDL_CURSOR_PRECISION_64 :
1360 DDL_CURSOR_PRECISION_32;
1361 plane_dl |= plane_prec | (drain_latency << DDL_CURSOR_SHIFT);
1362 }
1363
1364 I915_WRITE(VLV_DDL(pipe), plane_dl);
1365 }
1366
1367 #define single_plane_enabled(mask) is_power_of_2(mask)
1368
1369 static void valleyview_update_wm(struct drm_crtc *crtc)
1370 {
1371 struct drm_device *dev = crtc->dev;
1372 static const int sr_latency_ns = 12000;
1373 struct drm_i915_private *dev_priv = dev->dev_private;
1374 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1375 int plane_sr, cursor_sr;
1376 int ignore_plane_sr, ignore_cursor_sr;
1377 unsigned int enabled = 0;
1378 bool cxsr_enabled;
1379
1380 vlv_update_drain_latency(crtc);
1381
1382 if (g4x_compute_wm0(dev, PIPE_A,
1383 &valleyview_wm_info, latency_ns,
1384 &valleyview_cursor_wm_info, latency_ns,
1385 &planea_wm, &cursora_wm))
1386 enabled |= 1 << PIPE_A;
1387
1388 if (g4x_compute_wm0(dev, PIPE_B,
1389 &valleyview_wm_info, latency_ns,
1390 &valleyview_cursor_wm_info, latency_ns,
1391 &planeb_wm, &cursorb_wm))
1392 enabled |= 1 << PIPE_B;
1393
1394 if (single_plane_enabled(enabled) &&
1395 g4x_compute_srwm(dev, ffs(enabled) - 1,
1396 sr_latency_ns,
1397 &valleyview_wm_info,
1398 &valleyview_cursor_wm_info,
1399 &plane_sr, &ignore_cursor_sr) &&
1400 g4x_compute_srwm(dev, ffs(enabled) - 1,
1401 2*sr_latency_ns,
1402 &valleyview_wm_info,
1403 &valleyview_cursor_wm_info,
1404 &ignore_plane_sr, &cursor_sr)) {
1405 cxsr_enabled = true;
1406 } else {
1407 cxsr_enabled = false;
1408 intel_set_memory_cxsr(dev_priv, false);
1409 plane_sr = cursor_sr = 0;
1410 }
1411
1412 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1413 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1414 planea_wm, cursora_wm,
1415 planeb_wm, cursorb_wm,
1416 plane_sr, cursor_sr);
1417
1418 I915_WRITE(DSPFW1,
1419 (plane_sr << DSPFW_SR_SHIFT) |
1420 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1421 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1422 (planea_wm << DSPFW_PLANEA_SHIFT));
1423 I915_WRITE(DSPFW2,
1424 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1425 (cursora_wm << DSPFW_CURSORA_SHIFT));
1426 I915_WRITE(DSPFW3,
1427 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1428 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1429
1430 if (cxsr_enabled)
1431 intel_set_memory_cxsr(dev_priv, true);
1432 }
1433
1434 static void cherryview_update_wm(struct drm_crtc *crtc)
1435 {
1436 struct drm_device *dev = crtc->dev;
1437 static const int sr_latency_ns = 12000;
1438 struct drm_i915_private *dev_priv = dev->dev_private;
1439 int planea_wm, planeb_wm, planec_wm;
1440 int cursora_wm, cursorb_wm, cursorc_wm;
1441 int plane_sr, cursor_sr;
1442 int ignore_plane_sr, ignore_cursor_sr;
1443 unsigned int enabled = 0;
1444 bool cxsr_enabled;
1445
1446 vlv_update_drain_latency(crtc);
1447
1448 if (g4x_compute_wm0(dev, PIPE_A,
1449 &valleyview_wm_info, latency_ns,
1450 &valleyview_cursor_wm_info, latency_ns,
1451 &planea_wm, &cursora_wm))
1452 enabled |= 1 << PIPE_A;
1453
1454 if (g4x_compute_wm0(dev, PIPE_B,
1455 &valleyview_wm_info, latency_ns,
1456 &valleyview_cursor_wm_info, latency_ns,
1457 &planeb_wm, &cursorb_wm))
1458 enabled |= 1 << PIPE_B;
1459
1460 if (g4x_compute_wm0(dev, PIPE_C,
1461 &valleyview_wm_info, latency_ns,
1462 &valleyview_cursor_wm_info, latency_ns,
1463 &planec_wm, &cursorc_wm))
1464 enabled |= 1 << PIPE_C;
1465
1466 if (single_plane_enabled(enabled) &&
1467 g4x_compute_srwm(dev, ffs(enabled) - 1,
1468 sr_latency_ns,
1469 &valleyview_wm_info,
1470 &valleyview_cursor_wm_info,
1471 &plane_sr, &ignore_cursor_sr) &&
1472 g4x_compute_srwm(dev, ffs(enabled) - 1,
1473 2*sr_latency_ns,
1474 &valleyview_wm_info,
1475 &valleyview_cursor_wm_info,
1476 &ignore_plane_sr, &cursor_sr)) {
1477 cxsr_enabled = true;
1478 } else {
1479 cxsr_enabled = false;
1480 intel_set_memory_cxsr(dev_priv, false);
1481 plane_sr = cursor_sr = 0;
1482 }
1483
1484 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1485 "B: plane=%d, cursor=%d, C: plane=%d, cursor=%d, "
1486 "SR: plane=%d, cursor=%d\n",
1487 planea_wm, cursora_wm,
1488 planeb_wm, cursorb_wm,
1489 planec_wm, cursorc_wm,
1490 plane_sr, cursor_sr);
1491
1492 I915_WRITE(DSPFW1,
1493 (plane_sr << DSPFW_SR_SHIFT) |
1494 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1495 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1496 (planea_wm << DSPFW_PLANEA_SHIFT));
1497 I915_WRITE(DSPFW2,
1498 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1499 (cursora_wm << DSPFW_CURSORA_SHIFT));
1500 I915_WRITE(DSPFW3,
1501 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1502 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1503 I915_WRITE(DSPFW9_CHV,
1504 (I915_READ(DSPFW9_CHV) & ~(DSPFW_PLANEC_MASK |
1505 DSPFW_CURSORC_MASK)) |
1506 (planec_wm << DSPFW_PLANEC_SHIFT) |
1507 (cursorc_wm << DSPFW_CURSORC_SHIFT));
1508
1509 if (cxsr_enabled)
1510 intel_set_memory_cxsr(dev_priv, true);
1511 }
1512
1513 static void valleyview_update_sprite_wm(struct drm_plane *plane,
1514 struct drm_crtc *crtc,
1515 uint32_t sprite_width,
1516 uint32_t sprite_height,
1517 int pixel_size,
1518 bool enabled, bool scaled)
1519 {
1520 struct drm_device *dev = crtc->dev;
1521 struct drm_i915_private *dev_priv = dev->dev_private;
1522 int pipe = to_intel_plane(plane)->pipe;
1523 int sprite = to_intel_plane(plane)->plane;
1524 int drain_latency;
1525 int plane_prec;
1526 int sprite_dl;
1527 int prec_mult;
1528
1529 sprite_dl = I915_READ(VLV_DDL(pipe)) & ~(DDL_SPRITE_PRECISION_64(sprite) |
1530 (DRAIN_LATENCY_MASK << DDL_SPRITE_SHIFT(sprite)));
1531
1532 if (enabled && vlv_compute_drain_latency(crtc, pixel_size, &prec_mult,
1533 &drain_latency)) {
1534 plane_prec = (prec_mult == DRAIN_LATENCY_PRECISION_64) ?
1535 DDL_SPRITE_PRECISION_64(sprite) :
1536 DDL_SPRITE_PRECISION_32(sprite);
1537 sprite_dl |= plane_prec |
1538 (drain_latency << DDL_SPRITE_SHIFT(sprite));
1539 }
1540
1541 I915_WRITE(VLV_DDL(pipe), sprite_dl);
1542 }
1543
1544 static void g4x_update_wm(struct drm_crtc *crtc)
1545 {
1546 struct drm_device *dev = crtc->dev;
1547 static const int sr_latency_ns = 12000;
1548 struct drm_i915_private *dev_priv = dev->dev_private;
1549 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1550 int plane_sr, cursor_sr;
1551 unsigned int enabled = 0;
1552 bool cxsr_enabled;
1553
1554 if (g4x_compute_wm0(dev, PIPE_A,
1555 &g4x_wm_info, latency_ns,
1556 &g4x_cursor_wm_info, latency_ns,
1557 &planea_wm, &cursora_wm))
1558 enabled |= 1 << PIPE_A;
1559
1560 if (g4x_compute_wm0(dev, PIPE_B,
1561 &g4x_wm_info, latency_ns,
1562 &g4x_cursor_wm_info, latency_ns,
1563 &planeb_wm, &cursorb_wm))
1564 enabled |= 1 << PIPE_B;
1565
1566 if (single_plane_enabled(enabled) &&
1567 g4x_compute_srwm(dev, ffs(enabled) - 1,
1568 sr_latency_ns,
1569 &g4x_wm_info,
1570 &g4x_cursor_wm_info,
1571 &plane_sr, &cursor_sr)) {
1572 cxsr_enabled = true;
1573 } else {
1574 cxsr_enabled = false;
1575 intel_set_memory_cxsr(dev_priv, false);
1576 plane_sr = cursor_sr = 0;
1577 }
1578
1579 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1580 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1581 planea_wm, cursora_wm,
1582 planeb_wm, cursorb_wm,
1583 plane_sr, cursor_sr);
1584
1585 I915_WRITE(DSPFW1,
1586 (plane_sr << DSPFW_SR_SHIFT) |
1587 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1588 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1589 (planea_wm << DSPFW_PLANEA_SHIFT));
1590 I915_WRITE(DSPFW2,
1591 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1592 (cursora_wm << DSPFW_CURSORA_SHIFT));
1593 /* HPLL off in SR has some issues on G4x... disable it */
1594 I915_WRITE(DSPFW3,
1595 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1596 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1597
1598 if (cxsr_enabled)
1599 intel_set_memory_cxsr(dev_priv, true);
1600 }
1601
1602 static void i965_update_wm(struct drm_crtc *unused_crtc)
1603 {
1604 struct drm_device *dev = unused_crtc->dev;
1605 struct drm_i915_private *dev_priv = dev->dev_private;
1606 struct drm_crtc *crtc;
1607 int srwm = 1;
1608 int cursor_sr = 16;
1609 bool cxsr_enabled;
1610
1611 /* Calc sr entries for one plane configs */
1612 crtc = single_enabled_crtc(dev);
1613 if (crtc) {
1614 /* self-refresh has much higher latency */
1615 static const int sr_latency_ns = 12000;
1616 const struct drm_display_mode *adjusted_mode =
1617 &to_intel_crtc(crtc)->config.adjusted_mode;
1618 int clock = adjusted_mode->crtc_clock;
1619 int htotal = adjusted_mode->crtc_htotal;
1620 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1621 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1622 unsigned long line_time_us;
1623 int entries;
1624
1625 line_time_us = max(htotal * 1000 / clock, 1);
1626
1627 /* Use ns/us then divide to preserve precision */
1628 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1629 pixel_size * hdisplay;
1630 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1631 srwm = I965_FIFO_SIZE - entries;
1632 if (srwm < 0)
1633 srwm = 1;
1634 srwm &= 0x1ff;
1635 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1636 entries, srwm);
1637
1638 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1639 pixel_size * to_intel_crtc(crtc)->cursor_width;
1640 entries = DIV_ROUND_UP(entries,
1641 i965_cursor_wm_info.cacheline_size);
1642 cursor_sr = i965_cursor_wm_info.fifo_size -
1643 (entries + i965_cursor_wm_info.guard_size);
1644
1645 if (cursor_sr > i965_cursor_wm_info.max_wm)
1646 cursor_sr = i965_cursor_wm_info.max_wm;
1647
1648 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1649 "cursor %d\n", srwm, cursor_sr);
1650
1651 cxsr_enabled = true;
1652 } else {
1653 cxsr_enabled = false;
1654 /* Turn off self refresh if both pipes are enabled */
1655 intel_set_memory_cxsr(dev_priv, false);
1656 }
1657
1658 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1659 srwm);
1660
1661 /* 965 has limitations... */
1662 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1663 (8 << DSPFW_CURSORB_SHIFT) |
1664 (8 << DSPFW_PLANEB_SHIFT) |
1665 (8 << DSPFW_PLANEA_SHIFT));
1666 I915_WRITE(DSPFW2, (8 << DSPFW_CURSORA_SHIFT) |
1667 (8 << DSPFW_PLANEC_SHIFT_OLD));
1668 /* update cursor SR watermark */
1669 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1670
1671 if (cxsr_enabled)
1672 intel_set_memory_cxsr(dev_priv, true);
1673 }
1674
1675 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1676 {
1677 struct drm_device *dev = unused_crtc->dev;
1678 struct drm_i915_private *dev_priv = dev->dev_private;
1679 const struct intel_watermark_params *wm_info;
1680 uint32_t fwater_lo;
1681 uint32_t fwater_hi;
1682 int cwm, srwm = 1;
1683 int fifo_size;
1684 int planea_wm, planeb_wm;
1685 struct drm_crtc *crtc, *enabled = NULL;
1686
1687 if (IS_I945GM(dev))
1688 wm_info = &i945_wm_info;
1689 else if (!IS_GEN2(dev))
1690 wm_info = &i915_wm_info;
1691 else
1692 wm_info = &i830_wm_info;
1693
1694 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1695 crtc = intel_get_crtc_for_plane(dev, 0);
1696 if (intel_crtc_active(crtc)) {
1697 const struct drm_display_mode *adjusted_mode;
1698 int cpp = crtc->primary->fb->bits_per_pixel / 8;
1699 if (IS_GEN2(dev))
1700 cpp = 4;
1701
1702 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1703 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1704 wm_info, fifo_size, cpp,
1705 latency_ns);
1706 enabled = crtc;
1707 } else
1708 planea_wm = fifo_size - wm_info->guard_size;
1709
1710 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1711 crtc = intel_get_crtc_for_plane(dev, 1);
1712 if (intel_crtc_active(crtc)) {
1713 const struct drm_display_mode *adjusted_mode;
1714 int cpp = crtc->primary->fb->bits_per_pixel / 8;
1715 if (IS_GEN2(dev))
1716 cpp = 4;
1717
1718 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1719 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1720 wm_info, fifo_size, cpp,
1721 latency_ns);
1722 if (enabled == NULL)
1723 enabled = crtc;
1724 else
1725 enabled = NULL;
1726 } else
1727 planeb_wm = fifo_size - wm_info->guard_size;
1728
1729 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1730
1731 if (IS_I915GM(dev) && enabled) {
1732 struct drm_i915_gem_object *obj;
1733
1734 obj = intel_fb_obj(enabled->primary->fb);
1735
1736 /* self-refresh seems busted with untiled */
1737 if (obj->tiling_mode == I915_TILING_NONE)
1738 enabled = NULL;
1739 }
1740
1741 /*
1742 * Overlay gets an aggressive default since video jitter is bad.
1743 */
1744 cwm = 2;
1745
1746 /* Play safe and disable self-refresh before adjusting watermarks. */
1747 intel_set_memory_cxsr(dev_priv, false);
1748
1749 /* Calc sr entries for one plane configs */
1750 if (HAS_FW_BLC(dev) && enabled) {
1751 /* self-refresh has much higher latency */
1752 static const int sr_latency_ns = 6000;
1753 const struct drm_display_mode *adjusted_mode =
1754 &to_intel_crtc(enabled)->config.adjusted_mode;
1755 int clock = adjusted_mode->crtc_clock;
1756 int htotal = adjusted_mode->crtc_htotal;
1757 int hdisplay = to_intel_crtc(enabled)->config.pipe_src_w;
1758 int pixel_size = enabled->primary->fb->bits_per_pixel / 8;
1759 unsigned long line_time_us;
1760 int entries;
1761
1762 line_time_us = max(htotal * 1000 / clock, 1);
1763
1764 /* Use ns/us then divide to preserve precision */
1765 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1766 pixel_size * hdisplay;
1767 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1768 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1769 srwm = wm_info->fifo_size - entries;
1770 if (srwm < 0)
1771 srwm = 1;
1772
1773 if (IS_I945G(dev) || IS_I945GM(dev))
1774 I915_WRITE(FW_BLC_SELF,
1775 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1776 else if (IS_I915GM(dev))
1777 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1778 }
1779
1780 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1781 planea_wm, planeb_wm, cwm, srwm);
1782
1783 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1784 fwater_hi = (cwm & 0x1f);
1785
1786 /* Set request length to 8 cachelines per fetch */
1787 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1788 fwater_hi = fwater_hi | (1 << 8);
1789
1790 I915_WRITE(FW_BLC, fwater_lo);
1791 I915_WRITE(FW_BLC2, fwater_hi);
1792
1793 if (enabled)
1794 intel_set_memory_cxsr(dev_priv, true);
1795 }
1796
1797 static void i845_update_wm(struct drm_crtc *unused_crtc)
1798 {
1799 struct drm_device *dev = unused_crtc->dev;
1800 struct drm_i915_private *dev_priv = dev->dev_private;
1801 struct drm_crtc *crtc;
1802 const struct drm_display_mode *adjusted_mode;
1803 uint32_t fwater_lo;
1804 int planea_wm;
1805
1806 crtc = single_enabled_crtc(dev);
1807 if (crtc == NULL)
1808 return;
1809
1810 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1811 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1812 &i845_wm_info,
1813 dev_priv->display.get_fifo_size(dev, 0),
1814 4, latency_ns);
1815 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1816 fwater_lo |= (3<<8) | planea_wm;
1817
1818 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1819
1820 I915_WRITE(FW_BLC, fwater_lo);
1821 }
1822
1823 static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
1824 struct drm_crtc *crtc)
1825 {
1826 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1827 uint32_t pixel_rate;
1828
1829 pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock;
1830
1831 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1832 * adjust the pixel_rate here. */
1833
1834 if (intel_crtc->config.pch_pfit.enabled) {
1835 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1836 uint32_t pfit_size = intel_crtc->config.pch_pfit.size;
1837
1838 pipe_w = intel_crtc->config.pipe_src_w;
1839 pipe_h = intel_crtc->config.pipe_src_h;
1840 pfit_w = (pfit_size >> 16) & 0xFFFF;
1841 pfit_h = pfit_size & 0xFFFF;
1842 if (pipe_w < pfit_w)
1843 pipe_w = pfit_w;
1844 if (pipe_h < pfit_h)
1845 pipe_h = pfit_h;
1846
1847 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1848 pfit_w * pfit_h);
1849 }
1850
1851 return pixel_rate;
1852 }
1853
1854 /* latency must be in 0.1us units. */
1855 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
1856 uint32_t latency)
1857 {
1858 uint64_t ret;
1859
1860 if (WARN(latency == 0, "Latency value missing\n"))
1861 return UINT_MAX;
1862
1863 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1864 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1865
1866 return ret;
1867 }
1868
1869 /* latency must be in 0.1us units. */
1870 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1871 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1872 uint32_t latency)
1873 {
1874 uint32_t ret;
1875
1876 if (WARN(latency == 0, "Latency value missing\n"))
1877 return UINT_MAX;
1878
1879 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1880 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1881 ret = DIV_ROUND_UP(ret, 64) + 2;
1882 return ret;
1883 }
1884
1885 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1886 uint8_t bytes_per_pixel)
1887 {
1888 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1889 }
1890
1891 struct ilk_pipe_wm_parameters {
1892 bool active;
1893 uint32_t pipe_htotal;
1894 uint32_t pixel_rate;
1895 struct intel_plane_wm_parameters pri;
1896 struct intel_plane_wm_parameters spr;
1897 struct intel_plane_wm_parameters cur;
1898 };
1899
1900 struct ilk_wm_maximums {
1901 uint16_t pri;
1902 uint16_t spr;
1903 uint16_t cur;
1904 uint16_t fbc;
1905 };
1906
1907 /* used in computing the new watermarks state */
1908 struct intel_wm_config {
1909 unsigned int num_pipes_active;
1910 bool sprites_enabled;
1911 bool sprites_scaled;
1912 };
1913
1914 /*
1915 * For both WM_PIPE and WM_LP.
1916 * mem_value must be in 0.1us units.
1917 */
1918 static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params,
1919 uint32_t mem_value,
1920 bool is_lp)
1921 {
1922 uint32_t method1, method2;
1923
1924 if (!params->active || !params->pri.enabled)
1925 return 0;
1926
1927 method1 = ilk_wm_method1(params->pixel_rate,
1928 params->pri.bytes_per_pixel,
1929 mem_value);
1930
1931 if (!is_lp)
1932 return method1;
1933
1934 method2 = ilk_wm_method2(params->pixel_rate,
1935 params->pipe_htotal,
1936 params->pri.horiz_pixels,
1937 params->pri.bytes_per_pixel,
1938 mem_value);
1939
1940 return min(method1, method2);
1941 }
1942
1943 /*
1944 * For both WM_PIPE and WM_LP.
1945 * mem_value must be in 0.1us units.
1946 */
1947 static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params,
1948 uint32_t mem_value)
1949 {
1950 uint32_t method1, method2;
1951
1952 if (!params->active || !params->spr.enabled)
1953 return 0;
1954
1955 method1 = ilk_wm_method1(params->pixel_rate,
1956 params->spr.bytes_per_pixel,
1957 mem_value);
1958 method2 = ilk_wm_method2(params->pixel_rate,
1959 params->pipe_htotal,
1960 params->spr.horiz_pixels,
1961 params->spr.bytes_per_pixel,
1962 mem_value);
1963 return min(method1, method2);
1964 }
1965
1966 /*
1967 * For both WM_PIPE and WM_LP.
1968 * mem_value must be in 0.1us units.
1969 */
1970 static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params,
1971 uint32_t mem_value)
1972 {
1973 if (!params->active || !params->cur.enabled)
1974 return 0;
1975
1976 return ilk_wm_method2(params->pixel_rate,
1977 params->pipe_htotal,
1978 params->cur.horiz_pixels,
1979 params->cur.bytes_per_pixel,
1980 mem_value);
1981 }
1982
1983 /* Only for WM_LP. */
1984 static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params,
1985 uint32_t pri_val)
1986 {
1987 if (!params->active || !params->pri.enabled)
1988 return 0;
1989
1990 return ilk_wm_fbc(pri_val,
1991 params->pri.horiz_pixels,
1992 params->pri.bytes_per_pixel);
1993 }
1994
1995 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1996 {
1997 if (INTEL_INFO(dev)->gen >= 8)
1998 return 3072;
1999 else if (INTEL_INFO(dev)->gen >= 7)
2000 return 768;
2001 else
2002 return 512;
2003 }
2004
2005 static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
2006 int level, bool is_sprite)
2007 {
2008 if (INTEL_INFO(dev)->gen >= 8)
2009 /* BDW primary/sprite plane watermarks */
2010 return level == 0 ? 255 : 2047;
2011 else if (INTEL_INFO(dev)->gen >= 7)
2012 /* IVB/HSW primary/sprite plane watermarks */
2013 return level == 0 ? 127 : 1023;
2014 else if (!is_sprite)
2015 /* ILK/SNB primary plane watermarks */
2016 return level == 0 ? 127 : 511;
2017 else
2018 /* ILK/SNB sprite plane watermarks */
2019 return level == 0 ? 63 : 255;
2020 }
2021
2022 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
2023 int level)
2024 {
2025 if (INTEL_INFO(dev)->gen >= 7)
2026 return level == 0 ? 63 : 255;
2027 else
2028 return level == 0 ? 31 : 63;
2029 }
2030
2031 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
2032 {
2033 if (INTEL_INFO(dev)->gen >= 8)
2034 return 31;
2035 else
2036 return 15;
2037 }
2038
2039 /* Calculate the maximum primary/sprite plane watermark */
2040 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
2041 int level,
2042 const struct intel_wm_config *config,
2043 enum intel_ddb_partitioning ddb_partitioning,
2044 bool is_sprite)
2045 {
2046 unsigned int fifo_size = ilk_display_fifo_size(dev);
2047
2048 /* if sprites aren't enabled, sprites get nothing */
2049 if (is_sprite && !config->sprites_enabled)
2050 return 0;
2051
2052 /* HSW allows LP1+ watermarks even with multiple pipes */
2053 if (level == 0 || config->num_pipes_active > 1) {
2054 fifo_size /= INTEL_INFO(dev)->num_pipes;
2055
2056 /*
2057 * For some reason the non self refresh
2058 * FIFO size is only half of the self
2059 * refresh FIFO size on ILK/SNB.
2060 */
2061 if (INTEL_INFO(dev)->gen <= 6)
2062 fifo_size /= 2;
2063 }
2064
2065 if (config->sprites_enabled) {
2066 /* level 0 is always calculated with 1:1 split */
2067 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
2068 if (is_sprite)
2069 fifo_size *= 5;
2070 fifo_size /= 6;
2071 } else {
2072 fifo_size /= 2;
2073 }
2074 }
2075
2076 /* clamp to max that the registers can hold */
2077 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
2078 }
2079
2080 /* Calculate the maximum cursor plane watermark */
2081 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
2082 int level,
2083 const struct intel_wm_config *config)
2084 {
2085 /* HSW LP1+ watermarks w/ multiple pipes */
2086 if (level > 0 && config->num_pipes_active > 1)
2087 return 64;
2088
2089 /* otherwise just report max that registers can hold */
2090 return ilk_cursor_wm_reg_max(dev, level);
2091 }
2092
2093 static void ilk_compute_wm_maximums(const struct drm_device *dev,
2094 int level,
2095 const struct intel_wm_config *config,
2096 enum intel_ddb_partitioning ddb_partitioning,
2097 struct ilk_wm_maximums *max)
2098 {
2099 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
2100 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
2101 max->cur = ilk_cursor_wm_max(dev, level, config);
2102 max->fbc = ilk_fbc_wm_reg_max(dev);
2103 }
2104
2105 static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
2106 int level,
2107 struct ilk_wm_maximums *max)
2108 {
2109 max->pri = ilk_plane_wm_reg_max(dev, level, false);
2110 max->spr = ilk_plane_wm_reg_max(dev, level, true);
2111 max->cur = ilk_cursor_wm_reg_max(dev, level);
2112 max->fbc = ilk_fbc_wm_reg_max(dev);
2113 }
2114
2115 static bool ilk_validate_wm_level(int level,
2116 const struct ilk_wm_maximums *max,
2117 struct intel_wm_level *result)
2118 {
2119 bool ret;
2120
2121 /* already determined to be invalid? */
2122 if (!result->enable)
2123 return false;
2124
2125 result->enable = result->pri_val <= max->pri &&
2126 result->spr_val <= max->spr &&
2127 result->cur_val <= max->cur;
2128
2129 ret = result->enable;
2130
2131 /*
2132 * HACK until we can pre-compute everything,
2133 * and thus fail gracefully if LP0 watermarks
2134 * are exceeded...
2135 */
2136 if (level == 0 && !result->enable) {
2137 if (result->pri_val > max->pri)
2138 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2139 level, result->pri_val, max->pri);
2140 if (result->spr_val > max->spr)
2141 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2142 level, result->spr_val, max->spr);
2143 if (result->cur_val > max->cur)
2144 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2145 level, result->cur_val, max->cur);
2146
2147 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2148 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2149 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2150 result->enable = true;
2151 }
2152
2153 return ret;
2154 }
2155
2156 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
2157 int level,
2158 const struct ilk_pipe_wm_parameters *p,
2159 struct intel_wm_level *result)
2160 {
2161 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2162 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2163 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2164
2165 /* WM1+ latency values stored in 0.5us units */
2166 if (level > 0) {
2167 pri_latency *= 5;
2168 spr_latency *= 5;
2169 cur_latency *= 5;
2170 }
2171
2172 result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
2173 result->spr_val = ilk_compute_spr_wm(p, spr_latency);
2174 result->cur_val = ilk_compute_cur_wm(p, cur_latency);
2175 result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
2176 result->enable = true;
2177 }
2178
2179 static uint32_t
2180 hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
2181 {
2182 struct drm_i915_private *dev_priv = dev->dev_private;
2183 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2184 struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
2185 u32 linetime, ips_linetime;
2186
2187 if (!intel_crtc_active(crtc))
2188 return 0;
2189
2190 /* The WM are computed with base on how long it takes to fill a single
2191 * row at the given clock rate, multiplied by 8.
2192 * */
2193 linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
2194 mode->crtc_clock);
2195 ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
2196 intel_ddi_get_cdclk_freq(dev_priv));
2197
2198 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2199 PIPE_WM_LINETIME_TIME(linetime);
2200 }
2201
2202 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5])
2203 {
2204 struct drm_i915_private *dev_priv = dev->dev_private;
2205
2206 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2207 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2208
2209 wm[0] = (sskpd >> 56) & 0xFF;
2210 if (wm[0] == 0)
2211 wm[0] = sskpd & 0xF;
2212 wm[1] = (sskpd >> 4) & 0xFF;
2213 wm[2] = (sskpd >> 12) & 0xFF;
2214 wm[3] = (sskpd >> 20) & 0x1FF;
2215 wm[4] = (sskpd >> 32) & 0x1FF;
2216 } else if (INTEL_INFO(dev)->gen >= 6) {
2217 uint32_t sskpd = I915_READ(MCH_SSKPD);
2218
2219 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2220 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2221 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2222 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2223 } else if (INTEL_INFO(dev)->gen >= 5) {
2224 uint32_t mltr = I915_READ(MLTR_ILK);
2225
2226 /* ILK primary LP0 latency is 700 ns */
2227 wm[0] = 7;
2228 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2229 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2230 }
2231 }
2232
2233 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2234 {
2235 /* ILK sprite LP0 latency is 1300 ns */
2236 if (INTEL_INFO(dev)->gen == 5)
2237 wm[0] = 13;
2238 }
2239
2240 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2241 {
2242 /* ILK cursor LP0 latency is 1300 ns */
2243 if (INTEL_INFO(dev)->gen == 5)
2244 wm[0] = 13;
2245
2246 /* WaDoubleCursorLP3Latency:ivb */
2247 if (IS_IVYBRIDGE(dev))
2248 wm[3] *= 2;
2249 }
2250
2251 int ilk_wm_max_level(const struct drm_device *dev)
2252 {
2253 /* how many WM levels are we expecting */
2254 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2255 return 4;
2256 else if (INTEL_INFO(dev)->gen >= 6)
2257 return 3;
2258 else
2259 return 2;
2260 }
2261
2262 static void intel_print_wm_latency(struct drm_device *dev,
2263 const char *name,
2264 const uint16_t wm[5])
2265 {
2266 int level, max_level = ilk_wm_max_level(dev);
2267
2268 for (level = 0; level <= max_level; level++) {
2269 unsigned int latency = wm[level];
2270
2271 if (latency == 0) {
2272 DRM_ERROR("%s WM%d latency not provided\n",
2273 name, level);
2274 continue;
2275 }
2276
2277 /* WM1+ latency values in 0.5us units */
2278 if (level > 0)
2279 latency *= 5;
2280
2281 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2282 name, level, wm[level],
2283 latency / 10, latency % 10);
2284 }
2285 }
2286
2287 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2288 uint16_t wm[5], uint16_t min)
2289 {
2290 int level, max_level = ilk_wm_max_level(dev_priv->dev);
2291
2292 if (wm[0] >= min)
2293 return false;
2294
2295 wm[0] = max(wm[0], min);
2296 for (level = 1; level <= max_level; level++)
2297 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2298
2299 return true;
2300 }
2301
2302 static void snb_wm_latency_quirk(struct drm_device *dev)
2303 {
2304 struct drm_i915_private *dev_priv = dev->dev_private;
2305 bool changed;
2306
2307 /*
2308 * The BIOS provided WM memory latency values are often
2309 * inadequate for high resolution displays. Adjust them.
2310 */
2311 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2312 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2313 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2314
2315 if (!changed)
2316 return;
2317
2318 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2319 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2320 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2321 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2322 }
2323
2324 static void ilk_setup_wm_latency(struct drm_device *dev)
2325 {
2326 struct drm_i915_private *dev_priv = dev->dev_private;
2327
2328 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2329
2330 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2331 sizeof(dev_priv->wm.pri_latency));
2332 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2333 sizeof(dev_priv->wm.pri_latency));
2334
2335 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2336 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2337
2338 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2339 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2340 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2341
2342 if (IS_GEN6(dev))
2343 snb_wm_latency_quirk(dev);
2344 }
2345
2346 static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
2347 struct ilk_pipe_wm_parameters *p)
2348 {
2349 struct drm_device *dev = crtc->dev;
2350 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2351 enum pipe pipe = intel_crtc->pipe;
2352 struct drm_plane *plane;
2353
2354 if (!intel_crtc_active(crtc))
2355 return;
2356
2357 p->active = true;
2358 p->pipe_htotal = intel_crtc->config.adjusted_mode.crtc_htotal;
2359 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
2360 p->pri.bytes_per_pixel = crtc->primary->fb->bits_per_pixel / 8;
2361 p->cur.bytes_per_pixel = 4;
2362 p->pri.horiz_pixels = intel_crtc->config.pipe_src_w;
2363 p->cur.horiz_pixels = intel_crtc->cursor_width;
2364 /* TODO: for now, assume primary and cursor planes are always enabled. */
2365 p->pri.enabled = true;
2366 p->cur.enabled = true;
2367
2368 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
2369 struct intel_plane *intel_plane = to_intel_plane(plane);
2370
2371 if (intel_plane->pipe == pipe) {
2372 p->spr = intel_plane->wm;
2373 break;
2374 }
2375 }
2376 }
2377
2378 static void ilk_compute_wm_config(struct drm_device *dev,
2379 struct intel_wm_config *config)
2380 {
2381 struct intel_crtc *intel_crtc;
2382
2383 /* Compute the currently _active_ config */
2384 for_each_intel_crtc(dev, intel_crtc) {
2385 const struct intel_pipe_wm *wm = &intel_crtc->wm.active;
2386
2387 if (!wm->pipe_enabled)
2388 continue;
2389
2390 config->sprites_enabled |= wm->sprites_enabled;
2391 config->sprites_scaled |= wm->sprites_scaled;
2392 config->num_pipes_active++;
2393 }
2394 }
2395
2396 /* Compute new watermarks for the pipe */
2397 static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
2398 const struct ilk_pipe_wm_parameters *params,
2399 struct intel_pipe_wm *pipe_wm)
2400 {
2401 struct drm_device *dev = crtc->dev;
2402 const struct drm_i915_private *dev_priv = dev->dev_private;
2403 int level, max_level = ilk_wm_max_level(dev);
2404 /* LP0 watermark maximums depend on this pipe alone */
2405 struct intel_wm_config config = {
2406 .num_pipes_active = 1,
2407 .sprites_enabled = params->spr.enabled,
2408 .sprites_scaled = params->spr.scaled,
2409 };
2410 struct ilk_wm_maximums max;
2411
2412 pipe_wm->pipe_enabled = params->active;
2413 pipe_wm->sprites_enabled = params->spr.enabled;
2414 pipe_wm->sprites_scaled = params->spr.scaled;
2415
2416 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2417 if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled)
2418 max_level = 1;
2419
2420 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2421 if (params->spr.scaled)
2422 max_level = 0;
2423
2424 ilk_compute_wm_level(dev_priv, 0, params, &pipe_wm->wm[0]);
2425
2426 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2427 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
2428
2429 /* LP0 watermarks always use 1/2 DDB partitioning */
2430 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2431
2432 /* At least LP0 must be valid */
2433 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
2434 return false;
2435
2436 ilk_compute_wm_reg_maximums(dev, 1, &max);
2437
2438 for (level = 1; level <= max_level; level++) {
2439 struct intel_wm_level wm = {};
2440
2441 ilk_compute_wm_level(dev_priv, level, params, &wm);
2442
2443 /*
2444 * Disable any watermark level that exceeds the
2445 * register maximums since such watermarks are
2446 * always invalid.
2447 */
2448 if (!ilk_validate_wm_level(level, &max, &wm))
2449 break;
2450
2451 pipe_wm->wm[level] = wm;
2452 }
2453
2454 return true;
2455 }
2456
2457 /*
2458 * Merge the watermarks from all active pipes for a specific level.
2459 */
2460 static void ilk_merge_wm_level(struct drm_device *dev,
2461 int level,
2462 struct intel_wm_level *ret_wm)
2463 {
2464 const struct intel_crtc *intel_crtc;
2465
2466 ret_wm->enable = true;
2467
2468 for_each_intel_crtc(dev, intel_crtc) {
2469 const struct intel_pipe_wm *active = &intel_crtc->wm.active;
2470 const struct intel_wm_level *wm = &active->wm[level];
2471
2472 if (!active->pipe_enabled)
2473 continue;
2474
2475 /*
2476 * The watermark values may have been used in the past,
2477 * so we must maintain them in the registers for some
2478 * time even if the level is now disabled.
2479 */
2480 if (!wm->enable)
2481 ret_wm->enable = false;
2482
2483 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2484 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2485 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2486 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2487 }
2488 }
2489
2490 /*
2491 * Merge all low power watermarks for all active pipes.
2492 */
2493 static void ilk_wm_merge(struct drm_device *dev,
2494 const struct intel_wm_config *config,
2495 const struct ilk_wm_maximums *max,
2496 struct intel_pipe_wm *merged)
2497 {
2498 int level, max_level = ilk_wm_max_level(dev);
2499 int last_enabled_level = max_level;
2500
2501 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2502 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2503 config->num_pipes_active > 1)
2504 return;
2505
2506 /* ILK: FBC WM must be disabled always */
2507 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
2508
2509 /* merge each WM1+ level */
2510 for (level = 1; level <= max_level; level++) {
2511 struct intel_wm_level *wm = &merged->wm[level];
2512
2513 ilk_merge_wm_level(dev, level, wm);
2514
2515 if (level > last_enabled_level)
2516 wm->enable = false;
2517 else if (!ilk_validate_wm_level(level, max, wm))
2518 /* make sure all following levels get disabled */
2519 last_enabled_level = level - 1;
2520
2521 /*
2522 * The spec says it is preferred to disable
2523 * FBC WMs instead of disabling a WM level.
2524 */
2525 if (wm->fbc_val > max->fbc) {
2526 if (wm->enable)
2527 merged->fbc_wm_enabled = false;
2528 wm->fbc_val = 0;
2529 }
2530 }
2531
2532 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2533 /*
2534 * FIXME this is racy. FBC might get enabled later.
2535 * What we should check here is whether FBC can be
2536 * enabled sometime later.
2537 */
2538 if (IS_GEN5(dev) && !merged->fbc_wm_enabled && intel_fbc_enabled(dev)) {
2539 for (level = 2; level <= max_level; level++) {
2540 struct intel_wm_level *wm = &merged->wm[level];
2541
2542 wm->enable = false;
2543 }
2544 }
2545 }
2546
2547 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2548 {
2549 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2550 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2551 }
2552
2553 /* The value we need to program into the WM_LPx latency field */
2554 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2555 {
2556 struct drm_i915_private *dev_priv = dev->dev_private;
2557
2558 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2559 return 2 * level;
2560 else
2561 return dev_priv->wm.pri_latency[level];
2562 }
2563
2564 static void ilk_compute_wm_results(struct drm_device *dev,
2565 const struct intel_pipe_wm *merged,
2566 enum intel_ddb_partitioning partitioning,
2567 struct ilk_wm_values *results)
2568 {
2569 struct intel_crtc *intel_crtc;
2570 int level, wm_lp;
2571
2572 results->enable_fbc_wm = merged->fbc_wm_enabled;
2573 results->partitioning = partitioning;
2574
2575 /* LP1+ register values */
2576 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2577 const struct intel_wm_level *r;
2578
2579 level = ilk_wm_lp_to_level(wm_lp, merged);
2580
2581 r = &merged->wm[level];
2582
2583 /*
2584 * Maintain the watermark values even if the level is
2585 * disabled. Doing otherwise could cause underruns.
2586 */
2587 results->wm_lp[wm_lp - 1] =
2588 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2589 (r->pri_val << WM1_LP_SR_SHIFT) |
2590 r->cur_val;
2591
2592 if (r->enable)
2593 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2594
2595 if (INTEL_INFO(dev)->gen >= 8)
2596 results->wm_lp[wm_lp - 1] |=
2597 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2598 else
2599 results->wm_lp[wm_lp - 1] |=
2600 r->fbc_val << WM1_LP_FBC_SHIFT;
2601
2602 /*
2603 * Always set WM1S_LP_EN when spr_val != 0, even if the
2604 * level is disabled. Doing otherwise could cause underruns.
2605 */
2606 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2607 WARN_ON(wm_lp != 1);
2608 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2609 } else
2610 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2611 }
2612
2613 /* LP0 register values */
2614 for_each_intel_crtc(dev, intel_crtc) {
2615 enum pipe pipe = intel_crtc->pipe;
2616 const struct intel_wm_level *r =
2617 &intel_crtc->wm.active.wm[0];
2618
2619 if (WARN_ON(!r->enable))
2620 continue;
2621
2622 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
2623
2624 results->wm_pipe[pipe] =
2625 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2626 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2627 r->cur_val;
2628 }
2629 }
2630
2631 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2632 * case both are at the same level. Prefer r1 in case they're the same. */
2633 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2634 struct intel_pipe_wm *r1,
2635 struct intel_pipe_wm *r2)
2636 {
2637 int level, max_level = ilk_wm_max_level(dev);
2638 int level1 = 0, level2 = 0;
2639
2640 for (level = 1; level <= max_level; level++) {
2641 if (r1->wm[level].enable)
2642 level1 = level;
2643 if (r2->wm[level].enable)
2644 level2 = level;
2645 }
2646
2647 if (level1 == level2) {
2648 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2649 return r2;
2650 else
2651 return r1;
2652 } else if (level1 > level2) {
2653 return r1;
2654 } else {
2655 return r2;
2656 }
2657 }
2658
2659 /* dirty bits used to track which watermarks need changes */
2660 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2661 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2662 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2663 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2664 #define WM_DIRTY_FBC (1 << 24)
2665 #define WM_DIRTY_DDB (1 << 25)
2666
2667 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
2668 const struct ilk_wm_values *old,
2669 const struct ilk_wm_values *new)
2670 {
2671 unsigned int dirty = 0;
2672 enum pipe pipe;
2673 int wm_lp;
2674
2675 for_each_pipe(dev_priv, pipe) {
2676 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2677 dirty |= WM_DIRTY_LINETIME(pipe);
2678 /* Must disable LP1+ watermarks too */
2679 dirty |= WM_DIRTY_LP_ALL;
2680 }
2681
2682 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2683 dirty |= WM_DIRTY_PIPE(pipe);
2684 /* Must disable LP1+ watermarks too */
2685 dirty |= WM_DIRTY_LP_ALL;
2686 }
2687 }
2688
2689 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2690 dirty |= WM_DIRTY_FBC;
2691 /* Must disable LP1+ watermarks too */
2692 dirty |= WM_DIRTY_LP_ALL;
2693 }
2694
2695 if (old->partitioning != new->partitioning) {
2696 dirty |= WM_DIRTY_DDB;
2697 /* Must disable LP1+ watermarks too */
2698 dirty |= WM_DIRTY_LP_ALL;
2699 }
2700
2701 /* LP1+ watermarks already deemed dirty, no need to continue */
2702 if (dirty & WM_DIRTY_LP_ALL)
2703 return dirty;
2704
2705 /* Find the lowest numbered LP1+ watermark in need of an update... */
2706 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2707 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2708 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2709 break;
2710 }
2711
2712 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2713 for (; wm_lp <= 3; wm_lp++)
2714 dirty |= WM_DIRTY_LP(wm_lp);
2715
2716 return dirty;
2717 }
2718
2719 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2720 unsigned int dirty)
2721 {
2722 struct ilk_wm_values *previous = &dev_priv->wm.hw;
2723 bool changed = false;
2724
2725 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2726 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2727 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2728 changed = true;
2729 }
2730 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2731 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2732 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2733 changed = true;
2734 }
2735 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2736 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2737 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2738 changed = true;
2739 }
2740
2741 /*
2742 * Don't touch WM1S_LP_EN here.
2743 * Doing so could cause underruns.
2744 */
2745
2746 return changed;
2747 }
2748
2749 /*
2750 * The spec says we shouldn't write when we don't need, because every write
2751 * causes WMs to be re-evaluated, expending some power.
2752 */
2753 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2754 struct ilk_wm_values *results)
2755 {
2756 struct drm_device *dev = dev_priv->dev;
2757 struct ilk_wm_values *previous = &dev_priv->wm.hw;
2758 unsigned int dirty;
2759 uint32_t val;
2760
2761 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
2762 if (!dirty)
2763 return;
2764
2765 _ilk_disable_lp_wm(dev_priv, dirty);
2766
2767 if (dirty & WM_DIRTY_PIPE(PIPE_A))
2768 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2769 if (dirty & WM_DIRTY_PIPE(PIPE_B))
2770 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2771 if (dirty & WM_DIRTY_PIPE(PIPE_C))
2772 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2773
2774 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2775 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2776 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2777 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2778 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2779 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2780
2781 if (dirty & WM_DIRTY_DDB) {
2782 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2783 val = I915_READ(WM_MISC);
2784 if (results->partitioning == INTEL_DDB_PART_1_2)
2785 val &= ~WM_MISC_DATA_PARTITION_5_6;
2786 else
2787 val |= WM_MISC_DATA_PARTITION_5_6;
2788 I915_WRITE(WM_MISC, val);
2789 } else {
2790 val = I915_READ(DISP_ARB_CTL2);
2791 if (results->partitioning == INTEL_DDB_PART_1_2)
2792 val &= ~DISP_DATA_PARTITION_5_6;
2793 else
2794 val |= DISP_DATA_PARTITION_5_6;
2795 I915_WRITE(DISP_ARB_CTL2, val);
2796 }
2797 }
2798
2799 if (dirty & WM_DIRTY_FBC) {
2800 val = I915_READ(DISP_ARB_CTL);
2801 if (results->enable_fbc_wm)
2802 val &= ~DISP_FBC_WM_DIS;
2803 else
2804 val |= DISP_FBC_WM_DIS;
2805 I915_WRITE(DISP_ARB_CTL, val);
2806 }
2807
2808 if (dirty & WM_DIRTY_LP(1) &&
2809 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2810 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2811
2812 if (INTEL_INFO(dev)->gen >= 7) {
2813 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2814 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2815 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2816 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2817 }
2818
2819 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2820 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2821 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2822 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2823 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2824 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2825
2826 dev_priv->wm.hw = *results;
2827 }
2828
2829 static bool ilk_disable_lp_wm(struct drm_device *dev)
2830 {
2831 struct drm_i915_private *dev_priv = dev->dev_private;
2832
2833 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2834 }
2835
2836 static void ilk_update_wm(struct drm_crtc *crtc)
2837 {
2838 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2839 struct drm_device *dev = crtc->dev;
2840 struct drm_i915_private *dev_priv = dev->dev_private;
2841 struct ilk_wm_maximums max;
2842 struct ilk_pipe_wm_parameters params = {};
2843 struct ilk_wm_values results = {};
2844 enum intel_ddb_partitioning partitioning;
2845 struct intel_pipe_wm pipe_wm = {};
2846 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
2847 struct intel_wm_config config = {};
2848
2849 ilk_compute_wm_parameters(crtc, &params);
2850
2851 intel_compute_pipe_wm(crtc, &params, &pipe_wm);
2852
2853 if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
2854 return;
2855
2856 intel_crtc->wm.active = pipe_wm;
2857
2858 ilk_compute_wm_config(dev, &config);
2859
2860 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
2861 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
2862
2863 /* 5/6 split only in single pipe config on IVB+ */
2864 if (INTEL_INFO(dev)->gen >= 7 &&
2865 config.num_pipes_active == 1 && config.sprites_enabled) {
2866 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
2867 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
2868
2869 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
2870 } else {
2871 best_lp_wm = &lp_wm_1_2;
2872 }
2873
2874 partitioning = (best_lp_wm == &lp_wm_1_2) ?
2875 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
2876
2877 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
2878
2879 ilk_write_wm_values(dev_priv, &results);
2880 }
2881
2882 static void
2883 ilk_update_sprite_wm(struct drm_plane *plane,
2884 struct drm_crtc *crtc,
2885 uint32_t sprite_width, uint32_t sprite_height,
2886 int pixel_size, bool enabled, bool scaled)
2887 {
2888 struct drm_device *dev = plane->dev;
2889 struct intel_plane *intel_plane = to_intel_plane(plane);
2890
2891 intel_plane->wm.enabled = enabled;
2892 intel_plane->wm.scaled = scaled;
2893 intel_plane->wm.horiz_pixels = sprite_width;
2894 intel_plane->wm.vert_pixels = sprite_width;
2895 intel_plane->wm.bytes_per_pixel = pixel_size;
2896
2897 /*
2898 * IVB workaround: must disable low power watermarks for at least
2899 * one frame before enabling scaling. LP watermarks can be re-enabled
2900 * when scaling is disabled.
2901 *
2902 * WaCxSRDisabledForSpriteScaling:ivb
2903 */
2904 if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev))
2905 intel_wait_for_vblank(dev, intel_plane->pipe);
2906
2907 ilk_update_wm(crtc);
2908 }
2909
2910 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
2911 {
2912 struct drm_device *dev = crtc->dev;
2913 struct drm_i915_private *dev_priv = dev->dev_private;
2914 struct ilk_wm_values *hw = &dev_priv->wm.hw;
2915 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2916 struct intel_pipe_wm *active = &intel_crtc->wm.active;
2917 enum pipe pipe = intel_crtc->pipe;
2918 static const unsigned int wm0_pipe_reg[] = {
2919 [PIPE_A] = WM0_PIPEA_ILK,
2920 [PIPE_B] = WM0_PIPEB_ILK,
2921 [PIPE_C] = WM0_PIPEC_IVB,
2922 };
2923
2924 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
2925 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2926 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
2927
2928 active->pipe_enabled = intel_crtc_active(crtc);
2929
2930 if (active->pipe_enabled) {
2931 u32 tmp = hw->wm_pipe[pipe];
2932
2933 /*
2934 * For active pipes LP0 watermark is marked as
2935 * enabled, and LP1+ watermaks as disabled since
2936 * we can't really reverse compute them in case
2937 * multiple pipes are active.
2938 */
2939 active->wm[0].enable = true;
2940 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
2941 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
2942 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
2943 active->linetime = hw->wm_linetime[pipe];
2944 } else {
2945 int level, max_level = ilk_wm_max_level(dev);
2946
2947 /*
2948 * For inactive pipes, all watermark levels
2949 * should be marked as enabled but zeroed,
2950 * which is what we'd compute them to.
2951 */
2952 for (level = 0; level <= max_level; level++)
2953 active->wm[level].enable = true;
2954 }
2955 }
2956
2957 void ilk_wm_get_hw_state(struct drm_device *dev)
2958 {
2959 struct drm_i915_private *dev_priv = dev->dev_private;
2960 struct ilk_wm_values *hw = &dev_priv->wm.hw;
2961 struct drm_crtc *crtc;
2962
2963 for_each_crtc(dev, crtc)
2964 ilk_pipe_wm_get_hw_state(crtc);
2965
2966 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
2967 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
2968 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
2969
2970 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
2971 if (INTEL_INFO(dev)->gen >= 7) {
2972 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
2973 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
2974 }
2975
2976 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2977 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
2978 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
2979 else if (IS_IVYBRIDGE(dev))
2980 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
2981 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
2982
2983 hw->enable_fbc_wm =
2984 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
2985 }
2986
2987 /**
2988 * intel_update_watermarks - update FIFO watermark values based on current modes
2989 *
2990 * Calculate watermark values for the various WM regs based on current mode
2991 * and plane configuration.
2992 *
2993 * There are several cases to deal with here:
2994 * - normal (i.e. non-self-refresh)
2995 * - self-refresh (SR) mode
2996 * - lines are large relative to FIFO size (buffer can hold up to 2)
2997 * - lines are small relative to FIFO size (buffer can hold more than 2
2998 * lines), so need to account for TLB latency
2999 *
3000 * The normal calculation is:
3001 * watermark = dotclock * bytes per pixel * latency
3002 * where latency is platform & configuration dependent (we assume pessimal
3003 * values here).
3004 *
3005 * The SR calculation is:
3006 * watermark = (trunc(latency/line time)+1) * surface width *
3007 * bytes per pixel
3008 * where
3009 * line time = htotal / dotclock
3010 * surface width = hdisplay for normal plane and 64 for cursor
3011 * and latency is assumed to be high, as above.
3012 *
3013 * The final value programmed to the register should always be rounded up,
3014 * and include an extra 2 entries to account for clock crossings.
3015 *
3016 * We don't use the sprite, so we can ignore that. And on Crestline we have
3017 * to set the non-SR watermarks to 8.
3018 */
3019 void intel_update_watermarks(struct drm_crtc *crtc)
3020 {
3021 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
3022
3023 if (dev_priv->display.update_wm)
3024 dev_priv->display.update_wm(crtc);
3025 }
3026
3027 void intel_update_sprite_watermarks(struct drm_plane *plane,
3028 struct drm_crtc *crtc,
3029 uint32_t sprite_width,
3030 uint32_t sprite_height,
3031 int pixel_size,
3032 bool enabled, bool scaled)
3033 {
3034 struct drm_i915_private *dev_priv = plane->dev->dev_private;
3035
3036 if (dev_priv->display.update_sprite_wm)
3037 dev_priv->display.update_sprite_wm(plane, crtc,
3038 sprite_width, sprite_height,
3039 pixel_size, enabled, scaled);
3040 }
3041
3042 static struct drm_i915_gem_object *
3043 intel_alloc_context_page(struct drm_device *dev)
3044 {
3045 struct drm_i915_gem_object *ctx;
3046 int ret;
3047
3048 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3049
3050 ctx = i915_gem_alloc_object(dev, 4096);
3051 if (!ctx) {
3052 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
3053 return NULL;
3054 }
3055
3056 ret = i915_gem_obj_ggtt_pin(ctx, 4096, 0);
3057 if (ret) {
3058 DRM_ERROR("failed to pin power context: %d\n", ret);
3059 goto err_unref;
3060 }
3061
3062 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
3063 if (ret) {
3064 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
3065 goto err_unpin;
3066 }
3067
3068 return ctx;
3069
3070 err_unpin:
3071 i915_gem_object_ggtt_unpin(ctx);
3072 err_unref:
3073 drm_gem_object_unreference(&ctx->base);
3074 return NULL;
3075 }
3076
3077 /**
3078 * Lock protecting IPS related data structures
3079 */
3080 DEFINE_SPINLOCK(mchdev_lock);
3081
3082 /* Global for IPS driver to get at the current i915 device. Protected by
3083 * mchdev_lock. */
3084 static struct drm_i915_private *i915_mch_dev;
3085
3086 bool ironlake_set_drps(struct drm_device *dev, u8 val)
3087 {
3088 struct drm_i915_private *dev_priv = dev->dev_private;
3089 u16 rgvswctl;
3090
3091 assert_spin_locked(&mchdev_lock);
3092
3093 rgvswctl = I915_READ16(MEMSWCTL);
3094 if (rgvswctl & MEMCTL_CMD_STS) {
3095 DRM_DEBUG("gpu busy, RCS change rejected\n");
3096 return false; /* still busy with another command */
3097 }
3098
3099 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
3100 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
3101 I915_WRITE16(MEMSWCTL, rgvswctl);
3102 POSTING_READ16(MEMSWCTL);
3103
3104 rgvswctl |= MEMCTL_CMD_STS;
3105 I915_WRITE16(MEMSWCTL, rgvswctl);
3106
3107 return true;
3108 }
3109
3110 static void ironlake_enable_drps(struct drm_device *dev)
3111 {
3112 struct drm_i915_private *dev_priv = dev->dev_private;
3113 u32 rgvmodectl = I915_READ(MEMMODECTL);
3114 u8 fmax, fmin, fstart, vstart;
3115
3116 spin_lock_irq(&mchdev_lock);
3117
3118 /* Enable temp reporting */
3119 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
3120 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
3121
3122 /* 100ms RC evaluation intervals */
3123 I915_WRITE(RCUPEI, 100000);
3124 I915_WRITE(RCDNEI, 100000);
3125
3126 /* Set max/min thresholds to 90ms and 80ms respectively */
3127 I915_WRITE(RCBMAXAVG, 90000);
3128 I915_WRITE(RCBMINAVG, 80000);
3129
3130 I915_WRITE(MEMIHYST, 1);
3131
3132 /* Set up min, max, and cur for interrupt handling */
3133 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
3134 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
3135 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
3136 MEMMODE_FSTART_SHIFT;
3137
3138 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
3139 PXVFREQ_PX_SHIFT;
3140
3141 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
3142 dev_priv->ips.fstart = fstart;
3143
3144 dev_priv->ips.max_delay = fstart;
3145 dev_priv->ips.min_delay = fmin;
3146 dev_priv->ips.cur_delay = fstart;
3147
3148 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
3149 fmax, fmin, fstart);
3150
3151 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
3152
3153 /*
3154 * Interrupts will be enabled in ironlake_irq_postinstall
3155 */
3156
3157 I915_WRITE(VIDSTART, vstart);
3158 POSTING_READ(VIDSTART);
3159
3160 rgvmodectl |= MEMMODE_SWMODE_EN;
3161 I915_WRITE(MEMMODECTL, rgvmodectl);
3162
3163 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
3164 DRM_ERROR("stuck trying to change perf mode\n");
3165 mdelay(1);
3166
3167 ironlake_set_drps(dev, fstart);
3168
3169 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
3170 I915_READ(0x112e0);
3171 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
3172 dev_priv->ips.last_count2 = I915_READ(0x112f4);
3173 dev_priv->ips.last_time2 = ktime_get_raw_ns();
3174
3175 spin_unlock_irq(&mchdev_lock);
3176 }
3177
3178 static void ironlake_disable_drps(struct drm_device *dev)
3179 {
3180 struct drm_i915_private *dev_priv = dev->dev_private;
3181 u16 rgvswctl;
3182
3183 spin_lock_irq(&mchdev_lock);
3184
3185 rgvswctl = I915_READ16(MEMSWCTL);
3186
3187 /* Ack interrupts, disable EFC interrupt */
3188 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
3189 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
3190 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
3191 I915_WRITE(DEIIR, DE_PCU_EVENT);
3192 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
3193
3194 /* Go back to the starting frequency */
3195 ironlake_set_drps(dev, dev_priv->ips.fstart);
3196 mdelay(1);
3197 rgvswctl |= MEMCTL_CMD_STS;
3198 I915_WRITE(MEMSWCTL, rgvswctl);
3199 mdelay(1);
3200
3201 spin_unlock_irq(&mchdev_lock);
3202 }
3203
3204 /* There's a funny hw issue where the hw returns all 0 when reading from
3205 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3206 * ourselves, instead of doing a rmw cycle (which might result in us clearing
3207 * all limits and the gpu stuck at whatever frequency it is at atm).
3208 */
3209 static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)
3210 {
3211 u32 limits;
3212
3213 /* Only set the down limit when we've reached the lowest level to avoid
3214 * getting more interrupts, otherwise leave this clear. This prevents a
3215 * race in the hw when coming out of rc6: There's a tiny window where
3216 * the hw runs at the minimal clock before selecting the desired
3217 * frequency, if the down threshold expires in that window we will not
3218 * receive a down interrupt. */
3219 limits = dev_priv->rps.max_freq_softlimit << 24;
3220 if (val <= dev_priv->rps.min_freq_softlimit)
3221 limits |= dev_priv->rps.min_freq_softlimit << 16;
3222
3223 return limits;
3224 }
3225
3226 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
3227 {
3228 int new_power;
3229
3230 new_power = dev_priv->rps.power;
3231 switch (dev_priv->rps.power) {
3232 case LOW_POWER:
3233 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
3234 new_power = BETWEEN;
3235 break;
3236
3237 case BETWEEN:
3238 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
3239 new_power = LOW_POWER;
3240 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
3241 new_power = HIGH_POWER;
3242 break;
3243
3244 case HIGH_POWER:
3245 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
3246 new_power = BETWEEN;
3247 break;
3248 }
3249 /* Max/min bins are special */
3250 if (val == dev_priv->rps.min_freq_softlimit)
3251 new_power = LOW_POWER;
3252 if (val == dev_priv->rps.max_freq_softlimit)
3253 new_power = HIGH_POWER;
3254 if (new_power == dev_priv->rps.power)
3255 return;
3256
3257 /* Note the units here are not exactly 1us, but 1280ns. */
3258 switch (new_power) {
3259 case LOW_POWER:
3260 /* Upclock if more than 95% busy over 16ms */
3261 I915_WRITE(GEN6_RP_UP_EI, 12500);
3262 I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800);
3263
3264 /* Downclock if less than 85% busy over 32ms */
3265 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3266 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250);
3267
3268 I915_WRITE(GEN6_RP_CONTROL,
3269 GEN6_RP_MEDIA_TURBO |
3270 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3271 GEN6_RP_MEDIA_IS_GFX |
3272 GEN6_RP_ENABLE |
3273 GEN6_RP_UP_BUSY_AVG |
3274 GEN6_RP_DOWN_IDLE_AVG);
3275 break;
3276
3277 case BETWEEN:
3278 /* Upclock if more than 90% busy over 13ms */
3279 I915_WRITE(GEN6_RP_UP_EI, 10250);
3280 I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225);
3281
3282 /* Downclock if less than 75% busy over 32ms */
3283 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3284 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750);
3285
3286 I915_WRITE(GEN6_RP_CONTROL,
3287 GEN6_RP_MEDIA_TURBO |
3288 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3289 GEN6_RP_MEDIA_IS_GFX |
3290 GEN6_RP_ENABLE |
3291 GEN6_RP_UP_BUSY_AVG |
3292 GEN6_RP_DOWN_IDLE_AVG);
3293 break;
3294
3295 case HIGH_POWER:
3296 /* Upclock if more than 85% busy over 10ms */
3297 I915_WRITE(GEN6_RP_UP_EI, 8000);
3298 I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800);
3299
3300 /* Downclock if less than 60% busy over 32ms */
3301 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3302 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000);
3303
3304 I915_WRITE(GEN6_RP_CONTROL,
3305 GEN6_RP_MEDIA_TURBO |
3306 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3307 GEN6_RP_MEDIA_IS_GFX |
3308 GEN6_RP_ENABLE |
3309 GEN6_RP_UP_BUSY_AVG |
3310 GEN6_RP_DOWN_IDLE_AVG);
3311 break;
3312 }
3313
3314 dev_priv->rps.power = new_power;
3315 dev_priv->rps.last_adj = 0;
3316 }
3317
3318 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
3319 {
3320 u32 mask = 0;
3321
3322 if (val > dev_priv->rps.min_freq_softlimit)
3323 mask |= GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
3324 if (val < dev_priv->rps.max_freq_softlimit)
3325 mask |= GEN6_PM_RP_UP_THRESHOLD;
3326
3327 mask |= dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED);
3328 mask &= dev_priv->pm_rps_events;
3329
3330 /* IVB and SNB hard hangs on looping batchbuffer
3331 * if GEN6_PM_UP_EI_EXPIRED is masked.
3332 */
3333 if (INTEL_INFO(dev_priv->dev)->gen <= 7 && !IS_HASWELL(dev_priv->dev))
3334 mask |= GEN6_PM_RP_UP_EI_EXPIRED;
3335
3336 if (IS_GEN8(dev_priv->dev))
3337 mask |= GEN8_PMINTR_REDIRECT_TO_NON_DISP;
3338
3339 return ~mask;
3340 }
3341
3342 /* gen6_set_rps is called to update the frequency request, but should also be
3343 * called when the range (min_delay and max_delay) is modified so that we can
3344 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
3345 void gen6_set_rps(struct drm_device *dev, u8 val)
3346 {
3347 struct drm_i915_private *dev_priv = dev->dev_private;
3348
3349 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3350 WARN_ON(val > dev_priv->rps.max_freq_softlimit);
3351 WARN_ON(val < dev_priv->rps.min_freq_softlimit);
3352
3353 /* min/max delay may still have been modified so be sure to
3354 * write the limits value.
3355 */
3356 if (val != dev_priv->rps.cur_freq) {
3357 gen6_set_rps_thresholds(dev_priv, val);
3358
3359 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3360 I915_WRITE(GEN6_RPNSWREQ,
3361 HSW_FREQUENCY(val));
3362 else
3363 I915_WRITE(GEN6_RPNSWREQ,
3364 GEN6_FREQUENCY(val) |
3365 GEN6_OFFSET(0) |
3366 GEN6_AGGRESSIVE_TURBO);
3367 }
3368
3369 /* Make sure we continue to get interrupts
3370 * until we hit the minimum or maximum frequencies.
3371 */
3372 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, gen6_rps_limits(dev_priv, val));
3373 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
3374
3375 POSTING_READ(GEN6_RPNSWREQ);
3376
3377 dev_priv->rps.cur_freq = val;
3378 trace_intel_gpu_freq_change(val * 50);
3379 }
3380
3381 /* vlv_set_rps_idle: Set the frequency to Rpn if Gfx clocks are down
3382 *
3383 * * If Gfx is Idle, then
3384 * 1. Mask Turbo interrupts
3385 * 2. Bring up Gfx clock
3386 * 3. Change the freq to Rpn and wait till P-Unit updates freq
3387 * 4. Clear the Force GFX CLK ON bit so that Gfx can down
3388 * 5. Unmask Turbo interrupts
3389 */
3390 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
3391 {
3392 struct drm_device *dev = dev_priv->dev;
3393
3394 /* Latest VLV doesn't need to force the gfx clock */
3395 if (dev->pdev->revision >= 0xd) {
3396 valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3397 return;
3398 }
3399
3400 /*
3401 * When we are idle. Drop to min voltage state.
3402 */
3403
3404 if (dev_priv->rps.cur_freq <= dev_priv->rps.min_freq_softlimit)
3405 return;
3406
3407 /* Mask turbo interrupt so that they will not come in between */
3408 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3409
3410 vlv_force_gfx_clock(dev_priv, true);
3411
3412 dev_priv->rps.cur_freq = dev_priv->rps.min_freq_softlimit;
3413
3414 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ,
3415 dev_priv->rps.min_freq_softlimit);
3416
3417 if (wait_for(((vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS))
3418 & GENFREQSTATUS) == 0, 5))
3419 DRM_ERROR("timed out waiting for Punit\n");
3420
3421 vlv_force_gfx_clock(dev_priv, false);
3422
3423 I915_WRITE(GEN6_PMINTRMSK,
3424 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
3425 }
3426
3427 void gen6_rps_idle(struct drm_i915_private *dev_priv)
3428 {
3429 struct drm_device *dev = dev_priv->dev;
3430
3431 mutex_lock(&dev_priv->rps.hw_lock);
3432 if (dev_priv->rps.enabled) {
3433 if (IS_CHERRYVIEW(dev))
3434 valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3435 else if (IS_VALLEYVIEW(dev))
3436 vlv_set_rps_idle(dev_priv);
3437 else
3438 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3439 dev_priv->rps.last_adj = 0;
3440 }
3441 mutex_unlock(&dev_priv->rps.hw_lock);
3442 }
3443
3444 void gen6_rps_boost(struct drm_i915_private *dev_priv)
3445 {
3446 struct drm_device *dev = dev_priv->dev;
3447
3448 mutex_lock(&dev_priv->rps.hw_lock);
3449 if (dev_priv->rps.enabled) {
3450 if (IS_VALLEYVIEW(dev))
3451 valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
3452 else
3453 gen6_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
3454 dev_priv->rps.last_adj = 0;
3455 }
3456 mutex_unlock(&dev_priv->rps.hw_lock);
3457 }
3458
3459 void valleyview_set_rps(struct drm_device *dev, u8 val)
3460 {
3461 struct drm_i915_private *dev_priv = dev->dev_private;
3462
3463 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3464 WARN_ON(val > dev_priv->rps.max_freq_softlimit);
3465 WARN_ON(val < dev_priv->rps.min_freq_softlimit);
3466
3467 DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
3468 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
3469 dev_priv->rps.cur_freq,
3470 vlv_gpu_freq(dev_priv, val), val);
3471
3472 if (val != dev_priv->rps.cur_freq)
3473 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
3474
3475 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
3476
3477 dev_priv->rps.cur_freq = val;
3478 trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val));
3479 }
3480
3481 static void gen8_disable_rps_interrupts(struct drm_device *dev)
3482 {
3483 struct drm_i915_private *dev_priv = dev->dev_private;
3484
3485 I915_WRITE(GEN6_PMINTRMSK, ~GEN8_PMINTR_REDIRECT_TO_NON_DISP);
3486 I915_WRITE(GEN8_GT_IER(2), I915_READ(GEN8_GT_IER(2)) &
3487 ~dev_priv->pm_rps_events);
3488 /* Complete PM interrupt masking here doesn't race with the rps work
3489 * item again unmasking PM interrupts because that is using a different
3490 * register (GEN8_GT_IMR(2)) to mask PM interrupts. The only risk is in
3491 * leaving stale bits in GEN8_GT_IIR(2) and GEN8_GT_IMR(2) which
3492 * gen8_enable_rps will clean up. */
3493
3494 spin_lock_irq(&dev_priv->irq_lock);
3495 dev_priv->rps.pm_iir = 0;
3496 spin_unlock_irq(&dev_priv->irq_lock);
3497
3498 I915_WRITE(GEN8_GT_IIR(2), dev_priv->pm_rps_events);
3499 }
3500
3501 static void gen6_disable_rps_interrupts(struct drm_device *dev)
3502 {
3503 struct drm_i915_private *dev_priv = dev->dev_private;
3504
3505 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3506 I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) &
3507 ~dev_priv->pm_rps_events);
3508 /* Complete PM interrupt masking here doesn't race with the rps work
3509 * item again unmasking PM interrupts because that is using a different
3510 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3511 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3512
3513 spin_lock_irq(&dev_priv->irq_lock);
3514 dev_priv->rps.pm_iir = 0;
3515 spin_unlock_irq(&dev_priv->irq_lock);
3516
3517 I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events);
3518 }
3519
3520 static void gen6_disable_rps(struct drm_device *dev)
3521 {
3522 struct drm_i915_private *dev_priv = dev->dev_private;
3523
3524 I915_WRITE(GEN6_RC_CONTROL, 0);
3525 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
3526
3527 if (IS_BROADWELL(dev))
3528 gen8_disable_rps_interrupts(dev);
3529 else
3530 gen6_disable_rps_interrupts(dev);
3531 }
3532
3533 static void cherryview_disable_rps(struct drm_device *dev)
3534 {
3535 struct drm_i915_private *dev_priv = dev->dev_private;
3536
3537 I915_WRITE(GEN6_RC_CONTROL, 0);
3538
3539 gen8_disable_rps_interrupts(dev);
3540 }
3541
3542 static void valleyview_disable_rps(struct drm_device *dev)
3543 {
3544 struct drm_i915_private *dev_priv = dev->dev_private;
3545
3546 /* we're doing forcewake before Disabling RC6,
3547 * This what the BIOS expects when going into suspend */
3548 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3549
3550 I915_WRITE(GEN6_RC_CONTROL, 0);
3551
3552 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3553
3554 gen6_disable_rps_interrupts(dev);
3555 }
3556
3557 static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
3558 {
3559 if (IS_VALLEYVIEW(dev)) {
3560 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
3561 mode = GEN6_RC_CTL_RC6_ENABLE;
3562 else
3563 mode = 0;
3564 }
3565 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
3566 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3567 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3568 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
3569 }
3570
3571 static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
3572 {
3573 /* No RC6 before Ironlake */
3574 if (INTEL_INFO(dev)->gen < 5)
3575 return 0;
3576
3577 /* RC6 is only on Ironlake mobile not on desktop */
3578 if (INTEL_INFO(dev)->gen == 5 && !IS_IRONLAKE_M(dev))
3579 return 0;
3580
3581 /* Respect the kernel parameter if it is set */
3582 if (enable_rc6 >= 0) {
3583 int mask;
3584
3585 if (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
3586 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
3587 INTEL_RC6pp_ENABLE;
3588 else
3589 mask = INTEL_RC6_ENABLE;
3590
3591 if ((enable_rc6 & mask) != enable_rc6)
3592 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
3593 enable_rc6 & mask, enable_rc6, mask);
3594
3595 return enable_rc6 & mask;
3596 }
3597
3598 /* Disable RC6 on Ironlake */
3599 if (INTEL_INFO(dev)->gen == 5)
3600 return 0;
3601
3602 if (IS_IVYBRIDGE(dev))
3603 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
3604
3605 return INTEL_RC6_ENABLE;
3606 }
3607
3608 int intel_enable_rc6(const struct drm_device *dev)
3609 {
3610 return i915.enable_rc6;
3611 }
3612
3613 static void gen8_enable_rps_interrupts(struct drm_device *dev)
3614 {
3615 struct drm_i915_private *dev_priv = dev->dev_private;
3616
3617 spin_lock_irq(&dev_priv->irq_lock);
3618 WARN_ON(dev_priv->rps.pm_iir);
3619 gen8_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
3620 I915_WRITE(GEN8_GT_IIR(2), dev_priv->pm_rps_events);
3621 spin_unlock_irq(&dev_priv->irq_lock);
3622 }
3623
3624 static void gen6_enable_rps_interrupts(struct drm_device *dev)
3625 {
3626 struct drm_i915_private *dev_priv = dev->dev_private;
3627
3628 spin_lock_irq(&dev_priv->irq_lock);
3629 WARN_ON(dev_priv->rps.pm_iir);
3630 gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
3631 I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events);
3632 spin_unlock_irq(&dev_priv->irq_lock);
3633 }
3634
3635 static void parse_rp_state_cap(struct drm_i915_private *dev_priv, u32 rp_state_cap)
3636 {
3637 /* All of these values are in units of 50MHz */
3638 dev_priv->rps.cur_freq = 0;
3639 /* static values from HW: RP0 < RPe < RP1 < RPn (min_freq) */
3640 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
3641 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
3642 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
3643 /* XXX: only BYT has a special efficient freq */
3644 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
3645 /* hw_max = RP0 until we check for overclocking */
3646 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
3647
3648 /* Preserve min/max settings in case of re-init */
3649 if (dev_priv->rps.max_freq_softlimit == 0)
3650 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
3651
3652 if (dev_priv->rps.min_freq_softlimit == 0)
3653 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
3654 }
3655
3656 static void gen8_enable_rps(struct drm_device *dev)
3657 {
3658 struct drm_i915_private *dev_priv = dev->dev_private;
3659 struct intel_engine_cs *ring;
3660 uint32_t rc6_mask = 0, rp_state_cap;
3661 int unused;
3662
3663 /* 1a: Software RC state - RC0 */
3664 I915_WRITE(GEN6_RC_STATE, 0);
3665
3666 /* 1c & 1d: Get forcewake during program sequence. Although the driver
3667 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
3668 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3669
3670 /* 2a: Disable RC states. */
3671 I915_WRITE(GEN6_RC_CONTROL, 0);
3672
3673 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3674 parse_rp_state_cap(dev_priv, rp_state_cap);
3675
3676 /* 2b: Program RC6 thresholds.*/
3677 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
3678 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
3679 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
3680 for_each_ring(ring, dev_priv, unused)
3681 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3682 I915_WRITE(GEN6_RC_SLEEP, 0);
3683 if (IS_BROADWELL(dev))
3684 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
3685 else
3686 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
3687
3688 /* 3: Enable RC6 */
3689 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
3690 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
3691 intel_print_rc6_info(dev, rc6_mask);
3692 if (IS_BROADWELL(dev))
3693 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
3694 GEN7_RC_CTL_TO_MODE |
3695 rc6_mask);
3696 else
3697 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
3698 GEN6_RC_CTL_EI_MODE(1) |
3699 rc6_mask);
3700
3701 /* 4 Program defaults and thresholds for RPS*/
3702 I915_WRITE(GEN6_RPNSWREQ,
3703 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
3704 I915_WRITE(GEN6_RC_VIDEO_FREQ,
3705 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
3706 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
3707 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
3708
3709 /* Docs recommend 900MHz, and 300 MHz respectively */
3710 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
3711 dev_priv->rps.max_freq_softlimit << 24 |
3712 dev_priv->rps.min_freq_softlimit << 16);
3713
3714 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
3715 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
3716 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
3717 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
3718
3719 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3720
3721 /* 5: Enable RPS */
3722 I915_WRITE(GEN6_RP_CONTROL,
3723 GEN6_RP_MEDIA_TURBO |
3724 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3725 GEN6_RP_MEDIA_IS_GFX |
3726 GEN6_RP_ENABLE |
3727 GEN6_RP_UP_BUSY_AVG |
3728 GEN6_RP_DOWN_IDLE_AVG);
3729
3730 /* 6: Ring frequency + overclocking (our driver does this later */
3731
3732 gen6_set_rps(dev, (I915_READ(GEN6_GT_PERF_STATUS) & 0xff00) >> 8);
3733
3734 gen8_enable_rps_interrupts(dev);
3735
3736 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3737 }
3738
3739 static void gen6_enable_rps(struct drm_device *dev)
3740 {
3741 struct drm_i915_private *dev_priv = dev->dev_private;
3742 struct intel_engine_cs *ring;
3743 u32 rp_state_cap;
3744 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
3745 u32 gtfifodbg;
3746 int rc6_mode;
3747 int i, ret;
3748
3749 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3750
3751 /* Here begins a magic sequence of register writes to enable
3752 * auto-downclocking.
3753 *
3754 * Perhaps there might be some value in exposing these to
3755 * userspace...
3756 */
3757 I915_WRITE(GEN6_RC_STATE, 0);
3758
3759 /* Clear the DBG now so we don't confuse earlier errors */
3760 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3761 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3762 I915_WRITE(GTFIFODBG, gtfifodbg);
3763 }
3764
3765 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3766
3767 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3768
3769 parse_rp_state_cap(dev_priv, rp_state_cap);
3770
3771 /* disable the counters and set deterministic thresholds */
3772 I915_WRITE(GEN6_RC_CONTROL, 0);
3773
3774 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
3775 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
3776 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
3777 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3778 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3779
3780 for_each_ring(ring, dev_priv, i)
3781 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3782
3783 I915_WRITE(GEN6_RC_SLEEP, 0);
3784 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
3785 if (IS_IVYBRIDGE(dev))
3786 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
3787 else
3788 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
3789 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
3790 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
3791
3792 /* Check if we are enabling RC6 */
3793 rc6_mode = intel_enable_rc6(dev_priv->dev);
3794 if (rc6_mode & INTEL_RC6_ENABLE)
3795 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
3796
3797 /* We don't use those on Haswell */
3798 if (!IS_HASWELL(dev)) {
3799 if (rc6_mode & INTEL_RC6p_ENABLE)
3800 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
3801
3802 if (rc6_mode & INTEL_RC6pp_ENABLE)
3803 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
3804 }
3805
3806 intel_print_rc6_info(dev, rc6_mask);
3807
3808 I915_WRITE(GEN6_RC_CONTROL,
3809 rc6_mask |
3810 GEN6_RC_CTL_EI_MODE(1) |
3811 GEN6_RC_CTL_HW_ENABLE);
3812
3813 /* Power down if completely idle for over 50ms */
3814 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
3815 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3816
3817 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
3818 if (ret)
3819 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
3820
3821 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
3822 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
3823 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
3824 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
3825 (pcu_mbox & 0xff) * 50);
3826 dev_priv->rps.max_freq = pcu_mbox & 0xff;
3827 }
3828
3829 dev_priv->rps.power = HIGH_POWER; /* force a reset */
3830 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3831
3832 gen6_enable_rps_interrupts(dev);
3833
3834 rc6vids = 0;
3835 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
3836 if (IS_GEN6(dev) && ret) {
3837 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
3838 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
3839 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
3840 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
3841 rc6vids &= 0xffff00;
3842 rc6vids |= GEN6_ENCODE_RC6_VID(450);
3843 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
3844 if (ret)
3845 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
3846 }
3847
3848 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3849 }
3850
3851 static void __gen6_update_ring_freq(struct drm_device *dev)
3852 {
3853 struct drm_i915_private *dev_priv = dev->dev_private;
3854 int min_freq = 15;
3855 unsigned int gpu_freq;
3856 unsigned int max_ia_freq, min_ring_freq;
3857 int scaling_factor = 180;
3858 struct cpufreq_policy *policy;
3859
3860 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3861
3862 policy = cpufreq_cpu_get(0);
3863 if (policy) {
3864 max_ia_freq = policy->cpuinfo.max_freq;
3865 cpufreq_cpu_put(policy);
3866 } else {
3867 /*
3868 * Default to measured freq if none found, PCU will ensure we
3869 * don't go over
3870 */
3871 max_ia_freq = tsc_khz;
3872 }
3873
3874 /* Convert from kHz to MHz */
3875 max_ia_freq /= 1000;
3876
3877 min_ring_freq = I915_READ(DCLK) & 0xf;
3878 /* convert DDR frequency from units of 266.6MHz to bandwidth */
3879 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3880
3881 /*
3882 * For each potential GPU frequency, load a ring frequency we'd like
3883 * to use for memory access. We do this by specifying the IA frequency
3884 * the PCU should use as a reference to determine the ring frequency.
3885 */
3886 for (gpu_freq = dev_priv->rps.max_freq_softlimit; gpu_freq >= dev_priv->rps.min_freq_softlimit;
3887 gpu_freq--) {
3888 int diff = dev_priv->rps.max_freq_softlimit - gpu_freq;
3889 unsigned int ia_freq = 0, ring_freq = 0;
3890
3891 if (INTEL_INFO(dev)->gen >= 8) {
3892 /* max(2 * GT, DDR). NB: GT is 50MHz units */
3893 ring_freq = max(min_ring_freq, gpu_freq);
3894 } else if (IS_HASWELL(dev)) {
3895 ring_freq = mult_frac(gpu_freq, 5, 4);
3896 ring_freq = max(min_ring_freq, ring_freq);
3897 /* leave ia_freq as the default, chosen by cpufreq */
3898 } else {
3899 /* On older processors, there is no separate ring
3900 * clock domain, so in order to boost the bandwidth
3901 * of the ring, we need to upclock the CPU (ia_freq).
3902 *
3903 * For GPU frequencies less than 750MHz,
3904 * just use the lowest ring freq.
3905 */
3906 if (gpu_freq < min_freq)
3907 ia_freq = 800;
3908 else
3909 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
3910 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
3911 }
3912
3913 sandybridge_pcode_write(dev_priv,
3914 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3915 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
3916 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
3917 gpu_freq);
3918 }
3919 }
3920
3921 void gen6_update_ring_freq(struct drm_device *dev)
3922 {
3923 struct drm_i915_private *dev_priv = dev->dev_private;
3924
3925 if (INTEL_INFO(dev)->gen < 6 || IS_VALLEYVIEW(dev))
3926 return;
3927
3928 mutex_lock(&dev_priv->rps.hw_lock);
3929 __gen6_update_ring_freq(dev);
3930 mutex_unlock(&dev_priv->rps.hw_lock);
3931 }
3932
3933 static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
3934 {
3935 u32 val, rp0;
3936
3937 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
3938 rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & PUNIT_GPU_STATUS_MAX_FREQ_MASK;
3939
3940 return rp0;
3941 }
3942
3943 static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
3944 {
3945 u32 val, rpe;
3946
3947 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
3948 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
3949
3950 return rpe;
3951 }
3952
3953 static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
3954 {
3955 u32 val, rp1;
3956
3957 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
3958 rp1 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & PUNIT_GPU_STATUS_MAX_FREQ_MASK;
3959
3960 return rp1;
3961 }
3962
3963 static int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
3964 {
3965 u32 val, rpn;
3966
3967 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
3968 rpn = (val >> PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT) & PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK;
3969 return rpn;
3970 }
3971
3972 static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
3973 {
3974 u32 val, rp1;
3975
3976 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
3977
3978 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
3979
3980 return rp1;
3981 }
3982
3983 static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
3984 {
3985 u32 val, rp0;
3986
3987 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
3988
3989 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
3990 /* Clamp to max */
3991 rp0 = min_t(u32, rp0, 0xea);
3992
3993 return rp0;
3994 }
3995
3996 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
3997 {
3998 u32 val, rpe;
3999
4000 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
4001 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
4002 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
4003 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
4004
4005 return rpe;
4006 }
4007
4008 static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
4009 {
4010 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
4011 }
4012
4013 /* Check that the pctx buffer wasn't move under us. */
4014 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
4015 {
4016 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
4017
4018 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
4019 dev_priv->vlv_pctx->stolen->start);
4020 }
4021
4022
4023 /* Check that the pcbr address is not empty. */
4024 static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
4025 {
4026 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
4027
4028 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
4029 }
4030
4031 static void cherryview_setup_pctx(struct drm_device *dev)
4032 {
4033 struct drm_i915_private *dev_priv = dev->dev_private;
4034 unsigned long pctx_paddr, paddr;
4035 struct i915_gtt *gtt = &dev_priv->gtt;
4036 u32 pcbr;
4037 int pctx_size = 32*1024;
4038
4039 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4040
4041 pcbr = I915_READ(VLV_PCBR);
4042 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
4043 paddr = (dev_priv->mm.stolen_base +
4044 (gtt->stolen_size - pctx_size));
4045
4046 pctx_paddr = (paddr & (~4095));
4047 I915_WRITE(VLV_PCBR, pctx_paddr);
4048 }
4049 }
4050
4051 static void valleyview_setup_pctx(struct drm_device *dev)
4052 {
4053 struct drm_i915_private *dev_priv = dev->dev_private;
4054 struct drm_i915_gem_object *pctx;
4055 unsigned long pctx_paddr;
4056 u32 pcbr;
4057 int pctx_size = 24*1024;
4058
4059 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4060
4061 pcbr = I915_READ(VLV_PCBR);
4062 if (pcbr) {
4063 /* BIOS set it up already, grab the pre-alloc'd space */
4064 int pcbr_offset;
4065
4066 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
4067 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
4068 pcbr_offset,
4069 I915_GTT_OFFSET_NONE,
4070 pctx_size);
4071 goto out;
4072 }
4073
4074 /*
4075 * From the Gunit register HAS:
4076 * The Gfx driver is expected to program this register and ensure
4077 * proper allocation within Gfx stolen memory. For example, this
4078 * register should be programmed such than the PCBR range does not
4079 * overlap with other ranges, such as the frame buffer, protected
4080 * memory, or any other relevant ranges.
4081 */
4082 pctx = i915_gem_object_create_stolen(dev, pctx_size);
4083 if (!pctx) {
4084 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
4085 return;
4086 }
4087
4088 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
4089 I915_WRITE(VLV_PCBR, pctx_paddr);
4090
4091 out:
4092 dev_priv->vlv_pctx = pctx;
4093 }
4094
4095 static void valleyview_cleanup_pctx(struct drm_device *dev)
4096 {
4097 struct drm_i915_private *dev_priv = dev->dev_private;
4098
4099 if (WARN_ON(!dev_priv->vlv_pctx))
4100 return;
4101
4102 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
4103 dev_priv->vlv_pctx = NULL;
4104 }
4105
4106 static void valleyview_init_gt_powersave(struct drm_device *dev)
4107 {
4108 struct drm_i915_private *dev_priv = dev->dev_private;
4109
4110 valleyview_setup_pctx(dev);
4111
4112 mutex_lock(&dev_priv->rps.hw_lock);
4113
4114 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
4115 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
4116 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
4117 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4118 dev_priv->rps.max_freq);
4119
4120 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
4121 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
4122 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4123 dev_priv->rps.efficient_freq);
4124
4125 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
4126 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
4127 vlv_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
4128 dev_priv->rps.rp1_freq);
4129
4130 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
4131 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
4132 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4133 dev_priv->rps.min_freq);
4134
4135 /* Preserve min/max settings in case of re-init */
4136 if (dev_priv->rps.max_freq_softlimit == 0)
4137 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4138
4139 if (dev_priv->rps.min_freq_softlimit == 0)
4140 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
4141
4142 mutex_unlock(&dev_priv->rps.hw_lock);
4143 }
4144
4145 static void cherryview_init_gt_powersave(struct drm_device *dev)
4146 {
4147 struct drm_i915_private *dev_priv = dev->dev_private;
4148
4149 cherryview_setup_pctx(dev);
4150
4151 mutex_lock(&dev_priv->rps.hw_lock);
4152
4153 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
4154 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
4155 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
4156 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4157 dev_priv->rps.max_freq);
4158
4159 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
4160 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
4161 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4162 dev_priv->rps.efficient_freq);
4163
4164 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
4165 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
4166 vlv_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
4167 dev_priv->rps.rp1_freq);
4168
4169 dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv);
4170 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
4171 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4172 dev_priv->rps.min_freq);
4173
4174 /* Preserve min/max settings in case of re-init */
4175 if (dev_priv->rps.max_freq_softlimit == 0)
4176 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4177
4178 if (dev_priv->rps.min_freq_softlimit == 0)
4179 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
4180
4181 mutex_unlock(&dev_priv->rps.hw_lock);
4182 }
4183
4184 static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
4185 {
4186 valleyview_cleanup_pctx(dev);
4187 }
4188
4189 static void cherryview_enable_rps(struct drm_device *dev)
4190 {
4191 struct drm_i915_private *dev_priv = dev->dev_private;
4192 struct intel_engine_cs *ring;
4193 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
4194 int i;
4195
4196 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4197
4198 gtfifodbg = I915_READ(GTFIFODBG);
4199 if (gtfifodbg) {
4200 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4201 gtfifodbg);
4202 I915_WRITE(GTFIFODBG, gtfifodbg);
4203 }
4204
4205 cherryview_check_pctx(dev_priv);
4206
4207 /* 1a & 1b: Get forcewake during program sequence. Although the driver
4208 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4209 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
4210
4211 /* 2a: Program RC6 thresholds.*/
4212 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4213 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4214 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4215
4216 for_each_ring(ring, dev_priv, i)
4217 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4218 I915_WRITE(GEN6_RC_SLEEP, 0);
4219
4220 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
4221
4222 /* allows RC6 residency counter to work */
4223 I915_WRITE(VLV_COUNTER_CONTROL,
4224 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
4225 VLV_MEDIA_RC6_COUNT_EN |
4226 VLV_RENDER_RC6_COUNT_EN));
4227
4228 /* For now we assume BIOS is allocating and populating the PCBR */
4229 pcbr = I915_READ(VLV_PCBR);
4230
4231 DRM_DEBUG_DRIVER("PCBR offset : 0x%x\n", pcbr);
4232
4233 /* 3: Enable RC6 */
4234 if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
4235 (pcbr >> VLV_PCBR_ADDR_SHIFT))
4236 rc6_mode = GEN6_RC_CTL_EI_MODE(1);
4237
4238 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
4239
4240 /* 4 Program defaults and thresholds for RPS*/
4241 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
4242 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
4243 I915_WRITE(GEN6_RP_UP_EI, 66000);
4244 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
4245
4246 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4247
4248 /* WaDisablePwrmtrEvent:chv (pre-production hw) */
4249 I915_WRITE(0xA80C, I915_READ(0xA80C) & 0x00ffffff);
4250 I915_WRITE(0xA810, I915_READ(0xA810) & 0xffffff00);
4251
4252 /* 5: Enable RPS */
4253 I915_WRITE(GEN6_RP_CONTROL,
4254 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4255 GEN6_RP_MEDIA_IS_GFX | /* WaSetMaskForGfxBusyness:chv (pre-production hw ?) */
4256 GEN6_RP_ENABLE |
4257 GEN6_RP_UP_BUSY_AVG |
4258 GEN6_RP_DOWN_IDLE_AVG);
4259
4260 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4261
4262 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
4263 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
4264
4265 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
4266 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
4267 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
4268 dev_priv->rps.cur_freq);
4269
4270 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
4271 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4272 dev_priv->rps.efficient_freq);
4273
4274 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
4275
4276 gen8_enable_rps_interrupts(dev);
4277
4278 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
4279 }
4280
4281 static void valleyview_enable_rps(struct drm_device *dev)
4282 {
4283 struct drm_i915_private *dev_priv = dev->dev_private;
4284 struct intel_engine_cs *ring;
4285 u32 gtfifodbg, val, rc6_mode = 0;
4286 int i;
4287
4288 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4289
4290 valleyview_check_pctx(dev_priv);
4291
4292 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
4293 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4294 gtfifodbg);
4295 I915_WRITE(GTFIFODBG, gtfifodbg);
4296 }
4297
4298 /* If VLV, Forcewake all wells, else re-direct to regular path */
4299 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
4300
4301 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
4302 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
4303 I915_WRITE(GEN6_RP_UP_EI, 66000);
4304 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
4305
4306 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4307 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 0xf4240);
4308
4309 I915_WRITE(GEN6_RP_CONTROL,
4310 GEN6_RP_MEDIA_TURBO |
4311 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4312 GEN6_RP_MEDIA_IS_GFX |
4313 GEN6_RP_ENABLE |
4314 GEN6_RP_UP_BUSY_AVG |
4315 GEN6_RP_DOWN_IDLE_CONT);
4316
4317 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
4318 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4319 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4320
4321 for_each_ring(ring, dev_priv, i)
4322 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4323
4324 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
4325
4326 /* allows RC6 residency counter to work */
4327 I915_WRITE(VLV_COUNTER_CONTROL,
4328 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
4329 VLV_RENDER_RC0_COUNT_EN |
4330 VLV_MEDIA_RC6_COUNT_EN |
4331 VLV_RENDER_RC6_COUNT_EN));
4332
4333 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4334 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
4335
4336 intel_print_rc6_info(dev, rc6_mode);
4337
4338 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
4339
4340 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4341
4342 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
4343 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
4344
4345 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
4346 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
4347 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
4348 dev_priv->rps.cur_freq);
4349
4350 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
4351 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4352 dev_priv->rps.efficient_freq);
4353
4354 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
4355
4356 gen6_enable_rps_interrupts(dev);
4357
4358 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
4359 }
4360
4361 void ironlake_teardown_rc6(struct drm_device *dev)
4362 {
4363 struct drm_i915_private *dev_priv = dev->dev_private;
4364
4365 if (dev_priv->ips.renderctx) {
4366 i915_gem_object_ggtt_unpin(dev_priv->ips.renderctx);
4367 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
4368 dev_priv->ips.renderctx = NULL;
4369 }
4370
4371 if (dev_priv->ips.pwrctx) {
4372 i915_gem_object_ggtt_unpin(dev_priv->ips.pwrctx);
4373 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
4374 dev_priv->ips.pwrctx = NULL;
4375 }
4376 }
4377
4378 static void ironlake_disable_rc6(struct drm_device *dev)
4379 {
4380 struct drm_i915_private *dev_priv = dev->dev_private;
4381
4382 if (I915_READ(PWRCTXA)) {
4383 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
4384 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
4385 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
4386 50);
4387
4388 I915_WRITE(PWRCTXA, 0);
4389 POSTING_READ(PWRCTXA);
4390
4391 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
4392 POSTING_READ(RSTDBYCTL);
4393 }
4394 }
4395
4396 static int ironlake_setup_rc6(struct drm_device *dev)
4397 {
4398 struct drm_i915_private *dev_priv = dev->dev_private;
4399
4400 if (dev_priv->ips.renderctx == NULL)
4401 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
4402 if (!dev_priv->ips.renderctx)
4403 return -ENOMEM;
4404
4405 if (dev_priv->ips.pwrctx == NULL)
4406 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
4407 if (!dev_priv->ips.pwrctx) {
4408 ironlake_teardown_rc6(dev);
4409 return -ENOMEM;
4410 }
4411
4412 return 0;
4413 }
4414
4415 static void ironlake_enable_rc6(struct drm_device *dev)
4416 {
4417 struct drm_i915_private *dev_priv = dev->dev_private;
4418 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
4419 bool was_interruptible;
4420 int ret;
4421
4422 /* rc6 disabled by default due to repeated reports of hanging during
4423 * boot and resume.
4424 */
4425 if (!intel_enable_rc6(dev))
4426 return;
4427
4428 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4429
4430 ret = ironlake_setup_rc6(dev);
4431 if (ret)
4432 return;
4433
4434 was_interruptible = dev_priv->mm.interruptible;
4435 dev_priv->mm.interruptible = false;
4436
4437 /*
4438 * GPU can automatically power down the render unit if given a page
4439 * to save state.
4440 */
4441 ret = intel_ring_begin(ring, 6);
4442 if (ret) {
4443 ironlake_teardown_rc6(dev);
4444 dev_priv->mm.interruptible = was_interruptible;
4445 return;
4446 }
4447
4448 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
4449 intel_ring_emit(ring, MI_SET_CONTEXT);
4450 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) |
4451 MI_MM_SPACE_GTT |
4452 MI_SAVE_EXT_STATE_EN |
4453 MI_RESTORE_EXT_STATE_EN |
4454 MI_RESTORE_INHIBIT);
4455 intel_ring_emit(ring, MI_SUSPEND_FLUSH);
4456 intel_ring_emit(ring, MI_NOOP);
4457 intel_ring_emit(ring, MI_FLUSH);
4458 intel_ring_advance(ring);
4459
4460 /*
4461 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
4462 * does an implicit flush, combined with MI_FLUSH above, it should be
4463 * safe to assume that renderctx is valid
4464 */
4465 ret = intel_ring_idle(ring);
4466 dev_priv->mm.interruptible = was_interruptible;
4467 if (ret) {
4468 DRM_ERROR("failed to enable ironlake power savings\n");
4469 ironlake_teardown_rc6(dev);
4470 return;
4471 }
4472
4473 I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN);
4474 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
4475
4476 intel_print_rc6_info(dev, GEN6_RC_CTL_RC6_ENABLE);
4477 }
4478
4479 static unsigned long intel_pxfreq(u32 vidfreq)
4480 {
4481 unsigned long freq;
4482 int div = (vidfreq & 0x3f0000) >> 16;
4483 int post = (vidfreq & 0x3000) >> 12;
4484 int pre = (vidfreq & 0x7);
4485
4486 if (!pre)
4487 return 0;
4488
4489 freq = ((div * 133333) / ((1<<post) * pre));
4490
4491 return freq;
4492 }
4493
4494 static const struct cparams {
4495 u16 i;
4496 u16 t;
4497 u16 m;
4498 u16 c;
4499 } cparams[] = {
4500 { 1, 1333, 301, 28664 },
4501 { 1, 1066, 294, 24460 },
4502 { 1, 800, 294, 25192 },
4503 { 0, 1333, 276, 27605 },
4504 { 0, 1066, 276, 27605 },
4505 { 0, 800, 231, 23784 },
4506 };
4507
4508 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
4509 {
4510 u64 total_count, diff, ret;
4511 u32 count1, count2, count3, m = 0, c = 0;
4512 unsigned long now = jiffies_to_msecs(jiffies), diff1;
4513 int i;
4514
4515 assert_spin_locked(&mchdev_lock);
4516
4517 diff1 = now - dev_priv->ips.last_time1;
4518
4519 /* Prevent division-by-zero if we are asking too fast.
4520 * Also, we don't get interesting results if we are polling
4521 * faster than once in 10ms, so just return the saved value
4522 * in such cases.
4523 */
4524 if (diff1 <= 10)
4525 return dev_priv->ips.chipset_power;
4526
4527 count1 = I915_READ(DMIEC);
4528 count2 = I915_READ(DDREC);
4529 count3 = I915_READ(CSIEC);
4530
4531 total_count = count1 + count2 + count3;
4532
4533 /* FIXME: handle per-counter overflow */
4534 if (total_count < dev_priv->ips.last_count1) {
4535 diff = ~0UL - dev_priv->ips.last_count1;
4536 diff += total_count;
4537 } else {
4538 diff = total_count - dev_priv->ips.last_count1;
4539 }
4540
4541 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
4542 if (cparams[i].i == dev_priv->ips.c_m &&
4543 cparams[i].t == dev_priv->ips.r_t) {
4544 m = cparams[i].m;
4545 c = cparams[i].c;
4546 break;
4547 }
4548 }
4549
4550 diff = div_u64(diff, diff1);
4551 ret = ((m * diff) + c);
4552 ret = div_u64(ret, 10);
4553
4554 dev_priv->ips.last_count1 = total_count;
4555 dev_priv->ips.last_time1 = now;
4556
4557 dev_priv->ips.chipset_power = ret;
4558
4559 return ret;
4560 }
4561
4562 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
4563 {
4564 struct drm_device *dev = dev_priv->dev;
4565 unsigned long val;
4566
4567 if (INTEL_INFO(dev)->gen != 5)
4568 return 0;
4569
4570 spin_lock_irq(&mchdev_lock);
4571
4572 val = __i915_chipset_val(dev_priv);
4573
4574 spin_unlock_irq(&mchdev_lock);
4575
4576 return val;
4577 }
4578
4579 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
4580 {
4581 unsigned long m, x, b;
4582 u32 tsfs;
4583
4584 tsfs = I915_READ(TSFS);
4585
4586 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
4587 x = I915_READ8(TR1);
4588
4589 b = tsfs & TSFS_INTR_MASK;
4590
4591 return ((m * x) / 127) - b;
4592 }
4593
4594 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
4595 {
4596 struct drm_device *dev = dev_priv->dev;
4597 static const struct v_table {
4598 u16 vd; /* in .1 mil */
4599 u16 vm; /* in .1 mil */
4600 } v_table[] = {
4601 { 0, 0, },
4602 { 375, 0, },
4603 { 500, 0, },
4604 { 625, 0, },
4605 { 750, 0, },
4606 { 875, 0, },
4607 { 1000, 0, },
4608 { 1125, 0, },
4609 { 4125, 3000, },
4610 { 4125, 3000, },
4611 { 4125, 3000, },
4612 { 4125, 3000, },
4613 { 4125, 3000, },
4614 { 4125, 3000, },
4615 { 4125, 3000, },
4616 { 4125, 3000, },
4617 { 4125, 3000, },
4618 { 4125, 3000, },
4619 { 4125, 3000, },
4620 { 4125, 3000, },
4621 { 4125, 3000, },
4622 { 4125, 3000, },
4623 { 4125, 3000, },
4624 { 4125, 3000, },
4625 { 4125, 3000, },
4626 { 4125, 3000, },
4627 { 4125, 3000, },
4628 { 4125, 3000, },
4629 { 4125, 3000, },
4630 { 4125, 3000, },
4631 { 4125, 3000, },
4632 { 4125, 3000, },
4633 { 4250, 3125, },
4634 { 4375, 3250, },
4635 { 4500, 3375, },
4636 { 4625, 3500, },
4637 { 4750, 3625, },
4638 { 4875, 3750, },
4639 { 5000, 3875, },
4640 { 5125, 4000, },
4641 { 5250, 4125, },
4642 { 5375, 4250, },
4643 { 5500, 4375, },
4644 { 5625, 4500, },
4645 { 5750, 4625, },
4646 { 5875, 4750, },
4647 { 6000, 4875, },
4648 { 6125, 5000, },
4649 { 6250, 5125, },
4650 { 6375, 5250, },
4651 { 6500, 5375, },
4652 { 6625, 5500, },
4653 { 6750, 5625, },
4654 { 6875, 5750, },
4655 { 7000, 5875, },
4656 { 7125, 6000, },
4657 { 7250, 6125, },
4658 { 7375, 6250, },
4659 { 7500, 6375, },
4660 { 7625, 6500, },
4661 { 7750, 6625, },
4662 { 7875, 6750, },
4663 { 8000, 6875, },
4664 { 8125, 7000, },
4665 { 8250, 7125, },
4666 { 8375, 7250, },
4667 { 8500, 7375, },
4668 { 8625, 7500, },
4669 { 8750, 7625, },
4670 { 8875, 7750, },
4671 { 9000, 7875, },
4672 { 9125, 8000, },
4673 { 9250, 8125, },
4674 { 9375, 8250, },
4675 { 9500, 8375, },
4676 { 9625, 8500, },
4677 { 9750, 8625, },
4678 { 9875, 8750, },
4679 { 10000, 8875, },
4680 { 10125, 9000, },
4681 { 10250, 9125, },
4682 { 10375, 9250, },
4683 { 10500, 9375, },
4684 { 10625, 9500, },
4685 { 10750, 9625, },
4686 { 10875, 9750, },
4687 { 11000, 9875, },
4688 { 11125, 10000, },
4689 { 11250, 10125, },
4690 { 11375, 10250, },
4691 { 11500, 10375, },
4692 { 11625, 10500, },
4693 { 11750, 10625, },
4694 { 11875, 10750, },
4695 { 12000, 10875, },
4696 { 12125, 11000, },
4697 { 12250, 11125, },
4698 { 12375, 11250, },
4699 { 12500, 11375, },
4700 { 12625, 11500, },
4701 { 12750, 11625, },
4702 { 12875, 11750, },
4703 { 13000, 11875, },
4704 { 13125, 12000, },
4705 { 13250, 12125, },
4706 { 13375, 12250, },
4707 { 13500, 12375, },
4708 { 13625, 12500, },
4709 { 13750, 12625, },
4710 { 13875, 12750, },
4711 { 14000, 12875, },
4712 { 14125, 13000, },
4713 { 14250, 13125, },
4714 { 14375, 13250, },
4715 { 14500, 13375, },
4716 { 14625, 13500, },
4717 { 14750, 13625, },
4718 { 14875, 13750, },
4719 { 15000, 13875, },
4720 { 15125, 14000, },
4721 { 15250, 14125, },
4722 { 15375, 14250, },
4723 { 15500, 14375, },
4724 { 15625, 14500, },
4725 { 15750, 14625, },
4726 { 15875, 14750, },
4727 { 16000, 14875, },
4728 { 16125, 15000, },
4729 };
4730 if (INTEL_INFO(dev)->is_mobile)
4731 return v_table[pxvid].vm;
4732 else
4733 return v_table[pxvid].vd;
4734 }
4735
4736 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
4737 {
4738 u64 now, diff, diffms;
4739 u32 count;
4740
4741 assert_spin_locked(&mchdev_lock);
4742
4743 now = ktime_get_raw_ns();
4744 diffms = now - dev_priv->ips.last_time2;
4745 do_div(diffms, NSEC_PER_MSEC);
4746
4747 /* Don't divide by 0 */
4748 if (!diffms)
4749 return;
4750
4751 count = I915_READ(GFXEC);
4752
4753 if (count < dev_priv->ips.last_count2) {
4754 diff = ~0UL - dev_priv->ips.last_count2;
4755 diff += count;
4756 } else {
4757 diff = count - dev_priv->ips.last_count2;
4758 }
4759
4760 dev_priv->ips.last_count2 = count;
4761 dev_priv->ips.last_time2 = now;
4762
4763 /* More magic constants... */
4764 diff = diff * 1181;
4765 diff = div_u64(diff, diffms * 10);
4766 dev_priv->ips.gfx_power = diff;
4767 }
4768
4769 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
4770 {
4771 struct drm_device *dev = dev_priv->dev;
4772
4773 if (INTEL_INFO(dev)->gen != 5)
4774 return;
4775
4776 spin_lock_irq(&mchdev_lock);
4777
4778 __i915_update_gfx_val(dev_priv);
4779
4780 spin_unlock_irq(&mchdev_lock);
4781 }
4782
4783 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
4784 {
4785 unsigned long t, corr, state1, corr2, state2;
4786 u32 pxvid, ext_v;
4787
4788 assert_spin_locked(&mchdev_lock);
4789
4790 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_freq * 4));
4791 pxvid = (pxvid >> 24) & 0x7f;
4792 ext_v = pvid_to_extvid(dev_priv, pxvid);
4793
4794 state1 = ext_v;
4795
4796 t = i915_mch_val(dev_priv);
4797
4798 /* Revel in the empirically derived constants */
4799
4800 /* Correction factor in 1/100000 units */
4801 if (t > 80)
4802 corr = ((t * 2349) + 135940);
4803 else if (t >= 50)
4804 corr = ((t * 964) + 29317);
4805 else /* < 50 */
4806 corr = ((t * 301) + 1004);
4807
4808 corr = corr * ((150142 * state1) / 10000 - 78642);
4809 corr /= 100000;
4810 corr2 = (corr * dev_priv->ips.corr);
4811
4812 state2 = (corr2 * state1) / 10000;
4813 state2 /= 100; /* convert to mW */
4814
4815 __i915_update_gfx_val(dev_priv);
4816
4817 return dev_priv->ips.gfx_power + state2;
4818 }
4819
4820 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
4821 {
4822 struct drm_device *dev = dev_priv->dev;
4823 unsigned long val;
4824
4825 if (INTEL_INFO(dev)->gen != 5)
4826 return 0;
4827
4828 spin_lock_irq(&mchdev_lock);
4829
4830 val = __i915_gfx_val(dev_priv);
4831
4832 spin_unlock_irq(&mchdev_lock);
4833
4834 return val;
4835 }
4836
4837 /**
4838 * i915_read_mch_val - return value for IPS use
4839 *
4840 * Calculate and return a value for the IPS driver to use when deciding whether
4841 * we have thermal and power headroom to increase CPU or GPU power budget.
4842 */
4843 unsigned long i915_read_mch_val(void)
4844 {
4845 struct drm_i915_private *dev_priv;
4846 unsigned long chipset_val, graphics_val, ret = 0;
4847
4848 spin_lock_irq(&mchdev_lock);
4849 if (!i915_mch_dev)
4850 goto out_unlock;
4851 dev_priv = i915_mch_dev;
4852
4853 chipset_val = __i915_chipset_val(dev_priv);
4854 graphics_val = __i915_gfx_val(dev_priv);
4855
4856 ret = chipset_val + graphics_val;
4857
4858 out_unlock:
4859 spin_unlock_irq(&mchdev_lock);
4860
4861 return ret;
4862 }
4863 EXPORT_SYMBOL_GPL(i915_read_mch_val);
4864
4865 /**
4866 * i915_gpu_raise - raise GPU frequency limit
4867 *
4868 * Raise the limit; IPS indicates we have thermal headroom.
4869 */
4870 bool i915_gpu_raise(void)
4871 {
4872 struct drm_i915_private *dev_priv;
4873 bool ret = true;
4874
4875 spin_lock_irq(&mchdev_lock);
4876 if (!i915_mch_dev) {
4877 ret = false;
4878 goto out_unlock;
4879 }
4880 dev_priv = i915_mch_dev;
4881
4882 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
4883 dev_priv->ips.max_delay--;
4884
4885 out_unlock:
4886 spin_unlock_irq(&mchdev_lock);
4887
4888 return ret;
4889 }
4890 EXPORT_SYMBOL_GPL(i915_gpu_raise);
4891
4892 /**
4893 * i915_gpu_lower - lower GPU frequency limit
4894 *
4895 * IPS indicates we're close to a thermal limit, so throttle back the GPU
4896 * frequency maximum.
4897 */
4898 bool i915_gpu_lower(void)
4899 {
4900 struct drm_i915_private *dev_priv;
4901 bool ret = true;
4902
4903 spin_lock_irq(&mchdev_lock);
4904 if (!i915_mch_dev) {
4905 ret = false;
4906 goto out_unlock;
4907 }
4908 dev_priv = i915_mch_dev;
4909
4910 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
4911 dev_priv->ips.max_delay++;
4912
4913 out_unlock:
4914 spin_unlock_irq(&mchdev_lock);
4915
4916 return ret;
4917 }
4918 EXPORT_SYMBOL_GPL(i915_gpu_lower);
4919
4920 /**
4921 * i915_gpu_busy - indicate GPU business to IPS
4922 *
4923 * Tell the IPS driver whether or not the GPU is busy.
4924 */
4925 bool i915_gpu_busy(void)
4926 {
4927 struct drm_i915_private *dev_priv;
4928 struct intel_engine_cs *ring;
4929 bool ret = false;
4930 int i;
4931
4932 spin_lock_irq(&mchdev_lock);
4933 if (!i915_mch_dev)
4934 goto out_unlock;
4935 dev_priv = i915_mch_dev;
4936
4937 for_each_ring(ring, dev_priv, i)
4938 ret |= !list_empty(&ring->request_list);
4939
4940 out_unlock:
4941 spin_unlock_irq(&mchdev_lock);
4942
4943 return ret;
4944 }
4945 EXPORT_SYMBOL_GPL(i915_gpu_busy);
4946
4947 /**
4948 * i915_gpu_turbo_disable - disable graphics turbo
4949 *
4950 * Disable graphics turbo by resetting the max frequency and setting the
4951 * current frequency to the default.
4952 */
4953 bool i915_gpu_turbo_disable(void)
4954 {
4955 struct drm_i915_private *dev_priv;
4956 bool ret = true;
4957
4958 spin_lock_irq(&mchdev_lock);
4959 if (!i915_mch_dev) {
4960 ret = false;
4961 goto out_unlock;
4962 }
4963 dev_priv = i915_mch_dev;
4964
4965 dev_priv->ips.max_delay = dev_priv->ips.fstart;
4966
4967 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
4968 ret = false;
4969
4970 out_unlock:
4971 spin_unlock_irq(&mchdev_lock);
4972
4973 return ret;
4974 }
4975 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
4976
4977 /**
4978 * Tells the intel_ips driver that the i915 driver is now loaded, if
4979 * IPS got loaded first.
4980 *
4981 * This awkward dance is so that neither module has to depend on the
4982 * other in order for IPS to do the appropriate communication of
4983 * GPU turbo limits to i915.
4984 */
4985 static void
4986 ips_ping_for_i915_load(void)
4987 {
4988 void (*link)(void);
4989
4990 link = symbol_get(ips_link_to_i915_driver);
4991 if (link) {
4992 link();
4993 symbol_put(ips_link_to_i915_driver);
4994 }
4995 }
4996
4997 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
4998 {
4999 /* We only register the i915 ips part with intel-ips once everything is
5000 * set up, to avoid intel-ips sneaking in and reading bogus values. */
5001 spin_lock_irq(&mchdev_lock);
5002 i915_mch_dev = dev_priv;
5003 spin_unlock_irq(&mchdev_lock);
5004
5005 ips_ping_for_i915_load();
5006 }
5007
5008 void intel_gpu_ips_teardown(void)
5009 {
5010 spin_lock_irq(&mchdev_lock);
5011 i915_mch_dev = NULL;
5012 spin_unlock_irq(&mchdev_lock);
5013 }
5014
5015 static void intel_init_emon(struct drm_device *dev)
5016 {
5017 struct drm_i915_private *dev_priv = dev->dev_private;
5018 u32 lcfuse;
5019 u8 pxw[16];
5020 int i;
5021
5022 /* Disable to program */
5023 I915_WRITE(ECR, 0);
5024 POSTING_READ(ECR);
5025
5026 /* Program energy weights for various events */
5027 I915_WRITE(SDEW, 0x15040d00);
5028 I915_WRITE(CSIEW0, 0x007f0000);
5029 I915_WRITE(CSIEW1, 0x1e220004);
5030 I915_WRITE(CSIEW2, 0x04000004);
5031
5032 for (i = 0; i < 5; i++)
5033 I915_WRITE(PEW + (i * 4), 0);
5034 for (i = 0; i < 3; i++)
5035 I915_WRITE(DEW + (i * 4), 0);
5036
5037 /* Program P-state weights to account for frequency power adjustment */
5038 for (i = 0; i < 16; i++) {
5039 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
5040 unsigned long freq = intel_pxfreq(pxvidfreq);
5041 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5042 PXVFREQ_PX_SHIFT;
5043 unsigned long val;
5044
5045 val = vid * vid;
5046 val *= (freq / 1000);
5047 val *= 255;
5048 val /= (127*127*900);
5049 if (val > 0xff)
5050 DRM_ERROR("bad pxval: %ld\n", val);
5051 pxw[i] = val;
5052 }
5053 /* Render standby states get 0 weight */
5054 pxw[14] = 0;
5055 pxw[15] = 0;
5056
5057 for (i = 0; i < 4; i++) {
5058 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5059 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
5060 I915_WRITE(PXW + (i * 4), val);
5061 }
5062
5063 /* Adjust magic regs to magic values (more experimental results) */
5064 I915_WRITE(OGW0, 0);
5065 I915_WRITE(OGW1, 0);
5066 I915_WRITE(EG0, 0x00007f00);
5067 I915_WRITE(EG1, 0x0000000e);
5068 I915_WRITE(EG2, 0x000e0000);
5069 I915_WRITE(EG3, 0x68000300);
5070 I915_WRITE(EG4, 0x42000000);
5071 I915_WRITE(EG5, 0x00140031);
5072 I915_WRITE(EG6, 0);
5073 I915_WRITE(EG7, 0);
5074
5075 for (i = 0; i < 8; i++)
5076 I915_WRITE(PXWL + (i * 4), 0);
5077
5078 /* Enable PMON + select events */
5079 I915_WRITE(ECR, 0x80000019);
5080
5081 lcfuse = I915_READ(LCFUSE02);
5082
5083 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
5084 }
5085
5086 void intel_init_gt_powersave(struct drm_device *dev)
5087 {
5088 i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
5089
5090 if (IS_CHERRYVIEW(dev))
5091 cherryview_init_gt_powersave(dev);
5092 else if (IS_VALLEYVIEW(dev))
5093 valleyview_init_gt_powersave(dev);
5094 }
5095
5096 void intel_cleanup_gt_powersave(struct drm_device *dev)
5097 {
5098 if (IS_CHERRYVIEW(dev))
5099 return;
5100 else if (IS_VALLEYVIEW(dev))
5101 valleyview_cleanup_gt_powersave(dev);
5102 }
5103
5104 /**
5105 * intel_suspend_gt_powersave - suspend PM work and helper threads
5106 * @dev: drm device
5107 *
5108 * We don't want to disable RC6 or other features here, we just want
5109 * to make sure any work we've queued has finished and won't bother
5110 * us while we're suspended.
5111 */
5112 void intel_suspend_gt_powersave(struct drm_device *dev)
5113 {
5114 struct drm_i915_private *dev_priv = dev->dev_private;
5115
5116 /* Interrupts should be disabled already to avoid re-arming. */
5117 WARN_ON(intel_irqs_enabled(dev_priv));
5118
5119 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
5120
5121 cancel_work_sync(&dev_priv->rps.work);
5122
5123 /* Force GPU to min freq during suspend */
5124 gen6_rps_idle(dev_priv);
5125 }
5126
5127 void intel_disable_gt_powersave(struct drm_device *dev)
5128 {
5129 struct drm_i915_private *dev_priv = dev->dev_private;
5130
5131 /* Interrupts should be disabled already to avoid re-arming. */
5132 WARN_ON(intel_irqs_enabled(dev_priv));
5133
5134 if (IS_IRONLAKE_M(dev)) {
5135 ironlake_disable_drps(dev);
5136 ironlake_disable_rc6(dev);
5137 } else if (INTEL_INFO(dev)->gen >= 6) {
5138 intel_suspend_gt_powersave(dev);
5139
5140 mutex_lock(&dev_priv->rps.hw_lock);
5141 if (IS_CHERRYVIEW(dev))
5142 cherryview_disable_rps(dev);
5143 else if (IS_VALLEYVIEW(dev))
5144 valleyview_disable_rps(dev);
5145 else
5146 gen6_disable_rps(dev);
5147 dev_priv->rps.enabled = false;
5148 mutex_unlock(&dev_priv->rps.hw_lock);
5149 }
5150 }
5151
5152 static void intel_gen6_powersave_work(struct work_struct *work)
5153 {
5154 struct drm_i915_private *dev_priv =
5155 container_of(work, struct drm_i915_private,
5156 rps.delayed_resume_work.work);
5157 struct drm_device *dev = dev_priv->dev;
5158
5159 mutex_lock(&dev_priv->rps.hw_lock);
5160
5161 if (IS_CHERRYVIEW(dev)) {
5162 cherryview_enable_rps(dev);
5163 } else if (IS_VALLEYVIEW(dev)) {
5164 valleyview_enable_rps(dev);
5165 } else if (IS_BROADWELL(dev)) {
5166 gen8_enable_rps(dev);
5167 __gen6_update_ring_freq(dev);
5168 } else {
5169 gen6_enable_rps(dev);
5170 __gen6_update_ring_freq(dev);
5171 }
5172 dev_priv->rps.enabled = true;
5173 mutex_unlock(&dev_priv->rps.hw_lock);
5174
5175 intel_runtime_pm_put(dev_priv);
5176 }
5177
5178 void intel_enable_gt_powersave(struct drm_device *dev)
5179 {
5180 struct drm_i915_private *dev_priv = dev->dev_private;
5181
5182 if (IS_IRONLAKE_M(dev)) {
5183 mutex_lock(&dev->struct_mutex);
5184 ironlake_enable_drps(dev);
5185 ironlake_enable_rc6(dev);
5186 intel_init_emon(dev);
5187 mutex_unlock(&dev->struct_mutex);
5188 } else if (INTEL_INFO(dev)->gen >= 6) {
5189 /*
5190 * PCU communication is slow and this doesn't need to be
5191 * done at any specific time, so do this out of our fast path
5192 * to make resume and init faster.
5193 *
5194 * We depend on the HW RC6 power context save/restore
5195 * mechanism when entering D3 through runtime PM suspend. So
5196 * disable RPM until RPS/RC6 is properly setup. We can only
5197 * get here via the driver load/system resume/runtime resume
5198 * paths, so the _noresume version is enough (and in case of
5199 * runtime resume it's necessary).
5200 */
5201 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
5202 round_jiffies_up_relative(HZ)))
5203 intel_runtime_pm_get_noresume(dev_priv);
5204 }
5205 }
5206
5207 void intel_reset_gt_powersave(struct drm_device *dev)
5208 {
5209 struct drm_i915_private *dev_priv = dev->dev_private;
5210
5211 dev_priv->rps.enabled = false;
5212 intel_enable_gt_powersave(dev);
5213 }
5214
5215 static void ibx_init_clock_gating(struct drm_device *dev)
5216 {
5217 struct drm_i915_private *dev_priv = dev->dev_private;
5218
5219 /*
5220 * On Ibex Peak and Cougar Point, we need to disable clock
5221 * gating for the panel power sequencer or it will fail to
5222 * start up when no ports are active.
5223 */
5224 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
5225 }
5226
5227 static void g4x_disable_trickle_feed(struct drm_device *dev)
5228 {
5229 struct drm_i915_private *dev_priv = dev->dev_private;
5230 int pipe;
5231
5232 for_each_pipe(dev_priv, pipe) {
5233 I915_WRITE(DSPCNTR(pipe),
5234 I915_READ(DSPCNTR(pipe)) |
5235 DISPPLANE_TRICKLE_FEED_DISABLE);
5236 intel_flush_primary_plane(dev_priv, pipe);
5237 }
5238 }
5239
5240 static void ilk_init_lp_watermarks(struct drm_device *dev)
5241 {
5242 struct drm_i915_private *dev_priv = dev->dev_private;
5243
5244 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
5245 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
5246 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
5247
5248 /*
5249 * Don't touch WM1S_LP_EN here.
5250 * Doing so could cause underruns.
5251 */
5252 }
5253
5254 static void ironlake_init_clock_gating(struct drm_device *dev)
5255 {
5256 struct drm_i915_private *dev_priv = dev->dev_private;
5257 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
5258
5259 /*
5260 * Required for FBC
5261 * WaFbcDisableDpfcClockGating:ilk
5262 */
5263 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
5264 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
5265 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
5266
5267 I915_WRITE(PCH_3DCGDIS0,
5268 MARIUNIT_CLOCK_GATE_DISABLE |
5269 SVSMUNIT_CLOCK_GATE_DISABLE);
5270 I915_WRITE(PCH_3DCGDIS1,
5271 VFMUNIT_CLOCK_GATE_DISABLE);
5272
5273 /*
5274 * According to the spec the following bits should be set in
5275 * order to enable memory self-refresh
5276 * The bit 22/21 of 0x42004
5277 * The bit 5 of 0x42020
5278 * The bit 15 of 0x45000
5279 */
5280 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5281 (I915_READ(ILK_DISPLAY_CHICKEN2) |
5282 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
5283 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
5284 I915_WRITE(DISP_ARB_CTL,
5285 (I915_READ(DISP_ARB_CTL) |
5286 DISP_FBC_WM_DIS));
5287
5288 ilk_init_lp_watermarks(dev);
5289
5290 /*
5291 * Based on the document from hardware guys the following bits
5292 * should be set unconditionally in order to enable FBC.
5293 * The bit 22 of 0x42000
5294 * The bit 22 of 0x42004
5295 * The bit 7,8,9 of 0x42020.
5296 */
5297 if (IS_IRONLAKE_M(dev)) {
5298 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
5299 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5300 I915_READ(ILK_DISPLAY_CHICKEN1) |
5301 ILK_FBCQ_DIS);
5302 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5303 I915_READ(ILK_DISPLAY_CHICKEN2) |
5304 ILK_DPARB_GATE);
5305 }
5306
5307 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
5308
5309 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5310 I915_READ(ILK_DISPLAY_CHICKEN2) |
5311 ILK_ELPIN_409_SELECT);
5312 I915_WRITE(_3D_CHICKEN2,
5313 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
5314 _3D_CHICKEN2_WM_READ_PIPELINED);
5315
5316 /* WaDisableRenderCachePipelinedFlush:ilk */
5317 I915_WRITE(CACHE_MODE_0,
5318 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
5319
5320 /* WaDisable_RenderCache_OperationalFlush:ilk */
5321 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5322
5323 g4x_disable_trickle_feed(dev);
5324
5325 ibx_init_clock_gating(dev);
5326 }
5327
5328 static void cpt_init_clock_gating(struct drm_device *dev)
5329 {
5330 struct drm_i915_private *dev_priv = dev->dev_private;
5331 int pipe;
5332 uint32_t val;
5333
5334 /*
5335 * On Ibex Peak and Cougar Point, we need to disable clock
5336 * gating for the panel power sequencer or it will fail to
5337 * start up when no ports are active.
5338 */
5339 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
5340 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
5341 PCH_CPUNIT_CLOCK_GATE_DISABLE);
5342 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
5343 DPLS_EDP_PPS_FIX_DIS);
5344 /* The below fixes the weird display corruption, a few pixels shifted
5345 * downward, on (only) LVDS of some HP laptops with IVY.
5346 */
5347 for_each_pipe(dev_priv, pipe) {
5348 val = I915_READ(TRANS_CHICKEN2(pipe));
5349 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
5350 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
5351 if (dev_priv->vbt.fdi_rx_polarity_inverted)
5352 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
5353 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
5354 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
5355 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
5356 I915_WRITE(TRANS_CHICKEN2(pipe), val);
5357 }
5358 /* WADP0ClockGatingDisable */
5359 for_each_pipe(dev_priv, pipe) {
5360 I915_WRITE(TRANS_CHICKEN1(pipe),
5361 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
5362 }
5363 }
5364
5365 static void gen6_check_mch_setup(struct drm_device *dev)
5366 {
5367 struct drm_i915_private *dev_priv = dev->dev_private;
5368 uint32_t tmp;
5369
5370 tmp = I915_READ(MCH_SSKPD);
5371 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
5372 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
5373 tmp);
5374 }
5375
5376 static void gen6_init_clock_gating(struct drm_device *dev)
5377 {
5378 struct drm_i915_private *dev_priv = dev->dev_private;
5379 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
5380
5381 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
5382
5383 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5384 I915_READ(ILK_DISPLAY_CHICKEN2) |
5385 ILK_ELPIN_409_SELECT);
5386
5387 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
5388 I915_WRITE(_3D_CHICKEN,
5389 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
5390
5391 /* WaSetupGtModeTdRowDispatch:snb */
5392 if (IS_SNB_GT1(dev))
5393 I915_WRITE(GEN6_GT_MODE,
5394 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
5395
5396 /* WaDisable_RenderCache_OperationalFlush:snb */
5397 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5398
5399 /*
5400 * BSpec recoomends 8x4 when MSAA is used,
5401 * however in practice 16x4 seems fastest.
5402 *
5403 * Note that PS/WM thread counts depend on the WIZ hashing
5404 * disable bit, which we don't touch here, but it's good
5405 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5406 */
5407 I915_WRITE(GEN6_GT_MODE,
5408 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5409
5410 ilk_init_lp_watermarks(dev);
5411
5412 I915_WRITE(CACHE_MODE_0,
5413 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
5414
5415 I915_WRITE(GEN6_UCGCTL1,
5416 I915_READ(GEN6_UCGCTL1) |
5417 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
5418 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
5419
5420 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5421 * gating disable must be set. Failure to set it results in
5422 * flickering pixels due to Z write ordering failures after
5423 * some amount of runtime in the Mesa "fire" demo, and Unigine
5424 * Sanctuary and Tropics, and apparently anything else with
5425 * alpha test or pixel discard.
5426 *
5427 * According to the spec, bit 11 (RCCUNIT) must also be set,
5428 * but we didn't debug actual testcases to find it out.
5429 *
5430 * WaDisableRCCUnitClockGating:snb
5431 * WaDisableRCPBUnitClockGating:snb
5432 */
5433 I915_WRITE(GEN6_UCGCTL2,
5434 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
5435 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5436
5437 /* WaStripsFansDisableFastClipPerformanceFix:snb */
5438 I915_WRITE(_3D_CHICKEN3,
5439 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
5440
5441 /*
5442 * Bspec says:
5443 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
5444 * 3DSTATE_SF number of SF output attributes is more than 16."
5445 */
5446 I915_WRITE(_3D_CHICKEN3,
5447 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
5448
5449 /*
5450 * According to the spec the following bits should be
5451 * set in order to enable memory self-refresh and fbc:
5452 * The bit21 and bit22 of 0x42000
5453 * The bit21 and bit22 of 0x42004
5454 * The bit5 and bit7 of 0x42020
5455 * The bit14 of 0x70180
5456 * The bit14 of 0x71180
5457 *
5458 * WaFbcAsynchFlipDisableFbcQueue:snb
5459 */
5460 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5461 I915_READ(ILK_DISPLAY_CHICKEN1) |
5462 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
5463 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5464 I915_READ(ILK_DISPLAY_CHICKEN2) |
5465 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
5466 I915_WRITE(ILK_DSPCLK_GATE_D,
5467 I915_READ(ILK_DSPCLK_GATE_D) |
5468 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
5469 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
5470
5471 g4x_disable_trickle_feed(dev);
5472
5473 cpt_init_clock_gating(dev);
5474
5475 gen6_check_mch_setup(dev);
5476 }
5477
5478 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
5479 {
5480 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
5481
5482 /*
5483 * WaVSThreadDispatchOverride:ivb,vlv
5484 *
5485 * This actually overrides the dispatch
5486 * mode for all thread types.
5487 */
5488 reg &= ~GEN7_FF_SCHED_MASK;
5489 reg |= GEN7_FF_TS_SCHED_HW;
5490 reg |= GEN7_FF_VS_SCHED_HW;
5491 reg |= GEN7_FF_DS_SCHED_HW;
5492
5493 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
5494 }
5495
5496 static void lpt_init_clock_gating(struct drm_device *dev)
5497 {
5498 struct drm_i915_private *dev_priv = dev->dev_private;
5499
5500 /*
5501 * TODO: this bit should only be enabled when really needed, then
5502 * disabled when not needed anymore in order to save power.
5503 */
5504 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
5505 I915_WRITE(SOUTH_DSPCLK_GATE_D,
5506 I915_READ(SOUTH_DSPCLK_GATE_D) |
5507 PCH_LP_PARTITION_LEVEL_DISABLE);
5508
5509 /* WADPOClockGatingDisable:hsw */
5510 I915_WRITE(_TRANSA_CHICKEN1,
5511 I915_READ(_TRANSA_CHICKEN1) |
5512 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
5513 }
5514
5515 static void lpt_suspend_hw(struct drm_device *dev)
5516 {
5517 struct drm_i915_private *dev_priv = dev->dev_private;
5518
5519 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
5520 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
5521
5522 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
5523 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
5524 }
5525 }
5526
5527 static void broadwell_init_clock_gating(struct drm_device *dev)
5528 {
5529 struct drm_i915_private *dev_priv = dev->dev_private;
5530 enum pipe pipe;
5531
5532 I915_WRITE(WM3_LP_ILK, 0);
5533 I915_WRITE(WM2_LP_ILK, 0);
5534 I915_WRITE(WM1_LP_ILK, 0);
5535
5536 /* FIXME(BDW): Check all the w/a, some might only apply to
5537 * pre-production hw. */
5538
5539 /* WaDisablePartialInstShootdown:bdw */
5540 I915_WRITE(GEN8_ROW_CHICKEN,
5541 _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE));
5542
5543 /* WaDisableThreadStallDopClockGating:bdw */
5544 /* FIXME: Unclear whether we really need this on production bdw. */
5545 I915_WRITE(GEN8_ROW_CHICKEN,
5546 _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
5547
5548 /*
5549 * This GEN8_CENTROID_PIXEL_OPT_DIS W/A is only needed for
5550 * pre-production hardware
5551 */
5552 I915_WRITE(HALF_SLICE_CHICKEN3,
5553 _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS));
5554 I915_WRITE(HALF_SLICE_CHICKEN3,
5555 _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
5556 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE));
5557
5558 I915_WRITE(_3D_CHICKEN3,
5559 _MASKED_BIT_ENABLE(_3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2)));
5560
5561 I915_WRITE(COMMON_SLICE_CHICKEN2,
5562 _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE));
5563
5564 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5565 _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE));
5566
5567 /* WaDisableDopClockGating:bdw May not be needed for production */
5568 I915_WRITE(GEN7_ROW_CHICKEN2,
5569 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5570
5571 /* WaSwitchSolVfFArbitrationPriority:bdw */
5572 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
5573
5574 /* WaPsrDPAMaskVBlankInSRD:bdw */
5575 I915_WRITE(CHICKEN_PAR1_1,
5576 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
5577
5578 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
5579 for_each_pipe(dev_priv, pipe) {
5580 I915_WRITE(CHICKEN_PIPESL_1(pipe),
5581 I915_READ(CHICKEN_PIPESL_1(pipe)) |
5582 BDW_DPRS_MASK_VBLANK_SRD);
5583 }
5584
5585 /* Use Force Non-Coherent whenever executing a 3D context. This is a
5586 * workaround for for a possible hang in the unlikely event a TLB
5587 * invalidation occurs during a PSD flush.
5588 */
5589 I915_WRITE(HDC_CHICKEN0,
5590 I915_READ(HDC_CHICKEN0) |
5591 _MASKED_BIT_ENABLE(HDC_FORCE_NON_COHERENT));
5592
5593 /* WaVSRefCountFullforceMissDisable:bdw */
5594 /* WaDSRefCountFullforceMissDisable:bdw */
5595 I915_WRITE(GEN7_FF_THREAD_MODE,
5596 I915_READ(GEN7_FF_THREAD_MODE) &
5597 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
5598
5599 /*
5600 * BSpec recommends 8x4 when MSAA is used,
5601 * however in practice 16x4 seems fastest.
5602 *
5603 * Note that PS/WM thread counts depend on the WIZ hashing
5604 * disable bit, which we don't touch here, but it's good
5605 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5606 */
5607 I915_WRITE(GEN7_GT_MODE,
5608 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5609
5610 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
5611 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
5612
5613 /* WaDisableSDEUnitClockGating:bdw */
5614 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
5615 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5616
5617 /* Wa4x4STCOptimizationDisable:bdw */
5618 I915_WRITE(CACHE_MODE_1,
5619 _MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE));
5620
5621 lpt_init_clock_gating(dev);
5622 }
5623
5624 static void haswell_init_clock_gating(struct drm_device *dev)
5625 {
5626 struct drm_i915_private *dev_priv = dev->dev_private;
5627
5628 ilk_init_lp_watermarks(dev);
5629
5630 /* L3 caching of data atomics doesn't work -- disable it. */
5631 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
5632 I915_WRITE(HSW_ROW_CHICKEN3,
5633 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
5634
5635 /* This is required by WaCatErrorRejectionIssue:hsw */
5636 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5637 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5638 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5639
5640 /* WaVSRefCountFullforceMissDisable:hsw */
5641 I915_WRITE(GEN7_FF_THREAD_MODE,
5642 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
5643
5644 /* WaDisable_RenderCache_OperationalFlush:hsw */
5645 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5646
5647 /* enable HiZ Raw Stall Optimization */
5648 I915_WRITE(CACHE_MODE_0_GEN7,
5649 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
5650
5651 /* WaDisable4x2SubspanOptimization:hsw */
5652 I915_WRITE(CACHE_MODE_1,
5653 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5654
5655 /*
5656 * BSpec recommends 8x4 when MSAA is used,
5657 * however in practice 16x4 seems fastest.
5658 *
5659 * Note that PS/WM thread counts depend on the WIZ hashing
5660 * disable bit, which we don't touch here, but it's good
5661 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5662 */
5663 I915_WRITE(GEN7_GT_MODE,
5664 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5665
5666 /* WaSwitchSolVfFArbitrationPriority:hsw */
5667 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
5668
5669 /* WaRsPkgCStateDisplayPMReq:hsw */
5670 I915_WRITE(CHICKEN_PAR1_1,
5671 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
5672
5673 lpt_init_clock_gating(dev);
5674 }
5675
5676 static void ivybridge_init_clock_gating(struct drm_device *dev)
5677 {
5678 struct drm_i915_private *dev_priv = dev->dev_private;
5679 uint32_t snpcr;
5680
5681 ilk_init_lp_watermarks(dev);
5682
5683 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
5684
5685 /* WaDisableEarlyCull:ivb */
5686 I915_WRITE(_3D_CHICKEN3,
5687 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5688
5689 /* WaDisableBackToBackFlipFix:ivb */
5690 I915_WRITE(IVB_CHICKEN3,
5691 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5692 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5693
5694 /* WaDisablePSDDualDispatchEnable:ivb */
5695 if (IS_IVB_GT1(dev))
5696 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5697 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5698
5699 /* WaDisable_RenderCache_OperationalFlush:ivb */
5700 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5701
5702 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
5703 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5704 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5705
5706 /* WaApplyL3ControlAndL3ChickenMode:ivb */
5707 I915_WRITE(GEN7_L3CNTLREG1,
5708 GEN7_WA_FOR_GEN7_L3_CONTROL);
5709 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
5710 GEN7_WA_L3_CHICKEN_MODE);
5711 if (IS_IVB_GT1(dev))
5712 I915_WRITE(GEN7_ROW_CHICKEN2,
5713 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5714 else {
5715 /* must write both registers */
5716 I915_WRITE(GEN7_ROW_CHICKEN2,
5717 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5718 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
5719 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5720 }
5721
5722 /* WaForceL3Serialization:ivb */
5723 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5724 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5725
5726 /*
5727 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5728 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
5729 */
5730 I915_WRITE(GEN6_UCGCTL2,
5731 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
5732
5733 /* This is required by WaCatErrorRejectionIssue:ivb */
5734 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5735 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5736 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5737
5738 g4x_disable_trickle_feed(dev);
5739
5740 gen7_setup_fixed_func_scheduler(dev_priv);
5741
5742 if (0) { /* causes HiZ corruption on ivb:gt1 */
5743 /* enable HiZ Raw Stall Optimization */
5744 I915_WRITE(CACHE_MODE_0_GEN7,
5745 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
5746 }
5747
5748 /* WaDisable4x2SubspanOptimization:ivb */
5749 I915_WRITE(CACHE_MODE_1,
5750 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5751
5752 /*
5753 * BSpec recommends 8x4 when MSAA is used,
5754 * however in practice 16x4 seems fastest.
5755 *
5756 * Note that PS/WM thread counts depend on the WIZ hashing
5757 * disable bit, which we don't touch here, but it's good
5758 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5759 */
5760 I915_WRITE(GEN7_GT_MODE,
5761 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5762
5763 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5764 snpcr &= ~GEN6_MBC_SNPCR_MASK;
5765 snpcr |= GEN6_MBC_SNPCR_MED;
5766 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5767
5768 if (!HAS_PCH_NOP(dev))
5769 cpt_init_clock_gating(dev);
5770
5771 gen6_check_mch_setup(dev);
5772 }
5773
5774 static void valleyview_init_clock_gating(struct drm_device *dev)
5775 {
5776 struct drm_i915_private *dev_priv = dev->dev_private;
5777 u32 val;
5778
5779 mutex_lock(&dev_priv->rps.hw_lock);
5780 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5781 mutex_unlock(&dev_priv->rps.hw_lock);
5782 switch ((val >> 6) & 3) {
5783 case 0:
5784 case 1:
5785 dev_priv->mem_freq = 800;
5786 break;
5787 case 2:
5788 dev_priv->mem_freq = 1066;
5789 break;
5790 case 3:
5791 dev_priv->mem_freq = 1333;
5792 break;
5793 }
5794 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
5795
5796 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
5797
5798 /* WaDisableEarlyCull:vlv */
5799 I915_WRITE(_3D_CHICKEN3,
5800 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5801
5802 /* WaDisableBackToBackFlipFix:vlv */
5803 I915_WRITE(IVB_CHICKEN3,
5804 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5805 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5806
5807 /* WaPsdDispatchEnable:vlv */
5808 /* WaDisablePSDDualDispatchEnable:vlv */
5809 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5810 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
5811 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5812
5813 /* WaDisable_RenderCache_OperationalFlush:vlv */
5814 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5815
5816 /* WaForceL3Serialization:vlv */
5817 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5818 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5819
5820 /* WaDisableDopClockGating:vlv */
5821 I915_WRITE(GEN7_ROW_CHICKEN2,
5822 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5823
5824 /* This is required by WaCatErrorRejectionIssue:vlv */
5825 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5826 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5827 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5828
5829 gen7_setup_fixed_func_scheduler(dev_priv);
5830
5831 /*
5832 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5833 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
5834 */
5835 I915_WRITE(GEN6_UCGCTL2,
5836 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
5837
5838 /* WaDisableL3Bank2xClockGate:vlv
5839 * Disabling L3 clock gating- MMIO 940c[25] = 1
5840 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
5841 I915_WRITE(GEN7_UCGCTL4,
5842 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
5843
5844 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
5845
5846 /*
5847 * BSpec says this must be set, even though
5848 * WaDisable4x2SubspanOptimization isn't listed for VLV.
5849 */
5850 I915_WRITE(CACHE_MODE_1,
5851 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5852
5853 /*
5854 * WaIncreaseL3CreditsForVLVB0:vlv
5855 * This is the hardware default actually.
5856 */
5857 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
5858
5859 /*
5860 * WaDisableVLVClockGating_VBIIssue:vlv
5861 * Disable clock gating on th GCFG unit to prevent a delay
5862 * in the reporting of vblank events.
5863 */
5864 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
5865 }
5866
5867 static void cherryview_init_clock_gating(struct drm_device *dev)
5868 {
5869 struct drm_i915_private *dev_priv = dev->dev_private;
5870 u32 val;
5871
5872 mutex_lock(&dev_priv->rps.hw_lock);
5873 val = vlv_punit_read(dev_priv, CCK_FUSE_REG);
5874 mutex_unlock(&dev_priv->rps.hw_lock);
5875 switch ((val >> 2) & 0x7) {
5876 case 0:
5877 case 1:
5878 dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_200;
5879 dev_priv->mem_freq = 1600;
5880 break;
5881 case 2:
5882 dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_267;
5883 dev_priv->mem_freq = 1600;
5884 break;
5885 case 3:
5886 dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_333;
5887 dev_priv->mem_freq = 2000;
5888 break;
5889 case 4:
5890 dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_320;
5891 dev_priv->mem_freq = 1600;
5892 break;
5893 case 5:
5894 dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_400;
5895 dev_priv->mem_freq = 1600;
5896 break;
5897 }
5898 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
5899
5900 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
5901
5902 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
5903
5904 /* WaDisablePartialInstShootdown:chv */
5905 I915_WRITE(GEN8_ROW_CHICKEN,
5906 _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE));
5907
5908 /* WaDisableThreadStallDopClockGating:chv */
5909 I915_WRITE(GEN8_ROW_CHICKEN,
5910 _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
5911
5912 /* WaVSRefCountFullforceMissDisable:chv */
5913 /* WaDSRefCountFullforceMissDisable:chv */
5914 I915_WRITE(GEN7_FF_THREAD_MODE,
5915 I915_READ(GEN7_FF_THREAD_MODE) &
5916 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
5917
5918 /* WaDisableSemaphoreAndSyncFlipWait:chv */
5919 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
5920 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
5921
5922 /* WaDisableCSUnitClockGating:chv */
5923 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
5924 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
5925
5926 /* WaDisableSDEUnitClockGating:chv */
5927 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
5928 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5929
5930 /* WaDisableSamplerPowerBypass:chv (pre-production hw) */
5931 I915_WRITE(HALF_SLICE_CHICKEN3,
5932 _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
5933
5934 /* WaDisableGunitClockGating:chv (pre-production hw) */
5935 I915_WRITE(VLV_GUNIT_CLOCK_GATE, I915_READ(VLV_GUNIT_CLOCK_GATE) |
5936 GINT_DIS);
5937
5938 /* WaDisableFfDopClockGating:chv (pre-production hw) */
5939 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
5940 _MASKED_BIT_ENABLE(GEN8_FF_DOP_CLOCK_GATE_DISABLE));
5941
5942 /* WaDisableDopClockGating:chv (pre-production hw) */
5943 I915_WRITE(GEN7_ROW_CHICKEN2,
5944 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5945 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
5946 GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
5947 }
5948
5949 static void g4x_init_clock_gating(struct drm_device *dev)
5950 {
5951 struct drm_i915_private *dev_priv = dev->dev_private;
5952 uint32_t dspclk_gate;
5953
5954 I915_WRITE(RENCLK_GATE_D1, 0);
5955 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5956 GS_UNIT_CLOCK_GATE_DISABLE |
5957 CL_UNIT_CLOCK_GATE_DISABLE);
5958 I915_WRITE(RAMCLK_GATE_D, 0);
5959 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5960 OVRUNIT_CLOCK_GATE_DISABLE |
5961 OVCUNIT_CLOCK_GATE_DISABLE;
5962 if (IS_GM45(dev))
5963 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5964 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5965
5966 /* WaDisableRenderCachePipelinedFlush */
5967 I915_WRITE(CACHE_MODE_0,
5968 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
5969
5970 /* WaDisable_RenderCache_OperationalFlush:g4x */
5971 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5972
5973 g4x_disable_trickle_feed(dev);
5974 }
5975
5976 static void crestline_init_clock_gating(struct drm_device *dev)
5977 {
5978 struct drm_i915_private *dev_priv = dev->dev_private;
5979
5980 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5981 I915_WRITE(RENCLK_GATE_D2, 0);
5982 I915_WRITE(DSPCLK_GATE_D, 0);
5983 I915_WRITE(RAMCLK_GATE_D, 0);
5984 I915_WRITE16(DEUC, 0);
5985 I915_WRITE(MI_ARB_STATE,
5986 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
5987
5988 /* WaDisable_RenderCache_OperationalFlush:gen4 */
5989 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5990 }
5991
5992 static void broadwater_init_clock_gating(struct drm_device *dev)
5993 {
5994 struct drm_i915_private *dev_priv = dev->dev_private;
5995
5996 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5997 I965_RCC_CLOCK_GATE_DISABLE |
5998 I965_RCPB_CLOCK_GATE_DISABLE |
5999 I965_ISC_CLOCK_GATE_DISABLE |
6000 I965_FBC_CLOCK_GATE_DISABLE);
6001 I915_WRITE(RENCLK_GATE_D2, 0);
6002 I915_WRITE(MI_ARB_STATE,
6003 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6004
6005 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6006 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6007 }
6008
6009 static void gen3_init_clock_gating(struct drm_device *dev)
6010 {
6011 struct drm_i915_private *dev_priv = dev->dev_private;
6012 u32 dstate = I915_READ(D_STATE);
6013
6014 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
6015 DSTATE_DOT_CLOCK_GATING;
6016 I915_WRITE(D_STATE, dstate);
6017
6018 if (IS_PINEVIEW(dev))
6019 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
6020
6021 /* IIR "flip pending" means done if this bit is set */
6022 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
6023
6024 /* interrupts should cause a wake up from C3 */
6025 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
6026
6027 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
6028 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
6029 }
6030
6031 static void i85x_init_clock_gating(struct drm_device *dev)
6032 {
6033 struct drm_i915_private *dev_priv = dev->dev_private;
6034
6035 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
6036
6037 /* interrupts should cause a wake up from C3 */
6038 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
6039 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
6040 }
6041
6042 static void i830_init_clock_gating(struct drm_device *dev)
6043 {
6044 struct drm_i915_private *dev_priv = dev->dev_private;
6045
6046 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
6047 }
6048
6049 void intel_init_clock_gating(struct drm_device *dev)
6050 {
6051 struct drm_i915_private *dev_priv = dev->dev_private;
6052
6053 dev_priv->display.init_clock_gating(dev);
6054 }
6055
6056 void intel_suspend_hw(struct drm_device *dev)
6057 {
6058 if (HAS_PCH_LPT(dev))
6059 lpt_suspend_hw(dev);
6060 }
6061
6062 #define for_each_power_well(i, power_well, domain_mask, power_domains) \
6063 for (i = 0; \
6064 i < (power_domains)->power_well_count && \
6065 ((power_well) = &(power_domains)->power_wells[i]); \
6066 i++) \
6067 if ((power_well)->domains & (domain_mask))
6068
6069 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
6070 for (i = (power_domains)->power_well_count - 1; \
6071 i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
6072 i--) \
6073 if ((power_well)->domains & (domain_mask))
6074
6075 /**
6076 * We should only use the power well if we explicitly asked the hardware to
6077 * enable it, so check if it's enabled and also check if we've requested it to
6078 * be enabled.
6079 */
6080 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
6081 struct i915_power_well *power_well)
6082 {
6083 return I915_READ(HSW_PWR_WELL_DRIVER) ==
6084 (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
6085 }
6086
6087 bool intel_display_power_enabled_unlocked(struct drm_i915_private *dev_priv,
6088 enum intel_display_power_domain domain)
6089 {
6090 struct i915_power_domains *power_domains;
6091 struct i915_power_well *power_well;
6092 bool is_enabled;
6093 int i;
6094
6095 if (dev_priv->pm.suspended)
6096 return false;
6097
6098 power_domains = &dev_priv->power_domains;
6099
6100 is_enabled = true;
6101
6102 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
6103 if (power_well->always_on)
6104 continue;
6105
6106 if (!power_well->hw_enabled) {
6107 is_enabled = false;
6108 break;
6109 }
6110 }
6111
6112 return is_enabled;
6113 }
6114
6115 bool intel_display_power_enabled(struct drm_i915_private *dev_priv,
6116 enum intel_display_power_domain domain)
6117 {
6118 struct i915_power_domains *power_domains;
6119 bool ret;
6120
6121 power_domains = &dev_priv->power_domains;
6122
6123 mutex_lock(&power_domains->lock);
6124 ret = intel_display_power_enabled_unlocked(dev_priv, domain);
6125 mutex_unlock(&power_domains->lock);
6126
6127 return ret;
6128 }
6129
6130 /*
6131 * Starting with Haswell, we have a "Power Down Well" that can be turned off
6132 * when not needed anymore. We have 4 registers that can request the power well
6133 * to be enabled, and it will only be disabled if none of the registers is
6134 * requesting it to be enabled.
6135 */
6136 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
6137 {
6138 struct drm_device *dev = dev_priv->dev;
6139
6140 /*
6141 * After we re-enable the power well, if we touch VGA register 0x3d5
6142 * we'll get unclaimed register interrupts. This stops after we write
6143 * anything to the VGA MSR register. The vgacon module uses this
6144 * register all the time, so if we unbind our driver and, as a
6145 * consequence, bind vgacon, we'll get stuck in an infinite loop at
6146 * console_unlock(). So make here we touch the VGA MSR register, making
6147 * sure vgacon can keep working normally without triggering interrupts
6148 * and error messages.
6149 */
6150 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
6151 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
6152 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
6153
6154 if (IS_BROADWELL(dev))
6155 gen8_irq_power_well_post_enable(dev_priv);
6156 }
6157
6158 static void hsw_set_power_well(struct drm_i915_private *dev_priv,
6159 struct i915_power_well *power_well, bool enable)
6160 {
6161 bool is_enabled, enable_requested;
6162 uint32_t tmp;
6163
6164 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
6165 is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
6166 enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
6167
6168 if (enable) {
6169 if (!enable_requested)
6170 I915_WRITE(HSW_PWR_WELL_DRIVER,
6171 HSW_PWR_WELL_ENABLE_REQUEST);
6172
6173 if (!is_enabled) {
6174 DRM_DEBUG_KMS("Enabling power well\n");
6175 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
6176 HSW_PWR_WELL_STATE_ENABLED), 20))
6177 DRM_ERROR("Timeout enabling power well\n");
6178 }
6179
6180 hsw_power_well_post_enable(dev_priv);
6181 } else {
6182 if (enable_requested) {
6183 I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
6184 POSTING_READ(HSW_PWR_WELL_DRIVER);
6185 DRM_DEBUG_KMS("Requesting to disable the power well\n");
6186 }
6187 }
6188 }
6189
6190 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
6191 struct i915_power_well *power_well)
6192 {
6193 hsw_set_power_well(dev_priv, power_well, power_well->count > 0);
6194
6195 /*
6196 * We're taking over the BIOS, so clear any requests made by it since
6197 * the driver is in charge now.
6198 */
6199 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
6200 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
6201 }
6202
6203 static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
6204 struct i915_power_well *power_well)
6205 {
6206 hsw_set_power_well(dev_priv, power_well, true);
6207 }
6208
6209 static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
6210 struct i915_power_well *power_well)
6211 {
6212 hsw_set_power_well(dev_priv, power_well, false);
6213 }
6214
6215 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
6216 struct i915_power_well *power_well)
6217 {
6218 }
6219
6220 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
6221 struct i915_power_well *power_well)
6222 {
6223 return true;
6224 }
6225
6226 static void vlv_set_power_well(struct drm_i915_private *dev_priv,
6227 struct i915_power_well *power_well, bool enable)
6228 {
6229 enum punit_power_well power_well_id = power_well->data;
6230 u32 mask;
6231 u32 state;
6232 u32 ctrl;
6233
6234 mask = PUNIT_PWRGT_MASK(power_well_id);
6235 state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) :
6236 PUNIT_PWRGT_PWR_GATE(power_well_id);
6237
6238 mutex_lock(&dev_priv->rps.hw_lock);
6239
6240 #define COND \
6241 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
6242
6243 if (COND)
6244 goto out;
6245
6246 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
6247 ctrl &= ~mask;
6248 ctrl |= state;
6249 vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
6250
6251 if (wait_for(COND, 100))
6252 DRM_ERROR("timout setting power well state %08x (%08x)\n",
6253 state,
6254 vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
6255
6256 #undef COND
6257
6258 out:
6259 mutex_unlock(&dev_priv->rps.hw_lock);
6260 }
6261
6262 static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv,
6263 struct i915_power_well *power_well)
6264 {
6265 vlv_set_power_well(dev_priv, power_well, power_well->count > 0);
6266 }
6267
6268 static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
6269 struct i915_power_well *power_well)
6270 {
6271 vlv_set_power_well(dev_priv, power_well, true);
6272 }
6273
6274 static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
6275 struct i915_power_well *power_well)
6276 {
6277 vlv_set_power_well(dev_priv, power_well, false);
6278 }
6279
6280 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
6281 struct i915_power_well *power_well)
6282 {
6283 int power_well_id = power_well->data;
6284 bool enabled = false;
6285 u32 mask;
6286 u32 state;
6287 u32 ctrl;
6288
6289 mask = PUNIT_PWRGT_MASK(power_well_id);
6290 ctrl = PUNIT_PWRGT_PWR_ON(power_well_id);
6291
6292 mutex_lock(&dev_priv->rps.hw_lock);
6293
6294 state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
6295 /*
6296 * We only ever set the power-on and power-gate states, anything
6297 * else is unexpected.
6298 */
6299 WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) &&
6300 state != PUNIT_PWRGT_PWR_GATE(power_well_id));
6301 if (state == ctrl)
6302 enabled = true;
6303
6304 /*
6305 * A transient state at this point would mean some unexpected party
6306 * is poking at the power controls too.
6307 */
6308 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
6309 WARN_ON(ctrl != state);
6310
6311 mutex_unlock(&dev_priv->rps.hw_lock);
6312
6313 return enabled;
6314 }
6315
6316 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
6317 struct i915_power_well *power_well)
6318 {
6319 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
6320
6321 vlv_set_power_well(dev_priv, power_well, true);
6322
6323 spin_lock_irq(&dev_priv->irq_lock);
6324 valleyview_enable_display_irqs(dev_priv);
6325 spin_unlock_irq(&dev_priv->irq_lock);
6326
6327 /*
6328 * During driver initialization/resume we can avoid restoring the
6329 * part of the HW/SW state that will be inited anyway explicitly.
6330 */
6331 if (dev_priv->power_domains.initializing)
6332 return;
6333
6334 intel_hpd_init(dev_priv->dev);
6335
6336 i915_redisable_vga_power_on(dev_priv->dev);
6337 }
6338
6339 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
6340 struct i915_power_well *power_well)
6341 {
6342 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
6343
6344 spin_lock_irq(&dev_priv->irq_lock);
6345 valleyview_disable_display_irqs(dev_priv);
6346 spin_unlock_irq(&dev_priv->irq_lock);
6347
6348 vlv_set_power_well(dev_priv, power_well, false);
6349 }
6350
6351 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
6352 struct i915_power_well *power_well)
6353 {
6354 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
6355
6356 /*
6357 * Enable the CRI clock source so we can get at the
6358 * display and the reference clock for VGA
6359 * hotplug / manual detection.
6360 */
6361 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
6362 DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
6363 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
6364
6365 vlv_set_power_well(dev_priv, power_well, true);
6366
6367 /*
6368 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
6369 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
6370 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
6371 * b. The other bits such as sfr settings / modesel may all
6372 * be set to 0.
6373 *
6374 * This should only be done on init and resume from S3 with
6375 * both PLLs disabled, or we risk losing DPIO and PLL
6376 * synchronization.
6377 */
6378 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
6379 }
6380
6381 static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
6382 struct i915_power_well *power_well)
6383 {
6384 enum pipe pipe;
6385
6386 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
6387
6388 for_each_pipe(dev_priv, pipe)
6389 assert_pll_disabled(dev_priv, pipe);
6390
6391 /* Assert common reset */
6392 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST);
6393
6394 vlv_set_power_well(dev_priv, power_well, false);
6395 }
6396
6397 static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
6398 struct i915_power_well *power_well)
6399 {
6400 enum dpio_phy phy;
6401
6402 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
6403 power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
6404
6405 /*
6406 * Enable the CRI clock source so we can get at the
6407 * display and the reference clock for VGA
6408 * hotplug / manual detection.
6409 */
6410 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
6411 phy = DPIO_PHY0;
6412 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
6413 DPLL_REFA_CLK_ENABLE_VLV);
6414 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
6415 DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
6416 } else {
6417 phy = DPIO_PHY1;
6418 I915_WRITE(DPLL(PIPE_C), I915_READ(DPLL(PIPE_C)) |
6419 DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
6420 }
6421 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
6422 vlv_set_power_well(dev_priv, power_well, true);
6423
6424 /* Poll for phypwrgood signal */
6425 if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1))
6426 DRM_ERROR("Display PHY %d is not power up\n", phy);
6427
6428 I915_WRITE(DISPLAY_PHY_CONTROL, I915_READ(DISPLAY_PHY_CONTROL) |
6429 PHY_COM_LANE_RESET_DEASSERT(phy));
6430 }
6431
6432 static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
6433 struct i915_power_well *power_well)
6434 {
6435 enum dpio_phy phy;
6436
6437 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
6438 power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
6439
6440 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
6441 phy = DPIO_PHY0;
6442 assert_pll_disabled(dev_priv, PIPE_A);
6443 assert_pll_disabled(dev_priv, PIPE_B);
6444 } else {
6445 phy = DPIO_PHY1;
6446 assert_pll_disabled(dev_priv, PIPE_C);
6447 }
6448
6449 I915_WRITE(DISPLAY_PHY_CONTROL, I915_READ(DISPLAY_PHY_CONTROL) &
6450 ~PHY_COM_LANE_RESET_DEASSERT(phy));
6451
6452 vlv_set_power_well(dev_priv, power_well, false);
6453 }
6454
6455 static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,
6456 struct i915_power_well *power_well)
6457 {
6458 enum pipe pipe = power_well->data;
6459 bool enabled;
6460 u32 state, ctrl;
6461
6462 mutex_lock(&dev_priv->rps.hw_lock);
6463
6464 state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe);
6465 /*
6466 * We only ever set the power-on and power-gate states, anything
6467 * else is unexpected.
6468 */
6469 WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe));
6470 enabled = state == DP_SSS_PWR_ON(pipe);
6471
6472 /*
6473 * A transient state at this point would mean some unexpected party
6474 * is poking at the power controls too.
6475 */
6476 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe);
6477 WARN_ON(ctrl << 16 != state);
6478
6479 mutex_unlock(&dev_priv->rps.hw_lock);
6480
6481 return enabled;
6482 }
6483
6484 static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
6485 struct i915_power_well *power_well,
6486 bool enable)
6487 {
6488 enum pipe pipe = power_well->data;
6489 u32 state;
6490 u32 ctrl;
6491
6492 state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe);
6493
6494 mutex_lock(&dev_priv->rps.hw_lock);
6495
6496 #define COND \
6497 ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state)
6498
6499 if (COND)
6500 goto out;
6501
6502 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
6503 ctrl &= ~DP_SSC_MASK(pipe);
6504 ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe);
6505 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl);
6506
6507 if (wait_for(COND, 100))
6508 DRM_ERROR("timout setting power well state %08x (%08x)\n",
6509 state,
6510 vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ));
6511
6512 #undef COND
6513
6514 out:
6515 mutex_unlock(&dev_priv->rps.hw_lock);
6516 }
6517
6518 static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv,
6519 struct i915_power_well *power_well)
6520 {
6521 chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0);
6522 }
6523
6524 static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
6525 struct i915_power_well *power_well)
6526 {
6527 WARN_ON_ONCE(power_well->data != PIPE_A &&
6528 power_well->data != PIPE_B &&
6529 power_well->data != PIPE_C);
6530
6531 chv_set_pipe_power_well(dev_priv, power_well, true);
6532 }
6533
6534 static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
6535 struct i915_power_well *power_well)
6536 {
6537 WARN_ON_ONCE(power_well->data != PIPE_A &&
6538 power_well->data != PIPE_B &&
6539 power_well->data != PIPE_C);
6540
6541 chv_set_pipe_power_well(dev_priv, power_well, false);
6542 }
6543
6544 static void check_power_well_state(struct drm_i915_private *dev_priv,
6545 struct i915_power_well *power_well)
6546 {
6547 bool enabled = power_well->ops->is_enabled(dev_priv, power_well);
6548
6549 if (power_well->always_on || !i915.disable_power_well) {
6550 if (!enabled)
6551 goto mismatch;
6552
6553 return;
6554 }
6555
6556 if (enabled != (power_well->count > 0))
6557 goto mismatch;
6558
6559 return;
6560
6561 mismatch:
6562 WARN(1, "state mismatch for '%s' (always_on %d hw state %d use-count %d disable_power_well %d\n",
6563 power_well->name, power_well->always_on, enabled,
6564 power_well->count, i915.disable_power_well);
6565 }
6566
6567 void intel_display_power_get(struct drm_i915_private *dev_priv,
6568 enum intel_display_power_domain domain)
6569 {
6570 struct i915_power_domains *power_domains;
6571 struct i915_power_well *power_well;
6572 int i;
6573
6574 intel_runtime_pm_get(dev_priv);
6575
6576 power_domains = &dev_priv->power_domains;
6577
6578 mutex_lock(&power_domains->lock);
6579
6580 for_each_power_well(i, power_well, BIT(domain), power_domains) {
6581 if (!power_well->count++) {
6582 DRM_DEBUG_KMS("enabling %s\n", power_well->name);
6583 power_well->ops->enable(dev_priv, power_well);
6584 power_well->hw_enabled = true;
6585 }
6586
6587 check_power_well_state(dev_priv, power_well);
6588 }
6589
6590 power_domains->domain_use_count[domain]++;
6591
6592 mutex_unlock(&power_domains->lock);
6593 }
6594
6595 void intel_display_power_put(struct drm_i915_private *dev_priv,
6596 enum intel_display_power_domain domain)
6597 {
6598 struct i915_power_domains *power_domains;
6599 struct i915_power_well *power_well;
6600 int i;
6601
6602 power_domains = &dev_priv->power_domains;
6603
6604 mutex_lock(&power_domains->lock);
6605
6606 WARN_ON(!power_domains->domain_use_count[domain]);
6607 power_domains->domain_use_count[domain]--;
6608
6609 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
6610 WARN_ON(!power_well->count);
6611
6612 if (!--power_well->count && i915.disable_power_well) {
6613 DRM_DEBUG_KMS("disabling %s\n", power_well->name);
6614 power_well->hw_enabled = false;
6615 power_well->ops->disable(dev_priv, power_well);
6616 }
6617
6618 check_power_well_state(dev_priv, power_well);
6619 }
6620
6621 mutex_unlock(&power_domains->lock);
6622
6623 intel_runtime_pm_put(dev_priv);
6624 }
6625
6626 static struct i915_power_domains *hsw_pwr;
6627
6628 /* Display audio driver power well request */
6629 int i915_request_power_well(void)
6630 {
6631 struct drm_i915_private *dev_priv;
6632
6633 if (!hsw_pwr)
6634 return -ENODEV;
6635
6636 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
6637 power_domains);
6638 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
6639 return 0;
6640 }
6641 EXPORT_SYMBOL_GPL(i915_request_power_well);
6642
6643 /* Display audio driver power well release */
6644 int i915_release_power_well(void)
6645 {
6646 struct drm_i915_private *dev_priv;
6647
6648 if (!hsw_pwr)
6649 return -ENODEV;
6650
6651 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
6652 power_domains);
6653 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
6654 return 0;
6655 }
6656 EXPORT_SYMBOL_GPL(i915_release_power_well);
6657
6658 /*
6659 * Private interface for the audio driver to get CDCLK in kHz.
6660 *
6661 * Caller must request power well using i915_request_power_well() prior to
6662 * making the call.
6663 */
6664 int i915_get_cdclk_freq(void)
6665 {
6666 struct drm_i915_private *dev_priv;
6667
6668 if (!hsw_pwr)
6669 return -ENODEV;
6670
6671 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
6672 power_domains);
6673
6674 return intel_ddi_get_cdclk_freq(dev_priv);
6675 }
6676 EXPORT_SYMBOL_GPL(i915_get_cdclk_freq);
6677
6678
6679 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
6680
6681 #define HSW_ALWAYS_ON_POWER_DOMAINS ( \
6682 BIT(POWER_DOMAIN_PIPE_A) | \
6683 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
6684 BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
6685 BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
6686 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6687 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6688 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6689 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6690 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
6691 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
6692 BIT(POWER_DOMAIN_PORT_CRT) | \
6693 BIT(POWER_DOMAIN_PLLS) | \
6694 BIT(POWER_DOMAIN_INIT))
6695 #define HSW_DISPLAY_POWER_DOMAINS ( \
6696 (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \
6697 BIT(POWER_DOMAIN_INIT))
6698
6699 #define BDW_ALWAYS_ON_POWER_DOMAINS ( \
6700 HSW_ALWAYS_ON_POWER_DOMAINS | \
6701 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
6702 #define BDW_DISPLAY_POWER_DOMAINS ( \
6703 (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) | \
6704 BIT(POWER_DOMAIN_INIT))
6705
6706 #define VLV_ALWAYS_ON_POWER_DOMAINS BIT(POWER_DOMAIN_INIT)
6707 #define VLV_DISPLAY_POWER_DOMAINS POWER_DOMAIN_MASK
6708
6709 #define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \
6710 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6711 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6712 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6713 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6714 BIT(POWER_DOMAIN_PORT_CRT) | \
6715 BIT(POWER_DOMAIN_INIT))
6716
6717 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \
6718 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6719 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6720 BIT(POWER_DOMAIN_INIT))
6721
6722 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \
6723 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6724 BIT(POWER_DOMAIN_INIT))
6725
6726 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \
6727 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6728 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6729 BIT(POWER_DOMAIN_INIT))
6730
6731 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \
6732 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6733 BIT(POWER_DOMAIN_INIT))
6734
6735 #define CHV_PIPE_A_POWER_DOMAINS ( \
6736 BIT(POWER_DOMAIN_PIPE_A) | \
6737 BIT(POWER_DOMAIN_INIT))
6738
6739 #define CHV_PIPE_B_POWER_DOMAINS ( \
6740 BIT(POWER_DOMAIN_PIPE_B) | \
6741 BIT(POWER_DOMAIN_INIT))
6742
6743 #define CHV_PIPE_C_POWER_DOMAINS ( \
6744 BIT(POWER_DOMAIN_PIPE_C) | \
6745 BIT(POWER_DOMAIN_INIT))
6746
6747 #define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \
6748 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6749 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6750 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6751 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6752 BIT(POWER_DOMAIN_INIT))
6753
6754 #define CHV_DPIO_CMN_D_POWER_DOMAINS ( \
6755 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
6756 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
6757 BIT(POWER_DOMAIN_INIT))
6758
6759 #define CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS ( \
6760 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
6761 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
6762 BIT(POWER_DOMAIN_INIT))
6763
6764 #define CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS ( \
6765 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
6766 BIT(POWER_DOMAIN_INIT))
6767
6768 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
6769 .sync_hw = i9xx_always_on_power_well_noop,
6770 .enable = i9xx_always_on_power_well_noop,
6771 .disable = i9xx_always_on_power_well_noop,
6772 .is_enabled = i9xx_always_on_power_well_enabled,
6773 };
6774
6775 static const struct i915_power_well_ops chv_pipe_power_well_ops = {
6776 .sync_hw = chv_pipe_power_well_sync_hw,
6777 .enable = chv_pipe_power_well_enable,
6778 .disable = chv_pipe_power_well_disable,
6779 .is_enabled = chv_pipe_power_well_enabled,
6780 };
6781
6782 static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = {
6783 .sync_hw = vlv_power_well_sync_hw,
6784 .enable = chv_dpio_cmn_power_well_enable,
6785 .disable = chv_dpio_cmn_power_well_disable,
6786 .is_enabled = vlv_power_well_enabled,
6787 };
6788
6789 static struct i915_power_well i9xx_always_on_power_well[] = {
6790 {
6791 .name = "always-on",
6792 .always_on = 1,
6793 .domains = POWER_DOMAIN_MASK,
6794 .ops = &i9xx_always_on_power_well_ops,
6795 },
6796 };
6797
6798 static const struct i915_power_well_ops hsw_power_well_ops = {
6799 .sync_hw = hsw_power_well_sync_hw,
6800 .enable = hsw_power_well_enable,
6801 .disable = hsw_power_well_disable,
6802 .is_enabled = hsw_power_well_enabled,
6803 };
6804
6805 static struct i915_power_well hsw_power_wells[] = {
6806 {
6807 .name = "always-on",
6808 .always_on = 1,
6809 .domains = HSW_ALWAYS_ON_POWER_DOMAINS,
6810 .ops = &i9xx_always_on_power_well_ops,
6811 },
6812 {
6813 .name = "display",
6814 .domains = HSW_DISPLAY_POWER_DOMAINS,
6815 .ops = &hsw_power_well_ops,
6816 },
6817 };
6818
6819 static struct i915_power_well bdw_power_wells[] = {
6820 {
6821 .name = "always-on",
6822 .always_on = 1,
6823 .domains = BDW_ALWAYS_ON_POWER_DOMAINS,
6824 .ops = &i9xx_always_on_power_well_ops,
6825 },
6826 {
6827 .name = "display",
6828 .domains = BDW_DISPLAY_POWER_DOMAINS,
6829 .ops = &hsw_power_well_ops,
6830 },
6831 };
6832
6833 static const struct i915_power_well_ops vlv_display_power_well_ops = {
6834 .sync_hw = vlv_power_well_sync_hw,
6835 .enable = vlv_display_power_well_enable,
6836 .disable = vlv_display_power_well_disable,
6837 .is_enabled = vlv_power_well_enabled,
6838 };
6839
6840 static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = {
6841 .sync_hw = vlv_power_well_sync_hw,
6842 .enable = vlv_dpio_cmn_power_well_enable,
6843 .disable = vlv_dpio_cmn_power_well_disable,
6844 .is_enabled = vlv_power_well_enabled,
6845 };
6846
6847 static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
6848 .sync_hw = vlv_power_well_sync_hw,
6849 .enable = vlv_power_well_enable,
6850 .disable = vlv_power_well_disable,
6851 .is_enabled = vlv_power_well_enabled,
6852 };
6853
6854 static struct i915_power_well vlv_power_wells[] = {
6855 {
6856 .name = "always-on",
6857 .always_on = 1,
6858 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
6859 .ops = &i9xx_always_on_power_well_ops,
6860 },
6861 {
6862 .name = "display",
6863 .domains = VLV_DISPLAY_POWER_DOMAINS,
6864 .data = PUNIT_POWER_WELL_DISP2D,
6865 .ops = &vlv_display_power_well_ops,
6866 },
6867 {
6868 .name = "dpio-tx-b-01",
6869 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6870 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6871 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6872 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6873 .ops = &vlv_dpio_power_well_ops,
6874 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
6875 },
6876 {
6877 .name = "dpio-tx-b-23",
6878 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6879 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6880 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6881 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6882 .ops = &vlv_dpio_power_well_ops,
6883 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
6884 },
6885 {
6886 .name = "dpio-tx-c-01",
6887 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6888 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6889 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6890 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6891 .ops = &vlv_dpio_power_well_ops,
6892 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
6893 },
6894 {
6895 .name = "dpio-tx-c-23",
6896 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6897 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6898 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6899 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6900 .ops = &vlv_dpio_power_well_ops,
6901 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
6902 },
6903 {
6904 .name = "dpio-common",
6905 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
6906 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
6907 .ops = &vlv_dpio_cmn_power_well_ops,
6908 },
6909 };
6910
6911 static struct i915_power_well chv_power_wells[] = {
6912 {
6913 .name = "always-on",
6914 .always_on = 1,
6915 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
6916 .ops = &i9xx_always_on_power_well_ops,
6917 },
6918 #if 0
6919 {
6920 .name = "display",
6921 .domains = VLV_DISPLAY_POWER_DOMAINS,
6922 .data = PUNIT_POWER_WELL_DISP2D,
6923 .ops = &vlv_display_power_well_ops,
6924 },
6925 {
6926 .name = "pipe-a",
6927 .domains = CHV_PIPE_A_POWER_DOMAINS,
6928 .data = PIPE_A,
6929 .ops = &chv_pipe_power_well_ops,
6930 },
6931 {
6932 .name = "pipe-b",
6933 .domains = CHV_PIPE_B_POWER_DOMAINS,
6934 .data = PIPE_B,
6935 .ops = &chv_pipe_power_well_ops,
6936 },
6937 {
6938 .name = "pipe-c",
6939 .domains = CHV_PIPE_C_POWER_DOMAINS,
6940 .data = PIPE_C,
6941 .ops = &chv_pipe_power_well_ops,
6942 },
6943 #endif
6944 {
6945 .name = "dpio-common-bc",
6946 /*
6947 * XXX: cmnreset for one PHY seems to disturb the other.
6948 * As a workaround keep both powered on at the same
6949 * time for now.
6950 */
6951 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS | CHV_DPIO_CMN_D_POWER_DOMAINS,
6952 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
6953 .ops = &chv_dpio_cmn_power_well_ops,
6954 },
6955 {
6956 .name = "dpio-common-d",
6957 /*
6958 * XXX: cmnreset for one PHY seems to disturb the other.
6959 * As a workaround keep both powered on at the same
6960 * time for now.
6961 */
6962 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS | CHV_DPIO_CMN_D_POWER_DOMAINS,
6963 .data = PUNIT_POWER_WELL_DPIO_CMN_D,
6964 .ops = &chv_dpio_cmn_power_well_ops,
6965 },
6966 #if 0
6967 {
6968 .name = "dpio-tx-b-01",
6969 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6970 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS,
6971 .ops = &vlv_dpio_power_well_ops,
6972 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
6973 },
6974 {
6975 .name = "dpio-tx-b-23",
6976 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6977 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS,
6978 .ops = &vlv_dpio_power_well_ops,
6979 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
6980 },
6981 {
6982 .name = "dpio-tx-c-01",
6983 .domains = VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6984 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6985 .ops = &vlv_dpio_power_well_ops,
6986 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
6987 },
6988 {
6989 .name = "dpio-tx-c-23",
6990 .domains = VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6991 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6992 .ops = &vlv_dpio_power_well_ops,
6993 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
6994 },
6995 {
6996 .name = "dpio-tx-d-01",
6997 .domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS |
6998 CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS,
6999 .ops = &vlv_dpio_power_well_ops,
7000 .data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_01,
7001 },
7002 {
7003 .name = "dpio-tx-d-23",
7004 .domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS |
7005 CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS,
7006 .ops = &vlv_dpio_power_well_ops,
7007 .data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_23,
7008 },
7009 #endif
7010 };
7011
7012 static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv,
7013 enum punit_power_well power_well_id)
7014 {
7015 struct i915_power_domains *power_domains = &dev_priv->power_domains;
7016 struct i915_power_well *power_well;
7017 int i;
7018
7019 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
7020 if (power_well->data == power_well_id)
7021 return power_well;
7022 }
7023
7024 return NULL;
7025 }
7026
7027 #define set_power_wells(power_domains, __power_wells) ({ \
7028 (power_domains)->power_wells = (__power_wells); \
7029 (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \
7030 })
7031
7032 int intel_power_domains_init(struct drm_i915_private *dev_priv)
7033 {
7034 struct i915_power_domains *power_domains = &dev_priv->power_domains;
7035
7036 mutex_init(&power_domains->lock);
7037
7038 /*
7039 * The enabling order will be from lower to higher indexed wells,
7040 * the disabling order is reversed.
7041 */
7042 if (IS_HASWELL(dev_priv->dev)) {
7043 set_power_wells(power_domains, hsw_power_wells);
7044 hsw_pwr = power_domains;
7045 } else if (IS_BROADWELL(dev_priv->dev)) {
7046 set_power_wells(power_domains, bdw_power_wells);
7047 hsw_pwr = power_domains;
7048 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
7049 set_power_wells(power_domains, chv_power_wells);
7050 } else if (IS_VALLEYVIEW(dev_priv->dev)) {
7051 set_power_wells(power_domains, vlv_power_wells);
7052 } else {
7053 set_power_wells(power_domains, i9xx_always_on_power_well);
7054 }
7055
7056 return 0;
7057 }
7058
7059 void intel_power_domains_remove(struct drm_i915_private *dev_priv)
7060 {
7061 hsw_pwr = NULL;
7062 }
7063
7064 static void intel_power_domains_resume(struct drm_i915_private *dev_priv)
7065 {
7066 struct i915_power_domains *power_domains = &dev_priv->power_domains;
7067 struct i915_power_well *power_well;
7068 int i;
7069
7070 mutex_lock(&power_domains->lock);
7071 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
7072 power_well->ops->sync_hw(dev_priv, power_well);
7073 power_well->hw_enabled = power_well->ops->is_enabled(dev_priv,
7074 power_well);
7075 }
7076 mutex_unlock(&power_domains->lock);
7077 }
7078
7079 static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
7080 {
7081 struct i915_power_well *cmn =
7082 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
7083 struct i915_power_well *disp2d =
7084 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D);
7085
7086 /* nothing to do if common lane is already off */
7087 if (!cmn->ops->is_enabled(dev_priv, cmn))
7088 return;
7089
7090 /* If the display might be already active skip this */
7091 if (disp2d->ops->is_enabled(dev_priv, disp2d) &&
7092 I915_READ(DPIO_CTL) & DPIO_CMNRST)
7093 return;
7094
7095 DRM_DEBUG_KMS("toggling display PHY side reset\n");
7096
7097 /* cmnlane needs DPLL registers */
7098 disp2d->ops->enable(dev_priv, disp2d);
7099
7100 /*
7101 * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
7102 * Need to assert and de-assert PHY SB reset by gating the
7103 * common lane power, then un-gating it.
7104 * Simply ungating isn't enough to reset the PHY enough to get
7105 * ports and lanes running.
7106 */
7107 cmn->ops->disable(dev_priv, cmn);
7108 }
7109
7110 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv)
7111 {
7112 struct drm_device *dev = dev_priv->dev;
7113 struct i915_power_domains *power_domains = &dev_priv->power_domains;
7114
7115 power_domains->initializing = true;
7116
7117 if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
7118 mutex_lock(&power_domains->lock);
7119 vlv_cmnlane_wa(dev_priv);
7120 mutex_unlock(&power_domains->lock);
7121 }
7122
7123 /* For now, we need the power well to be always enabled. */
7124 intel_display_set_init_power(dev_priv, true);
7125 intel_power_domains_resume(dev_priv);
7126 power_domains->initializing = false;
7127 }
7128
7129 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)
7130 {
7131 intel_runtime_pm_get(dev_priv);
7132 }
7133
7134 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)
7135 {
7136 intel_runtime_pm_put(dev_priv);
7137 }
7138
7139 void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
7140 {
7141 struct drm_device *dev = dev_priv->dev;
7142 struct device *device = &dev->pdev->dev;
7143
7144 if (!HAS_RUNTIME_PM(dev))
7145 return;
7146
7147 pm_runtime_get_sync(device);
7148 WARN(dev_priv->pm.suspended, "Device still suspended.\n");
7149 }
7150
7151 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv)
7152 {
7153 struct drm_device *dev = dev_priv->dev;
7154 struct device *device = &dev->pdev->dev;
7155
7156 if (!HAS_RUNTIME_PM(dev))
7157 return;
7158
7159 WARN(dev_priv->pm.suspended, "Getting nosync-ref while suspended.\n");
7160 pm_runtime_get_noresume(device);
7161 }
7162
7163 void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
7164 {
7165 struct drm_device *dev = dev_priv->dev;
7166 struct device *device = &dev->pdev->dev;
7167
7168 if (!HAS_RUNTIME_PM(dev))
7169 return;
7170
7171 pm_runtime_mark_last_busy(device);
7172 pm_runtime_put_autosuspend(device);
7173 }
7174
7175 void intel_init_runtime_pm(struct drm_i915_private *dev_priv)
7176 {
7177 struct drm_device *dev = dev_priv->dev;
7178 struct device *device = &dev->pdev->dev;
7179
7180 if (!HAS_RUNTIME_PM(dev))
7181 return;
7182
7183 pm_runtime_set_active(device);
7184
7185 /*
7186 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
7187 * requirement.
7188 */
7189 if (!intel_enable_rc6(dev)) {
7190 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
7191 return;
7192 }
7193
7194 pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
7195 pm_runtime_mark_last_busy(device);
7196 pm_runtime_use_autosuspend(device);
7197
7198 pm_runtime_put_autosuspend(device);
7199 }
7200
7201 void intel_fini_runtime_pm(struct drm_i915_private *dev_priv)
7202 {
7203 struct drm_device *dev = dev_priv->dev;
7204 struct device *device = &dev->pdev->dev;
7205
7206 if (!HAS_RUNTIME_PM(dev))
7207 return;
7208
7209 if (!intel_enable_rc6(dev))
7210 return;
7211
7212 /* Make sure we're not suspended first. */
7213 pm_runtime_get_sync(device);
7214 pm_runtime_disable(device);
7215 }
7216
7217 /* Set up chip specific power management-related functions */
7218 void intel_init_pm(struct drm_device *dev)
7219 {
7220 struct drm_i915_private *dev_priv = dev->dev_private;
7221
7222 if (HAS_FBC(dev)) {
7223 if (INTEL_INFO(dev)->gen >= 7) {
7224 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
7225 dev_priv->display.enable_fbc = gen7_enable_fbc;
7226 dev_priv->display.disable_fbc = ironlake_disable_fbc;
7227 } else if (INTEL_INFO(dev)->gen >= 5) {
7228 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
7229 dev_priv->display.enable_fbc = ironlake_enable_fbc;
7230 dev_priv->display.disable_fbc = ironlake_disable_fbc;
7231 } else if (IS_GM45(dev)) {
7232 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
7233 dev_priv->display.enable_fbc = g4x_enable_fbc;
7234 dev_priv->display.disable_fbc = g4x_disable_fbc;
7235 } else {
7236 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
7237 dev_priv->display.enable_fbc = i8xx_enable_fbc;
7238 dev_priv->display.disable_fbc = i8xx_disable_fbc;
7239
7240 /* This value was pulled out of someone's hat */
7241 I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);
7242 }
7243 }
7244
7245 /* For cxsr */
7246 if (IS_PINEVIEW(dev))
7247 i915_pineview_get_mem_freq(dev);
7248 else if (IS_GEN5(dev))
7249 i915_ironlake_get_mem_freq(dev);
7250
7251 /* For FIFO watermark updates */
7252 if (HAS_PCH_SPLIT(dev)) {
7253 ilk_setup_wm_latency(dev);
7254
7255 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
7256 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7257 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7258 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
7259 dev_priv->display.update_wm = ilk_update_wm;
7260 dev_priv->display.update_sprite_wm = ilk_update_sprite_wm;
7261 } else {
7262 DRM_DEBUG_KMS("Failed to read display plane latency. "
7263 "Disable CxSR\n");
7264 }
7265
7266 if (IS_GEN5(dev))
7267 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7268 else if (IS_GEN6(dev))
7269 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7270 else if (IS_IVYBRIDGE(dev))
7271 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7272 else if (IS_HASWELL(dev))
7273 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7274 else if (INTEL_INFO(dev)->gen == 8)
7275 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7276 } else if (IS_CHERRYVIEW(dev)) {
7277 dev_priv->display.update_wm = cherryview_update_wm;
7278 dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;
7279 dev_priv->display.init_clock_gating =
7280 cherryview_init_clock_gating;
7281 } else if (IS_VALLEYVIEW(dev)) {
7282 dev_priv->display.update_wm = valleyview_update_wm;
7283 dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;
7284 dev_priv->display.init_clock_gating =
7285 valleyview_init_clock_gating;
7286 } else if (IS_PINEVIEW(dev)) {
7287 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7288 dev_priv->is_ddr3,
7289 dev_priv->fsb_freq,
7290 dev_priv->mem_freq)) {
7291 DRM_INFO("failed to find known CxSR latency "
7292 "(found ddr%s fsb freq %d, mem freq %d), "
7293 "disabling CxSR\n",
7294 (dev_priv->is_ddr3 == 1) ? "3" : "2",
7295 dev_priv->fsb_freq, dev_priv->mem_freq);
7296 /* Disable CxSR and never update its watermark again */
7297 intel_set_memory_cxsr(dev_priv, false);
7298 dev_priv->display.update_wm = NULL;
7299 } else
7300 dev_priv->display.update_wm = pineview_update_wm;
7301 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7302 } else if (IS_G4X(dev)) {
7303 dev_priv->display.update_wm = g4x_update_wm;
7304 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7305 } else if (IS_GEN4(dev)) {
7306 dev_priv->display.update_wm = i965_update_wm;
7307 if (IS_CRESTLINE(dev))
7308 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7309 else if (IS_BROADWATER(dev))
7310 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7311 } else if (IS_GEN3(dev)) {
7312 dev_priv->display.update_wm = i9xx_update_wm;
7313 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7314 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7315 } else if (IS_GEN2(dev)) {
7316 if (INTEL_INFO(dev)->num_pipes == 1) {
7317 dev_priv->display.update_wm = i845_update_wm;
7318 dev_priv->display.get_fifo_size = i845_get_fifo_size;
7319 } else {
7320 dev_priv->display.update_wm = i9xx_update_wm;
7321 dev_priv->display.get_fifo_size = i830_get_fifo_size;
7322 }
7323
7324 if (IS_I85X(dev) || IS_I865G(dev))
7325 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7326 else
7327 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7328 } else {
7329 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
7330 }
7331 }
7332
7333 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
7334 {
7335 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7336
7337 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7338 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7339 return -EAGAIN;
7340 }
7341
7342 I915_WRITE(GEN6_PCODE_DATA, *val);
7343 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7344
7345 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7346 500)) {
7347 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7348 return -ETIMEDOUT;
7349 }
7350
7351 *val = I915_READ(GEN6_PCODE_DATA);
7352 I915_WRITE(GEN6_PCODE_DATA, 0);
7353
7354 return 0;
7355 }
7356
7357 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
7358 {
7359 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7360
7361 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7362 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7363 return -EAGAIN;
7364 }
7365
7366 I915_WRITE(GEN6_PCODE_DATA, val);
7367 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7368
7369 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7370 500)) {
7371 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7372 return -ETIMEDOUT;
7373 }
7374
7375 I915_WRITE(GEN6_PCODE_DATA, 0);
7376
7377 return 0;
7378 }
7379
7380 static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7381 {
7382 int div;
7383
7384 /* 4 x czclk */
7385 switch (dev_priv->mem_freq) {
7386 case 800:
7387 div = 10;
7388 break;
7389 case 1066:
7390 div = 12;
7391 break;
7392 case 1333:
7393 div = 16;
7394 break;
7395 default:
7396 return -1;
7397 }
7398
7399 return DIV_ROUND_CLOSEST(dev_priv->mem_freq * (val + 6 - 0xbd), 4 * div);
7400 }
7401
7402 static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
7403 {
7404 int mul;
7405
7406 /* 4 x czclk */
7407 switch (dev_priv->mem_freq) {
7408 case 800:
7409 mul = 10;
7410 break;
7411 case 1066:
7412 mul = 12;
7413 break;
7414 case 1333:
7415 mul = 16;
7416 break;
7417 default:
7418 return -1;
7419 }
7420
7421 return DIV_ROUND_CLOSEST(4 * mul * val, dev_priv->mem_freq) + 0xbd - 6;
7422 }
7423
7424 static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
7425 {
7426 int div, freq;
7427
7428 switch (dev_priv->rps.cz_freq) {
7429 case 200:
7430 div = 5;
7431 break;
7432 case 267:
7433 div = 6;
7434 break;
7435 case 320:
7436 case 333:
7437 case 400:
7438 div = 8;
7439 break;
7440 default:
7441 return -1;
7442 }
7443
7444 freq = (DIV_ROUND_CLOSEST((dev_priv->rps.cz_freq * val), 2 * div) / 2);
7445
7446 return freq;
7447 }
7448
7449 static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
7450 {
7451 int mul, opcode;
7452
7453 switch (dev_priv->rps.cz_freq) {
7454 case 200:
7455 mul = 5;
7456 break;
7457 case 267:
7458 mul = 6;
7459 break;
7460 case 320:
7461 case 333:
7462 case 400:
7463 mul = 8;
7464 break;
7465 default:
7466 return -1;
7467 }
7468
7469 opcode = (DIV_ROUND_CLOSEST((val * 2 * mul), dev_priv->rps.cz_freq) * 2);
7470
7471 return opcode;
7472 }
7473
7474 int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val)
7475 {
7476 int ret = -1;
7477
7478 if (IS_CHERRYVIEW(dev_priv->dev))
7479 ret = chv_gpu_freq(dev_priv, val);
7480 else if (IS_VALLEYVIEW(dev_priv->dev))
7481 ret = byt_gpu_freq(dev_priv, val);
7482
7483 return ret;
7484 }
7485
7486 int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val)
7487 {
7488 int ret = -1;
7489
7490 if (IS_CHERRYVIEW(dev_priv->dev))
7491 ret = chv_freq_opcode(dev_priv, val);
7492 else if (IS_VALLEYVIEW(dev_priv->dev))
7493 ret = byt_freq_opcode(dev_priv, val);
7494
7495 return ret;
7496 }
7497
7498 void intel_pm_setup(struct drm_device *dev)
7499 {
7500 struct drm_i915_private *dev_priv = dev->dev_private;
7501
7502 mutex_init(&dev_priv->rps.hw_lock);
7503
7504 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
7505 intel_gen6_powersave_work);
7506
7507 dev_priv->pm.suspended = false;
7508 dev_priv->pm._irqs_disabled = false;
7509 }
Linux kernel - Deliverables
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