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drm/i915: Limit the watermark to at least 8 entries on gen2/3
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_pm.c
1 /*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28 #include <linux/cpufreq.h>
29 #include "i915_drv.h"
30 #include "intel_drv.h"
31 #include "../../../platform/x86/intel_ips.h"
32 #include <linux/module.h>
33 #include <linux/vgaarb.h>
34 #include <drm/i915_powerwell.h>
35 #include <linux/pm_runtime.h>
36
37 /**
38 * RC6 is a special power stage which allows the GPU to enter an very
39 * low-voltage mode when idle, using down to 0V while at this stage. This
40 * stage is entered automatically when the GPU is idle when RC6 support is
41 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
42 *
43 * There are different RC6 modes available in Intel GPU, which differentiate
44 * among each other with the latency required to enter and leave RC6 and
45 * voltage consumed by the GPU in different states.
46 *
47 * The combination of the following flags define which states GPU is allowed
48 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
49 * RC6pp is deepest RC6. Their support by hardware varies according to the
50 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
51 * which brings the most power savings; deeper states save more power, but
52 * require higher latency to switch to and wake up.
53 */
54 #define INTEL_RC6_ENABLE (1<<0)
55 #define INTEL_RC6p_ENABLE (1<<1)
56 #define INTEL_RC6pp_ENABLE (1<<2)
57
58 /* FBC, or Frame Buffer Compression, is a technique employed to compress the
59 * framebuffer contents in-memory, aiming at reducing the required bandwidth
60 * during in-memory transfers and, therefore, reduce the power packet.
61 *
62 * The benefits of FBC are mostly visible with solid backgrounds and
63 * variation-less patterns.
64 *
65 * FBC-related functionality can be enabled by the means of the
66 * i915.i915_enable_fbc parameter
67 */
68
69 static void i8xx_disable_fbc(struct drm_device *dev)
70 {
71 struct drm_i915_private *dev_priv = dev->dev_private;
72 u32 fbc_ctl;
73
74 /* Disable compression */
75 fbc_ctl = I915_READ(FBC_CONTROL);
76 if ((fbc_ctl & FBC_CTL_EN) == 0)
77 return;
78
79 fbc_ctl &= ~FBC_CTL_EN;
80 I915_WRITE(FBC_CONTROL, fbc_ctl);
81
82 /* Wait for compressing bit to clear */
83 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
84 DRM_DEBUG_KMS("FBC idle timed out\n");
85 return;
86 }
87
88 DRM_DEBUG_KMS("disabled FBC\n");
89 }
90
91 static void i8xx_enable_fbc(struct drm_crtc *crtc)
92 {
93 struct drm_device *dev = crtc->dev;
94 struct drm_i915_private *dev_priv = dev->dev_private;
95 struct drm_framebuffer *fb = crtc->primary->fb;
96 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
97 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
98 int cfb_pitch;
99 int i;
100 u32 fbc_ctl;
101
102 cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
103 if (fb->pitches[0] < cfb_pitch)
104 cfb_pitch = fb->pitches[0];
105
106 /* FBC_CTL wants 32B or 64B units */
107 if (IS_GEN2(dev))
108 cfb_pitch = (cfb_pitch / 32) - 1;
109 else
110 cfb_pitch = (cfb_pitch / 64) - 1;
111
112 /* Clear old tags */
113 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
114 I915_WRITE(FBC_TAG + (i * 4), 0);
115
116 if (IS_GEN4(dev)) {
117 u32 fbc_ctl2;
118
119 /* Set it up... */
120 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
121 fbc_ctl2 |= FBC_CTL_PLANE(intel_crtc->plane);
122 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
123 I915_WRITE(FBC_FENCE_OFF, crtc->y);
124 }
125
126 /* enable it... */
127 fbc_ctl = I915_READ(FBC_CONTROL);
128 fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT;
129 fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
130 if (IS_I945GM(dev))
131 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
132 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
133 fbc_ctl |= obj->fence_reg;
134 I915_WRITE(FBC_CONTROL, fbc_ctl);
135
136 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c\n",
137 cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
138 }
139
140 static bool i8xx_fbc_enabled(struct drm_device *dev)
141 {
142 struct drm_i915_private *dev_priv = dev->dev_private;
143
144 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
145 }
146
147 static void g4x_enable_fbc(struct drm_crtc *crtc)
148 {
149 struct drm_device *dev = crtc->dev;
150 struct drm_i915_private *dev_priv = dev->dev_private;
151 struct drm_framebuffer *fb = crtc->primary->fb;
152 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
153 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
154 u32 dpfc_ctl;
155
156 dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane) | DPFC_SR_EN;
157 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
158 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
159 else
160 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
161 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
162
163 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
164
165 /* enable it... */
166 I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
167
168 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
169 }
170
171 static void g4x_disable_fbc(struct drm_device *dev)
172 {
173 struct drm_i915_private *dev_priv = dev->dev_private;
174 u32 dpfc_ctl;
175
176 /* Disable compression */
177 dpfc_ctl = I915_READ(DPFC_CONTROL);
178 if (dpfc_ctl & DPFC_CTL_EN) {
179 dpfc_ctl &= ~DPFC_CTL_EN;
180 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
181
182 DRM_DEBUG_KMS("disabled FBC\n");
183 }
184 }
185
186 static bool g4x_fbc_enabled(struct drm_device *dev)
187 {
188 struct drm_i915_private *dev_priv = dev->dev_private;
189
190 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
191 }
192
193 static void sandybridge_blit_fbc_update(struct drm_device *dev)
194 {
195 struct drm_i915_private *dev_priv = dev->dev_private;
196 u32 blt_ecoskpd;
197
198 /* Make sure blitter notifies FBC of writes */
199
200 /* Blitter is part of Media powerwell on VLV. No impact of
201 * his param in other platforms for now */
202 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_MEDIA);
203
204 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
205 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
206 GEN6_BLITTER_LOCK_SHIFT;
207 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
208 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
209 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
210 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
211 GEN6_BLITTER_LOCK_SHIFT);
212 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
213 POSTING_READ(GEN6_BLITTER_ECOSKPD);
214
215 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_MEDIA);
216 }
217
218 static void ironlake_enable_fbc(struct drm_crtc *crtc)
219 {
220 struct drm_device *dev = crtc->dev;
221 struct drm_i915_private *dev_priv = dev->dev_private;
222 struct drm_framebuffer *fb = crtc->primary->fb;
223 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
224 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
225 u32 dpfc_ctl;
226
227 dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane);
228 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
229 dev_priv->fbc.threshold++;
230
231 switch (dev_priv->fbc.threshold) {
232 case 4:
233 case 3:
234 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
235 break;
236 case 2:
237 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
238 break;
239 case 1:
240 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
241 break;
242 }
243 dpfc_ctl |= DPFC_CTL_FENCE_EN;
244 if (IS_GEN5(dev))
245 dpfc_ctl |= obj->fence_reg;
246
247 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
248 I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
249 /* enable it... */
250 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
251
252 if (IS_GEN6(dev)) {
253 I915_WRITE(SNB_DPFC_CTL_SA,
254 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
255 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
256 sandybridge_blit_fbc_update(dev);
257 }
258
259 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
260 }
261
262 static void ironlake_disable_fbc(struct drm_device *dev)
263 {
264 struct drm_i915_private *dev_priv = dev->dev_private;
265 u32 dpfc_ctl;
266
267 /* Disable compression */
268 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
269 if (dpfc_ctl & DPFC_CTL_EN) {
270 dpfc_ctl &= ~DPFC_CTL_EN;
271 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
272
273 DRM_DEBUG_KMS("disabled FBC\n");
274 }
275 }
276
277 static bool ironlake_fbc_enabled(struct drm_device *dev)
278 {
279 struct drm_i915_private *dev_priv = dev->dev_private;
280
281 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
282 }
283
284 static void gen7_enable_fbc(struct drm_crtc *crtc)
285 {
286 struct drm_device *dev = crtc->dev;
287 struct drm_i915_private *dev_priv = dev->dev_private;
288 struct drm_framebuffer *fb = crtc->primary->fb;
289 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
290 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
291 u32 dpfc_ctl;
292
293 dpfc_ctl = IVB_DPFC_CTL_PLANE(intel_crtc->plane);
294 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
295 dev_priv->fbc.threshold++;
296
297 switch (dev_priv->fbc.threshold) {
298 case 4:
299 case 3:
300 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
301 break;
302 case 2:
303 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
304 break;
305 case 1:
306 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
307 break;
308 }
309
310 dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
311
312 if (dev_priv->fbc.false_color)
313 dpfc_ctl |= FBC_CTL_FALSE_COLOR;
314
315 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
316
317 if (IS_IVYBRIDGE(dev)) {
318 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
319 I915_WRITE(ILK_DISPLAY_CHICKEN1,
320 I915_READ(ILK_DISPLAY_CHICKEN1) |
321 ILK_FBCQ_DIS);
322 } else {
323 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
324 I915_WRITE(CHICKEN_PIPESL_1(intel_crtc->pipe),
325 I915_READ(CHICKEN_PIPESL_1(intel_crtc->pipe)) |
326 HSW_FBCQ_DIS);
327 }
328
329 I915_WRITE(SNB_DPFC_CTL_SA,
330 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
331 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
332
333 sandybridge_blit_fbc_update(dev);
334
335 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
336 }
337
338 bool intel_fbc_enabled(struct drm_device *dev)
339 {
340 struct drm_i915_private *dev_priv = dev->dev_private;
341
342 if (!dev_priv->display.fbc_enabled)
343 return false;
344
345 return dev_priv->display.fbc_enabled(dev);
346 }
347
348 void gen8_fbc_sw_flush(struct drm_device *dev, u32 value)
349 {
350 struct drm_i915_private *dev_priv = dev->dev_private;
351
352 if (!IS_GEN8(dev))
353 return;
354
355 I915_WRITE(MSG_FBC_REND_STATE, value);
356 }
357
358 static void intel_fbc_work_fn(struct work_struct *__work)
359 {
360 struct intel_fbc_work *work =
361 container_of(to_delayed_work(__work),
362 struct intel_fbc_work, work);
363 struct drm_device *dev = work->crtc->dev;
364 struct drm_i915_private *dev_priv = dev->dev_private;
365
366 mutex_lock(&dev->struct_mutex);
367 if (work == dev_priv->fbc.fbc_work) {
368 /* Double check that we haven't switched fb without cancelling
369 * the prior work.
370 */
371 if (work->crtc->primary->fb == work->fb) {
372 dev_priv->display.enable_fbc(work->crtc);
373
374 dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;
375 dev_priv->fbc.fb_id = work->crtc->primary->fb->base.id;
376 dev_priv->fbc.y = work->crtc->y;
377 }
378
379 dev_priv->fbc.fbc_work = NULL;
380 }
381 mutex_unlock(&dev->struct_mutex);
382
383 kfree(work);
384 }
385
386 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
387 {
388 if (dev_priv->fbc.fbc_work == NULL)
389 return;
390
391 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
392
393 /* Synchronisation is provided by struct_mutex and checking of
394 * dev_priv->fbc.fbc_work, so we can perform the cancellation
395 * entirely asynchronously.
396 */
397 if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
398 /* tasklet was killed before being run, clean up */
399 kfree(dev_priv->fbc.fbc_work);
400
401 /* Mark the work as no longer wanted so that if it does
402 * wake-up (because the work was already running and waiting
403 * for our mutex), it will discover that is no longer
404 * necessary to run.
405 */
406 dev_priv->fbc.fbc_work = NULL;
407 }
408
409 static void intel_enable_fbc(struct drm_crtc *crtc)
410 {
411 struct intel_fbc_work *work;
412 struct drm_device *dev = crtc->dev;
413 struct drm_i915_private *dev_priv = dev->dev_private;
414
415 if (!dev_priv->display.enable_fbc)
416 return;
417
418 intel_cancel_fbc_work(dev_priv);
419
420 work = kzalloc(sizeof(*work), GFP_KERNEL);
421 if (work == NULL) {
422 DRM_ERROR("Failed to allocate FBC work structure\n");
423 dev_priv->display.enable_fbc(crtc);
424 return;
425 }
426
427 work->crtc = crtc;
428 work->fb = crtc->primary->fb;
429 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
430
431 dev_priv->fbc.fbc_work = work;
432
433 /* Delay the actual enabling to let pageflipping cease and the
434 * display to settle before starting the compression. Note that
435 * this delay also serves a second purpose: it allows for a
436 * vblank to pass after disabling the FBC before we attempt
437 * to modify the control registers.
438 *
439 * A more complicated solution would involve tracking vblanks
440 * following the termination of the page-flipping sequence
441 * and indeed performing the enable as a co-routine and not
442 * waiting synchronously upon the vblank.
443 *
444 * WaFbcWaitForVBlankBeforeEnable:ilk,snb
445 */
446 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
447 }
448
449 void intel_disable_fbc(struct drm_device *dev)
450 {
451 struct drm_i915_private *dev_priv = dev->dev_private;
452
453 intel_cancel_fbc_work(dev_priv);
454
455 if (!dev_priv->display.disable_fbc)
456 return;
457
458 dev_priv->display.disable_fbc(dev);
459 dev_priv->fbc.plane = -1;
460 }
461
462 static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
463 enum no_fbc_reason reason)
464 {
465 if (dev_priv->fbc.no_fbc_reason == reason)
466 return false;
467
468 dev_priv->fbc.no_fbc_reason = reason;
469 return true;
470 }
471
472 /**
473 * intel_update_fbc - enable/disable FBC as needed
474 * @dev: the drm_device
475 *
476 * Set up the framebuffer compression hardware at mode set time. We
477 * enable it if possible:
478 * - plane A only (on pre-965)
479 * - no pixel mulitply/line duplication
480 * - no alpha buffer discard
481 * - no dual wide
482 * - framebuffer <= max_hdisplay in width, max_vdisplay in height
483 *
484 * We can't assume that any compression will take place (worst case),
485 * so the compressed buffer has to be the same size as the uncompressed
486 * one. It also must reside (along with the line length buffer) in
487 * stolen memory.
488 *
489 * We need to enable/disable FBC on a global basis.
490 */
491 void intel_update_fbc(struct drm_device *dev)
492 {
493 struct drm_i915_private *dev_priv = dev->dev_private;
494 struct drm_crtc *crtc = NULL, *tmp_crtc;
495 struct intel_crtc *intel_crtc;
496 struct drm_framebuffer *fb;
497 struct drm_i915_gem_object *obj;
498 const struct drm_display_mode *adjusted_mode;
499 unsigned int max_width, max_height;
500
501 if (!HAS_FBC(dev)) {
502 set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED);
503 return;
504 }
505
506 if (!i915.powersave) {
507 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
508 DRM_DEBUG_KMS("fbc disabled per module param\n");
509 return;
510 }
511
512 /*
513 * If FBC is already on, we just have to verify that we can
514 * keep it that way...
515 * Need to disable if:
516 * - more than one pipe is active
517 * - changing FBC params (stride, fence, mode)
518 * - new fb is too large to fit in compressed buffer
519 * - going to an unsupported config (interlace, pixel multiply, etc.)
520 */
521 for_each_crtc(dev, tmp_crtc) {
522 if (intel_crtc_active(tmp_crtc) &&
523 to_intel_crtc(tmp_crtc)->primary_enabled) {
524 if (crtc) {
525 if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
526 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
527 goto out_disable;
528 }
529 crtc = tmp_crtc;
530 }
531 }
532
533 if (!crtc || crtc->primary->fb == NULL) {
534 if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
535 DRM_DEBUG_KMS("no output, disabling\n");
536 goto out_disable;
537 }
538
539 intel_crtc = to_intel_crtc(crtc);
540 fb = crtc->primary->fb;
541 obj = intel_fb_obj(fb);
542 adjusted_mode = &intel_crtc->config.adjusted_mode;
543
544 if (i915.enable_fbc < 0) {
545 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
546 DRM_DEBUG_KMS("disabled per chip default\n");
547 goto out_disable;
548 }
549 if (!i915.enable_fbc) {
550 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
551 DRM_DEBUG_KMS("fbc disabled per module param\n");
552 goto out_disable;
553 }
554 if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ||
555 (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
556 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
557 DRM_DEBUG_KMS("mode incompatible with compression, "
558 "disabling\n");
559 goto out_disable;
560 }
561
562 if (INTEL_INFO(dev)->gen >= 8 || IS_HASWELL(dev)) {
563 max_width = 4096;
564 max_height = 4096;
565 } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
566 max_width = 4096;
567 max_height = 2048;
568 } else {
569 max_width = 2048;
570 max_height = 1536;
571 }
572 if (intel_crtc->config.pipe_src_w > max_width ||
573 intel_crtc->config.pipe_src_h > max_height) {
574 if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
575 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
576 goto out_disable;
577 }
578 if ((INTEL_INFO(dev)->gen < 4 || HAS_DDI(dev)) &&
579 intel_crtc->plane != PLANE_A) {
580 if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
581 DRM_DEBUG_KMS("plane not A, disabling compression\n");
582 goto out_disable;
583 }
584
585 /* The use of a CPU fence is mandatory in order to detect writes
586 * by the CPU to the scanout and trigger updates to the FBC.
587 */
588 if (obj->tiling_mode != I915_TILING_X ||
589 obj->fence_reg == I915_FENCE_REG_NONE) {
590 if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED))
591 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
592 goto out_disable;
593 }
594 if (INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
595 to_intel_plane(crtc->primary)->rotation != BIT(DRM_ROTATE_0)) {
596 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
597 DRM_DEBUG_KMS("Rotation unsupported, disabling\n");
598 goto out_disable;
599 }
600
601 /* If the kernel debugger is active, always disable compression */
602 if (in_dbg_master())
603 goto out_disable;
604
605 if (i915_gem_stolen_setup_compression(dev, obj->base.size,
606 drm_format_plane_cpp(fb->pixel_format, 0))) {
607 if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL))
608 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
609 goto out_disable;
610 }
611
612 /* If the scanout has not changed, don't modify the FBC settings.
613 * Note that we make the fundamental assumption that the fb->obj
614 * cannot be unpinned (and have its GTT offset and fence revoked)
615 * without first being decoupled from the scanout and FBC disabled.
616 */
617 if (dev_priv->fbc.plane == intel_crtc->plane &&
618 dev_priv->fbc.fb_id == fb->base.id &&
619 dev_priv->fbc.y == crtc->y)
620 return;
621
622 if (intel_fbc_enabled(dev)) {
623 /* We update FBC along two paths, after changing fb/crtc
624 * configuration (modeswitching) and after page-flipping
625 * finishes. For the latter, we know that not only did
626 * we disable the FBC at the start of the page-flip
627 * sequence, but also more than one vblank has passed.
628 *
629 * For the former case of modeswitching, it is possible
630 * to switch between two FBC valid configurations
631 * instantaneously so we do need to disable the FBC
632 * before we can modify its control registers. We also
633 * have to wait for the next vblank for that to take
634 * effect. However, since we delay enabling FBC we can
635 * assume that a vblank has passed since disabling and
636 * that we can safely alter the registers in the deferred
637 * callback.
638 *
639 * In the scenario that we go from a valid to invalid
640 * and then back to valid FBC configuration we have
641 * no strict enforcement that a vblank occurred since
642 * disabling the FBC. However, along all current pipe
643 * disabling paths we do need to wait for a vblank at
644 * some point. And we wait before enabling FBC anyway.
645 */
646 DRM_DEBUG_KMS("disabling active FBC for update\n");
647 intel_disable_fbc(dev);
648 }
649
650 intel_enable_fbc(crtc);
651 dev_priv->fbc.no_fbc_reason = FBC_OK;
652 return;
653
654 out_disable:
655 /* Multiple disables should be harmless */
656 if (intel_fbc_enabled(dev)) {
657 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
658 intel_disable_fbc(dev);
659 }
660 i915_gem_stolen_cleanup_compression(dev);
661 }
662
663 static void i915_pineview_get_mem_freq(struct drm_device *dev)
664 {
665 struct drm_i915_private *dev_priv = dev->dev_private;
666 u32 tmp;
667
668 tmp = I915_READ(CLKCFG);
669
670 switch (tmp & CLKCFG_FSB_MASK) {
671 case CLKCFG_FSB_533:
672 dev_priv->fsb_freq = 533; /* 133*4 */
673 break;
674 case CLKCFG_FSB_800:
675 dev_priv->fsb_freq = 800; /* 200*4 */
676 break;
677 case CLKCFG_FSB_667:
678 dev_priv->fsb_freq = 667; /* 167*4 */
679 break;
680 case CLKCFG_FSB_400:
681 dev_priv->fsb_freq = 400; /* 100*4 */
682 break;
683 }
684
685 switch (tmp & CLKCFG_MEM_MASK) {
686 case CLKCFG_MEM_533:
687 dev_priv->mem_freq = 533;
688 break;
689 case CLKCFG_MEM_667:
690 dev_priv->mem_freq = 667;
691 break;
692 case CLKCFG_MEM_800:
693 dev_priv->mem_freq = 800;
694 break;
695 }
696
697 /* detect pineview DDR3 setting */
698 tmp = I915_READ(CSHRDDR3CTL);
699 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
700 }
701
702 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
703 {
704 struct drm_i915_private *dev_priv = dev->dev_private;
705 u16 ddrpll, csipll;
706
707 ddrpll = I915_READ16(DDRMPLL1);
708 csipll = I915_READ16(CSIPLL0);
709
710 switch (ddrpll & 0xff) {
711 case 0xc:
712 dev_priv->mem_freq = 800;
713 break;
714 case 0x10:
715 dev_priv->mem_freq = 1066;
716 break;
717 case 0x14:
718 dev_priv->mem_freq = 1333;
719 break;
720 case 0x18:
721 dev_priv->mem_freq = 1600;
722 break;
723 default:
724 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
725 ddrpll & 0xff);
726 dev_priv->mem_freq = 0;
727 break;
728 }
729
730 dev_priv->ips.r_t = dev_priv->mem_freq;
731
732 switch (csipll & 0x3ff) {
733 case 0x00c:
734 dev_priv->fsb_freq = 3200;
735 break;
736 case 0x00e:
737 dev_priv->fsb_freq = 3733;
738 break;
739 case 0x010:
740 dev_priv->fsb_freq = 4266;
741 break;
742 case 0x012:
743 dev_priv->fsb_freq = 4800;
744 break;
745 case 0x014:
746 dev_priv->fsb_freq = 5333;
747 break;
748 case 0x016:
749 dev_priv->fsb_freq = 5866;
750 break;
751 case 0x018:
752 dev_priv->fsb_freq = 6400;
753 break;
754 default:
755 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
756 csipll & 0x3ff);
757 dev_priv->fsb_freq = 0;
758 break;
759 }
760
761 if (dev_priv->fsb_freq == 3200) {
762 dev_priv->ips.c_m = 0;
763 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
764 dev_priv->ips.c_m = 1;
765 } else {
766 dev_priv->ips.c_m = 2;
767 }
768 }
769
770 static const struct cxsr_latency cxsr_latency_table[] = {
771 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
772 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
773 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
774 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
775 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
776
777 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
778 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
779 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
780 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
781 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
782
783 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
784 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
785 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
786 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
787 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
788
789 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
790 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
791 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
792 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
793 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
794
795 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
796 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
797 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
798 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
799 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
800
801 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
802 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
803 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
804 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
805 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
806 };
807
808 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
809 int is_ddr3,
810 int fsb,
811 int mem)
812 {
813 const struct cxsr_latency *latency;
814 int i;
815
816 if (fsb == 0 || mem == 0)
817 return NULL;
818
819 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
820 latency = &cxsr_latency_table[i];
821 if (is_desktop == latency->is_desktop &&
822 is_ddr3 == latency->is_ddr3 &&
823 fsb == latency->fsb_freq && mem == latency->mem_freq)
824 return latency;
825 }
826
827 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
828
829 return NULL;
830 }
831
832 void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
833 {
834 struct drm_device *dev = dev_priv->dev;
835 u32 val;
836
837 if (IS_VALLEYVIEW(dev)) {
838 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
839 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
840 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
841 } else if (IS_PINEVIEW(dev)) {
842 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
843 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
844 I915_WRITE(DSPFW3, val);
845 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
846 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
847 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
848 I915_WRITE(FW_BLC_SELF, val);
849 } else if (IS_I915GM(dev)) {
850 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
851 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
852 I915_WRITE(INSTPM, val);
853 } else {
854 return;
855 }
856
857 DRM_DEBUG_KMS("memory self-refresh is %s\n",
858 enable ? "enabled" : "disabled");
859 }
860
861 /*
862 * Latency for FIFO fetches is dependent on several factors:
863 * - memory configuration (speed, channels)
864 * - chipset
865 * - current MCH state
866 * It can be fairly high in some situations, so here we assume a fairly
867 * pessimal value. It's a tradeoff between extra memory fetches (if we
868 * set this value too high, the FIFO will fetch frequently to stay full)
869 * and power consumption (set it too low to save power and we might see
870 * FIFO underruns and display "flicker").
871 *
872 * A value of 5us seems to be a good balance; safe for very low end
873 * platforms but not overly aggressive on lower latency configs.
874 */
875 static const int pessimal_latency_ns = 5000;
876
877 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
878 {
879 struct drm_i915_private *dev_priv = dev->dev_private;
880 uint32_t dsparb = I915_READ(DSPARB);
881 int size;
882
883 size = dsparb & 0x7f;
884 if (plane)
885 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
886
887 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
888 plane ? "B" : "A", size);
889
890 return size;
891 }
892
893 static int i830_get_fifo_size(struct drm_device *dev, int plane)
894 {
895 struct drm_i915_private *dev_priv = dev->dev_private;
896 uint32_t dsparb = I915_READ(DSPARB);
897 int size;
898
899 size = dsparb & 0x1ff;
900 if (plane)
901 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
902 size >>= 1; /* Convert to cachelines */
903
904 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
905 plane ? "B" : "A", size);
906
907 return size;
908 }
909
910 static int i845_get_fifo_size(struct drm_device *dev, int plane)
911 {
912 struct drm_i915_private *dev_priv = dev->dev_private;
913 uint32_t dsparb = I915_READ(DSPARB);
914 int size;
915
916 size = dsparb & 0x7f;
917 size >>= 2; /* Convert to cachelines */
918
919 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
920 plane ? "B" : "A",
921 size);
922
923 return size;
924 }
925
926 /* Pineview has different values for various configs */
927 static const struct intel_watermark_params pineview_display_wm = {
928 .fifo_size = PINEVIEW_DISPLAY_FIFO,
929 .max_wm = PINEVIEW_MAX_WM,
930 .default_wm = PINEVIEW_DFT_WM,
931 .guard_size = PINEVIEW_GUARD_WM,
932 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
933 };
934 static const struct intel_watermark_params pineview_display_hplloff_wm = {
935 .fifo_size = PINEVIEW_DISPLAY_FIFO,
936 .max_wm = PINEVIEW_MAX_WM,
937 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
938 .guard_size = PINEVIEW_GUARD_WM,
939 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
940 };
941 static const struct intel_watermark_params pineview_cursor_wm = {
942 .fifo_size = PINEVIEW_CURSOR_FIFO,
943 .max_wm = PINEVIEW_CURSOR_MAX_WM,
944 .default_wm = PINEVIEW_CURSOR_DFT_WM,
945 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
946 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
947 };
948 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
949 .fifo_size = PINEVIEW_CURSOR_FIFO,
950 .max_wm = PINEVIEW_CURSOR_MAX_WM,
951 .default_wm = PINEVIEW_CURSOR_DFT_WM,
952 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
953 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
954 };
955 static const struct intel_watermark_params g4x_wm_info = {
956 .fifo_size = G4X_FIFO_SIZE,
957 .max_wm = G4X_MAX_WM,
958 .default_wm = G4X_MAX_WM,
959 .guard_size = 2,
960 .cacheline_size = G4X_FIFO_LINE_SIZE,
961 };
962 static const struct intel_watermark_params g4x_cursor_wm_info = {
963 .fifo_size = I965_CURSOR_FIFO,
964 .max_wm = I965_CURSOR_MAX_WM,
965 .default_wm = I965_CURSOR_DFT_WM,
966 .guard_size = 2,
967 .cacheline_size = G4X_FIFO_LINE_SIZE,
968 };
969 static const struct intel_watermark_params valleyview_wm_info = {
970 .fifo_size = VALLEYVIEW_FIFO_SIZE,
971 .max_wm = VALLEYVIEW_MAX_WM,
972 .default_wm = VALLEYVIEW_MAX_WM,
973 .guard_size = 2,
974 .cacheline_size = G4X_FIFO_LINE_SIZE,
975 };
976 static const struct intel_watermark_params valleyview_cursor_wm_info = {
977 .fifo_size = I965_CURSOR_FIFO,
978 .max_wm = VALLEYVIEW_CURSOR_MAX_WM,
979 .default_wm = I965_CURSOR_DFT_WM,
980 .guard_size = 2,
981 .cacheline_size = G4X_FIFO_LINE_SIZE,
982 };
983 static const struct intel_watermark_params i965_cursor_wm_info = {
984 .fifo_size = I965_CURSOR_FIFO,
985 .max_wm = I965_CURSOR_MAX_WM,
986 .default_wm = I965_CURSOR_DFT_WM,
987 .guard_size = 2,
988 .cacheline_size = I915_FIFO_LINE_SIZE,
989 };
990 static const struct intel_watermark_params i945_wm_info = {
991 .fifo_size = I945_FIFO_SIZE,
992 .max_wm = I915_MAX_WM,
993 .default_wm = 1,
994 .guard_size = 2,
995 .cacheline_size = I915_FIFO_LINE_SIZE,
996 };
997 static const struct intel_watermark_params i915_wm_info = {
998 .fifo_size = I915_FIFO_SIZE,
999 .max_wm = I915_MAX_WM,
1000 .default_wm = 1,
1001 .guard_size = 2,
1002 .cacheline_size = I915_FIFO_LINE_SIZE,
1003 };
1004 static const struct intel_watermark_params i830_a_wm_info = {
1005 .fifo_size = I855GM_FIFO_SIZE,
1006 .max_wm = I915_MAX_WM,
1007 .default_wm = 1,
1008 .guard_size = 2,
1009 .cacheline_size = I830_FIFO_LINE_SIZE,
1010 };
1011 static const struct intel_watermark_params i830_bc_wm_info = {
1012 .fifo_size = I855GM_FIFO_SIZE,
1013 .max_wm = I915_MAX_WM/2,
1014 .default_wm = 1,
1015 .guard_size = 2,
1016 .cacheline_size = I830_FIFO_LINE_SIZE,
1017 };
1018 static const struct intel_watermark_params i845_wm_info = {
1019 .fifo_size = I830_FIFO_SIZE,
1020 .max_wm = I915_MAX_WM,
1021 .default_wm = 1,
1022 .guard_size = 2,
1023 .cacheline_size = I830_FIFO_LINE_SIZE,
1024 };
1025
1026 /**
1027 * intel_calculate_wm - calculate watermark level
1028 * @clock_in_khz: pixel clock
1029 * @wm: chip FIFO params
1030 * @pixel_size: display pixel size
1031 * @latency_ns: memory latency for the platform
1032 *
1033 * Calculate the watermark level (the level at which the display plane will
1034 * start fetching from memory again). Each chip has a different display
1035 * FIFO size and allocation, so the caller needs to figure that out and pass
1036 * in the correct intel_watermark_params structure.
1037 *
1038 * As the pixel clock runs, the FIFO will be drained at a rate that depends
1039 * on the pixel size. When it reaches the watermark level, it'll start
1040 * fetching FIFO line sized based chunks from memory until the FIFO fills
1041 * past the watermark point. If the FIFO drains completely, a FIFO underrun
1042 * will occur, and a display engine hang could result.
1043 */
1044 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
1045 const struct intel_watermark_params *wm,
1046 int fifo_size,
1047 int pixel_size,
1048 unsigned long latency_ns)
1049 {
1050 long entries_required, wm_size;
1051
1052 /*
1053 * Note: we need to make sure we don't overflow for various clock &
1054 * latency values.
1055 * clocks go from a few thousand to several hundred thousand.
1056 * latency is usually a few thousand
1057 */
1058 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
1059 1000;
1060 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
1061
1062 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
1063
1064 wm_size = fifo_size - (entries_required + wm->guard_size);
1065
1066 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
1067
1068 /* Don't promote wm_size to unsigned... */
1069 if (wm_size > (long)wm->max_wm)
1070 wm_size = wm->max_wm;
1071 if (wm_size <= 0)
1072 wm_size = wm->default_wm;
1073
1074 /*
1075 * Bspec seems to indicate that the value shouldn't be lower than
1076 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
1077 * Lets go for 8 which is the burst size since certain platforms
1078 * already use a hardcoded 8 (which is what the spec says should be
1079 * done).
1080 */
1081 if (wm_size <= 8)
1082 wm_size = 8;
1083
1084 return wm_size;
1085 }
1086
1087 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1088 {
1089 struct drm_crtc *crtc, *enabled = NULL;
1090
1091 for_each_crtc(dev, crtc) {
1092 if (intel_crtc_active(crtc)) {
1093 if (enabled)
1094 return NULL;
1095 enabled = crtc;
1096 }
1097 }
1098
1099 return enabled;
1100 }
1101
1102 static void pineview_update_wm(struct drm_crtc *unused_crtc)
1103 {
1104 struct drm_device *dev = unused_crtc->dev;
1105 struct drm_i915_private *dev_priv = dev->dev_private;
1106 struct drm_crtc *crtc;
1107 const struct cxsr_latency *latency;
1108 u32 reg;
1109 unsigned long wm;
1110
1111 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1112 dev_priv->fsb_freq, dev_priv->mem_freq);
1113 if (!latency) {
1114 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1115 intel_set_memory_cxsr(dev_priv, false);
1116 return;
1117 }
1118
1119 crtc = single_enabled_crtc(dev);
1120 if (crtc) {
1121 const struct drm_display_mode *adjusted_mode;
1122 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1123 int clock;
1124
1125 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1126 clock = adjusted_mode->crtc_clock;
1127
1128 /* Display SR */
1129 wm = intel_calculate_wm(clock, &pineview_display_wm,
1130 pineview_display_wm.fifo_size,
1131 pixel_size, latency->display_sr);
1132 reg = I915_READ(DSPFW1);
1133 reg &= ~DSPFW_SR_MASK;
1134 reg |= wm << DSPFW_SR_SHIFT;
1135 I915_WRITE(DSPFW1, reg);
1136 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1137
1138 /* cursor SR */
1139 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1140 pineview_display_wm.fifo_size,
1141 pixel_size, latency->cursor_sr);
1142 reg = I915_READ(DSPFW3);
1143 reg &= ~DSPFW_CURSOR_SR_MASK;
1144 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1145 I915_WRITE(DSPFW3, reg);
1146
1147 /* Display HPLL off SR */
1148 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1149 pineview_display_hplloff_wm.fifo_size,
1150 pixel_size, latency->display_hpll_disable);
1151 reg = I915_READ(DSPFW3);
1152 reg &= ~DSPFW_HPLL_SR_MASK;
1153 reg |= wm & DSPFW_HPLL_SR_MASK;
1154 I915_WRITE(DSPFW3, reg);
1155
1156 /* cursor HPLL off SR */
1157 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1158 pineview_display_hplloff_wm.fifo_size,
1159 pixel_size, latency->cursor_hpll_disable);
1160 reg = I915_READ(DSPFW3);
1161 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1162 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1163 I915_WRITE(DSPFW3, reg);
1164 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1165
1166 intel_set_memory_cxsr(dev_priv, true);
1167 } else {
1168 intel_set_memory_cxsr(dev_priv, false);
1169 }
1170 }
1171
1172 static bool g4x_compute_wm0(struct drm_device *dev,
1173 int plane,
1174 const struct intel_watermark_params *display,
1175 int display_latency_ns,
1176 const struct intel_watermark_params *cursor,
1177 int cursor_latency_ns,
1178 int *plane_wm,
1179 int *cursor_wm)
1180 {
1181 struct drm_crtc *crtc;
1182 const struct drm_display_mode *adjusted_mode;
1183 int htotal, hdisplay, clock, pixel_size;
1184 int line_time_us, line_count;
1185 int entries, tlb_miss;
1186
1187 crtc = intel_get_crtc_for_plane(dev, plane);
1188 if (!intel_crtc_active(crtc)) {
1189 *cursor_wm = cursor->guard_size;
1190 *plane_wm = display->guard_size;
1191 return false;
1192 }
1193
1194 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1195 clock = adjusted_mode->crtc_clock;
1196 htotal = adjusted_mode->crtc_htotal;
1197 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1198 pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1199
1200 /* Use the small buffer method to calculate plane watermark */
1201 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1202 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1203 if (tlb_miss > 0)
1204 entries += tlb_miss;
1205 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1206 *plane_wm = entries + display->guard_size;
1207 if (*plane_wm > (int)display->max_wm)
1208 *plane_wm = display->max_wm;
1209
1210 /* Use the large buffer method to calculate cursor watermark */
1211 line_time_us = max(htotal * 1000 / clock, 1);
1212 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1213 entries = line_count * to_intel_crtc(crtc)->cursor_width * pixel_size;
1214 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1215 if (tlb_miss > 0)
1216 entries += tlb_miss;
1217 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1218 *cursor_wm = entries + cursor->guard_size;
1219 if (*cursor_wm > (int)cursor->max_wm)
1220 *cursor_wm = (int)cursor->max_wm;
1221
1222 return true;
1223 }
1224
1225 /*
1226 * Check the wm result.
1227 *
1228 * If any calculated watermark values is larger than the maximum value that
1229 * can be programmed into the associated watermark register, that watermark
1230 * must be disabled.
1231 */
1232 static bool g4x_check_srwm(struct drm_device *dev,
1233 int display_wm, int cursor_wm,
1234 const struct intel_watermark_params *display,
1235 const struct intel_watermark_params *cursor)
1236 {
1237 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1238 display_wm, cursor_wm);
1239
1240 if (display_wm > display->max_wm) {
1241 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1242 display_wm, display->max_wm);
1243 return false;
1244 }
1245
1246 if (cursor_wm > cursor->max_wm) {
1247 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1248 cursor_wm, cursor->max_wm);
1249 return false;
1250 }
1251
1252 if (!(display_wm || cursor_wm)) {
1253 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1254 return false;
1255 }
1256
1257 return true;
1258 }
1259
1260 static bool g4x_compute_srwm(struct drm_device *dev,
1261 int plane,
1262 int latency_ns,
1263 const struct intel_watermark_params *display,
1264 const struct intel_watermark_params *cursor,
1265 int *display_wm, int *cursor_wm)
1266 {
1267 struct drm_crtc *crtc;
1268 const struct drm_display_mode *adjusted_mode;
1269 int hdisplay, htotal, pixel_size, clock;
1270 unsigned long line_time_us;
1271 int line_count, line_size;
1272 int small, large;
1273 int entries;
1274
1275 if (!latency_ns) {
1276 *display_wm = *cursor_wm = 0;
1277 return false;
1278 }
1279
1280 crtc = intel_get_crtc_for_plane(dev, plane);
1281 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1282 clock = adjusted_mode->crtc_clock;
1283 htotal = adjusted_mode->crtc_htotal;
1284 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1285 pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1286
1287 line_time_us = max(htotal * 1000 / clock, 1);
1288 line_count = (latency_ns / line_time_us + 1000) / 1000;
1289 line_size = hdisplay * pixel_size;
1290
1291 /* Use the minimum of the small and large buffer method for primary */
1292 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1293 large = line_count * line_size;
1294
1295 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1296 *display_wm = entries + display->guard_size;
1297
1298 /* calculate the self-refresh watermark for display cursor */
1299 entries = line_count * pixel_size * to_intel_crtc(crtc)->cursor_width;
1300 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1301 *cursor_wm = entries + cursor->guard_size;
1302
1303 return g4x_check_srwm(dev,
1304 *display_wm, *cursor_wm,
1305 display, cursor);
1306 }
1307
1308 static bool vlv_compute_drain_latency(struct drm_crtc *crtc,
1309 int pixel_size,
1310 int *prec_mult,
1311 int *drain_latency)
1312 {
1313 int entries;
1314 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
1315
1316 if (WARN(clock == 0, "Pixel clock is zero!\n"))
1317 return false;
1318
1319 if (WARN(pixel_size == 0, "Pixel size is zero!\n"))
1320 return false;
1321
1322 entries = DIV_ROUND_UP(clock, 1000) * pixel_size;
1323 *prec_mult = (entries > 128) ? DRAIN_LATENCY_PRECISION_64 :
1324 DRAIN_LATENCY_PRECISION_32;
1325 *drain_latency = (64 * (*prec_mult) * 4) / entries;
1326
1327 if (*drain_latency > DRAIN_LATENCY_MASK)
1328 *drain_latency = DRAIN_LATENCY_MASK;
1329
1330 return true;
1331 }
1332
1333 /*
1334 * Update drain latency registers of memory arbiter
1335 *
1336 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1337 * to be programmed. Each plane has a drain latency multiplier and a drain
1338 * latency value.
1339 */
1340
1341 static void vlv_update_drain_latency(struct drm_crtc *crtc)
1342 {
1343 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1344 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1345 int pixel_size;
1346 int drain_latency;
1347 enum pipe pipe = intel_crtc->pipe;
1348 int plane_prec, prec_mult, plane_dl;
1349
1350 plane_dl = I915_READ(VLV_DDL(pipe)) & ~(DDL_PLANE_PRECISION_64 |
1351 DRAIN_LATENCY_MASK | DDL_CURSOR_PRECISION_64 |
1352 (DRAIN_LATENCY_MASK << DDL_CURSOR_SHIFT));
1353
1354 if (!intel_crtc_active(crtc)) {
1355 I915_WRITE(VLV_DDL(pipe), plane_dl);
1356 return;
1357 }
1358
1359 /* Primary plane Drain Latency */
1360 pixel_size = crtc->primary->fb->bits_per_pixel / 8; /* BPP */
1361 if (vlv_compute_drain_latency(crtc, pixel_size, &prec_mult, &drain_latency)) {
1362 plane_prec = (prec_mult == DRAIN_LATENCY_PRECISION_64) ?
1363 DDL_PLANE_PRECISION_64 :
1364 DDL_PLANE_PRECISION_32;
1365 plane_dl |= plane_prec | drain_latency;
1366 }
1367
1368 /* Cursor Drain Latency
1369 * BPP is always 4 for cursor
1370 */
1371 pixel_size = 4;
1372
1373 /* Program cursor DL only if it is enabled */
1374 if (intel_crtc->cursor_base &&
1375 vlv_compute_drain_latency(crtc, pixel_size, &prec_mult, &drain_latency)) {
1376 plane_prec = (prec_mult == DRAIN_LATENCY_PRECISION_64) ?
1377 DDL_CURSOR_PRECISION_64 :
1378 DDL_CURSOR_PRECISION_32;
1379 plane_dl |= plane_prec | (drain_latency << DDL_CURSOR_SHIFT);
1380 }
1381
1382 I915_WRITE(VLV_DDL(pipe), plane_dl);
1383 }
1384
1385 #define single_plane_enabled(mask) is_power_of_2(mask)
1386
1387 static void valleyview_update_wm(struct drm_crtc *crtc)
1388 {
1389 struct drm_device *dev = crtc->dev;
1390 static const int sr_latency_ns = 12000;
1391 struct drm_i915_private *dev_priv = dev->dev_private;
1392 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1393 int plane_sr, cursor_sr;
1394 int ignore_plane_sr, ignore_cursor_sr;
1395 unsigned int enabled = 0;
1396 bool cxsr_enabled;
1397
1398 vlv_update_drain_latency(crtc);
1399
1400 if (g4x_compute_wm0(dev, PIPE_A,
1401 &valleyview_wm_info, pessimal_latency_ns,
1402 &valleyview_cursor_wm_info, pessimal_latency_ns,
1403 &planea_wm, &cursora_wm))
1404 enabled |= 1 << PIPE_A;
1405
1406 if (g4x_compute_wm0(dev, PIPE_B,
1407 &valleyview_wm_info, pessimal_latency_ns,
1408 &valleyview_cursor_wm_info, pessimal_latency_ns,
1409 &planeb_wm, &cursorb_wm))
1410 enabled |= 1 << PIPE_B;
1411
1412 if (single_plane_enabled(enabled) &&
1413 g4x_compute_srwm(dev, ffs(enabled) - 1,
1414 sr_latency_ns,
1415 &valleyview_wm_info,
1416 &valleyview_cursor_wm_info,
1417 &plane_sr, &ignore_cursor_sr) &&
1418 g4x_compute_srwm(dev, ffs(enabled) - 1,
1419 2*sr_latency_ns,
1420 &valleyview_wm_info,
1421 &valleyview_cursor_wm_info,
1422 &ignore_plane_sr, &cursor_sr)) {
1423 cxsr_enabled = true;
1424 } else {
1425 cxsr_enabled = false;
1426 intel_set_memory_cxsr(dev_priv, false);
1427 plane_sr = cursor_sr = 0;
1428 }
1429
1430 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1431 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1432 planea_wm, cursora_wm,
1433 planeb_wm, cursorb_wm,
1434 plane_sr, cursor_sr);
1435
1436 I915_WRITE(DSPFW1,
1437 (plane_sr << DSPFW_SR_SHIFT) |
1438 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1439 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1440 (planea_wm << DSPFW_PLANEA_SHIFT));
1441 I915_WRITE(DSPFW2,
1442 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1443 (cursora_wm << DSPFW_CURSORA_SHIFT));
1444 I915_WRITE(DSPFW3,
1445 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1446 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1447
1448 if (cxsr_enabled)
1449 intel_set_memory_cxsr(dev_priv, true);
1450 }
1451
1452 static void cherryview_update_wm(struct drm_crtc *crtc)
1453 {
1454 struct drm_device *dev = crtc->dev;
1455 static const int sr_latency_ns = 12000;
1456 struct drm_i915_private *dev_priv = dev->dev_private;
1457 int planea_wm, planeb_wm, planec_wm;
1458 int cursora_wm, cursorb_wm, cursorc_wm;
1459 int plane_sr, cursor_sr;
1460 int ignore_plane_sr, ignore_cursor_sr;
1461 unsigned int enabled = 0;
1462 bool cxsr_enabled;
1463
1464 vlv_update_drain_latency(crtc);
1465
1466 if (g4x_compute_wm0(dev, PIPE_A,
1467 &valleyview_wm_info, pessimal_latency_ns,
1468 &valleyview_cursor_wm_info, pessimal_latency_ns,
1469 &planea_wm, &cursora_wm))
1470 enabled |= 1 << PIPE_A;
1471
1472 if (g4x_compute_wm0(dev, PIPE_B,
1473 &valleyview_wm_info, pessimal_latency_ns,
1474 &valleyview_cursor_wm_info, pessimal_latency_ns,
1475 &planeb_wm, &cursorb_wm))
1476 enabled |= 1 << PIPE_B;
1477
1478 if (g4x_compute_wm0(dev, PIPE_C,
1479 &valleyview_wm_info, pessimal_latency_ns,
1480 &valleyview_cursor_wm_info, pessimal_latency_ns,
1481 &planec_wm, &cursorc_wm))
1482 enabled |= 1 << PIPE_C;
1483
1484 if (single_plane_enabled(enabled) &&
1485 g4x_compute_srwm(dev, ffs(enabled) - 1,
1486 sr_latency_ns,
1487 &valleyview_wm_info,
1488 &valleyview_cursor_wm_info,
1489 &plane_sr, &ignore_cursor_sr) &&
1490 g4x_compute_srwm(dev, ffs(enabled) - 1,
1491 2*sr_latency_ns,
1492 &valleyview_wm_info,
1493 &valleyview_cursor_wm_info,
1494 &ignore_plane_sr, &cursor_sr)) {
1495 cxsr_enabled = true;
1496 } else {
1497 cxsr_enabled = false;
1498 intel_set_memory_cxsr(dev_priv, false);
1499 plane_sr = cursor_sr = 0;
1500 }
1501
1502 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1503 "B: plane=%d, cursor=%d, C: plane=%d, cursor=%d, "
1504 "SR: plane=%d, cursor=%d\n",
1505 planea_wm, cursora_wm,
1506 planeb_wm, cursorb_wm,
1507 planec_wm, cursorc_wm,
1508 plane_sr, cursor_sr);
1509
1510 I915_WRITE(DSPFW1,
1511 (plane_sr << DSPFW_SR_SHIFT) |
1512 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1513 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1514 (planea_wm << DSPFW_PLANEA_SHIFT));
1515 I915_WRITE(DSPFW2,
1516 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1517 (cursora_wm << DSPFW_CURSORA_SHIFT));
1518 I915_WRITE(DSPFW3,
1519 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1520 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1521 I915_WRITE(DSPFW9_CHV,
1522 (I915_READ(DSPFW9_CHV) & ~(DSPFW_PLANEC_MASK |
1523 DSPFW_CURSORC_MASK)) |
1524 (planec_wm << DSPFW_PLANEC_SHIFT) |
1525 (cursorc_wm << DSPFW_CURSORC_SHIFT));
1526
1527 if (cxsr_enabled)
1528 intel_set_memory_cxsr(dev_priv, true);
1529 }
1530
1531 static void valleyview_update_sprite_wm(struct drm_plane *plane,
1532 struct drm_crtc *crtc,
1533 uint32_t sprite_width,
1534 uint32_t sprite_height,
1535 int pixel_size,
1536 bool enabled, bool scaled)
1537 {
1538 struct drm_device *dev = crtc->dev;
1539 struct drm_i915_private *dev_priv = dev->dev_private;
1540 int pipe = to_intel_plane(plane)->pipe;
1541 int sprite = to_intel_plane(plane)->plane;
1542 int drain_latency;
1543 int plane_prec;
1544 int sprite_dl;
1545 int prec_mult;
1546
1547 sprite_dl = I915_READ(VLV_DDL(pipe)) & ~(DDL_SPRITE_PRECISION_64(sprite) |
1548 (DRAIN_LATENCY_MASK << DDL_SPRITE_SHIFT(sprite)));
1549
1550 if (enabled && vlv_compute_drain_latency(crtc, pixel_size, &prec_mult,
1551 &drain_latency)) {
1552 plane_prec = (prec_mult == DRAIN_LATENCY_PRECISION_64) ?
1553 DDL_SPRITE_PRECISION_64(sprite) :
1554 DDL_SPRITE_PRECISION_32(sprite);
1555 sprite_dl |= plane_prec |
1556 (drain_latency << DDL_SPRITE_SHIFT(sprite));
1557 }
1558
1559 I915_WRITE(VLV_DDL(pipe), sprite_dl);
1560 }
1561
1562 static void g4x_update_wm(struct drm_crtc *crtc)
1563 {
1564 struct drm_device *dev = crtc->dev;
1565 static const int sr_latency_ns = 12000;
1566 struct drm_i915_private *dev_priv = dev->dev_private;
1567 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1568 int plane_sr, cursor_sr;
1569 unsigned int enabled = 0;
1570 bool cxsr_enabled;
1571
1572 if (g4x_compute_wm0(dev, PIPE_A,
1573 &g4x_wm_info, pessimal_latency_ns,
1574 &g4x_cursor_wm_info, pessimal_latency_ns,
1575 &planea_wm, &cursora_wm))
1576 enabled |= 1 << PIPE_A;
1577
1578 if (g4x_compute_wm0(dev, PIPE_B,
1579 &g4x_wm_info, pessimal_latency_ns,
1580 &g4x_cursor_wm_info, pessimal_latency_ns,
1581 &planeb_wm, &cursorb_wm))
1582 enabled |= 1 << PIPE_B;
1583
1584 if (single_plane_enabled(enabled) &&
1585 g4x_compute_srwm(dev, ffs(enabled) - 1,
1586 sr_latency_ns,
1587 &g4x_wm_info,
1588 &g4x_cursor_wm_info,
1589 &plane_sr, &cursor_sr)) {
1590 cxsr_enabled = true;
1591 } else {
1592 cxsr_enabled = false;
1593 intel_set_memory_cxsr(dev_priv, false);
1594 plane_sr = cursor_sr = 0;
1595 }
1596
1597 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1598 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1599 planea_wm, cursora_wm,
1600 planeb_wm, cursorb_wm,
1601 plane_sr, cursor_sr);
1602
1603 I915_WRITE(DSPFW1,
1604 (plane_sr << DSPFW_SR_SHIFT) |
1605 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1606 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1607 (planea_wm << DSPFW_PLANEA_SHIFT));
1608 I915_WRITE(DSPFW2,
1609 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1610 (cursora_wm << DSPFW_CURSORA_SHIFT));
1611 /* HPLL off in SR has some issues on G4x... disable it */
1612 I915_WRITE(DSPFW3,
1613 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1614 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1615
1616 if (cxsr_enabled)
1617 intel_set_memory_cxsr(dev_priv, true);
1618 }
1619
1620 static void i965_update_wm(struct drm_crtc *unused_crtc)
1621 {
1622 struct drm_device *dev = unused_crtc->dev;
1623 struct drm_i915_private *dev_priv = dev->dev_private;
1624 struct drm_crtc *crtc;
1625 int srwm = 1;
1626 int cursor_sr = 16;
1627 bool cxsr_enabled;
1628
1629 /* Calc sr entries for one plane configs */
1630 crtc = single_enabled_crtc(dev);
1631 if (crtc) {
1632 /* self-refresh has much higher latency */
1633 static const int sr_latency_ns = 12000;
1634 const struct drm_display_mode *adjusted_mode =
1635 &to_intel_crtc(crtc)->config.adjusted_mode;
1636 int clock = adjusted_mode->crtc_clock;
1637 int htotal = adjusted_mode->crtc_htotal;
1638 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1639 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1640 unsigned long line_time_us;
1641 int entries;
1642
1643 line_time_us = max(htotal * 1000 / clock, 1);
1644
1645 /* Use ns/us then divide to preserve precision */
1646 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1647 pixel_size * hdisplay;
1648 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1649 srwm = I965_FIFO_SIZE - entries;
1650 if (srwm < 0)
1651 srwm = 1;
1652 srwm &= 0x1ff;
1653 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1654 entries, srwm);
1655
1656 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1657 pixel_size * to_intel_crtc(crtc)->cursor_width;
1658 entries = DIV_ROUND_UP(entries,
1659 i965_cursor_wm_info.cacheline_size);
1660 cursor_sr = i965_cursor_wm_info.fifo_size -
1661 (entries + i965_cursor_wm_info.guard_size);
1662
1663 if (cursor_sr > i965_cursor_wm_info.max_wm)
1664 cursor_sr = i965_cursor_wm_info.max_wm;
1665
1666 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1667 "cursor %d\n", srwm, cursor_sr);
1668
1669 cxsr_enabled = true;
1670 } else {
1671 cxsr_enabled = false;
1672 /* Turn off self refresh if both pipes are enabled */
1673 intel_set_memory_cxsr(dev_priv, false);
1674 }
1675
1676 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1677 srwm);
1678
1679 /* 965 has limitations... */
1680 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1681 (8 << DSPFW_CURSORB_SHIFT) |
1682 (8 << DSPFW_PLANEB_SHIFT) |
1683 (8 << DSPFW_PLANEA_SHIFT));
1684 I915_WRITE(DSPFW2, (8 << DSPFW_CURSORA_SHIFT) |
1685 (8 << DSPFW_PLANEC_SHIFT_OLD));
1686 /* update cursor SR watermark */
1687 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1688
1689 if (cxsr_enabled)
1690 intel_set_memory_cxsr(dev_priv, true);
1691 }
1692
1693 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1694 {
1695 struct drm_device *dev = unused_crtc->dev;
1696 struct drm_i915_private *dev_priv = dev->dev_private;
1697 const struct intel_watermark_params *wm_info;
1698 uint32_t fwater_lo;
1699 uint32_t fwater_hi;
1700 int cwm, srwm = 1;
1701 int fifo_size;
1702 int planea_wm, planeb_wm;
1703 struct drm_crtc *crtc, *enabled = NULL;
1704
1705 if (IS_I945GM(dev))
1706 wm_info = &i945_wm_info;
1707 else if (!IS_GEN2(dev))
1708 wm_info = &i915_wm_info;
1709 else
1710 wm_info = &i830_a_wm_info;
1711
1712 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1713 crtc = intel_get_crtc_for_plane(dev, 0);
1714 if (intel_crtc_active(crtc)) {
1715 const struct drm_display_mode *adjusted_mode;
1716 int cpp = crtc->primary->fb->bits_per_pixel / 8;
1717 if (IS_GEN2(dev))
1718 cpp = 4;
1719
1720 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1721 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1722 wm_info, fifo_size, cpp,
1723 pessimal_latency_ns);
1724 enabled = crtc;
1725 } else {
1726 planea_wm = fifo_size - wm_info->guard_size;
1727 if (planea_wm > (long)wm_info->max_wm)
1728 planea_wm = wm_info->max_wm;
1729 }
1730
1731 if (IS_GEN2(dev))
1732 wm_info = &i830_bc_wm_info;
1733
1734 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1735 crtc = intel_get_crtc_for_plane(dev, 1);
1736 if (intel_crtc_active(crtc)) {
1737 const struct drm_display_mode *adjusted_mode;
1738 int cpp = crtc->primary->fb->bits_per_pixel / 8;
1739 if (IS_GEN2(dev))
1740 cpp = 4;
1741
1742 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1743 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1744 wm_info, fifo_size, cpp,
1745 pessimal_latency_ns);
1746 if (enabled == NULL)
1747 enabled = crtc;
1748 else
1749 enabled = NULL;
1750 } else {
1751 planeb_wm = fifo_size - wm_info->guard_size;
1752 if (planeb_wm > (long)wm_info->max_wm)
1753 planeb_wm = wm_info->max_wm;
1754 }
1755
1756 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1757
1758 if (IS_I915GM(dev) && enabled) {
1759 struct drm_i915_gem_object *obj;
1760
1761 obj = intel_fb_obj(enabled->primary->fb);
1762
1763 /* self-refresh seems busted with untiled */
1764 if (obj->tiling_mode == I915_TILING_NONE)
1765 enabled = NULL;
1766 }
1767
1768 /*
1769 * Overlay gets an aggressive default since video jitter is bad.
1770 */
1771 cwm = 2;
1772
1773 /* Play safe and disable self-refresh before adjusting watermarks. */
1774 intel_set_memory_cxsr(dev_priv, false);
1775
1776 /* Calc sr entries for one plane configs */
1777 if (HAS_FW_BLC(dev) && enabled) {
1778 /* self-refresh has much higher latency */
1779 static const int sr_latency_ns = 6000;
1780 const struct drm_display_mode *adjusted_mode =
1781 &to_intel_crtc(enabled)->config.adjusted_mode;
1782 int clock = adjusted_mode->crtc_clock;
1783 int htotal = adjusted_mode->crtc_htotal;
1784 int hdisplay = to_intel_crtc(enabled)->config.pipe_src_w;
1785 int pixel_size = enabled->primary->fb->bits_per_pixel / 8;
1786 unsigned long line_time_us;
1787 int entries;
1788
1789 line_time_us = max(htotal * 1000 / clock, 1);
1790
1791 /* Use ns/us then divide to preserve precision */
1792 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1793 pixel_size * hdisplay;
1794 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1795 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1796 srwm = wm_info->fifo_size - entries;
1797 if (srwm < 0)
1798 srwm = 1;
1799
1800 if (IS_I945G(dev) || IS_I945GM(dev))
1801 I915_WRITE(FW_BLC_SELF,
1802 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1803 else if (IS_I915GM(dev))
1804 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1805 }
1806
1807 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1808 planea_wm, planeb_wm, cwm, srwm);
1809
1810 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1811 fwater_hi = (cwm & 0x1f);
1812
1813 /* Set request length to 8 cachelines per fetch */
1814 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1815 fwater_hi = fwater_hi | (1 << 8);
1816
1817 I915_WRITE(FW_BLC, fwater_lo);
1818 I915_WRITE(FW_BLC2, fwater_hi);
1819
1820 if (enabled)
1821 intel_set_memory_cxsr(dev_priv, true);
1822 }
1823
1824 static void i845_update_wm(struct drm_crtc *unused_crtc)
1825 {
1826 struct drm_device *dev = unused_crtc->dev;
1827 struct drm_i915_private *dev_priv = dev->dev_private;
1828 struct drm_crtc *crtc;
1829 const struct drm_display_mode *adjusted_mode;
1830 uint32_t fwater_lo;
1831 int planea_wm;
1832
1833 crtc = single_enabled_crtc(dev);
1834 if (crtc == NULL)
1835 return;
1836
1837 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1838 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1839 &i845_wm_info,
1840 dev_priv->display.get_fifo_size(dev, 0),
1841 4, pessimal_latency_ns);
1842 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1843 fwater_lo |= (3<<8) | planea_wm;
1844
1845 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1846
1847 I915_WRITE(FW_BLC, fwater_lo);
1848 }
1849
1850 static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
1851 struct drm_crtc *crtc)
1852 {
1853 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1854 uint32_t pixel_rate;
1855
1856 pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock;
1857
1858 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1859 * adjust the pixel_rate here. */
1860
1861 if (intel_crtc->config.pch_pfit.enabled) {
1862 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1863 uint32_t pfit_size = intel_crtc->config.pch_pfit.size;
1864
1865 pipe_w = intel_crtc->config.pipe_src_w;
1866 pipe_h = intel_crtc->config.pipe_src_h;
1867 pfit_w = (pfit_size >> 16) & 0xFFFF;
1868 pfit_h = pfit_size & 0xFFFF;
1869 if (pipe_w < pfit_w)
1870 pipe_w = pfit_w;
1871 if (pipe_h < pfit_h)
1872 pipe_h = pfit_h;
1873
1874 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1875 pfit_w * pfit_h);
1876 }
1877
1878 return pixel_rate;
1879 }
1880
1881 /* latency must be in 0.1us units. */
1882 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
1883 uint32_t latency)
1884 {
1885 uint64_t ret;
1886
1887 if (WARN(latency == 0, "Latency value missing\n"))
1888 return UINT_MAX;
1889
1890 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1891 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1892
1893 return ret;
1894 }
1895
1896 /* latency must be in 0.1us units. */
1897 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1898 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1899 uint32_t latency)
1900 {
1901 uint32_t ret;
1902
1903 if (WARN(latency == 0, "Latency value missing\n"))
1904 return UINT_MAX;
1905
1906 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1907 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1908 ret = DIV_ROUND_UP(ret, 64) + 2;
1909 return ret;
1910 }
1911
1912 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1913 uint8_t bytes_per_pixel)
1914 {
1915 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1916 }
1917
1918 struct ilk_pipe_wm_parameters {
1919 bool active;
1920 uint32_t pipe_htotal;
1921 uint32_t pixel_rate;
1922 struct intel_plane_wm_parameters pri;
1923 struct intel_plane_wm_parameters spr;
1924 struct intel_plane_wm_parameters cur;
1925 };
1926
1927 struct ilk_wm_maximums {
1928 uint16_t pri;
1929 uint16_t spr;
1930 uint16_t cur;
1931 uint16_t fbc;
1932 };
1933
1934 /* used in computing the new watermarks state */
1935 struct intel_wm_config {
1936 unsigned int num_pipes_active;
1937 bool sprites_enabled;
1938 bool sprites_scaled;
1939 };
1940
1941 /*
1942 * For both WM_PIPE and WM_LP.
1943 * mem_value must be in 0.1us units.
1944 */
1945 static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params,
1946 uint32_t mem_value,
1947 bool is_lp)
1948 {
1949 uint32_t method1, method2;
1950
1951 if (!params->active || !params->pri.enabled)
1952 return 0;
1953
1954 method1 = ilk_wm_method1(params->pixel_rate,
1955 params->pri.bytes_per_pixel,
1956 mem_value);
1957
1958 if (!is_lp)
1959 return method1;
1960
1961 method2 = ilk_wm_method2(params->pixel_rate,
1962 params->pipe_htotal,
1963 params->pri.horiz_pixels,
1964 params->pri.bytes_per_pixel,
1965 mem_value);
1966
1967 return min(method1, method2);
1968 }
1969
1970 /*
1971 * For both WM_PIPE and WM_LP.
1972 * mem_value must be in 0.1us units.
1973 */
1974 static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params,
1975 uint32_t mem_value)
1976 {
1977 uint32_t method1, method2;
1978
1979 if (!params->active || !params->spr.enabled)
1980 return 0;
1981
1982 method1 = ilk_wm_method1(params->pixel_rate,
1983 params->spr.bytes_per_pixel,
1984 mem_value);
1985 method2 = ilk_wm_method2(params->pixel_rate,
1986 params->pipe_htotal,
1987 params->spr.horiz_pixels,
1988 params->spr.bytes_per_pixel,
1989 mem_value);
1990 return min(method1, method2);
1991 }
1992
1993 /*
1994 * For both WM_PIPE and WM_LP.
1995 * mem_value must be in 0.1us units.
1996 */
1997 static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params,
1998 uint32_t mem_value)
1999 {
2000 if (!params->active || !params->cur.enabled)
2001 return 0;
2002
2003 return ilk_wm_method2(params->pixel_rate,
2004 params->pipe_htotal,
2005 params->cur.horiz_pixels,
2006 params->cur.bytes_per_pixel,
2007 mem_value);
2008 }
2009
2010 /* Only for WM_LP. */
2011 static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params,
2012 uint32_t pri_val)
2013 {
2014 if (!params->active || !params->pri.enabled)
2015 return 0;
2016
2017 return ilk_wm_fbc(pri_val,
2018 params->pri.horiz_pixels,
2019 params->pri.bytes_per_pixel);
2020 }
2021
2022 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
2023 {
2024 if (INTEL_INFO(dev)->gen >= 8)
2025 return 3072;
2026 else if (INTEL_INFO(dev)->gen >= 7)
2027 return 768;
2028 else
2029 return 512;
2030 }
2031
2032 static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
2033 int level, bool is_sprite)
2034 {
2035 if (INTEL_INFO(dev)->gen >= 8)
2036 /* BDW primary/sprite plane watermarks */
2037 return level == 0 ? 255 : 2047;
2038 else if (INTEL_INFO(dev)->gen >= 7)
2039 /* IVB/HSW primary/sprite plane watermarks */
2040 return level == 0 ? 127 : 1023;
2041 else if (!is_sprite)
2042 /* ILK/SNB primary plane watermarks */
2043 return level == 0 ? 127 : 511;
2044 else
2045 /* ILK/SNB sprite plane watermarks */
2046 return level == 0 ? 63 : 255;
2047 }
2048
2049 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
2050 int level)
2051 {
2052 if (INTEL_INFO(dev)->gen >= 7)
2053 return level == 0 ? 63 : 255;
2054 else
2055 return level == 0 ? 31 : 63;
2056 }
2057
2058 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
2059 {
2060 if (INTEL_INFO(dev)->gen >= 8)
2061 return 31;
2062 else
2063 return 15;
2064 }
2065
2066 /* Calculate the maximum primary/sprite plane watermark */
2067 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
2068 int level,
2069 const struct intel_wm_config *config,
2070 enum intel_ddb_partitioning ddb_partitioning,
2071 bool is_sprite)
2072 {
2073 unsigned int fifo_size = ilk_display_fifo_size(dev);
2074
2075 /* if sprites aren't enabled, sprites get nothing */
2076 if (is_sprite && !config->sprites_enabled)
2077 return 0;
2078
2079 /* HSW allows LP1+ watermarks even with multiple pipes */
2080 if (level == 0 || config->num_pipes_active > 1) {
2081 fifo_size /= INTEL_INFO(dev)->num_pipes;
2082
2083 /*
2084 * For some reason the non self refresh
2085 * FIFO size is only half of the self
2086 * refresh FIFO size on ILK/SNB.
2087 */
2088 if (INTEL_INFO(dev)->gen <= 6)
2089 fifo_size /= 2;
2090 }
2091
2092 if (config->sprites_enabled) {
2093 /* level 0 is always calculated with 1:1 split */
2094 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
2095 if (is_sprite)
2096 fifo_size *= 5;
2097 fifo_size /= 6;
2098 } else {
2099 fifo_size /= 2;
2100 }
2101 }
2102
2103 /* clamp to max that the registers can hold */
2104 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
2105 }
2106
2107 /* Calculate the maximum cursor plane watermark */
2108 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
2109 int level,
2110 const struct intel_wm_config *config)
2111 {
2112 /* HSW LP1+ watermarks w/ multiple pipes */
2113 if (level > 0 && config->num_pipes_active > 1)
2114 return 64;
2115
2116 /* otherwise just report max that registers can hold */
2117 return ilk_cursor_wm_reg_max(dev, level);
2118 }
2119
2120 static void ilk_compute_wm_maximums(const struct drm_device *dev,
2121 int level,
2122 const struct intel_wm_config *config,
2123 enum intel_ddb_partitioning ddb_partitioning,
2124 struct ilk_wm_maximums *max)
2125 {
2126 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
2127 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
2128 max->cur = ilk_cursor_wm_max(dev, level, config);
2129 max->fbc = ilk_fbc_wm_reg_max(dev);
2130 }
2131
2132 static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
2133 int level,
2134 struct ilk_wm_maximums *max)
2135 {
2136 max->pri = ilk_plane_wm_reg_max(dev, level, false);
2137 max->spr = ilk_plane_wm_reg_max(dev, level, true);
2138 max->cur = ilk_cursor_wm_reg_max(dev, level);
2139 max->fbc = ilk_fbc_wm_reg_max(dev);
2140 }
2141
2142 static bool ilk_validate_wm_level(int level,
2143 const struct ilk_wm_maximums *max,
2144 struct intel_wm_level *result)
2145 {
2146 bool ret;
2147
2148 /* already determined to be invalid? */
2149 if (!result->enable)
2150 return false;
2151
2152 result->enable = result->pri_val <= max->pri &&
2153 result->spr_val <= max->spr &&
2154 result->cur_val <= max->cur;
2155
2156 ret = result->enable;
2157
2158 /*
2159 * HACK until we can pre-compute everything,
2160 * and thus fail gracefully if LP0 watermarks
2161 * are exceeded...
2162 */
2163 if (level == 0 && !result->enable) {
2164 if (result->pri_val > max->pri)
2165 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2166 level, result->pri_val, max->pri);
2167 if (result->spr_val > max->spr)
2168 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2169 level, result->spr_val, max->spr);
2170 if (result->cur_val > max->cur)
2171 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2172 level, result->cur_val, max->cur);
2173
2174 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2175 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2176 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2177 result->enable = true;
2178 }
2179
2180 return ret;
2181 }
2182
2183 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
2184 int level,
2185 const struct ilk_pipe_wm_parameters *p,
2186 struct intel_wm_level *result)
2187 {
2188 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2189 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2190 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2191
2192 /* WM1+ latency values stored in 0.5us units */
2193 if (level > 0) {
2194 pri_latency *= 5;
2195 spr_latency *= 5;
2196 cur_latency *= 5;
2197 }
2198
2199 result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
2200 result->spr_val = ilk_compute_spr_wm(p, spr_latency);
2201 result->cur_val = ilk_compute_cur_wm(p, cur_latency);
2202 result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
2203 result->enable = true;
2204 }
2205
2206 static uint32_t
2207 hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
2208 {
2209 struct drm_i915_private *dev_priv = dev->dev_private;
2210 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2211 struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
2212 u32 linetime, ips_linetime;
2213
2214 if (!intel_crtc_active(crtc))
2215 return 0;
2216
2217 /* The WM are computed with base on how long it takes to fill a single
2218 * row at the given clock rate, multiplied by 8.
2219 * */
2220 linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
2221 mode->crtc_clock);
2222 ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
2223 intel_ddi_get_cdclk_freq(dev_priv));
2224
2225 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2226 PIPE_WM_LINETIME_TIME(linetime);
2227 }
2228
2229 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5])
2230 {
2231 struct drm_i915_private *dev_priv = dev->dev_private;
2232
2233 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2234 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2235
2236 wm[0] = (sskpd >> 56) & 0xFF;
2237 if (wm[0] == 0)
2238 wm[0] = sskpd & 0xF;
2239 wm[1] = (sskpd >> 4) & 0xFF;
2240 wm[2] = (sskpd >> 12) & 0xFF;
2241 wm[3] = (sskpd >> 20) & 0x1FF;
2242 wm[4] = (sskpd >> 32) & 0x1FF;
2243 } else if (INTEL_INFO(dev)->gen >= 6) {
2244 uint32_t sskpd = I915_READ(MCH_SSKPD);
2245
2246 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2247 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2248 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2249 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2250 } else if (INTEL_INFO(dev)->gen >= 5) {
2251 uint32_t mltr = I915_READ(MLTR_ILK);
2252
2253 /* ILK primary LP0 latency is 700 ns */
2254 wm[0] = 7;
2255 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2256 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2257 }
2258 }
2259
2260 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2261 {
2262 /* ILK sprite LP0 latency is 1300 ns */
2263 if (INTEL_INFO(dev)->gen == 5)
2264 wm[0] = 13;
2265 }
2266
2267 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2268 {
2269 /* ILK cursor LP0 latency is 1300 ns */
2270 if (INTEL_INFO(dev)->gen == 5)
2271 wm[0] = 13;
2272
2273 /* WaDoubleCursorLP3Latency:ivb */
2274 if (IS_IVYBRIDGE(dev))
2275 wm[3] *= 2;
2276 }
2277
2278 int ilk_wm_max_level(const struct drm_device *dev)
2279 {
2280 /* how many WM levels are we expecting */
2281 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2282 return 4;
2283 else if (INTEL_INFO(dev)->gen >= 6)
2284 return 3;
2285 else
2286 return 2;
2287 }
2288 static void intel_print_wm_latency(struct drm_device *dev,
2289 const char *name,
2290 const uint16_t wm[5])
2291 {
2292 int level, max_level = ilk_wm_max_level(dev);
2293
2294 for (level = 0; level <= max_level; level++) {
2295 unsigned int latency = wm[level];
2296
2297 if (latency == 0) {
2298 DRM_ERROR("%s WM%d latency not provided\n",
2299 name, level);
2300 continue;
2301 }
2302
2303 /* WM1+ latency values in 0.5us units */
2304 if (level > 0)
2305 latency *= 5;
2306
2307 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2308 name, level, wm[level],
2309 latency / 10, latency % 10);
2310 }
2311 }
2312
2313 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2314 uint16_t wm[5], uint16_t min)
2315 {
2316 int level, max_level = ilk_wm_max_level(dev_priv->dev);
2317
2318 if (wm[0] >= min)
2319 return false;
2320
2321 wm[0] = max(wm[0], min);
2322 for (level = 1; level <= max_level; level++)
2323 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2324
2325 return true;
2326 }
2327
2328 static void snb_wm_latency_quirk(struct drm_device *dev)
2329 {
2330 struct drm_i915_private *dev_priv = dev->dev_private;
2331 bool changed;
2332
2333 /*
2334 * The BIOS provided WM memory latency values are often
2335 * inadequate for high resolution displays. Adjust them.
2336 */
2337 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2338 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2339 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2340
2341 if (!changed)
2342 return;
2343
2344 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2345 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2346 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2347 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2348 }
2349
2350 static void ilk_setup_wm_latency(struct drm_device *dev)
2351 {
2352 struct drm_i915_private *dev_priv = dev->dev_private;
2353
2354 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2355
2356 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2357 sizeof(dev_priv->wm.pri_latency));
2358 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2359 sizeof(dev_priv->wm.pri_latency));
2360
2361 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2362 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2363
2364 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2365 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2366 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2367
2368 if (IS_GEN6(dev))
2369 snb_wm_latency_quirk(dev);
2370 }
2371
2372 static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
2373 struct ilk_pipe_wm_parameters *p)
2374 {
2375 struct drm_device *dev = crtc->dev;
2376 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2377 enum pipe pipe = intel_crtc->pipe;
2378 struct drm_plane *plane;
2379
2380 if (!intel_crtc_active(crtc))
2381 return;
2382
2383 p->active = true;
2384 p->pipe_htotal = intel_crtc->config.adjusted_mode.crtc_htotal;
2385 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
2386 p->pri.bytes_per_pixel = crtc->primary->fb->bits_per_pixel / 8;
2387 p->cur.bytes_per_pixel = 4;
2388 p->pri.horiz_pixels = intel_crtc->config.pipe_src_w;
2389 p->cur.horiz_pixels = intel_crtc->cursor_width;
2390 /* TODO: for now, assume primary and cursor planes are always enabled. */
2391 p->pri.enabled = true;
2392 p->cur.enabled = true;
2393
2394 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
2395 struct intel_plane *intel_plane = to_intel_plane(plane);
2396
2397 if (intel_plane->pipe == pipe) {
2398 p->spr = intel_plane->wm;
2399 break;
2400 }
2401 }
2402 }
2403
2404 static void ilk_compute_wm_config(struct drm_device *dev,
2405 struct intel_wm_config *config)
2406 {
2407 struct intel_crtc *intel_crtc;
2408
2409 /* Compute the currently _active_ config */
2410 for_each_intel_crtc(dev, intel_crtc) {
2411 const struct intel_pipe_wm *wm = &intel_crtc->wm.active;
2412
2413 if (!wm->pipe_enabled)
2414 continue;
2415
2416 config->sprites_enabled |= wm->sprites_enabled;
2417 config->sprites_scaled |= wm->sprites_scaled;
2418 config->num_pipes_active++;
2419 }
2420 }
2421
2422 /* Compute new watermarks for the pipe */
2423 static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
2424 const struct ilk_pipe_wm_parameters *params,
2425 struct intel_pipe_wm *pipe_wm)
2426 {
2427 struct drm_device *dev = crtc->dev;
2428 const struct drm_i915_private *dev_priv = dev->dev_private;
2429 int level, max_level = ilk_wm_max_level(dev);
2430 /* LP0 watermark maximums depend on this pipe alone */
2431 struct intel_wm_config config = {
2432 .num_pipes_active = 1,
2433 .sprites_enabled = params->spr.enabled,
2434 .sprites_scaled = params->spr.scaled,
2435 };
2436 struct ilk_wm_maximums max;
2437
2438 pipe_wm->pipe_enabled = params->active;
2439 pipe_wm->sprites_enabled = params->spr.enabled;
2440 pipe_wm->sprites_scaled = params->spr.scaled;
2441
2442 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2443 if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled)
2444 max_level = 1;
2445
2446 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2447 if (params->spr.scaled)
2448 max_level = 0;
2449
2450 ilk_compute_wm_level(dev_priv, 0, params, &pipe_wm->wm[0]);
2451
2452 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2453 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
2454
2455 /* LP0 watermarks always use 1/2 DDB partitioning */
2456 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2457
2458 /* At least LP0 must be valid */
2459 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
2460 return false;
2461
2462 ilk_compute_wm_reg_maximums(dev, 1, &max);
2463
2464 for (level = 1; level <= max_level; level++) {
2465 struct intel_wm_level wm = {};
2466
2467 ilk_compute_wm_level(dev_priv, level, params, &wm);
2468
2469 /*
2470 * Disable any watermark level that exceeds the
2471 * register maximums since such watermarks are
2472 * always invalid.
2473 */
2474 if (!ilk_validate_wm_level(level, &max, &wm))
2475 break;
2476
2477 pipe_wm->wm[level] = wm;
2478 }
2479
2480 return true;
2481 }
2482
2483 /*
2484 * Merge the watermarks from all active pipes for a specific level.
2485 */
2486 static void ilk_merge_wm_level(struct drm_device *dev,
2487 int level,
2488 struct intel_wm_level *ret_wm)
2489 {
2490 const struct intel_crtc *intel_crtc;
2491
2492 ret_wm->enable = true;
2493
2494 for_each_intel_crtc(dev, intel_crtc) {
2495 const struct intel_pipe_wm *active = &intel_crtc->wm.active;
2496 const struct intel_wm_level *wm = &active->wm[level];
2497
2498 if (!active->pipe_enabled)
2499 continue;
2500
2501 /*
2502 * The watermark values may have been used in the past,
2503 * so we must maintain them in the registers for some
2504 * time even if the level is now disabled.
2505 */
2506 if (!wm->enable)
2507 ret_wm->enable = false;
2508
2509 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2510 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2511 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2512 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2513 }
2514 }
2515
2516 /*
2517 * Merge all low power watermarks for all active pipes.
2518 */
2519 static void ilk_wm_merge(struct drm_device *dev,
2520 const struct intel_wm_config *config,
2521 const struct ilk_wm_maximums *max,
2522 struct intel_pipe_wm *merged)
2523 {
2524 int level, max_level = ilk_wm_max_level(dev);
2525 int last_enabled_level = max_level;
2526
2527 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2528 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2529 config->num_pipes_active > 1)
2530 return;
2531
2532 /* ILK: FBC WM must be disabled always */
2533 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
2534
2535 /* merge each WM1+ level */
2536 for (level = 1; level <= max_level; level++) {
2537 struct intel_wm_level *wm = &merged->wm[level];
2538
2539 ilk_merge_wm_level(dev, level, wm);
2540
2541 if (level > last_enabled_level)
2542 wm->enable = false;
2543 else if (!ilk_validate_wm_level(level, max, wm))
2544 /* make sure all following levels get disabled */
2545 last_enabled_level = level - 1;
2546
2547 /*
2548 * The spec says it is preferred to disable
2549 * FBC WMs instead of disabling a WM level.
2550 */
2551 if (wm->fbc_val > max->fbc) {
2552 if (wm->enable)
2553 merged->fbc_wm_enabled = false;
2554 wm->fbc_val = 0;
2555 }
2556 }
2557
2558 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2559 /*
2560 * FIXME this is racy. FBC might get enabled later.
2561 * What we should check here is whether FBC can be
2562 * enabled sometime later.
2563 */
2564 if (IS_GEN5(dev) && !merged->fbc_wm_enabled && intel_fbc_enabled(dev)) {
2565 for (level = 2; level <= max_level; level++) {
2566 struct intel_wm_level *wm = &merged->wm[level];
2567
2568 wm->enable = false;
2569 }
2570 }
2571 }
2572
2573 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2574 {
2575 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2576 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2577 }
2578
2579 /* The value we need to program into the WM_LPx latency field */
2580 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2581 {
2582 struct drm_i915_private *dev_priv = dev->dev_private;
2583
2584 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2585 return 2 * level;
2586 else
2587 return dev_priv->wm.pri_latency[level];
2588 }
2589
2590 static void ilk_compute_wm_results(struct drm_device *dev,
2591 const struct intel_pipe_wm *merged,
2592 enum intel_ddb_partitioning partitioning,
2593 struct ilk_wm_values *results)
2594 {
2595 struct intel_crtc *intel_crtc;
2596 int level, wm_lp;
2597
2598 results->enable_fbc_wm = merged->fbc_wm_enabled;
2599 results->partitioning = partitioning;
2600
2601 /* LP1+ register values */
2602 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2603 const struct intel_wm_level *r;
2604
2605 level = ilk_wm_lp_to_level(wm_lp, merged);
2606
2607 r = &merged->wm[level];
2608
2609 /*
2610 * Maintain the watermark values even if the level is
2611 * disabled. Doing otherwise could cause underruns.
2612 */
2613 results->wm_lp[wm_lp - 1] =
2614 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2615 (r->pri_val << WM1_LP_SR_SHIFT) |
2616 r->cur_val;
2617
2618 if (r->enable)
2619 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2620
2621 if (INTEL_INFO(dev)->gen >= 8)
2622 results->wm_lp[wm_lp - 1] |=
2623 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2624 else
2625 results->wm_lp[wm_lp - 1] |=
2626 r->fbc_val << WM1_LP_FBC_SHIFT;
2627
2628 /*
2629 * Always set WM1S_LP_EN when spr_val != 0, even if the
2630 * level is disabled. Doing otherwise could cause underruns.
2631 */
2632 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2633 WARN_ON(wm_lp != 1);
2634 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2635 } else
2636 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2637 }
2638
2639 /* LP0 register values */
2640 for_each_intel_crtc(dev, intel_crtc) {
2641 enum pipe pipe = intel_crtc->pipe;
2642 const struct intel_wm_level *r =
2643 &intel_crtc->wm.active.wm[0];
2644
2645 if (WARN_ON(!r->enable))
2646 continue;
2647
2648 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
2649
2650 results->wm_pipe[pipe] =
2651 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2652 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2653 r->cur_val;
2654 }
2655 }
2656
2657 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2658 * case both are at the same level. Prefer r1 in case they're the same. */
2659 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2660 struct intel_pipe_wm *r1,
2661 struct intel_pipe_wm *r2)
2662 {
2663 int level, max_level = ilk_wm_max_level(dev);
2664 int level1 = 0, level2 = 0;
2665
2666 for (level = 1; level <= max_level; level++) {
2667 if (r1->wm[level].enable)
2668 level1 = level;
2669 if (r2->wm[level].enable)
2670 level2 = level;
2671 }
2672
2673 if (level1 == level2) {
2674 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2675 return r2;
2676 else
2677 return r1;
2678 } else if (level1 > level2) {
2679 return r1;
2680 } else {
2681 return r2;
2682 }
2683 }
2684
2685 /* dirty bits used to track which watermarks need changes */
2686 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2687 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2688 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2689 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2690 #define WM_DIRTY_FBC (1 << 24)
2691 #define WM_DIRTY_DDB (1 << 25)
2692
2693 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
2694 const struct ilk_wm_values *old,
2695 const struct ilk_wm_values *new)
2696 {
2697 unsigned int dirty = 0;
2698 enum pipe pipe;
2699 int wm_lp;
2700
2701 for_each_pipe(dev_priv, pipe) {
2702 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2703 dirty |= WM_DIRTY_LINETIME(pipe);
2704 /* Must disable LP1+ watermarks too */
2705 dirty |= WM_DIRTY_LP_ALL;
2706 }
2707
2708 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2709 dirty |= WM_DIRTY_PIPE(pipe);
2710 /* Must disable LP1+ watermarks too */
2711 dirty |= WM_DIRTY_LP_ALL;
2712 }
2713 }
2714
2715 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2716 dirty |= WM_DIRTY_FBC;
2717 /* Must disable LP1+ watermarks too */
2718 dirty |= WM_DIRTY_LP_ALL;
2719 }
2720
2721 if (old->partitioning != new->partitioning) {
2722 dirty |= WM_DIRTY_DDB;
2723 /* Must disable LP1+ watermarks too */
2724 dirty |= WM_DIRTY_LP_ALL;
2725 }
2726
2727 /* LP1+ watermarks already deemed dirty, no need to continue */
2728 if (dirty & WM_DIRTY_LP_ALL)
2729 return dirty;
2730
2731 /* Find the lowest numbered LP1+ watermark in need of an update... */
2732 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2733 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2734 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2735 break;
2736 }
2737
2738 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2739 for (; wm_lp <= 3; wm_lp++)
2740 dirty |= WM_DIRTY_LP(wm_lp);
2741
2742 return dirty;
2743 }
2744
2745 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2746 unsigned int dirty)
2747 {
2748 struct ilk_wm_values *previous = &dev_priv->wm.hw;
2749 bool changed = false;
2750
2751 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2752 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2753 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2754 changed = true;
2755 }
2756 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2757 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2758 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2759 changed = true;
2760 }
2761 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2762 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2763 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2764 changed = true;
2765 }
2766
2767 /*
2768 * Don't touch WM1S_LP_EN here.
2769 * Doing so could cause underruns.
2770 */
2771
2772 return changed;
2773 }
2774
2775 /*
2776 * The spec says we shouldn't write when we don't need, because every write
2777 * causes WMs to be re-evaluated, expending some power.
2778 */
2779 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2780 struct ilk_wm_values *results)
2781 {
2782 struct drm_device *dev = dev_priv->dev;
2783 struct ilk_wm_values *previous = &dev_priv->wm.hw;
2784 unsigned int dirty;
2785 uint32_t val;
2786
2787 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
2788 if (!dirty)
2789 return;
2790
2791 _ilk_disable_lp_wm(dev_priv, dirty);
2792
2793 if (dirty & WM_DIRTY_PIPE(PIPE_A))
2794 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2795 if (dirty & WM_DIRTY_PIPE(PIPE_B))
2796 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2797 if (dirty & WM_DIRTY_PIPE(PIPE_C))
2798 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2799
2800 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2801 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2802 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2803 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2804 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2805 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2806
2807 if (dirty & WM_DIRTY_DDB) {
2808 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2809 val = I915_READ(WM_MISC);
2810 if (results->partitioning == INTEL_DDB_PART_1_2)
2811 val &= ~WM_MISC_DATA_PARTITION_5_6;
2812 else
2813 val |= WM_MISC_DATA_PARTITION_5_6;
2814 I915_WRITE(WM_MISC, val);
2815 } else {
2816 val = I915_READ(DISP_ARB_CTL2);
2817 if (results->partitioning == INTEL_DDB_PART_1_2)
2818 val &= ~DISP_DATA_PARTITION_5_6;
2819 else
2820 val |= DISP_DATA_PARTITION_5_6;
2821 I915_WRITE(DISP_ARB_CTL2, val);
2822 }
2823 }
2824
2825 if (dirty & WM_DIRTY_FBC) {
2826 val = I915_READ(DISP_ARB_CTL);
2827 if (results->enable_fbc_wm)
2828 val &= ~DISP_FBC_WM_DIS;
2829 else
2830 val |= DISP_FBC_WM_DIS;
2831 I915_WRITE(DISP_ARB_CTL, val);
2832 }
2833
2834 if (dirty & WM_DIRTY_LP(1) &&
2835 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2836 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2837
2838 if (INTEL_INFO(dev)->gen >= 7) {
2839 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2840 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2841 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2842 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2843 }
2844
2845 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2846 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2847 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2848 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2849 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2850 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2851
2852 dev_priv->wm.hw = *results;
2853 }
2854
2855 static bool ilk_disable_lp_wm(struct drm_device *dev)
2856 {
2857 struct drm_i915_private *dev_priv = dev->dev_private;
2858
2859 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2860 }
2861
2862 static void ilk_update_wm(struct drm_crtc *crtc)
2863 {
2864 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2865 struct drm_device *dev = crtc->dev;
2866 struct drm_i915_private *dev_priv = dev->dev_private;
2867 struct ilk_wm_maximums max;
2868 struct ilk_pipe_wm_parameters params = {};
2869 struct ilk_wm_values results = {};
2870 enum intel_ddb_partitioning partitioning;
2871 struct intel_pipe_wm pipe_wm = {};
2872 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
2873 struct intel_wm_config config = {};
2874
2875 ilk_compute_wm_parameters(crtc, &params);
2876
2877 intel_compute_pipe_wm(crtc, &params, &pipe_wm);
2878
2879 if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
2880 return;
2881
2882 intel_crtc->wm.active = pipe_wm;
2883
2884 ilk_compute_wm_config(dev, &config);
2885
2886 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
2887 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
2888
2889 /* 5/6 split only in single pipe config on IVB+ */
2890 if (INTEL_INFO(dev)->gen >= 7 &&
2891 config.num_pipes_active == 1 && config.sprites_enabled) {
2892 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
2893 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
2894
2895 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
2896 } else {
2897 best_lp_wm = &lp_wm_1_2;
2898 }
2899
2900 partitioning = (best_lp_wm == &lp_wm_1_2) ?
2901 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
2902
2903 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
2904
2905 ilk_write_wm_values(dev_priv, &results);
2906 }
2907
2908 static void
2909 ilk_update_sprite_wm(struct drm_plane *plane,
2910 struct drm_crtc *crtc,
2911 uint32_t sprite_width, uint32_t sprite_height,
2912 int pixel_size, bool enabled, bool scaled)
2913 {
2914 struct drm_device *dev = plane->dev;
2915 struct intel_plane *intel_plane = to_intel_plane(plane);
2916
2917 intel_plane->wm.enabled = enabled;
2918 intel_plane->wm.scaled = scaled;
2919 intel_plane->wm.horiz_pixels = sprite_width;
2920 intel_plane->wm.vert_pixels = sprite_width;
2921 intel_plane->wm.bytes_per_pixel = pixel_size;
2922
2923 /*
2924 * IVB workaround: must disable low power watermarks for at least
2925 * one frame before enabling scaling. LP watermarks can be re-enabled
2926 * when scaling is disabled.
2927 *
2928 * WaCxSRDisabledForSpriteScaling:ivb
2929 */
2930 if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev))
2931 intel_wait_for_vblank(dev, intel_plane->pipe);
2932
2933 ilk_update_wm(crtc);
2934 }
2935
2936 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
2937 {
2938 struct drm_device *dev = crtc->dev;
2939 struct drm_i915_private *dev_priv = dev->dev_private;
2940 struct ilk_wm_values *hw = &dev_priv->wm.hw;
2941 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2942 struct intel_pipe_wm *active = &intel_crtc->wm.active;
2943 enum pipe pipe = intel_crtc->pipe;
2944 static const unsigned int wm0_pipe_reg[] = {
2945 [PIPE_A] = WM0_PIPEA_ILK,
2946 [PIPE_B] = WM0_PIPEB_ILK,
2947 [PIPE_C] = WM0_PIPEC_IVB,
2948 };
2949
2950 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
2951 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2952 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
2953
2954 active->pipe_enabled = intel_crtc_active(crtc);
2955
2956 if (active->pipe_enabled) {
2957 u32 tmp = hw->wm_pipe[pipe];
2958
2959 /*
2960 * For active pipes LP0 watermark is marked as
2961 * enabled, and LP1+ watermaks as disabled since
2962 * we can't really reverse compute them in case
2963 * multiple pipes are active.
2964 */
2965 active->wm[0].enable = true;
2966 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
2967 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
2968 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
2969 active->linetime = hw->wm_linetime[pipe];
2970 } else {
2971 int level, max_level = ilk_wm_max_level(dev);
2972
2973 /*
2974 * For inactive pipes, all watermark levels
2975 * should be marked as enabled but zeroed,
2976 * which is what we'd compute them to.
2977 */
2978 for (level = 0; level <= max_level; level++)
2979 active->wm[level].enable = true;
2980 }
2981 }
2982
2983 void ilk_wm_get_hw_state(struct drm_device *dev)
2984 {
2985 struct drm_i915_private *dev_priv = dev->dev_private;
2986 struct ilk_wm_values *hw = &dev_priv->wm.hw;
2987 struct drm_crtc *crtc;
2988
2989 for_each_crtc(dev, crtc)
2990 ilk_pipe_wm_get_hw_state(crtc);
2991
2992 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
2993 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
2994 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
2995
2996 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
2997 if (INTEL_INFO(dev)->gen >= 7) {
2998 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
2999 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
3000 }
3001
3002 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3003 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
3004 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
3005 else if (IS_IVYBRIDGE(dev))
3006 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
3007 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
3008
3009 hw->enable_fbc_wm =
3010 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
3011 }
3012
3013 /**
3014 * intel_update_watermarks - update FIFO watermark values based on current modes
3015 *
3016 * Calculate watermark values for the various WM regs based on current mode
3017 * and plane configuration.
3018 *
3019 * There are several cases to deal with here:
3020 * - normal (i.e. non-self-refresh)
3021 * - self-refresh (SR) mode
3022 * - lines are large relative to FIFO size (buffer can hold up to 2)
3023 * - lines are small relative to FIFO size (buffer can hold more than 2
3024 * lines), so need to account for TLB latency
3025 *
3026 * The normal calculation is:
3027 * watermark = dotclock * bytes per pixel * latency
3028 * where latency is platform & configuration dependent (we assume pessimal
3029 * values here).
3030 *
3031 * The SR calculation is:
3032 * watermark = (trunc(latency/line time)+1) * surface width *
3033 * bytes per pixel
3034 * where
3035 * line time = htotal / dotclock
3036 * surface width = hdisplay for normal plane and 64 for cursor
3037 * and latency is assumed to be high, as above.
3038 *
3039 * The final value programmed to the register should always be rounded up,
3040 * and include an extra 2 entries to account for clock crossings.
3041 *
3042 * We don't use the sprite, so we can ignore that. And on Crestline we have
3043 * to set the non-SR watermarks to 8.
3044 */
3045 void intel_update_watermarks(struct drm_crtc *crtc)
3046 {
3047 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
3048
3049 if (dev_priv->display.update_wm)
3050 dev_priv->display.update_wm(crtc);
3051 }
3052
3053 void intel_update_sprite_watermarks(struct drm_plane *plane,
3054 struct drm_crtc *crtc,
3055 uint32_t sprite_width,
3056 uint32_t sprite_height,
3057 int pixel_size,
3058 bool enabled, bool scaled)
3059 {
3060 struct drm_i915_private *dev_priv = plane->dev->dev_private;
3061
3062 if (dev_priv->display.update_sprite_wm)
3063 dev_priv->display.update_sprite_wm(plane, crtc,
3064 sprite_width, sprite_height,
3065 pixel_size, enabled, scaled);
3066 }
3067
3068 static struct drm_i915_gem_object *
3069 intel_alloc_context_page(struct drm_device *dev)
3070 {
3071 struct drm_i915_gem_object *ctx;
3072 int ret;
3073
3074 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3075
3076 ctx = i915_gem_alloc_object(dev, 4096);
3077 if (!ctx) {
3078 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
3079 return NULL;
3080 }
3081
3082 ret = i915_gem_obj_ggtt_pin(ctx, 4096, 0);
3083 if (ret) {
3084 DRM_ERROR("failed to pin power context: %d\n", ret);
3085 goto err_unref;
3086 }
3087
3088 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
3089 if (ret) {
3090 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
3091 goto err_unpin;
3092 }
3093
3094 return ctx;
3095
3096 err_unpin:
3097 i915_gem_object_ggtt_unpin(ctx);
3098 err_unref:
3099 drm_gem_object_unreference(&ctx->base);
3100 return NULL;
3101 }
3102
3103 /**
3104 * Lock protecting IPS related data structures
3105 */
3106 DEFINE_SPINLOCK(mchdev_lock);
3107
3108 /* Global for IPS driver to get at the current i915 device. Protected by
3109 * mchdev_lock. */
3110 static struct drm_i915_private *i915_mch_dev;
3111
3112 bool ironlake_set_drps(struct drm_device *dev, u8 val)
3113 {
3114 struct drm_i915_private *dev_priv = dev->dev_private;
3115 u16 rgvswctl;
3116
3117 assert_spin_locked(&mchdev_lock);
3118
3119 rgvswctl = I915_READ16(MEMSWCTL);
3120 if (rgvswctl & MEMCTL_CMD_STS) {
3121 DRM_DEBUG("gpu busy, RCS change rejected\n");
3122 return false; /* still busy with another command */
3123 }
3124
3125 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
3126 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
3127 I915_WRITE16(MEMSWCTL, rgvswctl);
3128 POSTING_READ16(MEMSWCTL);
3129
3130 rgvswctl |= MEMCTL_CMD_STS;
3131 I915_WRITE16(MEMSWCTL, rgvswctl);
3132
3133 return true;
3134 }
3135
3136 static void ironlake_enable_drps(struct drm_device *dev)
3137 {
3138 struct drm_i915_private *dev_priv = dev->dev_private;
3139 u32 rgvmodectl = I915_READ(MEMMODECTL);
3140 u8 fmax, fmin, fstart, vstart;
3141
3142 spin_lock_irq(&mchdev_lock);
3143
3144 /* Enable temp reporting */
3145 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
3146 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
3147
3148 /* 100ms RC evaluation intervals */
3149 I915_WRITE(RCUPEI, 100000);
3150 I915_WRITE(RCDNEI, 100000);
3151
3152 /* Set max/min thresholds to 90ms and 80ms respectively */
3153 I915_WRITE(RCBMAXAVG, 90000);
3154 I915_WRITE(RCBMINAVG, 80000);
3155
3156 I915_WRITE(MEMIHYST, 1);
3157
3158 /* Set up min, max, and cur for interrupt handling */
3159 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
3160 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
3161 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
3162 MEMMODE_FSTART_SHIFT;
3163
3164 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
3165 PXVFREQ_PX_SHIFT;
3166
3167 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
3168 dev_priv->ips.fstart = fstart;
3169
3170 dev_priv->ips.max_delay = fstart;
3171 dev_priv->ips.min_delay = fmin;
3172 dev_priv->ips.cur_delay = fstart;
3173
3174 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
3175 fmax, fmin, fstart);
3176
3177 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
3178
3179 /*
3180 * Interrupts will be enabled in ironlake_irq_postinstall
3181 */
3182
3183 I915_WRITE(VIDSTART, vstart);
3184 POSTING_READ(VIDSTART);
3185
3186 rgvmodectl |= MEMMODE_SWMODE_EN;
3187 I915_WRITE(MEMMODECTL, rgvmodectl);
3188
3189 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
3190 DRM_ERROR("stuck trying to change perf mode\n");
3191 mdelay(1);
3192
3193 ironlake_set_drps(dev, fstart);
3194
3195 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
3196 I915_READ(0x112e0);
3197 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
3198 dev_priv->ips.last_count2 = I915_READ(0x112f4);
3199 dev_priv->ips.last_time2 = ktime_get_raw_ns();
3200
3201 spin_unlock_irq(&mchdev_lock);
3202 }
3203
3204 static void ironlake_disable_drps(struct drm_device *dev)
3205 {
3206 struct drm_i915_private *dev_priv = dev->dev_private;
3207 u16 rgvswctl;
3208
3209 spin_lock_irq(&mchdev_lock);
3210
3211 rgvswctl = I915_READ16(MEMSWCTL);
3212
3213 /* Ack interrupts, disable EFC interrupt */
3214 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
3215 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
3216 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
3217 I915_WRITE(DEIIR, DE_PCU_EVENT);
3218 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
3219
3220 /* Go back to the starting frequency */
3221 ironlake_set_drps(dev, dev_priv->ips.fstart);
3222 mdelay(1);
3223 rgvswctl |= MEMCTL_CMD_STS;
3224 I915_WRITE(MEMSWCTL, rgvswctl);
3225 mdelay(1);
3226
3227 spin_unlock_irq(&mchdev_lock);
3228 }
3229
3230 /* There's a funny hw issue where the hw returns all 0 when reading from
3231 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3232 * ourselves, instead of doing a rmw cycle (which might result in us clearing
3233 * all limits and the gpu stuck at whatever frequency it is at atm).
3234 */
3235 static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)
3236 {
3237 u32 limits;
3238
3239 /* Only set the down limit when we've reached the lowest level to avoid
3240 * getting more interrupts, otherwise leave this clear. This prevents a
3241 * race in the hw when coming out of rc6: There's a tiny window where
3242 * the hw runs at the minimal clock before selecting the desired
3243 * frequency, if the down threshold expires in that window we will not
3244 * receive a down interrupt. */
3245 limits = dev_priv->rps.max_freq_softlimit << 24;
3246 if (val <= dev_priv->rps.min_freq_softlimit)
3247 limits |= dev_priv->rps.min_freq_softlimit << 16;
3248
3249 return limits;
3250 }
3251
3252 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
3253 {
3254 int new_power;
3255
3256 if (dev_priv->rps.is_bdw_sw_turbo)
3257 return;
3258
3259 new_power = dev_priv->rps.power;
3260 switch (dev_priv->rps.power) {
3261 case LOW_POWER:
3262 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
3263 new_power = BETWEEN;
3264 break;
3265
3266 case BETWEEN:
3267 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
3268 new_power = LOW_POWER;
3269 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
3270 new_power = HIGH_POWER;
3271 break;
3272
3273 case HIGH_POWER:
3274 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
3275 new_power = BETWEEN;
3276 break;
3277 }
3278 /* Max/min bins are special */
3279 if (val == dev_priv->rps.min_freq_softlimit)
3280 new_power = LOW_POWER;
3281 if (val == dev_priv->rps.max_freq_softlimit)
3282 new_power = HIGH_POWER;
3283 if (new_power == dev_priv->rps.power)
3284 return;
3285
3286 /* Note the units here are not exactly 1us, but 1280ns. */
3287 switch (new_power) {
3288 case LOW_POWER:
3289 /* Upclock if more than 95% busy over 16ms */
3290 I915_WRITE(GEN6_RP_UP_EI, 12500);
3291 I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800);
3292
3293 /* Downclock if less than 85% busy over 32ms */
3294 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3295 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250);
3296
3297 I915_WRITE(GEN6_RP_CONTROL,
3298 GEN6_RP_MEDIA_TURBO |
3299 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3300 GEN6_RP_MEDIA_IS_GFX |
3301 GEN6_RP_ENABLE |
3302 GEN6_RP_UP_BUSY_AVG |
3303 GEN6_RP_DOWN_IDLE_AVG);
3304 break;
3305
3306 case BETWEEN:
3307 /* Upclock if more than 90% busy over 13ms */
3308 I915_WRITE(GEN6_RP_UP_EI, 10250);
3309 I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225);
3310
3311 /* Downclock if less than 75% busy over 32ms */
3312 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3313 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750);
3314
3315 I915_WRITE(GEN6_RP_CONTROL,
3316 GEN6_RP_MEDIA_TURBO |
3317 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3318 GEN6_RP_MEDIA_IS_GFX |
3319 GEN6_RP_ENABLE |
3320 GEN6_RP_UP_BUSY_AVG |
3321 GEN6_RP_DOWN_IDLE_AVG);
3322 break;
3323
3324 case HIGH_POWER:
3325 /* Upclock if more than 85% busy over 10ms */
3326 I915_WRITE(GEN6_RP_UP_EI, 8000);
3327 I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800);
3328
3329 /* Downclock if less than 60% busy over 32ms */
3330 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3331 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000);
3332
3333 I915_WRITE(GEN6_RP_CONTROL,
3334 GEN6_RP_MEDIA_TURBO |
3335 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3336 GEN6_RP_MEDIA_IS_GFX |
3337 GEN6_RP_ENABLE |
3338 GEN6_RP_UP_BUSY_AVG |
3339 GEN6_RP_DOWN_IDLE_AVG);
3340 break;
3341 }
3342
3343 dev_priv->rps.power = new_power;
3344 dev_priv->rps.last_adj = 0;
3345 }
3346
3347 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
3348 {
3349 u32 mask = 0;
3350
3351 if (val > dev_priv->rps.min_freq_softlimit)
3352 mask |= GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
3353 if (val < dev_priv->rps.max_freq_softlimit)
3354 mask |= GEN6_PM_RP_UP_THRESHOLD;
3355
3356 mask |= dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED);
3357 mask &= dev_priv->pm_rps_events;
3358
3359 /* IVB and SNB hard hangs on looping batchbuffer
3360 * if GEN6_PM_UP_EI_EXPIRED is masked.
3361 */
3362 if (INTEL_INFO(dev_priv->dev)->gen <= 7 && !IS_HASWELL(dev_priv->dev))
3363 mask |= GEN6_PM_RP_UP_EI_EXPIRED;
3364
3365 if (IS_GEN8(dev_priv->dev))
3366 mask |= GEN8_PMINTR_REDIRECT_TO_NON_DISP;
3367
3368 return ~mask;
3369 }
3370
3371 /* gen6_set_rps is called to update the frequency request, but should also be
3372 * called when the range (min_delay and max_delay) is modified so that we can
3373 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
3374 void gen6_set_rps(struct drm_device *dev, u8 val)
3375 {
3376 struct drm_i915_private *dev_priv = dev->dev_private;
3377
3378 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3379 WARN_ON(val > dev_priv->rps.max_freq_softlimit);
3380 WARN_ON(val < dev_priv->rps.min_freq_softlimit);
3381
3382 /* min/max delay may still have been modified so be sure to
3383 * write the limits value.
3384 */
3385 if (val != dev_priv->rps.cur_freq) {
3386 gen6_set_rps_thresholds(dev_priv, val);
3387
3388 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3389 I915_WRITE(GEN6_RPNSWREQ,
3390 HSW_FREQUENCY(val));
3391 else
3392 I915_WRITE(GEN6_RPNSWREQ,
3393 GEN6_FREQUENCY(val) |
3394 GEN6_OFFSET(0) |
3395 GEN6_AGGRESSIVE_TURBO);
3396 }
3397
3398 /* Make sure we continue to get interrupts
3399 * until we hit the minimum or maximum frequencies.
3400 */
3401 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, gen6_rps_limits(dev_priv, val));
3402 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
3403
3404 POSTING_READ(GEN6_RPNSWREQ);
3405
3406 dev_priv->rps.cur_freq = val;
3407 trace_intel_gpu_freq_change(val * 50);
3408 }
3409
3410 /* vlv_set_rps_idle: Set the frequency to Rpn if Gfx clocks are down
3411 *
3412 * * If Gfx is Idle, then
3413 * 1. Mask Turbo interrupts
3414 * 2. Bring up Gfx clock
3415 * 3. Change the freq to Rpn and wait till P-Unit updates freq
3416 * 4. Clear the Force GFX CLK ON bit so that Gfx can down
3417 * 5. Unmask Turbo interrupts
3418 */
3419 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
3420 {
3421 struct drm_device *dev = dev_priv->dev;
3422
3423 /* Latest VLV doesn't need to force the gfx clock */
3424 if (dev->pdev->revision >= 0xd) {
3425 valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3426 return;
3427 }
3428
3429 /*
3430 * When we are idle. Drop to min voltage state.
3431 */
3432
3433 if (dev_priv->rps.cur_freq <= dev_priv->rps.min_freq_softlimit)
3434 return;
3435
3436 /* Mask turbo interrupt so that they will not come in between */
3437 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3438
3439 vlv_force_gfx_clock(dev_priv, true);
3440
3441 dev_priv->rps.cur_freq = dev_priv->rps.min_freq_softlimit;
3442
3443 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ,
3444 dev_priv->rps.min_freq_softlimit);
3445
3446 if (wait_for(((vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS))
3447 & GENFREQSTATUS) == 0, 5))
3448 DRM_ERROR("timed out waiting for Punit\n");
3449
3450 vlv_force_gfx_clock(dev_priv, false);
3451
3452 I915_WRITE(GEN6_PMINTRMSK,
3453 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
3454 }
3455
3456 void gen6_rps_idle(struct drm_i915_private *dev_priv)
3457 {
3458 struct drm_device *dev = dev_priv->dev;
3459
3460 mutex_lock(&dev_priv->rps.hw_lock);
3461 if (dev_priv->rps.enabled) {
3462 if (IS_CHERRYVIEW(dev))
3463 valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3464 else if (IS_VALLEYVIEW(dev))
3465 vlv_set_rps_idle(dev_priv);
3466 else if (!dev_priv->rps.is_bdw_sw_turbo
3467 || atomic_read(&dev_priv->rps.sw_turbo.flip_received)){
3468 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3469 }
3470
3471 dev_priv->rps.last_adj = 0;
3472 }
3473 mutex_unlock(&dev_priv->rps.hw_lock);
3474 }
3475
3476 void gen6_rps_boost(struct drm_i915_private *dev_priv)
3477 {
3478 struct drm_device *dev = dev_priv->dev;
3479
3480 mutex_lock(&dev_priv->rps.hw_lock);
3481 if (dev_priv->rps.enabled) {
3482 if (IS_VALLEYVIEW(dev))
3483 valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
3484 else if (!dev_priv->rps.is_bdw_sw_turbo
3485 || atomic_read(&dev_priv->rps.sw_turbo.flip_received)){
3486 gen6_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
3487 }
3488
3489 dev_priv->rps.last_adj = 0;
3490 }
3491 mutex_unlock(&dev_priv->rps.hw_lock);
3492 }
3493
3494 void valleyview_set_rps(struct drm_device *dev, u8 val)
3495 {
3496 struct drm_i915_private *dev_priv = dev->dev_private;
3497
3498 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3499 WARN_ON(val > dev_priv->rps.max_freq_softlimit);
3500 WARN_ON(val < dev_priv->rps.min_freq_softlimit);
3501
3502 DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
3503 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
3504 dev_priv->rps.cur_freq,
3505 vlv_gpu_freq(dev_priv, val), val);
3506
3507 if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1),
3508 "Odd GPU freq value\n"))
3509 val &= ~1;
3510
3511 if (val != dev_priv->rps.cur_freq)
3512 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
3513
3514 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
3515
3516 dev_priv->rps.cur_freq = val;
3517 trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val));
3518 }
3519
3520 static void gen8_disable_rps_interrupts(struct drm_device *dev)
3521 {
3522 struct drm_i915_private *dev_priv = dev->dev_private;
3523 if (IS_BROADWELL(dev) && dev_priv->rps.is_bdw_sw_turbo){
3524 if (atomic_read(&dev_priv->rps.sw_turbo.flip_received))
3525 del_timer(&dev_priv->rps.sw_turbo.flip_timer);
3526 dev_priv-> rps.is_bdw_sw_turbo = false;
3527 } else {
3528 I915_WRITE(GEN6_PMINTRMSK, ~GEN8_PMINTR_REDIRECT_TO_NON_DISP);
3529 I915_WRITE(GEN8_GT_IER(2), I915_READ(GEN8_GT_IER(2)) &
3530 ~dev_priv->pm_rps_events);
3531 /* Complete PM interrupt masking here doesn't race with the rps work
3532 * item again unmasking PM interrupts because that is using a different
3533 * register (GEN8_GT_IMR(2)) to mask PM interrupts. The only risk is in
3534 * leaving stale bits in GEN8_GT_IIR(2) and GEN8_GT_IMR(2) which
3535 * gen8_enable_rps will clean up. */
3536
3537 spin_lock_irq(&dev_priv->irq_lock);
3538 dev_priv->rps.pm_iir = 0;
3539 spin_unlock_irq(&dev_priv->irq_lock);
3540
3541 I915_WRITE(GEN8_GT_IIR(2), dev_priv->pm_rps_events);
3542 }
3543 }
3544
3545 static void gen6_disable_rps_interrupts(struct drm_device *dev)
3546 {
3547 struct drm_i915_private *dev_priv = dev->dev_private;
3548
3549 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3550 I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) &
3551 ~dev_priv->pm_rps_events);
3552 /* Complete PM interrupt masking here doesn't race with the rps work
3553 * item again unmasking PM interrupts because that is using a different
3554 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3555 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3556
3557 spin_lock_irq(&dev_priv->irq_lock);
3558 dev_priv->rps.pm_iir = 0;
3559 spin_unlock_irq(&dev_priv->irq_lock);
3560
3561 I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events);
3562 }
3563
3564 static void gen6_disable_rps(struct drm_device *dev)
3565 {
3566 struct drm_i915_private *dev_priv = dev->dev_private;
3567
3568 I915_WRITE(GEN6_RC_CONTROL, 0);
3569 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
3570
3571 if (IS_BROADWELL(dev))
3572 gen8_disable_rps_interrupts(dev);
3573 else
3574 gen6_disable_rps_interrupts(dev);
3575 }
3576
3577 static void cherryview_disable_rps(struct drm_device *dev)
3578 {
3579 struct drm_i915_private *dev_priv = dev->dev_private;
3580
3581 I915_WRITE(GEN6_RC_CONTROL, 0);
3582
3583 gen8_disable_rps_interrupts(dev);
3584 }
3585
3586 static void valleyview_disable_rps(struct drm_device *dev)
3587 {
3588 struct drm_i915_private *dev_priv = dev->dev_private;
3589
3590 /* we're doing forcewake before Disabling RC6,
3591 * This what the BIOS expects when going into suspend */
3592 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3593
3594 I915_WRITE(GEN6_RC_CONTROL, 0);
3595
3596 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3597
3598 gen6_disable_rps_interrupts(dev);
3599 }
3600
3601 static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
3602 {
3603 if (IS_VALLEYVIEW(dev)) {
3604 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
3605 mode = GEN6_RC_CTL_RC6_ENABLE;
3606 else
3607 mode = 0;
3608 }
3609 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
3610 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3611 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3612 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
3613 }
3614
3615 static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
3616 {
3617 /* No RC6 before Ironlake */
3618 if (INTEL_INFO(dev)->gen < 5)
3619 return 0;
3620
3621 /* RC6 is only on Ironlake mobile not on desktop */
3622 if (INTEL_INFO(dev)->gen == 5 && !IS_IRONLAKE_M(dev))
3623 return 0;
3624
3625 /* Respect the kernel parameter if it is set */
3626 if (enable_rc6 >= 0) {
3627 int mask;
3628
3629 if (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
3630 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
3631 INTEL_RC6pp_ENABLE;
3632 else
3633 mask = INTEL_RC6_ENABLE;
3634
3635 if ((enable_rc6 & mask) != enable_rc6)
3636 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
3637 enable_rc6 & mask, enable_rc6, mask);
3638
3639 return enable_rc6 & mask;
3640 }
3641
3642 /* Disable RC6 on Ironlake */
3643 if (INTEL_INFO(dev)->gen == 5)
3644 return 0;
3645
3646 if (IS_IVYBRIDGE(dev))
3647 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
3648
3649 return INTEL_RC6_ENABLE;
3650 }
3651
3652 int intel_enable_rc6(const struct drm_device *dev)
3653 {
3654 return i915.enable_rc6;
3655 }
3656
3657 static void gen8_enable_rps_interrupts(struct drm_device *dev)
3658 {
3659 struct drm_i915_private *dev_priv = dev->dev_private;
3660
3661 spin_lock_irq(&dev_priv->irq_lock);
3662 WARN_ON(dev_priv->rps.pm_iir);
3663 gen8_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
3664 I915_WRITE(GEN8_GT_IIR(2), dev_priv->pm_rps_events);
3665 spin_unlock_irq(&dev_priv->irq_lock);
3666 }
3667
3668 static void gen6_enable_rps_interrupts(struct drm_device *dev)
3669 {
3670 struct drm_i915_private *dev_priv = dev->dev_private;
3671
3672 spin_lock_irq(&dev_priv->irq_lock);
3673 WARN_ON(dev_priv->rps.pm_iir);
3674 gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
3675 I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events);
3676 spin_unlock_irq(&dev_priv->irq_lock);
3677 }
3678
3679 static void parse_rp_state_cap(struct drm_i915_private *dev_priv, u32 rp_state_cap)
3680 {
3681 /* All of these values are in units of 50MHz */
3682 dev_priv->rps.cur_freq = 0;
3683 /* static values from HW: RP0 < RPe < RP1 < RPn (min_freq) */
3684 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
3685 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
3686 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
3687 /* XXX: only BYT has a special efficient freq */
3688 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
3689 /* hw_max = RP0 until we check for overclocking */
3690 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
3691
3692 /* Preserve min/max settings in case of re-init */
3693 if (dev_priv->rps.max_freq_softlimit == 0)
3694 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
3695
3696 if (dev_priv->rps.min_freq_softlimit == 0)
3697 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
3698 }
3699
3700 static void bdw_sw_calculate_freq(struct drm_device *dev,
3701 struct intel_rps_bdw_cal *c, u32 *cur_time, u32 *c0)
3702 {
3703 struct drm_i915_private *dev_priv = dev->dev_private;
3704 u64 busy = 0;
3705 u32 busyness_pct = 0;
3706 u32 elapsed_time = 0;
3707 u16 new_freq = 0;
3708
3709 if (!c || !cur_time || !c0)
3710 return;
3711
3712 if (0 == c->last_c0)
3713 goto out;
3714
3715 /* Check Evaluation interval */
3716 elapsed_time = *cur_time - c->last_ts;
3717 if (elapsed_time < c->eval_interval)
3718 return;
3719
3720 mutex_lock(&dev_priv->rps.hw_lock);
3721
3722 /*
3723 * c0 unit in 32*1.28 usec, elapsed_time unit in 1 usec.
3724 * Whole busyness_pct calculation should be
3725 * busy = ((u64)(*c0 - c->last_c0) << 5 << 7) / 100;
3726 * busyness_pct = (u32)(busy * 100 / elapsed_time);
3727 * The final formula is to simplify CPU calculation
3728 */
3729 busy = (u64)(*c0 - c->last_c0) << 12;
3730 do_div(busy, elapsed_time);
3731 busyness_pct = (u32)busy;
3732
3733 if (c->is_up && busyness_pct >= c->it_threshold_pct)
3734 new_freq = (u16)dev_priv->rps.cur_freq + 3;
3735 if (!c->is_up && busyness_pct <= c->it_threshold_pct)
3736 new_freq = (u16)dev_priv->rps.cur_freq - 1;
3737
3738 /* Adjust to new frequency busyness and compare with threshold */
3739 if (0 != new_freq) {
3740 if (new_freq > dev_priv->rps.max_freq_softlimit)
3741 new_freq = dev_priv->rps.max_freq_softlimit;
3742 else if (new_freq < dev_priv->rps.min_freq_softlimit)
3743 new_freq = dev_priv->rps.min_freq_softlimit;
3744
3745 gen6_set_rps(dev, new_freq);
3746 }
3747
3748 mutex_unlock(&dev_priv->rps.hw_lock);
3749
3750 out:
3751 c->last_c0 = *c0;
3752 c->last_ts = *cur_time;
3753 }
3754
3755 static void gen8_set_frequency_RP0(struct work_struct *work)
3756 {
3757 struct intel_rps_bdw_turbo *p_bdw_turbo =
3758 container_of(work, struct intel_rps_bdw_turbo, work_max_freq);
3759 struct intel_gen6_power_mgmt *p_power_mgmt =
3760 container_of(p_bdw_turbo, struct intel_gen6_power_mgmt, sw_turbo);
3761 struct drm_i915_private *dev_priv =
3762 container_of(p_power_mgmt, struct drm_i915_private, rps);
3763
3764 mutex_lock(&dev_priv->rps.hw_lock);
3765 gen6_set_rps(dev_priv->dev, dev_priv->rps.rp0_freq);
3766 mutex_unlock(&dev_priv->rps.hw_lock);
3767 }
3768
3769 static void flip_active_timeout_handler(unsigned long var)
3770 {
3771 struct drm_i915_private *dev_priv = (struct drm_i915_private *) var;
3772
3773 del_timer(&dev_priv->rps.sw_turbo.flip_timer);
3774 atomic_set(&dev_priv->rps.sw_turbo.flip_received, false);
3775
3776 queue_work(dev_priv->wq, &dev_priv->rps.sw_turbo.work_max_freq);
3777 }
3778
3779 void bdw_software_turbo(struct drm_device *dev)
3780 {
3781 struct drm_i915_private *dev_priv = dev->dev_private;
3782
3783 u32 current_time = I915_READ(TIMESTAMP_CTR); /* unit in usec */
3784 u32 current_c0 = I915_READ(MCHBAR_PCU_C0); /* unit in 32*1.28 usec */
3785
3786 bdw_sw_calculate_freq(dev, &dev_priv->rps.sw_turbo.up,
3787 &current_time, &current_c0);
3788 bdw_sw_calculate_freq(dev, &dev_priv->rps.sw_turbo.down,
3789 &current_time, &current_c0);
3790 }
3791
3792 static void gen8_enable_rps(struct drm_device *dev)
3793 {
3794 struct drm_i915_private *dev_priv = dev->dev_private;
3795 struct intel_engine_cs *ring;
3796 uint32_t rc6_mask = 0, rp_state_cap;
3797 uint32_t threshold_up_pct, threshold_down_pct;
3798 uint32_t ei_up, ei_down; /* up and down evaluation interval */
3799 u32 rp_ctl_flag;
3800 int unused;
3801
3802 /* Use software Turbo for BDW */
3803 dev_priv->rps.is_bdw_sw_turbo = IS_BROADWELL(dev);
3804
3805 /* 1a: Software RC state - RC0 */
3806 I915_WRITE(GEN6_RC_STATE, 0);
3807
3808 /* 1c & 1d: Get forcewake during program sequence. Although the driver
3809 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
3810 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3811
3812 /* 2a: Disable RC states. */
3813 I915_WRITE(GEN6_RC_CONTROL, 0);
3814
3815 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3816 parse_rp_state_cap(dev_priv, rp_state_cap);
3817
3818 /* 2b: Program RC6 thresholds.*/
3819 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
3820 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
3821 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
3822 for_each_ring(ring, dev_priv, unused)
3823 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3824 I915_WRITE(GEN6_RC_SLEEP, 0);
3825 if (IS_BROADWELL(dev))
3826 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
3827 else
3828 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
3829
3830 /* 3: Enable RC6 */
3831 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
3832 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
3833 intel_print_rc6_info(dev, rc6_mask);
3834 if (IS_BROADWELL(dev))
3835 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
3836 GEN7_RC_CTL_TO_MODE |
3837 rc6_mask);
3838 else
3839 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
3840 GEN6_RC_CTL_EI_MODE(1) |
3841 rc6_mask);
3842
3843 /* 4 Program defaults and thresholds for RPS*/
3844 I915_WRITE(GEN6_RPNSWREQ,
3845 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
3846 I915_WRITE(GEN6_RC_VIDEO_FREQ,
3847 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
3848 ei_up = 84480; /* 84.48ms */
3849 ei_down = 448000;
3850 threshold_up_pct = 90; /* x percent busy */
3851 threshold_down_pct = 70;
3852
3853 if (dev_priv->rps.is_bdw_sw_turbo) {
3854 dev_priv->rps.sw_turbo.up.it_threshold_pct = threshold_up_pct;
3855 dev_priv->rps.sw_turbo.up.eval_interval = ei_up;
3856 dev_priv->rps.sw_turbo.up.is_up = true;
3857 dev_priv->rps.sw_turbo.up.last_ts = 0;
3858 dev_priv->rps.sw_turbo.up.last_c0 = 0;
3859
3860 dev_priv->rps.sw_turbo.down.it_threshold_pct = threshold_down_pct;
3861 dev_priv->rps.sw_turbo.down.eval_interval = ei_down;
3862 dev_priv->rps.sw_turbo.down.is_up = false;
3863 dev_priv->rps.sw_turbo.down.last_ts = 0;
3864 dev_priv->rps.sw_turbo.down.last_c0 = 0;
3865
3866 /* Start the timer to track if flip comes*/
3867 dev_priv->rps.sw_turbo.timeout = 200*1000; /* in us */
3868
3869 init_timer(&dev_priv->rps.sw_turbo.flip_timer);
3870 dev_priv->rps.sw_turbo.flip_timer.function = flip_active_timeout_handler;
3871 dev_priv->rps.sw_turbo.flip_timer.data = (unsigned long) dev_priv;
3872 dev_priv->rps.sw_turbo.flip_timer.expires =
3873 usecs_to_jiffies(dev_priv->rps.sw_turbo.timeout) + jiffies;
3874 add_timer(&dev_priv->rps.sw_turbo.flip_timer);
3875 INIT_WORK(&dev_priv->rps.sw_turbo.work_max_freq, gen8_set_frequency_RP0);
3876
3877 atomic_set(&dev_priv->rps.sw_turbo.flip_received, true);
3878 } else {
3879 /* NB: Docs say 1s, and 1000000 - which aren't equivalent
3880 * 1 second timeout*/
3881 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, FREQ_1_28_US(1000000));
3882
3883 /* Docs recommend 900MHz, and 300 MHz respectively */
3884 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
3885 dev_priv->rps.max_freq_softlimit << 24 |
3886 dev_priv->rps.min_freq_softlimit << 16);
3887
3888 I915_WRITE(GEN6_RP_UP_THRESHOLD,
3889 FREQ_1_28_US(ei_up * threshold_up_pct / 100));
3890 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
3891 FREQ_1_28_US(ei_down * threshold_down_pct / 100));
3892 I915_WRITE(GEN6_RP_UP_EI,
3893 FREQ_1_28_US(ei_up));
3894 I915_WRITE(GEN6_RP_DOWN_EI,
3895 FREQ_1_28_US(ei_down));
3896
3897 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3898 }
3899
3900 /* 5: Enable RPS */
3901 rp_ctl_flag = GEN6_RP_MEDIA_TURBO |
3902 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3903 GEN6_RP_MEDIA_IS_GFX |
3904 GEN6_RP_UP_BUSY_AVG |
3905 GEN6_RP_DOWN_IDLE_AVG;
3906 if (!dev_priv->rps.is_bdw_sw_turbo)
3907 rp_ctl_flag |= GEN6_RP_ENABLE;
3908
3909 I915_WRITE(GEN6_RP_CONTROL, rp_ctl_flag);
3910
3911 /* 6: Ring frequency + overclocking
3912 * (our driver does this later */
3913 gen6_set_rps(dev, (I915_READ(GEN6_GT_PERF_STATUS) & 0xff00) >> 8);
3914 if (!dev_priv->rps.is_bdw_sw_turbo)
3915 gen8_enable_rps_interrupts(dev);
3916
3917 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3918 }
3919
3920 static void gen6_enable_rps(struct drm_device *dev)
3921 {
3922 struct drm_i915_private *dev_priv = dev->dev_private;
3923 struct intel_engine_cs *ring;
3924 u32 rp_state_cap;
3925 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
3926 u32 gtfifodbg;
3927 int rc6_mode;
3928 int i, ret;
3929
3930 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3931
3932 /* Here begins a magic sequence of register writes to enable
3933 * auto-downclocking.
3934 *
3935 * Perhaps there might be some value in exposing these to
3936 * userspace...
3937 */
3938 I915_WRITE(GEN6_RC_STATE, 0);
3939
3940 /* Clear the DBG now so we don't confuse earlier errors */
3941 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3942 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3943 I915_WRITE(GTFIFODBG, gtfifodbg);
3944 }
3945
3946 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3947
3948 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3949
3950 parse_rp_state_cap(dev_priv, rp_state_cap);
3951
3952 /* disable the counters and set deterministic thresholds */
3953 I915_WRITE(GEN6_RC_CONTROL, 0);
3954
3955 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
3956 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
3957 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
3958 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3959 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3960
3961 for_each_ring(ring, dev_priv, i)
3962 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3963
3964 I915_WRITE(GEN6_RC_SLEEP, 0);
3965 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
3966 if (IS_IVYBRIDGE(dev))
3967 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
3968 else
3969 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
3970 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
3971 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
3972
3973 /* Check if we are enabling RC6 */
3974 rc6_mode = intel_enable_rc6(dev_priv->dev);
3975 if (rc6_mode & INTEL_RC6_ENABLE)
3976 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
3977
3978 /* We don't use those on Haswell */
3979 if (!IS_HASWELL(dev)) {
3980 if (rc6_mode & INTEL_RC6p_ENABLE)
3981 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
3982
3983 if (rc6_mode & INTEL_RC6pp_ENABLE)
3984 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
3985 }
3986
3987 intel_print_rc6_info(dev, rc6_mask);
3988
3989 I915_WRITE(GEN6_RC_CONTROL,
3990 rc6_mask |
3991 GEN6_RC_CTL_EI_MODE(1) |
3992 GEN6_RC_CTL_HW_ENABLE);
3993
3994 /* Power down if completely idle for over 50ms */
3995 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
3996 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3997
3998 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
3999 if (ret)
4000 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
4001
4002 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
4003 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
4004 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
4005 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
4006 (pcu_mbox & 0xff) * 50);
4007 dev_priv->rps.max_freq = pcu_mbox & 0xff;
4008 }
4009
4010 dev_priv->rps.power = HIGH_POWER; /* force a reset */
4011 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
4012
4013 gen6_enable_rps_interrupts(dev);
4014
4015 rc6vids = 0;
4016 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
4017 if (IS_GEN6(dev) && ret) {
4018 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
4019 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
4020 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
4021 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
4022 rc6vids &= 0xffff00;
4023 rc6vids |= GEN6_ENCODE_RC6_VID(450);
4024 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
4025 if (ret)
4026 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
4027 }
4028
4029 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
4030 }
4031
4032 static void __gen6_update_ring_freq(struct drm_device *dev)
4033 {
4034 struct drm_i915_private *dev_priv = dev->dev_private;
4035 int min_freq = 15;
4036 unsigned int gpu_freq;
4037 unsigned int max_ia_freq, min_ring_freq;
4038 int scaling_factor = 180;
4039 struct cpufreq_policy *policy;
4040
4041 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4042
4043 policy = cpufreq_cpu_get(0);
4044 if (policy) {
4045 max_ia_freq = policy->cpuinfo.max_freq;
4046 cpufreq_cpu_put(policy);
4047 } else {
4048 /*
4049 * Default to measured freq if none found, PCU will ensure we
4050 * don't go over
4051 */
4052 max_ia_freq = tsc_khz;
4053 }
4054
4055 /* Convert from kHz to MHz */
4056 max_ia_freq /= 1000;
4057
4058 min_ring_freq = I915_READ(DCLK) & 0xf;
4059 /* convert DDR frequency from units of 266.6MHz to bandwidth */
4060 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
4061
4062 /*
4063 * For each potential GPU frequency, load a ring frequency we'd like
4064 * to use for memory access. We do this by specifying the IA frequency
4065 * the PCU should use as a reference to determine the ring frequency.
4066 */
4067 for (gpu_freq = dev_priv->rps.max_freq_softlimit; gpu_freq >= dev_priv->rps.min_freq_softlimit;
4068 gpu_freq--) {
4069 int diff = dev_priv->rps.max_freq_softlimit - gpu_freq;
4070 unsigned int ia_freq = 0, ring_freq = 0;
4071
4072 if (INTEL_INFO(dev)->gen >= 8) {
4073 /* max(2 * GT, DDR). NB: GT is 50MHz units */
4074 ring_freq = max(min_ring_freq, gpu_freq);
4075 } else if (IS_HASWELL(dev)) {
4076 ring_freq = mult_frac(gpu_freq, 5, 4);
4077 ring_freq = max(min_ring_freq, ring_freq);
4078 /* leave ia_freq as the default, chosen by cpufreq */
4079 } else {
4080 /* On older processors, there is no separate ring
4081 * clock domain, so in order to boost the bandwidth
4082 * of the ring, we need to upclock the CPU (ia_freq).
4083 *
4084 * For GPU frequencies less than 750MHz,
4085 * just use the lowest ring freq.
4086 */
4087 if (gpu_freq < min_freq)
4088 ia_freq = 800;
4089 else
4090 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
4091 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
4092 }
4093
4094 sandybridge_pcode_write(dev_priv,
4095 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
4096 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
4097 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
4098 gpu_freq);
4099 }
4100 }
4101
4102 void gen6_update_ring_freq(struct drm_device *dev)
4103 {
4104 struct drm_i915_private *dev_priv = dev->dev_private;
4105
4106 if (INTEL_INFO(dev)->gen < 6 || IS_VALLEYVIEW(dev))
4107 return;
4108
4109 mutex_lock(&dev_priv->rps.hw_lock);
4110 __gen6_update_ring_freq(dev);
4111 mutex_unlock(&dev_priv->rps.hw_lock);
4112 }
4113
4114 static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
4115 {
4116 u32 val, rp0;
4117
4118 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
4119 rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & PUNIT_GPU_STATUS_MAX_FREQ_MASK;
4120
4121 return rp0;
4122 }
4123
4124 static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
4125 {
4126 u32 val, rpe;
4127
4128 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
4129 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
4130
4131 return rpe;
4132 }
4133
4134 static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
4135 {
4136 u32 val, rp1;
4137
4138 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4139 rp1 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & PUNIT_GPU_STATUS_MAX_FREQ_MASK;
4140
4141 return rp1;
4142 }
4143
4144 static int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
4145 {
4146 u32 val, rpn;
4147
4148 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
4149 rpn = (val >> PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT) & PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK;
4150 return rpn;
4151 }
4152
4153 static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
4154 {
4155 u32 val, rp1;
4156
4157 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
4158
4159 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
4160
4161 return rp1;
4162 }
4163
4164 static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
4165 {
4166 u32 val, rp0;
4167
4168 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
4169
4170 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
4171 /* Clamp to max */
4172 rp0 = min_t(u32, rp0, 0xea);
4173
4174 return rp0;
4175 }
4176
4177 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
4178 {
4179 u32 val, rpe;
4180
4181 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
4182 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
4183 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
4184 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
4185
4186 return rpe;
4187 }
4188
4189 static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
4190 {
4191 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
4192 }
4193
4194 /* Check that the pctx buffer wasn't move under us. */
4195 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
4196 {
4197 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
4198
4199 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
4200 dev_priv->vlv_pctx->stolen->start);
4201 }
4202
4203
4204 /* Check that the pcbr address is not empty. */
4205 static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
4206 {
4207 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
4208
4209 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
4210 }
4211
4212 static void cherryview_setup_pctx(struct drm_device *dev)
4213 {
4214 struct drm_i915_private *dev_priv = dev->dev_private;
4215 unsigned long pctx_paddr, paddr;
4216 struct i915_gtt *gtt = &dev_priv->gtt;
4217 u32 pcbr;
4218 int pctx_size = 32*1024;
4219
4220 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4221
4222 pcbr = I915_READ(VLV_PCBR);
4223 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
4224 paddr = (dev_priv->mm.stolen_base +
4225 (gtt->stolen_size - pctx_size));
4226
4227 pctx_paddr = (paddr & (~4095));
4228 I915_WRITE(VLV_PCBR, pctx_paddr);
4229 }
4230 }
4231
4232 static void valleyview_setup_pctx(struct drm_device *dev)
4233 {
4234 struct drm_i915_private *dev_priv = dev->dev_private;
4235 struct drm_i915_gem_object *pctx;
4236 unsigned long pctx_paddr;
4237 u32 pcbr;
4238 int pctx_size = 24*1024;
4239
4240 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4241
4242 pcbr = I915_READ(VLV_PCBR);
4243 if (pcbr) {
4244 /* BIOS set it up already, grab the pre-alloc'd space */
4245 int pcbr_offset;
4246
4247 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
4248 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
4249 pcbr_offset,
4250 I915_GTT_OFFSET_NONE,
4251 pctx_size);
4252 goto out;
4253 }
4254
4255 /*
4256 * From the Gunit register HAS:
4257 * The Gfx driver is expected to program this register and ensure
4258 * proper allocation within Gfx stolen memory. For example, this
4259 * register should be programmed such than the PCBR range does not
4260 * overlap with other ranges, such as the frame buffer, protected
4261 * memory, or any other relevant ranges.
4262 */
4263 pctx = i915_gem_object_create_stolen(dev, pctx_size);
4264 if (!pctx) {
4265 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
4266 return;
4267 }
4268
4269 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
4270 I915_WRITE(VLV_PCBR, pctx_paddr);
4271
4272 out:
4273 dev_priv->vlv_pctx = pctx;
4274 }
4275
4276 static void valleyview_cleanup_pctx(struct drm_device *dev)
4277 {
4278 struct drm_i915_private *dev_priv = dev->dev_private;
4279
4280 if (WARN_ON(!dev_priv->vlv_pctx))
4281 return;
4282
4283 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
4284 dev_priv->vlv_pctx = NULL;
4285 }
4286
4287 static void valleyview_init_gt_powersave(struct drm_device *dev)
4288 {
4289 struct drm_i915_private *dev_priv = dev->dev_private;
4290 u32 val;
4291
4292 valleyview_setup_pctx(dev);
4293
4294 mutex_lock(&dev_priv->rps.hw_lock);
4295
4296 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4297 switch ((val >> 6) & 3) {
4298 case 0:
4299 case 1:
4300 dev_priv->mem_freq = 800;
4301 break;
4302 case 2:
4303 dev_priv->mem_freq = 1066;
4304 break;
4305 case 3:
4306 dev_priv->mem_freq = 1333;
4307 break;
4308 }
4309 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
4310
4311 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
4312 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
4313 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
4314 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4315 dev_priv->rps.max_freq);
4316
4317 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
4318 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
4319 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4320 dev_priv->rps.efficient_freq);
4321
4322 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
4323 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
4324 vlv_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
4325 dev_priv->rps.rp1_freq);
4326
4327 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
4328 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
4329 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4330 dev_priv->rps.min_freq);
4331
4332 /* Preserve min/max settings in case of re-init */
4333 if (dev_priv->rps.max_freq_softlimit == 0)
4334 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4335
4336 if (dev_priv->rps.min_freq_softlimit == 0)
4337 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
4338
4339 mutex_unlock(&dev_priv->rps.hw_lock);
4340 }
4341
4342 static void cherryview_init_gt_powersave(struct drm_device *dev)
4343 {
4344 struct drm_i915_private *dev_priv = dev->dev_private;
4345 u32 val;
4346
4347 cherryview_setup_pctx(dev);
4348
4349 mutex_lock(&dev_priv->rps.hw_lock);
4350
4351 val = vlv_punit_read(dev_priv, CCK_FUSE_REG);
4352 switch ((val >> 2) & 0x7) {
4353 case 0:
4354 case 1:
4355 dev_priv->rps.cz_freq = 200;
4356 dev_priv->mem_freq = 1600;
4357 break;
4358 case 2:
4359 dev_priv->rps.cz_freq = 267;
4360 dev_priv->mem_freq = 1600;
4361 break;
4362 case 3:
4363 dev_priv->rps.cz_freq = 333;
4364 dev_priv->mem_freq = 2000;
4365 break;
4366 case 4:
4367 dev_priv->rps.cz_freq = 320;
4368 dev_priv->mem_freq = 1600;
4369 break;
4370 case 5:
4371 dev_priv->rps.cz_freq = 400;
4372 dev_priv->mem_freq = 1600;
4373 break;
4374 }
4375 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
4376
4377 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
4378 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
4379 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
4380 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4381 dev_priv->rps.max_freq);
4382
4383 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
4384 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
4385 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4386 dev_priv->rps.efficient_freq);
4387
4388 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
4389 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
4390 vlv_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
4391 dev_priv->rps.rp1_freq);
4392
4393 dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv);
4394 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
4395 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4396 dev_priv->rps.min_freq);
4397
4398 WARN_ONCE((dev_priv->rps.max_freq |
4399 dev_priv->rps.efficient_freq |
4400 dev_priv->rps.rp1_freq |
4401 dev_priv->rps.min_freq) & 1,
4402 "Odd GPU freq values\n");
4403
4404 /* Preserve min/max settings in case of re-init */
4405 if (dev_priv->rps.max_freq_softlimit == 0)
4406 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4407
4408 if (dev_priv->rps.min_freq_softlimit == 0)
4409 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
4410
4411 mutex_unlock(&dev_priv->rps.hw_lock);
4412 }
4413
4414 static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
4415 {
4416 valleyview_cleanup_pctx(dev);
4417 }
4418
4419 static void cherryview_enable_rps(struct drm_device *dev)
4420 {
4421 struct drm_i915_private *dev_priv = dev->dev_private;
4422 struct intel_engine_cs *ring;
4423 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
4424 int i;
4425
4426 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4427
4428 gtfifodbg = I915_READ(GTFIFODBG);
4429 if (gtfifodbg) {
4430 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4431 gtfifodbg);
4432 I915_WRITE(GTFIFODBG, gtfifodbg);
4433 }
4434
4435 cherryview_check_pctx(dev_priv);
4436
4437 /* 1a & 1b: Get forcewake during program sequence. Although the driver
4438 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4439 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
4440
4441 /* 2a: Program RC6 thresholds.*/
4442 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4443 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4444 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4445
4446 for_each_ring(ring, dev_priv, i)
4447 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4448 I915_WRITE(GEN6_RC_SLEEP, 0);
4449
4450 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
4451
4452 /* allows RC6 residency counter to work */
4453 I915_WRITE(VLV_COUNTER_CONTROL,
4454 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
4455 VLV_MEDIA_RC6_COUNT_EN |
4456 VLV_RENDER_RC6_COUNT_EN));
4457
4458 /* For now we assume BIOS is allocating and populating the PCBR */
4459 pcbr = I915_READ(VLV_PCBR);
4460
4461 DRM_DEBUG_DRIVER("PCBR offset : 0x%x\n", pcbr);
4462
4463 /* 3: Enable RC6 */
4464 if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
4465 (pcbr >> VLV_PCBR_ADDR_SHIFT))
4466 rc6_mode = GEN6_RC_CTL_EI_MODE(1);
4467
4468 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
4469
4470 /* 4 Program defaults and thresholds for RPS*/
4471 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
4472 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
4473 I915_WRITE(GEN6_RP_UP_EI, 66000);
4474 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
4475
4476 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4477
4478 /* WaDisablePwrmtrEvent:chv (pre-production hw) */
4479 I915_WRITE(0xA80C, I915_READ(0xA80C) & 0x00ffffff);
4480 I915_WRITE(0xA810, I915_READ(0xA810) & 0xffffff00);
4481
4482 /* 5: Enable RPS */
4483 I915_WRITE(GEN6_RP_CONTROL,
4484 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4485 GEN6_RP_MEDIA_IS_GFX | /* WaSetMaskForGfxBusyness:chv (pre-production hw ?) */
4486 GEN6_RP_ENABLE |
4487 GEN6_RP_UP_BUSY_AVG |
4488 GEN6_RP_DOWN_IDLE_AVG);
4489
4490 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4491
4492 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
4493 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
4494
4495 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
4496 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
4497 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
4498 dev_priv->rps.cur_freq);
4499
4500 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
4501 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4502 dev_priv->rps.efficient_freq);
4503
4504 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
4505
4506 gen8_enable_rps_interrupts(dev);
4507
4508 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
4509 }
4510
4511 static void valleyview_enable_rps(struct drm_device *dev)
4512 {
4513 struct drm_i915_private *dev_priv = dev->dev_private;
4514 struct intel_engine_cs *ring;
4515 u32 gtfifodbg, val, rc6_mode = 0;
4516 int i;
4517
4518 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4519
4520 valleyview_check_pctx(dev_priv);
4521
4522 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
4523 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4524 gtfifodbg);
4525 I915_WRITE(GTFIFODBG, gtfifodbg);
4526 }
4527
4528 /* If VLV, Forcewake all wells, else re-direct to regular path */
4529 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
4530
4531 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
4532 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
4533 I915_WRITE(GEN6_RP_UP_EI, 66000);
4534 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
4535
4536 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4537 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 0xf4240);
4538
4539 I915_WRITE(GEN6_RP_CONTROL,
4540 GEN6_RP_MEDIA_TURBO |
4541 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4542 GEN6_RP_MEDIA_IS_GFX |
4543 GEN6_RP_ENABLE |
4544 GEN6_RP_UP_BUSY_AVG |
4545 GEN6_RP_DOWN_IDLE_CONT);
4546
4547 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
4548 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4549 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4550
4551 for_each_ring(ring, dev_priv, i)
4552 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4553
4554 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
4555
4556 /* allows RC6 residency counter to work */
4557 I915_WRITE(VLV_COUNTER_CONTROL,
4558 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
4559 VLV_RENDER_RC0_COUNT_EN |
4560 VLV_MEDIA_RC6_COUNT_EN |
4561 VLV_RENDER_RC6_COUNT_EN));
4562
4563 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4564 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
4565
4566 intel_print_rc6_info(dev, rc6_mode);
4567
4568 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
4569
4570 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4571
4572 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
4573 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
4574
4575 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
4576 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
4577 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
4578 dev_priv->rps.cur_freq);
4579
4580 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
4581 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4582 dev_priv->rps.efficient_freq);
4583
4584 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
4585
4586 gen6_enable_rps_interrupts(dev);
4587
4588 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
4589 }
4590
4591 void ironlake_teardown_rc6(struct drm_device *dev)
4592 {
4593 struct drm_i915_private *dev_priv = dev->dev_private;
4594
4595 if (dev_priv->ips.renderctx) {
4596 i915_gem_object_ggtt_unpin(dev_priv->ips.renderctx);
4597 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
4598 dev_priv->ips.renderctx = NULL;
4599 }
4600
4601 if (dev_priv->ips.pwrctx) {
4602 i915_gem_object_ggtt_unpin(dev_priv->ips.pwrctx);
4603 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
4604 dev_priv->ips.pwrctx = NULL;
4605 }
4606 }
4607
4608 static void ironlake_disable_rc6(struct drm_device *dev)
4609 {
4610 struct drm_i915_private *dev_priv = dev->dev_private;
4611
4612 if (I915_READ(PWRCTXA)) {
4613 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
4614 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
4615 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
4616 50);
4617
4618 I915_WRITE(PWRCTXA, 0);
4619 POSTING_READ(PWRCTXA);
4620
4621 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
4622 POSTING_READ(RSTDBYCTL);
4623 }
4624 }
4625
4626 static int ironlake_setup_rc6(struct drm_device *dev)
4627 {
4628 struct drm_i915_private *dev_priv = dev->dev_private;
4629
4630 if (dev_priv->ips.renderctx == NULL)
4631 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
4632 if (!dev_priv->ips.renderctx)
4633 return -ENOMEM;
4634
4635 if (dev_priv->ips.pwrctx == NULL)
4636 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
4637 if (!dev_priv->ips.pwrctx) {
4638 ironlake_teardown_rc6(dev);
4639 return -ENOMEM;
4640 }
4641
4642 return 0;
4643 }
4644
4645 static void ironlake_enable_rc6(struct drm_device *dev)
4646 {
4647 struct drm_i915_private *dev_priv = dev->dev_private;
4648 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
4649 bool was_interruptible;
4650 int ret;
4651
4652 /* rc6 disabled by default due to repeated reports of hanging during
4653 * boot and resume.
4654 */
4655 if (!intel_enable_rc6(dev))
4656 return;
4657
4658 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4659
4660 ret = ironlake_setup_rc6(dev);
4661 if (ret)
4662 return;
4663
4664 was_interruptible = dev_priv->mm.interruptible;
4665 dev_priv->mm.interruptible = false;
4666
4667 /*
4668 * GPU can automatically power down the render unit if given a page
4669 * to save state.
4670 */
4671 ret = intel_ring_begin(ring, 6);
4672 if (ret) {
4673 ironlake_teardown_rc6(dev);
4674 dev_priv->mm.interruptible = was_interruptible;
4675 return;
4676 }
4677
4678 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
4679 intel_ring_emit(ring, MI_SET_CONTEXT);
4680 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) |
4681 MI_MM_SPACE_GTT |
4682 MI_SAVE_EXT_STATE_EN |
4683 MI_RESTORE_EXT_STATE_EN |
4684 MI_RESTORE_INHIBIT);
4685 intel_ring_emit(ring, MI_SUSPEND_FLUSH);
4686 intel_ring_emit(ring, MI_NOOP);
4687 intel_ring_emit(ring, MI_FLUSH);
4688 intel_ring_advance(ring);
4689
4690 /*
4691 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
4692 * does an implicit flush, combined with MI_FLUSH above, it should be
4693 * safe to assume that renderctx is valid
4694 */
4695 ret = intel_ring_idle(ring);
4696 dev_priv->mm.interruptible = was_interruptible;
4697 if (ret) {
4698 DRM_ERROR("failed to enable ironlake power savings\n");
4699 ironlake_teardown_rc6(dev);
4700 return;
4701 }
4702
4703 I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN);
4704 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
4705
4706 intel_print_rc6_info(dev, GEN6_RC_CTL_RC6_ENABLE);
4707 }
4708
4709 static unsigned long intel_pxfreq(u32 vidfreq)
4710 {
4711 unsigned long freq;
4712 int div = (vidfreq & 0x3f0000) >> 16;
4713 int post = (vidfreq & 0x3000) >> 12;
4714 int pre = (vidfreq & 0x7);
4715
4716 if (!pre)
4717 return 0;
4718
4719 freq = ((div * 133333) / ((1<<post) * pre));
4720
4721 return freq;
4722 }
4723
4724 static const struct cparams {
4725 u16 i;
4726 u16 t;
4727 u16 m;
4728 u16 c;
4729 } cparams[] = {
4730 { 1, 1333, 301, 28664 },
4731 { 1, 1066, 294, 24460 },
4732 { 1, 800, 294, 25192 },
4733 { 0, 1333, 276, 27605 },
4734 { 0, 1066, 276, 27605 },
4735 { 0, 800, 231, 23784 },
4736 };
4737
4738 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
4739 {
4740 u64 total_count, diff, ret;
4741 u32 count1, count2, count3, m = 0, c = 0;
4742 unsigned long now = jiffies_to_msecs(jiffies), diff1;
4743 int i;
4744
4745 assert_spin_locked(&mchdev_lock);
4746
4747 diff1 = now - dev_priv->ips.last_time1;
4748
4749 /* Prevent division-by-zero if we are asking too fast.
4750 * Also, we don't get interesting results if we are polling
4751 * faster than once in 10ms, so just return the saved value
4752 * in such cases.
4753 */
4754 if (diff1 <= 10)
4755 return dev_priv->ips.chipset_power;
4756
4757 count1 = I915_READ(DMIEC);
4758 count2 = I915_READ(DDREC);
4759 count3 = I915_READ(CSIEC);
4760
4761 total_count = count1 + count2 + count3;
4762
4763 /* FIXME: handle per-counter overflow */
4764 if (total_count < dev_priv->ips.last_count1) {
4765 diff = ~0UL - dev_priv->ips.last_count1;
4766 diff += total_count;
4767 } else {
4768 diff = total_count - dev_priv->ips.last_count1;
4769 }
4770
4771 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
4772 if (cparams[i].i == dev_priv->ips.c_m &&
4773 cparams[i].t == dev_priv->ips.r_t) {
4774 m = cparams[i].m;
4775 c = cparams[i].c;
4776 break;
4777 }
4778 }
4779
4780 diff = div_u64(diff, diff1);
4781 ret = ((m * diff) + c);
4782 ret = div_u64(ret, 10);
4783
4784 dev_priv->ips.last_count1 = total_count;
4785 dev_priv->ips.last_time1 = now;
4786
4787 dev_priv->ips.chipset_power = ret;
4788
4789 return ret;
4790 }
4791
4792 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
4793 {
4794 struct drm_device *dev = dev_priv->dev;
4795 unsigned long val;
4796
4797 if (INTEL_INFO(dev)->gen != 5)
4798 return 0;
4799
4800 spin_lock_irq(&mchdev_lock);
4801
4802 val = __i915_chipset_val(dev_priv);
4803
4804 spin_unlock_irq(&mchdev_lock);
4805
4806 return val;
4807 }
4808
4809 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
4810 {
4811 unsigned long m, x, b;
4812 u32 tsfs;
4813
4814 tsfs = I915_READ(TSFS);
4815
4816 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
4817 x = I915_READ8(TR1);
4818
4819 b = tsfs & TSFS_INTR_MASK;
4820
4821 return ((m * x) / 127) - b;
4822 }
4823
4824 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
4825 {
4826 struct drm_device *dev = dev_priv->dev;
4827 static const struct v_table {
4828 u16 vd; /* in .1 mil */
4829 u16 vm; /* in .1 mil */
4830 } v_table[] = {
4831 { 0, 0, },
4832 { 375, 0, },
4833 { 500, 0, },
4834 { 625, 0, },
4835 { 750, 0, },
4836 { 875, 0, },
4837 { 1000, 0, },
4838 { 1125, 0, },
4839 { 4125, 3000, },
4840 { 4125, 3000, },
4841 { 4125, 3000, },
4842 { 4125, 3000, },
4843 { 4125, 3000, },
4844 { 4125, 3000, },
4845 { 4125, 3000, },
4846 { 4125, 3000, },
4847 { 4125, 3000, },
4848 { 4125, 3000, },
4849 { 4125, 3000, },
4850 { 4125, 3000, },
4851 { 4125, 3000, },
4852 { 4125, 3000, },
4853 { 4125, 3000, },
4854 { 4125, 3000, },
4855 { 4125, 3000, },
4856 { 4125, 3000, },
4857 { 4125, 3000, },
4858 { 4125, 3000, },
4859 { 4125, 3000, },
4860 { 4125, 3000, },
4861 { 4125, 3000, },
4862 { 4125, 3000, },
4863 { 4250, 3125, },
4864 { 4375, 3250, },
4865 { 4500, 3375, },
4866 { 4625, 3500, },
4867 { 4750, 3625, },
4868 { 4875, 3750, },
4869 { 5000, 3875, },
4870 { 5125, 4000, },
4871 { 5250, 4125, },
4872 { 5375, 4250, },
4873 { 5500, 4375, },
4874 { 5625, 4500, },
4875 { 5750, 4625, },
4876 { 5875, 4750, },
4877 { 6000, 4875, },
4878 { 6125, 5000, },
4879 { 6250, 5125, },
4880 { 6375, 5250, },
4881 { 6500, 5375, },
4882 { 6625, 5500, },
4883 { 6750, 5625, },
4884 { 6875, 5750, },
4885 { 7000, 5875, },
4886 { 7125, 6000, },
4887 { 7250, 6125, },
4888 { 7375, 6250, },
4889 { 7500, 6375, },
4890 { 7625, 6500, },
4891 { 7750, 6625, },
4892 { 7875, 6750, },
4893 { 8000, 6875, },
4894 { 8125, 7000, },
4895 { 8250, 7125, },
4896 { 8375, 7250, },
4897 { 8500, 7375, },
4898 { 8625, 7500, },
4899 { 8750, 7625, },
4900 { 8875, 7750, },
4901 { 9000, 7875, },
4902 { 9125, 8000, },
4903 { 9250, 8125, },
4904 { 9375, 8250, },
4905 { 9500, 8375, },
4906 { 9625, 8500, },
4907 { 9750, 8625, },
4908 { 9875, 8750, },
4909 { 10000, 8875, },
4910 { 10125, 9000, },
4911 { 10250, 9125, },
4912 { 10375, 9250, },
4913 { 10500, 9375, },
4914 { 10625, 9500, },
4915 { 10750, 9625, },
4916 { 10875, 9750, },
4917 { 11000, 9875, },
4918 { 11125, 10000, },
4919 { 11250, 10125, },
4920 { 11375, 10250, },
4921 { 11500, 10375, },
4922 { 11625, 10500, },
4923 { 11750, 10625, },
4924 { 11875, 10750, },
4925 { 12000, 10875, },
4926 { 12125, 11000, },
4927 { 12250, 11125, },
4928 { 12375, 11250, },
4929 { 12500, 11375, },
4930 { 12625, 11500, },
4931 { 12750, 11625, },
4932 { 12875, 11750, },
4933 { 13000, 11875, },
4934 { 13125, 12000, },
4935 { 13250, 12125, },
4936 { 13375, 12250, },
4937 { 13500, 12375, },
4938 { 13625, 12500, },
4939 { 13750, 12625, },
4940 { 13875, 12750, },
4941 { 14000, 12875, },
4942 { 14125, 13000, },
4943 { 14250, 13125, },
4944 { 14375, 13250, },
4945 { 14500, 13375, },
4946 { 14625, 13500, },
4947 { 14750, 13625, },
4948 { 14875, 13750, },
4949 { 15000, 13875, },
4950 { 15125, 14000, },
4951 { 15250, 14125, },
4952 { 15375, 14250, },
4953 { 15500, 14375, },
4954 { 15625, 14500, },
4955 { 15750, 14625, },
4956 { 15875, 14750, },
4957 { 16000, 14875, },
4958 { 16125, 15000, },
4959 };
4960 if (INTEL_INFO(dev)->is_mobile)
4961 return v_table[pxvid].vm;
4962 else
4963 return v_table[pxvid].vd;
4964 }
4965
4966 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
4967 {
4968 u64 now, diff, diffms;
4969 u32 count;
4970
4971 assert_spin_locked(&mchdev_lock);
4972
4973 now = ktime_get_raw_ns();
4974 diffms = now - dev_priv->ips.last_time2;
4975 do_div(diffms, NSEC_PER_MSEC);
4976
4977 /* Don't divide by 0 */
4978 if (!diffms)
4979 return;
4980
4981 count = I915_READ(GFXEC);
4982
4983 if (count < dev_priv->ips.last_count2) {
4984 diff = ~0UL - dev_priv->ips.last_count2;
4985 diff += count;
4986 } else {
4987 diff = count - dev_priv->ips.last_count2;
4988 }
4989
4990 dev_priv->ips.last_count2 = count;
4991 dev_priv->ips.last_time2 = now;
4992
4993 /* More magic constants... */
4994 diff = diff * 1181;
4995 diff = div_u64(diff, diffms * 10);
4996 dev_priv->ips.gfx_power = diff;
4997 }
4998
4999 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
5000 {
5001 struct drm_device *dev = dev_priv->dev;
5002
5003 if (INTEL_INFO(dev)->gen != 5)
5004 return;
5005
5006 spin_lock_irq(&mchdev_lock);
5007
5008 __i915_update_gfx_val(dev_priv);
5009
5010 spin_unlock_irq(&mchdev_lock);
5011 }
5012
5013 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
5014 {
5015 unsigned long t, corr, state1, corr2, state2;
5016 u32 pxvid, ext_v;
5017
5018 assert_spin_locked(&mchdev_lock);
5019
5020 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_freq * 4));
5021 pxvid = (pxvid >> 24) & 0x7f;
5022 ext_v = pvid_to_extvid(dev_priv, pxvid);
5023
5024 state1 = ext_v;
5025
5026 t = i915_mch_val(dev_priv);
5027
5028 /* Revel in the empirically derived constants */
5029
5030 /* Correction factor in 1/100000 units */
5031 if (t > 80)
5032 corr = ((t * 2349) + 135940);
5033 else if (t >= 50)
5034 corr = ((t * 964) + 29317);
5035 else /* < 50 */
5036 corr = ((t * 301) + 1004);
5037
5038 corr = corr * ((150142 * state1) / 10000 - 78642);
5039 corr /= 100000;
5040 corr2 = (corr * dev_priv->ips.corr);
5041
5042 state2 = (corr2 * state1) / 10000;
5043 state2 /= 100; /* convert to mW */
5044
5045 __i915_update_gfx_val(dev_priv);
5046
5047 return dev_priv->ips.gfx_power + state2;
5048 }
5049
5050 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
5051 {
5052 struct drm_device *dev = dev_priv->dev;
5053 unsigned long val;
5054
5055 if (INTEL_INFO(dev)->gen != 5)
5056 return 0;
5057
5058 spin_lock_irq(&mchdev_lock);
5059
5060 val = __i915_gfx_val(dev_priv);
5061
5062 spin_unlock_irq(&mchdev_lock);
5063
5064 return val;
5065 }
5066
5067 /**
5068 * i915_read_mch_val - return value for IPS use
5069 *
5070 * Calculate and return a value for the IPS driver to use when deciding whether
5071 * we have thermal and power headroom to increase CPU or GPU power budget.
5072 */
5073 unsigned long i915_read_mch_val(void)
5074 {
5075 struct drm_i915_private *dev_priv;
5076 unsigned long chipset_val, graphics_val, ret = 0;
5077
5078 spin_lock_irq(&mchdev_lock);
5079 if (!i915_mch_dev)
5080 goto out_unlock;
5081 dev_priv = i915_mch_dev;
5082
5083 chipset_val = __i915_chipset_val(dev_priv);
5084 graphics_val = __i915_gfx_val(dev_priv);
5085
5086 ret = chipset_val + graphics_val;
5087
5088 out_unlock:
5089 spin_unlock_irq(&mchdev_lock);
5090
5091 return ret;
5092 }
5093 EXPORT_SYMBOL_GPL(i915_read_mch_val);
5094
5095 /**
5096 * i915_gpu_raise - raise GPU frequency limit
5097 *
5098 * Raise the limit; IPS indicates we have thermal headroom.
5099 */
5100 bool i915_gpu_raise(void)
5101 {
5102 struct drm_i915_private *dev_priv;
5103 bool ret = true;
5104
5105 spin_lock_irq(&mchdev_lock);
5106 if (!i915_mch_dev) {
5107 ret = false;
5108 goto out_unlock;
5109 }
5110 dev_priv = i915_mch_dev;
5111
5112 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
5113 dev_priv->ips.max_delay--;
5114
5115 out_unlock:
5116 spin_unlock_irq(&mchdev_lock);
5117
5118 return ret;
5119 }
5120 EXPORT_SYMBOL_GPL(i915_gpu_raise);
5121
5122 /**
5123 * i915_gpu_lower - lower GPU frequency limit
5124 *
5125 * IPS indicates we're close to a thermal limit, so throttle back the GPU
5126 * frequency maximum.
5127 */
5128 bool i915_gpu_lower(void)
5129 {
5130 struct drm_i915_private *dev_priv;
5131 bool ret = true;
5132
5133 spin_lock_irq(&mchdev_lock);
5134 if (!i915_mch_dev) {
5135 ret = false;
5136 goto out_unlock;
5137 }
5138 dev_priv = i915_mch_dev;
5139
5140 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
5141 dev_priv->ips.max_delay++;
5142
5143 out_unlock:
5144 spin_unlock_irq(&mchdev_lock);
5145
5146 return ret;
5147 }
5148 EXPORT_SYMBOL_GPL(i915_gpu_lower);
5149
5150 /**
5151 * i915_gpu_busy - indicate GPU business to IPS
5152 *
5153 * Tell the IPS driver whether or not the GPU is busy.
5154 */
5155 bool i915_gpu_busy(void)
5156 {
5157 struct drm_i915_private *dev_priv;
5158 struct intel_engine_cs *ring;
5159 bool ret = false;
5160 int i;
5161
5162 spin_lock_irq(&mchdev_lock);
5163 if (!i915_mch_dev)
5164 goto out_unlock;
5165 dev_priv = i915_mch_dev;
5166
5167 for_each_ring(ring, dev_priv, i)
5168 ret |= !list_empty(&ring->request_list);
5169
5170 out_unlock:
5171 spin_unlock_irq(&mchdev_lock);
5172
5173 return ret;
5174 }
5175 EXPORT_SYMBOL_GPL(i915_gpu_busy);
5176
5177 /**
5178 * i915_gpu_turbo_disable - disable graphics turbo
5179 *
5180 * Disable graphics turbo by resetting the max frequency and setting the
5181 * current frequency to the default.
5182 */
5183 bool i915_gpu_turbo_disable(void)
5184 {
5185 struct drm_i915_private *dev_priv;
5186 bool ret = true;
5187
5188 spin_lock_irq(&mchdev_lock);
5189 if (!i915_mch_dev) {
5190 ret = false;
5191 goto out_unlock;
5192 }
5193 dev_priv = i915_mch_dev;
5194
5195 dev_priv->ips.max_delay = dev_priv->ips.fstart;
5196
5197 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
5198 ret = false;
5199
5200 out_unlock:
5201 spin_unlock_irq(&mchdev_lock);
5202
5203 return ret;
5204 }
5205 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
5206
5207 /**
5208 * Tells the intel_ips driver that the i915 driver is now loaded, if
5209 * IPS got loaded first.
5210 *
5211 * This awkward dance is so that neither module has to depend on the
5212 * other in order for IPS to do the appropriate communication of
5213 * GPU turbo limits to i915.
5214 */
5215 static void
5216 ips_ping_for_i915_load(void)
5217 {
5218 void (*link)(void);
5219
5220 link = symbol_get(ips_link_to_i915_driver);
5221 if (link) {
5222 link();
5223 symbol_put(ips_link_to_i915_driver);
5224 }
5225 }
5226
5227 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
5228 {
5229 /* We only register the i915 ips part with intel-ips once everything is
5230 * set up, to avoid intel-ips sneaking in and reading bogus values. */
5231 spin_lock_irq(&mchdev_lock);
5232 i915_mch_dev = dev_priv;
5233 spin_unlock_irq(&mchdev_lock);
5234
5235 ips_ping_for_i915_load();
5236 }
5237
5238 void intel_gpu_ips_teardown(void)
5239 {
5240 spin_lock_irq(&mchdev_lock);
5241 i915_mch_dev = NULL;
5242 spin_unlock_irq(&mchdev_lock);
5243 }
5244
5245 static void intel_init_emon(struct drm_device *dev)
5246 {
5247 struct drm_i915_private *dev_priv = dev->dev_private;
5248 u32 lcfuse;
5249 u8 pxw[16];
5250 int i;
5251
5252 /* Disable to program */
5253 I915_WRITE(ECR, 0);
5254 POSTING_READ(ECR);
5255
5256 /* Program energy weights for various events */
5257 I915_WRITE(SDEW, 0x15040d00);
5258 I915_WRITE(CSIEW0, 0x007f0000);
5259 I915_WRITE(CSIEW1, 0x1e220004);
5260 I915_WRITE(CSIEW2, 0x04000004);
5261
5262 for (i = 0; i < 5; i++)
5263 I915_WRITE(PEW + (i * 4), 0);
5264 for (i = 0; i < 3; i++)
5265 I915_WRITE(DEW + (i * 4), 0);
5266
5267 /* Program P-state weights to account for frequency power adjustment */
5268 for (i = 0; i < 16; i++) {
5269 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
5270 unsigned long freq = intel_pxfreq(pxvidfreq);
5271 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5272 PXVFREQ_PX_SHIFT;
5273 unsigned long val;
5274
5275 val = vid * vid;
5276 val *= (freq / 1000);
5277 val *= 255;
5278 val /= (127*127*900);
5279 if (val > 0xff)
5280 DRM_ERROR("bad pxval: %ld\n", val);
5281 pxw[i] = val;
5282 }
5283 /* Render standby states get 0 weight */
5284 pxw[14] = 0;
5285 pxw[15] = 0;
5286
5287 for (i = 0; i < 4; i++) {
5288 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5289 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
5290 I915_WRITE(PXW + (i * 4), val);
5291 }
5292
5293 /* Adjust magic regs to magic values (more experimental results) */
5294 I915_WRITE(OGW0, 0);
5295 I915_WRITE(OGW1, 0);
5296 I915_WRITE(EG0, 0x00007f00);
5297 I915_WRITE(EG1, 0x0000000e);
5298 I915_WRITE(EG2, 0x000e0000);
5299 I915_WRITE(EG3, 0x68000300);
5300 I915_WRITE(EG4, 0x42000000);
5301 I915_WRITE(EG5, 0x00140031);
5302 I915_WRITE(EG6, 0);
5303 I915_WRITE(EG7, 0);
5304
5305 for (i = 0; i < 8; i++)
5306 I915_WRITE(PXWL + (i * 4), 0);
5307
5308 /* Enable PMON + select events */
5309 I915_WRITE(ECR, 0x80000019);
5310
5311 lcfuse = I915_READ(LCFUSE02);
5312
5313 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
5314 }
5315
5316 void intel_init_gt_powersave(struct drm_device *dev)
5317 {
5318 i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
5319
5320 if (IS_CHERRYVIEW(dev))
5321 cherryview_init_gt_powersave(dev);
5322 else if (IS_VALLEYVIEW(dev))
5323 valleyview_init_gt_powersave(dev);
5324 }
5325
5326 void intel_cleanup_gt_powersave(struct drm_device *dev)
5327 {
5328 if (IS_CHERRYVIEW(dev))
5329 return;
5330 else if (IS_VALLEYVIEW(dev))
5331 valleyview_cleanup_gt_powersave(dev);
5332 }
5333
5334 /**
5335 * intel_suspend_gt_powersave - suspend PM work and helper threads
5336 * @dev: drm device
5337 *
5338 * We don't want to disable RC6 or other features here, we just want
5339 * to make sure any work we've queued has finished and won't bother
5340 * us while we're suspended.
5341 */
5342 void intel_suspend_gt_powersave(struct drm_device *dev)
5343 {
5344 struct drm_i915_private *dev_priv = dev->dev_private;
5345
5346 /* Interrupts should be disabled already to avoid re-arming. */
5347 WARN_ON(intel_irqs_enabled(dev_priv));
5348
5349 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
5350
5351 cancel_work_sync(&dev_priv->rps.work);
5352
5353 /* Force GPU to min freq during suspend */
5354 gen6_rps_idle(dev_priv);
5355 }
5356
5357 void intel_disable_gt_powersave(struct drm_device *dev)
5358 {
5359 struct drm_i915_private *dev_priv = dev->dev_private;
5360
5361 /* Interrupts should be disabled already to avoid re-arming. */
5362 WARN_ON(intel_irqs_enabled(dev_priv));
5363
5364 if (IS_IRONLAKE_M(dev)) {
5365 ironlake_disable_drps(dev);
5366 ironlake_disable_rc6(dev);
5367 } else if (INTEL_INFO(dev)->gen >= 6) {
5368 intel_suspend_gt_powersave(dev);
5369
5370 mutex_lock(&dev_priv->rps.hw_lock);
5371 if (IS_CHERRYVIEW(dev))
5372 cherryview_disable_rps(dev);
5373 else if (IS_VALLEYVIEW(dev))
5374 valleyview_disable_rps(dev);
5375 else
5376 gen6_disable_rps(dev);
5377 dev_priv->rps.enabled = false;
5378 mutex_unlock(&dev_priv->rps.hw_lock);
5379 }
5380 }
5381
5382 static void intel_gen6_powersave_work(struct work_struct *work)
5383 {
5384 struct drm_i915_private *dev_priv =
5385 container_of(work, struct drm_i915_private,
5386 rps.delayed_resume_work.work);
5387 struct drm_device *dev = dev_priv->dev;
5388
5389 dev_priv->rps.is_bdw_sw_turbo = false;
5390
5391 mutex_lock(&dev_priv->rps.hw_lock);
5392
5393 if (IS_CHERRYVIEW(dev)) {
5394 cherryview_enable_rps(dev);
5395 } else if (IS_VALLEYVIEW(dev)) {
5396 valleyview_enable_rps(dev);
5397 } else if (IS_BROADWELL(dev)) {
5398 gen8_enable_rps(dev);
5399 __gen6_update_ring_freq(dev);
5400 } else {
5401 gen6_enable_rps(dev);
5402 __gen6_update_ring_freq(dev);
5403 }
5404 dev_priv->rps.enabled = true;
5405 mutex_unlock(&dev_priv->rps.hw_lock);
5406
5407 intel_runtime_pm_put(dev_priv);
5408 }
5409
5410 void intel_enable_gt_powersave(struct drm_device *dev)
5411 {
5412 struct drm_i915_private *dev_priv = dev->dev_private;
5413
5414 if (IS_IRONLAKE_M(dev)) {
5415 mutex_lock(&dev->struct_mutex);
5416 ironlake_enable_drps(dev);
5417 ironlake_enable_rc6(dev);
5418 intel_init_emon(dev);
5419 mutex_unlock(&dev->struct_mutex);
5420 } else if (INTEL_INFO(dev)->gen >= 6) {
5421 /*
5422 * PCU communication is slow and this doesn't need to be
5423 * done at any specific time, so do this out of our fast path
5424 * to make resume and init faster.
5425 *
5426 * We depend on the HW RC6 power context save/restore
5427 * mechanism when entering D3 through runtime PM suspend. So
5428 * disable RPM until RPS/RC6 is properly setup. We can only
5429 * get here via the driver load/system resume/runtime resume
5430 * paths, so the _noresume version is enough (and in case of
5431 * runtime resume it's necessary).
5432 */
5433 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
5434 round_jiffies_up_relative(HZ)))
5435 intel_runtime_pm_get_noresume(dev_priv);
5436 }
5437 }
5438
5439 void intel_reset_gt_powersave(struct drm_device *dev)
5440 {
5441 struct drm_i915_private *dev_priv = dev->dev_private;
5442
5443 dev_priv->rps.enabled = false;
5444 intel_enable_gt_powersave(dev);
5445 }
5446
5447 static void ibx_init_clock_gating(struct drm_device *dev)
5448 {
5449 struct drm_i915_private *dev_priv = dev->dev_private;
5450
5451 /*
5452 * On Ibex Peak and Cougar Point, we need to disable clock
5453 * gating for the panel power sequencer or it will fail to
5454 * start up when no ports are active.
5455 */
5456 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
5457 }
5458
5459 static void g4x_disable_trickle_feed(struct drm_device *dev)
5460 {
5461 struct drm_i915_private *dev_priv = dev->dev_private;
5462 int pipe;
5463
5464 for_each_pipe(dev_priv, pipe) {
5465 I915_WRITE(DSPCNTR(pipe),
5466 I915_READ(DSPCNTR(pipe)) |
5467 DISPPLANE_TRICKLE_FEED_DISABLE);
5468 intel_flush_primary_plane(dev_priv, pipe);
5469 }
5470 }
5471
5472 static void ilk_init_lp_watermarks(struct drm_device *dev)
5473 {
5474 struct drm_i915_private *dev_priv = dev->dev_private;
5475
5476 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
5477 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
5478 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
5479
5480 /*
5481 * Don't touch WM1S_LP_EN here.
5482 * Doing so could cause underruns.
5483 */
5484 }
5485
5486 static void ironlake_init_clock_gating(struct drm_device *dev)
5487 {
5488 struct drm_i915_private *dev_priv = dev->dev_private;
5489 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
5490
5491 /*
5492 * Required for FBC
5493 * WaFbcDisableDpfcClockGating:ilk
5494 */
5495 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
5496 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
5497 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
5498
5499 I915_WRITE(PCH_3DCGDIS0,
5500 MARIUNIT_CLOCK_GATE_DISABLE |
5501 SVSMUNIT_CLOCK_GATE_DISABLE);
5502 I915_WRITE(PCH_3DCGDIS1,
5503 VFMUNIT_CLOCK_GATE_DISABLE);
5504
5505 /*
5506 * According to the spec the following bits should be set in
5507 * order to enable memory self-refresh
5508 * The bit 22/21 of 0x42004
5509 * The bit 5 of 0x42020
5510 * The bit 15 of 0x45000
5511 */
5512 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5513 (I915_READ(ILK_DISPLAY_CHICKEN2) |
5514 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
5515 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
5516 I915_WRITE(DISP_ARB_CTL,
5517 (I915_READ(DISP_ARB_CTL) |
5518 DISP_FBC_WM_DIS));
5519
5520 ilk_init_lp_watermarks(dev);
5521
5522 /*
5523 * Based on the document from hardware guys the following bits
5524 * should be set unconditionally in order to enable FBC.
5525 * The bit 22 of 0x42000
5526 * The bit 22 of 0x42004
5527 * The bit 7,8,9 of 0x42020.
5528 */
5529 if (IS_IRONLAKE_M(dev)) {
5530 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
5531 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5532 I915_READ(ILK_DISPLAY_CHICKEN1) |
5533 ILK_FBCQ_DIS);
5534 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5535 I915_READ(ILK_DISPLAY_CHICKEN2) |
5536 ILK_DPARB_GATE);
5537 }
5538
5539 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
5540
5541 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5542 I915_READ(ILK_DISPLAY_CHICKEN2) |
5543 ILK_ELPIN_409_SELECT);
5544 I915_WRITE(_3D_CHICKEN2,
5545 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
5546 _3D_CHICKEN2_WM_READ_PIPELINED);
5547
5548 /* WaDisableRenderCachePipelinedFlush:ilk */
5549 I915_WRITE(CACHE_MODE_0,
5550 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
5551
5552 /* WaDisable_RenderCache_OperationalFlush:ilk */
5553 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5554
5555 g4x_disable_trickle_feed(dev);
5556
5557 ibx_init_clock_gating(dev);
5558 }
5559
5560 static void cpt_init_clock_gating(struct drm_device *dev)
5561 {
5562 struct drm_i915_private *dev_priv = dev->dev_private;
5563 int pipe;
5564 uint32_t val;
5565
5566 /*
5567 * On Ibex Peak and Cougar Point, we need to disable clock
5568 * gating for the panel power sequencer or it will fail to
5569 * start up when no ports are active.
5570 */
5571 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
5572 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
5573 PCH_CPUNIT_CLOCK_GATE_DISABLE);
5574 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
5575 DPLS_EDP_PPS_FIX_DIS);
5576 /* The below fixes the weird display corruption, a few pixels shifted
5577 * downward, on (only) LVDS of some HP laptops with IVY.
5578 */
5579 for_each_pipe(dev_priv, pipe) {
5580 val = I915_READ(TRANS_CHICKEN2(pipe));
5581 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
5582 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
5583 if (dev_priv->vbt.fdi_rx_polarity_inverted)
5584 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
5585 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
5586 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
5587 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
5588 I915_WRITE(TRANS_CHICKEN2(pipe), val);
5589 }
5590 /* WADP0ClockGatingDisable */
5591 for_each_pipe(dev_priv, pipe) {
5592 I915_WRITE(TRANS_CHICKEN1(pipe),
5593 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
5594 }
5595 }
5596
5597 static void gen6_check_mch_setup(struct drm_device *dev)
5598 {
5599 struct drm_i915_private *dev_priv = dev->dev_private;
5600 uint32_t tmp;
5601
5602 tmp = I915_READ(MCH_SSKPD);
5603 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
5604 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
5605 tmp);
5606 }
5607
5608 static void gen6_init_clock_gating(struct drm_device *dev)
5609 {
5610 struct drm_i915_private *dev_priv = dev->dev_private;
5611 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
5612
5613 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
5614
5615 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5616 I915_READ(ILK_DISPLAY_CHICKEN2) |
5617 ILK_ELPIN_409_SELECT);
5618
5619 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
5620 I915_WRITE(_3D_CHICKEN,
5621 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
5622
5623 /* WaSetupGtModeTdRowDispatch:snb */
5624 if (IS_SNB_GT1(dev))
5625 I915_WRITE(GEN6_GT_MODE,
5626 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
5627
5628 /* WaDisable_RenderCache_OperationalFlush:snb */
5629 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5630
5631 /*
5632 * BSpec recoomends 8x4 when MSAA is used,
5633 * however in practice 16x4 seems fastest.
5634 *
5635 * Note that PS/WM thread counts depend on the WIZ hashing
5636 * disable bit, which we don't touch here, but it's good
5637 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5638 */
5639 I915_WRITE(GEN6_GT_MODE,
5640 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5641
5642 ilk_init_lp_watermarks(dev);
5643
5644 I915_WRITE(CACHE_MODE_0,
5645 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
5646
5647 I915_WRITE(GEN6_UCGCTL1,
5648 I915_READ(GEN6_UCGCTL1) |
5649 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
5650 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
5651
5652 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5653 * gating disable must be set. Failure to set it results in
5654 * flickering pixels due to Z write ordering failures after
5655 * some amount of runtime in the Mesa "fire" demo, and Unigine
5656 * Sanctuary and Tropics, and apparently anything else with
5657 * alpha test or pixel discard.
5658 *
5659 * According to the spec, bit 11 (RCCUNIT) must also be set,
5660 * but we didn't debug actual testcases to find it out.
5661 *
5662 * WaDisableRCCUnitClockGating:snb
5663 * WaDisableRCPBUnitClockGating:snb
5664 */
5665 I915_WRITE(GEN6_UCGCTL2,
5666 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
5667 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5668
5669 /* WaStripsFansDisableFastClipPerformanceFix:snb */
5670 I915_WRITE(_3D_CHICKEN3,
5671 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
5672
5673 /*
5674 * Bspec says:
5675 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
5676 * 3DSTATE_SF number of SF output attributes is more than 16."
5677 */
5678 I915_WRITE(_3D_CHICKEN3,
5679 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
5680
5681 /*
5682 * According to the spec the following bits should be
5683 * set in order to enable memory self-refresh and fbc:
5684 * The bit21 and bit22 of 0x42000
5685 * The bit21 and bit22 of 0x42004
5686 * The bit5 and bit7 of 0x42020
5687 * The bit14 of 0x70180
5688 * The bit14 of 0x71180
5689 *
5690 * WaFbcAsynchFlipDisableFbcQueue:snb
5691 */
5692 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5693 I915_READ(ILK_DISPLAY_CHICKEN1) |
5694 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
5695 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5696 I915_READ(ILK_DISPLAY_CHICKEN2) |
5697 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
5698 I915_WRITE(ILK_DSPCLK_GATE_D,
5699 I915_READ(ILK_DSPCLK_GATE_D) |
5700 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
5701 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
5702
5703 g4x_disable_trickle_feed(dev);
5704
5705 cpt_init_clock_gating(dev);
5706
5707 gen6_check_mch_setup(dev);
5708 }
5709
5710 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
5711 {
5712 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
5713
5714 /*
5715 * WaVSThreadDispatchOverride:ivb,vlv
5716 *
5717 * This actually overrides the dispatch
5718 * mode for all thread types.
5719 */
5720 reg &= ~GEN7_FF_SCHED_MASK;
5721 reg |= GEN7_FF_TS_SCHED_HW;
5722 reg |= GEN7_FF_VS_SCHED_HW;
5723 reg |= GEN7_FF_DS_SCHED_HW;
5724
5725 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
5726 }
5727
5728 static void lpt_init_clock_gating(struct drm_device *dev)
5729 {
5730 struct drm_i915_private *dev_priv = dev->dev_private;
5731
5732 /*
5733 * TODO: this bit should only be enabled when really needed, then
5734 * disabled when not needed anymore in order to save power.
5735 */
5736 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
5737 I915_WRITE(SOUTH_DSPCLK_GATE_D,
5738 I915_READ(SOUTH_DSPCLK_GATE_D) |
5739 PCH_LP_PARTITION_LEVEL_DISABLE);
5740
5741 /* WADPOClockGatingDisable:hsw */
5742 I915_WRITE(_TRANSA_CHICKEN1,
5743 I915_READ(_TRANSA_CHICKEN1) |
5744 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
5745 }
5746
5747 static void lpt_suspend_hw(struct drm_device *dev)
5748 {
5749 struct drm_i915_private *dev_priv = dev->dev_private;
5750
5751 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
5752 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
5753
5754 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
5755 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
5756 }
5757 }
5758
5759 static void broadwell_init_clock_gating(struct drm_device *dev)
5760 {
5761 struct drm_i915_private *dev_priv = dev->dev_private;
5762 enum pipe pipe;
5763
5764 I915_WRITE(WM3_LP_ILK, 0);
5765 I915_WRITE(WM2_LP_ILK, 0);
5766 I915_WRITE(WM1_LP_ILK, 0);
5767
5768 /* FIXME(BDW): Check all the w/a, some might only apply to
5769 * pre-production hw. */
5770
5771
5772 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE));
5773
5774 I915_WRITE(_3D_CHICKEN3,
5775 _MASKED_BIT_ENABLE(_3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2)));
5776
5777
5778 /* WaSwitchSolVfFArbitrationPriority:bdw */
5779 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
5780
5781 /* WaPsrDPAMaskVBlankInSRD:bdw */
5782 I915_WRITE(CHICKEN_PAR1_1,
5783 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
5784
5785 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
5786 for_each_pipe(dev_priv, pipe) {
5787 I915_WRITE(CHICKEN_PIPESL_1(pipe),
5788 I915_READ(CHICKEN_PIPESL_1(pipe)) |
5789 BDW_DPRS_MASK_VBLANK_SRD);
5790 }
5791
5792 /* WaVSRefCountFullforceMissDisable:bdw */
5793 /* WaDSRefCountFullforceMissDisable:bdw */
5794 I915_WRITE(GEN7_FF_THREAD_MODE,
5795 I915_READ(GEN7_FF_THREAD_MODE) &
5796 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
5797
5798 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
5799 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
5800
5801 /* WaDisableSDEUnitClockGating:bdw */
5802 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
5803 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5804
5805 lpt_init_clock_gating(dev);
5806 }
5807
5808 static void haswell_init_clock_gating(struct drm_device *dev)
5809 {
5810 struct drm_i915_private *dev_priv = dev->dev_private;
5811
5812 ilk_init_lp_watermarks(dev);
5813
5814 /* L3 caching of data atomics doesn't work -- disable it. */
5815 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
5816 I915_WRITE(HSW_ROW_CHICKEN3,
5817 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
5818
5819 /* This is required by WaCatErrorRejectionIssue:hsw */
5820 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5821 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5822 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5823
5824 /* WaVSRefCountFullforceMissDisable:hsw */
5825 I915_WRITE(GEN7_FF_THREAD_MODE,
5826 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
5827
5828 /* WaDisable_RenderCache_OperationalFlush:hsw */
5829 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5830
5831 /* enable HiZ Raw Stall Optimization */
5832 I915_WRITE(CACHE_MODE_0_GEN7,
5833 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
5834
5835 /* WaDisable4x2SubspanOptimization:hsw */
5836 I915_WRITE(CACHE_MODE_1,
5837 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5838
5839 /*
5840 * BSpec recommends 8x4 when MSAA is used,
5841 * however in practice 16x4 seems fastest.
5842 *
5843 * Note that PS/WM thread counts depend on the WIZ hashing
5844 * disable bit, which we don't touch here, but it's good
5845 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5846 */
5847 I915_WRITE(GEN7_GT_MODE,
5848 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5849
5850 /* WaSwitchSolVfFArbitrationPriority:hsw */
5851 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
5852
5853 /* WaRsPkgCStateDisplayPMReq:hsw */
5854 I915_WRITE(CHICKEN_PAR1_1,
5855 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
5856
5857 lpt_init_clock_gating(dev);
5858 }
5859
5860 static void ivybridge_init_clock_gating(struct drm_device *dev)
5861 {
5862 struct drm_i915_private *dev_priv = dev->dev_private;
5863 uint32_t snpcr;
5864
5865 ilk_init_lp_watermarks(dev);
5866
5867 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
5868
5869 /* WaDisableEarlyCull:ivb */
5870 I915_WRITE(_3D_CHICKEN3,
5871 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5872
5873 /* WaDisableBackToBackFlipFix:ivb */
5874 I915_WRITE(IVB_CHICKEN3,
5875 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5876 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5877
5878 /* WaDisablePSDDualDispatchEnable:ivb */
5879 if (IS_IVB_GT1(dev))
5880 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5881 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5882
5883 /* WaDisable_RenderCache_OperationalFlush:ivb */
5884 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5885
5886 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
5887 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5888 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5889
5890 /* WaApplyL3ControlAndL3ChickenMode:ivb */
5891 I915_WRITE(GEN7_L3CNTLREG1,
5892 GEN7_WA_FOR_GEN7_L3_CONTROL);
5893 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
5894 GEN7_WA_L3_CHICKEN_MODE);
5895 if (IS_IVB_GT1(dev))
5896 I915_WRITE(GEN7_ROW_CHICKEN2,
5897 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5898 else {
5899 /* must write both registers */
5900 I915_WRITE(GEN7_ROW_CHICKEN2,
5901 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5902 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
5903 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5904 }
5905
5906 /* WaForceL3Serialization:ivb */
5907 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5908 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5909
5910 /*
5911 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5912 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
5913 */
5914 I915_WRITE(GEN6_UCGCTL2,
5915 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
5916
5917 /* This is required by WaCatErrorRejectionIssue:ivb */
5918 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5919 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5920 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5921
5922 g4x_disable_trickle_feed(dev);
5923
5924 gen7_setup_fixed_func_scheduler(dev_priv);
5925
5926 if (0) { /* causes HiZ corruption on ivb:gt1 */
5927 /* enable HiZ Raw Stall Optimization */
5928 I915_WRITE(CACHE_MODE_0_GEN7,
5929 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
5930 }
5931
5932 /* WaDisable4x2SubspanOptimization:ivb */
5933 I915_WRITE(CACHE_MODE_1,
5934 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5935
5936 /*
5937 * BSpec recommends 8x4 when MSAA is used,
5938 * however in practice 16x4 seems fastest.
5939 *
5940 * Note that PS/WM thread counts depend on the WIZ hashing
5941 * disable bit, which we don't touch here, but it's good
5942 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5943 */
5944 I915_WRITE(GEN7_GT_MODE,
5945 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5946
5947 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5948 snpcr &= ~GEN6_MBC_SNPCR_MASK;
5949 snpcr |= GEN6_MBC_SNPCR_MED;
5950 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5951
5952 if (!HAS_PCH_NOP(dev))
5953 cpt_init_clock_gating(dev);
5954
5955 gen6_check_mch_setup(dev);
5956 }
5957
5958 static void valleyview_init_clock_gating(struct drm_device *dev)
5959 {
5960 struct drm_i915_private *dev_priv = dev->dev_private;
5961
5962 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
5963
5964 /* WaDisableEarlyCull:vlv */
5965 I915_WRITE(_3D_CHICKEN3,
5966 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5967
5968 /* WaDisableBackToBackFlipFix:vlv */
5969 I915_WRITE(IVB_CHICKEN3,
5970 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5971 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5972
5973 /* WaPsdDispatchEnable:vlv */
5974 /* WaDisablePSDDualDispatchEnable:vlv */
5975 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5976 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
5977 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5978
5979 /* WaDisable_RenderCache_OperationalFlush:vlv */
5980 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5981
5982 /* WaForceL3Serialization:vlv */
5983 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5984 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5985
5986 /* WaDisableDopClockGating:vlv */
5987 I915_WRITE(GEN7_ROW_CHICKEN2,
5988 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5989
5990 /* This is required by WaCatErrorRejectionIssue:vlv */
5991 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5992 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5993 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5994
5995 gen7_setup_fixed_func_scheduler(dev_priv);
5996
5997 /*
5998 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5999 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
6000 */
6001 I915_WRITE(GEN6_UCGCTL2,
6002 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
6003
6004 /* WaDisableL3Bank2xClockGate:vlv
6005 * Disabling L3 clock gating- MMIO 940c[25] = 1
6006 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
6007 I915_WRITE(GEN7_UCGCTL4,
6008 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
6009
6010 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6011
6012 /*
6013 * BSpec says this must be set, even though
6014 * WaDisable4x2SubspanOptimization isn't listed for VLV.
6015 */
6016 I915_WRITE(CACHE_MODE_1,
6017 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6018
6019 /*
6020 * WaIncreaseL3CreditsForVLVB0:vlv
6021 * This is the hardware default actually.
6022 */
6023 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
6024
6025 /*
6026 * WaDisableVLVClockGating_VBIIssue:vlv
6027 * Disable clock gating on th GCFG unit to prevent a delay
6028 * in the reporting of vblank events.
6029 */
6030 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6031 }
6032
6033 static void cherryview_init_clock_gating(struct drm_device *dev)
6034 {
6035 struct drm_i915_private *dev_priv = dev->dev_private;
6036
6037 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6038
6039 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6040
6041 /* WaVSRefCountFullforceMissDisable:chv */
6042 /* WaDSRefCountFullforceMissDisable:chv */
6043 I915_WRITE(GEN7_FF_THREAD_MODE,
6044 I915_READ(GEN7_FF_THREAD_MODE) &
6045 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
6046
6047 /* WaDisableSemaphoreAndSyncFlipWait:chv */
6048 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6049 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
6050
6051 /* WaDisableCSUnitClockGating:chv */
6052 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
6053 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6054
6055 /* WaDisableSDEUnitClockGating:chv */
6056 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6057 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6058
6059 /* WaDisableGunitClockGating:chv (pre-production hw) */
6060 I915_WRITE(VLV_GUNIT_CLOCK_GATE, I915_READ(VLV_GUNIT_CLOCK_GATE) |
6061 GINT_DIS);
6062
6063 /* WaDisableFfDopClockGating:chv (pre-production hw) */
6064 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6065 _MASKED_BIT_ENABLE(GEN8_FF_DOP_CLOCK_GATE_DISABLE));
6066
6067 /* WaDisableDopClockGating:chv (pre-production hw) */
6068 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
6069 GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
6070 }
6071
6072 static void g4x_init_clock_gating(struct drm_device *dev)
6073 {
6074 struct drm_i915_private *dev_priv = dev->dev_private;
6075 uint32_t dspclk_gate;
6076
6077 I915_WRITE(RENCLK_GATE_D1, 0);
6078 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
6079 GS_UNIT_CLOCK_GATE_DISABLE |
6080 CL_UNIT_CLOCK_GATE_DISABLE);
6081 I915_WRITE(RAMCLK_GATE_D, 0);
6082 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
6083 OVRUNIT_CLOCK_GATE_DISABLE |
6084 OVCUNIT_CLOCK_GATE_DISABLE;
6085 if (IS_GM45(dev))
6086 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
6087 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
6088
6089 /* WaDisableRenderCachePipelinedFlush */
6090 I915_WRITE(CACHE_MODE_0,
6091 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6092
6093 /* WaDisable_RenderCache_OperationalFlush:g4x */
6094 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6095
6096 g4x_disable_trickle_feed(dev);
6097 }
6098
6099 static void crestline_init_clock_gating(struct drm_device *dev)
6100 {
6101 struct drm_i915_private *dev_priv = dev->dev_private;
6102
6103 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
6104 I915_WRITE(RENCLK_GATE_D2, 0);
6105 I915_WRITE(DSPCLK_GATE_D, 0);
6106 I915_WRITE(RAMCLK_GATE_D, 0);
6107 I915_WRITE16(DEUC, 0);
6108 I915_WRITE(MI_ARB_STATE,
6109 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6110
6111 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6112 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6113 }
6114
6115 static void broadwater_init_clock_gating(struct drm_device *dev)
6116 {
6117 struct drm_i915_private *dev_priv = dev->dev_private;
6118
6119 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
6120 I965_RCC_CLOCK_GATE_DISABLE |
6121 I965_RCPB_CLOCK_GATE_DISABLE |
6122 I965_ISC_CLOCK_GATE_DISABLE |
6123 I965_FBC_CLOCK_GATE_DISABLE);
6124 I915_WRITE(RENCLK_GATE_D2, 0);
6125 I915_WRITE(MI_ARB_STATE,
6126 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6127
6128 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6129 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6130 }
6131
6132 static void gen3_init_clock_gating(struct drm_device *dev)
6133 {
6134 struct drm_i915_private *dev_priv = dev->dev_private;
6135 u32 dstate = I915_READ(D_STATE);
6136
6137 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
6138 DSTATE_DOT_CLOCK_GATING;
6139 I915_WRITE(D_STATE, dstate);
6140
6141 if (IS_PINEVIEW(dev))
6142 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
6143
6144 /* IIR "flip pending" means done if this bit is set */
6145 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
6146
6147 /* interrupts should cause a wake up from C3 */
6148 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
6149
6150 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
6151 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
6152
6153 I915_WRITE(MI_ARB_STATE,
6154 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6155 }
6156
6157 static void i85x_init_clock_gating(struct drm_device *dev)
6158 {
6159 struct drm_i915_private *dev_priv = dev->dev_private;
6160
6161 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
6162
6163 /* interrupts should cause a wake up from C3 */
6164 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
6165 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
6166
6167 I915_WRITE(MEM_MODE,
6168 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
6169 }
6170
6171 static void i830_init_clock_gating(struct drm_device *dev)
6172 {
6173 struct drm_i915_private *dev_priv = dev->dev_private;
6174
6175 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
6176
6177 I915_WRITE(MEM_MODE,
6178 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
6179 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
6180 }
6181
6182 void intel_init_clock_gating(struct drm_device *dev)
6183 {
6184 struct drm_i915_private *dev_priv = dev->dev_private;
6185
6186 dev_priv->display.init_clock_gating(dev);
6187 }
6188
6189 void intel_suspend_hw(struct drm_device *dev)
6190 {
6191 if (HAS_PCH_LPT(dev))
6192 lpt_suspend_hw(dev);
6193 }
6194
6195 #define for_each_power_well(i, power_well, domain_mask, power_domains) \
6196 for (i = 0; \
6197 i < (power_domains)->power_well_count && \
6198 ((power_well) = &(power_domains)->power_wells[i]); \
6199 i++) \
6200 if ((power_well)->domains & (domain_mask))
6201
6202 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
6203 for (i = (power_domains)->power_well_count - 1; \
6204 i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
6205 i--) \
6206 if ((power_well)->domains & (domain_mask))
6207
6208 /**
6209 * We should only use the power well if we explicitly asked the hardware to
6210 * enable it, so check if it's enabled and also check if we've requested it to
6211 * be enabled.
6212 */
6213 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
6214 struct i915_power_well *power_well)
6215 {
6216 return I915_READ(HSW_PWR_WELL_DRIVER) ==
6217 (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
6218 }
6219
6220 bool intel_display_power_enabled_unlocked(struct drm_i915_private *dev_priv,
6221 enum intel_display_power_domain domain)
6222 {
6223 struct i915_power_domains *power_domains;
6224 struct i915_power_well *power_well;
6225 bool is_enabled;
6226 int i;
6227
6228 if (dev_priv->pm.suspended)
6229 return false;
6230
6231 power_domains = &dev_priv->power_domains;
6232
6233 is_enabled = true;
6234
6235 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
6236 if (power_well->always_on)
6237 continue;
6238
6239 if (!power_well->hw_enabled) {
6240 is_enabled = false;
6241 break;
6242 }
6243 }
6244
6245 return is_enabled;
6246 }
6247
6248 bool intel_display_power_enabled(struct drm_i915_private *dev_priv,
6249 enum intel_display_power_domain domain)
6250 {
6251 struct i915_power_domains *power_domains;
6252 bool ret;
6253
6254 power_domains = &dev_priv->power_domains;
6255
6256 mutex_lock(&power_domains->lock);
6257 ret = intel_display_power_enabled_unlocked(dev_priv, domain);
6258 mutex_unlock(&power_domains->lock);
6259
6260 return ret;
6261 }
6262
6263 /*
6264 * Starting with Haswell, we have a "Power Down Well" that can be turned off
6265 * when not needed anymore. We have 4 registers that can request the power well
6266 * to be enabled, and it will only be disabled if none of the registers is
6267 * requesting it to be enabled.
6268 */
6269 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
6270 {
6271 struct drm_device *dev = dev_priv->dev;
6272
6273 /*
6274 * After we re-enable the power well, if we touch VGA register 0x3d5
6275 * we'll get unclaimed register interrupts. This stops after we write
6276 * anything to the VGA MSR register. The vgacon module uses this
6277 * register all the time, so if we unbind our driver and, as a
6278 * consequence, bind vgacon, we'll get stuck in an infinite loop at
6279 * console_unlock(). So make here we touch the VGA MSR register, making
6280 * sure vgacon can keep working normally without triggering interrupts
6281 * and error messages.
6282 */
6283 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
6284 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
6285 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
6286
6287 if (IS_BROADWELL(dev))
6288 gen8_irq_power_well_post_enable(dev_priv);
6289 }
6290
6291 static void hsw_set_power_well(struct drm_i915_private *dev_priv,
6292 struct i915_power_well *power_well, bool enable)
6293 {
6294 bool is_enabled, enable_requested;
6295 uint32_t tmp;
6296
6297 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
6298 is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
6299 enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
6300
6301 if (enable) {
6302 if (!enable_requested)
6303 I915_WRITE(HSW_PWR_WELL_DRIVER,
6304 HSW_PWR_WELL_ENABLE_REQUEST);
6305
6306 if (!is_enabled) {
6307 DRM_DEBUG_KMS("Enabling power well\n");
6308 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
6309 HSW_PWR_WELL_STATE_ENABLED), 20))
6310 DRM_ERROR("Timeout enabling power well\n");
6311 }
6312
6313 hsw_power_well_post_enable(dev_priv);
6314 } else {
6315 if (enable_requested) {
6316 I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
6317 POSTING_READ(HSW_PWR_WELL_DRIVER);
6318 DRM_DEBUG_KMS("Requesting to disable the power well\n");
6319 }
6320 }
6321 }
6322
6323 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
6324 struct i915_power_well *power_well)
6325 {
6326 hsw_set_power_well(dev_priv, power_well, power_well->count > 0);
6327
6328 /*
6329 * We're taking over the BIOS, so clear any requests made by it since
6330 * the driver is in charge now.
6331 */
6332 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
6333 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
6334 }
6335
6336 static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
6337 struct i915_power_well *power_well)
6338 {
6339 hsw_set_power_well(dev_priv, power_well, true);
6340 }
6341
6342 static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
6343 struct i915_power_well *power_well)
6344 {
6345 hsw_set_power_well(dev_priv, power_well, false);
6346 }
6347
6348 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
6349 struct i915_power_well *power_well)
6350 {
6351 }
6352
6353 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
6354 struct i915_power_well *power_well)
6355 {
6356 return true;
6357 }
6358
6359 static void vlv_set_power_well(struct drm_i915_private *dev_priv,
6360 struct i915_power_well *power_well, bool enable)
6361 {
6362 enum punit_power_well power_well_id = power_well->data;
6363 u32 mask;
6364 u32 state;
6365 u32 ctrl;
6366
6367 mask = PUNIT_PWRGT_MASK(power_well_id);
6368 state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) :
6369 PUNIT_PWRGT_PWR_GATE(power_well_id);
6370
6371 mutex_lock(&dev_priv->rps.hw_lock);
6372
6373 #define COND \
6374 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
6375
6376 if (COND)
6377 goto out;
6378
6379 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
6380 ctrl &= ~mask;
6381 ctrl |= state;
6382 vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
6383
6384 if (wait_for(COND, 100))
6385 DRM_ERROR("timout setting power well state %08x (%08x)\n",
6386 state,
6387 vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
6388
6389 #undef COND
6390
6391 out:
6392 mutex_unlock(&dev_priv->rps.hw_lock);
6393 }
6394
6395 static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv,
6396 struct i915_power_well *power_well)
6397 {
6398 vlv_set_power_well(dev_priv, power_well, power_well->count > 0);
6399 }
6400
6401 static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
6402 struct i915_power_well *power_well)
6403 {
6404 vlv_set_power_well(dev_priv, power_well, true);
6405 }
6406
6407 static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
6408 struct i915_power_well *power_well)
6409 {
6410 vlv_set_power_well(dev_priv, power_well, false);
6411 }
6412
6413 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
6414 struct i915_power_well *power_well)
6415 {
6416 int power_well_id = power_well->data;
6417 bool enabled = false;
6418 u32 mask;
6419 u32 state;
6420 u32 ctrl;
6421
6422 mask = PUNIT_PWRGT_MASK(power_well_id);
6423 ctrl = PUNIT_PWRGT_PWR_ON(power_well_id);
6424
6425 mutex_lock(&dev_priv->rps.hw_lock);
6426
6427 state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
6428 /*
6429 * We only ever set the power-on and power-gate states, anything
6430 * else is unexpected.
6431 */
6432 WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) &&
6433 state != PUNIT_PWRGT_PWR_GATE(power_well_id));
6434 if (state == ctrl)
6435 enabled = true;
6436
6437 /*
6438 * A transient state at this point would mean some unexpected party
6439 * is poking at the power controls too.
6440 */
6441 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
6442 WARN_ON(ctrl != state);
6443
6444 mutex_unlock(&dev_priv->rps.hw_lock);
6445
6446 return enabled;
6447 }
6448
6449 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
6450 struct i915_power_well *power_well)
6451 {
6452 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
6453
6454 vlv_set_power_well(dev_priv, power_well, true);
6455
6456 spin_lock_irq(&dev_priv->irq_lock);
6457 valleyview_enable_display_irqs(dev_priv);
6458 spin_unlock_irq(&dev_priv->irq_lock);
6459
6460 /*
6461 * During driver initialization/resume we can avoid restoring the
6462 * part of the HW/SW state that will be inited anyway explicitly.
6463 */
6464 if (dev_priv->power_domains.initializing)
6465 return;
6466
6467 intel_hpd_init(dev_priv->dev);
6468
6469 i915_redisable_vga_power_on(dev_priv->dev);
6470 }
6471
6472 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
6473 struct i915_power_well *power_well)
6474 {
6475 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
6476
6477 spin_lock_irq(&dev_priv->irq_lock);
6478 valleyview_disable_display_irqs(dev_priv);
6479 spin_unlock_irq(&dev_priv->irq_lock);
6480
6481 vlv_set_power_well(dev_priv, power_well, false);
6482
6483 vlv_power_sequencer_reset(dev_priv);
6484 }
6485
6486 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
6487 struct i915_power_well *power_well)
6488 {
6489 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
6490
6491 /*
6492 * Enable the CRI clock source so we can get at the
6493 * display and the reference clock for VGA
6494 * hotplug / manual detection.
6495 */
6496 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
6497 DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
6498 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
6499
6500 vlv_set_power_well(dev_priv, power_well, true);
6501
6502 /*
6503 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
6504 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
6505 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
6506 * b. The other bits such as sfr settings / modesel may all
6507 * be set to 0.
6508 *
6509 * This should only be done on init and resume from S3 with
6510 * both PLLs disabled, or we risk losing DPIO and PLL
6511 * synchronization.
6512 */
6513 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
6514 }
6515
6516 static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
6517 struct i915_power_well *power_well)
6518 {
6519 enum pipe pipe;
6520
6521 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
6522
6523 for_each_pipe(dev_priv, pipe)
6524 assert_pll_disabled(dev_priv, pipe);
6525
6526 /* Assert common reset */
6527 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST);
6528
6529 vlv_set_power_well(dev_priv, power_well, false);
6530 }
6531
6532 static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
6533 struct i915_power_well *power_well)
6534 {
6535 enum dpio_phy phy;
6536
6537 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
6538 power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
6539
6540 /*
6541 * Enable the CRI clock source so we can get at the
6542 * display and the reference clock for VGA
6543 * hotplug / manual detection.
6544 */
6545 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
6546 phy = DPIO_PHY0;
6547 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
6548 DPLL_REFA_CLK_ENABLE_VLV);
6549 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
6550 DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
6551 } else {
6552 phy = DPIO_PHY1;
6553 I915_WRITE(DPLL(PIPE_C), I915_READ(DPLL(PIPE_C)) |
6554 DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
6555 }
6556 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
6557 vlv_set_power_well(dev_priv, power_well, true);
6558
6559 /* Poll for phypwrgood signal */
6560 if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1))
6561 DRM_ERROR("Display PHY %d is not power up\n", phy);
6562
6563 I915_WRITE(DISPLAY_PHY_CONTROL, I915_READ(DISPLAY_PHY_CONTROL) |
6564 PHY_COM_LANE_RESET_DEASSERT(phy));
6565 }
6566
6567 static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
6568 struct i915_power_well *power_well)
6569 {
6570 enum dpio_phy phy;
6571
6572 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
6573 power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
6574
6575 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
6576 phy = DPIO_PHY0;
6577 assert_pll_disabled(dev_priv, PIPE_A);
6578 assert_pll_disabled(dev_priv, PIPE_B);
6579 } else {
6580 phy = DPIO_PHY1;
6581 assert_pll_disabled(dev_priv, PIPE_C);
6582 }
6583
6584 I915_WRITE(DISPLAY_PHY_CONTROL, I915_READ(DISPLAY_PHY_CONTROL) &
6585 ~PHY_COM_LANE_RESET_DEASSERT(phy));
6586
6587 vlv_set_power_well(dev_priv, power_well, false);
6588 }
6589
6590 static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,
6591 struct i915_power_well *power_well)
6592 {
6593 enum pipe pipe = power_well->data;
6594 bool enabled;
6595 u32 state, ctrl;
6596
6597 mutex_lock(&dev_priv->rps.hw_lock);
6598
6599 state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe);
6600 /*
6601 * We only ever set the power-on and power-gate states, anything
6602 * else is unexpected.
6603 */
6604 WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe));
6605 enabled = state == DP_SSS_PWR_ON(pipe);
6606
6607 /*
6608 * A transient state at this point would mean some unexpected party
6609 * is poking at the power controls too.
6610 */
6611 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe);
6612 WARN_ON(ctrl << 16 != state);
6613
6614 mutex_unlock(&dev_priv->rps.hw_lock);
6615
6616 return enabled;
6617 }
6618
6619 static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
6620 struct i915_power_well *power_well,
6621 bool enable)
6622 {
6623 enum pipe pipe = power_well->data;
6624 u32 state;
6625 u32 ctrl;
6626
6627 state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe);
6628
6629 mutex_lock(&dev_priv->rps.hw_lock);
6630
6631 #define COND \
6632 ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state)
6633
6634 if (COND)
6635 goto out;
6636
6637 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
6638 ctrl &= ~DP_SSC_MASK(pipe);
6639 ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe);
6640 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl);
6641
6642 if (wait_for(COND, 100))
6643 DRM_ERROR("timout setting power well state %08x (%08x)\n",
6644 state,
6645 vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ));
6646
6647 #undef COND
6648
6649 out:
6650 mutex_unlock(&dev_priv->rps.hw_lock);
6651 }
6652
6653 static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv,
6654 struct i915_power_well *power_well)
6655 {
6656 chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0);
6657 }
6658
6659 static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
6660 struct i915_power_well *power_well)
6661 {
6662 WARN_ON_ONCE(power_well->data != PIPE_A &&
6663 power_well->data != PIPE_B &&
6664 power_well->data != PIPE_C);
6665
6666 chv_set_pipe_power_well(dev_priv, power_well, true);
6667 }
6668
6669 static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
6670 struct i915_power_well *power_well)
6671 {
6672 WARN_ON_ONCE(power_well->data != PIPE_A &&
6673 power_well->data != PIPE_B &&
6674 power_well->data != PIPE_C);
6675
6676 chv_set_pipe_power_well(dev_priv, power_well, false);
6677 }
6678
6679 static void check_power_well_state(struct drm_i915_private *dev_priv,
6680 struct i915_power_well *power_well)
6681 {
6682 bool enabled = power_well->ops->is_enabled(dev_priv, power_well);
6683
6684 if (power_well->always_on || !i915.disable_power_well) {
6685 if (!enabled)
6686 goto mismatch;
6687
6688 return;
6689 }
6690
6691 if (enabled != (power_well->count > 0))
6692 goto mismatch;
6693
6694 return;
6695
6696 mismatch:
6697 WARN(1, "state mismatch for '%s' (always_on %d hw state %d use-count %d disable_power_well %d\n",
6698 power_well->name, power_well->always_on, enabled,
6699 power_well->count, i915.disable_power_well);
6700 }
6701
6702 void intel_display_power_get(struct drm_i915_private *dev_priv,
6703 enum intel_display_power_domain domain)
6704 {
6705 struct i915_power_domains *power_domains;
6706 struct i915_power_well *power_well;
6707 int i;
6708
6709 intel_runtime_pm_get(dev_priv);
6710
6711 power_domains = &dev_priv->power_domains;
6712
6713 mutex_lock(&power_domains->lock);
6714
6715 for_each_power_well(i, power_well, BIT(domain), power_domains) {
6716 if (!power_well->count++) {
6717 DRM_DEBUG_KMS("enabling %s\n", power_well->name);
6718 power_well->ops->enable(dev_priv, power_well);
6719 power_well->hw_enabled = true;
6720 }
6721
6722 check_power_well_state(dev_priv, power_well);
6723 }
6724
6725 power_domains->domain_use_count[domain]++;
6726
6727 mutex_unlock(&power_domains->lock);
6728 }
6729
6730 void intel_display_power_put(struct drm_i915_private *dev_priv,
6731 enum intel_display_power_domain domain)
6732 {
6733 struct i915_power_domains *power_domains;
6734 struct i915_power_well *power_well;
6735 int i;
6736
6737 power_domains = &dev_priv->power_domains;
6738
6739 mutex_lock(&power_domains->lock);
6740
6741 WARN_ON(!power_domains->domain_use_count[domain]);
6742 power_domains->domain_use_count[domain]--;
6743
6744 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
6745 WARN_ON(!power_well->count);
6746
6747 if (!--power_well->count && i915.disable_power_well) {
6748 DRM_DEBUG_KMS("disabling %s\n", power_well->name);
6749 power_well->hw_enabled = false;
6750 power_well->ops->disable(dev_priv, power_well);
6751 }
6752
6753 check_power_well_state(dev_priv, power_well);
6754 }
6755
6756 mutex_unlock(&power_domains->lock);
6757
6758 intel_runtime_pm_put(dev_priv);
6759 }
6760
6761 static struct i915_power_domains *hsw_pwr;
6762
6763 /* Display audio driver power well request */
6764 int i915_request_power_well(void)
6765 {
6766 struct drm_i915_private *dev_priv;
6767
6768 if (!hsw_pwr)
6769 return -ENODEV;
6770
6771 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
6772 power_domains);
6773 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
6774 return 0;
6775 }
6776 EXPORT_SYMBOL_GPL(i915_request_power_well);
6777
6778 /* Display audio driver power well release */
6779 int i915_release_power_well(void)
6780 {
6781 struct drm_i915_private *dev_priv;
6782
6783 if (!hsw_pwr)
6784 return -ENODEV;
6785
6786 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
6787 power_domains);
6788 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
6789 return 0;
6790 }
6791 EXPORT_SYMBOL_GPL(i915_release_power_well);
6792
6793 /*
6794 * Private interface for the audio driver to get CDCLK in kHz.
6795 *
6796 * Caller must request power well using i915_request_power_well() prior to
6797 * making the call.
6798 */
6799 int i915_get_cdclk_freq(void)
6800 {
6801 struct drm_i915_private *dev_priv;
6802
6803 if (!hsw_pwr)
6804 return -ENODEV;
6805
6806 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
6807 power_domains);
6808
6809 return intel_ddi_get_cdclk_freq(dev_priv);
6810 }
6811 EXPORT_SYMBOL_GPL(i915_get_cdclk_freq);
6812
6813
6814 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
6815
6816 #define HSW_ALWAYS_ON_POWER_DOMAINS ( \
6817 BIT(POWER_DOMAIN_PIPE_A) | \
6818 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
6819 BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
6820 BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
6821 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6822 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6823 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6824 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6825 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
6826 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
6827 BIT(POWER_DOMAIN_PORT_CRT) | \
6828 BIT(POWER_DOMAIN_PLLS) | \
6829 BIT(POWER_DOMAIN_INIT))
6830 #define HSW_DISPLAY_POWER_DOMAINS ( \
6831 (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \
6832 BIT(POWER_DOMAIN_INIT))
6833
6834 #define BDW_ALWAYS_ON_POWER_DOMAINS ( \
6835 HSW_ALWAYS_ON_POWER_DOMAINS | \
6836 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
6837 #define BDW_DISPLAY_POWER_DOMAINS ( \
6838 (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) | \
6839 BIT(POWER_DOMAIN_INIT))
6840
6841 #define VLV_ALWAYS_ON_POWER_DOMAINS BIT(POWER_DOMAIN_INIT)
6842 #define VLV_DISPLAY_POWER_DOMAINS POWER_DOMAIN_MASK
6843
6844 #define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \
6845 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6846 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6847 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6848 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6849 BIT(POWER_DOMAIN_PORT_CRT) | \
6850 BIT(POWER_DOMAIN_INIT))
6851
6852 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \
6853 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6854 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6855 BIT(POWER_DOMAIN_INIT))
6856
6857 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \
6858 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6859 BIT(POWER_DOMAIN_INIT))
6860
6861 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \
6862 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6863 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6864 BIT(POWER_DOMAIN_INIT))
6865
6866 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \
6867 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6868 BIT(POWER_DOMAIN_INIT))
6869
6870 #define CHV_PIPE_A_POWER_DOMAINS ( \
6871 BIT(POWER_DOMAIN_PIPE_A) | \
6872 BIT(POWER_DOMAIN_INIT))
6873
6874 #define CHV_PIPE_B_POWER_DOMAINS ( \
6875 BIT(POWER_DOMAIN_PIPE_B) | \
6876 BIT(POWER_DOMAIN_INIT))
6877
6878 #define CHV_PIPE_C_POWER_DOMAINS ( \
6879 BIT(POWER_DOMAIN_PIPE_C) | \
6880 BIT(POWER_DOMAIN_INIT))
6881
6882 #define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \
6883 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6884 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6885 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6886 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6887 BIT(POWER_DOMAIN_INIT))
6888
6889 #define CHV_DPIO_CMN_D_POWER_DOMAINS ( \
6890 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
6891 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
6892 BIT(POWER_DOMAIN_INIT))
6893
6894 #define CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS ( \
6895 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
6896 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
6897 BIT(POWER_DOMAIN_INIT))
6898
6899 #define CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS ( \
6900 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
6901 BIT(POWER_DOMAIN_INIT))
6902
6903 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
6904 .sync_hw = i9xx_always_on_power_well_noop,
6905 .enable = i9xx_always_on_power_well_noop,
6906 .disable = i9xx_always_on_power_well_noop,
6907 .is_enabled = i9xx_always_on_power_well_enabled,
6908 };
6909
6910 static const struct i915_power_well_ops chv_pipe_power_well_ops = {
6911 .sync_hw = chv_pipe_power_well_sync_hw,
6912 .enable = chv_pipe_power_well_enable,
6913 .disable = chv_pipe_power_well_disable,
6914 .is_enabled = chv_pipe_power_well_enabled,
6915 };
6916
6917 static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = {
6918 .sync_hw = vlv_power_well_sync_hw,
6919 .enable = chv_dpio_cmn_power_well_enable,
6920 .disable = chv_dpio_cmn_power_well_disable,
6921 .is_enabled = vlv_power_well_enabled,
6922 };
6923
6924 static struct i915_power_well i9xx_always_on_power_well[] = {
6925 {
6926 .name = "always-on",
6927 .always_on = 1,
6928 .domains = POWER_DOMAIN_MASK,
6929 .ops = &i9xx_always_on_power_well_ops,
6930 },
6931 };
6932
6933 static const struct i915_power_well_ops hsw_power_well_ops = {
6934 .sync_hw = hsw_power_well_sync_hw,
6935 .enable = hsw_power_well_enable,
6936 .disable = hsw_power_well_disable,
6937 .is_enabled = hsw_power_well_enabled,
6938 };
6939
6940 static struct i915_power_well hsw_power_wells[] = {
6941 {
6942 .name = "always-on",
6943 .always_on = 1,
6944 .domains = HSW_ALWAYS_ON_POWER_DOMAINS,
6945 .ops = &i9xx_always_on_power_well_ops,
6946 },
6947 {
6948 .name = "display",
6949 .domains = HSW_DISPLAY_POWER_DOMAINS,
6950 .ops = &hsw_power_well_ops,
6951 },
6952 };
6953
6954 static struct i915_power_well bdw_power_wells[] = {
6955 {
6956 .name = "always-on",
6957 .always_on = 1,
6958 .domains = BDW_ALWAYS_ON_POWER_DOMAINS,
6959 .ops = &i9xx_always_on_power_well_ops,
6960 },
6961 {
6962 .name = "display",
6963 .domains = BDW_DISPLAY_POWER_DOMAINS,
6964 .ops = &hsw_power_well_ops,
6965 },
6966 };
6967
6968 static const struct i915_power_well_ops vlv_display_power_well_ops = {
6969 .sync_hw = vlv_power_well_sync_hw,
6970 .enable = vlv_display_power_well_enable,
6971 .disable = vlv_display_power_well_disable,
6972 .is_enabled = vlv_power_well_enabled,
6973 };
6974
6975 static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = {
6976 .sync_hw = vlv_power_well_sync_hw,
6977 .enable = vlv_dpio_cmn_power_well_enable,
6978 .disable = vlv_dpio_cmn_power_well_disable,
6979 .is_enabled = vlv_power_well_enabled,
6980 };
6981
6982 static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
6983 .sync_hw = vlv_power_well_sync_hw,
6984 .enable = vlv_power_well_enable,
6985 .disable = vlv_power_well_disable,
6986 .is_enabled = vlv_power_well_enabled,
6987 };
6988
6989 static struct i915_power_well vlv_power_wells[] = {
6990 {
6991 .name = "always-on",
6992 .always_on = 1,
6993 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
6994 .ops = &i9xx_always_on_power_well_ops,
6995 },
6996 {
6997 .name = "display",
6998 .domains = VLV_DISPLAY_POWER_DOMAINS,
6999 .data = PUNIT_POWER_WELL_DISP2D,
7000 .ops = &vlv_display_power_well_ops,
7001 },
7002 {
7003 .name = "dpio-tx-b-01",
7004 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
7005 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
7006 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
7007 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
7008 .ops = &vlv_dpio_power_well_ops,
7009 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
7010 },
7011 {
7012 .name = "dpio-tx-b-23",
7013 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
7014 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
7015 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
7016 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
7017 .ops = &vlv_dpio_power_well_ops,
7018 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
7019 },
7020 {
7021 .name = "dpio-tx-c-01",
7022 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
7023 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
7024 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
7025 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
7026 .ops = &vlv_dpio_power_well_ops,
7027 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
7028 },
7029 {
7030 .name = "dpio-tx-c-23",
7031 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
7032 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
7033 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
7034 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
7035 .ops = &vlv_dpio_power_well_ops,
7036 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
7037 },
7038 {
7039 .name = "dpio-common",
7040 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
7041 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
7042 .ops = &vlv_dpio_cmn_power_well_ops,
7043 },
7044 };
7045
7046 static struct i915_power_well chv_power_wells[] = {
7047 {
7048 .name = "always-on",
7049 .always_on = 1,
7050 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
7051 .ops = &i9xx_always_on_power_well_ops,
7052 },
7053 #if 0
7054 {
7055 .name = "display",
7056 .domains = VLV_DISPLAY_POWER_DOMAINS,
7057 .data = PUNIT_POWER_WELL_DISP2D,
7058 .ops = &vlv_display_power_well_ops,
7059 },
7060 {
7061 .name = "pipe-a",
7062 .domains = CHV_PIPE_A_POWER_DOMAINS,
7063 .data = PIPE_A,
7064 .ops = &chv_pipe_power_well_ops,
7065 },
7066 {
7067 .name = "pipe-b",
7068 .domains = CHV_PIPE_B_POWER_DOMAINS,
7069 .data = PIPE_B,
7070 .ops = &chv_pipe_power_well_ops,
7071 },
7072 {
7073 .name = "pipe-c",
7074 .domains = CHV_PIPE_C_POWER_DOMAINS,
7075 .data = PIPE_C,
7076 .ops = &chv_pipe_power_well_ops,
7077 },
7078 #endif
7079 {
7080 .name = "dpio-common-bc",
7081 /*
7082 * XXX: cmnreset for one PHY seems to disturb the other.
7083 * As a workaround keep both powered on at the same
7084 * time for now.
7085 */
7086 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS | CHV_DPIO_CMN_D_POWER_DOMAINS,
7087 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
7088 .ops = &chv_dpio_cmn_power_well_ops,
7089 },
7090 {
7091 .name = "dpio-common-d",
7092 /*
7093 * XXX: cmnreset for one PHY seems to disturb the other.
7094 * As a workaround keep both powered on at the same
7095 * time for now.
7096 */
7097 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS | CHV_DPIO_CMN_D_POWER_DOMAINS,
7098 .data = PUNIT_POWER_WELL_DPIO_CMN_D,
7099 .ops = &chv_dpio_cmn_power_well_ops,
7100 },
7101 #if 0
7102 {
7103 .name = "dpio-tx-b-01",
7104 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
7105 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS,
7106 .ops = &vlv_dpio_power_well_ops,
7107 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
7108 },
7109 {
7110 .name = "dpio-tx-b-23",
7111 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
7112 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS,
7113 .ops = &vlv_dpio_power_well_ops,
7114 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
7115 },
7116 {
7117 .name = "dpio-tx-c-01",
7118 .domains = VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
7119 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
7120 .ops = &vlv_dpio_power_well_ops,
7121 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
7122 },
7123 {
7124 .name = "dpio-tx-c-23",
7125 .domains = VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
7126 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
7127 .ops = &vlv_dpio_power_well_ops,
7128 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
7129 },
7130 {
7131 .name = "dpio-tx-d-01",
7132 .domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS |
7133 CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS,
7134 .ops = &vlv_dpio_power_well_ops,
7135 .data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_01,
7136 },
7137 {
7138 .name = "dpio-tx-d-23",
7139 .domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS |
7140 CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS,
7141 .ops = &vlv_dpio_power_well_ops,
7142 .data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_23,
7143 },
7144 #endif
7145 };
7146
7147 static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv,
7148 enum punit_power_well power_well_id)
7149 {
7150 struct i915_power_domains *power_domains = &dev_priv->power_domains;
7151 struct i915_power_well *power_well;
7152 int i;
7153
7154 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
7155 if (power_well->data == power_well_id)
7156 return power_well;
7157 }
7158
7159 return NULL;
7160 }
7161
7162 #define set_power_wells(power_domains, __power_wells) ({ \
7163 (power_domains)->power_wells = (__power_wells); \
7164 (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \
7165 })
7166
7167 int intel_power_domains_init(struct drm_i915_private *dev_priv)
7168 {
7169 struct i915_power_domains *power_domains = &dev_priv->power_domains;
7170
7171 mutex_init(&power_domains->lock);
7172
7173 /*
7174 * The enabling order will be from lower to higher indexed wells,
7175 * the disabling order is reversed.
7176 */
7177 if (IS_HASWELL(dev_priv->dev)) {
7178 set_power_wells(power_domains, hsw_power_wells);
7179 hsw_pwr = power_domains;
7180 } else if (IS_BROADWELL(dev_priv->dev)) {
7181 set_power_wells(power_domains, bdw_power_wells);
7182 hsw_pwr = power_domains;
7183 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
7184 set_power_wells(power_domains, chv_power_wells);
7185 } else if (IS_VALLEYVIEW(dev_priv->dev)) {
7186 set_power_wells(power_domains, vlv_power_wells);
7187 } else {
7188 set_power_wells(power_domains, i9xx_always_on_power_well);
7189 }
7190
7191 return 0;
7192 }
7193
7194 void intel_power_domains_remove(struct drm_i915_private *dev_priv)
7195 {
7196 hsw_pwr = NULL;
7197 }
7198
7199 static void intel_power_domains_resume(struct drm_i915_private *dev_priv)
7200 {
7201 struct i915_power_domains *power_domains = &dev_priv->power_domains;
7202 struct i915_power_well *power_well;
7203 int i;
7204
7205 mutex_lock(&power_domains->lock);
7206 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
7207 power_well->ops->sync_hw(dev_priv, power_well);
7208 power_well->hw_enabled = power_well->ops->is_enabled(dev_priv,
7209 power_well);
7210 }
7211 mutex_unlock(&power_domains->lock);
7212 }
7213
7214 static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
7215 {
7216 struct i915_power_well *cmn =
7217 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
7218 struct i915_power_well *disp2d =
7219 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D);
7220
7221 /* nothing to do if common lane is already off */
7222 if (!cmn->ops->is_enabled(dev_priv, cmn))
7223 return;
7224
7225 /* If the display might be already active skip this */
7226 if (disp2d->ops->is_enabled(dev_priv, disp2d) &&
7227 I915_READ(DPIO_CTL) & DPIO_CMNRST)
7228 return;
7229
7230 DRM_DEBUG_KMS("toggling display PHY side reset\n");
7231
7232 /* cmnlane needs DPLL registers */
7233 disp2d->ops->enable(dev_priv, disp2d);
7234
7235 /*
7236 * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
7237 * Need to assert and de-assert PHY SB reset by gating the
7238 * common lane power, then un-gating it.
7239 * Simply ungating isn't enough to reset the PHY enough to get
7240 * ports and lanes running.
7241 */
7242 cmn->ops->disable(dev_priv, cmn);
7243 }
7244
7245 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv)
7246 {
7247 struct drm_device *dev = dev_priv->dev;
7248 struct i915_power_domains *power_domains = &dev_priv->power_domains;
7249
7250 power_domains->initializing = true;
7251
7252 if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
7253 mutex_lock(&power_domains->lock);
7254 vlv_cmnlane_wa(dev_priv);
7255 mutex_unlock(&power_domains->lock);
7256 }
7257
7258 /* For now, we need the power well to be always enabled. */
7259 intel_display_set_init_power(dev_priv, true);
7260 intel_power_domains_resume(dev_priv);
7261 power_domains->initializing = false;
7262 }
7263
7264 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)
7265 {
7266 intel_runtime_pm_get(dev_priv);
7267 }
7268
7269 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)
7270 {
7271 intel_runtime_pm_put(dev_priv);
7272 }
7273
7274 void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
7275 {
7276 struct drm_device *dev = dev_priv->dev;
7277 struct device *device = &dev->pdev->dev;
7278
7279 if (!HAS_RUNTIME_PM(dev))
7280 return;
7281
7282 pm_runtime_get_sync(device);
7283 WARN(dev_priv->pm.suspended, "Device still suspended.\n");
7284 }
7285
7286 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv)
7287 {
7288 struct drm_device *dev = dev_priv->dev;
7289 struct device *device = &dev->pdev->dev;
7290
7291 if (!HAS_RUNTIME_PM(dev))
7292 return;
7293
7294 WARN(dev_priv->pm.suspended, "Getting nosync-ref while suspended.\n");
7295 pm_runtime_get_noresume(device);
7296 }
7297
7298 void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
7299 {
7300 struct drm_device *dev = dev_priv->dev;
7301 struct device *device = &dev->pdev->dev;
7302
7303 if (!HAS_RUNTIME_PM(dev))
7304 return;
7305
7306 pm_runtime_mark_last_busy(device);
7307 pm_runtime_put_autosuspend(device);
7308 }
7309
7310 void intel_init_runtime_pm(struct drm_i915_private *dev_priv)
7311 {
7312 struct drm_device *dev = dev_priv->dev;
7313 struct device *device = &dev->pdev->dev;
7314
7315 if (!HAS_RUNTIME_PM(dev))
7316 return;
7317
7318 pm_runtime_set_active(device);
7319
7320 /*
7321 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
7322 * requirement.
7323 */
7324 if (!intel_enable_rc6(dev)) {
7325 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
7326 return;
7327 }
7328
7329 pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
7330 pm_runtime_mark_last_busy(device);
7331 pm_runtime_use_autosuspend(device);
7332
7333 pm_runtime_put_autosuspend(device);
7334 }
7335
7336 void intel_fini_runtime_pm(struct drm_i915_private *dev_priv)
7337 {
7338 struct drm_device *dev = dev_priv->dev;
7339 struct device *device = &dev->pdev->dev;
7340
7341 if (!HAS_RUNTIME_PM(dev))
7342 return;
7343
7344 if (!intel_enable_rc6(dev))
7345 return;
7346
7347 /* Make sure we're not suspended first. */
7348 pm_runtime_get_sync(device);
7349 pm_runtime_disable(device);
7350 }
7351
7352 /* Set up chip specific power management-related functions */
7353 void intel_init_pm(struct drm_device *dev)
7354 {
7355 struct drm_i915_private *dev_priv = dev->dev_private;
7356
7357 if (HAS_FBC(dev)) {
7358 if (INTEL_INFO(dev)->gen >= 7) {
7359 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
7360 dev_priv->display.enable_fbc = gen7_enable_fbc;
7361 dev_priv->display.disable_fbc = ironlake_disable_fbc;
7362 } else if (INTEL_INFO(dev)->gen >= 5) {
7363 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
7364 dev_priv->display.enable_fbc = ironlake_enable_fbc;
7365 dev_priv->display.disable_fbc = ironlake_disable_fbc;
7366 } else if (IS_GM45(dev)) {
7367 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
7368 dev_priv->display.enable_fbc = g4x_enable_fbc;
7369 dev_priv->display.disable_fbc = g4x_disable_fbc;
7370 } else {
7371 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
7372 dev_priv->display.enable_fbc = i8xx_enable_fbc;
7373 dev_priv->display.disable_fbc = i8xx_disable_fbc;
7374
7375 /* This value was pulled out of someone's hat */
7376 I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);
7377 }
7378 }
7379
7380 /* For cxsr */
7381 if (IS_PINEVIEW(dev))
7382 i915_pineview_get_mem_freq(dev);
7383 else if (IS_GEN5(dev))
7384 i915_ironlake_get_mem_freq(dev);
7385
7386 /* For FIFO watermark updates */
7387 if (HAS_PCH_SPLIT(dev)) {
7388 ilk_setup_wm_latency(dev);
7389
7390 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
7391 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7392 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7393 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
7394 dev_priv->display.update_wm = ilk_update_wm;
7395 dev_priv->display.update_sprite_wm = ilk_update_sprite_wm;
7396 } else {
7397 DRM_DEBUG_KMS("Failed to read display plane latency. "
7398 "Disable CxSR\n");
7399 }
7400
7401 if (IS_GEN5(dev))
7402 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7403 else if (IS_GEN6(dev))
7404 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7405 else if (IS_IVYBRIDGE(dev))
7406 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7407 else if (IS_HASWELL(dev))
7408 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7409 else if (INTEL_INFO(dev)->gen == 8)
7410 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7411 } else if (IS_CHERRYVIEW(dev)) {
7412 dev_priv->display.update_wm = cherryview_update_wm;
7413 dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;
7414 dev_priv->display.init_clock_gating =
7415 cherryview_init_clock_gating;
7416 } else if (IS_VALLEYVIEW(dev)) {
7417 dev_priv->display.update_wm = valleyview_update_wm;
7418 dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;
7419 dev_priv->display.init_clock_gating =
7420 valleyview_init_clock_gating;
7421 } else if (IS_PINEVIEW(dev)) {
7422 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7423 dev_priv->is_ddr3,
7424 dev_priv->fsb_freq,
7425 dev_priv->mem_freq)) {
7426 DRM_INFO("failed to find known CxSR latency "
7427 "(found ddr%s fsb freq %d, mem freq %d), "
7428 "disabling CxSR\n",
7429 (dev_priv->is_ddr3 == 1) ? "3" : "2",
7430 dev_priv->fsb_freq, dev_priv->mem_freq);
7431 /* Disable CxSR and never update its watermark again */
7432 intel_set_memory_cxsr(dev_priv, false);
7433 dev_priv->display.update_wm = NULL;
7434 } else
7435 dev_priv->display.update_wm = pineview_update_wm;
7436 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7437 } else if (IS_G4X(dev)) {
7438 dev_priv->display.update_wm = g4x_update_wm;
7439 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7440 } else if (IS_GEN4(dev)) {
7441 dev_priv->display.update_wm = i965_update_wm;
7442 if (IS_CRESTLINE(dev))
7443 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7444 else if (IS_BROADWATER(dev))
7445 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7446 } else if (IS_GEN3(dev)) {
7447 dev_priv->display.update_wm = i9xx_update_wm;
7448 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7449 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7450 } else if (IS_GEN2(dev)) {
7451 if (INTEL_INFO(dev)->num_pipes == 1) {
7452 dev_priv->display.update_wm = i845_update_wm;
7453 dev_priv->display.get_fifo_size = i845_get_fifo_size;
7454 } else {
7455 dev_priv->display.update_wm = i9xx_update_wm;
7456 dev_priv->display.get_fifo_size = i830_get_fifo_size;
7457 }
7458
7459 if (IS_I85X(dev) || IS_I865G(dev))
7460 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7461 else
7462 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7463 } else {
7464 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
7465 }
7466 }
7467
7468 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
7469 {
7470 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7471
7472 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7473 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7474 return -EAGAIN;
7475 }
7476
7477 I915_WRITE(GEN6_PCODE_DATA, *val);
7478 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7479
7480 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7481 500)) {
7482 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7483 return -ETIMEDOUT;
7484 }
7485
7486 *val = I915_READ(GEN6_PCODE_DATA);
7487 I915_WRITE(GEN6_PCODE_DATA, 0);
7488
7489 return 0;
7490 }
7491
7492 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
7493 {
7494 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7495
7496 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7497 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7498 return -EAGAIN;
7499 }
7500
7501 I915_WRITE(GEN6_PCODE_DATA, val);
7502 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7503
7504 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7505 500)) {
7506 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7507 return -ETIMEDOUT;
7508 }
7509
7510 I915_WRITE(GEN6_PCODE_DATA, 0);
7511
7512 return 0;
7513 }
7514
7515 static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7516 {
7517 int div;
7518
7519 /* 4 x czclk */
7520 switch (dev_priv->mem_freq) {
7521 case 800:
7522 div = 10;
7523 break;
7524 case 1066:
7525 div = 12;
7526 break;
7527 case 1333:
7528 div = 16;
7529 break;
7530 default:
7531 return -1;
7532 }
7533
7534 return DIV_ROUND_CLOSEST(dev_priv->mem_freq * (val + 6 - 0xbd), 4 * div);
7535 }
7536
7537 static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
7538 {
7539 int mul;
7540
7541 /* 4 x czclk */
7542 switch (dev_priv->mem_freq) {
7543 case 800:
7544 mul = 10;
7545 break;
7546 case 1066:
7547 mul = 12;
7548 break;
7549 case 1333:
7550 mul = 16;
7551 break;
7552 default:
7553 return -1;
7554 }
7555
7556 return DIV_ROUND_CLOSEST(4 * mul * val, dev_priv->mem_freq) + 0xbd - 6;
7557 }
7558
7559 static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
7560 {
7561 int div, freq;
7562
7563 switch (dev_priv->rps.cz_freq) {
7564 case 200:
7565 div = 5;
7566 break;
7567 case 267:
7568 div = 6;
7569 break;
7570 case 320:
7571 case 333:
7572 case 400:
7573 div = 8;
7574 break;
7575 default:
7576 return -1;
7577 }
7578
7579 freq = (DIV_ROUND_CLOSEST((dev_priv->rps.cz_freq * val), 2 * div) / 2);
7580
7581 return freq;
7582 }
7583
7584 static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
7585 {
7586 int mul, opcode;
7587
7588 switch (dev_priv->rps.cz_freq) {
7589 case 200:
7590 mul = 5;
7591 break;
7592 case 267:
7593 mul = 6;
7594 break;
7595 case 320:
7596 case 333:
7597 case 400:
7598 mul = 8;
7599 break;
7600 default:
7601 return -1;
7602 }
7603
7604 /* CHV needs even values */
7605 opcode = (DIV_ROUND_CLOSEST((val * 2 * mul), dev_priv->rps.cz_freq) * 2);
7606
7607 return opcode;
7608 }
7609
7610 int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val)
7611 {
7612 int ret = -1;
7613
7614 if (IS_CHERRYVIEW(dev_priv->dev))
7615 ret = chv_gpu_freq(dev_priv, val);
7616 else if (IS_VALLEYVIEW(dev_priv->dev))
7617 ret = byt_gpu_freq(dev_priv, val);
7618
7619 return ret;
7620 }
7621
7622 int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val)
7623 {
7624 int ret = -1;
7625
7626 if (IS_CHERRYVIEW(dev_priv->dev))
7627 ret = chv_freq_opcode(dev_priv, val);
7628 else if (IS_VALLEYVIEW(dev_priv->dev))
7629 ret = byt_freq_opcode(dev_priv, val);
7630
7631 return ret;
7632 }
7633
7634 void intel_pm_setup(struct drm_device *dev)
7635 {
7636 struct drm_i915_private *dev_priv = dev->dev_private;
7637
7638 mutex_init(&dev_priv->rps.hw_lock);
7639
7640 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
7641 intel_gen6_powersave_work);
7642
7643 dev_priv->pm.suspended = false;
7644 dev_priv->pm._irqs_disabled = false;
7645 }
Linux kernel - Deliverables
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