2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
28 #include <linux/cpufreq.h>
30 #include "intel_drv.h"
31 #include "../../../platform/x86/intel_ips.h"
32 #include <linux/module.h>
33 #include <linux/vgaarb.h>
34 #include <drm/i915_powerwell.h>
35 #include <linux/pm_runtime.h>
38 * RC6 is a special power stage which allows the GPU to enter an very
39 * low-voltage mode when idle, using down to 0V while at this stage. This
40 * stage is entered automatically when the GPU is idle when RC6 support is
41 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
43 * There are different RC6 modes available in Intel GPU, which differentiate
44 * among each other with the latency required to enter and leave RC6 and
45 * voltage consumed by the GPU in different states.
47 * The combination of the following flags define which states GPU is allowed
48 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
49 * RC6pp is deepest RC6. Their support by hardware varies according to the
50 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
51 * which brings the most power savings; deeper states save more power, but
52 * require higher latency to switch to and wake up.
54 #define INTEL_RC6_ENABLE (1<<0)
55 #define INTEL_RC6p_ENABLE (1<<1)
56 #define INTEL_RC6pp_ENABLE (1<<2)
58 /* FBC, or Frame Buffer Compression, is a technique employed to compress the
59 * framebuffer contents in-memory, aiming at reducing the required bandwidth
60 * during in-memory transfers and, therefore, reduce the power packet.
62 * The benefits of FBC are mostly visible with solid backgrounds and
63 * variation-less patterns.
65 * FBC-related functionality can be enabled by the means of the
66 * i915.i915_enable_fbc parameter
69 static void i8xx_disable_fbc(struct drm_device
*dev
)
71 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
74 /* Disable compression */
75 fbc_ctl
= I915_READ(FBC_CONTROL
);
76 if ((fbc_ctl
& FBC_CTL_EN
) == 0)
79 fbc_ctl
&= ~FBC_CTL_EN
;
80 I915_WRITE(FBC_CONTROL
, fbc_ctl
);
82 /* Wait for compressing bit to clear */
83 if (wait_for((I915_READ(FBC_STATUS
) & FBC_STAT_COMPRESSING
) == 0, 10)) {
84 DRM_DEBUG_KMS("FBC idle timed out\n");
88 DRM_DEBUG_KMS("disabled FBC\n");
91 static void i8xx_enable_fbc(struct drm_crtc
*crtc
)
93 struct drm_device
*dev
= crtc
->dev
;
94 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
95 struct drm_framebuffer
*fb
= crtc
->primary
->fb
;
96 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
97 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
102 cfb_pitch
= dev_priv
->fbc
.size
/ FBC_LL_SIZE
;
103 if (fb
->pitches
[0] < cfb_pitch
)
104 cfb_pitch
= fb
->pitches
[0];
106 /* FBC_CTL wants 32B or 64B units */
108 cfb_pitch
= (cfb_pitch
/ 32) - 1;
110 cfb_pitch
= (cfb_pitch
/ 64) - 1;
113 for (i
= 0; i
< (FBC_LL_SIZE
/ 32) + 1; i
++)
114 I915_WRITE(FBC_TAG
+ (i
* 4), 0);
120 fbc_ctl2
= FBC_CTL_FENCE_DBL
| FBC_CTL_IDLE_IMM
| FBC_CTL_CPU_FENCE
;
121 fbc_ctl2
|= FBC_CTL_PLANE(intel_crtc
->plane
);
122 I915_WRITE(FBC_CONTROL2
, fbc_ctl2
);
123 I915_WRITE(FBC_FENCE_OFF
, crtc
->y
);
127 fbc_ctl
= I915_READ(FBC_CONTROL
);
128 fbc_ctl
&= 0x3fff << FBC_CTL_INTERVAL_SHIFT
;
129 fbc_ctl
|= FBC_CTL_EN
| FBC_CTL_PERIODIC
;
131 fbc_ctl
|= FBC_CTL_C3_IDLE
; /* 945 needs special SR handling */
132 fbc_ctl
|= (cfb_pitch
& 0xff) << FBC_CTL_STRIDE_SHIFT
;
133 fbc_ctl
|= obj
->fence_reg
;
134 I915_WRITE(FBC_CONTROL
, fbc_ctl
);
136 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c\n",
137 cfb_pitch
, crtc
->y
, plane_name(intel_crtc
->plane
));
140 static bool i8xx_fbc_enabled(struct drm_device
*dev
)
142 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
144 return I915_READ(FBC_CONTROL
) & FBC_CTL_EN
;
147 static void g4x_enable_fbc(struct drm_crtc
*crtc
)
149 struct drm_device
*dev
= crtc
->dev
;
150 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
151 struct drm_framebuffer
*fb
= crtc
->primary
->fb
;
152 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
153 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
156 dpfc_ctl
= DPFC_CTL_PLANE(intel_crtc
->plane
) | DPFC_SR_EN
;
157 if (drm_format_plane_cpp(fb
->pixel_format
, 0) == 2)
158 dpfc_ctl
|= DPFC_CTL_LIMIT_2X
;
160 dpfc_ctl
|= DPFC_CTL_LIMIT_1X
;
161 dpfc_ctl
|= DPFC_CTL_FENCE_EN
| obj
->fence_reg
;
163 I915_WRITE(DPFC_FENCE_YOFF
, crtc
->y
);
166 I915_WRITE(DPFC_CONTROL
, dpfc_ctl
| DPFC_CTL_EN
);
168 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc
->plane
));
171 static void g4x_disable_fbc(struct drm_device
*dev
)
173 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
176 /* Disable compression */
177 dpfc_ctl
= I915_READ(DPFC_CONTROL
);
178 if (dpfc_ctl
& DPFC_CTL_EN
) {
179 dpfc_ctl
&= ~DPFC_CTL_EN
;
180 I915_WRITE(DPFC_CONTROL
, dpfc_ctl
);
182 DRM_DEBUG_KMS("disabled FBC\n");
186 static bool g4x_fbc_enabled(struct drm_device
*dev
)
188 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
190 return I915_READ(DPFC_CONTROL
) & DPFC_CTL_EN
;
193 static void sandybridge_blit_fbc_update(struct drm_device
*dev
)
195 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
198 /* Make sure blitter notifies FBC of writes */
200 /* Blitter is part of Media powerwell on VLV. No impact of
201 * his param in other platforms for now */
202 gen6_gt_force_wake_get(dev_priv
, FORCEWAKE_MEDIA
);
204 blt_ecoskpd
= I915_READ(GEN6_BLITTER_ECOSKPD
);
205 blt_ecoskpd
|= GEN6_BLITTER_FBC_NOTIFY
<<
206 GEN6_BLITTER_LOCK_SHIFT
;
207 I915_WRITE(GEN6_BLITTER_ECOSKPD
, blt_ecoskpd
);
208 blt_ecoskpd
|= GEN6_BLITTER_FBC_NOTIFY
;
209 I915_WRITE(GEN6_BLITTER_ECOSKPD
, blt_ecoskpd
);
210 blt_ecoskpd
&= ~(GEN6_BLITTER_FBC_NOTIFY
<<
211 GEN6_BLITTER_LOCK_SHIFT
);
212 I915_WRITE(GEN6_BLITTER_ECOSKPD
, blt_ecoskpd
);
213 POSTING_READ(GEN6_BLITTER_ECOSKPD
);
215 gen6_gt_force_wake_put(dev_priv
, FORCEWAKE_MEDIA
);
218 static void ironlake_enable_fbc(struct drm_crtc
*crtc
)
220 struct drm_device
*dev
= crtc
->dev
;
221 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
222 struct drm_framebuffer
*fb
= crtc
->primary
->fb
;
223 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
224 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
227 dpfc_ctl
= DPFC_CTL_PLANE(intel_crtc
->plane
);
228 if (drm_format_plane_cpp(fb
->pixel_format
, 0) == 2)
229 dev_priv
->fbc
.threshold
++;
231 switch (dev_priv
->fbc
.threshold
) {
234 dpfc_ctl
|= DPFC_CTL_LIMIT_4X
;
237 dpfc_ctl
|= DPFC_CTL_LIMIT_2X
;
240 dpfc_ctl
|= DPFC_CTL_LIMIT_1X
;
243 dpfc_ctl
|= DPFC_CTL_FENCE_EN
;
245 dpfc_ctl
|= obj
->fence_reg
;
247 I915_WRITE(ILK_DPFC_FENCE_YOFF
, crtc
->y
);
248 I915_WRITE(ILK_FBC_RT_BASE
, i915_gem_obj_ggtt_offset(obj
) | ILK_FBC_RT_VALID
);
250 I915_WRITE(ILK_DPFC_CONTROL
, dpfc_ctl
| DPFC_CTL_EN
);
253 I915_WRITE(SNB_DPFC_CTL_SA
,
254 SNB_CPU_FENCE_ENABLE
| obj
->fence_reg
);
255 I915_WRITE(DPFC_CPU_FENCE_OFFSET
, crtc
->y
);
256 sandybridge_blit_fbc_update(dev
);
259 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc
->plane
));
262 static void ironlake_disable_fbc(struct drm_device
*dev
)
264 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
267 /* Disable compression */
268 dpfc_ctl
= I915_READ(ILK_DPFC_CONTROL
);
269 if (dpfc_ctl
& DPFC_CTL_EN
) {
270 dpfc_ctl
&= ~DPFC_CTL_EN
;
271 I915_WRITE(ILK_DPFC_CONTROL
, dpfc_ctl
);
273 DRM_DEBUG_KMS("disabled FBC\n");
277 static bool ironlake_fbc_enabled(struct drm_device
*dev
)
279 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
281 return I915_READ(ILK_DPFC_CONTROL
) & DPFC_CTL_EN
;
284 static void gen7_enable_fbc(struct drm_crtc
*crtc
)
286 struct drm_device
*dev
= crtc
->dev
;
287 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
288 struct drm_framebuffer
*fb
= crtc
->primary
->fb
;
289 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
290 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
293 dpfc_ctl
= IVB_DPFC_CTL_PLANE(intel_crtc
->plane
);
294 if (drm_format_plane_cpp(fb
->pixel_format
, 0) == 2)
295 dev_priv
->fbc
.threshold
++;
297 switch (dev_priv
->fbc
.threshold
) {
300 dpfc_ctl
|= DPFC_CTL_LIMIT_4X
;
303 dpfc_ctl
|= DPFC_CTL_LIMIT_2X
;
306 dpfc_ctl
|= DPFC_CTL_LIMIT_1X
;
310 dpfc_ctl
|= IVB_DPFC_CTL_FENCE_EN
;
312 I915_WRITE(ILK_DPFC_CONTROL
, dpfc_ctl
| DPFC_CTL_EN
);
314 if (IS_IVYBRIDGE(dev
)) {
315 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
316 I915_WRITE(ILK_DISPLAY_CHICKEN1
,
317 I915_READ(ILK_DISPLAY_CHICKEN1
) |
320 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
321 I915_WRITE(CHICKEN_PIPESL_1(intel_crtc
->pipe
),
322 I915_READ(CHICKEN_PIPESL_1(intel_crtc
->pipe
)) |
326 I915_WRITE(SNB_DPFC_CTL_SA
,
327 SNB_CPU_FENCE_ENABLE
| obj
->fence_reg
);
328 I915_WRITE(DPFC_CPU_FENCE_OFFSET
, crtc
->y
);
330 sandybridge_blit_fbc_update(dev
);
332 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc
->plane
));
335 bool intel_fbc_enabled(struct drm_device
*dev
)
337 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
339 if (!dev_priv
->display
.fbc_enabled
)
342 return dev_priv
->display
.fbc_enabled(dev
);
345 static void intel_fbc_work_fn(struct work_struct
*__work
)
347 struct intel_fbc_work
*work
=
348 container_of(to_delayed_work(__work
),
349 struct intel_fbc_work
, work
);
350 struct drm_device
*dev
= work
->crtc
->dev
;
351 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
353 mutex_lock(&dev
->struct_mutex
);
354 if (work
== dev_priv
->fbc
.fbc_work
) {
355 /* Double check that we haven't switched fb without cancelling
358 if (work
->crtc
->primary
->fb
== work
->fb
) {
359 dev_priv
->display
.enable_fbc(work
->crtc
);
361 dev_priv
->fbc
.plane
= to_intel_crtc(work
->crtc
)->plane
;
362 dev_priv
->fbc
.fb_id
= work
->crtc
->primary
->fb
->base
.id
;
363 dev_priv
->fbc
.y
= work
->crtc
->y
;
366 dev_priv
->fbc
.fbc_work
= NULL
;
368 mutex_unlock(&dev
->struct_mutex
);
373 static void intel_cancel_fbc_work(struct drm_i915_private
*dev_priv
)
375 if (dev_priv
->fbc
.fbc_work
== NULL
)
378 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
380 /* Synchronisation is provided by struct_mutex and checking of
381 * dev_priv->fbc.fbc_work, so we can perform the cancellation
382 * entirely asynchronously.
384 if (cancel_delayed_work(&dev_priv
->fbc
.fbc_work
->work
))
385 /* tasklet was killed before being run, clean up */
386 kfree(dev_priv
->fbc
.fbc_work
);
388 /* Mark the work as no longer wanted so that if it does
389 * wake-up (because the work was already running and waiting
390 * for our mutex), it will discover that is no longer
393 dev_priv
->fbc
.fbc_work
= NULL
;
396 static void intel_enable_fbc(struct drm_crtc
*crtc
)
398 struct intel_fbc_work
*work
;
399 struct drm_device
*dev
= crtc
->dev
;
400 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
402 if (!dev_priv
->display
.enable_fbc
)
405 intel_cancel_fbc_work(dev_priv
);
407 work
= kzalloc(sizeof(*work
), GFP_KERNEL
);
409 DRM_ERROR("Failed to allocate FBC work structure\n");
410 dev_priv
->display
.enable_fbc(crtc
);
415 work
->fb
= crtc
->primary
->fb
;
416 INIT_DELAYED_WORK(&work
->work
, intel_fbc_work_fn
);
418 dev_priv
->fbc
.fbc_work
= work
;
420 /* Delay the actual enabling to let pageflipping cease and the
421 * display to settle before starting the compression. Note that
422 * this delay also serves a second purpose: it allows for a
423 * vblank to pass after disabling the FBC before we attempt
424 * to modify the control registers.
426 * A more complicated solution would involve tracking vblanks
427 * following the termination of the page-flipping sequence
428 * and indeed performing the enable as a co-routine and not
429 * waiting synchronously upon the vblank.
431 * WaFbcWaitForVBlankBeforeEnable:ilk,snb
433 schedule_delayed_work(&work
->work
, msecs_to_jiffies(50));
436 void intel_disable_fbc(struct drm_device
*dev
)
438 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
440 intel_cancel_fbc_work(dev_priv
);
442 if (!dev_priv
->display
.disable_fbc
)
445 dev_priv
->display
.disable_fbc(dev
);
446 dev_priv
->fbc
.plane
= -1;
449 static bool set_no_fbc_reason(struct drm_i915_private
*dev_priv
,
450 enum no_fbc_reason reason
)
452 if (dev_priv
->fbc
.no_fbc_reason
== reason
)
455 dev_priv
->fbc
.no_fbc_reason
= reason
;
460 * intel_update_fbc - enable/disable FBC as needed
461 * @dev: the drm_device
463 * Set up the framebuffer compression hardware at mode set time. We
464 * enable it if possible:
465 * - plane A only (on pre-965)
466 * - no pixel mulitply/line duplication
467 * - no alpha buffer discard
469 * - framebuffer <= max_hdisplay in width, max_vdisplay in height
471 * We can't assume that any compression will take place (worst case),
472 * so the compressed buffer has to be the same size as the uncompressed
473 * one. It also must reside (along with the line length buffer) in
476 * We need to enable/disable FBC on a global basis.
478 void intel_update_fbc(struct drm_device
*dev
)
480 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
481 struct drm_crtc
*crtc
= NULL
, *tmp_crtc
;
482 struct intel_crtc
*intel_crtc
;
483 struct drm_framebuffer
*fb
;
484 struct drm_i915_gem_object
*obj
;
485 const struct drm_display_mode
*adjusted_mode
;
486 unsigned int max_width
, max_height
;
489 set_no_fbc_reason(dev_priv
, FBC_UNSUPPORTED
);
493 if (!i915
.powersave
) {
494 if (set_no_fbc_reason(dev_priv
, FBC_MODULE_PARAM
))
495 DRM_DEBUG_KMS("fbc disabled per module param\n");
500 * If FBC is already on, we just have to verify that we can
501 * keep it that way...
502 * Need to disable if:
503 * - more than one pipe is active
504 * - changing FBC params (stride, fence, mode)
505 * - new fb is too large to fit in compressed buffer
506 * - going to an unsupported config (interlace, pixel multiply, etc.)
508 for_each_crtc(dev
, tmp_crtc
) {
509 if (intel_crtc_active(tmp_crtc
) &&
510 to_intel_crtc(tmp_crtc
)->primary_enabled
) {
512 if (set_no_fbc_reason(dev_priv
, FBC_MULTIPLE_PIPES
))
513 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
520 if (!crtc
|| crtc
->primary
->fb
== NULL
) {
521 if (set_no_fbc_reason(dev_priv
, FBC_NO_OUTPUT
))
522 DRM_DEBUG_KMS("no output, disabling\n");
526 intel_crtc
= to_intel_crtc(crtc
);
527 fb
= crtc
->primary
->fb
;
528 obj
= intel_fb_obj(fb
);
529 adjusted_mode
= &intel_crtc
->config
.adjusted_mode
;
531 if (i915
.enable_fbc
< 0) {
532 if (set_no_fbc_reason(dev_priv
, FBC_CHIP_DEFAULT
))
533 DRM_DEBUG_KMS("disabled per chip default\n");
536 if (!i915
.enable_fbc
) {
537 if (set_no_fbc_reason(dev_priv
, FBC_MODULE_PARAM
))
538 DRM_DEBUG_KMS("fbc disabled per module param\n");
541 if ((adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) ||
542 (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLSCAN
)) {
543 if (set_no_fbc_reason(dev_priv
, FBC_UNSUPPORTED_MODE
))
544 DRM_DEBUG_KMS("mode incompatible with compression, "
549 if (INTEL_INFO(dev
)->gen
>= 8 || IS_HASWELL(dev
)) {
552 } else if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5) {
559 if (intel_crtc
->config
.pipe_src_w
> max_width
||
560 intel_crtc
->config
.pipe_src_h
> max_height
) {
561 if (set_no_fbc_reason(dev_priv
, FBC_MODE_TOO_LARGE
))
562 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
565 if ((INTEL_INFO(dev
)->gen
< 4 || HAS_DDI(dev
)) &&
566 intel_crtc
->plane
!= PLANE_A
) {
567 if (set_no_fbc_reason(dev_priv
, FBC_BAD_PLANE
))
568 DRM_DEBUG_KMS("plane not A, disabling compression\n");
572 /* The use of a CPU fence is mandatory in order to detect writes
573 * by the CPU to the scanout and trigger updates to the FBC.
575 if (obj
->tiling_mode
!= I915_TILING_X
||
576 obj
->fence_reg
== I915_FENCE_REG_NONE
) {
577 if (set_no_fbc_reason(dev_priv
, FBC_NOT_TILED
))
578 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
582 /* If the kernel debugger is active, always disable compression */
586 if (i915_gem_stolen_setup_compression(dev
, obj
->base
.size
,
587 drm_format_plane_cpp(fb
->pixel_format
, 0))) {
588 if (set_no_fbc_reason(dev_priv
, FBC_STOLEN_TOO_SMALL
))
589 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
593 /* If the scanout has not changed, don't modify the FBC settings.
594 * Note that we make the fundamental assumption that the fb->obj
595 * cannot be unpinned (and have its GTT offset and fence revoked)
596 * without first being decoupled from the scanout and FBC disabled.
598 if (dev_priv
->fbc
.plane
== intel_crtc
->plane
&&
599 dev_priv
->fbc
.fb_id
== fb
->base
.id
&&
600 dev_priv
->fbc
.y
== crtc
->y
)
603 if (intel_fbc_enabled(dev
)) {
604 /* We update FBC along two paths, after changing fb/crtc
605 * configuration (modeswitching) and after page-flipping
606 * finishes. For the latter, we know that not only did
607 * we disable the FBC at the start of the page-flip
608 * sequence, but also more than one vblank has passed.
610 * For the former case of modeswitching, it is possible
611 * to switch between two FBC valid configurations
612 * instantaneously so we do need to disable the FBC
613 * before we can modify its control registers. We also
614 * have to wait for the next vblank for that to take
615 * effect. However, since we delay enabling FBC we can
616 * assume that a vblank has passed since disabling and
617 * that we can safely alter the registers in the deferred
620 * In the scenario that we go from a valid to invalid
621 * and then back to valid FBC configuration we have
622 * no strict enforcement that a vblank occurred since
623 * disabling the FBC. However, along all current pipe
624 * disabling paths we do need to wait for a vblank at
625 * some point. And we wait before enabling FBC anyway.
627 DRM_DEBUG_KMS("disabling active FBC for update\n");
628 intel_disable_fbc(dev
);
631 intel_enable_fbc(crtc
);
632 dev_priv
->fbc
.no_fbc_reason
= FBC_OK
;
636 /* Multiple disables should be harmless */
637 if (intel_fbc_enabled(dev
)) {
638 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
639 intel_disable_fbc(dev
);
641 i915_gem_stolen_cleanup_compression(dev
);
644 static void i915_pineview_get_mem_freq(struct drm_device
*dev
)
646 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
649 tmp
= I915_READ(CLKCFG
);
651 switch (tmp
& CLKCFG_FSB_MASK
) {
653 dev_priv
->fsb_freq
= 533; /* 133*4 */
656 dev_priv
->fsb_freq
= 800; /* 200*4 */
659 dev_priv
->fsb_freq
= 667; /* 167*4 */
662 dev_priv
->fsb_freq
= 400; /* 100*4 */
666 switch (tmp
& CLKCFG_MEM_MASK
) {
668 dev_priv
->mem_freq
= 533;
671 dev_priv
->mem_freq
= 667;
674 dev_priv
->mem_freq
= 800;
678 /* detect pineview DDR3 setting */
679 tmp
= I915_READ(CSHRDDR3CTL
);
680 dev_priv
->is_ddr3
= (tmp
& CSHRDDR3CTL_DDR3
) ? 1 : 0;
683 static void i915_ironlake_get_mem_freq(struct drm_device
*dev
)
685 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
688 ddrpll
= I915_READ16(DDRMPLL1
);
689 csipll
= I915_READ16(CSIPLL0
);
691 switch (ddrpll
& 0xff) {
693 dev_priv
->mem_freq
= 800;
696 dev_priv
->mem_freq
= 1066;
699 dev_priv
->mem_freq
= 1333;
702 dev_priv
->mem_freq
= 1600;
705 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
707 dev_priv
->mem_freq
= 0;
711 dev_priv
->ips
.r_t
= dev_priv
->mem_freq
;
713 switch (csipll
& 0x3ff) {
715 dev_priv
->fsb_freq
= 3200;
718 dev_priv
->fsb_freq
= 3733;
721 dev_priv
->fsb_freq
= 4266;
724 dev_priv
->fsb_freq
= 4800;
727 dev_priv
->fsb_freq
= 5333;
730 dev_priv
->fsb_freq
= 5866;
733 dev_priv
->fsb_freq
= 6400;
736 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
738 dev_priv
->fsb_freq
= 0;
742 if (dev_priv
->fsb_freq
== 3200) {
743 dev_priv
->ips
.c_m
= 0;
744 } else if (dev_priv
->fsb_freq
> 3200 && dev_priv
->fsb_freq
<= 4800) {
745 dev_priv
->ips
.c_m
= 1;
747 dev_priv
->ips
.c_m
= 2;
751 static const struct cxsr_latency cxsr_latency_table
[] = {
752 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
753 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
754 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
755 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
756 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
758 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
759 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
760 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
761 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
762 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
764 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
765 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
766 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
767 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
768 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
770 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
771 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
772 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
773 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
774 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
776 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
777 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
778 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
779 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
780 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
782 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
783 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
784 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
785 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
786 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
789 static const struct cxsr_latency
*intel_get_cxsr_latency(int is_desktop
,
794 const struct cxsr_latency
*latency
;
797 if (fsb
== 0 || mem
== 0)
800 for (i
= 0; i
< ARRAY_SIZE(cxsr_latency_table
); i
++) {
801 latency
= &cxsr_latency_table
[i
];
802 if (is_desktop
== latency
->is_desktop
&&
803 is_ddr3
== latency
->is_ddr3
&&
804 fsb
== latency
->fsb_freq
&& mem
== latency
->mem_freq
)
808 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
813 void intel_set_memory_cxsr(struct drm_i915_private
*dev_priv
, bool enable
)
815 struct drm_device
*dev
= dev_priv
->dev
;
818 if (IS_VALLEYVIEW(dev
)) {
819 I915_WRITE(FW_BLC_SELF_VLV
, enable
? FW_CSPWRDWNEN
: 0);
820 } else if (IS_G4X(dev
) || IS_CRESTLINE(dev
)) {
821 I915_WRITE(FW_BLC_SELF
, enable
? FW_BLC_SELF_EN
: 0);
822 } else if (IS_PINEVIEW(dev
)) {
823 val
= I915_READ(DSPFW3
) & ~PINEVIEW_SELF_REFRESH_EN
;
824 val
|= enable
? PINEVIEW_SELF_REFRESH_EN
: 0;
825 I915_WRITE(DSPFW3
, val
);
826 } else if (IS_I945G(dev
) || IS_I945GM(dev
)) {
827 val
= enable
? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN
) :
828 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN
);
829 I915_WRITE(FW_BLC_SELF
, val
);
830 } else if (IS_I915GM(dev
)) {
831 val
= enable
? _MASKED_BIT_ENABLE(INSTPM_SELF_EN
) :
832 _MASKED_BIT_DISABLE(INSTPM_SELF_EN
);
833 I915_WRITE(INSTPM
, val
);
838 DRM_DEBUG_KMS("memory self-refresh is %s\n",
839 enable
? "enabled" : "disabled");
843 * Latency for FIFO fetches is dependent on several factors:
844 * - memory configuration (speed, channels)
846 * - current MCH state
847 * It can be fairly high in some situations, so here we assume a fairly
848 * pessimal value. It's a tradeoff between extra memory fetches (if we
849 * set this value too high, the FIFO will fetch frequently to stay full)
850 * and power consumption (set it too low to save power and we might see
851 * FIFO underruns and display "flicker").
853 * A value of 5us seems to be a good balance; safe for very low end
854 * platforms but not overly aggressive on lower latency configs.
856 static const int latency_ns
= 5000;
858 static int i9xx_get_fifo_size(struct drm_device
*dev
, int plane
)
860 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
861 uint32_t dsparb
= I915_READ(DSPARB
);
864 size
= dsparb
& 0x7f;
866 size
= ((dsparb
>> DSPARB_CSTART_SHIFT
) & 0x7f) - size
;
868 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
869 plane
? "B" : "A", size
);
874 static int i830_get_fifo_size(struct drm_device
*dev
, int plane
)
876 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
877 uint32_t dsparb
= I915_READ(DSPARB
);
880 size
= dsparb
& 0x1ff;
882 size
= ((dsparb
>> DSPARB_BEND_SHIFT
) & 0x1ff) - size
;
883 size
>>= 1; /* Convert to cachelines */
885 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
886 plane
? "B" : "A", size
);
891 static int i845_get_fifo_size(struct drm_device
*dev
, int plane
)
893 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
894 uint32_t dsparb
= I915_READ(DSPARB
);
897 size
= dsparb
& 0x7f;
898 size
>>= 2; /* Convert to cachelines */
900 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
907 /* Pineview has different values for various configs */
908 static const struct intel_watermark_params pineview_display_wm
= {
909 .fifo_size
= PINEVIEW_DISPLAY_FIFO
,
910 .max_wm
= PINEVIEW_MAX_WM
,
911 .default_wm
= PINEVIEW_DFT_WM
,
912 .guard_size
= PINEVIEW_GUARD_WM
,
913 .cacheline_size
= PINEVIEW_FIFO_LINE_SIZE
,
915 static const struct intel_watermark_params pineview_display_hplloff_wm
= {
916 .fifo_size
= PINEVIEW_DISPLAY_FIFO
,
917 .max_wm
= PINEVIEW_MAX_WM
,
918 .default_wm
= PINEVIEW_DFT_HPLLOFF_WM
,
919 .guard_size
= PINEVIEW_GUARD_WM
,
920 .cacheline_size
= PINEVIEW_FIFO_LINE_SIZE
,
922 static const struct intel_watermark_params pineview_cursor_wm
= {
923 .fifo_size
= PINEVIEW_CURSOR_FIFO
,
924 .max_wm
= PINEVIEW_CURSOR_MAX_WM
,
925 .default_wm
= PINEVIEW_CURSOR_DFT_WM
,
926 .guard_size
= PINEVIEW_CURSOR_GUARD_WM
,
927 .cacheline_size
= PINEVIEW_FIFO_LINE_SIZE
,
929 static const struct intel_watermark_params pineview_cursor_hplloff_wm
= {
930 .fifo_size
= PINEVIEW_CURSOR_FIFO
,
931 .max_wm
= PINEVIEW_CURSOR_MAX_WM
,
932 .default_wm
= PINEVIEW_CURSOR_DFT_WM
,
933 .guard_size
= PINEVIEW_CURSOR_GUARD_WM
,
934 .cacheline_size
= PINEVIEW_FIFO_LINE_SIZE
,
936 static const struct intel_watermark_params g4x_wm_info
= {
937 .fifo_size
= G4X_FIFO_SIZE
,
938 .max_wm
= G4X_MAX_WM
,
939 .default_wm
= G4X_MAX_WM
,
941 .cacheline_size
= G4X_FIFO_LINE_SIZE
,
943 static const struct intel_watermark_params g4x_cursor_wm_info
= {
944 .fifo_size
= I965_CURSOR_FIFO
,
945 .max_wm
= I965_CURSOR_MAX_WM
,
946 .default_wm
= I965_CURSOR_DFT_WM
,
948 .cacheline_size
= G4X_FIFO_LINE_SIZE
,
950 static const struct intel_watermark_params valleyview_wm_info
= {
951 .fifo_size
= VALLEYVIEW_FIFO_SIZE
,
952 .max_wm
= VALLEYVIEW_MAX_WM
,
953 .default_wm
= VALLEYVIEW_MAX_WM
,
955 .cacheline_size
= G4X_FIFO_LINE_SIZE
,
957 static const struct intel_watermark_params valleyview_cursor_wm_info
= {
958 .fifo_size
= I965_CURSOR_FIFO
,
959 .max_wm
= VALLEYVIEW_CURSOR_MAX_WM
,
960 .default_wm
= I965_CURSOR_DFT_WM
,
962 .cacheline_size
= G4X_FIFO_LINE_SIZE
,
964 static const struct intel_watermark_params i965_cursor_wm_info
= {
965 .fifo_size
= I965_CURSOR_FIFO
,
966 .max_wm
= I965_CURSOR_MAX_WM
,
967 .default_wm
= I965_CURSOR_DFT_WM
,
969 .cacheline_size
= I915_FIFO_LINE_SIZE
,
971 static const struct intel_watermark_params i945_wm_info
= {
972 .fifo_size
= I945_FIFO_SIZE
,
973 .max_wm
= I915_MAX_WM
,
976 .cacheline_size
= I915_FIFO_LINE_SIZE
,
978 static const struct intel_watermark_params i915_wm_info
= {
979 .fifo_size
= I915_FIFO_SIZE
,
980 .max_wm
= I915_MAX_WM
,
983 .cacheline_size
= I915_FIFO_LINE_SIZE
,
985 static const struct intel_watermark_params i830_wm_info
= {
986 .fifo_size
= I855GM_FIFO_SIZE
,
987 .max_wm
= I915_MAX_WM
,
990 .cacheline_size
= I830_FIFO_LINE_SIZE
,
992 static const struct intel_watermark_params i845_wm_info
= {
993 .fifo_size
= I830_FIFO_SIZE
,
994 .max_wm
= I915_MAX_WM
,
997 .cacheline_size
= I830_FIFO_LINE_SIZE
,
1001 * intel_calculate_wm - calculate watermark level
1002 * @clock_in_khz: pixel clock
1003 * @wm: chip FIFO params
1004 * @pixel_size: display pixel size
1005 * @latency_ns: memory latency for the platform
1007 * Calculate the watermark level (the level at which the display plane will
1008 * start fetching from memory again). Each chip has a different display
1009 * FIFO size and allocation, so the caller needs to figure that out and pass
1010 * in the correct intel_watermark_params structure.
1012 * As the pixel clock runs, the FIFO will be drained at a rate that depends
1013 * on the pixel size. When it reaches the watermark level, it'll start
1014 * fetching FIFO line sized based chunks from memory until the FIFO fills
1015 * past the watermark point. If the FIFO drains completely, a FIFO underrun
1016 * will occur, and a display engine hang could result.
1018 static unsigned long intel_calculate_wm(unsigned long clock_in_khz
,
1019 const struct intel_watermark_params
*wm
,
1022 unsigned long latency_ns
)
1024 long entries_required
, wm_size
;
1027 * Note: we need to make sure we don't overflow for various clock &
1029 * clocks go from a few thousand to several hundred thousand.
1030 * latency is usually a few thousand
1032 entries_required
= ((clock_in_khz
/ 1000) * pixel_size
* latency_ns
) /
1034 entries_required
= DIV_ROUND_UP(entries_required
, wm
->cacheline_size
);
1036 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required
);
1038 wm_size
= fifo_size
- (entries_required
+ wm
->guard_size
);
1040 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size
);
1042 /* Don't promote wm_size to unsigned... */
1043 if (wm_size
> (long)wm
->max_wm
)
1044 wm_size
= wm
->max_wm
;
1046 wm_size
= wm
->default_wm
;
1050 static struct drm_crtc
*single_enabled_crtc(struct drm_device
*dev
)
1052 struct drm_crtc
*crtc
, *enabled
= NULL
;
1054 for_each_crtc(dev
, crtc
) {
1055 if (intel_crtc_active(crtc
)) {
1065 static void pineview_update_wm(struct drm_crtc
*unused_crtc
)
1067 struct drm_device
*dev
= unused_crtc
->dev
;
1068 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1069 struct drm_crtc
*crtc
;
1070 const struct cxsr_latency
*latency
;
1074 latency
= intel_get_cxsr_latency(IS_PINEVIEW_G(dev
), dev_priv
->is_ddr3
,
1075 dev_priv
->fsb_freq
, dev_priv
->mem_freq
);
1077 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1078 intel_set_memory_cxsr(dev_priv
, false);
1082 crtc
= single_enabled_crtc(dev
);
1084 const struct drm_display_mode
*adjusted_mode
;
1085 int pixel_size
= crtc
->primary
->fb
->bits_per_pixel
/ 8;
1088 adjusted_mode
= &to_intel_crtc(crtc
)->config
.adjusted_mode
;
1089 clock
= adjusted_mode
->crtc_clock
;
1092 wm
= intel_calculate_wm(clock
, &pineview_display_wm
,
1093 pineview_display_wm
.fifo_size
,
1094 pixel_size
, latency
->display_sr
);
1095 reg
= I915_READ(DSPFW1
);
1096 reg
&= ~DSPFW_SR_MASK
;
1097 reg
|= wm
<< DSPFW_SR_SHIFT
;
1098 I915_WRITE(DSPFW1
, reg
);
1099 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg
);
1102 wm
= intel_calculate_wm(clock
, &pineview_cursor_wm
,
1103 pineview_display_wm
.fifo_size
,
1104 pixel_size
, latency
->cursor_sr
);
1105 reg
= I915_READ(DSPFW3
);
1106 reg
&= ~DSPFW_CURSOR_SR_MASK
;
1107 reg
|= (wm
& 0x3f) << DSPFW_CURSOR_SR_SHIFT
;
1108 I915_WRITE(DSPFW3
, reg
);
1110 /* Display HPLL off SR */
1111 wm
= intel_calculate_wm(clock
, &pineview_display_hplloff_wm
,
1112 pineview_display_hplloff_wm
.fifo_size
,
1113 pixel_size
, latency
->display_hpll_disable
);
1114 reg
= I915_READ(DSPFW3
);
1115 reg
&= ~DSPFW_HPLL_SR_MASK
;
1116 reg
|= wm
& DSPFW_HPLL_SR_MASK
;
1117 I915_WRITE(DSPFW3
, reg
);
1119 /* cursor HPLL off SR */
1120 wm
= intel_calculate_wm(clock
, &pineview_cursor_hplloff_wm
,
1121 pineview_display_hplloff_wm
.fifo_size
,
1122 pixel_size
, latency
->cursor_hpll_disable
);
1123 reg
= I915_READ(DSPFW3
);
1124 reg
&= ~DSPFW_HPLL_CURSOR_MASK
;
1125 reg
|= (wm
& 0x3f) << DSPFW_HPLL_CURSOR_SHIFT
;
1126 I915_WRITE(DSPFW3
, reg
);
1127 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg
);
1129 intel_set_memory_cxsr(dev_priv
, true);
1131 intel_set_memory_cxsr(dev_priv
, false);
1135 static bool g4x_compute_wm0(struct drm_device
*dev
,
1137 const struct intel_watermark_params
*display
,
1138 int display_latency_ns
,
1139 const struct intel_watermark_params
*cursor
,
1140 int cursor_latency_ns
,
1144 struct drm_crtc
*crtc
;
1145 const struct drm_display_mode
*adjusted_mode
;
1146 int htotal
, hdisplay
, clock
, pixel_size
;
1147 int line_time_us
, line_count
;
1148 int entries
, tlb_miss
;
1150 crtc
= intel_get_crtc_for_plane(dev
, plane
);
1151 if (!intel_crtc_active(crtc
)) {
1152 *cursor_wm
= cursor
->guard_size
;
1153 *plane_wm
= display
->guard_size
;
1157 adjusted_mode
= &to_intel_crtc(crtc
)->config
.adjusted_mode
;
1158 clock
= adjusted_mode
->crtc_clock
;
1159 htotal
= adjusted_mode
->crtc_htotal
;
1160 hdisplay
= to_intel_crtc(crtc
)->config
.pipe_src_w
;
1161 pixel_size
= crtc
->primary
->fb
->bits_per_pixel
/ 8;
1163 /* Use the small buffer method to calculate plane watermark */
1164 entries
= ((clock
* pixel_size
/ 1000) * display_latency_ns
) / 1000;
1165 tlb_miss
= display
->fifo_size
*display
->cacheline_size
- hdisplay
* 8;
1167 entries
+= tlb_miss
;
1168 entries
= DIV_ROUND_UP(entries
, display
->cacheline_size
);
1169 *plane_wm
= entries
+ display
->guard_size
;
1170 if (*plane_wm
> (int)display
->max_wm
)
1171 *plane_wm
= display
->max_wm
;
1173 /* Use the large buffer method to calculate cursor watermark */
1174 line_time_us
= max(htotal
* 1000 / clock
, 1);
1175 line_count
= (cursor_latency_ns
/ line_time_us
+ 1000) / 1000;
1176 entries
= line_count
* to_intel_crtc(crtc
)->cursor_width
* pixel_size
;
1177 tlb_miss
= cursor
->fifo_size
*cursor
->cacheline_size
- hdisplay
* 8;
1179 entries
+= tlb_miss
;
1180 entries
= DIV_ROUND_UP(entries
, cursor
->cacheline_size
);
1181 *cursor_wm
= entries
+ cursor
->guard_size
;
1182 if (*cursor_wm
> (int)cursor
->max_wm
)
1183 *cursor_wm
= (int)cursor
->max_wm
;
1189 * Check the wm result.
1191 * If any calculated watermark values is larger than the maximum value that
1192 * can be programmed into the associated watermark register, that watermark
1195 static bool g4x_check_srwm(struct drm_device
*dev
,
1196 int display_wm
, int cursor_wm
,
1197 const struct intel_watermark_params
*display
,
1198 const struct intel_watermark_params
*cursor
)
1200 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1201 display_wm
, cursor_wm
);
1203 if (display_wm
> display
->max_wm
) {
1204 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1205 display_wm
, display
->max_wm
);
1209 if (cursor_wm
> cursor
->max_wm
) {
1210 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1211 cursor_wm
, cursor
->max_wm
);
1215 if (!(display_wm
|| cursor_wm
)) {
1216 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1223 static bool g4x_compute_srwm(struct drm_device
*dev
,
1226 const struct intel_watermark_params
*display
,
1227 const struct intel_watermark_params
*cursor
,
1228 int *display_wm
, int *cursor_wm
)
1230 struct drm_crtc
*crtc
;
1231 const struct drm_display_mode
*adjusted_mode
;
1232 int hdisplay
, htotal
, pixel_size
, clock
;
1233 unsigned long line_time_us
;
1234 int line_count
, line_size
;
1239 *display_wm
= *cursor_wm
= 0;
1243 crtc
= intel_get_crtc_for_plane(dev
, plane
);
1244 adjusted_mode
= &to_intel_crtc(crtc
)->config
.adjusted_mode
;
1245 clock
= adjusted_mode
->crtc_clock
;
1246 htotal
= adjusted_mode
->crtc_htotal
;
1247 hdisplay
= to_intel_crtc(crtc
)->config
.pipe_src_w
;
1248 pixel_size
= crtc
->primary
->fb
->bits_per_pixel
/ 8;
1250 line_time_us
= max(htotal
* 1000 / clock
, 1);
1251 line_count
= (latency_ns
/ line_time_us
+ 1000) / 1000;
1252 line_size
= hdisplay
* pixel_size
;
1254 /* Use the minimum of the small and large buffer method for primary */
1255 small
= ((clock
* pixel_size
/ 1000) * latency_ns
) / 1000;
1256 large
= line_count
* line_size
;
1258 entries
= DIV_ROUND_UP(min(small
, large
), display
->cacheline_size
);
1259 *display_wm
= entries
+ display
->guard_size
;
1261 /* calculate the self-refresh watermark for display cursor */
1262 entries
= line_count
* pixel_size
* to_intel_crtc(crtc
)->cursor_width
;
1263 entries
= DIV_ROUND_UP(entries
, cursor
->cacheline_size
);
1264 *cursor_wm
= entries
+ cursor
->guard_size
;
1266 return g4x_check_srwm(dev
,
1267 *display_wm
, *cursor_wm
,
1271 static bool vlv_compute_drain_latency(struct drm_device
*dev
,
1273 int *plane_prec_mult
,
1275 int *cursor_prec_mult
,
1278 struct drm_crtc
*crtc
;
1279 int clock
, pixel_size
;
1282 crtc
= intel_get_crtc_for_plane(dev
, plane
);
1283 if (!intel_crtc_active(crtc
))
1286 clock
= to_intel_crtc(crtc
)->config
.adjusted_mode
.crtc_clock
;
1287 pixel_size
= crtc
->primary
->fb
->bits_per_pixel
/ 8; /* BPP */
1289 entries
= (clock
/ 1000) * pixel_size
;
1290 *plane_prec_mult
= (entries
> 128) ?
1291 DRAIN_LATENCY_PRECISION_64
: DRAIN_LATENCY_PRECISION_32
;
1292 *plane_dl
= (64 * (*plane_prec_mult
) * 4) / entries
;
1294 entries
= (clock
/ 1000) * 4; /* BPP is always 4 for cursor */
1295 *cursor_prec_mult
= (entries
> 128) ?
1296 DRAIN_LATENCY_PRECISION_64
: DRAIN_LATENCY_PRECISION_32
;
1297 *cursor_dl
= (64 * (*cursor_prec_mult
) * 4) / entries
;
1303 * Update drain latency registers of memory arbiter
1305 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1306 * to be programmed. Each plane has a drain latency multiplier and a drain
1310 static void vlv_update_drain_latency(struct drm_device
*dev
)
1312 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1313 int planea_prec
, planea_dl
, planeb_prec
, planeb_dl
;
1314 int cursora_prec
, cursora_dl
, cursorb_prec
, cursorb_dl
;
1315 int plane_prec_mult
, cursor_prec_mult
; /* Precision multiplier is
1318 /* For plane A, Cursor A */
1319 if (vlv_compute_drain_latency(dev
, 0, &plane_prec_mult
, &planea_dl
,
1320 &cursor_prec_mult
, &cursora_dl
)) {
1321 cursora_prec
= (cursor_prec_mult
== DRAIN_LATENCY_PRECISION_32
) ?
1322 DDL_CURSORA_PRECISION_32
: DDL_CURSORA_PRECISION_64
;
1323 planea_prec
= (plane_prec_mult
== DRAIN_LATENCY_PRECISION_32
) ?
1324 DDL_PLANEA_PRECISION_32
: DDL_PLANEA_PRECISION_64
;
1326 I915_WRITE(VLV_DDL1
, cursora_prec
|
1327 (cursora_dl
<< DDL_CURSORA_SHIFT
) |
1328 planea_prec
| planea_dl
);
1331 /* For plane B, Cursor B */
1332 if (vlv_compute_drain_latency(dev
, 1, &plane_prec_mult
, &planeb_dl
,
1333 &cursor_prec_mult
, &cursorb_dl
)) {
1334 cursorb_prec
= (cursor_prec_mult
== DRAIN_LATENCY_PRECISION_32
) ?
1335 DDL_CURSORB_PRECISION_32
: DDL_CURSORB_PRECISION_64
;
1336 planeb_prec
= (plane_prec_mult
== DRAIN_LATENCY_PRECISION_32
) ?
1337 DDL_PLANEB_PRECISION_32
: DDL_PLANEB_PRECISION_64
;
1339 I915_WRITE(VLV_DDL2
, cursorb_prec
|
1340 (cursorb_dl
<< DDL_CURSORB_SHIFT
) |
1341 planeb_prec
| planeb_dl
);
1345 #define single_plane_enabled(mask) is_power_of_2(mask)
1347 static void valleyview_update_wm(struct drm_crtc
*crtc
)
1349 struct drm_device
*dev
= crtc
->dev
;
1350 static const int sr_latency_ns
= 12000;
1351 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1352 int planea_wm
, planeb_wm
, cursora_wm
, cursorb_wm
;
1353 int plane_sr
, cursor_sr
;
1354 int ignore_plane_sr
, ignore_cursor_sr
;
1355 unsigned int enabled
= 0;
1358 vlv_update_drain_latency(dev
);
1360 if (g4x_compute_wm0(dev
, PIPE_A
,
1361 &valleyview_wm_info
, latency_ns
,
1362 &valleyview_cursor_wm_info
, latency_ns
,
1363 &planea_wm
, &cursora_wm
))
1364 enabled
|= 1 << PIPE_A
;
1366 if (g4x_compute_wm0(dev
, PIPE_B
,
1367 &valleyview_wm_info
, latency_ns
,
1368 &valleyview_cursor_wm_info
, latency_ns
,
1369 &planeb_wm
, &cursorb_wm
))
1370 enabled
|= 1 << PIPE_B
;
1372 if (single_plane_enabled(enabled
) &&
1373 g4x_compute_srwm(dev
, ffs(enabled
) - 1,
1375 &valleyview_wm_info
,
1376 &valleyview_cursor_wm_info
,
1377 &plane_sr
, &ignore_cursor_sr
) &&
1378 g4x_compute_srwm(dev
, ffs(enabled
) - 1,
1380 &valleyview_wm_info
,
1381 &valleyview_cursor_wm_info
,
1382 &ignore_plane_sr
, &cursor_sr
)) {
1383 cxsr_enabled
= true;
1385 cxsr_enabled
= false;
1386 intel_set_memory_cxsr(dev_priv
, false);
1387 plane_sr
= cursor_sr
= 0;
1390 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1391 planea_wm
, cursora_wm
,
1392 planeb_wm
, cursorb_wm
,
1393 plane_sr
, cursor_sr
);
1396 (plane_sr
<< DSPFW_SR_SHIFT
) |
1397 (cursorb_wm
<< DSPFW_CURSORB_SHIFT
) |
1398 (planeb_wm
<< DSPFW_PLANEB_SHIFT
) |
1401 (I915_READ(DSPFW2
) & ~DSPFW_CURSORA_MASK
) |
1402 (cursora_wm
<< DSPFW_CURSORA_SHIFT
));
1404 (I915_READ(DSPFW3
) & ~DSPFW_CURSOR_SR_MASK
) |
1405 (cursor_sr
<< DSPFW_CURSOR_SR_SHIFT
));
1408 intel_set_memory_cxsr(dev_priv
, true);
1411 static void g4x_update_wm(struct drm_crtc
*crtc
)
1413 struct drm_device
*dev
= crtc
->dev
;
1414 static const int sr_latency_ns
= 12000;
1415 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1416 int planea_wm
, planeb_wm
, cursora_wm
, cursorb_wm
;
1417 int plane_sr
, cursor_sr
;
1418 unsigned int enabled
= 0;
1421 if (g4x_compute_wm0(dev
, PIPE_A
,
1422 &g4x_wm_info
, latency_ns
,
1423 &g4x_cursor_wm_info
, latency_ns
,
1424 &planea_wm
, &cursora_wm
))
1425 enabled
|= 1 << PIPE_A
;
1427 if (g4x_compute_wm0(dev
, PIPE_B
,
1428 &g4x_wm_info
, latency_ns
,
1429 &g4x_cursor_wm_info
, latency_ns
,
1430 &planeb_wm
, &cursorb_wm
))
1431 enabled
|= 1 << PIPE_B
;
1433 if (single_plane_enabled(enabled
) &&
1434 g4x_compute_srwm(dev
, ffs(enabled
) - 1,
1437 &g4x_cursor_wm_info
,
1438 &plane_sr
, &cursor_sr
)) {
1439 cxsr_enabled
= true;
1441 cxsr_enabled
= false;
1442 intel_set_memory_cxsr(dev_priv
, false);
1443 plane_sr
= cursor_sr
= 0;
1446 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1447 planea_wm
, cursora_wm
,
1448 planeb_wm
, cursorb_wm
,
1449 plane_sr
, cursor_sr
);
1452 (plane_sr
<< DSPFW_SR_SHIFT
) |
1453 (cursorb_wm
<< DSPFW_CURSORB_SHIFT
) |
1454 (planeb_wm
<< DSPFW_PLANEB_SHIFT
) |
1457 (I915_READ(DSPFW2
) & ~DSPFW_CURSORA_MASK
) |
1458 (cursora_wm
<< DSPFW_CURSORA_SHIFT
));
1459 /* HPLL off in SR has some issues on G4x... disable it */
1461 (I915_READ(DSPFW3
) & ~(DSPFW_HPLL_SR_EN
| DSPFW_CURSOR_SR_MASK
)) |
1462 (cursor_sr
<< DSPFW_CURSOR_SR_SHIFT
));
1465 intel_set_memory_cxsr(dev_priv
, true);
1468 static void i965_update_wm(struct drm_crtc
*unused_crtc
)
1470 struct drm_device
*dev
= unused_crtc
->dev
;
1471 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1472 struct drm_crtc
*crtc
;
1477 /* Calc sr entries for one plane configs */
1478 crtc
= single_enabled_crtc(dev
);
1480 /* self-refresh has much higher latency */
1481 static const int sr_latency_ns
= 12000;
1482 const struct drm_display_mode
*adjusted_mode
=
1483 &to_intel_crtc(crtc
)->config
.adjusted_mode
;
1484 int clock
= adjusted_mode
->crtc_clock
;
1485 int htotal
= adjusted_mode
->crtc_htotal
;
1486 int hdisplay
= to_intel_crtc(crtc
)->config
.pipe_src_w
;
1487 int pixel_size
= crtc
->primary
->fb
->bits_per_pixel
/ 8;
1488 unsigned long line_time_us
;
1491 line_time_us
= max(htotal
* 1000 / clock
, 1);
1493 /* Use ns/us then divide to preserve precision */
1494 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
1495 pixel_size
* hdisplay
;
1496 entries
= DIV_ROUND_UP(entries
, I915_FIFO_LINE_SIZE
);
1497 srwm
= I965_FIFO_SIZE
- entries
;
1501 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1504 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
1505 pixel_size
* to_intel_crtc(crtc
)->cursor_width
;
1506 entries
= DIV_ROUND_UP(entries
,
1507 i965_cursor_wm_info
.cacheline_size
);
1508 cursor_sr
= i965_cursor_wm_info
.fifo_size
-
1509 (entries
+ i965_cursor_wm_info
.guard_size
);
1511 if (cursor_sr
> i965_cursor_wm_info
.max_wm
)
1512 cursor_sr
= i965_cursor_wm_info
.max_wm
;
1514 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1515 "cursor %d\n", srwm
, cursor_sr
);
1517 cxsr_enabled
= true;
1519 cxsr_enabled
= false;
1520 /* Turn off self refresh if both pipes are enabled */
1521 intel_set_memory_cxsr(dev_priv
, false);
1524 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1527 /* 965 has limitations... */
1528 I915_WRITE(DSPFW1
, (srwm
<< DSPFW_SR_SHIFT
) |
1529 (8 << 16) | (8 << 8) | (8 << 0));
1530 I915_WRITE(DSPFW2
, (8 << 8) | (8 << 0));
1531 /* update cursor SR watermark */
1532 I915_WRITE(DSPFW3
, (cursor_sr
<< DSPFW_CURSOR_SR_SHIFT
));
1535 intel_set_memory_cxsr(dev_priv
, true);
1538 static void i9xx_update_wm(struct drm_crtc
*unused_crtc
)
1540 struct drm_device
*dev
= unused_crtc
->dev
;
1541 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1542 const struct intel_watermark_params
*wm_info
;
1547 int planea_wm
, planeb_wm
;
1548 struct drm_crtc
*crtc
, *enabled
= NULL
;
1551 wm_info
= &i945_wm_info
;
1552 else if (!IS_GEN2(dev
))
1553 wm_info
= &i915_wm_info
;
1555 wm_info
= &i830_wm_info
;
1557 fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 0);
1558 crtc
= intel_get_crtc_for_plane(dev
, 0);
1559 if (intel_crtc_active(crtc
)) {
1560 const struct drm_display_mode
*adjusted_mode
;
1561 int cpp
= crtc
->primary
->fb
->bits_per_pixel
/ 8;
1565 adjusted_mode
= &to_intel_crtc(crtc
)->config
.adjusted_mode
;
1566 planea_wm
= intel_calculate_wm(adjusted_mode
->crtc_clock
,
1567 wm_info
, fifo_size
, cpp
,
1571 planea_wm
= fifo_size
- wm_info
->guard_size
;
1573 fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 1);
1574 crtc
= intel_get_crtc_for_plane(dev
, 1);
1575 if (intel_crtc_active(crtc
)) {
1576 const struct drm_display_mode
*adjusted_mode
;
1577 int cpp
= crtc
->primary
->fb
->bits_per_pixel
/ 8;
1581 adjusted_mode
= &to_intel_crtc(crtc
)->config
.adjusted_mode
;
1582 planeb_wm
= intel_calculate_wm(adjusted_mode
->crtc_clock
,
1583 wm_info
, fifo_size
, cpp
,
1585 if (enabled
== NULL
)
1590 planeb_wm
= fifo_size
- wm_info
->guard_size
;
1592 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm
, planeb_wm
);
1594 if (IS_I915GM(dev
) && enabled
) {
1595 struct drm_i915_gem_object
*obj
;
1597 obj
= intel_fb_obj(enabled
->primary
->fb
);
1599 /* self-refresh seems busted with untiled */
1600 if (obj
->tiling_mode
== I915_TILING_NONE
)
1605 * Overlay gets an aggressive default since video jitter is bad.
1609 /* Play safe and disable self-refresh before adjusting watermarks. */
1610 intel_set_memory_cxsr(dev_priv
, false);
1612 /* Calc sr entries for one plane configs */
1613 if (HAS_FW_BLC(dev
) && enabled
) {
1614 /* self-refresh has much higher latency */
1615 static const int sr_latency_ns
= 6000;
1616 const struct drm_display_mode
*adjusted_mode
=
1617 &to_intel_crtc(enabled
)->config
.adjusted_mode
;
1618 int clock
= adjusted_mode
->crtc_clock
;
1619 int htotal
= adjusted_mode
->crtc_htotal
;
1620 int hdisplay
= to_intel_crtc(enabled
)->config
.pipe_src_w
;
1621 int pixel_size
= enabled
->primary
->fb
->bits_per_pixel
/ 8;
1622 unsigned long line_time_us
;
1625 line_time_us
= max(htotal
* 1000 / clock
, 1);
1627 /* Use ns/us then divide to preserve precision */
1628 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
1629 pixel_size
* hdisplay
;
1630 entries
= DIV_ROUND_UP(entries
, wm_info
->cacheline_size
);
1631 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries
);
1632 srwm
= wm_info
->fifo_size
- entries
;
1636 if (IS_I945G(dev
) || IS_I945GM(dev
))
1637 I915_WRITE(FW_BLC_SELF
,
1638 FW_BLC_SELF_FIFO_MASK
| (srwm
& 0xff));
1639 else if (IS_I915GM(dev
))
1640 I915_WRITE(FW_BLC_SELF
, srwm
& 0x3f);
1643 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1644 planea_wm
, planeb_wm
, cwm
, srwm
);
1646 fwater_lo
= ((planeb_wm
& 0x3f) << 16) | (planea_wm
& 0x3f);
1647 fwater_hi
= (cwm
& 0x1f);
1649 /* Set request length to 8 cachelines per fetch */
1650 fwater_lo
= fwater_lo
| (1 << 24) | (1 << 8);
1651 fwater_hi
= fwater_hi
| (1 << 8);
1653 I915_WRITE(FW_BLC
, fwater_lo
);
1654 I915_WRITE(FW_BLC2
, fwater_hi
);
1657 intel_set_memory_cxsr(dev_priv
, true);
1660 static void i845_update_wm(struct drm_crtc
*unused_crtc
)
1662 struct drm_device
*dev
= unused_crtc
->dev
;
1663 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1664 struct drm_crtc
*crtc
;
1665 const struct drm_display_mode
*adjusted_mode
;
1669 crtc
= single_enabled_crtc(dev
);
1673 adjusted_mode
= &to_intel_crtc(crtc
)->config
.adjusted_mode
;
1674 planea_wm
= intel_calculate_wm(adjusted_mode
->crtc_clock
,
1676 dev_priv
->display
.get_fifo_size(dev
, 0),
1678 fwater_lo
= I915_READ(FW_BLC
) & ~0xfff;
1679 fwater_lo
|= (3<<8) | planea_wm
;
1681 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm
);
1683 I915_WRITE(FW_BLC
, fwater_lo
);
1686 static uint32_t ilk_pipe_pixel_rate(struct drm_device
*dev
,
1687 struct drm_crtc
*crtc
)
1689 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1690 uint32_t pixel_rate
;
1692 pixel_rate
= intel_crtc
->config
.adjusted_mode
.crtc_clock
;
1694 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1695 * adjust the pixel_rate here. */
1697 if (intel_crtc
->config
.pch_pfit
.enabled
) {
1698 uint64_t pipe_w
, pipe_h
, pfit_w
, pfit_h
;
1699 uint32_t pfit_size
= intel_crtc
->config
.pch_pfit
.size
;
1701 pipe_w
= intel_crtc
->config
.pipe_src_w
;
1702 pipe_h
= intel_crtc
->config
.pipe_src_h
;
1703 pfit_w
= (pfit_size
>> 16) & 0xFFFF;
1704 pfit_h
= pfit_size
& 0xFFFF;
1705 if (pipe_w
< pfit_w
)
1707 if (pipe_h
< pfit_h
)
1710 pixel_rate
= div_u64((uint64_t) pixel_rate
* pipe_w
* pipe_h
,
1717 /* latency must be in 0.1us units. */
1718 static uint32_t ilk_wm_method1(uint32_t pixel_rate
, uint8_t bytes_per_pixel
,
1723 if (WARN(latency
== 0, "Latency value missing\n"))
1726 ret
= (uint64_t) pixel_rate
* bytes_per_pixel
* latency
;
1727 ret
= DIV_ROUND_UP_ULL(ret
, 64 * 10000) + 2;
1732 /* latency must be in 0.1us units. */
1733 static uint32_t ilk_wm_method2(uint32_t pixel_rate
, uint32_t pipe_htotal
,
1734 uint32_t horiz_pixels
, uint8_t bytes_per_pixel
,
1739 if (WARN(latency
== 0, "Latency value missing\n"))
1742 ret
= (latency
* pixel_rate
) / (pipe_htotal
* 10000);
1743 ret
= (ret
+ 1) * horiz_pixels
* bytes_per_pixel
;
1744 ret
= DIV_ROUND_UP(ret
, 64) + 2;
1748 static uint32_t ilk_wm_fbc(uint32_t pri_val
, uint32_t horiz_pixels
,
1749 uint8_t bytes_per_pixel
)
1751 return DIV_ROUND_UP(pri_val
* 64, horiz_pixels
* bytes_per_pixel
) + 2;
1754 struct ilk_pipe_wm_parameters
{
1756 uint32_t pipe_htotal
;
1757 uint32_t pixel_rate
;
1758 struct intel_plane_wm_parameters pri
;
1759 struct intel_plane_wm_parameters spr
;
1760 struct intel_plane_wm_parameters cur
;
1763 struct ilk_wm_maximums
{
1770 /* used in computing the new watermarks state */
1771 struct intel_wm_config
{
1772 unsigned int num_pipes_active
;
1773 bool sprites_enabled
;
1774 bool sprites_scaled
;
1778 * For both WM_PIPE and WM_LP.
1779 * mem_value must be in 0.1us units.
1781 static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters
*params
,
1785 uint32_t method1
, method2
;
1787 if (!params
->active
|| !params
->pri
.enabled
)
1790 method1
= ilk_wm_method1(params
->pixel_rate
,
1791 params
->pri
.bytes_per_pixel
,
1797 method2
= ilk_wm_method2(params
->pixel_rate
,
1798 params
->pipe_htotal
,
1799 params
->pri
.horiz_pixels
,
1800 params
->pri
.bytes_per_pixel
,
1803 return min(method1
, method2
);
1807 * For both WM_PIPE and WM_LP.
1808 * mem_value must be in 0.1us units.
1810 static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters
*params
,
1813 uint32_t method1
, method2
;
1815 if (!params
->active
|| !params
->spr
.enabled
)
1818 method1
= ilk_wm_method1(params
->pixel_rate
,
1819 params
->spr
.bytes_per_pixel
,
1821 method2
= ilk_wm_method2(params
->pixel_rate
,
1822 params
->pipe_htotal
,
1823 params
->spr
.horiz_pixels
,
1824 params
->spr
.bytes_per_pixel
,
1826 return min(method1
, method2
);
1830 * For both WM_PIPE and WM_LP.
1831 * mem_value must be in 0.1us units.
1833 static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters
*params
,
1836 if (!params
->active
|| !params
->cur
.enabled
)
1839 return ilk_wm_method2(params
->pixel_rate
,
1840 params
->pipe_htotal
,
1841 params
->cur
.horiz_pixels
,
1842 params
->cur
.bytes_per_pixel
,
1846 /* Only for WM_LP. */
1847 static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters
*params
,
1850 if (!params
->active
|| !params
->pri
.enabled
)
1853 return ilk_wm_fbc(pri_val
,
1854 params
->pri
.horiz_pixels
,
1855 params
->pri
.bytes_per_pixel
);
1858 static unsigned int ilk_display_fifo_size(const struct drm_device
*dev
)
1860 if (INTEL_INFO(dev
)->gen
>= 8)
1862 else if (INTEL_INFO(dev
)->gen
>= 7)
1868 static unsigned int ilk_plane_wm_reg_max(const struct drm_device
*dev
,
1869 int level
, bool is_sprite
)
1871 if (INTEL_INFO(dev
)->gen
>= 8)
1872 /* BDW primary/sprite plane watermarks */
1873 return level
== 0 ? 255 : 2047;
1874 else if (INTEL_INFO(dev
)->gen
>= 7)
1875 /* IVB/HSW primary/sprite plane watermarks */
1876 return level
== 0 ? 127 : 1023;
1877 else if (!is_sprite
)
1878 /* ILK/SNB primary plane watermarks */
1879 return level
== 0 ? 127 : 511;
1881 /* ILK/SNB sprite plane watermarks */
1882 return level
== 0 ? 63 : 255;
1885 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device
*dev
,
1888 if (INTEL_INFO(dev
)->gen
>= 7)
1889 return level
== 0 ? 63 : 255;
1891 return level
== 0 ? 31 : 63;
1894 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device
*dev
)
1896 if (INTEL_INFO(dev
)->gen
>= 8)
1902 /* Calculate the maximum primary/sprite plane watermark */
1903 static unsigned int ilk_plane_wm_max(const struct drm_device
*dev
,
1905 const struct intel_wm_config
*config
,
1906 enum intel_ddb_partitioning ddb_partitioning
,
1909 unsigned int fifo_size
= ilk_display_fifo_size(dev
);
1911 /* if sprites aren't enabled, sprites get nothing */
1912 if (is_sprite
&& !config
->sprites_enabled
)
1915 /* HSW allows LP1+ watermarks even with multiple pipes */
1916 if (level
== 0 || config
->num_pipes_active
> 1) {
1917 fifo_size
/= INTEL_INFO(dev
)->num_pipes
;
1920 * For some reason the non self refresh
1921 * FIFO size is only half of the self
1922 * refresh FIFO size on ILK/SNB.
1924 if (INTEL_INFO(dev
)->gen
<= 6)
1928 if (config
->sprites_enabled
) {
1929 /* level 0 is always calculated with 1:1 split */
1930 if (level
> 0 && ddb_partitioning
== INTEL_DDB_PART_5_6
) {
1939 /* clamp to max that the registers can hold */
1940 return min(fifo_size
, ilk_plane_wm_reg_max(dev
, level
, is_sprite
));
1943 /* Calculate the maximum cursor plane watermark */
1944 static unsigned int ilk_cursor_wm_max(const struct drm_device
*dev
,
1946 const struct intel_wm_config
*config
)
1948 /* HSW LP1+ watermarks w/ multiple pipes */
1949 if (level
> 0 && config
->num_pipes_active
> 1)
1952 /* otherwise just report max that registers can hold */
1953 return ilk_cursor_wm_reg_max(dev
, level
);
1956 static void ilk_compute_wm_maximums(const struct drm_device
*dev
,
1958 const struct intel_wm_config
*config
,
1959 enum intel_ddb_partitioning ddb_partitioning
,
1960 struct ilk_wm_maximums
*max
)
1962 max
->pri
= ilk_plane_wm_max(dev
, level
, config
, ddb_partitioning
, false);
1963 max
->spr
= ilk_plane_wm_max(dev
, level
, config
, ddb_partitioning
, true);
1964 max
->cur
= ilk_cursor_wm_max(dev
, level
, config
);
1965 max
->fbc
= ilk_fbc_wm_reg_max(dev
);
1968 static void ilk_compute_wm_reg_maximums(struct drm_device
*dev
,
1970 struct ilk_wm_maximums
*max
)
1972 max
->pri
= ilk_plane_wm_reg_max(dev
, level
, false);
1973 max
->spr
= ilk_plane_wm_reg_max(dev
, level
, true);
1974 max
->cur
= ilk_cursor_wm_reg_max(dev
, level
);
1975 max
->fbc
= ilk_fbc_wm_reg_max(dev
);
1978 static bool ilk_validate_wm_level(int level
,
1979 const struct ilk_wm_maximums
*max
,
1980 struct intel_wm_level
*result
)
1984 /* already determined to be invalid? */
1985 if (!result
->enable
)
1988 result
->enable
= result
->pri_val
<= max
->pri
&&
1989 result
->spr_val
<= max
->spr
&&
1990 result
->cur_val
<= max
->cur
;
1992 ret
= result
->enable
;
1995 * HACK until we can pre-compute everything,
1996 * and thus fail gracefully if LP0 watermarks
1999 if (level
== 0 && !result
->enable
) {
2000 if (result
->pri_val
> max
->pri
)
2001 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2002 level
, result
->pri_val
, max
->pri
);
2003 if (result
->spr_val
> max
->spr
)
2004 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2005 level
, result
->spr_val
, max
->spr
);
2006 if (result
->cur_val
> max
->cur
)
2007 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2008 level
, result
->cur_val
, max
->cur
);
2010 result
->pri_val
= min_t(uint32_t, result
->pri_val
, max
->pri
);
2011 result
->spr_val
= min_t(uint32_t, result
->spr_val
, max
->spr
);
2012 result
->cur_val
= min_t(uint32_t, result
->cur_val
, max
->cur
);
2013 result
->enable
= true;
2019 static void ilk_compute_wm_level(const struct drm_i915_private
*dev_priv
,
2021 const struct ilk_pipe_wm_parameters
*p
,
2022 struct intel_wm_level
*result
)
2024 uint16_t pri_latency
= dev_priv
->wm
.pri_latency
[level
];
2025 uint16_t spr_latency
= dev_priv
->wm
.spr_latency
[level
];
2026 uint16_t cur_latency
= dev_priv
->wm
.cur_latency
[level
];
2028 /* WM1+ latency values stored in 0.5us units */
2035 result
->pri_val
= ilk_compute_pri_wm(p
, pri_latency
, level
);
2036 result
->spr_val
= ilk_compute_spr_wm(p
, spr_latency
);
2037 result
->cur_val
= ilk_compute_cur_wm(p
, cur_latency
);
2038 result
->fbc_val
= ilk_compute_fbc_wm(p
, result
->pri_val
);
2039 result
->enable
= true;
2043 hsw_compute_linetime_wm(struct drm_device
*dev
, struct drm_crtc
*crtc
)
2045 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2046 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2047 struct drm_display_mode
*mode
= &intel_crtc
->config
.adjusted_mode
;
2048 u32 linetime
, ips_linetime
;
2050 if (!intel_crtc_active(crtc
))
2053 /* The WM are computed with base on how long it takes to fill a single
2054 * row at the given clock rate, multiplied by 8.
2056 linetime
= DIV_ROUND_CLOSEST(mode
->crtc_htotal
* 1000 * 8,
2058 ips_linetime
= DIV_ROUND_CLOSEST(mode
->crtc_htotal
* 1000 * 8,
2059 intel_ddi_get_cdclk_freq(dev_priv
));
2061 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime
) |
2062 PIPE_WM_LINETIME_TIME(linetime
);
2065 static void intel_read_wm_latency(struct drm_device
*dev
, uint16_t wm
[5])
2067 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2069 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2070 uint64_t sskpd
= I915_READ64(MCH_SSKPD
);
2072 wm
[0] = (sskpd
>> 56) & 0xFF;
2074 wm
[0] = sskpd
& 0xF;
2075 wm
[1] = (sskpd
>> 4) & 0xFF;
2076 wm
[2] = (sskpd
>> 12) & 0xFF;
2077 wm
[3] = (sskpd
>> 20) & 0x1FF;
2078 wm
[4] = (sskpd
>> 32) & 0x1FF;
2079 } else if (INTEL_INFO(dev
)->gen
>= 6) {
2080 uint32_t sskpd
= I915_READ(MCH_SSKPD
);
2082 wm
[0] = (sskpd
>> SSKPD_WM0_SHIFT
) & SSKPD_WM_MASK
;
2083 wm
[1] = (sskpd
>> SSKPD_WM1_SHIFT
) & SSKPD_WM_MASK
;
2084 wm
[2] = (sskpd
>> SSKPD_WM2_SHIFT
) & SSKPD_WM_MASK
;
2085 wm
[3] = (sskpd
>> SSKPD_WM3_SHIFT
) & SSKPD_WM_MASK
;
2086 } else if (INTEL_INFO(dev
)->gen
>= 5) {
2087 uint32_t mltr
= I915_READ(MLTR_ILK
);
2089 /* ILK primary LP0 latency is 700 ns */
2091 wm
[1] = (mltr
>> MLTR_WM1_SHIFT
) & ILK_SRLT_MASK
;
2092 wm
[2] = (mltr
>> MLTR_WM2_SHIFT
) & ILK_SRLT_MASK
;
2096 static void intel_fixup_spr_wm_latency(struct drm_device
*dev
, uint16_t wm
[5])
2098 /* ILK sprite LP0 latency is 1300 ns */
2099 if (INTEL_INFO(dev
)->gen
== 5)
2103 static void intel_fixup_cur_wm_latency(struct drm_device
*dev
, uint16_t wm
[5])
2105 /* ILK cursor LP0 latency is 1300 ns */
2106 if (INTEL_INFO(dev
)->gen
== 5)
2109 /* WaDoubleCursorLP3Latency:ivb */
2110 if (IS_IVYBRIDGE(dev
))
2114 int ilk_wm_max_level(const struct drm_device
*dev
)
2116 /* how many WM levels are we expecting */
2117 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2119 else if (INTEL_INFO(dev
)->gen
>= 6)
2125 static void intel_print_wm_latency(struct drm_device
*dev
,
2127 const uint16_t wm
[5])
2129 int level
, max_level
= ilk_wm_max_level(dev
);
2131 for (level
= 0; level
<= max_level
; level
++) {
2132 unsigned int latency
= wm
[level
];
2135 DRM_ERROR("%s WM%d latency not provided\n",
2140 /* WM1+ latency values in 0.5us units */
2144 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2145 name
, level
, wm
[level
],
2146 latency
/ 10, latency
% 10);
2150 static bool ilk_increase_wm_latency(struct drm_i915_private
*dev_priv
,
2151 uint16_t wm
[5], uint16_t min
)
2153 int level
, max_level
= ilk_wm_max_level(dev_priv
->dev
);
2158 wm
[0] = max(wm
[0], min
);
2159 for (level
= 1; level
<= max_level
; level
++)
2160 wm
[level
] = max_t(uint16_t, wm
[level
], DIV_ROUND_UP(min
, 5));
2165 static void snb_wm_latency_quirk(struct drm_device
*dev
)
2167 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2171 * The BIOS provided WM memory latency values are often
2172 * inadequate for high resolution displays. Adjust them.
2174 changed
= ilk_increase_wm_latency(dev_priv
, dev_priv
->wm
.pri_latency
, 12) |
2175 ilk_increase_wm_latency(dev_priv
, dev_priv
->wm
.spr_latency
, 12) |
2176 ilk_increase_wm_latency(dev_priv
, dev_priv
->wm
.cur_latency
, 12);
2181 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2182 intel_print_wm_latency(dev
, "Primary", dev_priv
->wm
.pri_latency
);
2183 intel_print_wm_latency(dev
, "Sprite", dev_priv
->wm
.spr_latency
);
2184 intel_print_wm_latency(dev
, "Cursor", dev_priv
->wm
.cur_latency
);
2187 static void ilk_setup_wm_latency(struct drm_device
*dev
)
2189 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2191 intel_read_wm_latency(dev
, dev_priv
->wm
.pri_latency
);
2193 memcpy(dev_priv
->wm
.spr_latency
, dev_priv
->wm
.pri_latency
,
2194 sizeof(dev_priv
->wm
.pri_latency
));
2195 memcpy(dev_priv
->wm
.cur_latency
, dev_priv
->wm
.pri_latency
,
2196 sizeof(dev_priv
->wm
.pri_latency
));
2198 intel_fixup_spr_wm_latency(dev
, dev_priv
->wm
.spr_latency
);
2199 intel_fixup_cur_wm_latency(dev
, dev_priv
->wm
.cur_latency
);
2201 intel_print_wm_latency(dev
, "Primary", dev_priv
->wm
.pri_latency
);
2202 intel_print_wm_latency(dev
, "Sprite", dev_priv
->wm
.spr_latency
);
2203 intel_print_wm_latency(dev
, "Cursor", dev_priv
->wm
.cur_latency
);
2206 snb_wm_latency_quirk(dev
);
2209 static void ilk_compute_wm_parameters(struct drm_crtc
*crtc
,
2210 struct ilk_pipe_wm_parameters
*p
)
2212 struct drm_device
*dev
= crtc
->dev
;
2213 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2214 enum pipe pipe
= intel_crtc
->pipe
;
2215 struct drm_plane
*plane
;
2217 if (!intel_crtc_active(crtc
))
2221 p
->pipe_htotal
= intel_crtc
->config
.adjusted_mode
.crtc_htotal
;
2222 p
->pixel_rate
= ilk_pipe_pixel_rate(dev
, crtc
);
2223 p
->pri
.bytes_per_pixel
= crtc
->primary
->fb
->bits_per_pixel
/ 8;
2224 p
->cur
.bytes_per_pixel
= 4;
2225 p
->pri
.horiz_pixels
= intel_crtc
->config
.pipe_src_w
;
2226 p
->cur
.horiz_pixels
= intel_crtc
->cursor_width
;
2227 /* TODO: for now, assume primary and cursor planes are always enabled. */
2228 p
->pri
.enabled
= true;
2229 p
->cur
.enabled
= true;
2231 drm_for_each_legacy_plane(plane
, &dev
->mode_config
.plane_list
) {
2232 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
2234 if (intel_plane
->pipe
== pipe
) {
2235 p
->spr
= intel_plane
->wm
;
2241 static void ilk_compute_wm_config(struct drm_device
*dev
,
2242 struct intel_wm_config
*config
)
2244 struct intel_crtc
*intel_crtc
;
2246 /* Compute the currently _active_ config */
2247 for_each_intel_crtc(dev
, intel_crtc
) {
2248 const struct intel_pipe_wm
*wm
= &intel_crtc
->wm
.active
;
2250 if (!wm
->pipe_enabled
)
2253 config
->sprites_enabled
|= wm
->sprites_enabled
;
2254 config
->sprites_scaled
|= wm
->sprites_scaled
;
2255 config
->num_pipes_active
++;
2259 /* Compute new watermarks for the pipe */
2260 static bool intel_compute_pipe_wm(struct drm_crtc
*crtc
,
2261 const struct ilk_pipe_wm_parameters
*params
,
2262 struct intel_pipe_wm
*pipe_wm
)
2264 struct drm_device
*dev
= crtc
->dev
;
2265 const struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2266 int level
, max_level
= ilk_wm_max_level(dev
);
2267 /* LP0 watermark maximums depend on this pipe alone */
2268 struct intel_wm_config config
= {
2269 .num_pipes_active
= 1,
2270 .sprites_enabled
= params
->spr
.enabled
,
2271 .sprites_scaled
= params
->spr
.scaled
,
2273 struct ilk_wm_maximums max
;
2275 pipe_wm
->pipe_enabled
= params
->active
;
2276 pipe_wm
->sprites_enabled
= params
->spr
.enabled
;
2277 pipe_wm
->sprites_scaled
= params
->spr
.scaled
;
2279 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2280 if (INTEL_INFO(dev
)->gen
<= 6 && params
->spr
.enabled
)
2283 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2284 if (params
->spr
.scaled
)
2287 ilk_compute_wm_level(dev_priv
, 0, params
, &pipe_wm
->wm
[0]);
2289 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2290 pipe_wm
->linetime
= hsw_compute_linetime_wm(dev
, crtc
);
2292 /* LP0 watermarks always use 1/2 DDB partitioning */
2293 ilk_compute_wm_maximums(dev
, 0, &config
, INTEL_DDB_PART_1_2
, &max
);
2295 /* At least LP0 must be valid */
2296 if (!ilk_validate_wm_level(0, &max
, &pipe_wm
->wm
[0]))
2299 ilk_compute_wm_reg_maximums(dev
, 1, &max
);
2301 for (level
= 1; level
<= max_level
; level
++) {
2302 struct intel_wm_level wm
= {};
2304 ilk_compute_wm_level(dev_priv
, level
, params
, &wm
);
2307 * Disable any watermark level that exceeds the
2308 * register maximums since such watermarks are
2311 if (!ilk_validate_wm_level(level
, &max
, &wm
))
2314 pipe_wm
->wm
[level
] = wm
;
2321 * Merge the watermarks from all active pipes for a specific level.
2323 static void ilk_merge_wm_level(struct drm_device
*dev
,
2325 struct intel_wm_level
*ret_wm
)
2327 const struct intel_crtc
*intel_crtc
;
2329 ret_wm
->enable
= true;
2331 for_each_intel_crtc(dev
, intel_crtc
) {
2332 const struct intel_pipe_wm
*active
= &intel_crtc
->wm
.active
;
2333 const struct intel_wm_level
*wm
= &active
->wm
[level
];
2335 if (!active
->pipe_enabled
)
2339 * The watermark values may have been used in the past,
2340 * so we must maintain them in the registers for some
2341 * time even if the level is now disabled.
2344 ret_wm
->enable
= false;
2346 ret_wm
->pri_val
= max(ret_wm
->pri_val
, wm
->pri_val
);
2347 ret_wm
->spr_val
= max(ret_wm
->spr_val
, wm
->spr_val
);
2348 ret_wm
->cur_val
= max(ret_wm
->cur_val
, wm
->cur_val
);
2349 ret_wm
->fbc_val
= max(ret_wm
->fbc_val
, wm
->fbc_val
);
2354 * Merge all low power watermarks for all active pipes.
2356 static void ilk_wm_merge(struct drm_device
*dev
,
2357 const struct intel_wm_config
*config
,
2358 const struct ilk_wm_maximums
*max
,
2359 struct intel_pipe_wm
*merged
)
2361 int level
, max_level
= ilk_wm_max_level(dev
);
2362 int last_enabled_level
= max_level
;
2364 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2365 if ((INTEL_INFO(dev
)->gen
<= 6 || IS_IVYBRIDGE(dev
)) &&
2366 config
->num_pipes_active
> 1)
2369 /* ILK: FBC WM must be disabled always */
2370 merged
->fbc_wm_enabled
= INTEL_INFO(dev
)->gen
>= 6;
2372 /* merge each WM1+ level */
2373 for (level
= 1; level
<= max_level
; level
++) {
2374 struct intel_wm_level
*wm
= &merged
->wm
[level
];
2376 ilk_merge_wm_level(dev
, level
, wm
);
2378 if (level
> last_enabled_level
)
2380 else if (!ilk_validate_wm_level(level
, max
, wm
))
2381 /* make sure all following levels get disabled */
2382 last_enabled_level
= level
- 1;
2385 * The spec says it is preferred to disable
2386 * FBC WMs instead of disabling a WM level.
2388 if (wm
->fbc_val
> max
->fbc
) {
2390 merged
->fbc_wm_enabled
= false;
2395 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2397 * FIXME this is racy. FBC might get enabled later.
2398 * What we should check here is whether FBC can be
2399 * enabled sometime later.
2401 if (IS_GEN5(dev
) && !merged
->fbc_wm_enabled
&& intel_fbc_enabled(dev
)) {
2402 for (level
= 2; level
<= max_level
; level
++) {
2403 struct intel_wm_level
*wm
= &merged
->wm
[level
];
2410 static int ilk_wm_lp_to_level(int wm_lp
, const struct intel_pipe_wm
*pipe_wm
)
2412 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2413 return wm_lp
+ (wm_lp
>= 2 && pipe_wm
->wm
[4].enable
);
2416 /* The value we need to program into the WM_LPx latency field */
2417 static unsigned int ilk_wm_lp_latency(struct drm_device
*dev
, int level
)
2419 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2421 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2424 return dev_priv
->wm
.pri_latency
[level
];
2427 static void ilk_compute_wm_results(struct drm_device
*dev
,
2428 const struct intel_pipe_wm
*merged
,
2429 enum intel_ddb_partitioning partitioning
,
2430 struct ilk_wm_values
*results
)
2432 struct intel_crtc
*intel_crtc
;
2435 results
->enable_fbc_wm
= merged
->fbc_wm_enabled
;
2436 results
->partitioning
= partitioning
;
2438 /* LP1+ register values */
2439 for (wm_lp
= 1; wm_lp
<= 3; wm_lp
++) {
2440 const struct intel_wm_level
*r
;
2442 level
= ilk_wm_lp_to_level(wm_lp
, merged
);
2444 r
= &merged
->wm
[level
];
2447 * Maintain the watermark values even if the level is
2448 * disabled. Doing otherwise could cause underruns.
2450 results
->wm_lp
[wm_lp
- 1] =
2451 (ilk_wm_lp_latency(dev
, level
) << WM1_LP_LATENCY_SHIFT
) |
2452 (r
->pri_val
<< WM1_LP_SR_SHIFT
) |
2456 results
->wm_lp
[wm_lp
- 1] |= WM1_LP_SR_EN
;
2458 if (INTEL_INFO(dev
)->gen
>= 8)
2459 results
->wm_lp
[wm_lp
- 1] |=
2460 r
->fbc_val
<< WM1_LP_FBC_SHIFT_BDW
;
2462 results
->wm_lp
[wm_lp
- 1] |=
2463 r
->fbc_val
<< WM1_LP_FBC_SHIFT
;
2466 * Always set WM1S_LP_EN when spr_val != 0, even if the
2467 * level is disabled. Doing otherwise could cause underruns.
2469 if (INTEL_INFO(dev
)->gen
<= 6 && r
->spr_val
) {
2470 WARN_ON(wm_lp
!= 1);
2471 results
->wm_lp_spr
[wm_lp
- 1] = WM1S_LP_EN
| r
->spr_val
;
2473 results
->wm_lp_spr
[wm_lp
- 1] = r
->spr_val
;
2476 /* LP0 register values */
2477 for_each_intel_crtc(dev
, intel_crtc
) {
2478 enum pipe pipe
= intel_crtc
->pipe
;
2479 const struct intel_wm_level
*r
=
2480 &intel_crtc
->wm
.active
.wm
[0];
2482 if (WARN_ON(!r
->enable
))
2485 results
->wm_linetime
[pipe
] = intel_crtc
->wm
.active
.linetime
;
2487 results
->wm_pipe
[pipe
] =
2488 (r
->pri_val
<< WM0_PIPE_PLANE_SHIFT
) |
2489 (r
->spr_val
<< WM0_PIPE_SPRITE_SHIFT
) |
2494 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2495 * case both are at the same level. Prefer r1 in case they're the same. */
2496 static struct intel_pipe_wm
*ilk_find_best_result(struct drm_device
*dev
,
2497 struct intel_pipe_wm
*r1
,
2498 struct intel_pipe_wm
*r2
)
2500 int level
, max_level
= ilk_wm_max_level(dev
);
2501 int level1
= 0, level2
= 0;
2503 for (level
= 1; level
<= max_level
; level
++) {
2504 if (r1
->wm
[level
].enable
)
2506 if (r2
->wm
[level
].enable
)
2510 if (level1
== level2
) {
2511 if (r2
->fbc_wm_enabled
&& !r1
->fbc_wm_enabled
)
2515 } else if (level1
> level2
) {
2522 /* dirty bits used to track which watermarks need changes */
2523 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2524 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2525 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2526 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2527 #define WM_DIRTY_FBC (1 << 24)
2528 #define WM_DIRTY_DDB (1 << 25)
2530 static unsigned int ilk_compute_wm_dirty(struct drm_device
*dev
,
2531 const struct ilk_wm_values
*old
,
2532 const struct ilk_wm_values
*new)
2534 unsigned int dirty
= 0;
2538 for_each_pipe(pipe
) {
2539 if (old
->wm_linetime
[pipe
] != new->wm_linetime
[pipe
]) {
2540 dirty
|= WM_DIRTY_LINETIME(pipe
);
2541 /* Must disable LP1+ watermarks too */
2542 dirty
|= WM_DIRTY_LP_ALL
;
2545 if (old
->wm_pipe
[pipe
] != new->wm_pipe
[pipe
]) {
2546 dirty
|= WM_DIRTY_PIPE(pipe
);
2547 /* Must disable LP1+ watermarks too */
2548 dirty
|= WM_DIRTY_LP_ALL
;
2552 if (old
->enable_fbc_wm
!= new->enable_fbc_wm
) {
2553 dirty
|= WM_DIRTY_FBC
;
2554 /* Must disable LP1+ watermarks too */
2555 dirty
|= WM_DIRTY_LP_ALL
;
2558 if (old
->partitioning
!= new->partitioning
) {
2559 dirty
|= WM_DIRTY_DDB
;
2560 /* Must disable LP1+ watermarks too */
2561 dirty
|= WM_DIRTY_LP_ALL
;
2564 /* LP1+ watermarks already deemed dirty, no need to continue */
2565 if (dirty
& WM_DIRTY_LP_ALL
)
2568 /* Find the lowest numbered LP1+ watermark in need of an update... */
2569 for (wm_lp
= 1; wm_lp
<= 3; wm_lp
++) {
2570 if (old
->wm_lp
[wm_lp
- 1] != new->wm_lp
[wm_lp
- 1] ||
2571 old
->wm_lp_spr
[wm_lp
- 1] != new->wm_lp_spr
[wm_lp
- 1])
2575 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2576 for (; wm_lp
<= 3; wm_lp
++)
2577 dirty
|= WM_DIRTY_LP(wm_lp
);
2582 static bool _ilk_disable_lp_wm(struct drm_i915_private
*dev_priv
,
2585 struct ilk_wm_values
*previous
= &dev_priv
->wm
.hw
;
2586 bool changed
= false;
2588 if (dirty
& WM_DIRTY_LP(3) && previous
->wm_lp
[2] & WM1_LP_SR_EN
) {
2589 previous
->wm_lp
[2] &= ~WM1_LP_SR_EN
;
2590 I915_WRITE(WM3_LP_ILK
, previous
->wm_lp
[2]);
2593 if (dirty
& WM_DIRTY_LP(2) && previous
->wm_lp
[1] & WM1_LP_SR_EN
) {
2594 previous
->wm_lp
[1] &= ~WM1_LP_SR_EN
;
2595 I915_WRITE(WM2_LP_ILK
, previous
->wm_lp
[1]);
2598 if (dirty
& WM_DIRTY_LP(1) && previous
->wm_lp
[0] & WM1_LP_SR_EN
) {
2599 previous
->wm_lp
[0] &= ~WM1_LP_SR_EN
;
2600 I915_WRITE(WM1_LP_ILK
, previous
->wm_lp
[0]);
2605 * Don't touch WM1S_LP_EN here.
2606 * Doing so could cause underruns.
2613 * The spec says we shouldn't write when we don't need, because every write
2614 * causes WMs to be re-evaluated, expending some power.
2616 static void ilk_write_wm_values(struct drm_i915_private
*dev_priv
,
2617 struct ilk_wm_values
*results
)
2619 struct drm_device
*dev
= dev_priv
->dev
;
2620 struct ilk_wm_values
*previous
= &dev_priv
->wm
.hw
;
2624 dirty
= ilk_compute_wm_dirty(dev
, previous
, results
);
2628 _ilk_disable_lp_wm(dev_priv
, dirty
);
2630 if (dirty
& WM_DIRTY_PIPE(PIPE_A
))
2631 I915_WRITE(WM0_PIPEA_ILK
, results
->wm_pipe
[0]);
2632 if (dirty
& WM_DIRTY_PIPE(PIPE_B
))
2633 I915_WRITE(WM0_PIPEB_ILK
, results
->wm_pipe
[1]);
2634 if (dirty
& WM_DIRTY_PIPE(PIPE_C
))
2635 I915_WRITE(WM0_PIPEC_IVB
, results
->wm_pipe
[2]);
2637 if (dirty
& WM_DIRTY_LINETIME(PIPE_A
))
2638 I915_WRITE(PIPE_WM_LINETIME(PIPE_A
), results
->wm_linetime
[0]);
2639 if (dirty
& WM_DIRTY_LINETIME(PIPE_B
))
2640 I915_WRITE(PIPE_WM_LINETIME(PIPE_B
), results
->wm_linetime
[1]);
2641 if (dirty
& WM_DIRTY_LINETIME(PIPE_C
))
2642 I915_WRITE(PIPE_WM_LINETIME(PIPE_C
), results
->wm_linetime
[2]);
2644 if (dirty
& WM_DIRTY_DDB
) {
2645 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2646 val
= I915_READ(WM_MISC
);
2647 if (results
->partitioning
== INTEL_DDB_PART_1_2
)
2648 val
&= ~WM_MISC_DATA_PARTITION_5_6
;
2650 val
|= WM_MISC_DATA_PARTITION_5_6
;
2651 I915_WRITE(WM_MISC
, val
);
2653 val
= I915_READ(DISP_ARB_CTL2
);
2654 if (results
->partitioning
== INTEL_DDB_PART_1_2
)
2655 val
&= ~DISP_DATA_PARTITION_5_6
;
2657 val
|= DISP_DATA_PARTITION_5_6
;
2658 I915_WRITE(DISP_ARB_CTL2
, val
);
2662 if (dirty
& WM_DIRTY_FBC
) {
2663 val
= I915_READ(DISP_ARB_CTL
);
2664 if (results
->enable_fbc_wm
)
2665 val
&= ~DISP_FBC_WM_DIS
;
2667 val
|= DISP_FBC_WM_DIS
;
2668 I915_WRITE(DISP_ARB_CTL
, val
);
2671 if (dirty
& WM_DIRTY_LP(1) &&
2672 previous
->wm_lp_spr
[0] != results
->wm_lp_spr
[0])
2673 I915_WRITE(WM1S_LP_ILK
, results
->wm_lp_spr
[0]);
2675 if (INTEL_INFO(dev
)->gen
>= 7) {
2676 if (dirty
& WM_DIRTY_LP(2) && previous
->wm_lp_spr
[1] != results
->wm_lp_spr
[1])
2677 I915_WRITE(WM2S_LP_IVB
, results
->wm_lp_spr
[1]);
2678 if (dirty
& WM_DIRTY_LP(3) && previous
->wm_lp_spr
[2] != results
->wm_lp_spr
[2])
2679 I915_WRITE(WM3S_LP_IVB
, results
->wm_lp_spr
[2]);
2682 if (dirty
& WM_DIRTY_LP(1) && previous
->wm_lp
[0] != results
->wm_lp
[0])
2683 I915_WRITE(WM1_LP_ILK
, results
->wm_lp
[0]);
2684 if (dirty
& WM_DIRTY_LP(2) && previous
->wm_lp
[1] != results
->wm_lp
[1])
2685 I915_WRITE(WM2_LP_ILK
, results
->wm_lp
[1]);
2686 if (dirty
& WM_DIRTY_LP(3) && previous
->wm_lp
[2] != results
->wm_lp
[2])
2687 I915_WRITE(WM3_LP_ILK
, results
->wm_lp
[2]);
2689 dev_priv
->wm
.hw
= *results
;
2692 static bool ilk_disable_lp_wm(struct drm_device
*dev
)
2694 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2696 return _ilk_disable_lp_wm(dev_priv
, WM_DIRTY_LP_ALL
);
2699 static void ilk_update_wm(struct drm_crtc
*crtc
)
2701 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2702 struct drm_device
*dev
= crtc
->dev
;
2703 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2704 struct ilk_wm_maximums max
;
2705 struct ilk_pipe_wm_parameters params
= {};
2706 struct ilk_wm_values results
= {};
2707 enum intel_ddb_partitioning partitioning
;
2708 struct intel_pipe_wm pipe_wm
= {};
2709 struct intel_pipe_wm lp_wm_1_2
= {}, lp_wm_5_6
= {}, *best_lp_wm
;
2710 struct intel_wm_config config
= {};
2712 ilk_compute_wm_parameters(crtc
, ¶ms
);
2714 intel_compute_pipe_wm(crtc
, ¶ms
, &pipe_wm
);
2716 if (!memcmp(&intel_crtc
->wm
.active
, &pipe_wm
, sizeof(pipe_wm
)))
2719 intel_crtc
->wm
.active
= pipe_wm
;
2721 ilk_compute_wm_config(dev
, &config
);
2723 ilk_compute_wm_maximums(dev
, 1, &config
, INTEL_DDB_PART_1_2
, &max
);
2724 ilk_wm_merge(dev
, &config
, &max
, &lp_wm_1_2
);
2726 /* 5/6 split only in single pipe config on IVB+ */
2727 if (INTEL_INFO(dev
)->gen
>= 7 &&
2728 config
.num_pipes_active
== 1 && config
.sprites_enabled
) {
2729 ilk_compute_wm_maximums(dev
, 1, &config
, INTEL_DDB_PART_5_6
, &max
);
2730 ilk_wm_merge(dev
, &config
, &max
, &lp_wm_5_6
);
2732 best_lp_wm
= ilk_find_best_result(dev
, &lp_wm_1_2
, &lp_wm_5_6
);
2734 best_lp_wm
= &lp_wm_1_2
;
2737 partitioning
= (best_lp_wm
== &lp_wm_1_2
) ?
2738 INTEL_DDB_PART_1_2
: INTEL_DDB_PART_5_6
;
2740 ilk_compute_wm_results(dev
, best_lp_wm
, partitioning
, &results
);
2742 ilk_write_wm_values(dev_priv
, &results
);
2746 ilk_update_sprite_wm(struct drm_plane
*plane
,
2747 struct drm_crtc
*crtc
,
2748 uint32_t sprite_width
, uint32_t sprite_height
,
2749 int pixel_size
, bool enabled
, bool scaled
)
2751 struct drm_device
*dev
= plane
->dev
;
2752 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
2754 intel_plane
->wm
.enabled
= enabled
;
2755 intel_plane
->wm
.scaled
= scaled
;
2756 intel_plane
->wm
.horiz_pixels
= sprite_width
;
2757 intel_plane
->wm
.vert_pixels
= sprite_width
;
2758 intel_plane
->wm
.bytes_per_pixel
= pixel_size
;
2761 * IVB workaround: must disable low power watermarks for at least
2762 * one frame before enabling scaling. LP watermarks can be re-enabled
2763 * when scaling is disabled.
2765 * WaCxSRDisabledForSpriteScaling:ivb
2767 if (IS_IVYBRIDGE(dev
) && scaled
&& ilk_disable_lp_wm(dev
))
2768 intel_wait_for_vblank(dev
, intel_plane
->pipe
);
2770 ilk_update_wm(crtc
);
2773 static void ilk_pipe_wm_get_hw_state(struct drm_crtc
*crtc
)
2775 struct drm_device
*dev
= crtc
->dev
;
2776 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2777 struct ilk_wm_values
*hw
= &dev_priv
->wm
.hw
;
2778 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2779 struct intel_pipe_wm
*active
= &intel_crtc
->wm
.active
;
2780 enum pipe pipe
= intel_crtc
->pipe
;
2781 static const unsigned int wm0_pipe_reg
[] = {
2782 [PIPE_A
] = WM0_PIPEA_ILK
,
2783 [PIPE_B
] = WM0_PIPEB_ILK
,
2784 [PIPE_C
] = WM0_PIPEC_IVB
,
2787 hw
->wm_pipe
[pipe
] = I915_READ(wm0_pipe_reg
[pipe
]);
2788 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2789 hw
->wm_linetime
[pipe
] = I915_READ(PIPE_WM_LINETIME(pipe
));
2791 active
->pipe_enabled
= intel_crtc_active(crtc
);
2793 if (active
->pipe_enabled
) {
2794 u32 tmp
= hw
->wm_pipe
[pipe
];
2797 * For active pipes LP0 watermark is marked as
2798 * enabled, and LP1+ watermaks as disabled since
2799 * we can't really reverse compute them in case
2800 * multiple pipes are active.
2802 active
->wm
[0].enable
= true;
2803 active
->wm
[0].pri_val
= (tmp
& WM0_PIPE_PLANE_MASK
) >> WM0_PIPE_PLANE_SHIFT
;
2804 active
->wm
[0].spr_val
= (tmp
& WM0_PIPE_SPRITE_MASK
) >> WM0_PIPE_SPRITE_SHIFT
;
2805 active
->wm
[0].cur_val
= tmp
& WM0_PIPE_CURSOR_MASK
;
2806 active
->linetime
= hw
->wm_linetime
[pipe
];
2808 int level
, max_level
= ilk_wm_max_level(dev
);
2811 * For inactive pipes, all watermark levels
2812 * should be marked as enabled but zeroed,
2813 * which is what we'd compute them to.
2815 for (level
= 0; level
<= max_level
; level
++)
2816 active
->wm
[level
].enable
= true;
2820 void ilk_wm_get_hw_state(struct drm_device
*dev
)
2822 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2823 struct ilk_wm_values
*hw
= &dev_priv
->wm
.hw
;
2824 struct drm_crtc
*crtc
;
2826 for_each_crtc(dev
, crtc
)
2827 ilk_pipe_wm_get_hw_state(crtc
);
2829 hw
->wm_lp
[0] = I915_READ(WM1_LP_ILK
);
2830 hw
->wm_lp
[1] = I915_READ(WM2_LP_ILK
);
2831 hw
->wm_lp
[2] = I915_READ(WM3_LP_ILK
);
2833 hw
->wm_lp_spr
[0] = I915_READ(WM1S_LP_ILK
);
2834 if (INTEL_INFO(dev
)->gen
>= 7) {
2835 hw
->wm_lp_spr
[1] = I915_READ(WM2S_LP_IVB
);
2836 hw
->wm_lp_spr
[2] = I915_READ(WM3S_LP_IVB
);
2839 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2840 hw
->partitioning
= (I915_READ(WM_MISC
) & WM_MISC_DATA_PARTITION_5_6
) ?
2841 INTEL_DDB_PART_5_6
: INTEL_DDB_PART_1_2
;
2842 else if (IS_IVYBRIDGE(dev
))
2843 hw
->partitioning
= (I915_READ(DISP_ARB_CTL2
) & DISP_DATA_PARTITION_5_6
) ?
2844 INTEL_DDB_PART_5_6
: INTEL_DDB_PART_1_2
;
2847 !(I915_READ(DISP_ARB_CTL
) & DISP_FBC_WM_DIS
);
2851 * intel_update_watermarks - update FIFO watermark values based on current modes
2853 * Calculate watermark values for the various WM regs based on current mode
2854 * and plane configuration.
2856 * There are several cases to deal with here:
2857 * - normal (i.e. non-self-refresh)
2858 * - self-refresh (SR) mode
2859 * - lines are large relative to FIFO size (buffer can hold up to 2)
2860 * - lines are small relative to FIFO size (buffer can hold more than 2
2861 * lines), so need to account for TLB latency
2863 * The normal calculation is:
2864 * watermark = dotclock * bytes per pixel * latency
2865 * where latency is platform & configuration dependent (we assume pessimal
2868 * The SR calculation is:
2869 * watermark = (trunc(latency/line time)+1) * surface width *
2872 * line time = htotal / dotclock
2873 * surface width = hdisplay for normal plane and 64 for cursor
2874 * and latency is assumed to be high, as above.
2876 * The final value programmed to the register should always be rounded up,
2877 * and include an extra 2 entries to account for clock crossings.
2879 * We don't use the sprite, so we can ignore that. And on Crestline we have
2880 * to set the non-SR watermarks to 8.
2882 void intel_update_watermarks(struct drm_crtc
*crtc
)
2884 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
2886 if (dev_priv
->display
.update_wm
)
2887 dev_priv
->display
.update_wm(crtc
);
2890 void intel_update_sprite_watermarks(struct drm_plane
*plane
,
2891 struct drm_crtc
*crtc
,
2892 uint32_t sprite_width
,
2893 uint32_t sprite_height
,
2895 bool enabled
, bool scaled
)
2897 struct drm_i915_private
*dev_priv
= plane
->dev
->dev_private
;
2899 if (dev_priv
->display
.update_sprite_wm
)
2900 dev_priv
->display
.update_sprite_wm(plane
, crtc
,
2901 sprite_width
, sprite_height
,
2902 pixel_size
, enabled
, scaled
);
2905 static struct drm_i915_gem_object
*
2906 intel_alloc_context_page(struct drm_device
*dev
)
2908 struct drm_i915_gem_object
*ctx
;
2911 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
2913 ctx
= i915_gem_alloc_object(dev
, 4096);
2915 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
2919 ret
= i915_gem_obj_ggtt_pin(ctx
, 4096, 0);
2921 DRM_ERROR("failed to pin power context: %d\n", ret
);
2925 ret
= i915_gem_object_set_to_gtt_domain(ctx
, 1);
2927 DRM_ERROR("failed to set-domain on power context: %d\n", ret
);
2934 i915_gem_object_ggtt_unpin(ctx
);
2936 drm_gem_object_unreference(&ctx
->base
);
2941 * Lock protecting IPS related data structures
2943 DEFINE_SPINLOCK(mchdev_lock
);
2945 /* Global for IPS driver to get at the current i915 device. Protected by
2947 static struct drm_i915_private
*i915_mch_dev
;
2949 bool ironlake_set_drps(struct drm_device
*dev
, u8 val
)
2951 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2954 assert_spin_locked(&mchdev_lock
);
2956 rgvswctl
= I915_READ16(MEMSWCTL
);
2957 if (rgvswctl
& MEMCTL_CMD_STS
) {
2958 DRM_DEBUG("gpu busy, RCS change rejected\n");
2959 return false; /* still busy with another command */
2962 rgvswctl
= (MEMCTL_CMD_CHFREQ
<< MEMCTL_CMD_SHIFT
) |
2963 (val
<< MEMCTL_FREQ_SHIFT
) | MEMCTL_SFCAVM
;
2964 I915_WRITE16(MEMSWCTL
, rgvswctl
);
2965 POSTING_READ16(MEMSWCTL
);
2967 rgvswctl
|= MEMCTL_CMD_STS
;
2968 I915_WRITE16(MEMSWCTL
, rgvswctl
);
2973 static void ironlake_enable_drps(struct drm_device
*dev
)
2975 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2976 u32 rgvmodectl
= I915_READ(MEMMODECTL
);
2977 u8 fmax
, fmin
, fstart
, vstart
;
2979 spin_lock_irq(&mchdev_lock
);
2981 /* Enable temp reporting */
2982 I915_WRITE16(PMMISC
, I915_READ(PMMISC
) | MCPPCE_EN
);
2983 I915_WRITE16(TSC1
, I915_READ(TSC1
) | TSE
);
2985 /* 100ms RC evaluation intervals */
2986 I915_WRITE(RCUPEI
, 100000);
2987 I915_WRITE(RCDNEI
, 100000);
2989 /* Set max/min thresholds to 90ms and 80ms respectively */
2990 I915_WRITE(RCBMAXAVG
, 90000);
2991 I915_WRITE(RCBMINAVG
, 80000);
2993 I915_WRITE(MEMIHYST
, 1);
2995 /* Set up min, max, and cur for interrupt handling */
2996 fmax
= (rgvmodectl
& MEMMODE_FMAX_MASK
) >> MEMMODE_FMAX_SHIFT
;
2997 fmin
= (rgvmodectl
& MEMMODE_FMIN_MASK
);
2998 fstart
= (rgvmodectl
& MEMMODE_FSTART_MASK
) >>
2999 MEMMODE_FSTART_SHIFT
;
3001 vstart
= (I915_READ(PXVFREQ_BASE
+ (fstart
* 4)) & PXVFREQ_PX_MASK
) >>
3004 dev_priv
->ips
.fmax
= fmax
; /* IPS callback will increase this */
3005 dev_priv
->ips
.fstart
= fstart
;
3007 dev_priv
->ips
.max_delay
= fstart
;
3008 dev_priv
->ips
.min_delay
= fmin
;
3009 dev_priv
->ips
.cur_delay
= fstart
;
3011 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
3012 fmax
, fmin
, fstart
);
3014 I915_WRITE(MEMINTREN
, MEMINT_CX_SUPR_EN
| MEMINT_EVAL_CHG_EN
);
3017 * Interrupts will be enabled in ironlake_irq_postinstall
3020 I915_WRITE(VIDSTART
, vstart
);
3021 POSTING_READ(VIDSTART
);
3023 rgvmodectl
|= MEMMODE_SWMODE_EN
;
3024 I915_WRITE(MEMMODECTL
, rgvmodectl
);
3026 if (wait_for_atomic((I915_READ(MEMSWCTL
) & MEMCTL_CMD_STS
) == 0, 10))
3027 DRM_ERROR("stuck trying to change perf mode\n");
3030 ironlake_set_drps(dev
, fstart
);
3032 dev_priv
->ips
.last_count1
= I915_READ(0x112e4) + I915_READ(0x112e8) +
3034 dev_priv
->ips
.last_time1
= jiffies_to_msecs(jiffies
);
3035 dev_priv
->ips
.last_count2
= I915_READ(0x112f4);
3036 dev_priv
->ips
.last_time2
= ktime_get_raw_ns();
3038 spin_unlock_irq(&mchdev_lock
);
3041 static void ironlake_disable_drps(struct drm_device
*dev
)
3043 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3046 spin_lock_irq(&mchdev_lock
);
3048 rgvswctl
= I915_READ16(MEMSWCTL
);
3050 /* Ack interrupts, disable EFC interrupt */
3051 I915_WRITE(MEMINTREN
, I915_READ(MEMINTREN
) & ~MEMINT_EVAL_CHG_EN
);
3052 I915_WRITE(MEMINTRSTS
, MEMINT_EVAL_CHG
);
3053 I915_WRITE(DEIER
, I915_READ(DEIER
) & ~DE_PCU_EVENT
);
3054 I915_WRITE(DEIIR
, DE_PCU_EVENT
);
3055 I915_WRITE(DEIMR
, I915_READ(DEIMR
) | DE_PCU_EVENT
);
3057 /* Go back to the starting frequency */
3058 ironlake_set_drps(dev
, dev_priv
->ips
.fstart
);
3060 rgvswctl
|= MEMCTL_CMD_STS
;
3061 I915_WRITE(MEMSWCTL
, rgvswctl
);
3064 spin_unlock_irq(&mchdev_lock
);
3067 /* There's a funny hw issue where the hw returns all 0 when reading from
3068 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3069 * ourselves, instead of doing a rmw cycle (which might result in us clearing
3070 * all limits and the gpu stuck at whatever frequency it is at atm).
3072 static u32
gen6_rps_limits(struct drm_i915_private
*dev_priv
, u8 val
)
3076 /* Only set the down limit when we've reached the lowest level to avoid
3077 * getting more interrupts, otherwise leave this clear. This prevents a
3078 * race in the hw when coming out of rc6: There's a tiny window where
3079 * the hw runs at the minimal clock before selecting the desired
3080 * frequency, if the down threshold expires in that window we will not
3081 * receive a down interrupt. */
3082 limits
= dev_priv
->rps
.max_freq_softlimit
<< 24;
3083 if (val
<= dev_priv
->rps
.min_freq_softlimit
)
3084 limits
|= dev_priv
->rps
.min_freq_softlimit
<< 16;
3089 static void gen6_set_rps_thresholds(struct drm_i915_private
*dev_priv
, u8 val
)
3093 new_power
= dev_priv
->rps
.power
;
3094 switch (dev_priv
->rps
.power
) {
3096 if (val
> dev_priv
->rps
.efficient_freq
+ 1 && val
> dev_priv
->rps
.cur_freq
)
3097 new_power
= BETWEEN
;
3101 if (val
<= dev_priv
->rps
.efficient_freq
&& val
< dev_priv
->rps
.cur_freq
)
3102 new_power
= LOW_POWER
;
3103 else if (val
>= dev_priv
->rps
.rp0_freq
&& val
> dev_priv
->rps
.cur_freq
)
3104 new_power
= HIGH_POWER
;
3108 if (val
< (dev_priv
->rps
.rp1_freq
+ dev_priv
->rps
.rp0_freq
) >> 1 && val
< dev_priv
->rps
.cur_freq
)
3109 new_power
= BETWEEN
;
3112 /* Max/min bins are special */
3113 if (val
== dev_priv
->rps
.min_freq_softlimit
)
3114 new_power
= LOW_POWER
;
3115 if (val
== dev_priv
->rps
.max_freq_softlimit
)
3116 new_power
= HIGH_POWER
;
3117 if (new_power
== dev_priv
->rps
.power
)
3120 /* Note the units here are not exactly 1us, but 1280ns. */
3121 switch (new_power
) {
3123 /* Upclock if more than 95% busy over 16ms */
3124 I915_WRITE(GEN6_RP_UP_EI
, 12500);
3125 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 11800);
3127 /* Downclock if less than 85% busy over 32ms */
3128 I915_WRITE(GEN6_RP_DOWN_EI
, 25000);
3129 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 21250);
3131 I915_WRITE(GEN6_RP_CONTROL
,
3132 GEN6_RP_MEDIA_TURBO
|
3133 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
3134 GEN6_RP_MEDIA_IS_GFX
|
3136 GEN6_RP_UP_BUSY_AVG
|
3137 GEN6_RP_DOWN_IDLE_AVG
);
3141 /* Upclock if more than 90% busy over 13ms */
3142 I915_WRITE(GEN6_RP_UP_EI
, 10250);
3143 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 9225);
3145 /* Downclock if less than 75% busy over 32ms */
3146 I915_WRITE(GEN6_RP_DOWN_EI
, 25000);
3147 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 18750);
3149 I915_WRITE(GEN6_RP_CONTROL
,
3150 GEN6_RP_MEDIA_TURBO
|
3151 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
3152 GEN6_RP_MEDIA_IS_GFX
|
3154 GEN6_RP_UP_BUSY_AVG
|
3155 GEN6_RP_DOWN_IDLE_AVG
);
3159 /* Upclock if more than 85% busy over 10ms */
3160 I915_WRITE(GEN6_RP_UP_EI
, 8000);
3161 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 6800);
3163 /* Downclock if less than 60% busy over 32ms */
3164 I915_WRITE(GEN6_RP_DOWN_EI
, 25000);
3165 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 15000);
3167 I915_WRITE(GEN6_RP_CONTROL
,
3168 GEN6_RP_MEDIA_TURBO
|
3169 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
3170 GEN6_RP_MEDIA_IS_GFX
|
3172 GEN6_RP_UP_BUSY_AVG
|
3173 GEN6_RP_DOWN_IDLE_AVG
);
3177 dev_priv
->rps
.power
= new_power
;
3178 dev_priv
->rps
.last_adj
= 0;
3181 static u32
gen6_rps_pm_mask(struct drm_i915_private
*dev_priv
, u8 val
)
3185 if (val
> dev_priv
->rps
.min_freq_softlimit
)
3186 mask
|= GEN6_PM_RP_DOWN_THRESHOLD
| GEN6_PM_RP_DOWN_TIMEOUT
;
3187 if (val
< dev_priv
->rps
.max_freq_softlimit
)
3188 mask
|= GEN6_PM_RP_UP_THRESHOLD
;
3190 mask
|= dev_priv
->pm_rps_events
& (GEN6_PM_RP_DOWN_EI_EXPIRED
| GEN6_PM_RP_UP_EI_EXPIRED
);
3191 mask
&= dev_priv
->pm_rps_events
;
3193 /* IVB and SNB hard hangs on looping batchbuffer
3194 * if GEN6_PM_UP_EI_EXPIRED is masked.
3196 if (INTEL_INFO(dev_priv
->dev
)->gen
<= 7 && !IS_HASWELL(dev_priv
->dev
))
3197 mask
|= GEN6_PM_RP_UP_EI_EXPIRED
;
3199 if (IS_GEN8(dev_priv
->dev
))
3200 mask
|= GEN8_PMINTR_REDIRECT_TO_NON_DISP
;
3205 /* gen6_set_rps is called to update the frequency request, but should also be
3206 * called when the range (min_delay and max_delay) is modified so that we can
3207 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
3208 void gen6_set_rps(struct drm_device
*dev
, u8 val
)
3210 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3212 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
3213 WARN_ON(val
> dev_priv
->rps
.max_freq_softlimit
);
3214 WARN_ON(val
< dev_priv
->rps
.min_freq_softlimit
);
3216 /* min/max delay may still have been modified so be sure to
3217 * write the limits value.
3219 if (val
!= dev_priv
->rps
.cur_freq
) {
3220 gen6_set_rps_thresholds(dev_priv
, val
);
3222 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
3223 I915_WRITE(GEN6_RPNSWREQ
,
3224 HSW_FREQUENCY(val
));
3226 I915_WRITE(GEN6_RPNSWREQ
,
3227 GEN6_FREQUENCY(val
) |
3229 GEN6_AGGRESSIVE_TURBO
);
3232 /* Make sure we continue to get interrupts
3233 * until we hit the minimum or maximum frequencies.
3235 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS
, gen6_rps_limits(dev_priv
, val
));
3236 I915_WRITE(GEN6_PMINTRMSK
, gen6_rps_pm_mask(dev_priv
, val
));
3238 POSTING_READ(GEN6_RPNSWREQ
);
3240 dev_priv
->rps
.cur_freq
= val
;
3241 trace_intel_gpu_freq_change(val
* 50);
3244 /* vlv_set_rps_idle: Set the frequency to Rpn if Gfx clocks are down
3246 * * If Gfx is Idle, then
3247 * 1. Mask Turbo interrupts
3248 * 2. Bring up Gfx clock
3249 * 3. Change the freq to Rpn and wait till P-Unit updates freq
3250 * 4. Clear the Force GFX CLK ON bit so that Gfx can down
3251 * 5. Unmask Turbo interrupts
3253 static void vlv_set_rps_idle(struct drm_i915_private
*dev_priv
)
3255 struct drm_device
*dev
= dev_priv
->dev
;
3257 /* Latest VLV doesn't need to force the gfx clock */
3258 if (dev
->pdev
->revision
>= 0xd) {
3259 valleyview_set_rps(dev_priv
->dev
, dev_priv
->rps
.min_freq_softlimit
);
3264 * When we are idle. Drop to min voltage state.
3267 if (dev_priv
->rps
.cur_freq
<= dev_priv
->rps
.min_freq_softlimit
)
3270 /* Mask turbo interrupt so that they will not come in between */
3271 I915_WRITE(GEN6_PMINTRMSK
, 0xffffffff);
3273 vlv_force_gfx_clock(dev_priv
, true);
3275 dev_priv
->rps
.cur_freq
= dev_priv
->rps
.min_freq_softlimit
;
3277 vlv_punit_write(dev_priv
, PUNIT_REG_GPU_FREQ_REQ
,
3278 dev_priv
->rps
.min_freq_softlimit
);
3280 if (wait_for(((vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
))
3281 & GENFREQSTATUS
) == 0, 5))
3282 DRM_ERROR("timed out waiting for Punit\n");
3284 vlv_force_gfx_clock(dev_priv
, false);
3286 I915_WRITE(GEN6_PMINTRMSK
,
3287 gen6_rps_pm_mask(dev_priv
, dev_priv
->rps
.cur_freq
));
3290 void gen6_rps_idle(struct drm_i915_private
*dev_priv
)
3292 struct drm_device
*dev
= dev_priv
->dev
;
3294 mutex_lock(&dev_priv
->rps
.hw_lock
);
3295 if (dev_priv
->rps
.enabled
) {
3296 if (IS_CHERRYVIEW(dev
))
3297 valleyview_set_rps(dev_priv
->dev
, dev_priv
->rps
.min_freq_softlimit
);
3298 else if (IS_VALLEYVIEW(dev
))
3299 vlv_set_rps_idle(dev_priv
);
3301 gen6_set_rps(dev_priv
->dev
, dev_priv
->rps
.min_freq_softlimit
);
3302 dev_priv
->rps
.last_adj
= 0;
3304 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3307 void gen6_rps_boost(struct drm_i915_private
*dev_priv
)
3309 struct drm_device
*dev
= dev_priv
->dev
;
3311 mutex_lock(&dev_priv
->rps
.hw_lock
);
3312 if (dev_priv
->rps
.enabled
) {
3313 if (IS_VALLEYVIEW(dev
))
3314 valleyview_set_rps(dev_priv
->dev
, dev_priv
->rps
.max_freq_softlimit
);
3316 gen6_set_rps(dev_priv
->dev
, dev_priv
->rps
.max_freq_softlimit
);
3317 dev_priv
->rps
.last_adj
= 0;
3319 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3322 void valleyview_set_rps(struct drm_device
*dev
, u8 val
)
3324 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3326 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
3327 WARN_ON(val
> dev_priv
->rps
.max_freq_softlimit
);
3328 WARN_ON(val
< dev_priv
->rps
.min_freq_softlimit
);
3330 DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
3331 vlv_gpu_freq(dev_priv
, dev_priv
->rps
.cur_freq
),
3332 dev_priv
->rps
.cur_freq
,
3333 vlv_gpu_freq(dev_priv
, val
), val
);
3335 if (val
!= dev_priv
->rps
.cur_freq
)
3336 vlv_punit_write(dev_priv
, PUNIT_REG_GPU_FREQ_REQ
, val
);
3338 I915_WRITE(GEN6_PMINTRMSK
, gen6_rps_pm_mask(dev_priv
, val
));
3340 dev_priv
->rps
.cur_freq
= val
;
3341 trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv
, val
));
3344 static void gen8_disable_rps_interrupts(struct drm_device
*dev
)
3346 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3348 I915_WRITE(GEN6_PMINTRMSK
, ~GEN8_PMINTR_REDIRECT_TO_NON_DISP
);
3349 I915_WRITE(GEN8_GT_IER(2), I915_READ(GEN8_GT_IER(2)) &
3350 ~dev_priv
->pm_rps_events
);
3351 /* Complete PM interrupt masking here doesn't race with the rps work
3352 * item again unmasking PM interrupts because that is using a different
3353 * register (GEN8_GT_IMR(2)) to mask PM interrupts. The only risk is in
3354 * leaving stale bits in GEN8_GT_IIR(2) and GEN8_GT_IMR(2) which
3355 * gen8_enable_rps will clean up. */
3357 spin_lock_irq(&dev_priv
->irq_lock
);
3358 dev_priv
->rps
.pm_iir
= 0;
3359 spin_unlock_irq(&dev_priv
->irq_lock
);
3361 I915_WRITE(GEN8_GT_IIR(2), dev_priv
->pm_rps_events
);
3364 static void gen6_disable_rps_interrupts(struct drm_device
*dev
)
3366 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3368 I915_WRITE(GEN6_PMINTRMSK
, 0xffffffff);
3369 I915_WRITE(GEN6_PMIER
, I915_READ(GEN6_PMIER
) &
3370 ~dev_priv
->pm_rps_events
);
3371 /* Complete PM interrupt masking here doesn't race with the rps work
3372 * item again unmasking PM interrupts because that is using a different
3373 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3374 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3376 spin_lock_irq(&dev_priv
->irq_lock
);
3377 dev_priv
->rps
.pm_iir
= 0;
3378 spin_unlock_irq(&dev_priv
->irq_lock
);
3380 I915_WRITE(GEN6_PMIIR
, dev_priv
->pm_rps_events
);
3383 static void gen6_disable_rps(struct drm_device
*dev
)
3385 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3387 I915_WRITE(GEN6_RC_CONTROL
, 0);
3388 I915_WRITE(GEN6_RPNSWREQ
, 1 << 31);
3390 if (IS_BROADWELL(dev
))
3391 gen8_disable_rps_interrupts(dev
);
3393 gen6_disable_rps_interrupts(dev
);
3396 static void cherryview_disable_rps(struct drm_device
*dev
)
3398 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3400 I915_WRITE(GEN6_RC_CONTROL
, 0);
3402 gen8_disable_rps_interrupts(dev
);
3405 static void valleyview_disable_rps(struct drm_device
*dev
)
3407 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3409 I915_WRITE(GEN6_RC_CONTROL
, 0);
3411 gen6_disable_rps_interrupts(dev
);
3414 static void intel_print_rc6_info(struct drm_device
*dev
, u32 mode
)
3416 if (IS_VALLEYVIEW(dev
)) {
3417 if (mode
& (GEN7_RC_CTL_TO_MODE
| GEN6_RC_CTL_EI_MODE(1)))
3418 mode
= GEN6_RC_CTL_RC6_ENABLE
;
3422 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
3423 (mode
& GEN6_RC_CTL_RC6_ENABLE
) ? "on" : "off",
3424 (mode
& GEN6_RC_CTL_RC6p_ENABLE
) ? "on" : "off",
3425 (mode
& GEN6_RC_CTL_RC6pp_ENABLE
) ? "on" : "off");
3428 static int sanitize_rc6_option(const struct drm_device
*dev
, int enable_rc6
)
3430 /* No RC6 before Ironlake */
3431 if (INTEL_INFO(dev
)->gen
< 5)
3434 /* RC6 is only on Ironlake mobile not on desktop */
3435 if (INTEL_INFO(dev
)->gen
== 5 && !IS_IRONLAKE_M(dev
))
3438 /* Respect the kernel parameter if it is set */
3439 if (enable_rc6
>= 0) {
3442 if (INTEL_INFO(dev
)->gen
== 6 || IS_IVYBRIDGE(dev
))
3443 mask
= INTEL_RC6_ENABLE
| INTEL_RC6p_ENABLE
|
3446 mask
= INTEL_RC6_ENABLE
;
3448 if ((enable_rc6
& mask
) != enable_rc6
)
3449 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
3450 enable_rc6
& mask
, enable_rc6
, mask
);
3452 return enable_rc6
& mask
;
3455 /* Disable RC6 on Ironlake */
3456 if (INTEL_INFO(dev
)->gen
== 5)
3459 if (IS_IVYBRIDGE(dev
))
3460 return (INTEL_RC6_ENABLE
| INTEL_RC6p_ENABLE
);
3462 return INTEL_RC6_ENABLE
;
3465 int intel_enable_rc6(const struct drm_device
*dev
)
3467 return i915
.enable_rc6
;
3470 static void gen8_enable_rps_interrupts(struct drm_device
*dev
)
3472 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3474 spin_lock_irq(&dev_priv
->irq_lock
);
3475 WARN_ON(dev_priv
->rps
.pm_iir
);
3476 gen8_enable_pm_irq(dev_priv
, dev_priv
->pm_rps_events
);
3477 I915_WRITE(GEN8_GT_IIR(2), dev_priv
->pm_rps_events
);
3478 spin_unlock_irq(&dev_priv
->irq_lock
);
3481 static void gen6_enable_rps_interrupts(struct drm_device
*dev
)
3483 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3485 spin_lock_irq(&dev_priv
->irq_lock
);
3486 WARN_ON(dev_priv
->rps
.pm_iir
);
3487 gen6_enable_pm_irq(dev_priv
, dev_priv
->pm_rps_events
);
3488 I915_WRITE(GEN6_PMIIR
, dev_priv
->pm_rps_events
);
3489 spin_unlock_irq(&dev_priv
->irq_lock
);
3492 static void parse_rp_state_cap(struct drm_i915_private
*dev_priv
, u32 rp_state_cap
)
3494 /* All of these values are in units of 50MHz */
3495 dev_priv
->rps
.cur_freq
= 0;
3496 /* static values from HW: RP0 < RPe < RP1 < RPn (min_freq) */
3497 dev_priv
->rps
.rp1_freq
= (rp_state_cap
>> 8) & 0xff;
3498 dev_priv
->rps
.rp0_freq
= (rp_state_cap
>> 0) & 0xff;
3499 dev_priv
->rps
.min_freq
= (rp_state_cap
>> 16) & 0xff;
3500 /* XXX: only BYT has a special efficient freq */
3501 dev_priv
->rps
.efficient_freq
= dev_priv
->rps
.rp1_freq
;
3502 /* hw_max = RP0 until we check for overclocking */
3503 dev_priv
->rps
.max_freq
= dev_priv
->rps
.rp0_freq
;
3505 /* Preserve min/max settings in case of re-init */
3506 if (dev_priv
->rps
.max_freq_softlimit
== 0)
3507 dev_priv
->rps
.max_freq_softlimit
= dev_priv
->rps
.max_freq
;
3509 if (dev_priv
->rps
.min_freq_softlimit
== 0)
3510 dev_priv
->rps
.min_freq_softlimit
= dev_priv
->rps
.min_freq
;
3513 static void gen8_enable_rps(struct drm_device
*dev
)
3515 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3516 struct intel_engine_cs
*ring
;
3517 uint32_t rc6_mask
= 0, rp_state_cap
;
3520 /* 1a: Software RC state - RC0 */
3521 I915_WRITE(GEN6_RC_STATE
, 0);
3523 /* 1c & 1d: Get forcewake during program sequence. Although the driver
3524 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
3525 gen6_gt_force_wake_get(dev_priv
, FORCEWAKE_ALL
);
3527 /* 2a: Disable RC states. */
3528 I915_WRITE(GEN6_RC_CONTROL
, 0);
3530 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
3531 parse_rp_state_cap(dev_priv
, rp_state_cap
);
3533 /* 2b: Program RC6 thresholds.*/
3534 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 40 << 16);
3535 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000); /* 12500 * 1280ns */
3536 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25); /* 25 * 1280ns */
3537 for_each_ring(ring
, dev_priv
, unused
)
3538 I915_WRITE(RING_MAX_IDLE(ring
->mmio_base
), 10);
3539 I915_WRITE(GEN6_RC_SLEEP
, 0);
3540 if (IS_BROADWELL(dev
))
3541 I915_WRITE(GEN6_RC6_THRESHOLD
, 625); /* 800us/1.28 for TO */
3543 I915_WRITE(GEN6_RC6_THRESHOLD
, 50000); /* 50/125ms per EI */
3546 if (intel_enable_rc6(dev
) & INTEL_RC6_ENABLE
)
3547 rc6_mask
= GEN6_RC_CTL_RC6_ENABLE
;
3548 intel_print_rc6_info(dev
, rc6_mask
);
3549 if (IS_BROADWELL(dev
))
3550 I915_WRITE(GEN6_RC_CONTROL
, GEN6_RC_CTL_HW_ENABLE
|
3551 GEN7_RC_CTL_TO_MODE
|
3554 I915_WRITE(GEN6_RC_CONTROL
, GEN6_RC_CTL_HW_ENABLE
|
3555 GEN6_RC_CTL_EI_MODE(1) |
3558 /* 4 Program defaults and thresholds for RPS*/
3559 I915_WRITE(GEN6_RPNSWREQ
,
3560 HSW_FREQUENCY(dev_priv
->rps
.rp1_freq
));
3561 I915_WRITE(GEN6_RC_VIDEO_FREQ
,
3562 HSW_FREQUENCY(dev_priv
->rps
.rp1_freq
));
3563 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
3564 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 100000000 / 128); /* 1 second timeout */
3566 /* Docs recommend 900MHz, and 300 MHz respectively */
3567 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS
,
3568 dev_priv
->rps
.max_freq_softlimit
<< 24 |
3569 dev_priv
->rps
.min_freq_softlimit
<< 16);
3571 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 7600000 / 128); /* 76ms busyness per EI, 90% */
3572 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 31300000 / 128); /* 313ms busyness per EI, 70%*/
3573 I915_WRITE(GEN6_RP_UP_EI
, 66000); /* 84.48ms, XXX: random? */
3574 I915_WRITE(GEN6_RP_DOWN_EI
, 350000); /* 448ms, XXX: random? */
3576 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
3579 I915_WRITE(GEN6_RP_CONTROL
,
3580 GEN6_RP_MEDIA_TURBO
|
3581 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
3582 GEN6_RP_MEDIA_IS_GFX
|
3584 GEN6_RP_UP_BUSY_AVG
|
3585 GEN6_RP_DOWN_IDLE_AVG
);
3587 /* 6: Ring frequency + overclocking (our driver does this later */
3589 gen6_set_rps(dev
, (I915_READ(GEN6_GT_PERF_STATUS
) & 0xff00) >> 8);
3591 gen8_enable_rps_interrupts(dev
);
3593 gen6_gt_force_wake_put(dev_priv
, FORCEWAKE_ALL
);
3596 static void gen6_enable_rps(struct drm_device
*dev
)
3598 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3599 struct intel_engine_cs
*ring
;
3602 u32 rc6vids
, pcu_mbox
= 0, rc6_mask
= 0;
3607 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
3609 /* Here begins a magic sequence of register writes to enable
3610 * auto-downclocking.
3612 * Perhaps there might be some value in exposing these to
3615 I915_WRITE(GEN6_RC_STATE
, 0);
3617 /* Clear the DBG now so we don't confuse earlier errors */
3618 if ((gtfifodbg
= I915_READ(GTFIFODBG
))) {
3619 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg
);
3620 I915_WRITE(GTFIFODBG
, gtfifodbg
);
3623 gen6_gt_force_wake_get(dev_priv
, FORCEWAKE_ALL
);
3625 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
3626 gt_perf_status
= I915_READ(GEN6_GT_PERF_STATUS
);
3628 parse_rp_state_cap(dev_priv
, rp_state_cap
);
3630 /* disable the counters and set deterministic thresholds */
3631 I915_WRITE(GEN6_RC_CONTROL
, 0);
3633 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT
, 1000 << 16);
3634 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 40 << 16 | 30);
3635 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT
, 30);
3636 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000);
3637 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25);
3639 for_each_ring(ring
, dev_priv
, i
)
3640 I915_WRITE(RING_MAX_IDLE(ring
->mmio_base
), 10);
3642 I915_WRITE(GEN6_RC_SLEEP
, 0);
3643 I915_WRITE(GEN6_RC1e_THRESHOLD
, 1000);
3644 if (IS_IVYBRIDGE(dev
))
3645 I915_WRITE(GEN6_RC6_THRESHOLD
, 125000);
3647 I915_WRITE(GEN6_RC6_THRESHOLD
, 50000);
3648 I915_WRITE(GEN6_RC6p_THRESHOLD
, 150000);
3649 I915_WRITE(GEN6_RC6pp_THRESHOLD
, 64000); /* unused */
3651 /* Check if we are enabling RC6 */
3652 rc6_mode
= intel_enable_rc6(dev_priv
->dev
);
3653 if (rc6_mode
& INTEL_RC6_ENABLE
)
3654 rc6_mask
|= GEN6_RC_CTL_RC6_ENABLE
;
3656 /* We don't use those on Haswell */
3657 if (!IS_HASWELL(dev
)) {
3658 if (rc6_mode
& INTEL_RC6p_ENABLE
)
3659 rc6_mask
|= GEN6_RC_CTL_RC6p_ENABLE
;
3661 if (rc6_mode
& INTEL_RC6pp_ENABLE
)
3662 rc6_mask
|= GEN6_RC_CTL_RC6pp_ENABLE
;
3665 intel_print_rc6_info(dev
, rc6_mask
);
3667 I915_WRITE(GEN6_RC_CONTROL
,
3669 GEN6_RC_CTL_EI_MODE(1) |
3670 GEN6_RC_CTL_HW_ENABLE
);
3672 /* Power down if completely idle for over 50ms */
3673 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 50000);
3674 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
3676 ret
= sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_MIN_FREQ_TABLE
, 0);
3678 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
3680 ret
= sandybridge_pcode_read(dev_priv
, GEN6_READ_OC_PARAMS
, &pcu_mbox
);
3681 if (!ret
&& (pcu_mbox
& (1<<31))) { /* OC supported */
3682 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
3683 (dev_priv
->rps
.max_freq_softlimit
& 0xff) * 50,
3684 (pcu_mbox
& 0xff) * 50);
3685 dev_priv
->rps
.max_freq
= pcu_mbox
& 0xff;
3688 dev_priv
->rps
.power
= HIGH_POWER
; /* force a reset */
3689 gen6_set_rps(dev_priv
->dev
, dev_priv
->rps
.min_freq_softlimit
);
3691 gen6_enable_rps_interrupts(dev
);
3694 ret
= sandybridge_pcode_read(dev_priv
, GEN6_PCODE_READ_RC6VIDS
, &rc6vids
);
3695 if (IS_GEN6(dev
) && ret
) {
3696 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
3697 } else if (IS_GEN6(dev
) && (GEN6_DECODE_RC6_VID(rc6vids
& 0xff) < 450)) {
3698 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
3699 GEN6_DECODE_RC6_VID(rc6vids
& 0xff), 450);
3700 rc6vids
&= 0xffff00;
3701 rc6vids
|= GEN6_ENCODE_RC6_VID(450);
3702 ret
= sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_RC6VIDS
, rc6vids
);
3704 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
3707 gen6_gt_force_wake_put(dev_priv
, FORCEWAKE_ALL
);
3710 static void __gen6_update_ring_freq(struct drm_device
*dev
)
3712 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3714 unsigned int gpu_freq
;
3715 unsigned int max_ia_freq
, min_ring_freq
;
3716 int scaling_factor
= 180;
3717 struct cpufreq_policy
*policy
;
3719 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
3721 policy
= cpufreq_cpu_get(0);
3723 max_ia_freq
= policy
->cpuinfo
.max_freq
;
3724 cpufreq_cpu_put(policy
);
3727 * Default to measured freq if none found, PCU will ensure we
3730 max_ia_freq
= tsc_khz
;
3733 /* Convert from kHz to MHz */
3734 max_ia_freq
/= 1000;
3736 min_ring_freq
= I915_READ(DCLK
) & 0xf;
3737 /* convert DDR frequency from units of 266.6MHz to bandwidth */
3738 min_ring_freq
= mult_frac(min_ring_freq
, 8, 3);
3741 * For each potential GPU frequency, load a ring frequency we'd like
3742 * to use for memory access. We do this by specifying the IA frequency
3743 * the PCU should use as a reference to determine the ring frequency.
3745 for (gpu_freq
= dev_priv
->rps
.max_freq_softlimit
; gpu_freq
>= dev_priv
->rps
.min_freq_softlimit
;
3747 int diff
= dev_priv
->rps
.max_freq_softlimit
- gpu_freq
;
3748 unsigned int ia_freq
= 0, ring_freq
= 0;
3750 if (INTEL_INFO(dev
)->gen
>= 8) {
3751 /* max(2 * GT, DDR). NB: GT is 50MHz units */
3752 ring_freq
= max(min_ring_freq
, gpu_freq
);
3753 } else if (IS_HASWELL(dev
)) {
3754 ring_freq
= mult_frac(gpu_freq
, 5, 4);
3755 ring_freq
= max(min_ring_freq
, ring_freq
);
3756 /* leave ia_freq as the default, chosen by cpufreq */
3758 /* On older processors, there is no separate ring
3759 * clock domain, so in order to boost the bandwidth
3760 * of the ring, we need to upclock the CPU (ia_freq).
3762 * For GPU frequencies less than 750MHz,
3763 * just use the lowest ring freq.
3765 if (gpu_freq
< min_freq
)
3768 ia_freq
= max_ia_freq
- ((diff
* scaling_factor
) / 2);
3769 ia_freq
= DIV_ROUND_CLOSEST(ia_freq
, 100);
3772 sandybridge_pcode_write(dev_priv
,
3773 GEN6_PCODE_WRITE_MIN_FREQ_TABLE
,
3774 ia_freq
<< GEN6_PCODE_FREQ_IA_RATIO_SHIFT
|
3775 ring_freq
<< GEN6_PCODE_FREQ_RING_RATIO_SHIFT
|
3780 void gen6_update_ring_freq(struct drm_device
*dev
)
3782 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3784 if (INTEL_INFO(dev
)->gen
< 6 || IS_VALLEYVIEW(dev
))
3787 mutex_lock(&dev_priv
->rps
.hw_lock
);
3788 __gen6_update_ring_freq(dev
);
3789 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3792 static int cherryview_rps_max_freq(struct drm_i915_private
*dev_priv
)
3796 val
= vlv_punit_read(dev_priv
, PUNIT_GPU_STATUS_REG
);
3797 rp0
= (val
>> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT
) & PUNIT_GPU_STATUS_MAX_FREQ_MASK
;
3802 static int cherryview_rps_rpe_freq(struct drm_i915_private
*dev_priv
)
3806 val
= vlv_punit_read(dev_priv
, PUNIT_GPU_DUTYCYCLE_REG
);
3807 rpe
= (val
>> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT
) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK
;
3812 static int cherryview_rps_guar_freq(struct drm_i915_private
*dev_priv
)
3816 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
3817 rp1
= (val
>> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT
) & PUNIT_GPU_STATUS_MAX_FREQ_MASK
;
3822 static int cherryview_rps_min_freq(struct drm_i915_private
*dev_priv
)
3826 val
= vlv_punit_read(dev_priv
, PUNIT_GPU_STATUS_REG
);
3827 rpn
= (val
>> PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT
) & PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK
;
3831 static int valleyview_rps_guar_freq(struct drm_i915_private
*dev_priv
)
3835 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FREQ_FUSE
);
3837 rp1
= (val
& FB_GFX_FGUARANTEED_FREQ_FUSE_MASK
) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT
;
3842 static int valleyview_rps_max_freq(struct drm_i915_private
*dev_priv
)
3846 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FREQ_FUSE
);
3848 rp0
= (val
& FB_GFX_MAX_FREQ_FUSE_MASK
) >> FB_GFX_MAX_FREQ_FUSE_SHIFT
;
3850 rp0
= min_t(u32
, rp0
, 0xea);
3855 static int valleyview_rps_rpe_freq(struct drm_i915_private
*dev_priv
)
3859 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FMAX_FUSE_LO
);
3860 rpe
= (val
& FB_FMAX_VMIN_FREQ_LO_MASK
) >> FB_FMAX_VMIN_FREQ_LO_SHIFT
;
3861 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FMAX_FUSE_HI
);
3862 rpe
|= (val
& FB_FMAX_VMIN_FREQ_HI_MASK
) << 5;
3867 static int valleyview_rps_min_freq(struct drm_i915_private
*dev_priv
)
3869 return vlv_punit_read(dev_priv
, PUNIT_REG_GPU_LFM
) & 0xff;
3872 /* Check that the pctx buffer wasn't move under us. */
3873 static void valleyview_check_pctx(struct drm_i915_private
*dev_priv
)
3875 unsigned long pctx_addr
= I915_READ(VLV_PCBR
) & ~4095;
3877 WARN_ON(pctx_addr
!= dev_priv
->mm
.stolen_base
+
3878 dev_priv
->vlv_pctx
->stolen
->start
);
3882 /* Check that the pcbr address is not empty. */
3883 static void cherryview_check_pctx(struct drm_i915_private
*dev_priv
)
3885 unsigned long pctx_addr
= I915_READ(VLV_PCBR
) & ~4095;
3887 WARN_ON((pctx_addr
>> VLV_PCBR_ADDR_SHIFT
) == 0);
3890 static void cherryview_setup_pctx(struct drm_device
*dev
)
3892 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3893 unsigned long pctx_paddr
, paddr
;
3894 struct i915_gtt
*gtt
= &dev_priv
->gtt
;
3896 int pctx_size
= 32*1024;
3898 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
3900 pcbr
= I915_READ(VLV_PCBR
);
3901 if ((pcbr
>> VLV_PCBR_ADDR_SHIFT
) == 0) {
3902 paddr
= (dev_priv
->mm
.stolen_base
+
3903 (gtt
->stolen_size
- pctx_size
));
3905 pctx_paddr
= (paddr
& (~4095));
3906 I915_WRITE(VLV_PCBR
, pctx_paddr
);
3910 static void valleyview_setup_pctx(struct drm_device
*dev
)
3912 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3913 struct drm_i915_gem_object
*pctx
;
3914 unsigned long pctx_paddr
;
3916 int pctx_size
= 24*1024;
3918 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
3920 pcbr
= I915_READ(VLV_PCBR
);
3922 /* BIOS set it up already, grab the pre-alloc'd space */
3925 pcbr_offset
= (pcbr
& (~4095)) - dev_priv
->mm
.stolen_base
;
3926 pctx
= i915_gem_object_create_stolen_for_preallocated(dev_priv
->dev
,
3928 I915_GTT_OFFSET_NONE
,
3934 * From the Gunit register HAS:
3935 * The Gfx driver is expected to program this register and ensure
3936 * proper allocation within Gfx stolen memory. For example, this
3937 * register should be programmed such than the PCBR range does not
3938 * overlap with other ranges, such as the frame buffer, protected
3939 * memory, or any other relevant ranges.
3941 pctx
= i915_gem_object_create_stolen(dev
, pctx_size
);
3943 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
3947 pctx_paddr
= dev_priv
->mm
.stolen_base
+ pctx
->stolen
->start
;
3948 I915_WRITE(VLV_PCBR
, pctx_paddr
);
3951 dev_priv
->vlv_pctx
= pctx
;
3954 static void valleyview_cleanup_pctx(struct drm_device
*dev
)
3956 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3958 if (WARN_ON(!dev_priv
->vlv_pctx
))
3961 drm_gem_object_unreference(&dev_priv
->vlv_pctx
->base
);
3962 dev_priv
->vlv_pctx
= NULL
;
3965 static void valleyview_init_gt_powersave(struct drm_device
*dev
)
3967 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3969 valleyview_setup_pctx(dev
);
3971 mutex_lock(&dev_priv
->rps
.hw_lock
);
3973 dev_priv
->rps
.max_freq
= valleyview_rps_max_freq(dev_priv
);
3974 dev_priv
->rps
.rp0_freq
= dev_priv
->rps
.max_freq
;
3975 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
3976 vlv_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
),
3977 dev_priv
->rps
.max_freq
);
3979 dev_priv
->rps
.efficient_freq
= valleyview_rps_rpe_freq(dev_priv
);
3980 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
3981 vlv_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
),
3982 dev_priv
->rps
.efficient_freq
);
3984 dev_priv
->rps
.rp1_freq
= valleyview_rps_guar_freq(dev_priv
);
3985 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
3986 vlv_gpu_freq(dev_priv
, dev_priv
->rps
.rp1_freq
),
3987 dev_priv
->rps
.rp1_freq
);
3989 dev_priv
->rps
.min_freq
= valleyview_rps_min_freq(dev_priv
);
3990 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
3991 vlv_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
),
3992 dev_priv
->rps
.min_freq
);
3994 /* Preserve min/max settings in case of re-init */
3995 if (dev_priv
->rps
.max_freq_softlimit
== 0)
3996 dev_priv
->rps
.max_freq_softlimit
= dev_priv
->rps
.max_freq
;
3998 if (dev_priv
->rps
.min_freq_softlimit
== 0)
3999 dev_priv
->rps
.min_freq_softlimit
= dev_priv
->rps
.min_freq
;
4001 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4004 static void cherryview_init_gt_powersave(struct drm_device
*dev
)
4006 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4008 cherryview_setup_pctx(dev
);
4010 mutex_lock(&dev_priv
->rps
.hw_lock
);
4012 dev_priv
->rps
.max_freq
= cherryview_rps_max_freq(dev_priv
);
4013 dev_priv
->rps
.rp0_freq
= dev_priv
->rps
.max_freq
;
4014 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
4015 vlv_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
),
4016 dev_priv
->rps
.max_freq
);
4018 dev_priv
->rps
.efficient_freq
= cherryview_rps_rpe_freq(dev_priv
);
4019 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
4020 vlv_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
),
4021 dev_priv
->rps
.efficient_freq
);
4023 dev_priv
->rps
.rp1_freq
= cherryview_rps_guar_freq(dev_priv
);
4024 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
4025 vlv_gpu_freq(dev_priv
, dev_priv
->rps
.rp1_freq
),
4026 dev_priv
->rps
.rp1_freq
);
4028 dev_priv
->rps
.min_freq
= cherryview_rps_min_freq(dev_priv
);
4029 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
4030 vlv_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
),
4031 dev_priv
->rps
.min_freq
);
4033 /* Preserve min/max settings in case of re-init */
4034 if (dev_priv
->rps
.max_freq_softlimit
== 0)
4035 dev_priv
->rps
.max_freq_softlimit
= dev_priv
->rps
.max_freq
;
4037 if (dev_priv
->rps
.min_freq_softlimit
== 0)
4038 dev_priv
->rps
.min_freq_softlimit
= dev_priv
->rps
.min_freq
;
4040 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4043 static void valleyview_cleanup_gt_powersave(struct drm_device
*dev
)
4045 valleyview_cleanup_pctx(dev
);
4048 static void cherryview_enable_rps(struct drm_device
*dev
)
4050 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4051 struct intel_engine_cs
*ring
;
4052 u32 gtfifodbg
, val
, rc6_mode
= 0, pcbr
;
4055 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
4057 gtfifodbg
= I915_READ(GTFIFODBG
);
4059 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4061 I915_WRITE(GTFIFODBG
, gtfifodbg
);
4064 cherryview_check_pctx(dev_priv
);
4066 /* 1a & 1b: Get forcewake during program sequence. Although the driver
4067 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4068 gen6_gt_force_wake_get(dev_priv
, FORCEWAKE_ALL
);
4070 /* 2a: Program RC6 thresholds.*/
4071 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 40 << 16);
4072 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000); /* 12500 * 1280ns */
4073 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25); /* 25 * 1280ns */
4075 for_each_ring(ring
, dev_priv
, i
)
4076 I915_WRITE(RING_MAX_IDLE(ring
->mmio_base
), 10);
4077 I915_WRITE(GEN6_RC_SLEEP
, 0);
4079 I915_WRITE(GEN6_RC6_THRESHOLD
, 50000); /* 50/125ms per EI */
4081 /* allows RC6 residency counter to work */
4082 I915_WRITE(VLV_COUNTER_CONTROL
,
4083 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH
|
4084 VLV_MEDIA_RC6_COUNT_EN
|
4085 VLV_RENDER_RC6_COUNT_EN
));
4087 /* For now we assume BIOS is allocating and populating the PCBR */
4088 pcbr
= I915_READ(VLV_PCBR
);
4090 DRM_DEBUG_DRIVER("PCBR offset : 0x%x\n", pcbr
);
4093 if ((intel_enable_rc6(dev
) & INTEL_RC6_ENABLE
) &&
4094 (pcbr
>> VLV_PCBR_ADDR_SHIFT
))
4095 rc6_mode
= GEN6_RC_CTL_EI_MODE(1);
4097 I915_WRITE(GEN6_RC_CONTROL
, rc6_mode
);
4099 /* 4 Program defaults and thresholds for RPS*/
4100 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 59400);
4101 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 245000);
4102 I915_WRITE(GEN6_RP_UP_EI
, 66000);
4103 I915_WRITE(GEN6_RP_DOWN_EI
, 350000);
4105 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
4107 /* WaDisablePwrmtrEvent:chv (pre-production hw) */
4108 I915_WRITE(0xA80C, I915_READ(0xA80C) & 0x00ffffff);
4109 I915_WRITE(0xA810, I915_READ(0xA810) & 0xffffff00);
4112 I915_WRITE(GEN6_RP_CONTROL
,
4113 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
4114 GEN6_RP_MEDIA_IS_GFX
| /* WaSetMaskForGfxBusyness:chv (pre-production hw ?) */
4116 GEN6_RP_UP_BUSY_AVG
|
4117 GEN6_RP_DOWN_IDLE_AVG
);
4119 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
4121 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val
& 0x10 ? "yes" : "no");
4122 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val
);
4124 dev_priv
->rps
.cur_freq
= (val
>> 8) & 0xff;
4125 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
4126 vlv_gpu_freq(dev_priv
, dev_priv
->rps
.cur_freq
),
4127 dev_priv
->rps
.cur_freq
);
4129 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
4130 vlv_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
),
4131 dev_priv
->rps
.efficient_freq
);
4133 valleyview_set_rps(dev_priv
->dev
, dev_priv
->rps
.efficient_freq
);
4135 gen8_enable_rps_interrupts(dev
);
4137 gen6_gt_force_wake_put(dev_priv
, FORCEWAKE_ALL
);
4140 static void valleyview_enable_rps(struct drm_device
*dev
)
4142 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4143 struct intel_engine_cs
*ring
;
4144 u32 gtfifodbg
, val
, rc6_mode
= 0;
4147 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
4149 valleyview_check_pctx(dev_priv
);
4151 if ((gtfifodbg
= I915_READ(GTFIFODBG
))) {
4152 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4154 I915_WRITE(GTFIFODBG
, gtfifodbg
);
4157 /* If VLV, Forcewake all wells, else re-direct to regular path */
4158 gen6_gt_force_wake_get(dev_priv
, FORCEWAKE_ALL
);
4160 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 59400);
4161 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 245000);
4162 I915_WRITE(GEN6_RP_UP_EI
, 66000);
4163 I915_WRITE(GEN6_RP_DOWN_EI
, 350000);
4165 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
4166 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 0xf4240);
4168 I915_WRITE(GEN6_RP_CONTROL
,
4169 GEN6_RP_MEDIA_TURBO
|
4170 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
4171 GEN6_RP_MEDIA_IS_GFX
|
4173 GEN6_RP_UP_BUSY_AVG
|
4174 GEN6_RP_DOWN_IDLE_CONT
);
4176 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 0x00280000);
4177 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000);
4178 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25);
4180 for_each_ring(ring
, dev_priv
, i
)
4181 I915_WRITE(RING_MAX_IDLE(ring
->mmio_base
), 10);
4183 I915_WRITE(GEN6_RC6_THRESHOLD
, 0x557);
4185 /* allows RC6 residency counter to work */
4186 I915_WRITE(VLV_COUNTER_CONTROL
,
4187 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN
|
4188 VLV_RENDER_RC0_COUNT_EN
|
4189 VLV_MEDIA_RC6_COUNT_EN
|
4190 VLV_RENDER_RC6_COUNT_EN
));
4192 if (intel_enable_rc6(dev
) & INTEL_RC6_ENABLE
)
4193 rc6_mode
= GEN7_RC_CTL_TO_MODE
| VLV_RC_CTL_CTX_RST_PARALLEL
;
4195 intel_print_rc6_info(dev
, rc6_mode
);
4197 I915_WRITE(GEN6_RC_CONTROL
, rc6_mode
);
4199 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
4201 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val
& 0x10 ? "yes" : "no");
4202 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val
);
4204 dev_priv
->rps
.cur_freq
= (val
>> 8) & 0xff;
4205 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
4206 vlv_gpu_freq(dev_priv
, dev_priv
->rps
.cur_freq
),
4207 dev_priv
->rps
.cur_freq
);
4209 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
4210 vlv_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
),
4211 dev_priv
->rps
.efficient_freq
);
4213 valleyview_set_rps(dev_priv
->dev
, dev_priv
->rps
.efficient_freq
);
4215 gen6_enable_rps_interrupts(dev
);
4217 gen6_gt_force_wake_put(dev_priv
, FORCEWAKE_ALL
);
4220 void ironlake_teardown_rc6(struct drm_device
*dev
)
4222 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4224 if (dev_priv
->ips
.renderctx
) {
4225 i915_gem_object_ggtt_unpin(dev_priv
->ips
.renderctx
);
4226 drm_gem_object_unreference(&dev_priv
->ips
.renderctx
->base
);
4227 dev_priv
->ips
.renderctx
= NULL
;
4230 if (dev_priv
->ips
.pwrctx
) {
4231 i915_gem_object_ggtt_unpin(dev_priv
->ips
.pwrctx
);
4232 drm_gem_object_unreference(&dev_priv
->ips
.pwrctx
->base
);
4233 dev_priv
->ips
.pwrctx
= NULL
;
4237 static void ironlake_disable_rc6(struct drm_device
*dev
)
4239 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4241 if (I915_READ(PWRCTXA
)) {
4242 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
4243 I915_WRITE(RSTDBYCTL
, I915_READ(RSTDBYCTL
) | RCX_SW_EXIT
);
4244 wait_for(((I915_READ(RSTDBYCTL
) & RSX_STATUS_MASK
) == RSX_STATUS_ON
),
4247 I915_WRITE(PWRCTXA
, 0);
4248 POSTING_READ(PWRCTXA
);
4250 I915_WRITE(RSTDBYCTL
, I915_READ(RSTDBYCTL
) & ~RCX_SW_EXIT
);
4251 POSTING_READ(RSTDBYCTL
);
4255 static int ironlake_setup_rc6(struct drm_device
*dev
)
4257 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4259 if (dev_priv
->ips
.renderctx
== NULL
)
4260 dev_priv
->ips
.renderctx
= intel_alloc_context_page(dev
);
4261 if (!dev_priv
->ips
.renderctx
)
4264 if (dev_priv
->ips
.pwrctx
== NULL
)
4265 dev_priv
->ips
.pwrctx
= intel_alloc_context_page(dev
);
4266 if (!dev_priv
->ips
.pwrctx
) {
4267 ironlake_teardown_rc6(dev
);
4274 static void ironlake_enable_rc6(struct drm_device
*dev
)
4276 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4277 struct intel_engine_cs
*ring
= &dev_priv
->ring
[RCS
];
4278 bool was_interruptible
;
4281 /* rc6 disabled by default due to repeated reports of hanging during
4284 if (!intel_enable_rc6(dev
))
4287 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
4289 ret
= ironlake_setup_rc6(dev
);
4293 was_interruptible
= dev_priv
->mm
.interruptible
;
4294 dev_priv
->mm
.interruptible
= false;
4297 * GPU can automatically power down the render unit if given a page
4300 ret
= intel_ring_begin(ring
, 6);
4302 ironlake_teardown_rc6(dev
);
4303 dev_priv
->mm
.interruptible
= was_interruptible
;
4307 intel_ring_emit(ring
, MI_SUSPEND_FLUSH
| MI_SUSPEND_FLUSH_EN
);
4308 intel_ring_emit(ring
, MI_SET_CONTEXT
);
4309 intel_ring_emit(ring
, i915_gem_obj_ggtt_offset(dev_priv
->ips
.renderctx
) |
4311 MI_SAVE_EXT_STATE_EN
|
4312 MI_RESTORE_EXT_STATE_EN
|
4313 MI_RESTORE_INHIBIT
);
4314 intel_ring_emit(ring
, MI_SUSPEND_FLUSH
);
4315 intel_ring_emit(ring
, MI_NOOP
);
4316 intel_ring_emit(ring
, MI_FLUSH
);
4317 intel_ring_advance(ring
);
4320 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
4321 * does an implicit flush, combined with MI_FLUSH above, it should be
4322 * safe to assume that renderctx is valid
4324 ret
= intel_ring_idle(ring
);
4325 dev_priv
->mm
.interruptible
= was_interruptible
;
4327 DRM_ERROR("failed to enable ironlake power savings\n");
4328 ironlake_teardown_rc6(dev
);
4332 I915_WRITE(PWRCTXA
, i915_gem_obj_ggtt_offset(dev_priv
->ips
.pwrctx
) | PWRCTX_EN
);
4333 I915_WRITE(RSTDBYCTL
, I915_READ(RSTDBYCTL
) & ~RCX_SW_EXIT
);
4335 intel_print_rc6_info(dev
, GEN6_RC_CTL_RC6_ENABLE
);
4338 static unsigned long intel_pxfreq(u32 vidfreq
)
4341 int div
= (vidfreq
& 0x3f0000) >> 16;
4342 int post
= (vidfreq
& 0x3000) >> 12;
4343 int pre
= (vidfreq
& 0x7);
4348 freq
= ((div
* 133333) / ((1<<post
) * pre
));
4353 static const struct cparams
{
4359 { 1, 1333, 301, 28664 },
4360 { 1, 1066, 294, 24460 },
4361 { 1, 800, 294, 25192 },
4362 { 0, 1333, 276, 27605 },
4363 { 0, 1066, 276, 27605 },
4364 { 0, 800, 231, 23784 },
4367 static unsigned long __i915_chipset_val(struct drm_i915_private
*dev_priv
)
4369 u64 total_count
, diff
, ret
;
4370 u32 count1
, count2
, count3
, m
= 0, c
= 0;
4371 unsigned long now
= jiffies_to_msecs(jiffies
), diff1
;
4374 assert_spin_locked(&mchdev_lock
);
4376 diff1
= now
- dev_priv
->ips
.last_time1
;
4378 /* Prevent division-by-zero if we are asking too fast.
4379 * Also, we don't get interesting results if we are polling
4380 * faster than once in 10ms, so just return the saved value
4384 return dev_priv
->ips
.chipset_power
;
4386 count1
= I915_READ(DMIEC
);
4387 count2
= I915_READ(DDREC
);
4388 count3
= I915_READ(CSIEC
);
4390 total_count
= count1
+ count2
+ count3
;
4392 /* FIXME: handle per-counter overflow */
4393 if (total_count
< dev_priv
->ips
.last_count1
) {
4394 diff
= ~0UL - dev_priv
->ips
.last_count1
;
4395 diff
+= total_count
;
4397 diff
= total_count
- dev_priv
->ips
.last_count1
;
4400 for (i
= 0; i
< ARRAY_SIZE(cparams
); i
++) {
4401 if (cparams
[i
].i
== dev_priv
->ips
.c_m
&&
4402 cparams
[i
].t
== dev_priv
->ips
.r_t
) {
4409 diff
= div_u64(diff
, diff1
);
4410 ret
= ((m
* diff
) + c
);
4411 ret
= div_u64(ret
, 10);
4413 dev_priv
->ips
.last_count1
= total_count
;
4414 dev_priv
->ips
.last_time1
= now
;
4416 dev_priv
->ips
.chipset_power
= ret
;
4421 unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
)
4423 struct drm_device
*dev
= dev_priv
->dev
;
4426 if (INTEL_INFO(dev
)->gen
!= 5)
4429 spin_lock_irq(&mchdev_lock
);
4431 val
= __i915_chipset_val(dev_priv
);
4433 spin_unlock_irq(&mchdev_lock
);
4438 unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
)
4440 unsigned long m
, x
, b
;
4443 tsfs
= I915_READ(TSFS
);
4445 m
= ((tsfs
& TSFS_SLOPE_MASK
) >> TSFS_SLOPE_SHIFT
);
4446 x
= I915_READ8(TR1
);
4448 b
= tsfs
& TSFS_INTR_MASK
;
4450 return ((m
* x
) / 127) - b
;
4453 static u16
pvid_to_extvid(struct drm_i915_private
*dev_priv
, u8 pxvid
)
4455 struct drm_device
*dev
= dev_priv
->dev
;
4456 static const struct v_table
{
4457 u16 vd
; /* in .1 mil */
4458 u16 vm
; /* in .1 mil */
4589 if (INTEL_INFO(dev
)->is_mobile
)
4590 return v_table
[pxvid
].vm
;
4592 return v_table
[pxvid
].vd
;
4595 static void __i915_update_gfx_val(struct drm_i915_private
*dev_priv
)
4597 u64 now
, diff
, diffms
;
4600 assert_spin_locked(&mchdev_lock
);
4602 now
= ktime_get_raw_ns();
4603 diffms
= now
- dev_priv
->ips
.last_time2
;
4604 do_div(diffms
, NSEC_PER_MSEC
);
4606 /* Don't divide by 0 */
4610 count
= I915_READ(GFXEC
);
4612 if (count
< dev_priv
->ips
.last_count2
) {
4613 diff
= ~0UL - dev_priv
->ips
.last_count2
;
4616 diff
= count
- dev_priv
->ips
.last_count2
;
4619 dev_priv
->ips
.last_count2
= count
;
4620 dev_priv
->ips
.last_time2
= now
;
4622 /* More magic constants... */
4624 diff
= div_u64(diff
, diffms
* 10);
4625 dev_priv
->ips
.gfx_power
= diff
;
4628 void i915_update_gfx_val(struct drm_i915_private
*dev_priv
)
4630 struct drm_device
*dev
= dev_priv
->dev
;
4632 if (INTEL_INFO(dev
)->gen
!= 5)
4635 spin_lock_irq(&mchdev_lock
);
4637 __i915_update_gfx_val(dev_priv
);
4639 spin_unlock_irq(&mchdev_lock
);
4642 static unsigned long __i915_gfx_val(struct drm_i915_private
*dev_priv
)
4644 unsigned long t
, corr
, state1
, corr2
, state2
;
4647 assert_spin_locked(&mchdev_lock
);
4649 pxvid
= I915_READ(PXVFREQ_BASE
+ (dev_priv
->rps
.cur_freq
* 4));
4650 pxvid
= (pxvid
>> 24) & 0x7f;
4651 ext_v
= pvid_to_extvid(dev_priv
, pxvid
);
4655 t
= i915_mch_val(dev_priv
);
4657 /* Revel in the empirically derived constants */
4659 /* Correction factor in 1/100000 units */
4661 corr
= ((t
* 2349) + 135940);
4663 corr
= ((t
* 964) + 29317);
4665 corr
= ((t
* 301) + 1004);
4667 corr
= corr
* ((150142 * state1
) / 10000 - 78642);
4669 corr2
= (corr
* dev_priv
->ips
.corr
);
4671 state2
= (corr2
* state1
) / 10000;
4672 state2
/= 100; /* convert to mW */
4674 __i915_update_gfx_val(dev_priv
);
4676 return dev_priv
->ips
.gfx_power
+ state2
;
4679 unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
)
4681 struct drm_device
*dev
= dev_priv
->dev
;
4684 if (INTEL_INFO(dev
)->gen
!= 5)
4687 spin_lock_irq(&mchdev_lock
);
4689 val
= __i915_gfx_val(dev_priv
);
4691 spin_unlock_irq(&mchdev_lock
);
4697 * i915_read_mch_val - return value for IPS use
4699 * Calculate and return a value for the IPS driver to use when deciding whether
4700 * we have thermal and power headroom to increase CPU or GPU power budget.
4702 unsigned long i915_read_mch_val(void)
4704 struct drm_i915_private
*dev_priv
;
4705 unsigned long chipset_val
, graphics_val
, ret
= 0;
4707 spin_lock_irq(&mchdev_lock
);
4710 dev_priv
= i915_mch_dev
;
4712 chipset_val
= __i915_chipset_val(dev_priv
);
4713 graphics_val
= __i915_gfx_val(dev_priv
);
4715 ret
= chipset_val
+ graphics_val
;
4718 spin_unlock_irq(&mchdev_lock
);
4722 EXPORT_SYMBOL_GPL(i915_read_mch_val
);
4725 * i915_gpu_raise - raise GPU frequency limit
4727 * Raise the limit; IPS indicates we have thermal headroom.
4729 bool i915_gpu_raise(void)
4731 struct drm_i915_private
*dev_priv
;
4734 spin_lock_irq(&mchdev_lock
);
4735 if (!i915_mch_dev
) {
4739 dev_priv
= i915_mch_dev
;
4741 if (dev_priv
->ips
.max_delay
> dev_priv
->ips
.fmax
)
4742 dev_priv
->ips
.max_delay
--;
4745 spin_unlock_irq(&mchdev_lock
);
4749 EXPORT_SYMBOL_GPL(i915_gpu_raise
);
4752 * i915_gpu_lower - lower GPU frequency limit
4754 * IPS indicates we're close to a thermal limit, so throttle back the GPU
4755 * frequency maximum.
4757 bool i915_gpu_lower(void)
4759 struct drm_i915_private
*dev_priv
;
4762 spin_lock_irq(&mchdev_lock
);
4763 if (!i915_mch_dev
) {
4767 dev_priv
= i915_mch_dev
;
4769 if (dev_priv
->ips
.max_delay
< dev_priv
->ips
.min_delay
)
4770 dev_priv
->ips
.max_delay
++;
4773 spin_unlock_irq(&mchdev_lock
);
4777 EXPORT_SYMBOL_GPL(i915_gpu_lower
);
4780 * i915_gpu_busy - indicate GPU business to IPS
4782 * Tell the IPS driver whether or not the GPU is busy.
4784 bool i915_gpu_busy(void)
4786 struct drm_i915_private
*dev_priv
;
4787 struct intel_engine_cs
*ring
;
4791 spin_lock_irq(&mchdev_lock
);
4794 dev_priv
= i915_mch_dev
;
4796 for_each_ring(ring
, dev_priv
, i
)
4797 ret
|= !list_empty(&ring
->request_list
);
4800 spin_unlock_irq(&mchdev_lock
);
4804 EXPORT_SYMBOL_GPL(i915_gpu_busy
);
4807 * i915_gpu_turbo_disable - disable graphics turbo
4809 * Disable graphics turbo by resetting the max frequency and setting the
4810 * current frequency to the default.
4812 bool i915_gpu_turbo_disable(void)
4814 struct drm_i915_private
*dev_priv
;
4817 spin_lock_irq(&mchdev_lock
);
4818 if (!i915_mch_dev
) {
4822 dev_priv
= i915_mch_dev
;
4824 dev_priv
->ips
.max_delay
= dev_priv
->ips
.fstart
;
4826 if (!ironlake_set_drps(dev_priv
->dev
, dev_priv
->ips
.fstart
))
4830 spin_unlock_irq(&mchdev_lock
);
4834 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable
);
4837 * Tells the intel_ips driver that the i915 driver is now loaded, if
4838 * IPS got loaded first.
4840 * This awkward dance is so that neither module has to depend on the
4841 * other in order for IPS to do the appropriate communication of
4842 * GPU turbo limits to i915.
4845 ips_ping_for_i915_load(void)
4849 link
= symbol_get(ips_link_to_i915_driver
);
4852 symbol_put(ips_link_to_i915_driver
);
4856 void intel_gpu_ips_init(struct drm_i915_private
*dev_priv
)
4858 /* We only register the i915 ips part with intel-ips once everything is
4859 * set up, to avoid intel-ips sneaking in and reading bogus values. */
4860 spin_lock_irq(&mchdev_lock
);
4861 i915_mch_dev
= dev_priv
;
4862 spin_unlock_irq(&mchdev_lock
);
4864 ips_ping_for_i915_load();
4867 void intel_gpu_ips_teardown(void)
4869 spin_lock_irq(&mchdev_lock
);
4870 i915_mch_dev
= NULL
;
4871 spin_unlock_irq(&mchdev_lock
);
4874 static void intel_init_emon(struct drm_device
*dev
)
4876 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4881 /* Disable to program */
4885 /* Program energy weights for various events */
4886 I915_WRITE(SDEW
, 0x15040d00);
4887 I915_WRITE(CSIEW0
, 0x007f0000);
4888 I915_WRITE(CSIEW1
, 0x1e220004);
4889 I915_WRITE(CSIEW2
, 0x04000004);
4891 for (i
= 0; i
< 5; i
++)
4892 I915_WRITE(PEW
+ (i
* 4), 0);
4893 for (i
= 0; i
< 3; i
++)
4894 I915_WRITE(DEW
+ (i
* 4), 0);
4896 /* Program P-state weights to account for frequency power adjustment */
4897 for (i
= 0; i
< 16; i
++) {
4898 u32 pxvidfreq
= I915_READ(PXVFREQ_BASE
+ (i
* 4));
4899 unsigned long freq
= intel_pxfreq(pxvidfreq
);
4900 unsigned long vid
= (pxvidfreq
& PXVFREQ_PX_MASK
) >>
4905 val
*= (freq
/ 1000);
4907 val
/= (127*127*900);
4909 DRM_ERROR("bad pxval: %ld\n", val
);
4912 /* Render standby states get 0 weight */
4916 for (i
= 0; i
< 4; i
++) {
4917 u32 val
= (pxw
[i
*4] << 24) | (pxw
[(i
*4)+1] << 16) |
4918 (pxw
[(i
*4)+2] << 8) | (pxw
[(i
*4)+3]);
4919 I915_WRITE(PXW
+ (i
* 4), val
);
4922 /* Adjust magic regs to magic values (more experimental results) */
4923 I915_WRITE(OGW0
, 0);
4924 I915_WRITE(OGW1
, 0);
4925 I915_WRITE(EG0
, 0x00007f00);
4926 I915_WRITE(EG1
, 0x0000000e);
4927 I915_WRITE(EG2
, 0x000e0000);
4928 I915_WRITE(EG3
, 0x68000300);
4929 I915_WRITE(EG4
, 0x42000000);
4930 I915_WRITE(EG5
, 0x00140031);
4934 for (i
= 0; i
< 8; i
++)
4935 I915_WRITE(PXWL
+ (i
* 4), 0);
4937 /* Enable PMON + select events */
4938 I915_WRITE(ECR
, 0x80000019);
4940 lcfuse
= I915_READ(LCFUSE02
);
4942 dev_priv
->ips
.corr
= (lcfuse
& LCFUSE_HIV_MASK
);
4945 void intel_init_gt_powersave(struct drm_device
*dev
)
4947 i915
.enable_rc6
= sanitize_rc6_option(dev
, i915
.enable_rc6
);
4949 if (IS_CHERRYVIEW(dev
))
4950 cherryview_init_gt_powersave(dev
);
4951 else if (IS_VALLEYVIEW(dev
))
4952 valleyview_init_gt_powersave(dev
);
4955 void intel_cleanup_gt_powersave(struct drm_device
*dev
)
4957 if (IS_CHERRYVIEW(dev
))
4959 else if (IS_VALLEYVIEW(dev
))
4960 valleyview_cleanup_gt_powersave(dev
);
4964 * intel_suspend_gt_powersave - suspend PM work and helper threads
4967 * We don't want to disable RC6 or other features here, we just want
4968 * to make sure any work we've queued has finished and won't bother
4969 * us while we're suspended.
4971 void intel_suspend_gt_powersave(struct drm_device
*dev
)
4973 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4975 /* Interrupts should be disabled already to avoid re-arming. */
4976 WARN_ON(intel_irqs_enabled(dev_priv
));
4978 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
4980 cancel_work_sync(&dev_priv
->rps
.work
);
4982 /* Force GPU to min freq during suspend */
4983 gen6_rps_idle(dev_priv
);
4986 void intel_disable_gt_powersave(struct drm_device
*dev
)
4988 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4990 /* Interrupts should be disabled already to avoid re-arming. */
4991 WARN_ON(intel_irqs_enabled(dev_priv
));
4993 if (IS_IRONLAKE_M(dev
)) {
4994 ironlake_disable_drps(dev
);
4995 ironlake_disable_rc6(dev
);
4996 } else if (INTEL_INFO(dev
)->gen
>= 6) {
4997 intel_suspend_gt_powersave(dev
);
4999 mutex_lock(&dev_priv
->rps
.hw_lock
);
5000 if (IS_CHERRYVIEW(dev
))
5001 cherryview_disable_rps(dev
);
5002 else if (IS_VALLEYVIEW(dev
))
5003 valleyview_disable_rps(dev
);
5005 gen6_disable_rps(dev
);
5006 dev_priv
->rps
.enabled
= false;
5007 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5011 static void intel_gen6_powersave_work(struct work_struct
*work
)
5013 struct drm_i915_private
*dev_priv
=
5014 container_of(work
, struct drm_i915_private
,
5015 rps
.delayed_resume_work
.work
);
5016 struct drm_device
*dev
= dev_priv
->dev
;
5018 mutex_lock(&dev_priv
->rps
.hw_lock
);
5020 if (IS_CHERRYVIEW(dev
)) {
5021 cherryview_enable_rps(dev
);
5022 } else if (IS_VALLEYVIEW(dev
)) {
5023 valleyview_enable_rps(dev
);
5024 } else if (IS_BROADWELL(dev
)) {
5025 gen8_enable_rps(dev
);
5026 __gen6_update_ring_freq(dev
);
5028 gen6_enable_rps(dev
);
5029 __gen6_update_ring_freq(dev
);
5031 dev_priv
->rps
.enabled
= true;
5032 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5034 intel_runtime_pm_put(dev_priv
);
5037 void intel_enable_gt_powersave(struct drm_device
*dev
)
5039 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5041 if (IS_IRONLAKE_M(dev
)) {
5042 mutex_lock(&dev
->struct_mutex
);
5043 ironlake_enable_drps(dev
);
5044 ironlake_enable_rc6(dev
);
5045 intel_init_emon(dev
);
5046 mutex_unlock(&dev
->struct_mutex
);
5047 } else if (INTEL_INFO(dev
)->gen
>= 6) {
5049 * PCU communication is slow and this doesn't need to be
5050 * done at any specific time, so do this out of our fast path
5051 * to make resume and init faster.
5053 * We depend on the HW RC6 power context save/restore
5054 * mechanism when entering D3 through runtime PM suspend. So
5055 * disable RPM until RPS/RC6 is properly setup. We can only
5056 * get here via the driver load/system resume/runtime resume
5057 * paths, so the _noresume version is enough (and in case of
5058 * runtime resume it's necessary).
5060 if (schedule_delayed_work(&dev_priv
->rps
.delayed_resume_work
,
5061 round_jiffies_up_relative(HZ
)))
5062 intel_runtime_pm_get_noresume(dev_priv
);
5066 void intel_reset_gt_powersave(struct drm_device
*dev
)
5068 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5070 dev_priv
->rps
.enabled
= false;
5071 intel_enable_gt_powersave(dev
);
5074 static void ibx_init_clock_gating(struct drm_device
*dev
)
5076 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5079 * On Ibex Peak and Cougar Point, we need to disable clock
5080 * gating for the panel power sequencer or it will fail to
5081 * start up when no ports are active.
5083 I915_WRITE(SOUTH_DSPCLK_GATE_D
, PCH_DPLSUNIT_CLOCK_GATE_DISABLE
);
5086 static void g4x_disable_trickle_feed(struct drm_device
*dev
)
5088 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5091 for_each_pipe(pipe
) {
5092 I915_WRITE(DSPCNTR(pipe
),
5093 I915_READ(DSPCNTR(pipe
)) |
5094 DISPPLANE_TRICKLE_FEED_DISABLE
);
5095 intel_flush_primary_plane(dev_priv
, pipe
);
5099 static void ilk_init_lp_watermarks(struct drm_device
*dev
)
5101 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5103 I915_WRITE(WM3_LP_ILK
, I915_READ(WM3_LP_ILK
) & ~WM1_LP_SR_EN
);
5104 I915_WRITE(WM2_LP_ILK
, I915_READ(WM2_LP_ILK
) & ~WM1_LP_SR_EN
);
5105 I915_WRITE(WM1_LP_ILK
, I915_READ(WM1_LP_ILK
) & ~WM1_LP_SR_EN
);
5108 * Don't touch WM1S_LP_EN here.
5109 * Doing so could cause underruns.
5113 static void ironlake_init_clock_gating(struct drm_device
*dev
)
5115 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5116 uint32_t dspclk_gate
= ILK_VRHUNIT_CLOCK_GATE_DISABLE
;
5120 * WaFbcDisableDpfcClockGating:ilk
5122 dspclk_gate
|= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE
|
5123 ILK_DPFCUNIT_CLOCK_GATE_DISABLE
|
5124 ILK_DPFDUNIT_CLOCK_GATE_ENABLE
;
5126 I915_WRITE(PCH_3DCGDIS0
,
5127 MARIUNIT_CLOCK_GATE_DISABLE
|
5128 SVSMUNIT_CLOCK_GATE_DISABLE
);
5129 I915_WRITE(PCH_3DCGDIS1
,
5130 VFMUNIT_CLOCK_GATE_DISABLE
);
5133 * According to the spec the following bits should be set in
5134 * order to enable memory self-refresh
5135 * The bit 22/21 of 0x42004
5136 * The bit 5 of 0x42020
5137 * The bit 15 of 0x45000
5139 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
5140 (I915_READ(ILK_DISPLAY_CHICKEN2
) |
5141 ILK_DPARB_GATE
| ILK_VSDPFD_FULL
));
5142 dspclk_gate
|= ILK_DPARBUNIT_CLOCK_GATE_ENABLE
;
5143 I915_WRITE(DISP_ARB_CTL
,
5144 (I915_READ(DISP_ARB_CTL
) |
5147 ilk_init_lp_watermarks(dev
);
5150 * Based on the document from hardware guys the following bits
5151 * should be set unconditionally in order to enable FBC.
5152 * The bit 22 of 0x42000
5153 * The bit 22 of 0x42004
5154 * The bit 7,8,9 of 0x42020.
5156 if (IS_IRONLAKE_M(dev
)) {
5157 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
5158 I915_WRITE(ILK_DISPLAY_CHICKEN1
,
5159 I915_READ(ILK_DISPLAY_CHICKEN1
) |
5161 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
5162 I915_READ(ILK_DISPLAY_CHICKEN2
) |
5166 I915_WRITE(ILK_DSPCLK_GATE_D
, dspclk_gate
);
5168 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
5169 I915_READ(ILK_DISPLAY_CHICKEN2
) |
5170 ILK_ELPIN_409_SELECT
);
5171 I915_WRITE(_3D_CHICKEN2
,
5172 _3D_CHICKEN2_WM_READ_PIPELINED
<< 16 |
5173 _3D_CHICKEN2_WM_READ_PIPELINED
);
5175 /* WaDisableRenderCachePipelinedFlush:ilk */
5176 I915_WRITE(CACHE_MODE_0
,
5177 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE
));
5179 /* WaDisable_RenderCache_OperationalFlush:ilk */
5180 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
5182 g4x_disable_trickle_feed(dev
);
5184 ibx_init_clock_gating(dev
);
5187 static void cpt_init_clock_gating(struct drm_device
*dev
)
5189 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5194 * On Ibex Peak and Cougar Point, we need to disable clock
5195 * gating for the panel power sequencer or it will fail to
5196 * start up when no ports are active.
5198 I915_WRITE(SOUTH_DSPCLK_GATE_D
, PCH_DPLSUNIT_CLOCK_GATE_DISABLE
|
5199 PCH_DPLUNIT_CLOCK_GATE_DISABLE
|
5200 PCH_CPUNIT_CLOCK_GATE_DISABLE
);
5201 I915_WRITE(SOUTH_CHICKEN2
, I915_READ(SOUTH_CHICKEN2
) |
5202 DPLS_EDP_PPS_FIX_DIS
);
5203 /* The below fixes the weird display corruption, a few pixels shifted
5204 * downward, on (only) LVDS of some HP laptops with IVY.
5206 for_each_pipe(pipe
) {
5207 val
= I915_READ(TRANS_CHICKEN2(pipe
));
5208 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
5209 val
&= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED
;
5210 if (dev_priv
->vbt
.fdi_rx_polarity_inverted
)
5211 val
|= TRANS_CHICKEN2_FDI_POLARITY_REVERSED
;
5212 val
&= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK
;
5213 val
&= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER
;
5214 val
&= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH
;
5215 I915_WRITE(TRANS_CHICKEN2(pipe
), val
);
5217 /* WADP0ClockGatingDisable */
5218 for_each_pipe(pipe
) {
5219 I915_WRITE(TRANS_CHICKEN1(pipe
),
5220 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE
);
5224 static void gen6_check_mch_setup(struct drm_device
*dev
)
5226 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5229 tmp
= I915_READ(MCH_SSKPD
);
5230 if ((tmp
& MCH_SSKPD_WM0_MASK
) != MCH_SSKPD_WM0_VAL
)
5231 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
5235 static void gen6_init_clock_gating(struct drm_device
*dev
)
5237 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5238 uint32_t dspclk_gate
= ILK_VRHUNIT_CLOCK_GATE_DISABLE
;
5240 I915_WRITE(ILK_DSPCLK_GATE_D
, dspclk_gate
);
5242 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
5243 I915_READ(ILK_DISPLAY_CHICKEN2
) |
5244 ILK_ELPIN_409_SELECT
);
5246 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
5247 I915_WRITE(_3D_CHICKEN
,
5248 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB
));
5250 /* WaSetupGtModeTdRowDispatch:snb */
5251 if (IS_SNB_GT1(dev
))
5252 I915_WRITE(GEN6_GT_MODE
,
5253 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE
));
5255 /* WaDisable_RenderCache_OperationalFlush:snb */
5256 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
5259 * BSpec recoomends 8x4 when MSAA is used,
5260 * however in practice 16x4 seems fastest.
5262 * Note that PS/WM thread counts depend on the WIZ hashing
5263 * disable bit, which we don't touch here, but it's good
5264 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5266 I915_WRITE(GEN6_GT_MODE
,
5267 GEN6_WIZ_HASHING_MASK
| GEN6_WIZ_HASHING_16x4
);
5269 ilk_init_lp_watermarks(dev
);
5271 I915_WRITE(CACHE_MODE_0
,
5272 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB
));
5274 I915_WRITE(GEN6_UCGCTL1
,
5275 I915_READ(GEN6_UCGCTL1
) |
5276 GEN6_BLBUNIT_CLOCK_GATE_DISABLE
|
5277 GEN6_CSUNIT_CLOCK_GATE_DISABLE
);
5279 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5280 * gating disable must be set. Failure to set it results in
5281 * flickering pixels due to Z write ordering failures after
5282 * some amount of runtime in the Mesa "fire" demo, and Unigine
5283 * Sanctuary and Tropics, and apparently anything else with
5284 * alpha test or pixel discard.
5286 * According to the spec, bit 11 (RCCUNIT) must also be set,
5287 * but we didn't debug actual testcases to find it out.
5289 * WaDisableRCCUnitClockGating:snb
5290 * WaDisableRCPBUnitClockGating:snb
5292 I915_WRITE(GEN6_UCGCTL2
,
5293 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE
|
5294 GEN6_RCCUNIT_CLOCK_GATE_DISABLE
);
5296 /* WaStripsFansDisableFastClipPerformanceFix:snb */
5297 I915_WRITE(_3D_CHICKEN3
,
5298 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL
));
5302 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
5303 * 3DSTATE_SF number of SF output attributes is more than 16."
5305 I915_WRITE(_3D_CHICKEN3
,
5306 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH
));
5309 * According to the spec the following bits should be
5310 * set in order to enable memory self-refresh and fbc:
5311 * The bit21 and bit22 of 0x42000
5312 * The bit21 and bit22 of 0x42004
5313 * The bit5 and bit7 of 0x42020
5314 * The bit14 of 0x70180
5315 * The bit14 of 0x71180
5317 * WaFbcAsynchFlipDisableFbcQueue:snb
5319 I915_WRITE(ILK_DISPLAY_CHICKEN1
,
5320 I915_READ(ILK_DISPLAY_CHICKEN1
) |
5321 ILK_FBCQ_DIS
| ILK_PABSTRETCH_DIS
);
5322 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
5323 I915_READ(ILK_DISPLAY_CHICKEN2
) |
5324 ILK_DPARB_GATE
| ILK_VSDPFD_FULL
);
5325 I915_WRITE(ILK_DSPCLK_GATE_D
,
5326 I915_READ(ILK_DSPCLK_GATE_D
) |
5327 ILK_DPARBUNIT_CLOCK_GATE_ENABLE
|
5328 ILK_DPFDUNIT_CLOCK_GATE_ENABLE
);
5330 g4x_disable_trickle_feed(dev
);
5332 cpt_init_clock_gating(dev
);
5334 gen6_check_mch_setup(dev
);
5337 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private
*dev_priv
)
5339 uint32_t reg
= I915_READ(GEN7_FF_THREAD_MODE
);
5342 * WaVSThreadDispatchOverride:ivb,vlv
5344 * This actually overrides the dispatch
5345 * mode for all thread types.
5347 reg
&= ~GEN7_FF_SCHED_MASK
;
5348 reg
|= GEN7_FF_TS_SCHED_HW
;
5349 reg
|= GEN7_FF_VS_SCHED_HW
;
5350 reg
|= GEN7_FF_DS_SCHED_HW
;
5352 I915_WRITE(GEN7_FF_THREAD_MODE
, reg
);
5355 static void lpt_init_clock_gating(struct drm_device
*dev
)
5357 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5360 * TODO: this bit should only be enabled when really needed, then
5361 * disabled when not needed anymore in order to save power.
5363 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
)
5364 I915_WRITE(SOUTH_DSPCLK_GATE_D
,
5365 I915_READ(SOUTH_DSPCLK_GATE_D
) |
5366 PCH_LP_PARTITION_LEVEL_DISABLE
);
5368 /* WADPOClockGatingDisable:hsw */
5369 I915_WRITE(_TRANSA_CHICKEN1
,
5370 I915_READ(_TRANSA_CHICKEN1
) |
5371 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE
);
5374 static void lpt_suspend_hw(struct drm_device
*dev
)
5376 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5378 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
5379 uint32_t val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
5381 val
&= ~PCH_LP_PARTITION_LEVEL_DISABLE
;
5382 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
5386 static void gen8_init_clock_gating(struct drm_device
*dev
)
5388 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5391 I915_WRITE(WM3_LP_ILK
, 0);
5392 I915_WRITE(WM2_LP_ILK
, 0);
5393 I915_WRITE(WM1_LP_ILK
, 0);
5395 /* FIXME(BDW): Check all the w/a, some might only apply to
5396 * pre-production hw. */
5398 /* WaDisablePartialInstShootdown:bdw */
5399 I915_WRITE(GEN8_ROW_CHICKEN
,
5400 _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE
));
5402 /* WaDisableThreadStallDopClockGating:bdw */
5403 /* FIXME: Unclear whether we really need this on production bdw. */
5404 I915_WRITE(GEN8_ROW_CHICKEN
,
5405 _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE
));
5408 * This GEN8_CENTROID_PIXEL_OPT_DIS W/A is only needed for
5409 * pre-production hardware
5411 I915_WRITE(HALF_SLICE_CHICKEN3
,
5412 _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS
));
5413 I915_WRITE(HALF_SLICE_CHICKEN3
,
5414 _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS
));
5415 I915_WRITE(GAMTARBMODE
, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE
));
5417 I915_WRITE(_3D_CHICKEN3
,
5418 _MASKED_BIT_ENABLE(_3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2)));
5420 I915_WRITE(COMMON_SLICE_CHICKEN2
,
5421 _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE
));
5423 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1
,
5424 _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE
));
5426 /* WaDisableDopClockGating:bdw May not be needed for production */
5427 I915_WRITE(GEN7_ROW_CHICKEN2
,
5428 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
5430 /* WaSwitchSolVfFArbitrationPriority:bdw */
5431 I915_WRITE(GAM_ECOCHK
, I915_READ(GAM_ECOCHK
) | HSW_ECOCHK_ARB_PRIO_SOL
);
5433 /* WaPsrDPAMaskVBlankInSRD:bdw */
5434 I915_WRITE(CHICKEN_PAR1_1
,
5435 I915_READ(CHICKEN_PAR1_1
) | DPA_MASK_VBLANK_SRD
);
5437 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
5438 for_each_pipe(pipe
) {
5439 I915_WRITE(CHICKEN_PIPESL_1(pipe
),
5440 I915_READ(CHICKEN_PIPESL_1(pipe
)) |
5441 BDW_DPRS_MASK_VBLANK_SRD
);
5444 /* Use Force Non-Coherent whenever executing a 3D context. This is a
5445 * workaround for for a possible hang in the unlikely event a TLB
5446 * invalidation occurs during a PSD flush.
5448 I915_WRITE(HDC_CHICKEN0
,
5449 I915_READ(HDC_CHICKEN0
) |
5450 _MASKED_BIT_ENABLE(HDC_FORCE_NON_COHERENT
));
5452 /* WaVSRefCountFullforceMissDisable:bdw */
5453 /* WaDSRefCountFullforceMissDisable:bdw */
5454 I915_WRITE(GEN7_FF_THREAD_MODE
,
5455 I915_READ(GEN7_FF_THREAD_MODE
) &
5456 ~(GEN8_FF_DS_REF_CNT_FFME
| GEN7_FF_VS_REF_CNT_FFME
));
5459 * BSpec recommends 8x4 when MSAA is used,
5460 * however in practice 16x4 seems fastest.
5462 * Note that PS/WM thread counts depend on the WIZ hashing
5463 * disable bit, which we don't touch here, but it's good
5464 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5466 I915_WRITE(GEN7_GT_MODE
,
5467 GEN6_WIZ_HASHING_MASK
| GEN6_WIZ_HASHING_16x4
);
5469 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL
,
5470 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE
));
5472 /* WaDisableSDEUnitClockGating:bdw */
5473 I915_WRITE(GEN8_UCGCTL6
, I915_READ(GEN8_UCGCTL6
) |
5474 GEN8_SDEUNIT_CLOCK_GATE_DISABLE
);
5476 /* Wa4x4STCOptimizationDisable:bdw */
5477 I915_WRITE(CACHE_MODE_1
,
5478 _MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE
));
5481 static void haswell_init_clock_gating(struct drm_device
*dev
)
5483 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5485 ilk_init_lp_watermarks(dev
);
5487 /* L3 caching of data atomics doesn't work -- disable it. */
5488 I915_WRITE(HSW_SCRATCH1
, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE
);
5489 I915_WRITE(HSW_ROW_CHICKEN3
,
5490 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE
));
5492 /* This is required by WaCatErrorRejectionIssue:hsw */
5493 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
5494 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
5495 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
5497 /* WaVSRefCountFullforceMissDisable:hsw */
5498 I915_WRITE(GEN7_FF_THREAD_MODE
,
5499 I915_READ(GEN7_FF_THREAD_MODE
) & ~GEN7_FF_VS_REF_CNT_FFME
);
5501 /* WaDisable_RenderCache_OperationalFlush:hsw */
5502 I915_WRITE(CACHE_MODE_0_GEN7
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
5504 /* enable HiZ Raw Stall Optimization */
5505 I915_WRITE(CACHE_MODE_0_GEN7
,
5506 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE
));
5508 /* WaDisable4x2SubspanOptimization:hsw */
5509 I915_WRITE(CACHE_MODE_1
,
5510 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
));
5513 * BSpec recommends 8x4 when MSAA is used,
5514 * however in practice 16x4 seems fastest.
5516 * Note that PS/WM thread counts depend on the WIZ hashing
5517 * disable bit, which we don't touch here, but it's good
5518 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5520 I915_WRITE(GEN7_GT_MODE
,
5521 GEN6_WIZ_HASHING_MASK
| GEN6_WIZ_HASHING_16x4
);
5523 /* WaSwitchSolVfFArbitrationPriority:hsw */
5524 I915_WRITE(GAM_ECOCHK
, I915_READ(GAM_ECOCHK
) | HSW_ECOCHK_ARB_PRIO_SOL
);
5526 /* WaRsPkgCStateDisplayPMReq:hsw */
5527 I915_WRITE(CHICKEN_PAR1_1
,
5528 I915_READ(CHICKEN_PAR1_1
) | FORCE_ARB_IDLE_PLANES
);
5530 lpt_init_clock_gating(dev
);
5533 static void ivybridge_init_clock_gating(struct drm_device
*dev
)
5535 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5538 ilk_init_lp_watermarks(dev
);
5540 I915_WRITE(ILK_DSPCLK_GATE_D
, ILK_VRHUNIT_CLOCK_GATE_DISABLE
);
5542 /* WaDisableEarlyCull:ivb */
5543 I915_WRITE(_3D_CHICKEN3
,
5544 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL
));
5546 /* WaDisableBackToBackFlipFix:ivb */
5547 I915_WRITE(IVB_CHICKEN3
,
5548 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE
|
5549 CHICKEN3_DGMG_DONE_FIX_DISABLE
);
5551 /* WaDisablePSDDualDispatchEnable:ivb */
5552 if (IS_IVB_GT1(dev
))
5553 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1
,
5554 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE
));
5556 /* WaDisable_RenderCache_OperationalFlush:ivb */
5557 I915_WRITE(CACHE_MODE_0_GEN7
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
5559 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
5560 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1
,
5561 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC
);
5563 /* WaApplyL3ControlAndL3ChickenMode:ivb */
5564 I915_WRITE(GEN7_L3CNTLREG1
,
5565 GEN7_WA_FOR_GEN7_L3_CONTROL
);
5566 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER
,
5567 GEN7_WA_L3_CHICKEN_MODE
);
5568 if (IS_IVB_GT1(dev
))
5569 I915_WRITE(GEN7_ROW_CHICKEN2
,
5570 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
5572 /* must write both registers */
5573 I915_WRITE(GEN7_ROW_CHICKEN2
,
5574 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
5575 I915_WRITE(GEN7_ROW_CHICKEN2_GT2
,
5576 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
5579 /* WaForceL3Serialization:ivb */
5580 I915_WRITE(GEN7_L3SQCREG4
, I915_READ(GEN7_L3SQCREG4
) &
5581 ~L3SQ_URB_READ_CAM_MATCH_DISABLE
);
5584 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5585 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
5587 I915_WRITE(GEN6_UCGCTL2
,
5588 GEN6_RCZUNIT_CLOCK_GATE_DISABLE
);
5590 /* This is required by WaCatErrorRejectionIssue:ivb */
5591 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
5592 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
5593 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
5595 g4x_disable_trickle_feed(dev
);
5597 gen7_setup_fixed_func_scheduler(dev_priv
);
5599 if (0) { /* causes HiZ corruption on ivb:gt1 */
5600 /* enable HiZ Raw Stall Optimization */
5601 I915_WRITE(CACHE_MODE_0_GEN7
,
5602 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE
));
5605 /* WaDisable4x2SubspanOptimization:ivb */
5606 I915_WRITE(CACHE_MODE_1
,
5607 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
));
5610 * BSpec recommends 8x4 when MSAA is used,
5611 * however in practice 16x4 seems fastest.
5613 * Note that PS/WM thread counts depend on the WIZ hashing
5614 * disable bit, which we don't touch here, but it's good
5615 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5617 I915_WRITE(GEN7_GT_MODE
,
5618 GEN6_WIZ_HASHING_MASK
| GEN6_WIZ_HASHING_16x4
);
5620 snpcr
= I915_READ(GEN6_MBCUNIT_SNPCR
);
5621 snpcr
&= ~GEN6_MBC_SNPCR_MASK
;
5622 snpcr
|= GEN6_MBC_SNPCR_MED
;
5623 I915_WRITE(GEN6_MBCUNIT_SNPCR
, snpcr
);
5625 if (!HAS_PCH_NOP(dev
))
5626 cpt_init_clock_gating(dev
);
5628 gen6_check_mch_setup(dev
);
5631 static void valleyview_init_clock_gating(struct drm_device
*dev
)
5633 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5636 mutex_lock(&dev_priv
->rps
.hw_lock
);
5637 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
5638 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5639 switch ((val
>> 6) & 3) {
5642 dev_priv
->mem_freq
= 800;
5645 dev_priv
->mem_freq
= 1066;
5648 dev_priv
->mem_freq
= 1333;
5651 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv
->mem_freq
);
5653 I915_WRITE(DSPCLK_GATE_D
, VRHUNIT_CLOCK_GATE_DISABLE
);
5655 /* WaDisableEarlyCull:vlv */
5656 I915_WRITE(_3D_CHICKEN3
,
5657 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL
));
5659 /* WaDisableBackToBackFlipFix:vlv */
5660 I915_WRITE(IVB_CHICKEN3
,
5661 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE
|
5662 CHICKEN3_DGMG_DONE_FIX_DISABLE
);
5664 /* WaPsdDispatchEnable:vlv */
5665 /* WaDisablePSDDualDispatchEnable:vlv */
5666 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1
,
5667 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP
|
5668 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE
));
5670 /* WaDisable_RenderCache_OperationalFlush:vlv */
5671 I915_WRITE(CACHE_MODE_0_GEN7
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
5673 /* WaForceL3Serialization:vlv */
5674 I915_WRITE(GEN7_L3SQCREG4
, I915_READ(GEN7_L3SQCREG4
) &
5675 ~L3SQ_URB_READ_CAM_MATCH_DISABLE
);
5677 /* WaDisableDopClockGating:vlv */
5678 I915_WRITE(GEN7_ROW_CHICKEN2
,
5679 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
5681 /* This is required by WaCatErrorRejectionIssue:vlv */
5682 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
5683 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
5684 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
5686 gen7_setup_fixed_func_scheduler(dev_priv
);
5689 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5690 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
5692 I915_WRITE(GEN6_UCGCTL2
,
5693 GEN6_RCZUNIT_CLOCK_GATE_DISABLE
);
5695 /* WaDisableL3Bank2xClockGate:vlv
5696 * Disabling L3 clock gating- MMIO 940c[25] = 1
5697 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
5698 I915_WRITE(GEN7_UCGCTL4
,
5699 I915_READ(GEN7_UCGCTL4
) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE
);
5701 I915_WRITE(MI_ARB_VLV
, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
);
5704 * BSpec says this must be set, even though
5705 * WaDisable4x2SubspanOptimization isn't listed for VLV.
5707 I915_WRITE(CACHE_MODE_1
,
5708 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
));
5711 * WaIncreaseL3CreditsForVLVB0:vlv
5712 * This is the hardware default actually.
5714 I915_WRITE(GEN7_L3SQCREG1
, VLV_B0_WA_L3SQCREG1_VALUE
);
5717 * WaDisableVLVClockGating_VBIIssue:vlv
5718 * Disable clock gating on th GCFG unit to prevent a delay
5719 * in the reporting of vblank events.
5721 I915_WRITE(VLV_GUNIT_CLOCK_GATE
, GCFG_DIS
);
5724 static void cherryview_init_clock_gating(struct drm_device
*dev
)
5726 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5729 mutex_lock(&dev_priv
->rps
.hw_lock
);
5730 val
= vlv_punit_read(dev_priv
, CCK_FUSE_REG
);
5731 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5732 switch ((val
>> 2) & 0x7) {
5735 dev_priv
->rps
.cz_freq
= CHV_CZ_CLOCK_FREQ_MODE_200
;
5736 dev_priv
->mem_freq
= 1600;
5739 dev_priv
->rps
.cz_freq
= CHV_CZ_CLOCK_FREQ_MODE_267
;
5740 dev_priv
->mem_freq
= 1600;
5743 dev_priv
->rps
.cz_freq
= CHV_CZ_CLOCK_FREQ_MODE_333
;
5744 dev_priv
->mem_freq
= 2000;
5747 dev_priv
->rps
.cz_freq
= CHV_CZ_CLOCK_FREQ_MODE_320
;
5748 dev_priv
->mem_freq
= 1600;
5751 dev_priv
->rps
.cz_freq
= CHV_CZ_CLOCK_FREQ_MODE_400
;
5752 dev_priv
->mem_freq
= 1600;
5755 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv
->mem_freq
);
5757 I915_WRITE(DSPCLK_GATE_D
, VRHUNIT_CLOCK_GATE_DISABLE
);
5759 I915_WRITE(MI_ARB_VLV
, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
);
5761 /* WaDisablePartialInstShootdown:chv */
5762 I915_WRITE(GEN8_ROW_CHICKEN
,
5763 _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE
));
5765 /* WaDisableThreadStallDopClockGating:chv */
5766 I915_WRITE(GEN8_ROW_CHICKEN
,
5767 _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE
));
5769 /* WaVSRefCountFullforceMissDisable:chv */
5770 /* WaDSRefCountFullforceMissDisable:chv */
5771 I915_WRITE(GEN7_FF_THREAD_MODE
,
5772 I915_READ(GEN7_FF_THREAD_MODE
) &
5773 ~(GEN8_FF_DS_REF_CNT_FFME
| GEN7_FF_VS_REF_CNT_FFME
));
5775 /* WaDisableSemaphoreAndSyncFlipWait:chv */
5776 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL
,
5777 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE
));
5779 /* WaDisableCSUnitClockGating:chv */
5780 I915_WRITE(GEN6_UCGCTL1
, I915_READ(GEN6_UCGCTL1
) |
5781 GEN6_CSUNIT_CLOCK_GATE_DISABLE
);
5783 /* WaDisableSDEUnitClockGating:chv */
5784 I915_WRITE(GEN8_UCGCTL6
, I915_READ(GEN8_UCGCTL6
) |
5785 GEN8_SDEUNIT_CLOCK_GATE_DISABLE
);
5787 /* WaDisableSamplerPowerBypass:chv (pre-production hw) */
5788 I915_WRITE(HALF_SLICE_CHICKEN3
,
5789 _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS
));
5791 /* WaDisableGunitClockGating:chv (pre-production hw) */
5792 I915_WRITE(VLV_GUNIT_CLOCK_GATE
, I915_READ(VLV_GUNIT_CLOCK_GATE
) |
5795 /* WaDisableFfDopClockGating:chv (pre-production hw) */
5796 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL
,
5797 _MASKED_BIT_ENABLE(GEN8_FF_DOP_CLOCK_GATE_DISABLE
));
5799 /* WaDisableDopClockGating:chv (pre-production hw) */
5800 I915_WRITE(GEN7_ROW_CHICKEN2
,
5801 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
5802 I915_WRITE(GEN6_UCGCTL1
, I915_READ(GEN6_UCGCTL1
) |
5803 GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE
);
5806 static void g4x_init_clock_gating(struct drm_device
*dev
)
5808 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5809 uint32_t dspclk_gate
;
5811 I915_WRITE(RENCLK_GATE_D1
, 0);
5812 I915_WRITE(RENCLK_GATE_D2
, VF_UNIT_CLOCK_GATE_DISABLE
|
5813 GS_UNIT_CLOCK_GATE_DISABLE
|
5814 CL_UNIT_CLOCK_GATE_DISABLE
);
5815 I915_WRITE(RAMCLK_GATE_D
, 0);
5816 dspclk_gate
= VRHUNIT_CLOCK_GATE_DISABLE
|
5817 OVRUNIT_CLOCK_GATE_DISABLE
|
5818 OVCUNIT_CLOCK_GATE_DISABLE
;
5820 dspclk_gate
|= DSSUNIT_CLOCK_GATE_DISABLE
;
5821 I915_WRITE(DSPCLK_GATE_D
, dspclk_gate
);
5823 /* WaDisableRenderCachePipelinedFlush */
5824 I915_WRITE(CACHE_MODE_0
,
5825 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE
));
5827 /* WaDisable_RenderCache_OperationalFlush:g4x */
5828 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
5830 g4x_disable_trickle_feed(dev
);
5833 static void crestline_init_clock_gating(struct drm_device
*dev
)
5835 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5837 I915_WRITE(RENCLK_GATE_D1
, I965_RCC_CLOCK_GATE_DISABLE
);
5838 I915_WRITE(RENCLK_GATE_D2
, 0);
5839 I915_WRITE(DSPCLK_GATE_D
, 0);
5840 I915_WRITE(RAMCLK_GATE_D
, 0);
5841 I915_WRITE16(DEUC
, 0);
5842 I915_WRITE(MI_ARB_STATE
,
5843 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
));
5845 /* WaDisable_RenderCache_OperationalFlush:gen4 */
5846 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
5849 static void broadwater_init_clock_gating(struct drm_device
*dev
)
5851 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5853 I915_WRITE(RENCLK_GATE_D1
, I965_RCZ_CLOCK_GATE_DISABLE
|
5854 I965_RCC_CLOCK_GATE_DISABLE
|
5855 I965_RCPB_CLOCK_GATE_DISABLE
|
5856 I965_ISC_CLOCK_GATE_DISABLE
|
5857 I965_FBC_CLOCK_GATE_DISABLE
);
5858 I915_WRITE(RENCLK_GATE_D2
, 0);
5859 I915_WRITE(MI_ARB_STATE
,
5860 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
));
5862 /* WaDisable_RenderCache_OperationalFlush:gen4 */
5863 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
5866 static void gen3_init_clock_gating(struct drm_device
*dev
)
5868 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5869 u32 dstate
= I915_READ(D_STATE
);
5871 dstate
|= DSTATE_PLL_D3_OFF
| DSTATE_GFX_CLOCK_GATING
|
5872 DSTATE_DOT_CLOCK_GATING
;
5873 I915_WRITE(D_STATE
, dstate
);
5875 if (IS_PINEVIEW(dev
))
5876 I915_WRITE(ECOSKPD
, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY
));
5878 /* IIR "flip pending" means done if this bit is set */
5879 I915_WRITE(ECOSKPD
, _MASKED_BIT_DISABLE(ECO_FLIP_DONE
));
5881 /* interrupts should cause a wake up from C3 */
5882 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN
));
5884 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
5885 I915_WRITE(MI_ARB_STATE
, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE
));
5888 static void i85x_init_clock_gating(struct drm_device
*dev
)
5890 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5892 I915_WRITE(RENCLK_GATE_D1
, SV_CLOCK_GATE_DISABLE
);
5894 /* interrupts should cause a wake up from C3 */
5895 I915_WRITE(MI_STATE
, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN
) |
5896 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE
));
5899 static void i830_init_clock_gating(struct drm_device
*dev
)
5901 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5903 I915_WRITE(DSPCLK_GATE_D
, OVRUNIT_CLOCK_GATE_DISABLE
);
5906 void intel_init_clock_gating(struct drm_device
*dev
)
5908 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5910 dev_priv
->display
.init_clock_gating(dev
);
5913 void intel_suspend_hw(struct drm_device
*dev
)
5915 if (HAS_PCH_LPT(dev
))
5916 lpt_suspend_hw(dev
);
5919 #define for_each_power_well(i, power_well, domain_mask, power_domains) \
5921 i < (power_domains)->power_well_count && \
5922 ((power_well) = &(power_domains)->power_wells[i]); \
5924 if ((power_well)->domains & (domain_mask))
5926 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
5927 for (i = (power_domains)->power_well_count - 1; \
5928 i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
5930 if ((power_well)->domains & (domain_mask))
5933 * We should only use the power well if we explicitly asked the hardware to
5934 * enable it, so check if it's enabled and also check if we've requested it to
5937 static bool hsw_power_well_enabled(struct drm_i915_private
*dev_priv
,
5938 struct i915_power_well
*power_well
)
5940 return I915_READ(HSW_PWR_WELL_DRIVER
) ==
5941 (HSW_PWR_WELL_ENABLE_REQUEST
| HSW_PWR_WELL_STATE_ENABLED
);
5944 bool intel_display_power_enabled_unlocked(struct drm_i915_private
*dev_priv
,
5945 enum intel_display_power_domain domain
)
5947 struct i915_power_domains
*power_domains
;
5948 struct i915_power_well
*power_well
;
5952 if (dev_priv
->pm
.suspended
)
5955 power_domains
= &dev_priv
->power_domains
;
5959 for_each_power_well_rev(i
, power_well
, BIT(domain
), power_domains
) {
5960 if (power_well
->always_on
)
5963 if (!power_well
->hw_enabled
) {
5972 bool intel_display_power_enabled(struct drm_i915_private
*dev_priv
,
5973 enum intel_display_power_domain domain
)
5975 struct i915_power_domains
*power_domains
;
5978 power_domains
= &dev_priv
->power_domains
;
5980 mutex_lock(&power_domains
->lock
);
5981 ret
= intel_display_power_enabled_unlocked(dev_priv
, domain
);
5982 mutex_unlock(&power_domains
->lock
);
5988 * Starting with Haswell, we have a "Power Down Well" that can be turned off
5989 * when not needed anymore. We have 4 registers that can request the power well
5990 * to be enabled, and it will only be disabled if none of the registers is
5991 * requesting it to be enabled.
5993 static void hsw_power_well_post_enable(struct drm_i915_private
*dev_priv
)
5995 struct drm_device
*dev
= dev_priv
->dev
;
5998 * After we re-enable the power well, if we touch VGA register 0x3d5
5999 * we'll get unclaimed register interrupts. This stops after we write
6000 * anything to the VGA MSR register. The vgacon module uses this
6001 * register all the time, so if we unbind our driver and, as a
6002 * consequence, bind vgacon, we'll get stuck in an infinite loop at
6003 * console_unlock(). So make here we touch the VGA MSR register, making
6004 * sure vgacon can keep working normally without triggering interrupts
6005 * and error messages.
6007 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
6008 outb(inb(VGA_MSR_READ
), VGA_MSR_WRITE
);
6009 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
6011 if (IS_BROADWELL(dev
))
6012 gen8_irq_power_well_post_enable(dev_priv
);
6015 static void hsw_set_power_well(struct drm_i915_private
*dev_priv
,
6016 struct i915_power_well
*power_well
, bool enable
)
6018 bool is_enabled
, enable_requested
;
6021 tmp
= I915_READ(HSW_PWR_WELL_DRIVER
);
6022 is_enabled
= tmp
& HSW_PWR_WELL_STATE_ENABLED
;
6023 enable_requested
= tmp
& HSW_PWR_WELL_ENABLE_REQUEST
;
6026 if (!enable_requested
)
6027 I915_WRITE(HSW_PWR_WELL_DRIVER
,
6028 HSW_PWR_WELL_ENABLE_REQUEST
);
6031 DRM_DEBUG_KMS("Enabling power well\n");
6032 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER
) &
6033 HSW_PWR_WELL_STATE_ENABLED
), 20))
6034 DRM_ERROR("Timeout enabling power well\n");
6037 hsw_power_well_post_enable(dev_priv
);
6039 if (enable_requested
) {
6040 I915_WRITE(HSW_PWR_WELL_DRIVER
, 0);
6041 POSTING_READ(HSW_PWR_WELL_DRIVER
);
6042 DRM_DEBUG_KMS("Requesting to disable the power well\n");
6047 static void hsw_power_well_sync_hw(struct drm_i915_private
*dev_priv
,
6048 struct i915_power_well
*power_well
)
6050 hsw_set_power_well(dev_priv
, power_well
, power_well
->count
> 0);
6053 * We're taking over the BIOS, so clear any requests made by it since
6054 * the driver is in charge now.
6056 if (I915_READ(HSW_PWR_WELL_BIOS
) & HSW_PWR_WELL_ENABLE_REQUEST
)
6057 I915_WRITE(HSW_PWR_WELL_BIOS
, 0);
6060 static void hsw_power_well_enable(struct drm_i915_private
*dev_priv
,
6061 struct i915_power_well
*power_well
)
6063 hsw_set_power_well(dev_priv
, power_well
, true);
6066 static void hsw_power_well_disable(struct drm_i915_private
*dev_priv
,
6067 struct i915_power_well
*power_well
)
6069 hsw_set_power_well(dev_priv
, power_well
, false);
6072 static void i9xx_always_on_power_well_noop(struct drm_i915_private
*dev_priv
,
6073 struct i915_power_well
*power_well
)
6077 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private
*dev_priv
,
6078 struct i915_power_well
*power_well
)
6083 static void vlv_set_power_well(struct drm_i915_private
*dev_priv
,
6084 struct i915_power_well
*power_well
, bool enable
)
6086 enum punit_power_well power_well_id
= power_well
->data
;
6091 mask
= PUNIT_PWRGT_MASK(power_well_id
);
6092 state
= enable
? PUNIT_PWRGT_PWR_ON(power_well_id
) :
6093 PUNIT_PWRGT_PWR_GATE(power_well_id
);
6095 mutex_lock(&dev_priv
->rps
.hw_lock
);
6098 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
6103 ctrl
= vlv_punit_read(dev_priv
, PUNIT_REG_PWRGT_CTRL
);
6106 vlv_punit_write(dev_priv
, PUNIT_REG_PWRGT_CTRL
, ctrl
);
6108 if (wait_for(COND
, 100))
6109 DRM_ERROR("timout setting power well state %08x (%08x)\n",
6111 vlv_punit_read(dev_priv
, PUNIT_REG_PWRGT_CTRL
));
6116 mutex_unlock(&dev_priv
->rps
.hw_lock
);
6119 static void vlv_power_well_sync_hw(struct drm_i915_private
*dev_priv
,
6120 struct i915_power_well
*power_well
)
6122 vlv_set_power_well(dev_priv
, power_well
, power_well
->count
> 0);
6125 static void vlv_power_well_enable(struct drm_i915_private
*dev_priv
,
6126 struct i915_power_well
*power_well
)
6128 vlv_set_power_well(dev_priv
, power_well
, true);
6131 static void vlv_power_well_disable(struct drm_i915_private
*dev_priv
,
6132 struct i915_power_well
*power_well
)
6134 vlv_set_power_well(dev_priv
, power_well
, false);
6137 static bool vlv_power_well_enabled(struct drm_i915_private
*dev_priv
,
6138 struct i915_power_well
*power_well
)
6140 int power_well_id
= power_well
->data
;
6141 bool enabled
= false;
6146 mask
= PUNIT_PWRGT_MASK(power_well_id
);
6147 ctrl
= PUNIT_PWRGT_PWR_ON(power_well_id
);
6149 mutex_lock(&dev_priv
->rps
.hw_lock
);
6151 state
= vlv_punit_read(dev_priv
, PUNIT_REG_PWRGT_STATUS
) & mask
;
6153 * We only ever set the power-on and power-gate states, anything
6154 * else is unexpected.
6156 WARN_ON(state
!= PUNIT_PWRGT_PWR_ON(power_well_id
) &&
6157 state
!= PUNIT_PWRGT_PWR_GATE(power_well_id
));
6162 * A transient state at this point would mean some unexpected party
6163 * is poking at the power controls too.
6165 ctrl
= vlv_punit_read(dev_priv
, PUNIT_REG_PWRGT_CTRL
) & mask
;
6166 WARN_ON(ctrl
!= state
);
6168 mutex_unlock(&dev_priv
->rps
.hw_lock
);
6173 static void vlv_display_power_well_enable(struct drm_i915_private
*dev_priv
,
6174 struct i915_power_well
*power_well
)
6176 WARN_ON_ONCE(power_well
->data
!= PUNIT_POWER_WELL_DISP2D
);
6178 vlv_set_power_well(dev_priv
, power_well
, true);
6180 spin_lock_irq(&dev_priv
->irq_lock
);
6181 valleyview_enable_display_irqs(dev_priv
);
6182 spin_unlock_irq(&dev_priv
->irq_lock
);
6185 * During driver initialization/resume we can avoid restoring the
6186 * part of the HW/SW state that will be inited anyway explicitly.
6188 if (dev_priv
->power_domains
.initializing
)
6191 intel_hpd_init(dev_priv
->dev
);
6193 i915_redisable_vga_power_on(dev_priv
->dev
);
6196 static void vlv_display_power_well_disable(struct drm_i915_private
*dev_priv
,
6197 struct i915_power_well
*power_well
)
6199 WARN_ON_ONCE(power_well
->data
!= PUNIT_POWER_WELL_DISP2D
);
6201 spin_lock_irq(&dev_priv
->irq_lock
);
6202 valleyview_disable_display_irqs(dev_priv
);
6203 spin_unlock_irq(&dev_priv
->irq_lock
);
6205 vlv_set_power_well(dev_priv
, power_well
, false);
6208 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private
*dev_priv
,
6209 struct i915_power_well
*power_well
)
6211 WARN_ON_ONCE(power_well
->data
!= PUNIT_POWER_WELL_DPIO_CMN_BC
);
6214 * Enable the CRI clock source so we can get at the
6215 * display and the reference clock for VGA
6216 * hotplug / manual detection.
6218 I915_WRITE(DPLL(PIPE_B
), I915_READ(DPLL(PIPE_B
)) |
6219 DPLL_REFA_CLK_ENABLE_VLV
| DPLL_INTEGRATED_CRI_CLK_VLV
);
6220 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
6222 vlv_set_power_well(dev_priv
, power_well
, true);
6225 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
6226 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
6227 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
6228 * b. The other bits such as sfr settings / modesel may all
6231 * This should only be done on init and resume from S3 with
6232 * both PLLs disabled, or we risk losing DPIO and PLL
6235 I915_WRITE(DPIO_CTL
, I915_READ(DPIO_CTL
) | DPIO_CMNRST
);
6238 static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private
*dev_priv
,
6239 struct i915_power_well
*power_well
)
6241 struct drm_device
*dev
= dev_priv
->dev
;
6244 WARN_ON_ONCE(power_well
->data
!= PUNIT_POWER_WELL_DPIO_CMN_BC
);
6247 assert_pll_disabled(dev_priv
, pipe
);
6249 /* Assert common reset */
6250 I915_WRITE(DPIO_CTL
, I915_READ(DPIO_CTL
) & ~DPIO_CMNRST
);
6252 vlv_set_power_well(dev_priv
, power_well
, false);
6255 static void check_power_well_state(struct drm_i915_private
*dev_priv
,
6256 struct i915_power_well
*power_well
)
6258 bool enabled
= power_well
->ops
->is_enabled(dev_priv
, power_well
);
6260 if (power_well
->always_on
|| !i915
.disable_power_well
) {
6267 if (enabled
!= (power_well
->count
> 0))
6273 WARN(1, "state mismatch for '%s' (always_on %d hw state %d use-count %d disable_power_well %d\n",
6274 power_well
->name
, power_well
->always_on
, enabled
,
6275 power_well
->count
, i915
.disable_power_well
);
6278 void intel_display_power_get(struct drm_i915_private
*dev_priv
,
6279 enum intel_display_power_domain domain
)
6281 struct i915_power_domains
*power_domains
;
6282 struct i915_power_well
*power_well
;
6285 intel_runtime_pm_get(dev_priv
);
6287 power_domains
= &dev_priv
->power_domains
;
6289 mutex_lock(&power_domains
->lock
);
6291 for_each_power_well(i
, power_well
, BIT(domain
), power_domains
) {
6292 if (!power_well
->count
++) {
6293 DRM_DEBUG_KMS("enabling %s\n", power_well
->name
);
6294 power_well
->ops
->enable(dev_priv
, power_well
);
6295 power_well
->hw_enabled
= true;
6298 check_power_well_state(dev_priv
, power_well
);
6301 power_domains
->domain_use_count
[domain
]++;
6303 mutex_unlock(&power_domains
->lock
);
6306 void intel_display_power_put(struct drm_i915_private
*dev_priv
,
6307 enum intel_display_power_domain domain
)
6309 struct i915_power_domains
*power_domains
;
6310 struct i915_power_well
*power_well
;
6313 power_domains
= &dev_priv
->power_domains
;
6315 mutex_lock(&power_domains
->lock
);
6317 WARN_ON(!power_domains
->domain_use_count
[domain
]);
6318 power_domains
->domain_use_count
[domain
]--;
6320 for_each_power_well_rev(i
, power_well
, BIT(domain
), power_domains
) {
6321 WARN_ON(!power_well
->count
);
6323 if (!--power_well
->count
&& i915
.disable_power_well
) {
6324 DRM_DEBUG_KMS("disabling %s\n", power_well
->name
);
6325 power_well
->hw_enabled
= false;
6326 power_well
->ops
->disable(dev_priv
, power_well
);
6329 check_power_well_state(dev_priv
, power_well
);
6332 mutex_unlock(&power_domains
->lock
);
6334 intel_runtime_pm_put(dev_priv
);
6337 static struct i915_power_domains
*hsw_pwr
;
6339 /* Display audio driver power well request */
6340 int i915_request_power_well(void)
6342 struct drm_i915_private
*dev_priv
;
6347 dev_priv
= container_of(hsw_pwr
, struct drm_i915_private
,
6349 intel_display_power_get(dev_priv
, POWER_DOMAIN_AUDIO
);
6352 EXPORT_SYMBOL_GPL(i915_request_power_well
);
6354 /* Display audio driver power well release */
6355 int i915_release_power_well(void)
6357 struct drm_i915_private
*dev_priv
;
6362 dev_priv
= container_of(hsw_pwr
, struct drm_i915_private
,
6364 intel_display_power_put(dev_priv
, POWER_DOMAIN_AUDIO
);
6367 EXPORT_SYMBOL_GPL(i915_release_power_well
);
6370 * Private interface for the audio driver to get CDCLK in kHz.
6372 * Caller must request power well using i915_request_power_well() prior to
6375 int i915_get_cdclk_freq(void)
6377 struct drm_i915_private
*dev_priv
;
6382 dev_priv
= container_of(hsw_pwr
, struct drm_i915_private
,
6385 return intel_ddi_get_cdclk_freq(dev_priv
);
6387 EXPORT_SYMBOL_GPL(i915_get_cdclk_freq
);
6390 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
6392 #define HSW_ALWAYS_ON_POWER_DOMAINS ( \
6393 BIT(POWER_DOMAIN_PIPE_A) | \
6394 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
6395 BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
6396 BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
6397 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6398 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6399 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6400 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6401 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
6402 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
6403 BIT(POWER_DOMAIN_PORT_CRT) | \
6404 BIT(POWER_DOMAIN_PLLS) | \
6405 BIT(POWER_DOMAIN_INIT))
6406 #define HSW_DISPLAY_POWER_DOMAINS ( \
6407 (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \
6408 BIT(POWER_DOMAIN_INIT))
6410 #define BDW_ALWAYS_ON_POWER_DOMAINS ( \
6411 HSW_ALWAYS_ON_POWER_DOMAINS | \
6412 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
6413 #define BDW_DISPLAY_POWER_DOMAINS ( \
6414 (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) | \
6415 BIT(POWER_DOMAIN_INIT))
6417 #define VLV_ALWAYS_ON_POWER_DOMAINS BIT(POWER_DOMAIN_INIT)
6418 #define VLV_DISPLAY_POWER_DOMAINS POWER_DOMAIN_MASK
6420 #define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \
6421 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6422 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6423 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6424 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6425 BIT(POWER_DOMAIN_PORT_CRT) | \
6426 BIT(POWER_DOMAIN_INIT))
6428 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \
6429 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6430 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6431 BIT(POWER_DOMAIN_INIT))
6433 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \
6434 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6435 BIT(POWER_DOMAIN_INIT))
6437 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \
6438 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6439 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6440 BIT(POWER_DOMAIN_INIT))
6442 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \
6443 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6444 BIT(POWER_DOMAIN_INIT))
6446 static const struct i915_power_well_ops i9xx_always_on_power_well_ops
= {
6447 .sync_hw
= i9xx_always_on_power_well_noop
,
6448 .enable
= i9xx_always_on_power_well_noop
,
6449 .disable
= i9xx_always_on_power_well_noop
,
6450 .is_enabled
= i9xx_always_on_power_well_enabled
,
6453 static struct i915_power_well i9xx_always_on_power_well
[] = {
6455 .name
= "always-on",
6457 .domains
= POWER_DOMAIN_MASK
,
6458 .ops
= &i9xx_always_on_power_well_ops
,
6462 static const struct i915_power_well_ops hsw_power_well_ops
= {
6463 .sync_hw
= hsw_power_well_sync_hw
,
6464 .enable
= hsw_power_well_enable
,
6465 .disable
= hsw_power_well_disable
,
6466 .is_enabled
= hsw_power_well_enabled
,
6469 static struct i915_power_well hsw_power_wells
[] = {
6471 .name
= "always-on",
6473 .domains
= HSW_ALWAYS_ON_POWER_DOMAINS
,
6474 .ops
= &i9xx_always_on_power_well_ops
,
6478 .domains
= HSW_DISPLAY_POWER_DOMAINS
,
6479 .ops
= &hsw_power_well_ops
,
6483 static struct i915_power_well bdw_power_wells
[] = {
6485 .name
= "always-on",
6487 .domains
= BDW_ALWAYS_ON_POWER_DOMAINS
,
6488 .ops
= &i9xx_always_on_power_well_ops
,
6492 .domains
= BDW_DISPLAY_POWER_DOMAINS
,
6493 .ops
= &hsw_power_well_ops
,
6497 static const struct i915_power_well_ops vlv_display_power_well_ops
= {
6498 .sync_hw
= vlv_power_well_sync_hw
,
6499 .enable
= vlv_display_power_well_enable
,
6500 .disable
= vlv_display_power_well_disable
,
6501 .is_enabled
= vlv_power_well_enabled
,
6504 static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops
= {
6505 .sync_hw
= vlv_power_well_sync_hw
,
6506 .enable
= vlv_dpio_cmn_power_well_enable
,
6507 .disable
= vlv_dpio_cmn_power_well_disable
,
6508 .is_enabled
= vlv_power_well_enabled
,
6511 static const struct i915_power_well_ops vlv_dpio_power_well_ops
= {
6512 .sync_hw
= vlv_power_well_sync_hw
,
6513 .enable
= vlv_power_well_enable
,
6514 .disable
= vlv_power_well_disable
,
6515 .is_enabled
= vlv_power_well_enabled
,
6518 static struct i915_power_well vlv_power_wells
[] = {
6520 .name
= "always-on",
6522 .domains
= VLV_ALWAYS_ON_POWER_DOMAINS
,
6523 .ops
= &i9xx_always_on_power_well_ops
,
6527 .domains
= VLV_DISPLAY_POWER_DOMAINS
,
6528 .data
= PUNIT_POWER_WELL_DISP2D
,
6529 .ops
= &vlv_display_power_well_ops
,
6532 .name
= "dpio-tx-b-01",
6533 .domains
= VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS
|
6534 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS
|
6535 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS
|
6536 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS
,
6537 .ops
= &vlv_dpio_power_well_ops
,
6538 .data
= PUNIT_POWER_WELL_DPIO_TX_B_LANES_01
,
6541 .name
= "dpio-tx-b-23",
6542 .domains
= VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS
|
6543 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS
|
6544 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS
|
6545 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS
,
6546 .ops
= &vlv_dpio_power_well_ops
,
6547 .data
= PUNIT_POWER_WELL_DPIO_TX_B_LANES_23
,
6550 .name
= "dpio-tx-c-01",
6551 .domains
= VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS
|
6552 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS
|
6553 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS
|
6554 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS
,
6555 .ops
= &vlv_dpio_power_well_ops
,
6556 .data
= PUNIT_POWER_WELL_DPIO_TX_C_LANES_01
,
6559 .name
= "dpio-tx-c-23",
6560 .domains
= VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS
|
6561 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS
|
6562 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS
|
6563 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS
,
6564 .ops
= &vlv_dpio_power_well_ops
,
6565 .data
= PUNIT_POWER_WELL_DPIO_TX_C_LANES_23
,
6568 .name
= "dpio-common",
6569 .domains
= VLV_DPIO_CMN_BC_POWER_DOMAINS
,
6570 .data
= PUNIT_POWER_WELL_DPIO_CMN_BC
,
6571 .ops
= &vlv_dpio_cmn_power_well_ops
,
6575 static struct i915_power_well
*lookup_power_well(struct drm_i915_private
*dev_priv
,
6576 enum punit_power_well power_well_id
)
6578 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
6579 struct i915_power_well
*power_well
;
6582 for_each_power_well(i
, power_well
, POWER_DOMAIN_MASK
, power_domains
) {
6583 if (power_well
->data
== power_well_id
)
6590 #define set_power_wells(power_domains, __power_wells) ({ \
6591 (power_domains)->power_wells = (__power_wells); \
6592 (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \
6595 int intel_power_domains_init(struct drm_i915_private
*dev_priv
)
6597 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
6599 mutex_init(&power_domains
->lock
);
6602 * The enabling order will be from lower to higher indexed wells,
6603 * the disabling order is reversed.
6605 if (IS_HASWELL(dev_priv
->dev
)) {
6606 set_power_wells(power_domains
, hsw_power_wells
);
6607 hsw_pwr
= power_domains
;
6608 } else if (IS_BROADWELL(dev_priv
->dev
)) {
6609 set_power_wells(power_domains
, bdw_power_wells
);
6610 hsw_pwr
= power_domains
;
6611 } else if (IS_VALLEYVIEW(dev_priv
->dev
)) {
6612 set_power_wells(power_domains
, vlv_power_wells
);
6614 set_power_wells(power_domains
, i9xx_always_on_power_well
);
6620 void intel_power_domains_remove(struct drm_i915_private
*dev_priv
)
6625 static void intel_power_domains_resume(struct drm_i915_private
*dev_priv
)
6627 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
6628 struct i915_power_well
*power_well
;
6631 mutex_lock(&power_domains
->lock
);
6632 for_each_power_well(i
, power_well
, POWER_DOMAIN_MASK
, power_domains
) {
6633 power_well
->ops
->sync_hw(dev_priv
, power_well
);
6634 power_well
->hw_enabled
= power_well
->ops
->is_enabled(dev_priv
,
6637 mutex_unlock(&power_domains
->lock
);
6640 static void vlv_cmnlane_wa(struct drm_i915_private
*dev_priv
)
6642 struct i915_power_well
*cmn
=
6643 lookup_power_well(dev_priv
, PUNIT_POWER_WELL_DPIO_CMN_BC
);
6644 struct i915_power_well
*disp2d
=
6645 lookup_power_well(dev_priv
, PUNIT_POWER_WELL_DISP2D
);
6647 /* nothing to do if common lane is already off */
6648 if (!cmn
->ops
->is_enabled(dev_priv
, cmn
))
6651 /* If the display might be already active skip this */
6652 if (disp2d
->ops
->is_enabled(dev_priv
, disp2d
) &&
6653 I915_READ(DPIO_CTL
) & DPIO_CMNRST
)
6656 DRM_DEBUG_KMS("toggling display PHY side reset\n");
6658 /* cmnlane needs DPLL registers */
6659 disp2d
->ops
->enable(dev_priv
, disp2d
);
6662 * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
6663 * Need to assert and de-assert PHY SB reset by gating the
6664 * common lane power, then un-gating it.
6665 * Simply ungating isn't enough to reset the PHY enough to get
6666 * ports and lanes running.
6668 cmn
->ops
->disable(dev_priv
, cmn
);
6671 void intel_power_domains_init_hw(struct drm_i915_private
*dev_priv
)
6673 struct drm_device
*dev
= dev_priv
->dev
;
6674 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
6676 power_domains
->initializing
= true;
6678 if (IS_VALLEYVIEW(dev
) && !IS_CHERRYVIEW(dev
)) {
6679 mutex_lock(&power_domains
->lock
);
6680 vlv_cmnlane_wa(dev_priv
);
6681 mutex_unlock(&power_domains
->lock
);
6684 /* For now, we need the power well to be always enabled. */
6685 intel_display_set_init_power(dev_priv
, true);
6686 intel_power_domains_resume(dev_priv
);
6687 power_domains
->initializing
= false;
6690 void intel_aux_display_runtime_get(struct drm_i915_private
*dev_priv
)
6692 intel_runtime_pm_get(dev_priv
);
6695 void intel_aux_display_runtime_put(struct drm_i915_private
*dev_priv
)
6697 intel_runtime_pm_put(dev_priv
);
6700 void intel_runtime_pm_get(struct drm_i915_private
*dev_priv
)
6702 struct drm_device
*dev
= dev_priv
->dev
;
6703 struct device
*device
= &dev
->pdev
->dev
;
6705 if (!HAS_RUNTIME_PM(dev
))
6708 pm_runtime_get_sync(device
);
6709 WARN(dev_priv
->pm
.suspended
, "Device still suspended.\n");
6712 void intel_runtime_pm_get_noresume(struct drm_i915_private
*dev_priv
)
6714 struct drm_device
*dev
= dev_priv
->dev
;
6715 struct device
*device
= &dev
->pdev
->dev
;
6717 if (!HAS_RUNTIME_PM(dev
))
6720 WARN(dev_priv
->pm
.suspended
, "Getting nosync-ref while suspended.\n");
6721 pm_runtime_get_noresume(device
);
6724 void intel_runtime_pm_put(struct drm_i915_private
*dev_priv
)
6726 struct drm_device
*dev
= dev_priv
->dev
;
6727 struct device
*device
= &dev
->pdev
->dev
;
6729 if (!HAS_RUNTIME_PM(dev
))
6732 pm_runtime_mark_last_busy(device
);
6733 pm_runtime_put_autosuspend(device
);
6736 void intel_init_runtime_pm(struct drm_i915_private
*dev_priv
)
6738 struct drm_device
*dev
= dev_priv
->dev
;
6739 struct device
*device
= &dev
->pdev
->dev
;
6741 if (!HAS_RUNTIME_PM(dev
))
6744 pm_runtime_set_active(device
);
6747 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6750 if (!intel_enable_rc6(dev
)) {
6751 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6755 pm_runtime_set_autosuspend_delay(device
, 10000); /* 10s */
6756 pm_runtime_mark_last_busy(device
);
6757 pm_runtime_use_autosuspend(device
);
6759 pm_runtime_put_autosuspend(device
);
6762 void intel_fini_runtime_pm(struct drm_i915_private
*dev_priv
)
6764 struct drm_device
*dev
= dev_priv
->dev
;
6765 struct device
*device
= &dev
->pdev
->dev
;
6767 if (!HAS_RUNTIME_PM(dev
))
6770 if (!intel_enable_rc6(dev
))
6773 /* Make sure we're not suspended first. */
6774 pm_runtime_get_sync(device
);
6775 pm_runtime_disable(device
);
6778 /* Set up chip specific power management-related functions */
6779 void intel_init_pm(struct drm_device
*dev
)
6781 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6784 if (INTEL_INFO(dev
)->gen
>= 7) {
6785 dev_priv
->display
.fbc_enabled
= ironlake_fbc_enabled
;
6786 dev_priv
->display
.enable_fbc
= gen7_enable_fbc
;
6787 dev_priv
->display
.disable_fbc
= ironlake_disable_fbc
;
6788 } else if (INTEL_INFO(dev
)->gen
>= 5) {
6789 dev_priv
->display
.fbc_enabled
= ironlake_fbc_enabled
;
6790 dev_priv
->display
.enable_fbc
= ironlake_enable_fbc
;
6791 dev_priv
->display
.disable_fbc
= ironlake_disable_fbc
;
6792 } else if (IS_GM45(dev
)) {
6793 dev_priv
->display
.fbc_enabled
= g4x_fbc_enabled
;
6794 dev_priv
->display
.enable_fbc
= g4x_enable_fbc
;
6795 dev_priv
->display
.disable_fbc
= g4x_disable_fbc
;
6797 dev_priv
->display
.fbc_enabled
= i8xx_fbc_enabled
;
6798 dev_priv
->display
.enable_fbc
= i8xx_enable_fbc
;
6799 dev_priv
->display
.disable_fbc
= i8xx_disable_fbc
;
6801 /* This value was pulled out of someone's hat */
6802 I915_WRITE(FBC_CONTROL
, 500 << FBC_CTL_INTERVAL_SHIFT
);
6807 if (IS_PINEVIEW(dev
))
6808 i915_pineview_get_mem_freq(dev
);
6809 else if (IS_GEN5(dev
))
6810 i915_ironlake_get_mem_freq(dev
);
6812 /* For FIFO watermark updates */
6813 if (HAS_PCH_SPLIT(dev
)) {
6814 ilk_setup_wm_latency(dev
);
6816 if ((IS_GEN5(dev
) && dev_priv
->wm
.pri_latency
[1] &&
6817 dev_priv
->wm
.spr_latency
[1] && dev_priv
->wm
.cur_latency
[1]) ||
6818 (!IS_GEN5(dev
) && dev_priv
->wm
.pri_latency
[0] &&
6819 dev_priv
->wm
.spr_latency
[0] && dev_priv
->wm
.cur_latency
[0])) {
6820 dev_priv
->display
.update_wm
= ilk_update_wm
;
6821 dev_priv
->display
.update_sprite_wm
= ilk_update_sprite_wm
;
6823 DRM_DEBUG_KMS("Failed to read display plane latency. "
6828 dev_priv
->display
.init_clock_gating
= ironlake_init_clock_gating
;
6829 else if (IS_GEN6(dev
))
6830 dev_priv
->display
.init_clock_gating
= gen6_init_clock_gating
;
6831 else if (IS_IVYBRIDGE(dev
))
6832 dev_priv
->display
.init_clock_gating
= ivybridge_init_clock_gating
;
6833 else if (IS_HASWELL(dev
))
6834 dev_priv
->display
.init_clock_gating
= haswell_init_clock_gating
;
6835 else if (INTEL_INFO(dev
)->gen
== 8)
6836 dev_priv
->display
.init_clock_gating
= gen8_init_clock_gating
;
6837 } else if (IS_CHERRYVIEW(dev
)) {
6838 dev_priv
->display
.update_wm
= valleyview_update_wm
;
6839 dev_priv
->display
.init_clock_gating
=
6840 cherryview_init_clock_gating
;
6841 } else if (IS_VALLEYVIEW(dev
)) {
6842 dev_priv
->display
.update_wm
= valleyview_update_wm
;
6843 dev_priv
->display
.init_clock_gating
=
6844 valleyview_init_clock_gating
;
6845 } else if (IS_PINEVIEW(dev
)) {
6846 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev
),
6849 dev_priv
->mem_freq
)) {
6850 DRM_INFO("failed to find known CxSR latency "
6851 "(found ddr%s fsb freq %d, mem freq %d), "
6853 (dev_priv
->is_ddr3
== 1) ? "3" : "2",
6854 dev_priv
->fsb_freq
, dev_priv
->mem_freq
);
6855 /* Disable CxSR and never update its watermark again */
6856 intel_set_memory_cxsr(dev_priv
, false);
6857 dev_priv
->display
.update_wm
= NULL
;
6859 dev_priv
->display
.update_wm
= pineview_update_wm
;
6860 dev_priv
->display
.init_clock_gating
= gen3_init_clock_gating
;
6861 } else if (IS_G4X(dev
)) {
6862 dev_priv
->display
.update_wm
= g4x_update_wm
;
6863 dev_priv
->display
.init_clock_gating
= g4x_init_clock_gating
;
6864 } else if (IS_GEN4(dev
)) {
6865 dev_priv
->display
.update_wm
= i965_update_wm
;
6866 if (IS_CRESTLINE(dev
))
6867 dev_priv
->display
.init_clock_gating
= crestline_init_clock_gating
;
6868 else if (IS_BROADWATER(dev
))
6869 dev_priv
->display
.init_clock_gating
= broadwater_init_clock_gating
;
6870 } else if (IS_GEN3(dev
)) {
6871 dev_priv
->display
.update_wm
= i9xx_update_wm
;
6872 dev_priv
->display
.get_fifo_size
= i9xx_get_fifo_size
;
6873 dev_priv
->display
.init_clock_gating
= gen3_init_clock_gating
;
6874 } else if (IS_GEN2(dev
)) {
6875 if (INTEL_INFO(dev
)->num_pipes
== 1) {
6876 dev_priv
->display
.update_wm
= i845_update_wm
;
6877 dev_priv
->display
.get_fifo_size
= i845_get_fifo_size
;
6879 dev_priv
->display
.update_wm
= i9xx_update_wm
;
6880 dev_priv
->display
.get_fifo_size
= i830_get_fifo_size
;
6883 if (IS_I85X(dev
) || IS_I865G(dev
))
6884 dev_priv
->display
.init_clock_gating
= i85x_init_clock_gating
;
6886 dev_priv
->display
.init_clock_gating
= i830_init_clock_gating
;
6888 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
6892 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u8 mbox
, u32
*val
)
6894 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
6896 if (I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) {
6897 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
6901 I915_WRITE(GEN6_PCODE_DATA
, *val
);
6902 I915_WRITE(GEN6_PCODE_MAILBOX
, GEN6_PCODE_READY
| mbox
);
6904 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) == 0,
6906 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox
);
6910 *val
= I915_READ(GEN6_PCODE_DATA
);
6911 I915_WRITE(GEN6_PCODE_DATA
, 0);
6916 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
, u8 mbox
, u32 val
)
6918 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
6920 if (I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) {
6921 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
6925 I915_WRITE(GEN6_PCODE_DATA
, val
);
6926 I915_WRITE(GEN6_PCODE_MAILBOX
, GEN6_PCODE_READY
| mbox
);
6928 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) == 0,
6930 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox
);
6934 I915_WRITE(GEN6_PCODE_DATA
, 0);
6939 static int byt_gpu_freq(struct drm_i915_private
*dev_priv
, int val
)
6944 switch (dev_priv
->mem_freq
) {
6958 return DIV_ROUND_CLOSEST(dev_priv
->mem_freq
* (val
+ 6 - 0xbd), 4 * div
);
6961 static int byt_freq_opcode(struct drm_i915_private
*dev_priv
, int val
)
6966 switch (dev_priv
->mem_freq
) {
6980 return DIV_ROUND_CLOSEST(4 * mul
* val
, dev_priv
->mem_freq
) + 0xbd - 6;
6983 static int chv_gpu_freq(struct drm_i915_private
*dev_priv
, int val
)
6987 switch (dev_priv
->rps
.cz_freq
) {
7003 freq
= (DIV_ROUND_CLOSEST((dev_priv
->rps
.cz_freq
* val
), 2 * div
) / 2);
7008 static int chv_freq_opcode(struct drm_i915_private
*dev_priv
, int val
)
7012 switch (dev_priv
->rps
.cz_freq
) {
7028 opcode
= (DIV_ROUND_CLOSEST((val
* 2 * mul
), dev_priv
->rps
.cz_freq
) * 2);
7033 int vlv_gpu_freq(struct drm_i915_private
*dev_priv
, int val
)
7037 if (IS_CHERRYVIEW(dev_priv
->dev
))
7038 ret
= chv_gpu_freq(dev_priv
, val
);
7039 else if (IS_VALLEYVIEW(dev_priv
->dev
))
7040 ret
= byt_gpu_freq(dev_priv
, val
);
7045 int vlv_freq_opcode(struct drm_i915_private
*dev_priv
, int val
)
7049 if (IS_CHERRYVIEW(dev_priv
->dev
))
7050 ret
= chv_freq_opcode(dev_priv
, val
);
7051 else if (IS_VALLEYVIEW(dev_priv
->dev
))
7052 ret
= byt_freq_opcode(dev_priv
, val
);
7057 void intel_pm_setup(struct drm_device
*dev
)
7059 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7061 mutex_init(&dev_priv
->rps
.hw_lock
);
7063 INIT_DELAYED_WORK(&dev_priv
->rps
.delayed_resume_work
,
7064 intel_gen6_powersave_work
);
7066 dev_priv
->pm
.suspended
= false;
7067 dev_priv
->pm
._irqs_disabled
= false;