2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
28 #include <linux/cpufreq.h>
30 #include "intel_drv.h"
31 #include "../../../platform/x86/intel_ips.h"
32 #include <linux/module.h>
35 * RC6 is a special power stage which allows the GPU to enter an very
36 * low-voltage mode when idle, using down to 0V while at this stage. This
37 * stage is entered automatically when the GPU is idle when RC6 support is
38 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
40 * There are different RC6 modes available in Intel GPU, which differentiate
41 * among each other with the latency required to enter and leave RC6 and
42 * voltage consumed by the GPU in different states.
44 * The combination of the following flags define which states GPU is allowed
45 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
46 * RC6pp is deepest RC6. Their support by hardware varies according to the
47 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
48 * which brings the most power savings; deeper states save more power, but
49 * require higher latency to switch to and wake up.
51 #define INTEL_RC6_ENABLE (1<<0)
52 #define INTEL_RC6p_ENABLE (1<<1)
53 #define INTEL_RC6pp_ENABLE (1<<2)
55 static void gen9_init_clock_gating(struct drm_device
*dev
)
57 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
59 /* WaEnableLbsSlaRetryTimerDecrement:skl */
60 I915_WRITE(BDW_SCRATCH1
, I915_READ(BDW_SCRATCH1
) |
61 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE
);
64 static void skl_init_clock_gating(struct drm_device
*dev
)
66 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
68 gen9_init_clock_gating(dev
);
70 if (INTEL_REVID(dev
) <= SKL_REVID_B0
) {
72 * WaDisableSDEUnitClockGating:skl
73 * WaSetGAPSunitClckGateDisable:skl
75 I915_WRITE(GEN8_UCGCTL6
, I915_READ(GEN8_UCGCTL6
) |
76 GEN8_GAPSUNIT_CLOCK_GATE_DISABLE
|
77 GEN8_SDEUNIT_CLOCK_GATE_DISABLE
);
79 /* WaDisableVFUnitClockGating:skl */
80 I915_WRITE(GEN6_UCGCTL2
, I915_READ(GEN6_UCGCTL2
) |
81 GEN6_VFUNIT_CLOCK_GATE_DISABLE
);
84 if (INTEL_REVID(dev
) <= SKL_REVID_D0
) {
85 /* WaDisableHDCInvalidation:skl */
86 I915_WRITE(GAM_ECOCHK
, I915_READ(GAM_ECOCHK
) |
87 BDW_DISABLE_HDC_INVALIDATION
);
89 /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
90 I915_WRITE(FF_SLICE_CS_CHICKEN2
,
91 _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE
));
94 if (INTEL_REVID(dev
) <= SKL_REVID_E0
)
95 /* WaDisableLSQCROPERFforOCL:skl */
96 I915_WRITE(GEN8_L3SQCREG4
, I915_READ(GEN8_L3SQCREG4
) |
97 GEN8_LQSC_RO_PERF_DIS
);
100 static void bxt_init_clock_gating(struct drm_device
*dev
)
102 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
104 gen9_init_clock_gating(dev
);
108 * GEN8_SDEUNIT_CLOCK_GATE_DISABLE applies on A0 only.
109 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
111 /* WaDisableSDEUnitClockGating:bxt */
112 I915_WRITE(GEN8_UCGCTL6
, I915_READ(GEN8_UCGCTL6
) |
113 GEN8_SDEUNIT_CLOCK_GATE_DISABLE
|
114 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ
);
116 /* FIXME: apply on A0 only */
117 I915_WRITE(TILECTL
, I915_READ(TILECTL
) | TILECTL_TLBPF
);
120 static void i915_pineview_get_mem_freq(struct drm_device
*dev
)
122 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
125 tmp
= I915_READ(CLKCFG
);
127 switch (tmp
& CLKCFG_FSB_MASK
) {
129 dev_priv
->fsb_freq
= 533; /* 133*4 */
132 dev_priv
->fsb_freq
= 800; /* 200*4 */
135 dev_priv
->fsb_freq
= 667; /* 167*4 */
138 dev_priv
->fsb_freq
= 400; /* 100*4 */
142 switch (tmp
& CLKCFG_MEM_MASK
) {
144 dev_priv
->mem_freq
= 533;
147 dev_priv
->mem_freq
= 667;
150 dev_priv
->mem_freq
= 800;
154 /* detect pineview DDR3 setting */
155 tmp
= I915_READ(CSHRDDR3CTL
);
156 dev_priv
->is_ddr3
= (tmp
& CSHRDDR3CTL_DDR3
) ? 1 : 0;
159 static void i915_ironlake_get_mem_freq(struct drm_device
*dev
)
161 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
164 ddrpll
= I915_READ16(DDRMPLL1
);
165 csipll
= I915_READ16(CSIPLL0
);
167 switch (ddrpll
& 0xff) {
169 dev_priv
->mem_freq
= 800;
172 dev_priv
->mem_freq
= 1066;
175 dev_priv
->mem_freq
= 1333;
178 dev_priv
->mem_freq
= 1600;
181 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
183 dev_priv
->mem_freq
= 0;
187 dev_priv
->ips
.r_t
= dev_priv
->mem_freq
;
189 switch (csipll
& 0x3ff) {
191 dev_priv
->fsb_freq
= 3200;
194 dev_priv
->fsb_freq
= 3733;
197 dev_priv
->fsb_freq
= 4266;
200 dev_priv
->fsb_freq
= 4800;
203 dev_priv
->fsb_freq
= 5333;
206 dev_priv
->fsb_freq
= 5866;
209 dev_priv
->fsb_freq
= 6400;
212 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
214 dev_priv
->fsb_freq
= 0;
218 if (dev_priv
->fsb_freq
== 3200) {
219 dev_priv
->ips
.c_m
= 0;
220 } else if (dev_priv
->fsb_freq
> 3200 && dev_priv
->fsb_freq
<= 4800) {
221 dev_priv
->ips
.c_m
= 1;
223 dev_priv
->ips
.c_m
= 2;
227 static const struct cxsr_latency cxsr_latency_table
[] = {
228 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
229 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
230 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
231 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
232 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
234 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
235 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
236 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
237 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
238 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
240 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
241 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
242 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
243 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
244 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
246 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
247 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
248 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
249 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
250 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
252 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
253 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
254 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
255 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
256 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
258 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
259 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
260 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
261 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
262 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
265 static const struct cxsr_latency
*intel_get_cxsr_latency(int is_desktop
,
270 const struct cxsr_latency
*latency
;
273 if (fsb
== 0 || mem
== 0)
276 for (i
= 0; i
< ARRAY_SIZE(cxsr_latency_table
); i
++) {
277 latency
= &cxsr_latency_table
[i
];
278 if (is_desktop
== latency
->is_desktop
&&
279 is_ddr3
== latency
->is_ddr3
&&
280 fsb
== latency
->fsb_freq
&& mem
== latency
->mem_freq
)
284 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
289 static void chv_set_memory_dvfs(struct drm_i915_private
*dev_priv
, bool enable
)
293 mutex_lock(&dev_priv
->rps
.hw_lock
);
295 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DDR_SETUP2
);
297 val
&= ~FORCE_DDR_HIGH_FREQ
;
299 val
|= FORCE_DDR_HIGH_FREQ
;
300 val
&= ~FORCE_DDR_LOW_FREQ
;
301 val
|= FORCE_DDR_FREQ_REQ_ACK
;
302 vlv_punit_write(dev_priv
, PUNIT_REG_DDR_SETUP2
, val
);
304 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DDR_SETUP2
) &
305 FORCE_DDR_FREQ_REQ_ACK
) == 0, 3))
306 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
308 mutex_unlock(&dev_priv
->rps
.hw_lock
);
311 static void chv_set_memory_pm5(struct drm_i915_private
*dev_priv
, bool enable
)
315 mutex_lock(&dev_priv
->rps
.hw_lock
);
317 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
319 val
|= DSP_MAXFIFO_PM5_ENABLE
;
321 val
&= ~DSP_MAXFIFO_PM5_ENABLE
;
322 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
324 mutex_unlock(&dev_priv
->rps
.hw_lock
);
327 #define FW_WM(value, plane) \
328 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
330 void intel_set_memory_cxsr(struct drm_i915_private
*dev_priv
, bool enable
)
332 struct drm_device
*dev
= dev_priv
->dev
;
335 if (IS_VALLEYVIEW(dev
)) {
336 I915_WRITE(FW_BLC_SELF_VLV
, enable
? FW_CSPWRDWNEN
: 0);
337 POSTING_READ(FW_BLC_SELF_VLV
);
338 dev_priv
->wm
.vlv
.cxsr
= enable
;
339 } else if (IS_G4X(dev
) || IS_CRESTLINE(dev
)) {
340 I915_WRITE(FW_BLC_SELF
, enable
? FW_BLC_SELF_EN
: 0);
341 POSTING_READ(FW_BLC_SELF
);
342 } else if (IS_PINEVIEW(dev
)) {
343 val
= I915_READ(DSPFW3
) & ~PINEVIEW_SELF_REFRESH_EN
;
344 val
|= enable
? PINEVIEW_SELF_REFRESH_EN
: 0;
345 I915_WRITE(DSPFW3
, val
);
346 POSTING_READ(DSPFW3
);
347 } else if (IS_I945G(dev
) || IS_I945GM(dev
)) {
348 val
= enable
? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN
) :
349 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN
);
350 I915_WRITE(FW_BLC_SELF
, val
);
351 POSTING_READ(FW_BLC_SELF
);
352 } else if (IS_I915GM(dev
)) {
353 val
= enable
? _MASKED_BIT_ENABLE(INSTPM_SELF_EN
) :
354 _MASKED_BIT_DISABLE(INSTPM_SELF_EN
);
355 I915_WRITE(INSTPM
, val
);
356 POSTING_READ(INSTPM
);
361 DRM_DEBUG_KMS("memory self-refresh is %s\n",
362 enable
? "enabled" : "disabled");
367 * Latency for FIFO fetches is dependent on several factors:
368 * - memory configuration (speed, channels)
370 * - current MCH state
371 * It can be fairly high in some situations, so here we assume a fairly
372 * pessimal value. It's a tradeoff between extra memory fetches (if we
373 * set this value too high, the FIFO will fetch frequently to stay full)
374 * and power consumption (set it too low to save power and we might see
375 * FIFO underruns and display "flicker").
377 * A value of 5us seems to be a good balance; safe for very low end
378 * platforms but not overly aggressive on lower latency configs.
380 static const int pessimal_latency_ns
= 5000;
382 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
383 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
385 static int vlv_get_fifo_size(struct drm_device
*dev
,
386 enum pipe pipe
, int plane
)
388 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
389 int sprite0_start
, sprite1_start
, size
;
392 uint32_t dsparb
, dsparb2
, dsparb3
;
394 dsparb
= I915_READ(DSPARB
);
395 dsparb2
= I915_READ(DSPARB2
);
396 sprite0_start
= VLV_FIFO_START(dsparb
, dsparb2
, 0, 0);
397 sprite1_start
= VLV_FIFO_START(dsparb
, dsparb2
, 8, 4);
400 dsparb
= I915_READ(DSPARB
);
401 dsparb2
= I915_READ(DSPARB2
);
402 sprite0_start
= VLV_FIFO_START(dsparb
, dsparb2
, 16, 8);
403 sprite1_start
= VLV_FIFO_START(dsparb
, dsparb2
, 24, 12);
406 dsparb2
= I915_READ(DSPARB2
);
407 dsparb3
= I915_READ(DSPARB3
);
408 sprite0_start
= VLV_FIFO_START(dsparb3
, dsparb2
, 0, 16);
409 sprite1_start
= VLV_FIFO_START(dsparb3
, dsparb2
, 8, 20);
417 size
= sprite0_start
;
420 size
= sprite1_start
- sprite0_start
;
423 size
= 512 - 1 - sprite1_start
;
429 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
430 pipe_name(pipe
), plane
== 0 ? "primary" : "sprite",
431 plane
== 0 ? plane_name(pipe
) : sprite_name(pipe
, plane
- 1),
437 static int i9xx_get_fifo_size(struct drm_device
*dev
, int plane
)
439 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
440 uint32_t dsparb
= I915_READ(DSPARB
);
443 size
= dsparb
& 0x7f;
445 size
= ((dsparb
>> DSPARB_CSTART_SHIFT
) & 0x7f) - size
;
447 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
448 plane
? "B" : "A", size
);
453 static int i830_get_fifo_size(struct drm_device
*dev
, int plane
)
455 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
456 uint32_t dsparb
= I915_READ(DSPARB
);
459 size
= dsparb
& 0x1ff;
461 size
= ((dsparb
>> DSPARB_BEND_SHIFT
) & 0x1ff) - size
;
462 size
>>= 1; /* Convert to cachelines */
464 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
465 plane
? "B" : "A", size
);
470 static int i845_get_fifo_size(struct drm_device
*dev
, int plane
)
472 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
473 uint32_t dsparb
= I915_READ(DSPARB
);
476 size
= dsparb
& 0x7f;
477 size
>>= 2; /* Convert to cachelines */
479 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
486 /* Pineview has different values for various configs */
487 static const struct intel_watermark_params pineview_display_wm
= {
488 .fifo_size
= PINEVIEW_DISPLAY_FIFO
,
489 .max_wm
= PINEVIEW_MAX_WM
,
490 .default_wm
= PINEVIEW_DFT_WM
,
491 .guard_size
= PINEVIEW_GUARD_WM
,
492 .cacheline_size
= PINEVIEW_FIFO_LINE_SIZE
,
494 static const struct intel_watermark_params pineview_display_hplloff_wm
= {
495 .fifo_size
= PINEVIEW_DISPLAY_FIFO
,
496 .max_wm
= PINEVIEW_MAX_WM
,
497 .default_wm
= PINEVIEW_DFT_HPLLOFF_WM
,
498 .guard_size
= PINEVIEW_GUARD_WM
,
499 .cacheline_size
= PINEVIEW_FIFO_LINE_SIZE
,
501 static const struct intel_watermark_params pineview_cursor_wm
= {
502 .fifo_size
= PINEVIEW_CURSOR_FIFO
,
503 .max_wm
= PINEVIEW_CURSOR_MAX_WM
,
504 .default_wm
= PINEVIEW_CURSOR_DFT_WM
,
505 .guard_size
= PINEVIEW_CURSOR_GUARD_WM
,
506 .cacheline_size
= PINEVIEW_FIFO_LINE_SIZE
,
508 static const struct intel_watermark_params pineview_cursor_hplloff_wm
= {
509 .fifo_size
= PINEVIEW_CURSOR_FIFO
,
510 .max_wm
= PINEVIEW_CURSOR_MAX_WM
,
511 .default_wm
= PINEVIEW_CURSOR_DFT_WM
,
512 .guard_size
= PINEVIEW_CURSOR_GUARD_WM
,
513 .cacheline_size
= PINEVIEW_FIFO_LINE_SIZE
,
515 static const struct intel_watermark_params g4x_wm_info
= {
516 .fifo_size
= G4X_FIFO_SIZE
,
517 .max_wm
= G4X_MAX_WM
,
518 .default_wm
= G4X_MAX_WM
,
520 .cacheline_size
= G4X_FIFO_LINE_SIZE
,
522 static const struct intel_watermark_params g4x_cursor_wm_info
= {
523 .fifo_size
= I965_CURSOR_FIFO
,
524 .max_wm
= I965_CURSOR_MAX_WM
,
525 .default_wm
= I965_CURSOR_DFT_WM
,
527 .cacheline_size
= G4X_FIFO_LINE_SIZE
,
529 static const struct intel_watermark_params valleyview_wm_info
= {
530 .fifo_size
= VALLEYVIEW_FIFO_SIZE
,
531 .max_wm
= VALLEYVIEW_MAX_WM
,
532 .default_wm
= VALLEYVIEW_MAX_WM
,
534 .cacheline_size
= G4X_FIFO_LINE_SIZE
,
536 static const struct intel_watermark_params valleyview_cursor_wm_info
= {
537 .fifo_size
= I965_CURSOR_FIFO
,
538 .max_wm
= VALLEYVIEW_CURSOR_MAX_WM
,
539 .default_wm
= I965_CURSOR_DFT_WM
,
541 .cacheline_size
= G4X_FIFO_LINE_SIZE
,
543 static const struct intel_watermark_params i965_cursor_wm_info
= {
544 .fifo_size
= I965_CURSOR_FIFO
,
545 .max_wm
= I965_CURSOR_MAX_WM
,
546 .default_wm
= I965_CURSOR_DFT_WM
,
548 .cacheline_size
= I915_FIFO_LINE_SIZE
,
550 static const struct intel_watermark_params i945_wm_info
= {
551 .fifo_size
= I945_FIFO_SIZE
,
552 .max_wm
= I915_MAX_WM
,
555 .cacheline_size
= I915_FIFO_LINE_SIZE
,
557 static const struct intel_watermark_params i915_wm_info
= {
558 .fifo_size
= I915_FIFO_SIZE
,
559 .max_wm
= I915_MAX_WM
,
562 .cacheline_size
= I915_FIFO_LINE_SIZE
,
564 static const struct intel_watermark_params i830_a_wm_info
= {
565 .fifo_size
= I855GM_FIFO_SIZE
,
566 .max_wm
= I915_MAX_WM
,
569 .cacheline_size
= I830_FIFO_LINE_SIZE
,
571 static const struct intel_watermark_params i830_bc_wm_info
= {
572 .fifo_size
= I855GM_FIFO_SIZE
,
573 .max_wm
= I915_MAX_WM
/2,
576 .cacheline_size
= I830_FIFO_LINE_SIZE
,
578 static const struct intel_watermark_params i845_wm_info
= {
579 .fifo_size
= I830_FIFO_SIZE
,
580 .max_wm
= I915_MAX_WM
,
583 .cacheline_size
= I830_FIFO_LINE_SIZE
,
587 * intel_calculate_wm - calculate watermark level
588 * @clock_in_khz: pixel clock
589 * @wm: chip FIFO params
590 * @pixel_size: display pixel size
591 * @latency_ns: memory latency for the platform
593 * Calculate the watermark level (the level at which the display plane will
594 * start fetching from memory again). Each chip has a different display
595 * FIFO size and allocation, so the caller needs to figure that out and pass
596 * in the correct intel_watermark_params structure.
598 * As the pixel clock runs, the FIFO will be drained at a rate that depends
599 * on the pixel size. When it reaches the watermark level, it'll start
600 * fetching FIFO line sized based chunks from memory until the FIFO fills
601 * past the watermark point. If the FIFO drains completely, a FIFO underrun
602 * will occur, and a display engine hang could result.
604 static unsigned long intel_calculate_wm(unsigned long clock_in_khz
,
605 const struct intel_watermark_params
*wm
,
608 unsigned long latency_ns
)
610 long entries_required
, wm_size
;
613 * Note: we need to make sure we don't overflow for various clock &
615 * clocks go from a few thousand to several hundred thousand.
616 * latency is usually a few thousand
618 entries_required
= ((clock_in_khz
/ 1000) * pixel_size
* latency_ns
) /
620 entries_required
= DIV_ROUND_UP(entries_required
, wm
->cacheline_size
);
622 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required
);
624 wm_size
= fifo_size
- (entries_required
+ wm
->guard_size
);
626 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size
);
628 /* Don't promote wm_size to unsigned... */
629 if (wm_size
> (long)wm
->max_wm
)
630 wm_size
= wm
->max_wm
;
632 wm_size
= wm
->default_wm
;
635 * Bspec seems to indicate that the value shouldn't be lower than
636 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
637 * Lets go for 8 which is the burst size since certain platforms
638 * already use a hardcoded 8 (which is what the spec says should be
647 static struct drm_crtc
*single_enabled_crtc(struct drm_device
*dev
)
649 struct drm_crtc
*crtc
, *enabled
= NULL
;
651 for_each_crtc(dev
, crtc
) {
652 if (intel_crtc_active(crtc
)) {
662 static void pineview_update_wm(struct drm_crtc
*unused_crtc
)
664 struct drm_device
*dev
= unused_crtc
->dev
;
665 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
666 struct drm_crtc
*crtc
;
667 const struct cxsr_latency
*latency
;
671 latency
= intel_get_cxsr_latency(IS_PINEVIEW_G(dev
), dev_priv
->is_ddr3
,
672 dev_priv
->fsb_freq
, dev_priv
->mem_freq
);
674 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
675 intel_set_memory_cxsr(dev_priv
, false);
679 crtc
= single_enabled_crtc(dev
);
681 const struct drm_display_mode
*adjusted_mode
;
682 int pixel_size
= crtc
->primary
->state
->fb
->bits_per_pixel
/ 8;
685 adjusted_mode
= &to_intel_crtc(crtc
)->config
->base
.adjusted_mode
;
686 clock
= adjusted_mode
->crtc_clock
;
689 wm
= intel_calculate_wm(clock
, &pineview_display_wm
,
690 pineview_display_wm
.fifo_size
,
691 pixel_size
, latency
->display_sr
);
692 reg
= I915_READ(DSPFW1
);
693 reg
&= ~DSPFW_SR_MASK
;
694 reg
|= FW_WM(wm
, SR
);
695 I915_WRITE(DSPFW1
, reg
);
696 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg
);
699 wm
= intel_calculate_wm(clock
, &pineview_cursor_wm
,
700 pineview_display_wm
.fifo_size
,
701 pixel_size
, latency
->cursor_sr
);
702 reg
= I915_READ(DSPFW3
);
703 reg
&= ~DSPFW_CURSOR_SR_MASK
;
704 reg
|= FW_WM(wm
, CURSOR_SR
);
705 I915_WRITE(DSPFW3
, reg
);
707 /* Display HPLL off SR */
708 wm
= intel_calculate_wm(clock
, &pineview_display_hplloff_wm
,
709 pineview_display_hplloff_wm
.fifo_size
,
710 pixel_size
, latency
->display_hpll_disable
);
711 reg
= I915_READ(DSPFW3
);
712 reg
&= ~DSPFW_HPLL_SR_MASK
;
713 reg
|= FW_WM(wm
, HPLL_SR
);
714 I915_WRITE(DSPFW3
, reg
);
716 /* cursor HPLL off SR */
717 wm
= intel_calculate_wm(clock
, &pineview_cursor_hplloff_wm
,
718 pineview_display_hplloff_wm
.fifo_size
,
719 pixel_size
, latency
->cursor_hpll_disable
);
720 reg
= I915_READ(DSPFW3
);
721 reg
&= ~DSPFW_HPLL_CURSOR_MASK
;
722 reg
|= FW_WM(wm
, HPLL_CURSOR
);
723 I915_WRITE(DSPFW3
, reg
);
724 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg
);
726 intel_set_memory_cxsr(dev_priv
, true);
728 intel_set_memory_cxsr(dev_priv
, false);
732 static bool g4x_compute_wm0(struct drm_device
*dev
,
734 const struct intel_watermark_params
*display
,
735 int display_latency_ns
,
736 const struct intel_watermark_params
*cursor
,
737 int cursor_latency_ns
,
741 struct drm_crtc
*crtc
;
742 const struct drm_display_mode
*adjusted_mode
;
743 int htotal
, hdisplay
, clock
, pixel_size
;
744 int line_time_us
, line_count
;
745 int entries
, tlb_miss
;
747 crtc
= intel_get_crtc_for_plane(dev
, plane
);
748 if (!intel_crtc_active(crtc
)) {
749 *cursor_wm
= cursor
->guard_size
;
750 *plane_wm
= display
->guard_size
;
754 adjusted_mode
= &to_intel_crtc(crtc
)->config
->base
.adjusted_mode
;
755 clock
= adjusted_mode
->crtc_clock
;
756 htotal
= adjusted_mode
->crtc_htotal
;
757 hdisplay
= to_intel_crtc(crtc
)->config
->pipe_src_w
;
758 pixel_size
= crtc
->primary
->state
->fb
->bits_per_pixel
/ 8;
760 /* Use the small buffer method to calculate plane watermark */
761 entries
= ((clock
* pixel_size
/ 1000) * display_latency_ns
) / 1000;
762 tlb_miss
= display
->fifo_size
*display
->cacheline_size
- hdisplay
* 8;
765 entries
= DIV_ROUND_UP(entries
, display
->cacheline_size
);
766 *plane_wm
= entries
+ display
->guard_size
;
767 if (*plane_wm
> (int)display
->max_wm
)
768 *plane_wm
= display
->max_wm
;
770 /* Use the large buffer method to calculate cursor watermark */
771 line_time_us
= max(htotal
* 1000 / clock
, 1);
772 line_count
= (cursor_latency_ns
/ line_time_us
+ 1000) / 1000;
773 entries
= line_count
* crtc
->cursor
->state
->crtc_w
* pixel_size
;
774 tlb_miss
= cursor
->fifo_size
*cursor
->cacheline_size
- hdisplay
* 8;
777 entries
= DIV_ROUND_UP(entries
, cursor
->cacheline_size
);
778 *cursor_wm
= entries
+ cursor
->guard_size
;
779 if (*cursor_wm
> (int)cursor
->max_wm
)
780 *cursor_wm
= (int)cursor
->max_wm
;
786 * Check the wm result.
788 * If any calculated watermark values is larger than the maximum value that
789 * can be programmed into the associated watermark register, that watermark
792 static bool g4x_check_srwm(struct drm_device
*dev
,
793 int display_wm
, int cursor_wm
,
794 const struct intel_watermark_params
*display
,
795 const struct intel_watermark_params
*cursor
)
797 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
798 display_wm
, cursor_wm
);
800 if (display_wm
> display
->max_wm
) {
801 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
802 display_wm
, display
->max_wm
);
806 if (cursor_wm
> cursor
->max_wm
) {
807 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
808 cursor_wm
, cursor
->max_wm
);
812 if (!(display_wm
|| cursor_wm
)) {
813 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
820 static bool g4x_compute_srwm(struct drm_device
*dev
,
823 const struct intel_watermark_params
*display
,
824 const struct intel_watermark_params
*cursor
,
825 int *display_wm
, int *cursor_wm
)
827 struct drm_crtc
*crtc
;
828 const struct drm_display_mode
*adjusted_mode
;
829 int hdisplay
, htotal
, pixel_size
, clock
;
830 unsigned long line_time_us
;
831 int line_count
, line_size
;
836 *display_wm
= *cursor_wm
= 0;
840 crtc
= intel_get_crtc_for_plane(dev
, plane
);
841 adjusted_mode
= &to_intel_crtc(crtc
)->config
->base
.adjusted_mode
;
842 clock
= adjusted_mode
->crtc_clock
;
843 htotal
= adjusted_mode
->crtc_htotal
;
844 hdisplay
= to_intel_crtc(crtc
)->config
->pipe_src_w
;
845 pixel_size
= crtc
->primary
->state
->fb
->bits_per_pixel
/ 8;
847 line_time_us
= max(htotal
* 1000 / clock
, 1);
848 line_count
= (latency_ns
/ line_time_us
+ 1000) / 1000;
849 line_size
= hdisplay
* pixel_size
;
851 /* Use the minimum of the small and large buffer method for primary */
852 small
= ((clock
* pixel_size
/ 1000) * latency_ns
) / 1000;
853 large
= line_count
* line_size
;
855 entries
= DIV_ROUND_UP(min(small
, large
), display
->cacheline_size
);
856 *display_wm
= entries
+ display
->guard_size
;
858 /* calculate the self-refresh watermark for display cursor */
859 entries
= line_count
* pixel_size
* crtc
->cursor
->state
->crtc_w
;
860 entries
= DIV_ROUND_UP(entries
, cursor
->cacheline_size
);
861 *cursor_wm
= entries
+ cursor
->guard_size
;
863 return g4x_check_srwm(dev
,
864 *display_wm
, *cursor_wm
,
868 #define FW_WM_VLV(value, plane) \
869 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
871 static void vlv_write_wm_values(struct intel_crtc
*crtc
,
872 const struct vlv_wm_values
*wm
)
874 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
875 enum pipe pipe
= crtc
->pipe
;
877 I915_WRITE(VLV_DDL(pipe
),
878 (wm
->ddl
[pipe
].cursor
<< DDL_CURSOR_SHIFT
) |
879 (wm
->ddl
[pipe
].sprite
[1] << DDL_SPRITE_SHIFT(1)) |
880 (wm
->ddl
[pipe
].sprite
[0] << DDL_SPRITE_SHIFT(0)) |
881 (wm
->ddl
[pipe
].primary
<< DDL_PLANE_SHIFT
));
884 FW_WM(wm
->sr
.plane
, SR
) |
885 FW_WM(wm
->pipe
[PIPE_B
].cursor
, CURSORB
) |
886 FW_WM_VLV(wm
->pipe
[PIPE_B
].primary
, PLANEB
) |
887 FW_WM_VLV(wm
->pipe
[PIPE_A
].primary
, PLANEA
));
889 FW_WM_VLV(wm
->pipe
[PIPE_A
].sprite
[1], SPRITEB
) |
890 FW_WM(wm
->pipe
[PIPE_A
].cursor
, CURSORA
) |
891 FW_WM_VLV(wm
->pipe
[PIPE_A
].sprite
[0], SPRITEA
));
893 FW_WM(wm
->sr
.cursor
, CURSOR_SR
));
895 if (IS_CHERRYVIEW(dev_priv
)) {
896 I915_WRITE(DSPFW7_CHV
,
897 FW_WM_VLV(wm
->pipe
[PIPE_B
].sprite
[1], SPRITED
) |
898 FW_WM_VLV(wm
->pipe
[PIPE_B
].sprite
[0], SPRITEC
));
899 I915_WRITE(DSPFW8_CHV
,
900 FW_WM_VLV(wm
->pipe
[PIPE_C
].sprite
[1], SPRITEF
) |
901 FW_WM_VLV(wm
->pipe
[PIPE_C
].sprite
[0], SPRITEE
));
902 I915_WRITE(DSPFW9_CHV
,
903 FW_WM_VLV(wm
->pipe
[PIPE_C
].primary
, PLANEC
) |
904 FW_WM(wm
->pipe
[PIPE_C
].cursor
, CURSORC
));
906 FW_WM(wm
->sr
.plane
>> 9, SR_HI
) |
907 FW_WM(wm
->pipe
[PIPE_C
].sprite
[1] >> 8, SPRITEF_HI
) |
908 FW_WM(wm
->pipe
[PIPE_C
].sprite
[0] >> 8, SPRITEE_HI
) |
909 FW_WM(wm
->pipe
[PIPE_C
].primary
>> 8, PLANEC_HI
) |
910 FW_WM(wm
->pipe
[PIPE_B
].sprite
[1] >> 8, SPRITED_HI
) |
911 FW_WM(wm
->pipe
[PIPE_B
].sprite
[0] >> 8, SPRITEC_HI
) |
912 FW_WM(wm
->pipe
[PIPE_B
].primary
>> 8, PLANEB_HI
) |
913 FW_WM(wm
->pipe
[PIPE_A
].sprite
[1] >> 8, SPRITEB_HI
) |
914 FW_WM(wm
->pipe
[PIPE_A
].sprite
[0] >> 8, SPRITEA_HI
) |
915 FW_WM(wm
->pipe
[PIPE_A
].primary
>> 8, PLANEA_HI
));
918 FW_WM_VLV(wm
->pipe
[PIPE_B
].sprite
[1], SPRITED
) |
919 FW_WM_VLV(wm
->pipe
[PIPE_B
].sprite
[0], SPRITEC
));
921 FW_WM(wm
->sr
.plane
>> 9, SR_HI
) |
922 FW_WM(wm
->pipe
[PIPE_B
].sprite
[1] >> 8, SPRITED_HI
) |
923 FW_WM(wm
->pipe
[PIPE_B
].sprite
[0] >> 8, SPRITEC_HI
) |
924 FW_WM(wm
->pipe
[PIPE_B
].primary
>> 8, PLANEB_HI
) |
925 FW_WM(wm
->pipe
[PIPE_A
].sprite
[1] >> 8, SPRITEB_HI
) |
926 FW_WM(wm
->pipe
[PIPE_A
].sprite
[0] >> 8, SPRITEA_HI
) |
927 FW_WM(wm
->pipe
[PIPE_A
].primary
>> 8, PLANEA_HI
));
930 /* zero (unused) WM1 watermarks */
931 I915_WRITE(DSPFW4
, 0);
932 I915_WRITE(DSPFW5
, 0);
933 I915_WRITE(DSPFW6
, 0);
934 I915_WRITE(DSPHOWM1
, 0);
936 POSTING_READ(DSPFW1
);
944 VLV_WM_LEVEL_DDR_DVFS
,
946 VLV_WM_NUM_LEVELS
= 1,
949 /* latency must be in 0.1us units. */
950 static unsigned int vlv_wm_method2(unsigned int pixel_rate
,
951 unsigned int pipe_htotal
,
952 unsigned int horiz_pixels
,
953 unsigned int bytes_per_pixel
,
954 unsigned int latency
)
958 ret
= (latency
* pixel_rate
) / (pipe_htotal
* 10000);
959 ret
= (ret
+ 1) * horiz_pixels
* bytes_per_pixel
;
960 ret
= DIV_ROUND_UP(ret
, 64);
965 static void vlv_setup_wm_latency(struct drm_device
*dev
)
967 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
969 /* all latencies in usec */
970 dev_priv
->wm
.pri_latency
[VLV_WM_LEVEL_PM2
] = 3;
972 if (IS_CHERRYVIEW(dev_priv
)) {
973 dev_priv
->wm
.pri_latency
[VLV_WM_LEVEL_PM5
] = 12;
974 dev_priv
->wm
.pri_latency
[VLV_WM_LEVEL_DDR_DVFS
] = 33;
978 static uint16_t vlv_compute_wm_level(struct intel_plane
*plane
,
979 struct intel_crtc
*crtc
,
980 const struct intel_plane_state
*state
,
983 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
984 int clock
, htotal
, pixel_size
, width
, wm
;
986 if (dev_priv
->wm
.pri_latency
[level
] == 0)
992 pixel_size
= drm_format_plane_cpp(state
->base
.fb
->pixel_format
, 0);
993 clock
= crtc
->config
->base
.adjusted_mode
.crtc_clock
;
994 htotal
= crtc
->config
->base
.adjusted_mode
.crtc_htotal
;
995 width
= crtc
->config
->pipe_src_w
;
996 if (WARN_ON(htotal
== 0))
999 if (plane
->base
.type
== DRM_PLANE_TYPE_CURSOR
) {
1001 * FIXME the formula gives values that are
1002 * too big for the cursor FIFO, and hence we
1003 * would never be able to use cursors. For
1004 * now just hardcode the watermark.
1008 wm
= vlv_wm_method2(clock
, htotal
, width
, pixel_size
,
1009 dev_priv
->wm
.pri_latency
[level
] * 10);
1012 return min_t(int, wm
, USHRT_MAX
);
1015 static void vlv_compute_fifo(struct intel_crtc
*crtc
)
1017 struct drm_device
*dev
= crtc
->base
.dev
;
1018 struct vlv_wm_state
*wm_state
= &crtc
->wm_state
;
1019 struct intel_plane
*plane
;
1020 unsigned int total_rate
= 0;
1021 const int fifo_size
= 512 - 1;
1022 int fifo_extra
, fifo_left
= fifo_size
;
1024 for_each_intel_plane_on_crtc(dev
, crtc
, plane
) {
1025 struct intel_plane_state
*state
=
1026 to_intel_plane_state(plane
->base
.state
);
1028 if (plane
->base
.type
== DRM_PLANE_TYPE_CURSOR
)
1031 if (state
->visible
) {
1032 wm_state
->num_active_planes
++;
1033 total_rate
+= drm_format_plane_cpp(state
->base
.fb
->pixel_format
, 0);
1037 for_each_intel_plane_on_crtc(dev
, crtc
, plane
) {
1038 struct intel_plane_state
*state
=
1039 to_intel_plane_state(plane
->base
.state
);
1042 if (plane
->base
.type
== DRM_PLANE_TYPE_CURSOR
) {
1043 plane
->wm
.fifo_size
= 63;
1047 if (!state
->visible
) {
1048 plane
->wm
.fifo_size
= 0;
1052 rate
= drm_format_plane_cpp(state
->base
.fb
->pixel_format
, 0);
1053 plane
->wm
.fifo_size
= fifo_size
* rate
/ total_rate
;
1054 fifo_left
-= plane
->wm
.fifo_size
;
1057 fifo_extra
= DIV_ROUND_UP(fifo_left
, wm_state
->num_active_planes
?: 1);
1059 /* spread the remainder evenly */
1060 for_each_intel_plane_on_crtc(dev
, crtc
, plane
) {
1066 if (plane
->base
.type
== DRM_PLANE_TYPE_CURSOR
)
1069 /* give it all to the first plane if none are active */
1070 if (plane
->wm
.fifo_size
== 0 &&
1071 wm_state
->num_active_planes
)
1074 plane_extra
= min(fifo_extra
, fifo_left
);
1075 plane
->wm
.fifo_size
+= plane_extra
;
1076 fifo_left
-= plane_extra
;
1079 WARN_ON(fifo_left
!= 0);
1082 static void vlv_invert_wms(struct intel_crtc
*crtc
)
1084 struct vlv_wm_state
*wm_state
= &crtc
->wm_state
;
1087 for (level
= 0; level
< wm_state
->num_levels
; level
++) {
1088 struct drm_device
*dev
= crtc
->base
.dev
;
1089 const int sr_fifo_size
= INTEL_INFO(dev
)->num_pipes
* 512 - 1;
1090 struct intel_plane
*plane
;
1092 wm_state
->sr
[level
].plane
= sr_fifo_size
- wm_state
->sr
[level
].plane
;
1093 wm_state
->sr
[level
].cursor
= 63 - wm_state
->sr
[level
].cursor
;
1095 for_each_intel_plane_on_crtc(dev
, crtc
, plane
) {
1096 switch (plane
->base
.type
) {
1098 case DRM_PLANE_TYPE_CURSOR
:
1099 wm_state
->wm
[level
].cursor
= plane
->wm
.fifo_size
-
1100 wm_state
->wm
[level
].cursor
;
1102 case DRM_PLANE_TYPE_PRIMARY
:
1103 wm_state
->wm
[level
].primary
= plane
->wm
.fifo_size
-
1104 wm_state
->wm
[level
].primary
;
1106 case DRM_PLANE_TYPE_OVERLAY
:
1107 sprite
= plane
->plane
;
1108 wm_state
->wm
[level
].sprite
[sprite
] = plane
->wm
.fifo_size
-
1109 wm_state
->wm
[level
].sprite
[sprite
];
1116 static void vlv_compute_wm(struct intel_crtc
*crtc
)
1118 struct drm_device
*dev
= crtc
->base
.dev
;
1119 struct vlv_wm_state
*wm_state
= &crtc
->wm_state
;
1120 struct intel_plane
*plane
;
1121 int sr_fifo_size
= INTEL_INFO(dev
)->num_pipes
* 512 - 1;
1124 memset(wm_state
, 0, sizeof(*wm_state
));
1126 wm_state
->cxsr
= crtc
->pipe
!= PIPE_C
&& crtc
->wm
.cxsr_allowed
;
1127 if (IS_CHERRYVIEW(dev
))
1128 wm_state
->num_levels
= CHV_WM_NUM_LEVELS
;
1130 wm_state
->num_levels
= VLV_WM_NUM_LEVELS
;
1132 wm_state
->num_active_planes
= 0;
1134 vlv_compute_fifo(crtc
);
1136 if (wm_state
->num_active_planes
!= 1)
1137 wm_state
->cxsr
= false;
1139 if (wm_state
->cxsr
) {
1140 for (level
= 0; level
< wm_state
->num_levels
; level
++) {
1141 wm_state
->sr
[level
].plane
= sr_fifo_size
;
1142 wm_state
->sr
[level
].cursor
= 63;
1146 for_each_intel_plane_on_crtc(dev
, crtc
, plane
) {
1147 struct intel_plane_state
*state
=
1148 to_intel_plane_state(plane
->base
.state
);
1150 if (!state
->visible
)
1153 /* normal watermarks */
1154 for (level
= 0; level
< wm_state
->num_levels
; level
++) {
1155 int wm
= vlv_compute_wm_level(plane
, crtc
, state
, level
);
1156 int max_wm
= plane
->base
.type
== DRM_PLANE_TYPE_CURSOR
? 63 : 511;
1159 if (WARN_ON(level
== 0 && wm
> max_wm
))
1162 if (wm
> plane
->wm
.fifo_size
)
1165 switch (plane
->base
.type
) {
1167 case DRM_PLANE_TYPE_CURSOR
:
1168 wm_state
->wm
[level
].cursor
= wm
;
1170 case DRM_PLANE_TYPE_PRIMARY
:
1171 wm_state
->wm
[level
].primary
= wm
;
1173 case DRM_PLANE_TYPE_OVERLAY
:
1174 sprite
= plane
->plane
;
1175 wm_state
->wm
[level
].sprite
[sprite
] = wm
;
1180 wm_state
->num_levels
= level
;
1182 if (!wm_state
->cxsr
)
1185 /* maxfifo watermarks */
1186 switch (plane
->base
.type
) {
1188 case DRM_PLANE_TYPE_CURSOR
:
1189 for (level
= 0; level
< wm_state
->num_levels
; level
++)
1190 wm_state
->sr
[level
].cursor
=
1191 wm_state
->sr
[level
].cursor
;
1193 case DRM_PLANE_TYPE_PRIMARY
:
1194 for (level
= 0; level
< wm_state
->num_levels
; level
++)
1195 wm_state
->sr
[level
].plane
=
1196 min(wm_state
->sr
[level
].plane
,
1197 wm_state
->wm
[level
].primary
);
1199 case DRM_PLANE_TYPE_OVERLAY
:
1200 sprite
= plane
->plane
;
1201 for (level
= 0; level
< wm_state
->num_levels
; level
++)
1202 wm_state
->sr
[level
].plane
=
1203 min(wm_state
->sr
[level
].plane
,
1204 wm_state
->wm
[level
].sprite
[sprite
]);
1209 /* clear any (partially) filled invalid levels */
1210 for (level
= wm_state
->num_levels
; level
< CHV_WM_NUM_LEVELS
; level
++) {
1211 memset(&wm_state
->wm
[level
], 0, sizeof(wm_state
->wm
[level
]));
1212 memset(&wm_state
->sr
[level
], 0, sizeof(wm_state
->sr
[level
]));
1215 vlv_invert_wms(crtc
);
1218 #define VLV_FIFO(plane, value) \
1219 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1221 static void vlv_pipe_set_fifo_size(struct intel_crtc
*crtc
)
1223 struct drm_device
*dev
= crtc
->base
.dev
;
1224 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1225 struct intel_plane
*plane
;
1226 int sprite0_start
= 0, sprite1_start
= 0, fifo_size
= 0;
1228 for_each_intel_plane_on_crtc(dev
, crtc
, plane
) {
1229 if (plane
->base
.type
== DRM_PLANE_TYPE_CURSOR
) {
1230 WARN_ON(plane
->wm
.fifo_size
!= 63);
1234 if (plane
->base
.type
== DRM_PLANE_TYPE_PRIMARY
)
1235 sprite0_start
= plane
->wm
.fifo_size
;
1236 else if (plane
->plane
== 0)
1237 sprite1_start
= sprite0_start
+ plane
->wm
.fifo_size
;
1239 fifo_size
= sprite1_start
+ plane
->wm
.fifo_size
;
1242 WARN_ON(fifo_size
!= 512 - 1);
1244 DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1245 pipe_name(crtc
->pipe
), sprite0_start
,
1246 sprite1_start
, fifo_size
);
1248 switch (crtc
->pipe
) {
1249 uint32_t dsparb
, dsparb2
, dsparb3
;
1251 dsparb
= I915_READ(DSPARB
);
1252 dsparb2
= I915_READ(DSPARB2
);
1254 dsparb
&= ~(VLV_FIFO(SPRITEA
, 0xff) |
1255 VLV_FIFO(SPRITEB
, 0xff));
1256 dsparb
|= (VLV_FIFO(SPRITEA
, sprite0_start
) |
1257 VLV_FIFO(SPRITEB
, sprite1_start
));
1259 dsparb2
&= ~(VLV_FIFO(SPRITEA_HI
, 0x1) |
1260 VLV_FIFO(SPRITEB_HI
, 0x1));
1261 dsparb2
|= (VLV_FIFO(SPRITEA_HI
, sprite0_start
>> 8) |
1262 VLV_FIFO(SPRITEB_HI
, sprite1_start
>> 8));
1264 I915_WRITE(DSPARB
, dsparb
);
1265 I915_WRITE(DSPARB2
, dsparb2
);
1268 dsparb
= I915_READ(DSPARB
);
1269 dsparb2
= I915_READ(DSPARB2
);
1271 dsparb
&= ~(VLV_FIFO(SPRITEC
, 0xff) |
1272 VLV_FIFO(SPRITED
, 0xff));
1273 dsparb
|= (VLV_FIFO(SPRITEC
, sprite0_start
) |
1274 VLV_FIFO(SPRITED
, sprite1_start
));
1276 dsparb2
&= ~(VLV_FIFO(SPRITEC_HI
, 0xff) |
1277 VLV_FIFO(SPRITED_HI
, 0xff));
1278 dsparb2
|= (VLV_FIFO(SPRITEC_HI
, sprite0_start
>> 8) |
1279 VLV_FIFO(SPRITED_HI
, sprite1_start
>> 8));
1281 I915_WRITE(DSPARB
, dsparb
);
1282 I915_WRITE(DSPARB2
, dsparb2
);
1285 dsparb3
= I915_READ(DSPARB3
);
1286 dsparb2
= I915_READ(DSPARB2
);
1288 dsparb3
&= ~(VLV_FIFO(SPRITEE
, 0xff) |
1289 VLV_FIFO(SPRITEF
, 0xff));
1290 dsparb3
|= (VLV_FIFO(SPRITEE
, sprite0_start
) |
1291 VLV_FIFO(SPRITEF
, sprite1_start
));
1293 dsparb2
&= ~(VLV_FIFO(SPRITEE_HI
, 0xff) |
1294 VLV_FIFO(SPRITEF_HI
, 0xff));
1295 dsparb2
|= (VLV_FIFO(SPRITEE_HI
, sprite0_start
>> 8) |
1296 VLV_FIFO(SPRITEF_HI
, sprite1_start
>> 8));
1298 I915_WRITE(DSPARB3
, dsparb3
);
1299 I915_WRITE(DSPARB2
, dsparb2
);
1308 static void vlv_merge_wm(struct drm_device
*dev
,
1309 struct vlv_wm_values
*wm
)
1311 struct intel_crtc
*crtc
;
1312 int num_active_crtcs
= 0;
1314 if (IS_CHERRYVIEW(dev
))
1315 wm
->level
= VLV_WM_LEVEL_DDR_DVFS
;
1317 wm
->level
= VLV_WM_LEVEL_PM2
;
1320 for_each_intel_crtc(dev
, crtc
) {
1321 const struct vlv_wm_state
*wm_state
= &crtc
->wm_state
;
1326 if (!wm_state
->cxsr
)
1330 wm
->level
= min_t(int, wm
->level
, wm_state
->num_levels
- 1);
1333 if (num_active_crtcs
!= 1)
1336 if (num_active_crtcs
> 1)
1337 wm
->level
= VLV_WM_LEVEL_PM2
;
1339 for_each_intel_crtc(dev
, crtc
) {
1340 struct vlv_wm_state
*wm_state
= &crtc
->wm_state
;
1341 enum pipe pipe
= crtc
->pipe
;
1346 wm
->pipe
[pipe
] = wm_state
->wm
[wm
->level
];
1348 wm
->sr
= wm_state
->sr
[wm
->level
];
1350 wm
->ddl
[pipe
].primary
= DDL_PRECISION_HIGH
| 2;
1351 wm
->ddl
[pipe
].sprite
[0] = DDL_PRECISION_HIGH
| 2;
1352 wm
->ddl
[pipe
].sprite
[1] = DDL_PRECISION_HIGH
| 2;
1353 wm
->ddl
[pipe
].cursor
= DDL_PRECISION_HIGH
| 2;
1357 static void vlv_update_wm(struct drm_crtc
*crtc
)
1359 struct drm_device
*dev
= crtc
->dev
;
1360 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1361 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1362 enum pipe pipe
= intel_crtc
->pipe
;
1363 struct vlv_wm_values wm
= {};
1365 vlv_compute_wm(intel_crtc
);
1366 vlv_merge_wm(dev
, &wm
);
1368 if (memcmp(&dev_priv
->wm
.vlv
, &wm
, sizeof(wm
)) == 0) {
1369 /* FIXME should be part of crtc atomic commit */
1370 vlv_pipe_set_fifo_size(intel_crtc
);
1374 if (wm
.level
< VLV_WM_LEVEL_DDR_DVFS
&&
1375 dev_priv
->wm
.vlv
.level
>= VLV_WM_LEVEL_DDR_DVFS
)
1376 chv_set_memory_dvfs(dev_priv
, false);
1378 if (wm
.level
< VLV_WM_LEVEL_PM5
&&
1379 dev_priv
->wm
.vlv
.level
>= VLV_WM_LEVEL_PM5
)
1380 chv_set_memory_pm5(dev_priv
, false);
1382 if (!wm
.cxsr
&& dev_priv
->wm
.vlv
.cxsr
)
1383 intel_set_memory_cxsr(dev_priv
, false);
1385 /* FIXME should be part of crtc atomic commit */
1386 vlv_pipe_set_fifo_size(intel_crtc
);
1388 vlv_write_wm_values(intel_crtc
, &wm
);
1390 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1391 "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1392 pipe_name(pipe
), wm
.pipe
[pipe
].primary
, wm
.pipe
[pipe
].cursor
,
1393 wm
.pipe
[pipe
].sprite
[0], wm
.pipe
[pipe
].sprite
[1],
1394 wm
.sr
.plane
, wm
.sr
.cursor
, wm
.level
, wm
.cxsr
);
1396 if (wm
.cxsr
&& !dev_priv
->wm
.vlv
.cxsr
)
1397 intel_set_memory_cxsr(dev_priv
, true);
1399 if (wm
.level
>= VLV_WM_LEVEL_PM5
&&
1400 dev_priv
->wm
.vlv
.level
< VLV_WM_LEVEL_PM5
)
1401 chv_set_memory_pm5(dev_priv
, true);
1403 if (wm
.level
>= VLV_WM_LEVEL_DDR_DVFS
&&
1404 dev_priv
->wm
.vlv
.level
< VLV_WM_LEVEL_DDR_DVFS
)
1405 chv_set_memory_dvfs(dev_priv
, true);
1407 dev_priv
->wm
.vlv
= wm
;
1410 #define single_plane_enabled(mask) is_power_of_2(mask)
1412 static void g4x_update_wm(struct drm_crtc
*crtc
)
1414 struct drm_device
*dev
= crtc
->dev
;
1415 static const int sr_latency_ns
= 12000;
1416 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1417 int planea_wm
, planeb_wm
, cursora_wm
, cursorb_wm
;
1418 int plane_sr
, cursor_sr
;
1419 unsigned int enabled
= 0;
1422 if (g4x_compute_wm0(dev
, PIPE_A
,
1423 &g4x_wm_info
, pessimal_latency_ns
,
1424 &g4x_cursor_wm_info
, pessimal_latency_ns
,
1425 &planea_wm
, &cursora_wm
))
1426 enabled
|= 1 << PIPE_A
;
1428 if (g4x_compute_wm0(dev
, PIPE_B
,
1429 &g4x_wm_info
, pessimal_latency_ns
,
1430 &g4x_cursor_wm_info
, pessimal_latency_ns
,
1431 &planeb_wm
, &cursorb_wm
))
1432 enabled
|= 1 << PIPE_B
;
1434 if (single_plane_enabled(enabled
) &&
1435 g4x_compute_srwm(dev
, ffs(enabled
) - 1,
1438 &g4x_cursor_wm_info
,
1439 &plane_sr
, &cursor_sr
)) {
1440 cxsr_enabled
= true;
1442 cxsr_enabled
= false;
1443 intel_set_memory_cxsr(dev_priv
, false);
1444 plane_sr
= cursor_sr
= 0;
1447 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1448 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1449 planea_wm
, cursora_wm
,
1450 planeb_wm
, cursorb_wm
,
1451 plane_sr
, cursor_sr
);
1454 FW_WM(plane_sr
, SR
) |
1455 FW_WM(cursorb_wm
, CURSORB
) |
1456 FW_WM(planeb_wm
, PLANEB
) |
1457 FW_WM(planea_wm
, PLANEA
));
1459 (I915_READ(DSPFW2
) & ~DSPFW_CURSORA_MASK
) |
1460 FW_WM(cursora_wm
, CURSORA
));
1461 /* HPLL off in SR has some issues on G4x... disable it */
1463 (I915_READ(DSPFW3
) & ~(DSPFW_HPLL_SR_EN
| DSPFW_CURSOR_SR_MASK
)) |
1464 FW_WM(cursor_sr
, CURSOR_SR
));
1467 intel_set_memory_cxsr(dev_priv
, true);
1470 static void i965_update_wm(struct drm_crtc
*unused_crtc
)
1472 struct drm_device
*dev
= unused_crtc
->dev
;
1473 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1474 struct drm_crtc
*crtc
;
1479 /* Calc sr entries for one plane configs */
1480 crtc
= single_enabled_crtc(dev
);
1482 /* self-refresh has much higher latency */
1483 static const int sr_latency_ns
= 12000;
1484 const struct drm_display_mode
*adjusted_mode
=
1485 &to_intel_crtc(crtc
)->config
->base
.adjusted_mode
;
1486 int clock
= adjusted_mode
->crtc_clock
;
1487 int htotal
= adjusted_mode
->crtc_htotal
;
1488 int hdisplay
= to_intel_crtc(crtc
)->config
->pipe_src_w
;
1489 int pixel_size
= crtc
->primary
->state
->fb
->bits_per_pixel
/ 8;
1490 unsigned long line_time_us
;
1493 line_time_us
= max(htotal
* 1000 / clock
, 1);
1495 /* Use ns/us then divide to preserve precision */
1496 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
1497 pixel_size
* hdisplay
;
1498 entries
= DIV_ROUND_UP(entries
, I915_FIFO_LINE_SIZE
);
1499 srwm
= I965_FIFO_SIZE
- entries
;
1503 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1506 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
1507 pixel_size
* crtc
->cursor
->state
->crtc_w
;
1508 entries
= DIV_ROUND_UP(entries
,
1509 i965_cursor_wm_info
.cacheline_size
);
1510 cursor_sr
= i965_cursor_wm_info
.fifo_size
-
1511 (entries
+ i965_cursor_wm_info
.guard_size
);
1513 if (cursor_sr
> i965_cursor_wm_info
.max_wm
)
1514 cursor_sr
= i965_cursor_wm_info
.max_wm
;
1516 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1517 "cursor %d\n", srwm
, cursor_sr
);
1519 cxsr_enabled
= true;
1521 cxsr_enabled
= false;
1522 /* Turn off self refresh if both pipes are enabled */
1523 intel_set_memory_cxsr(dev_priv
, false);
1526 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1529 /* 965 has limitations... */
1530 I915_WRITE(DSPFW1
, FW_WM(srwm
, SR
) |
1534 I915_WRITE(DSPFW2
, FW_WM(8, CURSORA
) |
1535 FW_WM(8, PLANEC_OLD
));
1536 /* update cursor SR watermark */
1537 I915_WRITE(DSPFW3
, FW_WM(cursor_sr
, CURSOR_SR
));
1540 intel_set_memory_cxsr(dev_priv
, true);
1545 static void i9xx_update_wm(struct drm_crtc
*unused_crtc
)
1547 struct drm_device
*dev
= unused_crtc
->dev
;
1548 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1549 const struct intel_watermark_params
*wm_info
;
1554 int planea_wm
, planeb_wm
;
1555 struct drm_crtc
*crtc
, *enabled
= NULL
;
1558 wm_info
= &i945_wm_info
;
1559 else if (!IS_GEN2(dev
))
1560 wm_info
= &i915_wm_info
;
1562 wm_info
= &i830_a_wm_info
;
1564 fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 0);
1565 crtc
= intel_get_crtc_for_plane(dev
, 0);
1566 if (intel_crtc_active(crtc
)) {
1567 const struct drm_display_mode
*adjusted_mode
;
1568 int cpp
= crtc
->primary
->state
->fb
->bits_per_pixel
/ 8;
1572 adjusted_mode
= &to_intel_crtc(crtc
)->config
->base
.adjusted_mode
;
1573 planea_wm
= intel_calculate_wm(adjusted_mode
->crtc_clock
,
1574 wm_info
, fifo_size
, cpp
,
1575 pessimal_latency_ns
);
1578 planea_wm
= fifo_size
- wm_info
->guard_size
;
1579 if (planea_wm
> (long)wm_info
->max_wm
)
1580 planea_wm
= wm_info
->max_wm
;
1584 wm_info
= &i830_bc_wm_info
;
1586 fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 1);
1587 crtc
= intel_get_crtc_for_plane(dev
, 1);
1588 if (intel_crtc_active(crtc
)) {
1589 const struct drm_display_mode
*adjusted_mode
;
1590 int cpp
= crtc
->primary
->state
->fb
->bits_per_pixel
/ 8;
1594 adjusted_mode
= &to_intel_crtc(crtc
)->config
->base
.adjusted_mode
;
1595 planeb_wm
= intel_calculate_wm(adjusted_mode
->crtc_clock
,
1596 wm_info
, fifo_size
, cpp
,
1597 pessimal_latency_ns
);
1598 if (enabled
== NULL
)
1603 planeb_wm
= fifo_size
- wm_info
->guard_size
;
1604 if (planeb_wm
> (long)wm_info
->max_wm
)
1605 planeb_wm
= wm_info
->max_wm
;
1608 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm
, planeb_wm
);
1610 if (IS_I915GM(dev
) && enabled
) {
1611 struct drm_i915_gem_object
*obj
;
1613 obj
= intel_fb_obj(enabled
->primary
->state
->fb
);
1615 /* self-refresh seems busted with untiled */
1616 if (obj
->tiling_mode
== I915_TILING_NONE
)
1621 * Overlay gets an aggressive default since video jitter is bad.
1625 /* Play safe and disable self-refresh before adjusting watermarks. */
1626 intel_set_memory_cxsr(dev_priv
, false);
1628 /* Calc sr entries for one plane configs */
1629 if (HAS_FW_BLC(dev
) && enabled
) {
1630 /* self-refresh has much higher latency */
1631 static const int sr_latency_ns
= 6000;
1632 const struct drm_display_mode
*adjusted_mode
=
1633 &to_intel_crtc(enabled
)->config
->base
.adjusted_mode
;
1634 int clock
= adjusted_mode
->crtc_clock
;
1635 int htotal
= adjusted_mode
->crtc_htotal
;
1636 int hdisplay
= to_intel_crtc(enabled
)->config
->pipe_src_w
;
1637 int pixel_size
= enabled
->primary
->state
->fb
->bits_per_pixel
/ 8;
1638 unsigned long line_time_us
;
1641 line_time_us
= max(htotal
* 1000 / clock
, 1);
1643 /* Use ns/us then divide to preserve precision */
1644 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
1645 pixel_size
* hdisplay
;
1646 entries
= DIV_ROUND_UP(entries
, wm_info
->cacheline_size
);
1647 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries
);
1648 srwm
= wm_info
->fifo_size
- entries
;
1652 if (IS_I945G(dev
) || IS_I945GM(dev
))
1653 I915_WRITE(FW_BLC_SELF
,
1654 FW_BLC_SELF_FIFO_MASK
| (srwm
& 0xff));
1655 else if (IS_I915GM(dev
))
1656 I915_WRITE(FW_BLC_SELF
, srwm
& 0x3f);
1659 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1660 planea_wm
, planeb_wm
, cwm
, srwm
);
1662 fwater_lo
= ((planeb_wm
& 0x3f) << 16) | (planea_wm
& 0x3f);
1663 fwater_hi
= (cwm
& 0x1f);
1665 /* Set request length to 8 cachelines per fetch */
1666 fwater_lo
= fwater_lo
| (1 << 24) | (1 << 8);
1667 fwater_hi
= fwater_hi
| (1 << 8);
1669 I915_WRITE(FW_BLC
, fwater_lo
);
1670 I915_WRITE(FW_BLC2
, fwater_hi
);
1673 intel_set_memory_cxsr(dev_priv
, true);
1676 static void i845_update_wm(struct drm_crtc
*unused_crtc
)
1678 struct drm_device
*dev
= unused_crtc
->dev
;
1679 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1680 struct drm_crtc
*crtc
;
1681 const struct drm_display_mode
*adjusted_mode
;
1685 crtc
= single_enabled_crtc(dev
);
1689 adjusted_mode
= &to_intel_crtc(crtc
)->config
->base
.adjusted_mode
;
1690 planea_wm
= intel_calculate_wm(adjusted_mode
->crtc_clock
,
1692 dev_priv
->display
.get_fifo_size(dev
, 0),
1693 4, pessimal_latency_ns
);
1694 fwater_lo
= I915_READ(FW_BLC
) & ~0xfff;
1695 fwater_lo
|= (3<<8) | planea_wm
;
1697 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm
);
1699 I915_WRITE(FW_BLC
, fwater_lo
);
1702 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state
*pipe_config
)
1704 uint32_t pixel_rate
;
1706 pixel_rate
= pipe_config
->base
.adjusted_mode
.crtc_clock
;
1708 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1709 * adjust the pixel_rate here. */
1711 if (pipe_config
->pch_pfit
.enabled
) {
1712 uint64_t pipe_w
, pipe_h
, pfit_w
, pfit_h
;
1713 uint32_t pfit_size
= pipe_config
->pch_pfit
.size
;
1715 pipe_w
= pipe_config
->pipe_src_w
;
1716 pipe_h
= pipe_config
->pipe_src_h
;
1718 pfit_w
= (pfit_size
>> 16) & 0xFFFF;
1719 pfit_h
= pfit_size
& 0xFFFF;
1720 if (pipe_w
< pfit_w
)
1722 if (pipe_h
< pfit_h
)
1725 pixel_rate
= div_u64((uint64_t) pixel_rate
* pipe_w
* pipe_h
,
1732 /* latency must be in 0.1us units. */
1733 static uint32_t ilk_wm_method1(uint32_t pixel_rate
, uint8_t bytes_per_pixel
,
1738 if (WARN(latency
== 0, "Latency value missing\n"))
1741 ret
= (uint64_t) pixel_rate
* bytes_per_pixel
* latency
;
1742 ret
= DIV_ROUND_UP_ULL(ret
, 64 * 10000) + 2;
1747 /* latency must be in 0.1us units. */
1748 static uint32_t ilk_wm_method2(uint32_t pixel_rate
, uint32_t pipe_htotal
,
1749 uint32_t horiz_pixels
, uint8_t bytes_per_pixel
,
1754 if (WARN(latency
== 0, "Latency value missing\n"))
1757 ret
= (latency
* pixel_rate
) / (pipe_htotal
* 10000);
1758 ret
= (ret
+ 1) * horiz_pixels
* bytes_per_pixel
;
1759 ret
= DIV_ROUND_UP(ret
, 64) + 2;
1763 static uint32_t ilk_wm_fbc(uint32_t pri_val
, uint32_t horiz_pixels
,
1764 uint8_t bytes_per_pixel
)
1766 return DIV_ROUND_UP(pri_val
* 64, horiz_pixels
* bytes_per_pixel
) + 2;
1769 struct skl_pipe_wm_parameters
{
1771 uint32_t pipe_htotal
;
1772 uint32_t pixel_rate
; /* in KHz */
1773 struct intel_plane_wm_parameters plane
[I915_MAX_PLANES
];
1774 struct intel_plane_wm_parameters cursor
;
1777 struct ilk_pipe_wm_parameters
{
1779 uint32_t pipe_htotal
;
1780 uint32_t pixel_rate
;
1781 struct intel_plane_wm_parameters pri
;
1782 struct intel_plane_wm_parameters spr
;
1783 struct intel_plane_wm_parameters cur
;
1786 struct ilk_wm_maximums
{
1793 /* used in computing the new watermarks state */
1794 struct intel_wm_config
{
1795 unsigned int num_pipes_active
;
1796 bool sprites_enabled
;
1797 bool sprites_scaled
;
1801 * For both WM_PIPE and WM_LP.
1802 * mem_value must be in 0.1us units.
1804 static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters
*params
,
1808 uint32_t method1
, method2
;
1810 if (!params
->active
|| !params
->pri
.enabled
)
1813 method1
= ilk_wm_method1(params
->pixel_rate
,
1814 params
->pri
.bytes_per_pixel
,
1820 method2
= ilk_wm_method2(params
->pixel_rate
,
1821 params
->pipe_htotal
,
1822 params
->pri
.horiz_pixels
,
1823 params
->pri
.bytes_per_pixel
,
1826 return min(method1
, method2
);
1830 * For both WM_PIPE and WM_LP.
1831 * mem_value must be in 0.1us units.
1833 static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters
*params
,
1836 uint32_t method1
, method2
;
1838 if (!params
->active
|| !params
->spr
.enabled
)
1841 method1
= ilk_wm_method1(params
->pixel_rate
,
1842 params
->spr
.bytes_per_pixel
,
1844 method2
= ilk_wm_method2(params
->pixel_rate
,
1845 params
->pipe_htotal
,
1846 params
->spr
.horiz_pixels
,
1847 params
->spr
.bytes_per_pixel
,
1849 return min(method1
, method2
);
1853 * For both WM_PIPE and WM_LP.
1854 * mem_value must be in 0.1us units.
1856 static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters
*params
,
1859 if (!params
->active
|| !params
->cur
.enabled
)
1862 return ilk_wm_method2(params
->pixel_rate
,
1863 params
->pipe_htotal
,
1864 params
->cur
.horiz_pixels
,
1865 params
->cur
.bytes_per_pixel
,
1869 /* Only for WM_LP. */
1870 static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters
*params
,
1873 if (!params
->active
|| !params
->pri
.enabled
)
1876 return ilk_wm_fbc(pri_val
,
1877 params
->pri
.horiz_pixels
,
1878 params
->pri
.bytes_per_pixel
);
1881 static unsigned int ilk_display_fifo_size(const struct drm_device
*dev
)
1883 if (INTEL_INFO(dev
)->gen
>= 8)
1885 else if (INTEL_INFO(dev
)->gen
>= 7)
1891 static unsigned int ilk_plane_wm_reg_max(const struct drm_device
*dev
,
1892 int level
, bool is_sprite
)
1894 if (INTEL_INFO(dev
)->gen
>= 8)
1895 /* BDW primary/sprite plane watermarks */
1896 return level
== 0 ? 255 : 2047;
1897 else if (INTEL_INFO(dev
)->gen
>= 7)
1898 /* IVB/HSW primary/sprite plane watermarks */
1899 return level
== 0 ? 127 : 1023;
1900 else if (!is_sprite
)
1901 /* ILK/SNB primary plane watermarks */
1902 return level
== 0 ? 127 : 511;
1904 /* ILK/SNB sprite plane watermarks */
1905 return level
== 0 ? 63 : 255;
1908 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device
*dev
,
1911 if (INTEL_INFO(dev
)->gen
>= 7)
1912 return level
== 0 ? 63 : 255;
1914 return level
== 0 ? 31 : 63;
1917 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device
*dev
)
1919 if (INTEL_INFO(dev
)->gen
>= 8)
1925 /* Calculate the maximum primary/sprite plane watermark */
1926 static unsigned int ilk_plane_wm_max(const struct drm_device
*dev
,
1928 const struct intel_wm_config
*config
,
1929 enum intel_ddb_partitioning ddb_partitioning
,
1932 unsigned int fifo_size
= ilk_display_fifo_size(dev
);
1934 /* if sprites aren't enabled, sprites get nothing */
1935 if (is_sprite
&& !config
->sprites_enabled
)
1938 /* HSW allows LP1+ watermarks even with multiple pipes */
1939 if (level
== 0 || config
->num_pipes_active
> 1) {
1940 fifo_size
/= INTEL_INFO(dev
)->num_pipes
;
1943 * For some reason the non self refresh
1944 * FIFO size is only half of the self
1945 * refresh FIFO size on ILK/SNB.
1947 if (INTEL_INFO(dev
)->gen
<= 6)
1951 if (config
->sprites_enabled
) {
1952 /* level 0 is always calculated with 1:1 split */
1953 if (level
> 0 && ddb_partitioning
== INTEL_DDB_PART_5_6
) {
1962 /* clamp to max that the registers can hold */
1963 return min(fifo_size
, ilk_plane_wm_reg_max(dev
, level
, is_sprite
));
1966 /* Calculate the maximum cursor plane watermark */
1967 static unsigned int ilk_cursor_wm_max(const struct drm_device
*dev
,
1969 const struct intel_wm_config
*config
)
1971 /* HSW LP1+ watermarks w/ multiple pipes */
1972 if (level
> 0 && config
->num_pipes_active
> 1)
1975 /* otherwise just report max that registers can hold */
1976 return ilk_cursor_wm_reg_max(dev
, level
);
1979 static void ilk_compute_wm_maximums(const struct drm_device
*dev
,
1981 const struct intel_wm_config
*config
,
1982 enum intel_ddb_partitioning ddb_partitioning
,
1983 struct ilk_wm_maximums
*max
)
1985 max
->pri
= ilk_plane_wm_max(dev
, level
, config
, ddb_partitioning
, false);
1986 max
->spr
= ilk_plane_wm_max(dev
, level
, config
, ddb_partitioning
, true);
1987 max
->cur
= ilk_cursor_wm_max(dev
, level
, config
);
1988 max
->fbc
= ilk_fbc_wm_reg_max(dev
);
1991 static void ilk_compute_wm_reg_maximums(struct drm_device
*dev
,
1993 struct ilk_wm_maximums
*max
)
1995 max
->pri
= ilk_plane_wm_reg_max(dev
, level
, false);
1996 max
->spr
= ilk_plane_wm_reg_max(dev
, level
, true);
1997 max
->cur
= ilk_cursor_wm_reg_max(dev
, level
);
1998 max
->fbc
= ilk_fbc_wm_reg_max(dev
);
2001 static bool ilk_validate_wm_level(int level
,
2002 const struct ilk_wm_maximums
*max
,
2003 struct intel_wm_level
*result
)
2007 /* already determined to be invalid? */
2008 if (!result
->enable
)
2011 result
->enable
= result
->pri_val
<= max
->pri
&&
2012 result
->spr_val
<= max
->spr
&&
2013 result
->cur_val
<= max
->cur
;
2015 ret
= result
->enable
;
2018 * HACK until we can pre-compute everything,
2019 * and thus fail gracefully if LP0 watermarks
2022 if (level
== 0 && !result
->enable
) {
2023 if (result
->pri_val
> max
->pri
)
2024 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2025 level
, result
->pri_val
, max
->pri
);
2026 if (result
->spr_val
> max
->spr
)
2027 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2028 level
, result
->spr_val
, max
->spr
);
2029 if (result
->cur_val
> max
->cur
)
2030 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2031 level
, result
->cur_val
, max
->cur
);
2033 result
->pri_val
= min_t(uint32_t, result
->pri_val
, max
->pri
);
2034 result
->spr_val
= min_t(uint32_t, result
->spr_val
, max
->spr
);
2035 result
->cur_val
= min_t(uint32_t, result
->cur_val
, max
->cur
);
2036 result
->enable
= true;
2042 static void ilk_compute_wm_level(const struct drm_i915_private
*dev_priv
,
2044 const struct ilk_pipe_wm_parameters
*p
,
2045 struct intel_wm_level
*result
)
2047 uint16_t pri_latency
= dev_priv
->wm
.pri_latency
[level
];
2048 uint16_t spr_latency
= dev_priv
->wm
.spr_latency
[level
];
2049 uint16_t cur_latency
= dev_priv
->wm
.cur_latency
[level
];
2051 /* WM1+ latency values stored in 0.5us units */
2058 result
->pri_val
= ilk_compute_pri_wm(p
, pri_latency
, level
);
2059 result
->spr_val
= ilk_compute_spr_wm(p
, spr_latency
);
2060 result
->cur_val
= ilk_compute_cur_wm(p
, cur_latency
);
2061 result
->fbc_val
= ilk_compute_fbc_wm(p
, result
->pri_val
);
2062 result
->enable
= true;
2066 hsw_compute_linetime_wm(struct drm_device
*dev
, struct drm_crtc
*crtc
)
2068 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2069 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2070 struct drm_display_mode
*mode
= &intel_crtc
->config
->base
.adjusted_mode
;
2071 u32 linetime
, ips_linetime
;
2073 if (!intel_crtc
->active
)
2076 /* The WM are computed with base on how long it takes to fill a single
2077 * row at the given clock rate, multiplied by 8.
2079 linetime
= DIV_ROUND_CLOSEST(mode
->crtc_htotal
* 1000 * 8,
2081 ips_linetime
= DIV_ROUND_CLOSEST(mode
->crtc_htotal
* 1000 * 8,
2082 dev_priv
->cdclk_freq
);
2084 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime
) |
2085 PIPE_WM_LINETIME_TIME(linetime
);
2088 static void intel_read_wm_latency(struct drm_device
*dev
, uint16_t wm
[8])
2090 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2095 int level
, max_level
= ilk_wm_max_level(dev
);
2097 /* read the first set of memory latencies[0:3] */
2098 val
= 0; /* data0 to be programmed to 0 for first set */
2099 mutex_lock(&dev_priv
->rps
.hw_lock
);
2100 ret
= sandybridge_pcode_read(dev_priv
,
2101 GEN9_PCODE_READ_MEM_LATENCY
,
2103 mutex_unlock(&dev_priv
->rps
.hw_lock
);
2106 DRM_ERROR("SKL Mailbox read error = %d\n", ret
);
2110 wm
[0] = val
& GEN9_MEM_LATENCY_LEVEL_MASK
;
2111 wm
[1] = (val
>> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT
) &
2112 GEN9_MEM_LATENCY_LEVEL_MASK
;
2113 wm
[2] = (val
>> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT
) &
2114 GEN9_MEM_LATENCY_LEVEL_MASK
;
2115 wm
[3] = (val
>> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT
) &
2116 GEN9_MEM_LATENCY_LEVEL_MASK
;
2118 /* read the second set of memory latencies[4:7] */
2119 val
= 1; /* data0 to be programmed to 1 for second set */
2120 mutex_lock(&dev_priv
->rps
.hw_lock
);
2121 ret
= sandybridge_pcode_read(dev_priv
,
2122 GEN9_PCODE_READ_MEM_LATENCY
,
2124 mutex_unlock(&dev_priv
->rps
.hw_lock
);
2126 DRM_ERROR("SKL Mailbox read error = %d\n", ret
);
2130 wm
[4] = val
& GEN9_MEM_LATENCY_LEVEL_MASK
;
2131 wm
[5] = (val
>> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT
) &
2132 GEN9_MEM_LATENCY_LEVEL_MASK
;
2133 wm
[6] = (val
>> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT
) &
2134 GEN9_MEM_LATENCY_LEVEL_MASK
;
2135 wm
[7] = (val
>> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT
) &
2136 GEN9_MEM_LATENCY_LEVEL_MASK
;
2139 * WaWmMemoryReadLatency:skl
2141 * punit doesn't take into account the read latency so we need
2142 * to add 2us to the various latency levels we retrieve from
2144 * - W0 is a bit special in that it's the only level that
2145 * can't be disabled if we want to have display working, so
2146 * we always add 2us there.
2147 * - For levels >=1, punit returns 0us latency when they are
2148 * disabled, so we respect that and don't add 2us then
2150 * Additionally, if a level n (n > 1) has a 0us latency, all
2151 * levels m (m >= n) need to be disabled. We make sure to
2152 * sanitize the values out of the punit to satisfy this
2156 for (level
= 1; level
<= max_level
; level
++)
2160 for (i
= level
+ 1; i
<= max_level
; i
++)
2165 } else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2166 uint64_t sskpd
= I915_READ64(MCH_SSKPD
);
2168 wm
[0] = (sskpd
>> 56) & 0xFF;
2170 wm
[0] = sskpd
& 0xF;
2171 wm
[1] = (sskpd
>> 4) & 0xFF;
2172 wm
[2] = (sskpd
>> 12) & 0xFF;
2173 wm
[3] = (sskpd
>> 20) & 0x1FF;
2174 wm
[4] = (sskpd
>> 32) & 0x1FF;
2175 } else if (INTEL_INFO(dev
)->gen
>= 6) {
2176 uint32_t sskpd
= I915_READ(MCH_SSKPD
);
2178 wm
[0] = (sskpd
>> SSKPD_WM0_SHIFT
) & SSKPD_WM_MASK
;
2179 wm
[1] = (sskpd
>> SSKPD_WM1_SHIFT
) & SSKPD_WM_MASK
;
2180 wm
[2] = (sskpd
>> SSKPD_WM2_SHIFT
) & SSKPD_WM_MASK
;
2181 wm
[3] = (sskpd
>> SSKPD_WM3_SHIFT
) & SSKPD_WM_MASK
;
2182 } else if (INTEL_INFO(dev
)->gen
>= 5) {
2183 uint32_t mltr
= I915_READ(MLTR_ILK
);
2185 /* ILK primary LP0 latency is 700 ns */
2187 wm
[1] = (mltr
>> MLTR_WM1_SHIFT
) & ILK_SRLT_MASK
;
2188 wm
[2] = (mltr
>> MLTR_WM2_SHIFT
) & ILK_SRLT_MASK
;
2192 static void intel_fixup_spr_wm_latency(struct drm_device
*dev
, uint16_t wm
[5])
2194 /* ILK sprite LP0 latency is 1300 ns */
2195 if (INTEL_INFO(dev
)->gen
== 5)
2199 static void intel_fixup_cur_wm_latency(struct drm_device
*dev
, uint16_t wm
[5])
2201 /* ILK cursor LP0 latency is 1300 ns */
2202 if (INTEL_INFO(dev
)->gen
== 5)
2205 /* WaDoubleCursorLP3Latency:ivb */
2206 if (IS_IVYBRIDGE(dev
))
2210 int ilk_wm_max_level(const struct drm_device
*dev
)
2212 /* how many WM levels are we expecting */
2213 if (INTEL_INFO(dev
)->gen
>= 9)
2215 else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2217 else if (INTEL_INFO(dev
)->gen
>= 6)
2223 static void intel_print_wm_latency(struct drm_device
*dev
,
2225 const uint16_t wm
[8])
2227 int level
, max_level
= ilk_wm_max_level(dev
);
2229 for (level
= 0; level
<= max_level
; level
++) {
2230 unsigned int latency
= wm
[level
];
2233 DRM_ERROR("%s WM%d latency not provided\n",
2239 * - latencies are in us on gen9.
2240 * - before then, WM1+ latency values are in 0.5us units
2247 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2248 name
, level
, wm
[level
],
2249 latency
/ 10, latency
% 10);
2253 static bool ilk_increase_wm_latency(struct drm_i915_private
*dev_priv
,
2254 uint16_t wm
[5], uint16_t min
)
2256 int level
, max_level
= ilk_wm_max_level(dev_priv
->dev
);
2261 wm
[0] = max(wm
[0], min
);
2262 for (level
= 1; level
<= max_level
; level
++)
2263 wm
[level
] = max_t(uint16_t, wm
[level
], DIV_ROUND_UP(min
, 5));
2268 static void snb_wm_latency_quirk(struct drm_device
*dev
)
2270 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2274 * The BIOS provided WM memory latency values are often
2275 * inadequate for high resolution displays. Adjust them.
2277 changed
= ilk_increase_wm_latency(dev_priv
, dev_priv
->wm
.pri_latency
, 12) |
2278 ilk_increase_wm_latency(dev_priv
, dev_priv
->wm
.spr_latency
, 12) |
2279 ilk_increase_wm_latency(dev_priv
, dev_priv
->wm
.cur_latency
, 12);
2284 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2285 intel_print_wm_latency(dev
, "Primary", dev_priv
->wm
.pri_latency
);
2286 intel_print_wm_latency(dev
, "Sprite", dev_priv
->wm
.spr_latency
);
2287 intel_print_wm_latency(dev
, "Cursor", dev_priv
->wm
.cur_latency
);
2290 static void ilk_setup_wm_latency(struct drm_device
*dev
)
2292 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2294 intel_read_wm_latency(dev
, dev_priv
->wm
.pri_latency
);
2296 memcpy(dev_priv
->wm
.spr_latency
, dev_priv
->wm
.pri_latency
,
2297 sizeof(dev_priv
->wm
.pri_latency
));
2298 memcpy(dev_priv
->wm
.cur_latency
, dev_priv
->wm
.pri_latency
,
2299 sizeof(dev_priv
->wm
.pri_latency
));
2301 intel_fixup_spr_wm_latency(dev
, dev_priv
->wm
.spr_latency
);
2302 intel_fixup_cur_wm_latency(dev
, dev_priv
->wm
.cur_latency
);
2304 intel_print_wm_latency(dev
, "Primary", dev_priv
->wm
.pri_latency
);
2305 intel_print_wm_latency(dev
, "Sprite", dev_priv
->wm
.spr_latency
);
2306 intel_print_wm_latency(dev
, "Cursor", dev_priv
->wm
.cur_latency
);
2309 snb_wm_latency_quirk(dev
);
2312 static void skl_setup_wm_latency(struct drm_device
*dev
)
2314 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2316 intel_read_wm_latency(dev
, dev_priv
->wm
.skl_latency
);
2317 intel_print_wm_latency(dev
, "Gen9 Plane", dev_priv
->wm
.skl_latency
);
2320 static void ilk_compute_wm_parameters(struct drm_crtc
*crtc
,
2321 struct ilk_pipe_wm_parameters
*p
)
2323 struct drm_device
*dev
= crtc
->dev
;
2324 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2325 enum pipe pipe
= intel_crtc
->pipe
;
2326 struct drm_plane
*plane
;
2328 if (!intel_crtc
->active
)
2332 p
->pipe_htotal
= intel_crtc
->config
->base
.adjusted_mode
.crtc_htotal
;
2333 p
->pixel_rate
= ilk_pipe_pixel_rate(intel_crtc
->config
);
2335 if (crtc
->primary
->state
->fb
)
2336 p
->pri
.bytes_per_pixel
=
2337 crtc
->primary
->state
->fb
->bits_per_pixel
/ 8;
2339 p
->pri
.bytes_per_pixel
= 4;
2341 p
->cur
.bytes_per_pixel
= 4;
2343 * TODO: for now, assume primary and cursor planes are always enabled.
2344 * Setting them to false makes the screen flicker.
2346 p
->pri
.enabled
= true;
2347 p
->cur
.enabled
= true;
2349 p
->pri
.horiz_pixels
= intel_crtc
->config
->pipe_src_w
;
2350 p
->cur
.horiz_pixels
= intel_crtc
->base
.cursor
->state
->crtc_w
;
2352 drm_for_each_legacy_plane(plane
, &dev
->mode_config
.plane_list
) {
2353 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
2355 if (intel_plane
->pipe
== pipe
) {
2356 p
->spr
= intel_plane
->wm
;
2362 static void ilk_compute_wm_config(struct drm_device
*dev
,
2363 struct intel_wm_config
*config
)
2365 struct intel_crtc
*intel_crtc
;
2367 /* Compute the currently _active_ config */
2368 for_each_intel_crtc(dev
, intel_crtc
) {
2369 const struct intel_pipe_wm
*wm
= &intel_crtc
->wm
.active
;
2371 if (!wm
->pipe_enabled
)
2374 config
->sprites_enabled
|= wm
->sprites_enabled
;
2375 config
->sprites_scaled
|= wm
->sprites_scaled
;
2376 config
->num_pipes_active
++;
2380 /* Compute new watermarks for the pipe */
2381 static bool intel_compute_pipe_wm(struct drm_crtc
*crtc
,
2382 const struct ilk_pipe_wm_parameters
*params
,
2383 struct intel_pipe_wm
*pipe_wm
)
2385 struct drm_device
*dev
= crtc
->dev
;
2386 const struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2387 int level
, max_level
= ilk_wm_max_level(dev
);
2388 /* LP0 watermark maximums depend on this pipe alone */
2389 struct intel_wm_config config
= {
2390 .num_pipes_active
= 1,
2391 .sprites_enabled
= params
->spr
.enabled
,
2392 .sprites_scaled
= params
->spr
.scaled
,
2394 struct ilk_wm_maximums max
;
2396 pipe_wm
->pipe_enabled
= params
->active
;
2397 pipe_wm
->sprites_enabled
= params
->spr
.enabled
;
2398 pipe_wm
->sprites_scaled
= params
->spr
.scaled
;
2400 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2401 if (INTEL_INFO(dev
)->gen
<= 6 && params
->spr
.enabled
)
2404 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2405 if (params
->spr
.scaled
)
2408 ilk_compute_wm_level(dev_priv
, 0, params
, &pipe_wm
->wm
[0]);
2410 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2411 pipe_wm
->linetime
= hsw_compute_linetime_wm(dev
, crtc
);
2413 /* LP0 watermarks always use 1/2 DDB partitioning */
2414 ilk_compute_wm_maximums(dev
, 0, &config
, INTEL_DDB_PART_1_2
, &max
);
2416 /* At least LP0 must be valid */
2417 if (!ilk_validate_wm_level(0, &max
, &pipe_wm
->wm
[0]))
2420 ilk_compute_wm_reg_maximums(dev
, 1, &max
);
2422 for (level
= 1; level
<= max_level
; level
++) {
2423 struct intel_wm_level wm
= {};
2425 ilk_compute_wm_level(dev_priv
, level
, params
, &wm
);
2428 * Disable any watermark level that exceeds the
2429 * register maximums since such watermarks are
2432 if (!ilk_validate_wm_level(level
, &max
, &wm
))
2435 pipe_wm
->wm
[level
] = wm
;
2442 * Merge the watermarks from all active pipes for a specific level.
2444 static void ilk_merge_wm_level(struct drm_device
*dev
,
2446 struct intel_wm_level
*ret_wm
)
2448 const struct intel_crtc
*intel_crtc
;
2450 ret_wm
->enable
= true;
2452 for_each_intel_crtc(dev
, intel_crtc
) {
2453 const struct intel_pipe_wm
*active
= &intel_crtc
->wm
.active
;
2454 const struct intel_wm_level
*wm
= &active
->wm
[level
];
2456 if (!active
->pipe_enabled
)
2460 * The watermark values may have been used in the past,
2461 * so we must maintain them in the registers for some
2462 * time even if the level is now disabled.
2465 ret_wm
->enable
= false;
2467 ret_wm
->pri_val
= max(ret_wm
->pri_val
, wm
->pri_val
);
2468 ret_wm
->spr_val
= max(ret_wm
->spr_val
, wm
->spr_val
);
2469 ret_wm
->cur_val
= max(ret_wm
->cur_val
, wm
->cur_val
);
2470 ret_wm
->fbc_val
= max(ret_wm
->fbc_val
, wm
->fbc_val
);
2475 * Merge all low power watermarks for all active pipes.
2477 static void ilk_wm_merge(struct drm_device
*dev
,
2478 const struct intel_wm_config
*config
,
2479 const struct ilk_wm_maximums
*max
,
2480 struct intel_pipe_wm
*merged
)
2482 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2483 int level
, max_level
= ilk_wm_max_level(dev
);
2484 int last_enabled_level
= max_level
;
2486 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2487 if ((INTEL_INFO(dev
)->gen
<= 6 || IS_IVYBRIDGE(dev
)) &&
2488 config
->num_pipes_active
> 1)
2491 /* ILK: FBC WM must be disabled always */
2492 merged
->fbc_wm_enabled
= INTEL_INFO(dev
)->gen
>= 6;
2494 /* merge each WM1+ level */
2495 for (level
= 1; level
<= max_level
; level
++) {
2496 struct intel_wm_level
*wm
= &merged
->wm
[level
];
2498 ilk_merge_wm_level(dev
, level
, wm
);
2500 if (level
> last_enabled_level
)
2502 else if (!ilk_validate_wm_level(level
, max
, wm
))
2503 /* make sure all following levels get disabled */
2504 last_enabled_level
= level
- 1;
2507 * The spec says it is preferred to disable
2508 * FBC WMs instead of disabling a WM level.
2510 if (wm
->fbc_val
> max
->fbc
) {
2512 merged
->fbc_wm_enabled
= false;
2517 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2519 * FIXME this is racy. FBC might get enabled later.
2520 * What we should check here is whether FBC can be
2521 * enabled sometime later.
2523 if (IS_GEN5(dev
) && !merged
->fbc_wm_enabled
&&
2524 intel_fbc_enabled(dev_priv
)) {
2525 for (level
= 2; level
<= max_level
; level
++) {
2526 struct intel_wm_level
*wm
= &merged
->wm
[level
];
2533 static int ilk_wm_lp_to_level(int wm_lp
, const struct intel_pipe_wm
*pipe_wm
)
2535 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2536 return wm_lp
+ (wm_lp
>= 2 && pipe_wm
->wm
[4].enable
);
2539 /* The value we need to program into the WM_LPx latency field */
2540 static unsigned int ilk_wm_lp_latency(struct drm_device
*dev
, int level
)
2542 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2544 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2547 return dev_priv
->wm
.pri_latency
[level
];
2550 static void ilk_compute_wm_results(struct drm_device
*dev
,
2551 const struct intel_pipe_wm
*merged
,
2552 enum intel_ddb_partitioning partitioning
,
2553 struct ilk_wm_values
*results
)
2555 struct intel_crtc
*intel_crtc
;
2558 results
->enable_fbc_wm
= merged
->fbc_wm_enabled
;
2559 results
->partitioning
= partitioning
;
2561 /* LP1+ register values */
2562 for (wm_lp
= 1; wm_lp
<= 3; wm_lp
++) {
2563 const struct intel_wm_level
*r
;
2565 level
= ilk_wm_lp_to_level(wm_lp
, merged
);
2567 r
= &merged
->wm
[level
];
2570 * Maintain the watermark values even if the level is
2571 * disabled. Doing otherwise could cause underruns.
2573 results
->wm_lp
[wm_lp
- 1] =
2574 (ilk_wm_lp_latency(dev
, level
) << WM1_LP_LATENCY_SHIFT
) |
2575 (r
->pri_val
<< WM1_LP_SR_SHIFT
) |
2579 results
->wm_lp
[wm_lp
- 1] |= WM1_LP_SR_EN
;
2581 if (INTEL_INFO(dev
)->gen
>= 8)
2582 results
->wm_lp
[wm_lp
- 1] |=
2583 r
->fbc_val
<< WM1_LP_FBC_SHIFT_BDW
;
2585 results
->wm_lp
[wm_lp
- 1] |=
2586 r
->fbc_val
<< WM1_LP_FBC_SHIFT
;
2589 * Always set WM1S_LP_EN when spr_val != 0, even if the
2590 * level is disabled. Doing otherwise could cause underruns.
2592 if (INTEL_INFO(dev
)->gen
<= 6 && r
->spr_val
) {
2593 WARN_ON(wm_lp
!= 1);
2594 results
->wm_lp_spr
[wm_lp
- 1] = WM1S_LP_EN
| r
->spr_val
;
2596 results
->wm_lp_spr
[wm_lp
- 1] = r
->spr_val
;
2599 /* LP0 register values */
2600 for_each_intel_crtc(dev
, intel_crtc
) {
2601 enum pipe pipe
= intel_crtc
->pipe
;
2602 const struct intel_wm_level
*r
=
2603 &intel_crtc
->wm
.active
.wm
[0];
2605 if (WARN_ON(!r
->enable
))
2608 results
->wm_linetime
[pipe
] = intel_crtc
->wm
.active
.linetime
;
2610 results
->wm_pipe
[pipe
] =
2611 (r
->pri_val
<< WM0_PIPE_PLANE_SHIFT
) |
2612 (r
->spr_val
<< WM0_PIPE_SPRITE_SHIFT
) |
2617 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2618 * case both are at the same level. Prefer r1 in case they're the same. */
2619 static struct intel_pipe_wm
*ilk_find_best_result(struct drm_device
*dev
,
2620 struct intel_pipe_wm
*r1
,
2621 struct intel_pipe_wm
*r2
)
2623 int level
, max_level
= ilk_wm_max_level(dev
);
2624 int level1
= 0, level2
= 0;
2626 for (level
= 1; level
<= max_level
; level
++) {
2627 if (r1
->wm
[level
].enable
)
2629 if (r2
->wm
[level
].enable
)
2633 if (level1
== level2
) {
2634 if (r2
->fbc_wm_enabled
&& !r1
->fbc_wm_enabled
)
2638 } else if (level1
> level2
) {
2645 /* dirty bits used to track which watermarks need changes */
2646 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2647 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2648 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2649 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2650 #define WM_DIRTY_FBC (1 << 24)
2651 #define WM_DIRTY_DDB (1 << 25)
2653 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private
*dev_priv
,
2654 const struct ilk_wm_values
*old
,
2655 const struct ilk_wm_values
*new)
2657 unsigned int dirty
= 0;
2661 for_each_pipe(dev_priv
, pipe
) {
2662 if (old
->wm_linetime
[pipe
] != new->wm_linetime
[pipe
]) {
2663 dirty
|= WM_DIRTY_LINETIME(pipe
);
2664 /* Must disable LP1+ watermarks too */
2665 dirty
|= WM_DIRTY_LP_ALL
;
2668 if (old
->wm_pipe
[pipe
] != new->wm_pipe
[pipe
]) {
2669 dirty
|= WM_DIRTY_PIPE(pipe
);
2670 /* Must disable LP1+ watermarks too */
2671 dirty
|= WM_DIRTY_LP_ALL
;
2675 if (old
->enable_fbc_wm
!= new->enable_fbc_wm
) {
2676 dirty
|= WM_DIRTY_FBC
;
2677 /* Must disable LP1+ watermarks too */
2678 dirty
|= WM_DIRTY_LP_ALL
;
2681 if (old
->partitioning
!= new->partitioning
) {
2682 dirty
|= WM_DIRTY_DDB
;
2683 /* Must disable LP1+ watermarks too */
2684 dirty
|= WM_DIRTY_LP_ALL
;
2687 /* LP1+ watermarks already deemed dirty, no need to continue */
2688 if (dirty
& WM_DIRTY_LP_ALL
)
2691 /* Find the lowest numbered LP1+ watermark in need of an update... */
2692 for (wm_lp
= 1; wm_lp
<= 3; wm_lp
++) {
2693 if (old
->wm_lp
[wm_lp
- 1] != new->wm_lp
[wm_lp
- 1] ||
2694 old
->wm_lp_spr
[wm_lp
- 1] != new->wm_lp_spr
[wm_lp
- 1])
2698 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2699 for (; wm_lp
<= 3; wm_lp
++)
2700 dirty
|= WM_DIRTY_LP(wm_lp
);
2705 static bool _ilk_disable_lp_wm(struct drm_i915_private
*dev_priv
,
2708 struct ilk_wm_values
*previous
= &dev_priv
->wm
.hw
;
2709 bool changed
= false;
2711 if (dirty
& WM_DIRTY_LP(3) && previous
->wm_lp
[2] & WM1_LP_SR_EN
) {
2712 previous
->wm_lp
[2] &= ~WM1_LP_SR_EN
;
2713 I915_WRITE(WM3_LP_ILK
, previous
->wm_lp
[2]);
2716 if (dirty
& WM_DIRTY_LP(2) && previous
->wm_lp
[1] & WM1_LP_SR_EN
) {
2717 previous
->wm_lp
[1] &= ~WM1_LP_SR_EN
;
2718 I915_WRITE(WM2_LP_ILK
, previous
->wm_lp
[1]);
2721 if (dirty
& WM_DIRTY_LP(1) && previous
->wm_lp
[0] & WM1_LP_SR_EN
) {
2722 previous
->wm_lp
[0] &= ~WM1_LP_SR_EN
;
2723 I915_WRITE(WM1_LP_ILK
, previous
->wm_lp
[0]);
2728 * Don't touch WM1S_LP_EN here.
2729 * Doing so could cause underruns.
2736 * The spec says we shouldn't write when we don't need, because every write
2737 * causes WMs to be re-evaluated, expending some power.
2739 static void ilk_write_wm_values(struct drm_i915_private
*dev_priv
,
2740 struct ilk_wm_values
*results
)
2742 struct drm_device
*dev
= dev_priv
->dev
;
2743 struct ilk_wm_values
*previous
= &dev_priv
->wm
.hw
;
2747 dirty
= ilk_compute_wm_dirty(dev_priv
, previous
, results
);
2751 _ilk_disable_lp_wm(dev_priv
, dirty
);
2753 if (dirty
& WM_DIRTY_PIPE(PIPE_A
))
2754 I915_WRITE(WM0_PIPEA_ILK
, results
->wm_pipe
[0]);
2755 if (dirty
& WM_DIRTY_PIPE(PIPE_B
))
2756 I915_WRITE(WM0_PIPEB_ILK
, results
->wm_pipe
[1]);
2757 if (dirty
& WM_DIRTY_PIPE(PIPE_C
))
2758 I915_WRITE(WM0_PIPEC_IVB
, results
->wm_pipe
[2]);
2760 if (dirty
& WM_DIRTY_LINETIME(PIPE_A
))
2761 I915_WRITE(PIPE_WM_LINETIME(PIPE_A
), results
->wm_linetime
[0]);
2762 if (dirty
& WM_DIRTY_LINETIME(PIPE_B
))
2763 I915_WRITE(PIPE_WM_LINETIME(PIPE_B
), results
->wm_linetime
[1]);
2764 if (dirty
& WM_DIRTY_LINETIME(PIPE_C
))
2765 I915_WRITE(PIPE_WM_LINETIME(PIPE_C
), results
->wm_linetime
[2]);
2767 if (dirty
& WM_DIRTY_DDB
) {
2768 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2769 val
= I915_READ(WM_MISC
);
2770 if (results
->partitioning
== INTEL_DDB_PART_1_2
)
2771 val
&= ~WM_MISC_DATA_PARTITION_5_6
;
2773 val
|= WM_MISC_DATA_PARTITION_5_6
;
2774 I915_WRITE(WM_MISC
, val
);
2776 val
= I915_READ(DISP_ARB_CTL2
);
2777 if (results
->partitioning
== INTEL_DDB_PART_1_2
)
2778 val
&= ~DISP_DATA_PARTITION_5_6
;
2780 val
|= DISP_DATA_PARTITION_5_6
;
2781 I915_WRITE(DISP_ARB_CTL2
, val
);
2785 if (dirty
& WM_DIRTY_FBC
) {
2786 val
= I915_READ(DISP_ARB_CTL
);
2787 if (results
->enable_fbc_wm
)
2788 val
&= ~DISP_FBC_WM_DIS
;
2790 val
|= DISP_FBC_WM_DIS
;
2791 I915_WRITE(DISP_ARB_CTL
, val
);
2794 if (dirty
& WM_DIRTY_LP(1) &&
2795 previous
->wm_lp_spr
[0] != results
->wm_lp_spr
[0])
2796 I915_WRITE(WM1S_LP_ILK
, results
->wm_lp_spr
[0]);
2798 if (INTEL_INFO(dev
)->gen
>= 7) {
2799 if (dirty
& WM_DIRTY_LP(2) && previous
->wm_lp_spr
[1] != results
->wm_lp_spr
[1])
2800 I915_WRITE(WM2S_LP_IVB
, results
->wm_lp_spr
[1]);
2801 if (dirty
& WM_DIRTY_LP(3) && previous
->wm_lp_spr
[2] != results
->wm_lp_spr
[2])
2802 I915_WRITE(WM3S_LP_IVB
, results
->wm_lp_spr
[2]);
2805 if (dirty
& WM_DIRTY_LP(1) && previous
->wm_lp
[0] != results
->wm_lp
[0])
2806 I915_WRITE(WM1_LP_ILK
, results
->wm_lp
[0]);
2807 if (dirty
& WM_DIRTY_LP(2) && previous
->wm_lp
[1] != results
->wm_lp
[1])
2808 I915_WRITE(WM2_LP_ILK
, results
->wm_lp
[1]);
2809 if (dirty
& WM_DIRTY_LP(3) && previous
->wm_lp
[2] != results
->wm_lp
[2])
2810 I915_WRITE(WM3_LP_ILK
, results
->wm_lp
[2]);
2812 dev_priv
->wm
.hw
= *results
;
2815 static bool ilk_disable_lp_wm(struct drm_device
*dev
)
2817 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2819 return _ilk_disable_lp_wm(dev_priv
, WM_DIRTY_LP_ALL
);
2823 * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2824 * different active planes.
2827 #define SKL_DDB_SIZE 896 /* in blocks */
2828 #define BXT_DDB_SIZE 512
2831 skl_ddb_get_pipe_allocation_limits(struct drm_device
*dev
,
2832 struct drm_crtc
*for_crtc
,
2833 const struct intel_wm_config
*config
,
2834 const struct skl_pipe_wm_parameters
*params
,
2835 struct skl_ddb_entry
*alloc
/* out */)
2837 struct drm_crtc
*crtc
;
2838 unsigned int pipe_size
, ddb_size
;
2839 int nth_active_pipe
;
2841 if (!params
->active
) {
2847 if (IS_BROXTON(dev
))
2848 ddb_size
= BXT_DDB_SIZE
;
2850 ddb_size
= SKL_DDB_SIZE
;
2852 ddb_size
-= 4; /* 4 blocks for bypass path allocation */
2854 nth_active_pipe
= 0;
2855 for_each_crtc(dev
, crtc
) {
2856 if (!to_intel_crtc(crtc
)->active
)
2859 if (crtc
== for_crtc
)
2865 pipe_size
= ddb_size
/ config
->num_pipes_active
;
2866 alloc
->start
= nth_active_pipe
* ddb_size
/ config
->num_pipes_active
;
2867 alloc
->end
= alloc
->start
+ pipe_size
;
2870 static unsigned int skl_cursor_allocation(const struct intel_wm_config
*config
)
2872 if (config
->num_pipes_active
== 1)
2878 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry
*entry
, u32 reg
)
2880 entry
->start
= reg
& 0x3ff;
2881 entry
->end
= (reg
>> 16) & 0x3ff;
2886 void skl_ddb_get_hw_state(struct drm_i915_private
*dev_priv
,
2887 struct skl_ddb_allocation
*ddb
/* out */)
2893 for_each_pipe(dev_priv
, pipe
) {
2894 for_each_plane(dev_priv
, pipe
, plane
) {
2895 val
= I915_READ(PLANE_BUF_CFG(pipe
, plane
));
2896 skl_ddb_entry_init_from_hw(&ddb
->plane
[pipe
][plane
],
2900 val
= I915_READ(CUR_BUF_CFG(pipe
));
2901 skl_ddb_entry_init_from_hw(&ddb
->cursor
[pipe
], val
);
2906 skl_plane_relative_data_rate(const struct intel_plane_wm_parameters
*p
, int y
)
2909 /* for planar format */
2910 if (p
->y_bytes_per_pixel
) {
2911 if (y
) /* y-plane data rate */
2912 return p
->horiz_pixels
* p
->vert_pixels
* p
->y_bytes_per_pixel
;
2913 else /* uv-plane data rate */
2914 return (p
->horiz_pixels
/2) * (p
->vert_pixels
/2) * p
->bytes_per_pixel
;
2917 /* for packed formats */
2918 return p
->horiz_pixels
* p
->vert_pixels
* p
->bytes_per_pixel
;
2922 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
2923 * a 8192x4096@32bpp framebuffer:
2924 * 3 * 4096 * 8192 * 4 < 2^32
2927 skl_get_total_relative_data_rate(struct intel_crtc
*intel_crtc
,
2928 const struct skl_pipe_wm_parameters
*params
)
2930 unsigned int total_data_rate
= 0;
2933 for (plane
= 0; plane
< intel_num_planes(intel_crtc
); plane
++) {
2934 const struct intel_plane_wm_parameters
*p
;
2936 p
= ¶ms
->plane
[plane
];
2940 total_data_rate
+= skl_plane_relative_data_rate(p
, 0); /* packed/uv */
2941 if (p
->y_bytes_per_pixel
) {
2942 total_data_rate
+= skl_plane_relative_data_rate(p
, 1); /* y-plane */
2946 return total_data_rate
;
2950 skl_allocate_pipe_ddb(struct drm_crtc
*crtc
,
2951 const struct intel_wm_config
*config
,
2952 const struct skl_pipe_wm_parameters
*params
,
2953 struct skl_ddb_allocation
*ddb
/* out */)
2955 struct drm_device
*dev
= crtc
->dev
;
2956 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2957 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2958 enum pipe pipe
= intel_crtc
->pipe
;
2959 struct skl_ddb_entry
*alloc
= &ddb
->pipe
[pipe
];
2960 uint16_t alloc_size
, start
, cursor_blocks
;
2961 uint16_t minimum
[I915_MAX_PLANES
];
2962 uint16_t y_minimum
[I915_MAX_PLANES
];
2963 unsigned int total_data_rate
;
2966 skl_ddb_get_pipe_allocation_limits(dev
, crtc
, config
, params
, alloc
);
2967 alloc_size
= skl_ddb_entry_size(alloc
);
2968 if (alloc_size
== 0) {
2969 memset(ddb
->plane
[pipe
], 0, sizeof(ddb
->plane
[pipe
]));
2970 memset(&ddb
->cursor
[pipe
], 0, sizeof(ddb
->cursor
[pipe
]));
2974 cursor_blocks
= skl_cursor_allocation(config
);
2975 ddb
->cursor
[pipe
].start
= alloc
->end
- cursor_blocks
;
2976 ddb
->cursor
[pipe
].end
= alloc
->end
;
2978 alloc_size
-= cursor_blocks
;
2979 alloc
->end
-= cursor_blocks
;
2981 /* 1. Allocate the mininum required blocks for each active plane */
2982 for_each_plane(dev_priv
, pipe
, plane
) {
2983 const struct intel_plane_wm_parameters
*p
;
2985 p
= ¶ms
->plane
[plane
];
2990 alloc_size
-= minimum
[plane
];
2991 y_minimum
[plane
] = p
->y_bytes_per_pixel
? 8 : 0;
2992 alloc_size
-= y_minimum
[plane
];
2996 * 2. Distribute the remaining space in proportion to the amount of
2997 * data each plane needs to fetch from memory.
2999 * FIXME: we may not allocate every single block here.
3001 total_data_rate
= skl_get_total_relative_data_rate(intel_crtc
, params
);
3003 start
= alloc
->start
;
3004 for (plane
= 0; plane
< intel_num_planes(intel_crtc
); plane
++) {
3005 const struct intel_plane_wm_parameters
*p
;
3006 unsigned int data_rate
, y_data_rate
;
3007 uint16_t plane_blocks
, y_plane_blocks
= 0;
3009 p
= ¶ms
->plane
[plane
];
3013 data_rate
= skl_plane_relative_data_rate(p
, 0);
3016 * allocation for (packed formats) or (uv-plane part of planar format):
3017 * promote the expression to 64 bits to avoid overflowing, the
3018 * result is < available as data_rate / total_data_rate < 1
3020 plane_blocks
= minimum
[plane
];
3021 plane_blocks
+= div_u64((uint64_t)alloc_size
* data_rate
,
3024 ddb
->plane
[pipe
][plane
].start
= start
;
3025 ddb
->plane
[pipe
][plane
].end
= start
+ plane_blocks
;
3027 start
+= plane_blocks
;
3030 * allocation for y_plane part of planar format:
3032 if (p
->y_bytes_per_pixel
) {
3033 y_data_rate
= skl_plane_relative_data_rate(p
, 1);
3034 y_plane_blocks
= y_minimum
[plane
];
3035 y_plane_blocks
+= div_u64((uint64_t)alloc_size
* y_data_rate
,
3038 ddb
->y_plane
[pipe
][plane
].start
= start
;
3039 ddb
->y_plane
[pipe
][plane
].end
= start
+ y_plane_blocks
;
3041 start
+= y_plane_blocks
;
3048 static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state
*config
)
3050 /* TODO: Take into account the scalers once we support them */
3051 return config
->base
.adjusted_mode
.crtc_clock
;
3055 * The max latency should be 257 (max the punit can code is 255 and we add 2us
3056 * for the read latency) and bytes_per_pixel should always be <= 8, so that
3057 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3058 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3060 static uint32_t skl_wm_method1(uint32_t pixel_rate
, uint8_t bytes_per_pixel
,
3063 uint32_t wm_intermediate_val
, ret
;
3068 wm_intermediate_val
= latency
* pixel_rate
* bytes_per_pixel
/ 512;
3069 ret
= DIV_ROUND_UP(wm_intermediate_val
, 1000);
3074 static uint32_t skl_wm_method2(uint32_t pixel_rate
, uint32_t pipe_htotal
,
3075 uint32_t horiz_pixels
, uint8_t bytes_per_pixel
,
3076 uint64_t tiling
, uint32_t latency
)
3079 uint32_t plane_bytes_per_line
, plane_blocks_per_line
;
3080 uint32_t wm_intermediate_val
;
3085 plane_bytes_per_line
= horiz_pixels
* bytes_per_pixel
;
3087 if (tiling
== I915_FORMAT_MOD_Y_TILED
||
3088 tiling
== I915_FORMAT_MOD_Yf_TILED
) {
3089 plane_bytes_per_line
*= 4;
3090 plane_blocks_per_line
= DIV_ROUND_UP(plane_bytes_per_line
, 512);
3091 plane_blocks_per_line
/= 4;
3093 plane_blocks_per_line
= DIV_ROUND_UP(plane_bytes_per_line
, 512);
3096 wm_intermediate_val
= latency
* pixel_rate
;
3097 ret
= DIV_ROUND_UP(wm_intermediate_val
, pipe_htotal
* 1000) *
3098 plane_blocks_per_line
;
3103 static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation
*new_ddb
,
3104 const struct intel_crtc
*intel_crtc
)
3106 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3107 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3108 const struct skl_ddb_allocation
*cur_ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
3109 enum pipe pipe
= intel_crtc
->pipe
;
3111 if (memcmp(new_ddb
->plane
[pipe
], cur_ddb
->plane
[pipe
],
3112 sizeof(new_ddb
->plane
[pipe
])))
3115 if (memcmp(&new_ddb
->cursor
[pipe
], &cur_ddb
->cursor
[pipe
],
3116 sizeof(new_ddb
->cursor
[pipe
])))
3122 static void skl_compute_wm_global_parameters(struct drm_device
*dev
,
3123 struct intel_wm_config
*config
)
3125 struct drm_crtc
*crtc
;
3126 struct drm_plane
*plane
;
3128 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
)
3129 config
->num_pipes_active
+= to_intel_crtc(crtc
)->active
;
3131 /* FIXME: I don't think we need those two global parameters on SKL */
3132 list_for_each_entry(plane
, &dev
->mode_config
.plane_list
, head
) {
3133 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
3135 config
->sprites_enabled
|= intel_plane
->wm
.enabled
;
3136 config
->sprites_scaled
|= intel_plane
->wm
.scaled
;
3140 static void skl_compute_wm_pipe_parameters(struct drm_crtc
*crtc
,
3141 struct skl_pipe_wm_parameters
*p
)
3143 struct drm_device
*dev
= crtc
->dev
;
3144 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3145 enum pipe pipe
= intel_crtc
->pipe
;
3146 struct drm_plane
*plane
;
3147 struct drm_framebuffer
*fb
;
3148 int i
= 1; /* Index for sprite planes start */
3150 p
->active
= intel_crtc
->active
;
3152 p
->pipe_htotal
= intel_crtc
->config
->base
.adjusted_mode
.crtc_htotal
;
3153 p
->pixel_rate
= skl_pipe_pixel_rate(intel_crtc
->config
);
3155 fb
= crtc
->primary
->state
->fb
;
3156 /* For planar: Bpp is for uv plane, y_Bpp is for y plane */
3158 p
->plane
[0].enabled
= true;
3159 p
->plane
[0].bytes_per_pixel
= fb
->pixel_format
== DRM_FORMAT_NV12
?
3160 drm_format_plane_cpp(fb
->pixel_format
, 1) : fb
->bits_per_pixel
/ 8;
3161 p
->plane
[0].y_bytes_per_pixel
= fb
->pixel_format
== DRM_FORMAT_NV12
?
3162 drm_format_plane_cpp(fb
->pixel_format
, 0) : 0;
3163 p
->plane
[0].tiling
= fb
->modifier
[0];
3165 p
->plane
[0].enabled
= false;
3166 p
->plane
[0].bytes_per_pixel
= 0;
3167 p
->plane
[0].y_bytes_per_pixel
= 0;
3168 p
->plane
[0].tiling
= DRM_FORMAT_MOD_NONE
;
3170 p
->plane
[0].horiz_pixels
= intel_crtc
->config
->pipe_src_w
;
3171 p
->plane
[0].vert_pixels
= intel_crtc
->config
->pipe_src_h
;
3172 p
->plane
[0].rotation
= crtc
->primary
->state
->rotation
;
3174 fb
= crtc
->cursor
->state
->fb
;
3175 p
->cursor
.y_bytes_per_pixel
= 0;
3177 p
->cursor
.enabled
= true;
3178 p
->cursor
.bytes_per_pixel
= fb
->bits_per_pixel
/ 8;
3179 p
->cursor
.horiz_pixels
= crtc
->cursor
->state
->crtc_w
;
3180 p
->cursor
.vert_pixels
= crtc
->cursor
->state
->crtc_h
;
3182 p
->cursor
.enabled
= false;
3183 p
->cursor
.bytes_per_pixel
= 0;
3184 p
->cursor
.horiz_pixels
= 64;
3185 p
->cursor
.vert_pixels
= 64;
3189 list_for_each_entry(plane
, &dev
->mode_config
.plane_list
, head
) {
3190 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
3192 if (intel_plane
->pipe
== pipe
&&
3193 plane
->type
== DRM_PLANE_TYPE_OVERLAY
)
3194 p
->plane
[i
++] = intel_plane
->wm
;
3198 static bool skl_compute_plane_wm(const struct drm_i915_private
*dev_priv
,
3199 struct skl_pipe_wm_parameters
*p
,
3200 struct intel_plane_wm_parameters
*p_params
,
3201 uint16_t ddb_allocation
,
3203 uint16_t *out_blocks
, /* out */
3204 uint8_t *out_lines
/* out */)
3206 uint32_t latency
= dev_priv
->wm
.skl_latency
[level
];
3207 uint32_t method1
, method2
;
3208 uint32_t plane_bytes_per_line
, plane_blocks_per_line
;
3209 uint32_t res_blocks
, res_lines
;
3210 uint32_t selected_result
;
3211 uint8_t bytes_per_pixel
;
3213 if (latency
== 0 || !p
->active
|| !p_params
->enabled
)
3216 bytes_per_pixel
= p_params
->y_bytes_per_pixel
?
3217 p_params
->y_bytes_per_pixel
:
3218 p_params
->bytes_per_pixel
;
3219 method1
= skl_wm_method1(p
->pixel_rate
,
3222 method2
= skl_wm_method2(p
->pixel_rate
,
3224 p_params
->horiz_pixels
,
3229 plane_bytes_per_line
= p_params
->horiz_pixels
* bytes_per_pixel
;
3230 plane_blocks_per_line
= DIV_ROUND_UP(plane_bytes_per_line
, 512);
3232 if (p_params
->tiling
== I915_FORMAT_MOD_Y_TILED
||
3233 p_params
->tiling
== I915_FORMAT_MOD_Yf_TILED
) {
3234 uint32_t min_scanlines
= 4;
3235 uint32_t y_tile_minimum
;
3236 if (intel_rotation_90_or_270(p_params
->rotation
)) {
3237 switch (p_params
->bytes_per_pixel
) {
3245 WARN(1, "Unsupported pixel depth for rotation");
3248 y_tile_minimum
= plane_blocks_per_line
* min_scanlines
;
3249 selected_result
= max(method2
, y_tile_minimum
);
3251 if ((ddb_allocation
/ plane_blocks_per_line
) >= 1)
3252 selected_result
= min(method1
, method2
);
3254 selected_result
= method1
;
3257 res_blocks
= selected_result
+ 1;
3258 res_lines
= DIV_ROUND_UP(selected_result
, plane_blocks_per_line
);
3260 if (level
>= 1 && level
<= 7) {
3261 if (p_params
->tiling
== I915_FORMAT_MOD_Y_TILED
||
3262 p_params
->tiling
== I915_FORMAT_MOD_Yf_TILED
)
3268 if (res_blocks
>= ddb_allocation
|| res_lines
> 31)
3271 *out_blocks
= res_blocks
;
3272 *out_lines
= res_lines
;
3277 static void skl_compute_wm_level(const struct drm_i915_private
*dev_priv
,
3278 struct skl_ddb_allocation
*ddb
,
3279 struct skl_pipe_wm_parameters
*p
,
3283 struct skl_wm_level
*result
)
3285 uint16_t ddb_blocks
;
3288 for (i
= 0; i
< num_planes
; i
++) {
3289 ddb_blocks
= skl_ddb_entry_size(&ddb
->plane
[pipe
][i
]);
3291 result
->plane_en
[i
] = skl_compute_plane_wm(dev_priv
,
3295 &result
->plane_res_b
[i
],
3296 &result
->plane_res_l
[i
]);
3299 ddb_blocks
= skl_ddb_entry_size(&ddb
->cursor
[pipe
]);
3300 result
->cursor_en
= skl_compute_plane_wm(dev_priv
, p
, &p
->cursor
,
3302 &result
->cursor_res_b
,
3303 &result
->cursor_res_l
);
3307 skl_compute_linetime_wm(struct drm_crtc
*crtc
, struct skl_pipe_wm_parameters
*p
)
3309 if (!to_intel_crtc(crtc
)->active
)
3312 return DIV_ROUND_UP(8 * p
->pipe_htotal
* 1000, p
->pixel_rate
);
3316 static void skl_compute_transition_wm(struct drm_crtc
*crtc
,
3317 struct skl_pipe_wm_parameters
*params
,
3318 struct skl_wm_level
*trans_wm
/* out */)
3320 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3323 if (!params
->active
)
3326 /* Until we know more, just disable transition WMs */
3327 for (i
= 0; i
< intel_num_planes(intel_crtc
); i
++)
3328 trans_wm
->plane_en
[i
] = false;
3329 trans_wm
->cursor_en
= false;
3332 static void skl_compute_pipe_wm(struct drm_crtc
*crtc
,
3333 struct skl_ddb_allocation
*ddb
,
3334 struct skl_pipe_wm_parameters
*params
,
3335 struct skl_pipe_wm
*pipe_wm
)
3337 struct drm_device
*dev
= crtc
->dev
;
3338 const struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3339 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3340 int level
, max_level
= ilk_wm_max_level(dev
);
3342 for (level
= 0; level
<= max_level
; level
++) {
3343 skl_compute_wm_level(dev_priv
, ddb
, params
, intel_crtc
->pipe
,
3344 level
, intel_num_planes(intel_crtc
),
3345 &pipe_wm
->wm
[level
]);
3347 pipe_wm
->linetime
= skl_compute_linetime_wm(crtc
, params
);
3349 skl_compute_transition_wm(crtc
, params
, &pipe_wm
->trans_wm
);
3352 static void skl_compute_wm_results(struct drm_device
*dev
,
3353 struct skl_pipe_wm_parameters
*p
,
3354 struct skl_pipe_wm
*p_wm
,
3355 struct skl_wm_values
*r
,
3356 struct intel_crtc
*intel_crtc
)
3358 int level
, max_level
= ilk_wm_max_level(dev
);
3359 enum pipe pipe
= intel_crtc
->pipe
;
3363 for (level
= 0; level
<= max_level
; level
++) {
3364 for (i
= 0; i
< intel_num_planes(intel_crtc
); i
++) {
3367 temp
|= p_wm
->wm
[level
].plane_res_l
[i
] <<
3368 PLANE_WM_LINES_SHIFT
;
3369 temp
|= p_wm
->wm
[level
].plane_res_b
[i
];
3370 if (p_wm
->wm
[level
].plane_en
[i
])
3371 temp
|= PLANE_WM_EN
;
3373 r
->plane
[pipe
][i
][level
] = temp
;
3378 temp
|= p_wm
->wm
[level
].cursor_res_l
<< PLANE_WM_LINES_SHIFT
;
3379 temp
|= p_wm
->wm
[level
].cursor_res_b
;
3381 if (p_wm
->wm
[level
].cursor_en
)
3382 temp
|= PLANE_WM_EN
;
3384 r
->cursor
[pipe
][level
] = temp
;
3388 /* transition WMs */
3389 for (i
= 0; i
< intel_num_planes(intel_crtc
); i
++) {
3391 temp
|= p_wm
->trans_wm
.plane_res_l
[i
] << PLANE_WM_LINES_SHIFT
;
3392 temp
|= p_wm
->trans_wm
.plane_res_b
[i
];
3393 if (p_wm
->trans_wm
.plane_en
[i
])
3394 temp
|= PLANE_WM_EN
;
3396 r
->plane_trans
[pipe
][i
] = temp
;
3400 temp
|= p_wm
->trans_wm
.cursor_res_l
<< PLANE_WM_LINES_SHIFT
;
3401 temp
|= p_wm
->trans_wm
.cursor_res_b
;
3402 if (p_wm
->trans_wm
.cursor_en
)
3403 temp
|= PLANE_WM_EN
;
3405 r
->cursor_trans
[pipe
] = temp
;
3407 r
->wm_linetime
[pipe
] = p_wm
->linetime
;
3410 static void skl_ddb_entry_write(struct drm_i915_private
*dev_priv
, uint32_t reg
,
3411 const struct skl_ddb_entry
*entry
)
3414 I915_WRITE(reg
, (entry
->end
- 1) << 16 | entry
->start
);
3419 static void skl_write_wm_values(struct drm_i915_private
*dev_priv
,
3420 const struct skl_wm_values
*new)
3422 struct drm_device
*dev
= dev_priv
->dev
;
3423 struct intel_crtc
*crtc
;
3425 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, base
.head
) {
3426 int i
, level
, max_level
= ilk_wm_max_level(dev
);
3427 enum pipe pipe
= crtc
->pipe
;
3429 if (!new->dirty
[pipe
])
3432 I915_WRITE(PIPE_WM_LINETIME(pipe
), new->wm_linetime
[pipe
]);
3434 for (level
= 0; level
<= max_level
; level
++) {
3435 for (i
= 0; i
< intel_num_planes(crtc
); i
++)
3436 I915_WRITE(PLANE_WM(pipe
, i
, level
),
3437 new->plane
[pipe
][i
][level
]);
3438 I915_WRITE(CUR_WM(pipe
, level
),
3439 new->cursor
[pipe
][level
]);
3441 for (i
= 0; i
< intel_num_planes(crtc
); i
++)
3442 I915_WRITE(PLANE_WM_TRANS(pipe
, i
),
3443 new->plane_trans
[pipe
][i
]);
3444 I915_WRITE(CUR_WM_TRANS(pipe
), new->cursor_trans
[pipe
]);
3446 for (i
= 0; i
< intel_num_planes(crtc
); i
++) {
3447 skl_ddb_entry_write(dev_priv
,
3448 PLANE_BUF_CFG(pipe
, i
),
3449 &new->ddb
.plane
[pipe
][i
]);
3450 skl_ddb_entry_write(dev_priv
,
3451 PLANE_NV12_BUF_CFG(pipe
, i
),
3452 &new->ddb
.y_plane
[pipe
][i
]);
3455 skl_ddb_entry_write(dev_priv
, CUR_BUF_CFG(pipe
),
3456 &new->ddb
.cursor
[pipe
]);
3461 * When setting up a new DDB allocation arrangement, we need to correctly
3462 * sequence the times at which the new allocations for the pipes are taken into
3463 * account or we'll have pipes fetching from space previously allocated to
3466 * Roughly the sequence looks like:
3467 * 1. re-allocate the pipe(s) with the allocation being reduced and not
3468 * overlapping with a previous light-up pipe (another way to put it is:
3469 * pipes with their new allocation strickly included into their old ones).
3470 * 2. re-allocate the other pipes that get their allocation reduced
3471 * 3. allocate the pipes having their allocation increased
3473 * Steps 1. and 2. are here to take care of the following case:
3474 * - Initially DDB looks like this:
3477 * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
3481 * We need to sequence the re-allocation: C, B, A (and not B, C, A).
3485 skl_wm_flush_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int pass
)
3489 DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe
), pass
);
3491 for_each_plane(dev_priv
, pipe
, plane
) {
3492 I915_WRITE(PLANE_SURF(pipe
, plane
),
3493 I915_READ(PLANE_SURF(pipe
, plane
)));
3495 I915_WRITE(CURBASE(pipe
), I915_READ(CURBASE(pipe
)));
3499 skl_ddb_allocation_included(const struct skl_ddb_allocation
*old
,
3500 const struct skl_ddb_allocation
*new,
3503 uint16_t old_size
, new_size
;
3505 old_size
= skl_ddb_entry_size(&old
->pipe
[pipe
]);
3506 new_size
= skl_ddb_entry_size(&new->pipe
[pipe
]);
3508 return old_size
!= new_size
&&
3509 new->pipe
[pipe
].start
>= old
->pipe
[pipe
].start
&&
3510 new->pipe
[pipe
].end
<= old
->pipe
[pipe
].end
;
3513 static void skl_flush_wm_values(struct drm_i915_private
*dev_priv
,
3514 struct skl_wm_values
*new_values
)
3516 struct drm_device
*dev
= dev_priv
->dev
;
3517 struct skl_ddb_allocation
*cur_ddb
, *new_ddb
;
3518 bool reallocated
[I915_MAX_PIPES
] = {};
3519 struct intel_crtc
*crtc
;
3522 new_ddb
= &new_values
->ddb
;
3523 cur_ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
3526 * First pass: flush the pipes with the new allocation contained into
3529 * We'll wait for the vblank on those pipes to ensure we can safely
3530 * re-allocate the freed space without this pipe fetching from it.
3532 for_each_intel_crtc(dev
, crtc
) {
3538 if (!skl_ddb_allocation_included(cur_ddb
, new_ddb
, pipe
))
3541 skl_wm_flush_pipe(dev_priv
, pipe
, 1);
3542 intel_wait_for_vblank(dev
, pipe
);
3544 reallocated
[pipe
] = true;
3549 * Second pass: flush the pipes that are having their allocation
3550 * reduced, but overlapping with a previous allocation.
3552 * Here as well we need to wait for the vblank to make sure the freed
3553 * space is not used anymore.
3555 for_each_intel_crtc(dev
, crtc
) {
3561 if (reallocated
[pipe
])
3564 if (skl_ddb_entry_size(&new_ddb
->pipe
[pipe
]) <
3565 skl_ddb_entry_size(&cur_ddb
->pipe
[pipe
])) {
3566 skl_wm_flush_pipe(dev_priv
, pipe
, 2);
3567 intel_wait_for_vblank(dev
, pipe
);
3568 reallocated
[pipe
] = true;
3573 * Third pass: flush the pipes that got more space allocated.
3575 * We don't need to actively wait for the update here, next vblank
3576 * will just get more DDB space with the correct WM values.
3578 for_each_intel_crtc(dev
, crtc
) {
3585 * At this point, only the pipes more space than before are
3586 * left to re-allocate.
3588 if (reallocated
[pipe
])
3591 skl_wm_flush_pipe(dev_priv
, pipe
, 3);
3595 static bool skl_update_pipe_wm(struct drm_crtc
*crtc
,
3596 struct skl_pipe_wm_parameters
*params
,
3597 struct intel_wm_config
*config
,
3598 struct skl_ddb_allocation
*ddb
, /* out */
3599 struct skl_pipe_wm
*pipe_wm
/* out */)
3601 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3603 skl_compute_wm_pipe_parameters(crtc
, params
);
3604 skl_allocate_pipe_ddb(crtc
, config
, params
, ddb
);
3605 skl_compute_pipe_wm(crtc
, ddb
, params
, pipe_wm
);
3607 if (!memcmp(&intel_crtc
->wm
.skl_active
, pipe_wm
, sizeof(*pipe_wm
)))
3610 intel_crtc
->wm
.skl_active
= *pipe_wm
;
3615 static void skl_update_other_pipe_wm(struct drm_device
*dev
,
3616 struct drm_crtc
*crtc
,
3617 struct intel_wm_config
*config
,
3618 struct skl_wm_values
*r
)
3620 struct intel_crtc
*intel_crtc
;
3621 struct intel_crtc
*this_crtc
= to_intel_crtc(crtc
);
3624 * If the WM update hasn't changed the allocation for this_crtc (the
3625 * crtc we are currently computing the new WM values for), other
3626 * enabled crtcs will keep the same allocation and we don't need to
3627 * recompute anything for them.
3629 if (!skl_ddb_allocation_changed(&r
->ddb
, this_crtc
))
3633 * Otherwise, because of this_crtc being freshly enabled/disabled, the
3634 * other active pipes need new DDB allocation and WM values.
3636 list_for_each_entry(intel_crtc
, &dev
->mode_config
.crtc_list
,
3638 struct skl_pipe_wm_parameters params
= {};
3639 struct skl_pipe_wm pipe_wm
= {};
3642 if (this_crtc
->pipe
== intel_crtc
->pipe
)
3645 if (!intel_crtc
->active
)
3648 wm_changed
= skl_update_pipe_wm(&intel_crtc
->base
,
3653 * If we end up re-computing the other pipe WM values, it's
3654 * because it was really needed, so we expect the WM values to
3657 WARN_ON(!wm_changed
);
3659 skl_compute_wm_results(dev
, ¶ms
, &pipe_wm
, r
, intel_crtc
);
3660 r
->dirty
[intel_crtc
->pipe
] = true;
3664 static void skl_update_wm(struct drm_crtc
*crtc
)
3666 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3667 struct drm_device
*dev
= crtc
->dev
;
3668 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3669 struct skl_pipe_wm_parameters params
= {};
3670 struct skl_wm_values
*results
= &dev_priv
->wm
.skl_results
;
3671 struct skl_pipe_wm pipe_wm
= {};
3672 struct intel_wm_config config
= {};
3674 memset(results
, 0, sizeof(*results
));
3676 skl_compute_wm_global_parameters(dev
, &config
);
3678 if (!skl_update_pipe_wm(crtc
, ¶ms
, &config
,
3679 &results
->ddb
, &pipe_wm
))
3682 skl_compute_wm_results(dev
, ¶ms
, &pipe_wm
, results
, intel_crtc
);
3683 results
->dirty
[intel_crtc
->pipe
] = true;
3685 skl_update_other_pipe_wm(dev
, crtc
, &config
, results
);
3686 skl_write_wm_values(dev_priv
, results
);
3687 skl_flush_wm_values(dev_priv
, results
);
3689 /* store the new configuration */
3690 dev_priv
->wm
.skl_hw
= *results
;
3694 skl_update_sprite_wm(struct drm_plane
*plane
, struct drm_crtc
*crtc
,
3695 uint32_t sprite_width
, uint32_t sprite_height
,
3696 int pixel_size
, bool enabled
, bool scaled
)
3698 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
3699 struct drm_framebuffer
*fb
= plane
->state
->fb
;
3701 intel_plane
->wm
.enabled
= enabled
;
3702 intel_plane
->wm
.scaled
= scaled
;
3703 intel_plane
->wm
.horiz_pixels
= sprite_width
;
3704 intel_plane
->wm
.vert_pixels
= sprite_height
;
3705 intel_plane
->wm
.tiling
= DRM_FORMAT_MOD_NONE
;
3707 /* For planar: Bpp is for UV plane, y_Bpp is for Y plane */
3708 intel_plane
->wm
.bytes_per_pixel
=
3709 (fb
&& fb
->pixel_format
== DRM_FORMAT_NV12
) ?
3710 drm_format_plane_cpp(plane
->state
->fb
->pixel_format
, 1) : pixel_size
;
3711 intel_plane
->wm
.y_bytes_per_pixel
=
3712 (fb
&& fb
->pixel_format
== DRM_FORMAT_NV12
) ?
3713 drm_format_plane_cpp(plane
->state
->fb
->pixel_format
, 0) : 0;
3716 * Framebuffer can be NULL on plane disable, but it does not
3717 * matter for watermarks if we assume no tiling in that case.
3720 intel_plane
->wm
.tiling
= fb
->modifier
[0];
3721 intel_plane
->wm
.rotation
= plane
->state
->rotation
;
3723 skl_update_wm(crtc
);
3726 static void ilk_update_wm(struct drm_crtc
*crtc
)
3728 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3729 struct drm_device
*dev
= crtc
->dev
;
3730 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3731 struct ilk_wm_maximums max
;
3732 struct ilk_pipe_wm_parameters params
= {};
3733 struct ilk_wm_values results
= {};
3734 enum intel_ddb_partitioning partitioning
;
3735 struct intel_pipe_wm pipe_wm
= {};
3736 struct intel_pipe_wm lp_wm_1_2
= {}, lp_wm_5_6
= {}, *best_lp_wm
;
3737 struct intel_wm_config config
= {};
3739 ilk_compute_wm_parameters(crtc
, ¶ms
);
3741 intel_compute_pipe_wm(crtc
, ¶ms
, &pipe_wm
);
3743 if (!memcmp(&intel_crtc
->wm
.active
, &pipe_wm
, sizeof(pipe_wm
)))
3746 intel_crtc
->wm
.active
= pipe_wm
;
3748 ilk_compute_wm_config(dev
, &config
);
3750 ilk_compute_wm_maximums(dev
, 1, &config
, INTEL_DDB_PART_1_2
, &max
);
3751 ilk_wm_merge(dev
, &config
, &max
, &lp_wm_1_2
);
3753 /* 5/6 split only in single pipe config on IVB+ */
3754 if (INTEL_INFO(dev
)->gen
>= 7 &&
3755 config
.num_pipes_active
== 1 && config
.sprites_enabled
) {
3756 ilk_compute_wm_maximums(dev
, 1, &config
, INTEL_DDB_PART_5_6
, &max
);
3757 ilk_wm_merge(dev
, &config
, &max
, &lp_wm_5_6
);
3759 best_lp_wm
= ilk_find_best_result(dev
, &lp_wm_1_2
, &lp_wm_5_6
);
3761 best_lp_wm
= &lp_wm_1_2
;
3764 partitioning
= (best_lp_wm
== &lp_wm_1_2
) ?
3765 INTEL_DDB_PART_1_2
: INTEL_DDB_PART_5_6
;
3767 ilk_compute_wm_results(dev
, best_lp_wm
, partitioning
, &results
);
3769 ilk_write_wm_values(dev_priv
, &results
);
3773 ilk_update_sprite_wm(struct drm_plane
*plane
,
3774 struct drm_crtc
*crtc
,
3775 uint32_t sprite_width
, uint32_t sprite_height
,
3776 int pixel_size
, bool enabled
, bool scaled
)
3778 struct drm_device
*dev
= plane
->dev
;
3779 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
3781 intel_plane
->wm
.enabled
= enabled
;
3782 intel_plane
->wm
.scaled
= scaled
;
3783 intel_plane
->wm
.horiz_pixels
= sprite_width
;
3784 intel_plane
->wm
.vert_pixels
= sprite_width
;
3785 intel_plane
->wm
.bytes_per_pixel
= pixel_size
;
3788 * IVB workaround: must disable low power watermarks for at least
3789 * one frame before enabling scaling. LP watermarks can be re-enabled
3790 * when scaling is disabled.
3792 * WaCxSRDisabledForSpriteScaling:ivb
3794 if (IS_IVYBRIDGE(dev
) && scaled
&& ilk_disable_lp_wm(dev
))
3795 intel_wait_for_vblank(dev
, intel_plane
->pipe
);
3797 ilk_update_wm(crtc
);
3800 static void skl_pipe_wm_active_state(uint32_t val
,
3801 struct skl_pipe_wm
*active
,
3807 bool is_enabled
= (val
& PLANE_WM_EN
) != 0;
3811 active
->wm
[level
].plane_en
[i
] = is_enabled
;
3812 active
->wm
[level
].plane_res_b
[i
] =
3813 val
& PLANE_WM_BLOCKS_MASK
;
3814 active
->wm
[level
].plane_res_l
[i
] =
3815 (val
>> PLANE_WM_LINES_SHIFT
) &
3816 PLANE_WM_LINES_MASK
;
3818 active
->wm
[level
].cursor_en
= is_enabled
;
3819 active
->wm
[level
].cursor_res_b
=
3820 val
& PLANE_WM_BLOCKS_MASK
;
3821 active
->wm
[level
].cursor_res_l
=
3822 (val
>> PLANE_WM_LINES_SHIFT
) &
3823 PLANE_WM_LINES_MASK
;
3827 active
->trans_wm
.plane_en
[i
] = is_enabled
;
3828 active
->trans_wm
.plane_res_b
[i
] =
3829 val
& PLANE_WM_BLOCKS_MASK
;
3830 active
->trans_wm
.plane_res_l
[i
] =
3831 (val
>> PLANE_WM_LINES_SHIFT
) &
3832 PLANE_WM_LINES_MASK
;
3834 active
->trans_wm
.cursor_en
= is_enabled
;
3835 active
->trans_wm
.cursor_res_b
=
3836 val
& PLANE_WM_BLOCKS_MASK
;
3837 active
->trans_wm
.cursor_res_l
=
3838 (val
>> PLANE_WM_LINES_SHIFT
) &
3839 PLANE_WM_LINES_MASK
;
3844 static void skl_pipe_wm_get_hw_state(struct drm_crtc
*crtc
)
3846 struct drm_device
*dev
= crtc
->dev
;
3847 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3848 struct skl_wm_values
*hw
= &dev_priv
->wm
.skl_hw
;
3849 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3850 struct skl_pipe_wm
*active
= &intel_crtc
->wm
.skl_active
;
3851 enum pipe pipe
= intel_crtc
->pipe
;
3852 int level
, i
, max_level
;
3855 max_level
= ilk_wm_max_level(dev
);
3857 hw
->wm_linetime
[pipe
] = I915_READ(PIPE_WM_LINETIME(pipe
));
3859 for (level
= 0; level
<= max_level
; level
++) {
3860 for (i
= 0; i
< intel_num_planes(intel_crtc
); i
++)
3861 hw
->plane
[pipe
][i
][level
] =
3862 I915_READ(PLANE_WM(pipe
, i
, level
));
3863 hw
->cursor
[pipe
][level
] = I915_READ(CUR_WM(pipe
, level
));
3866 for (i
= 0; i
< intel_num_planes(intel_crtc
); i
++)
3867 hw
->plane_trans
[pipe
][i
] = I915_READ(PLANE_WM_TRANS(pipe
, i
));
3868 hw
->cursor_trans
[pipe
] = I915_READ(CUR_WM_TRANS(pipe
));
3870 if (!intel_crtc
->active
)
3873 hw
->dirty
[pipe
] = true;
3875 active
->linetime
= hw
->wm_linetime
[pipe
];
3877 for (level
= 0; level
<= max_level
; level
++) {
3878 for (i
= 0; i
< intel_num_planes(intel_crtc
); i
++) {
3879 temp
= hw
->plane
[pipe
][i
][level
];
3880 skl_pipe_wm_active_state(temp
, active
, false,
3883 temp
= hw
->cursor
[pipe
][level
];
3884 skl_pipe_wm_active_state(temp
, active
, false, true, i
, level
);
3887 for (i
= 0; i
< intel_num_planes(intel_crtc
); i
++) {
3888 temp
= hw
->plane_trans
[pipe
][i
];
3889 skl_pipe_wm_active_state(temp
, active
, true, false, i
, 0);
3892 temp
= hw
->cursor_trans
[pipe
];
3893 skl_pipe_wm_active_state(temp
, active
, true, true, i
, 0);
3896 void skl_wm_get_hw_state(struct drm_device
*dev
)
3898 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3899 struct skl_ddb_allocation
*ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
3900 struct drm_crtc
*crtc
;
3902 skl_ddb_get_hw_state(dev_priv
, ddb
);
3903 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
)
3904 skl_pipe_wm_get_hw_state(crtc
);
3907 static void ilk_pipe_wm_get_hw_state(struct drm_crtc
*crtc
)
3909 struct drm_device
*dev
= crtc
->dev
;
3910 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3911 struct ilk_wm_values
*hw
= &dev_priv
->wm
.hw
;
3912 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3913 struct intel_pipe_wm
*active
= &intel_crtc
->wm
.active
;
3914 enum pipe pipe
= intel_crtc
->pipe
;
3915 static const unsigned int wm0_pipe_reg
[] = {
3916 [PIPE_A
] = WM0_PIPEA_ILK
,
3917 [PIPE_B
] = WM0_PIPEB_ILK
,
3918 [PIPE_C
] = WM0_PIPEC_IVB
,
3921 hw
->wm_pipe
[pipe
] = I915_READ(wm0_pipe_reg
[pipe
]);
3922 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
3923 hw
->wm_linetime
[pipe
] = I915_READ(PIPE_WM_LINETIME(pipe
));
3925 active
->pipe_enabled
= intel_crtc
->active
;
3927 if (active
->pipe_enabled
) {
3928 u32 tmp
= hw
->wm_pipe
[pipe
];
3931 * For active pipes LP0 watermark is marked as
3932 * enabled, and LP1+ watermaks as disabled since
3933 * we can't really reverse compute them in case
3934 * multiple pipes are active.
3936 active
->wm
[0].enable
= true;
3937 active
->wm
[0].pri_val
= (tmp
& WM0_PIPE_PLANE_MASK
) >> WM0_PIPE_PLANE_SHIFT
;
3938 active
->wm
[0].spr_val
= (tmp
& WM0_PIPE_SPRITE_MASK
) >> WM0_PIPE_SPRITE_SHIFT
;
3939 active
->wm
[0].cur_val
= tmp
& WM0_PIPE_CURSOR_MASK
;
3940 active
->linetime
= hw
->wm_linetime
[pipe
];
3942 int level
, max_level
= ilk_wm_max_level(dev
);
3945 * For inactive pipes, all watermark levels
3946 * should be marked as enabled but zeroed,
3947 * which is what we'd compute them to.
3949 for (level
= 0; level
<= max_level
; level
++)
3950 active
->wm
[level
].enable
= true;
3954 #define _FW_WM(value, plane) \
3955 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
3956 #define _FW_WM_VLV(value, plane) \
3957 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
3959 static void vlv_read_wm_values(struct drm_i915_private
*dev_priv
,
3960 struct vlv_wm_values
*wm
)
3965 for_each_pipe(dev_priv
, pipe
) {
3966 tmp
= I915_READ(VLV_DDL(pipe
));
3968 wm
->ddl
[pipe
].primary
=
3969 (tmp
>> DDL_PLANE_SHIFT
) & (DDL_PRECISION_HIGH
| DRAIN_LATENCY_MASK
);
3970 wm
->ddl
[pipe
].cursor
=
3971 (tmp
>> DDL_CURSOR_SHIFT
) & (DDL_PRECISION_HIGH
| DRAIN_LATENCY_MASK
);
3972 wm
->ddl
[pipe
].sprite
[0] =
3973 (tmp
>> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH
| DRAIN_LATENCY_MASK
);
3974 wm
->ddl
[pipe
].sprite
[1] =
3975 (tmp
>> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH
| DRAIN_LATENCY_MASK
);
3978 tmp
= I915_READ(DSPFW1
);
3979 wm
->sr
.plane
= _FW_WM(tmp
, SR
);
3980 wm
->pipe
[PIPE_B
].cursor
= _FW_WM(tmp
, CURSORB
);
3981 wm
->pipe
[PIPE_B
].primary
= _FW_WM_VLV(tmp
, PLANEB
);
3982 wm
->pipe
[PIPE_A
].primary
= _FW_WM_VLV(tmp
, PLANEA
);
3984 tmp
= I915_READ(DSPFW2
);
3985 wm
->pipe
[PIPE_A
].sprite
[1] = _FW_WM_VLV(tmp
, SPRITEB
);
3986 wm
->pipe
[PIPE_A
].cursor
= _FW_WM(tmp
, CURSORA
);
3987 wm
->pipe
[PIPE_A
].sprite
[0] = _FW_WM_VLV(tmp
, SPRITEA
);
3989 tmp
= I915_READ(DSPFW3
);
3990 wm
->sr
.cursor
= _FW_WM(tmp
, CURSOR_SR
);
3992 if (IS_CHERRYVIEW(dev_priv
)) {
3993 tmp
= I915_READ(DSPFW7_CHV
);
3994 wm
->pipe
[PIPE_B
].sprite
[1] = _FW_WM_VLV(tmp
, SPRITED
);
3995 wm
->pipe
[PIPE_B
].sprite
[0] = _FW_WM_VLV(tmp
, SPRITEC
);
3997 tmp
= I915_READ(DSPFW8_CHV
);
3998 wm
->pipe
[PIPE_C
].sprite
[1] = _FW_WM_VLV(tmp
, SPRITEF
);
3999 wm
->pipe
[PIPE_C
].sprite
[0] = _FW_WM_VLV(tmp
, SPRITEE
);
4001 tmp
= I915_READ(DSPFW9_CHV
);
4002 wm
->pipe
[PIPE_C
].primary
= _FW_WM_VLV(tmp
, PLANEC
);
4003 wm
->pipe
[PIPE_C
].cursor
= _FW_WM(tmp
, CURSORC
);
4005 tmp
= I915_READ(DSPHOWM
);
4006 wm
->sr
.plane
|= _FW_WM(tmp
, SR_HI
) << 9;
4007 wm
->pipe
[PIPE_C
].sprite
[1] |= _FW_WM(tmp
, SPRITEF_HI
) << 8;
4008 wm
->pipe
[PIPE_C
].sprite
[0] |= _FW_WM(tmp
, SPRITEE_HI
) << 8;
4009 wm
->pipe
[PIPE_C
].primary
|= _FW_WM(tmp
, PLANEC_HI
) << 8;
4010 wm
->pipe
[PIPE_B
].sprite
[1] |= _FW_WM(tmp
, SPRITED_HI
) << 8;
4011 wm
->pipe
[PIPE_B
].sprite
[0] |= _FW_WM(tmp
, SPRITEC_HI
) << 8;
4012 wm
->pipe
[PIPE_B
].primary
|= _FW_WM(tmp
, PLANEB_HI
) << 8;
4013 wm
->pipe
[PIPE_A
].sprite
[1] |= _FW_WM(tmp
, SPRITEB_HI
) << 8;
4014 wm
->pipe
[PIPE_A
].sprite
[0] |= _FW_WM(tmp
, SPRITEA_HI
) << 8;
4015 wm
->pipe
[PIPE_A
].primary
|= _FW_WM(tmp
, PLANEA_HI
) << 8;
4017 tmp
= I915_READ(DSPFW7
);
4018 wm
->pipe
[PIPE_B
].sprite
[1] = _FW_WM_VLV(tmp
, SPRITED
);
4019 wm
->pipe
[PIPE_B
].sprite
[0] = _FW_WM_VLV(tmp
, SPRITEC
);
4021 tmp
= I915_READ(DSPHOWM
);
4022 wm
->sr
.plane
|= _FW_WM(tmp
, SR_HI
) << 9;
4023 wm
->pipe
[PIPE_B
].sprite
[1] |= _FW_WM(tmp
, SPRITED_HI
) << 8;
4024 wm
->pipe
[PIPE_B
].sprite
[0] |= _FW_WM(tmp
, SPRITEC_HI
) << 8;
4025 wm
->pipe
[PIPE_B
].primary
|= _FW_WM(tmp
, PLANEB_HI
) << 8;
4026 wm
->pipe
[PIPE_A
].sprite
[1] |= _FW_WM(tmp
, SPRITEB_HI
) << 8;
4027 wm
->pipe
[PIPE_A
].sprite
[0] |= _FW_WM(tmp
, SPRITEA_HI
) << 8;
4028 wm
->pipe
[PIPE_A
].primary
|= _FW_WM(tmp
, PLANEA_HI
) << 8;
4035 void vlv_wm_get_hw_state(struct drm_device
*dev
)
4037 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4038 struct vlv_wm_values
*wm
= &dev_priv
->wm
.vlv
;
4039 struct intel_plane
*plane
;
4043 vlv_read_wm_values(dev_priv
, wm
);
4045 for_each_intel_plane(dev
, plane
) {
4046 switch (plane
->base
.type
) {
4048 case DRM_PLANE_TYPE_CURSOR
:
4049 plane
->wm
.fifo_size
= 63;
4051 case DRM_PLANE_TYPE_PRIMARY
:
4052 plane
->wm
.fifo_size
= vlv_get_fifo_size(dev
, plane
->pipe
, 0);
4054 case DRM_PLANE_TYPE_OVERLAY
:
4055 sprite
= plane
->plane
;
4056 plane
->wm
.fifo_size
= vlv_get_fifo_size(dev
, plane
->pipe
, sprite
+ 1);
4061 wm
->cxsr
= I915_READ(FW_BLC_SELF_VLV
) & FW_CSPWRDWNEN
;
4062 wm
->level
= VLV_WM_LEVEL_PM2
;
4064 if (IS_CHERRYVIEW(dev_priv
)) {
4065 mutex_lock(&dev_priv
->rps
.hw_lock
);
4067 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
4068 if (val
& DSP_MAXFIFO_PM5_ENABLE
)
4069 wm
->level
= VLV_WM_LEVEL_PM5
;
4071 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DDR_SETUP2
);
4072 if ((val
& FORCE_DDR_HIGH_FREQ
) == 0)
4073 wm
->level
= VLV_WM_LEVEL_DDR_DVFS
;
4075 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4078 for_each_pipe(dev_priv
, pipe
)
4079 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4080 pipe_name(pipe
), wm
->pipe
[pipe
].primary
, wm
->pipe
[pipe
].cursor
,
4081 wm
->pipe
[pipe
].sprite
[0], wm
->pipe
[pipe
].sprite
[1]);
4083 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4084 wm
->sr
.plane
, wm
->sr
.cursor
, wm
->level
, wm
->cxsr
);
4087 void ilk_wm_get_hw_state(struct drm_device
*dev
)
4089 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4090 struct ilk_wm_values
*hw
= &dev_priv
->wm
.hw
;
4091 struct drm_crtc
*crtc
;
4093 for_each_crtc(dev
, crtc
)
4094 ilk_pipe_wm_get_hw_state(crtc
);
4096 hw
->wm_lp
[0] = I915_READ(WM1_LP_ILK
);
4097 hw
->wm_lp
[1] = I915_READ(WM2_LP_ILK
);
4098 hw
->wm_lp
[2] = I915_READ(WM3_LP_ILK
);
4100 hw
->wm_lp_spr
[0] = I915_READ(WM1S_LP_ILK
);
4101 if (INTEL_INFO(dev
)->gen
>= 7) {
4102 hw
->wm_lp_spr
[1] = I915_READ(WM2S_LP_IVB
);
4103 hw
->wm_lp_spr
[2] = I915_READ(WM3S_LP_IVB
);
4106 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
4107 hw
->partitioning
= (I915_READ(WM_MISC
) & WM_MISC_DATA_PARTITION_5_6
) ?
4108 INTEL_DDB_PART_5_6
: INTEL_DDB_PART_1_2
;
4109 else if (IS_IVYBRIDGE(dev
))
4110 hw
->partitioning
= (I915_READ(DISP_ARB_CTL2
) & DISP_DATA_PARTITION_5_6
) ?
4111 INTEL_DDB_PART_5_6
: INTEL_DDB_PART_1_2
;
4114 !(I915_READ(DISP_ARB_CTL
) & DISP_FBC_WM_DIS
);
4118 * intel_update_watermarks - update FIFO watermark values based on current modes
4120 * Calculate watermark values for the various WM regs based on current mode
4121 * and plane configuration.
4123 * There are several cases to deal with here:
4124 * - normal (i.e. non-self-refresh)
4125 * - self-refresh (SR) mode
4126 * - lines are large relative to FIFO size (buffer can hold up to 2)
4127 * - lines are small relative to FIFO size (buffer can hold more than 2
4128 * lines), so need to account for TLB latency
4130 * The normal calculation is:
4131 * watermark = dotclock * bytes per pixel * latency
4132 * where latency is platform & configuration dependent (we assume pessimal
4135 * The SR calculation is:
4136 * watermark = (trunc(latency/line time)+1) * surface width *
4139 * line time = htotal / dotclock
4140 * surface width = hdisplay for normal plane and 64 for cursor
4141 * and latency is assumed to be high, as above.
4143 * The final value programmed to the register should always be rounded up,
4144 * and include an extra 2 entries to account for clock crossings.
4146 * We don't use the sprite, so we can ignore that. And on Crestline we have
4147 * to set the non-SR watermarks to 8.
4149 void intel_update_watermarks(struct drm_crtc
*crtc
)
4151 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
4153 if (dev_priv
->display
.update_wm
)
4154 dev_priv
->display
.update_wm(crtc
);
4157 void intel_update_sprite_watermarks(struct drm_plane
*plane
,
4158 struct drm_crtc
*crtc
,
4159 uint32_t sprite_width
,
4160 uint32_t sprite_height
,
4162 bool enabled
, bool scaled
)
4164 struct drm_i915_private
*dev_priv
= plane
->dev
->dev_private
;
4166 if (dev_priv
->display
.update_sprite_wm
)
4167 dev_priv
->display
.update_sprite_wm(plane
, crtc
,
4168 sprite_width
, sprite_height
,
4169 pixel_size
, enabled
, scaled
);
4173 * Lock protecting IPS related data structures
4175 DEFINE_SPINLOCK(mchdev_lock
);
4177 /* Global for IPS driver to get at the current i915 device. Protected by
4179 static struct drm_i915_private
*i915_mch_dev
;
4181 bool ironlake_set_drps(struct drm_device
*dev
, u8 val
)
4183 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4186 assert_spin_locked(&mchdev_lock
);
4188 rgvswctl
= I915_READ16(MEMSWCTL
);
4189 if (rgvswctl
& MEMCTL_CMD_STS
) {
4190 DRM_DEBUG("gpu busy, RCS change rejected\n");
4191 return false; /* still busy with another command */
4194 rgvswctl
= (MEMCTL_CMD_CHFREQ
<< MEMCTL_CMD_SHIFT
) |
4195 (val
<< MEMCTL_FREQ_SHIFT
) | MEMCTL_SFCAVM
;
4196 I915_WRITE16(MEMSWCTL
, rgvswctl
);
4197 POSTING_READ16(MEMSWCTL
);
4199 rgvswctl
|= MEMCTL_CMD_STS
;
4200 I915_WRITE16(MEMSWCTL
, rgvswctl
);
4205 static void ironlake_enable_drps(struct drm_device
*dev
)
4207 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4208 u32 rgvmodectl
= I915_READ(MEMMODECTL
);
4209 u8 fmax
, fmin
, fstart
, vstart
;
4211 spin_lock_irq(&mchdev_lock
);
4213 /* Enable temp reporting */
4214 I915_WRITE16(PMMISC
, I915_READ(PMMISC
) | MCPPCE_EN
);
4215 I915_WRITE16(TSC1
, I915_READ(TSC1
) | TSE
);
4217 /* 100ms RC evaluation intervals */
4218 I915_WRITE(RCUPEI
, 100000);
4219 I915_WRITE(RCDNEI
, 100000);
4221 /* Set max/min thresholds to 90ms and 80ms respectively */
4222 I915_WRITE(RCBMAXAVG
, 90000);
4223 I915_WRITE(RCBMINAVG
, 80000);
4225 I915_WRITE(MEMIHYST
, 1);
4227 /* Set up min, max, and cur for interrupt handling */
4228 fmax
= (rgvmodectl
& MEMMODE_FMAX_MASK
) >> MEMMODE_FMAX_SHIFT
;
4229 fmin
= (rgvmodectl
& MEMMODE_FMIN_MASK
);
4230 fstart
= (rgvmodectl
& MEMMODE_FSTART_MASK
) >>
4231 MEMMODE_FSTART_SHIFT
;
4233 vstart
= (I915_READ(PXVFREQ_BASE
+ (fstart
* 4)) & PXVFREQ_PX_MASK
) >>
4236 dev_priv
->ips
.fmax
= fmax
; /* IPS callback will increase this */
4237 dev_priv
->ips
.fstart
= fstart
;
4239 dev_priv
->ips
.max_delay
= fstart
;
4240 dev_priv
->ips
.min_delay
= fmin
;
4241 dev_priv
->ips
.cur_delay
= fstart
;
4243 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4244 fmax
, fmin
, fstart
);
4246 I915_WRITE(MEMINTREN
, MEMINT_CX_SUPR_EN
| MEMINT_EVAL_CHG_EN
);
4249 * Interrupts will be enabled in ironlake_irq_postinstall
4252 I915_WRITE(VIDSTART
, vstart
);
4253 POSTING_READ(VIDSTART
);
4255 rgvmodectl
|= MEMMODE_SWMODE_EN
;
4256 I915_WRITE(MEMMODECTL
, rgvmodectl
);
4258 if (wait_for_atomic((I915_READ(MEMSWCTL
) & MEMCTL_CMD_STS
) == 0, 10))
4259 DRM_ERROR("stuck trying to change perf mode\n");
4262 ironlake_set_drps(dev
, fstart
);
4264 dev_priv
->ips
.last_count1
= I915_READ(0x112e4) + I915_READ(0x112e8) +
4266 dev_priv
->ips
.last_time1
= jiffies_to_msecs(jiffies
);
4267 dev_priv
->ips
.last_count2
= I915_READ(0x112f4);
4268 dev_priv
->ips
.last_time2
= ktime_get_raw_ns();
4270 spin_unlock_irq(&mchdev_lock
);
4273 static void ironlake_disable_drps(struct drm_device
*dev
)
4275 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4278 spin_lock_irq(&mchdev_lock
);
4280 rgvswctl
= I915_READ16(MEMSWCTL
);
4282 /* Ack interrupts, disable EFC interrupt */
4283 I915_WRITE(MEMINTREN
, I915_READ(MEMINTREN
) & ~MEMINT_EVAL_CHG_EN
);
4284 I915_WRITE(MEMINTRSTS
, MEMINT_EVAL_CHG
);
4285 I915_WRITE(DEIER
, I915_READ(DEIER
) & ~DE_PCU_EVENT
);
4286 I915_WRITE(DEIIR
, DE_PCU_EVENT
);
4287 I915_WRITE(DEIMR
, I915_READ(DEIMR
) | DE_PCU_EVENT
);
4289 /* Go back to the starting frequency */
4290 ironlake_set_drps(dev
, dev_priv
->ips
.fstart
);
4292 rgvswctl
|= MEMCTL_CMD_STS
;
4293 I915_WRITE(MEMSWCTL
, rgvswctl
);
4296 spin_unlock_irq(&mchdev_lock
);
4299 /* There's a funny hw issue where the hw returns all 0 when reading from
4300 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4301 * ourselves, instead of doing a rmw cycle (which might result in us clearing
4302 * all limits and the gpu stuck at whatever frequency it is at atm).
4304 static u32
intel_rps_limits(struct drm_i915_private
*dev_priv
, u8 val
)
4308 /* Only set the down limit when we've reached the lowest level to avoid
4309 * getting more interrupts, otherwise leave this clear. This prevents a
4310 * race in the hw when coming out of rc6: There's a tiny window where
4311 * the hw runs at the minimal clock before selecting the desired
4312 * frequency, if the down threshold expires in that window we will not
4313 * receive a down interrupt. */
4314 if (IS_GEN9(dev_priv
->dev
)) {
4315 limits
= (dev_priv
->rps
.max_freq_softlimit
) << 23;
4316 if (val
<= dev_priv
->rps
.min_freq_softlimit
)
4317 limits
|= (dev_priv
->rps
.min_freq_softlimit
) << 14;
4319 limits
= dev_priv
->rps
.max_freq_softlimit
<< 24;
4320 if (val
<= dev_priv
->rps
.min_freq_softlimit
)
4321 limits
|= dev_priv
->rps
.min_freq_softlimit
<< 16;
4327 static void gen6_set_rps_thresholds(struct drm_i915_private
*dev_priv
, u8 val
)
4330 u32 threshold_up
= 0, threshold_down
= 0; /* in % */
4331 u32 ei_up
= 0, ei_down
= 0;
4333 new_power
= dev_priv
->rps
.power
;
4334 switch (dev_priv
->rps
.power
) {
4336 if (val
> dev_priv
->rps
.efficient_freq
+ 1 && val
> dev_priv
->rps
.cur_freq
)
4337 new_power
= BETWEEN
;
4341 if (val
<= dev_priv
->rps
.efficient_freq
&& val
< dev_priv
->rps
.cur_freq
)
4342 new_power
= LOW_POWER
;
4343 else if (val
>= dev_priv
->rps
.rp0_freq
&& val
> dev_priv
->rps
.cur_freq
)
4344 new_power
= HIGH_POWER
;
4348 if (val
< (dev_priv
->rps
.rp1_freq
+ dev_priv
->rps
.rp0_freq
) >> 1 && val
< dev_priv
->rps
.cur_freq
)
4349 new_power
= BETWEEN
;
4352 /* Max/min bins are special */
4353 if (val
<= dev_priv
->rps
.min_freq_softlimit
)
4354 new_power
= LOW_POWER
;
4355 if (val
>= dev_priv
->rps
.max_freq_softlimit
)
4356 new_power
= HIGH_POWER
;
4357 if (new_power
== dev_priv
->rps
.power
)
4360 /* Note the units here are not exactly 1us, but 1280ns. */
4361 switch (new_power
) {
4363 /* Upclock if more than 95% busy over 16ms */
4367 /* Downclock if less than 85% busy over 32ms */
4369 threshold_down
= 85;
4373 /* Upclock if more than 90% busy over 13ms */
4377 /* Downclock if less than 75% busy over 32ms */
4379 threshold_down
= 75;
4383 /* Upclock if more than 85% busy over 10ms */
4387 /* Downclock if less than 60% busy over 32ms */
4389 threshold_down
= 60;
4393 I915_WRITE(GEN6_RP_UP_EI
,
4394 GT_INTERVAL_FROM_US(dev_priv
, ei_up
));
4395 I915_WRITE(GEN6_RP_UP_THRESHOLD
,
4396 GT_INTERVAL_FROM_US(dev_priv
, (ei_up
* threshold_up
/ 100)));
4398 I915_WRITE(GEN6_RP_DOWN_EI
,
4399 GT_INTERVAL_FROM_US(dev_priv
, ei_down
));
4400 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
,
4401 GT_INTERVAL_FROM_US(dev_priv
, (ei_down
* threshold_down
/ 100)));
4403 I915_WRITE(GEN6_RP_CONTROL
,
4404 GEN6_RP_MEDIA_TURBO
|
4405 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
4406 GEN6_RP_MEDIA_IS_GFX
|
4408 GEN6_RP_UP_BUSY_AVG
|
4409 GEN6_RP_DOWN_IDLE_AVG
);
4411 dev_priv
->rps
.power
= new_power
;
4412 dev_priv
->rps
.up_threshold
= threshold_up
;
4413 dev_priv
->rps
.down_threshold
= threshold_down
;
4414 dev_priv
->rps
.last_adj
= 0;
4417 static u32
gen6_rps_pm_mask(struct drm_i915_private
*dev_priv
, u8 val
)
4421 if (val
> dev_priv
->rps
.min_freq_softlimit
)
4422 mask
|= GEN6_PM_RP_DOWN_EI_EXPIRED
| GEN6_PM_RP_DOWN_THRESHOLD
| GEN6_PM_RP_DOWN_TIMEOUT
;
4423 if (val
< dev_priv
->rps
.max_freq_softlimit
)
4424 mask
|= GEN6_PM_RP_UP_EI_EXPIRED
| GEN6_PM_RP_UP_THRESHOLD
;
4426 mask
&= dev_priv
->pm_rps_events
;
4428 return gen6_sanitize_rps_pm_mask(dev_priv
, ~mask
);
4431 /* gen6_set_rps is called to update the frequency request, but should also be
4432 * called when the range (min_delay and max_delay) is modified so that we can
4433 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
4434 static void gen6_set_rps(struct drm_device
*dev
, u8 val
)
4436 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4438 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
4439 WARN_ON(val
> dev_priv
->rps
.max_freq
);
4440 WARN_ON(val
< dev_priv
->rps
.min_freq
);
4442 /* min/max delay may still have been modified so be sure to
4443 * write the limits value.
4445 if (val
!= dev_priv
->rps
.cur_freq
) {
4446 gen6_set_rps_thresholds(dev_priv
, val
);
4449 I915_WRITE(GEN6_RPNSWREQ
,
4450 GEN9_FREQUENCY(val
));
4451 else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
4452 I915_WRITE(GEN6_RPNSWREQ
,
4453 HSW_FREQUENCY(val
));
4455 I915_WRITE(GEN6_RPNSWREQ
,
4456 GEN6_FREQUENCY(val
) |
4458 GEN6_AGGRESSIVE_TURBO
);
4461 /* Make sure we continue to get interrupts
4462 * until we hit the minimum or maximum frequencies.
4464 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS
, intel_rps_limits(dev_priv
, val
));
4465 I915_WRITE(GEN6_PMINTRMSK
, gen6_rps_pm_mask(dev_priv
, val
));
4467 POSTING_READ(GEN6_RPNSWREQ
);
4469 dev_priv
->rps
.cur_freq
= val
;
4470 trace_intel_gpu_freq_change(val
* 50);
4473 static void valleyview_set_rps(struct drm_device
*dev
, u8 val
)
4475 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4477 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
4478 WARN_ON(val
> dev_priv
->rps
.max_freq
);
4479 WARN_ON(val
< dev_priv
->rps
.min_freq
);
4481 if (WARN_ONCE(IS_CHERRYVIEW(dev
) && (val
& 1),
4482 "Odd GPU freq value\n"))
4485 I915_WRITE(GEN6_PMINTRMSK
, gen6_rps_pm_mask(dev_priv
, val
));
4487 if (val
!= dev_priv
->rps
.cur_freq
) {
4488 vlv_punit_write(dev_priv
, PUNIT_REG_GPU_FREQ_REQ
, val
);
4489 if (!IS_CHERRYVIEW(dev_priv
))
4490 gen6_set_rps_thresholds(dev_priv
, val
);
4493 dev_priv
->rps
.cur_freq
= val
;
4494 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv
, val
));
4497 /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
4499 * * If Gfx is Idle, then
4500 * 1. Forcewake Media well.
4501 * 2. Request idle freq.
4502 * 3. Release Forcewake of Media well.
4504 static void vlv_set_rps_idle(struct drm_i915_private
*dev_priv
)
4506 u32 val
= dev_priv
->rps
.idle_freq
;
4508 if (dev_priv
->rps
.cur_freq
<= val
)
4511 /* Wake up the media well, as that takes a lot less
4512 * power than the Render well. */
4513 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_MEDIA
);
4514 valleyview_set_rps(dev_priv
->dev
, val
);
4515 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_MEDIA
);
4518 void gen6_rps_busy(struct drm_i915_private
*dev_priv
)
4520 mutex_lock(&dev_priv
->rps
.hw_lock
);
4521 if (dev_priv
->rps
.enabled
) {
4522 if (dev_priv
->pm_rps_events
& (GEN6_PM_RP_DOWN_EI_EXPIRED
| GEN6_PM_RP_UP_EI_EXPIRED
))
4523 gen6_rps_reset_ei(dev_priv
);
4524 I915_WRITE(GEN6_PMINTRMSK
,
4525 gen6_rps_pm_mask(dev_priv
, dev_priv
->rps
.cur_freq
));
4527 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4530 void gen6_rps_idle(struct drm_i915_private
*dev_priv
)
4532 struct drm_device
*dev
= dev_priv
->dev
;
4534 mutex_lock(&dev_priv
->rps
.hw_lock
);
4535 if (dev_priv
->rps
.enabled
) {
4536 if (IS_VALLEYVIEW(dev
))
4537 vlv_set_rps_idle(dev_priv
);
4539 gen6_set_rps(dev_priv
->dev
, dev_priv
->rps
.idle_freq
);
4540 dev_priv
->rps
.last_adj
= 0;
4541 I915_WRITE(GEN6_PMINTRMSK
, 0xffffffff);
4543 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4545 spin_lock(&dev_priv
->rps
.client_lock
);
4546 while (!list_empty(&dev_priv
->rps
.clients
))
4547 list_del_init(dev_priv
->rps
.clients
.next
);
4548 spin_unlock(&dev_priv
->rps
.client_lock
);
4551 void gen6_rps_boost(struct drm_i915_private
*dev_priv
,
4552 struct intel_rps_client
*rps
,
4553 unsigned long submitted
)
4555 /* This is intentionally racy! We peek at the state here, then
4556 * validate inside the RPS worker.
4558 if (!(dev_priv
->mm
.busy
&&
4559 dev_priv
->rps
.enabled
&&
4560 dev_priv
->rps
.cur_freq
< dev_priv
->rps
.max_freq_softlimit
))
4563 /* Force a RPS boost (and don't count it against the client) if
4564 * the GPU is severely congested.
4566 if (rps
&& time_after(jiffies
, submitted
+ DRM_I915_THROTTLE_JIFFIES
))
4569 spin_lock(&dev_priv
->rps
.client_lock
);
4570 if (rps
== NULL
|| list_empty(&rps
->link
)) {
4571 spin_lock_irq(&dev_priv
->irq_lock
);
4572 if (dev_priv
->rps
.interrupts_enabled
) {
4573 dev_priv
->rps
.client_boost
= true;
4574 queue_work(dev_priv
->wq
, &dev_priv
->rps
.work
);
4576 spin_unlock_irq(&dev_priv
->irq_lock
);
4579 list_add(&rps
->link
, &dev_priv
->rps
.clients
);
4582 dev_priv
->rps
.boosts
++;
4584 spin_unlock(&dev_priv
->rps
.client_lock
);
4587 void intel_set_rps(struct drm_device
*dev
, u8 val
)
4589 if (IS_VALLEYVIEW(dev
))
4590 valleyview_set_rps(dev
, val
);
4592 gen6_set_rps(dev
, val
);
4595 static void gen9_disable_rps(struct drm_device
*dev
)
4597 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4599 I915_WRITE(GEN6_RC_CONTROL
, 0);
4600 I915_WRITE(GEN9_PG_ENABLE
, 0);
4603 static void gen6_disable_rps(struct drm_device
*dev
)
4605 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4607 I915_WRITE(GEN6_RC_CONTROL
, 0);
4608 I915_WRITE(GEN6_RPNSWREQ
, 1 << 31);
4611 static void cherryview_disable_rps(struct drm_device
*dev
)
4613 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4615 I915_WRITE(GEN6_RC_CONTROL
, 0);
4618 static void valleyview_disable_rps(struct drm_device
*dev
)
4620 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4622 /* we're doing forcewake before Disabling RC6,
4623 * This what the BIOS expects when going into suspend */
4624 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
4626 I915_WRITE(GEN6_RC_CONTROL
, 0);
4628 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
4631 static void intel_print_rc6_info(struct drm_device
*dev
, u32 mode
)
4633 if (IS_VALLEYVIEW(dev
)) {
4634 if (mode
& (GEN7_RC_CTL_TO_MODE
| GEN6_RC_CTL_EI_MODE(1)))
4635 mode
= GEN6_RC_CTL_RC6_ENABLE
;
4640 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
4641 (mode
& GEN6_RC_CTL_RC6_ENABLE
) ? "on" : "off",
4642 (mode
& GEN6_RC_CTL_RC6p_ENABLE
) ? "on" : "off",
4643 (mode
& GEN6_RC_CTL_RC6pp_ENABLE
) ? "on" : "off");
4646 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
4647 (mode
& GEN6_RC_CTL_RC6_ENABLE
) ? "on" : "off");
4650 static int sanitize_rc6_option(const struct drm_device
*dev
, int enable_rc6
)
4652 /* No RC6 before Ironlake and code is gone for ilk. */
4653 if (INTEL_INFO(dev
)->gen
< 6)
4656 /* Respect the kernel parameter if it is set */
4657 if (enable_rc6
>= 0) {
4661 mask
= INTEL_RC6_ENABLE
| INTEL_RC6p_ENABLE
|
4664 mask
= INTEL_RC6_ENABLE
;
4666 if ((enable_rc6
& mask
) != enable_rc6
)
4667 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
4668 enable_rc6
& mask
, enable_rc6
, mask
);
4670 return enable_rc6
& mask
;
4673 if (IS_IVYBRIDGE(dev
))
4674 return (INTEL_RC6_ENABLE
| INTEL_RC6p_ENABLE
);
4676 return INTEL_RC6_ENABLE
;
4679 int intel_enable_rc6(const struct drm_device
*dev
)
4681 return i915
.enable_rc6
;
4684 static void gen6_init_rps_frequencies(struct drm_device
*dev
)
4686 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4687 uint32_t rp_state_cap
;
4688 u32 ddcc_status
= 0;
4691 /* All of these values are in units of 50MHz */
4692 dev_priv
->rps
.cur_freq
= 0;
4693 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
4694 if (IS_BROXTON(dev
)) {
4695 rp_state_cap
= I915_READ(BXT_RP_STATE_CAP
);
4696 dev_priv
->rps
.rp0_freq
= (rp_state_cap
>> 16) & 0xff;
4697 dev_priv
->rps
.rp1_freq
= (rp_state_cap
>> 8) & 0xff;
4698 dev_priv
->rps
.min_freq
= (rp_state_cap
>> 0) & 0xff;
4700 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
4701 dev_priv
->rps
.rp0_freq
= (rp_state_cap
>> 0) & 0xff;
4702 dev_priv
->rps
.rp1_freq
= (rp_state_cap
>> 8) & 0xff;
4703 dev_priv
->rps
.min_freq
= (rp_state_cap
>> 16) & 0xff;
4706 /* hw_max = RP0 until we check for overclocking */
4707 dev_priv
->rps
.max_freq
= dev_priv
->rps
.rp0_freq
;
4709 dev_priv
->rps
.efficient_freq
= dev_priv
->rps
.rp1_freq
;
4710 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
) || IS_SKYLAKE(dev
)) {
4711 ret
= sandybridge_pcode_read(dev_priv
,
4712 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL
,
4715 dev_priv
->rps
.efficient_freq
=
4717 ((ddcc_status
>> 8) & 0xff),
4718 dev_priv
->rps
.min_freq
,
4719 dev_priv
->rps
.max_freq
);
4722 if (IS_SKYLAKE(dev
)) {
4723 /* Store the frequency values in 16.66 MHZ units, which is
4724 the natural hardware unit for SKL */
4725 dev_priv
->rps
.rp0_freq
*= GEN9_FREQ_SCALER
;
4726 dev_priv
->rps
.rp1_freq
*= GEN9_FREQ_SCALER
;
4727 dev_priv
->rps
.min_freq
*= GEN9_FREQ_SCALER
;
4728 dev_priv
->rps
.max_freq
*= GEN9_FREQ_SCALER
;
4729 dev_priv
->rps
.efficient_freq
*= GEN9_FREQ_SCALER
;
4732 dev_priv
->rps
.idle_freq
= dev_priv
->rps
.min_freq
;
4734 /* Preserve min/max settings in case of re-init */
4735 if (dev_priv
->rps
.max_freq_softlimit
== 0)
4736 dev_priv
->rps
.max_freq_softlimit
= dev_priv
->rps
.max_freq
;
4738 if (dev_priv
->rps
.min_freq_softlimit
== 0) {
4739 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
4740 dev_priv
->rps
.min_freq_softlimit
=
4741 max_t(int, dev_priv
->rps
.efficient_freq
,
4742 intel_freq_opcode(dev_priv
, 450));
4744 dev_priv
->rps
.min_freq_softlimit
=
4745 dev_priv
->rps
.min_freq
;
4749 /* See the Gen9_GT_PM_Programming_Guide doc for the below */
4750 static void gen9_enable_rps(struct drm_device
*dev
)
4752 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4754 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
4756 gen6_init_rps_frequencies(dev
);
4758 /* Program defaults and thresholds for RPS*/
4759 I915_WRITE(GEN6_RC_VIDEO_FREQ
,
4760 GEN9_FREQUENCY(dev_priv
->rps
.rp1_freq
));
4762 /* 1 second timeout*/
4763 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
,
4764 GT_INTERVAL_FROM_US(dev_priv
, 1000000));
4766 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 0xa);
4768 /* Leaning on the below call to gen6_set_rps to program/setup the
4769 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
4770 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
4771 dev_priv
->rps
.power
= HIGH_POWER
; /* force a reset */
4772 gen6_set_rps(dev_priv
->dev
, dev_priv
->rps
.min_freq_softlimit
);
4774 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
4777 static void gen9_enable_rc6(struct drm_device
*dev
)
4779 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4780 struct intel_engine_cs
*ring
;
4781 uint32_t rc6_mask
= 0;
4784 /* 1a: Software RC state - RC0 */
4785 I915_WRITE(GEN6_RC_STATE
, 0);
4787 /* 1b: Get forcewake during program sequence. Although the driver
4788 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4789 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
4791 /* 2a: Disable RC states. */
4792 I915_WRITE(GEN6_RC_CONTROL
, 0);
4794 /* 2b: Program RC6 thresholds.*/
4795 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 54 << 16);
4796 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000); /* 12500 * 1280ns */
4797 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25); /* 25 * 1280ns */
4798 for_each_ring(ring
, dev_priv
, unused
)
4799 I915_WRITE(RING_MAX_IDLE(ring
->mmio_base
), 10);
4800 I915_WRITE(GEN6_RC_SLEEP
, 0);
4801 I915_WRITE(GEN6_RC6_THRESHOLD
, 37500); /* 37.5/125ms per EI */
4803 /* 2c: Program Coarse Power Gating Policies. */
4804 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS
, 25);
4805 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS
, 25);
4807 /* 3a: Enable RC6 */
4808 if (intel_enable_rc6(dev
) & INTEL_RC6_ENABLE
)
4809 rc6_mask
= GEN6_RC_CTL_RC6_ENABLE
;
4810 DRM_INFO("RC6 %s\n", (rc6_mask
& GEN6_RC_CTL_RC6_ENABLE
) ?
4812 I915_WRITE(GEN6_RC_CONTROL
, GEN6_RC_CTL_HW_ENABLE
|
4813 GEN6_RC_CTL_EI_MODE(1) |
4817 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
4818 * WaDisableRenderPowerGating:skl,bxt - Render PG need to be disabled with RC6.
4820 I915_WRITE(GEN9_PG_ENABLE
, (rc6_mask
& GEN6_RC_CTL_RC6_ENABLE
) ?
4821 GEN9_MEDIA_PG_ENABLE
: 0);
4824 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
4828 static void gen8_enable_rps(struct drm_device
*dev
)
4830 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4831 struct intel_engine_cs
*ring
;
4832 uint32_t rc6_mask
= 0;
4835 /* 1a: Software RC state - RC0 */
4836 I915_WRITE(GEN6_RC_STATE
, 0);
4838 /* 1c & 1d: Get forcewake during program sequence. Although the driver
4839 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4840 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
4842 /* 2a: Disable RC states. */
4843 I915_WRITE(GEN6_RC_CONTROL
, 0);
4845 /* Initialize rps frequencies */
4846 gen6_init_rps_frequencies(dev
);
4848 /* 2b: Program RC6 thresholds.*/
4849 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 40 << 16);
4850 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000); /* 12500 * 1280ns */
4851 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25); /* 25 * 1280ns */
4852 for_each_ring(ring
, dev_priv
, unused
)
4853 I915_WRITE(RING_MAX_IDLE(ring
->mmio_base
), 10);
4854 I915_WRITE(GEN6_RC_SLEEP
, 0);
4855 if (IS_BROADWELL(dev
))
4856 I915_WRITE(GEN6_RC6_THRESHOLD
, 625); /* 800us/1.28 for TO */
4858 I915_WRITE(GEN6_RC6_THRESHOLD
, 50000); /* 50/125ms per EI */
4861 if (intel_enable_rc6(dev
) & INTEL_RC6_ENABLE
)
4862 rc6_mask
= GEN6_RC_CTL_RC6_ENABLE
;
4863 intel_print_rc6_info(dev
, rc6_mask
);
4864 if (IS_BROADWELL(dev
))
4865 I915_WRITE(GEN6_RC_CONTROL
, GEN6_RC_CTL_HW_ENABLE
|
4866 GEN7_RC_CTL_TO_MODE
|
4869 I915_WRITE(GEN6_RC_CONTROL
, GEN6_RC_CTL_HW_ENABLE
|
4870 GEN6_RC_CTL_EI_MODE(1) |
4873 /* 4 Program defaults and thresholds for RPS*/
4874 I915_WRITE(GEN6_RPNSWREQ
,
4875 HSW_FREQUENCY(dev_priv
->rps
.rp1_freq
));
4876 I915_WRITE(GEN6_RC_VIDEO_FREQ
,
4877 HSW_FREQUENCY(dev_priv
->rps
.rp1_freq
));
4878 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
4879 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 100000000 / 128); /* 1 second timeout */
4881 /* Docs recommend 900MHz, and 300 MHz respectively */
4882 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS
,
4883 dev_priv
->rps
.max_freq_softlimit
<< 24 |
4884 dev_priv
->rps
.min_freq_softlimit
<< 16);
4886 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 7600000 / 128); /* 76ms busyness per EI, 90% */
4887 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 31300000 / 128); /* 313ms busyness per EI, 70%*/
4888 I915_WRITE(GEN6_RP_UP_EI
, 66000); /* 84.48ms, XXX: random? */
4889 I915_WRITE(GEN6_RP_DOWN_EI
, 350000); /* 448ms, XXX: random? */
4891 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
4894 I915_WRITE(GEN6_RP_CONTROL
,
4895 GEN6_RP_MEDIA_TURBO
|
4896 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
4897 GEN6_RP_MEDIA_IS_GFX
|
4899 GEN6_RP_UP_BUSY_AVG
|
4900 GEN6_RP_DOWN_IDLE_AVG
);
4902 /* 6: Ring frequency + overclocking (our driver does this later */
4904 dev_priv
->rps
.power
= HIGH_POWER
; /* force a reset */
4905 gen6_set_rps(dev_priv
->dev
, dev_priv
->rps
.idle_freq
);
4907 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
4910 static void gen6_enable_rps(struct drm_device
*dev
)
4912 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4913 struct intel_engine_cs
*ring
;
4914 u32 rc6vids
, pcu_mbox
= 0, rc6_mask
= 0;
4919 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
4921 /* Here begins a magic sequence of register writes to enable
4922 * auto-downclocking.
4924 * Perhaps there might be some value in exposing these to
4927 I915_WRITE(GEN6_RC_STATE
, 0);
4929 /* Clear the DBG now so we don't confuse earlier errors */
4930 if ((gtfifodbg
= I915_READ(GTFIFODBG
))) {
4931 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg
);
4932 I915_WRITE(GTFIFODBG
, gtfifodbg
);
4935 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
4937 /* Initialize rps frequencies */
4938 gen6_init_rps_frequencies(dev
);
4940 /* disable the counters and set deterministic thresholds */
4941 I915_WRITE(GEN6_RC_CONTROL
, 0);
4943 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT
, 1000 << 16);
4944 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 40 << 16 | 30);
4945 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT
, 30);
4946 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000);
4947 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25);
4949 for_each_ring(ring
, dev_priv
, i
)
4950 I915_WRITE(RING_MAX_IDLE(ring
->mmio_base
), 10);
4952 I915_WRITE(GEN6_RC_SLEEP
, 0);
4953 I915_WRITE(GEN6_RC1e_THRESHOLD
, 1000);
4954 if (IS_IVYBRIDGE(dev
))
4955 I915_WRITE(GEN6_RC6_THRESHOLD
, 125000);
4957 I915_WRITE(GEN6_RC6_THRESHOLD
, 50000);
4958 I915_WRITE(GEN6_RC6p_THRESHOLD
, 150000);
4959 I915_WRITE(GEN6_RC6pp_THRESHOLD
, 64000); /* unused */
4961 /* Check if we are enabling RC6 */
4962 rc6_mode
= intel_enable_rc6(dev_priv
->dev
);
4963 if (rc6_mode
& INTEL_RC6_ENABLE
)
4964 rc6_mask
|= GEN6_RC_CTL_RC6_ENABLE
;
4966 /* We don't use those on Haswell */
4967 if (!IS_HASWELL(dev
)) {
4968 if (rc6_mode
& INTEL_RC6p_ENABLE
)
4969 rc6_mask
|= GEN6_RC_CTL_RC6p_ENABLE
;
4971 if (rc6_mode
& INTEL_RC6pp_ENABLE
)
4972 rc6_mask
|= GEN6_RC_CTL_RC6pp_ENABLE
;
4975 intel_print_rc6_info(dev
, rc6_mask
);
4977 I915_WRITE(GEN6_RC_CONTROL
,
4979 GEN6_RC_CTL_EI_MODE(1) |
4980 GEN6_RC_CTL_HW_ENABLE
);
4982 /* Power down if completely idle for over 50ms */
4983 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 50000);
4984 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
4986 ret
= sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_MIN_FREQ_TABLE
, 0);
4988 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
4990 ret
= sandybridge_pcode_read(dev_priv
, GEN6_READ_OC_PARAMS
, &pcu_mbox
);
4991 if (!ret
&& (pcu_mbox
& (1<<31))) { /* OC supported */
4992 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
4993 (dev_priv
->rps
.max_freq_softlimit
& 0xff) * 50,
4994 (pcu_mbox
& 0xff) * 50);
4995 dev_priv
->rps
.max_freq
= pcu_mbox
& 0xff;
4998 dev_priv
->rps
.power
= HIGH_POWER
; /* force a reset */
4999 gen6_set_rps(dev_priv
->dev
, dev_priv
->rps
.idle_freq
);
5002 ret
= sandybridge_pcode_read(dev_priv
, GEN6_PCODE_READ_RC6VIDS
, &rc6vids
);
5003 if (IS_GEN6(dev
) && ret
) {
5004 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
5005 } else if (IS_GEN6(dev
) && (GEN6_DECODE_RC6_VID(rc6vids
& 0xff) < 450)) {
5006 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5007 GEN6_DECODE_RC6_VID(rc6vids
& 0xff), 450);
5008 rc6vids
&= 0xffff00;
5009 rc6vids
|= GEN6_ENCODE_RC6_VID(450);
5010 ret
= sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_RC6VIDS
, rc6vids
);
5012 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5015 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
5018 static void __gen6_update_ring_freq(struct drm_device
*dev
)
5020 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5022 unsigned int gpu_freq
;
5023 unsigned int max_ia_freq
, min_ring_freq
;
5024 unsigned int max_gpu_freq
, min_gpu_freq
;
5025 int scaling_factor
= 180;
5026 struct cpufreq_policy
*policy
;
5028 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
5030 policy
= cpufreq_cpu_get(0);
5032 max_ia_freq
= policy
->cpuinfo
.max_freq
;
5033 cpufreq_cpu_put(policy
);
5036 * Default to measured freq if none found, PCU will ensure we
5039 max_ia_freq
= tsc_khz
;
5042 /* Convert from kHz to MHz */
5043 max_ia_freq
/= 1000;
5045 min_ring_freq
= I915_READ(DCLK
) & 0xf;
5046 /* convert DDR frequency from units of 266.6MHz to bandwidth */
5047 min_ring_freq
= mult_frac(min_ring_freq
, 8, 3);
5049 if (IS_SKYLAKE(dev
)) {
5050 /* Convert GT frequency to 50 HZ units */
5051 min_gpu_freq
= dev_priv
->rps
.min_freq
/ GEN9_FREQ_SCALER
;
5052 max_gpu_freq
= dev_priv
->rps
.max_freq
/ GEN9_FREQ_SCALER
;
5054 min_gpu_freq
= dev_priv
->rps
.min_freq
;
5055 max_gpu_freq
= dev_priv
->rps
.max_freq
;
5059 * For each potential GPU frequency, load a ring frequency we'd like
5060 * to use for memory access. We do this by specifying the IA frequency
5061 * the PCU should use as a reference to determine the ring frequency.
5063 for (gpu_freq
= max_gpu_freq
; gpu_freq
>= min_gpu_freq
; gpu_freq
--) {
5064 int diff
= max_gpu_freq
- gpu_freq
;
5065 unsigned int ia_freq
= 0, ring_freq
= 0;
5067 if (IS_SKYLAKE(dev
)) {
5069 * ring_freq = 2 * GT. ring_freq is in 100MHz units
5070 * No floor required for ring frequency on SKL.
5072 ring_freq
= gpu_freq
;
5073 } else if (INTEL_INFO(dev
)->gen
>= 8) {
5074 /* max(2 * GT, DDR). NB: GT is 50MHz units */
5075 ring_freq
= max(min_ring_freq
, gpu_freq
);
5076 } else if (IS_HASWELL(dev
)) {
5077 ring_freq
= mult_frac(gpu_freq
, 5, 4);
5078 ring_freq
= max(min_ring_freq
, ring_freq
);
5079 /* leave ia_freq as the default, chosen by cpufreq */
5081 /* On older processors, there is no separate ring
5082 * clock domain, so in order to boost the bandwidth
5083 * of the ring, we need to upclock the CPU (ia_freq).
5085 * For GPU frequencies less than 750MHz,
5086 * just use the lowest ring freq.
5088 if (gpu_freq
< min_freq
)
5091 ia_freq
= max_ia_freq
- ((diff
* scaling_factor
) / 2);
5092 ia_freq
= DIV_ROUND_CLOSEST(ia_freq
, 100);
5095 sandybridge_pcode_write(dev_priv
,
5096 GEN6_PCODE_WRITE_MIN_FREQ_TABLE
,
5097 ia_freq
<< GEN6_PCODE_FREQ_IA_RATIO_SHIFT
|
5098 ring_freq
<< GEN6_PCODE_FREQ_RING_RATIO_SHIFT
|
5103 void gen6_update_ring_freq(struct drm_device
*dev
)
5105 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5107 if (INTEL_INFO(dev
)->gen
< 6 || IS_VALLEYVIEW(dev
))
5110 mutex_lock(&dev_priv
->rps
.hw_lock
);
5111 __gen6_update_ring_freq(dev
);
5112 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5115 static int cherryview_rps_max_freq(struct drm_i915_private
*dev_priv
)
5117 struct drm_device
*dev
= dev_priv
->dev
;
5120 if (dev
->pdev
->revision
>= 0x20) {
5121 val
= vlv_punit_read(dev_priv
, FB_GFX_FMAX_AT_VMAX_FUSE
);
5123 switch (INTEL_INFO(dev
)->eu_total
) {
5125 /* (2 * 4) config */
5126 rp0
= (val
>> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT
);
5129 /* (2 * 6) config */
5130 rp0
= (val
>> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT
);
5133 /* (2 * 8) config */
5135 /* Setting (2 * 8) Min RP0 for any other combination */
5136 rp0
= (val
>> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT
);
5139 rp0
= (rp0
& FB_GFX_FREQ_FUSE_MASK
);
5141 /* For pre-production hardware */
5142 val
= vlv_punit_read(dev_priv
, PUNIT_GPU_STATUS_REG
);
5143 rp0
= (val
>> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT
) &
5144 PUNIT_GPU_STATUS_MAX_FREQ_MASK
;
5149 static int cherryview_rps_rpe_freq(struct drm_i915_private
*dev_priv
)
5153 val
= vlv_punit_read(dev_priv
, PUNIT_GPU_DUTYCYCLE_REG
);
5154 rpe
= (val
>> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT
) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK
;
5159 static int cherryview_rps_guar_freq(struct drm_i915_private
*dev_priv
)
5161 struct drm_device
*dev
= dev_priv
->dev
;
5164 if (dev
->pdev
->revision
>= 0x20) {
5165 val
= vlv_punit_read(dev_priv
, FB_GFX_FMAX_AT_VMAX_FUSE
);
5166 rp1
= (val
& FB_GFX_FREQ_FUSE_MASK
);
5168 /* For pre-production hardware */
5169 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
5170 rp1
= ((val
>> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT
) &
5171 PUNIT_GPU_STATUS_MAX_FREQ_MASK
);
5176 static int valleyview_rps_guar_freq(struct drm_i915_private
*dev_priv
)
5180 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FREQ_FUSE
);
5182 rp1
= (val
& FB_GFX_FGUARANTEED_FREQ_FUSE_MASK
) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT
;
5187 static int valleyview_rps_max_freq(struct drm_i915_private
*dev_priv
)
5191 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FREQ_FUSE
);
5193 rp0
= (val
& FB_GFX_MAX_FREQ_FUSE_MASK
) >> FB_GFX_MAX_FREQ_FUSE_SHIFT
;
5195 rp0
= min_t(u32
, rp0
, 0xea);
5200 static int valleyview_rps_rpe_freq(struct drm_i915_private
*dev_priv
)
5204 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FMAX_FUSE_LO
);
5205 rpe
= (val
& FB_FMAX_VMIN_FREQ_LO_MASK
) >> FB_FMAX_VMIN_FREQ_LO_SHIFT
;
5206 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FMAX_FUSE_HI
);
5207 rpe
|= (val
& FB_FMAX_VMIN_FREQ_HI_MASK
) << 5;
5212 static int valleyview_rps_min_freq(struct drm_i915_private
*dev_priv
)
5214 return vlv_punit_read(dev_priv
, PUNIT_REG_GPU_LFM
) & 0xff;
5217 /* Check that the pctx buffer wasn't move under us. */
5218 static void valleyview_check_pctx(struct drm_i915_private
*dev_priv
)
5220 unsigned long pctx_addr
= I915_READ(VLV_PCBR
) & ~4095;
5222 WARN_ON(pctx_addr
!= dev_priv
->mm
.stolen_base
+
5223 dev_priv
->vlv_pctx
->stolen
->start
);
5227 /* Check that the pcbr address is not empty. */
5228 static void cherryview_check_pctx(struct drm_i915_private
*dev_priv
)
5230 unsigned long pctx_addr
= I915_READ(VLV_PCBR
) & ~4095;
5232 WARN_ON((pctx_addr
>> VLV_PCBR_ADDR_SHIFT
) == 0);
5235 static void cherryview_setup_pctx(struct drm_device
*dev
)
5237 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5238 unsigned long pctx_paddr
, paddr
;
5239 struct i915_gtt
*gtt
= &dev_priv
->gtt
;
5241 int pctx_size
= 32*1024;
5243 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
5245 pcbr
= I915_READ(VLV_PCBR
);
5246 if ((pcbr
>> VLV_PCBR_ADDR_SHIFT
) == 0) {
5247 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5248 paddr
= (dev_priv
->mm
.stolen_base
+
5249 (gtt
->stolen_size
- pctx_size
));
5251 pctx_paddr
= (paddr
& (~4095));
5252 I915_WRITE(VLV_PCBR
, pctx_paddr
);
5255 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR
));
5258 static void valleyview_setup_pctx(struct drm_device
*dev
)
5260 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5261 struct drm_i915_gem_object
*pctx
;
5262 unsigned long pctx_paddr
;
5264 int pctx_size
= 24*1024;
5266 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
5268 pcbr
= I915_READ(VLV_PCBR
);
5270 /* BIOS set it up already, grab the pre-alloc'd space */
5273 pcbr_offset
= (pcbr
& (~4095)) - dev_priv
->mm
.stolen_base
;
5274 pctx
= i915_gem_object_create_stolen_for_preallocated(dev_priv
->dev
,
5276 I915_GTT_OFFSET_NONE
,
5281 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5284 * From the Gunit register HAS:
5285 * The Gfx driver is expected to program this register and ensure
5286 * proper allocation within Gfx stolen memory. For example, this
5287 * register should be programmed such than the PCBR range does not
5288 * overlap with other ranges, such as the frame buffer, protected
5289 * memory, or any other relevant ranges.
5291 pctx
= i915_gem_object_create_stolen(dev
, pctx_size
);
5293 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
5297 pctx_paddr
= dev_priv
->mm
.stolen_base
+ pctx
->stolen
->start
;
5298 I915_WRITE(VLV_PCBR
, pctx_paddr
);
5301 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR
));
5302 dev_priv
->vlv_pctx
= pctx
;
5305 static void valleyview_cleanup_pctx(struct drm_device
*dev
)
5307 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5309 if (WARN_ON(!dev_priv
->vlv_pctx
))
5312 drm_gem_object_unreference(&dev_priv
->vlv_pctx
->base
);
5313 dev_priv
->vlv_pctx
= NULL
;
5316 static void valleyview_init_gt_powersave(struct drm_device
*dev
)
5318 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5321 valleyview_setup_pctx(dev
);
5323 mutex_lock(&dev_priv
->rps
.hw_lock
);
5325 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
5326 switch ((val
>> 6) & 3) {
5329 dev_priv
->mem_freq
= 800;
5332 dev_priv
->mem_freq
= 1066;
5335 dev_priv
->mem_freq
= 1333;
5338 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv
->mem_freq
);
5340 dev_priv
->rps
.max_freq
= valleyview_rps_max_freq(dev_priv
);
5341 dev_priv
->rps
.rp0_freq
= dev_priv
->rps
.max_freq
;
5342 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5343 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
),
5344 dev_priv
->rps
.max_freq
);
5346 dev_priv
->rps
.efficient_freq
= valleyview_rps_rpe_freq(dev_priv
);
5347 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5348 intel_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
),
5349 dev_priv
->rps
.efficient_freq
);
5351 dev_priv
->rps
.rp1_freq
= valleyview_rps_guar_freq(dev_priv
);
5352 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
5353 intel_gpu_freq(dev_priv
, dev_priv
->rps
.rp1_freq
),
5354 dev_priv
->rps
.rp1_freq
);
5356 dev_priv
->rps
.min_freq
= valleyview_rps_min_freq(dev_priv
);
5357 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5358 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
),
5359 dev_priv
->rps
.min_freq
);
5361 dev_priv
->rps
.idle_freq
= dev_priv
->rps
.min_freq
;
5363 /* Preserve min/max settings in case of re-init */
5364 if (dev_priv
->rps
.max_freq_softlimit
== 0)
5365 dev_priv
->rps
.max_freq_softlimit
= dev_priv
->rps
.max_freq
;
5367 if (dev_priv
->rps
.min_freq_softlimit
== 0)
5368 dev_priv
->rps
.min_freq_softlimit
= dev_priv
->rps
.min_freq
;
5370 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5373 static void cherryview_init_gt_powersave(struct drm_device
*dev
)
5375 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5378 cherryview_setup_pctx(dev
);
5380 mutex_lock(&dev_priv
->rps
.hw_lock
);
5382 mutex_lock(&dev_priv
->sb_lock
);
5383 val
= vlv_cck_read(dev_priv
, CCK_FUSE_REG
);
5384 mutex_unlock(&dev_priv
->sb_lock
);
5386 switch ((val
>> 2) & 0x7) {
5389 dev_priv
->rps
.cz_freq
= 200;
5390 dev_priv
->mem_freq
= 1600;
5393 dev_priv
->rps
.cz_freq
= 267;
5394 dev_priv
->mem_freq
= 1600;
5397 dev_priv
->rps
.cz_freq
= 333;
5398 dev_priv
->mem_freq
= 2000;
5401 dev_priv
->rps
.cz_freq
= 320;
5402 dev_priv
->mem_freq
= 1600;
5405 dev_priv
->rps
.cz_freq
= 400;
5406 dev_priv
->mem_freq
= 1600;
5409 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv
->mem_freq
);
5411 dev_priv
->rps
.max_freq
= cherryview_rps_max_freq(dev_priv
);
5412 dev_priv
->rps
.rp0_freq
= dev_priv
->rps
.max_freq
;
5413 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5414 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
),
5415 dev_priv
->rps
.max_freq
);
5417 dev_priv
->rps
.efficient_freq
= cherryview_rps_rpe_freq(dev_priv
);
5418 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5419 intel_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
),
5420 dev_priv
->rps
.efficient_freq
);
5422 dev_priv
->rps
.rp1_freq
= cherryview_rps_guar_freq(dev_priv
);
5423 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
5424 intel_gpu_freq(dev_priv
, dev_priv
->rps
.rp1_freq
),
5425 dev_priv
->rps
.rp1_freq
);
5427 /* PUnit validated range is only [RPe, RP0] */
5428 dev_priv
->rps
.min_freq
= dev_priv
->rps
.efficient_freq
;
5429 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5430 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
),
5431 dev_priv
->rps
.min_freq
);
5433 WARN_ONCE((dev_priv
->rps
.max_freq
|
5434 dev_priv
->rps
.efficient_freq
|
5435 dev_priv
->rps
.rp1_freq
|
5436 dev_priv
->rps
.min_freq
) & 1,
5437 "Odd GPU freq values\n");
5439 dev_priv
->rps
.idle_freq
= dev_priv
->rps
.min_freq
;
5441 /* Preserve min/max settings in case of re-init */
5442 if (dev_priv
->rps
.max_freq_softlimit
== 0)
5443 dev_priv
->rps
.max_freq_softlimit
= dev_priv
->rps
.max_freq
;
5445 if (dev_priv
->rps
.min_freq_softlimit
== 0)
5446 dev_priv
->rps
.min_freq_softlimit
= dev_priv
->rps
.min_freq
;
5448 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5451 static void valleyview_cleanup_gt_powersave(struct drm_device
*dev
)
5453 valleyview_cleanup_pctx(dev
);
5456 static void cherryview_enable_rps(struct drm_device
*dev
)
5458 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5459 struct intel_engine_cs
*ring
;
5460 u32 gtfifodbg
, val
, rc6_mode
= 0, pcbr
;
5463 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
5465 gtfifodbg
= I915_READ(GTFIFODBG
);
5467 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5469 I915_WRITE(GTFIFODBG
, gtfifodbg
);
5472 cherryview_check_pctx(dev_priv
);
5474 /* 1a & 1b: Get forcewake during program sequence. Although the driver
5475 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5476 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
5478 /* Disable RC states. */
5479 I915_WRITE(GEN6_RC_CONTROL
, 0);
5481 /* 2a: Program RC6 thresholds.*/
5482 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 40 << 16);
5483 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000); /* 12500 * 1280ns */
5484 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25); /* 25 * 1280ns */
5486 for_each_ring(ring
, dev_priv
, i
)
5487 I915_WRITE(RING_MAX_IDLE(ring
->mmio_base
), 10);
5488 I915_WRITE(GEN6_RC_SLEEP
, 0);
5490 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
5491 I915_WRITE(GEN6_RC6_THRESHOLD
, 0x186);
5493 /* allows RC6 residency counter to work */
5494 I915_WRITE(VLV_COUNTER_CONTROL
,
5495 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH
|
5496 VLV_MEDIA_RC6_COUNT_EN
|
5497 VLV_RENDER_RC6_COUNT_EN
));
5499 /* For now we assume BIOS is allocating and populating the PCBR */
5500 pcbr
= I915_READ(VLV_PCBR
);
5503 if ((intel_enable_rc6(dev
) & INTEL_RC6_ENABLE
) &&
5504 (pcbr
>> VLV_PCBR_ADDR_SHIFT
))
5505 rc6_mode
= GEN7_RC_CTL_TO_MODE
;
5507 I915_WRITE(GEN6_RC_CONTROL
, rc6_mode
);
5509 /* 4 Program defaults and thresholds for RPS*/
5510 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 1000000);
5511 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 59400);
5512 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 245000);
5513 I915_WRITE(GEN6_RP_UP_EI
, 66000);
5514 I915_WRITE(GEN6_RP_DOWN_EI
, 350000);
5516 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
5519 I915_WRITE(GEN6_RP_CONTROL
,
5520 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
5521 GEN6_RP_MEDIA_IS_GFX
|
5523 GEN6_RP_UP_BUSY_AVG
|
5524 GEN6_RP_DOWN_IDLE_AVG
);
5526 /* Setting Fixed Bias */
5527 val
= VLV_OVERRIDE_EN
|
5529 CHV_BIAS_CPU_50_SOC_50
;
5530 vlv_punit_write(dev_priv
, VLV_TURBO_SOC_OVERRIDE
, val
);
5532 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
5534 /* RPS code assumes GPLL is used */
5535 WARN_ONCE((val
& GPLLENABLE
) == 0, "GPLL not enabled\n");
5537 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val
& GPLLENABLE
? "yes" : "no");
5538 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val
);
5540 dev_priv
->rps
.cur_freq
= (val
>> 8) & 0xff;
5541 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5542 intel_gpu_freq(dev_priv
, dev_priv
->rps
.cur_freq
),
5543 dev_priv
->rps
.cur_freq
);
5545 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5546 intel_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
),
5547 dev_priv
->rps
.efficient_freq
);
5549 valleyview_set_rps(dev_priv
->dev
, dev_priv
->rps
.efficient_freq
);
5551 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
5554 static void valleyview_enable_rps(struct drm_device
*dev
)
5556 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5557 struct intel_engine_cs
*ring
;
5558 u32 gtfifodbg
, val
, rc6_mode
= 0;
5561 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
5563 valleyview_check_pctx(dev_priv
);
5565 if ((gtfifodbg
= I915_READ(GTFIFODBG
))) {
5566 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5568 I915_WRITE(GTFIFODBG
, gtfifodbg
);
5571 /* If VLV, Forcewake all wells, else re-direct to regular path */
5572 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
5574 /* Disable RC states. */
5575 I915_WRITE(GEN6_RC_CONTROL
, 0);
5577 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 1000000);
5578 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 59400);
5579 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 245000);
5580 I915_WRITE(GEN6_RP_UP_EI
, 66000);
5581 I915_WRITE(GEN6_RP_DOWN_EI
, 350000);
5583 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
5585 I915_WRITE(GEN6_RP_CONTROL
,
5586 GEN6_RP_MEDIA_TURBO
|
5587 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
5588 GEN6_RP_MEDIA_IS_GFX
|
5590 GEN6_RP_UP_BUSY_AVG
|
5591 GEN6_RP_DOWN_IDLE_CONT
);
5593 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 0x00280000);
5594 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000);
5595 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25);
5597 for_each_ring(ring
, dev_priv
, i
)
5598 I915_WRITE(RING_MAX_IDLE(ring
->mmio_base
), 10);
5600 I915_WRITE(GEN6_RC6_THRESHOLD
, 0x557);
5602 /* allows RC6 residency counter to work */
5603 I915_WRITE(VLV_COUNTER_CONTROL
,
5604 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN
|
5605 VLV_RENDER_RC0_COUNT_EN
|
5606 VLV_MEDIA_RC6_COUNT_EN
|
5607 VLV_RENDER_RC6_COUNT_EN
));
5609 if (intel_enable_rc6(dev
) & INTEL_RC6_ENABLE
)
5610 rc6_mode
= GEN7_RC_CTL_TO_MODE
| VLV_RC_CTL_CTX_RST_PARALLEL
;
5612 intel_print_rc6_info(dev
, rc6_mode
);
5614 I915_WRITE(GEN6_RC_CONTROL
, rc6_mode
);
5616 /* Setting Fixed Bias */
5617 val
= VLV_OVERRIDE_EN
|
5619 VLV_BIAS_CPU_125_SOC_875
;
5620 vlv_punit_write(dev_priv
, VLV_TURBO_SOC_OVERRIDE
, val
);
5622 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
5624 /* RPS code assumes GPLL is used */
5625 WARN_ONCE((val
& GPLLENABLE
) == 0, "GPLL not enabled\n");
5627 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val
& GPLLENABLE
? "yes" : "no");
5628 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val
);
5630 dev_priv
->rps
.cur_freq
= (val
>> 8) & 0xff;
5631 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5632 intel_gpu_freq(dev_priv
, dev_priv
->rps
.cur_freq
),
5633 dev_priv
->rps
.cur_freq
);
5635 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5636 intel_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
),
5637 dev_priv
->rps
.efficient_freq
);
5639 valleyview_set_rps(dev_priv
->dev
, dev_priv
->rps
.efficient_freq
);
5641 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
5644 static unsigned long intel_pxfreq(u32 vidfreq
)
5647 int div
= (vidfreq
& 0x3f0000) >> 16;
5648 int post
= (vidfreq
& 0x3000) >> 12;
5649 int pre
= (vidfreq
& 0x7);
5654 freq
= ((div
* 133333) / ((1<<post
) * pre
));
5659 static const struct cparams
{
5665 { 1, 1333, 301, 28664 },
5666 { 1, 1066, 294, 24460 },
5667 { 1, 800, 294, 25192 },
5668 { 0, 1333, 276, 27605 },
5669 { 0, 1066, 276, 27605 },
5670 { 0, 800, 231, 23784 },
5673 static unsigned long __i915_chipset_val(struct drm_i915_private
*dev_priv
)
5675 u64 total_count
, diff
, ret
;
5676 u32 count1
, count2
, count3
, m
= 0, c
= 0;
5677 unsigned long now
= jiffies_to_msecs(jiffies
), diff1
;
5680 assert_spin_locked(&mchdev_lock
);
5682 diff1
= now
- dev_priv
->ips
.last_time1
;
5684 /* Prevent division-by-zero if we are asking too fast.
5685 * Also, we don't get interesting results if we are polling
5686 * faster than once in 10ms, so just return the saved value
5690 return dev_priv
->ips
.chipset_power
;
5692 count1
= I915_READ(DMIEC
);
5693 count2
= I915_READ(DDREC
);
5694 count3
= I915_READ(CSIEC
);
5696 total_count
= count1
+ count2
+ count3
;
5698 /* FIXME: handle per-counter overflow */
5699 if (total_count
< dev_priv
->ips
.last_count1
) {
5700 diff
= ~0UL - dev_priv
->ips
.last_count1
;
5701 diff
+= total_count
;
5703 diff
= total_count
- dev_priv
->ips
.last_count1
;
5706 for (i
= 0; i
< ARRAY_SIZE(cparams
); i
++) {
5707 if (cparams
[i
].i
== dev_priv
->ips
.c_m
&&
5708 cparams
[i
].t
== dev_priv
->ips
.r_t
) {
5715 diff
= div_u64(diff
, diff1
);
5716 ret
= ((m
* diff
) + c
);
5717 ret
= div_u64(ret
, 10);
5719 dev_priv
->ips
.last_count1
= total_count
;
5720 dev_priv
->ips
.last_time1
= now
;
5722 dev_priv
->ips
.chipset_power
= ret
;
5727 unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
)
5729 struct drm_device
*dev
= dev_priv
->dev
;
5732 if (INTEL_INFO(dev
)->gen
!= 5)
5735 spin_lock_irq(&mchdev_lock
);
5737 val
= __i915_chipset_val(dev_priv
);
5739 spin_unlock_irq(&mchdev_lock
);
5744 unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
)
5746 unsigned long m
, x
, b
;
5749 tsfs
= I915_READ(TSFS
);
5751 m
= ((tsfs
& TSFS_SLOPE_MASK
) >> TSFS_SLOPE_SHIFT
);
5752 x
= I915_READ8(TR1
);
5754 b
= tsfs
& TSFS_INTR_MASK
;
5756 return ((m
* x
) / 127) - b
;
5759 static int _pxvid_to_vd(u8 pxvid
)
5764 if (pxvid
>= 8 && pxvid
< 31)
5767 return (pxvid
+ 2) * 125;
5770 static u32
pvid_to_extvid(struct drm_i915_private
*dev_priv
, u8 pxvid
)
5772 struct drm_device
*dev
= dev_priv
->dev
;
5773 const int vd
= _pxvid_to_vd(pxvid
);
5774 const int vm
= vd
- 1125;
5776 if (INTEL_INFO(dev
)->is_mobile
)
5777 return vm
> 0 ? vm
: 0;
5782 static void __i915_update_gfx_val(struct drm_i915_private
*dev_priv
)
5784 u64 now
, diff
, diffms
;
5787 assert_spin_locked(&mchdev_lock
);
5789 now
= ktime_get_raw_ns();
5790 diffms
= now
- dev_priv
->ips
.last_time2
;
5791 do_div(diffms
, NSEC_PER_MSEC
);
5793 /* Don't divide by 0 */
5797 count
= I915_READ(GFXEC
);
5799 if (count
< dev_priv
->ips
.last_count2
) {
5800 diff
= ~0UL - dev_priv
->ips
.last_count2
;
5803 diff
= count
- dev_priv
->ips
.last_count2
;
5806 dev_priv
->ips
.last_count2
= count
;
5807 dev_priv
->ips
.last_time2
= now
;
5809 /* More magic constants... */
5811 diff
= div_u64(diff
, diffms
* 10);
5812 dev_priv
->ips
.gfx_power
= diff
;
5815 void i915_update_gfx_val(struct drm_i915_private
*dev_priv
)
5817 struct drm_device
*dev
= dev_priv
->dev
;
5819 if (INTEL_INFO(dev
)->gen
!= 5)
5822 spin_lock_irq(&mchdev_lock
);
5824 __i915_update_gfx_val(dev_priv
);
5826 spin_unlock_irq(&mchdev_lock
);
5829 static unsigned long __i915_gfx_val(struct drm_i915_private
*dev_priv
)
5831 unsigned long t
, corr
, state1
, corr2
, state2
;
5834 assert_spin_locked(&mchdev_lock
);
5836 pxvid
= I915_READ(PXVFREQ_BASE
+ (dev_priv
->rps
.cur_freq
* 4));
5837 pxvid
= (pxvid
>> 24) & 0x7f;
5838 ext_v
= pvid_to_extvid(dev_priv
, pxvid
);
5842 t
= i915_mch_val(dev_priv
);
5844 /* Revel in the empirically derived constants */
5846 /* Correction factor in 1/100000 units */
5848 corr
= ((t
* 2349) + 135940);
5850 corr
= ((t
* 964) + 29317);
5852 corr
= ((t
* 301) + 1004);
5854 corr
= corr
* ((150142 * state1
) / 10000 - 78642);
5856 corr2
= (corr
* dev_priv
->ips
.corr
);
5858 state2
= (corr2
* state1
) / 10000;
5859 state2
/= 100; /* convert to mW */
5861 __i915_update_gfx_val(dev_priv
);
5863 return dev_priv
->ips
.gfx_power
+ state2
;
5866 unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
)
5868 struct drm_device
*dev
= dev_priv
->dev
;
5871 if (INTEL_INFO(dev
)->gen
!= 5)
5874 spin_lock_irq(&mchdev_lock
);
5876 val
= __i915_gfx_val(dev_priv
);
5878 spin_unlock_irq(&mchdev_lock
);
5884 * i915_read_mch_val - return value for IPS use
5886 * Calculate and return a value for the IPS driver to use when deciding whether
5887 * we have thermal and power headroom to increase CPU or GPU power budget.
5889 unsigned long i915_read_mch_val(void)
5891 struct drm_i915_private
*dev_priv
;
5892 unsigned long chipset_val
, graphics_val
, ret
= 0;
5894 spin_lock_irq(&mchdev_lock
);
5897 dev_priv
= i915_mch_dev
;
5899 chipset_val
= __i915_chipset_val(dev_priv
);
5900 graphics_val
= __i915_gfx_val(dev_priv
);
5902 ret
= chipset_val
+ graphics_val
;
5905 spin_unlock_irq(&mchdev_lock
);
5909 EXPORT_SYMBOL_GPL(i915_read_mch_val
);
5912 * i915_gpu_raise - raise GPU frequency limit
5914 * Raise the limit; IPS indicates we have thermal headroom.
5916 bool i915_gpu_raise(void)
5918 struct drm_i915_private
*dev_priv
;
5921 spin_lock_irq(&mchdev_lock
);
5922 if (!i915_mch_dev
) {
5926 dev_priv
= i915_mch_dev
;
5928 if (dev_priv
->ips
.max_delay
> dev_priv
->ips
.fmax
)
5929 dev_priv
->ips
.max_delay
--;
5932 spin_unlock_irq(&mchdev_lock
);
5936 EXPORT_SYMBOL_GPL(i915_gpu_raise
);
5939 * i915_gpu_lower - lower GPU frequency limit
5941 * IPS indicates we're close to a thermal limit, so throttle back the GPU
5942 * frequency maximum.
5944 bool i915_gpu_lower(void)
5946 struct drm_i915_private
*dev_priv
;
5949 spin_lock_irq(&mchdev_lock
);
5950 if (!i915_mch_dev
) {
5954 dev_priv
= i915_mch_dev
;
5956 if (dev_priv
->ips
.max_delay
< dev_priv
->ips
.min_delay
)
5957 dev_priv
->ips
.max_delay
++;
5960 spin_unlock_irq(&mchdev_lock
);
5964 EXPORT_SYMBOL_GPL(i915_gpu_lower
);
5967 * i915_gpu_busy - indicate GPU business to IPS
5969 * Tell the IPS driver whether or not the GPU is busy.
5971 bool i915_gpu_busy(void)
5973 struct drm_i915_private
*dev_priv
;
5974 struct intel_engine_cs
*ring
;
5978 spin_lock_irq(&mchdev_lock
);
5981 dev_priv
= i915_mch_dev
;
5983 for_each_ring(ring
, dev_priv
, i
)
5984 ret
|= !list_empty(&ring
->request_list
);
5987 spin_unlock_irq(&mchdev_lock
);
5991 EXPORT_SYMBOL_GPL(i915_gpu_busy
);
5994 * i915_gpu_turbo_disable - disable graphics turbo
5996 * Disable graphics turbo by resetting the max frequency and setting the
5997 * current frequency to the default.
5999 bool i915_gpu_turbo_disable(void)
6001 struct drm_i915_private
*dev_priv
;
6004 spin_lock_irq(&mchdev_lock
);
6005 if (!i915_mch_dev
) {
6009 dev_priv
= i915_mch_dev
;
6011 dev_priv
->ips
.max_delay
= dev_priv
->ips
.fstart
;
6013 if (!ironlake_set_drps(dev_priv
->dev
, dev_priv
->ips
.fstart
))
6017 spin_unlock_irq(&mchdev_lock
);
6021 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable
);
6024 * Tells the intel_ips driver that the i915 driver is now loaded, if
6025 * IPS got loaded first.
6027 * This awkward dance is so that neither module has to depend on the
6028 * other in order for IPS to do the appropriate communication of
6029 * GPU turbo limits to i915.
6032 ips_ping_for_i915_load(void)
6036 link
= symbol_get(ips_link_to_i915_driver
);
6039 symbol_put(ips_link_to_i915_driver
);
6043 void intel_gpu_ips_init(struct drm_i915_private
*dev_priv
)
6045 /* We only register the i915 ips part with intel-ips once everything is
6046 * set up, to avoid intel-ips sneaking in and reading bogus values. */
6047 spin_lock_irq(&mchdev_lock
);
6048 i915_mch_dev
= dev_priv
;
6049 spin_unlock_irq(&mchdev_lock
);
6051 ips_ping_for_i915_load();
6054 void intel_gpu_ips_teardown(void)
6056 spin_lock_irq(&mchdev_lock
);
6057 i915_mch_dev
= NULL
;
6058 spin_unlock_irq(&mchdev_lock
);
6061 static void intel_init_emon(struct drm_device
*dev
)
6063 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6068 /* Disable to program */
6072 /* Program energy weights for various events */
6073 I915_WRITE(SDEW
, 0x15040d00);
6074 I915_WRITE(CSIEW0
, 0x007f0000);
6075 I915_WRITE(CSIEW1
, 0x1e220004);
6076 I915_WRITE(CSIEW2
, 0x04000004);
6078 for (i
= 0; i
< 5; i
++)
6079 I915_WRITE(PEW
+ (i
* 4), 0);
6080 for (i
= 0; i
< 3; i
++)
6081 I915_WRITE(DEW
+ (i
* 4), 0);
6083 /* Program P-state weights to account for frequency power adjustment */
6084 for (i
= 0; i
< 16; i
++) {
6085 u32 pxvidfreq
= I915_READ(PXVFREQ_BASE
+ (i
* 4));
6086 unsigned long freq
= intel_pxfreq(pxvidfreq
);
6087 unsigned long vid
= (pxvidfreq
& PXVFREQ_PX_MASK
) >>
6092 val
*= (freq
/ 1000);
6094 val
/= (127*127*900);
6096 DRM_ERROR("bad pxval: %ld\n", val
);
6099 /* Render standby states get 0 weight */
6103 for (i
= 0; i
< 4; i
++) {
6104 u32 val
= (pxw
[i
*4] << 24) | (pxw
[(i
*4)+1] << 16) |
6105 (pxw
[(i
*4)+2] << 8) | (pxw
[(i
*4)+3]);
6106 I915_WRITE(PXW
+ (i
* 4), val
);
6109 /* Adjust magic regs to magic values (more experimental results) */
6110 I915_WRITE(OGW0
, 0);
6111 I915_WRITE(OGW1
, 0);
6112 I915_WRITE(EG0
, 0x00007f00);
6113 I915_WRITE(EG1
, 0x0000000e);
6114 I915_WRITE(EG2
, 0x000e0000);
6115 I915_WRITE(EG3
, 0x68000300);
6116 I915_WRITE(EG4
, 0x42000000);
6117 I915_WRITE(EG5
, 0x00140031);
6121 for (i
= 0; i
< 8; i
++)
6122 I915_WRITE(PXWL
+ (i
* 4), 0);
6124 /* Enable PMON + select events */
6125 I915_WRITE(ECR
, 0x80000019);
6127 lcfuse
= I915_READ(LCFUSE02
);
6129 dev_priv
->ips
.corr
= (lcfuse
& LCFUSE_HIV_MASK
);
6132 void intel_init_gt_powersave(struct drm_device
*dev
)
6134 i915
.enable_rc6
= sanitize_rc6_option(dev
, i915
.enable_rc6
);
6136 if (IS_CHERRYVIEW(dev
))
6137 cherryview_init_gt_powersave(dev
);
6138 else if (IS_VALLEYVIEW(dev
))
6139 valleyview_init_gt_powersave(dev
);
6142 void intel_cleanup_gt_powersave(struct drm_device
*dev
)
6144 if (IS_CHERRYVIEW(dev
))
6146 else if (IS_VALLEYVIEW(dev
))
6147 valleyview_cleanup_gt_powersave(dev
);
6150 static void gen6_suspend_rps(struct drm_device
*dev
)
6152 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6154 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
6156 gen6_disable_rps_interrupts(dev
);
6160 * intel_suspend_gt_powersave - suspend PM work and helper threads
6163 * We don't want to disable RC6 or other features here, we just want
6164 * to make sure any work we've queued has finished and won't bother
6165 * us while we're suspended.
6167 void intel_suspend_gt_powersave(struct drm_device
*dev
)
6169 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6171 if (INTEL_INFO(dev
)->gen
< 6)
6174 gen6_suspend_rps(dev
);
6176 /* Force GPU to min freq during suspend */
6177 gen6_rps_idle(dev_priv
);
6180 void intel_disable_gt_powersave(struct drm_device
*dev
)
6182 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6184 if (IS_IRONLAKE_M(dev
)) {
6185 ironlake_disable_drps(dev
);
6186 } else if (INTEL_INFO(dev
)->gen
>= 6) {
6187 intel_suspend_gt_powersave(dev
);
6189 mutex_lock(&dev_priv
->rps
.hw_lock
);
6190 if (INTEL_INFO(dev
)->gen
>= 9)
6191 gen9_disable_rps(dev
);
6192 else if (IS_CHERRYVIEW(dev
))
6193 cherryview_disable_rps(dev
);
6194 else if (IS_VALLEYVIEW(dev
))
6195 valleyview_disable_rps(dev
);
6197 gen6_disable_rps(dev
);
6199 dev_priv
->rps
.enabled
= false;
6200 mutex_unlock(&dev_priv
->rps
.hw_lock
);
6204 static void intel_gen6_powersave_work(struct work_struct
*work
)
6206 struct drm_i915_private
*dev_priv
=
6207 container_of(work
, struct drm_i915_private
,
6208 rps
.delayed_resume_work
.work
);
6209 struct drm_device
*dev
= dev_priv
->dev
;
6211 mutex_lock(&dev_priv
->rps
.hw_lock
);
6213 gen6_reset_rps_interrupts(dev
);
6215 if (IS_CHERRYVIEW(dev
)) {
6216 cherryview_enable_rps(dev
);
6217 } else if (IS_VALLEYVIEW(dev
)) {
6218 valleyview_enable_rps(dev
);
6219 } else if (INTEL_INFO(dev
)->gen
>= 9) {
6220 gen9_enable_rc6(dev
);
6221 gen9_enable_rps(dev
);
6222 __gen6_update_ring_freq(dev
);
6223 } else if (IS_BROADWELL(dev
)) {
6224 gen8_enable_rps(dev
);
6225 __gen6_update_ring_freq(dev
);
6227 gen6_enable_rps(dev
);
6228 __gen6_update_ring_freq(dev
);
6231 WARN_ON(dev_priv
->rps
.max_freq
< dev_priv
->rps
.min_freq
);
6232 WARN_ON(dev_priv
->rps
.idle_freq
> dev_priv
->rps
.max_freq
);
6234 WARN_ON(dev_priv
->rps
.efficient_freq
< dev_priv
->rps
.min_freq
);
6235 WARN_ON(dev_priv
->rps
.efficient_freq
> dev_priv
->rps
.max_freq
);
6237 dev_priv
->rps
.enabled
= true;
6239 gen6_enable_rps_interrupts(dev
);
6241 mutex_unlock(&dev_priv
->rps
.hw_lock
);
6243 intel_runtime_pm_put(dev_priv
);
6246 void intel_enable_gt_powersave(struct drm_device
*dev
)
6248 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6250 /* Powersaving is controlled by the host when inside a VM */
6251 if (intel_vgpu_active(dev
))
6254 if (IS_IRONLAKE_M(dev
)) {
6255 mutex_lock(&dev
->struct_mutex
);
6256 ironlake_enable_drps(dev
);
6257 intel_init_emon(dev
);
6258 mutex_unlock(&dev
->struct_mutex
);
6259 } else if (INTEL_INFO(dev
)->gen
>= 6) {
6261 * PCU communication is slow and this doesn't need to be
6262 * done at any specific time, so do this out of our fast path
6263 * to make resume and init faster.
6265 * We depend on the HW RC6 power context save/restore
6266 * mechanism when entering D3 through runtime PM suspend. So
6267 * disable RPM until RPS/RC6 is properly setup. We can only
6268 * get here via the driver load/system resume/runtime resume
6269 * paths, so the _noresume version is enough (and in case of
6270 * runtime resume it's necessary).
6272 if (schedule_delayed_work(&dev_priv
->rps
.delayed_resume_work
,
6273 round_jiffies_up_relative(HZ
)))
6274 intel_runtime_pm_get_noresume(dev_priv
);
6278 void intel_reset_gt_powersave(struct drm_device
*dev
)
6280 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6282 if (INTEL_INFO(dev
)->gen
< 6)
6285 gen6_suspend_rps(dev
);
6286 dev_priv
->rps
.enabled
= false;
6289 static void ibx_init_clock_gating(struct drm_device
*dev
)
6291 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6294 * On Ibex Peak and Cougar Point, we need to disable clock
6295 * gating for the panel power sequencer or it will fail to
6296 * start up when no ports are active.
6298 I915_WRITE(SOUTH_DSPCLK_GATE_D
, PCH_DPLSUNIT_CLOCK_GATE_DISABLE
);
6301 static void g4x_disable_trickle_feed(struct drm_device
*dev
)
6303 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6306 for_each_pipe(dev_priv
, pipe
) {
6307 I915_WRITE(DSPCNTR(pipe
),
6308 I915_READ(DSPCNTR(pipe
)) |
6309 DISPPLANE_TRICKLE_FEED_DISABLE
);
6311 I915_WRITE(DSPSURF(pipe
), I915_READ(DSPSURF(pipe
)));
6312 POSTING_READ(DSPSURF(pipe
));
6316 static void ilk_init_lp_watermarks(struct drm_device
*dev
)
6318 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6320 I915_WRITE(WM3_LP_ILK
, I915_READ(WM3_LP_ILK
) & ~WM1_LP_SR_EN
);
6321 I915_WRITE(WM2_LP_ILK
, I915_READ(WM2_LP_ILK
) & ~WM1_LP_SR_EN
);
6322 I915_WRITE(WM1_LP_ILK
, I915_READ(WM1_LP_ILK
) & ~WM1_LP_SR_EN
);
6325 * Don't touch WM1S_LP_EN here.
6326 * Doing so could cause underruns.
6330 static void ironlake_init_clock_gating(struct drm_device
*dev
)
6332 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6333 uint32_t dspclk_gate
= ILK_VRHUNIT_CLOCK_GATE_DISABLE
;
6337 * WaFbcDisableDpfcClockGating:ilk
6339 dspclk_gate
|= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE
|
6340 ILK_DPFCUNIT_CLOCK_GATE_DISABLE
|
6341 ILK_DPFDUNIT_CLOCK_GATE_ENABLE
;
6343 I915_WRITE(PCH_3DCGDIS0
,
6344 MARIUNIT_CLOCK_GATE_DISABLE
|
6345 SVSMUNIT_CLOCK_GATE_DISABLE
);
6346 I915_WRITE(PCH_3DCGDIS1
,
6347 VFMUNIT_CLOCK_GATE_DISABLE
);
6350 * According to the spec the following bits should be set in
6351 * order to enable memory self-refresh
6352 * The bit 22/21 of 0x42004
6353 * The bit 5 of 0x42020
6354 * The bit 15 of 0x45000
6356 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
6357 (I915_READ(ILK_DISPLAY_CHICKEN2
) |
6358 ILK_DPARB_GATE
| ILK_VSDPFD_FULL
));
6359 dspclk_gate
|= ILK_DPARBUNIT_CLOCK_GATE_ENABLE
;
6360 I915_WRITE(DISP_ARB_CTL
,
6361 (I915_READ(DISP_ARB_CTL
) |
6364 ilk_init_lp_watermarks(dev
);
6367 * Based on the document from hardware guys the following bits
6368 * should be set unconditionally in order to enable FBC.
6369 * The bit 22 of 0x42000
6370 * The bit 22 of 0x42004
6371 * The bit 7,8,9 of 0x42020.
6373 if (IS_IRONLAKE_M(dev
)) {
6374 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6375 I915_WRITE(ILK_DISPLAY_CHICKEN1
,
6376 I915_READ(ILK_DISPLAY_CHICKEN1
) |
6378 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
6379 I915_READ(ILK_DISPLAY_CHICKEN2
) |
6383 I915_WRITE(ILK_DSPCLK_GATE_D
, dspclk_gate
);
6385 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
6386 I915_READ(ILK_DISPLAY_CHICKEN2
) |
6387 ILK_ELPIN_409_SELECT
);
6388 I915_WRITE(_3D_CHICKEN2
,
6389 _3D_CHICKEN2_WM_READ_PIPELINED
<< 16 |
6390 _3D_CHICKEN2_WM_READ_PIPELINED
);
6392 /* WaDisableRenderCachePipelinedFlush:ilk */
6393 I915_WRITE(CACHE_MODE_0
,
6394 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE
));
6396 /* WaDisable_RenderCache_OperationalFlush:ilk */
6397 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
6399 g4x_disable_trickle_feed(dev
);
6401 ibx_init_clock_gating(dev
);
6404 static void cpt_init_clock_gating(struct drm_device
*dev
)
6406 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6411 * On Ibex Peak and Cougar Point, we need to disable clock
6412 * gating for the panel power sequencer or it will fail to
6413 * start up when no ports are active.
6415 I915_WRITE(SOUTH_DSPCLK_GATE_D
, PCH_DPLSUNIT_CLOCK_GATE_DISABLE
|
6416 PCH_DPLUNIT_CLOCK_GATE_DISABLE
|
6417 PCH_CPUNIT_CLOCK_GATE_DISABLE
);
6418 I915_WRITE(SOUTH_CHICKEN2
, I915_READ(SOUTH_CHICKEN2
) |
6419 DPLS_EDP_PPS_FIX_DIS
);
6420 /* The below fixes the weird display corruption, a few pixels shifted
6421 * downward, on (only) LVDS of some HP laptops with IVY.
6423 for_each_pipe(dev_priv
, pipe
) {
6424 val
= I915_READ(TRANS_CHICKEN2(pipe
));
6425 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
6426 val
&= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED
;
6427 if (dev_priv
->vbt
.fdi_rx_polarity_inverted
)
6428 val
|= TRANS_CHICKEN2_FDI_POLARITY_REVERSED
;
6429 val
&= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK
;
6430 val
&= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER
;
6431 val
&= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH
;
6432 I915_WRITE(TRANS_CHICKEN2(pipe
), val
);
6434 /* WADP0ClockGatingDisable */
6435 for_each_pipe(dev_priv
, pipe
) {
6436 I915_WRITE(TRANS_CHICKEN1(pipe
),
6437 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE
);
6441 static void gen6_check_mch_setup(struct drm_device
*dev
)
6443 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6446 tmp
= I915_READ(MCH_SSKPD
);
6447 if ((tmp
& MCH_SSKPD_WM0_MASK
) != MCH_SSKPD_WM0_VAL
)
6448 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6452 static void gen6_init_clock_gating(struct drm_device
*dev
)
6454 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6455 uint32_t dspclk_gate
= ILK_VRHUNIT_CLOCK_GATE_DISABLE
;
6457 I915_WRITE(ILK_DSPCLK_GATE_D
, dspclk_gate
);
6459 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
6460 I915_READ(ILK_DISPLAY_CHICKEN2
) |
6461 ILK_ELPIN_409_SELECT
);
6463 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
6464 I915_WRITE(_3D_CHICKEN
,
6465 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB
));
6467 /* WaDisable_RenderCache_OperationalFlush:snb */
6468 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
6471 * BSpec recoomends 8x4 when MSAA is used,
6472 * however in practice 16x4 seems fastest.
6474 * Note that PS/WM thread counts depend on the WIZ hashing
6475 * disable bit, which we don't touch here, but it's good
6476 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6478 I915_WRITE(GEN6_GT_MODE
,
6479 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK
, GEN6_WIZ_HASHING_16x4
));
6481 ilk_init_lp_watermarks(dev
);
6483 I915_WRITE(CACHE_MODE_0
,
6484 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB
));
6486 I915_WRITE(GEN6_UCGCTL1
,
6487 I915_READ(GEN6_UCGCTL1
) |
6488 GEN6_BLBUNIT_CLOCK_GATE_DISABLE
|
6489 GEN6_CSUNIT_CLOCK_GATE_DISABLE
);
6491 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
6492 * gating disable must be set. Failure to set it results in
6493 * flickering pixels due to Z write ordering failures after
6494 * some amount of runtime in the Mesa "fire" demo, and Unigine
6495 * Sanctuary and Tropics, and apparently anything else with
6496 * alpha test or pixel discard.
6498 * According to the spec, bit 11 (RCCUNIT) must also be set,
6499 * but we didn't debug actual testcases to find it out.
6501 * WaDisableRCCUnitClockGating:snb
6502 * WaDisableRCPBUnitClockGating:snb
6504 I915_WRITE(GEN6_UCGCTL2
,
6505 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE
|
6506 GEN6_RCCUNIT_CLOCK_GATE_DISABLE
);
6508 /* WaStripsFansDisableFastClipPerformanceFix:snb */
6509 I915_WRITE(_3D_CHICKEN3
,
6510 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL
));
6514 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
6515 * 3DSTATE_SF number of SF output attributes is more than 16."
6517 I915_WRITE(_3D_CHICKEN3
,
6518 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH
));
6521 * According to the spec the following bits should be
6522 * set in order to enable memory self-refresh and fbc:
6523 * The bit21 and bit22 of 0x42000
6524 * The bit21 and bit22 of 0x42004
6525 * The bit5 and bit7 of 0x42020
6526 * The bit14 of 0x70180
6527 * The bit14 of 0x71180
6529 * WaFbcAsynchFlipDisableFbcQueue:snb
6531 I915_WRITE(ILK_DISPLAY_CHICKEN1
,
6532 I915_READ(ILK_DISPLAY_CHICKEN1
) |
6533 ILK_FBCQ_DIS
| ILK_PABSTRETCH_DIS
);
6534 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
6535 I915_READ(ILK_DISPLAY_CHICKEN2
) |
6536 ILK_DPARB_GATE
| ILK_VSDPFD_FULL
);
6537 I915_WRITE(ILK_DSPCLK_GATE_D
,
6538 I915_READ(ILK_DSPCLK_GATE_D
) |
6539 ILK_DPARBUNIT_CLOCK_GATE_ENABLE
|
6540 ILK_DPFDUNIT_CLOCK_GATE_ENABLE
);
6542 g4x_disable_trickle_feed(dev
);
6544 cpt_init_clock_gating(dev
);
6546 gen6_check_mch_setup(dev
);
6549 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private
*dev_priv
)
6551 uint32_t reg
= I915_READ(GEN7_FF_THREAD_MODE
);
6554 * WaVSThreadDispatchOverride:ivb,vlv
6556 * This actually overrides the dispatch
6557 * mode for all thread types.
6559 reg
&= ~GEN7_FF_SCHED_MASK
;
6560 reg
|= GEN7_FF_TS_SCHED_HW
;
6561 reg
|= GEN7_FF_VS_SCHED_HW
;
6562 reg
|= GEN7_FF_DS_SCHED_HW
;
6564 I915_WRITE(GEN7_FF_THREAD_MODE
, reg
);
6567 static void lpt_init_clock_gating(struct drm_device
*dev
)
6569 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6572 * TODO: this bit should only be enabled when really needed, then
6573 * disabled when not needed anymore in order to save power.
6575 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
)
6576 I915_WRITE(SOUTH_DSPCLK_GATE_D
,
6577 I915_READ(SOUTH_DSPCLK_GATE_D
) |
6578 PCH_LP_PARTITION_LEVEL_DISABLE
);
6580 /* WADPOClockGatingDisable:hsw */
6581 I915_WRITE(_TRANSA_CHICKEN1
,
6582 I915_READ(_TRANSA_CHICKEN1
) |
6583 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE
);
6586 static void lpt_suspend_hw(struct drm_device
*dev
)
6588 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6590 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
6591 uint32_t val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
6593 val
&= ~PCH_LP_PARTITION_LEVEL_DISABLE
;
6594 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
6598 static void broadwell_init_clock_gating(struct drm_device
*dev
)
6600 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6604 ilk_init_lp_watermarks(dev
);
6606 /* WaSwitchSolVfFArbitrationPriority:bdw */
6607 I915_WRITE(GAM_ECOCHK
, I915_READ(GAM_ECOCHK
) | HSW_ECOCHK_ARB_PRIO_SOL
);
6609 /* WaPsrDPAMaskVBlankInSRD:bdw */
6610 I915_WRITE(CHICKEN_PAR1_1
,
6611 I915_READ(CHICKEN_PAR1_1
) | DPA_MASK_VBLANK_SRD
);
6613 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
6614 for_each_pipe(dev_priv
, pipe
) {
6615 I915_WRITE(CHICKEN_PIPESL_1(pipe
),
6616 I915_READ(CHICKEN_PIPESL_1(pipe
)) |
6617 BDW_DPRS_MASK_VBLANK_SRD
);
6620 /* WaVSRefCountFullforceMissDisable:bdw */
6621 /* WaDSRefCountFullforceMissDisable:bdw */
6622 I915_WRITE(GEN7_FF_THREAD_MODE
,
6623 I915_READ(GEN7_FF_THREAD_MODE
) &
6624 ~(GEN8_FF_DS_REF_CNT_FFME
| GEN7_FF_VS_REF_CNT_FFME
));
6626 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL
,
6627 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE
));
6629 /* WaDisableSDEUnitClockGating:bdw */
6630 I915_WRITE(GEN8_UCGCTL6
, I915_READ(GEN8_UCGCTL6
) |
6631 GEN8_SDEUNIT_CLOCK_GATE_DISABLE
);
6634 * WaProgramL3SqcReg1Default:bdw
6635 * WaTempDisableDOPClkGating:bdw
6637 misccpctl
= I915_READ(GEN7_MISCCPCTL
);
6638 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
& ~GEN7_DOP_CLOCK_GATE_ENABLE
);
6639 I915_WRITE(GEN8_L3SQCREG1
, BDW_WA_L3SQCREG1_DEFAULT
);
6640 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
);
6643 * WaGttCachingOffByDefault:bdw
6644 * GTT cache may not work with big pages, so if those
6645 * are ever enabled GTT cache may need to be disabled.
6647 I915_WRITE(HSW_GTT_CACHE_EN
, GTT_CACHE_EN_ALL
);
6649 lpt_init_clock_gating(dev
);
6652 static void haswell_init_clock_gating(struct drm_device
*dev
)
6654 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6656 ilk_init_lp_watermarks(dev
);
6658 /* L3 caching of data atomics doesn't work -- disable it. */
6659 I915_WRITE(HSW_SCRATCH1
, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE
);
6660 I915_WRITE(HSW_ROW_CHICKEN3
,
6661 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE
));
6663 /* This is required by WaCatErrorRejectionIssue:hsw */
6664 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
6665 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
6666 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
6668 /* WaVSRefCountFullforceMissDisable:hsw */
6669 I915_WRITE(GEN7_FF_THREAD_MODE
,
6670 I915_READ(GEN7_FF_THREAD_MODE
) & ~GEN7_FF_VS_REF_CNT_FFME
);
6672 /* WaDisable_RenderCache_OperationalFlush:hsw */
6673 I915_WRITE(CACHE_MODE_0_GEN7
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
6675 /* enable HiZ Raw Stall Optimization */
6676 I915_WRITE(CACHE_MODE_0_GEN7
,
6677 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE
));
6679 /* WaDisable4x2SubspanOptimization:hsw */
6680 I915_WRITE(CACHE_MODE_1
,
6681 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
));
6684 * BSpec recommends 8x4 when MSAA is used,
6685 * however in practice 16x4 seems fastest.
6687 * Note that PS/WM thread counts depend on the WIZ hashing
6688 * disable bit, which we don't touch here, but it's good
6689 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6691 I915_WRITE(GEN7_GT_MODE
,
6692 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK
, GEN6_WIZ_HASHING_16x4
));
6694 /* WaSampleCChickenBitEnable:hsw */
6695 I915_WRITE(HALF_SLICE_CHICKEN3
,
6696 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE
));
6698 /* WaSwitchSolVfFArbitrationPriority:hsw */
6699 I915_WRITE(GAM_ECOCHK
, I915_READ(GAM_ECOCHK
) | HSW_ECOCHK_ARB_PRIO_SOL
);
6701 /* WaRsPkgCStateDisplayPMReq:hsw */
6702 I915_WRITE(CHICKEN_PAR1_1
,
6703 I915_READ(CHICKEN_PAR1_1
) | FORCE_ARB_IDLE_PLANES
);
6705 lpt_init_clock_gating(dev
);
6708 static void ivybridge_init_clock_gating(struct drm_device
*dev
)
6710 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6713 ilk_init_lp_watermarks(dev
);
6715 I915_WRITE(ILK_DSPCLK_GATE_D
, ILK_VRHUNIT_CLOCK_GATE_DISABLE
);
6717 /* WaDisableEarlyCull:ivb */
6718 I915_WRITE(_3D_CHICKEN3
,
6719 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL
));
6721 /* WaDisableBackToBackFlipFix:ivb */
6722 I915_WRITE(IVB_CHICKEN3
,
6723 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE
|
6724 CHICKEN3_DGMG_DONE_FIX_DISABLE
);
6726 /* WaDisablePSDDualDispatchEnable:ivb */
6727 if (IS_IVB_GT1(dev
))
6728 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1
,
6729 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE
));
6731 /* WaDisable_RenderCache_OperationalFlush:ivb */
6732 I915_WRITE(CACHE_MODE_0_GEN7
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
6734 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6735 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1
,
6736 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC
);
6738 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6739 I915_WRITE(GEN7_L3CNTLREG1
,
6740 GEN7_WA_FOR_GEN7_L3_CONTROL
);
6741 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER
,
6742 GEN7_WA_L3_CHICKEN_MODE
);
6743 if (IS_IVB_GT1(dev
))
6744 I915_WRITE(GEN7_ROW_CHICKEN2
,
6745 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
6747 /* must write both registers */
6748 I915_WRITE(GEN7_ROW_CHICKEN2
,
6749 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
6750 I915_WRITE(GEN7_ROW_CHICKEN2_GT2
,
6751 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
6754 /* WaForceL3Serialization:ivb */
6755 I915_WRITE(GEN7_L3SQCREG4
, I915_READ(GEN7_L3SQCREG4
) &
6756 ~L3SQ_URB_READ_CAM_MATCH_DISABLE
);
6759 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6760 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
6762 I915_WRITE(GEN6_UCGCTL2
,
6763 GEN6_RCZUNIT_CLOCK_GATE_DISABLE
);
6765 /* This is required by WaCatErrorRejectionIssue:ivb */
6766 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
6767 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
6768 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
6770 g4x_disable_trickle_feed(dev
);
6772 gen7_setup_fixed_func_scheduler(dev_priv
);
6774 if (0) { /* causes HiZ corruption on ivb:gt1 */
6775 /* enable HiZ Raw Stall Optimization */
6776 I915_WRITE(CACHE_MODE_0_GEN7
,
6777 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE
));
6780 /* WaDisable4x2SubspanOptimization:ivb */
6781 I915_WRITE(CACHE_MODE_1
,
6782 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
));
6785 * BSpec recommends 8x4 when MSAA is used,
6786 * however in practice 16x4 seems fastest.
6788 * Note that PS/WM thread counts depend on the WIZ hashing
6789 * disable bit, which we don't touch here, but it's good
6790 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6792 I915_WRITE(GEN7_GT_MODE
,
6793 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK
, GEN6_WIZ_HASHING_16x4
));
6795 snpcr
= I915_READ(GEN6_MBCUNIT_SNPCR
);
6796 snpcr
&= ~GEN6_MBC_SNPCR_MASK
;
6797 snpcr
|= GEN6_MBC_SNPCR_MED
;
6798 I915_WRITE(GEN6_MBCUNIT_SNPCR
, snpcr
);
6800 if (!HAS_PCH_NOP(dev
))
6801 cpt_init_clock_gating(dev
);
6803 gen6_check_mch_setup(dev
);
6806 static void vlv_init_display_clock_gating(struct drm_i915_private
*dev_priv
)
6808 I915_WRITE(DSPCLK_GATE_D
, VRHUNIT_CLOCK_GATE_DISABLE
);
6811 * Disable trickle feed and enable pnd deadline calculation
6813 I915_WRITE(MI_ARB_VLV
, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
);
6814 I915_WRITE(CBR1_VLV
, 0);
6817 static void valleyview_init_clock_gating(struct drm_device
*dev
)
6819 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6821 vlv_init_display_clock_gating(dev_priv
);
6823 /* WaDisableEarlyCull:vlv */
6824 I915_WRITE(_3D_CHICKEN3
,
6825 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL
));
6827 /* WaDisableBackToBackFlipFix:vlv */
6828 I915_WRITE(IVB_CHICKEN3
,
6829 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE
|
6830 CHICKEN3_DGMG_DONE_FIX_DISABLE
);
6832 /* WaPsdDispatchEnable:vlv */
6833 /* WaDisablePSDDualDispatchEnable:vlv */
6834 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1
,
6835 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP
|
6836 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE
));
6838 /* WaDisable_RenderCache_OperationalFlush:vlv */
6839 I915_WRITE(CACHE_MODE_0_GEN7
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
6841 /* WaForceL3Serialization:vlv */
6842 I915_WRITE(GEN7_L3SQCREG4
, I915_READ(GEN7_L3SQCREG4
) &
6843 ~L3SQ_URB_READ_CAM_MATCH_DISABLE
);
6845 /* WaDisableDopClockGating:vlv */
6846 I915_WRITE(GEN7_ROW_CHICKEN2
,
6847 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
6849 /* This is required by WaCatErrorRejectionIssue:vlv */
6850 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
6851 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
6852 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
6854 gen7_setup_fixed_func_scheduler(dev_priv
);
6857 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6858 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
6860 I915_WRITE(GEN6_UCGCTL2
,
6861 GEN6_RCZUNIT_CLOCK_GATE_DISABLE
);
6863 /* WaDisableL3Bank2xClockGate:vlv
6864 * Disabling L3 clock gating- MMIO 940c[25] = 1
6865 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
6866 I915_WRITE(GEN7_UCGCTL4
,
6867 I915_READ(GEN7_UCGCTL4
) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE
);
6870 * BSpec says this must be set, even though
6871 * WaDisable4x2SubspanOptimization isn't listed for VLV.
6873 I915_WRITE(CACHE_MODE_1
,
6874 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
));
6877 * BSpec recommends 8x4 when MSAA is used,
6878 * however in practice 16x4 seems fastest.
6880 * Note that PS/WM thread counts depend on the WIZ hashing
6881 * disable bit, which we don't touch here, but it's good
6882 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6884 I915_WRITE(GEN7_GT_MODE
,
6885 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK
, GEN6_WIZ_HASHING_16x4
));
6888 * WaIncreaseL3CreditsForVLVB0:vlv
6889 * This is the hardware default actually.
6891 I915_WRITE(GEN7_L3SQCREG1
, VLV_B0_WA_L3SQCREG1_VALUE
);
6894 * WaDisableVLVClockGating_VBIIssue:vlv
6895 * Disable clock gating on th GCFG unit to prevent a delay
6896 * in the reporting of vblank events.
6898 I915_WRITE(VLV_GUNIT_CLOCK_GATE
, GCFG_DIS
);
6901 static void cherryview_init_clock_gating(struct drm_device
*dev
)
6903 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6905 vlv_init_display_clock_gating(dev_priv
);
6907 /* WaVSRefCountFullforceMissDisable:chv */
6908 /* WaDSRefCountFullforceMissDisable:chv */
6909 I915_WRITE(GEN7_FF_THREAD_MODE
,
6910 I915_READ(GEN7_FF_THREAD_MODE
) &
6911 ~(GEN8_FF_DS_REF_CNT_FFME
| GEN7_FF_VS_REF_CNT_FFME
));
6913 /* WaDisableSemaphoreAndSyncFlipWait:chv */
6914 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL
,
6915 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE
));
6917 /* WaDisableCSUnitClockGating:chv */
6918 I915_WRITE(GEN6_UCGCTL1
, I915_READ(GEN6_UCGCTL1
) |
6919 GEN6_CSUNIT_CLOCK_GATE_DISABLE
);
6921 /* WaDisableSDEUnitClockGating:chv */
6922 I915_WRITE(GEN8_UCGCTL6
, I915_READ(GEN8_UCGCTL6
) |
6923 GEN8_SDEUNIT_CLOCK_GATE_DISABLE
);
6926 * GTT cache may not work with big pages, so if those
6927 * are ever enabled GTT cache may need to be disabled.
6929 I915_WRITE(HSW_GTT_CACHE_EN
, GTT_CACHE_EN_ALL
);
6932 static void g4x_init_clock_gating(struct drm_device
*dev
)
6934 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6935 uint32_t dspclk_gate
;
6937 I915_WRITE(RENCLK_GATE_D1
, 0);
6938 I915_WRITE(RENCLK_GATE_D2
, VF_UNIT_CLOCK_GATE_DISABLE
|
6939 GS_UNIT_CLOCK_GATE_DISABLE
|
6940 CL_UNIT_CLOCK_GATE_DISABLE
);
6941 I915_WRITE(RAMCLK_GATE_D
, 0);
6942 dspclk_gate
= VRHUNIT_CLOCK_GATE_DISABLE
|
6943 OVRUNIT_CLOCK_GATE_DISABLE
|
6944 OVCUNIT_CLOCK_GATE_DISABLE
;
6946 dspclk_gate
|= DSSUNIT_CLOCK_GATE_DISABLE
;
6947 I915_WRITE(DSPCLK_GATE_D
, dspclk_gate
);
6949 /* WaDisableRenderCachePipelinedFlush */
6950 I915_WRITE(CACHE_MODE_0
,
6951 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE
));
6953 /* WaDisable_RenderCache_OperationalFlush:g4x */
6954 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
6956 g4x_disable_trickle_feed(dev
);
6959 static void crestline_init_clock_gating(struct drm_device
*dev
)
6961 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6963 I915_WRITE(RENCLK_GATE_D1
, I965_RCC_CLOCK_GATE_DISABLE
);
6964 I915_WRITE(RENCLK_GATE_D2
, 0);
6965 I915_WRITE(DSPCLK_GATE_D
, 0);
6966 I915_WRITE(RAMCLK_GATE_D
, 0);
6967 I915_WRITE16(DEUC
, 0);
6968 I915_WRITE(MI_ARB_STATE
,
6969 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
));
6971 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6972 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
6975 static void broadwater_init_clock_gating(struct drm_device
*dev
)
6977 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6979 I915_WRITE(RENCLK_GATE_D1
, I965_RCZ_CLOCK_GATE_DISABLE
|
6980 I965_RCC_CLOCK_GATE_DISABLE
|
6981 I965_RCPB_CLOCK_GATE_DISABLE
|
6982 I965_ISC_CLOCK_GATE_DISABLE
|
6983 I965_FBC_CLOCK_GATE_DISABLE
);
6984 I915_WRITE(RENCLK_GATE_D2
, 0);
6985 I915_WRITE(MI_ARB_STATE
,
6986 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
));
6988 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6989 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
6992 static void gen3_init_clock_gating(struct drm_device
*dev
)
6994 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6995 u32 dstate
= I915_READ(D_STATE
);
6997 dstate
|= DSTATE_PLL_D3_OFF
| DSTATE_GFX_CLOCK_GATING
|
6998 DSTATE_DOT_CLOCK_GATING
;
6999 I915_WRITE(D_STATE
, dstate
);
7001 if (IS_PINEVIEW(dev
))
7002 I915_WRITE(ECOSKPD
, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY
));
7004 /* IIR "flip pending" means done if this bit is set */
7005 I915_WRITE(ECOSKPD
, _MASKED_BIT_DISABLE(ECO_FLIP_DONE
));
7007 /* interrupts should cause a wake up from C3 */
7008 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN
));
7010 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7011 I915_WRITE(MI_ARB_STATE
, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE
));
7013 I915_WRITE(MI_ARB_STATE
,
7014 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
));
7017 static void i85x_init_clock_gating(struct drm_device
*dev
)
7019 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7021 I915_WRITE(RENCLK_GATE_D1
, SV_CLOCK_GATE_DISABLE
);
7023 /* interrupts should cause a wake up from C3 */
7024 I915_WRITE(MI_STATE
, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN
) |
7025 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE
));
7027 I915_WRITE(MEM_MODE
,
7028 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE
));
7031 static void i830_init_clock_gating(struct drm_device
*dev
)
7033 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7035 I915_WRITE(DSPCLK_GATE_D
, OVRUNIT_CLOCK_GATE_DISABLE
);
7037 I915_WRITE(MEM_MODE
,
7038 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE
) |
7039 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE
));
7042 void intel_init_clock_gating(struct drm_device
*dev
)
7044 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7046 if (dev_priv
->display
.init_clock_gating
)
7047 dev_priv
->display
.init_clock_gating(dev
);
7050 void intel_suspend_hw(struct drm_device
*dev
)
7052 if (HAS_PCH_LPT(dev
))
7053 lpt_suspend_hw(dev
);
7056 /* Set up chip specific power management-related functions */
7057 void intel_init_pm(struct drm_device
*dev
)
7059 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7061 intel_fbc_init(dev_priv
);
7064 if (IS_PINEVIEW(dev
))
7065 i915_pineview_get_mem_freq(dev
);
7066 else if (IS_GEN5(dev
))
7067 i915_ironlake_get_mem_freq(dev
);
7069 /* For FIFO watermark updates */
7070 if (INTEL_INFO(dev
)->gen
>= 9) {
7071 skl_setup_wm_latency(dev
);
7073 if (IS_BROXTON(dev
))
7074 dev_priv
->display
.init_clock_gating
=
7075 bxt_init_clock_gating
;
7076 else if (IS_SKYLAKE(dev
))
7077 dev_priv
->display
.init_clock_gating
=
7078 skl_init_clock_gating
;
7079 dev_priv
->display
.update_wm
= skl_update_wm
;
7080 dev_priv
->display
.update_sprite_wm
= skl_update_sprite_wm
;
7081 } else if (HAS_PCH_SPLIT(dev
)) {
7082 ilk_setup_wm_latency(dev
);
7084 if ((IS_GEN5(dev
) && dev_priv
->wm
.pri_latency
[1] &&
7085 dev_priv
->wm
.spr_latency
[1] && dev_priv
->wm
.cur_latency
[1]) ||
7086 (!IS_GEN5(dev
) && dev_priv
->wm
.pri_latency
[0] &&
7087 dev_priv
->wm
.spr_latency
[0] && dev_priv
->wm
.cur_latency
[0])) {
7088 dev_priv
->display
.update_wm
= ilk_update_wm
;
7089 dev_priv
->display
.update_sprite_wm
= ilk_update_sprite_wm
;
7091 DRM_DEBUG_KMS("Failed to read display plane latency. "
7096 dev_priv
->display
.init_clock_gating
= ironlake_init_clock_gating
;
7097 else if (IS_GEN6(dev
))
7098 dev_priv
->display
.init_clock_gating
= gen6_init_clock_gating
;
7099 else if (IS_IVYBRIDGE(dev
))
7100 dev_priv
->display
.init_clock_gating
= ivybridge_init_clock_gating
;
7101 else if (IS_HASWELL(dev
))
7102 dev_priv
->display
.init_clock_gating
= haswell_init_clock_gating
;
7103 else if (INTEL_INFO(dev
)->gen
== 8)
7104 dev_priv
->display
.init_clock_gating
= broadwell_init_clock_gating
;
7105 } else if (IS_CHERRYVIEW(dev
)) {
7106 vlv_setup_wm_latency(dev
);
7108 dev_priv
->display
.update_wm
= vlv_update_wm
;
7109 dev_priv
->display
.init_clock_gating
=
7110 cherryview_init_clock_gating
;
7111 } else if (IS_VALLEYVIEW(dev
)) {
7112 vlv_setup_wm_latency(dev
);
7114 dev_priv
->display
.update_wm
= vlv_update_wm
;
7115 dev_priv
->display
.init_clock_gating
=
7116 valleyview_init_clock_gating
;
7117 } else if (IS_PINEVIEW(dev
)) {
7118 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev
),
7121 dev_priv
->mem_freq
)) {
7122 DRM_INFO("failed to find known CxSR latency "
7123 "(found ddr%s fsb freq %d, mem freq %d), "
7125 (dev_priv
->is_ddr3
== 1) ? "3" : "2",
7126 dev_priv
->fsb_freq
, dev_priv
->mem_freq
);
7127 /* Disable CxSR and never update its watermark again */
7128 intel_set_memory_cxsr(dev_priv
, false);
7129 dev_priv
->display
.update_wm
= NULL
;
7131 dev_priv
->display
.update_wm
= pineview_update_wm
;
7132 dev_priv
->display
.init_clock_gating
= gen3_init_clock_gating
;
7133 } else if (IS_G4X(dev
)) {
7134 dev_priv
->display
.update_wm
= g4x_update_wm
;
7135 dev_priv
->display
.init_clock_gating
= g4x_init_clock_gating
;
7136 } else if (IS_GEN4(dev
)) {
7137 dev_priv
->display
.update_wm
= i965_update_wm
;
7138 if (IS_CRESTLINE(dev
))
7139 dev_priv
->display
.init_clock_gating
= crestline_init_clock_gating
;
7140 else if (IS_BROADWATER(dev
))
7141 dev_priv
->display
.init_clock_gating
= broadwater_init_clock_gating
;
7142 } else if (IS_GEN3(dev
)) {
7143 dev_priv
->display
.update_wm
= i9xx_update_wm
;
7144 dev_priv
->display
.get_fifo_size
= i9xx_get_fifo_size
;
7145 dev_priv
->display
.init_clock_gating
= gen3_init_clock_gating
;
7146 } else if (IS_GEN2(dev
)) {
7147 if (INTEL_INFO(dev
)->num_pipes
== 1) {
7148 dev_priv
->display
.update_wm
= i845_update_wm
;
7149 dev_priv
->display
.get_fifo_size
= i845_get_fifo_size
;
7151 dev_priv
->display
.update_wm
= i9xx_update_wm
;
7152 dev_priv
->display
.get_fifo_size
= i830_get_fifo_size
;
7155 if (IS_I85X(dev
) || IS_I865G(dev
))
7156 dev_priv
->display
.init_clock_gating
= i85x_init_clock_gating
;
7158 dev_priv
->display
.init_clock_gating
= i830_init_clock_gating
;
7160 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
7164 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u32 mbox
, u32
*val
)
7166 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
7168 if (I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) {
7169 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7173 I915_WRITE(GEN6_PCODE_DATA
, *val
);
7174 I915_WRITE(GEN6_PCODE_DATA1
, 0);
7175 I915_WRITE(GEN6_PCODE_MAILBOX
, GEN6_PCODE_READY
| mbox
);
7177 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) == 0,
7179 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox
);
7183 *val
= I915_READ(GEN6_PCODE_DATA
);
7184 I915_WRITE(GEN6_PCODE_DATA
, 0);
7189 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
, u32 mbox
, u32 val
)
7191 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
7193 if (I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) {
7194 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7198 I915_WRITE(GEN6_PCODE_DATA
, val
);
7199 I915_WRITE(GEN6_PCODE_MAILBOX
, GEN6_PCODE_READY
| mbox
);
7201 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) == 0,
7203 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox
);
7207 I915_WRITE(GEN6_PCODE_DATA
, 0);
7212 static int vlv_gpu_freq_div(unsigned int czclk_freq
)
7214 switch (czclk_freq
) {
7229 static int byt_gpu_freq(struct drm_i915_private
*dev_priv
, int val
)
7231 int div
, czclk_freq
= DIV_ROUND_CLOSEST(dev_priv
->mem_freq
, 4);
7233 div
= vlv_gpu_freq_div(czclk_freq
);
7237 return DIV_ROUND_CLOSEST(czclk_freq
* (val
+ 6 - 0xbd), div
);
7240 static int byt_freq_opcode(struct drm_i915_private
*dev_priv
, int val
)
7242 int mul
, czclk_freq
= DIV_ROUND_CLOSEST(dev_priv
->mem_freq
, 4);
7244 mul
= vlv_gpu_freq_div(czclk_freq
);
7248 return DIV_ROUND_CLOSEST(mul
* val
, czclk_freq
) + 0xbd - 6;
7251 static int chv_gpu_freq(struct drm_i915_private
*dev_priv
, int val
)
7253 int div
, czclk_freq
= dev_priv
->rps
.cz_freq
;
7255 div
= vlv_gpu_freq_div(czclk_freq
) / 2;
7259 return DIV_ROUND_CLOSEST(czclk_freq
* val
, 2 * div
) / 2;
7262 static int chv_freq_opcode(struct drm_i915_private
*dev_priv
, int val
)
7264 int mul
, czclk_freq
= dev_priv
->rps
.cz_freq
;
7266 mul
= vlv_gpu_freq_div(czclk_freq
) / 2;
7270 /* CHV needs even values */
7271 return DIV_ROUND_CLOSEST(val
* 2 * mul
, czclk_freq
) * 2;
7274 int intel_gpu_freq(struct drm_i915_private
*dev_priv
, int val
)
7276 if (IS_GEN9(dev_priv
->dev
))
7277 return (val
* GT_FREQUENCY_MULTIPLIER
) / GEN9_FREQ_SCALER
;
7278 else if (IS_CHERRYVIEW(dev_priv
->dev
))
7279 return chv_gpu_freq(dev_priv
, val
);
7280 else if (IS_VALLEYVIEW(dev_priv
->dev
))
7281 return byt_gpu_freq(dev_priv
, val
);
7283 return val
* GT_FREQUENCY_MULTIPLIER
;
7286 int intel_freq_opcode(struct drm_i915_private
*dev_priv
, int val
)
7288 if (IS_GEN9(dev_priv
->dev
))
7289 return (val
* GEN9_FREQ_SCALER
) / GT_FREQUENCY_MULTIPLIER
;
7290 else if (IS_CHERRYVIEW(dev_priv
->dev
))
7291 return chv_freq_opcode(dev_priv
, val
);
7292 else if (IS_VALLEYVIEW(dev_priv
->dev
))
7293 return byt_freq_opcode(dev_priv
, val
);
7295 return val
/ GT_FREQUENCY_MULTIPLIER
;
7298 struct request_boost
{
7299 struct work_struct work
;
7300 struct drm_i915_gem_request
*req
;
7303 static void __intel_rps_boost_work(struct work_struct
*work
)
7305 struct request_boost
*boost
= container_of(work
, struct request_boost
, work
);
7306 struct drm_i915_gem_request
*req
= boost
->req
;
7308 if (!i915_gem_request_completed(req
, true))
7309 gen6_rps_boost(to_i915(req
->ring
->dev
), NULL
,
7310 req
->emitted_jiffies
);
7312 i915_gem_request_unreference__unlocked(req
);
7316 void intel_queue_rps_boost_for_request(struct drm_device
*dev
,
7317 struct drm_i915_gem_request
*req
)
7319 struct request_boost
*boost
;
7321 if (req
== NULL
|| INTEL_INFO(dev
)->gen
< 6)
7324 if (i915_gem_request_completed(req
, true))
7327 boost
= kmalloc(sizeof(*boost
), GFP_ATOMIC
);
7331 i915_gem_request_reference(req
);
7334 INIT_WORK(&boost
->work
, __intel_rps_boost_work
);
7335 queue_work(to_i915(dev
)->wq
, &boost
->work
);
7338 void intel_pm_setup(struct drm_device
*dev
)
7340 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7342 mutex_init(&dev_priv
->rps
.hw_lock
);
7343 spin_lock_init(&dev_priv
->rps
.client_lock
);
7345 INIT_DELAYED_WORK(&dev_priv
->rps
.delayed_resume_work
,
7346 intel_gen6_powersave_work
);
7347 INIT_LIST_HEAD(&dev_priv
->rps
.clients
);
7348 INIT_LIST_HEAD(&dev_priv
->rps
.semaphores
.link
);
7349 INIT_LIST_HEAD(&dev_priv
->rps
.mmioflips
.link
);
7351 dev_priv
->pm
.suspended
= false;