2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
28 #include <linux/cpufreq.h>
30 #include "intel_drv.h"
31 #include "../../../platform/x86/intel_ips.h"
32 #include <linux/module.h>
34 #define FORCEWAKE_ACK_TIMEOUT_MS 2
36 /* FBC, or Frame Buffer Compression, is a technique employed to compress the
37 * framebuffer contents in-memory, aiming at reducing the required bandwidth
38 * during in-memory transfers and, therefore, reduce the power packet.
40 * The benefits of FBC are mostly visible with solid backgrounds and
41 * variation-less patterns.
43 * FBC-related functionality can be enabled by the means of the
44 * i915.i915_enable_fbc parameter
47 static bool intel_crtc_active(struct drm_crtc
*crtc
)
49 /* Be paranoid as we can arrive here with only partial
50 * state retrieved from the hardware during setup.
52 return to_intel_crtc(crtc
)->active
&& crtc
->fb
&& crtc
->mode
.clock
;
55 static void i8xx_disable_fbc(struct drm_device
*dev
)
57 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
60 /* Disable compression */
61 fbc_ctl
= I915_READ(FBC_CONTROL
);
62 if ((fbc_ctl
& FBC_CTL_EN
) == 0)
65 fbc_ctl
&= ~FBC_CTL_EN
;
66 I915_WRITE(FBC_CONTROL
, fbc_ctl
);
68 /* Wait for compressing bit to clear */
69 if (wait_for((I915_READ(FBC_STATUS
) & FBC_STAT_COMPRESSING
) == 0, 10)) {
70 DRM_DEBUG_KMS("FBC idle timed out\n");
74 DRM_DEBUG_KMS("disabled FBC\n");
77 static void i8xx_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
79 struct drm_device
*dev
= crtc
->dev
;
80 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
81 struct drm_framebuffer
*fb
= crtc
->fb
;
82 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
83 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
84 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
87 u32 fbc_ctl
, fbc_ctl2
;
89 cfb_pitch
= dev_priv
->cfb_size
/ FBC_LL_SIZE
;
90 if (fb
->pitches
[0] < cfb_pitch
)
91 cfb_pitch
= fb
->pitches
[0];
93 /* FBC_CTL wants 64B units */
94 cfb_pitch
= (cfb_pitch
/ 64) - 1;
95 plane
= intel_crtc
->plane
== 0 ? FBC_CTL_PLANEA
: FBC_CTL_PLANEB
;
98 for (i
= 0; i
< (FBC_LL_SIZE
/ 32) + 1; i
++)
99 I915_WRITE(FBC_TAG
+ (i
* 4), 0);
102 fbc_ctl2
= FBC_CTL_FENCE_DBL
| FBC_CTL_IDLE_IMM
| FBC_CTL_CPU_FENCE
;
104 I915_WRITE(FBC_CONTROL2
, fbc_ctl2
);
105 I915_WRITE(FBC_FENCE_OFF
, crtc
->y
);
108 fbc_ctl
= FBC_CTL_EN
| FBC_CTL_PERIODIC
;
110 fbc_ctl
|= FBC_CTL_C3_IDLE
; /* 945 needs special SR handling */
111 fbc_ctl
|= (cfb_pitch
& 0xff) << FBC_CTL_STRIDE_SHIFT
;
112 fbc_ctl
|= (interval
& 0x2fff) << FBC_CTL_INTERVAL_SHIFT
;
113 fbc_ctl
|= obj
->fence_reg
;
114 I915_WRITE(FBC_CONTROL
, fbc_ctl
);
116 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c, ",
117 cfb_pitch
, crtc
->y
, plane_name(intel_crtc
->plane
));
120 static bool i8xx_fbc_enabled(struct drm_device
*dev
)
122 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
124 return I915_READ(FBC_CONTROL
) & FBC_CTL_EN
;
127 static void g4x_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
129 struct drm_device
*dev
= crtc
->dev
;
130 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
131 struct drm_framebuffer
*fb
= crtc
->fb
;
132 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
133 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
134 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
135 int plane
= intel_crtc
->plane
== 0 ? DPFC_CTL_PLANEA
: DPFC_CTL_PLANEB
;
136 unsigned long stall_watermark
= 200;
139 dpfc_ctl
= plane
| DPFC_SR_EN
| DPFC_CTL_LIMIT_1X
;
140 dpfc_ctl
|= DPFC_CTL_FENCE_EN
| obj
->fence_reg
;
141 I915_WRITE(DPFC_CHICKEN
, DPFC_HT_MODIFY
);
143 I915_WRITE(DPFC_RECOMP_CTL
, DPFC_RECOMP_STALL_EN
|
144 (stall_watermark
<< DPFC_RECOMP_STALL_WM_SHIFT
) |
145 (interval
<< DPFC_RECOMP_TIMER_COUNT_SHIFT
));
146 I915_WRITE(DPFC_FENCE_YOFF
, crtc
->y
);
149 I915_WRITE(DPFC_CONTROL
, I915_READ(DPFC_CONTROL
) | DPFC_CTL_EN
);
151 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc
->plane
));
154 static void g4x_disable_fbc(struct drm_device
*dev
)
156 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
159 /* Disable compression */
160 dpfc_ctl
= I915_READ(DPFC_CONTROL
);
161 if (dpfc_ctl
& DPFC_CTL_EN
) {
162 dpfc_ctl
&= ~DPFC_CTL_EN
;
163 I915_WRITE(DPFC_CONTROL
, dpfc_ctl
);
165 DRM_DEBUG_KMS("disabled FBC\n");
169 static bool g4x_fbc_enabled(struct drm_device
*dev
)
171 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
173 return I915_READ(DPFC_CONTROL
) & DPFC_CTL_EN
;
176 static void sandybridge_blit_fbc_update(struct drm_device
*dev
)
178 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
181 /* Make sure blitter notifies FBC of writes */
182 gen6_gt_force_wake_get(dev_priv
);
183 blt_ecoskpd
= I915_READ(GEN6_BLITTER_ECOSKPD
);
184 blt_ecoskpd
|= GEN6_BLITTER_FBC_NOTIFY
<<
185 GEN6_BLITTER_LOCK_SHIFT
;
186 I915_WRITE(GEN6_BLITTER_ECOSKPD
, blt_ecoskpd
);
187 blt_ecoskpd
|= GEN6_BLITTER_FBC_NOTIFY
;
188 I915_WRITE(GEN6_BLITTER_ECOSKPD
, blt_ecoskpd
);
189 blt_ecoskpd
&= ~(GEN6_BLITTER_FBC_NOTIFY
<<
190 GEN6_BLITTER_LOCK_SHIFT
);
191 I915_WRITE(GEN6_BLITTER_ECOSKPD
, blt_ecoskpd
);
192 POSTING_READ(GEN6_BLITTER_ECOSKPD
);
193 gen6_gt_force_wake_put(dev_priv
);
196 static void ironlake_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
198 struct drm_device
*dev
= crtc
->dev
;
199 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
200 struct drm_framebuffer
*fb
= crtc
->fb
;
201 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
202 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
203 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
204 int plane
= intel_crtc
->plane
== 0 ? DPFC_CTL_PLANEA
: DPFC_CTL_PLANEB
;
205 unsigned long stall_watermark
= 200;
208 dpfc_ctl
= I915_READ(ILK_DPFC_CONTROL
);
209 dpfc_ctl
&= DPFC_RESERVED
;
210 dpfc_ctl
|= (plane
| DPFC_CTL_LIMIT_1X
);
211 /* Set persistent mode for front-buffer rendering, ala X. */
212 dpfc_ctl
|= DPFC_CTL_PERSISTENT_MODE
;
213 dpfc_ctl
|= (DPFC_CTL_FENCE_EN
| obj
->fence_reg
);
214 I915_WRITE(ILK_DPFC_CHICKEN
, DPFC_HT_MODIFY
);
216 I915_WRITE(ILK_DPFC_RECOMP_CTL
, DPFC_RECOMP_STALL_EN
|
217 (stall_watermark
<< DPFC_RECOMP_STALL_WM_SHIFT
) |
218 (interval
<< DPFC_RECOMP_TIMER_COUNT_SHIFT
));
219 I915_WRITE(ILK_DPFC_FENCE_YOFF
, crtc
->y
);
220 I915_WRITE(ILK_FBC_RT_BASE
, obj
->gtt_offset
| ILK_FBC_RT_VALID
);
222 I915_WRITE(ILK_DPFC_CONTROL
, dpfc_ctl
| DPFC_CTL_EN
);
225 I915_WRITE(SNB_DPFC_CTL_SA
,
226 SNB_CPU_FENCE_ENABLE
| obj
->fence_reg
);
227 I915_WRITE(DPFC_CPU_FENCE_OFFSET
, crtc
->y
);
228 sandybridge_blit_fbc_update(dev
);
231 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc
->plane
));
234 static void ironlake_disable_fbc(struct drm_device
*dev
)
236 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
239 /* Disable compression */
240 dpfc_ctl
= I915_READ(ILK_DPFC_CONTROL
);
241 if (dpfc_ctl
& DPFC_CTL_EN
) {
242 dpfc_ctl
&= ~DPFC_CTL_EN
;
243 I915_WRITE(ILK_DPFC_CONTROL
, dpfc_ctl
);
245 if (IS_IVYBRIDGE(dev
))
246 /* WaFbcDisableDpfcClockGating:ivb */
247 I915_WRITE(ILK_DSPCLK_GATE_D
,
248 I915_READ(ILK_DSPCLK_GATE_D
) &
249 ~ILK_DPFCUNIT_CLOCK_GATE_DISABLE
);
252 /* WaFbcDisableDpfcClockGating:hsw */
253 I915_WRITE(HSW_CLKGATE_DISABLE_PART_1
,
254 I915_READ(HSW_CLKGATE_DISABLE_PART_1
) &
255 ~HSW_DPFC_GATING_DISABLE
);
257 DRM_DEBUG_KMS("disabled FBC\n");
261 static bool ironlake_fbc_enabled(struct drm_device
*dev
)
263 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
265 return I915_READ(ILK_DPFC_CONTROL
) & DPFC_CTL_EN
;
268 static void gen7_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
270 struct drm_device
*dev
= crtc
->dev
;
271 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
272 struct drm_framebuffer
*fb
= crtc
->fb
;
273 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
274 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
275 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
277 I915_WRITE(IVB_FBC_RT_BASE
, obj
->gtt_offset
| ILK_FBC_RT_VALID
);
279 I915_WRITE(ILK_DPFC_CONTROL
, DPFC_CTL_EN
| DPFC_CTL_LIMIT_1X
|
280 IVB_DPFC_CTL_FENCE_EN
|
281 intel_crtc
->plane
<< IVB_DPFC_CTL_PLANE_SHIFT
);
283 if (IS_IVYBRIDGE(dev
)) {
284 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
285 I915_WRITE(ILK_DISPLAY_CHICKEN1
, ILK_FBCQ_DIS
);
286 /* WaFbcDisableDpfcClockGating:ivb */
287 I915_WRITE(ILK_DSPCLK_GATE_D
,
288 I915_READ(ILK_DSPCLK_GATE_D
) |
289 ILK_DPFCUNIT_CLOCK_GATE_DISABLE
);
291 /* WaFbcAsynchFlipDisableFbcQueue:hsw */
292 I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc
->pipe
),
293 HSW_BYPASS_FBC_QUEUE
);
294 /* WaFbcDisableDpfcClockGating:hsw */
295 I915_WRITE(HSW_CLKGATE_DISABLE_PART_1
,
296 I915_READ(HSW_CLKGATE_DISABLE_PART_1
) |
297 HSW_DPFC_GATING_DISABLE
);
300 I915_WRITE(SNB_DPFC_CTL_SA
,
301 SNB_CPU_FENCE_ENABLE
| obj
->fence_reg
);
302 I915_WRITE(DPFC_CPU_FENCE_OFFSET
, crtc
->y
);
304 sandybridge_blit_fbc_update(dev
);
306 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc
->plane
);
309 bool intel_fbc_enabled(struct drm_device
*dev
)
311 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
313 if (!dev_priv
->display
.fbc_enabled
)
316 return dev_priv
->display
.fbc_enabled(dev
);
319 static void intel_fbc_work_fn(struct work_struct
*__work
)
321 struct intel_fbc_work
*work
=
322 container_of(to_delayed_work(__work
),
323 struct intel_fbc_work
, work
);
324 struct drm_device
*dev
= work
->crtc
->dev
;
325 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
327 mutex_lock(&dev
->struct_mutex
);
328 if (work
== dev_priv
->fbc_work
) {
329 /* Double check that we haven't switched fb without cancelling
332 if (work
->crtc
->fb
== work
->fb
) {
333 dev_priv
->display
.enable_fbc(work
->crtc
,
336 dev_priv
->cfb_plane
= to_intel_crtc(work
->crtc
)->plane
;
337 dev_priv
->cfb_fb
= work
->crtc
->fb
->base
.id
;
338 dev_priv
->cfb_y
= work
->crtc
->y
;
341 dev_priv
->fbc_work
= NULL
;
343 mutex_unlock(&dev
->struct_mutex
);
348 static void intel_cancel_fbc_work(struct drm_i915_private
*dev_priv
)
350 if (dev_priv
->fbc_work
== NULL
)
353 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
355 /* Synchronisation is provided by struct_mutex and checking of
356 * dev_priv->fbc_work, so we can perform the cancellation
357 * entirely asynchronously.
359 if (cancel_delayed_work(&dev_priv
->fbc_work
->work
))
360 /* tasklet was killed before being run, clean up */
361 kfree(dev_priv
->fbc_work
);
363 /* Mark the work as no longer wanted so that if it does
364 * wake-up (because the work was already running and waiting
365 * for our mutex), it will discover that is no longer
368 dev_priv
->fbc_work
= NULL
;
371 void intel_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
373 struct intel_fbc_work
*work
;
374 struct drm_device
*dev
= crtc
->dev
;
375 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
377 if (!dev_priv
->display
.enable_fbc
)
380 intel_cancel_fbc_work(dev_priv
);
382 work
= kzalloc(sizeof *work
, GFP_KERNEL
);
384 dev_priv
->display
.enable_fbc(crtc
, interval
);
390 work
->interval
= interval
;
391 INIT_DELAYED_WORK(&work
->work
, intel_fbc_work_fn
);
393 dev_priv
->fbc_work
= work
;
395 DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
397 /* Delay the actual enabling to let pageflipping cease and the
398 * display to settle before starting the compression. Note that
399 * this delay also serves a second purpose: it allows for a
400 * vblank to pass after disabling the FBC before we attempt
401 * to modify the control registers.
403 * A more complicated solution would involve tracking vblanks
404 * following the termination of the page-flipping sequence
405 * and indeed performing the enable as a co-routine and not
406 * waiting synchronously upon the vblank.
408 schedule_delayed_work(&work
->work
, msecs_to_jiffies(50));
411 void intel_disable_fbc(struct drm_device
*dev
)
413 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
415 intel_cancel_fbc_work(dev_priv
);
417 if (!dev_priv
->display
.disable_fbc
)
420 dev_priv
->display
.disable_fbc(dev
);
421 dev_priv
->cfb_plane
= -1;
425 * intel_update_fbc - enable/disable FBC as needed
426 * @dev: the drm_device
428 * Set up the framebuffer compression hardware at mode set time. We
429 * enable it if possible:
430 * - plane A only (on pre-965)
431 * - no pixel mulitply/line duplication
432 * - no alpha buffer discard
434 * - framebuffer <= 2048 in width, 1536 in height
436 * We can't assume that any compression will take place (worst case),
437 * so the compressed buffer has to be the same size as the uncompressed
438 * one. It also must reside (along with the line length buffer) in
441 * We need to enable/disable FBC on a global basis.
443 void intel_update_fbc(struct drm_device
*dev
)
445 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
446 struct drm_crtc
*crtc
= NULL
, *tmp_crtc
;
447 struct intel_crtc
*intel_crtc
;
448 struct drm_framebuffer
*fb
;
449 struct intel_framebuffer
*intel_fb
;
450 struct drm_i915_gem_object
*obj
;
456 if (!I915_HAS_FBC(dev
))
460 * If FBC is already on, we just have to verify that we can
461 * keep it that way...
462 * Need to disable if:
463 * - more than one pipe is active
464 * - changing FBC params (stride, fence, mode)
465 * - new fb is too large to fit in compressed buffer
466 * - going to an unsupported config (interlace, pixel multiply, etc.)
468 list_for_each_entry(tmp_crtc
, &dev
->mode_config
.crtc_list
, head
) {
469 if (intel_crtc_active(tmp_crtc
) &&
470 !to_intel_crtc(tmp_crtc
)->primary_disabled
) {
472 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
473 dev_priv
->no_fbc_reason
= FBC_MULTIPLE_PIPES
;
480 if (!crtc
|| crtc
->fb
== NULL
) {
481 DRM_DEBUG_KMS("no output, disabling\n");
482 dev_priv
->no_fbc_reason
= FBC_NO_OUTPUT
;
486 intel_crtc
= to_intel_crtc(crtc
);
488 intel_fb
= to_intel_framebuffer(fb
);
491 enable_fbc
= i915_enable_fbc
;
492 if (enable_fbc
< 0) {
493 DRM_DEBUG_KMS("fbc set to per-chip default\n");
495 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
499 DRM_DEBUG_KMS("fbc disabled per module param\n");
500 dev_priv
->no_fbc_reason
= FBC_MODULE_PARAM
;
503 if ((crtc
->mode
.flags
& DRM_MODE_FLAG_INTERLACE
) ||
504 (crtc
->mode
.flags
& DRM_MODE_FLAG_DBLSCAN
)) {
505 DRM_DEBUG_KMS("mode incompatible with compression, "
507 dev_priv
->no_fbc_reason
= FBC_UNSUPPORTED_MODE
;
510 if ((crtc
->mode
.hdisplay
> 2048) ||
511 (crtc
->mode
.vdisplay
> 1536)) {
512 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
513 dev_priv
->no_fbc_reason
= FBC_MODE_TOO_LARGE
;
516 if ((IS_I915GM(dev
) || IS_I945GM(dev
) || IS_HASWELL(dev
)) &&
517 intel_crtc
->plane
!= 0) {
518 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
519 dev_priv
->no_fbc_reason
= FBC_BAD_PLANE
;
523 /* The use of a CPU fence is mandatory in order to detect writes
524 * by the CPU to the scanout and trigger updates to the FBC.
526 if (obj
->tiling_mode
!= I915_TILING_X
||
527 obj
->fence_reg
== I915_FENCE_REG_NONE
) {
528 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
529 dev_priv
->no_fbc_reason
= FBC_NOT_TILED
;
533 /* If the kernel debugger is active, always disable compression */
537 if (i915_gem_stolen_setup_compression(dev
, intel_fb
->obj
->base
.size
)) {
538 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
539 dev_priv
->no_fbc_reason
= FBC_STOLEN_TOO_SMALL
;
543 /* If the scanout has not changed, don't modify the FBC settings.
544 * Note that we make the fundamental assumption that the fb->obj
545 * cannot be unpinned (and have its GTT offset and fence revoked)
546 * without first being decoupled from the scanout and FBC disabled.
548 if (dev_priv
->cfb_plane
== intel_crtc
->plane
&&
549 dev_priv
->cfb_fb
== fb
->base
.id
&&
550 dev_priv
->cfb_y
== crtc
->y
)
553 if (intel_fbc_enabled(dev
)) {
554 /* We update FBC along two paths, after changing fb/crtc
555 * configuration (modeswitching) and after page-flipping
556 * finishes. For the latter, we know that not only did
557 * we disable the FBC at the start of the page-flip
558 * sequence, but also more than one vblank has passed.
560 * For the former case of modeswitching, it is possible
561 * to switch between two FBC valid configurations
562 * instantaneously so we do need to disable the FBC
563 * before we can modify its control registers. We also
564 * have to wait for the next vblank for that to take
565 * effect. However, since we delay enabling FBC we can
566 * assume that a vblank has passed since disabling and
567 * that we can safely alter the registers in the deferred
570 * In the scenario that we go from a valid to invalid
571 * and then back to valid FBC configuration we have
572 * no strict enforcement that a vblank occurred since
573 * disabling the FBC. However, along all current pipe
574 * disabling paths we do need to wait for a vblank at
575 * some point. And we wait before enabling FBC anyway.
577 DRM_DEBUG_KMS("disabling active FBC for update\n");
578 intel_disable_fbc(dev
);
581 intel_enable_fbc(crtc
, 500);
585 /* Multiple disables should be harmless */
586 if (intel_fbc_enabled(dev
)) {
587 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
588 intel_disable_fbc(dev
);
590 i915_gem_stolen_cleanup_compression(dev
);
593 static void i915_pineview_get_mem_freq(struct drm_device
*dev
)
595 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
598 tmp
= I915_READ(CLKCFG
);
600 switch (tmp
& CLKCFG_FSB_MASK
) {
602 dev_priv
->fsb_freq
= 533; /* 133*4 */
605 dev_priv
->fsb_freq
= 800; /* 200*4 */
608 dev_priv
->fsb_freq
= 667; /* 167*4 */
611 dev_priv
->fsb_freq
= 400; /* 100*4 */
615 switch (tmp
& CLKCFG_MEM_MASK
) {
617 dev_priv
->mem_freq
= 533;
620 dev_priv
->mem_freq
= 667;
623 dev_priv
->mem_freq
= 800;
627 /* detect pineview DDR3 setting */
628 tmp
= I915_READ(CSHRDDR3CTL
);
629 dev_priv
->is_ddr3
= (tmp
& CSHRDDR3CTL_DDR3
) ? 1 : 0;
632 static void i915_ironlake_get_mem_freq(struct drm_device
*dev
)
634 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
637 ddrpll
= I915_READ16(DDRMPLL1
);
638 csipll
= I915_READ16(CSIPLL0
);
640 switch (ddrpll
& 0xff) {
642 dev_priv
->mem_freq
= 800;
645 dev_priv
->mem_freq
= 1066;
648 dev_priv
->mem_freq
= 1333;
651 dev_priv
->mem_freq
= 1600;
654 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
656 dev_priv
->mem_freq
= 0;
660 dev_priv
->ips
.r_t
= dev_priv
->mem_freq
;
662 switch (csipll
& 0x3ff) {
664 dev_priv
->fsb_freq
= 3200;
667 dev_priv
->fsb_freq
= 3733;
670 dev_priv
->fsb_freq
= 4266;
673 dev_priv
->fsb_freq
= 4800;
676 dev_priv
->fsb_freq
= 5333;
679 dev_priv
->fsb_freq
= 5866;
682 dev_priv
->fsb_freq
= 6400;
685 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
687 dev_priv
->fsb_freq
= 0;
691 if (dev_priv
->fsb_freq
== 3200) {
692 dev_priv
->ips
.c_m
= 0;
693 } else if (dev_priv
->fsb_freq
> 3200 && dev_priv
->fsb_freq
<= 4800) {
694 dev_priv
->ips
.c_m
= 1;
696 dev_priv
->ips
.c_m
= 2;
700 static const struct cxsr_latency cxsr_latency_table
[] = {
701 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
702 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
703 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
704 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
705 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
707 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
708 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
709 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
710 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
711 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
713 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
714 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
715 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
716 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
717 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
719 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
720 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
721 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
722 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
723 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
725 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
726 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
727 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
728 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
729 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
731 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
732 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
733 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
734 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
735 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
738 static const struct cxsr_latency
*intel_get_cxsr_latency(int is_desktop
,
743 const struct cxsr_latency
*latency
;
746 if (fsb
== 0 || mem
== 0)
749 for (i
= 0; i
< ARRAY_SIZE(cxsr_latency_table
); i
++) {
750 latency
= &cxsr_latency_table
[i
];
751 if (is_desktop
== latency
->is_desktop
&&
752 is_ddr3
== latency
->is_ddr3
&&
753 fsb
== latency
->fsb_freq
&& mem
== latency
->mem_freq
)
757 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
762 static void pineview_disable_cxsr(struct drm_device
*dev
)
764 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
766 /* deactivate cxsr */
767 I915_WRITE(DSPFW3
, I915_READ(DSPFW3
) & ~PINEVIEW_SELF_REFRESH_EN
);
771 * Latency for FIFO fetches is dependent on several factors:
772 * - memory configuration (speed, channels)
774 * - current MCH state
775 * It can be fairly high in some situations, so here we assume a fairly
776 * pessimal value. It's a tradeoff between extra memory fetches (if we
777 * set this value too high, the FIFO will fetch frequently to stay full)
778 * and power consumption (set it too low to save power and we might see
779 * FIFO underruns and display "flicker").
781 * A value of 5us seems to be a good balance; safe for very low end
782 * platforms but not overly aggressive on lower latency configs.
784 static const int latency_ns
= 5000;
786 static int i9xx_get_fifo_size(struct drm_device
*dev
, int plane
)
788 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
789 uint32_t dsparb
= I915_READ(DSPARB
);
792 size
= dsparb
& 0x7f;
794 size
= ((dsparb
>> DSPARB_CSTART_SHIFT
) & 0x7f) - size
;
796 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
797 plane
? "B" : "A", size
);
802 static int i85x_get_fifo_size(struct drm_device
*dev
, int plane
)
804 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
805 uint32_t dsparb
= I915_READ(DSPARB
);
808 size
= dsparb
& 0x1ff;
810 size
= ((dsparb
>> DSPARB_BEND_SHIFT
) & 0x1ff) - size
;
811 size
>>= 1; /* Convert to cachelines */
813 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
814 plane
? "B" : "A", size
);
819 static int i845_get_fifo_size(struct drm_device
*dev
, int plane
)
821 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
822 uint32_t dsparb
= I915_READ(DSPARB
);
825 size
= dsparb
& 0x7f;
826 size
>>= 2; /* Convert to cachelines */
828 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
835 static int i830_get_fifo_size(struct drm_device
*dev
, int plane
)
837 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
838 uint32_t dsparb
= I915_READ(DSPARB
);
841 size
= dsparb
& 0x7f;
842 size
>>= 1; /* Convert to cachelines */
844 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
845 plane
? "B" : "A", size
);
850 /* Pineview has different values for various configs */
851 static const struct intel_watermark_params pineview_display_wm
= {
852 PINEVIEW_DISPLAY_FIFO
,
856 PINEVIEW_FIFO_LINE_SIZE
858 static const struct intel_watermark_params pineview_display_hplloff_wm
= {
859 PINEVIEW_DISPLAY_FIFO
,
861 PINEVIEW_DFT_HPLLOFF_WM
,
863 PINEVIEW_FIFO_LINE_SIZE
865 static const struct intel_watermark_params pineview_cursor_wm
= {
866 PINEVIEW_CURSOR_FIFO
,
867 PINEVIEW_CURSOR_MAX_WM
,
868 PINEVIEW_CURSOR_DFT_WM
,
869 PINEVIEW_CURSOR_GUARD_WM
,
870 PINEVIEW_FIFO_LINE_SIZE
,
872 static const struct intel_watermark_params pineview_cursor_hplloff_wm
= {
873 PINEVIEW_CURSOR_FIFO
,
874 PINEVIEW_CURSOR_MAX_WM
,
875 PINEVIEW_CURSOR_DFT_WM
,
876 PINEVIEW_CURSOR_GUARD_WM
,
877 PINEVIEW_FIFO_LINE_SIZE
879 static const struct intel_watermark_params g4x_wm_info
= {
886 static const struct intel_watermark_params g4x_cursor_wm_info
= {
893 static const struct intel_watermark_params valleyview_wm_info
= {
894 VALLEYVIEW_FIFO_SIZE
,
900 static const struct intel_watermark_params valleyview_cursor_wm_info
= {
902 VALLEYVIEW_CURSOR_MAX_WM
,
907 static const struct intel_watermark_params i965_cursor_wm_info
= {
914 static const struct intel_watermark_params i945_wm_info
= {
921 static const struct intel_watermark_params i915_wm_info
= {
928 static const struct intel_watermark_params i855_wm_info
= {
935 static const struct intel_watermark_params i830_wm_info
= {
943 static const struct intel_watermark_params ironlake_display_wm_info
= {
950 static const struct intel_watermark_params ironlake_cursor_wm_info
= {
957 static const struct intel_watermark_params ironlake_display_srwm_info
= {
959 ILK_DISPLAY_MAX_SRWM
,
960 ILK_DISPLAY_DFT_SRWM
,
964 static const struct intel_watermark_params ironlake_cursor_srwm_info
= {
972 static const struct intel_watermark_params sandybridge_display_wm_info
= {
979 static const struct intel_watermark_params sandybridge_cursor_wm_info
= {
986 static const struct intel_watermark_params sandybridge_display_srwm_info
= {
988 SNB_DISPLAY_MAX_SRWM
,
989 SNB_DISPLAY_DFT_SRWM
,
993 static const struct intel_watermark_params sandybridge_cursor_srwm_info
= {
1003 * intel_calculate_wm - calculate watermark level
1004 * @clock_in_khz: pixel clock
1005 * @wm: chip FIFO params
1006 * @pixel_size: display pixel size
1007 * @latency_ns: memory latency for the platform
1009 * Calculate the watermark level (the level at which the display plane will
1010 * start fetching from memory again). Each chip has a different display
1011 * FIFO size and allocation, so the caller needs to figure that out and pass
1012 * in the correct intel_watermark_params structure.
1014 * As the pixel clock runs, the FIFO will be drained at a rate that depends
1015 * on the pixel size. When it reaches the watermark level, it'll start
1016 * fetching FIFO line sized based chunks from memory until the FIFO fills
1017 * past the watermark point. If the FIFO drains completely, a FIFO underrun
1018 * will occur, and a display engine hang could result.
1020 static unsigned long intel_calculate_wm(unsigned long clock_in_khz
,
1021 const struct intel_watermark_params
*wm
,
1024 unsigned long latency_ns
)
1026 long entries_required
, wm_size
;
1029 * Note: we need to make sure we don't overflow for various clock &
1031 * clocks go from a few thousand to several hundred thousand.
1032 * latency is usually a few thousand
1034 entries_required
= ((clock_in_khz
/ 1000) * pixel_size
* latency_ns
) /
1036 entries_required
= DIV_ROUND_UP(entries_required
, wm
->cacheline_size
);
1038 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required
);
1040 wm_size
= fifo_size
- (entries_required
+ wm
->guard_size
);
1042 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size
);
1044 /* Don't promote wm_size to unsigned... */
1045 if (wm_size
> (long)wm
->max_wm
)
1046 wm_size
= wm
->max_wm
;
1048 wm_size
= wm
->default_wm
;
1052 static struct drm_crtc
*single_enabled_crtc(struct drm_device
*dev
)
1054 struct drm_crtc
*crtc
, *enabled
= NULL
;
1056 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
1057 if (intel_crtc_active(crtc
)) {
1067 static void pineview_update_wm(struct drm_device
*dev
)
1069 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1070 struct drm_crtc
*crtc
;
1071 const struct cxsr_latency
*latency
;
1075 latency
= intel_get_cxsr_latency(IS_PINEVIEW_G(dev
), dev_priv
->is_ddr3
,
1076 dev_priv
->fsb_freq
, dev_priv
->mem_freq
);
1078 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1079 pineview_disable_cxsr(dev
);
1083 crtc
= single_enabled_crtc(dev
);
1085 int clock
= crtc
->mode
.clock
;
1086 int pixel_size
= crtc
->fb
->bits_per_pixel
/ 8;
1089 wm
= intel_calculate_wm(clock
, &pineview_display_wm
,
1090 pineview_display_wm
.fifo_size
,
1091 pixel_size
, latency
->display_sr
);
1092 reg
= I915_READ(DSPFW1
);
1093 reg
&= ~DSPFW_SR_MASK
;
1094 reg
|= wm
<< DSPFW_SR_SHIFT
;
1095 I915_WRITE(DSPFW1
, reg
);
1096 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg
);
1099 wm
= intel_calculate_wm(clock
, &pineview_cursor_wm
,
1100 pineview_display_wm
.fifo_size
,
1101 pixel_size
, latency
->cursor_sr
);
1102 reg
= I915_READ(DSPFW3
);
1103 reg
&= ~DSPFW_CURSOR_SR_MASK
;
1104 reg
|= (wm
& 0x3f) << DSPFW_CURSOR_SR_SHIFT
;
1105 I915_WRITE(DSPFW3
, reg
);
1107 /* Display HPLL off SR */
1108 wm
= intel_calculate_wm(clock
, &pineview_display_hplloff_wm
,
1109 pineview_display_hplloff_wm
.fifo_size
,
1110 pixel_size
, latency
->display_hpll_disable
);
1111 reg
= I915_READ(DSPFW3
);
1112 reg
&= ~DSPFW_HPLL_SR_MASK
;
1113 reg
|= wm
& DSPFW_HPLL_SR_MASK
;
1114 I915_WRITE(DSPFW3
, reg
);
1116 /* cursor HPLL off SR */
1117 wm
= intel_calculate_wm(clock
, &pineview_cursor_hplloff_wm
,
1118 pineview_display_hplloff_wm
.fifo_size
,
1119 pixel_size
, latency
->cursor_hpll_disable
);
1120 reg
= I915_READ(DSPFW3
);
1121 reg
&= ~DSPFW_HPLL_CURSOR_MASK
;
1122 reg
|= (wm
& 0x3f) << DSPFW_HPLL_CURSOR_SHIFT
;
1123 I915_WRITE(DSPFW3
, reg
);
1124 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg
);
1128 I915_READ(DSPFW3
) | PINEVIEW_SELF_REFRESH_EN
);
1129 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1131 pineview_disable_cxsr(dev
);
1132 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1136 static bool g4x_compute_wm0(struct drm_device
*dev
,
1138 const struct intel_watermark_params
*display
,
1139 int display_latency_ns
,
1140 const struct intel_watermark_params
*cursor
,
1141 int cursor_latency_ns
,
1145 struct drm_crtc
*crtc
;
1146 int htotal
, hdisplay
, clock
, pixel_size
;
1147 int line_time_us
, line_count
;
1148 int entries
, tlb_miss
;
1150 crtc
= intel_get_crtc_for_plane(dev
, plane
);
1151 if (!intel_crtc_active(crtc
)) {
1152 *cursor_wm
= cursor
->guard_size
;
1153 *plane_wm
= display
->guard_size
;
1157 htotal
= crtc
->mode
.htotal
;
1158 hdisplay
= crtc
->mode
.hdisplay
;
1159 clock
= crtc
->mode
.clock
;
1160 pixel_size
= crtc
->fb
->bits_per_pixel
/ 8;
1162 /* Use the small buffer method to calculate plane watermark */
1163 entries
= ((clock
* pixel_size
/ 1000) * display_latency_ns
) / 1000;
1164 tlb_miss
= display
->fifo_size
*display
->cacheline_size
- hdisplay
* 8;
1166 entries
+= tlb_miss
;
1167 entries
= DIV_ROUND_UP(entries
, display
->cacheline_size
);
1168 *plane_wm
= entries
+ display
->guard_size
;
1169 if (*plane_wm
> (int)display
->max_wm
)
1170 *plane_wm
= display
->max_wm
;
1172 /* Use the large buffer method to calculate cursor watermark */
1173 line_time_us
= ((htotal
* 1000) / clock
);
1174 line_count
= (cursor_latency_ns
/ line_time_us
+ 1000) / 1000;
1175 entries
= line_count
* 64 * pixel_size
;
1176 tlb_miss
= cursor
->fifo_size
*cursor
->cacheline_size
- hdisplay
* 8;
1178 entries
+= tlb_miss
;
1179 entries
= DIV_ROUND_UP(entries
, cursor
->cacheline_size
);
1180 *cursor_wm
= entries
+ cursor
->guard_size
;
1181 if (*cursor_wm
> (int)cursor
->max_wm
)
1182 *cursor_wm
= (int)cursor
->max_wm
;
1188 * Check the wm result.
1190 * If any calculated watermark values is larger than the maximum value that
1191 * can be programmed into the associated watermark register, that watermark
1194 static bool g4x_check_srwm(struct drm_device
*dev
,
1195 int display_wm
, int cursor_wm
,
1196 const struct intel_watermark_params
*display
,
1197 const struct intel_watermark_params
*cursor
)
1199 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1200 display_wm
, cursor_wm
);
1202 if (display_wm
> display
->max_wm
) {
1203 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1204 display_wm
, display
->max_wm
);
1208 if (cursor_wm
> cursor
->max_wm
) {
1209 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1210 cursor_wm
, cursor
->max_wm
);
1214 if (!(display_wm
|| cursor_wm
)) {
1215 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1222 static bool g4x_compute_srwm(struct drm_device
*dev
,
1225 const struct intel_watermark_params
*display
,
1226 const struct intel_watermark_params
*cursor
,
1227 int *display_wm
, int *cursor_wm
)
1229 struct drm_crtc
*crtc
;
1230 int hdisplay
, htotal
, pixel_size
, clock
;
1231 unsigned long line_time_us
;
1232 int line_count
, line_size
;
1237 *display_wm
= *cursor_wm
= 0;
1241 crtc
= intel_get_crtc_for_plane(dev
, plane
);
1242 hdisplay
= crtc
->mode
.hdisplay
;
1243 htotal
= crtc
->mode
.htotal
;
1244 clock
= crtc
->mode
.clock
;
1245 pixel_size
= crtc
->fb
->bits_per_pixel
/ 8;
1247 line_time_us
= (htotal
* 1000) / clock
;
1248 line_count
= (latency_ns
/ line_time_us
+ 1000) / 1000;
1249 line_size
= hdisplay
* pixel_size
;
1251 /* Use the minimum of the small and large buffer method for primary */
1252 small
= ((clock
* pixel_size
/ 1000) * latency_ns
) / 1000;
1253 large
= line_count
* line_size
;
1255 entries
= DIV_ROUND_UP(min(small
, large
), display
->cacheline_size
);
1256 *display_wm
= entries
+ display
->guard_size
;
1258 /* calculate the self-refresh watermark for display cursor */
1259 entries
= line_count
* pixel_size
* 64;
1260 entries
= DIV_ROUND_UP(entries
, cursor
->cacheline_size
);
1261 *cursor_wm
= entries
+ cursor
->guard_size
;
1263 return g4x_check_srwm(dev
,
1264 *display_wm
, *cursor_wm
,
1268 static bool vlv_compute_drain_latency(struct drm_device
*dev
,
1270 int *plane_prec_mult
,
1272 int *cursor_prec_mult
,
1275 struct drm_crtc
*crtc
;
1276 int clock
, pixel_size
;
1279 crtc
= intel_get_crtc_for_plane(dev
, plane
);
1280 if (!intel_crtc_active(crtc
))
1283 clock
= crtc
->mode
.clock
; /* VESA DOT Clock */
1284 pixel_size
= crtc
->fb
->bits_per_pixel
/ 8; /* BPP */
1286 entries
= (clock
/ 1000) * pixel_size
;
1287 *plane_prec_mult
= (entries
> 256) ?
1288 DRAIN_LATENCY_PRECISION_32
: DRAIN_LATENCY_PRECISION_16
;
1289 *plane_dl
= (64 * (*plane_prec_mult
) * 4) / ((clock
/ 1000) *
1292 entries
= (clock
/ 1000) * 4; /* BPP is always 4 for cursor */
1293 *cursor_prec_mult
= (entries
> 256) ?
1294 DRAIN_LATENCY_PRECISION_32
: DRAIN_LATENCY_PRECISION_16
;
1295 *cursor_dl
= (64 * (*cursor_prec_mult
) * 4) / ((clock
/ 1000) * 4);
1301 * Update drain latency registers of memory arbiter
1303 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1304 * to be programmed. Each plane has a drain latency multiplier and a drain
1308 static void vlv_update_drain_latency(struct drm_device
*dev
)
1310 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1311 int planea_prec
, planea_dl
, planeb_prec
, planeb_dl
;
1312 int cursora_prec
, cursora_dl
, cursorb_prec
, cursorb_dl
;
1313 int plane_prec_mult
, cursor_prec_mult
; /* Precision multiplier is
1316 /* For plane A, Cursor A */
1317 if (vlv_compute_drain_latency(dev
, 0, &plane_prec_mult
, &planea_dl
,
1318 &cursor_prec_mult
, &cursora_dl
)) {
1319 cursora_prec
= (cursor_prec_mult
== DRAIN_LATENCY_PRECISION_32
) ?
1320 DDL_CURSORA_PRECISION_32
: DDL_CURSORA_PRECISION_16
;
1321 planea_prec
= (plane_prec_mult
== DRAIN_LATENCY_PRECISION_32
) ?
1322 DDL_PLANEA_PRECISION_32
: DDL_PLANEA_PRECISION_16
;
1324 I915_WRITE(VLV_DDL1
, cursora_prec
|
1325 (cursora_dl
<< DDL_CURSORA_SHIFT
) |
1326 planea_prec
| planea_dl
);
1329 /* For plane B, Cursor B */
1330 if (vlv_compute_drain_latency(dev
, 1, &plane_prec_mult
, &planeb_dl
,
1331 &cursor_prec_mult
, &cursorb_dl
)) {
1332 cursorb_prec
= (cursor_prec_mult
== DRAIN_LATENCY_PRECISION_32
) ?
1333 DDL_CURSORB_PRECISION_32
: DDL_CURSORB_PRECISION_16
;
1334 planeb_prec
= (plane_prec_mult
== DRAIN_LATENCY_PRECISION_32
) ?
1335 DDL_PLANEB_PRECISION_32
: DDL_PLANEB_PRECISION_16
;
1337 I915_WRITE(VLV_DDL2
, cursorb_prec
|
1338 (cursorb_dl
<< DDL_CURSORB_SHIFT
) |
1339 planeb_prec
| planeb_dl
);
1343 #define single_plane_enabled(mask) is_power_of_2(mask)
1345 static void valleyview_update_wm(struct drm_device
*dev
)
1347 static const int sr_latency_ns
= 12000;
1348 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1349 int planea_wm
, planeb_wm
, cursora_wm
, cursorb_wm
;
1350 int plane_sr
, cursor_sr
;
1351 int ignore_plane_sr
, ignore_cursor_sr
;
1352 unsigned int enabled
= 0;
1354 vlv_update_drain_latency(dev
);
1356 if (g4x_compute_wm0(dev
, PIPE_A
,
1357 &valleyview_wm_info
, latency_ns
,
1358 &valleyview_cursor_wm_info
, latency_ns
,
1359 &planea_wm
, &cursora_wm
))
1360 enabled
|= 1 << PIPE_A
;
1362 if (g4x_compute_wm0(dev
, PIPE_B
,
1363 &valleyview_wm_info
, latency_ns
,
1364 &valleyview_cursor_wm_info
, latency_ns
,
1365 &planeb_wm
, &cursorb_wm
))
1366 enabled
|= 1 << PIPE_B
;
1368 if (single_plane_enabled(enabled
) &&
1369 g4x_compute_srwm(dev
, ffs(enabled
) - 1,
1371 &valleyview_wm_info
,
1372 &valleyview_cursor_wm_info
,
1373 &plane_sr
, &ignore_cursor_sr
) &&
1374 g4x_compute_srwm(dev
, ffs(enabled
) - 1,
1376 &valleyview_wm_info
,
1377 &valleyview_cursor_wm_info
,
1378 &ignore_plane_sr
, &cursor_sr
)) {
1379 I915_WRITE(FW_BLC_SELF_VLV
, FW_CSPWRDWNEN
);
1381 I915_WRITE(FW_BLC_SELF_VLV
,
1382 I915_READ(FW_BLC_SELF_VLV
) & ~FW_CSPWRDWNEN
);
1383 plane_sr
= cursor_sr
= 0;
1386 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1387 planea_wm
, cursora_wm
,
1388 planeb_wm
, cursorb_wm
,
1389 plane_sr
, cursor_sr
);
1392 (plane_sr
<< DSPFW_SR_SHIFT
) |
1393 (cursorb_wm
<< DSPFW_CURSORB_SHIFT
) |
1394 (planeb_wm
<< DSPFW_PLANEB_SHIFT
) |
1397 (I915_READ(DSPFW2
) & ~DSPFW_CURSORA_MASK
) |
1398 (cursora_wm
<< DSPFW_CURSORA_SHIFT
));
1400 (I915_READ(DSPFW3
) & ~DSPFW_CURSOR_SR_MASK
) |
1401 (cursor_sr
<< DSPFW_CURSOR_SR_SHIFT
));
1404 static void g4x_update_wm(struct drm_device
*dev
)
1406 static const int sr_latency_ns
= 12000;
1407 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1408 int planea_wm
, planeb_wm
, cursora_wm
, cursorb_wm
;
1409 int plane_sr
, cursor_sr
;
1410 unsigned int enabled
= 0;
1412 if (g4x_compute_wm0(dev
, PIPE_A
,
1413 &g4x_wm_info
, latency_ns
,
1414 &g4x_cursor_wm_info
, latency_ns
,
1415 &planea_wm
, &cursora_wm
))
1416 enabled
|= 1 << PIPE_A
;
1418 if (g4x_compute_wm0(dev
, PIPE_B
,
1419 &g4x_wm_info
, latency_ns
,
1420 &g4x_cursor_wm_info
, latency_ns
,
1421 &planeb_wm
, &cursorb_wm
))
1422 enabled
|= 1 << PIPE_B
;
1424 if (single_plane_enabled(enabled
) &&
1425 g4x_compute_srwm(dev
, ffs(enabled
) - 1,
1428 &g4x_cursor_wm_info
,
1429 &plane_sr
, &cursor_sr
)) {
1430 I915_WRITE(FW_BLC_SELF
, FW_BLC_SELF_EN
);
1432 I915_WRITE(FW_BLC_SELF
,
1433 I915_READ(FW_BLC_SELF
) & ~FW_BLC_SELF_EN
);
1434 plane_sr
= cursor_sr
= 0;
1437 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1438 planea_wm
, cursora_wm
,
1439 planeb_wm
, cursorb_wm
,
1440 plane_sr
, cursor_sr
);
1443 (plane_sr
<< DSPFW_SR_SHIFT
) |
1444 (cursorb_wm
<< DSPFW_CURSORB_SHIFT
) |
1445 (planeb_wm
<< DSPFW_PLANEB_SHIFT
) |
1448 (I915_READ(DSPFW2
) & ~DSPFW_CURSORA_MASK
) |
1449 (cursora_wm
<< DSPFW_CURSORA_SHIFT
));
1450 /* HPLL off in SR has some issues on G4x... disable it */
1452 (I915_READ(DSPFW3
) & ~(DSPFW_HPLL_SR_EN
| DSPFW_CURSOR_SR_MASK
)) |
1453 (cursor_sr
<< DSPFW_CURSOR_SR_SHIFT
));
1456 static void i965_update_wm(struct drm_device
*dev
)
1458 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1459 struct drm_crtc
*crtc
;
1463 /* Calc sr entries for one plane configs */
1464 crtc
= single_enabled_crtc(dev
);
1466 /* self-refresh has much higher latency */
1467 static const int sr_latency_ns
= 12000;
1468 int clock
= crtc
->mode
.clock
;
1469 int htotal
= crtc
->mode
.htotal
;
1470 int hdisplay
= crtc
->mode
.hdisplay
;
1471 int pixel_size
= crtc
->fb
->bits_per_pixel
/ 8;
1472 unsigned long line_time_us
;
1475 line_time_us
= ((htotal
* 1000) / clock
);
1477 /* Use ns/us then divide to preserve precision */
1478 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
1479 pixel_size
* hdisplay
;
1480 entries
= DIV_ROUND_UP(entries
, I915_FIFO_LINE_SIZE
);
1481 srwm
= I965_FIFO_SIZE
- entries
;
1485 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1488 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
1490 entries
= DIV_ROUND_UP(entries
,
1491 i965_cursor_wm_info
.cacheline_size
);
1492 cursor_sr
= i965_cursor_wm_info
.fifo_size
-
1493 (entries
+ i965_cursor_wm_info
.guard_size
);
1495 if (cursor_sr
> i965_cursor_wm_info
.max_wm
)
1496 cursor_sr
= i965_cursor_wm_info
.max_wm
;
1498 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1499 "cursor %d\n", srwm
, cursor_sr
);
1501 if (IS_CRESTLINE(dev
))
1502 I915_WRITE(FW_BLC_SELF
, FW_BLC_SELF_EN
);
1504 /* Turn off self refresh if both pipes are enabled */
1505 if (IS_CRESTLINE(dev
))
1506 I915_WRITE(FW_BLC_SELF
, I915_READ(FW_BLC_SELF
)
1510 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1513 /* 965 has limitations... */
1514 I915_WRITE(DSPFW1
, (srwm
<< DSPFW_SR_SHIFT
) |
1515 (8 << 16) | (8 << 8) | (8 << 0));
1516 I915_WRITE(DSPFW2
, (8 << 8) | (8 << 0));
1517 /* update cursor SR watermark */
1518 I915_WRITE(DSPFW3
, (cursor_sr
<< DSPFW_CURSOR_SR_SHIFT
));
1521 static void i9xx_update_wm(struct drm_device
*dev
)
1523 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1524 const struct intel_watermark_params
*wm_info
;
1529 int planea_wm
, planeb_wm
;
1530 struct drm_crtc
*crtc
, *enabled
= NULL
;
1533 wm_info
= &i945_wm_info
;
1534 else if (!IS_GEN2(dev
))
1535 wm_info
= &i915_wm_info
;
1537 wm_info
= &i855_wm_info
;
1539 fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 0);
1540 crtc
= intel_get_crtc_for_plane(dev
, 0);
1541 if (intel_crtc_active(crtc
)) {
1542 int cpp
= crtc
->fb
->bits_per_pixel
/ 8;
1546 planea_wm
= intel_calculate_wm(crtc
->mode
.clock
,
1547 wm_info
, fifo_size
, cpp
,
1551 planea_wm
= fifo_size
- wm_info
->guard_size
;
1553 fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 1);
1554 crtc
= intel_get_crtc_for_plane(dev
, 1);
1555 if (intel_crtc_active(crtc
)) {
1556 int cpp
= crtc
->fb
->bits_per_pixel
/ 8;
1560 planeb_wm
= intel_calculate_wm(crtc
->mode
.clock
,
1561 wm_info
, fifo_size
, cpp
,
1563 if (enabled
== NULL
)
1568 planeb_wm
= fifo_size
- wm_info
->guard_size
;
1570 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm
, planeb_wm
);
1573 * Overlay gets an aggressive default since video jitter is bad.
1577 /* Play safe and disable self-refresh before adjusting watermarks. */
1578 if (IS_I945G(dev
) || IS_I945GM(dev
))
1579 I915_WRITE(FW_BLC_SELF
, FW_BLC_SELF_EN_MASK
| 0);
1580 else if (IS_I915GM(dev
))
1581 I915_WRITE(INSTPM
, I915_READ(INSTPM
) & ~INSTPM_SELF_EN
);
1583 /* Calc sr entries for one plane configs */
1584 if (HAS_FW_BLC(dev
) && enabled
) {
1585 /* self-refresh has much higher latency */
1586 static const int sr_latency_ns
= 6000;
1587 int clock
= enabled
->mode
.clock
;
1588 int htotal
= enabled
->mode
.htotal
;
1589 int hdisplay
= enabled
->mode
.hdisplay
;
1590 int pixel_size
= enabled
->fb
->bits_per_pixel
/ 8;
1591 unsigned long line_time_us
;
1594 line_time_us
= (htotal
* 1000) / clock
;
1596 /* Use ns/us then divide to preserve precision */
1597 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
1598 pixel_size
* hdisplay
;
1599 entries
= DIV_ROUND_UP(entries
, wm_info
->cacheline_size
);
1600 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries
);
1601 srwm
= wm_info
->fifo_size
- entries
;
1605 if (IS_I945G(dev
) || IS_I945GM(dev
))
1606 I915_WRITE(FW_BLC_SELF
,
1607 FW_BLC_SELF_FIFO_MASK
| (srwm
& 0xff));
1608 else if (IS_I915GM(dev
))
1609 I915_WRITE(FW_BLC_SELF
, srwm
& 0x3f);
1612 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1613 planea_wm
, planeb_wm
, cwm
, srwm
);
1615 fwater_lo
= ((planeb_wm
& 0x3f) << 16) | (planea_wm
& 0x3f);
1616 fwater_hi
= (cwm
& 0x1f);
1618 /* Set request length to 8 cachelines per fetch */
1619 fwater_lo
= fwater_lo
| (1 << 24) | (1 << 8);
1620 fwater_hi
= fwater_hi
| (1 << 8);
1622 I915_WRITE(FW_BLC
, fwater_lo
);
1623 I915_WRITE(FW_BLC2
, fwater_hi
);
1625 if (HAS_FW_BLC(dev
)) {
1627 if (IS_I945G(dev
) || IS_I945GM(dev
))
1628 I915_WRITE(FW_BLC_SELF
,
1629 FW_BLC_SELF_EN_MASK
| FW_BLC_SELF_EN
);
1630 else if (IS_I915GM(dev
))
1631 I915_WRITE(INSTPM
, I915_READ(INSTPM
) | INSTPM_SELF_EN
);
1632 DRM_DEBUG_KMS("memory self refresh enabled\n");
1634 DRM_DEBUG_KMS("memory self refresh disabled\n");
1638 static void i830_update_wm(struct drm_device
*dev
)
1640 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1641 struct drm_crtc
*crtc
;
1645 crtc
= single_enabled_crtc(dev
);
1649 planea_wm
= intel_calculate_wm(crtc
->mode
.clock
, &i830_wm_info
,
1650 dev_priv
->display
.get_fifo_size(dev
, 0),
1652 fwater_lo
= I915_READ(FW_BLC
) & ~0xfff;
1653 fwater_lo
|= (3<<8) | planea_wm
;
1655 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm
);
1657 I915_WRITE(FW_BLC
, fwater_lo
);
1660 #define ILK_LP0_PLANE_LATENCY 700
1661 #define ILK_LP0_CURSOR_LATENCY 1300
1664 * Check the wm result.
1666 * If any calculated watermark values is larger than the maximum value that
1667 * can be programmed into the associated watermark register, that watermark
1670 static bool ironlake_check_srwm(struct drm_device
*dev
, int level
,
1671 int fbc_wm
, int display_wm
, int cursor_wm
,
1672 const struct intel_watermark_params
*display
,
1673 const struct intel_watermark_params
*cursor
)
1675 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1677 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
1678 " cursor %d\n", level
, display_wm
, fbc_wm
, cursor_wm
);
1680 if (fbc_wm
> SNB_FBC_MAX_SRWM
) {
1681 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
1682 fbc_wm
, SNB_FBC_MAX_SRWM
, level
);
1684 /* fbc has it's own way to disable FBC WM */
1685 I915_WRITE(DISP_ARB_CTL
,
1686 I915_READ(DISP_ARB_CTL
) | DISP_FBC_WM_DIS
);
1688 } else if (INTEL_INFO(dev
)->gen
>= 6) {
1689 /* enable FBC WM (except on ILK, where it must remain off) */
1690 I915_WRITE(DISP_ARB_CTL
,
1691 I915_READ(DISP_ARB_CTL
) & ~DISP_FBC_WM_DIS
);
1694 if (display_wm
> display
->max_wm
) {
1695 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
1696 display_wm
, SNB_DISPLAY_MAX_SRWM
, level
);
1700 if (cursor_wm
> cursor
->max_wm
) {
1701 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
1702 cursor_wm
, SNB_CURSOR_MAX_SRWM
, level
);
1706 if (!(fbc_wm
|| display_wm
|| cursor_wm
)) {
1707 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level
, level
);
1715 * Compute watermark values of WM[1-3],
1717 static bool ironlake_compute_srwm(struct drm_device
*dev
, int level
, int plane
,
1719 const struct intel_watermark_params
*display
,
1720 const struct intel_watermark_params
*cursor
,
1721 int *fbc_wm
, int *display_wm
, int *cursor_wm
)
1723 struct drm_crtc
*crtc
;
1724 unsigned long line_time_us
;
1725 int hdisplay
, htotal
, pixel_size
, clock
;
1726 int line_count
, line_size
;
1731 *fbc_wm
= *display_wm
= *cursor_wm
= 0;
1735 crtc
= intel_get_crtc_for_plane(dev
, plane
);
1736 hdisplay
= crtc
->mode
.hdisplay
;
1737 htotal
= crtc
->mode
.htotal
;
1738 clock
= crtc
->mode
.clock
;
1739 pixel_size
= crtc
->fb
->bits_per_pixel
/ 8;
1741 line_time_us
= (htotal
* 1000) / clock
;
1742 line_count
= (latency_ns
/ line_time_us
+ 1000) / 1000;
1743 line_size
= hdisplay
* pixel_size
;
1745 /* Use the minimum of the small and large buffer method for primary */
1746 small
= ((clock
* pixel_size
/ 1000) * latency_ns
) / 1000;
1747 large
= line_count
* line_size
;
1749 entries
= DIV_ROUND_UP(min(small
, large
), display
->cacheline_size
);
1750 *display_wm
= entries
+ display
->guard_size
;
1754 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
1756 *fbc_wm
= DIV_ROUND_UP(*display_wm
* 64, line_size
) + 2;
1758 /* calculate the self-refresh watermark for display cursor */
1759 entries
= line_count
* pixel_size
* 64;
1760 entries
= DIV_ROUND_UP(entries
, cursor
->cacheline_size
);
1761 *cursor_wm
= entries
+ cursor
->guard_size
;
1763 return ironlake_check_srwm(dev
, level
,
1764 *fbc_wm
, *display_wm
, *cursor_wm
,
1768 static void ironlake_update_wm(struct drm_device
*dev
)
1770 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1771 int fbc_wm
, plane_wm
, cursor_wm
;
1772 unsigned int enabled
;
1775 if (g4x_compute_wm0(dev
, PIPE_A
,
1776 &ironlake_display_wm_info
,
1777 ILK_LP0_PLANE_LATENCY
,
1778 &ironlake_cursor_wm_info
,
1779 ILK_LP0_CURSOR_LATENCY
,
1780 &plane_wm
, &cursor_wm
)) {
1781 I915_WRITE(WM0_PIPEA_ILK
,
1782 (plane_wm
<< WM0_PIPE_PLANE_SHIFT
) | cursor_wm
);
1783 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1784 " plane %d, " "cursor: %d\n",
1785 plane_wm
, cursor_wm
);
1786 enabled
|= 1 << PIPE_A
;
1789 if (g4x_compute_wm0(dev
, PIPE_B
,
1790 &ironlake_display_wm_info
,
1791 ILK_LP0_PLANE_LATENCY
,
1792 &ironlake_cursor_wm_info
,
1793 ILK_LP0_CURSOR_LATENCY
,
1794 &plane_wm
, &cursor_wm
)) {
1795 I915_WRITE(WM0_PIPEB_ILK
,
1796 (plane_wm
<< WM0_PIPE_PLANE_SHIFT
) | cursor_wm
);
1797 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1798 " plane %d, cursor: %d\n",
1799 plane_wm
, cursor_wm
);
1800 enabled
|= 1 << PIPE_B
;
1804 * Calculate and update the self-refresh watermark only when one
1805 * display plane is used.
1807 I915_WRITE(WM3_LP_ILK
, 0);
1808 I915_WRITE(WM2_LP_ILK
, 0);
1809 I915_WRITE(WM1_LP_ILK
, 0);
1811 if (!single_plane_enabled(enabled
))
1813 enabled
= ffs(enabled
) - 1;
1816 if (!ironlake_compute_srwm(dev
, 1, enabled
,
1817 ILK_READ_WM1_LATENCY() * 500,
1818 &ironlake_display_srwm_info
,
1819 &ironlake_cursor_srwm_info
,
1820 &fbc_wm
, &plane_wm
, &cursor_wm
))
1823 I915_WRITE(WM1_LP_ILK
,
1825 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT
) |
1826 (fbc_wm
<< WM1_LP_FBC_SHIFT
) |
1827 (plane_wm
<< WM1_LP_SR_SHIFT
) |
1831 if (!ironlake_compute_srwm(dev
, 2, enabled
,
1832 ILK_READ_WM2_LATENCY() * 500,
1833 &ironlake_display_srwm_info
,
1834 &ironlake_cursor_srwm_info
,
1835 &fbc_wm
, &plane_wm
, &cursor_wm
))
1838 I915_WRITE(WM2_LP_ILK
,
1840 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT
) |
1841 (fbc_wm
<< WM1_LP_FBC_SHIFT
) |
1842 (plane_wm
<< WM1_LP_SR_SHIFT
) |
1846 * WM3 is unsupported on ILK, probably because we don't have latency
1847 * data for that power state
1851 static void sandybridge_update_wm(struct drm_device
*dev
)
1853 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1854 int latency
= SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
1856 int fbc_wm
, plane_wm
, cursor_wm
;
1857 unsigned int enabled
;
1860 if (g4x_compute_wm0(dev
, PIPE_A
,
1861 &sandybridge_display_wm_info
, latency
,
1862 &sandybridge_cursor_wm_info
, latency
,
1863 &plane_wm
, &cursor_wm
)) {
1864 val
= I915_READ(WM0_PIPEA_ILK
);
1865 val
&= ~(WM0_PIPE_PLANE_MASK
| WM0_PIPE_CURSOR_MASK
);
1866 I915_WRITE(WM0_PIPEA_ILK
, val
|
1867 ((plane_wm
<< WM0_PIPE_PLANE_SHIFT
) | cursor_wm
));
1868 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1869 " plane %d, " "cursor: %d\n",
1870 plane_wm
, cursor_wm
);
1871 enabled
|= 1 << PIPE_A
;
1874 if (g4x_compute_wm0(dev
, PIPE_B
,
1875 &sandybridge_display_wm_info
, latency
,
1876 &sandybridge_cursor_wm_info
, latency
,
1877 &plane_wm
, &cursor_wm
)) {
1878 val
= I915_READ(WM0_PIPEB_ILK
);
1879 val
&= ~(WM0_PIPE_PLANE_MASK
| WM0_PIPE_CURSOR_MASK
);
1880 I915_WRITE(WM0_PIPEB_ILK
, val
|
1881 ((plane_wm
<< WM0_PIPE_PLANE_SHIFT
) | cursor_wm
));
1882 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1883 " plane %d, cursor: %d\n",
1884 plane_wm
, cursor_wm
);
1885 enabled
|= 1 << PIPE_B
;
1889 * Calculate and update the self-refresh watermark only when one
1890 * display plane is used.
1892 * SNB support 3 levels of watermark.
1894 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1895 * and disabled in the descending order
1898 I915_WRITE(WM3_LP_ILK
, 0);
1899 I915_WRITE(WM2_LP_ILK
, 0);
1900 I915_WRITE(WM1_LP_ILK
, 0);
1902 if (!single_plane_enabled(enabled
) ||
1903 dev_priv
->sprite_scaling_enabled
)
1905 enabled
= ffs(enabled
) - 1;
1908 if (!ironlake_compute_srwm(dev
, 1, enabled
,
1909 SNB_READ_WM1_LATENCY() * 500,
1910 &sandybridge_display_srwm_info
,
1911 &sandybridge_cursor_srwm_info
,
1912 &fbc_wm
, &plane_wm
, &cursor_wm
))
1915 I915_WRITE(WM1_LP_ILK
,
1917 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT
) |
1918 (fbc_wm
<< WM1_LP_FBC_SHIFT
) |
1919 (plane_wm
<< WM1_LP_SR_SHIFT
) |
1923 if (!ironlake_compute_srwm(dev
, 2, enabled
,
1924 SNB_READ_WM2_LATENCY() * 500,
1925 &sandybridge_display_srwm_info
,
1926 &sandybridge_cursor_srwm_info
,
1927 &fbc_wm
, &plane_wm
, &cursor_wm
))
1930 I915_WRITE(WM2_LP_ILK
,
1932 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT
) |
1933 (fbc_wm
<< WM1_LP_FBC_SHIFT
) |
1934 (plane_wm
<< WM1_LP_SR_SHIFT
) |
1938 if (!ironlake_compute_srwm(dev
, 3, enabled
,
1939 SNB_READ_WM3_LATENCY() * 500,
1940 &sandybridge_display_srwm_info
,
1941 &sandybridge_cursor_srwm_info
,
1942 &fbc_wm
, &plane_wm
, &cursor_wm
))
1945 I915_WRITE(WM3_LP_ILK
,
1947 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT
) |
1948 (fbc_wm
<< WM1_LP_FBC_SHIFT
) |
1949 (plane_wm
<< WM1_LP_SR_SHIFT
) |
1953 static void ivybridge_update_wm(struct drm_device
*dev
)
1955 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1956 int latency
= SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
1958 int fbc_wm
, plane_wm
, cursor_wm
;
1959 int ignore_fbc_wm
, ignore_plane_wm
, ignore_cursor_wm
;
1960 unsigned int enabled
;
1963 if (g4x_compute_wm0(dev
, PIPE_A
,
1964 &sandybridge_display_wm_info
, latency
,
1965 &sandybridge_cursor_wm_info
, latency
,
1966 &plane_wm
, &cursor_wm
)) {
1967 val
= I915_READ(WM0_PIPEA_ILK
);
1968 val
&= ~(WM0_PIPE_PLANE_MASK
| WM0_PIPE_CURSOR_MASK
);
1969 I915_WRITE(WM0_PIPEA_ILK
, val
|
1970 ((plane_wm
<< WM0_PIPE_PLANE_SHIFT
) | cursor_wm
));
1971 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1972 " plane %d, " "cursor: %d\n",
1973 plane_wm
, cursor_wm
);
1974 enabled
|= 1 << PIPE_A
;
1977 if (g4x_compute_wm0(dev
, PIPE_B
,
1978 &sandybridge_display_wm_info
, latency
,
1979 &sandybridge_cursor_wm_info
, latency
,
1980 &plane_wm
, &cursor_wm
)) {
1981 val
= I915_READ(WM0_PIPEB_ILK
);
1982 val
&= ~(WM0_PIPE_PLANE_MASK
| WM0_PIPE_CURSOR_MASK
);
1983 I915_WRITE(WM0_PIPEB_ILK
, val
|
1984 ((plane_wm
<< WM0_PIPE_PLANE_SHIFT
) | cursor_wm
));
1985 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1986 " plane %d, cursor: %d\n",
1987 plane_wm
, cursor_wm
);
1988 enabled
|= 1 << PIPE_B
;
1991 if (g4x_compute_wm0(dev
, PIPE_C
,
1992 &sandybridge_display_wm_info
, latency
,
1993 &sandybridge_cursor_wm_info
, latency
,
1994 &plane_wm
, &cursor_wm
)) {
1995 val
= I915_READ(WM0_PIPEC_IVB
);
1996 val
&= ~(WM0_PIPE_PLANE_MASK
| WM0_PIPE_CURSOR_MASK
);
1997 I915_WRITE(WM0_PIPEC_IVB
, val
|
1998 ((plane_wm
<< WM0_PIPE_PLANE_SHIFT
) | cursor_wm
));
1999 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
2000 " plane %d, cursor: %d\n",
2001 plane_wm
, cursor_wm
);
2002 enabled
|= 1 << PIPE_C
;
2006 * Calculate and update the self-refresh watermark only when one
2007 * display plane is used.
2009 * SNB support 3 levels of watermark.
2011 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
2012 * and disabled in the descending order
2015 I915_WRITE(WM3_LP_ILK
, 0);
2016 I915_WRITE(WM2_LP_ILK
, 0);
2017 I915_WRITE(WM1_LP_ILK
, 0);
2019 if (!single_plane_enabled(enabled
) ||
2020 dev_priv
->sprite_scaling_enabled
)
2022 enabled
= ffs(enabled
) - 1;
2025 if (!ironlake_compute_srwm(dev
, 1, enabled
,
2026 SNB_READ_WM1_LATENCY() * 500,
2027 &sandybridge_display_srwm_info
,
2028 &sandybridge_cursor_srwm_info
,
2029 &fbc_wm
, &plane_wm
, &cursor_wm
))
2032 I915_WRITE(WM1_LP_ILK
,
2034 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT
) |
2035 (fbc_wm
<< WM1_LP_FBC_SHIFT
) |
2036 (plane_wm
<< WM1_LP_SR_SHIFT
) |
2040 if (!ironlake_compute_srwm(dev
, 2, enabled
,
2041 SNB_READ_WM2_LATENCY() * 500,
2042 &sandybridge_display_srwm_info
,
2043 &sandybridge_cursor_srwm_info
,
2044 &fbc_wm
, &plane_wm
, &cursor_wm
))
2047 I915_WRITE(WM2_LP_ILK
,
2049 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT
) |
2050 (fbc_wm
<< WM1_LP_FBC_SHIFT
) |
2051 (plane_wm
<< WM1_LP_SR_SHIFT
) |
2054 /* WM3, note we have to correct the cursor latency */
2055 if (!ironlake_compute_srwm(dev
, 3, enabled
,
2056 SNB_READ_WM3_LATENCY() * 500,
2057 &sandybridge_display_srwm_info
,
2058 &sandybridge_cursor_srwm_info
,
2059 &fbc_wm
, &plane_wm
, &ignore_cursor_wm
) ||
2060 !ironlake_compute_srwm(dev
, 3, enabled
,
2061 2 * SNB_READ_WM3_LATENCY() * 500,
2062 &sandybridge_display_srwm_info
,
2063 &sandybridge_cursor_srwm_info
,
2064 &ignore_fbc_wm
, &ignore_plane_wm
, &cursor_wm
))
2067 I915_WRITE(WM3_LP_ILK
,
2069 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT
) |
2070 (fbc_wm
<< WM1_LP_FBC_SHIFT
) |
2071 (plane_wm
<< WM1_LP_SR_SHIFT
) |
2075 static uint32_t hsw_wm_get_pixel_rate(struct drm_device
*dev
,
2076 struct drm_crtc
*crtc
)
2078 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2079 uint32_t pixel_rate
, pfit_size
;
2081 if (intel_crtc
->config
.pixel_target_clock
)
2082 pixel_rate
= intel_crtc
->config
.pixel_target_clock
;
2084 pixel_rate
= intel_crtc
->config
.adjusted_mode
.clock
;
2086 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
2087 * adjust the pixel_rate here. */
2089 pfit_size
= intel_crtc
->config
.pch_pfit
.size
;
2091 uint64_t pipe_w
, pipe_h
, pfit_w
, pfit_h
;
2093 pipe_w
= intel_crtc
->config
.requested_mode
.hdisplay
;
2094 pipe_h
= intel_crtc
->config
.requested_mode
.vdisplay
;
2095 pfit_w
= (pfit_size
>> 16) & 0xFFFF;
2096 pfit_h
= pfit_size
& 0xFFFF;
2097 if (pipe_w
< pfit_w
)
2099 if (pipe_h
< pfit_h
)
2102 pixel_rate
= div_u64((uint64_t) pixel_rate
* pipe_w
* pipe_h
,
2109 static uint32_t hsw_wm_method1(uint32_t pixel_rate
, uint8_t bytes_per_pixel
,
2114 ret
= (uint64_t) pixel_rate
* bytes_per_pixel
* latency
;
2115 ret
= DIV_ROUND_UP_ULL(ret
, 64 * 10000) + 2;
2120 static uint32_t hsw_wm_method2(uint32_t pixel_rate
, uint32_t pipe_htotal
,
2121 uint32_t horiz_pixels
, uint8_t bytes_per_pixel
,
2126 ret
= (latency
* pixel_rate
) / (pipe_htotal
* 10000);
2127 ret
= (ret
+ 1) * horiz_pixels
* bytes_per_pixel
;
2128 ret
= DIV_ROUND_UP(ret
, 64) + 2;
2132 static uint32_t hsw_wm_fbc(uint32_t pri_val
, uint32_t horiz_pixels
,
2133 uint8_t bytes_per_pixel
)
2135 return DIV_ROUND_UP(pri_val
* 64, horiz_pixels
* bytes_per_pixel
) + 2;
2138 struct hsw_pipe_wm_parameters
{
2140 bool sprite_enabled
;
2141 uint8_t pri_bytes_per_pixel
;
2142 uint8_t spr_bytes_per_pixel
;
2143 uint8_t cur_bytes_per_pixel
;
2144 uint32_t pri_horiz_pixels
;
2145 uint32_t spr_horiz_pixels
;
2146 uint32_t cur_horiz_pixels
;
2147 uint32_t pipe_htotal
;
2148 uint32_t pixel_rate
;
2151 struct hsw_wm_maximums
{
2158 struct hsw_lp_wm_result
{
2167 struct hsw_wm_values
{
2168 uint32_t wm_pipe
[3];
2170 uint32_t wm_lp_spr
[3];
2171 uint32_t wm_linetime
[3];
2175 enum hsw_data_buf_partitioning
{
2176 HSW_DATA_BUF_PART_1_2
,
2177 HSW_DATA_BUF_PART_5_6
,
2180 /* For both WM_PIPE and WM_LP. */
2181 static uint32_t hsw_compute_pri_wm(struct hsw_pipe_wm_parameters
*params
,
2185 uint32_t method1
, method2
;
2187 /* TODO: for now, assume the primary plane is always enabled. */
2188 if (!params
->active
)
2191 method1
= hsw_wm_method1(params
->pixel_rate
,
2192 params
->pri_bytes_per_pixel
,
2198 method2
= hsw_wm_method2(params
->pixel_rate
,
2199 params
->pipe_htotal
,
2200 params
->pri_horiz_pixels
,
2201 params
->pri_bytes_per_pixel
,
2204 return min(method1
, method2
);
2207 /* For both WM_PIPE and WM_LP. */
2208 static uint32_t hsw_compute_spr_wm(struct hsw_pipe_wm_parameters
*params
,
2211 uint32_t method1
, method2
;
2213 if (!params
->active
|| !params
->sprite_enabled
)
2216 method1
= hsw_wm_method1(params
->pixel_rate
,
2217 params
->spr_bytes_per_pixel
,
2219 method2
= hsw_wm_method2(params
->pixel_rate
,
2220 params
->pipe_htotal
,
2221 params
->spr_horiz_pixels
,
2222 params
->spr_bytes_per_pixel
,
2224 return min(method1
, method2
);
2227 /* For both WM_PIPE and WM_LP. */
2228 static uint32_t hsw_compute_cur_wm(struct hsw_pipe_wm_parameters
*params
,
2231 if (!params
->active
)
2234 return hsw_wm_method2(params
->pixel_rate
,
2235 params
->pipe_htotal
,
2236 params
->cur_horiz_pixels
,
2237 params
->cur_bytes_per_pixel
,
2241 /* Only for WM_LP. */
2242 static uint32_t hsw_compute_fbc_wm(struct hsw_pipe_wm_parameters
*params
,
2246 if (!params
->active
)
2249 return hsw_wm_fbc(pri_val
,
2250 params
->pri_horiz_pixels
,
2251 params
->pri_bytes_per_pixel
);
2254 static bool hsw_compute_lp_wm(uint32_t mem_value
, struct hsw_wm_maximums
*max
,
2255 struct hsw_pipe_wm_parameters
*params
,
2256 struct hsw_lp_wm_result
*result
)
2259 uint32_t pri_val
[3], spr_val
[3], cur_val
[3], fbc_val
[3];
2261 for (pipe
= PIPE_A
; pipe
<= PIPE_C
; pipe
++) {
2262 struct hsw_pipe_wm_parameters
*p
= ¶ms
[pipe
];
2264 pri_val
[pipe
] = hsw_compute_pri_wm(p
, mem_value
, true);
2265 spr_val
[pipe
] = hsw_compute_spr_wm(p
, mem_value
);
2266 cur_val
[pipe
] = hsw_compute_cur_wm(p
, mem_value
);
2267 fbc_val
[pipe
] = hsw_compute_fbc_wm(p
, pri_val
[pipe
], mem_value
);
2270 result
->pri_val
= max3(pri_val
[0], pri_val
[1], pri_val
[2]);
2271 result
->spr_val
= max3(spr_val
[0], spr_val
[1], spr_val
[2]);
2272 result
->cur_val
= max3(cur_val
[0], cur_val
[1], cur_val
[2]);
2273 result
->fbc_val
= max3(fbc_val
[0], fbc_val
[1], fbc_val
[2]);
2275 if (result
->fbc_val
> max
->fbc
) {
2276 result
->fbc_enable
= false;
2277 result
->fbc_val
= 0;
2279 result
->fbc_enable
= true;
2282 result
->enable
= result
->pri_val
<= max
->pri
&&
2283 result
->spr_val
<= max
->spr
&&
2284 result
->cur_val
<= max
->cur
;
2285 return result
->enable
;
2288 static uint32_t hsw_compute_wm_pipe(struct drm_i915_private
*dev_priv
,
2289 uint32_t mem_value
, enum pipe pipe
,
2290 struct hsw_pipe_wm_parameters
*params
)
2292 uint32_t pri_val
, cur_val
, spr_val
;
2294 pri_val
= hsw_compute_pri_wm(params
, mem_value
, false);
2295 spr_val
= hsw_compute_spr_wm(params
, mem_value
);
2296 cur_val
= hsw_compute_cur_wm(params
, mem_value
);
2299 "Primary WM error, mode not supported for pipe %c\n",
2302 "Sprite WM error, mode not supported for pipe %c\n",
2305 "Cursor WM error, mode not supported for pipe %c\n",
2308 return (pri_val
<< WM0_PIPE_PLANE_SHIFT
) |
2309 (spr_val
<< WM0_PIPE_SPRITE_SHIFT
) |
2314 hsw_compute_linetime_wm(struct drm_device
*dev
, struct drm_crtc
*crtc
)
2316 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2317 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2318 struct drm_display_mode
*mode
= &intel_crtc
->config
.adjusted_mode
;
2319 u32 linetime
, ips_linetime
;
2321 if (!intel_crtc_active(crtc
))
2324 /* The WM are computed with base on how long it takes to fill a single
2325 * row at the given clock rate, multiplied by 8.
2327 linetime
= DIV_ROUND_CLOSEST(mode
->htotal
* 1000 * 8, mode
->clock
);
2328 ips_linetime
= DIV_ROUND_CLOSEST(mode
->htotal
* 1000 * 8,
2329 intel_ddi_get_cdclk_freq(dev_priv
));
2331 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime
) |
2332 PIPE_WM_LINETIME_TIME(linetime
);
2335 static void hsw_compute_wm_parameters(struct drm_device
*dev
,
2336 struct hsw_pipe_wm_parameters
*params
,
2338 struct hsw_wm_maximums
*lp_max_1_2
,
2339 struct hsw_wm_maximums
*lp_max_5_6
)
2341 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2342 struct drm_crtc
*crtc
;
2343 struct drm_plane
*plane
;
2344 uint64_t sskpd
= I915_READ64(MCH_SSKPD
);
2346 int pipes_active
= 0, sprites_enabled
= 0;
2348 if ((sskpd
>> 56) & 0xFF)
2349 wm
[0] = (sskpd
>> 56) & 0xFF;
2351 wm
[0] = sskpd
& 0xF;
2352 wm
[1] = ((sskpd
>> 4) & 0xFF) * 5;
2353 wm
[2] = ((sskpd
>> 12) & 0xFF) * 5;
2354 wm
[3] = ((sskpd
>> 20) & 0x1FF) * 5;
2355 wm
[4] = ((sskpd
>> 32) & 0x1FF) * 5;
2357 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
2358 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2359 struct hsw_pipe_wm_parameters
*p
;
2361 pipe
= intel_crtc
->pipe
;
2364 p
->active
= intel_crtc_active(crtc
);
2370 p
->pipe_htotal
= intel_crtc
->config
.adjusted_mode
.htotal
;
2371 p
->pixel_rate
= hsw_wm_get_pixel_rate(dev
, crtc
);
2372 p
->pri_bytes_per_pixel
= crtc
->fb
->bits_per_pixel
/ 8;
2373 p
->cur_bytes_per_pixel
= 4;
2374 p
->pri_horiz_pixels
=
2375 intel_crtc
->config
.requested_mode
.hdisplay
;
2376 p
->cur_horiz_pixels
= 64;
2379 list_for_each_entry(plane
, &dev
->mode_config
.plane_list
, head
) {
2380 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
2381 struct hsw_pipe_wm_parameters
*p
;
2383 pipe
= intel_plane
->pipe
;
2386 p
->sprite_enabled
= intel_plane
->wm
.enable
;
2387 p
->spr_bytes_per_pixel
= intel_plane
->wm
.bytes_per_pixel
;
2388 p
->spr_horiz_pixels
= intel_plane
->wm
.horiz_pixels
;
2390 if (p
->sprite_enabled
)
2394 if (pipes_active
> 1) {
2395 lp_max_1_2
->pri
= lp_max_5_6
->pri
= sprites_enabled
? 128 : 256;
2396 lp_max_1_2
->spr
= lp_max_5_6
->spr
= 128;
2397 lp_max_1_2
->cur
= lp_max_5_6
->cur
= 64;
2399 lp_max_1_2
->pri
= sprites_enabled
? 384 : 768;
2400 lp_max_5_6
->pri
= sprites_enabled
? 128 : 768;
2401 lp_max_1_2
->spr
= 384;
2402 lp_max_5_6
->spr
= 640;
2403 lp_max_1_2
->cur
= lp_max_5_6
->cur
= 255;
2405 lp_max_1_2
->fbc
= lp_max_5_6
->fbc
= 15;
2408 static void hsw_compute_wm_results(struct drm_device
*dev
,
2409 struct hsw_pipe_wm_parameters
*params
,
2411 struct hsw_wm_maximums
*lp_maximums
,
2412 struct hsw_wm_values
*results
)
2414 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2415 struct drm_crtc
*crtc
;
2416 struct hsw_lp_wm_result lp_results
[4] = {};
2418 int level
, max_level
, wm_lp
;
2420 for (level
= 1; level
<= 4; level
++)
2421 if (!hsw_compute_lp_wm(wm
[level
], lp_maximums
, params
,
2422 &lp_results
[level
- 1]))
2424 max_level
= level
- 1;
2426 /* The spec says it is preferred to disable FBC WMs instead of disabling
2428 results
->enable_fbc_wm
= true;
2429 for (level
= 1; level
<= max_level
; level
++) {
2430 if (!lp_results
[level
- 1].fbc_enable
) {
2431 results
->enable_fbc_wm
= false;
2436 memset(results
, 0, sizeof(*results
));
2437 for (wm_lp
= 1; wm_lp
<= 3; wm_lp
++) {
2438 const struct hsw_lp_wm_result
*r
;
2440 level
= (max_level
== 4 && wm_lp
> 1) ? wm_lp
+ 1 : wm_lp
;
2441 if (level
> max_level
)
2444 r
= &lp_results
[level
- 1];
2445 results
->wm_lp
[wm_lp
- 1] = HSW_WM_LP_VAL(level
* 2,
2449 results
->wm_lp_spr
[wm_lp
- 1] = r
->spr_val
;
2453 results
->wm_pipe
[pipe
] = hsw_compute_wm_pipe(dev_priv
, wm
[0],
2457 for_each_pipe(pipe
) {
2458 crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
2459 results
->wm_linetime
[pipe
] = hsw_compute_linetime_wm(dev
, crtc
);
2463 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2464 * case both are at the same level. Prefer r1 in case they're the same. */
2465 struct hsw_wm_values
*hsw_find_best_result(struct hsw_wm_values
*r1
,
2466 struct hsw_wm_values
*r2
)
2468 int i
, val_r1
= 0, val_r2
= 0;
2470 for (i
= 0; i
< 3; i
++) {
2471 if (r1
->wm_lp
[i
] & WM3_LP_EN
)
2472 val_r1
= r1
->wm_lp
[i
] & WM1_LP_LATENCY_MASK
;
2473 if (r2
->wm_lp
[i
] & WM3_LP_EN
)
2474 val_r2
= r2
->wm_lp
[i
] & WM1_LP_LATENCY_MASK
;
2477 if (val_r1
== val_r2
) {
2478 if (r2
->enable_fbc_wm
&& !r1
->enable_fbc_wm
)
2482 } else if (val_r1
> val_r2
) {
2490 * The spec says we shouldn't write when we don't need, because every write
2491 * causes WMs to be re-evaluated, expending some power.
2493 static void hsw_write_wm_values(struct drm_i915_private
*dev_priv
,
2494 struct hsw_wm_values
*results
,
2495 enum hsw_data_buf_partitioning partitioning
)
2497 struct hsw_wm_values previous
;
2499 enum hsw_data_buf_partitioning prev_partitioning
;
2500 bool prev_enable_fbc_wm
;
2502 previous
.wm_pipe
[0] = I915_READ(WM0_PIPEA_ILK
);
2503 previous
.wm_pipe
[1] = I915_READ(WM0_PIPEB_ILK
);
2504 previous
.wm_pipe
[2] = I915_READ(WM0_PIPEC_IVB
);
2505 previous
.wm_lp
[0] = I915_READ(WM1_LP_ILK
);
2506 previous
.wm_lp
[1] = I915_READ(WM2_LP_ILK
);
2507 previous
.wm_lp
[2] = I915_READ(WM3_LP_ILK
);
2508 previous
.wm_lp_spr
[0] = I915_READ(WM1S_LP_ILK
);
2509 previous
.wm_lp_spr
[1] = I915_READ(WM2S_LP_IVB
);
2510 previous
.wm_lp_spr
[2] = I915_READ(WM3S_LP_IVB
);
2511 previous
.wm_linetime
[0] = I915_READ(PIPE_WM_LINETIME(PIPE_A
));
2512 previous
.wm_linetime
[1] = I915_READ(PIPE_WM_LINETIME(PIPE_B
));
2513 previous
.wm_linetime
[2] = I915_READ(PIPE_WM_LINETIME(PIPE_C
));
2515 prev_partitioning
= (I915_READ(WM_MISC
) & WM_MISC_DATA_PARTITION_5_6
) ?
2516 HSW_DATA_BUF_PART_5_6
: HSW_DATA_BUF_PART_1_2
;
2518 prev_enable_fbc_wm
= !(I915_READ(DISP_ARB_CTL
) & DISP_FBC_WM_DIS
);
2520 if (memcmp(results
->wm_pipe
, previous
.wm_pipe
,
2521 sizeof(results
->wm_pipe
)) == 0 &&
2522 memcmp(results
->wm_lp
, previous
.wm_lp
,
2523 sizeof(results
->wm_lp
)) == 0 &&
2524 memcmp(results
->wm_lp_spr
, previous
.wm_lp_spr
,
2525 sizeof(results
->wm_lp_spr
)) == 0 &&
2526 memcmp(results
->wm_linetime
, previous
.wm_linetime
,
2527 sizeof(results
->wm_linetime
)) == 0 &&
2528 partitioning
== prev_partitioning
&&
2529 results
->enable_fbc_wm
== prev_enable_fbc_wm
)
2532 if (previous
.wm_lp
[2] != 0)
2533 I915_WRITE(WM3_LP_ILK
, 0);
2534 if (previous
.wm_lp
[1] != 0)
2535 I915_WRITE(WM2_LP_ILK
, 0);
2536 if (previous
.wm_lp
[0] != 0)
2537 I915_WRITE(WM1_LP_ILK
, 0);
2539 if (previous
.wm_pipe
[0] != results
->wm_pipe
[0])
2540 I915_WRITE(WM0_PIPEA_ILK
, results
->wm_pipe
[0]);
2541 if (previous
.wm_pipe
[1] != results
->wm_pipe
[1])
2542 I915_WRITE(WM0_PIPEB_ILK
, results
->wm_pipe
[1]);
2543 if (previous
.wm_pipe
[2] != results
->wm_pipe
[2])
2544 I915_WRITE(WM0_PIPEC_IVB
, results
->wm_pipe
[2]);
2546 if (previous
.wm_linetime
[0] != results
->wm_linetime
[0])
2547 I915_WRITE(PIPE_WM_LINETIME(PIPE_A
), results
->wm_linetime
[0]);
2548 if (previous
.wm_linetime
[1] != results
->wm_linetime
[1])
2549 I915_WRITE(PIPE_WM_LINETIME(PIPE_B
), results
->wm_linetime
[1]);
2550 if (previous
.wm_linetime
[2] != results
->wm_linetime
[2])
2551 I915_WRITE(PIPE_WM_LINETIME(PIPE_C
), results
->wm_linetime
[2]);
2553 if (prev_partitioning
!= partitioning
) {
2554 val
= I915_READ(WM_MISC
);
2555 if (partitioning
== HSW_DATA_BUF_PART_1_2
)
2556 val
&= ~WM_MISC_DATA_PARTITION_5_6
;
2558 val
|= WM_MISC_DATA_PARTITION_5_6
;
2559 I915_WRITE(WM_MISC
, val
);
2562 if (prev_enable_fbc_wm
!= results
->enable_fbc_wm
) {
2563 val
= I915_READ(DISP_ARB_CTL
);
2564 if (results
->enable_fbc_wm
)
2565 val
&= ~DISP_FBC_WM_DIS
;
2567 val
|= DISP_FBC_WM_DIS
;
2568 I915_WRITE(DISP_ARB_CTL
, val
);
2571 if (previous
.wm_lp_spr
[0] != results
->wm_lp_spr
[0])
2572 I915_WRITE(WM1S_LP_ILK
, results
->wm_lp_spr
[0]);
2573 if (previous
.wm_lp_spr
[1] != results
->wm_lp_spr
[1])
2574 I915_WRITE(WM2S_LP_IVB
, results
->wm_lp_spr
[1]);
2575 if (previous
.wm_lp_spr
[2] != results
->wm_lp_spr
[2])
2576 I915_WRITE(WM3S_LP_IVB
, results
->wm_lp_spr
[2]);
2578 if (results
->wm_lp
[0] != 0)
2579 I915_WRITE(WM1_LP_ILK
, results
->wm_lp
[0]);
2580 if (results
->wm_lp
[1] != 0)
2581 I915_WRITE(WM2_LP_ILK
, results
->wm_lp
[1]);
2582 if (results
->wm_lp
[2] != 0)
2583 I915_WRITE(WM3_LP_ILK
, results
->wm_lp
[2]);
2586 static void haswell_update_wm(struct drm_device
*dev
)
2588 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2589 struct hsw_wm_maximums lp_max_1_2
, lp_max_5_6
;
2590 struct hsw_pipe_wm_parameters params
[3];
2591 struct hsw_wm_values results_1_2
, results_5_6
, *best_results
;
2593 enum hsw_data_buf_partitioning partitioning
;
2595 hsw_compute_wm_parameters(dev
, params
, wm
, &lp_max_1_2
, &lp_max_5_6
);
2597 hsw_compute_wm_results(dev
, params
, wm
, &lp_max_1_2
, &results_1_2
);
2598 if (lp_max_1_2
.pri
!= lp_max_5_6
.pri
) {
2599 hsw_compute_wm_results(dev
, params
, wm
, &lp_max_5_6
,
2601 best_results
= hsw_find_best_result(&results_1_2
, &results_5_6
);
2603 best_results
= &results_1_2
;
2606 partitioning
= (best_results
== &results_1_2
) ?
2607 HSW_DATA_BUF_PART_1_2
: HSW_DATA_BUF_PART_5_6
;
2609 hsw_write_wm_values(dev_priv
, best_results
, partitioning
);
2612 static void haswell_update_sprite_wm(struct drm_device
*dev
, int pipe
,
2613 uint32_t sprite_width
, int pixel_size
,
2616 struct drm_plane
*plane
;
2618 list_for_each_entry(plane
, &dev
->mode_config
.plane_list
, head
) {
2619 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
2621 if (intel_plane
->pipe
== pipe
) {
2622 intel_plane
->wm
.enable
= enable
;
2623 intel_plane
->wm
.horiz_pixels
= sprite_width
+ 1;
2624 intel_plane
->wm
.bytes_per_pixel
= pixel_size
;
2629 haswell_update_wm(dev
);
2633 sandybridge_compute_sprite_wm(struct drm_device
*dev
, int plane
,
2634 uint32_t sprite_width
, int pixel_size
,
2635 const struct intel_watermark_params
*display
,
2636 int display_latency_ns
, int *sprite_wm
)
2638 struct drm_crtc
*crtc
;
2640 int entries
, tlb_miss
;
2642 crtc
= intel_get_crtc_for_plane(dev
, plane
);
2643 if (!intel_crtc_active(crtc
)) {
2644 *sprite_wm
= display
->guard_size
;
2648 clock
= crtc
->mode
.clock
;
2650 /* Use the small buffer method to calculate the sprite watermark */
2651 entries
= ((clock
* pixel_size
/ 1000) * display_latency_ns
) / 1000;
2652 tlb_miss
= display
->fifo_size
*display
->cacheline_size
-
2655 entries
+= tlb_miss
;
2656 entries
= DIV_ROUND_UP(entries
, display
->cacheline_size
);
2657 *sprite_wm
= entries
+ display
->guard_size
;
2658 if (*sprite_wm
> (int)display
->max_wm
)
2659 *sprite_wm
= display
->max_wm
;
2665 sandybridge_compute_sprite_srwm(struct drm_device
*dev
, int plane
,
2666 uint32_t sprite_width
, int pixel_size
,
2667 const struct intel_watermark_params
*display
,
2668 int latency_ns
, int *sprite_wm
)
2670 struct drm_crtc
*crtc
;
2671 unsigned long line_time_us
;
2673 int line_count
, line_size
;
2682 crtc
= intel_get_crtc_for_plane(dev
, plane
);
2683 clock
= crtc
->mode
.clock
;
2689 line_time_us
= (sprite_width
* 1000) / clock
;
2690 if (!line_time_us
) {
2695 line_count
= (latency_ns
/ line_time_us
+ 1000) / 1000;
2696 line_size
= sprite_width
* pixel_size
;
2698 /* Use the minimum of the small and large buffer method for primary */
2699 small
= ((clock
* pixel_size
/ 1000) * latency_ns
) / 1000;
2700 large
= line_count
* line_size
;
2702 entries
= DIV_ROUND_UP(min(small
, large
), display
->cacheline_size
);
2703 *sprite_wm
= entries
+ display
->guard_size
;
2705 return *sprite_wm
> 0x3ff ? false : true;
2708 static void sandybridge_update_sprite_wm(struct drm_device
*dev
, int pipe
,
2709 uint32_t sprite_width
, int pixel_size
,
2712 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2713 int latency
= SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
2723 reg
= WM0_PIPEA_ILK
;
2726 reg
= WM0_PIPEB_ILK
;
2729 reg
= WM0_PIPEC_IVB
;
2732 return; /* bad pipe */
2735 ret
= sandybridge_compute_sprite_wm(dev
, pipe
, sprite_width
, pixel_size
,
2736 &sandybridge_display_wm_info
,
2737 latency
, &sprite_wm
);
2739 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %c\n",
2744 val
= I915_READ(reg
);
2745 val
&= ~WM0_PIPE_SPRITE_MASK
;
2746 I915_WRITE(reg
, val
| (sprite_wm
<< WM0_PIPE_SPRITE_SHIFT
));
2747 DRM_DEBUG_KMS("sprite watermarks For pipe %c - %d\n", pipe_name(pipe
), sprite_wm
);
2750 ret
= sandybridge_compute_sprite_srwm(dev
, pipe
, sprite_width
,
2752 &sandybridge_display_srwm_info
,
2753 SNB_READ_WM1_LATENCY() * 500,
2756 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %c\n",
2760 I915_WRITE(WM1S_LP_ILK
, sprite_wm
);
2762 /* Only IVB has two more LP watermarks for sprite */
2763 if (!IS_IVYBRIDGE(dev
))
2766 ret
= sandybridge_compute_sprite_srwm(dev
, pipe
, sprite_width
,
2768 &sandybridge_display_srwm_info
,
2769 SNB_READ_WM2_LATENCY() * 500,
2772 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %c\n",
2776 I915_WRITE(WM2S_LP_IVB
, sprite_wm
);
2778 ret
= sandybridge_compute_sprite_srwm(dev
, pipe
, sprite_width
,
2780 &sandybridge_display_srwm_info
,
2781 SNB_READ_WM3_LATENCY() * 500,
2784 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %c\n",
2788 I915_WRITE(WM3S_LP_IVB
, sprite_wm
);
2792 * intel_update_watermarks - update FIFO watermark values based on current modes
2794 * Calculate watermark values for the various WM regs based on current mode
2795 * and plane configuration.
2797 * There are several cases to deal with here:
2798 * - normal (i.e. non-self-refresh)
2799 * - self-refresh (SR) mode
2800 * - lines are large relative to FIFO size (buffer can hold up to 2)
2801 * - lines are small relative to FIFO size (buffer can hold more than 2
2802 * lines), so need to account for TLB latency
2804 * The normal calculation is:
2805 * watermark = dotclock * bytes per pixel * latency
2806 * where latency is platform & configuration dependent (we assume pessimal
2809 * The SR calculation is:
2810 * watermark = (trunc(latency/line time)+1) * surface width *
2813 * line time = htotal / dotclock
2814 * surface width = hdisplay for normal plane and 64 for cursor
2815 * and latency is assumed to be high, as above.
2817 * The final value programmed to the register should always be rounded up,
2818 * and include an extra 2 entries to account for clock crossings.
2820 * We don't use the sprite, so we can ignore that. And on Crestline we have
2821 * to set the non-SR watermarks to 8.
2823 void intel_update_watermarks(struct drm_device
*dev
)
2825 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2827 if (dev_priv
->display
.update_wm
)
2828 dev_priv
->display
.update_wm(dev
);
2831 void intel_update_sprite_watermarks(struct drm_device
*dev
, int pipe
,
2832 uint32_t sprite_width
, int pixel_size
,
2835 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2837 if (dev_priv
->display
.update_sprite_wm
)
2838 dev_priv
->display
.update_sprite_wm(dev
, pipe
, sprite_width
,
2839 pixel_size
, enable
);
2842 static struct drm_i915_gem_object
*
2843 intel_alloc_context_page(struct drm_device
*dev
)
2845 struct drm_i915_gem_object
*ctx
;
2848 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
2850 ctx
= i915_gem_alloc_object(dev
, 4096);
2852 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
2856 ret
= i915_gem_object_pin(ctx
, 4096, true, false);
2858 DRM_ERROR("failed to pin power context: %d\n", ret
);
2862 ret
= i915_gem_object_set_to_gtt_domain(ctx
, 1);
2864 DRM_ERROR("failed to set-domain on power context: %d\n", ret
);
2871 i915_gem_object_unpin(ctx
);
2873 drm_gem_object_unreference(&ctx
->base
);
2878 * Lock protecting IPS related data structures
2880 DEFINE_SPINLOCK(mchdev_lock
);
2882 /* Global for IPS driver to get at the current i915 device. Protected by
2884 static struct drm_i915_private
*i915_mch_dev
;
2886 bool ironlake_set_drps(struct drm_device
*dev
, u8 val
)
2888 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2891 assert_spin_locked(&mchdev_lock
);
2893 rgvswctl
= I915_READ16(MEMSWCTL
);
2894 if (rgvswctl
& MEMCTL_CMD_STS
) {
2895 DRM_DEBUG("gpu busy, RCS change rejected\n");
2896 return false; /* still busy with another command */
2899 rgvswctl
= (MEMCTL_CMD_CHFREQ
<< MEMCTL_CMD_SHIFT
) |
2900 (val
<< MEMCTL_FREQ_SHIFT
) | MEMCTL_SFCAVM
;
2901 I915_WRITE16(MEMSWCTL
, rgvswctl
);
2902 POSTING_READ16(MEMSWCTL
);
2904 rgvswctl
|= MEMCTL_CMD_STS
;
2905 I915_WRITE16(MEMSWCTL
, rgvswctl
);
2910 static void ironlake_enable_drps(struct drm_device
*dev
)
2912 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2913 u32 rgvmodectl
= I915_READ(MEMMODECTL
);
2914 u8 fmax
, fmin
, fstart
, vstart
;
2916 spin_lock_irq(&mchdev_lock
);
2918 /* Enable temp reporting */
2919 I915_WRITE16(PMMISC
, I915_READ(PMMISC
) | MCPPCE_EN
);
2920 I915_WRITE16(TSC1
, I915_READ(TSC1
) | TSE
);
2922 /* 100ms RC evaluation intervals */
2923 I915_WRITE(RCUPEI
, 100000);
2924 I915_WRITE(RCDNEI
, 100000);
2926 /* Set max/min thresholds to 90ms and 80ms respectively */
2927 I915_WRITE(RCBMAXAVG
, 90000);
2928 I915_WRITE(RCBMINAVG
, 80000);
2930 I915_WRITE(MEMIHYST
, 1);
2932 /* Set up min, max, and cur for interrupt handling */
2933 fmax
= (rgvmodectl
& MEMMODE_FMAX_MASK
) >> MEMMODE_FMAX_SHIFT
;
2934 fmin
= (rgvmodectl
& MEMMODE_FMIN_MASK
);
2935 fstart
= (rgvmodectl
& MEMMODE_FSTART_MASK
) >>
2936 MEMMODE_FSTART_SHIFT
;
2938 vstart
= (I915_READ(PXVFREQ_BASE
+ (fstart
* 4)) & PXVFREQ_PX_MASK
) >>
2941 dev_priv
->ips
.fmax
= fmax
; /* IPS callback will increase this */
2942 dev_priv
->ips
.fstart
= fstart
;
2944 dev_priv
->ips
.max_delay
= fstart
;
2945 dev_priv
->ips
.min_delay
= fmin
;
2946 dev_priv
->ips
.cur_delay
= fstart
;
2948 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
2949 fmax
, fmin
, fstart
);
2951 I915_WRITE(MEMINTREN
, MEMINT_CX_SUPR_EN
| MEMINT_EVAL_CHG_EN
);
2954 * Interrupts will be enabled in ironlake_irq_postinstall
2957 I915_WRITE(VIDSTART
, vstart
);
2958 POSTING_READ(VIDSTART
);
2960 rgvmodectl
|= MEMMODE_SWMODE_EN
;
2961 I915_WRITE(MEMMODECTL
, rgvmodectl
);
2963 if (wait_for_atomic((I915_READ(MEMSWCTL
) & MEMCTL_CMD_STS
) == 0, 10))
2964 DRM_ERROR("stuck trying to change perf mode\n");
2967 ironlake_set_drps(dev
, fstart
);
2969 dev_priv
->ips
.last_count1
= I915_READ(0x112e4) + I915_READ(0x112e8) +
2971 dev_priv
->ips
.last_time1
= jiffies_to_msecs(jiffies
);
2972 dev_priv
->ips
.last_count2
= I915_READ(0x112f4);
2973 getrawmonotonic(&dev_priv
->ips
.last_time2
);
2975 spin_unlock_irq(&mchdev_lock
);
2978 static void ironlake_disable_drps(struct drm_device
*dev
)
2980 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2983 spin_lock_irq(&mchdev_lock
);
2985 rgvswctl
= I915_READ16(MEMSWCTL
);
2987 /* Ack interrupts, disable EFC interrupt */
2988 I915_WRITE(MEMINTREN
, I915_READ(MEMINTREN
) & ~MEMINT_EVAL_CHG_EN
);
2989 I915_WRITE(MEMINTRSTS
, MEMINT_EVAL_CHG
);
2990 I915_WRITE(DEIER
, I915_READ(DEIER
) & ~DE_PCU_EVENT
);
2991 I915_WRITE(DEIIR
, DE_PCU_EVENT
);
2992 I915_WRITE(DEIMR
, I915_READ(DEIMR
) | DE_PCU_EVENT
);
2994 /* Go back to the starting frequency */
2995 ironlake_set_drps(dev
, dev_priv
->ips
.fstart
);
2997 rgvswctl
|= MEMCTL_CMD_STS
;
2998 I915_WRITE(MEMSWCTL
, rgvswctl
);
3001 spin_unlock_irq(&mchdev_lock
);
3004 /* There's a funny hw issue where the hw returns all 0 when reading from
3005 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3006 * ourselves, instead of doing a rmw cycle (which might result in us clearing
3007 * all limits and the gpu stuck at whatever frequency it is at atm).
3009 static u32
gen6_rps_limits(struct drm_i915_private
*dev_priv
, u8
*val
)
3015 if (*val
>= dev_priv
->rps
.max_delay
)
3016 *val
= dev_priv
->rps
.max_delay
;
3017 limits
|= dev_priv
->rps
.max_delay
<< 24;
3019 /* Only set the down limit when we've reached the lowest level to avoid
3020 * getting more interrupts, otherwise leave this clear. This prevents a
3021 * race in the hw when coming out of rc6: There's a tiny window where
3022 * the hw runs at the minimal clock before selecting the desired
3023 * frequency, if the down threshold expires in that window we will not
3024 * receive a down interrupt. */
3025 if (*val
<= dev_priv
->rps
.min_delay
) {
3026 *val
= dev_priv
->rps
.min_delay
;
3027 limits
|= dev_priv
->rps
.min_delay
<< 16;
3033 void gen6_set_rps(struct drm_device
*dev
, u8 val
)
3035 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3036 u32 limits
= gen6_rps_limits(dev_priv
, &val
);
3038 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
3039 WARN_ON(val
> dev_priv
->rps
.max_delay
);
3040 WARN_ON(val
< dev_priv
->rps
.min_delay
);
3042 if (val
== dev_priv
->rps
.cur_delay
)
3045 if (IS_HASWELL(dev
))
3046 I915_WRITE(GEN6_RPNSWREQ
,
3047 HSW_FREQUENCY(val
));
3049 I915_WRITE(GEN6_RPNSWREQ
,
3050 GEN6_FREQUENCY(val
) |
3052 GEN6_AGGRESSIVE_TURBO
);
3054 /* Make sure we continue to get interrupts
3055 * until we hit the minimum or maximum frequencies.
3057 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS
, limits
);
3059 POSTING_READ(GEN6_RPNSWREQ
);
3061 dev_priv
->rps
.cur_delay
= val
;
3063 trace_intel_gpu_freq_change(val
* 50);
3066 void valleyview_set_rps(struct drm_device
*dev
, u8 val
)
3068 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3069 unsigned long timeout
= jiffies
+ msecs_to_jiffies(10);
3070 u32 limits
= gen6_rps_limits(dev_priv
, &val
);
3073 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
3074 WARN_ON(val
> dev_priv
->rps
.max_delay
);
3075 WARN_ON(val
< dev_priv
->rps
.min_delay
);
3077 DRM_DEBUG_DRIVER("gpu freq request from %d to %d\n",
3078 vlv_gpu_freq(dev_priv
->mem_freq
,
3079 dev_priv
->rps
.cur_delay
),
3080 vlv_gpu_freq(dev_priv
->mem_freq
, val
));
3082 if (val
== dev_priv
->rps
.cur_delay
)
3085 vlv_punit_write(dev_priv
, PUNIT_REG_GPU_FREQ_REQ
, val
);
3088 pval
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
3089 if (time_after(jiffies
, timeout
)) {
3090 DRM_DEBUG_DRIVER("timed out waiting for Punit\n");
3096 pval
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
3097 if ((pval
>> 8) != val
)
3098 DRM_DEBUG_DRIVER("punit overrode freq: %d requested, but got %d\n",
3101 /* Make sure we continue to get interrupts
3102 * until we hit the minimum or maximum frequencies.
3104 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS
, limits
);
3106 dev_priv
->rps
.cur_delay
= pval
>> 8;
3108 trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv
->mem_freq
, val
));
3112 static void gen6_disable_rps(struct drm_device
*dev
)
3114 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3116 I915_WRITE(GEN6_RC_CONTROL
, 0);
3117 I915_WRITE(GEN6_RPNSWREQ
, 1 << 31);
3118 I915_WRITE(GEN6_PMINTRMSK
, 0xffffffff);
3119 I915_WRITE(GEN6_PMIER
, I915_READ(GEN6_PMIER
) & ~GEN6_PM_RPS_EVENTS
);
3120 /* Complete PM interrupt masking here doesn't race with the rps work
3121 * item again unmasking PM interrupts because that is using a different
3122 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3123 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3125 spin_lock_irq(&dev_priv
->rps
.lock
);
3126 dev_priv
->rps
.pm_iir
= 0;
3127 spin_unlock_irq(&dev_priv
->rps
.lock
);
3129 I915_WRITE(GEN6_PMIIR
, GEN6_PM_RPS_EVENTS
);
3132 static void valleyview_disable_rps(struct drm_device
*dev
)
3134 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3136 I915_WRITE(GEN6_RC_CONTROL
, 0);
3137 I915_WRITE(GEN6_PMINTRMSK
, 0xffffffff);
3138 I915_WRITE(GEN6_PMIER
, 0);
3139 /* Complete PM interrupt masking here doesn't race with the rps work
3140 * item again unmasking PM interrupts because that is using a different
3141 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3142 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3144 spin_lock_irq(&dev_priv
->rps
.lock
);
3145 dev_priv
->rps
.pm_iir
= 0;
3146 spin_unlock_irq(&dev_priv
->rps
.lock
);
3148 I915_WRITE(GEN6_PMIIR
, I915_READ(GEN6_PMIIR
));
3150 if (dev_priv
->vlv_pctx
) {
3151 drm_gem_object_unreference(&dev_priv
->vlv_pctx
->base
);
3152 dev_priv
->vlv_pctx
= NULL
;
3156 int intel_enable_rc6(const struct drm_device
*dev
)
3158 /* Respect the kernel parameter if it is set */
3159 if (i915_enable_rc6
>= 0)
3160 return i915_enable_rc6
;
3162 /* Disable RC6 on Ironlake */
3163 if (INTEL_INFO(dev
)->gen
== 5)
3166 if (IS_HASWELL(dev
)) {
3167 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
3168 return INTEL_RC6_ENABLE
;
3171 /* snb/ivb have more than one rc6 state. */
3172 if (INTEL_INFO(dev
)->gen
== 6) {
3173 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
3174 return INTEL_RC6_ENABLE
;
3177 DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n");
3178 return (INTEL_RC6_ENABLE
| INTEL_RC6p_ENABLE
);
3181 static void gen6_enable_rps(struct drm_device
*dev
)
3183 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3184 struct intel_ring_buffer
*ring
;
3187 u32 rc6vids
, pcu_mbox
, rc6_mask
= 0;
3192 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
3194 /* Here begins a magic sequence of register writes to enable
3195 * auto-downclocking.
3197 * Perhaps there might be some value in exposing these to
3200 I915_WRITE(GEN6_RC_STATE
, 0);
3202 /* Clear the DBG now so we don't confuse earlier errors */
3203 if ((gtfifodbg
= I915_READ(GTFIFODBG
))) {
3204 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg
);
3205 I915_WRITE(GTFIFODBG
, gtfifodbg
);
3208 gen6_gt_force_wake_get(dev_priv
);
3210 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
3211 gt_perf_status
= I915_READ(GEN6_GT_PERF_STATUS
);
3213 /* In units of 50MHz */
3214 dev_priv
->rps
.hw_max
= dev_priv
->rps
.max_delay
= rp_state_cap
& 0xff;
3215 dev_priv
->rps
.min_delay
= (rp_state_cap
& 0xff0000) >> 16;
3216 dev_priv
->rps
.cur_delay
= 0;
3218 /* disable the counters and set deterministic thresholds */
3219 I915_WRITE(GEN6_RC_CONTROL
, 0);
3221 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT
, 1000 << 16);
3222 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 40 << 16 | 30);
3223 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT
, 30);
3224 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000);
3225 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25);
3227 for_each_ring(ring
, dev_priv
, i
)
3228 I915_WRITE(RING_MAX_IDLE(ring
->mmio_base
), 10);
3230 I915_WRITE(GEN6_RC_SLEEP
, 0);
3231 I915_WRITE(GEN6_RC1e_THRESHOLD
, 1000);
3232 I915_WRITE(GEN6_RC6_THRESHOLD
, 50000);
3233 I915_WRITE(GEN6_RC6p_THRESHOLD
, 150000);
3234 I915_WRITE(GEN6_RC6pp_THRESHOLD
, 64000); /* unused */
3236 /* Check if we are enabling RC6 */
3237 rc6_mode
= intel_enable_rc6(dev_priv
->dev
);
3238 if (rc6_mode
& INTEL_RC6_ENABLE
)
3239 rc6_mask
|= GEN6_RC_CTL_RC6_ENABLE
;
3241 /* We don't use those on Haswell */
3242 if (!IS_HASWELL(dev
)) {
3243 if (rc6_mode
& INTEL_RC6p_ENABLE
)
3244 rc6_mask
|= GEN6_RC_CTL_RC6p_ENABLE
;
3246 if (rc6_mode
& INTEL_RC6pp_ENABLE
)
3247 rc6_mask
|= GEN6_RC_CTL_RC6pp_ENABLE
;
3250 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
3251 (rc6_mask
& GEN6_RC_CTL_RC6_ENABLE
) ? "on" : "off",
3252 (rc6_mask
& GEN6_RC_CTL_RC6p_ENABLE
) ? "on" : "off",
3253 (rc6_mask
& GEN6_RC_CTL_RC6pp_ENABLE
) ? "on" : "off");
3255 I915_WRITE(GEN6_RC_CONTROL
,
3257 GEN6_RC_CTL_EI_MODE(1) |
3258 GEN6_RC_CTL_HW_ENABLE
);
3260 if (IS_HASWELL(dev
)) {
3261 I915_WRITE(GEN6_RPNSWREQ
,
3263 I915_WRITE(GEN6_RC_VIDEO_FREQ
,
3266 I915_WRITE(GEN6_RPNSWREQ
,
3267 GEN6_FREQUENCY(10) |
3269 GEN6_AGGRESSIVE_TURBO
);
3270 I915_WRITE(GEN6_RC_VIDEO_FREQ
,
3271 GEN6_FREQUENCY(12));
3274 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 1000000);
3275 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS
,
3276 dev_priv
->rps
.max_delay
<< 24 |
3277 dev_priv
->rps
.min_delay
<< 16);
3279 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 59400);
3280 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 245000);
3281 I915_WRITE(GEN6_RP_UP_EI
, 66000);
3282 I915_WRITE(GEN6_RP_DOWN_EI
, 350000);
3284 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
3285 I915_WRITE(GEN6_RP_CONTROL
,
3286 GEN6_RP_MEDIA_TURBO
|
3287 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
3288 GEN6_RP_MEDIA_IS_GFX
|
3290 GEN6_RP_UP_BUSY_AVG
|
3291 (IS_HASWELL(dev
) ? GEN7_RP_DOWN_IDLE_AVG
: GEN6_RP_DOWN_IDLE_CONT
));
3293 ret
= sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_MIN_FREQ_TABLE
, 0);
3296 ret
= sandybridge_pcode_read(dev_priv
, GEN6_READ_OC_PARAMS
, &pcu_mbox
);
3297 if (!ret
&& (pcu_mbox
& (1<<31))) { /* OC supported */
3298 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
3299 (dev_priv
->rps
.max_delay
& 0xff) * 50,
3300 (pcu_mbox
& 0xff) * 50);
3301 dev_priv
->rps
.hw_max
= pcu_mbox
& 0xff;
3304 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
3307 gen6_set_rps(dev_priv
->dev
, (gt_perf_status
& 0xff00) >> 8);
3309 /* requires MSI enabled */
3310 I915_WRITE(GEN6_PMIER
, I915_READ(GEN6_PMIER
) | GEN6_PM_RPS_EVENTS
);
3311 spin_lock_irq(&dev_priv
->rps
.lock
);
3312 /* FIXME: Our interrupt enabling sequence is bonghits.
3313 * dev_priv->rps.pm_iir really should be 0 here. */
3314 dev_priv
->rps
.pm_iir
= 0;
3315 I915_WRITE(GEN6_PMIMR
, I915_READ(GEN6_PMIMR
) & ~GEN6_PM_RPS_EVENTS
);
3316 I915_WRITE(GEN6_PMIIR
, GEN6_PM_RPS_EVENTS
);
3317 spin_unlock_irq(&dev_priv
->rps
.lock
);
3318 /* unmask all PM interrupts */
3319 I915_WRITE(GEN6_PMINTRMSK
, 0);
3322 ret
= sandybridge_pcode_read(dev_priv
, GEN6_PCODE_READ_RC6VIDS
, &rc6vids
);
3323 if (IS_GEN6(dev
) && ret
) {
3324 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
3325 } else if (IS_GEN6(dev
) && (GEN6_DECODE_RC6_VID(rc6vids
& 0xff) < 450)) {
3326 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
3327 GEN6_DECODE_RC6_VID(rc6vids
& 0xff), 450);
3328 rc6vids
&= 0xffff00;
3329 rc6vids
|= GEN6_ENCODE_RC6_VID(450);
3330 ret
= sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_RC6VIDS
, rc6vids
);
3332 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
3335 gen6_gt_force_wake_put(dev_priv
);
3338 static void gen6_update_ring_freq(struct drm_device
*dev
)
3340 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3342 unsigned int gpu_freq
;
3343 unsigned int max_ia_freq
, min_ring_freq
;
3344 int scaling_factor
= 180;
3346 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
3348 max_ia_freq
= cpufreq_quick_get_max(0);
3350 * Default to measured freq if none found, PCU will ensure we don't go
3354 max_ia_freq
= tsc_khz
;
3356 /* Convert from kHz to MHz */
3357 max_ia_freq
/= 1000;
3359 min_ring_freq
= I915_READ(MCHBAR_MIRROR_BASE_SNB
+ DCLK
);
3360 /* convert DDR frequency from units of 133.3MHz to bandwidth */
3361 min_ring_freq
= (2 * 4 * min_ring_freq
+ 2) / 3;
3364 * For each potential GPU frequency, load a ring frequency we'd like
3365 * to use for memory access. We do this by specifying the IA frequency
3366 * the PCU should use as a reference to determine the ring frequency.
3368 for (gpu_freq
= dev_priv
->rps
.max_delay
; gpu_freq
>= dev_priv
->rps
.min_delay
;
3370 int diff
= dev_priv
->rps
.max_delay
- gpu_freq
;
3371 unsigned int ia_freq
= 0, ring_freq
= 0;
3373 if (IS_HASWELL(dev
)) {
3374 ring_freq
= (gpu_freq
* 5 + 3) / 4;
3375 ring_freq
= max(min_ring_freq
, ring_freq
);
3376 /* leave ia_freq as the default, chosen by cpufreq */
3378 /* On older processors, there is no separate ring
3379 * clock domain, so in order to boost the bandwidth
3380 * of the ring, we need to upclock the CPU (ia_freq).
3382 * For GPU frequencies less than 750MHz,
3383 * just use the lowest ring freq.
3385 if (gpu_freq
< min_freq
)
3388 ia_freq
= max_ia_freq
- ((diff
* scaling_factor
) / 2);
3389 ia_freq
= DIV_ROUND_CLOSEST(ia_freq
, 100);
3392 sandybridge_pcode_write(dev_priv
,
3393 GEN6_PCODE_WRITE_MIN_FREQ_TABLE
,
3394 ia_freq
<< GEN6_PCODE_FREQ_IA_RATIO_SHIFT
|
3395 ring_freq
<< GEN6_PCODE_FREQ_RING_RATIO_SHIFT
|
3400 int valleyview_rps_max_freq(struct drm_i915_private
*dev_priv
)
3404 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FREQ_FUSE
);
3406 rp0
= (val
& FB_GFX_MAX_FREQ_FUSE_MASK
) >> FB_GFX_MAX_FREQ_FUSE_SHIFT
;
3408 rp0
= min_t(u32
, rp0
, 0xea);
3413 static int valleyview_rps_rpe_freq(struct drm_i915_private
*dev_priv
)
3417 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FMAX_FUSE_LO
);
3418 rpe
= (val
& FB_FMAX_VMIN_FREQ_LO_MASK
) >> FB_FMAX_VMIN_FREQ_LO_SHIFT
;
3419 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FMAX_FUSE_HI
);
3420 rpe
|= (val
& FB_FMAX_VMIN_FREQ_HI_MASK
) << 5;
3425 int valleyview_rps_min_freq(struct drm_i915_private
*dev_priv
)
3427 return vlv_punit_read(dev_priv
, PUNIT_REG_GPU_LFM
) & 0xff;
3430 static void vlv_rps_timer_work(struct work_struct
*work
)
3432 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
3436 * Timer fired, we must be idle. Drop to min voltage state.
3437 * Note: we use RPe here since it should match the
3438 * Vmin we were shooting for. That should give us better
3439 * perf when we come back out of RC6 than if we used the
3440 * min freq available.
3442 mutex_lock(&dev_priv
->rps
.hw_lock
);
3443 valleyview_set_rps(dev_priv
->dev
, dev_priv
->rps
.rpe_delay
);
3444 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3447 static void valleyview_setup_pctx(struct drm_device
*dev
)
3449 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3450 struct drm_i915_gem_object
*pctx
;
3451 unsigned long pctx_paddr
;
3453 int pctx_size
= 24*1024;
3455 pcbr
= I915_READ(VLV_PCBR
);
3457 /* BIOS set it up already, grab the pre-alloc'd space */
3460 pcbr_offset
= (pcbr
& (~4095)) - dev_priv
->mm
.stolen_base
;
3461 pctx
= i915_gem_object_create_stolen_for_preallocated(dev_priv
->dev
,
3469 * From the Gunit register HAS:
3470 * The Gfx driver is expected to program this register and ensure
3471 * proper allocation within Gfx stolen memory. For example, this
3472 * register should be programmed such than the PCBR range does not
3473 * overlap with other ranges, such as the frame buffer, protected
3474 * memory, or any other relevant ranges.
3476 pctx
= i915_gem_object_create_stolen(dev
, pctx_size
);
3478 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
3482 pctx_paddr
= dev_priv
->mm
.stolen_base
+ pctx
->stolen
->start
;
3483 I915_WRITE(VLV_PCBR
, pctx_paddr
);
3486 dev_priv
->vlv_pctx
= pctx
;
3489 static void valleyview_enable_rps(struct drm_device
*dev
)
3491 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3492 struct intel_ring_buffer
*ring
;
3493 u32 gtfifodbg
, val
, rpe
;
3496 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
3498 if ((gtfifodbg
= I915_READ(GTFIFODBG
))) {
3499 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg
);
3500 I915_WRITE(GTFIFODBG
, gtfifodbg
);
3503 valleyview_setup_pctx(dev
);
3505 gen6_gt_force_wake_get(dev_priv
);
3507 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 59400);
3508 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 245000);
3509 I915_WRITE(GEN6_RP_UP_EI
, 66000);
3510 I915_WRITE(GEN6_RP_DOWN_EI
, 350000);
3512 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
3514 I915_WRITE(GEN6_RP_CONTROL
,
3515 GEN6_RP_MEDIA_TURBO
|
3516 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
3517 GEN6_RP_MEDIA_IS_GFX
|
3519 GEN6_RP_UP_BUSY_AVG
|
3520 GEN6_RP_DOWN_IDLE_CONT
);
3522 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 0x00280000);
3523 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000);
3524 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25);
3526 for_each_ring(ring
, dev_priv
, i
)
3527 I915_WRITE(RING_MAX_IDLE(ring
->mmio_base
), 10);
3529 I915_WRITE(GEN6_RC6_THRESHOLD
, 0xc350);
3531 /* allows RC6 residency counter to work */
3532 I915_WRITE(0x138104, _MASKED_BIT_ENABLE(0x3));
3533 I915_WRITE(GEN6_RC_CONTROL
,
3534 GEN7_RC_CTL_TO_MODE
);
3536 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
3537 switch ((val
>> 6) & 3) {
3540 dev_priv
->mem_freq
= 800;
3543 dev_priv
->mem_freq
= 1066;
3546 dev_priv
->mem_freq
= 1333;
3549 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv
->mem_freq
);
3551 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val
& 0x10 ? "yes" : "no");
3552 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val
);
3554 DRM_DEBUG_DRIVER("current GPU freq: %d\n",
3555 vlv_gpu_freq(dev_priv
->mem_freq
, (val
>> 8) & 0xff));
3556 dev_priv
->rps
.cur_delay
= (val
>> 8) & 0xff;
3558 dev_priv
->rps
.max_delay
= valleyview_rps_max_freq(dev_priv
);
3559 dev_priv
->rps
.hw_max
= dev_priv
->rps
.max_delay
;
3560 DRM_DEBUG_DRIVER("max GPU freq: %d\n", vlv_gpu_freq(dev_priv
->mem_freq
,
3561 dev_priv
->rps
.max_delay
));
3563 rpe
= valleyview_rps_rpe_freq(dev_priv
);
3564 DRM_DEBUG_DRIVER("RPe GPU freq: %d\n",
3565 vlv_gpu_freq(dev_priv
->mem_freq
, rpe
));
3566 dev_priv
->rps
.rpe_delay
= rpe
;
3568 val
= valleyview_rps_min_freq(dev_priv
);
3569 DRM_DEBUG_DRIVER("min GPU freq: %d\n", vlv_gpu_freq(dev_priv
->mem_freq
,
3571 dev_priv
->rps
.min_delay
= val
;
3573 DRM_DEBUG_DRIVER("setting GPU freq to %d\n",
3574 vlv_gpu_freq(dev_priv
->mem_freq
, rpe
));
3576 INIT_DELAYED_WORK(&dev_priv
->rps
.vlv_work
, vlv_rps_timer_work
);
3578 valleyview_set_rps(dev_priv
->dev
, rpe
);
3580 /* requires MSI enabled */
3581 I915_WRITE(GEN6_PMIER
, GEN6_PM_RPS_EVENTS
);
3582 spin_lock_irq(&dev_priv
->rps
.lock
);
3583 WARN_ON(dev_priv
->rps
.pm_iir
!= 0);
3584 I915_WRITE(GEN6_PMIMR
, 0);
3585 spin_unlock_irq(&dev_priv
->rps
.lock
);
3586 /* enable all PM interrupts */
3587 I915_WRITE(GEN6_PMINTRMSK
, 0);
3589 gen6_gt_force_wake_put(dev_priv
);
3592 void ironlake_teardown_rc6(struct drm_device
*dev
)
3594 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3596 if (dev_priv
->ips
.renderctx
) {
3597 i915_gem_object_unpin(dev_priv
->ips
.renderctx
);
3598 drm_gem_object_unreference(&dev_priv
->ips
.renderctx
->base
);
3599 dev_priv
->ips
.renderctx
= NULL
;
3602 if (dev_priv
->ips
.pwrctx
) {
3603 i915_gem_object_unpin(dev_priv
->ips
.pwrctx
);
3604 drm_gem_object_unreference(&dev_priv
->ips
.pwrctx
->base
);
3605 dev_priv
->ips
.pwrctx
= NULL
;
3609 static void ironlake_disable_rc6(struct drm_device
*dev
)
3611 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3613 if (I915_READ(PWRCTXA
)) {
3614 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
3615 I915_WRITE(RSTDBYCTL
, I915_READ(RSTDBYCTL
) | RCX_SW_EXIT
);
3616 wait_for(((I915_READ(RSTDBYCTL
) & RSX_STATUS_MASK
) == RSX_STATUS_ON
),
3619 I915_WRITE(PWRCTXA
, 0);
3620 POSTING_READ(PWRCTXA
);
3622 I915_WRITE(RSTDBYCTL
, I915_READ(RSTDBYCTL
) & ~RCX_SW_EXIT
);
3623 POSTING_READ(RSTDBYCTL
);
3627 static int ironlake_setup_rc6(struct drm_device
*dev
)
3629 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3631 if (dev_priv
->ips
.renderctx
== NULL
)
3632 dev_priv
->ips
.renderctx
= intel_alloc_context_page(dev
);
3633 if (!dev_priv
->ips
.renderctx
)
3636 if (dev_priv
->ips
.pwrctx
== NULL
)
3637 dev_priv
->ips
.pwrctx
= intel_alloc_context_page(dev
);
3638 if (!dev_priv
->ips
.pwrctx
) {
3639 ironlake_teardown_rc6(dev
);
3646 static void ironlake_enable_rc6(struct drm_device
*dev
)
3648 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3649 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
3650 bool was_interruptible
;
3653 /* rc6 disabled by default due to repeated reports of hanging during
3656 if (!intel_enable_rc6(dev
))
3659 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
3661 ret
= ironlake_setup_rc6(dev
);
3665 was_interruptible
= dev_priv
->mm
.interruptible
;
3666 dev_priv
->mm
.interruptible
= false;
3669 * GPU can automatically power down the render unit if given a page
3672 ret
= intel_ring_begin(ring
, 6);
3674 ironlake_teardown_rc6(dev
);
3675 dev_priv
->mm
.interruptible
= was_interruptible
;
3679 intel_ring_emit(ring
, MI_SUSPEND_FLUSH
| MI_SUSPEND_FLUSH_EN
);
3680 intel_ring_emit(ring
, MI_SET_CONTEXT
);
3681 intel_ring_emit(ring
, dev_priv
->ips
.renderctx
->gtt_offset
|
3683 MI_SAVE_EXT_STATE_EN
|
3684 MI_RESTORE_EXT_STATE_EN
|
3685 MI_RESTORE_INHIBIT
);
3686 intel_ring_emit(ring
, MI_SUSPEND_FLUSH
);
3687 intel_ring_emit(ring
, MI_NOOP
);
3688 intel_ring_emit(ring
, MI_FLUSH
);
3689 intel_ring_advance(ring
);
3692 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
3693 * does an implicit flush, combined with MI_FLUSH above, it should be
3694 * safe to assume that renderctx is valid
3696 ret
= intel_ring_idle(ring
);
3697 dev_priv
->mm
.interruptible
= was_interruptible
;
3699 DRM_ERROR("failed to enable ironlake power savings\n");
3700 ironlake_teardown_rc6(dev
);
3704 I915_WRITE(PWRCTXA
, dev_priv
->ips
.pwrctx
->gtt_offset
| PWRCTX_EN
);
3705 I915_WRITE(RSTDBYCTL
, I915_READ(RSTDBYCTL
) & ~RCX_SW_EXIT
);
3708 static unsigned long intel_pxfreq(u32 vidfreq
)
3711 int div
= (vidfreq
& 0x3f0000) >> 16;
3712 int post
= (vidfreq
& 0x3000) >> 12;
3713 int pre
= (vidfreq
& 0x7);
3718 freq
= ((div
* 133333) / ((1<<post
) * pre
));
3723 static const struct cparams
{
3729 { 1, 1333, 301, 28664 },
3730 { 1, 1066, 294, 24460 },
3731 { 1, 800, 294, 25192 },
3732 { 0, 1333, 276, 27605 },
3733 { 0, 1066, 276, 27605 },
3734 { 0, 800, 231, 23784 },
3737 static unsigned long __i915_chipset_val(struct drm_i915_private
*dev_priv
)
3739 u64 total_count
, diff
, ret
;
3740 u32 count1
, count2
, count3
, m
= 0, c
= 0;
3741 unsigned long now
= jiffies_to_msecs(jiffies
), diff1
;
3744 assert_spin_locked(&mchdev_lock
);
3746 diff1
= now
- dev_priv
->ips
.last_time1
;
3748 /* Prevent division-by-zero if we are asking too fast.
3749 * Also, we don't get interesting results if we are polling
3750 * faster than once in 10ms, so just return the saved value
3754 return dev_priv
->ips
.chipset_power
;
3756 count1
= I915_READ(DMIEC
);
3757 count2
= I915_READ(DDREC
);
3758 count3
= I915_READ(CSIEC
);
3760 total_count
= count1
+ count2
+ count3
;
3762 /* FIXME: handle per-counter overflow */
3763 if (total_count
< dev_priv
->ips
.last_count1
) {
3764 diff
= ~0UL - dev_priv
->ips
.last_count1
;
3765 diff
+= total_count
;
3767 diff
= total_count
- dev_priv
->ips
.last_count1
;
3770 for (i
= 0; i
< ARRAY_SIZE(cparams
); i
++) {
3771 if (cparams
[i
].i
== dev_priv
->ips
.c_m
&&
3772 cparams
[i
].t
== dev_priv
->ips
.r_t
) {
3779 diff
= div_u64(diff
, diff1
);
3780 ret
= ((m
* diff
) + c
);
3781 ret
= div_u64(ret
, 10);
3783 dev_priv
->ips
.last_count1
= total_count
;
3784 dev_priv
->ips
.last_time1
= now
;
3786 dev_priv
->ips
.chipset_power
= ret
;
3791 unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
)
3795 if (dev_priv
->info
->gen
!= 5)
3798 spin_lock_irq(&mchdev_lock
);
3800 val
= __i915_chipset_val(dev_priv
);
3802 spin_unlock_irq(&mchdev_lock
);
3807 unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
)
3809 unsigned long m
, x
, b
;
3812 tsfs
= I915_READ(TSFS
);
3814 m
= ((tsfs
& TSFS_SLOPE_MASK
) >> TSFS_SLOPE_SHIFT
);
3815 x
= I915_READ8(TR1
);
3817 b
= tsfs
& TSFS_INTR_MASK
;
3819 return ((m
* x
) / 127) - b
;
3822 static u16
pvid_to_extvid(struct drm_i915_private
*dev_priv
, u8 pxvid
)
3824 static const struct v_table
{
3825 u16 vd
; /* in .1 mil */
3826 u16 vm
; /* in .1 mil */
3957 if (dev_priv
->info
->is_mobile
)
3958 return v_table
[pxvid
].vm
;
3960 return v_table
[pxvid
].vd
;
3963 static void __i915_update_gfx_val(struct drm_i915_private
*dev_priv
)
3965 struct timespec now
, diff1
;
3967 unsigned long diffms
;
3970 assert_spin_locked(&mchdev_lock
);
3972 getrawmonotonic(&now
);
3973 diff1
= timespec_sub(now
, dev_priv
->ips
.last_time2
);
3975 /* Don't divide by 0 */
3976 diffms
= diff1
.tv_sec
* 1000 + diff1
.tv_nsec
/ 1000000;
3980 count
= I915_READ(GFXEC
);
3982 if (count
< dev_priv
->ips
.last_count2
) {
3983 diff
= ~0UL - dev_priv
->ips
.last_count2
;
3986 diff
= count
- dev_priv
->ips
.last_count2
;
3989 dev_priv
->ips
.last_count2
= count
;
3990 dev_priv
->ips
.last_time2
= now
;
3992 /* More magic constants... */
3994 diff
= div_u64(diff
, diffms
* 10);
3995 dev_priv
->ips
.gfx_power
= diff
;
3998 void i915_update_gfx_val(struct drm_i915_private
*dev_priv
)
4000 if (dev_priv
->info
->gen
!= 5)
4003 spin_lock_irq(&mchdev_lock
);
4005 __i915_update_gfx_val(dev_priv
);
4007 spin_unlock_irq(&mchdev_lock
);
4010 static unsigned long __i915_gfx_val(struct drm_i915_private
*dev_priv
)
4012 unsigned long t
, corr
, state1
, corr2
, state2
;
4015 assert_spin_locked(&mchdev_lock
);
4017 pxvid
= I915_READ(PXVFREQ_BASE
+ (dev_priv
->rps
.cur_delay
* 4));
4018 pxvid
= (pxvid
>> 24) & 0x7f;
4019 ext_v
= pvid_to_extvid(dev_priv
, pxvid
);
4023 t
= i915_mch_val(dev_priv
);
4025 /* Revel in the empirically derived constants */
4027 /* Correction factor in 1/100000 units */
4029 corr
= ((t
* 2349) + 135940);
4031 corr
= ((t
* 964) + 29317);
4033 corr
= ((t
* 301) + 1004);
4035 corr
= corr
* ((150142 * state1
) / 10000 - 78642);
4037 corr2
= (corr
* dev_priv
->ips
.corr
);
4039 state2
= (corr2
* state1
) / 10000;
4040 state2
/= 100; /* convert to mW */
4042 __i915_update_gfx_val(dev_priv
);
4044 return dev_priv
->ips
.gfx_power
+ state2
;
4047 unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
)
4051 if (dev_priv
->info
->gen
!= 5)
4054 spin_lock_irq(&mchdev_lock
);
4056 val
= __i915_gfx_val(dev_priv
);
4058 spin_unlock_irq(&mchdev_lock
);
4064 * i915_read_mch_val - return value for IPS use
4066 * Calculate and return a value for the IPS driver to use when deciding whether
4067 * we have thermal and power headroom to increase CPU or GPU power budget.
4069 unsigned long i915_read_mch_val(void)
4071 struct drm_i915_private
*dev_priv
;
4072 unsigned long chipset_val
, graphics_val
, ret
= 0;
4074 spin_lock_irq(&mchdev_lock
);
4077 dev_priv
= i915_mch_dev
;
4079 chipset_val
= __i915_chipset_val(dev_priv
);
4080 graphics_val
= __i915_gfx_val(dev_priv
);
4082 ret
= chipset_val
+ graphics_val
;
4085 spin_unlock_irq(&mchdev_lock
);
4089 EXPORT_SYMBOL_GPL(i915_read_mch_val
);
4092 * i915_gpu_raise - raise GPU frequency limit
4094 * Raise the limit; IPS indicates we have thermal headroom.
4096 bool i915_gpu_raise(void)
4098 struct drm_i915_private
*dev_priv
;
4101 spin_lock_irq(&mchdev_lock
);
4102 if (!i915_mch_dev
) {
4106 dev_priv
= i915_mch_dev
;
4108 if (dev_priv
->ips
.max_delay
> dev_priv
->ips
.fmax
)
4109 dev_priv
->ips
.max_delay
--;
4112 spin_unlock_irq(&mchdev_lock
);
4116 EXPORT_SYMBOL_GPL(i915_gpu_raise
);
4119 * i915_gpu_lower - lower GPU frequency limit
4121 * IPS indicates we're close to a thermal limit, so throttle back the GPU
4122 * frequency maximum.
4124 bool i915_gpu_lower(void)
4126 struct drm_i915_private
*dev_priv
;
4129 spin_lock_irq(&mchdev_lock
);
4130 if (!i915_mch_dev
) {
4134 dev_priv
= i915_mch_dev
;
4136 if (dev_priv
->ips
.max_delay
< dev_priv
->ips
.min_delay
)
4137 dev_priv
->ips
.max_delay
++;
4140 spin_unlock_irq(&mchdev_lock
);
4144 EXPORT_SYMBOL_GPL(i915_gpu_lower
);
4147 * i915_gpu_busy - indicate GPU business to IPS
4149 * Tell the IPS driver whether or not the GPU is busy.
4151 bool i915_gpu_busy(void)
4153 struct drm_i915_private
*dev_priv
;
4154 struct intel_ring_buffer
*ring
;
4158 spin_lock_irq(&mchdev_lock
);
4161 dev_priv
= i915_mch_dev
;
4163 for_each_ring(ring
, dev_priv
, i
)
4164 ret
|= !list_empty(&ring
->request_list
);
4167 spin_unlock_irq(&mchdev_lock
);
4171 EXPORT_SYMBOL_GPL(i915_gpu_busy
);
4174 * i915_gpu_turbo_disable - disable graphics turbo
4176 * Disable graphics turbo by resetting the max frequency and setting the
4177 * current frequency to the default.
4179 bool i915_gpu_turbo_disable(void)
4181 struct drm_i915_private
*dev_priv
;
4184 spin_lock_irq(&mchdev_lock
);
4185 if (!i915_mch_dev
) {
4189 dev_priv
= i915_mch_dev
;
4191 dev_priv
->ips
.max_delay
= dev_priv
->ips
.fstart
;
4193 if (!ironlake_set_drps(dev_priv
->dev
, dev_priv
->ips
.fstart
))
4197 spin_unlock_irq(&mchdev_lock
);
4201 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable
);
4204 * Tells the intel_ips driver that the i915 driver is now loaded, if
4205 * IPS got loaded first.
4207 * This awkward dance is so that neither module has to depend on the
4208 * other in order for IPS to do the appropriate communication of
4209 * GPU turbo limits to i915.
4212 ips_ping_for_i915_load(void)
4216 link
= symbol_get(ips_link_to_i915_driver
);
4219 symbol_put(ips_link_to_i915_driver
);
4223 void intel_gpu_ips_init(struct drm_i915_private
*dev_priv
)
4225 /* We only register the i915 ips part with intel-ips once everything is
4226 * set up, to avoid intel-ips sneaking in and reading bogus values. */
4227 spin_lock_irq(&mchdev_lock
);
4228 i915_mch_dev
= dev_priv
;
4229 spin_unlock_irq(&mchdev_lock
);
4231 ips_ping_for_i915_load();
4234 void intel_gpu_ips_teardown(void)
4236 spin_lock_irq(&mchdev_lock
);
4237 i915_mch_dev
= NULL
;
4238 spin_unlock_irq(&mchdev_lock
);
4240 static void intel_init_emon(struct drm_device
*dev
)
4242 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4247 /* Disable to program */
4251 /* Program energy weights for various events */
4252 I915_WRITE(SDEW
, 0x15040d00);
4253 I915_WRITE(CSIEW0
, 0x007f0000);
4254 I915_WRITE(CSIEW1
, 0x1e220004);
4255 I915_WRITE(CSIEW2
, 0x04000004);
4257 for (i
= 0; i
< 5; i
++)
4258 I915_WRITE(PEW
+ (i
* 4), 0);
4259 for (i
= 0; i
< 3; i
++)
4260 I915_WRITE(DEW
+ (i
* 4), 0);
4262 /* Program P-state weights to account for frequency power adjustment */
4263 for (i
= 0; i
< 16; i
++) {
4264 u32 pxvidfreq
= I915_READ(PXVFREQ_BASE
+ (i
* 4));
4265 unsigned long freq
= intel_pxfreq(pxvidfreq
);
4266 unsigned long vid
= (pxvidfreq
& PXVFREQ_PX_MASK
) >>
4271 val
*= (freq
/ 1000);
4273 val
/= (127*127*900);
4275 DRM_ERROR("bad pxval: %ld\n", val
);
4278 /* Render standby states get 0 weight */
4282 for (i
= 0; i
< 4; i
++) {
4283 u32 val
= (pxw
[i
*4] << 24) | (pxw
[(i
*4)+1] << 16) |
4284 (pxw
[(i
*4)+2] << 8) | (pxw
[(i
*4)+3]);
4285 I915_WRITE(PXW
+ (i
* 4), val
);
4288 /* Adjust magic regs to magic values (more experimental results) */
4289 I915_WRITE(OGW0
, 0);
4290 I915_WRITE(OGW1
, 0);
4291 I915_WRITE(EG0
, 0x00007f00);
4292 I915_WRITE(EG1
, 0x0000000e);
4293 I915_WRITE(EG2
, 0x000e0000);
4294 I915_WRITE(EG3
, 0x68000300);
4295 I915_WRITE(EG4
, 0x42000000);
4296 I915_WRITE(EG5
, 0x00140031);
4300 for (i
= 0; i
< 8; i
++)
4301 I915_WRITE(PXWL
+ (i
* 4), 0);
4303 /* Enable PMON + select events */
4304 I915_WRITE(ECR
, 0x80000019);
4306 lcfuse
= I915_READ(LCFUSE02
);
4308 dev_priv
->ips
.corr
= (lcfuse
& LCFUSE_HIV_MASK
);
4311 void intel_disable_gt_powersave(struct drm_device
*dev
)
4313 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4315 /* Interrupts should be disabled already to avoid re-arming. */
4316 WARN_ON(dev
->irq_enabled
);
4318 if (IS_IRONLAKE_M(dev
)) {
4319 ironlake_disable_drps(dev
);
4320 ironlake_disable_rc6(dev
);
4321 } else if (INTEL_INFO(dev
)->gen
>= 6) {
4322 cancel_delayed_work_sync(&dev_priv
->rps
.delayed_resume_work
);
4323 cancel_work_sync(&dev_priv
->rps
.work
);
4324 if (IS_VALLEYVIEW(dev
))
4325 cancel_delayed_work_sync(&dev_priv
->rps
.vlv_work
);
4326 mutex_lock(&dev_priv
->rps
.hw_lock
);
4327 if (IS_VALLEYVIEW(dev
))
4328 valleyview_disable_rps(dev
);
4330 gen6_disable_rps(dev
);
4331 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4335 static void intel_gen6_powersave_work(struct work_struct
*work
)
4337 struct drm_i915_private
*dev_priv
=
4338 container_of(work
, struct drm_i915_private
,
4339 rps
.delayed_resume_work
.work
);
4340 struct drm_device
*dev
= dev_priv
->dev
;
4342 mutex_lock(&dev_priv
->rps
.hw_lock
);
4344 if (IS_VALLEYVIEW(dev
)) {
4345 valleyview_enable_rps(dev
);
4347 gen6_enable_rps(dev
);
4348 gen6_update_ring_freq(dev
);
4350 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4353 void intel_enable_gt_powersave(struct drm_device
*dev
)
4355 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4357 if (IS_IRONLAKE_M(dev
)) {
4358 ironlake_enable_drps(dev
);
4359 ironlake_enable_rc6(dev
);
4360 intel_init_emon(dev
);
4361 } else if (IS_GEN6(dev
) || IS_GEN7(dev
)) {
4363 * PCU communication is slow and this doesn't need to be
4364 * done at any specific time, so do this out of our fast path
4365 * to make resume and init faster.
4367 schedule_delayed_work(&dev_priv
->rps
.delayed_resume_work
,
4368 round_jiffies_up_relative(HZ
));
4372 static void ibx_init_clock_gating(struct drm_device
*dev
)
4374 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4377 * On Ibex Peak and Cougar Point, we need to disable clock
4378 * gating for the panel power sequencer or it will fail to
4379 * start up when no ports are active.
4381 I915_WRITE(SOUTH_DSPCLK_GATE_D
, PCH_DPLSUNIT_CLOCK_GATE_DISABLE
);
4384 static void ironlake_init_clock_gating(struct drm_device
*dev
)
4386 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4387 uint32_t dspclk_gate
= ILK_VRHUNIT_CLOCK_GATE_DISABLE
;
4389 /* Required for FBC */
4390 dspclk_gate
|= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE
|
4391 ILK_DPFCUNIT_CLOCK_GATE_DISABLE
|
4392 ILK_DPFDUNIT_CLOCK_GATE_ENABLE
;
4394 I915_WRITE(PCH_3DCGDIS0
,
4395 MARIUNIT_CLOCK_GATE_DISABLE
|
4396 SVSMUNIT_CLOCK_GATE_DISABLE
);
4397 I915_WRITE(PCH_3DCGDIS1
,
4398 VFMUNIT_CLOCK_GATE_DISABLE
);
4401 * According to the spec the following bits should be set in
4402 * order to enable memory self-refresh
4403 * The bit 22/21 of 0x42004
4404 * The bit 5 of 0x42020
4405 * The bit 15 of 0x45000
4407 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
4408 (I915_READ(ILK_DISPLAY_CHICKEN2
) |
4409 ILK_DPARB_GATE
| ILK_VSDPFD_FULL
));
4410 dspclk_gate
|= ILK_DPARBUNIT_CLOCK_GATE_ENABLE
;
4411 I915_WRITE(DISP_ARB_CTL
,
4412 (I915_READ(DISP_ARB_CTL
) |
4414 I915_WRITE(WM3_LP_ILK
, 0);
4415 I915_WRITE(WM2_LP_ILK
, 0);
4416 I915_WRITE(WM1_LP_ILK
, 0);
4419 * Based on the document from hardware guys the following bits
4420 * should be set unconditionally in order to enable FBC.
4421 * The bit 22 of 0x42000
4422 * The bit 22 of 0x42004
4423 * The bit 7,8,9 of 0x42020.
4425 if (IS_IRONLAKE_M(dev
)) {
4426 I915_WRITE(ILK_DISPLAY_CHICKEN1
,
4427 I915_READ(ILK_DISPLAY_CHICKEN1
) |
4429 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
4430 I915_READ(ILK_DISPLAY_CHICKEN2
) |
4434 I915_WRITE(ILK_DSPCLK_GATE_D
, dspclk_gate
);
4436 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
4437 I915_READ(ILK_DISPLAY_CHICKEN2
) |
4438 ILK_ELPIN_409_SELECT
);
4439 I915_WRITE(_3D_CHICKEN2
,
4440 _3D_CHICKEN2_WM_READ_PIPELINED
<< 16 |
4441 _3D_CHICKEN2_WM_READ_PIPELINED
);
4443 /* WaDisableRenderCachePipelinedFlush:ilk */
4444 I915_WRITE(CACHE_MODE_0
,
4445 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE
));
4447 ibx_init_clock_gating(dev
);
4450 static void cpt_init_clock_gating(struct drm_device
*dev
)
4452 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4457 * On Ibex Peak and Cougar Point, we need to disable clock
4458 * gating for the panel power sequencer or it will fail to
4459 * start up when no ports are active.
4461 I915_WRITE(SOUTH_DSPCLK_GATE_D
, PCH_DPLSUNIT_CLOCK_GATE_DISABLE
);
4462 I915_WRITE(SOUTH_CHICKEN2
, I915_READ(SOUTH_CHICKEN2
) |
4463 DPLS_EDP_PPS_FIX_DIS
);
4464 /* The below fixes the weird display corruption, a few pixels shifted
4465 * downward, on (only) LVDS of some HP laptops with IVY.
4467 for_each_pipe(pipe
) {
4468 val
= I915_READ(TRANS_CHICKEN2(pipe
));
4469 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
4470 val
&= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED
;
4471 if (dev_priv
->vbt
.fdi_rx_polarity_inverted
)
4472 val
|= TRANS_CHICKEN2_FDI_POLARITY_REVERSED
;
4473 val
&= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK
;
4474 val
&= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER
;
4475 val
&= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH
;
4476 I915_WRITE(TRANS_CHICKEN2(pipe
), val
);
4478 /* WADP0ClockGatingDisable */
4479 for_each_pipe(pipe
) {
4480 I915_WRITE(TRANS_CHICKEN1(pipe
),
4481 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE
);
4485 static void gen6_check_mch_setup(struct drm_device
*dev
)
4487 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4490 tmp
= I915_READ(MCH_SSKPD
);
4491 if ((tmp
& MCH_SSKPD_WM0_MASK
) != MCH_SSKPD_WM0_VAL
) {
4492 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp
);
4493 DRM_INFO("This can cause pipe underruns and display issues.\n");
4494 DRM_INFO("Please upgrade your BIOS to fix this.\n");
4498 static void gen6_init_clock_gating(struct drm_device
*dev
)
4500 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4502 uint32_t dspclk_gate
= ILK_VRHUNIT_CLOCK_GATE_DISABLE
;
4504 I915_WRITE(ILK_DSPCLK_GATE_D
, dspclk_gate
);
4506 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
4507 I915_READ(ILK_DISPLAY_CHICKEN2
) |
4508 ILK_ELPIN_409_SELECT
);
4510 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4511 I915_WRITE(_3D_CHICKEN
,
4512 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB
));
4514 /* WaSetupGtModeTdRowDispatch:snb */
4515 if (IS_SNB_GT1(dev
))
4516 I915_WRITE(GEN6_GT_MODE
,
4517 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE
));
4519 I915_WRITE(WM3_LP_ILK
, 0);
4520 I915_WRITE(WM2_LP_ILK
, 0);
4521 I915_WRITE(WM1_LP_ILK
, 0);
4523 I915_WRITE(CACHE_MODE_0
,
4524 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB
));
4526 I915_WRITE(GEN6_UCGCTL1
,
4527 I915_READ(GEN6_UCGCTL1
) |
4528 GEN6_BLBUNIT_CLOCK_GATE_DISABLE
|
4529 GEN6_CSUNIT_CLOCK_GATE_DISABLE
);
4531 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4532 * gating disable must be set. Failure to set it results in
4533 * flickering pixels due to Z write ordering failures after
4534 * some amount of runtime in the Mesa "fire" demo, and Unigine
4535 * Sanctuary and Tropics, and apparently anything else with
4536 * alpha test or pixel discard.
4538 * According to the spec, bit 11 (RCCUNIT) must also be set,
4539 * but we didn't debug actual testcases to find it out.
4541 * Also apply WaDisableVDSUnitClockGating:snb and
4542 * WaDisableRCPBUnitClockGating:snb.
4544 I915_WRITE(GEN6_UCGCTL2
,
4545 GEN7_VDSUNIT_CLOCK_GATE_DISABLE
|
4546 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE
|
4547 GEN6_RCCUNIT_CLOCK_GATE_DISABLE
);
4549 /* Bspec says we need to always set all mask bits. */
4550 I915_WRITE(_3D_CHICKEN3
, (0xFFFF << 16) |
4551 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL
);
4554 * According to the spec the following bits should be
4555 * set in order to enable memory self-refresh and fbc:
4556 * The bit21 and bit22 of 0x42000
4557 * The bit21 and bit22 of 0x42004
4558 * The bit5 and bit7 of 0x42020
4559 * The bit14 of 0x70180
4560 * The bit14 of 0x71180
4562 I915_WRITE(ILK_DISPLAY_CHICKEN1
,
4563 I915_READ(ILK_DISPLAY_CHICKEN1
) |
4564 ILK_FBCQ_DIS
| ILK_PABSTRETCH_DIS
);
4565 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
4566 I915_READ(ILK_DISPLAY_CHICKEN2
) |
4567 ILK_DPARB_GATE
| ILK_VSDPFD_FULL
);
4568 I915_WRITE(ILK_DSPCLK_GATE_D
,
4569 I915_READ(ILK_DSPCLK_GATE_D
) |
4570 ILK_DPARBUNIT_CLOCK_GATE_ENABLE
|
4571 ILK_DPFDUNIT_CLOCK_GATE_ENABLE
);
4573 /* WaMbcDriverBootEnable:snb */
4574 I915_WRITE(GEN6_MBCTL
, I915_READ(GEN6_MBCTL
) |
4575 GEN6_MBCTL_ENABLE_BOOT_FETCH
);
4577 for_each_pipe(pipe
) {
4578 I915_WRITE(DSPCNTR(pipe
),
4579 I915_READ(DSPCNTR(pipe
)) |
4580 DISPPLANE_TRICKLE_FEED_DISABLE
);
4581 intel_flush_display_plane(dev_priv
, pipe
);
4584 /* The default value should be 0x200 according to docs, but the two
4585 * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
4586 I915_WRITE(GEN6_GT_MODE
, _MASKED_BIT_DISABLE(0xffff));
4587 I915_WRITE(GEN6_GT_MODE
, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI
));
4589 cpt_init_clock_gating(dev
);
4591 gen6_check_mch_setup(dev
);
4594 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private
*dev_priv
)
4596 uint32_t reg
= I915_READ(GEN7_FF_THREAD_MODE
);
4598 reg
&= ~GEN7_FF_SCHED_MASK
;
4599 reg
|= GEN7_FF_TS_SCHED_HW
;
4600 reg
|= GEN7_FF_VS_SCHED_HW
;
4601 reg
|= GEN7_FF_DS_SCHED_HW
;
4603 if (IS_HASWELL(dev_priv
->dev
))
4604 reg
&= ~GEN7_FF_VS_REF_CNT_FFME
;
4606 I915_WRITE(GEN7_FF_THREAD_MODE
, reg
);
4609 static void lpt_init_clock_gating(struct drm_device
*dev
)
4611 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4614 * TODO: this bit should only be enabled when really needed, then
4615 * disabled when not needed anymore in order to save power.
4617 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
)
4618 I915_WRITE(SOUTH_DSPCLK_GATE_D
,
4619 I915_READ(SOUTH_DSPCLK_GATE_D
) |
4620 PCH_LP_PARTITION_LEVEL_DISABLE
);
4622 /* WADPOClockGatingDisable:hsw */
4623 I915_WRITE(_TRANSA_CHICKEN1
,
4624 I915_READ(_TRANSA_CHICKEN1
) |
4625 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE
);
4628 static void lpt_suspend_hw(struct drm_device
*dev
)
4630 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4632 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
4633 uint32_t val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
4635 val
&= ~PCH_LP_PARTITION_LEVEL_DISABLE
;
4636 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
4640 static void haswell_init_clock_gating(struct drm_device
*dev
)
4642 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4645 I915_WRITE(WM3_LP_ILK
, 0);
4646 I915_WRITE(WM2_LP_ILK
, 0);
4647 I915_WRITE(WM1_LP_ILK
, 0);
4649 /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
4650 * This implements the WaDisableRCZUnitClockGating:hsw workaround.
4652 I915_WRITE(GEN6_UCGCTL2
, GEN6_RCZUNIT_CLOCK_GATE_DISABLE
);
4654 /* Apply the WaDisableRHWOOptimizationForRenderHang:hsw workaround. */
4655 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1
,
4656 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC
);
4658 /* WaApplyL3ControlAndL3ChickenMode:hsw */
4659 I915_WRITE(GEN7_L3CNTLREG1
,
4660 GEN7_WA_FOR_GEN7_L3_CONTROL
);
4661 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER
,
4662 GEN7_WA_L3_CHICKEN_MODE
);
4664 /* This is required by WaCatErrorRejectionIssue:hsw */
4665 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
4666 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
4667 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
4669 for_each_pipe(pipe
) {
4670 I915_WRITE(DSPCNTR(pipe
),
4671 I915_READ(DSPCNTR(pipe
)) |
4672 DISPPLANE_TRICKLE_FEED_DISABLE
);
4673 intel_flush_display_plane(dev_priv
, pipe
);
4676 /* WaVSRefCountFullforceMissDisable:hsw */
4677 gen7_setup_fixed_func_scheduler(dev_priv
);
4679 /* WaDisable4x2SubspanOptimization:hsw */
4680 I915_WRITE(CACHE_MODE_1
,
4681 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
));
4683 /* WaMbcDriverBootEnable:hsw */
4684 I915_WRITE(GEN6_MBCTL
, I915_READ(GEN6_MBCTL
) |
4685 GEN6_MBCTL_ENABLE_BOOT_FETCH
);
4687 /* WaSwitchSolVfFArbitrationPriority:hsw */
4688 I915_WRITE(GAM_ECOCHK
, I915_READ(GAM_ECOCHK
) | HSW_ECOCHK_ARB_PRIO_SOL
);
4690 /* WaRsPkgCStateDisplayPMReq:hsw */
4691 I915_WRITE(CHICKEN_PAR1_1
,
4692 I915_READ(CHICKEN_PAR1_1
) | FORCE_ARB_IDLE_PLANES
);
4694 lpt_init_clock_gating(dev
);
4697 static void ivybridge_init_clock_gating(struct drm_device
*dev
)
4699 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4703 I915_WRITE(WM3_LP_ILK
, 0);
4704 I915_WRITE(WM2_LP_ILK
, 0);
4705 I915_WRITE(WM1_LP_ILK
, 0);
4707 I915_WRITE(ILK_DSPCLK_GATE_D
, ILK_VRHUNIT_CLOCK_GATE_DISABLE
);
4709 /* WaDisableEarlyCull:ivb */
4710 I915_WRITE(_3D_CHICKEN3
,
4711 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL
));
4713 /* WaDisableBackToBackFlipFix:ivb */
4714 I915_WRITE(IVB_CHICKEN3
,
4715 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE
|
4716 CHICKEN3_DGMG_DONE_FIX_DISABLE
);
4718 /* WaDisablePSDDualDispatchEnable:ivb */
4719 if (IS_IVB_GT1(dev
))
4720 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1
,
4721 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE
));
4723 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2
,
4724 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE
));
4726 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
4727 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1
,
4728 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC
);
4730 /* WaApplyL3ControlAndL3ChickenMode:ivb */
4731 I915_WRITE(GEN7_L3CNTLREG1
,
4732 GEN7_WA_FOR_GEN7_L3_CONTROL
);
4733 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER
,
4734 GEN7_WA_L3_CHICKEN_MODE
);
4735 if (IS_IVB_GT1(dev
))
4736 I915_WRITE(GEN7_ROW_CHICKEN2
,
4737 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
4739 I915_WRITE(GEN7_ROW_CHICKEN2_GT2
,
4740 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
4743 /* WaForceL3Serialization:ivb */
4744 I915_WRITE(GEN7_L3SQCREG4
, I915_READ(GEN7_L3SQCREG4
) &
4745 ~L3SQ_URB_READ_CAM_MATCH_DISABLE
);
4747 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4748 * gating disable must be set. Failure to set it results in
4749 * flickering pixels due to Z write ordering failures after
4750 * some amount of runtime in the Mesa "fire" demo, and Unigine
4751 * Sanctuary and Tropics, and apparently anything else with
4752 * alpha test or pixel discard.
4754 * According to the spec, bit 11 (RCCUNIT) must also be set,
4755 * but we didn't debug actual testcases to find it out.
4757 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
4758 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
4760 I915_WRITE(GEN6_UCGCTL2
,
4761 GEN6_RCZUNIT_CLOCK_GATE_DISABLE
|
4762 GEN6_RCCUNIT_CLOCK_GATE_DISABLE
);
4764 /* This is required by WaCatErrorRejectionIssue:ivb */
4765 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
4766 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
4767 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
4769 for_each_pipe(pipe
) {
4770 I915_WRITE(DSPCNTR(pipe
),
4771 I915_READ(DSPCNTR(pipe
)) |
4772 DISPPLANE_TRICKLE_FEED_DISABLE
);
4773 intel_flush_display_plane(dev_priv
, pipe
);
4776 /* WaMbcDriverBootEnable:ivb */
4777 I915_WRITE(GEN6_MBCTL
, I915_READ(GEN6_MBCTL
) |
4778 GEN6_MBCTL_ENABLE_BOOT_FETCH
);
4780 /* WaVSRefCountFullforceMissDisable:ivb */
4781 gen7_setup_fixed_func_scheduler(dev_priv
);
4783 /* WaDisable4x2SubspanOptimization:ivb */
4784 I915_WRITE(CACHE_MODE_1
,
4785 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
));
4787 snpcr
= I915_READ(GEN6_MBCUNIT_SNPCR
);
4788 snpcr
&= ~GEN6_MBC_SNPCR_MASK
;
4789 snpcr
|= GEN6_MBC_SNPCR_MED
;
4790 I915_WRITE(GEN6_MBCUNIT_SNPCR
, snpcr
);
4792 if (!HAS_PCH_NOP(dev
))
4793 cpt_init_clock_gating(dev
);
4795 gen6_check_mch_setup(dev
);
4798 static void valleyview_init_clock_gating(struct drm_device
*dev
)
4800 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4803 I915_WRITE(WM3_LP_ILK
, 0);
4804 I915_WRITE(WM2_LP_ILK
, 0);
4805 I915_WRITE(WM1_LP_ILK
, 0);
4807 I915_WRITE(ILK_DSPCLK_GATE_D
, ILK_VRHUNIT_CLOCK_GATE_DISABLE
);
4809 /* WaDisableEarlyCull:vlv */
4810 I915_WRITE(_3D_CHICKEN3
,
4811 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL
));
4813 /* WaDisableBackToBackFlipFix:vlv */
4814 I915_WRITE(IVB_CHICKEN3
,
4815 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE
|
4816 CHICKEN3_DGMG_DONE_FIX_DISABLE
);
4818 /* WaDisablePSDDualDispatchEnable:vlv */
4819 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1
,
4820 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP
|
4821 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE
));
4823 /* Apply the WaDisableRHWOOptimizationForRenderHang:vlv workaround. */
4824 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1
,
4825 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC
);
4827 /* WaApplyL3ControlAndL3ChickenMode:vlv */
4828 I915_WRITE(GEN7_L3CNTLREG1
, I915_READ(GEN7_L3CNTLREG1
) | GEN7_L3AGDIS
);
4829 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER
, GEN7_WA_L3_CHICKEN_MODE
);
4831 /* WaForceL3Serialization:vlv */
4832 I915_WRITE(GEN7_L3SQCREG4
, I915_READ(GEN7_L3SQCREG4
) &
4833 ~L3SQ_URB_READ_CAM_MATCH_DISABLE
);
4835 /* WaDisableDopClockGating:vlv */
4836 I915_WRITE(GEN7_ROW_CHICKEN2
,
4837 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
4839 /* WaForceL3Serialization:vlv */
4840 I915_WRITE(GEN7_L3SQCREG4
, I915_READ(GEN7_L3SQCREG4
) &
4841 ~L3SQ_URB_READ_CAM_MATCH_DISABLE
);
4843 /* This is required by WaCatErrorRejectionIssue:vlv */
4844 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
4845 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
4846 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
4848 /* WaMbcDriverBootEnable:vlv */
4849 I915_WRITE(GEN6_MBCTL
, I915_READ(GEN6_MBCTL
) |
4850 GEN6_MBCTL_ENABLE_BOOT_FETCH
);
4853 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4854 * gating disable must be set. Failure to set it results in
4855 * flickering pixels due to Z write ordering failures after
4856 * some amount of runtime in the Mesa "fire" demo, and Unigine
4857 * Sanctuary and Tropics, and apparently anything else with
4858 * alpha test or pixel discard.
4860 * According to the spec, bit 11 (RCCUNIT) must also be set,
4861 * but we didn't debug actual testcases to find it out.
4863 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
4864 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
4866 * Also apply WaDisableVDSUnitClockGating:vlv and
4867 * WaDisableRCPBUnitClockGating:vlv.
4869 I915_WRITE(GEN6_UCGCTL2
,
4870 GEN7_VDSUNIT_CLOCK_GATE_DISABLE
|
4871 GEN7_TDLUNIT_CLOCK_GATE_DISABLE
|
4872 GEN6_RCZUNIT_CLOCK_GATE_DISABLE
|
4873 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE
|
4874 GEN6_RCCUNIT_CLOCK_GATE_DISABLE
);
4876 I915_WRITE(GEN7_UCGCTL4
, GEN7_L3BANK2X_CLOCK_GATE_DISABLE
);
4878 for_each_pipe(pipe
) {
4879 I915_WRITE(DSPCNTR(pipe
),
4880 I915_READ(DSPCNTR(pipe
)) |
4881 DISPPLANE_TRICKLE_FEED_DISABLE
);
4882 intel_flush_display_plane(dev_priv
, pipe
);
4885 I915_WRITE(CACHE_MODE_1
,
4886 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
));
4889 * WaDisableVLVClockGating_VBIIssue:vlv
4890 * Disable clock gating on th GCFG unit to prevent a delay
4891 * in the reporting of vblank events.
4893 I915_WRITE(VLV_GUNIT_CLOCK_GATE
, 0xffffffff);
4895 /* Conservative clock gating settings for now */
4896 I915_WRITE(0x9400, 0xffffffff);
4897 I915_WRITE(0x9404, 0xffffffff);
4898 I915_WRITE(0x9408, 0xffffffff);
4899 I915_WRITE(0x940c, 0xffffffff);
4900 I915_WRITE(0x9410, 0xffffffff);
4901 I915_WRITE(0x9414, 0xffffffff);
4902 I915_WRITE(0x9418, 0xffffffff);
4905 static void g4x_init_clock_gating(struct drm_device
*dev
)
4907 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4908 uint32_t dspclk_gate
;
4910 I915_WRITE(RENCLK_GATE_D1
, 0);
4911 I915_WRITE(RENCLK_GATE_D2
, VF_UNIT_CLOCK_GATE_DISABLE
|
4912 GS_UNIT_CLOCK_GATE_DISABLE
|
4913 CL_UNIT_CLOCK_GATE_DISABLE
);
4914 I915_WRITE(RAMCLK_GATE_D
, 0);
4915 dspclk_gate
= VRHUNIT_CLOCK_GATE_DISABLE
|
4916 OVRUNIT_CLOCK_GATE_DISABLE
|
4917 OVCUNIT_CLOCK_GATE_DISABLE
;
4919 dspclk_gate
|= DSSUNIT_CLOCK_GATE_DISABLE
;
4920 I915_WRITE(DSPCLK_GATE_D
, dspclk_gate
);
4922 /* WaDisableRenderCachePipelinedFlush */
4923 I915_WRITE(CACHE_MODE_0
,
4924 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE
));
4927 static void crestline_init_clock_gating(struct drm_device
*dev
)
4929 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4931 I915_WRITE(RENCLK_GATE_D1
, I965_RCC_CLOCK_GATE_DISABLE
);
4932 I915_WRITE(RENCLK_GATE_D2
, 0);
4933 I915_WRITE(DSPCLK_GATE_D
, 0);
4934 I915_WRITE(RAMCLK_GATE_D
, 0);
4935 I915_WRITE16(DEUC
, 0);
4938 static void broadwater_init_clock_gating(struct drm_device
*dev
)
4940 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4942 I915_WRITE(RENCLK_GATE_D1
, I965_RCZ_CLOCK_GATE_DISABLE
|
4943 I965_RCC_CLOCK_GATE_DISABLE
|
4944 I965_RCPB_CLOCK_GATE_DISABLE
|
4945 I965_ISC_CLOCK_GATE_DISABLE
|
4946 I965_FBC_CLOCK_GATE_DISABLE
);
4947 I915_WRITE(RENCLK_GATE_D2
, 0);
4950 static void gen3_init_clock_gating(struct drm_device
*dev
)
4952 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4953 u32 dstate
= I915_READ(D_STATE
);
4955 dstate
|= DSTATE_PLL_D3_OFF
| DSTATE_GFX_CLOCK_GATING
|
4956 DSTATE_DOT_CLOCK_GATING
;
4957 I915_WRITE(D_STATE
, dstate
);
4959 if (IS_PINEVIEW(dev
))
4960 I915_WRITE(ECOSKPD
, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY
));
4962 /* IIR "flip pending" means done if this bit is set */
4963 I915_WRITE(ECOSKPD
, _MASKED_BIT_DISABLE(ECO_FLIP_DONE
));
4966 static void i85x_init_clock_gating(struct drm_device
*dev
)
4968 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4970 I915_WRITE(RENCLK_GATE_D1
, SV_CLOCK_GATE_DISABLE
);
4973 static void i830_init_clock_gating(struct drm_device
*dev
)
4975 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4977 I915_WRITE(DSPCLK_GATE_D
, OVRUNIT_CLOCK_GATE_DISABLE
);
4980 void intel_init_clock_gating(struct drm_device
*dev
)
4982 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4984 dev_priv
->display
.init_clock_gating(dev
);
4987 void intel_suspend_hw(struct drm_device
*dev
)
4989 if (HAS_PCH_LPT(dev
))
4990 lpt_suspend_hw(dev
);
4994 * We should only use the power well if we explicitly asked the hardware to
4995 * enable it, so check if it's enabled and also check if we've requested it to
4998 bool intel_display_power_enabled(struct drm_device
*dev
,
4999 enum intel_display_power_domain domain
)
5001 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5003 if (!HAS_POWER_WELL(dev
))
5007 case POWER_DOMAIN_PIPE_A
:
5008 case POWER_DOMAIN_TRANSCODER_EDP
:
5010 case POWER_DOMAIN_PIPE_B
:
5011 case POWER_DOMAIN_PIPE_C
:
5012 case POWER_DOMAIN_PIPE_A_PANEL_FITTER
:
5013 case POWER_DOMAIN_PIPE_B_PANEL_FITTER
:
5014 case POWER_DOMAIN_PIPE_C_PANEL_FITTER
:
5015 case POWER_DOMAIN_TRANSCODER_A
:
5016 case POWER_DOMAIN_TRANSCODER_B
:
5017 case POWER_DOMAIN_TRANSCODER_C
:
5018 return I915_READ(HSW_PWR_WELL_DRIVER
) ==
5019 (HSW_PWR_WELL_ENABLE
| HSW_PWR_WELL_STATE
);
5025 void intel_set_power_well(struct drm_device
*dev
, bool enable
)
5027 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5028 bool is_enabled
, enable_requested
;
5031 if (!HAS_POWER_WELL(dev
))
5034 if (!i915_disable_power_well
&& !enable
)
5037 tmp
= I915_READ(HSW_PWR_WELL_DRIVER
);
5038 is_enabled
= tmp
& HSW_PWR_WELL_STATE
;
5039 enable_requested
= tmp
& HSW_PWR_WELL_ENABLE
;
5042 if (!enable_requested
)
5043 I915_WRITE(HSW_PWR_WELL_DRIVER
, HSW_PWR_WELL_ENABLE
);
5046 DRM_DEBUG_KMS("Enabling power well\n");
5047 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER
) &
5048 HSW_PWR_WELL_STATE
), 20))
5049 DRM_ERROR("Timeout enabling power well\n");
5052 if (enable_requested
) {
5053 I915_WRITE(HSW_PWR_WELL_DRIVER
, 0);
5054 DRM_DEBUG_KMS("Requesting to disable the power well\n");
5060 * Starting with Haswell, we have a "Power Down Well" that can be turned off
5061 * when not needed anymore. We have 4 registers that can request the power well
5062 * to be enabled, and it will only be disabled if none of the registers is
5063 * requesting it to be enabled.
5065 void intel_init_power_well(struct drm_device
*dev
)
5067 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5069 if (!HAS_POWER_WELL(dev
))
5072 /* For now, we need the power well to be always enabled. */
5073 intel_set_power_well(dev
, true);
5075 /* We're taking over the BIOS, so clear any requests made by it since
5076 * the driver is in charge now. */
5077 if (I915_READ(HSW_PWR_WELL_BIOS
) & HSW_PWR_WELL_ENABLE
)
5078 I915_WRITE(HSW_PWR_WELL_BIOS
, 0);
5081 /* Set up chip specific power management-related functions */
5082 void intel_init_pm(struct drm_device
*dev
)
5084 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5086 if (I915_HAS_FBC(dev
)) {
5087 if (HAS_PCH_SPLIT(dev
)) {
5088 dev_priv
->display
.fbc_enabled
= ironlake_fbc_enabled
;
5089 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
))
5090 dev_priv
->display
.enable_fbc
=
5093 dev_priv
->display
.enable_fbc
=
5094 ironlake_enable_fbc
;
5095 dev_priv
->display
.disable_fbc
= ironlake_disable_fbc
;
5096 } else if (IS_GM45(dev
)) {
5097 dev_priv
->display
.fbc_enabled
= g4x_fbc_enabled
;
5098 dev_priv
->display
.enable_fbc
= g4x_enable_fbc
;
5099 dev_priv
->display
.disable_fbc
= g4x_disable_fbc
;
5100 } else if (IS_CRESTLINE(dev
)) {
5101 dev_priv
->display
.fbc_enabled
= i8xx_fbc_enabled
;
5102 dev_priv
->display
.enable_fbc
= i8xx_enable_fbc
;
5103 dev_priv
->display
.disable_fbc
= i8xx_disable_fbc
;
5105 /* 855GM needs testing */
5109 if (IS_PINEVIEW(dev
))
5110 i915_pineview_get_mem_freq(dev
);
5111 else if (IS_GEN5(dev
))
5112 i915_ironlake_get_mem_freq(dev
);
5114 /* For FIFO watermark updates */
5115 if (HAS_PCH_SPLIT(dev
)) {
5117 if (I915_READ(MLTR_ILK
) & ILK_SRLT_MASK
)
5118 dev_priv
->display
.update_wm
= ironlake_update_wm
;
5120 DRM_DEBUG_KMS("Failed to get proper latency. "
5122 dev_priv
->display
.update_wm
= NULL
;
5124 dev_priv
->display
.init_clock_gating
= ironlake_init_clock_gating
;
5125 } else if (IS_GEN6(dev
)) {
5126 if (SNB_READ_WM0_LATENCY()) {
5127 dev_priv
->display
.update_wm
= sandybridge_update_wm
;
5128 dev_priv
->display
.update_sprite_wm
= sandybridge_update_sprite_wm
;
5130 DRM_DEBUG_KMS("Failed to read display plane latency. "
5132 dev_priv
->display
.update_wm
= NULL
;
5134 dev_priv
->display
.init_clock_gating
= gen6_init_clock_gating
;
5135 } else if (IS_IVYBRIDGE(dev
)) {
5136 if (SNB_READ_WM0_LATENCY()) {
5137 dev_priv
->display
.update_wm
= ivybridge_update_wm
;
5138 dev_priv
->display
.update_sprite_wm
= sandybridge_update_sprite_wm
;
5140 DRM_DEBUG_KMS("Failed to read display plane latency. "
5142 dev_priv
->display
.update_wm
= NULL
;
5144 dev_priv
->display
.init_clock_gating
= ivybridge_init_clock_gating
;
5145 } else if (IS_HASWELL(dev
)) {
5146 if (I915_READ64(MCH_SSKPD
)) {
5147 dev_priv
->display
.update_wm
= haswell_update_wm
;
5148 dev_priv
->display
.update_sprite_wm
=
5149 haswell_update_sprite_wm
;
5151 DRM_DEBUG_KMS("Failed to read display plane latency. "
5153 dev_priv
->display
.update_wm
= NULL
;
5155 dev_priv
->display
.init_clock_gating
= haswell_init_clock_gating
;
5157 dev_priv
->display
.update_wm
= NULL
;
5158 } else if (IS_VALLEYVIEW(dev
)) {
5159 dev_priv
->display
.update_wm
= valleyview_update_wm
;
5160 dev_priv
->display
.init_clock_gating
=
5161 valleyview_init_clock_gating
;
5162 } else if (IS_PINEVIEW(dev
)) {
5163 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev
),
5166 dev_priv
->mem_freq
)) {
5167 DRM_INFO("failed to find known CxSR latency "
5168 "(found ddr%s fsb freq %d, mem freq %d), "
5170 (dev_priv
->is_ddr3
== 1) ? "3" : "2",
5171 dev_priv
->fsb_freq
, dev_priv
->mem_freq
);
5172 /* Disable CxSR and never update its watermark again */
5173 pineview_disable_cxsr(dev
);
5174 dev_priv
->display
.update_wm
= NULL
;
5176 dev_priv
->display
.update_wm
= pineview_update_wm
;
5177 dev_priv
->display
.init_clock_gating
= gen3_init_clock_gating
;
5178 } else if (IS_G4X(dev
)) {
5179 dev_priv
->display
.update_wm
= g4x_update_wm
;
5180 dev_priv
->display
.init_clock_gating
= g4x_init_clock_gating
;
5181 } else if (IS_GEN4(dev
)) {
5182 dev_priv
->display
.update_wm
= i965_update_wm
;
5183 if (IS_CRESTLINE(dev
))
5184 dev_priv
->display
.init_clock_gating
= crestline_init_clock_gating
;
5185 else if (IS_BROADWATER(dev
))
5186 dev_priv
->display
.init_clock_gating
= broadwater_init_clock_gating
;
5187 } else if (IS_GEN3(dev
)) {
5188 dev_priv
->display
.update_wm
= i9xx_update_wm
;
5189 dev_priv
->display
.get_fifo_size
= i9xx_get_fifo_size
;
5190 dev_priv
->display
.init_clock_gating
= gen3_init_clock_gating
;
5191 } else if (IS_I865G(dev
)) {
5192 dev_priv
->display
.update_wm
= i830_update_wm
;
5193 dev_priv
->display
.init_clock_gating
= i85x_init_clock_gating
;
5194 dev_priv
->display
.get_fifo_size
= i830_get_fifo_size
;
5195 } else if (IS_I85X(dev
)) {
5196 dev_priv
->display
.update_wm
= i9xx_update_wm
;
5197 dev_priv
->display
.get_fifo_size
= i85x_get_fifo_size
;
5198 dev_priv
->display
.init_clock_gating
= i85x_init_clock_gating
;
5200 dev_priv
->display
.update_wm
= i830_update_wm
;
5201 dev_priv
->display
.init_clock_gating
= i830_init_clock_gating
;
5203 dev_priv
->display
.get_fifo_size
= i845_get_fifo_size
;
5205 dev_priv
->display
.get_fifo_size
= i830_get_fifo_size
;
5209 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private
*dev_priv
)
5211 u32 gt_thread_status_mask
;
5213 if (IS_HASWELL(dev_priv
->dev
))
5214 gt_thread_status_mask
= GEN6_GT_THREAD_STATUS_CORE_MASK_HSW
;
5216 gt_thread_status_mask
= GEN6_GT_THREAD_STATUS_CORE_MASK
;
5218 /* w/a for a sporadic read returning 0 by waiting for the GT
5219 * thread to wake up.
5221 if (wait_for_atomic_us((I915_READ_NOTRACE(GEN6_GT_THREAD_STATUS_REG
) & gt_thread_status_mask
) == 0, 500))
5222 DRM_ERROR("GT thread status wait timed out\n");
5225 static void __gen6_gt_force_wake_reset(struct drm_i915_private
*dev_priv
)
5227 I915_WRITE_NOTRACE(FORCEWAKE
, 0);
5228 POSTING_READ(ECOBUS
); /* something from same cacheline, but !FORCEWAKE */
5231 static void __gen6_gt_force_wake_get(struct drm_i915_private
*dev_priv
)
5233 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK
) & 1) == 0,
5234 FORCEWAKE_ACK_TIMEOUT_MS
))
5235 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
5237 I915_WRITE_NOTRACE(FORCEWAKE
, 1);
5238 POSTING_READ(ECOBUS
); /* something from same cacheline, but !FORCEWAKE */
5240 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK
) & 1),
5241 FORCEWAKE_ACK_TIMEOUT_MS
))
5242 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
5244 /* WaRsForcewakeWaitTC0:snb */
5245 __gen6_gt_wait_for_thread_c0(dev_priv
);
5248 static void __gen6_gt_force_wake_mt_reset(struct drm_i915_private
*dev_priv
)
5250 I915_WRITE_NOTRACE(FORCEWAKE_MT
, _MASKED_BIT_DISABLE(0xffff));
5251 /* something from same cacheline, but !FORCEWAKE_MT */
5252 POSTING_READ(ECOBUS
);
5255 static void __gen6_gt_force_wake_mt_get(struct drm_i915_private
*dev_priv
)
5259 if (IS_HASWELL(dev_priv
->dev
))
5260 forcewake_ack
= FORCEWAKE_ACK_HSW
;
5262 forcewake_ack
= FORCEWAKE_MT_ACK
;
5264 if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack
) & FORCEWAKE_KERNEL
) == 0,
5265 FORCEWAKE_ACK_TIMEOUT_MS
))
5266 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
5268 I915_WRITE_NOTRACE(FORCEWAKE_MT
, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL
));
5269 /* something from same cacheline, but !FORCEWAKE_MT */
5270 POSTING_READ(ECOBUS
);
5272 if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack
) & FORCEWAKE_KERNEL
),
5273 FORCEWAKE_ACK_TIMEOUT_MS
))
5274 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
5276 /* WaRsForcewakeWaitTC0:ivb,hsw */
5277 __gen6_gt_wait_for_thread_c0(dev_priv
);
5281 * Generally this is called implicitly by the register read function. However,
5282 * if some sequence requires the GT to not power down then this function should
5283 * be called at the beginning of the sequence followed by a call to
5284 * gen6_gt_force_wake_put() at the end of the sequence.
5286 void gen6_gt_force_wake_get(struct drm_i915_private
*dev_priv
)
5288 unsigned long irqflags
;
5290 spin_lock_irqsave(&dev_priv
->gt_lock
, irqflags
);
5291 if (dev_priv
->forcewake_count
++ == 0)
5292 dev_priv
->gt
.force_wake_get(dev_priv
);
5293 spin_unlock_irqrestore(&dev_priv
->gt_lock
, irqflags
);
5296 void gen6_gt_check_fifodbg(struct drm_i915_private
*dev_priv
)
5299 gtfifodbg
= I915_READ_NOTRACE(GTFIFODBG
);
5300 if (WARN(gtfifodbg
& GT_FIFO_CPU_ERROR_MASK
,
5301 "MMIO read or write has been dropped %x\n", gtfifodbg
))
5302 I915_WRITE_NOTRACE(GTFIFODBG
, GT_FIFO_CPU_ERROR_MASK
);
5305 static void __gen6_gt_force_wake_put(struct drm_i915_private
*dev_priv
)
5307 I915_WRITE_NOTRACE(FORCEWAKE
, 0);
5308 /* something from same cacheline, but !FORCEWAKE */
5309 POSTING_READ(ECOBUS
);
5310 gen6_gt_check_fifodbg(dev_priv
);
5313 static void __gen6_gt_force_wake_mt_put(struct drm_i915_private
*dev_priv
)
5315 I915_WRITE_NOTRACE(FORCEWAKE_MT
, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL
));
5316 /* something from same cacheline, but !FORCEWAKE_MT */
5317 POSTING_READ(ECOBUS
);
5318 gen6_gt_check_fifodbg(dev_priv
);
5322 * see gen6_gt_force_wake_get()
5324 void gen6_gt_force_wake_put(struct drm_i915_private
*dev_priv
)
5326 unsigned long irqflags
;
5328 spin_lock_irqsave(&dev_priv
->gt_lock
, irqflags
);
5329 if (--dev_priv
->forcewake_count
== 0)
5330 dev_priv
->gt
.force_wake_put(dev_priv
);
5331 spin_unlock_irqrestore(&dev_priv
->gt_lock
, irqflags
);
5334 int __gen6_gt_wait_for_fifo(struct drm_i915_private
*dev_priv
)
5338 if (dev_priv
->gt_fifo_count
< GT_FIFO_NUM_RESERVED_ENTRIES
) {
5340 u32 fifo
= I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES
);
5341 while (fifo
<= GT_FIFO_NUM_RESERVED_ENTRIES
&& loop
--) {
5343 fifo
= I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES
);
5345 if (WARN_ON(loop
< 0 && fifo
<= GT_FIFO_NUM_RESERVED_ENTRIES
))
5347 dev_priv
->gt_fifo_count
= fifo
;
5349 dev_priv
->gt_fifo_count
--;
5354 static void vlv_force_wake_reset(struct drm_i915_private
*dev_priv
)
5356 I915_WRITE_NOTRACE(FORCEWAKE_VLV
, _MASKED_BIT_DISABLE(0xffff));
5357 /* something from same cacheline, but !FORCEWAKE_VLV */
5358 POSTING_READ(FORCEWAKE_ACK_VLV
);
5361 static void vlv_force_wake_get(struct drm_i915_private
*dev_priv
)
5363 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV
) & FORCEWAKE_KERNEL
) == 0,
5364 FORCEWAKE_ACK_TIMEOUT_MS
))
5365 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
5367 I915_WRITE_NOTRACE(FORCEWAKE_VLV
, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL
));
5368 I915_WRITE_NOTRACE(FORCEWAKE_MEDIA_VLV
,
5369 _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL
));
5371 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV
) & FORCEWAKE_KERNEL
),
5372 FORCEWAKE_ACK_TIMEOUT_MS
))
5373 DRM_ERROR("Timed out waiting for GT to ack forcewake request.\n");
5375 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_MEDIA_VLV
) &
5377 FORCEWAKE_ACK_TIMEOUT_MS
))
5378 DRM_ERROR("Timed out waiting for media to ack forcewake request.\n");
5380 /* WaRsForcewakeWaitTC0:vlv */
5381 __gen6_gt_wait_for_thread_c0(dev_priv
);
5384 static void vlv_force_wake_put(struct drm_i915_private
*dev_priv
)
5386 I915_WRITE_NOTRACE(FORCEWAKE_VLV
, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL
));
5387 I915_WRITE_NOTRACE(FORCEWAKE_MEDIA_VLV
,
5388 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL
));
5389 /* The below doubles as a POSTING_READ */
5390 gen6_gt_check_fifodbg(dev_priv
);
5393 void intel_gt_reset(struct drm_device
*dev
)
5395 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5397 if (IS_VALLEYVIEW(dev
)) {
5398 vlv_force_wake_reset(dev_priv
);
5399 } else if (INTEL_INFO(dev
)->gen
>= 6) {
5400 __gen6_gt_force_wake_reset(dev_priv
);
5401 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
))
5402 __gen6_gt_force_wake_mt_reset(dev_priv
);
5406 void intel_gt_init(struct drm_device
*dev
)
5408 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5410 spin_lock_init(&dev_priv
->gt_lock
);
5412 intel_gt_reset(dev
);
5414 if (IS_VALLEYVIEW(dev
)) {
5415 dev_priv
->gt
.force_wake_get
= vlv_force_wake_get
;
5416 dev_priv
->gt
.force_wake_put
= vlv_force_wake_put
;
5417 } else if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
)) {
5418 dev_priv
->gt
.force_wake_get
= __gen6_gt_force_wake_mt_get
;
5419 dev_priv
->gt
.force_wake_put
= __gen6_gt_force_wake_mt_put
;
5420 } else if (IS_GEN6(dev
)) {
5421 dev_priv
->gt
.force_wake_get
= __gen6_gt_force_wake_get
;
5422 dev_priv
->gt
.force_wake_put
= __gen6_gt_force_wake_put
;
5424 INIT_DELAYED_WORK(&dev_priv
->rps
.delayed_resume_work
,
5425 intel_gen6_powersave_work
);
5428 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u8 mbox
, u32
*val
)
5430 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
5432 if (I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) {
5433 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
5437 I915_WRITE(GEN6_PCODE_DATA
, *val
);
5438 I915_WRITE(GEN6_PCODE_MAILBOX
, GEN6_PCODE_READY
| mbox
);
5440 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) == 0,
5442 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox
);
5446 *val
= I915_READ(GEN6_PCODE_DATA
);
5447 I915_WRITE(GEN6_PCODE_DATA
, 0);
5452 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
, u8 mbox
, u32 val
)
5454 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
5456 if (I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) {
5457 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
5461 I915_WRITE(GEN6_PCODE_DATA
, val
);
5462 I915_WRITE(GEN6_PCODE_MAILBOX
, GEN6_PCODE_READY
| mbox
);
5464 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) == 0,
5466 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox
);
5470 I915_WRITE(GEN6_PCODE_DATA
, 0);
5475 int vlv_gpu_freq(int ddr_freq
, int val
)
5496 return ((val
- 0xbd) * mult
) + base
;
5499 int vlv_freq_opcode(int ddr_freq
, int val
)