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drm/i915: Add two-stage ILK-style watermark programming (v11)
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_pm.c
1 /*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28 #include <linux/cpufreq.h>
29 #include "i915_drv.h"
30 #include "intel_drv.h"
31 #include "../../../platform/x86/intel_ips.h"
32 #include <linux/module.h>
33
34 /**
35 * DOC: RC6
36 *
37 * RC6 is a special power stage which allows the GPU to enter an very
38 * low-voltage mode when idle, using down to 0V while at this stage. This
39 * stage is entered automatically when the GPU is idle when RC6 support is
40 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
41 *
42 * There are different RC6 modes available in Intel GPU, which differentiate
43 * among each other with the latency required to enter and leave RC6 and
44 * voltage consumed by the GPU in different states.
45 *
46 * The combination of the following flags define which states GPU is allowed
47 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
48 * RC6pp is deepest RC6. Their support by hardware varies according to the
49 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
50 * which brings the most power savings; deeper states save more power, but
51 * require higher latency to switch to and wake up.
52 */
53 #define INTEL_RC6_ENABLE (1<<0)
54 #define INTEL_RC6p_ENABLE (1<<1)
55 #define INTEL_RC6pp_ENABLE (1<<2)
56
57 static void bxt_init_clock_gating(struct drm_device *dev)
58 {
59 struct drm_i915_private *dev_priv = dev->dev_private;
60
61 /* WaDisableSDEUnitClockGating:bxt */
62 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
63 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
64
65 /*
66 * FIXME:
67 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
68 */
69 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
70 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
71
72 /*
73 * Wa: Backlight PWM may stop in the asserted state, causing backlight
74 * to stay fully on.
75 */
76 if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
77 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
78 PWM1_GATING_DIS | PWM2_GATING_DIS);
79 }
80
81 static void i915_pineview_get_mem_freq(struct drm_device *dev)
82 {
83 struct drm_i915_private *dev_priv = dev->dev_private;
84 u32 tmp;
85
86 tmp = I915_READ(CLKCFG);
87
88 switch (tmp & CLKCFG_FSB_MASK) {
89 case CLKCFG_FSB_533:
90 dev_priv->fsb_freq = 533; /* 133*4 */
91 break;
92 case CLKCFG_FSB_800:
93 dev_priv->fsb_freq = 800; /* 200*4 */
94 break;
95 case CLKCFG_FSB_667:
96 dev_priv->fsb_freq = 667; /* 167*4 */
97 break;
98 case CLKCFG_FSB_400:
99 dev_priv->fsb_freq = 400; /* 100*4 */
100 break;
101 }
102
103 switch (tmp & CLKCFG_MEM_MASK) {
104 case CLKCFG_MEM_533:
105 dev_priv->mem_freq = 533;
106 break;
107 case CLKCFG_MEM_667:
108 dev_priv->mem_freq = 667;
109 break;
110 case CLKCFG_MEM_800:
111 dev_priv->mem_freq = 800;
112 break;
113 }
114
115 /* detect pineview DDR3 setting */
116 tmp = I915_READ(CSHRDDR3CTL);
117 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
118 }
119
120 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
121 {
122 struct drm_i915_private *dev_priv = dev->dev_private;
123 u16 ddrpll, csipll;
124
125 ddrpll = I915_READ16(DDRMPLL1);
126 csipll = I915_READ16(CSIPLL0);
127
128 switch (ddrpll & 0xff) {
129 case 0xc:
130 dev_priv->mem_freq = 800;
131 break;
132 case 0x10:
133 dev_priv->mem_freq = 1066;
134 break;
135 case 0x14:
136 dev_priv->mem_freq = 1333;
137 break;
138 case 0x18:
139 dev_priv->mem_freq = 1600;
140 break;
141 default:
142 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
143 ddrpll & 0xff);
144 dev_priv->mem_freq = 0;
145 break;
146 }
147
148 dev_priv->ips.r_t = dev_priv->mem_freq;
149
150 switch (csipll & 0x3ff) {
151 case 0x00c:
152 dev_priv->fsb_freq = 3200;
153 break;
154 case 0x00e:
155 dev_priv->fsb_freq = 3733;
156 break;
157 case 0x010:
158 dev_priv->fsb_freq = 4266;
159 break;
160 case 0x012:
161 dev_priv->fsb_freq = 4800;
162 break;
163 case 0x014:
164 dev_priv->fsb_freq = 5333;
165 break;
166 case 0x016:
167 dev_priv->fsb_freq = 5866;
168 break;
169 case 0x018:
170 dev_priv->fsb_freq = 6400;
171 break;
172 default:
173 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
174 csipll & 0x3ff);
175 dev_priv->fsb_freq = 0;
176 break;
177 }
178
179 if (dev_priv->fsb_freq == 3200) {
180 dev_priv->ips.c_m = 0;
181 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
182 dev_priv->ips.c_m = 1;
183 } else {
184 dev_priv->ips.c_m = 2;
185 }
186 }
187
188 static const struct cxsr_latency cxsr_latency_table[] = {
189 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
190 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
191 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
192 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
193 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
194
195 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
196 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
197 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
198 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
199 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
200
201 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
202 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
203 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
204 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
205 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
206
207 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
208 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
209 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
210 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
211 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
212
213 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
214 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
215 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
216 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
217 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
218
219 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
220 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
221 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
222 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
223 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
224 };
225
226 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
227 int is_ddr3,
228 int fsb,
229 int mem)
230 {
231 const struct cxsr_latency *latency;
232 int i;
233
234 if (fsb == 0 || mem == 0)
235 return NULL;
236
237 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
238 latency = &cxsr_latency_table[i];
239 if (is_desktop == latency->is_desktop &&
240 is_ddr3 == latency->is_ddr3 &&
241 fsb == latency->fsb_freq && mem == latency->mem_freq)
242 return latency;
243 }
244
245 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
246
247 return NULL;
248 }
249
250 static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
251 {
252 u32 val;
253
254 mutex_lock(&dev_priv->rps.hw_lock);
255
256 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
257 if (enable)
258 val &= ~FORCE_DDR_HIGH_FREQ;
259 else
260 val |= FORCE_DDR_HIGH_FREQ;
261 val &= ~FORCE_DDR_LOW_FREQ;
262 val |= FORCE_DDR_FREQ_REQ_ACK;
263 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
264
265 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
266 FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
267 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
268
269 mutex_unlock(&dev_priv->rps.hw_lock);
270 }
271
272 static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
273 {
274 u32 val;
275
276 mutex_lock(&dev_priv->rps.hw_lock);
277
278 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
279 if (enable)
280 val |= DSP_MAXFIFO_PM5_ENABLE;
281 else
282 val &= ~DSP_MAXFIFO_PM5_ENABLE;
283 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
284
285 mutex_unlock(&dev_priv->rps.hw_lock);
286 }
287
288 #define FW_WM(value, plane) \
289 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
290
291 void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
292 {
293 struct drm_device *dev = dev_priv->dev;
294 u32 val;
295
296 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
297 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
298 POSTING_READ(FW_BLC_SELF_VLV);
299 dev_priv->wm.vlv.cxsr = enable;
300 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
301 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
302 POSTING_READ(FW_BLC_SELF);
303 } else if (IS_PINEVIEW(dev)) {
304 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
305 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
306 I915_WRITE(DSPFW3, val);
307 POSTING_READ(DSPFW3);
308 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
309 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
310 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
311 I915_WRITE(FW_BLC_SELF, val);
312 POSTING_READ(FW_BLC_SELF);
313 } else if (IS_I915GM(dev)) {
314 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
315 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
316 I915_WRITE(INSTPM, val);
317 POSTING_READ(INSTPM);
318 } else {
319 return;
320 }
321
322 DRM_DEBUG_KMS("memory self-refresh is %s\n",
323 enable ? "enabled" : "disabled");
324 }
325
326
327 /*
328 * Latency for FIFO fetches is dependent on several factors:
329 * - memory configuration (speed, channels)
330 * - chipset
331 * - current MCH state
332 * It can be fairly high in some situations, so here we assume a fairly
333 * pessimal value. It's a tradeoff between extra memory fetches (if we
334 * set this value too high, the FIFO will fetch frequently to stay full)
335 * and power consumption (set it too low to save power and we might see
336 * FIFO underruns and display "flicker").
337 *
338 * A value of 5us seems to be a good balance; safe for very low end
339 * platforms but not overly aggressive on lower latency configs.
340 */
341 static const int pessimal_latency_ns = 5000;
342
343 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
344 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
345
346 static int vlv_get_fifo_size(struct drm_device *dev,
347 enum pipe pipe, int plane)
348 {
349 struct drm_i915_private *dev_priv = dev->dev_private;
350 int sprite0_start, sprite1_start, size;
351
352 switch (pipe) {
353 uint32_t dsparb, dsparb2, dsparb3;
354 case PIPE_A:
355 dsparb = I915_READ(DSPARB);
356 dsparb2 = I915_READ(DSPARB2);
357 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
358 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
359 break;
360 case PIPE_B:
361 dsparb = I915_READ(DSPARB);
362 dsparb2 = I915_READ(DSPARB2);
363 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
364 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
365 break;
366 case PIPE_C:
367 dsparb2 = I915_READ(DSPARB2);
368 dsparb3 = I915_READ(DSPARB3);
369 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
370 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
371 break;
372 default:
373 return 0;
374 }
375
376 switch (plane) {
377 case 0:
378 size = sprite0_start;
379 break;
380 case 1:
381 size = sprite1_start - sprite0_start;
382 break;
383 case 2:
384 size = 512 - 1 - sprite1_start;
385 break;
386 default:
387 return 0;
388 }
389
390 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
391 pipe_name(pipe), plane == 0 ? "primary" : "sprite",
392 plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
393 size);
394
395 return size;
396 }
397
398 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
399 {
400 struct drm_i915_private *dev_priv = dev->dev_private;
401 uint32_t dsparb = I915_READ(DSPARB);
402 int size;
403
404 size = dsparb & 0x7f;
405 if (plane)
406 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
407
408 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
409 plane ? "B" : "A", size);
410
411 return size;
412 }
413
414 static int i830_get_fifo_size(struct drm_device *dev, int plane)
415 {
416 struct drm_i915_private *dev_priv = dev->dev_private;
417 uint32_t dsparb = I915_READ(DSPARB);
418 int size;
419
420 size = dsparb & 0x1ff;
421 if (plane)
422 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
423 size >>= 1; /* Convert to cachelines */
424
425 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
426 plane ? "B" : "A", size);
427
428 return size;
429 }
430
431 static int i845_get_fifo_size(struct drm_device *dev, int plane)
432 {
433 struct drm_i915_private *dev_priv = dev->dev_private;
434 uint32_t dsparb = I915_READ(DSPARB);
435 int size;
436
437 size = dsparb & 0x7f;
438 size >>= 2; /* Convert to cachelines */
439
440 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
441 plane ? "B" : "A",
442 size);
443
444 return size;
445 }
446
447 /* Pineview has different values for various configs */
448 static const struct intel_watermark_params pineview_display_wm = {
449 .fifo_size = PINEVIEW_DISPLAY_FIFO,
450 .max_wm = PINEVIEW_MAX_WM,
451 .default_wm = PINEVIEW_DFT_WM,
452 .guard_size = PINEVIEW_GUARD_WM,
453 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
454 };
455 static const struct intel_watermark_params pineview_display_hplloff_wm = {
456 .fifo_size = PINEVIEW_DISPLAY_FIFO,
457 .max_wm = PINEVIEW_MAX_WM,
458 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
459 .guard_size = PINEVIEW_GUARD_WM,
460 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
461 };
462 static const struct intel_watermark_params pineview_cursor_wm = {
463 .fifo_size = PINEVIEW_CURSOR_FIFO,
464 .max_wm = PINEVIEW_CURSOR_MAX_WM,
465 .default_wm = PINEVIEW_CURSOR_DFT_WM,
466 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
467 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
468 };
469 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
470 .fifo_size = PINEVIEW_CURSOR_FIFO,
471 .max_wm = PINEVIEW_CURSOR_MAX_WM,
472 .default_wm = PINEVIEW_CURSOR_DFT_WM,
473 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
474 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
475 };
476 static const struct intel_watermark_params g4x_wm_info = {
477 .fifo_size = G4X_FIFO_SIZE,
478 .max_wm = G4X_MAX_WM,
479 .default_wm = G4X_MAX_WM,
480 .guard_size = 2,
481 .cacheline_size = G4X_FIFO_LINE_SIZE,
482 };
483 static const struct intel_watermark_params g4x_cursor_wm_info = {
484 .fifo_size = I965_CURSOR_FIFO,
485 .max_wm = I965_CURSOR_MAX_WM,
486 .default_wm = I965_CURSOR_DFT_WM,
487 .guard_size = 2,
488 .cacheline_size = G4X_FIFO_LINE_SIZE,
489 };
490 static const struct intel_watermark_params valleyview_wm_info = {
491 .fifo_size = VALLEYVIEW_FIFO_SIZE,
492 .max_wm = VALLEYVIEW_MAX_WM,
493 .default_wm = VALLEYVIEW_MAX_WM,
494 .guard_size = 2,
495 .cacheline_size = G4X_FIFO_LINE_SIZE,
496 };
497 static const struct intel_watermark_params valleyview_cursor_wm_info = {
498 .fifo_size = I965_CURSOR_FIFO,
499 .max_wm = VALLEYVIEW_CURSOR_MAX_WM,
500 .default_wm = I965_CURSOR_DFT_WM,
501 .guard_size = 2,
502 .cacheline_size = G4X_FIFO_LINE_SIZE,
503 };
504 static const struct intel_watermark_params i965_cursor_wm_info = {
505 .fifo_size = I965_CURSOR_FIFO,
506 .max_wm = I965_CURSOR_MAX_WM,
507 .default_wm = I965_CURSOR_DFT_WM,
508 .guard_size = 2,
509 .cacheline_size = I915_FIFO_LINE_SIZE,
510 };
511 static const struct intel_watermark_params i945_wm_info = {
512 .fifo_size = I945_FIFO_SIZE,
513 .max_wm = I915_MAX_WM,
514 .default_wm = 1,
515 .guard_size = 2,
516 .cacheline_size = I915_FIFO_LINE_SIZE,
517 };
518 static const struct intel_watermark_params i915_wm_info = {
519 .fifo_size = I915_FIFO_SIZE,
520 .max_wm = I915_MAX_WM,
521 .default_wm = 1,
522 .guard_size = 2,
523 .cacheline_size = I915_FIFO_LINE_SIZE,
524 };
525 static const struct intel_watermark_params i830_a_wm_info = {
526 .fifo_size = I855GM_FIFO_SIZE,
527 .max_wm = I915_MAX_WM,
528 .default_wm = 1,
529 .guard_size = 2,
530 .cacheline_size = I830_FIFO_LINE_SIZE,
531 };
532 static const struct intel_watermark_params i830_bc_wm_info = {
533 .fifo_size = I855GM_FIFO_SIZE,
534 .max_wm = I915_MAX_WM/2,
535 .default_wm = 1,
536 .guard_size = 2,
537 .cacheline_size = I830_FIFO_LINE_SIZE,
538 };
539 static const struct intel_watermark_params i845_wm_info = {
540 .fifo_size = I830_FIFO_SIZE,
541 .max_wm = I915_MAX_WM,
542 .default_wm = 1,
543 .guard_size = 2,
544 .cacheline_size = I830_FIFO_LINE_SIZE,
545 };
546
547 /**
548 * intel_calculate_wm - calculate watermark level
549 * @clock_in_khz: pixel clock
550 * @wm: chip FIFO params
551 * @cpp: bytes per pixel
552 * @latency_ns: memory latency for the platform
553 *
554 * Calculate the watermark level (the level at which the display plane will
555 * start fetching from memory again). Each chip has a different display
556 * FIFO size and allocation, so the caller needs to figure that out and pass
557 * in the correct intel_watermark_params structure.
558 *
559 * As the pixel clock runs, the FIFO will be drained at a rate that depends
560 * on the pixel size. When it reaches the watermark level, it'll start
561 * fetching FIFO line sized based chunks from memory until the FIFO fills
562 * past the watermark point. If the FIFO drains completely, a FIFO underrun
563 * will occur, and a display engine hang could result.
564 */
565 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
566 const struct intel_watermark_params *wm,
567 int fifo_size, int cpp,
568 unsigned long latency_ns)
569 {
570 long entries_required, wm_size;
571
572 /*
573 * Note: we need to make sure we don't overflow for various clock &
574 * latency values.
575 * clocks go from a few thousand to several hundred thousand.
576 * latency is usually a few thousand
577 */
578 entries_required = ((clock_in_khz / 1000) * cpp * latency_ns) /
579 1000;
580 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
581
582 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
583
584 wm_size = fifo_size - (entries_required + wm->guard_size);
585
586 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
587
588 /* Don't promote wm_size to unsigned... */
589 if (wm_size > (long)wm->max_wm)
590 wm_size = wm->max_wm;
591 if (wm_size <= 0)
592 wm_size = wm->default_wm;
593
594 /*
595 * Bspec seems to indicate that the value shouldn't be lower than
596 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
597 * Lets go for 8 which is the burst size since certain platforms
598 * already use a hardcoded 8 (which is what the spec says should be
599 * done).
600 */
601 if (wm_size <= 8)
602 wm_size = 8;
603
604 return wm_size;
605 }
606
607 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
608 {
609 struct drm_crtc *crtc, *enabled = NULL;
610
611 for_each_crtc(dev, crtc) {
612 if (intel_crtc_active(crtc)) {
613 if (enabled)
614 return NULL;
615 enabled = crtc;
616 }
617 }
618
619 return enabled;
620 }
621
622 static void pineview_update_wm(struct drm_crtc *unused_crtc)
623 {
624 struct drm_device *dev = unused_crtc->dev;
625 struct drm_i915_private *dev_priv = dev->dev_private;
626 struct drm_crtc *crtc;
627 const struct cxsr_latency *latency;
628 u32 reg;
629 unsigned long wm;
630
631 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
632 dev_priv->fsb_freq, dev_priv->mem_freq);
633 if (!latency) {
634 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
635 intel_set_memory_cxsr(dev_priv, false);
636 return;
637 }
638
639 crtc = single_enabled_crtc(dev);
640 if (crtc) {
641 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
642 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
643 int clock = adjusted_mode->crtc_clock;
644
645 /* Display SR */
646 wm = intel_calculate_wm(clock, &pineview_display_wm,
647 pineview_display_wm.fifo_size,
648 cpp, latency->display_sr);
649 reg = I915_READ(DSPFW1);
650 reg &= ~DSPFW_SR_MASK;
651 reg |= FW_WM(wm, SR);
652 I915_WRITE(DSPFW1, reg);
653 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
654
655 /* cursor SR */
656 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
657 pineview_display_wm.fifo_size,
658 cpp, latency->cursor_sr);
659 reg = I915_READ(DSPFW3);
660 reg &= ~DSPFW_CURSOR_SR_MASK;
661 reg |= FW_WM(wm, CURSOR_SR);
662 I915_WRITE(DSPFW3, reg);
663
664 /* Display HPLL off SR */
665 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
666 pineview_display_hplloff_wm.fifo_size,
667 cpp, latency->display_hpll_disable);
668 reg = I915_READ(DSPFW3);
669 reg &= ~DSPFW_HPLL_SR_MASK;
670 reg |= FW_WM(wm, HPLL_SR);
671 I915_WRITE(DSPFW3, reg);
672
673 /* cursor HPLL off SR */
674 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
675 pineview_display_hplloff_wm.fifo_size,
676 cpp, latency->cursor_hpll_disable);
677 reg = I915_READ(DSPFW3);
678 reg &= ~DSPFW_HPLL_CURSOR_MASK;
679 reg |= FW_WM(wm, HPLL_CURSOR);
680 I915_WRITE(DSPFW3, reg);
681 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
682
683 intel_set_memory_cxsr(dev_priv, true);
684 } else {
685 intel_set_memory_cxsr(dev_priv, false);
686 }
687 }
688
689 static bool g4x_compute_wm0(struct drm_device *dev,
690 int plane,
691 const struct intel_watermark_params *display,
692 int display_latency_ns,
693 const struct intel_watermark_params *cursor,
694 int cursor_latency_ns,
695 int *plane_wm,
696 int *cursor_wm)
697 {
698 struct drm_crtc *crtc;
699 const struct drm_display_mode *adjusted_mode;
700 int htotal, hdisplay, clock, cpp;
701 int line_time_us, line_count;
702 int entries, tlb_miss;
703
704 crtc = intel_get_crtc_for_plane(dev, plane);
705 if (!intel_crtc_active(crtc)) {
706 *cursor_wm = cursor->guard_size;
707 *plane_wm = display->guard_size;
708 return false;
709 }
710
711 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
712 clock = adjusted_mode->crtc_clock;
713 htotal = adjusted_mode->crtc_htotal;
714 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
715 cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
716
717 /* Use the small buffer method to calculate plane watermark */
718 entries = ((clock * cpp / 1000) * display_latency_ns) / 1000;
719 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
720 if (tlb_miss > 0)
721 entries += tlb_miss;
722 entries = DIV_ROUND_UP(entries, display->cacheline_size);
723 *plane_wm = entries + display->guard_size;
724 if (*plane_wm > (int)display->max_wm)
725 *plane_wm = display->max_wm;
726
727 /* Use the large buffer method to calculate cursor watermark */
728 line_time_us = max(htotal * 1000 / clock, 1);
729 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
730 entries = line_count * crtc->cursor->state->crtc_w * cpp;
731 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
732 if (tlb_miss > 0)
733 entries += tlb_miss;
734 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
735 *cursor_wm = entries + cursor->guard_size;
736 if (*cursor_wm > (int)cursor->max_wm)
737 *cursor_wm = (int)cursor->max_wm;
738
739 return true;
740 }
741
742 /*
743 * Check the wm result.
744 *
745 * If any calculated watermark values is larger than the maximum value that
746 * can be programmed into the associated watermark register, that watermark
747 * must be disabled.
748 */
749 static bool g4x_check_srwm(struct drm_device *dev,
750 int display_wm, int cursor_wm,
751 const struct intel_watermark_params *display,
752 const struct intel_watermark_params *cursor)
753 {
754 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
755 display_wm, cursor_wm);
756
757 if (display_wm > display->max_wm) {
758 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
759 display_wm, display->max_wm);
760 return false;
761 }
762
763 if (cursor_wm > cursor->max_wm) {
764 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
765 cursor_wm, cursor->max_wm);
766 return false;
767 }
768
769 if (!(display_wm || cursor_wm)) {
770 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
771 return false;
772 }
773
774 return true;
775 }
776
777 static bool g4x_compute_srwm(struct drm_device *dev,
778 int plane,
779 int latency_ns,
780 const struct intel_watermark_params *display,
781 const struct intel_watermark_params *cursor,
782 int *display_wm, int *cursor_wm)
783 {
784 struct drm_crtc *crtc;
785 const struct drm_display_mode *adjusted_mode;
786 int hdisplay, htotal, cpp, clock;
787 unsigned long line_time_us;
788 int line_count, line_size;
789 int small, large;
790 int entries;
791
792 if (!latency_ns) {
793 *display_wm = *cursor_wm = 0;
794 return false;
795 }
796
797 crtc = intel_get_crtc_for_plane(dev, plane);
798 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
799 clock = adjusted_mode->crtc_clock;
800 htotal = adjusted_mode->crtc_htotal;
801 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
802 cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
803
804 line_time_us = max(htotal * 1000 / clock, 1);
805 line_count = (latency_ns / line_time_us + 1000) / 1000;
806 line_size = hdisplay * cpp;
807
808 /* Use the minimum of the small and large buffer method for primary */
809 small = ((clock * cpp / 1000) * latency_ns) / 1000;
810 large = line_count * line_size;
811
812 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
813 *display_wm = entries + display->guard_size;
814
815 /* calculate the self-refresh watermark for display cursor */
816 entries = line_count * cpp * crtc->cursor->state->crtc_w;
817 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
818 *cursor_wm = entries + cursor->guard_size;
819
820 return g4x_check_srwm(dev,
821 *display_wm, *cursor_wm,
822 display, cursor);
823 }
824
825 #define FW_WM_VLV(value, plane) \
826 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
827
828 static void vlv_write_wm_values(struct intel_crtc *crtc,
829 const struct vlv_wm_values *wm)
830 {
831 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
832 enum pipe pipe = crtc->pipe;
833
834 I915_WRITE(VLV_DDL(pipe),
835 (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
836 (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
837 (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
838 (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
839
840 I915_WRITE(DSPFW1,
841 FW_WM(wm->sr.plane, SR) |
842 FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
843 FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
844 FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
845 I915_WRITE(DSPFW2,
846 FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
847 FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
848 FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
849 I915_WRITE(DSPFW3,
850 FW_WM(wm->sr.cursor, CURSOR_SR));
851
852 if (IS_CHERRYVIEW(dev_priv)) {
853 I915_WRITE(DSPFW7_CHV,
854 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
855 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
856 I915_WRITE(DSPFW8_CHV,
857 FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
858 FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
859 I915_WRITE(DSPFW9_CHV,
860 FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
861 FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
862 I915_WRITE(DSPHOWM,
863 FW_WM(wm->sr.plane >> 9, SR_HI) |
864 FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
865 FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
866 FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
867 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
868 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
869 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
870 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
871 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
872 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
873 } else {
874 I915_WRITE(DSPFW7,
875 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
876 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
877 I915_WRITE(DSPHOWM,
878 FW_WM(wm->sr.plane >> 9, SR_HI) |
879 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
880 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
881 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
882 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
883 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
884 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
885 }
886
887 /* zero (unused) WM1 watermarks */
888 I915_WRITE(DSPFW4, 0);
889 I915_WRITE(DSPFW5, 0);
890 I915_WRITE(DSPFW6, 0);
891 I915_WRITE(DSPHOWM1, 0);
892
893 POSTING_READ(DSPFW1);
894 }
895
896 #undef FW_WM_VLV
897
898 enum vlv_wm_level {
899 VLV_WM_LEVEL_PM2,
900 VLV_WM_LEVEL_PM5,
901 VLV_WM_LEVEL_DDR_DVFS,
902 };
903
904 /* latency must be in 0.1us units. */
905 static unsigned int vlv_wm_method2(unsigned int pixel_rate,
906 unsigned int pipe_htotal,
907 unsigned int horiz_pixels,
908 unsigned int cpp,
909 unsigned int latency)
910 {
911 unsigned int ret;
912
913 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
914 ret = (ret + 1) * horiz_pixels * cpp;
915 ret = DIV_ROUND_UP(ret, 64);
916
917 return ret;
918 }
919
920 static void vlv_setup_wm_latency(struct drm_device *dev)
921 {
922 struct drm_i915_private *dev_priv = dev->dev_private;
923
924 /* all latencies in usec */
925 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
926
927 dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
928
929 if (IS_CHERRYVIEW(dev_priv)) {
930 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
931 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
932
933 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
934 }
935 }
936
937 static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
938 struct intel_crtc *crtc,
939 const struct intel_plane_state *state,
940 int level)
941 {
942 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
943 int clock, htotal, cpp, width, wm;
944
945 if (dev_priv->wm.pri_latency[level] == 0)
946 return USHRT_MAX;
947
948 if (!state->visible)
949 return 0;
950
951 cpp = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
952 clock = crtc->config->base.adjusted_mode.crtc_clock;
953 htotal = crtc->config->base.adjusted_mode.crtc_htotal;
954 width = crtc->config->pipe_src_w;
955 if (WARN_ON(htotal == 0))
956 htotal = 1;
957
958 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
959 /*
960 * FIXME the formula gives values that are
961 * too big for the cursor FIFO, and hence we
962 * would never be able to use cursors. For
963 * now just hardcode the watermark.
964 */
965 wm = 63;
966 } else {
967 wm = vlv_wm_method2(clock, htotal, width, cpp,
968 dev_priv->wm.pri_latency[level] * 10);
969 }
970
971 return min_t(int, wm, USHRT_MAX);
972 }
973
974 static void vlv_compute_fifo(struct intel_crtc *crtc)
975 {
976 struct drm_device *dev = crtc->base.dev;
977 struct vlv_wm_state *wm_state = &crtc->wm_state;
978 struct intel_plane *plane;
979 unsigned int total_rate = 0;
980 const int fifo_size = 512 - 1;
981 int fifo_extra, fifo_left = fifo_size;
982
983 for_each_intel_plane_on_crtc(dev, crtc, plane) {
984 struct intel_plane_state *state =
985 to_intel_plane_state(plane->base.state);
986
987 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
988 continue;
989
990 if (state->visible) {
991 wm_state->num_active_planes++;
992 total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
993 }
994 }
995
996 for_each_intel_plane_on_crtc(dev, crtc, plane) {
997 struct intel_plane_state *state =
998 to_intel_plane_state(plane->base.state);
999 unsigned int rate;
1000
1001 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1002 plane->wm.fifo_size = 63;
1003 continue;
1004 }
1005
1006 if (!state->visible) {
1007 plane->wm.fifo_size = 0;
1008 continue;
1009 }
1010
1011 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1012 plane->wm.fifo_size = fifo_size * rate / total_rate;
1013 fifo_left -= plane->wm.fifo_size;
1014 }
1015
1016 fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1017
1018 /* spread the remainder evenly */
1019 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1020 int plane_extra;
1021
1022 if (fifo_left == 0)
1023 break;
1024
1025 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1026 continue;
1027
1028 /* give it all to the first plane if none are active */
1029 if (plane->wm.fifo_size == 0 &&
1030 wm_state->num_active_planes)
1031 continue;
1032
1033 plane_extra = min(fifo_extra, fifo_left);
1034 plane->wm.fifo_size += plane_extra;
1035 fifo_left -= plane_extra;
1036 }
1037
1038 WARN_ON(fifo_left != 0);
1039 }
1040
1041 static void vlv_invert_wms(struct intel_crtc *crtc)
1042 {
1043 struct vlv_wm_state *wm_state = &crtc->wm_state;
1044 int level;
1045
1046 for (level = 0; level < wm_state->num_levels; level++) {
1047 struct drm_device *dev = crtc->base.dev;
1048 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1049 struct intel_plane *plane;
1050
1051 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1052 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1053
1054 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1055 switch (plane->base.type) {
1056 int sprite;
1057 case DRM_PLANE_TYPE_CURSOR:
1058 wm_state->wm[level].cursor = plane->wm.fifo_size -
1059 wm_state->wm[level].cursor;
1060 break;
1061 case DRM_PLANE_TYPE_PRIMARY:
1062 wm_state->wm[level].primary = plane->wm.fifo_size -
1063 wm_state->wm[level].primary;
1064 break;
1065 case DRM_PLANE_TYPE_OVERLAY:
1066 sprite = plane->plane;
1067 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1068 wm_state->wm[level].sprite[sprite];
1069 break;
1070 }
1071 }
1072 }
1073 }
1074
1075 static void vlv_compute_wm(struct intel_crtc *crtc)
1076 {
1077 struct drm_device *dev = crtc->base.dev;
1078 struct vlv_wm_state *wm_state = &crtc->wm_state;
1079 struct intel_plane *plane;
1080 int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1081 int level;
1082
1083 memset(wm_state, 0, sizeof(*wm_state));
1084
1085 wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
1086 wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
1087
1088 wm_state->num_active_planes = 0;
1089
1090 vlv_compute_fifo(crtc);
1091
1092 if (wm_state->num_active_planes != 1)
1093 wm_state->cxsr = false;
1094
1095 if (wm_state->cxsr) {
1096 for (level = 0; level < wm_state->num_levels; level++) {
1097 wm_state->sr[level].plane = sr_fifo_size;
1098 wm_state->sr[level].cursor = 63;
1099 }
1100 }
1101
1102 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1103 struct intel_plane_state *state =
1104 to_intel_plane_state(plane->base.state);
1105
1106 if (!state->visible)
1107 continue;
1108
1109 /* normal watermarks */
1110 for (level = 0; level < wm_state->num_levels; level++) {
1111 int wm = vlv_compute_wm_level(plane, crtc, state, level);
1112 int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1113
1114 /* hack */
1115 if (WARN_ON(level == 0 && wm > max_wm))
1116 wm = max_wm;
1117
1118 if (wm > plane->wm.fifo_size)
1119 break;
1120
1121 switch (plane->base.type) {
1122 int sprite;
1123 case DRM_PLANE_TYPE_CURSOR:
1124 wm_state->wm[level].cursor = wm;
1125 break;
1126 case DRM_PLANE_TYPE_PRIMARY:
1127 wm_state->wm[level].primary = wm;
1128 break;
1129 case DRM_PLANE_TYPE_OVERLAY:
1130 sprite = plane->plane;
1131 wm_state->wm[level].sprite[sprite] = wm;
1132 break;
1133 }
1134 }
1135
1136 wm_state->num_levels = level;
1137
1138 if (!wm_state->cxsr)
1139 continue;
1140
1141 /* maxfifo watermarks */
1142 switch (plane->base.type) {
1143 int sprite, level;
1144 case DRM_PLANE_TYPE_CURSOR:
1145 for (level = 0; level < wm_state->num_levels; level++)
1146 wm_state->sr[level].cursor =
1147 wm_state->wm[level].cursor;
1148 break;
1149 case DRM_PLANE_TYPE_PRIMARY:
1150 for (level = 0; level < wm_state->num_levels; level++)
1151 wm_state->sr[level].plane =
1152 min(wm_state->sr[level].plane,
1153 wm_state->wm[level].primary);
1154 break;
1155 case DRM_PLANE_TYPE_OVERLAY:
1156 sprite = plane->plane;
1157 for (level = 0; level < wm_state->num_levels; level++)
1158 wm_state->sr[level].plane =
1159 min(wm_state->sr[level].plane,
1160 wm_state->wm[level].sprite[sprite]);
1161 break;
1162 }
1163 }
1164
1165 /* clear any (partially) filled invalid levels */
1166 for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
1167 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1168 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1169 }
1170
1171 vlv_invert_wms(crtc);
1172 }
1173
1174 #define VLV_FIFO(plane, value) \
1175 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1176
1177 static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1178 {
1179 struct drm_device *dev = crtc->base.dev;
1180 struct drm_i915_private *dev_priv = to_i915(dev);
1181 struct intel_plane *plane;
1182 int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1183
1184 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1185 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1186 WARN_ON(plane->wm.fifo_size != 63);
1187 continue;
1188 }
1189
1190 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1191 sprite0_start = plane->wm.fifo_size;
1192 else if (plane->plane == 0)
1193 sprite1_start = sprite0_start + plane->wm.fifo_size;
1194 else
1195 fifo_size = sprite1_start + plane->wm.fifo_size;
1196 }
1197
1198 WARN_ON(fifo_size != 512 - 1);
1199
1200 DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1201 pipe_name(crtc->pipe), sprite0_start,
1202 sprite1_start, fifo_size);
1203
1204 switch (crtc->pipe) {
1205 uint32_t dsparb, dsparb2, dsparb3;
1206 case PIPE_A:
1207 dsparb = I915_READ(DSPARB);
1208 dsparb2 = I915_READ(DSPARB2);
1209
1210 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1211 VLV_FIFO(SPRITEB, 0xff));
1212 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1213 VLV_FIFO(SPRITEB, sprite1_start));
1214
1215 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1216 VLV_FIFO(SPRITEB_HI, 0x1));
1217 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1218 VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1219
1220 I915_WRITE(DSPARB, dsparb);
1221 I915_WRITE(DSPARB2, dsparb2);
1222 break;
1223 case PIPE_B:
1224 dsparb = I915_READ(DSPARB);
1225 dsparb2 = I915_READ(DSPARB2);
1226
1227 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1228 VLV_FIFO(SPRITED, 0xff));
1229 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1230 VLV_FIFO(SPRITED, sprite1_start));
1231
1232 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1233 VLV_FIFO(SPRITED_HI, 0xff));
1234 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1235 VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1236
1237 I915_WRITE(DSPARB, dsparb);
1238 I915_WRITE(DSPARB2, dsparb2);
1239 break;
1240 case PIPE_C:
1241 dsparb3 = I915_READ(DSPARB3);
1242 dsparb2 = I915_READ(DSPARB2);
1243
1244 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1245 VLV_FIFO(SPRITEF, 0xff));
1246 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1247 VLV_FIFO(SPRITEF, sprite1_start));
1248
1249 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1250 VLV_FIFO(SPRITEF_HI, 0xff));
1251 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1252 VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1253
1254 I915_WRITE(DSPARB3, dsparb3);
1255 I915_WRITE(DSPARB2, dsparb2);
1256 break;
1257 default:
1258 break;
1259 }
1260 }
1261
1262 #undef VLV_FIFO
1263
1264 static void vlv_merge_wm(struct drm_device *dev,
1265 struct vlv_wm_values *wm)
1266 {
1267 struct intel_crtc *crtc;
1268 int num_active_crtcs = 0;
1269
1270 wm->level = to_i915(dev)->wm.max_level;
1271 wm->cxsr = true;
1272
1273 for_each_intel_crtc(dev, crtc) {
1274 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1275
1276 if (!crtc->active)
1277 continue;
1278
1279 if (!wm_state->cxsr)
1280 wm->cxsr = false;
1281
1282 num_active_crtcs++;
1283 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1284 }
1285
1286 if (num_active_crtcs != 1)
1287 wm->cxsr = false;
1288
1289 if (num_active_crtcs > 1)
1290 wm->level = VLV_WM_LEVEL_PM2;
1291
1292 for_each_intel_crtc(dev, crtc) {
1293 struct vlv_wm_state *wm_state = &crtc->wm_state;
1294 enum pipe pipe = crtc->pipe;
1295
1296 if (!crtc->active)
1297 continue;
1298
1299 wm->pipe[pipe] = wm_state->wm[wm->level];
1300 if (wm->cxsr)
1301 wm->sr = wm_state->sr[wm->level];
1302
1303 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1304 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1305 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1306 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1307 }
1308 }
1309
1310 static void vlv_update_wm(struct drm_crtc *crtc)
1311 {
1312 struct drm_device *dev = crtc->dev;
1313 struct drm_i915_private *dev_priv = dev->dev_private;
1314 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1315 enum pipe pipe = intel_crtc->pipe;
1316 struct vlv_wm_values wm = {};
1317
1318 vlv_compute_wm(intel_crtc);
1319 vlv_merge_wm(dev, &wm);
1320
1321 if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1322 /* FIXME should be part of crtc atomic commit */
1323 vlv_pipe_set_fifo_size(intel_crtc);
1324 return;
1325 }
1326
1327 if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1328 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1329 chv_set_memory_dvfs(dev_priv, false);
1330
1331 if (wm.level < VLV_WM_LEVEL_PM5 &&
1332 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1333 chv_set_memory_pm5(dev_priv, false);
1334
1335 if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
1336 intel_set_memory_cxsr(dev_priv, false);
1337
1338 /* FIXME should be part of crtc atomic commit */
1339 vlv_pipe_set_fifo_size(intel_crtc);
1340
1341 vlv_write_wm_values(intel_crtc, &wm);
1342
1343 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1344 "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1345 pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1346 wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1347 wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1348
1349 if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
1350 intel_set_memory_cxsr(dev_priv, true);
1351
1352 if (wm.level >= VLV_WM_LEVEL_PM5 &&
1353 dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1354 chv_set_memory_pm5(dev_priv, true);
1355
1356 if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1357 dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1358 chv_set_memory_dvfs(dev_priv, true);
1359
1360 dev_priv->wm.vlv = wm;
1361 }
1362
1363 #define single_plane_enabled(mask) is_power_of_2(mask)
1364
1365 static void g4x_update_wm(struct drm_crtc *crtc)
1366 {
1367 struct drm_device *dev = crtc->dev;
1368 static const int sr_latency_ns = 12000;
1369 struct drm_i915_private *dev_priv = dev->dev_private;
1370 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1371 int plane_sr, cursor_sr;
1372 unsigned int enabled = 0;
1373 bool cxsr_enabled;
1374
1375 if (g4x_compute_wm0(dev, PIPE_A,
1376 &g4x_wm_info, pessimal_latency_ns,
1377 &g4x_cursor_wm_info, pessimal_latency_ns,
1378 &planea_wm, &cursora_wm))
1379 enabled |= 1 << PIPE_A;
1380
1381 if (g4x_compute_wm0(dev, PIPE_B,
1382 &g4x_wm_info, pessimal_latency_ns,
1383 &g4x_cursor_wm_info, pessimal_latency_ns,
1384 &planeb_wm, &cursorb_wm))
1385 enabled |= 1 << PIPE_B;
1386
1387 if (single_plane_enabled(enabled) &&
1388 g4x_compute_srwm(dev, ffs(enabled) - 1,
1389 sr_latency_ns,
1390 &g4x_wm_info,
1391 &g4x_cursor_wm_info,
1392 &plane_sr, &cursor_sr)) {
1393 cxsr_enabled = true;
1394 } else {
1395 cxsr_enabled = false;
1396 intel_set_memory_cxsr(dev_priv, false);
1397 plane_sr = cursor_sr = 0;
1398 }
1399
1400 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1401 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1402 planea_wm, cursora_wm,
1403 planeb_wm, cursorb_wm,
1404 plane_sr, cursor_sr);
1405
1406 I915_WRITE(DSPFW1,
1407 FW_WM(plane_sr, SR) |
1408 FW_WM(cursorb_wm, CURSORB) |
1409 FW_WM(planeb_wm, PLANEB) |
1410 FW_WM(planea_wm, PLANEA));
1411 I915_WRITE(DSPFW2,
1412 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1413 FW_WM(cursora_wm, CURSORA));
1414 /* HPLL off in SR has some issues on G4x... disable it */
1415 I915_WRITE(DSPFW3,
1416 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1417 FW_WM(cursor_sr, CURSOR_SR));
1418
1419 if (cxsr_enabled)
1420 intel_set_memory_cxsr(dev_priv, true);
1421 }
1422
1423 static void i965_update_wm(struct drm_crtc *unused_crtc)
1424 {
1425 struct drm_device *dev = unused_crtc->dev;
1426 struct drm_i915_private *dev_priv = dev->dev_private;
1427 struct drm_crtc *crtc;
1428 int srwm = 1;
1429 int cursor_sr = 16;
1430 bool cxsr_enabled;
1431
1432 /* Calc sr entries for one plane configs */
1433 crtc = single_enabled_crtc(dev);
1434 if (crtc) {
1435 /* self-refresh has much higher latency */
1436 static const int sr_latency_ns = 12000;
1437 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1438 int clock = adjusted_mode->crtc_clock;
1439 int htotal = adjusted_mode->crtc_htotal;
1440 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
1441 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
1442 unsigned long line_time_us;
1443 int entries;
1444
1445 line_time_us = max(htotal * 1000 / clock, 1);
1446
1447 /* Use ns/us then divide to preserve precision */
1448 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1449 cpp * hdisplay;
1450 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1451 srwm = I965_FIFO_SIZE - entries;
1452 if (srwm < 0)
1453 srwm = 1;
1454 srwm &= 0x1ff;
1455 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1456 entries, srwm);
1457
1458 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1459 cpp * crtc->cursor->state->crtc_w;
1460 entries = DIV_ROUND_UP(entries,
1461 i965_cursor_wm_info.cacheline_size);
1462 cursor_sr = i965_cursor_wm_info.fifo_size -
1463 (entries + i965_cursor_wm_info.guard_size);
1464
1465 if (cursor_sr > i965_cursor_wm_info.max_wm)
1466 cursor_sr = i965_cursor_wm_info.max_wm;
1467
1468 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1469 "cursor %d\n", srwm, cursor_sr);
1470
1471 cxsr_enabled = true;
1472 } else {
1473 cxsr_enabled = false;
1474 /* Turn off self refresh if both pipes are enabled */
1475 intel_set_memory_cxsr(dev_priv, false);
1476 }
1477
1478 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1479 srwm);
1480
1481 /* 965 has limitations... */
1482 I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1483 FW_WM(8, CURSORB) |
1484 FW_WM(8, PLANEB) |
1485 FW_WM(8, PLANEA));
1486 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1487 FW_WM(8, PLANEC_OLD));
1488 /* update cursor SR watermark */
1489 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
1490
1491 if (cxsr_enabled)
1492 intel_set_memory_cxsr(dev_priv, true);
1493 }
1494
1495 #undef FW_WM
1496
1497 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1498 {
1499 struct drm_device *dev = unused_crtc->dev;
1500 struct drm_i915_private *dev_priv = dev->dev_private;
1501 const struct intel_watermark_params *wm_info;
1502 uint32_t fwater_lo;
1503 uint32_t fwater_hi;
1504 int cwm, srwm = 1;
1505 int fifo_size;
1506 int planea_wm, planeb_wm;
1507 struct drm_crtc *crtc, *enabled = NULL;
1508
1509 if (IS_I945GM(dev))
1510 wm_info = &i945_wm_info;
1511 else if (!IS_GEN2(dev))
1512 wm_info = &i915_wm_info;
1513 else
1514 wm_info = &i830_a_wm_info;
1515
1516 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1517 crtc = intel_get_crtc_for_plane(dev, 0);
1518 if (intel_crtc_active(crtc)) {
1519 const struct drm_display_mode *adjusted_mode;
1520 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
1521 if (IS_GEN2(dev))
1522 cpp = 4;
1523
1524 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1525 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1526 wm_info, fifo_size, cpp,
1527 pessimal_latency_ns);
1528 enabled = crtc;
1529 } else {
1530 planea_wm = fifo_size - wm_info->guard_size;
1531 if (planea_wm > (long)wm_info->max_wm)
1532 planea_wm = wm_info->max_wm;
1533 }
1534
1535 if (IS_GEN2(dev))
1536 wm_info = &i830_bc_wm_info;
1537
1538 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1539 crtc = intel_get_crtc_for_plane(dev, 1);
1540 if (intel_crtc_active(crtc)) {
1541 const struct drm_display_mode *adjusted_mode;
1542 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
1543 if (IS_GEN2(dev))
1544 cpp = 4;
1545
1546 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1547 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1548 wm_info, fifo_size, cpp,
1549 pessimal_latency_ns);
1550 if (enabled == NULL)
1551 enabled = crtc;
1552 else
1553 enabled = NULL;
1554 } else {
1555 planeb_wm = fifo_size - wm_info->guard_size;
1556 if (planeb_wm > (long)wm_info->max_wm)
1557 planeb_wm = wm_info->max_wm;
1558 }
1559
1560 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1561
1562 if (IS_I915GM(dev) && enabled) {
1563 struct drm_i915_gem_object *obj;
1564
1565 obj = intel_fb_obj(enabled->primary->state->fb);
1566
1567 /* self-refresh seems busted with untiled */
1568 if (obj->tiling_mode == I915_TILING_NONE)
1569 enabled = NULL;
1570 }
1571
1572 /*
1573 * Overlay gets an aggressive default since video jitter is bad.
1574 */
1575 cwm = 2;
1576
1577 /* Play safe and disable self-refresh before adjusting watermarks. */
1578 intel_set_memory_cxsr(dev_priv, false);
1579
1580 /* Calc sr entries for one plane configs */
1581 if (HAS_FW_BLC(dev) && enabled) {
1582 /* self-refresh has much higher latency */
1583 static const int sr_latency_ns = 6000;
1584 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode;
1585 int clock = adjusted_mode->crtc_clock;
1586 int htotal = adjusted_mode->crtc_htotal;
1587 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
1588 int cpp = drm_format_plane_cpp(enabled->primary->state->fb->pixel_format, 0);
1589 unsigned long line_time_us;
1590 int entries;
1591
1592 line_time_us = max(htotal * 1000 / clock, 1);
1593
1594 /* Use ns/us then divide to preserve precision */
1595 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1596 cpp * hdisplay;
1597 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1598 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1599 srwm = wm_info->fifo_size - entries;
1600 if (srwm < 0)
1601 srwm = 1;
1602
1603 if (IS_I945G(dev) || IS_I945GM(dev))
1604 I915_WRITE(FW_BLC_SELF,
1605 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1606 else if (IS_I915GM(dev))
1607 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1608 }
1609
1610 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1611 planea_wm, planeb_wm, cwm, srwm);
1612
1613 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1614 fwater_hi = (cwm & 0x1f);
1615
1616 /* Set request length to 8 cachelines per fetch */
1617 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1618 fwater_hi = fwater_hi | (1 << 8);
1619
1620 I915_WRITE(FW_BLC, fwater_lo);
1621 I915_WRITE(FW_BLC2, fwater_hi);
1622
1623 if (enabled)
1624 intel_set_memory_cxsr(dev_priv, true);
1625 }
1626
1627 static void i845_update_wm(struct drm_crtc *unused_crtc)
1628 {
1629 struct drm_device *dev = unused_crtc->dev;
1630 struct drm_i915_private *dev_priv = dev->dev_private;
1631 struct drm_crtc *crtc;
1632 const struct drm_display_mode *adjusted_mode;
1633 uint32_t fwater_lo;
1634 int planea_wm;
1635
1636 crtc = single_enabled_crtc(dev);
1637 if (crtc == NULL)
1638 return;
1639
1640 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1641 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1642 &i845_wm_info,
1643 dev_priv->display.get_fifo_size(dev, 0),
1644 4, pessimal_latency_ns);
1645 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1646 fwater_lo |= (3<<8) | planea_wm;
1647
1648 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1649
1650 I915_WRITE(FW_BLC, fwater_lo);
1651 }
1652
1653 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
1654 {
1655 uint32_t pixel_rate;
1656
1657 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
1658
1659 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1660 * adjust the pixel_rate here. */
1661
1662 if (pipe_config->pch_pfit.enabled) {
1663 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1664 uint32_t pfit_size = pipe_config->pch_pfit.size;
1665
1666 pipe_w = pipe_config->pipe_src_w;
1667 pipe_h = pipe_config->pipe_src_h;
1668
1669 pfit_w = (pfit_size >> 16) & 0xFFFF;
1670 pfit_h = pfit_size & 0xFFFF;
1671 if (pipe_w < pfit_w)
1672 pipe_w = pfit_w;
1673 if (pipe_h < pfit_h)
1674 pipe_h = pfit_h;
1675
1676 if (WARN_ON(!pfit_w || !pfit_h))
1677 return pixel_rate;
1678
1679 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1680 pfit_w * pfit_h);
1681 }
1682
1683 return pixel_rate;
1684 }
1685
1686 /* latency must be in 0.1us units. */
1687 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
1688 {
1689 uint64_t ret;
1690
1691 if (WARN(latency == 0, "Latency value missing\n"))
1692 return UINT_MAX;
1693
1694 ret = (uint64_t) pixel_rate * cpp * latency;
1695 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1696
1697 return ret;
1698 }
1699
1700 /* latency must be in 0.1us units. */
1701 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1702 uint32_t horiz_pixels, uint8_t cpp,
1703 uint32_t latency)
1704 {
1705 uint32_t ret;
1706
1707 if (WARN(latency == 0, "Latency value missing\n"))
1708 return UINT_MAX;
1709 if (WARN_ON(!pipe_htotal))
1710 return UINT_MAX;
1711
1712 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1713 ret = (ret + 1) * horiz_pixels * cpp;
1714 ret = DIV_ROUND_UP(ret, 64) + 2;
1715 return ret;
1716 }
1717
1718 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1719 uint8_t cpp)
1720 {
1721 /*
1722 * Neither of these should be possible since this function shouldn't be
1723 * called if the CRTC is off or the plane is invisible. But let's be
1724 * extra paranoid to avoid a potential divide-by-zero if we screw up
1725 * elsewhere in the driver.
1726 */
1727 if (WARN_ON(!cpp))
1728 return 0;
1729 if (WARN_ON(!horiz_pixels))
1730 return 0;
1731
1732 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
1733 }
1734
1735 struct ilk_wm_maximums {
1736 uint16_t pri;
1737 uint16_t spr;
1738 uint16_t cur;
1739 uint16_t fbc;
1740 };
1741
1742 /*
1743 * For both WM_PIPE and WM_LP.
1744 * mem_value must be in 0.1us units.
1745 */
1746 static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
1747 const struct intel_plane_state *pstate,
1748 uint32_t mem_value,
1749 bool is_lp)
1750 {
1751 int cpp = pstate->base.fb ?
1752 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1753 uint32_t method1, method2;
1754
1755 if (!cstate->base.active || !pstate->visible)
1756 return 0;
1757
1758 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
1759
1760 if (!is_lp)
1761 return method1;
1762
1763 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1764 cstate->base.adjusted_mode.crtc_htotal,
1765 drm_rect_width(&pstate->dst),
1766 cpp, mem_value);
1767
1768 return min(method1, method2);
1769 }
1770
1771 /*
1772 * For both WM_PIPE and WM_LP.
1773 * mem_value must be in 0.1us units.
1774 */
1775 static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
1776 const struct intel_plane_state *pstate,
1777 uint32_t mem_value)
1778 {
1779 int cpp = pstate->base.fb ?
1780 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1781 uint32_t method1, method2;
1782
1783 if (!cstate->base.active || !pstate->visible)
1784 return 0;
1785
1786 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
1787 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1788 cstate->base.adjusted_mode.crtc_htotal,
1789 drm_rect_width(&pstate->dst),
1790 cpp, mem_value);
1791 return min(method1, method2);
1792 }
1793
1794 /*
1795 * For both WM_PIPE and WM_LP.
1796 * mem_value must be in 0.1us units.
1797 */
1798 static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
1799 const struct intel_plane_state *pstate,
1800 uint32_t mem_value)
1801 {
1802 /*
1803 * We treat the cursor plane as always-on for the purposes of watermark
1804 * calculation. Until we have two-stage watermark programming merged,
1805 * this is necessary to avoid flickering.
1806 */
1807 int cpp = 4;
1808 int width = pstate->visible ? pstate->base.crtc_w : 64;
1809
1810 if (!cstate->base.active)
1811 return 0;
1812
1813 return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1814 cstate->base.adjusted_mode.crtc_htotal,
1815 width, cpp, mem_value);
1816 }
1817
1818 /* Only for WM_LP. */
1819 static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
1820 const struct intel_plane_state *pstate,
1821 uint32_t pri_val)
1822 {
1823 int cpp = pstate->base.fb ?
1824 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1825
1826 if (!cstate->base.active || !pstate->visible)
1827 return 0;
1828
1829 return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->dst), cpp);
1830 }
1831
1832 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1833 {
1834 if (INTEL_INFO(dev)->gen >= 8)
1835 return 3072;
1836 else if (INTEL_INFO(dev)->gen >= 7)
1837 return 768;
1838 else
1839 return 512;
1840 }
1841
1842 static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1843 int level, bool is_sprite)
1844 {
1845 if (INTEL_INFO(dev)->gen >= 8)
1846 /* BDW primary/sprite plane watermarks */
1847 return level == 0 ? 255 : 2047;
1848 else if (INTEL_INFO(dev)->gen >= 7)
1849 /* IVB/HSW primary/sprite plane watermarks */
1850 return level == 0 ? 127 : 1023;
1851 else if (!is_sprite)
1852 /* ILK/SNB primary plane watermarks */
1853 return level == 0 ? 127 : 511;
1854 else
1855 /* ILK/SNB sprite plane watermarks */
1856 return level == 0 ? 63 : 255;
1857 }
1858
1859 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1860 int level)
1861 {
1862 if (INTEL_INFO(dev)->gen >= 7)
1863 return level == 0 ? 63 : 255;
1864 else
1865 return level == 0 ? 31 : 63;
1866 }
1867
1868 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1869 {
1870 if (INTEL_INFO(dev)->gen >= 8)
1871 return 31;
1872 else
1873 return 15;
1874 }
1875
1876 /* Calculate the maximum primary/sprite plane watermark */
1877 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1878 int level,
1879 const struct intel_wm_config *config,
1880 enum intel_ddb_partitioning ddb_partitioning,
1881 bool is_sprite)
1882 {
1883 unsigned int fifo_size = ilk_display_fifo_size(dev);
1884
1885 /* if sprites aren't enabled, sprites get nothing */
1886 if (is_sprite && !config->sprites_enabled)
1887 return 0;
1888
1889 /* HSW allows LP1+ watermarks even with multiple pipes */
1890 if (level == 0 || config->num_pipes_active > 1) {
1891 fifo_size /= INTEL_INFO(dev)->num_pipes;
1892
1893 /*
1894 * For some reason the non self refresh
1895 * FIFO size is only half of the self
1896 * refresh FIFO size on ILK/SNB.
1897 */
1898 if (INTEL_INFO(dev)->gen <= 6)
1899 fifo_size /= 2;
1900 }
1901
1902 if (config->sprites_enabled) {
1903 /* level 0 is always calculated with 1:1 split */
1904 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1905 if (is_sprite)
1906 fifo_size *= 5;
1907 fifo_size /= 6;
1908 } else {
1909 fifo_size /= 2;
1910 }
1911 }
1912
1913 /* clamp to max that the registers can hold */
1914 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
1915 }
1916
1917 /* Calculate the maximum cursor plane watermark */
1918 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
1919 int level,
1920 const struct intel_wm_config *config)
1921 {
1922 /* HSW LP1+ watermarks w/ multiple pipes */
1923 if (level > 0 && config->num_pipes_active > 1)
1924 return 64;
1925
1926 /* otherwise just report max that registers can hold */
1927 return ilk_cursor_wm_reg_max(dev, level);
1928 }
1929
1930 static void ilk_compute_wm_maximums(const struct drm_device *dev,
1931 int level,
1932 const struct intel_wm_config *config,
1933 enum intel_ddb_partitioning ddb_partitioning,
1934 struct ilk_wm_maximums *max)
1935 {
1936 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1937 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1938 max->cur = ilk_cursor_wm_max(dev, level, config);
1939 max->fbc = ilk_fbc_wm_reg_max(dev);
1940 }
1941
1942 static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1943 int level,
1944 struct ilk_wm_maximums *max)
1945 {
1946 max->pri = ilk_plane_wm_reg_max(dev, level, false);
1947 max->spr = ilk_plane_wm_reg_max(dev, level, true);
1948 max->cur = ilk_cursor_wm_reg_max(dev, level);
1949 max->fbc = ilk_fbc_wm_reg_max(dev);
1950 }
1951
1952 static bool ilk_validate_wm_level(int level,
1953 const struct ilk_wm_maximums *max,
1954 struct intel_wm_level *result)
1955 {
1956 bool ret;
1957
1958 /* already determined to be invalid? */
1959 if (!result->enable)
1960 return false;
1961
1962 result->enable = result->pri_val <= max->pri &&
1963 result->spr_val <= max->spr &&
1964 result->cur_val <= max->cur;
1965
1966 ret = result->enable;
1967
1968 /*
1969 * HACK until we can pre-compute everything,
1970 * and thus fail gracefully if LP0 watermarks
1971 * are exceeded...
1972 */
1973 if (level == 0 && !result->enable) {
1974 if (result->pri_val > max->pri)
1975 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1976 level, result->pri_val, max->pri);
1977 if (result->spr_val > max->spr)
1978 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1979 level, result->spr_val, max->spr);
1980 if (result->cur_val > max->cur)
1981 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1982 level, result->cur_val, max->cur);
1983
1984 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
1985 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
1986 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
1987 result->enable = true;
1988 }
1989
1990 return ret;
1991 }
1992
1993 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
1994 const struct intel_crtc *intel_crtc,
1995 int level,
1996 struct intel_crtc_state *cstate,
1997 struct intel_plane_state *pristate,
1998 struct intel_plane_state *sprstate,
1999 struct intel_plane_state *curstate,
2000 struct intel_wm_level *result)
2001 {
2002 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2003 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2004 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2005
2006 /* WM1+ latency values stored in 0.5us units */
2007 if (level > 0) {
2008 pri_latency *= 5;
2009 spr_latency *= 5;
2010 cur_latency *= 5;
2011 }
2012
2013 result->pri_val = ilk_compute_pri_wm(cstate, pristate,
2014 pri_latency, level);
2015 result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
2016 result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
2017 result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
2018 result->enable = true;
2019 }
2020
2021 static uint32_t
2022 hsw_compute_linetime_wm(struct drm_device *dev,
2023 struct intel_crtc_state *cstate)
2024 {
2025 struct drm_i915_private *dev_priv = dev->dev_private;
2026 const struct drm_display_mode *adjusted_mode =
2027 &cstate->base.adjusted_mode;
2028 u32 linetime, ips_linetime;
2029
2030 if (!cstate->base.active)
2031 return 0;
2032 if (WARN_ON(adjusted_mode->crtc_clock == 0))
2033 return 0;
2034 if (WARN_ON(dev_priv->cdclk_freq == 0))
2035 return 0;
2036
2037 /* The WM are computed with base on how long it takes to fill a single
2038 * row at the given clock rate, multiplied by 8.
2039 * */
2040 linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2041 adjusted_mode->crtc_clock);
2042 ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2043 dev_priv->cdclk_freq);
2044
2045 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2046 PIPE_WM_LINETIME_TIME(linetime);
2047 }
2048
2049 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
2050 {
2051 struct drm_i915_private *dev_priv = dev->dev_private;
2052
2053 if (IS_GEN9(dev)) {
2054 uint32_t val;
2055 int ret, i;
2056 int level, max_level = ilk_wm_max_level(dev);
2057
2058 /* read the first set of memory latencies[0:3] */
2059 val = 0; /* data0 to be programmed to 0 for first set */
2060 mutex_lock(&dev_priv->rps.hw_lock);
2061 ret = sandybridge_pcode_read(dev_priv,
2062 GEN9_PCODE_READ_MEM_LATENCY,
2063 &val);
2064 mutex_unlock(&dev_priv->rps.hw_lock);
2065
2066 if (ret) {
2067 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2068 return;
2069 }
2070
2071 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2072 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2073 GEN9_MEM_LATENCY_LEVEL_MASK;
2074 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2075 GEN9_MEM_LATENCY_LEVEL_MASK;
2076 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2077 GEN9_MEM_LATENCY_LEVEL_MASK;
2078
2079 /* read the second set of memory latencies[4:7] */
2080 val = 1; /* data0 to be programmed to 1 for second set */
2081 mutex_lock(&dev_priv->rps.hw_lock);
2082 ret = sandybridge_pcode_read(dev_priv,
2083 GEN9_PCODE_READ_MEM_LATENCY,
2084 &val);
2085 mutex_unlock(&dev_priv->rps.hw_lock);
2086 if (ret) {
2087 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2088 return;
2089 }
2090
2091 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2092 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2093 GEN9_MEM_LATENCY_LEVEL_MASK;
2094 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2095 GEN9_MEM_LATENCY_LEVEL_MASK;
2096 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2097 GEN9_MEM_LATENCY_LEVEL_MASK;
2098
2099 /*
2100 * WaWmMemoryReadLatency:skl
2101 *
2102 * punit doesn't take into account the read latency so we need
2103 * to add 2us to the various latency levels we retrieve from
2104 * the punit.
2105 * - W0 is a bit special in that it's the only level that
2106 * can't be disabled if we want to have display working, so
2107 * we always add 2us there.
2108 * - For levels >=1, punit returns 0us latency when they are
2109 * disabled, so we respect that and don't add 2us then
2110 *
2111 * Additionally, if a level n (n > 1) has a 0us latency, all
2112 * levels m (m >= n) need to be disabled. We make sure to
2113 * sanitize the values out of the punit to satisfy this
2114 * requirement.
2115 */
2116 wm[0] += 2;
2117 for (level = 1; level <= max_level; level++)
2118 if (wm[level] != 0)
2119 wm[level] += 2;
2120 else {
2121 for (i = level + 1; i <= max_level; i++)
2122 wm[i] = 0;
2123
2124 break;
2125 }
2126 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2127 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2128
2129 wm[0] = (sskpd >> 56) & 0xFF;
2130 if (wm[0] == 0)
2131 wm[0] = sskpd & 0xF;
2132 wm[1] = (sskpd >> 4) & 0xFF;
2133 wm[2] = (sskpd >> 12) & 0xFF;
2134 wm[3] = (sskpd >> 20) & 0x1FF;
2135 wm[4] = (sskpd >> 32) & 0x1FF;
2136 } else if (INTEL_INFO(dev)->gen >= 6) {
2137 uint32_t sskpd = I915_READ(MCH_SSKPD);
2138
2139 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2140 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2141 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2142 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2143 } else if (INTEL_INFO(dev)->gen >= 5) {
2144 uint32_t mltr = I915_READ(MLTR_ILK);
2145
2146 /* ILK primary LP0 latency is 700 ns */
2147 wm[0] = 7;
2148 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2149 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2150 }
2151 }
2152
2153 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2154 {
2155 /* ILK sprite LP0 latency is 1300 ns */
2156 if (INTEL_INFO(dev)->gen == 5)
2157 wm[0] = 13;
2158 }
2159
2160 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2161 {
2162 /* ILK cursor LP0 latency is 1300 ns */
2163 if (INTEL_INFO(dev)->gen == 5)
2164 wm[0] = 13;
2165
2166 /* WaDoubleCursorLP3Latency:ivb */
2167 if (IS_IVYBRIDGE(dev))
2168 wm[3] *= 2;
2169 }
2170
2171 int ilk_wm_max_level(const struct drm_device *dev)
2172 {
2173 /* how many WM levels are we expecting */
2174 if (INTEL_INFO(dev)->gen >= 9)
2175 return 7;
2176 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2177 return 4;
2178 else if (INTEL_INFO(dev)->gen >= 6)
2179 return 3;
2180 else
2181 return 2;
2182 }
2183
2184 static void intel_print_wm_latency(struct drm_device *dev,
2185 const char *name,
2186 const uint16_t wm[8])
2187 {
2188 int level, max_level = ilk_wm_max_level(dev);
2189
2190 for (level = 0; level <= max_level; level++) {
2191 unsigned int latency = wm[level];
2192
2193 if (latency == 0) {
2194 DRM_ERROR("%s WM%d latency not provided\n",
2195 name, level);
2196 continue;
2197 }
2198
2199 /*
2200 * - latencies are in us on gen9.
2201 * - before then, WM1+ latency values are in 0.5us units
2202 */
2203 if (IS_GEN9(dev))
2204 latency *= 10;
2205 else if (level > 0)
2206 latency *= 5;
2207
2208 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2209 name, level, wm[level],
2210 latency / 10, latency % 10);
2211 }
2212 }
2213
2214 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2215 uint16_t wm[5], uint16_t min)
2216 {
2217 int level, max_level = ilk_wm_max_level(dev_priv->dev);
2218
2219 if (wm[0] >= min)
2220 return false;
2221
2222 wm[0] = max(wm[0], min);
2223 for (level = 1; level <= max_level; level++)
2224 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2225
2226 return true;
2227 }
2228
2229 static void snb_wm_latency_quirk(struct drm_device *dev)
2230 {
2231 struct drm_i915_private *dev_priv = dev->dev_private;
2232 bool changed;
2233
2234 /*
2235 * The BIOS provided WM memory latency values are often
2236 * inadequate for high resolution displays. Adjust them.
2237 */
2238 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2239 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2240 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2241
2242 if (!changed)
2243 return;
2244
2245 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2246 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2247 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2248 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2249 }
2250
2251 static void ilk_setup_wm_latency(struct drm_device *dev)
2252 {
2253 struct drm_i915_private *dev_priv = dev->dev_private;
2254
2255 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2256
2257 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2258 sizeof(dev_priv->wm.pri_latency));
2259 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2260 sizeof(dev_priv->wm.pri_latency));
2261
2262 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2263 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2264
2265 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2266 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2267 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2268
2269 if (IS_GEN6(dev))
2270 snb_wm_latency_quirk(dev);
2271 }
2272
2273 static void skl_setup_wm_latency(struct drm_device *dev)
2274 {
2275 struct drm_i915_private *dev_priv = dev->dev_private;
2276
2277 intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2278 intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2279 }
2280
2281 static bool ilk_validate_pipe_wm(struct drm_device *dev,
2282 struct intel_pipe_wm *pipe_wm)
2283 {
2284 /* LP0 watermark maximums depend on this pipe alone */
2285 const struct intel_wm_config config = {
2286 .num_pipes_active = 1,
2287 .sprites_enabled = pipe_wm->sprites_enabled,
2288 .sprites_scaled = pipe_wm->sprites_scaled,
2289 };
2290 struct ilk_wm_maximums max;
2291
2292 /* LP0 watermarks always use 1/2 DDB partitioning */
2293 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2294
2295 /* At least LP0 must be valid */
2296 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
2297 DRM_DEBUG_KMS("LP0 watermark invalid\n");
2298 return false;
2299 }
2300
2301 return true;
2302 }
2303
2304 /* Compute new watermarks for the pipe */
2305 static int ilk_compute_pipe_wm(struct intel_crtc *intel_crtc,
2306 struct drm_atomic_state *state)
2307 {
2308 struct intel_pipe_wm *pipe_wm;
2309 struct drm_device *dev = intel_crtc->base.dev;
2310 const struct drm_i915_private *dev_priv = dev->dev_private;
2311 struct intel_crtc_state *cstate = NULL;
2312 struct intel_plane *intel_plane;
2313 struct drm_plane_state *ps;
2314 struct intel_plane_state *pristate = NULL;
2315 struct intel_plane_state *sprstate = NULL;
2316 struct intel_plane_state *curstate = NULL;
2317 int level, max_level = ilk_wm_max_level(dev);
2318 struct ilk_wm_maximums max;
2319
2320 cstate = intel_atomic_get_crtc_state(state, intel_crtc);
2321 if (IS_ERR(cstate))
2322 return PTR_ERR(cstate);
2323
2324 pipe_wm = &cstate->wm.optimal.ilk;
2325 memset(pipe_wm, 0, sizeof(*pipe_wm));
2326
2327 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2328 ps = drm_atomic_get_plane_state(state,
2329 &intel_plane->base);
2330 if (IS_ERR(ps))
2331 return PTR_ERR(ps);
2332
2333 if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
2334 pristate = to_intel_plane_state(ps);
2335 else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
2336 sprstate = to_intel_plane_state(ps);
2337 else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
2338 curstate = to_intel_plane_state(ps);
2339 }
2340
2341 pipe_wm->pipe_enabled = cstate->base.active;
2342 pipe_wm->sprites_enabled = sprstate->visible;
2343 pipe_wm->sprites_scaled = sprstate->visible &&
2344 (drm_rect_width(&sprstate->dst) != drm_rect_width(&sprstate->src) >> 16 ||
2345 drm_rect_height(&sprstate->dst) != drm_rect_height(&sprstate->src) >> 16);
2346
2347 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2348 if (INTEL_INFO(dev)->gen <= 6 && sprstate->visible)
2349 max_level = 1;
2350
2351 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2352 if (pipe_wm->sprites_scaled)
2353 max_level = 0;
2354
2355 ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
2356 pristate, sprstate, curstate, &pipe_wm->wm[0]);
2357
2358 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2359 pipe_wm->linetime = hsw_compute_linetime_wm(dev, cstate);
2360
2361 if (!ilk_validate_pipe_wm(dev, pipe_wm))
2362 return false;
2363
2364 ilk_compute_wm_reg_maximums(dev, 1, &max);
2365
2366 for (level = 1; level <= max_level; level++) {
2367 struct intel_wm_level wm = {};
2368
2369 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
2370 pristate, sprstate, curstate, &wm);
2371
2372 /*
2373 * Disable any watermark level that exceeds the
2374 * register maximums since such watermarks are
2375 * always invalid.
2376 */
2377 if (!ilk_validate_wm_level(level, &max, &wm))
2378 break;
2379
2380 pipe_wm->wm[level] = wm;
2381 }
2382
2383 return 0;
2384 }
2385
2386 /*
2387 * Build a set of 'intermediate' watermark values that satisfy both the old
2388 * state and the new state. These can be programmed to the hardware
2389 * immediately.
2390 */
2391 static int ilk_compute_intermediate_wm(struct drm_device *dev,
2392 struct intel_crtc *intel_crtc,
2393 struct intel_crtc_state *newstate)
2394 {
2395 struct intel_pipe_wm *a = &newstate->wm.intermediate;
2396 struct intel_pipe_wm *b = &intel_crtc->wm.active.ilk;
2397 int level, max_level = ilk_wm_max_level(dev);
2398
2399 /*
2400 * Start with the final, target watermarks, then combine with the
2401 * currently active watermarks to get values that are safe both before
2402 * and after the vblank.
2403 */
2404 *a = newstate->wm.optimal.ilk;
2405 a->pipe_enabled |= b->pipe_enabled;
2406 a->sprites_enabled |= b->sprites_enabled;
2407 a->sprites_scaled |= b->sprites_scaled;
2408
2409 for (level = 0; level <= max_level; level++) {
2410 struct intel_wm_level *a_wm = &a->wm[level];
2411 const struct intel_wm_level *b_wm = &b->wm[level];
2412
2413 a_wm->enable &= b_wm->enable;
2414 a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val);
2415 a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val);
2416 a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val);
2417 a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val);
2418 }
2419
2420 /*
2421 * We need to make sure that these merged watermark values are
2422 * actually a valid configuration themselves. If they're not,
2423 * there's no safe way to transition from the old state to
2424 * the new state, so we need to fail the atomic transaction.
2425 */
2426 if (!ilk_validate_pipe_wm(dev, a))
2427 return -EINVAL;
2428
2429 /*
2430 * If our intermediate WM are identical to the final WM, then we can
2431 * omit the post-vblank programming; only update if it's different.
2432 */
2433 if (memcmp(a, &newstate->wm.optimal.ilk, sizeof(*a)) == 0)
2434 newstate->wm.need_postvbl_update = false;
2435
2436 return 0;
2437 }
2438
2439 /*
2440 * Merge the watermarks from all active pipes for a specific level.
2441 */
2442 static void ilk_merge_wm_level(struct drm_device *dev,
2443 int level,
2444 struct intel_wm_level *ret_wm)
2445 {
2446 const struct intel_crtc *intel_crtc;
2447
2448 ret_wm->enable = true;
2449
2450 for_each_intel_crtc(dev, intel_crtc) {
2451 const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk;
2452 const struct intel_wm_level *wm = &active->wm[level];
2453
2454 if (!active->pipe_enabled)
2455 continue;
2456
2457 /*
2458 * The watermark values may have been used in the past,
2459 * so we must maintain them in the registers for some
2460 * time even if the level is now disabled.
2461 */
2462 if (!wm->enable)
2463 ret_wm->enable = false;
2464
2465 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2466 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2467 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2468 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2469 }
2470 }
2471
2472 /*
2473 * Merge all low power watermarks for all active pipes.
2474 */
2475 static void ilk_wm_merge(struct drm_device *dev,
2476 const struct intel_wm_config *config,
2477 const struct ilk_wm_maximums *max,
2478 struct intel_pipe_wm *merged)
2479 {
2480 struct drm_i915_private *dev_priv = dev->dev_private;
2481 int level, max_level = ilk_wm_max_level(dev);
2482 int last_enabled_level = max_level;
2483
2484 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2485 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2486 config->num_pipes_active > 1)
2487 return;
2488
2489 /* ILK: FBC WM must be disabled always */
2490 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
2491
2492 /* merge each WM1+ level */
2493 for (level = 1; level <= max_level; level++) {
2494 struct intel_wm_level *wm = &merged->wm[level];
2495
2496 ilk_merge_wm_level(dev, level, wm);
2497
2498 if (level > last_enabled_level)
2499 wm->enable = false;
2500 else if (!ilk_validate_wm_level(level, max, wm))
2501 /* make sure all following levels get disabled */
2502 last_enabled_level = level - 1;
2503
2504 /*
2505 * The spec says it is preferred to disable
2506 * FBC WMs instead of disabling a WM level.
2507 */
2508 if (wm->fbc_val > max->fbc) {
2509 if (wm->enable)
2510 merged->fbc_wm_enabled = false;
2511 wm->fbc_val = 0;
2512 }
2513 }
2514
2515 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2516 /*
2517 * FIXME this is racy. FBC might get enabled later.
2518 * What we should check here is whether FBC can be
2519 * enabled sometime later.
2520 */
2521 if (IS_GEN5(dev) && !merged->fbc_wm_enabled &&
2522 intel_fbc_is_active(dev_priv)) {
2523 for (level = 2; level <= max_level; level++) {
2524 struct intel_wm_level *wm = &merged->wm[level];
2525
2526 wm->enable = false;
2527 }
2528 }
2529 }
2530
2531 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2532 {
2533 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2534 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2535 }
2536
2537 /* The value we need to program into the WM_LPx latency field */
2538 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2539 {
2540 struct drm_i915_private *dev_priv = dev->dev_private;
2541
2542 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2543 return 2 * level;
2544 else
2545 return dev_priv->wm.pri_latency[level];
2546 }
2547
2548 static void ilk_compute_wm_results(struct drm_device *dev,
2549 const struct intel_pipe_wm *merged,
2550 enum intel_ddb_partitioning partitioning,
2551 struct ilk_wm_values *results)
2552 {
2553 struct intel_crtc *intel_crtc;
2554 int level, wm_lp;
2555
2556 results->enable_fbc_wm = merged->fbc_wm_enabled;
2557 results->partitioning = partitioning;
2558
2559 /* LP1+ register values */
2560 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2561 const struct intel_wm_level *r;
2562
2563 level = ilk_wm_lp_to_level(wm_lp, merged);
2564
2565 r = &merged->wm[level];
2566
2567 /*
2568 * Maintain the watermark values even if the level is
2569 * disabled. Doing otherwise could cause underruns.
2570 */
2571 results->wm_lp[wm_lp - 1] =
2572 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2573 (r->pri_val << WM1_LP_SR_SHIFT) |
2574 r->cur_val;
2575
2576 if (r->enable)
2577 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2578
2579 if (INTEL_INFO(dev)->gen >= 8)
2580 results->wm_lp[wm_lp - 1] |=
2581 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2582 else
2583 results->wm_lp[wm_lp - 1] |=
2584 r->fbc_val << WM1_LP_FBC_SHIFT;
2585
2586 /*
2587 * Always set WM1S_LP_EN when spr_val != 0, even if the
2588 * level is disabled. Doing otherwise could cause underruns.
2589 */
2590 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2591 WARN_ON(wm_lp != 1);
2592 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2593 } else
2594 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2595 }
2596
2597 /* LP0 register values */
2598 for_each_intel_crtc(dev, intel_crtc) {
2599 enum pipe pipe = intel_crtc->pipe;
2600 const struct intel_wm_level *r =
2601 &intel_crtc->wm.active.ilk.wm[0];
2602
2603 if (WARN_ON(!r->enable))
2604 continue;
2605
2606 results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime;
2607
2608 results->wm_pipe[pipe] =
2609 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2610 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2611 r->cur_val;
2612 }
2613 }
2614
2615 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2616 * case both are at the same level. Prefer r1 in case they're the same. */
2617 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2618 struct intel_pipe_wm *r1,
2619 struct intel_pipe_wm *r2)
2620 {
2621 int level, max_level = ilk_wm_max_level(dev);
2622 int level1 = 0, level2 = 0;
2623
2624 for (level = 1; level <= max_level; level++) {
2625 if (r1->wm[level].enable)
2626 level1 = level;
2627 if (r2->wm[level].enable)
2628 level2 = level;
2629 }
2630
2631 if (level1 == level2) {
2632 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2633 return r2;
2634 else
2635 return r1;
2636 } else if (level1 > level2) {
2637 return r1;
2638 } else {
2639 return r2;
2640 }
2641 }
2642
2643 /* dirty bits used to track which watermarks need changes */
2644 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2645 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2646 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2647 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2648 #define WM_DIRTY_FBC (1 << 24)
2649 #define WM_DIRTY_DDB (1 << 25)
2650
2651 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
2652 const struct ilk_wm_values *old,
2653 const struct ilk_wm_values *new)
2654 {
2655 unsigned int dirty = 0;
2656 enum pipe pipe;
2657 int wm_lp;
2658
2659 for_each_pipe(dev_priv, pipe) {
2660 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2661 dirty |= WM_DIRTY_LINETIME(pipe);
2662 /* Must disable LP1+ watermarks too */
2663 dirty |= WM_DIRTY_LP_ALL;
2664 }
2665
2666 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2667 dirty |= WM_DIRTY_PIPE(pipe);
2668 /* Must disable LP1+ watermarks too */
2669 dirty |= WM_DIRTY_LP_ALL;
2670 }
2671 }
2672
2673 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2674 dirty |= WM_DIRTY_FBC;
2675 /* Must disable LP1+ watermarks too */
2676 dirty |= WM_DIRTY_LP_ALL;
2677 }
2678
2679 if (old->partitioning != new->partitioning) {
2680 dirty |= WM_DIRTY_DDB;
2681 /* Must disable LP1+ watermarks too */
2682 dirty |= WM_DIRTY_LP_ALL;
2683 }
2684
2685 /* LP1+ watermarks already deemed dirty, no need to continue */
2686 if (dirty & WM_DIRTY_LP_ALL)
2687 return dirty;
2688
2689 /* Find the lowest numbered LP1+ watermark in need of an update... */
2690 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2691 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2692 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2693 break;
2694 }
2695
2696 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2697 for (; wm_lp <= 3; wm_lp++)
2698 dirty |= WM_DIRTY_LP(wm_lp);
2699
2700 return dirty;
2701 }
2702
2703 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2704 unsigned int dirty)
2705 {
2706 struct ilk_wm_values *previous = &dev_priv->wm.hw;
2707 bool changed = false;
2708
2709 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2710 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2711 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2712 changed = true;
2713 }
2714 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2715 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2716 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2717 changed = true;
2718 }
2719 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2720 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2721 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2722 changed = true;
2723 }
2724
2725 /*
2726 * Don't touch WM1S_LP_EN here.
2727 * Doing so could cause underruns.
2728 */
2729
2730 return changed;
2731 }
2732
2733 /*
2734 * The spec says we shouldn't write when we don't need, because every write
2735 * causes WMs to be re-evaluated, expending some power.
2736 */
2737 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2738 struct ilk_wm_values *results)
2739 {
2740 struct drm_device *dev = dev_priv->dev;
2741 struct ilk_wm_values *previous = &dev_priv->wm.hw;
2742 unsigned int dirty;
2743 uint32_t val;
2744
2745 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
2746 if (!dirty)
2747 return;
2748
2749 _ilk_disable_lp_wm(dev_priv, dirty);
2750
2751 if (dirty & WM_DIRTY_PIPE(PIPE_A))
2752 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2753 if (dirty & WM_DIRTY_PIPE(PIPE_B))
2754 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2755 if (dirty & WM_DIRTY_PIPE(PIPE_C))
2756 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2757
2758 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2759 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2760 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2761 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2762 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2763 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2764
2765 if (dirty & WM_DIRTY_DDB) {
2766 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2767 val = I915_READ(WM_MISC);
2768 if (results->partitioning == INTEL_DDB_PART_1_2)
2769 val &= ~WM_MISC_DATA_PARTITION_5_6;
2770 else
2771 val |= WM_MISC_DATA_PARTITION_5_6;
2772 I915_WRITE(WM_MISC, val);
2773 } else {
2774 val = I915_READ(DISP_ARB_CTL2);
2775 if (results->partitioning == INTEL_DDB_PART_1_2)
2776 val &= ~DISP_DATA_PARTITION_5_6;
2777 else
2778 val |= DISP_DATA_PARTITION_5_6;
2779 I915_WRITE(DISP_ARB_CTL2, val);
2780 }
2781 }
2782
2783 if (dirty & WM_DIRTY_FBC) {
2784 val = I915_READ(DISP_ARB_CTL);
2785 if (results->enable_fbc_wm)
2786 val &= ~DISP_FBC_WM_DIS;
2787 else
2788 val |= DISP_FBC_WM_DIS;
2789 I915_WRITE(DISP_ARB_CTL, val);
2790 }
2791
2792 if (dirty & WM_DIRTY_LP(1) &&
2793 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2794 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2795
2796 if (INTEL_INFO(dev)->gen >= 7) {
2797 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2798 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2799 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2800 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2801 }
2802
2803 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2804 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2805 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2806 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2807 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2808 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2809
2810 dev_priv->wm.hw = *results;
2811 }
2812
2813 bool ilk_disable_lp_wm(struct drm_device *dev)
2814 {
2815 struct drm_i915_private *dev_priv = dev->dev_private;
2816
2817 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2818 }
2819
2820 /*
2821 * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2822 * different active planes.
2823 */
2824
2825 #define SKL_DDB_SIZE 896 /* in blocks */
2826 #define BXT_DDB_SIZE 512
2827
2828 /*
2829 * Return the index of a plane in the SKL DDB and wm result arrays. Primary
2830 * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
2831 * other universal planes are in indices 1..n. Note that this may leave unused
2832 * indices between the top "sprite" plane and the cursor.
2833 */
2834 static int
2835 skl_wm_plane_id(const struct intel_plane *plane)
2836 {
2837 switch (plane->base.type) {
2838 case DRM_PLANE_TYPE_PRIMARY:
2839 return 0;
2840 case DRM_PLANE_TYPE_CURSOR:
2841 return PLANE_CURSOR;
2842 case DRM_PLANE_TYPE_OVERLAY:
2843 return plane->plane + 1;
2844 default:
2845 MISSING_CASE(plane->base.type);
2846 return plane->plane;
2847 }
2848 }
2849
2850 static void
2851 skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
2852 const struct intel_crtc_state *cstate,
2853 const struct intel_wm_config *config,
2854 struct skl_ddb_entry *alloc /* out */)
2855 {
2856 struct drm_crtc *for_crtc = cstate->base.crtc;
2857 struct drm_crtc *crtc;
2858 unsigned int pipe_size, ddb_size;
2859 int nth_active_pipe;
2860
2861 if (!cstate->base.active) {
2862 alloc->start = 0;
2863 alloc->end = 0;
2864 return;
2865 }
2866
2867 if (IS_BROXTON(dev))
2868 ddb_size = BXT_DDB_SIZE;
2869 else
2870 ddb_size = SKL_DDB_SIZE;
2871
2872 ddb_size -= 4; /* 4 blocks for bypass path allocation */
2873
2874 nth_active_pipe = 0;
2875 for_each_crtc(dev, crtc) {
2876 if (!to_intel_crtc(crtc)->active)
2877 continue;
2878
2879 if (crtc == for_crtc)
2880 break;
2881
2882 nth_active_pipe++;
2883 }
2884
2885 pipe_size = ddb_size / config->num_pipes_active;
2886 alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active;
2887 alloc->end = alloc->start + pipe_size;
2888 }
2889
2890 static unsigned int skl_cursor_allocation(const struct intel_wm_config *config)
2891 {
2892 if (config->num_pipes_active == 1)
2893 return 32;
2894
2895 return 8;
2896 }
2897
2898 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
2899 {
2900 entry->start = reg & 0x3ff;
2901 entry->end = (reg >> 16) & 0x3ff;
2902 if (entry->end)
2903 entry->end += 1;
2904 }
2905
2906 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2907 struct skl_ddb_allocation *ddb /* out */)
2908 {
2909 enum pipe pipe;
2910 int plane;
2911 u32 val;
2912
2913 memset(ddb, 0, sizeof(*ddb));
2914
2915 for_each_pipe(dev_priv, pipe) {
2916 enum intel_display_power_domain power_domain;
2917
2918 power_domain = POWER_DOMAIN_PIPE(pipe);
2919 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
2920 continue;
2921
2922 for_each_plane(dev_priv, pipe, plane) {
2923 val = I915_READ(PLANE_BUF_CFG(pipe, plane));
2924 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
2925 val);
2926 }
2927
2928 val = I915_READ(CUR_BUF_CFG(pipe));
2929 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
2930 val);
2931
2932 intel_display_power_put(dev_priv, power_domain);
2933 }
2934 }
2935
2936 static unsigned int
2937 skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
2938 const struct drm_plane_state *pstate,
2939 int y)
2940 {
2941 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
2942 struct drm_framebuffer *fb = pstate->fb;
2943
2944 /* for planar format */
2945 if (fb->pixel_format == DRM_FORMAT_NV12) {
2946 if (y) /* y-plane data rate */
2947 return intel_crtc->config->pipe_src_w *
2948 intel_crtc->config->pipe_src_h *
2949 drm_format_plane_cpp(fb->pixel_format, 0);
2950 else /* uv-plane data rate */
2951 return (intel_crtc->config->pipe_src_w/2) *
2952 (intel_crtc->config->pipe_src_h/2) *
2953 drm_format_plane_cpp(fb->pixel_format, 1);
2954 }
2955
2956 /* for packed formats */
2957 return intel_crtc->config->pipe_src_w *
2958 intel_crtc->config->pipe_src_h *
2959 drm_format_plane_cpp(fb->pixel_format, 0);
2960 }
2961
2962 /*
2963 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
2964 * a 8192x4096@32bpp framebuffer:
2965 * 3 * 4096 * 8192 * 4 < 2^32
2966 */
2967 static unsigned int
2968 skl_get_total_relative_data_rate(const struct intel_crtc_state *cstate)
2969 {
2970 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
2971 struct drm_device *dev = intel_crtc->base.dev;
2972 const struct intel_plane *intel_plane;
2973 unsigned int total_data_rate = 0;
2974
2975 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2976 const struct drm_plane_state *pstate = intel_plane->base.state;
2977
2978 if (pstate->fb == NULL)
2979 continue;
2980
2981 if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
2982 continue;
2983
2984 /* packed/uv */
2985 total_data_rate += skl_plane_relative_data_rate(cstate,
2986 pstate,
2987 0);
2988
2989 if (pstate->fb->pixel_format == DRM_FORMAT_NV12)
2990 /* y-plane */
2991 total_data_rate += skl_plane_relative_data_rate(cstate,
2992 pstate,
2993 1);
2994 }
2995
2996 return total_data_rate;
2997 }
2998
2999 static void
3000 skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
3001 struct skl_ddb_allocation *ddb /* out */)
3002 {
3003 struct drm_crtc *crtc = cstate->base.crtc;
3004 struct drm_device *dev = crtc->dev;
3005 struct drm_i915_private *dev_priv = to_i915(dev);
3006 struct intel_wm_config *config = &dev_priv->wm.config;
3007 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3008 struct intel_plane *intel_plane;
3009 enum pipe pipe = intel_crtc->pipe;
3010 struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
3011 uint16_t alloc_size, start, cursor_blocks;
3012 uint16_t minimum[I915_MAX_PLANES];
3013 uint16_t y_minimum[I915_MAX_PLANES];
3014 unsigned int total_data_rate;
3015
3016 skl_ddb_get_pipe_allocation_limits(dev, cstate, config, alloc);
3017 alloc_size = skl_ddb_entry_size(alloc);
3018 if (alloc_size == 0) {
3019 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3020 memset(&ddb->plane[pipe][PLANE_CURSOR], 0,
3021 sizeof(ddb->plane[pipe][PLANE_CURSOR]));
3022 return;
3023 }
3024
3025 cursor_blocks = skl_cursor_allocation(config);
3026 ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks;
3027 ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
3028
3029 alloc_size -= cursor_blocks;
3030 alloc->end -= cursor_blocks;
3031
3032 /* 1. Allocate the mininum required blocks for each active plane */
3033 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3034 struct drm_plane *plane = &intel_plane->base;
3035 struct drm_framebuffer *fb = plane->state->fb;
3036 int id = skl_wm_plane_id(intel_plane);
3037
3038 if (fb == NULL)
3039 continue;
3040 if (plane->type == DRM_PLANE_TYPE_CURSOR)
3041 continue;
3042
3043 minimum[id] = 8;
3044 alloc_size -= minimum[id];
3045 y_minimum[id] = (fb->pixel_format == DRM_FORMAT_NV12) ? 8 : 0;
3046 alloc_size -= y_minimum[id];
3047 }
3048
3049 /*
3050 * 2. Distribute the remaining space in proportion to the amount of
3051 * data each plane needs to fetch from memory.
3052 *
3053 * FIXME: we may not allocate every single block here.
3054 */
3055 total_data_rate = skl_get_total_relative_data_rate(cstate);
3056
3057 start = alloc->start;
3058 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3059 struct drm_plane *plane = &intel_plane->base;
3060 struct drm_plane_state *pstate = intel_plane->base.state;
3061 unsigned int data_rate, y_data_rate;
3062 uint16_t plane_blocks, y_plane_blocks = 0;
3063 int id = skl_wm_plane_id(intel_plane);
3064
3065 if (pstate->fb == NULL)
3066 continue;
3067 if (plane->type == DRM_PLANE_TYPE_CURSOR)
3068 continue;
3069
3070 data_rate = skl_plane_relative_data_rate(cstate, pstate, 0);
3071
3072 /*
3073 * allocation for (packed formats) or (uv-plane part of planar format):
3074 * promote the expression to 64 bits to avoid overflowing, the
3075 * result is < available as data_rate / total_data_rate < 1
3076 */
3077 plane_blocks = minimum[id];
3078 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3079 total_data_rate);
3080
3081 ddb->plane[pipe][id].start = start;
3082 ddb->plane[pipe][id].end = start + plane_blocks;
3083
3084 start += plane_blocks;
3085
3086 /*
3087 * allocation for y_plane part of planar format:
3088 */
3089 if (pstate->fb->pixel_format == DRM_FORMAT_NV12) {
3090 y_data_rate = skl_plane_relative_data_rate(cstate,
3091 pstate,
3092 1);
3093 y_plane_blocks = y_minimum[id];
3094 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3095 total_data_rate);
3096
3097 ddb->y_plane[pipe][id].start = start;
3098 ddb->y_plane[pipe][id].end = start + y_plane_blocks;
3099
3100 start += y_plane_blocks;
3101 }
3102
3103 }
3104
3105 }
3106
3107 static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
3108 {
3109 /* TODO: Take into account the scalers once we support them */
3110 return config->base.adjusted_mode.crtc_clock;
3111 }
3112
3113 /*
3114 * The max latency should be 257 (max the punit can code is 255 and we add 2us
3115 * for the read latency) and cpp should always be <= 8, so that
3116 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3117 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3118 */
3119 static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
3120 {
3121 uint32_t wm_intermediate_val, ret;
3122
3123 if (latency == 0)
3124 return UINT_MAX;
3125
3126 wm_intermediate_val = latency * pixel_rate * cpp / 512;
3127 ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3128
3129 return ret;
3130 }
3131
3132 static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
3133 uint32_t horiz_pixels, uint8_t cpp,
3134 uint64_t tiling, uint32_t latency)
3135 {
3136 uint32_t ret;
3137 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3138 uint32_t wm_intermediate_val;
3139
3140 if (latency == 0)
3141 return UINT_MAX;
3142
3143 plane_bytes_per_line = horiz_pixels * cpp;
3144
3145 if (tiling == I915_FORMAT_MOD_Y_TILED ||
3146 tiling == I915_FORMAT_MOD_Yf_TILED) {
3147 plane_bytes_per_line *= 4;
3148 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3149 plane_blocks_per_line /= 4;
3150 } else {
3151 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3152 }
3153
3154 wm_intermediate_val = latency * pixel_rate;
3155 ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
3156 plane_blocks_per_line;
3157
3158 return ret;
3159 }
3160
3161 static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb,
3162 const struct intel_crtc *intel_crtc)
3163 {
3164 struct drm_device *dev = intel_crtc->base.dev;
3165 struct drm_i915_private *dev_priv = dev->dev_private;
3166 const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
3167
3168 /*
3169 * If ddb allocation of pipes changed, it may require recalculation of
3170 * watermarks
3171 */
3172 if (memcmp(new_ddb->pipe, cur_ddb->pipe, sizeof(new_ddb->pipe)))
3173 return true;
3174
3175 return false;
3176 }
3177
3178 static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3179 struct intel_crtc_state *cstate,
3180 struct intel_plane *intel_plane,
3181 uint16_t ddb_allocation,
3182 int level,
3183 uint16_t *out_blocks, /* out */
3184 uint8_t *out_lines /* out */)
3185 {
3186 struct drm_plane *plane = &intel_plane->base;
3187 struct drm_framebuffer *fb = plane->state->fb;
3188 uint32_t latency = dev_priv->wm.skl_latency[level];
3189 uint32_t method1, method2;
3190 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3191 uint32_t res_blocks, res_lines;
3192 uint32_t selected_result;
3193 uint8_t cpp;
3194
3195 if (latency == 0 || !cstate->base.active || !fb)
3196 return false;
3197
3198 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
3199 method1 = skl_wm_method1(skl_pipe_pixel_rate(cstate),
3200 cpp, latency);
3201 method2 = skl_wm_method2(skl_pipe_pixel_rate(cstate),
3202 cstate->base.adjusted_mode.crtc_htotal,
3203 cstate->pipe_src_w,
3204 cpp, fb->modifier[0],
3205 latency);
3206
3207 plane_bytes_per_line = cstate->pipe_src_w * cpp;
3208 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3209
3210 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3211 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
3212 uint32_t min_scanlines = 4;
3213 uint32_t y_tile_minimum;
3214 if (intel_rotation_90_or_270(plane->state->rotation)) {
3215 int cpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
3216 drm_format_plane_cpp(fb->pixel_format, 1) :
3217 drm_format_plane_cpp(fb->pixel_format, 0);
3218
3219 switch (cpp) {
3220 case 1:
3221 min_scanlines = 16;
3222 break;
3223 case 2:
3224 min_scanlines = 8;
3225 break;
3226 case 8:
3227 WARN(1, "Unsupported pixel depth for rotation");
3228 }
3229 }
3230 y_tile_minimum = plane_blocks_per_line * min_scanlines;
3231 selected_result = max(method2, y_tile_minimum);
3232 } else {
3233 if ((ddb_allocation / plane_blocks_per_line) >= 1)
3234 selected_result = min(method1, method2);
3235 else
3236 selected_result = method1;
3237 }
3238
3239 res_blocks = selected_result + 1;
3240 res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
3241
3242 if (level >= 1 && level <= 7) {
3243 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3244 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED)
3245 res_lines += 4;
3246 else
3247 res_blocks++;
3248 }
3249
3250 if (res_blocks >= ddb_allocation || res_lines > 31)
3251 return false;
3252
3253 *out_blocks = res_blocks;
3254 *out_lines = res_lines;
3255
3256 return true;
3257 }
3258
3259 static void skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3260 struct skl_ddb_allocation *ddb,
3261 struct intel_crtc_state *cstate,
3262 int level,
3263 struct skl_wm_level *result)
3264 {
3265 struct drm_device *dev = dev_priv->dev;
3266 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
3267 struct intel_plane *intel_plane;
3268 uint16_t ddb_blocks;
3269 enum pipe pipe = intel_crtc->pipe;
3270
3271 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3272 int i = skl_wm_plane_id(intel_plane);
3273
3274 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3275
3276 result->plane_en[i] = skl_compute_plane_wm(dev_priv,
3277 cstate,
3278 intel_plane,
3279 ddb_blocks,
3280 level,
3281 &result->plane_res_b[i],
3282 &result->plane_res_l[i]);
3283 }
3284 }
3285
3286 static uint32_t
3287 skl_compute_linetime_wm(struct intel_crtc_state *cstate)
3288 {
3289 if (!cstate->base.active)
3290 return 0;
3291
3292 if (WARN_ON(skl_pipe_pixel_rate(cstate) == 0))
3293 return 0;
3294
3295 return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
3296 skl_pipe_pixel_rate(cstate));
3297 }
3298
3299 static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
3300 struct skl_wm_level *trans_wm /* out */)
3301 {
3302 struct drm_crtc *crtc = cstate->base.crtc;
3303 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3304 struct intel_plane *intel_plane;
3305
3306 if (!cstate->base.active)
3307 return;
3308
3309 /* Until we know more, just disable transition WMs */
3310 for_each_intel_plane_on_crtc(crtc->dev, intel_crtc, intel_plane) {
3311 int i = skl_wm_plane_id(intel_plane);
3312
3313 trans_wm->plane_en[i] = false;
3314 }
3315 }
3316
3317 static void skl_compute_pipe_wm(struct intel_crtc_state *cstate,
3318 struct skl_ddb_allocation *ddb,
3319 struct skl_pipe_wm *pipe_wm)
3320 {
3321 struct drm_device *dev = cstate->base.crtc->dev;
3322 const struct drm_i915_private *dev_priv = dev->dev_private;
3323 int level, max_level = ilk_wm_max_level(dev);
3324
3325 for (level = 0; level <= max_level; level++) {
3326 skl_compute_wm_level(dev_priv, ddb, cstate,
3327 level, &pipe_wm->wm[level]);
3328 }
3329 pipe_wm->linetime = skl_compute_linetime_wm(cstate);
3330
3331 skl_compute_transition_wm(cstate, &pipe_wm->trans_wm);
3332 }
3333
3334 static void skl_compute_wm_results(struct drm_device *dev,
3335 struct skl_pipe_wm *p_wm,
3336 struct skl_wm_values *r,
3337 struct intel_crtc *intel_crtc)
3338 {
3339 int level, max_level = ilk_wm_max_level(dev);
3340 enum pipe pipe = intel_crtc->pipe;
3341 uint32_t temp;
3342 int i;
3343
3344 for (level = 0; level <= max_level; level++) {
3345 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3346 temp = 0;
3347
3348 temp |= p_wm->wm[level].plane_res_l[i] <<
3349 PLANE_WM_LINES_SHIFT;
3350 temp |= p_wm->wm[level].plane_res_b[i];
3351 if (p_wm->wm[level].plane_en[i])
3352 temp |= PLANE_WM_EN;
3353
3354 r->plane[pipe][i][level] = temp;
3355 }
3356
3357 temp = 0;
3358
3359 temp |= p_wm->wm[level].plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3360 temp |= p_wm->wm[level].plane_res_b[PLANE_CURSOR];
3361
3362 if (p_wm->wm[level].plane_en[PLANE_CURSOR])
3363 temp |= PLANE_WM_EN;
3364
3365 r->plane[pipe][PLANE_CURSOR][level] = temp;
3366
3367 }
3368
3369 /* transition WMs */
3370 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3371 temp = 0;
3372 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3373 temp |= p_wm->trans_wm.plane_res_b[i];
3374 if (p_wm->trans_wm.plane_en[i])
3375 temp |= PLANE_WM_EN;
3376
3377 r->plane_trans[pipe][i] = temp;
3378 }
3379
3380 temp = 0;
3381 temp |= p_wm->trans_wm.plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3382 temp |= p_wm->trans_wm.plane_res_b[PLANE_CURSOR];
3383 if (p_wm->trans_wm.plane_en[PLANE_CURSOR])
3384 temp |= PLANE_WM_EN;
3385
3386 r->plane_trans[pipe][PLANE_CURSOR] = temp;
3387
3388 r->wm_linetime[pipe] = p_wm->linetime;
3389 }
3390
3391 static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
3392 i915_reg_t reg,
3393 const struct skl_ddb_entry *entry)
3394 {
3395 if (entry->end)
3396 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3397 else
3398 I915_WRITE(reg, 0);
3399 }
3400
3401 static void skl_write_wm_values(struct drm_i915_private *dev_priv,
3402 const struct skl_wm_values *new)
3403 {
3404 struct drm_device *dev = dev_priv->dev;
3405 struct intel_crtc *crtc;
3406
3407 for_each_intel_crtc(dev, crtc) {
3408 int i, level, max_level = ilk_wm_max_level(dev);
3409 enum pipe pipe = crtc->pipe;
3410
3411 if (!new->dirty[pipe])
3412 continue;
3413
3414 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]);
3415
3416 for (level = 0; level <= max_level; level++) {
3417 for (i = 0; i < intel_num_planes(crtc); i++)
3418 I915_WRITE(PLANE_WM(pipe, i, level),
3419 new->plane[pipe][i][level]);
3420 I915_WRITE(CUR_WM(pipe, level),
3421 new->plane[pipe][PLANE_CURSOR][level]);
3422 }
3423 for (i = 0; i < intel_num_planes(crtc); i++)
3424 I915_WRITE(PLANE_WM_TRANS(pipe, i),
3425 new->plane_trans[pipe][i]);
3426 I915_WRITE(CUR_WM_TRANS(pipe),
3427 new->plane_trans[pipe][PLANE_CURSOR]);
3428
3429 for (i = 0; i < intel_num_planes(crtc); i++) {
3430 skl_ddb_entry_write(dev_priv,
3431 PLANE_BUF_CFG(pipe, i),
3432 &new->ddb.plane[pipe][i]);
3433 skl_ddb_entry_write(dev_priv,
3434 PLANE_NV12_BUF_CFG(pipe, i),
3435 &new->ddb.y_plane[pipe][i]);
3436 }
3437
3438 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3439 &new->ddb.plane[pipe][PLANE_CURSOR]);
3440 }
3441 }
3442
3443 /*
3444 * When setting up a new DDB allocation arrangement, we need to correctly
3445 * sequence the times at which the new allocations for the pipes are taken into
3446 * account or we'll have pipes fetching from space previously allocated to
3447 * another pipe.
3448 *
3449 * Roughly the sequence looks like:
3450 * 1. re-allocate the pipe(s) with the allocation being reduced and not
3451 * overlapping with a previous light-up pipe (another way to put it is:
3452 * pipes with their new allocation strickly included into their old ones).
3453 * 2. re-allocate the other pipes that get their allocation reduced
3454 * 3. allocate the pipes having their allocation increased
3455 *
3456 * Steps 1. and 2. are here to take care of the following case:
3457 * - Initially DDB looks like this:
3458 * | B | C |
3459 * - enable pipe A.
3460 * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
3461 * allocation
3462 * | A | B | C |
3463 *
3464 * We need to sequence the re-allocation: C, B, A (and not B, C, A).
3465 */
3466
3467 static void
3468 skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass)
3469 {
3470 int plane;
3471
3472 DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);
3473
3474 for_each_plane(dev_priv, pipe, plane) {
3475 I915_WRITE(PLANE_SURF(pipe, plane),
3476 I915_READ(PLANE_SURF(pipe, plane)));
3477 }
3478 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3479 }
3480
3481 static bool
3482 skl_ddb_allocation_included(const struct skl_ddb_allocation *old,
3483 const struct skl_ddb_allocation *new,
3484 enum pipe pipe)
3485 {
3486 uint16_t old_size, new_size;
3487
3488 old_size = skl_ddb_entry_size(&old->pipe[pipe]);
3489 new_size = skl_ddb_entry_size(&new->pipe[pipe]);
3490
3491 return old_size != new_size &&
3492 new->pipe[pipe].start >= old->pipe[pipe].start &&
3493 new->pipe[pipe].end <= old->pipe[pipe].end;
3494 }
3495
3496 static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
3497 struct skl_wm_values *new_values)
3498 {
3499 struct drm_device *dev = dev_priv->dev;
3500 struct skl_ddb_allocation *cur_ddb, *new_ddb;
3501 bool reallocated[I915_MAX_PIPES] = {};
3502 struct intel_crtc *crtc;
3503 enum pipe pipe;
3504
3505 new_ddb = &new_values->ddb;
3506 cur_ddb = &dev_priv->wm.skl_hw.ddb;
3507
3508 /*
3509 * First pass: flush the pipes with the new allocation contained into
3510 * the old space.
3511 *
3512 * We'll wait for the vblank on those pipes to ensure we can safely
3513 * re-allocate the freed space without this pipe fetching from it.
3514 */
3515 for_each_intel_crtc(dev, crtc) {
3516 if (!crtc->active)
3517 continue;
3518
3519 pipe = crtc->pipe;
3520
3521 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))
3522 continue;
3523
3524 skl_wm_flush_pipe(dev_priv, pipe, 1);
3525 intel_wait_for_vblank(dev, pipe);
3526
3527 reallocated[pipe] = true;
3528 }
3529
3530
3531 /*
3532 * Second pass: flush the pipes that are having their allocation
3533 * reduced, but overlapping with a previous allocation.
3534 *
3535 * Here as well we need to wait for the vblank to make sure the freed
3536 * space is not used anymore.
3537 */
3538 for_each_intel_crtc(dev, crtc) {
3539 if (!crtc->active)
3540 continue;
3541
3542 pipe = crtc->pipe;
3543
3544 if (reallocated[pipe])
3545 continue;
3546
3547 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <
3548 skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
3549 skl_wm_flush_pipe(dev_priv, pipe, 2);
3550 intel_wait_for_vblank(dev, pipe);
3551 reallocated[pipe] = true;
3552 }
3553 }
3554
3555 /*
3556 * Third pass: flush the pipes that got more space allocated.
3557 *
3558 * We don't need to actively wait for the update here, next vblank
3559 * will just get more DDB space with the correct WM values.
3560 */
3561 for_each_intel_crtc(dev, crtc) {
3562 if (!crtc->active)
3563 continue;
3564
3565 pipe = crtc->pipe;
3566
3567 /*
3568 * At this point, only the pipes more space than before are
3569 * left to re-allocate.
3570 */
3571 if (reallocated[pipe])
3572 continue;
3573
3574 skl_wm_flush_pipe(dev_priv, pipe, 3);
3575 }
3576 }
3577
3578 static bool skl_update_pipe_wm(struct drm_crtc *crtc,
3579 struct skl_ddb_allocation *ddb, /* out */
3580 struct skl_pipe_wm *pipe_wm /* out */)
3581 {
3582 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3583 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3584
3585 skl_allocate_pipe_ddb(cstate, ddb);
3586 skl_compute_pipe_wm(cstate, ddb, pipe_wm);
3587
3588 if (!memcmp(&intel_crtc->wm.active.skl, pipe_wm, sizeof(*pipe_wm)))
3589 return false;
3590
3591 intel_crtc->wm.active.skl = *pipe_wm;
3592
3593 return true;
3594 }
3595
3596 static void skl_update_other_pipe_wm(struct drm_device *dev,
3597 struct drm_crtc *crtc,
3598 struct skl_wm_values *r)
3599 {
3600 struct intel_crtc *intel_crtc;
3601 struct intel_crtc *this_crtc = to_intel_crtc(crtc);
3602
3603 /*
3604 * If the WM update hasn't changed the allocation for this_crtc (the
3605 * crtc we are currently computing the new WM values for), other
3606 * enabled crtcs will keep the same allocation and we don't need to
3607 * recompute anything for them.
3608 */
3609 if (!skl_ddb_allocation_changed(&r->ddb, this_crtc))
3610 return;
3611
3612 /*
3613 * Otherwise, because of this_crtc being freshly enabled/disabled, the
3614 * other active pipes need new DDB allocation and WM values.
3615 */
3616 for_each_intel_crtc(dev, intel_crtc) {
3617 struct skl_pipe_wm pipe_wm = {};
3618 bool wm_changed;
3619
3620 if (this_crtc->pipe == intel_crtc->pipe)
3621 continue;
3622
3623 if (!intel_crtc->active)
3624 continue;
3625
3626 wm_changed = skl_update_pipe_wm(&intel_crtc->base,
3627 &r->ddb, &pipe_wm);
3628
3629 /*
3630 * If we end up re-computing the other pipe WM values, it's
3631 * because it was really needed, so we expect the WM values to
3632 * be different.
3633 */
3634 WARN_ON(!wm_changed);
3635
3636 skl_compute_wm_results(dev, &pipe_wm, r, intel_crtc);
3637 r->dirty[intel_crtc->pipe] = true;
3638 }
3639 }
3640
3641 static void skl_clear_wm(struct skl_wm_values *watermarks, enum pipe pipe)
3642 {
3643 watermarks->wm_linetime[pipe] = 0;
3644 memset(watermarks->plane[pipe], 0,
3645 sizeof(uint32_t) * 8 * I915_MAX_PLANES);
3646 memset(watermarks->plane_trans[pipe],
3647 0, sizeof(uint32_t) * I915_MAX_PLANES);
3648 watermarks->plane_trans[pipe][PLANE_CURSOR] = 0;
3649
3650 /* Clear ddb entries for pipe */
3651 memset(&watermarks->ddb.pipe[pipe], 0, sizeof(struct skl_ddb_entry));
3652 memset(&watermarks->ddb.plane[pipe], 0,
3653 sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
3654 memset(&watermarks->ddb.y_plane[pipe], 0,
3655 sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
3656 memset(&watermarks->ddb.plane[pipe][PLANE_CURSOR], 0,
3657 sizeof(struct skl_ddb_entry));
3658
3659 }
3660
3661 static void skl_update_wm(struct drm_crtc *crtc)
3662 {
3663 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3664 struct drm_device *dev = crtc->dev;
3665 struct drm_i915_private *dev_priv = dev->dev_private;
3666 struct skl_wm_values *results = &dev_priv->wm.skl_results;
3667 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3668 struct skl_pipe_wm *pipe_wm = &cstate->wm.optimal.skl;
3669
3670
3671 /* Clear all dirty flags */
3672 memset(results->dirty, 0, sizeof(bool) * I915_MAX_PIPES);
3673
3674 skl_clear_wm(results, intel_crtc->pipe);
3675
3676 if (!skl_update_pipe_wm(crtc, &results->ddb, pipe_wm))
3677 return;
3678
3679 skl_compute_wm_results(dev, pipe_wm, results, intel_crtc);
3680 results->dirty[intel_crtc->pipe] = true;
3681
3682 skl_update_other_pipe_wm(dev, crtc, results);
3683 skl_write_wm_values(dev_priv, results);
3684 skl_flush_wm_values(dev_priv, results);
3685
3686 /* store the new configuration */
3687 dev_priv->wm.skl_hw = *results;
3688 }
3689
3690 static void ilk_compute_wm_config(struct drm_device *dev,
3691 struct intel_wm_config *config)
3692 {
3693 struct intel_crtc *crtc;
3694
3695 /* Compute the currently _active_ config */
3696 for_each_intel_crtc(dev, crtc) {
3697 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
3698
3699 if (!wm->pipe_enabled)
3700 continue;
3701
3702 config->sprites_enabled |= wm->sprites_enabled;
3703 config->sprites_scaled |= wm->sprites_scaled;
3704 config->num_pipes_active++;
3705 }
3706 }
3707
3708 static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
3709 {
3710 struct drm_device *dev = dev_priv->dev;
3711 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
3712 struct ilk_wm_maximums max;
3713 struct intel_wm_config config = {};
3714 struct ilk_wm_values results = {};
3715 enum intel_ddb_partitioning partitioning;
3716
3717 ilk_compute_wm_config(dev, &config);
3718
3719 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
3720 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
3721
3722 /* 5/6 split only in single pipe config on IVB+ */
3723 if (INTEL_INFO(dev)->gen >= 7 &&
3724 config.num_pipes_active == 1 && config.sprites_enabled) {
3725 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
3726 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
3727
3728 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
3729 } else {
3730 best_lp_wm = &lp_wm_1_2;
3731 }
3732
3733 partitioning = (best_lp_wm == &lp_wm_1_2) ?
3734 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
3735
3736 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
3737
3738 ilk_write_wm_values(dev_priv, &results);
3739 }
3740
3741 static void ilk_initial_watermarks(struct intel_crtc_state *cstate)
3742 {
3743 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
3744 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
3745
3746 mutex_lock(&dev_priv->wm.wm_mutex);
3747 intel_crtc->wm.active.ilk = cstate->wm.intermediate;
3748 ilk_program_watermarks(dev_priv);
3749 mutex_unlock(&dev_priv->wm.wm_mutex);
3750 }
3751
3752 static void ilk_optimize_watermarks(struct intel_crtc_state *cstate)
3753 {
3754 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
3755 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
3756
3757 mutex_lock(&dev_priv->wm.wm_mutex);
3758 if (cstate->wm.need_postvbl_update) {
3759 intel_crtc->wm.active.ilk = cstate->wm.optimal.ilk;
3760 ilk_program_watermarks(dev_priv);
3761 }
3762 mutex_unlock(&dev_priv->wm.wm_mutex);
3763 }
3764
3765 static void skl_pipe_wm_active_state(uint32_t val,
3766 struct skl_pipe_wm *active,
3767 bool is_transwm,
3768 bool is_cursor,
3769 int i,
3770 int level)
3771 {
3772 bool is_enabled = (val & PLANE_WM_EN) != 0;
3773
3774 if (!is_transwm) {
3775 if (!is_cursor) {
3776 active->wm[level].plane_en[i] = is_enabled;
3777 active->wm[level].plane_res_b[i] =
3778 val & PLANE_WM_BLOCKS_MASK;
3779 active->wm[level].plane_res_l[i] =
3780 (val >> PLANE_WM_LINES_SHIFT) &
3781 PLANE_WM_LINES_MASK;
3782 } else {
3783 active->wm[level].plane_en[PLANE_CURSOR] = is_enabled;
3784 active->wm[level].plane_res_b[PLANE_CURSOR] =
3785 val & PLANE_WM_BLOCKS_MASK;
3786 active->wm[level].plane_res_l[PLANE_CURSOR] =
3787 (val >> PLANE_WM_LINES_SHIFT) &
3788 PLANE_WM_LINES_MASK;
3789 }
3790 } else {
3791 if (!is_cursor) {
3792 active->trans_wm.plane_en[i] = is_enabled;
3793 active->trans_wm.plane_res_b[i] =
3794 val & PLANE_WM_BLOCKS_MASK;
3795 active->trans_wm.plane_res_l[i] =
3796 (val >> PLANE_WM_LINES_SHIFT) &
3797 PLANE_WM_LINES_MASK;
3798 } else {
3799 active->trans_wm.plane_en[PLANE_CURSOR] = is_enabled;
3800 active->trans_wm.plane_res_b[PLANE_CURSOR] =
3801 val & PLANE_WM_BLOCKS_MASK;
3802 active->trans_wm.plane_res_l[PLANE_CURSOR] =
3803 (val >> PLANE_WM_LINES_SHIFT) &
3804 PLANE_WM_LINES_MASK;
3805 }
3806 }
3807 }
3808
3809 static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3810 {
3811 struct drm_device *dev = crtc->dev;
3812 struct drm_i915_private *dev_priv = dev->dev_private;
3813 struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
3814 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3815 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3816 struct skl_pipe_wm *active = &cstate->wm.optimal.skl;
3817 enum pipe pipe = intel_crtc->pipe;
3818 int level, i, max_level;
3819 uint32_t temp;
3820
3821 max_level = ilk_wm_max_level(dev);
3822
3823 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3824
3825 for (level = 0; level <= max_level; level++) {
3826 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3827 hw->plane[pipe][i][level] =
3828 I915_READ(PLANE_WM(pipe, i, level));
3829 hw->plane[pipe][PLANE_CURSOR][level] = I915_READ(CUR_WM(pipe, level));
3830 }
3831
3832 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3833 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
3834 hw->plane_trans[pipe][PLANE_CURSOR] = I915_READ(CUR_WM_TRANS(pipe));
3835
3836 if (!intel_crtc->active)
3837 return;
3838
3839 hw->dirty[pipe] = true;
3840
3841 active->linetime = hw->wm_linetime[pipe];
3842
3843 for (level = 0; level <= max_level; level++) {
3844 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3845 temp = hw->plane[pipe][i][level];
3846 skl_pipe_wm_active_state(temp, active, false,
3847 false, i, level);
3848 }
3849 temp = hw->plane[pipe][PLANE_CURSOR][level];
3850 skl_pipe_wm_active_state(temp, active, false, true, i, level);
3851 }
3852
3853 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3854 temp = hw->plane_trans[pipe][i];
3855 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
3856 }
3857
3858 temp = hw->plane_trans[pipe][PLANE_CURSOR];
3859 skl_pipe_wm_active_state(temp, active, true, true, i, 0);
3860
3861 intel_crtc->wm.active.skl = *active;
3862 }
3863
3864 void skl_wm_get_hw_state(struct drm_device *dev)
3865 {
3866 struct drm_i915_private *dev_priv = dev->dev_private;
3867 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3868 struct drm_crtc *crtc;
3869
3870 skl_ddb_get_hw_state(dev_priv, ddb);
3871 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3872 skl_pipe_wm_get_hw_state(crtc);
3873 }
3874
3875 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3876 {
3877 struct drm_device *dev = crtc->dev;
3878 struct drm_i915_private *dev_priv = dev->dev_private;
3879 struct ilk_wm_values *hw = &dev_priv->wm.hw;
3880 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3881 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3882 struct intel_pipe_wm *active = &cstate->wm.optimal.ilk;
3883 enum pipe pipe = intel_crtc->pipe;
3884 static const i915_reg_t wm0_pipe_reg[] = {
3885 [PIPE_A] = WM0_PIPEA_ILK,
3886 [PIPE_B] = WM0_PIPEB_ILK,
3887 [PIPE_C] = WM0_PIPEC_IVB,
3888 };
3889
3890 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
3891 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3892 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3893
3894 active->pipe_enabled = intel_crtc->active;
3895
3896 if (active->pipe_enabled) {
3897 u32 tmp = hw->wm_pipe[pipe];
3898
3899 /*
3900 * For active pipes LP0 watermark is marked as
3901 * enabled, and LP1+ watermaks as disabled since
3902 * we can't really reverse compute them in case
3903 * multiple pipes are active.
3904 */
3905 active->wm[0].enable = true;
3906 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3907 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3908 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3909 active->linetime = hw->wm_linetime[pipe];
3910 } else {
3911 int level, max_level = ilk_wm_max_level(dev);
3912
3913 /*
3914 * For inactive pipes, all watermark levels
3915 * should be marked as enabled but zeroed,
3916 * which is what we'd compute them to.
3917 */
3918 for (level = 0; level <= max_level; level++)
3919 active->wm[level].enable = true;
3920 }
3921
3922 intel_crtc->wm.active.ilk = *active;
3923 }
3924
3925 #define _FW_WM(value, plane) \
3926 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
3927 #define _FW_WM_VLV(value, plane) \
3928 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
3929
3930 static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
3931 struct vlv_wm_values *wm)
3932 {
3933 enum pipe pipe;
3934 uint32_t tmp;
3935
3936 for_each_pipe(dev_priv, pipe) {
3937 tmp = I915_READ(VLV_DDL(pipe));
3938
3939 wm->ddl[pipe].primary =
3940 (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3941 wm->ddl[pipe].cursor =
3942 (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3943 wm->ddl[pipe].sprite[0] =
3944 (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3945 wm->ddl[pipe].sprite[1] =
3946 (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3947 }
3948
3949 tmp = I915_READ(DSPFW1);
3950 wm->sr.plane = _FW_WM(tmp, SR);
3951 wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
3952 wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
3953 wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
3954
3955 tmp = I915_READ(DSPFW2);
3956 wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
3957 wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
3958 wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
3959
3960 tmp = I915_READ(DSPFW3);
3961 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
3962
3963 if (IS_CHERRYVIEW(dev_priv)) {
3964 tmp = I915_READ(DSPFW7_CHV);
3965 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
3966 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
3967
3968 tmp = I915_READ(DSPFW8_CHV);
3969 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
3970 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
3971
3972 tmp = I915_READ(DSPFW9_CHV);
3973 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
3974 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
3975
3976 tmp = I915_READ(DSPHOWM);
3977 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
3978 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
3979 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
3980 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
3981 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
3982 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
3983 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
3984 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
3985 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
3986 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
3987 } else {
3988 tmp = I915_READ(DSPFW7);
3989 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
3990 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
3991
3992 tmp = I915_READ(DSPHOWM);
3993 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
3994 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
3995 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
3996 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
3997 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
3998 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
3999 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4000 }
4001 }
4002
4003 #undef _FW_WM
4004 #undef _FW_WM_VLV
4005
4006 void vlv_wm_get_hw_state(struct drm_device *dev)
4007 {
4008 struct drm_i915_private *dev_priv = to_i915(dev);
4009 struct vlv_wm_values *wm = &dev_priv->wm.vlv;
4010 struct intel_plane *plane;
4011 enum pipe pipe;
4012 u32 val;
4013
4014 vlv_read_wm_values(dev_priv, wm);
4015
4016 for_each_intel_plane(dev, plane) {
4017 switch (plane->base.type) {
4018 int sprite;
4019 case DRM_PLANE_TYPE_CURSOR:
4020 plane->wm.fifo_size = 63;
4021 break;
4022 case DRM_PLANE_TYPE_PRIMARY:
4023 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
4024 break;
4025 case DRM_PLANE_TYPE_OVERLAY:
4026 sprite = plane->plane;
4027 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
4028 break;
4029 }
4030 }
4031
4032 wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4033 wm->level = VLV_WM_LEVEL_PM2;
4034
4035 if (IS_CHERRYVIEW(dev_priv)) {
4036 mutex_lock(&dev_priv->rps.hw_lock);
4037
4038 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4039 if (val & DSP_MAXFIFO_PM5_ENABLE)
4040 wm->level = VLV_WM_LEVEL_PM5;
4041
4042 /*
4043 * If DDR DVFS is disabled in the BIOS, Punit
4044 * will never ack the request. So if that happens
4045 * assume we don't have to enable/disable DDR DVFS
4046 * dynamically. To test that just set the REQ_ACK
4047 * bit to poke the Punit, but don't change the
4048 * HIGH/LOW bits so that we don't actually change
4049 * the current state.
4050 */
4051 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4052 val |= FORCE_DDR_FREQ_REQ_ACK;
4053 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
4054
4055 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
4056 FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
4057 DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4058 "assuming DDR DVFS is disabled\n");
4059 dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
4060 } else {
4061 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4062 if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4063 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4064 }
4065
4066 mutex_unlock(&dev_priv->rps.hw_lock);
4067 }
4068
4069 for_each_pipe(dev_priv, pipe)
4070 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4071 pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4072 wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4073
4074 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4075 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4076 }
4077
4078 void ilk_wm_get_hw_state(struct drm_device *dev)
4079 {
4080 struct drm_i915_private *dev_priv = dev->dev_private;
4081 struct ilk_wm_values *hw = &dev_priv->wm.hw;
4082 struct drm_crtc *crtc;
4083
4084 for_each_crtc(dev, crtc)
4085 ilk_pipe_wm_get_hw_state(crtc);
4086
4087 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4088 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4089 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4090
4091 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
4092 if (INTEL_INFO(dev)->gen >= 7) {
4093 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4094 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4095 }
4096
4097 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4098 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4099 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4100 else if (IS_IVYBRIDGE(dev))
4101 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4102 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4103
4104 hw->enable_fbc_wm =
4105 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4106 }
4107
4108 /**
4109 * intel_update_watermarks - update FIFO watermark values based on current modes
4110 *
4111 * Calculate watermark values for the various WM regs based on current mode
4112 * and plane configuration.
4113 *
4114 * There are several cases to deal with here:
4115 * - normal (i.e. non-self-refresh)
4116 * - self-refresh (SR) mode
4117 * - lines are large relative to FIFO size (buffer can hold up to 2)
4118 * - lines are small relative to FIFO size (buffer can hold more than 2
4119 * lines), so need to account for TLB latency
4120 *
4121 * The normal calculation is:
4122 * watermark = dotclock * bytes per pixel * latency
4123 * where latency is platform & configuration dependent (we assume pessimal
4124 * values here).
4125 *
4126 * The SR calculation is:
4127 * watermark = (trunc(latency/line time)+1) * surface width *
4128 * bytes per pixel
4129 * where
4130 * line time = htotal / dotclock
4131 * surface width = hdisplay for normal plane and 64 for cursor
4132 * and latency is assumed to be high, as above.
4133 *
4134 * The final value programmed to the register should always be rounded up,
4135 * and include an extra 2 entries to account for clock crossings.
4136 *
4137 * We don't use the sprite, so we can ignore that. And on Crestline we have
4138 * to set the non-SR watermarks to 8.
4139 */
4140 void intel_update_watermarks(struct drm_crtc *crtc)
4141 {
4142 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4143
4144 if (dev_priv->display.update_wm)
4145 dev_priv->display.update_wm(crtc);
4146 }
4147
4148 /*
4149 * Lock protecting IPS related data structures
4150 */
4151 DEFINE_SPINLOCK(mchdev_lock);
4152
4153 /* Global for IPS driver to get at the current i915 device. Protected by
4154 * mchdev_lock. */
4155 static struct drm_i915_private *i915_mch_dev;
4156
4157 bool ironlake_set_drps(struct drm_device *dev, u8 val)
4158 {
4159 struct drm_i915_private *dev_priv = dev->dev_private;
4160 u16 rgvswctl;
4161
4162 assert_spin_locked(&mchdev_lock);
4163
4164 rgvswctl = I915_READ16(MEMSWCTL);
4165 if (rgvswctl & MEMCTL_CMD_STS) {
4166 DRM_DEBUG("gpu busy, RCS change rejected\n");
4167 return false; /* still busy with another command */
4168 }
4169
4170 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4171 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4172 I915_WRITE16(MEMSWCTL, rgvswctl);
4173 POSTING_READ16(MEMSWCTL);
4174
4175 rgvswctl |= MEMCTL_CMD_STS;
4176 I915_WRITE16(MEMSWCTL, rgvswctl);
4177
4178 return true;
4179 }
4180
4181 static void ironlake_enable_drps(struct drm_device *dev)
4182 {
4183 struct drm_i915_private *dev_priv = dev->dev_private;
4184 u32 rgvmodectl;
4185 u8 fmax, fmin, fstart, vstart;
4186
4187 spin_lock_irq(&mchdev_lock);
4188
4189 rgvmodectl = I915_READ(MEMMODECTL);
4190
4191 /* Enable temp reporting */
4192 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4193 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4194
4195 /* 100ms RC evaluation intervals */
4196 I915_WRITE(RCUPEI, 100000);
4197 I915_WRITE(RCDNEI, 100000);
4198
4199 /* Set max/min thresholds to 90ms and 80ms respectively */
4200 I915_WRITE(RCBMAXAVG, 90000);
4201 I915_WRITE(RCBMINAVG, 80000);
4202
4203 I915_WRITE(MEMIHYST, 1);
4204
4205 /* Set up min, max, and cur for interrupt handling */
4206 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4207 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4208 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4209 MEMMODE_FSTART_SHIFT;
4210
4211 vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
4212 PXVFREQ_PX_SHIFT;
4213
4214 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4215 dev_priv->ips.fstart = fstart;
4216
4217 dev_priv->ips.max_delay = fstart;
4218 dev_priv->ips.min_delay = fmin;
4219 dev_priv->ips.cur_delay = fstart;
4220
4221 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4222 fmax, fmin, fstart);
4223
4224 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4225
4226 /*
4227 * Interrupts will be enabled in ironlake_irq_postinstall
4228 */
4229
4230 I915_WRITE(VIDSTART, vstart);
4231 POSTING_READ(VIDSTART);
4232
4233 rgvmodectl |= MEMMODE_SWMODE_EN;
4234 I915_WRITE(MEMMODECTL, rgvmodectl);
4235
4236 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
4237 DRM_ERROR("stuck trying to change perf mode\n");
4238 mdelay(1);
4239
4240 ironlake_set_drps(dev, fstart);
4241
4242 dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4243 I915_READ(DDREC) + I915_READ(CSIEC);
4244 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
4245 dev_priv->ips.last_count2 = I915_READ(GFXEC);
4246 dev_priv->ips.last_time2 = ktime_get_raw_ns();
4247
4248 spin_unlock_irq(&mchdev_lock);
4249 }
4250
4251 static void ironlake_disable_drps(struct drm_device *dev)
4252 {
4253 struct drm_i915_private *dev_priv = dev->dev_private;
4254 u16 rgvswctl;
4255
4256 spin_lock_irq(&mchdev_lock);
4257
4258 rgvswctl = I915_READ16(MEMSWCTL);
4259
4260 /* Ack interrupts, disable EFC interrupt */
4261 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4262 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4263 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4264 I915_WRITE(DEIIR, DE_PCU_EVENT);
4265 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4266
4267 /* Go back to the starting frequency */
4268 ironlake_set_drps(dev, dev_priv->ips.fstart);
4269 mdelay(1);
4270 rgvswctl |= MEMCTL_CMD_STS;
4271 I915_WRITE(MEMSWCTL, rgvswctl);
4272 mdelay(1);
4273
4274 spin_unlock_irq(&mchdev_lock);
4275 }
4276
4277 /* There's a funny hw issue where the hw returns all 0 when reading from
4278 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4279 * ourselves, instead of doing a rmw cycle (which might result in us clearing
4280 * all limits and the gpu stuck at whatever frequency it is at atm).
4281 */
4282 static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
4283 {
4284 u32 limits;
4285
4286 /* Only set the down limit when we've reached the lowest level to avoid
4287 * getting more interrupts, otherwise leave this clear. This prevents a
4288 * race in the hw when coming out of rc6: There's a tiny window where
4289 * the hw runs at the minimal clock before selecting the desired
4290 * frequency, if the down threshold expires in that window we will not
4291 * receive a down interrupt. */
4292 if (IS_GEN9(dev_priv->dev)) {
4293 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4294 if (val <= dev_priv->rps.min_freq_softlimit)
4295 limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4296 } else {
4297 limits = dev_priv->rps.max_freq_softlimit << 24;
4298 if (val <= dev_priv->rps.min_freq_softlimit)
4299 limits |= dev_priv->rps.min_freq_softlimit << 16;
4300 }
4301
4302 return limits;
4303 }
4304
4305 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4306 {
4307 int new_power;
4308 u32 threshold_up = 0, threshold_down = 0; /* in % */
4309 u32 ei_up = 0, ei_down = 0;
4310
4311 new_power = dev_priv->rps.power;
4312 switch (dev_priv->rps.power) {
4313 case LOW_POWER:
4314 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
4315 new_power = BETWEEN;
4316 break;
4317
4318 case BETWEEN:
4319 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
4320 new_power = LOW_POWER;
4321 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
4322 new_power = HIGH_POWER;
4323 break;
4324
4325 case HIGH_POWER:
4326 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
4327 new_power = BETWEEN;
4328 break;
4329 }
4330 /* Max/min bins are special */
4331 if (val <= dev_priv->rps.min_freq_softlimit)
4332 new_power = LOW_POWER;
4333 if (val >= dev_priv->rps.max_freq_softlimit)
4334 new_power = HIGH_POWER;
4335 if (new_power == dev_priv->rps.power)
4336 return;
4337
4338 /* Note the units here are not exactly 1us, but 1280ns. */
4339 switch (new_power) {
4340 case LOW_POWER:
4341 /* Upclock if more than 95% busy over 16ms */
4342 ei_up = 16000;
4343 threshold_up = 95;
4344
4345 /* Downclock if less than 85% busy over 32ms */
4346 ei_down = 32000;
4347 threshold_down = 85;
4348 break;
4349
4350 case BETWEEN:
4351 /* Upclock if more than 90% busy over 13ms */
4352 ei_up = 13000;
4353 threshold_up = 90;
4354
4355 /* Downclock if less than 75% busy over 32ms */
4356 ei_down = 32000;
4357 threshold_down = 75;
4358 break;
4359
4360 case HIGH_POWER:
4361 /* Upclock if more than 85% busy over 10ms */
4362 ei_up = 10000;
4363 threshold_up = 85;
4364
4365 /* Downclock if less than 60% busy over 32ms */
4366 ei_down = 32000;
4367 threshold_down = 60;
4368 break;
4369 }
4370
4371 I915_WRITE(GEN6_RP_UP_EI,
4372 GT_INTERVAL_FROM_US(dev_priv, ei_up));
4373 I915_WRITE(GEN6_RP_UP_THRESHOLD,
4374 GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100)));
4375
4376 I915_WRITE(GEN6_RP_DOWN_EI,
4377 GT_INTERVAL_FROM_US(dev_priv, ei_down));
4378 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4379 GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100)));
4380
4381 I915_WRITE(GEN6_RP_CONTROL,
4382 GEN6_RP_MEDIA_TURBO |
4383 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4384 GEN6_RP_MEDIA_IS_GFX |
4385 GEN6_RP_ENABLE |
4386 GEN6_RP_UP_BUSY_AVG |
4387 GEN6_RP_DOWN_IDLE_AVG);
4388
4389 dev_priv->rps.power = new_power;
4390 dev_priv->rps.up_threshold = threshold_up;
4391 dev_priv->rps.down_threshold = threshold_down;
4392 dev_priv->rps.last_adj = 0;
4393 }
4394
4395 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4396 {
4397 u32 mask = 0;
4398
4399 if (val > dev_priv->rps.min_freq_softlimit)
4400 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
4401 if (val < dev_priv->rps.max_freq_softlimit)
4402 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
4403
4404 mask &= dev_priv->pm_rps_events;
4405
4406 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
4407 }
4408
4409 /* gen6_set_rps is called to update the frequency request, but should also be
4410 * called when the range (min_delay and max_delay) is modified so that we can
4411 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
4412 static void gen6_set_rps(struct drm_device *dev, u8 val)
4413 {
4414 struct drm_i915_private *dev_priv = dev->dev_private;
4415
4416 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4417 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
4418 return;
4419
4420 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4421 WARN_ON(val > dev_priv->rps.max_freq);
4422 WARN_ON(val < dev_priv->rps.min_freq);
4423
4424 /* min/max delay may still have been modified so be sure to
4425 * write the limits value.
4426 */
4427 if (val != dev_priv->rps.cur_freq) {
4428 gen6_set_rps_thresholds(dev_priv, val);
4429
4430 if (IS_GEN9(dev))
4431 I915_WRITE(GEN6_RPNSWREQ,
4432 GEN9_FREQUENCY(val));
4433 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4434 I915_WRITE(GEN6_RPNSWREQ,
4435 HSW_FREQUENCY(val));
4436 else
4437 I915_WRITE(GEN6_RPNSWREQ,
4438 GEN6_FREQUENCY(val) |
4439 GEN6_OFFSET(0) |
4440 GEN6_AGGRESSIVE_TURBO);
4441 }
4442
4443 /* Make sure we continue to get interrupts
4444 * until we hit the minimum or maximum frequencies.
4445 */
4446 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
4447 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4448
4449 POSTING_READ(GEN6_RPNSWREQ);
4450
4451 dev_priv->rps.cur_freq = val;
4452 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4453 }
4454
4455 static void valleyview_set_rps(struct drm_device *dev, u8 val)
4456 {
4457 struct drm_i915_private *dev_priv = dev->dev_private;
4458
4459 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4460 WARN_ON(val > dev_priv->rps.max_freq);
4461 WARN_ON(val < dev_priv->rps.min_freq);
4462
4463 if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1),
4464 "Odd GPU freq value\n"))
4465 val &= ~1;
4466
4467 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4468
4469 if (val != dev_priv->rps.cur_freq) {
4470 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
4471 if (!IS_CHERRYVIEW(dev_priv))
4472 gen6_set_rps_thresholds(dev_priv, val);
4473 }
4474
4475 dev_priv->rps.cur_freq = val;
4476 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4477 }
4478
4479 /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
4480 *
4481 * * If Gfx is Idle, then
4482 * 1. Forcewake Media well.
4483 * 2. Request idle freq.
4484 * 3. Release Forcewake of Media well.
4485 */
4486 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4487 {
4488 u32 val = dev_priv->rps.idle_freq;
4489
4490 if (dev_priv->rps.cur_freq <= val)
4491 return;
4492
4493 /* Wake up the media well, as that takes a lot less
4494 * power than the Render well. */
4495 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
4496 valleyview_set_rps(dev_priv->dev, val);
4497 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
4498 }
4499
4500 void gen6_rps_busy(struct drm_i915_private *dev_priv)
4501 {
4502 mutex_lock(&dev_priv->rps.hw_lock);
4503 if (dev_priv->rps.enabled) {
4504 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
4505 gen6_rps_reset_ei(dev_priv);
4506 I915_WRITE(GEN6_PMINTRMSK,
4507 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
4508 }
4509 mutex_unlock(&dev_priv->rps.hw_lock);
4510 }
4511
4512 void gen6_rps_idle(struct drm_i915_private *dev_priv)
4513 {
4514 struct drm_device *dev = dev_priv->dev;
4515
4516 mutex_lock(&dev_priv->rps.hw_lock);
4517 if (dev_priv->rps.enabled) {
4518 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
4519 vlv_set_rps_idle(dev_priv);
4520 else
4521 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
4522 dev_priv->rps.last_adj = 0;
4523 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
4524 }
4525 mutex_unlock(&dev_priv->rps.hw_lock);
4526
4527 spin_lock(&dev_priv->rps.client_lock);
4528 while (!list_empty(&dev_priv->rps.clients))
4529 list_del_init(dev_priv->rps.clients.next);
4530 spin_unlock(&dev_priv->rps.client_lock);
4531 }
4532
4533 void gen6_rps_boost(struct drm_i915_private *dev_priv,
4534 struct intel_rps_client *rps,
4535 unsigned long submitted)
4536 {
4537 /* This is intentionally racy! We peek at the state here, then
4538 * validate inside the RPS worker.
4539 */
4540 if (!(dev_priv->mm.busy &&
4541 dev_priv->rps.enabled &&
4542 dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit))
4543 return;
4544
4545 /* Force a RPS boost (and don't count it against the client) if
4546 * the GPU is severely congested.
4547 */
4548 if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
4549 rps = NULL;
4550
4551 spin_lock(&dev_priv->rps.client_lock);
4552 if (rps == NULL || list_empty(&rps->link)) {
4553 spin_lock_irq(&dev_priv->irq_lock);
4554 if (dev_priv->rps.interrupts_enabled) {
4555 dev_priv->rps.client_boost = true;
4556 queue_work(dev_priv->wq, &dev_priv->rps.work);
4557 }
4558 spin_unlock_irq(&dev_priv->irq_lock);
4559
4560 if (rps != NULL) {
4561 list_add(&rps->link, &dev_priv->rps.clients);
4562 rps->boosts++;
4563 } else
4564 dev_priv->rps.boosts++;
4565 }
4566 spin_unlock(&dev_priv->rps.client_lock);
4567 }
4568
4569 void intel_set_rps(struct drm_device *dev, u8 val)
4570 {
4571 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
4572 valleyview_set_rps(dev, val);
4573 else
4574 gen6_set_rps(dev, val);
4575 }
4576
4577 static void gen9_disable_rps(struct drm_device *dev)
4578 {
4579 struct drm_i915_private *dev_priv = dev->dev_private;
4580
4581 I915_WRITE(GEN6_RC_CONTROL, 0);
4582 I915_WRITE(GEN9_PG_ENABLE, 0);
4583 }
4584
4585 static void gen6_disable_rps(struct drm_device *dev)
4586 {
4587 struct drm_i915_private *dev_priv = dev->dev_private;
4588
4589 I915_WRITE(GEN6_RC_CONTROL, 0);
4590 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
4591 }
4592
4593 static void cherryview_disable_rps(struct drm_device *dev)
4594 {
4595 struct drm_i915_private *dev_priv = dev->dev_private;
4596
4597 I915_WRITE(GEN6_RC_CONTROL, 0);
4598 }
4599
4600 static void valleyview_disable_rps(struct drm_device *dev)
4601 {
4602 struct drm_i915_private *dev_priv = dev->dev_private;
4603
4604 /* we're doing forcewake before Disabling RC6,
4605 * This what the BIOS expects when going into suspend */
4606 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4607
4608 I915_WRITE(GEN6_RC_CONTROL, 0);
4609
4610 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4611 }
4612
4613 static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
4614 {
4615 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
4616 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
4617 mode = GEN6_RC_CTL_RC6_ENABLE;
4618 else
4619 mode = 0;
4620 }
4621 if (HAS_RC6p(dev))
4622 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
4623 onoff(mode & GEN6_RC_CTL_RC6_ENABLE),
4624 onoff(mode & GEN6_RC_CTL_RC6p_ENABLE),
4625 onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE));
4626
4627 else
4628 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
4629 onoff(mode & GEN6_RC_CTL_RC6_ENABLE));
4630 }
4631
4632 static bool bxt_check_bios_rc6_setup(const struct drm_device *dev)
4633 {
4634 struct drm_i915_private *dev_priv = dev->dev_private;
4635 bool enable_rc6 = true;
4636 unsigned long rc6_ctx_base;
4637
4638 if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
4639 DRM_DEBUG_KMS("RC6 Base location not set properly.\n");
4640 enable_rc6 = false;
4641 }
4642
4643 /*
4644 * The exact context size is not known for BXT, so assume a page size
4645 * for this check.
4646 */
4647 rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
4648 if (!((rc6_ctx_base >= dev_priv->gtt.stolen_reserved_base) &&
4649 (rc6_ctx_base + PAGE_SIZE <= dev_priv->gtt.stolen_reserved_base +
4650 dev_priv->gtt.stolen_reserved_size))) {
4651 DRM_DEBUG_KMS("RC6 Base address not as expected.\n");
4652 enable_rc6 = false;
4653 }
4654
4655 if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) &&
4656 ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) &&
4657 ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) &&
4658 ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) {
4659 DRM_DEBUG_KMS("Engine Idle wait time not set properly.\n");
4660 enable_rc6 = false;
4661 }
4662
4663 if (!(I915_READ(GEN6_RC_CONTROL) & (GEN6_RC_CTL_RC6_ENABLE |
4664 GEN6_RC_CTL_HW_ENABLE)) &&
4665 ((I915_READ(GEN6_RC_CONTROL) & GEN6_RC_CTL_HW_ENABLE) ||
4666 !(I915_READ(GEN6_RC_STATE) & RC6_STATE))) {
4667 DRM_DEBUG_KMS("HW/SW RC6 is not enabled by BIOS.\n");
4668 enable_rc6 = false;
4669 }
4670
4671 return enable_rc6;
4672 }
4673
4674 int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
4675 {
4676 /* No RC6 before Ironlake and code is gone for ilk. */
4677 if (INTEL_INFO(dev)->gen < 6)
4678 return 0;
4679
4680 if (!enable_rc6)
4681 return 0;
4682
4683 if (IS_BROXTON(dev) && !bxt_check_bios_rc6_setup(dev)) {
4684 DRM_INFO("RC6 disabled by BIOS\n");
4685 return 0;
4686 }
4687
4688 /* Respect the kernel parameter if it is set */
4689 if (enable_rc6 >= 0) {
4690 int mask;
4691
4692 if (HAS_RC6p(dev))
4693 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
4694 INTEL_RC6pp_ENABLE;
4695 else
4696 mask = INTEL_RC6_ENABLE;
4697
4698 if ((enable_rc6 & mask) != enable_rc6)
4699 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
4700 enable_rc6 & mask, enable_rc6, mask);
4701
4702 return enable_rc6 & mask;
4703 }
4704
4705 if (IS_IVYBRIDGE(dev))
4706 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
4707
4708 return INTEL_RC6_ENABLE;
4709 }
4710
4711 int intel_enable_rc6(const struct drm_device *dev)
4712 {
4713 return i915.enable_rc6;
4714 }
4715
4716 static void gen6_init_rps_frequencies(struct drm_device *dev)
4717 {
4718 struct drm_i915_private *dev_priv = dev->dev_private;
4719 uint32_t rp_state_cap;
4720 u32 ddcc_status = 0;
4721 int ret;
4722
4723 /* All of these values are in units of 50MHz */
4724 dev_priv->rps.cur_freq = 0;
4725 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
4726 if (IS_BROXTON(dev)) {
4727 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
4728 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
4729 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
4730 dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff;
4731 } else {
4732 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
4733 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
4734 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
4735 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
4736 }
4737
4738 /* hw_max = RP0 until we check for overclocking */
4739 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
4740
4741 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
4742 if (IS_HASWELL(dev) || IS_BROADWELL(dev) ||
4743 IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
4744 ret = sandybridge_pcode_read(dev_priv,
4745 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
4746 &ddcc_status);
4747 if (0 == ret)
4748 dev_priv->rps.efficient_freq =
4749 clamp_t(u8,
4750 ((ddcc_status >> 8) & 0xff),
4751 dev_priv->rps.min_freq,
4752 dev_priv->rps.max_freq);
4753 }
4754
4755 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
4756 /* Store the frequency values in 16.66 MHZ units, which is
4757 the natural hardware unit for SKL */
4758 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
4759 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
4760 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
4761 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
4762 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
4763 }
4764
4765 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
4766
4767 /* Preserve min/max settings in case of re-init */
4768 if (dev_priv->rps.max_freq_softlimit == 0)
4769 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4770
4771 if (dev_priv->rps.min_freq_softlimit == 0) {
4772 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4773 dev_priv->rps.min_freq_softlimit =
4774 max_t(int, dev_priv->rps.efficient_freq,
4775 intel_freq_opcode(dev_priv, 450));
4776 else
4777 dev_priv->rps.min_freq_softlimit =
4778 dev_priv->rps.min_freq;
4779 }
4780 }
4781
4782 /* See the Gen9_GT_PM_Programming_Guide doc for the below */
4783 static void gen9_enable_rps(struct drm_device *dev)
4784 {
4785 struct drm_i915_private *dev_priv = dev->dev_private;
4786
4787 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4788
4789 gen6_init_rps_frequencies(dev);
4790
4791 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4792 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
4793 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4794 return;
4795 }
4796
4797 /* Program defaults and thresholds for RPS*/
4798 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4799 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
4800
4801 /* 1 second timeout*/
4802 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
4803 GT_INTERVAL_FROM_US(dev_priv, 1000000));
4804
4805 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
4806
4807 /* Leaning on the below call to gen6_set_rps to program/setup the
4808 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
4809 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
4810 dev_priv->rps.power = HIGH_POWER; /* force a reset */
4811 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
4812
4813 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4814 }
4815
4816 static void gen9_enable_rc6(struct drm_device *dev)
4817 {
4818 struct drm_i915_private *dev_priv = dev->dev_private;
4819 struct intel_engine_cs *ring;
4820 uint32_t rc6_mask = 0;
4821 int unused;
4822
4823 /* 1a: Software RC state - RC0 */
4824 I915_WRITE(GEN6_RC_STATE, 0);
4825
4826 /* 1b: Get forcewake during program sequence. Although the driver
4827 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4828 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4829
4830 /* 2a: Disable RC states. */
4831 I915_WRITE(GEN6_RC_CONTROL, 0);
4832
4833 /* 2b: Program RC6 thresholds.*/
4834
4835 /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
4836 if (IS_SKYLAKE(dev))
4837 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
4838 else
4839 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
4840 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4841 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4842 for_each_ring(ring, dev_priv, unused)
4843 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4844
4845 if (HAS_GUC_UCODE(dev))
4846 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
4847
4848 I915_WRITE(GEN6_RC_SLEEP, 0);
4849
4850 /* 2c: Program Coarse Power Gating Policies. */
4851 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
4852 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
4853
4854 /* 3a: Enable RC6 */
4855 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4856 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4857 DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
4858 /* WaRsUseTimeoutMode */
4859 if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) ||
4860 IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
4861 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
4862 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4863 GEN7_RC_CTL_TO_MODE |
4864 rc6_mask);
4865 } else {
4866 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
4867 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4868 GEN6_RC_CTL_EI_MODE(1) |
4869 rc6_mask);
4870 }
4871
4872 /*
4873 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
4874 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
4875 */
4876 if (NEEDS_WaRsDisableCoarsePowerGating(dev))
4877 I915_WRITE(GEN9_PG_ENABLE, 0);
4878 else
4879 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4880 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
4881
4882 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4883
4884 }
4885
4886 static void gen8_enable_rps(struct drm_device *dev)
4887 {
4888 struct drm_i915_private *dev_priv = dev->dev_private;
4889 struct intel_engine_cs *ring;
4890 uint32_t rc6_mask = 0;
4891 int unused;
4892
4893 /* 1a: Software RC state - RC0 */
4894 I915_WRITE(GEN6_RC_STATE, 0);
4895
4896 /* 1c & 1d: Get forcewake during program sequence. Although the driver
4897 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4898 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4899
4900 /* 2a: Disable RC states. */
4901 I915_WRITE(GEN6_RC_CONTROL, 0);
4902
4903 /* Initialize rps frequencies */
4904 gen6_init_rps_frequencies(dev);
4905
4906 /* 2b: Program RC6 thresholds.*/
4907 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4908 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4909 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4910 for_each_ring(ring, dev_priv, unused)
4911 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4912 I915_WRITE(GEN6_RC_SLEEP, 0);
4913 if (IS_BROADWELL(dev))
4914 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
4915 else
4916 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
4917
4918 /* 3: Enable RC6 */
4919 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4920 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4921 intel_print_rc6_info(dev, rc6_mask);
4922 if (IS_BROADWELL(dev))
4923 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4924 GEN7_RC_CTL_TO_MODE |
4925 rc6_mask);
4926 else
4927 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4928 GEN6_RC_CTL_EI_MODE(1) |
4929 rc6_mask);
4930
4931 /* 4 Program defaults and thresholds for RPS*/
4932 I915_WRITE(GEN6_RPNSWREQ,
4933 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4934 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4935 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4936 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
4937 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
4938
4939 /* Docs recommend 900MHz, and 300 MHz respectively */
4940 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
4941 dev_priv->rps.max_freq_softlimit << 24 |
4942 dev_priv->rps.min_freq_softlimit << 16);
4943
4944 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
4945 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
4946 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
4947 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
4948
4949 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4950
4951 /* 5: Enable RPS */
4952 I915_WRITE(GEN6_RP_CONTROL,
4953 GEN6_RP_MEDIA_TURBO |
4954 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4955 GEN6_RP_MEDIA_IS_GFX |
4956 GEN6_RP_ENABLE |
4957 GEN6_RP_UP_BUSY_AVG |
4958 GEN6_RP_DOWN_IDLE_AVG);
4959
4960 /* 6: Ring frequency + overclocking (our driver does this later */
4961
4962 dev_priv->rps.power = HIGH_POWER; /* force a reset */
4963 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
4964
4965 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4966 }
4967
4968 static void gen6_enable_rps(struct drm_device *dev)
4969 {
4970 struct drm_i915_private *dev_priv = dev->dev_private;
4971 struct intel_engine_cs *ring;
4972 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
4973 u32 gtfifodbg;
4974 int rc6_mode;
4975 int i, ret;
4976
4977 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4978
4979 /* Here begins a magic sequence of register writes to enable
4980 * auto-downclocking.
4981 *
4982 * Perhaps there might be some value in exposing these to
4983 * userspace...
4984 */
4985 I915_WRITE(GEN6_RC_STATE, 0);
4986
4987 /* Clear the DBG now so we don't confuse earlier errors */
4988 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
4989 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
4990 I915_WRITE(GTFIFODBG, gtfifodbg);
4991 }
4992
4993 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4994
4995 /* Initialize rps frequencies */
4996 gen6_init_rps_frequencies(dev);
4997
4998 /* disable the counters and set deterministic thresholds */
4999 I915_WRITE(GEN6_RC_CONTROL, 0);
5000
5001 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
5002 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
5003 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
5004 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5005 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5006
5007 for_each_ring(ring, dev_priv, i)
5008 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5009
5010 I915_WRITE(GEN6_RC_SLEEP, 0);
5011 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
5012 if (IS_IVYBRIDGE(dev))
5013 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
5014 else
5015 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
5016 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
5017 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
5018
5019 /* Check if we are enabling RC6 */
5020 rc6_mode = intel_enable_rc6(dev_priv->dev);
5021 if (rc6_mode & INTEL_RC6_ENABLE)
5022 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
5023
5024 /* We don't use those on Haswell */
5025 if (!IS_HASWELL(dev)) {
5026 if (rc6_mode & INTEL_RC6p_ENABLE)
5027 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
5028
5029 if (rc6_mode & INTEL_RC6pp_ENABLE)
5030 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
5031 }
5032
5033 intel_print_rc6_info(dev, rc6_mask);
5034
5035 I915_WRITE(GEN6_RC_CONTROL,
5036 rc6_mask |
5037 GEN6_RC_CTL_EI_MODE(1) |
5038 GEN6_RC_CTL_HW_ENABLE);
5039
5040 /* Power down if completely idle for over 50ms */
5041 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
5042 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5043
5044 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
5045 if (ret)
5046 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
5047
5048 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
5049 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
5050 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
5051 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
5052 (pcu_mbox & 0xff) * 50);
5053 dev_priv->rps.max_freq = pcu_mbox & 0xff;
5054 }
5055
5056 dev_priv->rps.power = HIGH_POWER; /* force a reset */
5057 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
5058
5059 rc6vids = 0;
5060 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
5061 if (IS_GEN6(dev) && ret) {
5062 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
5063 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
5064 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5065 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5066 rc6vids &= 0xffff00;
5067 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5068 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5069 if (ret)
5070 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5071 }
5072
5073 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5074 }
5075
5076 static void __gen6_update_ring_freq(struct drm_device *dev)
5077 {
5078 struct drm_i915_private *dev_priv = dev->dev_private;
5079 int min_freq = 15;
5080 unsigned int gpu_freq;
5081 unsigned int max_ia_freq, min_ring_freq;
5082 unsigned int max_gpu_freq, min_gpu_freq;
5083 int scaling_factor = 180;
5084 struct cpufreq_policy *policy;
5085
5086 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5087
5088 policy = cpufreq_cpu_get(0);
5089 if (policy) {
5090 max_ia_freq = policy->cpuinfo.max_freq;
5091 cpufreq_cpu_put(policy);
5092 } else {
5093 /*
5094 * Default to measured freq if none found, PCU will ensure we
5095 * don't go over
5096 */
5097 max_ia_freq = tsc_khz;
5098 }
5099
5100 /* Convert from kHz to MHz */
5101 max_ia_freq /= 1000;
5102
5103 min_ring_freq = I915_READ(DCLK) & 0xf;
5104 /* convert DDR frequency from units of 266.6MHz to bandwidth */
5105 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
5106
5107 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5108 /* Convert GT frequency to 50 HZ units */
5109 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5110 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5111 } else {
5112 min_gpu_freq = dev_priv->rps.min_freq;
5113 max_gpu_freq = dev_priv->rps.max_freq;
5114 }
5115
5116 /*
5117 * For each potential GPU frequency, load a ring frequency we'd like
5118 * to use for memory access. We do this by specifying the IA frequency
5119 * the PCU should use as a reference to determine the ring frequency.
5120 */
5121 for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5122 int diff = max_gpu_freq - gpu_freq;
5123 unsigned int ia_freq = 0, ring_freq = 0;
5124
5125 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5126 /*
5127 * ring_freq = 2 * GT. ring_freq is in 100MHz units
5128 * No floor required for ring frequency on SKL.
5129 */
5130 ring_freq = gpu_freq;
5131 } else if (INTEL_INFO(dev)->gen >= 8) {
5132 /* max(2 * GT, DDR). NB: GT is 50MHz units */
5133 ring_freq = max(min_ring_freq, gpu_freq);
5134 } else if (IS_HASWELL(dev)) {
5135 ring_freq = mult_frac(gpu_freq, 5, 4);
5136 ring_freq = max(min_ring_freq, ring_freq);
5137 /* leave ia_freq as the default, chosen by cpufreq */
5138 } else {
5139 /* On older processors, there is no separate ring
5140 * clock domain, so in order to boost the bandwidth
5141 * of the ring, we need to upclock the CPU (ia_freq).
5142 *
5143 * For GPU frequencies less than 750MHz,
5144 * just use the lowest ring freq.
5145 */
5146 if (gpu_freq < min_freq)
5147 ia_freq = 800;
5148 else
5149 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5150 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5151 }
5152
5153 sandybridge_pcode_write(dev_priv,
5154 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
5155 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5156 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5157 gpu_freq);
5158 }
5159 }
5160
5161 void gen6_update_ring_freq(struct drm_device *dev)
5162 {
5163 struct drm_i915_private *dev_priv = dev->dev_private;
5164
5165 if (!HAS_CORE_RING_FREQ(dev))
5166 return;
5167
5168 mutex_lock(&dev_priv->rps.hw_lock);
5169 __gen6_update_ring_freq(dev);
5170 mutex_unlock(&dev_priv->rps.hw_lock);
5171 }
5172
5173 static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
5174 {
5175 struct drm_device *dev = dev_priv->dev;
5176 u32 val, rp0;
5177
5178 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5179
5180 switch (INTEL_INFO(dev)->eu_total) {
5181 case 8:
5182 /* (2 * 4) config */
5183 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5184 break;
5185 case 12:
5186 /* (2 * 6) config */
5187 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5188 break;
5189 case 16:
5190 /* (2 * 8) config */
5191 default:
5192 /* Setting (2 * 8) Min RP0 for any other combination */
5193 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5194 break;
5195 }
5196
5197 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5198
5199 return rp0;
5200 }
5201
5202 static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5203 {
5204 u32 val, rpe;
5205
5206 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5207 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5208
5209 return rpe;
5210 }
5211
5212 static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5213 {
5214 u32 val, rp1;
5215
5216 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5217 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5218
5219 return rp1;
5220 }
5221
5222 static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5223 {
5224 u32 val, rp1;
5225
5226 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5227
5228 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5229
5230 return rp1;
5231 }
5232
5233 static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
5234 {
5235 u32 val, rp0;
5236
5237 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5238
5239 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5240 /* Clamp to max */
5241 rp0 = min_t(u32, rp0, 0xea);
5242
5243 return rp0;
5244 }
5245
5246 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5247 {
5248 u32 val, rpe;
5249
5250 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
5251 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
5252 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
5253 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5254
5255 return rpe;
5256 }
5257
5258 static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
5259 {
5260 u32 val;
5261
5262 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5263 /*
5264 * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
5265 * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
5266 * a BYT-M B0 the above register contains 0xbf. Moreover when setting
5267 * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
5268 * to make sure it matches what Punit accepts.
5269 */
5270 return max_t(u32, val, 0xc0);
5271 }
5272
5273 /* Check that the pctx buffer wasn't move under us. */
5274 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5275 {
5276 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5277
5278 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5279 dev_priv->vlv_pctx->stolen->start);
5280 }
5281
5282
5283 /* Check that the pcbr address is not empty. */
5284 static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5285 {
5286 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5287
5288 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5289 }
5290
5291 static void cherryview_setup_pctx(struct drm_device *dev)
5292 {
5293 struct drm_i915_private *dev_priv = dev->dev_private;
5294 unsigned long pctx_paddr, paddr;
5295 struct i915_gtt *gtt = &dev_priv->gtt;
5296 u32 pcbr;
5297 int pctx_size = 32*1024;
5298
5299 pcbr = I915_READ(VLV_PCBR);
5300 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
5301 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5302 paddr = (dev_priv->mm.stolen_base +
5303 (gtt->stolen_size - pctx_size));
5304
5305 pctx_paddr = (paddr & (~4095));
5306 I915_WRITE(VLV_PCBR, pctx_paddr);
5307 }
5308
5309 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5310 }
5311
5312 static void valleyview_setup_pctx(struct drm_device *dev)
5313 {
5314 struct drm_i915_private *dev_priv = dev->dev_private;
5315 struct drm_i915_gem_object *pctx;
5316 unsigned long pctx_paddr;
5317 u32 pcbr;
5318 int pctx_size = 24*1024;
5319
5320 mutex_lock(&dev->struct_mutex);
5321
5322 pcbr = I915_READ(VLV_PCBR);
5323 if (pcbr) {
5324 /* BIOS set it up already, grab the pre-alloc'd space */
5325 int pcbr_offset;
5326
5327 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
5328 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
5329 pcbr_offset,
5330 I915_GTT_OFFSET_NONE,
5331 pctx_size);
5332 goto out;
5333 }
5334
5335 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5336
5337 /*
5338 * From the Gunit register HAS:
5339 * The Gfx driver is expected to program this register and ensure
5340 * proper allocation within Gfx stolen memory. For example, this
5341 * register should be programmed such than the PCBR range does not
5342 * overlap with other ranges, such as the frame buffer, protected
5343 * memory, or any other relevant ranges.
5344 */
5345 pctx = i915_gem_object_create_stolen(dev, pctx_size);
5346 if (!pctx) {
5347 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
5348 goto out;
5349 }
5350
5351 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5352 I915_WRITE(VLV_PCBR, pctx_paddr);
5353
5354 out:
5355 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5356 dev_priv->vlv_pctx = pctx;
5357 mutex_unlock(&dev->struct_mutex);
5358 }
5359
5360 static void valleyview_cleanup_pctx(struct drm_device *dev)
5361 {
5362 struct drm_i915_private *dev_priv = dev->dev_private;
5363
5364 if (WARN_ON(!dev_priv->vlv_pctx))
5365 return;
5366
5367 drm_gem_object_unreference_unlocked(&dev_priv->vlv_pctx->base);
5368 dev_priv->vlv_pctx = NULL;
5369 }
5370
5371 static void valleyview_init_gt_powersave(struct drm_device *dev)
5372 {
5373 struct drm_i915_private *dev_priv = dev->dev_private;
5374 u32 val;
5375
5376 valleyview_setup_pctx(dev);
5377
5378 mutex_lock(&dev_priv->rps.hw_lock);
5379
5380 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5381 switch ((val >> 6) & 3) {
5382 case 0:
5383 case 1:
5384 dev_priv->mem_freq = 800;
5385 break;
5386 case 2:
5387 dev_priv->mem_freq = 1066;
5388 break;
5389 case 3:
5390 dev_priv->mem_freq = 1333;
5391 break;
5392 }
5393 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5394
5395 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5396 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5397 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5398 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5399 dev_priv->rps.max_freq);
5400
5401 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5402 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5403 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5404 dev_priv->rps.efficient_freq);
5405
5406 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5407 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
5408 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5409 dev_priv->rps.rp1_freq);
5410
5411 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5412 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5413 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5414 dev_priv->rps.min_freq);
5415
5416 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5417
5418 /* Preserve min/max settings in case of re-init */
5419 if (dev_priv->rps.max_freq_softlimit == 0)
5420 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5421
5422 if (dev_priv->rps.min_freq_softlimit == 0)
5423 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5424
5425 mutex_unlock(&dev_priv->rps.hw_lock);
5426 }
5427
5428 static void cherryview_init_gt_powersave(struct drm_device *dev)
5429 {
5430 struct drm_i915_private *dev_priv = dev->dev_private;
5431 u32 val;
5432
5433 cherryview_setup_pctx(dev);
5434
5435 mutex_lock(&dev_priv->rps.hw_lock);
5436
5437 mutex_lock(&dev_priv->sb_lock);
5438 val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
5439 mutex_unlock(&dev_priv->sb_lock);
5440
5441 switch ((val >> 2) & 0x7) {
5442 case 3:
5443 dev_priv->mem_freq = 2000;
5444 break;
5445 default:
5446 dev_priv->mem_freq = 1600;
5447 break;
5448 }
5449 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5450
5451 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5452 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5453 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5454 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5455 dev_priv->rps.max_freq);
5456
5457 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5458 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5459 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5460 dev_priv->rps.efficient_freq);
5461
5462 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5463 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
5464 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5465 dev_priv->rps.rp1_freq);
5466
5467 /* PUnit validated range is only [RPe, RP0] */
5468 dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
5469 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5470 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5471 dev_priv->rps.min_freq);
5472
5473 WARN_ONCE((dev_priv->rps.max_freq |
5474 dev_priv->rps.efficient_freq |
5475 dev_priv->rps.rp1_freq |
5476 dev_priv->rps.min_freq) & 1,
5477 "Odd GPU freq values\n");
5478
5479 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5480
5481 /* Preserve min/max settings in case of re-init */
5482 if (dev_priv->rps.max_freq_softlimit == 0)
5483 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5484
5485 if (dev_priv->rps.min_freq_softlimit == 0)
5486 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5487
5488 mutex_unlock(&dev_priv->rps.hw_lock);
5489 }
5490
5491 static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
5492 {
5493 valleyview_cleanup_pctx(dev);
5494 }
5495
5496 static void cherryview_enable_rps(struct drm_device *dev)
5497 {
5498 struct drm_i915_private *dev_priv = dev->dev_private;
5499 struct intel_engine_cs *ring;
5500 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
5501 int i;
5502
5503 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5504
5505 gtfifodbg = I915_READ(GTFIFODBG);
5506 if (gtfifodbg) {
5507 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5508 gtfifodbg);
5509 I915_WRITE(GTFIFODBG, gtfifodbg);
5510 }
5511
5512 cherryview_check_pctx(dev_priv);
5513
5514 /* 1a & 1b: Get forcewake during program sequence. Although the driver
5515 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5516 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5517
5518 /* Disable RC states. */
5519 I915_WRITE(GEN6_RC_CONTROL, 0);
5520
5521 /* 2a: Program RC6 thresholds.*/
5522 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5523 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5524 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5525
5526 for_each_ring(ring, dev_priv, i)
5527 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5528 I915_WRITE(GEN6_RC_SLEEP, 0);
5529
5530 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
5531 I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
5532
5533 /* allows RC6 residency counter to work */
5534 I915_WRITE(VLV_COUNTER_CONTROL,
5535 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
5536 VLV_MEDIA_RC6_COUNT_EN |
5537 VLV_RENDER_RC6_COUNT_EN));
5538
5539 /* For now we assume BIOS is allocating and populating the PCBR */
5540 pcbr = I915_READ(VLV_PCBR);
5541
5542 /* 3: Enable RC6 */
5543 if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
5544 (pcbr >> VLV_PCBR_ADDR_SHIFT))
5545 rc6_mode = GEN7_RC_CTL_TO_MODE;
5546
5547 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5548
5549 /* 4 Program defaults and thresholds for RPS*/
5550 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
5551 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5552 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5553 I915_WRITE(GEN6_RP_UP_EI, 66000);
5554 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5555
5556 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5557
5558 /* 5: Enable RPS */
5559 I915_WRITE(GEN6_RP_CONTROL,
5560 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5561 GEN6_RP_MEDIA_IS_GFX |
5562 GEN6_RP_ENABLE |
5563 GEN6_RP_UP_BUSY_AVG |
5564 GEN6_RP_DOWN_IDLE_AVG);
5565
5566 /* Setting Fixed Bias */
5567 val = VLV_OVERRIDE_EN |
5568 VLV_SOC_TDP_EN |
5569 CHV_BIAS_CPU_50_SOC_50;
5570 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5571
5572 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5573
5574 /* RPS code assumes GPLL is used */
5575 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5576
5577 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
5578 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5579
5580 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5581 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5582 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
5583 dev_priv->rps.cur_freq);
5584
5585 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5586 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5587 dev_priv->rps.efficient_freq);
5588
5589 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5590
5591 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5592 }
5593
5594 static void valleyview_enable_rps(struct drm_device *dev)
5595 {
5596 struct drm_i915_private *dev_priv = dev->dev_private;
5597 struct intel_engine_cs *ring;
5598 u32 gtfifodbg, val, rc6_mode = 0;
5599 int i;
5600
5601 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5602
5603 valleyview_check_pctx(dev_priv);
5604
5605 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
5606 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5607 gtfifodbg);
5608 I915_WRITE(GTFIFODBG, gtfifodbg);
5609 }
5610
5611 /* If VLV, Forcewake all wells, else re-direct to regular path */
5612 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5613
5614 /* Disable RC states. */
5615 I915_WRITE(GEN6_RC_CONTROL, 0);
5616
5617 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
5618 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5619 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5620 I915_WRITE(GEN6_RP_UP_EI, 66000);
5621 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5622
5623 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5624
5625 I915_WRITE(GEN6_RP_CONTROL,
5626 GEN6_RP_MEDIA_TURBO |
5627 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5628 GEN6_RP_MEDIA_IS_GFX |
5629 GEN6_RP_ENABLE |
5630 GEN6_RP_UP_BUSY_AVG |
5631 GEN6_RP_DOWN_IDLE_CONT);
5632
5633 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
5634 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5635 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5636
5637 for_each_ring(ring, dev_priv, i)
5638 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5639
5640 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
5641
5642 /* allows RC6 residency counter to work */
5643 I915_WRITE(VLV_COUNTER_CONTROL,
5644 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
5645 VLV_RENDER_RC0_COUNT_EN |
5646 VLV_MEDIA_RC6_COUNT_EN |
5647 VLV_RENDER_RC6_COUNT_EN));
5648
5649 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
5650 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
5651
5652 intel_print_rc6_info(dev, rc6_mode);
5653
5654 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5655
5656 /* Setting Fixed Bias */
5657 val = VLV_OVERRIDE_EN |
5658 VLV_SOC_TDP_EN |
5659 VLV_BIAS_CPU_125_SOC_875;
5660 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5661
5662 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5663
5664 /* RPS code assumes GPLL is used */
5665 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5666
5667 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
5668 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5669
5670 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5671 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5672 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
5673 dev_priv->rps.cur_freq);
5674
5675 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5676 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5677 dev_priv->rps.efficient_freq);
5678
5679 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5680
5681 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5682 }
5683
5684 static unsigned long intel_pxfreq(u32 vidfreq)
5685 {
5686 unsigned long freq;
5687 int div = (vidfreq & 0x3f0000) >> 16;
5688 int post = (vidfreq & 0x3000) >> 12;
5689 int pre = (vidfreq & 0x7);
5690
5691 if (!pre)
5692 return 0;
5693
5694 freq = ((div * 133333) / ((1<<post) * pre));
5695
5696 return freq;
5697 }
5698
5699 static const struct cparams {
5700 u16 i;
5701 u16 t;
5702 u16 m;
5703 u16 c;
5704 } cparams[] = {
5705 { 1, 1333, 301, 28664 },
5706 { 1, 1066, 294, 24460 },
5707 { 1, 800, 294, 25192 },
5708 { 0, 1333, 276, 27605 },
5709 { 0, 1066, 276, 27605 },
5710 { 0, 800, 231, 23784 },
5711 };
5712
5713 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
5714 {
5715 u64 total_count, diff, ret;
5716 u32 count1, count2, count3, m = 0, c = 0;
5717 unsigned long now = jiffies_to_msecs(jiffies), diff1;
5718 int i;
5719
5720 assert_spin_locked(&mchdev_lock);
5721
5722 diff1 = now - dev_priv->ips.last_time1;
5723
5724 /* Prevent division-by-zero if we are asking too fast.
5725 * Also, we don't get interesting results if we are polling
5726 * faster than once in 10ms, so just return the saved value
5727 * in such cases.
5728 */
5729 if (diff1 <= 10)
5730 return dev_priv->ips.chipset_power;
5731
5732 count1 = I915_READ(DMIEC);
5733 count2 = I915_READ(DDREC);
5734 count3 = I915_READ(CSIEC);
5735
5736 total_count = count1 + count2 + count3;
5737
5738 /* FIXME: handle per-counter overflow */
5739 if (total_count < dev_priv->ips.last_count1) {
5740 diff = ~0UL - dev_priv->ips.last_count1;
5741 diff += total_count;
5742 } else {
5743 diff = total_count - dev_priv->ips.last_count1;
5744 }
5745
5746 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
5747 if (cparams[i].i == dev_priv->ips.c_m &&
5748 cparams[i].t == dev_priv->ips.r_t) {
5749 m = cparams[i].m;
5750 c = cparams[i].c;
5751 break;
5752 }
5753 }
5754
5755 diff = div_u64(diff, diff1);
5756 ret = ((m * diff) + c);
5757 ret = div_u64(ret, 10);
5758
5759 dev_priv->ips.last_count1 = total_count;
5760 dev_priv->ips.last_time1 = now;
5761
5762 dev_priv->ips.chipset_power = ret;
5763
5764 return ret;
5765 }
5766
5767 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
5768 {
5769 struct drm_device *dev = dev_priv->dev;
5770 unsigned long val;
5771
5772 if (INTEL_INFO(dev)->gen != 5)
5773 return 0;
5774
5775 spin_lock_irq(&mchdev_lock);
5776
5777 val = __i915_chipset_val(dev_priv);
5778
5779 spin_unlock_irq(&mchdev_lock);
5780
5781 return val;
5782 }
5783
5784 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
5785 {
5786 unsigned long m, x, b;
5787 u32 tsfs;
5788
5789 tsfs = I915_READ(TSFS);
5790
5791 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
5792 x = I915_READ8(TR1);
5793
5794 b = tsfs & TSFS_INTR_MASK;
5795
5796 return ((m * x) / 127) - b;
5797 }
5798
5799 static int _pxvid_to_vd(u8 pxvid)
5800 {
5801 if (pxvid == 0)
5802 return 0;
5803
5804 if (pxvid >= 8 && pxvid < 31)
5805 pxvid = 31;
5806
5807 return (pxvid + 2) * 125;
5808 }
5809
5810 static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
5811 {
5812 struct drm_device *dev = dev_priv->dev;
5813 const int vd = _pxvid_to_vd(pxvid);
5814 const int vm = vd - 1125;
5815
5816 if (INTEL_INFO(dev)->is_mobile)
5817 return vm > 0 ? vm : 0;
5818
5819 return vd;
5820 }
5821
5822 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
5823 {
5824 u64 now, diff, diffms;
5825 u32 count;
5826
5827 assert_spin_locked(&mchdev_lock);
5828
5829 now = ktime_get_raw_ns();
5830 diffms = now - dev_priv->ips.last_time2;
5831 do_div(diffms, NSEC_PER_MSEC);
5832
5833 /* Don't divide by 0 */
5834 if (!diffms)
5835 return;
5836
5837 count = I915_READ(GFXEC);
5838
5839 if (count < dev_priv->ips.last_count2) {
5840 diff = ~0UL - dev_priv->ips.last_count2;
5841 diff += count;
5842 } else {
5843 diff = count - dev_priv->ips.last_count2;
5844 }
5845
5846 dev_priv->ips.last_count2 = count;
5847 dev_priv->ips.last_time2 = now;
5848
5849 /* More magic constants... */
5850 diff = diff * 1181;
5851 diff = div_u64(diff, diffms * 10);
5852 dev_priv->ips.gfx_power = diff;
5853 }
5854
5855 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
5856 {
5857 struct drm_device *dev = dev_priv->dev;
5858
5859 if (INTEL_INFO(dev)->gen != 5)
5860 return;
5861
5862 spin_lock_irq(&mchdev_lock);
5863
5864 __i915_update_gfx_val(dev_priv);
5865
5866 spin_unlock_irq(&mchdev_lock);
5867 }
5868
5869 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
5870 {
5871 unsigned long t, corr, state1, corr2, state2;
5872 u32 pxvid, ext_v;
5873
5874 assert_spin_locked(&mchdev_lock);
5875
5876 pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
5877 pxvid = (pxvid >> 24) & 0x7f;
5878 ext_v = pvid_to_extvid(dev_priv, pxvid);
5879
5880 state1 = ext_v;
5881
5882 t = i915_mch_val(dev_priv);
5883
5884 /* Revel in the empirically derived constants */
5885
5886 /* Correction factor in 1/100000 units */
5887 if (t > 80)
5888 corr = ((t * 2349) + 135940);
5889 else if (t >= 50)
5890 corr = ((t * 964) + 29317);
5891 else /* < 50 */
5892 corr = ((t * 301) + 1004);
5893
5894 corr = corr * ((150142 * state1) / 10000 - 78642);
5895 corr /= 100000;
5896 corr2 = (corr * dev_priv->ips.corr);
5897
5898 state2 = (corr2 * state1) / 10000;
5899 state2 /= 100; /* convert to mW */
5900
5901 __i915_update_gfx_val(dev_priv);
5902
5903 return dev_priv->ips.gfx_power + state2;
5904 }
5905
5906 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
5907 {
5908 struct drm_device *dev = dev_priv->dev;
5909 unsigned long val;
5910
5911 if (INTEL_INFO(dev)->gen != 5)
5912 return 0;
5913
5914 spin_lock_irq(&mchdev_lock);
5915
5916 val = __i915_gfx_val(dev_priv);
5917
5918 spin_unlock_irq(&mchdev_lock);
5919
5920 return val;
5921 }
5922
5923 /**
5924 * i915_read_mch_val - return value for IPS use
5925 *
5926 * Calculate and return a value for the IPS driver to use when deciding whether
5927 * we have thermal and power headroom to increase CPU or GPU power budget.
5928 */
5929 unsigned long i915_read_mch_val(void)
5930 {
5931 struct drm_i915_private *dev_priv;
5932 unsigned long chipset_val, graphics_val, ret = 0;
5933
5934 spin_lock_irq(&mchdev_lock);
5935 if (!i915_mch_dev)
5936 goto out_unlock;
5937 dev_priv = i915_mch_dev;
5938
5939 chipset_val = __i915_chipset_val(dev_priv);
5940 graphics_val = __i915_gfx_val(dev_priv);
5941
5942 ret = chipset_val + graphics_val;
5943
5944 out_unlock:
5945 spin_unlock_irq(&mchdev_lock);
5946
5947 return ret;
5948 }
5949 EXPORT_SYMBOL_GPL(i915_read_mch_val);
5950
5951 /**
5952 * i915_gpu_raise - raise GPU frequency limit
5953 *
5954 * Raise the limit; IPS indicates we have thermal headroom.
5955 */
5956 bool i915_gpu_raise(void)
5957 {
5958 struct drm_i915_private *dev_priv;
5959 bool ret = true;
5960
5961 spin_lock_irq(&mchdev_lock);
5962 if (!i915_mch_dev) {
5963 ret = false;
5964 goto out_unlock;
5965 }
5966 dev_priv = i915_mch_dev;
5967
5968 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
5969 dev_priv->ips.max_delay--;
5970
5971 out_unlock:
5972 spin_unlock_irq(&mchdev_lock);
5973
5974 return ret;
5975 }
5976 EXPORT_SYMBOL_GPL(i915_gpu_raise);
5977
5978 /**
5979 * i915_gpu_lower - lower GPU frequency limit
5980 *
5981 * IPS indicates we're close to a thermal limit, so throttle back the GPU
5982 * frequency maximum.
5983 */
5984 bool i915_gpu_lower(void)
5985 {
5986 struct drm_i915_private *dev_priv;
5987 bool ret = true;
5988
5989 spin_lock_irq(&mchdev_lock);
5990 if (!i915_mch_dev) {
5991 ret = false;
5992 goto out_unlock;
5993 }
5994 dev_priv = i915_mch_dev;
5995
5996 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
5997 dev_priv->ips.max_delay++;
5998
5999 out_unlock:
6000 spin_unlock_irq(&mchdev_lock);
6001
6002 return ret;
6003 }
6004 EXPORT_SYMBOL_GPL(i915_gpu_lower);
6005
6006 /**
6007 * i915_gpu_busy - indicate GPU business to IPS
6008 *
6009 * Tell the IPS driver whether or not the GPU is busy.
6010 */
6011 bool i915_gpu_busy(void)
6012 {
6013 struct drm_i915_private *dev_priv;
6014 struct intel_engine_cs *ring;
6015 bool ret = false;
6016 int i;
6017
6018 spin_lock_irq(&mchdev_lock);
6019 if (!i915_mch_dev)
6020 goto out_unlock;
6021 dev_priv = i915_mch_dev;
6022
6023 for_each_ring(ring, dev_priv, i)
6024 ret |= !list_empty(&ring->request_list);
6025
6026 out_unlock:
6027 spin_unlock_irq(&mchdev_lock);
6028
6029 return ret;
6030 }
6031 EXPORT_SYMBOL_GPL(i915_gpu_busy);
6032
6033 /**
6034 * i915_gpu_turbo_disable - disable graphics turbo
6035 *
6036 * Disable graphics turbo by resetting the max frequency and setting the
6037 * current frequency to the default.
6038 */
6039 bool i915_gpu_turbo_disable(void)
6040 {
6041 struct drm_i915_private *dev_priv;
6042 bool ret = true;
6043
6044 spin_lock_irq(&mchdev_lock);
6045 if (!i915_mch_dev) {
6046 ret = false;
6047 goto out_unlock;
6048 }
6049 dev_priv = i915_mch_dev;
6050
6051 dev_priv->ips.max_delay = dev_priv->ips.fstart;
6052
6053 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
6054 ret = false;
6055
6056 out_unlock:
6057 spin_unlock_irq(&mchdev_lock);
6058
6059 return ret;
6060 }
6061 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6062
6063 /**
6064 * Tells the intel_ips driver that the i915 driver is now loaded, if
6065 * IPS got loaded first.
6066 *
6067 * This awkward dance is so that neither module has to depend on the
6068 * other in order for IPS to do the appropriate communication of
6069 * GPU turbo limits to i915.
6070 */
6071 static void
6072 ips_ping_for_i915_load(void)
6073 {
6074 void (*link)(void);
6075
6076 link = symbol_get(ips_link_to_i915_driver);
6077 if (link) {
6078 link();
6079 symbol_put(ips_link_to_i915_driver);
6080 }
6081 }
6082
6083 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6084 {
6085 /* We only register the i915 ips part with intel-ips once everything is
6086 * set up, to avoid intel-ips sneaking in and reading bogus values. */
6087 spin_lock_irq(&mchdev_lock);
6088 i915_mch_dev = dev_priv;
6089 spin_unlock_irq(&mchdev_lock);
6090
6091 ips_ping_for_i915_load();
6092 }
6093
6094 void intel_gpu_ips_teardown(void)
6095 {
6096 spin_lock_irq(&mchdev_lock);
6097 i915_mch_dev = NULL;
6098 spin_unlock_irq(&mchdev_lock);
6099 }
6100
6101 static void intel_init_emon(struct drm_device *dev)
6102 {
6103 struct drm_i915_private *dev_priv = dev->dev_private;
6104 u32 lcfuse;
6105 u8 pxw[16];
6106 int i;
6107
6108 /* Disable to program */
6109 I915_WRITE(ECR, 0);
6110 POSTING_READ(ECR);
6111
6112 /* Program energy weights for various events */
6113 I915_WRITE(SDEW, 0x15040d00);
6114 I915_WRITE(CSIEW0, 0x007f0000);
6115 I915_WRITE(CSIEW1, 0x1e220004);
6116 I915_WRITE(CSIEW2, 0x04000004);
6117
6118 for (i = 0; i < 5; i++)
6119 I915_WRITE(PEW(i), 0);
6120 for (i = 0; i < 3; i++)
6121 I915_WRITE(DEW(i), 0);
6122
6123 /* Program P-state weights to account for frequency power adjustment */
6124 for (i = 0; i < 16; i++) {
6125 u32 pxvidfreq = I915_READ(PXVFREQ(i));
6126 unsigned long freq = intel_pxfreq(pxvidfreq);
6127 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6128 PXVFREQ_PX_SHIFT;
6129 unsigned long val;
6130
6131 val = vid * vid;
6132 val *= (freq / 1000);
6133 val *= 255;
6134 val /= (127*127*900);
6135 if (val > 0xff)
6136 DRM_ERROR("bad pxval: %ld\n", val);
6137 pxw[i] = val;
6138 }
6139 /* Render standby states get 0 weight */
6140 pxw[14] = 0;
6141 pxw[15] = 0;
6142
6143 for (i = 0; i < 4; i++) {
6144 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6145 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
6146 I915_WRITE(PXW(i), val);
6147 }
6148
6149 /* Adjust magic regs to magic values (more experimental results) */
6150 I915_WRITE(OGW0, 0);
6151 I915_WRITE(OGW1, 0);
6152 I915_WRITE(EG0, 0x00007f00);
6153 I915_WRITE(EG1, 0x0000000e);
6154 I915_WRITE(EG2, 0x000e0000);
6155 I915_WRITE(EG3, 0x68000300);
6156 I915_WRITE(EG4, 0x42000000);
6157 I915_WRITE(EG5, 0x00140031);
6158 I915_WRITE(EG6, 0);
6159 I915_WRITE(EG7, 0);
6160
6161 for (i = 0; i < 8; i++)
6162 I915_WRITE(PXWL(i), 0);
6163
6164 /* Enable PMON + select events */
6165 I915_WRITE(ECR, 0x80000019);
6166
6167 lcfuse = I915_READ(LCFUSE02);
6168
6169 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
6170 }
6171
6172 void intel_init_gt_powersave(struct drm_device *dev)
6173 {
6174 struct drm_i915_private *dev_priv = dev->dev_private;
6175
6176 /*
6177 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6178 * requirement.
6179 */
6180 if (!i915.enable_rc6) {
6181 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6182 intel_runtime_pm_get(dev_priv);
6183 }
6184
6185 if (IS_CHERRYVIEW(dev))
6186 cherryview_init_gt_powersave(dev);
6187 else if (IS_VALLEYVIEW(dev))
6188 valleyview_init_gt_powersave(dev);
6189 }
6190
6191 void intel_cleanup_gt_powersave(struct drm_device *dev)
6192 {
6193 struct drm_i915_private *dev_priv = dev->dev_private;
6194
6195 if (IS_CHERRYVIEW(dev))
6196 return;
6197 else if (IS_VALLEYVIEW(dev))
6198 valleyview_cleanup_gt_powersave(dev);
6199
6200 if (!i915.enable_rc6)
6201 intel_runtime_pm_put(dev_priv);
6202 }
6203
6204 static void gen6_suspend_rps(struct drm_device *dev)
6205 {
6206 struct drm_i915_private *dev_priv = dev->dev_private;
6207
6208 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
6209
6210 gen6_disable_rps_interrupts(dev);
6211 }
6212
6213 /**
6214 * intel_suspend_gt_powersave - suspend PM work and helper threads
6215 * @dev: drm device
6216 *
6217 * We don't want to disable RC6 or other features here, we just want
6218 * to make sure any work we've queued has finished and won't bother
6219 * us while we're suspended.
6220 */
6221 void intel_suspend_gt_powersave(struct drm_device *dev)
6222 {
6223 struct drm_i915_private *dev_priv = dev->dev_private;
6224
6225 if (INTEL_INFO(dev)->gen < 6)
6226 return;
6227
6228 gen6_suspend_rps(dev);
6229
6230 /* Force GPU to min freq during suspend */
6231 gen6_rps_idle(dev_priv);
6232 }
6233
6234 void intel_disable_gt_powersave(struct drm_device *dev)
6235 {
6236 struct drm_i915_private *dev_priv = dev->dev_private;
6237
6238 if (IS_IRONLAKE_M(dev)) {
6239 ironlake_disable_drps(dev);
6240 } else if (INTEL_INFO(dev)->gen >= 6) {
6241 intel_suspend_gt_powersave(dev);
6242
6243 mutex_lock(&dev_priv->rps.hw_lock);
6244 if (INTEL_INFO(dev)->gen >= 9)
6245 gen9_disable_rps(dev);
6246 else if (IS_CHERRYVIEW(dev))
6247 cherryview_disable_rps(dev);
6248 else if (IS_VALLEYVIEW(dev))
6249 valleyview_disable_rps(dev);
6250 else
6251 gen6_disable_rps(dev);
6252
6253 dev_priv->rps.enabled = false;
6254 mutex_unlock(&dev_priv->rps.hw_lock);
6255 }
6256 }
6257
6258 static void intel_gen6_powersave_work(struct work_struct *work)
6259 {
6260 struct drm_i915_private *dev_priv =
6261 container_of(work, struct drm_i915_private,
6262 rps.delayed_resume_work.work);
6263 struct drm_device *dev = dev_priv->dev;
6264
6265 mutex_lock(&dev_priv->rps.hw_lock);
6266
6267 gen6_reset_rps_interrupts(dev);
6268
6269 if (IS_CHERRYVIEW(dev)) {
6270 cherryview_enable_rps(dev);
6271 } else if (IS_VALLEYVIEW(dev)) {
6272 valleyview_enable_rps(dev);
6273 } else if (INTEL_INFO(dev)->gen >= 9) {
6274 gen9_enable_rc6(dev);
6275 gen9_enable_rps(dev);
6276 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
6277 __gen6_update_ring_freq(dev);
6278 } else if (IS_BROADWELL(dev)) {
6279 gen8_enable_rps(dev);
6280 __gen6_update_ring_freq(dev);
6281 } else {
6282 gen6_enable_rps(dev);
6283 __gen6_update_ring_freq(dev);
6284 }
6285
6286 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6287 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6288
6289 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6290 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6291
6292 dev_priv->rps.enabled = true;
6293
6294 gen6_enable_rps_interrupts(dev);
6295
6296 mutex_unlock(&dev_priv->rps.hw_lock);
6297
6298 intel_runtime_pm_put(dev_priv);
6299 }
6300
6301 void intel_enable_gt_powersave(struct drm_device *dev)
6302 {
6303 struct drm_i915_private *dev_priv = dev->dev_private;
6304
6305 /* Powersaving is controlled by the host when inside a VM */
6306 if (intel_vgpu_active(dev))
6307 return;
6308
6309 if (IS_IRONLAKE_M(dev)) {
6310 ironlake_enable_drps(dev);
6311 mutex_lock(&dev->struct_mutex);
6312 intel_init_emon(dev);
6313 mutex_unlock(&dev->struct_mutex);
6314 } else if (INTEL_INFO(dev)->gen >= 6) {
6315 /*
6316 * PCU communication is slow and this doesn't need to be
6317 * done at any specific time, so do this out of our fast path
6318 * to make resume and init faster.
6319 *
6320 * We depend on the HW RC6 power context save/restore
6321 * mechanism when entering D3 through runtime PM suspend. So
6322 * disable RPM until RPS/RC6 is properly setup. We can only
6323 * get here via the driver load/system resume/runtime resume
6324 * paths, so the _noresume version is enough (and in case of
6325 * runtime resume it's necessary).
6326 */
6327 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
6328 round_jiffies_up_relative(HZ)))
6329 intel_runtime_pm_get_noresume(dev_priv);
6330 }
6331 }
6332
6333 void intel_reset_gt_powersave(struct drm_device *dev)
6334 {
6335 struct drm_i915_private *dev_priv = dev->dev_private;
6336
6337 if (INTEL_INFO(dev)->gen < 6)
6338 return;
6339
6340 gen6_suspend_rps(dev);
6341 dev_priv->rps.enabled = false;
6342 }
6343
6344 static void ibx_init_clock_gating(struct drm_device *dev)
6345 {
6346 struct drm_i915_private *dev_priv = dev->dev_private;
6347
6348 /*
6349 * On Ibex Peak and Cougar Point, we need to disable clock
6350 * gating for the panel power sequencer or it will fail to
6351 * start up when no ports are active.
6352 */
6353 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6354 }
6355
6356 static void g4x_disable_trickle_feed(struct drm_device *dev)
6357 {
6358 struct drm_i915_private *dev_priv = dev->dev_private;
6359 enum pipe pipe;
6360
6361 for_each_pipe(dev_priv, pipe) {
6362 I915_WRITE(DSPCNTR(pipe),
6363 I915_READ(DSPCNTR(pipe)) |
6364 DISPPLANE_TRICKLE_FEED_DISABLE);
6365
6366 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6367 POSTING_READ(DSPSURF(pipe));
6368 }
6369 }
6370
6371 static void ilk_init_lp_watermarks(struct drm_device *dev)
6372 {
6373 struct drm_i915_private *dev_priv = dev->dev_private;
6374
6375 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6376 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6377 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6378
6379 /*
6380 * Don't touch WM1S_LP_EN here.
6381 * Doing so could cause underruns.
6382 */
6383 }
6384
6385 static void ironlake_init_clock_gating(struct drm_device *dev)
6386 {
6387 struct drm_i915_private *dev_priv = dev->dev_private;
6388 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6389
6390 /*
6391 * Required for FBC
6392 * WaFbcDisableDpfcClockGating:ilk
6393 */
6394 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6395 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6396 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6397
6398 I915_WRITE(PCH_3DCGDIS0,
6399 MARIUNIT_CLOCK_GATE_DISABLE |
6400 SVSMUNIT_CLOCK_GATE_DISABLE);
6401 I915_WRITE(PCH_3DCGDIS1,
6402 VFMUNIT_CLOCK_GATE_DISABLE);
6403
6404 /*
6405 * According to the spec the following bits should be set in
6406 * order to enable memory self-refresh
6407 * The bit 22/21 of 0x42004
6408 * The bit 5 of 0x42020
6409 * The bit 15 of 0x45000
6410 */
6411 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6412 (I915_READ(ILK_DISPLAY_CHICKEN2) |
6413 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
6414 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6415 I915_WRITE(DISP_ARB_CTL,
6416 (I915_READ(DISP_ARB_CTL) |
6417 DISP_FBC_WM_DIS));
6418
6419 ilk_init_lp_watermarks(dev);
6420
6421 /*
6422 * Based on the document from hardware guys the following bits
6423 * should be set unconditionally in order to enable FBC.
6424 * The bit 22 of 0x42000
6425 * The bit 22 of 0x42004
6426 * The bit 7,8,9 of 0x42020.
6427 */
6428 if (IS_IRONLAKE_M(dev)) {
6429 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6430 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6431 I915_READ(ILK_DISPLAY_CHICKEN1) |
6432 ILK_FBCQ_DIS);
6433 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6434 I915_READ(ILK_DISPLAY_CHICKEN2) |
6435 ILK_DPARB_GATE);
6436 }
6437
6438 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6439
6440 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6441 I915_READ(ILK_DISPLAY_CHICKEN2) |
6442 ILK_ELPIN_409_SELECT);
6443 I915_WRITE(_3D_CHICKEN2,
6444 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6445 _3D_CHICKEN2_WM_READ_PIPELINED);
6446
6447 /* WaDisableRenderCachePipelinedFlush:ilk */
6448 I915_WRITE(CACHE_MODE_0,
6449 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6450
6451 /* WaDisable_RenderCache_OperationalFlush:ilk */
6452 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6453
6454 g4x_disable_trickle_feed(dev);
6455
6456 ibx_init_clock_gating(dev);
6457 }
6458
6459 static void cpt_init_clock_gating(struct drm_device *dev)
6460 {
6461 struct drm_i915_private *dev_priv = dev->dev_private;
6462 int pipe;
6463 uint32_t val;
6464
6465 /*
6466 * On Ibex Peak and Cougar Point, we need to disable clock
6467 * gating for the panel power sequencer or it will fail to
6468 * start up when no ports are active.
6469 */
6470 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6471 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6472 PCH_CPUNIT_CLOCK_GATE_DISABLE);
6473 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6474 DPLS_EDP_PPS_FIX_DIS);
6475 /* The below fixes the weird display corruption, a few pixels shifted
6476 * downward, on (only) LVDS of some HP laptops with IVY.
6477 */
6478 for_each_pipe(dev_priv, pipe) {
6479 val = I915_READ(TRANS_CHICKEN2(pipe));
6480 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6481 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6482 if (dev_priv->vbt.fdi_rx_polarity_inverted)
6483 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6484 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6485 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6486 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
6487 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6488 }
6489 /* WADP0ClockGatingDisable */
6490 for_each_pipe(dev_priv, pipe) {
6491 I915_WRITE(TRANS_CHICKEN1(pipe),
6492 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6493 }
6494 }
6495
6496 static void gen6_check_mch_setup(struct drm_device *dev)
6497 {
6498 struct drm_i915_private *dev_priv = dev->dev_private;
6499 uint32_t tmp;
6500
6501 tmp = I915_READ(MCH_SSKPD);
6502 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6503 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6504 tmp);
6505 }
6506
6507 static void gen6_init_clock_gating(struct drm_device *dev)
6508 {
6509 struct drm_i915_private *dev_priv = dev->dev_private;
6510 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6511
6512 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6513
6514 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6515 I915_READ(ILK_DISPLAY_CHICKEN2) |
6516 ILK_ELPIN_409_SELECT);
6517
6518 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
6519 I915_WRITE(_3D_CHICKEN,
6520 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
6521
6522 /* WaDisable_RenderCache_OperationalFlush:snb */
6523 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6524
6525 /*
6526 * BSpec recoomends 8x4 when MSAA is used,
6527 * however in practice 16x4 seems fastest.
6528 *
6529 * Note that PS/WM thread counts depend on the WIZ hashing
6530 * disable bit, which we don't touch here, but it's good
6531 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6532 */
6533 I915_WRITE(GEN6_GT_MODE,
6534 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6535
6536 ilk_init_lp_watermarks(dev);
6537
6538 I915_WRITE(CACHE_MODE_0,
6539 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6540
6541 I915_WRITE(GEN6_UCGCTL1,
6542 I915_READ(GEN6_UCGCTL1) |
6543 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
6544 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6545
6546 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
6547 * gating disable must be set. Failure to set it results in
6548 * flickering pixels due to Z write ordering failures after
6549 * some amount of runtime in the Mesa "fire" demo, and Unigine
6550 * Sanctuary and Tropics, and apparently anything else with
6551 * alpha test or pixel discard.
6552 *
6553 * According to the spec, bit 11 (RCCUNIT) must also be set,
6554 * but we didn't debug actual testcases to find it out.
6555 *
6556 * WaDisableRCCUnitClockGating:snb
6557 * WaDisableRCPBUnitClockGating:snb
6558 */
6559 I915_WRITE(GEN6_UCGCTL2,
6560 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
6561 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
6562
6563 /* WaStripsFansDisableFastClipPerformanceFix:snb */
6564 I915_WRITE(_3D_CHICKEN3,
6565 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6566
6567 /*
6568 * Bspec says:
6569 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
6570 * 3DSTATE_SF number of SF output attributes is more than 16."
6571 */
6572 I915_WRITE(_3D_CHICKEN3,
6573 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
6574
6575 /*
6576 * According to the spec the following bits should be
6577 * set in order to enable memory self-refresh and fbc:
6578 * The bit21 and bit22 of 0x42000
6579 * The bit21 and bit22 of 0x42004
6580 * The bit5 and bit7 of 0x42020
6581 * The bit14 of 0x70180
6582 * The bit14 of 0x71180
6583 *
6584 * WaFbcAsynchFlipDisableFbcQueue:snb
6585 */
6586 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6587 I915_READ(ILK_DISPLAY_CHICKEN1) |
6588 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6589 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6590 I915_READ(ILK_DISPLAY_CHICKEN2) |
6591 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
6592 I915_WRITE(ILK_DSPCLK_GATE_D,
6593 I915_READ(ILK_DSPCLK_GATE_D) |
6594 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
6595 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6596
6597 g4x_disable_trickle_feed(dev);
6598
6599 cpt_init_clock_gating(dev);
6600
6601 gen6_check_mch_setup(dev);
6602 }
6603
6604 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
6605 {
6606 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
6607
6608 /*
6609 * WaVSThreadDispatchOverride:ivb,vlv
6610 *
6611 * This actually overrides the dispatch
6612 * mode for all thread types.
6613 */
6614 reg &= ~GEN7_FF_SCHED_MASK;
6615 reg |= GEN7_FF_TS_SCHED_HW;
6616 reg |= GEN7_FF_VS_SCHED_HW;
6617 reg |= GEN7_FF_DS_SCHED_HW;
6618
6619 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
6620 }
6621
6622 static void lpt_init_clock_gating(struct drm_device *dev)
6623 {
6624 struct drm_i915_private *dev_priv = dev->dev_private;
6625
6626 /*
6627 * TODO: this bit should only be enabled when really needed, then
6628 * disabled when not needed anymore in order to save power.
6629 */
6630 if (HAS_PCH_LPT_LP(dev))
6631 I915_WRITE(SOUTH_DSPCLK_GATE_D,
6632 I915_READ(SOUTH_DSPCLK_GATE_D) |
6633 PCH_LP_PARTITION_LEVEL_DISABLE);
6634
6635 /* WADPOClockGatingDisable:hsw */
6636 I915_WRITE(TRANS_CHICKEN1(PIPE_A),
6637 I915_READ(TRANS_CHICKEN1(PIPE_A)) |
6638 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6639 }
6640
6641 static void lpt_suspend_hw(struct drm_device *dev)
6642 {
6643 struct drm_i915_private *dev_priv = dev->dev_private;
6644
6645 if (HAS_PCH_LPT_LP(dev)) {
6646 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
6647
6648 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6649 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6650 }
6651 }
6652
6653 static void broadwell_init_clock_gating(struct drm_device *dev)
6654 {
6655 struct drm_i915_private *dev_priv = dev->dev_private;
6656 enum pipe pipe;
6657 uint32_t misccpctl;
6658
6659 ilk_init_lp_watermarks(dev);
6660
6661 /* WaSwitchSolVfFArbitrationPriority:bdw */
6662 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6663
6664 /* WaPsrDPAMaskVBlankInSRD:bdw */
6665 I915_WRITE(CHICKEN_PAR1_1,
6666 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
6667
6668 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
6669 for_each_pipe(dev_priv, pipe) {
6670 I915_WRITE(CHICKEN_PIPESL_1(pipe),
6671 I915_READ(CHICKEN_PIPESL_1(pipe)) |
6672 BDW_DPRS_MASK_VBLANK_SRD);
6673 }
6674
6675 /* WaVSRefCountFullforceMissDisable:bdw */
6676 /* WaDSRefCountFullforceMissDisable:bdw */
6677 I915_WRITE(GEN7_FF_THREAD_MODE,
6678 I915_READ(GEN7_FF_THREAD_MODE) &
6679 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
6680
6681 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6682 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
6683
6684 /* WaDisableSDEUnitClockGating:bdw */
6685 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6686 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6687
6688 /*
6689 * WaProgramL3SqcReg1Default:bdw
6690 * WaTempDisableDOPClkGating:bdw
6691 */
6692 misccpctl = I915_READ(GEN7_MISCCPCTL);
6693 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
6694 I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
6695 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
6696
6697 /*
6698 * WaGttCachingOffByDefault:bdw
6699 * GTT cache may not work with big pages, so if those
6700 * are ever enabled GTT cache may need to be disabled.
6701 */
6702 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
6703
6704 lpt_init_clock_gating(dev);
6705 }
6706
6707 static void haswell_init_clock_gating(struct drm_device *dev)
6708 {
6709 struct drm_i915_private *dev_priv = dev->dev_private;
6710
6711 ilk_init_lp_watermarks(dev);
6712
6713 /* L3 caching of data atomics doesn't work -- disable it. */
6714 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
6715 I915_WRITE(HSW_ROW_CHICKEN3,
6716 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
6717
6718 /* This is required by WaCatErrorRejectionIssue:hsw */
6719 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6720 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6721 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6722
6723 /* WaVSRefCountFullforceMissDisable:hsw */
6724 I915_WRITE(GEN7_FF_THREAD_MODE,
6725 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
6726
6727 /* WaDisable_RenderCache_OperationalFlush:hsw */
6728 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6729
6730 /* enable HiZ Raw Stall Optimization */
6731 I915_WRITE(CACHE_MODE_0_GEN7,
6732 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6733
6734 /* WaDisable4x2SubspanOptimization:hsw */
6735 I915_WRITE(CACHE_MODE_1,
6736 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6737
6738 /*
6739 * BSpec recommends 8x4 when MSAA is used,
6740 * however in practice 16x4 seems fastest.
6741 *
6742 * Note that PS/WM thread counts depend on the WIZ hashing
6743 * disable bit, which we don't touch here, but it's good
6744 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6745 */
6746 I915_WRITE(GEN7_GT_MODE,
6747 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6748
6749 /* WaSampleCChickenBitEnable:hsw */
6750 I915_WRITE(HALF_SLICE_CHICKEN3,
6751 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
6752
6753 /* WaSwitchSolVfFArbitrationPriority:hsw */
6754 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6755
6756 /* WaRsPkgCStateDisplayPMReq:hsw */
6757 I915_WRITE(CHICKEN_PAR1_1,
6758 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
6759
6760 lpt_init_clock_gating(dev);
6761 }
6762
6763 static void ivybridge_init_clock_gating(struct drm_device *dev)
6764 {
6765 struct drm_i915_private *dev_priv = dev->dev_private;
6766 uint32_t snpcr;
6767
6768 ilk_init_lp_watermarks(dev);
6769
6770 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6771
6772 /* WaDisableEarlyCull:ivb */
6773 I915_WRITE(_3D_CHICKEN3,
6774 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6775
6776 /* WaDisableBackToBackFlipFix:ivb */
6777 I915_WRITE(IVB_CHICKEN3,
6778 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6779 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6780
6781 /* WaDisablePSDDualDispatchEnable:ivb */
6782 if (IS_IVB_GT1(dev))
6783 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6784 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
6785
6786 /* WaDisable_RenderCache_OperationalFlush:ivb */
6787 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6788
6789 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6790 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
6791 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
6792
6793 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6794 I915_WRITE(GEN7_L3CNTLREG1,
6795 GEN7_WA_FOR_GEN7_L3_CONTROL);
6796 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
6797 GEN7_WA_L3_CHICKEN_MODE);
6798 if (IS_IVB_GT1(dev))
6799 I915_WRITE(GEN7_ROW_CHICKEN2,
6800 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6801 else {
6802 /* must write both registers */
6803 I915_WRITE(GEN7_ROW_CHICKEN2,
6804 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6805 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
6806 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6807 }
6808
6809 /* WaForceL3Serialization:ivb */
6810 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6811 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6812
6813 /*
6814 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6815 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
6816 */
6817 I915_WRITE(GEN6_UCGCTL2,
6818 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
6819
6820 /* This is required by WaCatErrorRejectionIssue:ivb */
6821 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6822 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6823 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6824
6825 g4x_disable_trickle_feed(dev);
6826
6827 gen7_setup_fixed_func_scheduler(dev_priv);
6828
6829 if (0) { /* causes HiZ corruption on ivb:gt1 */
6830 /* enable HiZ Raw Stall Optimization */
6831 I915_WRITE(CACHE_MODE_0_GEN7,
6832 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6833 }
6834
6835 /* WaDisable4x2SubspanOptimization:ivb */
6836 I915_WRITE(CACHE_MODE_1,
6837 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6838
6839 /*
6840 * BSpec recommends 8x4 when MSAA is used,
6841 * however in practice 16x4 seems fastest.
6842 *
6843 * Note that PS/WM thread counts depend on the WIZ hashing
6844 * disable bit, which we don't touch here, but it's good
6845 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6846 */
6847 I915_WRITE(GEN7_GT_MODE,
6848 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6849
6850 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
6851 snpcr &= ~GEN6_MBC_SNPCR_MASK;
6852 snpcr |= GEN6_MBC_SNPCR_MED;
6853 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
6854
6855 if (!HAS_PCH_NOP(dev))
6856 cpt_init_clock_gating(dev);
6857
6858 gen6_check_mch_setup(dev);
6859 }
6860
6861 static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
6862 {
6863 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6864
6865 /*
6866 * Disable trickle feed and enable pnd deadline calculation
6867 */
6868 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6869 I915_WRITE(CBR1_VLV, 0);
6870 }
6871
6872 static void valleyview_init_clock_gating(struct drm_device *dev)
6873 {
6874 struct drm_i915_private *dev_priv = dev->dev_private;
6875
6876 vlv_init_display_clock_gating(dev_priv);
6877
6878 /* WaDisableEarlyCull:vlv */
6879 I915_WRITE(_3D_CHICKEN3,
6880 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6881
6882 /* WaDisableBackToBackFlipFix:vlv */
6883 I915_WRITE(IVB_CHICKEN3,
6884 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6885 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6886
6887 /* WaPsdDispatchEnable:vlv */
6888 /* WaDisablePSDDualDispatchEnable:vlv */
6889 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6890 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
6891 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
6892
6893 /* WaDisable_RenderCache_OperationalFlush:vlv */
6894 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6895
6896 /* WaForceL3Serialization:vlv */
6897 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6898 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6899
6900 /* WaDisableDopClockGating:vlv */
6901 I915_WRITE(GEN7_ROW_CHICKEN2,
6902 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6903
6904 /* This is required by WaCatErrorRejectionIssue:vlv */
6905 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6906 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6907 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6908
6909 gen7_setup_fixed_func_scheduler(dev_priv);
6910
6911 /*
6912 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6913 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
6914 */
6915 I915_WRITE(GEN6_UCGCTL2,
6916 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
6917
6918 /* WaDisableL3Bank2xClockGate:vlv
6919 * Disabling L3 clock gating- MMIO 940c[25] = 1
6920 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
6921 I915_WRITE(GEN7_UCGCTL4,
6922 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
6923
6924 /*
6925 * BSpec says this must be set, even though
6926 * WaDisable4x2SubspanOptimization isn't listed for VLV.
6927 */
6928 I915_WRITE(CACHE_MODE_1,
6929 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6930
6931 /*
6932 * BSpec recommends 8x4 when MSAA is used,
6933 * however in practice 16x4 seems fastest.
6934 *
6935 * Note that PS/WM thread counts depend on the WIZ hashing
6936 * disable bit, which we don't touch here, but it's good
6937 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6938 */
6939 I915_WRITE(GEN7_GT_MODE,
6940 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6941
6942 /*
6943 * WaIncreaseL3CreditsForVLVB0:vlv
6944 * This is the hardware default actually.
6945 */
6946 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
6947
6948 /*
6949 * WaDisableVLVClockGating_VBIIssue:vlv
6950 * Disable clock gating on th GCFG unit to prevent a delay
6951 * in the reporting of vblank events.
6952 */
6953 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6954 }
6955
6956 static void cherryview_init_clock_gating(struct drm_device *dev)
6957 {
6958 struct drm_i915_private *dev_priv = dev->dev_private;
6959
6960 vlv_init_display_clock_gating(dev_priv);
6961
6962 /* WaVSRefCountFullforceMissDisable:chv */
6963 /* WaDSRefCountFullforceMissDisable:chv */
6964 I915_WRITE(GEN7_FF_THREAD_MODE,
6965 I915_READ(GEN7_FF_THREAD_MODE) &
6966 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
6967
6968 /* WaDisableSemaphoreAndSyncFlipWait:chv */
6969 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6970 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
6971
6972 /* WaDisableCSUnitClockGating:chv */
6973 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
6974 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6975
6976 /* WaDisableSDEUnitClockGating:chv */
6977 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6978 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6979
6980 /*
6981 * GTT cache may not work with big pages, so if those
6982 * are ever enabled GTT cache may need to be disabled.
6983 */
6984 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
6985 }
6986
6987 static void g4x_init_clock_gating(struct drm_device *dev)
6988 {
6989 struct drm_i915_private *dev_priv = dev->dev_private;
6990 uint32_t dspclk_gate;
6991
6992 I915_WRITE(RENCLK_GATE_D1, 0);
6993 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
6994 GS_UNIT_CLOCK_GATE_DISABLE |
6995 CL_UNIT_CLOCK_GATE_DISABLE);
6996 I915_WRITE(RAMCLK_GATE_D, 0);
6997 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
6998 OVRUNIT_CLOCK_GATE_DISABLE |
6999 OVCUNIT_CLOCK_GATE_DISABLE;
7000 if (IS_GM45(dev))
7001 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7002 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
7003
7004 /* WaDisableRenderCachePipelinedFlush */
7005 I915_WRITE(CACHE_MODE_0,
7006 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
7007
7008 /* WaDisable_RenderCache_OperationalFlush:g4x */
7009 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7010
7011 g4x_disable_trickle_feed(dev);
7012 }
7013
7014 static void crestline_init_clock_gating(struct drm_device *dev)
7015 {
7016 struct drm_i915_private *dev_priv = dev->dev_private;
7017
7018 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7019 I915_WRITE(RENCLK_GATE_D2, 0);
7020 I915_WRITE(DSPCLK_GATE_D, 0);
7021 I915_WRITE(RAMCLK_GATE_D, 0);
7022 I915_WRITE16(DEUC, 0);
7023 I915_WRITE(MI_ARB_STATE,
7024 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7025
7026 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7027 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7028 }
7029
7030 static void broadwater_init_clock_gating(struct drm_device *dev)
7031 {
7032 struct drm_i915_private *dev_priv = dev->dev_private;
7033
7034 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7035 I965_RCC_CLOCK_GATE_DISABLE |
7036 I965_RCPB_CLOCK_GATE_DISABLE |
7037 I965_ISC_CLOCK_GATE_DISABLE |
7038 I965_FBC_CLOCK_GATE_DISABLE);
7039 I915_WRITE(RENCLK_GATE_D2, 0);
7040 I915_WRITE(MI_ARB_STATE,
7041 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7042
7043 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7044 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7045 }
7046
7047 static void gen3_init_clock_gating(struct drm_device *dev)
7048 {
7049 struct drm_i915_private *dev_priv = dev->dev_private;
7050 u32 dstate = I915_READ(D_STATE);
7051
7052 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7053 DSTATE_DOT_CLOCK_GATING;
7054 I915_WRITE(D_STATE, dstate);
7055
7056 if (IS_PINEVIEW(dev))
7057 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
7058
7059 /* IIR "flip pending" means done if this bit is set */
7060 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
7061
7062 /* interrupts should cause a wake up from C3 */
7063 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
7064
7065 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7066 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
7067
7068 I915_WRITE(MI_ARB_STATE,
7069 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7070 }
7071
7072 static void i85x_init_clock_gating(struct drm_device *dev)
7073 {
7074 struct drm_i915_private *dev_priv = dev->dev_private;
7075
7076 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7077
7078 /* interrupts should cause a wake up from C3 */
7079 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7080 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
7081
7082 I915_WRITE(MEM_MODE,
7083 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
7084 }
7085
7086 static void i830_init_clock_gating(struct drm_device *dev)
7087 {
7088 struct drm_i915_private *dev_priv = dev->dev_private;
7089
7090 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
7091
7092 I915_WRITE(MEM_MODE,
7093 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7094 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
7095 }
7096
7097 void intel_init_clock_gating(struct drm_device *dev)
7098 {
7099 struct drm_i915_private *dev_priv = dev->dev_private;
7100
7101 if (dev_priv->display.init_clock_gating)
7102 dev_priv->display.init_clock_gating(dev);
7103 }
7104
7105 void intel_suspend_hw(struct drm_device *dev)
7106 {
7107 if (HAS_PCH_LPT(dev))
7108 lpt_suspend_hw(dev);
7109 }
7110
7111 /* Set up chip specific power management-related functions */
7112 void intel_init_pm(struct drm_device *dev)
7113 {
7114 struct drm_i915_private *dev_priv = dev->dev_private;
7115
7116 intel_fbc_init(dev_priv);
7117
7118 /* For cxsr */
7119 if (IS_PINEVIEW(dev))
7120 i915_pineview_get_mem_freq(dev);
7121 else if (IS_GEN5(dev))
7122 i915_ironlake_get_mem_freq(dev);
7123
7124 /* For FIFO watermark updates */
7125 if (INTEL_INFO(dev)->gen >= 9) {
7126 skl_setup_wm_latency(dev);
7127
7128 if (IS_BROXTON(dev))
7129 dev_priv->display.init_clock_gating =
7130 bxt_init_clock_gating;
7131 dev_priv->display.update_wm = skl_update_wm;
7132 } else if (HAS_PCH_SPLIT(dev)) {
7133 ilk_setup_wm_latency(dev);
7134
7135 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
7136 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7137 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7138 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
7139 dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
7140 dev_priv->display.compute_intermediate_wm =
7141 ilk_compute_intermediate_wm;
7142 dev_priv->display.initial_watermarks =
7143 ilk_initial_watermarks;
7144 dev_priv->display.optimize_watermarks =
7145 ilk_optimize_watermarks;
7146 } else {
7147 DRM_DEBUG_KMS("Failed to read display plane latency. "
7148 "Disable CxSR\n");
7149 }
7150
7151 if (IS_GEN5(dev))
7152 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7153 else if (IS_GEN6(dev))
7154 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7155 else if (IS_IVYBRIDGE(dev))
7156 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7157 else if (IS_HASWELL(dev))
7158 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7159 else if (INTEL_INFO(dev)->gen == 8)
7160 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7161 } else if (IS_CHERRYVIEW(dev)) {
7162 vlv_setup_wm_latency(dev);
7163
7164 dev_priv->display.update_wm = vlv_update_wm;
7165 dev_priv->display.init_clock_gating =
7166 cherryview_init_clock_gating;
7167 } else if (IS_VALLEYVIEW(dev)) {
7168 vlv_setup_wm_latency(dev);
7169
7170 dev_priv->display.update_wm = vlv_update_wm;
7171 dev_priv->display.init_clock_gating =
7172 valleyview_init_clock_gating;
7173 } else if (IS_PINEVIEW(dev)) {
7174 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7175 dev_priv->is_ddr3,
7176 dev_priv->fsb_freq,
7177 dev_priv->mem_freq)) {
7178 DRM_INFO("failed to find known CxSR latency "
7179 "(found ddr%s fsb freq %d, mem freq %d), "
7180 "disabling CxSR\n",
7181 (dev_priv->is_ddr3 == 1) ? "3" : "2",
7182 dev_priv->fsb_freq, dev_priv->mem_freq);
7183 /* Disable CxSR and never update its watermark again */
7184 intel_set_memory_cxsr(dev_priv, false);
7185 dev_priv->display.update_wm = NULL;
7186 } else
7187 dev_priv->display.update_wm = pineview_update_wm;
7188 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7189 } else if (IS_G4X(dev)) {
7190 dev_priv->display.update_wm = g4x_update_wm;
7191 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7192 } else if (IS_GEN4(dev)) {
7193 dev_priv->display.update_wm = i965_update_wm;
7194 if (IS_CRESTLINE(dev))
7195 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7196 else if (IS_BROADWATER(dev))
7197 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7198 } else if (IS_GEN3(dev)) {
7199 dev_priv->display.update_wm = i9xx_update_wm;
7200 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7201 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7202 } else if (IS_GEN2(dev)) {
7203 if (INTEL_INFO(dev)->num_pipes == 1) {
7204 dev_priv->display.update_wm = i845_update_wm;
7205 dev_priv->display.get_fifo_size = i845_get_fifo_size;
7206 } else {
7207 dev_priv->display.update_wm = i9xx_update_wm;
7208 dev_priv->display.get_fifo_size = i830_get_fifo_size;
7209 }
7210
7211 if (IS_I85X(dev) || IS_I865G(dev))
7212 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7213 else
7214 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7215 } else {
7216 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
7217 }
7218 }
7219
7220 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
7221 {
7222 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7223
7224 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7225 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7226 return -EAGAIN;
7227 }
7228
7229 I915_WRITE(GEN6_PCODE_DATA, *val);
7230 I915_WRITE(GEN6_PCODE_DATA1, 0);
7231 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7232
7233 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7234 500)) {
7235 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7236 return -ETIMEDOUT;
7237 }
7238
7239 *val = I915_READ(GEN6_PCODE_DATA);
7240 I915_WRITE(GEN6_PCODE_DATA, 0);
7241
7242 return 0;
7243 }
7244
7245 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val)
7246 {
7247 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7248
7249 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7250 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7251 return -EAGAIN;
7252 }
7253
7254 I915_WRITE(GEN6_PCODE_DATA, val);
7255 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7256
7257 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7258 500)) {
7259 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7260 return -ETIMEDOUT;
7261 }
7262
7263 I915_WRITE(GEN6_PCODE_DATA, 0);
7264
7265 return 0;
7266 }
7267
7268 static int vlv_gpu_freq_div(unsigned int czclk_freq)
7269 {
7270 switch (czclk_freq) {
7271 case 200:
7272 return 10;
7273 case 267:
7274 return 12;
7275 case 320:
7276 case 333:
7277 return 16;
7278 case 400:
7279 return 20;
7280 default:
7281 return -1;
7282 }
7283 }
7284
7285 static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7286 {
7287 int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
7288
7289 div = vlv_gpu_freq_div(czclk_freq);
7290 if (div < 0)
7291 return div;
7292
7293 return DIV_ROUND_CLOSEST(czclk_freq * (val + 6 - 0xbd), div);
7294 }
7295
7296 static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
7297 {
7298 int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
7299
7300 mul = vlv_gpu_freq_div(czclk_freq);
7301 if (mul < 0)
7302 return mul;
7303
7304 return DIV_ROUND_CLOSEST(mul * val, czclk_freq) + 0xbd - 6;
7305 }
7306
7307 static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
7308 {
7309 int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
7310
7311 div = vlv_gpu_freq_div(czclk_freq);
7312 if (div < 0)
7313 return div;
7314 div /= 2;
7315
7316 return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2;
7317 }
7318
7319 static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
7320 {
7321 int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
7322
7323 mul = vlv_gpu_freq_div(czclk_freq);
7324 if (mul < 0)
7325 return mul;
7326 mul /= 2;
7327
7328 /* CHV needs even values */
7329 return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2;
7330 }
7331
7332 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
7333 {
7334 if (IS_GEN9(dev_priv->dev))
7335 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
7336 GEN9_FREQ_SCALER);
7337 else if (IS_CHERRYVIEW(dev_priv->dev))
7338 return chv_gpu_freq(dev_priv, val);
7339 else if (IS_VALLEYVIEW(dev_priv->dev))
7340 return byt_gpu_freq(dev_priv, val);
7341 else
7342 return val * GT_FREQUENCY_MULTIPLIER;
7343 }
7344
7345 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7346 {
7347 if (IS_GEN9(dev_priv->dev))
7348 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
7349 GT_FREQUENCY_MULTIPLIER);
7350 else if (IS_CHERRYVIEW(dev_priv->dev))
7351 return chv_freq_opcode(dev_priv, val);
7352 else if (IS_VALLEYVIEW(dev_priv->dev))
7353 return byt_freq_opcode(dev_priv, val);
7354 else
7355 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
7356 }
7357
7358 struct request_boost {
7359 struct work_struct work;
7360 struct drm_i915_gem_request *req;
7361 };
7362
7363 static void __intel_rps_boost_work(struct work_struct *work)
7364 {
7365 struct request_boost *boost = container_of(work, struct request_boost, work);
7366 struct drm_i915_gem_request *req = boost->req;
7367
7368 if (!i915_gem_request_completed(req, true))
7369 gen6_rps_boost(to_i915(req->ring->dev), NULL,
7370 req->emitted_jiffies);
7371
7372 i915_gem_request_unreference__unlocked(req);
7373 kfree(boost);
7374 }
7375
7376 void intel_queue_rps_boost_for_request(struct drm_device *dev,
7377 struct drm_i915_gem_request *req)
7378 {
7379 struct request_boost *boost;
7380
7381 if (req == NULL || INTEL_INFO(dev)->gen < 6)
7382 return;
7383
7384 if (i915_gem_request_completed(req, true))
7385 return;
7386
7387 boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
7388 if (boost == NULL)
7389 return;
7390
7391 i915_gem_request_reference(req);
7392 boost->req = req;
7393
7394 INIT_WORK(&boost->work, __intel_rps_boost_work);
7395 queue_work(to_i915(dev)->wq, &boost->work);
7396 }
7397
7398 void intel_pm_setup(struct drm_device *dev)
7399 {
7400 struct drm_i915_private *dev_priv = dev->dev_private;
7401
7402 mutex_init(&dev_priv->rps.hw_lock);
7403 spin_lock_init(&dev_priv->rps.client_lock);
7404
7405 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
7406 intel_gen6_powersave_work);
7407 INIT_LIST_HEAD(&dev_priv->rps.clients);
7408 INIT_LIST_HEAD(&dev_priv->rps.semaphores.link);
7409 INIT_LIST_HEAD(&dev_priv->rps.mmioflips.link);
7410
7411 dev_priv->pm.suspended = false;
7412 atomic_set(&dev_priv->pm.wakeref_count, 0);
7413 atomic_set(&dev_priv->pm.atomic_seq, 0);
7414 }
Linux kernel - Deliverables
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