2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
28 #include <linux/cpufreq.h>
30 #include "intel_drv.h"
31 #include "../../../platform/x86/intel_ips.h"
32 #include <linux/module.h>
33 #include <linux/vgaarb.h>
34 #include <drm/i915_powerwell.h>
35 #include <linux/pm_runtime.h>
38 * RC6 is a special power stage which allows the GPU to enter an very
39 * low-voltage mode when idle, using down to 0V while at this stage. This
40 * stage is entered automatically when the GPU is idle when RC6 support is
41 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
43 * There are different RC6 modes available in Intel GPU, which differentiate
44 * among each other with the latency required to enter and leave RC6 and
45 * voltage consumed by the GPU in different states.
47 * The combination of the following flags define which states GPU is allowed
48 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
49 * RC6pp is deepest RC6. Their support by hardware varies according to the
50 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
51 * which brings the most power savings; deeper states save more power, but
52 * require higher latency to switch to and wake up.
54 #define INTEL_RC6_ENABLE (1<<0)
55 #define INTEL_RC6p_ENABLE (1<<1)
56 #define INTEL_RC6pp_ENABLE (1<<2)
58 /* FBC, or Frame Buffer Compression, is a technique employed to compress the
59 * framebuffer contents in-memory, aiming at reducing the required bandwidth
60 * during in-memory transfers and, therefore, reduce the power packet.
62 * The benefits of FBC are mostly visible with solid backgrounds and
63 * variation-less patterns.
65 * FBC-related functionality can be enabled by the means of the
66 * i915.i915_enable_fbc parameter
69 static void i8xx_disable_fbc(struct drm_device
*dev
)
71 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
74 /* Disable compression */
75 fbc_ctl
= I915_READ(FBC_CONTROL
);
76 if ((fbc_ctl
& FBC_CTL_EN
) == 0)
79 fbc_ctl
&= ~FBC_CTL_EN
;
80 I915_WRITE(FBC_CONTROL
, fbc_ctl
);
82 /* Wait for compressing bit to clear */
83 if (wait_for((I915_READ(FBC_STATUS
) & FBC_STAT_COMPRESSING
) == 0, 10)) {
84 DRM_DEBUG_KMS("FBC idle timed out\n");
88 DRM_DEBUG_KMS("disabled FBC\n");
91 static void i8xx_enable_fbc(struct drm_crtc
*crtc
)
93 struct drm_device
*dev
= crtc
->dev
;
94 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
95 struct drm_framebuffer
*fb
= crtc
->primary
->fb
;
96 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
97 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
102 cfb_pitch
= dev_priv
->fbc
.size
/ FBC_LL_SIZE
;
103 if (fb
->pitches
[0] < cfb_pitch
)
104 cfb_pitch
= fb
->pitches
[0];
106 /* FBC_CTL wants 32B or 64B units */
108 cfb_pitch
= (cfb_pitch
/ 32) - 1;
110 cfb_pitch
= (cfb_pitch
/ 64) - 1;
113 for (i
= 0; i
< (FBC_LL_SIZE
/ 32) + 1; i
++)
114 I915_WRITE(FBC_TAG
+ (i
* 4), 0);
120 fbc_ctl2
= FBC_CTL_FENCE_DBL
| FBC_CTL_IDLE_IMM
| FBC_CTL_CPU_FENCE
;
121 fbc_ctl2
|= FBC_CTL_PLANE(intel_crtc
->plane
);
122 I915_WRITE(FBC_CONTROL2
, fbc_ctl2
);
123 I915_WRITE(FBC_FENCE_OFF
, crtc
->y
);
127 fbc_ctl
= I915_READ(FBC_CONTROL
);
128 fbc_ctl
&= 0x3fff << FBC_CTL_INTERVAL_SHIFT
;
129 fbc_ctl
|= FBC_CTL_EN
| FBC_CTL_PERIODIC
;
131 fbc_ctl
|= FBC_CTL_C3_IDLE
; /* 945 needs special SR handling */
132 fbc_ctl
|= (cfb_pitch
& 0xff) << FBC_CTL_STRIDE_SHIFT
;
133 fbc_ctl
|= obj
->fence_reg
;
134 I915_WRITE(FBC_CONTROL
, fbc_ctl
);
136 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c\n",
137 cfb_pitch
, crtc
->y
, plane_name(intel_crtc
->plane
));
140 static bool i8xx_fbc_enabled(struct drm_device
*dev
)
142 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
144 return I915_READ(FBC_CONTROL
) & FBC_CTL_EN
;
147 static void g4x_enable_fbc(struct drm_crtc
*crtc
)
149 struct drm_device
*dev
= crtc
->dev
;
150 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
151 struct drm_framebuffer
*fb
= crtc
->primary
->fb
;
152 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
153 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
156 dpfc_ctl
= DPFC_CTL_PLANE(intel_crtc
->plane
) | DPFC_SR_EN
;
157 if (drm_format_plane_cpp(fb
->pixel_format
, 0) == 2)
158 dpfc_ctl
|= DPFC_CTL_LIMIT_2X
;
160 dpfc_ctl
|= DPFC_CTL_LIMIT_1X
;
161 dpfc_ctl
|= DPFC_CTL_FENCE_EN
| obj
->fence_reg
;
163 I915_WRITE(DPFC_FENCE_YOFF
, crtc
->y
);
166 I915_WRITE(DPFC_CONTROL
, dpfc_ctl
| DPFC_CTL_EN
);
168 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc
->plane
));
171 static void g4x_disable_fbc(struct drm_device
*dev
)
173 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
176 /* Disable compression */
177 dpfc_ctl
= I915_READ(DPFC_CONTROL
);
178 if (dpfc_ctl
& DPFC_CTL_EN
) {
179 dpfc_ctl
&= ~DPFC_CTL_EN
;
180 I915_WRITE(DPFC_CONTROL
, dpfc_ctl
);
182 DRM_DEBUG_KMS("disabled FBC\n");
186 static bool g4x_fbc_enabled(struct drm_device
*dev
)
188 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
190 return I915_READ(DPFC_CONTROL
) & DPFC_CTL_EN
;
193 static void sandybridge_blit_fbc_update(struct drm_device
*dev
)
195 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
198 /* Make sure blitter notifies FBC of writes */
200 /* Blitter is part of Media powerwell on VLV. No impact of
201 * his param in other platforms for now */
202 gen6_gt_force_wake_get(dev_priv
, FORCEWAKE_MEDIA
);
204 blt_ecoskpd
= I915_READ(GEN6_BLITTER_ECOSKPD
);
205 blt_ecoskpd
|= GEN6_BLITTER_FBC_NOTIFY
<<
206 GEN6_BLITTER_LOCK_SHIFT
;
207 I915_WRITE(GEN6_BLITTER_ECOSKPD
, blt_ecoskpd
);
208 blt_ecoskpd
|= GEN6_BLITTER_FBC_NOTIFY
;
209 I915_WRITE(GEN6_BLITTER_ECOSKPD
, blt_ecoskpd
);
210 blt_ecoskpd
&= ~(GEN6_BLITTER_FBC_NOTIFY
<<
211 GEN6_BLITTER_LOCK_SHIFT
);
212 I915_WRITE(GEN6_BLITTER_ECOSKPD
, blt_ecoskpd
);
213 POSTING_READ(GEN6_BLITTER_ECOSKPD
);
215 gen6_gt_force_wake_put(dev_priv
, FORCEWAKE_MEDIA
);
218 static void ironlake_enable_fbc(struct drm_crtc
*crtc
)
220 struct drm_device
*dev
= crtc
->dev
;
221 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
222 struct drm_framebuffer
*fb
= crtc
->primary
->fb
;
223 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
224 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
227 dpfc_ctl
= DPFC_CTL_PLANE(intel_crtc
->plane
);
228 if (drm_format_plane_cpp(fb
->pixel_format
, 0) == 2)
229 dev_priv
->fbc
.threshold
++;
231 switch (dev_priv
->fbc
.threshold
) {
234 dpfc_ctl
|= DPFC_CTL_LIMIT_4X
;
237 dpfc_ctl
|= DPFC_CTL_LIMIT_2X
;
240 dpfc_ctl
|= DPFC_CTL_LIMIT_1X
;
243 dpfc_ctl
|= DPFC_CTL_FENCE_EN
;
245 dpfc_ctl
|= obj
->fence_reg
;
247 I915_WRITE(ILK_DPFC_FENCE_YOFF
, crtc
->y
);
248 I915_WRITE(ILK_FBC_RT_BASE
, i915_gem_obj_ggtt_offset(obj
) | ILK_FBC_RT_VALID
);
250 I915_WRITE(ILK_DPFC_CONTROL
, dpfc_ctl
| DPFC_CTL_EN
);
253 I915_WRITE(SNB_DPFC_CTL_SA
,
254 SNB_CPU_FENCE_ENABLE
| obj
->fence_reg
);
255 I915_WRITE(DPFC_CPU_FENCE_OFFSET
, crtc
->y
);
256 sandybridge_blit_fbc_update(dev
);
259 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc
->plane
));
262 static void ironlake_disable_fbc(struct drm_device
*dev
)
264 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
267 /* Disable compression */
268 dpfc_ctl
= I915_READ(ILK_DPFC_CONTROL
);
269 if (dpfc_ctl
& DPFC_CTL_EN
) {
270 dpfc_ctl
&= ~DPFC_CTL_EN
;
271 I915_WRITE(ILK_DPFC_CONTROL
, dpfc_ctl
);
273 DRM_DEBUG_KMS("disabled FBC\n");
277 static bool ironlake_fbc_enabled(struct drm_device
*dev
)
279 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
281 return I915_READ(ILK_DPFC_CONTROL
) & DPFC_CTL_EN
;
284 static void gen7_enable_fbc(struct drm_crtc
*crtc
)
286 struct drm_device
*dev
= crtc
->dev
;
287 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
288 struct drm_framebuffer
*fb
= crtc
->primary
->fb
;
289 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
290 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
293 dpfc_ctl
= IVB_DPFC_CTL_PLANE(intel_crtc
->plane
);
294 if (drm_format_plane_cpp(fb
->pixel_format
, 0) == 2)
295 dev_priv
->fbc
.threshold
++;
297 switch (dev_priv
->fbc
.threshold
) {
300 dpfc_ctl
|= DPFC_CTL_LIMIT_4X
;
303 dpfc_ctl
|= DPFC_CTL_LIMIT_2X
;
306 dpfc_ctl
|= DPFC_CTL_LIMIT_1X
;
310 dpfc_ctl
|= IVB_DPFC_CTL_FENCE_EN
;
312 if (dev_priv
->fbc
.false_color
)
313 dpfc_ctl
|= FBC_CTL_FALSE_COLOR
;
315 I915_WRITE(ILK_DPFC_CONTROL
, dpfc_ctl
| DPFC_CTL_EN
);
317 if (IS_IVYBRIDGE(dev
)) {
318 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
319 I915_WRITE(ILK_DISPLAY_CHICKEN1
,
320 I915_READ(ILK_DISPLAY_CHICKEN1
) |
323 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
324 I915_WRITE(CHICKEN_PIPESL_1(intel_crtc
->pipe
),
325 I915_READ(CHICKEN_PIPESL_1(intel_crtc
->pipe
)) |
329 I915_WRITE(SNB_DPFC_CTL_SA
,
330 SNB_CPU_FENCE_ENABLE
| obj
->fence_reg
);
331 I915_WRITE(DPFC_CPU_FENCE_OFFSET
, crtc
->y
);
333 sandybridge_blit_fbc_update(dev
);
335 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc
->plane
));
338 bool intel_fbc_enabled(struct drm_device
*dev
)
340 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
342 if (!dev_priv
->display
.fbc_enabled
)
345 return dev_priv
->display
.fbc_enabled(dev
);
348 static void intel_fbc_work_fn(struct work_struct
*__work
)
350 struct intel_fbc_work
*work
=
351 container_of(to_delayed_work(__work
),
352 struct intel_fbc_work
, work
);
353 struct drm_device
*dev
= work
->crtc
->dev
;
354 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
356 mutex_lock(&dev
->struct_mutex
);
357 if (work
== dev_priv
->fbc
.fbc_work
) {
358 /* Double check that we haven't switched fb without cancelling
361 if (work
->crtc
->primary
->fb
== work
->fb
) {
362 dev_priv
->display
.enable_fbc(work
->crtc
);
364 dev_priv
->fbc
.plane
= to_intel_crtc(work
->crtc
)->plane
;
365 dev_priv
->fbc
.fb_id
= work
->crtc
->primary
->fb
->base
.id
;
366 dev_priv
->fbc
.y
= work
->crtc
->y
;
369 dev_priv
->fbc
.fbc_work
= NULL
;
371 mutex_unlock(&dev
->struct_mutex
);
376 static void intel_cancel_fbc_work(struct drm_i915_private
*dev_priv
)
378 if (dev_priv
->fbc
.fbc_work
== NULL
)
381 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
383 /* Synchronisation is provided by struct_mutex and checking of
384 * dev_priv->fbc.fbc_work, so we can perform the cancellation
385 * entirely asynchronously.
387 if (cancel_delayed_work(&dev_priv
->fbc
.fbc_work
->work
))
388 /* tasklet was killed before being run, clean up */
389 kfree(dev_priv
->fbc
.fbc_work
);
391 /* Mark the work as no longer wanted so that if it does
392 * wake-up (because the work was already running and waiting
393 * for our mutex), it will discover that is no longer
396 dev_priv
->fbc
.fbc_work
= NULL
;
399 static void intel_enable_fbc(struct drm_crtc
*crtc
)
401 struct intel_fbc_work
*work
;
402 struct drm_device
*dev
= crtc
->dev
;
403 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
405 if (!dev_priv
->display
.enable_fbc
)
408 intel_cancel_fbc_work(dev_priv
);
410 work
= kzalloc(sizeof(*work
), GFP_KERNEL
);
412 DRM_ERROR("Failed to allocate FBC work structure\n");
413 dev_priv
->display
.enable_fbc(crtc
);
418 work
->fb
= crtc
->primary
->fb
;
419 INIT_DELAYED_WORK(&work
->work
, intel_fbc_work_fn
);
421 dev_priv
->fbc
.fbc_work
= work
;
423 /* Delay the actual enabling to let pageflipping cease and the
424 * display to settle before starting the compression. Note that
425 * this delay also serves a second purpose: it allows for a
426 * vblank to pass after disabling the FBC before we attempt
427 * to modify the control registers.
429 * A more complicated solution would involve tracking vblanks
430 * following the termination of the page-flipping sequence
431 * and indeed performing the enable as a co-routine and not
432 * waiting synchronously upon the vblank.
434 * WaFbcWaitForVBlankBeforeEnable:ilk,snb
436 schedule_delayed_work(&work
->work
, msecs_to_jiffies(50));
439 void intel_disable_fbc(struct drm_device
*dev
)
441 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
443 intel_cancel_fbc_work(dev_priv
);
445 if (!dev_priv
->display
.disable_fbc
)
448 dev_priv
->display
.disable_fbc(dev
);
449 dev_priv
->fbc
.plane
= -1;
452 static bool set_no_fbc_reason(struct drm_i915_private
*dev_priv
,
453 enum no_fbc_reason reason
)
455 if (dev_priv
->fbc
.no_fbc_reason
== reason
)
458 dev_priv
->fbc
.no_fbc_reason
= reason
;
463 * intel_update_fbc - enable/disable FBC as needed
464 * @dev: the drm_device
466 * Set up the framebuffer compression hardware at mode set time. We
467 * enable it if possible:
468 * - plane A only (on pre-965)
469 * - no pixel mulitply/line duplication
470 * - no alpha buffer discard
472 * - framebuffer <= max_hdisplay in width, max_vdisplay in height
474 * We can't assume that any compression will take place (worst case),
475 * so the compressed buffer has to be the same size as the uncompressed
476 * one. It also must reside (along with the line length buffer) in
479 * We need to enable/disable FBC on a global basis.
481 void intel_update_fbc(struct drm_device
*dev
)
483 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
484 struct drm_crtc
*crtc
= NULL
, *tmp_crtc
;
485 struct intel_crtc
*intel_crtc
;
486 struct drm_framebuffer
*fb
;
487 struct drm_i915_gem_object
*obj
;
488 const struct drm_display_mode
*adjusted_mode
;
489 unsigned int max_width
, max_height
;
492 set_no_fbc_reason(dev_priv
, FBC_UNSUPPORTED
);
496 if (!i915
.powersave
) {
497 if (set_no_fbc_reason(dev_priv
, FBC_MODULE_PARAM
))
498 DRM_DEBUG_KMS("fbc disabled per module param\n");
503 * If FBC is already on, we just have to verify that we can
504 * keep it that way...
505 * Need to disable if:
506 * - more than one pipe is active
507 * - changing FBC params (stride, fence, mode)
508 * - new fb is too large to fit in compressed buffer
509 * - going to an unsupported config (interlace, pixel multiply, etc.)
511 for_each_crtc(dev
, tmp_crtc
) {
512 if (intel_crtc_active(tmp_crtc
) &&
513 to_intel_crtc(tmp_crtc
)->primary_enabled
) {
515 if (set_no_fbc_reason(dev_priv
, FBC_MULTIPLE_PIPES
))
516 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
523 if (!crtc
|| crtc
->primary
->fb
== NULL
) {
524 if (set_no_fbc_reason(dev_priv
, FBC_NO_OUTPUT
))
525 DRM_DEBUG_KMS("no output, disabling\n");
529 intel_crtc
= to_intel_crtc(crtc
);
530 fb
= crtc
->primary
->fb
;
531 obj
= intel_fb_obj(fb
);
532 adjusted_mode
= &intel_crtc
->config
.adjusted_mode
;
534 if (i915
.enable_fbc
< 0) {
535 if (set_no_fbc_reason(dev_priv
, FBC_CHIP_DEFAULT
))
536 DRM_DEBUG_KMS("disabled per chip default\n");
539 if (!i915
.enable_fbc
) {
540 if (set_no_fbc_reason(dev_priv
, FBC_MODULE_PARAM
))
541 DRM_DEBUG_KMS("fbc disabled per module param\n");
544 if ((adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) ||
545 (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLSCAN
)) {
546 if (set_no_fbc_reason(dev_priv
, FBC_UNSUPPORTED_MODE
))
547 DRM_DEBUG_KMS("mode incompatible with compression, "
552 if (INTEL_INFO(dev
)->gen
>= 8 || IS_HASWELL(dev
)) {
555 } else if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5) {
562 if (intel_crtc
->config
.pipe_src_w
> max_width
||
563 intel_crtc
->config
.pipe_src_h
> max_height
) {
564 if (set_no_fbc_reason(dev_priv
, FBC_MODE_TOO_LARGE
))
565 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
568 if ((INTEL_INFO(dev
)->gen
< 4 || HAS_DDI(dev
)) &&
569 intel_crtc
->plane
!= PLANE_A
) {
570 if (set_no_fbc_reason(dev_priv
, FBC_BAD_PLANE
))
571 DRM_DEBUG_KMS("plane not A, disabling compression\n");
575 /* The use of a CPU fence is mandatory in order to detect writes
576 * by the CPU to the scanout and trigger updates to the FBC.
578 if (obj
->tiling_mode
!= I915_TILING_X
||
579 obj
->fence_reg
== I915_FENCE_REG_NONE
) {
580 if (set_no_fbc_reason(dev_priv
, FBC_NOT_TILED
))
581 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
585 /* If the kernel debugger is active, always disable compression */
589 if (i915_gem_stolen_setup_compression(dev
, obj
->base
.size
,
590 drm_format_plane_cpp(fb
->pixel_format
, 0))) {
591 if (set_no_fbc_reason(dev_priv
, FBC_STOLEN_TOO_SMALL
))
592 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
596 /* If the scanout has not changed, don't modify the FBC settings.
597 * Note that we make the fundamental assumption that the fb->obj
598 * cannot be unpinned (and have its GTT offset and fence revoked)
599 * without first being decoupled from the scanout and FBC disabled.
601 if (dev_priv
->fbc
.plane
== intel_crtc
->plane
&&
602 dev_priv
->fbc
.fb_id
== fb
->base
.id
&&
603 dev_priv
->fbc
.y
== crtc
->y
)
606 if (intel_fbc_enabled(dev
)) {
607 /* We update FBC along two paths, after changing fb/crtc
608 * configuration (modeswitching) and after page-flipping
609 * finishes. For the latter, we know that not only did
610 * we disable the FBC at the start of the page-flip
611 * sequence, but also more than one vblank has passed.
613 * For the former case of modeswitching, it is possible
614 * to switch between two FBC valid configurations
615 * instantaneously so we do need to disable the FBC
616 * before we can modify its control registers. We also
617 * have to wait for the next vblank for that to take
618 * effect. However, since we delay enabling FBC we can
619 * assume that a vblank has passed since disabling and
620 * that we can safely alter the registers in the deferred
623 * In the scenario that we go from a valid to invalid
624 * and then back to valid FBC configuration we have
625 * no strict enforcement that a vblank occurred since
626 * disabling the FBC. However, along all current pipe
627 * disabling paths we do need to wait for a vblank at
628 * some point. And we wait before enabling FBC anyway.
630 DRM_DEBUG_KMS("disabling active FBC for update\n");
631 intel_disable_fbc(dev
);
634 intel_enable_fbc(crtc
);
635 dev_priv
->fbc
.no_fbc_reason
= FBC_OK
;
639 /* Multiple disables should be harmless */
640 if (intel_fbc_enabled(dev
)) {
641 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
642 intel_disable_fbc(dev
);
644 i915_gem_stolen_cleanup_compression(dev
);
647 static void i915_pineview_get_mem_freq(struct drm_device
*dev
)
649 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
652 tmp
= I915_READ(CLKCFG
);
654 switch (tmp
& CLKCFG_FSB_MASK
) {
656 dev_priv
->fsb_freq
= 533; /* 133*4 */
659 dev_priv
->fsb_freq
= 800; /* 200*4 */
662 dev_priv
->fsb_freq
= 667; /* 167*4 */
665 dev_priv
->fsb_freq
= 400; /* 100*4 */
669 switch (tmp
& CLKCFG_MEM_MASK
) {
671 dev_priv
->mem_freq
= 533;
674 dev_priv
->mem_freq
= 667;
677 dev_priv
->mem_freq
= 800;
681 /* detect pineview DDR3 setting */
682 tmp
= I915_READ(CSHRDDR3CTL
);
683 dev_priv
->is_ddr3
= (tmp
& CSHRDDR3CTL_DDR3
) ? 1 : 0;
686 static void i915_ironlake_get_mem_freq(struct drm_device
*dev
)
688 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
691 ddrpll
= I915_READ16(DDRMPLL1
);
692 csipll
= I915_READ16(CSIPLL0
);
694 switch (ddrpll
& 0xff) {
696 dev_priv
->mem_freq
= 800;
699 dev_priv
->mem_freq
= 1066;
702 dev_priv
->mem_freq
= 1333;
705 dev_priv
->mem_freq
= 1600;
708 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
710 dev_priv
->mem_freq
= 0;
714 dev_priv
->ips
.r_t
= dev_priv
->mem_freq
;
716 switch (csipll
& 0x3ff) {
718 dev_priv
->fsb_freq
= 3200;
721 dev_priv
->fsb_freq
= 3733;
724 dev_priv
->fsb_freq
= 4266;
727 dev_priv
->fsb_freq
= 4800;
730 dev_priv
->fsb_freq
= 5333;
733 dev_priv
->fsb_freq
= 5866;
736 dev_priv
->fsb_freq
= 6400;
739 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
741 dev_priv
->fsb_freq
= 0;
745 if (dev_priv
->fsb_freq
== 3200) {
746 dev_priv
->ips
.c_m
= 0;
747 } else if (dev_priv
->fsb_freq
> 3200 && dev_priv
->fsb_freq
<= 4800) {
748 dev_priv
->ips
.c_m
= 1;
750 dev_priv
->ips
.c_m
= 2;
754 static const struct cxsr_latency cxsr_latency_table
[] = {
755 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
756 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
757 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
758 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
759 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
761 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
762 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
763 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
764 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
765 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
767 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
768 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
769 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
770 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
771 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
773 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
774 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
775 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
776 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
777 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
779 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
780 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
781 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
782 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
783 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
785 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
786 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
787 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
788 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
789 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
792 static const struct cxsr_latency
*intel_get_cxsr_latency(int is_desktop
,
797 const struct cxsr_latency
*latency
;
800 if (fsb
== 0 || mem
== 0)
803 for (i
= 0; i
< ARRAY_SIZE(cxsr_latency_table
); i
++) {
804 latency
= &cxsr_latency_table
[i
];
805 if (is_desktop
== latency
->is_desktop
&&
806 is_ddr3
== latency
->is_ddr3
&&
807 fsb
== latency
->fsb_freq
&& mem
== latency
->mem_freq
)
811 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
816 void intel_set_memory_cxsr(struct drm_i915_private
*dev_priv
, bool enable
)
818 struct drm_device
*dev
= dev_priv
->dev
;
821 if (IS_VALLEYVIEW(dev
)) {
822 I915_WRITE(FW_BLC_SELF_VLV
, enable
? FW_CSPWRDWNEN
: 0);
823 } else if (IS_G4X(dev
) || IS_CRESTLINE(dev
)) {
824 I915_WRITE(FW_BLC_SELF
, enable
? FW_BLC_SELF_EN
: 0);
825 } else if (IS_PINEVIEW(dev
)) {
826 val
= I915_READ(DSPFW3
) & ~PINEVIEW_SELF_REFRESH_EN
;
827 val
|= enable
? PINEVIEW_SELF_REFRESH_EN
: 0;
828 I915_WRITE(DSPFW3
, val
);
829 } else if (IS_I945G(dev
) || IS_I945GM(dev
)) {
830 val
= enable
? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN
) :
831 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN
);
832 I915_WRITE(FW_BLC_SELF
, val
);
833 } else if (IS_I915GM(dev
)) {
834 val
= enable
? _MASKED_BIT_ENABLE(INSTPM_SELF_EN
) :
835 _MASKED_BIT_DISABLE(INSTPM_SELF_EN
);
836 I915_WRITE(INSTPM
, val
);
841 DRM_DEBUG_KMS("memory self-refresh is %s\n",
842 enable
? "enabled" : "disabled");
846 * Latency for FIFO fetches is dependent on several factors:
847 * - memory configuration (speed, channels)
849 * - current MCH state
850 * It can be fairly high in some situations, so here we assume a fairly
851 * pessimal value. It's a tradeoff between extra memory fetches (if we
852 * set this value too high, the FIFO will fetch frequently to stay full)
853 * and power consumption (set it too low to save power and we might see
854 * FIFO underruns and display "flicker").
856 * A value of 5us seems to be a good balance; safe for very low end
857 * platforms but not overly aggressive on lower latency configs.
859 static const int latency_ns
= 5000;
861 static int i9xx_get_fifo_size(struct drm_device
*dev
, int plane
)
863 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
864 uint32_t dsparb
= I915_READ(DSPARB
);
867 size
= dsparb
& 0x7f;
869 size
= ((dsparb
>> DSPARB_CSTART_SHIFT
) & 0x7f) - size
;
871 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
872 plane
? "B" : "A", size
);
877 static int i830_get_fifo_size(struct drm_device
*dev
, int plane
)
879 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
880 uint32_t dsparb
= I915_READ(DSPARB
);
883 size
= dsparb
& 0x1ff;
885 size
= ((dsparb
>> DSPARB_BEND_SHIFT
) & 0x1ff) - size
;
886 size
>>= 1; /* Convert to cachelines */
888 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
889 plane
? "B" : "A", size
);
894 static int i845_get_fifo_size(struct drm_device
*dev
, int plane
)
896 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
897 uint32_t dsparb
= I915_READ(DSPARB
);
900 size
= dsparb
& 0x7f;
901 size
>>= 2; /* Convert to cachelines */
903 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
910 /* Pineview has different values for various configs */
911 static const struct intel_watermark_params pineview_display_wm
= {
912 .fifo_size
= PINEVIEW_DISPLAY_FIFO
,
913 .max_wm
= PINEVIEW_MAX_WM
,
914 .default_wm
= PINEVIEW_DFT_WM
,
915 .guard_size
= PINEVIEW_GUARD_WM
,
916 .cacheline_size
= PINEVIEW_FIFO_LINE_SIZE
,
918 static const struct intel_watermark_params pineview_display_hplloff_wm
= {
919 .fifo_size
= PINEVIEW_DISPLAY_FIFO
,
920 .max_wm
= PINEVIEW_MAX_WM
,
921 .default_wm
= PINEVIEW_DFT_HPLLOFF_WM
,
922 .guard_size
= PINEVIEW_GUARD_WM
,
923 .cacheline_size
= PINEVIEW_FIFO_LINE_SIZE
,
925 static const struct intel_watermark_params pineview_cursor_wm
= {
926 .fifo_size
= PINEVIEW_CURSOR_FIFO
,
927 .max_wm
= PINEVIEW_CURSOR_MAX_WM
,
928 .default_wm
= PINEVIEW_CURSOR_DFT_WM
,
929 .guard_size
= PINEVIEW_CURSOR_GUARD_WM
,
930 .cacheline_size
= PINEVIEW_FIFO_LINE_SIZE
,
932 static const struct intel_watermark_params pineview_cursor_hplloff_wm
= {
933 .fifo_size
= PINEVIEW_CURSOR_FIFO
,
934 .max_wm
= PINEVIEW_CURSOR_MAX_WM
,
935 .default_wm
= PINEVIEW_CURSOR_DFT_WM
,
936 .guard_size
= PINEVIEW_CURSOR_GUARD_WM
,
937 .cacheline_size
= PINEVIEW_FIFO_LINE_SIZE
,
939 static const struct intel_watermark_params g4x_wm_info
= {
940 .fifo_size
= G4X_FIFO_SIZE
,
941 .max_wm
= G4X_MAX_WM
,
942 .default_wm
= G4X_MAX_WM
,
944 .cacheline_size
= G4X_FIFO_LINE_SIZE
,
946 static const struct intel_watermark_params g4x_cursor_wm_info
= {
947 .fifo_size
= I965_CURSOR_FIFO
,
948 .max_wm
= I965_CURSOR_MAX_WM
,
949 .default_wm
= I965_CURSOR_DFT_WM
,
951 .cacheline_size
= G4X_FIFO_LINE_SIZE
,
953 static const struct intel_watermark_params valleyview_wm_info
= {
954 .fifo_size
= VALLEYVIEW_FIFO_SIZE
,
955 .max_wm
= VALLEYVIEW_MAX_WM
,
956 .default_wm
= VALLEYVIEW_MAX_WM
,
958 .cacheline_size
= G4X_FIFO_LINE_SIZE
,
960 static const struct intel_watermark_params valleyview_cursor_wm_info
= {
961 .fifo_size
= I965_CURSOR_FIFO
,
962 .max_wm
= VALLEYVIEW_CURSOR_MAX_WM
,
963 .default_wm
= I965_CURSOR_DFT_WM
,
965 .cacheline_size
= G4X_FIFO_LINE_SIZE
,
967 static const struct intel_watermark_params i965_cursor_wm_info
= {
968 .fifo_size
= I965_CURSOR_FIFO
,
969 .max_wm
= I965_CURSOR_MAX_WM
,
970 .default_wm
= I965_CURSOR_DFT_WM
,
972 .cacheline_size
= I915_FIFO_LINE_SIZE
,
974 static const struct intel_watermark_params i945_wm_info
= {
975 .fifo_size
= I945_FIFO_SIZE
,
976 .max_wm
= I915_MAX_WM
,
979 .cacheline_size
= I915_FIFO_LINE_SIZE
,
981 static const struct intel_watermark_params i915_wm_info
= {
982 .fifo_size
= I915_FIFO_SIZE
,
983 .max_wm
= I915_MAX_WM
,
986 .cacheline_size
= I915_FIFO_LINE_SIZE
,
988 static const struct intel_watermark_params i830_wm_info
= {
989 .fifo_size
= I855GM_FIFO_SIZE
,
990 .max_wm
= I915_MAX_WM
,
993 .cacheline_size
= I830_FIFO_LINE_SIZE
,
995 static const struct intel_watermark_params i845_wm_info
= {
996 .fifo_size
= I830_FIFO_SIZE
,
997 .max_wm
= I915_MAX_WM
,
1000 .cacheline_size
= I830_FIFO_LINE_SIZE
,
1004 * intel_calculate_wm - calculate watermark level
1005 * @clock_in_khz: pixel clock
1006 * @wm: chip FIFO params
1007 * @pixel_size: display pixel size
1008 * @latency_ns: memory latency for the platform
1010 * Calculate the watermark level (the level at which the display plane will
1011 * start fetching from memory again). Each chip has a different display
1012 * FIFO size and allocation, so the caller needs to figure that out and pass
1013 * in the correct intel_watermark_params structure.
1015 * As the pixel clock runs, the FIFO will be drained at a rate that depends
1016 * on the pixel size. When it reaches the watermark level, it'll start
1017 * fetching FIFO line sized based chunks from memory until the FIFO fills
1018 * past the watermark point. If the FIFO drains completely, a FIFO underrun
1019 * will occur, and a display engine hang could result.
1021 static unsigned long intel_calculate_wm(unsigned long clock_in_khz
,
1022 const struct intel_watermark_params
*wm
,
1025 unsigned long latency_ns
)
1027 long entries_required
, wm_size
;
1030 * Note: we need to make sure we don't overflow for various clock &
1032 * clocks go from a few thousand to several hundred thousand.
1033 * latency is usually a few thousand
1035 entries_required
= ((clock_in_khz
/ 1000) * pixel_size
* latency_ns
) /
1037 entries_required
= DIV_ROUND_UP(entries_required
, wm
->cacheline_size
);
1039 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required
);
1041 wm_size
= fifo_size
- (entries_required
+ wm
->guard_size
);
1043 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size
);
1045 /* Don't promote wm_size to unsigned... */
1046 if (wm_size
> (long)wm
->max_wm
)
1047 wm_size
= wm
->max_wm
;
1049 wm_size
= wm
->default_wm
;
1053 static struct drm_crtc
*single_enabled_crtc(struct drm_device
*dev
)
1055 struct drm_crtc
*crtc
, *enabled
= NULL
;
1057 for_each_crtc(dev
, crtc
) {
1058 if (intel_crtc_active(crtc
)) {
1068 static void pineview_update_wm(struct drm_crtc
*unused_crtc
)
1070 struct drm_device
*dev
= unused_crtc
->dev
;
1071 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1072 struct drm_crtc
*crtc
;
1073 const struct cxsr_latency
*latency
;
1077 latency
= intel_get_cxsr_latency(IS_PINEVIEW_G(dev
), dev_priv
->is_ddr3
,
1078 dev_priv
->fsb_freq
, dev_priv
->mem_freq
);
1080 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1081 intel_set_memory_cxsr(dev_priv
, false);
1085 crtc
= single_enabled_crtc(dev
);
1087 const struct drm_display_mode
*adjusted_mode
;
1088 int pixel_size
= crtc
->primary
->fb
->bits_per_pixel
/ 8;
1091 adjusted_mode
= &to_intel_crtc(crtc
)->config
.adjusted_mode
;
1092 clock
= adjusted_mode
->crtc_clock
;
1095 wm
= intel_calculate_wm(clock
, &pineview_display_wm
,
1096 pineview_display_wm
.fifo_size
,
1097 pixel_size
, latency
->display_sr
);
1098 reg
= I915_READ(DSPFW1
);
1099 reg
&= ~DSPFW_SR_MASK
;
1100 reg
|= wm
<< DSPFW_SR_SHIFT
;
1101 I915_WRITE(DSPFW1
, reg
);
1102 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg
);
1105 wm
= intel_calculate_wm(clock
, &pineview_cursor_wm
,
1106 pineview_display_wm
.fifo_size
,
1107 pixel_size
, latency
->cursor_sr
);
1108 reg
= I915_READ(DSPFW3
);
1109 reg
&= ~DSPFW_CURSOR_SR_MASK
;
1110 reg
|= (wm
& 0x3f) << DSPFW_CURSOR_SR_SHIFT
;
1111 I915_WRITE(DSPFW3
, reg
);
1113 /* Display HPLL off SR */
1114 wm
= intel_calculate_wm(clock
, &pineview_display_hplloff_wm
,
1115 pineview_display_hplloff_wm
.fifo_size
,
1116 pixel_size
, latency
->display_hpll_disable
);
1117 reg
= I915_READ(DSPFW3
);
1118 reg
&= ~DSPFW_HPLL_SR_MASK
;
1119 reg
|= wm
& DSPFW_HPLL_SR_MASK
;
1120 I915_WRITE(DSPFW3
, reg
);
1122 /* cursor HPLL off SR */
1123 wm
= intel_calculate_wm(clock
, &pineview_cursor_hplloff_wm
,
1124 pineview_display_hplloff_wm
.fifo_size
,
1125 pixel_size
, latency
->cursor_hpll_disable
);
1126 reg
= I915_READ(DSPFW3
);
1127 reg
&= ~DSPFW_HPLL_CURSOR_MASK
;
1128 reg
|= (wm
& 0x3f) << DSPFW_HPLL_CURSOR_SHIFT
;
1129 I915_WRITE(DSPFW3
, reg
);
1130 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg
);
1132 intel_set_memory_cxsr(dev_priv
, true);
1134 intel_set_memory_cxsr(dev_priv
, false);
1138 static bool g4x_compute_wm0(struct drm_device
*dev
,
1140 const struct intel_watermark_params
*display
,
1141 int display_latency_ns
,
1142 const struct intel_watermark_params
*cursor
,
1143 int cursor_latency_ns
,
1147 struct drm_crtc
*crtc
;
1148 const struct drm_display_mode
*adjusted_mode
;
1149 int htotal
, hdisplay
, clock
, pixel_size
;
1150 int line_time_us
, line_count
;
1151 int entries
, tlb_miss
;
1153 crtc
= intel_get_crtc_for_plane(dev
, plane
);
1154 if (!intel_crtc_active(crtc
)) {
1155 *cursor_wm
= cursor
->guard_size
;
1156 *plane_wm
= display
->guard_size
;
1160 adjusted_mode
= &to_intel_crtc(crtc
)->config
.adjusted_mode
;
1161 clock
= adjusted_mode
->crtc_clock
;
1162 htotal
= adjusted_mode
->crtc_htotal
;
1163 hdisplay
= to_intel_crtc(crtc
)->config
.pipe_src_w
;
1164 pixel_size
= crtc
->primary
->fb
->bits_per_pixel
/ 8;
1166 /* Use the small buffer method to calculate plane watermark */
1167 entries
= ((clock
* pixel_size
/ 1000) * display_latency_ns
) / 1000;
1168 tlb_miss
= display
->fifo_size
*display
->cacheline_size
- hdisplay
* 8;
1170 entries
+= tlb_miss
;
1171 entries
= DIV_ROUND_UP(entries
, display
->cacheline_size
);
1172 *plane_wm
= entries
+ display
->guard_size
;
1173 if (*plane_wm
> (int)display
->max_wm
)
1174 *plane_wm
= display
->max_wm
;
1176 /* Use the large buffer method to calculate cursor watermark */
1177 line_time_us
= max(htotal
* 1000 / clock
, 1);
1178 line_count
= (cursor_latency_ns
/ line_time_us
+ 1000) / 1000;
1179 entries
= line_count
* to_intel_crtc(crtc
)->cursor_width
* pixel_size
;
1180 tlb_miss
= cursor
->fifo_size
*cursor
->cacheline_size
- hdisplay
* 8;
1182 entries
+= tlb_miss
;
1183 entries
= DIV_ROUND_UP(entries
, cursor
->cacheline_size
);
1184 *cursor_wm
= entries
+ cursor
->guard_size
;
1185 if (*cursor_wm
> (int)cursor
->max_wm
)
1186 *cursor_wm
= (int)cursor
->max_wm
;
1192 * Check the wm result.
1194 * If any calculated watermark values is larger than the maximum value that
1195 * can be programmed into the associated watermark register, that watermark
1198 static bool g4x_check_srwm(struct drm_device
*dev
,
1199 int display_wm
, int cursor_wm
,
1200 const struct intel_watermark_params
*display
,
1201 const struct intel_watermark_params
*cursor
)
1203 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1204 display_wm
, cursor_wm
);
1206 if (display_wm
> display
->max_wm
) {
1207 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1208 display_wm
, display
->max_wm
);
1212 if (cursor_wm
> cursor
->max_wm
) {
1213 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1214 cursor_wm
, cursor
->max_wm
);
1218 if (!(display_wm
|| cursor_wm
)) {
1219 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1226 static bool g4x_compute_srwm(struct drm_device
*dev
,
1229 const struct intel_watermark_params
*display
,
1230 const struct intel_watermark_params
*cursor
,
1231 int *display_wm
, int *cursor_wm
)
1233 struct drm_crtc
*crtc
;
1234 const struct drm_display_mode
*adjusted_mode
;
1235 int hdisplay
, htotal
, pixel_size
, clock
;
1236 unsigned long line_time_us
;
1237 int line_count
, line_size
;
1242 *display_wm
= *cursor_wm
= 0;
1246 crtc
= intel_get_crtc_for_plane(dev
, plane
);
1247 adjusted_mode
= &to_intel_crtc(crtc
)->config
.adjusted_mode
;
1248 clock
= adjusted_mode
->crtc_clock
;
1249 htotal
= adjusted_mode
->crtc_htotal
;
1250 hdisplay
= to_intel_crtc(crtc
)->config
.pipe_src_w
;
1251 pixel_size
= crtc
->primary
->fb
->bits_per_pixel
/ 8;
1253 line_time_us
= max(htotal
* 1000 / clock
, 1);
1254 line_count
= (latency_ns
/ line_time_us
+ 1000) / 1000;
1255 line_size
= hdisplay
* pixel_size
;
1257 /* Use the minimum of the small and large buffer method for primary */
1258 small
= ((clock
* pixel_size
/ 1000) * latency_ns
) / 1000;
1259 large
= line_count
* line_size
;
1261 entries
= DIV_ROUND_UP(min(small
, large
), display
->cacheline_size
);
1262 *display_wm
= entries
+ display
->guard_size
;
1264 /* calculate the self-refresh watermark for display cursor */
1265 entries
= line_count
* pixel_size
* to_intel_crtc(crtc
)->cursor_width
;
1266 entries
= DIV_ROUND_UP(entries
, cursor
->cacheline_size
);
1267 *cursor_wm
= entries
+ cursor
->guard_size
;
1269 return g4x_check_srwm(dev
,
1270 *display_wm
, *cursor_wm
,
1274 static bool vlv_compute_drain_latency(struct drm_device
*dev
,
1276 int *plane_prec_mult
,
1278 int *cursor_prec_mult
,
1281 struct drm_crtc
*crtc
;
1282 int clock
, pixel_size
;
1285 crtc
= intel_get_crtc_for_plane(dev
, plane
);
1286 if (!intel_crtc_active(crtc
))
1289 clock
= to_intel_crtc(crtc
)->config
.adjusted_mode
.crtc_clock
;
1290 pixel_size
= crtc
->primary
->fb
->bits_per_pixel
/ 8; /* BPP */
1292 entries
= (clock
/ 1000) * pixel_size
;
1293 *plane_prec_mult
= (entries
> 128) ?
1294 DRAIN_LATENCY_PRECISION_64
: DRAIN_LATENCY_PRECISION_32
;
1295 *plane_dl
= (64 * (*plane_prec_mult
) * 4) / entries
;
1297 entries
= (clock
/ 1000) * 4; /* BPP is always 4 for cursor */
1298 *cursor_prec_mult
= (entries
> 128) ?
1299 DRAIN_LATENCY_PRECISION_64
: DRAIN_LATENCY_PRECISION_32
;
1300 *cursor_dl
= (64 * (*cursor_prec_mult
) * 4) / entries
;
1306 * Update drain latency registers of memory arbiter
1308 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1309 * to be programmed. Each plane has a drain latency multiplier and a drain
1313 static void vlv_update_drain_latency(struct drm_crtc
*crtc
)
1315 struct drm_device
*dev
= crtc
->dev
;
1316 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1317 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
1318 int plane_prec
, plane_dl
;
1319 int cursor_prec
, cursor_dl
;
1320 int plane_prec_mult
, cursor_prec_mult
;
1322 if (vlv_compute_drain_latency(dev
, pipe
, &plane_prec_mult
, &plane_dl
,
1323 &cursor_prec_mult
, &cursor_dl
)) {
1324 cursor_prec
= (cursor_prec_mult
== DRAIN_LATENCY_PRECISION_64
) ?
1325 DDL_CURSOR_PRECISION_64
: DDL_CURSOR_PRECISION_32
;
1326 plane_prec
= (plane_prec_mult
== DRAIN_LATENCY_PRECISION_64
) ?
1327 DDL_PLANE_PRECISION_64
: DDL_PLANE_PRECISION_32
;
1329 I915_WRITE(VLV_DDL(pipe
), cursor_prec
|
1330 (cursor_dl
<< DDL_CURSOR_SHIFT
) |
1331 plane_prec
| (plane_dl
<< DDL_PLANE_SHIFT
));
1335 #define single_plane_enabled(mask) is_power_of_2(mask)
1337 static void valleyview_update_wm(struct drm_crtc
*crtc
)
1339 struct drm_device
*dev
= crtc
->dev
;
1340 static const int sr_latency_ns
= 12000;
1341 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1342 int planea_wm
, planeb_wm
, cursora_wm
, cursorb_wm
;
1343 int plane_sr
, cursor_sr
;
1344 int ignore_plane_sr
, ignore_cursor_sr
;
1345 unsigned int enabled
= 0;
1348 vlv_update_drain_latency(crtc
);
1350 if (g4x_compute_wm0(dev
, PIPE_A
,
1351 &valleyview_wm_info
, latency_ns
,
1352 &valleyview_cursor_wm_info
, latency_ns
,
1353 &planea_wm
, &cursora_wm
))
1354 enabled
|= 1 << PIPE_A
;
1356 if (g4x_compute_wm0(dev
, PIPE_B
,
1357 &valleyview_wm_info
, latency_ns
,
1358 &valleyview_cursor_wm_info
, latency_ns
,
1359 &planeb_wm
, &cursorb_wm
))
1360 enabled
|= 1 << PIPE_B
;
1362 if (single_plane_enabled(enabled
) &&
1363 g4x_compute_srwm(dev
, ffs(enabled
) - 1,
1365 &valleyview_wm_info
,
1366 &valleyview_cursor_wm_info
,
1367 &plane_sr
, &ignore_cursor_sr
) &&
1368 g4x_compute_srwm(dev
, ffs(enabled
) - 1,
1370 &valleyview_wm_info
,
1371 &valleyview_cursor_wm_info
,
1372 &ignore_plane_sr
, &cursor_sr
)) {
1373 cxsr_enabled
= true;
1375 cxsr_enabled
= false;
1376 intel_set_memory_cxsr(dev_priv
, false);
1377 plane_sr
= cursor_sr
= 0;
1380 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1381 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1382 planea_wm
, cursora_wm
,
1383 planeb_wm
, cursorb_wm
,
1384 plane_sr
, cursor_sr
);
1387 (plane_sr
<< DSPFW_SR_SHIFT
) |
1388 (cursorb_wm
<< DSPFW_CURSORB_SHIFT
) |
1389 (planeb_wm
<< DSPFW_PLANEB_SHIFT
) |
1390 (planea_wm
<< DSPFW_PLANEA_SHIFT
));
1392 (I915_READ(DSPFW2
) & ~DSPFW_CURSORA_MASK
) |
1393 (cursora_wm
<< DSPFW_CURSORA_SHIFT
));
1395 (I915_READ(DSPFW3
) & ~DSPFW_CURSOR_SR_MASK
) |
1396 (cursor_sr
<< DSPFW_CURSOR_SR_SHIFT
));
1399 intel_set_memory_cxsr(dev_priv
, true);
1402 static void cherryview_update_wm(struct drm_crtc
*crtc
)
1404 struct drm_device
*dev
= crtc
->dev
;
1405 static const int sr_latency_ns
= 12000;
1406 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1407 int planea_wm
, planeb_wm
, planec_wm
;
1408 int cursora_wm
, cursorb_wm
, cursorc_wm
;
1409 int plane_sr
, cursor_sr
;
1410 int ignore_plane_sr
, ignore_cursor_sr
;
1411 unsigned int enabled
= 0;
1414 vlv_update_drain_latency(crtc
);
1416 if (g4x_compute_wm0(dev
, PIPE_A
,
1417 &valleyview_wm_info
, latency_ns
,
1418 &valleyview_cursor_wm_info
, latency_ns
,
1419 &planea_wm
, &cursora_wm
))
1420 enabled
|= 1 << PIPE_A
;
1422 if (g4x_compute_wm0(dev
, PIPE_B
,
1423 &valleyview_wm_info
, latency_ns
,
1424 &valleyview_cursor_wm_info
, latency_ns
,
1425 &planeb_wm
, &cursorb_wm
))
1426 enabled
|= 1 << PIPE_B
;
1428 if (g4x_compute_wm0(dev
, PIPE_C
,
1429 &valleyview_wm_info
, latency_ns
,
1430 &valleyview_cursor_wm_info
, latency_ns
,
1431 &planec_wm
, &cursorc_wm
))
1432 enabled
|= 1 << PIPE_C
;
1434 if (single_plane_enabled(enabled
) &&
1435 g4x_compute_srwm(dev
, ffs(enabled
) - 1,
1437 &valleyview_wm_info
,
1438 &valleyview_cursor_wm_info
,
1439 &plane_sr
, &ignore_cursor_sr
) &&
1440 g4x_compute_srwm(dev
, ffs(enabled
) - 1,
1442 &valleyview_wm_info
,
1443 &valleyview_cursor_wm_info
,
1444 &ignore_plane_sr
, &cursor_sr
)) {
1445 cxsr_enabled
= true;
1447 cxsr_enabled
= false;
1448 intel_set_memory_cxsr(dev_priv
, false);
1449 plane_sr
= cursor_sr
= 0;
1452 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1453 "B: plane=%d, cursor=%d, C: plane=%d, cursor=%d, "
1454 "SR: plane=%d, cursor=%d\n",
1455 planea_wm
, cursora_wm
,
1456 planeb_wm
, cursorb_wm
,
1457 planec_wm
, cursorc_wm
,
1458 plane_sr
, cursor_sr
);
1461 (plane_sr
<< DSPFW_SR_SHIFT
) |
1462 (cursorb_wm
<< DSPFW_CURSORB_SHIFT
) |
1463 (planeb_wm
<< DSPFW_PLANEB_SHIFT
) |
1464 (planea_wm
<< DSPFW_PLANEA_SHIFT
));
1466 (I915_READ(DSPFW2
) & ~DSPFW_CURSORA_MASK
) |
1467 (cursora_wm
<< DSPFW_CURSORA_SHIFT
));
1469 (I915_READ(DSPFW3
) & ~DSPFW_CURSOR_SR_MASK
) |
1470 (cursor_sr
<< DSPFW_CURSOR_SR_SHIFT
));
1471 I915_WRITE(DSPFW9_CHV
,
1472 (I915_READ(DSPFW9_CHV
) & ~(DSPFW_PLANEC_MASK
|
1473 DSPFW_CURSORC_MASK
)) |
1474 (planec_wm
<< DSPFW_PLANEC_SHIFT
) |
1475 (cursorc_wm
<< DSPFW_CURSORC_SHIFT
));
1478 intel_set_memory_cxsr(dev_priv
, true);
1481 static void g4x_update_wm(struct drm_crtc
*crtc
)
1483 struct drm_device
*dev
= crtc
->dev
;
1484 static const int sr_latency_ns
= 12000;
1485 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1486 int planea_wm
, planeb_wm
, cursora_wm
, cursorb_wm
;
1487 int plane_sr
, cursor_sr
;
1488 unsigned int enabled
= 0;
1491 if (g4x_compute_wm0(dev
, PIPE_A
,
1492 &g4x_wm_info
, latency_ns
,
1493 &g4x_cursor_wm_info
, latency_ns
,
1494 &planea_wm
, &cursora_wm
))
1495 enabled
|= 1 << PIPE_A
;
1497 if (g4x_compute_wm0(dev
, PIPE_B
,
1498 &g4x_wm_info
, latency_ns
,
1499 &g4x_cursor_wm_info
, latency_ns
,
1500 &planeb_wm
, &cursorb_wm
))
1501 enabled
|= 1 << PIPE_B
;
1503 if (single_plane_enabled(enabled
) &&
1504 g4x_compute_srwm(dev
, ffs(enabled
) - 1,
1507 &g4x_cursor_wm_info
,
1508 &plane_sr
, &cursor_sr
)) {
1509 cxsr_enabled
= true;
1511 cxsr_enabled
= false;
1512 intel_set_memory_cxsr(dev_priv
, false);
1513 plane_sr
= cursor_sr
= 0;
1516 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1517 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1518 planea_wm
, cursora_wm
,
1519 planeb_wm
, cursorb_wm
,
1520 plane_sr
, cursor_sr
);
1523 (plane_sr
<< DSPFW_SR_SHIFT
) |
1524 (cursorb_wm
<< DSPFW_CURSORB_SHIFT
) |
1525 (planeb_wm
<< DSPFW_PLANEB_SHIFT
) |
1526 (planea_wm
<< DSPFW_PLANEA_SHIFT
));
1528 (I915_READ(DSPFW2
) & ~DSPFW_CURSORA_MASK
) |
1529 (cursora_wm
<< DSPFW_CURSORA_SHIFT
));
1530 /* HPLL off in SR has some issues on G4x... disable it */
1532 (I915_READ(DSPFW3
) & ~(DSPFW_HPLL_SR_EN
| DSPFW_CURSOR_SR_MASK
)) |
1533 (cursor_sr
<< DSPFW_CURSOR_SR_SHIFT
));
1536 intel_set_memory_cxsr(dev_priv
, true);
1539 static void i965_update_wm(struct drm_crtc
*unused_crtc
)
1541 struct drm_device
*dev
= unused_crtc
->dev
;
1542 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1543 struct drm_crtc
*crtc
;
1548 /* Calc sr entries for one plane configs */
1549 crtc
= single_enabled_crtc(dev
);
1551 /* self-refresh has much higher latency */
1552 static const int sr_latency_ns
= 12000;
1553 const struct drm_display_mode
*adjusted_mode
=
1554 &to_intel_crtc(crtc
)->config
.adjusted_mode
;
1555 int clock
= adjusted_mode
->crtc_clock
;
1556 int htotal
= adjusted_mode
->crtc_htotal
;
1557 int hdisplay
= to_intel_crtc(crtc
)->config
.pipe_src_w
;
1558 int pixel_size
= crtc
->primary
->fb
->bits_per_pixel
/ 8;
1559 unsigned long line_time_us
;
1562 line_time_us
= max(htotal
* 1000 / clock
, 1);
1564 /* Use ns/us then divide to preserve precision */
1565 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
1566 pixel_size
* hdisplay
;
1567 entries
= DIV_ROUND_UP(entries
, I915_FIFO_LINE_SIZE
);
1568 srwm
= I965_FIFO_SIZE
- entries
;
1572 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1575 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
1576 pixel_size
* to_intel_crtc(crtc
)->cursor_width
;
1577 entries
= DIV_ROUND_UP(entries
,
1578 i965_cursor_wm_info
.cacheline_size
);
1579 cursor_sr
= i965_cursor_wm_info
.fifo_size
-
1580 (entries
+ i965_cursor_wm_info
.guard_size
);
1582 if (cursor_sr
> i965_cursor_wm_info
.max_wm
)
1583 cursor_sr
= i965_cursor_wm_info
.max_wm
;
1585 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1586 "cursor %d\n", srwm
, cursor_sr
);
1588 cxsr_enabled
= true;
1590 cxsr_enabled
= false;
1591 /* Turn off self refresh if both pipes are enabled */
1592 intel_set_memory_cxsr(dev_priv
, false);
1595 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1598 /* 965 has limitations... */
1599 I915_WRITE(DSPFW1
, (srwm
<< DSPFW_SR_SHIFT
) |
1600 (8 << DSPFW_CURSORB_SHIFT
) |
1601 (8 << DSPFW_PLANEB_SHIFT
) |
1602 (8 << DSPFW_PLANEA_SHIFT
));
1603 I915_WRITE(DSPFW2
, (8 << DSPFW_CURSORA_SHIFT
) |
1604 (8 << DSPFW_PLANEC_SHIFT_OLD
));
1605 /* update cursor SR watermark */
1606 I915_WRITE(DSPFW3
, (cursor_sr
<< DSPFW_CURSOR_SR_SHIFT
));
1609 intel_set_memory_cxsr(dev_priv
, true);
1612 static void i9xx_update_wm(struct drm_crtc
*unused_crtc
)
1614 struct drm_device
*dev
= unused_crtc
->dev
;
1615 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1616 const struct intel_watermark_params
*wm_info
;
1621 int planea_wm
, planeb_wm
;
1622 struct drm_crtc
*crtc
, *enabled
= NULL
;
1625 wm_info
= &i945_wm_info
;
1626 else if (!IS_GEN2(dev
))
1627 wm_info
= &i915_wm_info
;
1629 wm_info
= &i830_wm_info
;
1631 fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 0);
1632 crtc
= intel_get_crtc_for_plane(dev
, 0);
1633 if (intel_crtc_active(crtc
)) {
1634 const struct drm_display_mode
*adjusted_mode
;
1635 int cpp
= crtc
->primary
->fb
->bits_per_pixel
/ 8;
1639 adjusted_mode
= &to_intel_crtc(crtc
)->config
.adjusted_mode
;
1640 planea_wm
= intel_calculate_wm(adjusted_mode
->crtc_clock
,
1641 wm_info
, fifo_size
, cpp
,
1645 planea_wm
= fifo_size
- wm_info
->guard_size
;
1647 fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 1);
1648 crtc
= intel_get_crtc_for_plane(dev
, 1);
1649 if (intel_crtc_active(crtc
)) {
1650 const struct drm_display_mode
*adjusted_mode
;
1651 int cpp
= crtc
->primary
->fb
->bits_per_pixel
/ 8;
1655 adjusted_mode
= &to_intel_crtc(crtc
)->config
.adjusted_mode
;
1656 planeb_wm
= intel_calculate_wm(adjusted_mode
->crtc_clock
,
1657 wm_info
, fifo_size
, cpp
,
1659 if (enabled
== NULL
)
1664 planeb_wm
= fifo_size
- wm_info
->guard_size
;
1666 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm
, planeb_wm
);
1668 if (IS_I915GM(dev
) && enabled
) {
1669 struct drm_i915_gem_object
*obj
;
1671 obj
= intel_fb_obj(enabled
->primary
->fb
);
1673 /* self-refresh seems busted with untiled */
1674 if (obj
->tiling_mode
== I915_TILING_NONE
)
1679 * Overlay gets an aggressive default since video jitter is bad.
1683 /* Play safe and disable self-refresh before adjusting watermarks. */
1684 intel_set_memory_cxsr(dev_priv
, false);
1686 /* Calc sr entries for one plane configs */
1687 if (HAS_FW_BLC(dev
) && enabled
) {
1688 /* self-refresh has much higher latency */
1689 static const int sr_latency_ns
= 6000;
1690 const struct drm_display_mode
*adjusted_mode
=
1691 &to_intel_crtc(enabled
)->config
.adjusted_mode
;
1692 int clock
= adjusted_mode
->crtc_clock
;
1693 int htotal
= adjusted_mode
->crtc_htotal
;
1694 int hdisplay
= to_intel_crtc(enabled
)->config
.pipe_src_w
;
1695 int pixel_size
= enabled
->primary
->fb
->bits_per_pixel
/ 8;
1696 unsigned long line_time_us
;
1699 line_time_us
= max(htotal
* 1000 / clock
, 1);
1701 /* Use ns/us then divide to preserve precision */
1702 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
1703 pixel_size
* hdisplay
;
1704 entries
= DIV_ROUND_UP(entries
, wm_info
->cacheline_size
);
1705 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries
);
1706 srwm
= wm_info
->fifo_size
- entries
;
1710 if (IS_I945G(dev
) || IS_I945GM(dev
))
1711 I915_WRITE(FW_BLC_SELF
,
1712 FW_BLC_SELF_FIFO_MASK
| (srwm
& 0xff));
1713 else if (IS_I915GM(dev
))
1714 I915_WRITE(FW_BLC_SELF
, srwm
& 0x3f);
1717 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1718 planea_wm
, planeb_wm
, cwm
, srwm
);
1720 fwater_lo
= ((planeb_wm
& 0x3f) << 16) | (planea_wm
& 0x3f);
1721 fwater_hi
= (cwm
& 0x1f);
1723 /* Set request length to 8 cachelines per fetch */
1724 fwater_lo
= fwater_lo
| (1 << 24) | (1 << 8);
1725 fwater_hi
= fwater_hi
| (1 << 8);
1727 I915_WRITE(FW_BLC
, fwater_lo
);
1728 I915_WRITE(FW_BLC2
, fwater_hi
);
1731 intel_set_memory_cxsr(dev_priv
, true);
1734 static void i845_update_wm(struct drm_crtc
*unused_crtc
)
1736 struct drm_device
*dev
= unused_crtc
->dev
;
1737 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1738 struct drm_crtc
*crtc
;
1739 const struct drm_display_mode
*adjusted_mode
;
1743 crtc
= single_enabled_crtc(dev
);
1747 adjusted_mode
= &to_intel_crtc(crtc
)->config
.adjusted_mode
;
1748 planea_wm
= intel_calculate_wm(adjusted_mode
->crtc_clock
,
1750 dev_priv
->display
.get_fifo_size(dev
, 0),
1752 fwater_lo
= I915_READ(FW_BLC
) & ~0xfff;
1753 fwater_lo
|= (3<<8) | planea_wm
;
1755 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm
);
1757 I915_WRITE(FW_BLC
, fwater_lo
);
1760 static uint32_t ilk_pipe_pixel_rate(struct drm_device
*dev
,
1761 struct drm_crtc
*crtc
)
1763 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1764 uint32_t pixel_rate
;
1766 pixel_rate
= intel_crtc
->config
.adjusted_mode
.crtc_clock
;
1768 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1769 * adjust the pixel_rate here. */
1771 if (intel_crtc
->config
.pch_pfit
.enabled
) {
1772 uint64_t pipe_w
, pipe_h
, pfit_w
, pfit_h
;
1773 uint32_t pfit_size
= intel_crtc
->config
.pch_pfit
.size
;
1775 pipe_w
= intel_crtc
->config
.pipe_src_w
;
1776 pipe_h
= intel_crtc
->config
.pipe_src_h
;
1777 pfit_w
= (pfit_size
>> 16) & 0xFFFF;
1778 pfit_h
= pfit_size
& 0xFFFF;
1779 if (pipe_w
< pfit_w
)
1781 if (pipe_h
< pfit_h
)
1784 pixel_rate
= div_u64((uint64_t) pixel_rate
* pipe_w
* pipe_h
,
1791 /* latency must be in 0.1us units. */
1792 static uint32_t ilk_wm_method1(uint32_t pixel_rate
, uint8_t bytes_per_pixel
,
1797 if (WARN(latency
== 0, "Latency value missing\n"))
1800 ret
= (uint64_t) pixel_rate
* bytes_per_pixel
* latency
;
1801 ret
= DIV_ROUND_UP_ULL(ret
, 64 * 10000) + 2;
1806 /* latency must be in 0.1us units. */
1807 static uint32_t ilk_wm_method2(uint32_t pixel_rate
, uint32_t pipe_htotal
,
1808 uint32_t horiz_pixels
, uint8_t bytes_per_pixel
,
1813 if (WARN(latency
== 0, "Latency value missing\n"))
1816 ret
= (latency
* pixel_rate
) / (pipe_htotal
* 10000);
1817 ret
= (ret
+ 1) * horiz_pixels
* bytes_per_pixel
;
1818 ret
= DIV_ROUND_UP(ret
, 64) + 2;
1822 static uint32_t ilk_wm_fbc(uint32_t pri_val
, uint32_t horiz_pixels
,
1823 uint8_t bytes_per_pixel
)
1825 return DIV_ROUND_UP(pri_val
* 64, horiz_pixels
* bytes_per_pixel
) + 2;
1828 struct ilk_pipe_wm_parameters
{
1830 uint32_t pipe_htotal
;
1831 uint32_t pixel_rate
;
1832 struct intel_plane_wm_parameters pri
;
1833 struct intel_plane_wm_parameters spr
;
1834 struct intel_plane_wm_parameters cur
;
1837 struct ilk_wm_maximums
{
1844 /* used in computing the new watermarks state */
1845 struct intel_wm_config
{
1846 unsigned int num_pipes_active
;
1847 bool sprites_enabled
;
1848 bool sprites_scaled
;
1852 * For both WM_PIPE and WM_LP.
1853 * mem_value must be in 0.1us units.
1855 static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters
*params
,
1859 uint32_t method1
, method2
;
1861 if (!params
->active
|| !params
->pri
.enabled
)
1864 method1
= ilk_wm_method1(params
->pixel_rate
,
1865 params
->pri
.bytes_per_pixel
,
1871 method2
= ilk_wm_method2(params
->pixel_rate
,
1872 params
->pipe_htotal
,
1873 params
->pri
.horiz_pixels
,
1874 params
->pri
.bytes_per_pixel
,
1877 return min(method1
, method2
);
1881 * For both WM_PIPE and WM_LP.
1882 * mem_value must be in 0.1us units.
1884 static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters
*params
,
1887 uint32_t method1
, method2
;
1889 if (!params
->active
|| !params
->spr
.enabled
)
1892 method1
= ilk_wm_method1(params
->pixel_rate
,
1893 params
->spr
.bytes_per_pixel
,
1895 method2
= ilk_wm_method2(params
->pixel_rate
,
1896 params
->pipe_htotal
,
1897 params
->spr
.horiz_pixels
,
1898 params
->spr
.bytes_per_pixel
,
1900 return min(method1
, method2
);
1904 * For both WM_PIPE and WM_LP.
1905 * mem_value must be in 0.1us units.
1907 static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters
*params
,
1910 if (!params
->active
|| !params
->cur
.enabled
)
1913 return ilk_wm_method2(params
->pixel_rate
,
1914 params
->pipe_htotal
,
1915 params
->cur
.horiz_pixels
,
1916 params
->cur
.bytes_per_pixel
,
1920 /* Only for WM_LP. */
1921 static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters
*params
,
1924 if (!params
->active
|| !params
->pri
.enabled
)
1927 return ilk_wm_fbc(pri_val
,
1928 params
->pri
.horiz_pixels
,
1929 params
->pri
.bytes_per_pixel
);
1932 static unsigned int ilk_display_fifo_size(const struct drm_device
*dev
)
1934 if (INTEL_INFO(dev
)->gen
>= 8)
1936 else if (INTEL_INFO(dev
)->gen
>= 7)
1942 static unsigned int ilk_plane_wm_reg_max(const struct drm_device
*dev
,
1943 int level
, bool is_sprite
)
1945 if (INTEL_INFO(dev
)->gen
>= 8)
1946 /* BDW primary/sprite plane watermarks */
1947 return level
== 0 ? 255 : 2047;
1948 else if (INTEL_INFO(dev
)->gen
>= 7)
1949 /* IVB/HSW primary/sprite plane watermarks */
1950 return level
== 0 ? 127 : 1023;
1951 else if (!is_sprite
)
1952 /* ILK/SNB primary plane watermarks */
1953 return level
== 0 ? 127 : 511;
1955 /* ILK/SNB sprite plane watermarks */
1956 return level
== 0 ? 63 : 255;
1959 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device
*dev
,
1962 if (INTEL_INFO(dev
)->gen
>= 7)
1963 return level
== 0 ? 63 : 255;
1965 return level
== 0 ? 31 : 63;
1968 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device
*dev
)
1970 if (INTEL_INFO(dev
)->gen
>= 8)
1976 /* Calculate the maximum primary/sprite plane watermark */
1977 static unsigned int ilk_plane_wm_max(const struct drm_device
*dev
,
1979 const struct intel_wm_config
*config
,
1980 enum intel_ddb_partitioning ddb_partitioning
,
1983 unsigned int fifo_size
= ilk_display_fifo_size(dev
);
1985 /* if sprites aren't enabled, sprites get nothing */
1986 if (is_sprite
&& !config
->sprites_enabled
)
1989 /* HSW allows LP1+ watermarks even with multiple pipes */
1990 if (level
== 0 || config
->num_pipes_active
> 1) {
1991 fifo_size
/= INTEL_INFO(dev
)->num_pipes
;
1994 * For some reason the non self refresh
1995 * FIFO size is only half of the self
1996 * refresh FIFO size on ILK/SNB.
1998 if (INTEL_INFO(dev
)->gen
<= 6)
2002 if (config
->sprites_enabled
) {
2003 /* level 0 is always calculated with 1:1 split */
2004 if (level
> 0 && ddb_partitioning
== INTEL_DDB_PART_5_6
) {
2013 /* clamp to max that the registers can hold */
2014 return min(fifo_size
, ilk_plane_wm_reg_max(dev
, level
, is_sprite
));
2017 /* Calculate the maximum cursor plane watermark */
2018 static unsigned int ilk_cursor_wm_max(const struct drm_device
*dev
,
2020 const struct intel_wm_config
*config
)
2022 /* HSW LP1+ watermarks w/ multiple pipes */
2023 if (level
> 0 && config
->num_pipes_active
> 1)
2026 /* otherwise just report max that registers can hold */
2027 return ilk_cursor_wm_reg_max(dev
, level
);
2030 static void ilk_compute_wm_maximums(const struct drm_device
*dev
,
2032 const struct intel_wm_config
*config
,
2033 enum intel_ddb_partitioning ddb_partitioning
,
2034 struct ilk_wm_maximums
*max
)
2036 max
->pri
= ilk_plane_wm_max(dev
, level
, config
, ddb_partitioning
, false);
2037 max
->spr
= ilk_plane_wm_max(dev
, level
, config
, ddb_partitioning
, true);
2038 max
->cur
= ilk_cursor_wm_max(dev
, level
, config
);
2039 max
->fbc
= ilk_fbc_wm_reg_max(dev
);
2042 static void ilk_compute_wm_reg_maximums(struct drm_device
*dev
,
2044 struct ilk_wm_maximums
*max
)
2046 max
->pri
= ilk_plane_wm_reg_max(dev
, level
, false);
2047 max
->spr
= ilk_plane_wm_reg_max(dev
, level
, true);
2048 max
->cur
= ilk_cursor_wm_reg_max(dev
, level
);
2049 max
->fbc
= ilk_fbc_wm_reg_max(dev
);
2052 static bool ilk_validate_wm_level(int level
,
2053 const struct ilk_wm_maximums
*max
,
2054 struct intel_wm_level
*result
)
2058 /* already determined to be invalid? */
2059 if (!result
->enable
)
2062 result
->enable
= result
->pri_val
<= max
->pri
&&
2063 result
->spr_val
<= max
->spr
&&
2064 result
->cur_val
<= max
->cur
;
2066 ret
= result
->enable
;
2069 * HACK until we can pre-compute everything,
2070 * and thus fail gracefully if LP0 watermarks
2073 if (level
== 0 && !result
->enable
) {
2074 if (result
->pri_val
> max
->pri
)
2075 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2076 level
, result
->pri_val
, max
->pri
);
2077 if (result
->spr_val
> max
->spr
)
2078 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2079 level
, result
->spr_val
, max
->spr
);
2080 if (result
->cur_val
> max
->cur
)
2081 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2082 level
, result
->cur_val
, max
->cur
);
2084 result
->pri_val
= min_t(uint32_t, result
->pri_val
, max
->pri
);
2085 result
->spr_val
= min_t(uint32_t, result
->spr_val
, max
->spr
);
2086 result
->cur_val
= min_t(uint32_t, result
->cur_val
, max
->cur
);
2087 result
->enable
= true;
2093 static void ilk_compute_wm_level(const struct drm_i915_private
*dev_priv
,
2095 const struct ilk_pipe_wm_parameters
*p
,
2096 struct intel_wm_level
*result
)
2098 uint16_t pri_latency
= dev_priv
->wm
.pri_latency
[level
];
2099 uint16_t spr_latency
= dev_priv
->wm
.spr_latency
[level
];
2100 uint16_t cur_latency
= dev_priv
->wm
.cur_latency
[level
];
2102 /* WM1+ latency values stored in 0.5us units */
2109 result
->pri_val
= ilk_compute_pri_wm(p
, pri_latency
, level
);
2110 result
->spr_val
= ilk_compute_spr_wm(p
, spr_latency
);
2111 result
->cur_val
= ilk_compute_cur_wm(p
, cur_latency
);
2112 result
->fbc_val
= ilk_compute_fbc_wm(p
, result
->pri_val
);
2113 result
->enable
= true;
2117 hsw_compute_linetime_wm(struct drm_device
*dev
, struct drm_crtc
*crtc
)
2119 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2120 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2121 struct drm_display_mode
*mode
= &intel_crtc
->config
.adjusted_mode
;
2122 u32 linetime
, ips_linetime
;
2124 if (!intel_crtc_active(crtc
))
2127 /* The WM are computed with base on how long it takes to fill a single
2128 * row at the given clock rate, multiplied by 8.
2130 linetime
= DIV_ROUND_CLOSEST(mode
->crtc_htotal
* 1000 * 8,
2132 ips_linetime
= DIV_ROUND_CLOSEST(mode
->crtc_htotal
* 1000 * 8,
2133 intel_ddi_get_cdclk_freq(dev_priv
));
2135 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime
) |
2136 PIPE_WM_LINETIME_TIME(linetime
);
2139 static void intel_read_wm_latency(struct drm_device
*dev
, uint16_t wm
[5])
2141 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2143 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2144 uint64_t sskpd
= I915_READ64(MCH_SSKPD
);
2146 wm
[0] = (sskpd
>> 56) & 0xFF;
2148 wm
[0] = sskpd
& 0xF;
2149 wm
[1] = (sskpd
>> 4) & 0xFF;
2150 wm
[2] = (sskpd
>> 12) & 0xFF;
2151 wm
[3] = (sskpd
>> 20) & 0x1FF;
2152 wm
[4] = (sskpd
>> 32) & 0x1FF;
2153 } else if (INTEL_INFO(dev
)->gen
>= 6) {
2154 uint32_t sskpd
= I915_READ(MCH_SSKPD
);
2156 wm
[0] = (sskpd
>> SSKPD_WM0_SHIFT
) & SSKPD_WM_MASK
;
2157 wm
[1] = (sskpd
>> SSKPD_WM1_SHIFT
) & SSKPD_WM_MASK
;
2158 wm
[2] = (sskpd
>> SSKPD_WM2_SHIFT
) & SSKPD_WM_MASK
;
2159 wm
[3] = (sskpd
>> SSKPD_WM3_SHIFT
) & SSKPD_WM_MASK
;
2160 } else if (INTEL_INFO(dev
)->gen
>= 5) {
2161 uint32_t mltr
= I915_READ(MLTR_ILK
);
2163 /* ILK primary LP0 latency is 700 ns */
2165 wm
[1] = (mltr
>> MLTR_WM1_SHIFT
) & ILK_SRLT_MASK
;
2166 wm
[2] = (mltr
>> MLTR_WM2_SHIFT
) & ILK_SRLT_MASK
;
2170 static void intel_fixup_spr_wm_latency(struct drm_device
*dev
, uint16_t wm
[5])
2172 /* ILK sprite LP0 latency is 1300 ns */
2173 if (INTEL_INFO(dev
)->gen
== 5)
2177 static void intel_fixup_cur_wm_latency(struct drm_device
*dev
, uint16_t wm
[5])
2179 /* ILK cursor LP0 latency is 1300 ns */
2180 if (INTEL_INFO(dev
)->gen
== 5)
2183 /* WaDoubleCursorLP3Latency:ivb */
2184 if (IS_IVYBRIDGE(dev
))
2188 int ilk_wm_max_level(const struct drm_device
*dev
)
2190 /* how many WM levels are we expecting */
2191 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2193 else if (INTEL_INFO(dev
)->gen
>= 6)
2199 static void intel_print_wm_latency(struct drm_device
*dev
,
2201 const uint16_t wm
[5])
2203 int level
, max_level
= ilk_wm_max_level(dev
);
2205 for (level
= 0; level
<= max_level
; level
++) {
2206 unsigned int latency
= wm
[level
];
2209 DRM_ERROR("%s WM%d latency not provided\n",
2214 /* WM1+ latency values in 0.5us units */
2218 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2219 name
, level
, wm
[level
],
2220 latency
/ 10, latency
% 10);
2224 static bool ilk_increase_wm_latency(struct drm_i915_private
*dev_priv
,
2225 uint16_t wm
[5], uint16_t min
)
2227 int level
, max_level
= ilk_wm_max_level(dev_priv
->dev
);
2232 wm
[0] = max(wm
[0], min
);
2233 for (level
= 1; level
<= max_level
; level
++)
2234 wm
[level
] = max_t(uint16_t, wm
[level
], DIV_ROUND_UP(min
, 5));
2239 static void snb_wm_latency_quirk(struct drm_device
*dev
)
2241 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2245 * The BIOS provided WM memory latency values are often
2246 * inadequate for high resolution displays. Adjust them.
2248 changed
= ilk_increase_wm_latency(dev_priv
, dev_priv
->wm
.pri_latency
, 12) |
2249 ilk_increase_wm_latency(dev_priv
, dev_priv
->wm
.spr_latency
, 12) |
2250 ilk_increase_wm_latency(dev_priv
, dev_priv
->wm
.cur_latency
, 12);
2255 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2256 intel_print_wm_latency(dev
, "Primary", dev_priv
->wm
.pri_latency
);
2257 intel_print_wm_latency(dev
, "Sprite", dev_priv
->wm
.spr_latency
);
2258 intel_print_wm_latency(dev
, "Cursor", dev_priv
->wm
.cur_latency
);
2261 static void ilk_setup_wm_latency(struct drm_device
*dev
)
2263 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2265 intel_read_wm_latency(dev
, dev_priv
->wm
.pri_latency
);
2267 memcpy(dev_priv
->wm
.spr_latency
, dev_priv
->wm
.pri_latency
,
2268 sizeof(dev_priv
->wm
.pri_latency
));
2269 memcpy(dev_priv
->wm
.cur_latency
, dev_priv
->wm
.pri_latency
,
2270 sizeof(dev_priv
->wm
.pri_latency
));
2272 intel_fixup_spr_wm_latency(dev
, dev_priv
->wm
.spr_latency
);
2273 intel_fixup_cur_wm_latency(dev
, dev_priv
->wm
.cur_latency
);
2275 intel_print_wm_latency(dev
, "Primary", dev_priv
->wm
.pri_latency
);
2276 intel_print_wm_latency(dev
, "Sprite", dev_priv
->wm
.spr_latency
);
2277 intel_print_wm_latency(dev
, "Cursor", dev_priv
->wm
.cur_latency
);
2280 snb_wm_latency_quirk(dev
);
2283 static void ilk_compute_wm_parameters(struct drm_crtc
*crtc
,
2284 struct ilk_pipe_wm_parameters
*p
)
2286 struct drm_device
*dev
= crtc
->dev
;
2287 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2288 enum pipe pipe
= intel_crtc
->pipe
;
2289 struct drm_plane
*plane
;
2291 if (!intel_crtc_active(crtc
))
2295 p
->pipe_htotal
= intel_crtc
->config
.adjusted_mode
.crtc_htotal
;
2296 p
->pixel_rate
= ilk_pipe_pixel_rate(dev
, crtc
);
2297 p
->pri
.bytes_per_pixel
= crtc
->primary
->fb
->bits_per_pixel
/ 8;
2298 p
->cur
.bytes_per_pixel
= 4;
2299 p
->pri
.horiz_pixels
= intel_crtc
->config
.pipe_src_w
;
2300 p
->cur
.horiz_pixels
= intel_crtc
->cursor_width
;
2301 /* TODO: for now, assume primary and cursor planes are always enabled. */
2302 p
->pri
.enabled
= true;
2303 p
->cur
.enabled
= true;
2305 drm_for_each_legacy_plane(plane
, &dev
->mode_config
.plane_list
) {
2306 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
2308 if (intel_plane
->pipe
== pipe
) {
2309 p
->spr
= intel_plane
->wm
;
2315 static void ilk_compute_wm_config(struct drm_device
*dev
,
2316 struct intel_wm_config
*config
)
2318 struct intel_crtc
*intel_crtc
;
2320 /* Compute the currently _active_ config */
2321 for_each_intel_crtc(dev
, intel_crtc
) {
2322 const struct intel_pipe_wm
*wm
= &intel_crtc
->wm
.active
;
2324 if (!wm
->pipe_enabled
)
2327 config
->sprites_enabled
|= wm
->sprites_enabled
;
2328 config
->sprites_scaled
|= wm
->sprites_scaled
;
2329 config
->num_pipes_active
++;
2333 /* Compute new watermarks for the pipe */
2334 static bool intel_compute_pipe_wm(struct drm_crtc
*crtc
,
2335 const struct ilk_pipe_wm_parameters
*params
,
2336 struct intel_pipe_wm
*pipe_wm
)
2338 struct drm_device
*dev
= crtc
->dev
;
2339 const struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2340 int level
, max_level
= ilk_wm_max_level(dev
);
2341 /* LP0 watermark maximums depend on this pipe alone */
2342 struct intel_wm_config config
= {
2343 .num_pipes_active
= 1,
2344 .sprites_enabled
= params
->spr
.enabled
,
2345 .sprites_scaled
= params
->spr
.scaled
,
2347 struct ilk_wm_maximums max
;
2349 pipe_wm
->pipe_enabled
= params
->active
;
2350 pipe_wm
->sprites_enabled
= params
->spr
.enabled
;
2351 pipe_wm
->sprites_scaled
= params
->spr
.scaled
;
2353 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2354 if (INTEL_INFO(dev
)->gen
<= 6 && params
->spr
.enabled
)
2357 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2358 if (params
->spr
.scaled
)
2361 ilk_compute_wm_level(dev_priv
, 0, params
, &pipe_wm
->wm
[0]);
2363 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2364 pipe_wm
->linetime
= hsw_compute_linetime_wm(dev
, crtc
);
2366 /* LP0 watermarks always use 1/2 DDB partitioning */
2367 ilk_compute_wm_maximums(dev
, 0, &config
, INTEL_DDB_PART_1_2
, &max
);
2369 /* At least LP0 must be valid */
2370 if (!ilk_validate_wm_level(0, &max
, &pipe_wm
->wm
[0]))
2373 ilk_compute_wm_reg_maximums(dev
, 1, &max
);
2375 for (level
= 1; level
<= max_level
; level
++) {
2376 struct intel_wm_level wm
= {};
2378 ilk_compute_wm_level(dev_priv
, level
, params
, &wm
);
2381 * Disable any watermark level that exceeds the
2382 * register maximums since such watermarks are
2385 if (!ilk_validate_wm_level(level
, &max
, &wm
))
2388 pipe_wm
->wm
[level
] = wm
;
2395 * Merge the watermarks from all active pipes for a specific level.
2397 static void ilk_merge_wm_level(struct drm_device
*dev
,
2399 struct intel_wm_level
*ret_wm
)
2401 const struct intel_crtc
*intel_crtc
;
2403 ret_wm
->enable
= true;
2405 for_each_intel_crtc(dev
, intel_crtc
) {
2406 const struct intel_pipe_wm
*active
= &intel_crtc
->wm
.active
;
2407 const struct intel_wm_level
*wm
= &active
->wm
[level
];
2409 if (!active
->pipe_enabled
)
2413 * The watermark values may have been used in the past,
2414 * so we must maintain them in the registers for some
2415 * time even if the level is now disabled.
2418 ret_wm
->enable
= false;
2420 ret_wm
->pri_val
= max(ret_wm
->pri_val
, wm
->pri_val
);
2421 ret_wm
->spr_val
= max(ret_wm
->spr_val
, wm
->spr_val
);
2422 ret_wm
->cur_val
= max(ret_wm
->cur_val
, wm
->cur_val
);
2423 ret_wm
->fbc_val
= max(ret_wm
->fbc_val
, wm
->fbc_val
);
2428 * Merge all low power watermarks for all active pipes.
2430 static void ilk_wm_merge(struct drm_device
*dev
,
2431 const struct intel_wm_config
*config
,
2432 const struct ilk_wm_maximums
*max
,
2433 struct intel_pipe_wm
*merged
)
2435 int level
, max_level
= ilk_wm_max_level(dev
);
2436 int last_enabled_level
= max_level
;
2438 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2439 if ((INTEL_INFO(dev
)->gen
<= 6 || IS_IVYBRIDGE(dev
)) &&
2440 config
->num_pipes_active
> 1)
2443 /* ILK: FBC WM must be disabled always */
2444 merged
->fbc_wm_enabled
= INTEL_INFO(dev
)->gen
>= 6;
2446 /* merge each WM1+ level */
2447 for (level
= 1; level
<= max_level
; level
++) {
2448 struct intel_wm_level
*wm
= &merged
->wm
[level
];
2450 ilk_merge_wm_level(dev
, level
, wm
);
2452 if (level
> last_enabled_level
)
2454 else if (!ilk_validate_wm_level(level
, max
, wm
))
2455 /* make sure all following levels get disabled */
2456 last_enabled_level
= level
- 1;
2459 * The spec says it is preferred to disable
2460 * FBC WMs instead of disabling a WM level.
2462 if (wm
->fbc_val
> max
->fbc
) {
2464 merged
->fbc_wm_enabled
= false;
2469 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2471 * FIXME this is racy. FBC might get enabled later.
2472 * What we should check here is whether FBC can be
2473 * enabled sometime later.
2475 if (IS_GEN5(dev
) && !merged
->fbc_wm_enabled
&& intel_fbc_enabled(dev
)) {
2476 for (level
= 2; level
<= max_level
; level
++) {
2477 struct intel_wm_level
*wm
= &merged
->wm
[level
];
2484 static int ilk_wm_lp_to_level(int wm_lp
, const struct intel_pipe_wm
*pipe_wm
)
2486 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2487 return wm_lp
+ (wm_lp
>= 2 && pipe_wm
->wm
[4].enable
);
2490 /* The value we need to program into the WM_LPx latency field */
2491 static unsigned int ilk_wm_lp_latency(struct drm_device
*dev
, int level
)
2493 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2495 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2498 return dev_priv
->wm
.pri_latency
[level
];
2501 static void ilk_compute_wm_results(struct drm_device
*dev
,
2502 const struct intel_pipe_wm
*merged
,
2503 enum intel_ddb_partitioning partitioning
,
2504 struct ilk_wm_values
*results
)
2506 struct intel_crtc
*intel_crtc
;
2509 results
->enable_fbc_wm
= merged
->fbc_wm_enabled
;
2510 results
->partitioning
= partitioning
;
2512 /* LP1+ register values */
2513 for (wm_lp
= 1; wm_lp
<= 3; wm_lp
++) {
2514 const struct intel_wm_level
*r
;
2516 level
= ilk_wm_lp_to_level(wm_lp
, merged
);
2518 r
= &merged
->wm
[level
];
2521 * Maintain the watermark values even if the level is
2522 * disabled. Doing otherwise could cause underruns.
2524 results
->wm_lp
[wm_lp
- 1] =
2525 (ilk_wm_lp_latency(dev
, level
) << WM1_LP_LATENCY_SHIFT
) |
2526 (r
->pri_val
<< WM1_LP_SR_SHIFT
) |
2530 results
->wm_lp
[wm_lp
- 1] |= WM1_LP_SR_EN
;
2532 if (INTEL_INFO(dev
)->gen
>= 8)
2533 results
->wm_lp
[wm_lp
- 1] |=
2534 r
->fbc_val
<< WM1_LP_FBC_SHIFT_BDW
;
2536 results
->wm_lp
[wm_lp
- 1] |=
2537 r
->fbc_val
<< WM1_LP_FBC_SHIFT
;
2540 * Always set WM1S_LP_EN when spr_val != 0, even if the
2541 * level is disabled. Doing otherwise could cause underruns.
2543 if (INTEL_INFO(dev
)->gen
<= 6 && r
->spr_val
) {
2544 WARN_ON(wm_lp
!= 1);
2545 results
->wm_lp_spr
[wm_lp
- 1] = WM1S_LP_EN
| r
->spr_val
;
2547 results
->wm_lp_spr
[wm_lp
- 1] = r
->spr_val
;
2550 /* LP0 register values */
2551 for_each_intel_crtc(dev
, intel_crtc
) {
2552 enum pipe pipe
= intel_crtc
->pipe
;
2553 const struct intel_wm_level
*r
=
2554 &intel_crtc
->wm
.active
.wm
[0];
2556 if (WARN_ON(!r
->enable
))
2559 results
->wm_linetime
[pipe
] = intel_crtc
->wm
.active
.linetime
;
2561 results
->wm_pipe
[pipe
] =
2562 (r
->pri_val
<< WM0_PIPE_PLANE_SHIFT
) |
2563 (r
->spr_val
<< WM0_PIPE_SPRITE_SHIFT
) |
2568 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2569 * case both are at the same level. Prefer r1 in case they're the same. */
2570 static struct intel_pipe_wm
*ilk_find_best_result(struct drm_device
*dev
,
2571 struct intel_pipe_wm
*r1
,
2572 struct intel_pipe_wm
*r2
)
2574 int level
, max_level
= ilk_wm_max_level(dev
);
2575 int level1
= 0, level2
= 0;
2577 for (level
= 1; level
<= max_level
; level
++) {
2578 if (r1
->wm
[level
].enable
)
2580 if (r2
->wm
[level
].enable
)
2584 if (level1
== level2
) {
2585 if (r2
->fbc_wm_enabled
&& !r1
->fbc_wm_enabled
)
2589 } else if (level1
> level2
) {
2596 /* dirty bits used to track which watermarks need changes */
2597 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2598 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2599 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2600 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2601 #define WM_DIRTY_FBC (1 << 24)
2602 #define WM_DIRTY_DDB (1 << 25)
2604 static unsigned int ilk_compute_wm_dirty(struct drm_device
*dev
,
2605 const struct ilk_wm_values
*old
,
2606 const struct ilk_wm_values
*new)
2608 unsigned int dirty
= 0;
2612 for_each_pipe(pipe
) {
2613 if (old
->wm_linetime
[pipe
] != new->wm_linetime
[pipe
]) {
2614 dirty
|= WM_DIRTY_LINETIME(pipe
);
2615 /* Must disable LP1+ watermarks too */
2616 dirty
|= WM_DIRTY_LP_ALL
;
2619 if (old
->wm_pipe
[pipe
] != new->wm_pipe
[pipe
]) {
2620 dirty
|= WM_DIRTY_PIPE(pipe
);
2621 /* Must disable LP1+ watermarks too */
2622 dirty
|= WM_DIRTY_LP_ALL
;
2626 if (old
->enable_fbc_wm
!= new->enable_fbc_wm
) {
2627 dirty
|= WM_DIRTY_FBC
;
2628 /* Must disable LP1+ watermarks too */
2629 dirty
|= WM_DIRTY_LP_ALL
;
2632 if (old
->partitioning
!= new->partitioning
) {
2633 dirty
|= WM_DIRTY_DDB
;
2634 /* Must disable LP1+ watermarks too */
2635 dirty
|= WM_DIRTY_LP_ALL
;
2638 /* LP1+ watermarks already deemed dirty, no need to continue */
2639 if (dirty
& WM_DIRTY_LP_ALL
)
2642 /* Find the lowest numbered LP1+ watermark in need of an update... */
2643 for (wm_lp
= 1; wm_lp
<= 3; wm_lp
++) {
2644 if (old
->wm_lp
[wm_lp
- 1] != new->wm_lp
[wm_lp
- 1] ||
2645 old
->wm_lp_spr
[wm_lp
- 1] != new->wm_lp_spr
[wm_lp
- 1])
2649 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2650 for (; wm_lp
<= 3; wm_lp
++)
2651 dirty
|= WM_DIRTY_LP(wm_lp
);
2656 static bool _ilk_disable_lp_wm(struct drm_i915_private
*dev_priv
,
2659 struct ilk_wm_values
*previous
= &dev_priv
->wm
.hw
;
2660 bool changed
= false;
2662 if (dirty
& WM_DIRTY_LP(3) && previous
->wm_lp
[2] & WM1_LP_SR_EN
) {
2663 previous
->wm_lp
[2] &= ~WM1_LP_SR_EN
;
2664 I915_WRITE(WM3_LP_ILK
, previous
->wm_lp
[2]);
2667 if (dirty
& WM_DIRTY_LP(2) && previous
->wm_lp
[1] & WM1_LP_SR_EN
) {
2668 previous
->wm_lp
[1] &= ~WM1_LP_SR_EN
;
2669 I915_WRITE(WM2_LP_ILK
, previous
->wm_lp
[1]);
2672 if (dirty
& WM_DIRTY_LP(1) && previous
->wm_lp
[0] & WM1_LP_SR_EN
) {
2673 previous
->wm_lp
[0] &= ~WM1_LP_SR_EN
;
2674 I915_WRITE(WM1_LP_ILK
, previous
->wm_lp
[0]);
2679 * Don't touch WM1S_LP_EN here.
2680 * Doing so could cause underruns.
2687 * The spec says we shouldn't write when we don't need, because every write
2688 * causes WMs to be re-evaluated, expending some power.
2690 static void ilk_write_wm_values(struct drm_i915_private
*dev_priv
,
2691 struct ilk_wm_values
*results
)
2693 struct drm_device
*dev
= dev_priv
->dev
;
2694 struct ilk_wm_values
*previous
= &dev_priv
->wm
.hw
;
2698 dirty
= ilk_compute_wm_dirty(dev
, previous
, results
);
2702 _ilk_disable_lp_wm(dev_priv
, dirty
);
2704 if (dirty
& WM_DIRTY_PIPE(PIPE_A
))
2705 I915_WRITE(WM0_PIPEA_ILK
, results
->wm_pipe
[0]);
2706 if (dirty
& WM_DIRTY_PIPE(PIPE_B
))
2707 I915_WRITE(WM0_PIPEB_ILK
, results
->wm_pipe
[1]);
2708 if (dirty
& WM_DIRTY_PIPE(PIPE_C
))
2709 I915_WRITE(WM0_PIPEC_IVB
, results
->wm_pipe
[2]);
2711 if (dirty
& WM_DIRTY_LINETIME(PIPE_A
))
2712 I915_WRITE(PIPE_WM_LINETIME(PIPE_A
), results
->wm_linetime
[0]);
2713 if (dirty
& WM_DIRTY_LINETIME(PIPE_B
))
2714 I915_WRITE(PIPE_WM_LINETIME(PIPE_B
), results
->wm_linetime
[1]);
2715 if (dirty
& WM_DIRTY_LINETIME(PIPE_C
))
2716 I915_WRITE(PIPE_WM_LINETIME(PIPE_C
), results
->wm_linetime
[2]);
2718 if (dirty
& WM_DIRTY_DDB
) {
2719 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2720 val
= I915_READ(WM_MISC
);
2721 if (results
->partitioning
== INTEL_DDB_PART_1_2
)
2722 val
&= ~WM_MISC_DATA_PARTITION_5_6
;
2724 val
|= WM_MISC_DATA_PARTITION_5_6
;
2725 I915_WRITE(WM_MISC
, val
);
2727 val
= I915_READ(DISP_ARB_CTL2
);
2728 if (results
->partitioning
== INTEL_DDB_PART_1_2
)
2729 val
&= ~DISP_DATA_PARTITION_5_6
;
2731 val
|= DISP_DATA_PARTITION_5_6
;
2732 I915_WRITE(DISP_ARB_CTL2
, val
);
2736 if (dirty
& WM_DIRTY_FBC
) {
2737 val
= I915_READ(DISP_ARB_CTL
);
2738 if (results
->enable_fbc_wm
)
2739 val
&= ~DISP_FBC_WM_DIS
;
2741 val
|= DISP_FBC_WM_DIS
;
2742 I915_WRITE(DISP_ARB_CTL
, val
);
2745 if (dirty
& WM_DIRTY_LP(1) &&
2746 previous
->wm_lp_spr
[0] != results
->wm_lp_spr
[0])
2747 I915_WRITE(WM1S_LP_ILK
, results
->wm_lp_spr
[0]);
2749 if (INTEL_INFO(dev
)->gen
>= 7) {
2750 if (dirty
& WM_DIRTY_LP(2) && previous
->wm_lp_spr
[1] != results
->wm_lp_spr
[1])
2751 I915_WRITE(WM2S_LP_IVB
, results
->wm_lp_spr
[1]);
2752 if (dirty
& WM_DIRTY_LP(3) && previous
->wm_lp_spr
[2] != results
->wm_lp_spr
[2])
2753 I915_WRITE(WM3S_LP_IVB
, results
->wm_lp_spr
[2]);
2756 if (dirty
& WM_DIRTY_LP(1) && previous
->wm_lp
[0] != results
->wm_lp
[0])
2757 I915_WRITE(WM1_LP_ILK
, results
->wm_lp
[0]);
2758 if (dirty
& WM_DIRTY_LP(2) && previous
->wm_lp
[1] != results
->wm_lp
[1])
2759 I915_WRITE(WM2_LP_ILK
, results
->wm_lp
[1]);
2760 if (dirty
& WM_DIRTY_LP(3) && previous
->wm_lp
[2] != results
->wm_lp
[2])
2761 I915_WRITE(WM3_LP_ILK
, results
->wm_lp
[2]);
2763 dev_priv
->wm
.hw
= *results
;
2766 static bool ilk_disable_lp_wm(struct drm_device
*dev
)
2768 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2770 return _ilk_disable_lp_wm(dev_priv
, WM_DIRTY_LP_ALL
);
2773 static void ilk_update_wm(struct drm_crtc
*crtc
)
2775 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2776 struct drm_device
*dev
= crtc
->dev
;
2777 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2778 struct ilk_wm_maximums max
;
2779 struct ilk_pipe_wm_parameters params
= {};
2780 struct ilk_wm_values results
= {};
2781 enum intel_ddb_partitioning partitioning
;
2782 struct intel_pipe_wm pipe_wm
= {};
2783 struct intel_pipe_wm lp_wm_1_2
= {}, lp_wm_5_6
= {}, *best_lp_wm
;
2784 struct intel_wm_config config
= {};
2786 ilk_compute_wm_parameters(crtc
, ¶ms
);
2788 intel_compute_pipe_wm(crtc
, ¶ms
, &pipe_wm
);
2790 if (!memcmp(&intel_crtc
->wm
.active
, &pipe_wm
, sizeof(pipe_wm
)))
2793 intel_crtc
->wm
.active
= pipe_wm
;
2795 ilk_compute_wm_config(dev
, &config
);
2797 ilk_compute_wm_maximums(dev
, 1, &config
, INTEL_DDB_PART_1_2
, &max
);
2798 ilk_wm_merge(dev
, &config
, &max
, &lp_wm_1_2
);
2800 /* 5/6 split only in single pipe config on IVB+ */
2801 if (INTEL_INFO(dev
)->gen
>= 7 &&
2802 config
.num_pipes_active
== 1 && config
.sprites_enabled
) {
2803 ilk_compute_wm_maximums(dev
, 1, &config
, INTEL_DDB_PART_5_6
, &max
);
2804 ilk_wm_merge(dev
, &config
, &max
, &lp_wm_5_6
);
2806 best_lp_wm
= ilk_find_best_result(dev
, &lp_wm_1_2
, &lp_wm_5_6
);
2808 best_lp_wm
= &lp_wm_1_2
;
2811 partitioning
= (best_lp_wm
== &lp_wm_1_2
) ?
2812 INTEL_DDB_PART_1_2
: INTEL_DDB_PART_5_6
;
2814 ilk_compute_wm_results(dev
, best_lp_wm
, partitioning
, &results
);
2816 ilk_write_wm_values(dev_priv
, &results
);
2820 ilk_update_sprite_wm(struct drm_plane
*plane
,
2821 struct drm_crtc
*crtc
,
2822 uint32_t sprite_width
, uint32_t sprite_height
,
2823 int pixel_size
, bool enabled
, bool scaled
)
2825 struct drm_device
*dev
= plane
->dev
;
2826 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
2828 intel_plane
->wm
.enabled
= enabled
;
2829 intel_plane
->wm
.scaled
= scaled
;
2830 intel_plane
->wm
.horiz_pixels
= sprite_width
;
2831 intel_plane
->wm
.vert_pixels
= sprite_width
;
2832 intel_plane
->wm
.bytes_per_pixel
= pixel_size
;
2835 * IVB workaround: must disable low power watermarks for at least
2836 * one frame before enabling scaling. LP watermarks can be re-enabled
2837 * when scaling is disabled.
2839 * WaCxSRDisabledForSpriteScaling:ivb
2841 if (IS_IVYBRIDGE(dev
) && scaled
&& ilk_disable_lp_wm(dev
))
2842 intel_wait_for_vblank(dev
, intel_plane
->pipe
);
2844 ilk_update_wm(crtc
);
2847 static void ilk_pipe_wm_get_hw_state(struct drm_crtc
*crtc
)
2849 struct drm_device
*dev
= crtc
->dev
;
2850 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2851 struct ilk_wm_values
*hw
= &dev_priv
->wm
.hw
;
2852 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2853 struct intel_pipe_wm
*active
= &intel_crtc
->wm
.active
;
2854 enum pipe pipe
= intel_crtc
->pipe
;
2855 static const unsigned int wm0_pipe_reg
[] = {
2856 [PIPE_A
] = WM0_PIPEA_ILK
,
2857 [PIPE_B
] = WM0_PIPEB_ILK
,
2858 [PIPE_C
] = WM0_PIPEC_IVB
,
2861 hw
->wm_pipe
[pipe
] = I915_READ(wm0_pipe_reg
[pipe
]);
2862 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2863 hw
->wm_linetime
[pipe
] = I915_READ(PIPE_WM_LINETIME(pipe
));
2865 active
->pipe_enabled
= intel_crtc_active(crtc
);
2867 if (active
->pipe_enabled
) {
2868 u32 tmp
= hw
->wm_pipe
[pipe
];
2871 * For active pipes LP0 watermark is marked as
2872 * enabled, and LP1+ watermaks as disabled since
2873 * we can't really reverse compute them in case
2874 * multiple pipes are active.
2876 active
->wm
[0].enable
= true;
2877 active
->wm
[0].pri_val
= (tmp
& WM0_PIPE_PLANE_MASK
) >> WM0_PIPE_PLANE_SHIFT
;
2878 active
->wm
[0].spr_val
= (tmp
& WM0_PIPE_SPRITE_MASK
) >> WM0_PIPE_SPRITE_SHIFT
;
2879 active
->wm
[0].cur_val
= tmp
& WM0_PIPE_CURSOR_MASK
;
2880 active
->linetime
= hw
->wm_linetime
[pipe
];
2882 int level
, max_level
= ilk_wm_max_level(dev
);
2885 * For inactive pipes, all watermark levels
2886 * should be marked as enabled but zeroed,
2887 * which is what we'd compute them to.
2889 for (level
= 0; level
<= max_level
; level
++)
2890 active
->wm
[level
].enable
= true;
2894 void ilk_wm_get_hw_state(struct drm_device
*dev
)
2896 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2897 struct ilk_wm_values
*hw
= &dev_priv
->wm
.hw
;
2898 struct drm_crtc
*crtc
;
2900 for_each_crtc(dev
, crtc
)
2901 ilk_pipe_wm_get_hw_state(crtc
);
2903 hw
->wm_lp
[0] = I915_READ(WM1_LP_ILK
);
2904 hw
->wm_lp
[1] = I915_READ(WM2_LP_ILK
);
2905 hw
->wm_lp
[2] = I915_READ(WM3_LP_ILK
);
2907 hw
->wm_lp_spr
[0] = I915_READ(WM1S_LP_ILK
);
2908 if (INTEL_INFO(dev
)->gen
>= 7) {
2909 hw
->wm_lp_spr
[1] = I915_READ(WM2S_LP_IVB
);
2910 hw
->wm_lp_spr
[2] = I915_READ(WM3S_LP_IVB
);
2913 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2914 hw
->partitioning
= (I915_READ(WM_MISC
) & WM_MISC_DATA_PARTITION_5_6
) ?
2915 INTEL_DDB_PART_5_6
: INTEL_DDB_PART_1_2
;
2916 else if (IS_IVYBRIDGE(dev
))
2917 hw
->partitioning
= (I915_READ(DISP_ARB_CTL2
) & DISP_DATA_PARTITION_5_6
) ?
2918 INTEL_DDB_PART_5_6
: INTEL_DDB_PART_1_2
;
2921 !(I915_READ(DISP_ARB_CTL
) & DISP_FBC_WM_DIS
);
2925 * intel_update_watermarks - update FIFO watermark values based on current modes
2927 * Calculate watermark values for the various WM regs based on current mode
2928 * and plane configuration.
2930 * There are several cases to deal with here:
2931 * - normal (i.e. non-self-refresh)
2932 * - self-refresh (SR) mode
2933 * - lines are large relative to FIFO size (buffer can hold up to 2)
2934 * - lines are small relative to FIFO size (buffer can hold more than 2
2935 * lines), so need to account for TLB latency
2937 * The normal calculation is:
2938 * watermark = dotclock * bytes per pixel * latency
2939 * where latency is platform & configuration dependent (we assume pessimal
2942 * The SR calculation is:
2943 * watermark = (trunc(latency/line time)+1) * surface width *
2946 * line time = htotal / dotclock
2947 * surface width = hdisplay for normal plane and 64 for cursor
2948 * and latency is assumed to be high, as above.
2950 * The final value programmed to the register should always be rounded up,
2951 * and include an extra 2 entries to account for clock crossings.
2953 * We don't use the sprite, so we can ignore that. And on Crestline we have
2954 * to set the non-SR watermarks to 8.
2956 void intel_update_watermarks(struct drm_crtc
*crtc
)
2958 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
2960 if (dev_priv
->display
.update_wm
)
2961 dev_priv
->display
.update_wm(crtc
);
2964 void intel_update_sprite_watermarks(struct drm_plane
*plane
,
2965 struct drm_crtc
*crtc
,
2966 uint32_t sprite_width
,
2967 uint32_t sprite_height
,
2969 bool enabled
, bool scaled
)
2971 struct drm_i915_private
*dev_priv
= plane
->dev
->dev_private
;
2973 if (dev_priv
->display
.update_sprite_wm
)
2974 dev_priv
->display
.update_sprite_wm(plane
, crtc
,
2975 sprite_width
, sprite_height
,
2976 pixel_size
, enabled
, scaled
);
2979 static struct drm_i915_gem_object
*
2980 intel_alloc_context_page(struct drm_device
*dev
)
2982 struct drm_i915_gem_object
*ctx
;
2985 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
2987 ctx
= i915_gem_alloc_object(dev
, 4096);
2989 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
2993 ret
= i915_gem_obj_ggtt_pin(ctx
, 4096, 0);
2995 DRM_ERROR("failed to pin power context: %d\n", ret
);
2999 ret
= i915_gem_object_set_to_gtt_domain(ctx
, 1);
3001 DRM_ERROR("failed to set-domain on power context: %d\n", ret
);
3008 i915_gem_object_ggtt_unpin(ctx
);
3010 drm_gem_object_unreference(&ctx
->base
);
3015 * Lock protecting IPS related data structures
3017 DEFINE_SPINLOCK(mchdev_lock
);
3019 /* Global for IPS driver to get at the current i915 device. Protected by
3021 static struct drm_i915_private
*i915_mch_dev
;
3023 bool ironlake_set_drps(struct drm_device
*dev
, u8 val
)
3025 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3028 assert_spin_locked(&mchdev_lock
);
3030 rgvswctl
= I915_READ16(MEMSWCTL
);
3031 if (rgvswctl
& MEMCTL_CMD_STS
) {
3032 DRM_DEBUG("gpu busy, RCS change rejected\n");
3033 return false; /* still busy with another command */
3036 rgvswctl
= (MEMCTL_CMD_CHFREQ
<< MEMCTL_CMD_SHIFT
) |
3037 (val
<< MEMCTL_FREQ_SHIFT
) | MEMCTL_SFCAVM
;
3038 I915_WRITE16(MEMSWCTL
, rgvswctl
);
3039 POSTING_READ16(MEMSWCTL
);
3041 rgvswctl
|= MEMCTL_CMD_STS
;
3042 I915_WRITE16(MEMSWCTL
, rgvswctl
);
3047 static void ironlake_enable_drps(struct drm_device
*dev
)
3049 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3050 u32 rgvmodectl
= I915_READ(MEMMODECTL
);
3051 u8 fmax
, fmin
, fstart
, vstart
;
3053 spin_lock_irq(&mchdev_lock
);
3055 /* Enable temp reporting */
3056 I915_WRITE16(PMMISC
, I915_READ(PMMISC
) | MCPPCE_EN
);
3057 I915_WRITE16(TSC1
, I915_READ(TSC1
) | TSE
);
3059 /* 100ms RC evaluation intervals */
3060 I915_WRITE(RCUPEI
, 100000);
3061 I915_WRITE(RCDNEI
, 100000);
3063 /* Set max/min thresholds to 90ms and 80ms respectively */
3064 I915_WRITE(RCBMAXAVG
, 90000);
3065 I915_WRITE(RCBMINAVG
, 80000);
3067 I915_WRITE(MEMIHYST
, 1);
3069 /* Set up min, max, and cur for interrupt handling */
3070 fmax
= (rgvmodectl
& MEMMODE_FMAX_MASK
) >> MEMMODE_FMAX_SHIFT
;
3071 fmin
= (rgvmodectl
& MEMMODE_FMIN_MASK
);
3072 fstart
= (rgvmodectl
& MEMMODE_FSTART_MASK
) >>
3073 MEMMODE_FSTART_SHIFT
;
3075 vstart
= (I915_READ(PXVFREQ_BASE
+ (fstart
* 4)) & PXVFREQ_PX_MASK
) >>
3078 dev_priv
->ips
.fmax
= fmax
; /* IPS callback will increase this */
3079 dev_priv
->ips
.fstart
= fstart
;
3081 dev_priv
->ips
.max_delay
= fstart
;
3082 dev_priv
->ips
.min_delay
= fmin
;
3083 dev_priv
->ips
.cur_delay
= fstart
;
3085 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
3086 fmax
, fmin
, fstart
);
3088 I915_WRITE(MEMINTREN
, MEMINT_CX_SUPR_EN
| MEMINT_EVAL_CHG_EN
);
3091 * Interrupts will be enabled in ironlake_irq_postinstall
3094 I915_WRITE(VIDSTART
, vstart
);
3095 POSTING_READ(VIDSTART
);
3097 rgvmodectl
|= MEMMODE_SWMODE_EN
;
3098 I915_WRITE(MEMMODECTL
, rgvmodectl
);
3100 if (wait_for_atomic((I915_READ(MEMSWCTL
) & MEMCTL_CMD_STS
) == 0, 10))
3101 DRM_ERROR("stuck trying to change perf mode\n");
3104 ironlake_set_drps(dev
, fstart
);
3106 dev_priv
->ips
.last_count1
= I915_READ(0x112e4) + I915_READ(0x112e8) +
3108 dev_priv
->ips
.last_time1
= jiffies_to_msecs(jiffies
);
3109 dev_priv
->ips
.last_count2
= I915_READ(0x112f4);
3110 getrawmonotonic(&dev_priv
->ips
.last_time2
);
3112 spin_unlock_irq(&mchdev_lock
);
3115 static void ironlake_disable_drps(struct drm_device
*dev
)
3117 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3120 spin_lock_irq(&mchdev_lock
);
3122 rgvswctl
= I915_READ16(MEMSWCTL
);
3124 /* Ack interrupts, disable EFC interrupt */
3125 I915_WRITE(MEMINTREN
, I915_READ(MEMINTREN
) & ~MEMINT_EVAL_CHG_EN
);
3126 I915_WRITE(MEMINTRSTS
, MEMINT_EVAL_CHG
);
3127 I915_WRITE(DEIER
, I915_READ(DEIER
) & ~DE_PCU_EVENT
);
3128 I915_WRITE(DEIIR
, DE_PCU_EVENT
);
3129 I915_WRITE(DEIMR
, I915_READ(DEIMR
) | DE_PCU_EVENT
);
3131 /* Go back to the starting frequency */
3132 ironlake_set_drps(dev
, dev_priv
->ips
.fstart
);
3134 rgvswctl
|= MEMCTL_CMD_STS
;
3135 I915_WRITE(MEMSWCTL
, rgvswctl
);
3138 spin_unlock_irq(&mchdev_lock
);
3141 /* There's a funny hw issue where the hw returns all 0 when reading from
3142 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3143 * ourselves, instead of doing a rmw cycle (which might result in us clearing
3144 * all limits and the gpu stuck at whatever frequency it is at atm).
3146 static u32
gen6_rps_limits(struct drm_i915_private
*dev_priv
, u8 val
)
3150 /* Only set the down limit when we've reached the lowest level to avoid
3151 * getting more interrupts, otherwise leave this clear. This prevents a
3152 * race in the hw when coming out of rc6: There's a tiny window where
3153 * the hw runs at the minimal clock before selecting the desired
3154 * frequency, if the down threshold expires in that window we will not
3155 * receive a down interrupt. */
3156 limits
= dev_priv
->rps
.max_freq_softlimit
<< 24;
3157 if (val
<= dev_priv
->rps
.min_freq_softlimit
)
3158 limits
|= dev_priv
->rps
.min_freq_softlimit
<< 16;
3163 static void gen6_set_rps_thresholds(struct drm_i915_private
*dev_priv
, u8 val
)
3167 new_power
= dev_priv
->rps
.power
;
3168 switch (dev_priv
->rps
.power
) {
3170 if (val
> dev_priv
->rps
.efficient_freq
+ 1 && val
> dev_priv
->rps
.cur_freq
)
3171 new_power
= BETWEEN
;
3175 if (val
<= dev_priv
->rps
.efficient_freq
&& val
< dev_priv
->rps
.cur_freq
)
3176 new_power
= LOW_POWER
;
3177 else if (val
>= dev_priv
->rps
.rp0_freq
&& val
> dev_priv
->rps
.cur_freq
)
3178 new_power
= HIGH_POWER
;
3182 if (val
< (dev_priv
->rps
.rp1_freq
+ dev_priv
->rps
.rp0_freq
) >> 1 && val
< dev_priv
->rps
.cur_freq
)
3183 new_power
= BETWEEN
;
3186 /* Max/min bins are special */
3187 if (val
== dev_priv
->rps
.min_freq_softlimit
)
3188 new_power
= LOW_POWER
;
3189 if (val
== dev_priv
->rps
.max_freq_softlimit
)
3190 new_power
= HIGH_POWER
;
3191 if (new_power
== dev_priv
->rps
.power
)
3194 /* Note the units here are not exactly 1us, but 1280ns. */
3195 switch (new_power
) {
3197 /* Upclock if more than 95% busy over 16ms */
3198 I915_WRITE(GEN6_RP_UP_EI
, 12500);
3199 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 11800);
3201 /* Downclock if less than 85% busy over 32ms */
3202 I915_WRITE(GEN6_RP_DOWN_EI
, 25000);
3203 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 21250);
3205 I915_WRITE(GEN6_RP_CONTROL
,
3206 GEN6_RP_MEDIA_TURBO
|
3207 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
3208 GEN6_RP_MEDIA_IS_GFX
|
3210 GEN6_RP_UP_BUSY_AVG
|
3211 GEN6_RP_DOWN_IDLE_AVG
);
3215 /* Upclock if more than 90% busy over 13ms */
3216 I915_WRITE(GEN6_RP_UP_EI
, 10250);
3217 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 9225);
3219 /* Downclock if less than 75% busy over 32ms */
3220 I915_WRITE(GEN6_RP_DOWN_EI
, 25000);
3221 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 18750);
3223 I915_WRITE(GEN6_RP_CONTROL
,
3224 GEN6_RP_MEDIA_TURBO
|
3225 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
3226 GEN6_RP_MEDIA_IS_GFX
|
3228 GEN6_RP_UP_BUSY_AVG
|
3229 GEN6_RP_DOWN_IDLE_AVG
);
3233 /* Upclock if more than 85% busy over 10ms */
3234 I915_WRITE(GEN6_RP_UP_EI
, 8000);
3235 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 6800);
3237 /* Downclock if less than 60% busy over 32ms */
3238 I915_WRITE(GEN6_RP_DOWN_EI
, 25000);
3239 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 15000);
3241 I915_WRITE(GEN6_RP_CONTROL
,
3242 GEN6_RP_MEDIA_TURBO
|
3243 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
3244 GEN6_RP_MEDIA_IS_GFX
|
3246 GEN6_RP_UP_BUSY_AVG
|
3247 GEN6_RP_DOWN_IDLE_AVG
);
3251 dev_priv
->rps
.power
= new_power
;
3252 dev_priv
->rps
.last_adj
= 0;
3255 static u32
gen6_rps_pm_mask(struct drm_i915_private
*dev_priv
, u8 val
)
3259 if (val
> dev_priv
->rps
.min_freq_softlimit
)
3260 mask
|= GEN6_PM_RP_DOWN_THRESHOLD
| GEN6_PM_RP_DOWN_TIMEOUT
;
3261 if (val
< dev_priv
->rps
.max_freq_softlimit
)
3262 mask
|= GEN6_PM_RP_UP_THRESHOLD
;
3264 mask
|= dev_priv
->pm_rps_events
& (GEN6_PM_RP_DOWN_EI_EXPIRED
| GEN6_PM_RP_UP_EI_EXPIRED
);
3265 mask
&= dev_priv
->pm_rps_events
;
3267 /* IVB and SNB hard hangs on looping batchbuffer
3268 * if GEN6_PM_UP_EI_EXPIRED is masked.
3270 if (INTEL_INFO(dev_priv
->dev
)->gen
<= 7 && !IS_HASWELL(dev_priv
->dev
))
3271 mask
|= GEN6_PM_RP_UP_EI_EXPIRED
;
3273 if (IS_GEN8(dev_priv
->dev
))
3274 mask
|= GEN8_PMINTR_REDIRECT_TO_NON_DISP
;
3279 /* gen6_set_rps is called to update the frequency request, but should also be
3280 * called when the range (min_delay and max_delay) is modified so that we can
3281 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
3282 void gen6_set_rps(struct drm_device
*dev
, u8 val
)
3284 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3286 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
3287 WARN_ON(val
> dev_priv
->rps
.max_freq_softlimit
);
3288 WARN_ON(val
< dev_priv
->rps
.min_freq_softlimit
);
3290 /* min/max delay may still have been modified so be sure to
3291 * write the limits value.
3293 if (val
!= dev_priv
->rps
.cur_freq
) {
3294 gen6_set_rps_thresholds(dev_priv
, val
);
3296 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
3297 I915_WRITE(GEN6_RPNSWREQ
,
3298 HSW_FREQUENCY(val
));
3300 I915_WRITE(GEN6_RPNSWREQ
,
3301 GEN6_FREQUENCY(val
) |
3303 GEN6_AGGRESSIVE_TURBO
);
3306 /* Make sure we continue to get interrupts
3307 * until we hit the minimum or maximum frequencies.
3309 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS
, gen6_rps_limits(dev_priv
, val
));
3310 I915_WRITE(GEN6_PMINTRMSK
, gen6_rps_pm_mask(dev_priv
, val
));
3312 POSTING_READ(GEN6_RPNSWREQ
);
3314 dev_priv
->rps
.cur_freq
= val
;
3315 trace_intel_gpu_freq_change(val
* 50);
3318 /* vlv_set_rps_idle: Set the frequency to Rpn if Gfx clocks are down
3320 * * If Gfx is Idle, then
3321 * 1. Mask Turbo interrupts
3322 * 2. Bring up Gfx clock
3323 * 3. Change the freq to Rpn and wait till P-Unit updates freq
3324 * 4. Clear the Force GFX CLK ON bit so that Gfx can down
3325 * 5. Unmask Turbo interrupts
3327 static void vlv_set_rps_idle(struct drm_i915_private
*dev_priv
)
3329 struct drm_device
*dev
= dev_priv
->dev
;
3331 /* Latest VLV doesn't need to force the gfx clock */
3332 if (dev
->pdev
->revision
>= 0xd) {
3333 valleyview_set_rps(dev_priv
->dev
, dev_priv
->rps
.min_freq_softlimit
);
3338 * When we are idle. Drop to min voltage state.
3341 if (dev_priv
->rps
.cur_freq
<= dev_priv
->rps
.min_freq_softlimit
)
3344 /* Mask turbo interrupt so that they will not come in between */
3345 I915_WRITE(GEN6_PMINTRMSK
, 0xffffffff);
3347 vlv_force_gfx_clock(dev_priv
, true);
3349 dev_priv
->rps
.cur_freq
= dev_priv
->rps
.min_freq_softlimit
;
3351 vlv_punit_write(dev_priv
, PUNIT_REG_GPU_FREQ_REQ
,
3352 dev_priv
->rps
.min_freq_softlimit
);
3354 if (wait_for(((vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
))
3355 & GENFREQSTATUS
) == 0, 5))
3356 DRM_ERROR("timed out waiting for Punit\n");
3358 vlv_force_gfx_clock(dev_priv
, false);
3360 I915_WRITE(GEN6_PMINTRMSK
,
3361 gen6_rps_pm_mask(dev_priv
, dev_priv
->rps
.cur_freq
));
3364 void gen6_rps_idle(struct drm_i915_private
*dev_priv
)
3366 struct drm_device
*dev
= dev_priv
->dev
;
3368 mutex_lock(&dev_priv
->rps
.hw_lock
);
3369 if (dev_priv
->rps
.enabled
) {
3370 if (IS_CHERRYVIEW(dev
))
3371 valleyview_set_rps(dev_priv
->dev
, dev_priv
->rps
.min_freq_softlimit
);
3372 else if (IS_VALLEYVIEW(dev
))
3373 vlv_set_rps_idle(dev_priv
);
3375 gen6_set_rps(dev_priv
->dev
, dev_priv
->rps
.min_freq_softlimit
);
3376 dev_priv
->rps
.last_adj
= 0;
3378 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3381 void gen6_rps_boost(struct drm_i915_private
*dev_priv
)
3383 struct drm_device
*dev
= dev_priv
->dev
;
3385 mutex_lock(&dev_priv
->rps
.hw_lock
);
3386 if (dev_priv
->rps
.enabled
) {
3387 if (IS_VALLEYVIEW(dev
))
3388 valleyview_set_rps(dev_priv
->dev
, dev_priv
->rps
.max_freq_softlimit
);
3390 gen6_set_rps(dev_priv
->dev
, dev_priv
->rps
.max_freq_softlimit
);
3391 dev_priv
->rps
.last_adj
= 0;
3393 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3396 void valleyview_set_rps(struct drm_device
*dev
, u8 val
)
3398 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3400 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
3401 WARN_ON(val
> dev_priv
->rps
.max_freq_softlimit
);
3402 WARN_ON(val
< dev_priv
->rps
.min_freq_softlimit
);
3404 DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
3405 vlv_gpu_freq(dev_priv
, dev_priv
->rps
.cur_freq
),
3406 dev_priv
->rps
.cur_freq
,
3407 vlv_gpu_freq(dev_priv
, val
), val
);
3409 if (val
!= dev_priv
->rps
.cur_freq
)
3410 vlv_punit_write(dev_priv
, PUNIT_REG_GPU_FREQ_REQ
, val
);
3412 I915_WRITE(GEN6_PMINTRMSK
, gen6_rps_pm_mask(dev_priv
, val
));
3414 dev_priv
->rps
.cur_freq
= val
;
3415 trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv
, val
));
3418 static void gen8_disable_rps_interrupts(struct drm_device
*dev
)
3420 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3422 I915_WRITE(GEN6_PMINTRMSK
, ~GEN8_PMINTR_REDIRECT_TO_NON_DISP
);
3423 I915_WRITE(GEN8_GT_IER(2), I915_READ(GEN8_GT_IER(2)) &
3424 ~dev_priv
->pm_rps_events
);
3425 /* Complete PM interrupt masking here doesn't race with the rps work
3426 * item again unmasking PM interrupts because that is using a different
3427 * register (GEN8_GT_IMR(2)) to mask PM interrupts. The only risk is in
3428 * leaving stale bits in GEN8_GT_IIR(2) and GEN8_GT_IMR(2) which
3429 * gen8_enable_rps will clean up. */
3431 spin_lock_irq(&dev_priv
->irq_lock
);
3432 dev_priv
->rps
.pm_iir
= 0;
3433 spin_unlock_irq(&dev_priv
->irq_lock
);
3435 I915_WRITE(GEN8_GT_IIR(2), dev_priv
->pm_rps_events
);
3438 static void gen6_disable_rps_interrupts(struct drm_device
*dev
)
3440 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3442 I915_WRITE(GEN6_PMINTRMSK
, 0xffffffff);
3443 I915_WRITE(GEN6_PMIER
, I915_READ(GEN6_PMIER
) &
3444 ~dev_priv
->pm_rps_events
);
3445 /* Complete PM interrupt masking here doesn't race with the rps work
3446 * item again unmasking PM interrupts because that is using a different
3447 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3448 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3450 spin_lock_irq(&dev_priv
->irq_lock
);
3451 dev_priv
->rps
.pm_iir
= 0;
3452 spin_unlock_irq(&dev_priv
->irq_lock
);
3454 I915_WRITE(GEN6_PMIIR
, dev_priv
->pm_rps_events
);
3457 static void gen6_disable_rps(struct drm_device
*dev
)
3459 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3461 I915_WRITE(GEN6_RC_CONTROL
, 0);
3462 I915_WRITE(GEN6_RPNSWREQ
, 1 << 31);
3464 if (IS_BROADWELL(dev
))
3465 gen8_disable_rps_interrupts(dev
);
3467 gen6_disable_rps_interrupts(dev
);
3470 static void cherryview_disable_rps(struct drm_device
*dev
)
3472 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3474 I915_WRITE(GEN6_RC_CONTROL
, 0);
3476 gen8_disable_rps_interrupts(dev
);
3479 static void valleyview_disable_rps(struct drm_device
*dev
)
3481 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3483 I915_WRITE(GEN6_RC_CONTROL
, 0);
3485 gen6_disable_rps_interrupts(dev
);
3488 static void intel_print_rc6_info(struct drm_device
*dev
, u32 mode
)
3490 if (IS_VALLEYVIEW(dev
)) {
3491 if (mode
& (GEN7_RC_CTL_TO_MODE
| GEN6_RC_CTL_EI_MODE(1)))
3492 mode
= GEN6_RC_CTL_RC6_ENABLE
;
3496 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
3497 (mode
& GEN6_RC_CTL_RC6_ENABLE
) ? "on" : "off",
3498 (mode
& GEN6_RC_CTL_RC6p_ENABLE
) ? "on" : "off",
3499 (mode
& GEN6_RC_CTL_RC6pp_ENABLE
) ? "on" : "off");
3502 static int sanitize_rc6_option(const struct drm_device
*dev
, int enable_rc6
)
3504 /* No RC6 before Ironlake */
3505 if (INTEL_INFO(dev
)->gen
< 5)
3508 /* RC6 is only on Ironlake mobile not on desktop */
3509 if (INTEL_INFO(dev
)->gen
== 5 && !IS_IRONLAKE_M(dev
))
3512 /* Respect the kernel parameter if it is set */
3513 if (enable_rc6
>= 0) {
3516 if (INTEL_INFO(dev
)->gen
== 6 || IS_IVYBRIDGE(dev
))
3517 mask
= INTEL_RC6_ENABLE
| INTEL_RC6p_ENABLE
|
3520 mask
= INTEL_RC6_ENABLE
;
3522 if ((enable_rc6
& mask
) != enable_rc6
)
3523 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
3524 enable_rc6
& mask
, enable_rc6
, mask
);
3526 return enable_rc6
& mask
;
3529 /* Disable RC6 on Ironlake */
3530 if (INTEL_INFO(dev
)->gen
== 5)
3533 if (IS_IVYBRIDGE(dev
))
3534 return (INTEL_RC6_ENABLE
| INTEL_RC6p_ENABLE
);
3536 return INTEL_RC6_ENABLE
;
3539 int intel_enable_rc6(const struct drm_device
*dev
)
3541 return i915
.enable_rc6
;
3544 static void gen8_enable_rps_interrupts(struct drm_device
*dev
)
3546 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3548 spin_lock_irq(&dev_priv
->irq_lock
);
3549 WARN_ON(dev_priv
->rps
.pm_iir
);
3550 gen8_enable_pm_irq(dev_priv
, dev_priv
->pm_rps_events
);
3551 I915_WRITE(GEN8_GT_IIR(2), dev_priv
->pm_rps_events
);
3552 spin_unlock_irq(&dev_priv
->irq_lock
);
3555 static void gen6_enable_rps_interrupts(struct drm_device
*dev
)
3557 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3559 spin_lock_irq(&dev_priv
->irq_lock
);
3560 WARN_ON(dev_priv
->rps
.pm_iir
);
3561 gen6_enable_pm_irq(dev_priv
, dev_priv
->pm_rps_events
);
3562 I915_WRITE(GEN6_PMIIR
, dev_priv
->pm_rps_events
);
3563 spin_unlock_irq(&dev_priv
->irq_lock
);
3566 static void parse_rp_state_cap(struct drm_i915_private
*dev_priv
, u32 rp_state_cap
)
3568 /* All of these values are in units of 50MHz */
3569 dev_priv
->rps
.cur_freq
= 0;
3570 /* static values from HW: RP0 < RPe < RP1 < RPn (min_freq) */
3571 dev_priv
->rps
.rp1_freq
= (rp_state_cap
>> 8) & 0xff;
3572 dev_priv
->rps
.rp0_freq
= (rp_state_cap
>> 0) & 0xff;
3573 dev_priv
->rps
.min_freq
= (rp_state_cap
>> 16) & 0xff;
3574 /* XXX: only BYT has a special efficient freq */
3575 dev_priv
->rps
.efficient_freq
= dev_priv
->rps
.rp1_freq
;
3576 /* hw_max = RP0 until we check for overclocking */
3577 dev_priv
->rps
.max_freq
= dev_priv
->rps
.rp0_freq
;
3579 /* Preserve min/max settings in case of re-init */
3580 if (dev_priv
->rps
.max_freq_softlimit
== 0)
3581 dev_priv
->rps
.max_freq_softlimit
= dev_priv
->rps
.max_freq
;
3583 if (dev_priv
->rps
.min_freq_softlimit
== 0)
3584 dev_priv
->rps
.min_freq_softlimit
= dev_priv
->rps
.min_freq
;
3587 static void gen8_enable_rps(struct drm_device
*dev
)
3589 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3590 struct intel_engine_cs
*ring
;
3591 uint32_t rc6_mask
= 0, rp_state_cap
;
3594 /* 1a: Software RC state - RC0 */
3595 I915_WRITE(GEN6_RC_STATE
, 0);
3597 /* 1c & 1d: Get forcewake during program sequence. Although the driver
3598 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
3599 gen6_gt_force_wake_get(dev_priv
, FORCEWAKE_ALL
);
3601 /* 2a: Disable RC states. */
3602 I915_WRITE(GEN6_RC_CONTROL
, 0);
3604 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
3605 parse_rp_state_cap(dev_priv
, rp_state_cap
);
3607 /* 2b: Program RC6 thresholds.*/
3608 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 40 << 16);
3609 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000); /* 12500 * 1280ns */
3610 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25); /* 25 * 1280ns */
3611 for_each_ring(ring
, dev_priv
, unused
)
3612 I915_WRITE(RING_MAX_IDLE(ring
->mmio_base
), 10);
3613 I915_WRITE(GEN6_RC_SLEEP
, 0);
3614 if (IS_BROADWELL(dev
))
3615 I915_WRITE(GEN6_RC6_THRESHOLD
, 625); /* 800us/1.28 for TO */
3617 I915_WRITE(GEN6_RC6_THRESHOLD
, 50000); /* 50/125ms per EI */
3620 if (intel_enable_rc6(dev
) & INTEL_RC6_ENABLE
)
3621 rc6_mask
= GEN6_RC_CTL_RC6_ENABLE
;
3622 intel_print_rc6_info(dev
, rc6_mask
);
3623 if (IS_BROADWELL(dev
))
3624 I915_WRITE(GEN6_RC_CONTROL
, GEN6_RC_CTL_HW_ENABLE
|
3625 GEN7_RC_CTL_TO_MODE
|
3628 I915_WRITE(GEN6_RC_CONTROL
, GEN6_RC_CTL_HW_ENABLE
|
3629 GEN6_RC_CTL_EI_MODE(1) |
3632 /* 4 Program defaults and thresholds for RPS*/
3633 I915_WRITE(GEN6_RPNSWREQ
,
3634 HSW_FREQUENCY(dev_priv
->rps
.rp1_freq
));
3635 I915_WRITE(GEN6_RC_VIDEO_FREQ
,
3636 HSW_FREQUENCY(dev_priv
->rps
.rp1_freq
));
3637 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
3638 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 100000000 / 128); /* 1 second timeout */
3640 /* Docs recommend 900MHz, and 300 MHz respectively */
3641 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS
,
3642 dev_priv
->rps
.max_freq_softlimit
<< 24 |
3643 dev_priv
->rps
.min_freq_softlimit
<< 16);
3645 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 7600000 / 128); /* 76ms busyness per EI, 90% */
3646 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 31300000 / 128); /* 313ms busyness per EI, 70%*/
3647 I915_WRITE(GEN6_RP_UP_EI
, 66000); /* 84.48ms, XXX: random? */
3648 I915_WRITE(GEN6_RP_DOWN_EI
, 350000); /* 448ms, XXX: random? */
3650 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
3653 I915_WRITE(GEN6_RP_CONTROL
,
3654 GEN6_RP_MEDIA_TURBO
|
3655 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
3656 GEN6_RP_MEDIA_IS_GFX
|
3658 GEN6_RP_UP_BUSY_AVG
|
3659 GEN6_RP_DOWN_IDLE_AVG
);
3661 /* 6: Ring frequency + overclocking (our driver does this later */
3663 gen6_set_rps(dev
, (I915_READ(GEN6_GT_PERF_STATUS
) & 0xff00) >> 8);
3665 gen8_enable_rps_interrupts(dev
);
3667 gen6_gt_force_wake_put(dev_priv
, FORCEWAKE_ALL
);
3670 static void gen6_enable_rps(struct drm_device
*dev
)
3672 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3673 struct intel_engine_cs
*ring
;
3676 u32 rc6vids
, pcu_mbox
= 0, rc6_mask
= 0;
3681 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
3683 /* Here begins a magic sequence of register writes to enable
3684 * auto-downclocking.
3686 * Perhaps there might be some value in exposing these to
3689 I915_WRITE(GEN6_RC_STATE
, 0);
3691 /* Clear the DBG now so we don't confuse earlier errors */
3692 if ((gtfifodbg
= I915_READ(GTFIFODBG
))) {
3693 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg
);
3694 I915_WRITE(GTFIFODBG
, gtfifodbg
);
3697 gen6_gt_force_wake_get(dev_priv
, FORCEWAKE_ALL
);
3699 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
3700 gt_perf_status
= I915_READ(GEN6_GT_PERF_STATUS
);
3702 parse_rp_state_cap(dev_priv
, rp_state_cap
);
3704 /* disable the counters and set deterministic thresholds */
3705 I915_WRITE(GEN6_RC_CONTROL
, 0);
3707 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT
, 1000 << 16);
3708 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 40 << 16 | 30);
3709 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT
, 30);
3710 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000);
3711 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25);
3713 for_each_ring(ring
, dev_priv
, i
)
3714 I915_WRITE(RING_MAX_IDLE(ring
->mmio_base
), 10);
3716 I915_WRITE(GEN6_RC_SLEEP
, 0);
3717 I915_WRITE(GEN6_RC1e_THRESHOLD
, 1000);
3718 if (IS_IVYBRIDGE(dev
))
3719 I915_WRITE(GEN6_RC6_THRESHOLD
, 125000);
3721 I915_WRITE(GEN6_RC6_THRESHOLD
, 50000);
3722 I915_WRITE(GEN6_RC6p_THRESHOLD
, 150000);
3723 I915_WRITE(GEN6_RC6pp_THRESHOLD
, 64000); /* unused */
3725 /* Check if we are enabling RC6 */
3726 rc6_mode
= intel_enable_rc6(dev_priv
->dev
);
3727 if (rc6_mode
& INTEL_RC6_ENABLE
)
3728 rc6_mask
|= GEN6_RC_CTL_RC6_ENABLE
;
3730 /* We don't use those on Haswell */
3731 if (!IS_HASWELL(dev
)) {
3732 if (rc6_mode
& INTEL_RC6p_ENABLE
)
3733 rc6_mask
|= GEN6_RC_CTL_RC6p_ENABLE
;
3735 if (rc6_mode
& INTEL_RC6pp_ENABLE
)
3736 rc6_mask
|= GEN6_RC_CTL_RC6pp_ENABLE
;
3739 intel_print_rc6_info(dev
, rc6_mask
);
3741 I915_WRITE(GEN6_RC_CONTROL
,
3743 GEN6_RC_CTL_EI_MODE(1) |
3744 GEN6_RC_CTL_HW_ENABLE
);
3746 /* Power down if completely idle for over 50ms */
3747 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 50000);
3748 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
3750 ret
= sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_MIN_FREQ_TABLE
, 0);
3752 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
3754 ret
= sandybridge_pcode_read(dev_priv
, GEN6_READ_OC_PARAMS
, &pcu_mbox
);
3755 if (!ret
&& (pcu_mbox
& (1<<31))) { /* OC supported */
3756 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
3757 (dev_priv
->rps
.max_freq_softlimit
& 0xff) * 50,
3758 (pcu_mbox
& 0xff) * 50);
3759 dev_priv
->rps
.max_freq
= pcu_mbox
& 0xff;
3762 dev_priv
->rps
.power
= HIGH_POWER
; /* force a reset */
3763 gen6_set_rps(dev_priv
->dev
, dev_priv
->rps
.min_freq_softlimit
);
3765 gen6_enable_rps_interrupts(dev
);
3768 ret
= sandybridge_pcode_read(dev_priv
, GEN6_PCODE_READ_RC6VIDS
, &rc6vids
);
3769 if (IS_GEN6(dev
) && ret
) {
3770 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
3771 } else if (IS_GEN6(dev
) && (GEN6_DECODE_RC6_VID(rc6vids
& 0xff) < 450)) {
3772 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
3773 GEN6_DECODE_RC6_VID(rc6vids
& 0xff), 450);
3774 rc6vids
&= 0xffff00;
3775 rc6vids
|= GEN6_ENCODE_RC6_VID(450);
3776 ret
= sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_RC6VIDS
, rc6vids
);
3778 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
3781 gen6_gt_force_wake_put(dev_priv
, FORCEWAKE_ALL
);
3784 static void __gen6_update_ring_freq(struct drm_device
*dev
)
3786 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3788 unsigned int gpu_freq
;
3789 unsigned int max_ia_freq
, min_ring_freq
;
3790 int scaling_factor
= 180;
3791 struct cpufreq_policy
*policy
;
3793 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
3795 policy
= cpufreq_cpu_get(0);
3797 max_ia_freq
= policy
->cpuinfo
.max_freq
;
3798 cpufreq_cpu_put(policy
);
3801 * Default to measured freq if none found, PCU will ensure we
3804 max_ia_freq
= tsc_khz
;
3807 /* Convert from kHz to MHz */
3808 max_ia_freq
/= 1000;
3810 min_ring_freq
= I915_READ(DCLK
) & 0xf;
3811 /* convert DDR frequency from units of 266.6MHz to bandwidth */
3812 min_ring_freq
= mult_frac(min_ring_freq
, 8, 3);
3815 * For each potential GPU frequency, load a ring frequency we'd like
3816 * to use for memory access. We do this by specifying the IA frequency
3817 * the PCU should use as a reference to determine the ring frequency.
3819 for (gpu_freq
= dev_priv
->rps
.max_freq_softlimit
; gpu_freq
>= dev_priv
->rps
.min_freq_softlimit
;
3821 int diff
= dev_priv
->rps
.max_freq_softlimit
- gpu_freq
;
3822 unsigned int ia_freq
= 0, ring_freq
= 0;
3824 if (INTEL_INFO(dev
)->gen
>= 8) {
3825 /* max(2 * GT, DDR). NB: GT is 50MHz units */
3826 ring_freq
= max(min_ring_freq
, gpu_freq
);
3827 } else if (IS_HASWELL(dev
)) {
3828 ring_freq
= mult_frac(gpu_freq
, 5, 4);
3829 ring_freq
= max(min_ring_freq
, ring_freq
);
3830 /* leave ia_freq as the default, chosen by cpufreq */
3832 /* On older processors, there is no separate ring
3833 * clock domain, so in order to boost the bandwidth
3834 * of the ring, we need to upclock the CPU (ia_freq).
3836 * For GPU frequencies less than 750MHz,
3837 * just use the lowest ring freq.
3839 if (gpu_freq
< min_freq
)
3842 ia_freq
= max_ia_freq
- ((diff
* scaling_factor
) / 2);
3843 ia_freq
= DIV_ROUND_CLOSEST(ia_freq
, 100);
3846 sandybridge_pcode_write(dev_priv
,
3847 GEN6_PCODE_WRITE_MIN_FREQ_TABLE
,
3848 ia_freq
<< GEN6_PCODE_FREQ_IA_RATIO_SHIFT
|
3849 ring_freq
<< GEN6_PCODE_FREQ_RING_RATIO_SHIFT
|
3854 void gen6_update_ring_freq(struct drm_device
*dev
)
3856 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3858 if (INTEL_INFO(dev
)->gen
< 6 || IS_VALLEYVIEW(dev
))
3861 mutex_lock(&dev_priv
->rps
.hw_lock
);
3862 __gen6_update_ring_freq(dev
);
3863 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3866 static int cherryview_rps_max_freq(struct drm_i915_private
*dev_priv
)
3870 val
= vlv_punit_read(dev_priv
, PUNIT_GPU_STATUS_REG
);
3871 rp0
= (val
>> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT
) & PUNIT_GPU_STATUS_MAX_FREQ_MASK
;
3876 static int cherryview_rps_rpe_freq(struct drm_i915_private
*dev_priv
)
3880 val
= vlv_punit_read(dev_priv
, PUNIT_GPU_DUTYCYCLE_REG
);
3881 rpe
= (val
>> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT
) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK
;
3886 static int cherryview_rps_guar_freq(struct drm_i915_private
*dev_priv
)
3890 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
3891 rp1
= (val
>> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT
) & PUNIT_GPU_STATUS_MAX_FREQ_MASK
;
3896 static int cherryview_rps_min_freq(struct drm_i915_private
*dev_priv
)
3900 val
= vlv_punit_read(dev_priv
, PUNIT_GPU_STATUS_REG
);
3901 rpn
= (val
>> PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT
) & PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK
;
3905 static int valleyview_rps_guar_freq(struct drm_i915_private
*dev_priv
)
3909 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FREQ_FUSE
);
3911 rp1
= (val
& FB_GFX_FGUARANTEED_FREQ_FUSE_MASK
) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT
;
3916 static int valleyview_rps_max_freq(struct drm_i915_private
*dev_priv
)
3920 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FREQ_FUSE
);
3922 rp0
= (val
& FB_GFX_MAX_FREQ_FUSE_MASK
) >> FB_GFX_MAX_FREQ_FUSE_SHIFT
;
3924 rp0
= min_t(u32
, rp0
, 0xea);
3929 static int valleyview_rps_rpe_freq(struct drm_i915_private
*dev_priv
)
3933 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FMAX_FUSE_LO
);
3934 rpe
= (val
& FB_FMAX_VMIN_FREQ_LO_MASK
) >> FB_FMAX_VMIN_FREQ_LO_SHIFT
;
3935 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FMAX_FUSE_HI
);
3936 rpe
|= (val
& FB_FMAX_VMIN_FREQ_HI_MASK
) << 5;
3941 static int valleyview_rps_min_freq(struct drm_i915_private
*dev_priv
)
3943 return vlv_punit_read(dev_priv
, PUNIT_REG_GPU_LFM
) & 0xff;
3946 /* Check that the pctx buffer wasn't move under us. */
3947 static void valleyview_check_pctx(struct drm_i915_private
*dev_priv
)
3949 unsigned long pctx_addr
= I915_READ(VLV_PCBR
) & ~4095;
3951 WARN_ON(pctx_addr
!= dev_priv
->mm
.stolen_base
+
3952 dev_priv
->vlv_pctx
->stolen
->start
);
3956 /* Check that the pcbr address is not empty. */
3957 static void cherryview_check_pctx(struct drm_i915_private
*dev_priv
)
3959 unsigned long pctx_addr
= I915_READ(VLV_PCBR
) & ~4095;
3961 WARN_ON((pctx_addr
>> VLV_PCBR_ADDR_SHIFT
) == 0);
3964 static void cherryview_setup_pctx(struct drm_device
*dev
)
3966 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3967 unsigned long pctx_paddr
, paddr
;
3968 struct i915_gtt
*gtt
= &dev_priv
->gtt
;
3970 int pctx_size
= 32*1024;
3972 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
3974 pcbr
= I915_READ(VLV_PCBR
);
3975 if ((pcbr
>> VLV_PCBR_ADDR_SHIFT
) == 0) {
3976 paddr
= (dev_priv
->mm
.stolen_base
+
3977 (gtt
->stolen_size
- pctx_size
));
3979 pctx_paddr
= (paddr
& (~4095));
3980 I915_WRITE(VLV_PCBR
, pctx_paddr
);
3984 static void valleyview_setup_pctx(struct drm_device
*dev
)
3986 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3987 struct drm_i915_gem_object
*pctx
;
3988 unsigned long pctx_paddr
;
3990 int pctx_size
= 24*1024;
3992 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
3994 pcbr
= I915_READ(VLV_PCBR
);
3996 /* BIOS set it up already, grab the pre-alloc'd space */
3999 pcbr_offset
= (pcbr
& (~4095)) - dev_priv
->mm
.stolen_base
;
4000 pctx
= i915_gem_object_create_stolen_for_preallocated(dev_priv
->dev
,
4002 I915_GTT_OFFSET_NONE
,
4008 * From the Gunit register HAS:
4009 * The Gfx driver is expected to program this register and ensure
4010 * proper allocation within Gfx stolen memory. For example, this
4011 * register should be programmed such than the PCBR range does not
4012 * overlap with other ranges, such as the frame buffer, protected
4013 * memory, or any other relevant ranges.
4015 pctx
= i915_gem_object_create_stolen(dev
, pctx_size
);
4017 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
4021 pctx_paddr
= dev_priv
->mm
.stolen_base
+ pctx
->stolen
->start
;
4022 I915_WRITE(VLV_PCBR
, pctx_paddr
);
4025 dev_priv
->vlv_pctx
= pctx
;
4028 static void valleyview_cleanup_pctx(struct drm_device
*dev
)
4030 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4032 if (WARN_ON(!dev_priv
->vlv_pctx
))
4035 drm_gem_object_unreference(&dev_priv
->vlv_pctx
->base
);
4036 dev_priv
->vlv_pctx
= NULL
;
4039 static void valleyview_init_gt_powersave(struct drm_device
*dev
)
4041 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4043 valleyview_setup_pctx(dev
);
4045 mutex_lock(&dev_priv
->rps
.hw_lock
);
4047 dev_priv
->rps
.max_freq
= valleyview_rps_max_freq(dev_priv
);
4048 dev_priv
->rps
.rp0_freq
= dev_priv
->rps
.max_freq
;
4049 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
4050 vlv_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
),
4051 dev_priv
->rps
.max_freq
);
4053 dev_priv
->rps
.efficient_freq
= valleyview_rps_rpe_freq(dev_priv
);
4054 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
4055 vlv_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
),
4056 dev_priv
->rps
.efficient_freq
);
4058 dev_priv
->rps
.rp1_freq
= valleyview_rps_guar_freq(dev_priv
);
4059 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
4060 vlv_gpu_freq(dev_priv
, dev_priv
->rps
.rp1_freq
),
4061 dev_priv
->rps
.rp1_freq
);
4063 dev_priv
->rps
.min_freq
= valleyview_rps_min_freq(dev_priv
);
4064 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
4065 vlv_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
),
4066 dev_priv
->rps
.min_freq
);
4068 /* Preserve min/max settings in case of re-init */
4069 if (dev_priv
->rps
.max_freq_softlimit
== 0)
4070 dev_priv
->rps
.max_freq_softlimit
= dev_priv
->rps
.max_freq
;
4072 if (dev_priv
->rps
.min_freq_softlimit
== 0)
4073 dev_priv
->rps
.min_freq_softlimit
= dev_priv
->rps
.min_freq
;
4075 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4078 static void cherryview_init_gt_powersave(struct drm_device
*dev
)
4080 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4082 cherryview_setup_pctx(dev
);
4084 mutex_lock(&dev_priv
->rps
.hw_lock
);
4086 dev_priv
->rps
.max_freq
= cherryview_rps_max_freq(dev_priv
);
4087 dev_priv
->rps
.rp0_freq
= dev_priv
->rps
.max_freq
;
4088 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
4089 vlv_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
),
4090 dev_priv
->rps
.max_freq
);
4092 dev_priv
->rps
.efficient_freq
= cherryview_rps_rpe_freq(dev_priv
);
4093 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
4094 vlv_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
),
4095 dev_priv
->rps
.efficient_freq
);
4097 dev_priv
->rps
.rp1_freq
= cherryview_rps_guar_freq(dev_priv
);
4098 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
4099 vlv_gpu_freq(dev_priv
, dev_priv
->rps
.rp1_freq
),
4100 dev_priv
->rps
.rp1_freq
);
4102 dev_priv
->rps
.min_freq
= cherryview_rps_min_freq(dev_priv
);
4103 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
4104 vlv_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
),
4105 dev_priv
->rps
.min_freq
);
4107 /* Preserve min/max settings in case of re-init */
4108 if (dev_priv
->rps
.max_freq_softlimit
== 0)
4109 dev_priv
->rps
.max_freq_softlimit
= dev_priv
->rps
.max_freq
;
4111 if (dev_priv
->rps
.min_freq_softlimit
== 0)
4112 dev_priv
->rps
.min_freq_softlimit
= dev_priv
->rps
.min_freq
;
4114 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4117 static void valleyview_cleanup_gt_powersave(struct drm_device
*dev
)
4119 valleyview_cleanup_pctx(dev
);
4122 static void cherryview_enable_rps(struct drm_device
*dev
)
4124 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4125 struct intel_engine_cs
*ring
;
4126 u32 gtfifodbg
, val
, rc6_mode
= 0, pcbr
;
4129 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
4131 gtfifodbg
= I915_READ(GTFIFODBG
);
4133 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4135 I915_WRITE(GTFIFODBG
, gtfifodbg
);
4138 cherryview_check_pctx(dev_priv
);
4140 /* 1a & 1b: Get forcewake during program sequence. Although the driver
4141 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4142 gen6_gt_force_wake_get(dev_priv
, FORCEWAKE_ALL
);
4144 /* 2a: Program RC6 thresholds.*/
4145 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 40 << 16);
4146 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000); /* 12500 * 1280ns */
4147 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25); /* 25 * 1280ns */
4149 for_each_ring(ring
, dev_priv
, i
)
4150 I915_WRITE(RING_MAX_IDLE(ring
->mmio_base
), 10);
4151 I915_WRITE(GEN6_RC_SLEEP
, 0);
4153 I915_WRITE(GEN6_RC6_THRESHOLD
, 50000); /* 50/125ms per EI */
4155 /* allows RC6 residency counter to work */
4156 I915_WRITE(VLV_COUNTER_CONTROL
,
4157 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH
|
4158 VLV_MEDIA_RC6_COUNT_EN
|
4159 VLV_RENDER_RC6_COUNT_EN
));
4161 /* For now we assume BIOS is allocating and populating the PCBR */
4162 pcbr
= I915_READ(VLV_PCBR
);
4164 DRM_DEBUG_DRIVER("PCBR offset : 0x%x\n", pcbr
);
4167 if ((intel_enable_rc6(dev
) & INTEL_RC6_ENABLE
) &&
4168 (pcbr
>> VLV_PCBR_ADDR_SHIFT
))
4169 rc6_mode
= GEN6_RC_CTL_EI_MODE(1);
4171 I915_WRITE(GEN6_RC_CONTROL
, rc6_mode
);
4173 /* 4 Program defaults and thresholds for RPS*/
4174 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 59400);
4175 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 245000);
4176 I915_WRITE(GEN6_RP_UP_EI
, 66000);
4177 I915_WRITE(GEN6_RP_DOWN_EI
, 350000);
4179 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
4181 /* WaDisablePwrmtrEvent:chv (pre-production hw) */
4182 I915_WRITE(0xA80C, I915_READ(0xA80C) & 0x00ffffff);
4183 I915_WRITE(0xA810, I915_READ(0xA810) & 0xffffff00);
4186 I915_WRITE(GEN6_RP_CONTROL
,
4187 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
4188 GEN6_RP_MEDIA_IS_GFX
| /* WaSetMaskForGfxBusyness:chv (pre-production hw ?) */
4190 GEN6_RP_UP_BUSY_AVG
|
4191 GEN6_RP_DOWN_IDLE_AVG
);
4193 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
4195 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val
& 0x10 ? "yes" : "no");
4196 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val
);
4198 dev_priv
->rps
.cur_freq
= (val
>> 8) & 0xff;
4199 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
4200 vlv_gpu_freq(dev_priv
, dev_priv
->rps
.cur_freq
),
4201 dev_priv
->rps
.cur_freq
);
4203 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
4204 vlv_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
),
4205 dev_priv
->rps
.efficient_freq
);
4207 valleyview_set_rps(dev_priv
->dev
, dev_priv
->rps
.efficient_freq
);
4209 gen8_enable_rps_interrupts(dev
);
4211 gen6_gt_force_wake_put(dev_priv
, FORCEWAKE_ALL
);
4214 static void valleyview_enable_rps(struct drm_device
*dev
)
4216 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4217 struct intel_engine_cs
*ring
;
4218 u32 gtfifodbg
, val
, rc6_mode
= 0;
4221 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
4223 valleyview_check_pctx(dev_priv
);
4225 if ((gtfifodbg
= I915_READ(GTFIFODBG
))) {
4226 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4228 I915_WRITE(GTFIFODBG
, gtfifodbg
);
4231 /* If VLV, Forcewake all wells, else re-direct to regular path */
4232 gen6_gt_force_wake_get(dev_priv
, FORCEWAKE_ALL
);
4234 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 59400);
4235 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 245000);
4236 I915_WRITE(GEN6_RP_UP_EI
, 66000);
4237 I915_WRITE(GEN6_RP_DOWN_EI
, 350000);
4239 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
4240 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 0xf4240);
4242 I915_WRITE(GEN6_RP_CONTROL
,
4243 GEN6_RP_MEDIA_TURBO
|
4244 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
4245 GEN6_RP_MEDIA_IS_GFX
|
4247 GEN6_RP_UP_BUSY_AVG
|
4248 GEN6_RP_DOWN_IDLE_CONT
);
4250 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 0x00280000);
4251 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000);
4252 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25);
4254 for_each_ring(ring
, dev_priv
, i
)
4255 I915_WRITE(RING_MAX_IDLE(ring
->mmio_base
), 10);
4257 I915_WRITE(GEN6_RC6_THRESHOLD
, 0x557);
4259 /* allows RC6 residency counter to work */
4260 I915_WRITE(VLV_COUNTER_CONTROL
,
4261 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN
|
4262 VLV_RENDER_RC0_COUNT_EN
|
4263 VLV_MEDIA_RC6_COUNT_EN
|
4264 VLV_RENDER_RC6_COUNT_EN
));
4266 if (intel_enable_rc6(dev
) & INTEL_RC6_ENABLE
)
4267 rc6_mode
= GEN7_RC_CTL_TO_MODE
| VLV_RC_CTL_CTX_RST_PARALLEL
;
4269 intel_print_rc6_info(dev
, rc6_mode
);
4271 I915_WRITE(GEN6_RC_CONTROL
, rc6_mode
);
4273 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
4275 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val
& 0x10 ? "yes" : "no");
4276 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val
);
4278 dev_priv
->rps
.cur_freq
= (val
>> 8) & 0xff;
4279 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
4280 vlv_gpu_freq(dev_priv
, dev_priv
->rps
.cur_freq
),
4281 dev_priv
->rps
.cur_freq
);
4283 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
4284 vlv_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
),
4285 dev_priv
->rps
.efficient_freq
);
4287 valleyview_set_rps(dev_priv
->dev
, dev_priv
->rps
.efficient_freq
);
4289 gen6_enable_rps_interrupts(dev
);
4291 gen6_gt_force_wake_put(dev_priv
, FORCEWAKE_ALL
);
4294 void ironlake_teardown_rc6(struct drm_device
*dev
)
4296 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4298 if (dev_priv
->ips
.renderctx
) {
4299 i915_gem_object_ggtt_unpin(dev_priv
->ips
.renderctx
);
4300 drm_gem_object_unreference(&dev_priv
->ips
.renderctx
->base
);
4301 dev_priv
->ips
.renderctx
= NULL
;
4304 if (dev_priv
->ips
.pwrctx
) {
4305 i915_gem_object_ggtt_unpin(dev_priv
->ips
.pwrctx
);
4306 drm_gem_object_unreference(&dev_priv
->ips
.pwrctx
->base
);
4307 dev_priv
->ips
.pwrctx
= NULL
;
4311 static void ironlake_disable_rc6(struct drm_device
*dev
)
4313 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4315 if (I915_READ(PWRCTXA
)) {
4316 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
4317 I915_WRITE(RSTDBYCTL
, I915_READ(RSTDBYCTL
) | RCX_SW_EXIT
);
4318 wait_for(((I915_READ(RSTDBYCTL
) & RSX_STATUS_MASK
) == RSX_STATUS_ON
),
4321 I915_WRITE(PWRCTXA
, 0);
4322 POSTING_READ(PWRCTXA
);
4324 I915_WRITE(RSTDBYCTL
, I915_READ(RSTDBYCTL
) & ~RCX_SW_EXIT
);
4325 POSTING_READ(RSTDBYCTL
);
4329 static int ironlake_setup_rc6(struct drm_device
*dev
)
4331 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4333 if (dev_priv
->ips
.renderctx
== NULL
)
4334 dev_priv
->ips
.renderctx
= intel_alloc_context_page(dev
);
4335 if (!dev_priv
->ips
.renderctx
)
4338 if (dev_priv
->ips
.pwrctx
== NULL
)
4339 dev_priv
->ips
.pwrctx
= intel_alloc_context_page(dev
);
4340 if (!dev_priv
->ips
.pwrctx
) {
4341 ironlake_teardown_rc6(dev
);
4348 static void ironlake_enable_rc6(struct drm_device
*dev
)
4350 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4351 struct intel_engine_cs
*ring
= &dev_priv
->ring
[RCS
];
4352 bool was_interruptible
;
4355 /* rc6 disabled by default due to repeated reports of hanging during
4358 if (!intel_enable_rc6(dev
))
4361 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
4363 ret
= ironlake_setup_rc6(dev
);
4367 was_interruptible
= dev_priv
->mm
.interruptible
;
4368 dev_priv
->mm
.interruptible
= false;
4371 * GPU can automatically power down the render unit if given a page
4374 ret
= intel_ring_begin(ring
, 6);
4376 ironlake_teardown_rc6(dev
);
4377 dev_priv
->mm
.interruptible
= was_interruptible
;
4381 intel_ring_emit(ring
, MI_SUSPEND_FLUSH
| MI_SUSPEND_FLUSH_EN
);
4382 intel_ring_emit(ring
, MI_SET_CONTEXT
);
4383 intel_ring_emit(ring
, i915_gem_obj_ggtt_offset(dev_priv
->ips
.renderctx
) |
4385 MI_SAVE_EXT_STATE_EN
|
4386 MI_RESTORE_EXT_STATE_EN
|
4387 MI_RESTORE_INHIBIT
);
4388 intel_ring_emit(ring
, MI_SUSPEND_FLUSH
);
4389 intel_ring_emit(ring
, MI_NOOP
);
4390 intel_ring_emit(ring
, MI_FLUSH
);
4391 intel_ring_advance(ring
);
4394 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
4395 * does an implicit flush, combined with MI_FLUSH above, it should be
4396 * safe to assume that renderctx is valid
4398 ret
= intel_ring_idle(ring
);
4399 dev_priv
->mm
.interruptible
= was_interruptible
;
4401 DRM_ERROR("failed to enable ironlake power savings\n");
4402 ironlake_teardown_rc6(dev
);
4406 I915_WRITE(PWRCTXA
, i915_gem_obj_ggtt_offset(dev_priv
->ips
.pwrctx
) | PWRCTX_EN
);
4407 I915_WRITE(RSTDBYCTL
, I915_READ(RSTDBYCTL
) & ~RCX_SW_EXIT
);
4409 intel_print_rc6_info(dev
, GEN6_RC_CTL_RC6_ENABLE
);
4412 static unsigned long intel_pxfreq(u32 vidfreq
)
4415 int div
= (vidfreq
& 0x3f0000) >> 16;
4416 int post
= (vidfreq
& 0x3000) >> 12;
4417 int pre
= (vidfreq
& 0x7);
4422 freq
= ((div
* 133333) / ((1<<post
) * pre
));
4427 static const struct cparams
{
4433 { 1, 1333, 301, 28664 },
4434 { 1, 1066, 294, 24460 },
4435 { 1, 800, 294, 25192 },
4436 { 0, 1333, 276, 27605 },
4437 { 0, 1066, 276, 27605 },
4438 { 0, 800, 231, 23784 },
4441 static unsigned long __i915_chipset_val(struct drm_i915_private
*dev_priv
)
4443 u64 total_count
, diff
, ret
;
4444 u32 count1
, count2
, count3
, m
= 0, c
= 0;
4445 unsigned long now
= jiffies_to_msecs(jiffies
), diff1
;
4448 assert_spin_locked(&mchdev_lock
);
4450 diff1
= now
- dev_priv
->ips
.last_time1
;
4452 /* Prevent division-by-zero if we are asking too fast.
4453 * Also, we don't get interesting results if we are polling
4454 * faster than once in 10ms, so just return the saved value
4458 return dev_priv
->ips
.chipset_power
;
4460 count1
= I915_READ(DMIEC
);
4461 count2
= I915_READ(DDREC
);
4462 count3
= I915_READ(CSIEC
);
4464 total_count
= count1
+ count2
+ count3
;
4466 /* FIXME: handle per-counter overflow */
4467 if (total_count
< dev_priv
->ips
.last_count1
) {
4468 diff
= ~0UL - dev_priv
->ips
.last_count1
;
4469 diff
+= total_count
;
4471 diff
= total_count
- dev_priv
->ips
.last_count1
;
4474 for (i
= 0; i
< ARRAY_SIZE(cparams
); i
++) {
4475 if (cparams
[i
].i
== dev_priv
->ips
.c_m
&&
4476 cparams
[i
].t
== dev_priv
->ips
.r_t
) {
4483 diff
= div_u64(diff
, diff1
);
4484 ret
= ((m
* diff
) + c
);
4485 ret
= div_u64(ret
, 10);
4487 dev_priv
->ips
.last_count1
= total_count
;
4488 dev_priv
->ips
.last_time1
= now
;
4490 dev_priv
->ips
.chipset_power
= ret
;
4495 unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
)
4497 struct drm_device
*dev
= dev_priv
->dev
;
4500 if (INTEL_INFO(dev
)->gen
!= 5)
4503 spin_lock_irq(&mchdev_lock
);
4505 val
= __i915_chipset_val(dev_priv
);
4507 spin_unlock_irq(&mchdev_lock
);
4512 unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
)
4514 unsigned long m
, x
, b
;
4517 tsfs
= I915_READ(TSFS
);
4519 m
= ((tsfs
& TSFS_SLOPE_MASK
) >> TSFS_SLOPE_SHIFT
);
4520 x
= I915_READ8(TR1
);
4522 b
= tsfs
& TSFS_INTR_MASK
;
4524 return ((m
* x
) / 127) - b
;
4527 static u16
pvid_to_extvid(struct drm_i915_private
*dev_priv
, u8 pxvid
)
4529 struct drm_device
*dev
= dev_priv
->dev
;
4530 static const struct v_table
{
4531 u16 vd
; /* in .1 mil */
4532 u16 vm
; /* in .1 mil */
4663 if (INTEL_INFO(dev
)->is_mobile
)
4664 return v_table
[pxvid
].vm
;
4666 return v_table
[pxvid
].vd
;
4669 static void __i915_update_gfx_val(struct drm_i915_private
*dev_priv
)
4671 struct timespec now
, diff1
;
4673 unsigned long diffms
;
4676 assert_spin_locked(&mchdev_lock
);
4678 getrawmonotonic(&now
);
4679 diff1
= timespec_sub(now
, dev_priv
->ips
.last_time2
);
4681 /* Don't divide by 0 */
4682 diffms
= diff1
.tv_sec
* 1000 + diff1
.tv_nsec
/ 1000000;
4686 count
= I915_READ(GFXEC
);
4688 if (count
< dev_priv
->ips
.last_count2
) {
4689 diff
= ~0UL - dev_priv
->ips
.last_count2
;
4692 diff
= count
- dev_priv
->ips
.last_count2
;
4695 dev_priv
->ips
.last_count2
= count
;
4696 dev_priv
->ips
.last_time2
= now
;
4698 /* More magic constants... */
4700 diff
= div_u64(diff
, diffms
* 10);
4701 dev_priv
->ips
.gfx_power
= diff
;
4704 void i915_update_gfx_val(struct drm_i915_private
*dev_priv
)
4706 struct drm_device
*dev
= dev_priv
->dev
;
4708 if (INTEL_INFO(dev
)->gen
!= 5)
4711 spin_lock_irq(&mchdev_lock
);
4713 __i915_update_gfx_val(dev_priv
);
4715 spin_unlock_irq(&mchdev_lock
);
4718 static unsigned long __i915_gfx_val(struct drm_i915_private
*dev_priv
)
4720 unsigned long t
, corr
, state1
, corr2
, state2
;
4723 assert_spin_locked(&mchdev_lock
);
4725 pxvid
= I915_READ(PXVFREQ_BASE
+ (dev_priv
->rps
.cur_freq
* 4));
4726 pxvid
= (pxvid
>> 24) & 0x7f;
4727 ext_v
= pvid_to_extvid(dev_priv
, pxvid
);
4731 t
= i915_mch_val(dev_priv
);
4733 /* Revel in the empirically derived constants */
4735 /* Correction factor in 1/100000 units */
4737 corr
= ((t
* 2349) + 135940);
4739 corr
= ((t
* 964) + 29317);
4741 corr
= ((t
* 301) + 1004);
4743 corr
= corr
* ((150142 * state1
) / 10000 - 78642);
4745 corr2
= (corr
* dev_priv
->ips
.corr
);
4747 state2
= (corr2
* state1
) / 10000;
4748 state2
/= 100; /* convert to mW */
4750 __i915_update_gfx_val(dev_priv
);
4752 return dev_priv
->ips
.gfx_power
+ state2
;
4755 unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
)
4757 struct drm_device
*dev
= dev_priv
->dev
;
4760 if (INTEL_INFO(dev
)->gen
!= 5)
4763 spin_lock_irq(&mchdev_lock
);
4765 val
= __i915_gfx_val(dev_priv
);
4767 spin_unlock_irq(&mchdev_lock
);
4773 * i915_read_mch_val - return value for IPS use
4775 * Calculate and return a value for the IPS driver to use when deciding whether
4776 * we have thermal and power headroom to increase CPU or GPU power budget.
4778 unsigned long i915_read_mch_val(void)
4780 struct drm_i915_private
*dev_priv
;
4781 unsigned long chipset_val
, graphics_val
, ret
= 0;
4783 spin_lock_irq(&mchdev_lock
);
4786 dev_priv
= i915_mch_dev
;
4788 chipset_val
= __i915_chipset_val(dev_priv
);
4789 graphics_val
= __i915_gfx_val(dev_priv
);
4791 ret
= chipset_val
+ graphics_val
;
4794 spin_unlock_irq(&mchdev_lock
);
4798 EXPORT_SYMBOL_GPL(i915_read_mch_val
);
4801 * i915_gpu_raise - raise GPU frequency limit
4803 * Raise the limit; IPS indicates we have thermal headroom.
4805 bool i915_gpu_raise(void)
4807 struct drm_i915_private
*dev_priv
;
4810 spin_lock_irq(&mchdev_lock
);
4811 if (!i915_mch_dev
) {
4815 dev_priv
= i915_mch_dev
;
4817 if (dev_priv
->ips
.max_delay
> dev_priv
->ips
.fmax
)
4818 dev_priv
->ips
.max_delay
--;
4821 spin_unlock_irq(&mchdev_lock
);
4825 EXPORT_SYMBOL_GPL(i915_gpu_raise
);
4828 * i915_gpu_lower - lower GPU frequency limit
4830 * IPS indicates we're close to a thermal limit, so throttle back the GPU
4831 * frequency maximum.
4833 bool i915_gpu_lower(void)
4835 struct drm_i915_private
*dev_priv
;
4838 spin_lock_irq(&mchdev_lock
);
4839 if (!i915_mch_dev
) {
4843 dev_priv
= i915_mch_dev
;
4845 if (dev_priv
->ips
.max_delay
< dev_priv
->ips
.min_delay
)
4846 dev_priv
->ips
.max_delay
++;
4849 spin_unlock_irq(&mchdev_lock
);
4853 EXPORT_SYMBOL_GPL(i915_gpu_lower
);
4856 * i915_gpu_busy - indicate GPU business to IPS
4858 * Tell the IPS driver whether or not the GPU is busy.
4860 bool i915_gpu_busy(void)
4862 struct drm_i915_private
*dev_priv
;
4863 struct intel_engine_cs
*ring
;
4867 spin_lock_irq(&mchdev_lock
);
4870 dev_priv
= i915_mch_dev
;
4872 for_each_ring(ring
, dev_priv
, i
)
4873 ret
|= !list_empty(&ring
->request_list
);
4876 spin_unlock_irq(&mchdev_lock
);
4880 EXPORT_SYMBOL_GPL(i915_gpu_busy
);
4883 * i915_gpu_turbo_disable - disable graphics turbo
4885 * Disable graphics turbo by resetting the max frequency and setting the
4886 * current frequency to the default.
4888 bool i915_gpu_turbo_disable(void)
4890 struct drm_i915_private
*dev_priv
;
4893 spin_lock_irq(&mchdev_lock
);
4894 if (!i915_mch_dev
) {
4898 dev_priv
= i915_mch_dev
;
4900 dev_priv
->ips
.max_delay
= dev_priv
->ips
.fstart
;
4902 if (!ironlake_set_drps(dev_priv
->dev
, dev_priv
->ips
.fstart
))
4906 spin_unlock_irq(&mchdev_lock
);
4910 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable
);
4913 * Tells the intel_ips driver that the i915 driver is now loaded, if
4914 * IPS got loaded first.
4916 * This awkward dance is so that neither module has to depend on the
4917 * other in order for IPS to do the appropriate communication of
4918 * GPU turbo limits to i915.
4921 ips_ping_for_i915_load(void)
4925 link
= symbol_get(ips_link_to_i915_driver
);
4928 symbol_put(ips_link_to_i915_driver
);
4932 void intel_gpu_ips_init(struct drm_i915_private
*dev_priv
)
4934 /* We only register the i915 ips part with intel-ips once everything is
4935 * set up, to avoid intel-ips sneaking in and reading bogus values. */
4936 spin_lock_irq(&mchdev_lock
);
4937 i915_mch_dev
= dev_priv
;
4938 spin_unlock_irq(&mchdev_lock
);
4940 ips_ping_for_i915_load();
4943 void intel_gpu_ips_teardown(void)
4945 spin_lock_irq(&mchdev_lock
);
4946 i915_mch_dev
= NULL
;
4947 spin_unlock_irq(&mchdev_lock
);
4950 static void intel_init_emon(struct drm_device
*dev
)
4952 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4957 /* Disable to program */
4961 /* Program energy weights for various events */
4962 I915_WRITE(SDEW
, 0x15040d00);
4963 I915_WRITE(CSIEW0
, 0x007f0000);
4964 I915_WRITE(CSIEW1
, 0x1e220004);
4965 I915_WRITE(CSIEW2
, 0x04000004);
4967 for (i
= 0; i
< 5; i
++)
4968 I915_WRITE(PEW
+ (i
* 4), 0);
4969 for (i
= 0; i
< 3; i
++)
4970 I915_WRITE(DEW
+ (i
* 4), 0);
4972 /* Program P-state weights to account for frequency power adjustment */
4973 for (i
= 0; i
< 16; i
++) {
4974 u32 pxvidfreq
= I915_READ(PXVFREQ_BASE
+ (i
* 4));
4975 unsigned long freq
= intel_pxfreq(pxvidfreq
);
4976 unsigned long vid
= (pxvidfreq
& PXVFREQ_PX_MASK
) >>
4981 val
*= (freq
/ 1000);
4983 val
/= (127*127*900);
4985 DRM_ERROR("bad pxval: %ld\n", val
);
4988 /* Render standby states get 0 weight */
4992 for (i
= 0; i
< 4; i
++) {
4993 u32 val
= (pxw
[i
*4] << 24) | (pxw
[(i
*4)+1] << 16) |
4994 (pxw
[(i
*4)+2] << 8) | (pxw
[(i
*4)+3]);
4995 I915_WRITE(PXW
+ (i
* 4), val
);
4998 /* Adjust magic regs to magic values (more experimental results) */
4999 I915_WRITE(OGW0
, 0);
5000 I915_WRITE(OGW1
, 0);
5001 I915_WRITE(EG0
, 0x00007f00);
5002 I915_WRITE(EG1
, 0x0000000e);
5003 I915_WRITE(EG2
, 0x000e0000);
5004 I915_WRITE(EG3
, 0x68000300);
5005 I915_WRITE(EG4
, 0x42000000);
5006 I915_WRITE(EG5
, 0x00140031);
5010 for (i
= 0; i
< 8; i
++)
5011 I915_WRITE(PXWL
+ (i
* 4), 0);
5013 /* Enable PMON + select events */
5014 I915_WRITE(ECR
, 0x80000019);
5016 lcfuse
= I915_READ(LCFUSE02
);
5018 dev_priv
->ips
.corr
= (lcfuse
& LCFUSE_HIV_MASK
);
5021 void intel_init_gt_powersave(struct drm_device
*dev
)
5023 i915
.enable_rc6
= sanitize_rc6_option(dev
, i915
.enable_rc6
);
5025 if (IS_CHERRYVIEW(dev
))
5026 cherryview_init_gt_powersave(dev
);
5027 else if (IS_VALLEYVIEW(dev
))
5028 valleyview_init_gt_powersave(dev
);
5031 void intel_cleanup_gt_powersave(struct drm_device
*dev
)
5033 if (IS_CHERRYVIEW(dev
))
5035 else if (IS_VALLEYVIEW(dev
))
5036 valleyview_cleanup_gt_powersave(dev
);
5040 * intel_suspend_gt_powersave - suspend PM work and helper threads
5043 * We don't want to disable RC6 or other features here, we just want
5044 * to make sure any work we've queued has finished and won't bother
5045 * us while we're suspended.
5047 void intel_suspend_gt_powersave(struct drm_device
*dev
)
5049 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5051 /* Interrupts should be disabled already to avoid re-arming. */
5052 WARN_ON(intel_irqs_enabled(dev_priv
));
5054 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
5056 cancel_work_sync(&dev_priv
->rps
.work
);
5058 /* Force GPU to min freq during suspend */
5059 gen6_rps_idle(dev_priv
);
5062 void intel_disable_gt_powersave(struct drm_device
*dev
)
5064 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5066 /* Interrupts should be disabled already to avoid re-arming. */
5067 WARN_ON(intel_irqs_enabled(dev_priv
));
5069 if (IS_IRONLAKE_M(dev
)) {
5070 ironlake_disable_drps(dev
);
5071 ironlake_disable_rc6(dev
);
5072 } else if (INTEL_INFO(dev
)->gen
>= 6) {
5073 intel_suspend_gt_powersave(dev
);
5075 mutex_lock(&dev_priv
->rps
.hw_lock
);
5076 if (IS_CHERRYVIEW(dev
))
5077 cherryview_disable_rps(dev
);
5078 else if (IS_VALLEYVIEW(dev
))
5079 valleyview_disable_rps(dev
);
5081 gen6_disable_rps(dev
);
5082 dev_priv
->rps
.enabled
= false;
5083 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5087 static void intel_gen6_powersave_work(struct work_struct
*work
)
5089 struct drm_i915_private
*dev_priv
=
5090 container_of(work
, struct drm_i915_private
,
5091 rps
.delayed_resume_work
.work
);
5092 struct drm_device
*dev
= dev_priv
->dev
;
5094 mutex_lock(&dev_priv
->rps
.hw_lock
);
5096 if (IS_CHERRYVIEW(dev
)) {
5097 cherryview_enable_rps(dev
);
5098 } else if (IS_VALLEYVIEW(dev
)) {
5099 valleyview_enable_rps(dev
);
5100 } else if (IS_BROADWELL(dev
)) {
5101 gen8_enable_rps(dev
);
5102 __gen6_update_ring_freq(dev
);
5104 gen6_enable_rps(dev
);
5105 __gen6_update_ring_freq(dev
);
5107 dev_priv
->rps
.enabled
= true;
5108 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5110 intel_runtime_pm_put(dev_priv
);
5113 void intel_enable_gt_powersave(struct drm_device
*dev
)
5115 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5117 if (IS_IRONLAKE_M(dev
)) {
5118 mutex_lock(&dev
->struct_mutex
);
5119 ironlake_enable_drps(dev
);
5120 ironlake_enable_rc6(dev
);
5121 intel_init_emon(dev
);
5122 mutex_unlock(&dev
->struct_mutex
);
5123 } else if (INTEL_INFO(dev
)->gen
>= 6) {
5125 * PCU communication is slow and this doesn't need to be
5126 * done at any specific time, so do this out of our fast path
5127 * to make resume and init faster.
5129 * We depend on the HW RC6 power context save/restore
5130 * mechanism when entering D3 through runtime PM suspend. So
5131 * disable RPM until RPS/RC6 is properly setup. We can only
5132 * get here via the driver load/system resume/runtime resume
5133 * paths, so the _noresume version is enough (and in case of
5134 * runtime resume it's necessary).
5136 if (schedule_delayed_work(&dev_priv
->rps
.delayed_resume_work
,
5137 round_jiffies_up_relative(HZ
)))
5138 intel_runtime_pm_get_noresume(dev_priv
);
5142 void intel_reset_gt_powersave(struct drm_device
*dev
)
5144 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5146 dev_priv
->rps
.enabled
= false;
5147 intel_enable_gt_powersave(dev
);
5150 static void ibx_init_clock_gating(struct drm_device
*dev
)
5152 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5155 * On Ibex Peak and Cougar Point, we need to disable clock
5156 * gating for the panel power sequencer or it will fail to
5157 * start up when no ports are active.
5159 I915_WRITE(SOUTH_DSPCLK_GATE_D
, PCH_DPLSUNIT_CLOCK_GATE_DISABLE
);
5162 static void g4x_disable_trickle_feed(struct drm_device
*dev
)
5164 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5167 for_each_pipe(pipe
) {
5168 I915_WRITE(DSPCNTR(pipe
),
5169 I915_READ(DSPCNTR(pipe
)) |
5170 DISPPLANE_TRICKLE_FEED_DISABLE
);
5171 intel_flush_primary_plane(dev_priv
, pipe
);
5175 static void ilk_init_lp_watermarks(struct drm_device
*dev
)
5177 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5179 I915_WRITE(WM3_LP_ILK
, I915_READ(WM3_LP_ILK
) & ~WM1_LP_SR_EN
);
5180 I915_WRITE(WM2_LP_ILK
, I915_READ(WM2_LP_ILK
) & ~WM1_LP_SR_EN
);
5181 I915_WRITE(WM1_LP_ILK
, I915_READ(WM1_LP_ILK
) & ~WM1_LP_SR_EN
);
5184 * Don't touch WM1S_LP_EN here.
5185 * Doing so could cause underruns.
5189 static void ironlake_init_clock_gating(struct drm_device
*dev
)
5191 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5192 uint32_t dspclk_gate
= ILK_VRHUNIT_CLOCK_GATE_DISABLE
;
5196 * WaFbcDisableDpfcClockGating:ilk
5198 dspclk_gate
|= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE
|
5199 ILK_DPFCUNIT_CLOCK_GATE_DISABLE
|
5200 ILK_DPFDUNIT_CLOCK_GATE_ENABLE
;
5202 I915_WRITE(PCH_3DCGDIS0
,
5203 MARIUNIT_CLOCK_GATE_DISABLE
|
5204 SVSMUNIT_CLOCK_GATE_DISABLE
);
5205 I915_WRITE(PCH_3DCGDIS1
,
5206 VFMUNIT_CLOCK_GATE_DISABLE
);
5209 * According to the spec the following bits should be set in
5210 * order to enable memory self-refresh
5211 * The bit 22/21 of 0x42004
5212 * The bit 5 of 0x42020
5213 * The bit 15 of 0x45000
5215 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
5216 (I915_READ(ILK_DISPLAY_CHICKEN2
) |
5217 ILK_DPARB_GATE
| ILK_VSDPFD_FULL
));
5218 dspclk_gate
|= ILK_DPARBUNIT_CLOCK_GATE_ENABLE
;
5219 I915_WRITE(DISP_ARB_CTL
,
5220 (I915_READ(DISP_ARB_CTL
) |
5223 ilk_init_lp_watermarks(dev
);
5226 * Based on the document from hardware guys the following bits
5227 * should be set unconditionally in order to enable FBC.
5228 * The bit 22 of 0x42000
5229 * The bit 22 of 0x42004
5230 * The bit 7,8,9 of 0x42020.
5232 if (IS_IRONLAKE_M(dev
)) {
5233 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
5234 I915_WRITE(ILK_DISPLAY_CHICKEN1
,
5235 I915_READ(ILK_DISPLAY_CHICKEN1
) |
5237 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
5238 I915_READ(ILK_DISPLAY_CHICKEN2
) |
5242 I915_WRITE(ILK_DSPCLK_GATE_D
, dspclk_gate
);
5244 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
5245 I915_READ(ILK_DISPLAY_CHICKEN2
) |
5246 ILK_ELPIN_409_SELECT
);
5247 I915_WRITE(_3D_CHICKEN2
,
5248 _3D_CHICKEN2_WM_READ_PIPELINED
<< 16 |
5249 _3D_CHICKEN2_WM_READ_PIPELINED
);
5251 /* WaDisableRenderCachePipelinedFlush:ilk */
5252 I915_WRITE(CACHE_MODE_0
,
5253 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE
));
5255 /* WaDisable_RenderCache_OperationalFlush:ilk */
5256 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
5258 g4x_disable_trickle_feed(dev
);
5260 ibx_init_clock_gating(dev
);
5263 static void cpt_init_clock_gating(struct drm_device
*dev
)
5265 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5270 * On Ibex Peak and Cougar Point, we need to disable clock
5271 * gating for the panel power sequencer or it will fail to
5272 * start up when no ports are active.
5274 I915_WRITE(SOUTH_DSPCLK_GATE_D
, PCH_DPLSUNIT_CLOCK_GATE_DISABLE
|
5275 PCH_DPLUNIT_CLOCK_GATE_DISABLE
|
5276 PCH_CPUNIT_CLOCK_GATE_DISABLE
);
5277 I915_WRITE(SOUTH_CHICKEN2
, I915_READ(SOUTH_CHICKEN2
) |
5278 DPLS_EDP_PPS_FIX_DIS
);
5279 /* The below fixes the weird display corruption, a few pixels shifted
5280 * downward, on (only) LVDS of some HP laptops with IVY.
5282 for_each_pipe(pipe
) {
5283 val
= I915_READ(TRANS_CHICKEN2(pipe
));
5284 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
5285 val
&= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED
;
5286 if (dev_priv
->vbt
.fdi_rx_polarity_inverted
)
5287 val
|= TRANS_CHICKEN2_FDI_POLARITY_REVERSED
;
5288 val
&= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK
;
5289 val
&= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER
;
5290 val
&= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH
;
5291 I915_WRITE(TRANS_CHICKEN2(pipe
), val
);
5293 /* WADP0ClockGatingDisable */
5294 for_each_pipe(pipe
) {
5295 I915_WRITE(TRANS_CHICKEN1(pipe
),
5296 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE
);
5300 static void gen6_check_mch_setup(struct drm_device
*dev
)
5302 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5305 tmp
= I915_READ(MCH_SSKPD
);
5306 if ((tmp
& MCH_SSKPD_WM0_MASK
) != MCH_SSKPD_WM0_VAL
)
5307 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
5311 static void gen6_init_clock_gating(struct drm_device
*dev
)
5313 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5314 uint32_t dspclk_gate
= ILK_VRHUNIT_CLOCK_GATE_DISABLE
;
5316 I915_WRITE(ILK_DSPCLK_GATE_D
, dspclk_gate
);
5318 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
5319 I915_READ(ILK_DISPLAY_CHICKEN2
) |
5320 ILK_ELPIN_409_SELECT
);
5322 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
5323 I915_WRITE(_3D_CHICKEN
,
5324 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB
));
5326 /* WaSetupGtModeTdRowDispatch:snb */
5327 if (IS_SNB_GT1(dev
))
5328 I915_WRITE(GEN6_GT_MODE
,
5329 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE
));
5331 /* WaDisable_RenderCache_OperationalFlush:snb */
5332 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
5335 * BSpec recoomends 8x4 when MSAA is used,
5336 * however in practice 16x4 seems fastest.
5338 * Note that PS/WM thread counts depend on the WIZ hashing
5339 * disable bit, which we don't touch here, but it's good
5340 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5342 I915_WRITE(GEN6_GT_MODE
,
5343 GEN6_WIZ_HASHING_MASK
| GEN6_WIZ_HASHING_16x4
);
5345 ilk_init_lp_watermarks(dev
);
5347 I915_WRITE(CACHE_MODE_0
,
5348 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB
));
5350 I915_WRITE(GEN6_UCGCTL1
,
5351 I915_READ(GEN6_UCGCTL1
) |
5352 GEN6_BLBUNIT_CLOCK_GATE_DISABLE
|
5353 GEN6_CSUNIT_CLOCK_GATE_DISABLE
);
5355 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5356 * gating disable must be set. Failure to set it results in
5357 * flickering pixels due to Z write ordering failures after
5358 * some amount of runtime in the Mesa "fire" demo, and Unigine
5359 * Sanctuary and Tropics, and apparently anything else with
5360 * alpha test or pixel discard.
5362 * According to the spec, bit 11 (RCCUNIT) must also be set,
5363 * but we didn't debug actual testcases to find it out.
5365 * WaDisableRCCUnitClockGating:snb
5366 * WaDisableRCPBUnitClockGating:snb
5368 I915_WRITE(GEN6_UCGCTL2
,
5369 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE
|
5370 GEN6_RCCUNIT_CLOCK_GATE_DISABLE
);
5372 /* WaStripsFansDisableFastClipPerformanceFix:snb */
5373 I915_WRITE(_3D_CHICKEN3
,
5374 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL
));
5378 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
5379 * 3DSTATE_SF number of SF output attributes is more than 16."
5381 I915_WRITE(_3D_CHICKEN3
,
5382 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH
));
5385 * According to the spec the following bits should be
5386 * set in order to enable memory self-refresh and fbc:
5387 * The bit21 and bit22 of 0x42000
5388 * The bit21 and bit22 of 0x42004
5389 * The bit5 and bit7 of 0x42020
5390 * The bit14 of 0x70180
5391 * The bit14 of 0x71180
5393 * WaFbcAsynchFlipDisableFbcQueue:snb
5395 I915_WRITE(ILK_DISPLAY_CHICKEN1
,
5396 I915_READ(ILK_DISPLAY_CHICKEN1
) |
5397 ILK_FBCQ_DIS
| ILK_PABSTRETCH_DIS
);
5398 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
5399 I915_READ(ILK_DISPLAY_CHICKEN2
) |
5400 ILK_DPARB_GATE
| ILK_VSDPFD_FULL
);
5401 I915_WRITE(ILK_DSPCLK_GATE_D
,
5402 I915_READ(ILK_DSPCLK_GATE_D
) |
5403 ILK_DPARBUNIT_CLOCK_GATE_ENABLE
|
5404 ILK_DPFDUNIT_CLOCK_GATE_ENABLE
);
5406 g4x_disable_trickle_feed(dev
);
5408 cpt_init_clock_gating(dev
);
5410 gen6_check_mch_setup(dev
);
5413 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private
*dev_priv
)
5415 uint32_t reg
= I915_READ(GEN7_FF_THREAD_MODE
);
5418 * WaVSThreadDispatchOverride:ivb,vlv
5420 * This actually overrides the dispatch
5421 * mode for all thread types.
5423 reg
&= ~GEN7_FF_SCHED_MASK
;
5424 reg
|= GEN7_FF_TS_SCHED_HW
;
5425 reg
|= GEN7_FF_VS_SCHED_HW
;
5426 reg
|= GEN7_FF_DS_SCHED_HW
;
5428 I915_WRITE(GEN7_FF_THREAD_MODE
, reg
);
5431 static void lpt_init_clock_gating(struct drm_device
*dev
)
5433 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5436 * TODO: this bit should only be enabled when really needed, then
5437 * disabled when not needed anymore in order to save power.
5439 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
)
5440 I915_WRITE(SOUTH_DSPCLK_GATE_D
,
5441 I915_READ(SOUTH_DSPCLK_GATE_D
) |
5442 PCH_LP_PARTITION_LEVEL_DISABLE
);
5444 /* WADPOClockGatingDisable:hsw */
5445 I915_WRITE(_TRANSA_CHICKEN1
,
5446 I915_READ(_TRANSA_CHICKEN1
) |
5447 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE
);
5450 static void lpt_suspend_hw(struct drm_device
*dev
)
5452 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5454 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
5455 uint32_t val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
5457 val
&= ~PCH_LP_PARTITION_LEVEL_DISABLE
;
5458 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
5462 static void gen8_init_clock_gating(struct drm_device
*dev
)
5464 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5467 I915_WRITE(WM3_LP_ILK
, 0);
5468 I915_WRITE(WM2_LP_ILK
, 0);
5469 I915_WRITE(WM1_LP_ILK
, 0);
5471 /* FIXME(BDW): Check all the w/a, some might only apply to
5472 * pre-production hw. */
5474 /* WaDisablePartialInstShootdown:bdw */
5475 I915_WRITE(GEN8_ROW_CHICKEN
,
5476 _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE
));
5478 /* WaDisableThreadStallDopClockGating:bdw */
5479 /* FIXME: Unclear whether we really need this on production bdw. */
5480 I915_WRITE(GEN8_ROW_CHICKEN
,
5481 _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE
));
5484 * This GEN8_CENTROID_PIXEL_OPT_DIS W/A is only needed for
5485 * pre-production hardware
5487 I915_WRITE(HALF_SLICE_CHICKEN3
,
5488 _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS
));
5489 I915_WRITE(HALF_SLICE_CHICKEN3
,
5490 _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS
));
5491 I915_WRITE(GAMTARBMODE
, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE
));
5493 I915_WRITE(_3D_CHICKEN3
,
5494 _MASKED_BIT_ENABLE(_3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2)));
5496 I915_WRITE(COMMON_SLICE_CHICKEN2
,
5497 _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE
));
5499 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1
,
5500 _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE
));
5502 /* WaDisableDopClockGating:bdw May not be needed for production */
5503 I915_WRITE(GEN7_ROW_CHICKEN2
,
5504 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
5506 /* WaSwitchSolVfFArbitrationPriority:bdw */
5507 I915_WRITE(GAM_ECOCHK
, I915_READ(GAM_ECOCHK
) | HSW_ECOCHK_ARB_PRIO_SOL
);
5509 /* WaPsrDPAMaskVBlankInSRD:bdw */
5510 I915_WRITE(CHICKEN_PAR1_1
,
5511 I915_READ(CHICKEN_PAR1_1
) | DPA_MASK_VBLANK_SRD
);
5513 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
5514 for_each_pipe(pipe
) {
5515 I915_WRITE(CHICKEN_PIPESL_1(pipe
),
5516 I915_READ(CHICKEN_PIPESL_1(pipe
)) |
5517 BDW_DPRS_MASK_VBLANK_SRD
);
5520 /* Use Force Non-Coherent whenever executing a 3D context. This is a
5521 * workaround for for a possible hang in the unlikely event a TLB
5522 * invalidation occurs during a PSD flush.
5524 I915_WRITE(HDC_CHICKEN0
,
5525 I915_READ(HDC_CHICKEN0
) |
5526 _MASKED_BIT_ENABLE(HDC_FORCE_NON_COHERENT
));
5528 /* WaVSRefCountFullforceMissDisable:bdw */
5529 /* WaDSRefCountFullforceMissDisable:bdw */
5530 I915_WRITE(GEN7_FF_THREAD_MODE
,
5531 I915_READ(GEN7_FF_THREAD_MODE
) &
5532 ~(GEN8_FF_DS_REF_CNT_FFME
| GEN7_FF_VS_REF_CNT_FFME
));
5535 * BSpec recommends 8x4 when MSAA is used,
5536 * however in practice 16x4 seems fastest.
5538 * Note that PS/WM thread counts depend on the WIZ hashing
5539 * disable bit, which we don't touch here, but it's good
5540 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5542 I915_WRITE(GEN7_GT_MODE
,
5543 GEN6_WIZ_HASHING_MASK
| GEN6_WIZ_HASHING_16x4
);
5545 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL
,
5546 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE
));
5548 /* WaDisableSDEUnitClockGating:bdw */
5549 I915_WRITE(GEN8_UCGCTL6
, I915_READ(GEN8_UCGCTL6
) |
5550 GEN8_SDEUNIT_CLOCK_GATE_DISABLE
);
5552 /* Wa4x4STCOptimizationDisable:bdw */
5553 I915_WRITE(CACHE_MODE_1
,
5554 _MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE
));
5557 static void haswell_init_clock_gating(struct drm_device
*dev
)
5559 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5561 ilk_init_lp_watermarks(dev
);
5563 /* L3 caching of data atomics doesn't work -- disable it. */
5564 I915_WRITE(HSW_SCRATCH1
, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE
);
5565 I915_WRITE(HSW_ROW_CHICKEN3
,
5566 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE
));
5568 /* This is required by WaCatErrorRejectionIssue:hsw */
5569 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
5570 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
5571 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
5573 /* WaVSRefCountFullforceMissDisable:hsw */
5574 I915_WRITE(GEN7_FF_THREAD_MODE
,
5575 I915_READ(GEN7_FF_THREAD_MODE
) & ~GEN7_FF_VS_REF_CNT_FFME
);
5577 /* WaDisable_RenderCache_OperationalFlush:hsw */
5578 I915_WRITE(CACHE_MODE_0_GEN7
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
5580 /* enable HiZ Raw Stall Optimization */
5581 I915_WRITE(CACHE_MODE_0_GEN7
,
5582 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE
));
5584 /* WaDisable4x2SubspanOptimization:hsw */
5585 I915_WRITE(CACHE_MODE_1
,
5586 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
));
5589 * BSpec recommends 8x4 when MSAA is used,
5590 * however in practice 16x4 seems fastest.
5592 * Note that PS/WM thread counts depend on the WIZ hashing
5593 * disable bit, which we don't touch here, but it's good
5594 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5596 I915_WRITE(GEN7_GT_MODE
,
5597 GEN6_WIZ_HASHING_MASK
| GEN6_WIZ_HASHING_16x4
);
5599 /* WaSwitchSolVfFArbitrationPriority:hsw */
5600 I915_WRITE(GAM_ECOCHK
, I915_READ(GAM_ECOCHK
) | HSW_ECOCHK_ARB_PRIO_SOL
);
5602 /* WaRsPkgCStateDisplayPMReq:hsw */
5603 I915_WRITE(CHICKEN_PAR1_1
,
5604 I915_READ(CHICKEN_PAR1_1
) | FORCE_ARB_IDLE_PLANES
);
5606 lpt_init_clock_gating(dev
);
5609 static void ivybridge_init_clock_gating(struct drm_device
*dev
)
5611 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5614 ilk_init_lp_watermarks(dev
);
5616 I915_WRITE(ILK_DSPCLK_GATE_D
, ILK_VRHUNIT_CLOCK_GATE_DISABLE
);
5618 /* WaDisableEarlyCull:ivb */
5619 I915_WRITE(_3D_CHICKEN3
,
5620 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL
));
5622 /* WaDisableBackToBackFlipFix:ivb */
5623 I915_WRITE(IVB_CHICKEN3
,
5624 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE
|
5625 CHICKEN3_DGMG_DONE_FIX_DISABLE
);
5627 /* WaDisablePSDDualDispatchEnable:ivb */
5628 if (IS_IVB_GT1(dev
))
5629 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1
,
5630 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE
));
5632 /* WaDisable_RenderCache_OperationalFlush:ivb */
5633 I915_WRITE(CACHE_MODE_0_GEN7
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
5635 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
5636 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1
,
5637 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC
);
5639 /* WaApplyL3ControlAndL3ChickenMode:ivb */
5640 I915_WRITE(GEN7_L3CNTLREG1
,
5641 GEN7_WA_FOR_GEN7_L3_CONTROL
);
5642 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER
,
5643 GEN7_WA_L3_CHICKEN_MODE
);
5644 if (IS_IVB_GT1(dev
))
5645 I915_WRITE(GEN7_ROW_CHICKEN2
,
5646 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
5648 /* must write both registers */
5649 I915_WRITE(GEN7_ROW_CHICKEN2
,
5650 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
5651 I915_WRITE(GEN7_ROW_CHICKEN2_GT2
,
5652 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
5655 /* WaForceL3Serialization:ivb */
5656 I915_WRITE(GEN7_L3SQCREG4
, I915_READ(GEN7_L3SQCREG4
) &
5657 ~L3SQ_URB_READ_CAM_MATCH_DISABLE
);
5660 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5661 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
5663 I915_WRITE(GEN6_UCGCTL2
,
5664 GEN6_RCZUNIT_CLOCK_GATE_DISABLE
);
5666 /* This is required by WaCatErrorRejectionIssue:ivb */
5667 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
5668 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
5669 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
5671 g4x_disable_trickle_feed(dev
);
5673 gen7_setup_fixed_func_scheduler(dev_priv
);
5675 if (0) { /* causes HiZ corruption on ivb:gt1 */
5676 /* enable HiZ Raw Stall Optimization */
5677 I915_WRITE(CACHE_MODE_0_GEN7
,
5678 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE
));
5681 /* WaDisable4x2SubspanOptimization:ivb */
5682 I915_WRITE(CACHE_MODE_1
,
5683 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
));
5686 * BSpec recommends 8x4 when MSAA is used,
5687 * however in practice 16x4 seems fastest.
5689 * Note that PS/WM thread counts depend on the WIZ hashing
5690 * disable bit, which we don't touch here, but it's good
5691 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5693 I915_WRITE(GEN7_GT_MODE
,
5694 GEN6_WIZ_HASHING_MASK
| GEN6_WIZ_HASHING_16x4
);
5696 snpcr
= I915_READ(GEN6_MBCUNIT_SNPCR
);
5697 snpcr
&= ~GEN6_MBC_SNPCR_MASK
;
5698 snpcr
|= GEN6_MBC_SNPCR_MED
;
5699 I915_WRITE(GEN6_MBCUNIT_SNPCR
, snpcr
);
5701 if (!HAS_PCH_NOP(dev
))
5702 cpt_init_clock_gating(dev
);
5704 gen6_check_mch_setup(dev
);
5707 static void valleyview_init_clock_gating(struct drm_device
*dev
)
5709 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5712 mutex_lock(&dev_priv
->rps
.hw_lock
);
5713 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
5714 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5715 switch ((val
>> 6) & 3) {
5718 dev_priv
->mem_freq
= 800;
5721 dev_priv
->mem_freq
= 1066;
5724 dev_priv
->mem_freq
= 1333;
5727 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv
->mem_freq
);
5729 I915_WRITE(DSPCLK_GATE_D
, VRHUNIT_CLOCK_GATE_DISABLE
);
5731 /* WaDisableEarlyCull:vlv */
5732 I915_WRITE(_3D_CHICKEN3
,
5733 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL
));
5735 /* WaDisableBackToBackFlipFix:vlv */
5736 I915_WRITE(IVB_CHICKEN3
,
5737 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE
|
5738 CHICKEN3_DGMG_DONE_FIX_DISABLE
);
5740 /* WaPsdDispatchEnable:vlv */
5741 /* WaDisablePSDDualDispatchEnable:vlv */
5742 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1
,
5743 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP
|
5744 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE
));
5746 /* WaDisable_RenderCache_OperationalFlush:vlv */
5747 I915_WRITE(CACHE_MODE_0_GEN7
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
5749 /* WaForceL3Serialization:vlv */
5750 I915_WRITE(GEN7_L3SQCREG4
, I915_READ(GEN7_L3SQCREG4
) &
5751 ~L3SQ_URB_READ_CAM_MATCH_DISABLE
);
5753 /* WaDisableDopClockGating:vlv */
5754 I915_WRITE(GEN7_ROW_CHICKEN2
,
5755 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
5757 /* This is required by WaCatErrorRejectionIssue:vlv */
5758 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
5759 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
5760 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
5762 gen7_setup_fixed_func_scheduler(dev_priv
);
5765 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5766 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
5768 I915_WRITE(GEN6_UCGCTL2
,
5769 GEN6_RCZUNIT_CLOCK_GATE_DISABLE
);
5771 /* WaDisableL3Bank2xClockGate:vlv
5772 * Disabling L3 clock gating- MMIO 940c[25] = 1
5773 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
5774 I915_WRITE(GEN7_UCGCTL4
,
5775 I915_READ(GEN7_UCGCTL4
) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE
);
5777 I915_WRITE(MI_ARB_VLV
, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
);
5780 * BSpec says this must be set, even though
5781 * WaDisable4x2SubspanOptimization isn't listed for VLV.
5783 I915_WRITE(CACHE_MODE_1
,
5784 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
));
5787 * WaIncreaseL3CreditsForVLVB0:vlv
5788 * This is the hardware default actually.
5790 I915_WRITE(GEN7_L3SQCREG1
, VLV_B0_WA_L3SQCREG1_VALUE
);
5793 * WaDisableVLVClockGating_VBIIssue:vlv
5794 * Disable clock gating on th GCFG unit to prevent a delay
5795 * in the reporting of vblank events.
5797 I915_WRITE(VLV_GUNIT_CLOCK_GATE
, GCFG_DIS
);
5800 static void cherryview_init_clock_gating(struct drm_device
*dev
)
5802 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5805 mutex_lock(&dev_priv
->rps
.hw_lock
);
5806 val
= vlv_punit_read(dev_priv
, CCK_FUSE_REG
);
5807 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5808 switch ((val
>> 2) & 0x7) {
5811 dev_priv
->rps
.cz_freq
= CHV_CZ_CLOCK_FREQ_MODE_200
;
5812 dev_priv
->mem_freq
= 1600;
5815 dev_priv
->rps
.cz_freq
= CHV_CZ_CLOCK_FREQ_MODE_267
;
5816 dev_priv
->mem_freq
= 1600;
5819 dev_priv
->rps
.cz_freq
= CHV_CZ_CLOCK_FREQ_MODE_333
;
5820 dev_priv
->mem_freq
= 2000;
5823 dev_priv
->rps
.cz_freq
= CHV_CZ_CLOCK_FREQ_MODE_320
;
5824 dev_priv
->mem_freq
= 1600;
5827 dev_priv
->rps
.cz_freq
= CHV_CZ_CLOCK_FREQ_MODE_400
;
5828 dev_priv
->mem_freq
= 1600;
5831 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv
->mem_freq
);
5833 I915_WRITE(DSPCLK_GATE_D
, VRHUNIT_CLOCK_GATE_DISABLE
);
5835 I915_WRITE(MI_ARB_VLV
, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
);
5837 /* WaDisablePartialInstShootdown:chv */
5838 I915_WRITE(GEN8_ROW_CHICKEN
,
5839 _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE
));
5841 /* WaDisableThreadStallDopClockGating:chv */
5842 I915_WRITE(GEN8_ROW_CHICKEN
,
5843 _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE
));
5845 /* WaVSRefCountFullforceMissDisable:chv */
5846 /* WaDSRefCountFullforceMissDisable:chv */
5847 I915_WRITE(GEN7_FF_THREAD_MODE
,
5848 I915_READ(GEN7_FF_THREAD_MODE
) &
5849 ~(GEN8_FF_DS_REF_CNT_FFME
| GEN7_FF_VS_REF_CNT_FFME
));
5851 /* WaDisableSemaphoreAndSyncFlipWait:chv */
5852 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL
,
5853 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE
));
5855 /* WaDisableCSUnitClockGating:chv */
5856 I915_WRITE(GEN6_UCGCTL1
, I915_READ(GEN6_UCGCTL1
) |
5857 GEN6_CSUNIT_CLOCK_GATE_DISABLE
);
5859 /* WaDisableSDEUnitClockGating:chv */
5860 I915_WRITE(GEN8_UCGCTL6
, I915_READ(GEN8_UCGCTL6
) |
5861 GEN8_SDEUNIT_CLOCK_GATE_DISABLE
);
5863 /* WaDisableSamplerPowerBypass:chv (pre-production hw) */
5864 I915_WRITE(HALF_SLICE_CHICKEN3
,
5865 _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS
));
5867 /* WaDisableGunitClockGating:chv (pre-production hw) */
5868 I915_WRITE(VLV_GUNIT_CLOCK_GATE
, I915_READ(VLV_GUNIT_CLOCK_GATE
) |
5871 /* WaDisableFfDopClockGating:chv (pre-production hw) */
5872 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL
,
5873 _MASKED_BIT_ENABLE(GEN8_FF_DOP_CLOCK_GATE_DISABLE
));
5875 /* WaDisableDopClockGating:chv (pre-production hw) */
5876 I915_WRITE(GEN7_ROW_CHICKEN2
,
5877 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
5878 I915_WRITE(GEN6_UCGCTL1
, I915_READ(GEN6_UCGCTL1
) |
5879 GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE
);
5882 static void g4x_init_clock_gating(struct drm_device
*dev
)
5884 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5885 uint32_t dspclk_gate
;
5887 I915_WRITE(RENCLK_GATE_D1
, 0);
5888 I915_WRITE(RENCLK_GATE_D2
, VF_UNIT_CLOCK_GATE_DISABLE
|
5889 GS_UNIT_CLOCK_GATE_DISABLE
|
5890 CL_UNIT_CLOCK_GATE_DISABLE
);
5891 I915_WRITE(RAMCLK_GATE_D
, 0);
5892 dspclk_gate
= VRHUNIT_CLOCK_GATE_DISABLE
|
5893 OVRUNIT_CLOCK_GATE_DISABLE
|
5894 OVCUNIT_CLOCK_GATE_DISABLE
;
5896 dspclk_gate
|= DSSUNIT_CLOCK_GATE_DISABLE
;
5897 I915_WRITE(DSPCLK_GATE_D
, dspclk_gate
);
5899 /* WaDisableRenderCachePipelinedFlush */
5900 I915_WRITE(CACHE_MODE_0
,
5901 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE
));
5903 /* WaDisable_RenderCache_OperationalFlush:g4x */
5904 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
5906 g4x_disable_trickle_feed(dev
);
5909 static void crestline_init_clock_gating(struct drm_device
*dev
)
5911 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5913 I915_WRITE(RENCLK_GATE_D1
, I965_RCC_CLOCK_GATE_DISABLE
);
5914 I915_WRITE(RENCLK_GATE_D2
, 0);
5915 I915_WRITE(DSPCLK_GATE_D
, 0);
5916 I915_WRITE(RAMCLK_GATE_D
, 0);
5917 I915_WRITE16(DEUC
, 0);
5918 I915_WRITE(MI_ARB_STATE
,
5919 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
));
5921 /* WaDisable_RenderCache_OperationalFlush:gen4 */
5922 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
5925 static void broadwater_init_clock_gating(struct drm_device
*dev
)
5927 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5929 I915_WRITE(RENCLK_GATE_D1
, I965_RCZ_CLOCK_GATE_DISABLE
|
5930 I965_RCC_CLOCK_GATE_DISABLE
|
5931 I965_RCPB_CLOCK_GATE_DISABLE
|
5932 I965_ISC_CLOCK_GATE_DISABLE
|
5933 I965_FBC_CLOCK_GATE_DISABLE
);
5934 I915_WRITE(RENCLK_GATE_D2
, 0);
5935 I915_WRITE(MI_ARB_STATE
,
5936 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
));
5938 /* WaDisable_RenderCache_OperationalFlush:gen4 */
5939 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
5942 static void gen3_init_clock_gating(struct drm_device
*dev
)
5944 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5945 u32 dstate
= I915_READ(D_STATE
);
5947 dstate
|= DSTATE_PLL_D3_OFF
| DSTATE_GFX_CLOCK_GATING
|
5948 DSTATE_DOT_CLOCK_GATING
;
5949 I915_WRITE(D_STATE
, dstate
);
5951 if (IS_PINEVIEW(dev
))
5952 I915_WRITE(ECOSKPD
, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY
));
5954 /* IIR "flip pending" means done if this bit is set */
5955 I915_WRITE(ECOSKPD
, _MASKED_BIT_DISABLE(ECO_FLIP_DONE
));
5957 /* interrupts should cause a wake up from C3 */
5958 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN
));
5960 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
5961 I915_WRITE(MI_ARB_STATE
, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE
));
5964 static void i85x_init_clock_gating(struct drm_device
*dev
)
5966 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5968 I915_WRITE(RENCLK_GATE_D1
, SV_CLOCK_GATE_DISABLE
);
5970 /* interrupts should cause a wake up from C3 */
5971 I915_WRITE(MI_STATE
, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN
) |
5972 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE
));
5975 static void i830_init_clock_gating(struct drm_device
*dev
)
5977 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5979 I915_WRITE(DSPCLK_GATE_D
, OVRUNIT_CLOCK_GATE_DISABLE
);
5982 void intel_init_clock_gating(struct drm_device
*dev
)
5984 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5986 dev_priv
->display
.init_clock_gating(dev
);
5989 void intel_suspend_hw(struct drm_device
*dev
)
5991 if (HAS_PCH_LPT(dev
))
5992 lpt_suspend_hw(dev
);
5995 #define for_each_power_well(i, power_well, domain_mask, power_domains) \
5997 i < (power_domains)->power_well_count && \
5998 ((power_well) = &(power_domains)->power_wells[i]); \
6000 if ((power_well)->domains & (domain_mask))
6002 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
6003 for (i = (power_domains)->power_well_count - 1; \
6004 i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
6006 if ((power_well)->domains & (domain_mask))
6009 * We should only use the power well if we explicitly asked the hardware to
6010 * enable it, so check if it's enabled and also check if we've requested it to
6013 static bool hsw_power_well_enabled(struct drm_i915_private
*dev_priv
,
6014 struct i915_power_well
*power_well
)
6016 return I915_READ(HSW_PWR_WELL_DRIVER
) ==
6017 (HSW_PWR_WELL_ENABLE_REQUEST
| HSW_PWR_WELL_STATE_ENABLED
);
6020 bool intel_display_power_enabled_unlocked(struct drm_i915_private
*dev_priv
,
6021 enum intel_display_power_domain domain
)
6023 struct i915_power_domains
*power_domains
;
6024 struct i915_power_well
*power_well
;
6028 if (dev_priv
->pm
.suspended
)
6031 power_domains
= &dev_priv
->power_domains
;
6035 for_each_power_well_rev(i
, power_well
, BIT(domain
), power_domains
) {
6036 if (power_well
->always_on
)
6039 if (!power_well
->hw_enabled
) {
6048 bool intel_display_power_enabled(struct drm_i915_private
*dev_priv
,
6049 enum intel_display_power_domain domain
)
6051 struct i915_power_domains
*power_domains
;
6054 power_domains
= &dev_priv
->power_domains
;
6056 mutex_lock(&power_domains
->lock
);
6057 ret
= intel_display_power_enabled_unlocked(dev_priv
, domain
);
6058 mutex_unlock(&power_domains
->lock
);
6064 * Starting with Haswell, we have a "Power Down Well" that can be turned off
6065 * when not needed anymore. We have 4 registers that can request the power well
6066 * to be enabled, and it will only be disabled if none of the registers is
6067 * requesting it to be enabled.
6069 static void hsw_power_well_post_enable(struct drm_i915_private
*dev_priv
)
6071 struct drm_device
*dev
= dev_priv
->dev
;
6074 * After we re-enable the power well, if we touch VGA register 0x3d5
6075 * we'll get unclaimed register interrupts. This stops after we write
6076 * anything to the VGA MSR register. The vgacon module uses this
6077 * register all the time, so if we unbind our driver and, as a
6078 * consequence, bind vgacon, we'll get stuck in an infinite loop at
6079 * console_unlock(). So make here we touch the VGA MSR register, making
6080 * sure vgacon can keep working normally without triggering interrupts
6081 * and error messages.
6083 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
6084 outb(inb(VGA_MSR_READ
), VGA_MSR_WRITE
);
6085 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
6087 if (IS_BROADWELL(dev
))
6088 gen8_irq_power_well_post_enable(dev_priv
);
6091 static void hsw_set_power_well(struct drm_i915_private
*dev_priv
,
6092 struct i915_power_well
*power_well
, bool enable
)
6094 bool is_enabled
, enable_requested
;
6097 tmp
= I915_READ(HSW_PWR_WELL_DRIVER
);
6098 is_enabled
= tmp
& HSW_PWR_WELL_STATE_ENABLED
;
6099 enable_requested
= tmp
& HSW_PWR_WELL_ENABLE_REQUEST
;
6102 if (!enable_requested
)
6103 I915_WRITE(HSW_PWR_WELL_DRIVER
,
6104 HSW_PWR_WELL_ENABLE_REQUEST
);
6107 DRM_DEBUG_KMS("Enabling power well\n");
6108 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER
) &
6109 HSW_PWR_WELL_STATE_ENABLED
), 20))
6110 DRM_ERROR("Timeout enabling power well\n");
6113 hsw_power_well_post_enable(dev_priv
);
6115 if (enable_requested
) {
6116 I915_WRITE(HSW_PWR_WELL_DRIVER
, 0);
6117 POSTING_READ(HSW_PWR_WELL_DRIVER
);
6118 DRM_DEBUG_KMS("Requesting to disable the power well\n");
6123 static void hsw_power_well_sync_hw(struct drm_i915_private
*dev_priv
,
6124 struct i915_power_well
*power_well
)
6126 hsw_set_power_well(dev_priv
, power_well
, power_well
->count
> 0);
6129 * We're taking over the BIOS, so clear any requests made by it since
6130 * the driver is in charge now.
6132 if (I915_READ(HSW_PWR_WELL_BIOS
) & HSW_PWR_WELL_ENABLE_REQUEST
)
6133 I915_WRITE(HSW_PWR_WELL_BIOS
, 0);
6136 static void hsw_power_well_enable(struct drm_i915_private
*dev_priv
,
6137 struct i915_power_well
*power_well
)
6139 hsw_set_power_well(dev_priv
, power_well
, true);
6142 static void hsw_power_well_disable(struct drm_i915_private
*dev_priv
,
6143 struct i915_power_well
*power_well
)
6145 hsw_set_power_well(dev_priv
, power_well
, false);
6148 static void i9xx_always_on_power_well_noop(struct drm_i915_private
*dev_priv
,
6149 struct i915_power_well
*power_well
)
6153 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private
*dev_priv
,
6154 struct i915_power_well
*power_well
)
6159 static void vlv_set_power_well(struct drm_i915_private
*dev_priv
,
6160 struct i915_power_well
*power_well
, bool enable
)
6162 enum punit_power_well power_well_id
= power_well
->data
;
6167 mask
= PUNIT_PWRGT_MASK(power_well_id
);
6168 state
= enable
? PUNIT_PWRGT_PWR_ON(power_well_id
) :
6169 PUNIT_PWRGT_PWR_GATE(power_well_id
);
6171 mutex_lock(&dev_priv
->rps
.hw_lock
);
6174 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
6179 ctrl
= vlv_punit_read(dev_priv
, PUNIT_REG_PWRGT_CTRL
);
6182 vlv_punit_write(dev_priv
, PUNIT_REG_PWRGT_CTRL
, ctrl
);
6184 if (wait_for(COND
, 100))
6185 DRM_ERROR("timout setting power well state %08x (%08x)\n",
6187 vlv_punit_read(dev_priv
, PUNIT_REG_PWRGT_CTRL
));
6192 mutex_unlock(&dev_priv
->rps
.hw_lock
);
6195 static void vlv_power_well_sync_hw(struct drm_i915_private
*dev_priv
,
6196 struct i915_power_well
*power_well
)
6198 vlv_set_power_well(dev_priv
, power_well
, power_well
->count
> 0);
6201 static void vlv_power_well_enable(struct drm_i915_private
*dev_priv
,
6202 struct i915_power_well
*power_well
)
6204 vlv_set_power_well(dev_priv
, power_well
, true);
6207 static void vlv_power_well_disable(struct drm_i915_private
*dev_priv
,
6208 struct i915_power_well
*power_well
)
6210 vlv_set_power_well(dev_priv
, power_well
, false);
6213 static bool vlv_power_well_enabled(struct drm_i915_private
*dev_priv
,
6214 struct i915_power_well
*power_well
)
6216 int power_well_id
= power_well
->data
;
6217 bool enabled
= false;
6222 mask
= PUNIT_PWRGT_MASK(power_well_id
);
6223 ctrl
= PUNIT_PWRGT_PWR_ON(power_well_id
);
6225 mutex_lock(&dev_priv
->rps
.hw_lock
);
6227 state
= vlv_punit_read(dev_priv
, PUNIT_REG_PWRGT_STATUS
) & mask
;
6229 * We only ever set the power-on and power-gate states, anything
6230 * else is unexpected.
6232 WARN_ON(state
!= PUNIT_PWRGT_PWR_ON(power_well_id
) &&
6233 state
!= PUNIT_PWRGT_PWR_GATE(power_well_id
));
6238 * A transient state at this point would mean some unexpected party
6239 * is poking at the power controls too.
6241 ctrl
= vlv_punit_read(dev_priv
, PUNIT_REG_PWRGT_CTRL
) & mask
;
6242 WARN_ON(ctrl
!= state
);
6244 mutex_unlock(&dev_priv
->rps
.hw_lock
);
6249 static void vlv_display_power_well_enable(struct drm_i915_private
*dev_priv
,
6250 struct i915_power_well
*power_well
)
6252 WARN_ON_ONCE(power_well
->data
!= PUNIT_POWER_WELL_DISP2D
);
6254 vlv_set_power_well(dev_priv
, power_well
, true);
6256 spin_lock_irq(&dev_priv
->irq_lock
);
6257 valleyview_enable_display_irqs(dev_priv
);
6258 spin_unlock_irq(&dev_priv
->irq_lock
);
6261 * During driver initialization/resume we can avoid restoring the
6262 * part of the HW/SW state that will be inited anyway explicitly.
6264 if (dev_priv
->power_domains
.initializing
)
6267 intel_hpd_init(dev_priv
->dev
);
6269 i915_redisable_vga_power_on(dev_priv
->dev
);
6272 static void vlv_display_power_well_disable(struct drm_i915_private
*dev_priv
,
6273 struct i915_power_well
*power_well
)
6275 WARN_ON_ONCE(power_well
->data
!= PUNIT_POWER_WELL_DISP2D
);
6277 spin_lock_irq(&dev_priv
->irq_lock
);
6278 valleyview_disable_display_irqs(dev_priv
);
6279 spin_unlock_irq(&dev_priv
->irq_lock
);
6281 vlv_set_power_well(dev_priv
, power_well
, false);
6284 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private
*dev_priv
,
6285 struct i915_power_well
*power_well
)
6287 WARN_ON_ONCE(power_well
->data
!= PUNIT_POWER_WELL_DPIO_CMN_BC
);
6290 * Enable the CRI clock source so we can get at the
6291 * display and the reference clock for VGA
6292 * hotplug / manual detection.
6294 I915_WRITE(DPLL(PIPE_B
), I915_READ(DPLL(PIPE_B
)) |
6295 DPLL_REFA_CLK_ENABLE_VLV
| DPLL_INTEGRATED_CRI_CLK_VLV
);
6296 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
6298 vlv_set_power_well(dev_priv
, power_well
, true);
6301 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
6302 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
6303 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
6304 * b. The other bits such as sfr settings / modesel may all
6307 * This should only be done on init and resume from S3 with
6308 * both PLLs disabled, or we risk losing DPIO and PLL
6311 I915_WRITE(DPIO_CTL
, I915_READ(DPIO_CTL
) | DPIO_CMNRST
);
6314 static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private
*dev_priv
,
6315 struct i915_power_well
*power_well
)
6317 struct drm_device
*dev
= dev_priv
->dev
;
6320 WARN_ON_ONCE(power_well
->data
!= PUNIT_POWER_WELL_DPIO_CMN_BC
);
6323 assert_pll_disabled(dev_priv
, pipe
);
6325 /* Assert common reset */
6326 I915_WRITE(DPIO_CTL
, I915_READ(DPIO_CTL
) & ~DPIO_CMNRST
);
6328 vlv_set_power_well(dev_priv
, power_well
, false);
6331 static void chv_dpio_cmn_power_well_enable(struct drm_i915_private
*dev_priv
,
6332 struct i915_power_well
*power_well
)
6336 WARN_ON_ONCE(power_well
->data
!= PUNIT_POWER_WELL_DPIO_CMN_BC
&&
6337 power_well
->data
!= PUNIT_POWER_WELL_DPIO_CMN_D
);
6340 * Enable the CRI clock source so we can get at the
6341 * display and the reference clock for VGA
6342 * hotplug / manual detection.
6344 if (power_well
->data
== PUNIT_POWER_WELL_DPIO_CMN_BC
) {
6346 I915_WRITE(DPLL(PIPE_B
), I915_READ(DPLL(PIPE_B
)) |
6347 DPLL_REFA_CLK_ENABLE_VLV
);
6348 I915_WRITE(DPLL(PIPE_B
), I915_READ(DPLL(PIPE_B
)) |
6349 DPLL_REFA_CLK_ENABLE_VLV
| DPLL_INTEGRATED_CRI_CLK_VLV
);
6352 I915_WRITE(DPLL(PIPE_C
), I915_READ(DPLL(PIPE_C
)) |
6353 DPLL_REFA_CLK_ENABLE_VLV
| DPLL_INTEGRATED_CRI_CLK_VLV
);
6355 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
6356 vlv_set_power_well(dev_priv
, power_well
, true);
6358 /* Poll for phypwrgood signal */
6359 if (wait_for(I915_READ(DISPLAY_PHY_STATUS
) & PHY_POWERGOOD(phy
), 1))
6360 DRM_ERROR("Display PHY %d is not power up\n", phy
);
6362 I915_WRITE(DISPLAY_PHY_CONTROL
, I915_READ(DISPLAY_PHY_CONTROL
) |
6363 PHY_COM_LANE_RESET_DEASSERT(phy
));
6366 static void chv_dpio_cmn_power_well_disable(struct drm_i915_private
*dev_priv
,
6367 struct i915_power_well
*power_well
)
6371 WARN_ON_ONCE(power_well
->data
!= PUNIT_POWER_WELL_DPIO_CMN_BC
&&
6372 power_well
->data
!= PUNIT_POWER_WELL_DPIO_CMN_D
);
6374 if (power_well
->data
== PUNIT_POWER_WELL_DPIO_CMN_BC
) {
6376 assert_pll_disabled(dev_priv
, PIPE_A
);
6377 assert_pll_disabled(dev_priv
, PIPE_B
);
6380 assert_pll_disabled(dev_priv
, PIPE_C
);
6383 I915_WRITE(DISPLAY_PHY_CONTROL
, I915_READ(DISPLAY_PHY_CONTROL
) &
6384 ~PHY_COM_LANE_RESET_DEASSERT(phy
));
6386 vlv_set_power_well(dev_priv
, power_well
, false);
6389 static bool chv_pipe_power_well_enabled(struct drm_i915_private
*dev_priv
,
6390 struct i915_power_well
*power_well
)
6392 enum pipe pipe
= power_well
->data
;
6396 mutex_lock(&dev_priv
->rps
.hw_lock
);
6398 state
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) & DP_SSS_MASK(pipe
);
6400 * We only ever set the power-on and power-gate states, anything
6401 * else is unexpected.
6403 WARN_ON(state
!= DP_SSS_PWR_ON(pipe
) && state
!= DP_SSS_PWR_GATE(pipe
));
6404 enabled
= state
== DP_SSS_PWR_ON(pipe
);
6407 * A transient state at this point would mean some unexpected party
6408 * is poking at the power controls too.
6410 ctrl
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) & DP_SSC_MASK(pipe
);
6411 WARN_ON(ctrl
<< 16 != state
);
6413 mutex_unlock(&dev_priv
->rps
.hw_lock
);
6418 static void chv_set_pipe_power_well(struct drm_i915_private
*dev_priv
,
6419 struct i915_power_well
*power_well
,
6422 enum pipe pipe
= power_well
->data
;
6426 state
= enable
? DP_SSS_PWR_ON(pipe
) : DP_SSS_PWR_GATE(pipe
);
6428 mutex_lock(&dev_priv
->rps
.hw_lock
);
6431 ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state)
6436 ctrl
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
6437 ctrl
&= ~DP_SSC_MASK(pipe
);
6438 ctrl
|= enable
? DP_SSC_PWR_ON(pipe
) : DP_SSC_PWR_GATE(pipe
);
6439 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, ctrl
);
6441 if (wait_for(COND
, 100))
6442 DRM_ERROR("timout setting power well state %08x (%08x)\n",
6444 vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
));
6449 mutex_unlock(&dev_priv
->rps
.hw_lock
);
6452 static void chv_pipe_power_well_sync_hw(struct drm_i915_private
*dev_priv
,
6453 struct i915_power_well
*power_well
)
6455 chv_set_pipe_power_well(dev_priv
, power_well
, power_well
->count
> 0);
6458 static void chv_pipe_power_well_enable(struct drm_i915_private
*dev_priv
,
6459 struct i915_power_well
*power_well
)
6461 WARN_ON_ONCE(power_well
->data
!= PIPE_A
&&
6462 power_well
->data
!= PIPE_B
&&
6463 power_well
->data
!= PIPE_C
);
6465 chv_set_pipe_power_well(dev_priv
, power_well
, true);
6468 static void chv_pipe_power_well_disable(struct drm_i915_private
*dev_priv
,
6469 struct i915_power_well
*power_well
)
6471 WARN_ON_ONCE(power_well
->data
!= PIPE_A
&&
6472 power_well
->data
!= PIPE_B
&&
6473 power_well
->data
!= PIPE_C
);
6475 chv_set_pipe_power_well(dev_priv
, power_well
, false);
6478 static void check_power_well_state(struct drm_i915_private
*dev_priv
,
6479 struct i915_power_well
*power_well
)
6481 bool enabled
= power_well
->ops
->is_enabled(dev_priv
, power_well
);
6483 if (power_well
->always_on
|| !i915
.disable_power_well
) {
6490 if (enabled
!= (power_well
->count
> 0))
6496 WARN(1, "state mismatch for '%s' (always_on %d hw state %d use-count %d disable_power_well %d\n",
6497 power_well
->name
, power_well
->always_on
, enabled
,
6498 power_well
->count
, i915
.disable_power_well
);
6501 void intel_display_power_get(struct drm_i915_private
*dev_priv
,
6502 enum intel_display_power_domain domain
)
6504 struct i915_power_domains
*power_domains
;
6505 struct i915_power_well
*power_well
;
6508 intel_runtime_pm_get(dev_priv
);
6510 power_domains
= &dev_priv
->power_domains
;
6512 mutex_lock(&power_domains
->lock
);
6514 for_each_power_well(i
, power_well
, BIT(domain
), power_domains
) {
6515 if (!power_well
->count
++) {
6516 DRM_DEBUG_KMS("enabling %s\n", power_well
->name
);
6517 power_well
->ops
->enable(dev_priv
, power_well
);
6518 power_well
->hw_enabled
= true;
6521 check_power_well_state(dev_priv
, power_well
);
6524 power_domains
->domain_use_count
[domain
]++;
6526 mutex_unlock(&power_domains
->lock
);
6529 void intel_display_power_put(struct drm_i915_private
*dev_priv
,
6530 enum intel_display_power_domain domain
)
6532 struct i915_power_domains
*power_domains
;
6533 struct i915_power_well
*power_well
;
6536 power_domains
= &dev_priv
->power_domains
;
6538 mutex_lock(&power_domains
->lock
);
6540 WARN_ON(!power_domains
->domain_use_count
[domain
]);
6541 power_domains
->domain_use_count
[domain
]--;
6543 for_each_power_well_rev(i
, power_well
, BIT(domain
), power_domains
) {
6544 WARN_ON(!power_well
->count
);
6546 if (!--power_well
->count
&& i915
.disable_power_well
) {
6547 DRM_DEBUG_KMS("disabling %s\n", power_well
->name
);
6548 power_well
->hw_enabled
= false;
6549 power_well
->ops
->disable(dev_priv
, power_well
);
6552 check_power_well_state(dev_priv
, power_well
);
6555 mutex_unlock(&power_domains
->lock
);
6557 intel_runtime_pm_put(dev_priv
);
6560 static struct i915_power_domains
*hsw_pwr
;
6562 /* Display audio driver power well request */
6563 int i915_request_power_well(void)
6565 struct drm_i915_private
*dev_priv
;
6570 dev_priv
= container_of(hsw_pwr
, struct drm_i915_private
,
6572 intel_display_power_get(dev_priv
, POWER_DOMAIN_AUDIO
);
6575 EXPORT_SYMBOL_GPL(i915_request_power_well
);
6577 /* Display audio driver power well release */
6578 int i915_release_power_well(void)
6580 struct drm_i915_private
*dev_priv
;
6585 dev_priv
= container_of(hsw_pwr
, struct drm_i915_private
,
6587 intel_display_power_put(dev_priv
, POWER_DOMAIN_AUDIO
);
6590 EXPORT_SYMBOL_GPL(i915_release_power_well
);
6593 * Private interface for the audio driver to get CDCLK in kHz.
6595 * Caller must request power well using i915_request_power_well() prior to
6598 int i915_get_cdclk_freq(void)
6600 struct drm_i915_private
*dev_priv
;
6605 dev_priv
= container_of(hsw_pwr
, struct drm_i915_private
,
6608 return intel_ddi_get_cdclk_freq(dev_priv
);
6610 EXPORT_SYMBOL_GPL(i915_get_cdclk_freq
);
6613 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
6615 #define HSW_ALWAYS_ON_POWER_DOMAINS ( \
6616 BIT(POWER_DOMAIN_PIPE_A) | \
6617 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
6618 BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
6619 BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
6620 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6621 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6622 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6623 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6624 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
6625 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
6626 BIT(POWER_DOMAIN_PORT_CRT) | \
6627 BIT(POWER_DOMAIN_PLLS) | \
6628 BIT(POWER_DOMAIN_INIT))
6629 #define HSW_DISPLAY_POWER_DOMAINS ( \
6630 (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \
6631 BIT(POWER_DOMAIN_INIT))
6633 #define BDW_ALWAYS_ON_POWER_DOMAINS ( \
6634 HSW_ALWAYS_ON_POWER_DOMAINS | \
6635 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
6636 #define BDW_DISPLAY_POWER_DOMAINS ( \
6637 (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) | \
6638 BIT(POWER_DOMAIN_INIT))
6640 #define VLV_ALWAYS_ON_POWER_DOMAINS BIT(POWER_DOMAIN_INIT)
6641 #define VLV_DISPLAY_POWER_DOMAINS POWER_DOMAIN_MASK
6643 #define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \
6644 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6645 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6646 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6647 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6648 BIT(POWER_DOMAIN_PORT_CRT) | \
6649 BIT(POWER_DOMAIN_INIT))
6651 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \
6652 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6653 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6654 BIT(POWER_DOMAIN_INIT))
6656 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \
6657 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6658 BIT(POWER_DOMAIN_INIT))
6660 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \
6661 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6662 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6663 BIT(POWER_DOMAIN_INIT))
6665 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \
6666 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6667 BIT(POWER_DOMAIN_INIT))
6669 #define CHV_PIPE_A_POWER_DOMAINS ( \
6670 BIT(POWER_DOMAIN_PIPE_A) | \
6671 BIT(POWER_DOMAIN_INIT))
6673 #define CHV_PIPE_B_POWER_DOMAINS ( \
6674 BIT(POWER_DOMAIN_PIPE_B) | \
6675 BIT(POWER_DOMAIN_INIT))
6677 #define CHV_PIPE_C_POWER_DOMAINS ( \
6678 BIT(POWER_DOMAIN_PIPE_C) | \
6679 BIT(POWER_DOMAIN_INIT))
6681 #define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \
6682 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6683 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6684 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6685 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6686 BIT(POWER_DOMAIN_INIT))
6688 #define CHV_DPIO_CMN_D_POWER_DOMAINS ( \
6689 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
6690 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
6691 BIT(POWER_DOMAIN_INIT))
6693 #define CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS ( \
6694 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
6695 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
6696 BIT(POWER_DOMAIN_INIT))
6698 #define CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS ( \
6699 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
6700 BIT(POWER_DOMAIN_INIT))
6702 static const struct i915_power_well_ops i9xx_always_on_power_well_ops
= {
6703 .sync_hw
= i9xx_always_on_power_well_noop
,
6704 .enable
= i9xx_always_on_power_well_noop
,
6705 .disable
= i9xx_always_on_power_well_noop
,
6706 .is_enabled
= i9xx_always_on_power_well_enabled
,
6709 static const struct i915_power_well_ops chv_pipe_power_well_ops
= {
6710 .sync_hw
= chv_pipe_power_well_sync_hw
,
6711 .enable
= chv_pipe_power_well_enable
,
6712 .disable
= chv_pipe_power_well_disable
,
6713 .is_enabled
= chv_pipe_power_well_enabled
,
6716 static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops
= {
6717 .sync_hw
= vlv_power_well_sync_hw
,
6718 .enable
= chv_dpio_cmn_power_well_enable
,
6719 .disable
= chv_dpio_cmn_power_well_disable
,
6720 .is_enabled
= vlv_power_well_enabled
,
6723 static struct i915_power_well i9xx_always_on_power_well
[] = {
6725 .name
= "always-on",
6727 .domains
= POWER_DOMAIN_MASK
,
6728 .ops
= &i9xx_always_on_power_well_ops
,
6732 static const struct i915_power_well_ops hsw_power_well_ops
= {
6733 .sync_hw
= hsw_power_well_sync_hw
,
6734 .enable
= hsw_power_well_enable
,
6735 .disable
= hsw_power_well_disable
,
6736 .is_enabled
= hsw_power_well_enabled
,
6739 static struct i915_power_well hsw_power_wells
[] = {
6741 .name
= "always-on",
6743 .domains
= HSW_ALWAYS_ON_POWER_DOMAINS
,
6744 .ops
= &i9xx_always_on_power_well_ops
,
6748 .domains
= HSW_DISPLAY_POWER_DOMAINS
,
6749 .ops
= &hsw_power_well_ops
,
6753 static struct i915_power_well bdw_power_wells
[] = {
6755 .name
= "always-on",
6757 .domains
= BDW_ALWAYS_ON_POWER_DOMAINS
,
6758 .ops
= &i9xx_always_on_power_well_ops
,
6762 .domains
= BDW_DISPLAY_POWER_DOMAINS
,
6763 .ops
= &hsw_power_well_ops
,
6767 static const struct i915_power_well_ops vlv_display_power_well_ops
= {
6768 .sync_hw
= vlv_power_well_sync_hw
,
6769 .enable
= vlv_display_power_well_enable
,
6770 .disable
= vlv_display_power_well_disable
,
6771 .is_enabled
= vlv_power_well_enabled
,
6774 static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops
= {
6775 .sync_hw
= vlv_power_well_sync_hw
,
6776 .enable
= vlv_dpio_cmn_power_well_enable
,
6777 .disable
= vlv_dpio_cmn_power_well_disable
,
6778 .is_enabled
= vlv_power_well_enabled
,
6781 static const struct i915_power_well_ops vlv_dpio_power_well_ops
= {
6782 .sync_hw
= vlv_power_well_sync_hw
,
6783 .enable
= vlv_power_well_enable
,
6784 .disable
= vlv_power_well_disable
,
6785 .is_enabled
= vlv_power_well_enabled
,
6788 static struct i915_power_well vlv_power_wells
[] = {
6790 .name
= "always-on",
6792 .domains
= VLV_ALWAYS_ON_POWER_DOMAINS
,
6793 .ops
= &i9xx_always_on_power_well_ops
,
6797 .domains
= VLV_DISPLAY_POWER_DOMAINS
,
6798 .data
= PUNIT_POWER_WELL_DISP2D
,
6799 .ops
= &vlv_display_power_well_ops
,
6802 .name
= "dpio-tx-b-01",
6803 .domains
= VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS
|
6804 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS
|
6805 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS
|
6806 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS
,
6807 .ops
= &vlv_dpio_power_well_ops
,
6808 .data
= PUNIT_POWER_WELL_DPIO_TX_B_LANES_01
,
6811 .name
= "dpio-tx-b-23",
6812 .domains
= VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS
|
6813 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS
|
6814 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS
|
6815 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS
,
6816 .ops
= &vlv_dpio_power_well_ops
,
6817 .data
= PUNIT_POWER_WELL_DPIO_TX_B_LANES_23
,
6820 .name
= "dpio-tx-c-01",
6821 .domains
= VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS
|
6822 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS
|
6823 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS
|
6824 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS
,
6825 .ops
= &vlv_dpio_power_well_ops
,
6826 .data
= PUNIT_POWER_WELL_DPIO_TX_C_LANES_01
,
6829 .name
= "dpio-tx-c-23",
6830 .domains
= VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS
|
6831 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS
|
6832 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS
|
6833 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS
,
6834 .ops
= &vlv_dpio_power_well_ops
,
6835 .data
= PUNIT_POWER_WELL_DPIO_TX_C_LANES_23
,
6838 .name
= "dpio-common",
6839 .domains
= VLV_DPIO_CMN_BC_POWER_DOMAINS
,
6840 .data
= PUNIT_POWER_WELL_DPIO_CMN_BC
,
6841 .ops
= &vlv_dpio_cmn_power_well_ops
,
6845 static struct i915_power_well chv_power_wells
[] = {
6847 .name
= "always-on",
6849 .domains
= VLV_ALWAYS_ON_POWER_DOMAINS
,
6850 .ops
= &i9xx_always_on_power_well_ops
,
6855 .domains
= VLV_DISPLAY_POWER_DOMAINS
,
6856 .data
= PUNIT_POWER_WELL_DISP2D
,
6857 .ops
= &vlv_display_power_well_ops
,
6861 .domains
= CHV_PIPE_A_POWER_DOMAINS
,
6863 .ops
= &chv_pipe_power_well_ops
,
6867 .domains
= CHV_PIPE_B_POWER_DOMAINS
,
6869 .ops
= &chv_pipe_power_well_ops
,
6873 .domains
= CHV_PIPE_C_POWER_DOMAINS
,
6875 .ops
= &chv_pipe_power_well_ops
,
6879 .name
= "dpio-common-bc",
6881 * XXX: cmnreset for one PHY seems to disturb the other.
6882 * As a workaround keep both powered on at the same
6885 .domains
= CHV_DPIO_CMN_BC_POWER_DOMAINS
| CHV_DPIO_CMN_D_POWER_DOMAINS
,
6886 .data
= PUNIT_POWER_WELL_DPIO_CMN_BC
,
6887 .ops
= &chv_dpio_cmn_power_well_ops
,
6890 .name
= "dpio-common-d",
6892 * XXX: cmnreset for one PHY seems to disturb the other.
6893 * As a workaround keep both powered on at the same
6896 .domains
= CHV_DPIO_CMN_BC_POWER_DOMAINS
| CHV_DPIO_CMN_D_POWER_DOMAINS
,
6897 .data
= PUNIT_POWER_WELL_DPIO_CMN_D
,
6898 .ops
= &chv_dpio_cmn_power_well_ops
,
6902 .name
= "dpio-tx-b-01",
6903 .domains
= VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS
|
6904 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS
,
6905 .ops
= &vlv_dpio_power_well_ops
,
6906 .data
= PUNIT_POWER_WELL_DPIO_TX_B_LANES_01
,
6909 .name
= "dpio-tx-b-23",
6910 .domains
= VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS
|
6911 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS
,
6912 .ops
= &vlv_dpio_power_well_ops
,
6913 .data
= PUNIT_POWER_WELL_DPIO_TX_B_LANES_23
,
6916 .name
= "dpio-tx-c-01",
6917 .domains
= VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS
|
6918 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS
,
6919 .ops
= &vlv_dpio_power_well_ops
,
6920 .data
= PUNIT_POWER_WELL_DPIO_TX_C_LANES_01
,
6923 .name
= "dpio-tx-c-23",
6924 .domains
= VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS
|
6925 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS
,
6926 .ops
= &vlv_dpio_power_well_ops
,
6927 .data
= PUNIT_POWER_WELL_DPIO_TX_C_LANES_23
,
6930 .name
= "dpio-tx-d-01",
6931 .domains
= CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS
|
6932 CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS
,
6933 .ops
= &vlv_dpio_power_well_ops
,
6934 .data
= PUNIT_POWER_WELL_DPIO_TX_D_LANES_01
,
6937 .name
= "dpio-tx-d-23",
6938 .domains
= CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS
|
6939 CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS
,
6940 .ops
= &vlv_dpio_power_well_ops
,
6941 .data
= PUNIT_POWER_WELL_DPIO_TX_D_LANES_23
,
6946 static struct i915_power_well
*lookup_power_well(struct drm_i915_private
*dev_priv
,
6947 enum punit_power_well power_well_id
)
6949 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
6950 struct i915_power_well
*power_well
;
6953 for_each_power_well(i
, power_well
, POWER_DOMAIN_MASK
, power_domains
) {
6954 if (power_well
->data
== power_well_id
)
6961 #define set_power_wells(power_domains, __power_wells) ({ \
6962 (power_domains)->power_wells = (__power_wells); \
6963 (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \
6966 int intel_power_domains_init(struct drm_i915_private
*dev_priv
)
6968 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
6970 mutex_init(&power_domains
->lock
);
6973 * The enabling order will be from lower to higher indexed wells,
6974 * the disabling order is reversed.
6976 if (IS_HASWELL(dev_priv
->dev
)) {
6977 set_power_wells(power_domains
, hsw_power_wells
);
6978 hsw_pwr
= power_domains
;
6979 } else if (IS_BROADWELL(dev_priv
->dev
)) {
6980 set_power_wells(power_domains
, bdw_power_wells
);
6981 hsw_pwr
= power_domains
;
6982 } else if (IS_CHERRYVIEW(dev_priv
->dev
)) {
6983 set_power_wells(power_domains
, chv_power_wells
);
6984 } else if (IS_VALLEYVIEW(dev_priv
->dev
)) {
6985 set_power_wells(power_domains
, vlv_power_wells
);
6987 set_power_wells(power_domains
, i9xx_always_on_power_well
);
6993 void intel_power_domains_remove(struct drm_i915_private
*dev_priv
)
6998 static void intel_power_domains_resume(struct drm_i915_private
*dev_priv
)
7000 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
7001 struct i915_power_well
*power_well
;
7004 mutex_lock(&power_domains
->lock
);
7005 for_each_power_well(i
, power_well
, POWER_DOMAIN_MASK
, power_domains
) {
7006 power_well
->ops
->sync_hw(dev_priv
, power_well
);
7007 power_well
->hw_enabled
= power_well
->ops
->is_enabled(dev_priv
,
7010 mutex_unlock(&power_domains
->lock
);
7013 static void vlv_cmnlane_wa(struct drm_i915_private
*dev_priv
)
7015 struct i915_power_well
*cmn
=
7016 lookup_power_well(dev_priv
, PUNIT_POWER_WELL_DPIO_CMN_BC
);
7017 struct i915_power_well
*disp2d
=
7018 lookup_power_well(dev_priv
, PUNIT_POWER_WELL_DISP2D
);
7020 /* nothing to do if common lane is already off */
7021 if (!cmn
->ops
->is_enabled(dev_priv
, cmn
))
7024 /* If the display might be already active skip this */
7025 if (disp2d
->ops
->is_enabled(dev_priv
, disp2d
) &&
7026 I915_READ(DPIO_CTL
) & DPIO_CMNRST
)
7029 DRM_DEBUG_KMS("toggling display PHY side reset\n");
7031 /* cmnlane needs DPLL registers */
7032 disp2d
->ops
->enable(dev_priv
, disp2d
);
7035 * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
7036 * Need to assert and de-assert PHY SB reset by gating the
7037 * common lane power, then un-gating it.
7038 * Simply ungating isn't enough to reset the PHY enough to get
7039 * ports and lanes running.
7041 cmn
->ops
->disable(dev_priv
, cmn
);
7044 void intel_power_domains_init_hw(struct drm_i915_private
*dev_priv
)
7046 struct drm_device
*dev
= dev_priv
->dev
;
7047 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
7049 power_domains
->initializing
= true;
7051 if (IS_VALLEYVIEW(dev
) && !IS_CHERRYVIEW(dev
)) {
7052 mutex_lock(&power_domains
->lock
);
7053 vlv_cmnlane_wa(dev_priv
);
7054 mutex_unlock(&power_domains
->lock
);
7057 /* For now, we need the power well to be always enabled. */
7058 intel_display_set_init_power(dev_priv
, true);
7059 intel_power_domains_resume(dev_priv
);
7060 power_domains
->initializing
= false;
7063 void intel_aux_display_runtime_get(struct drm_i915_private
*dev_priv
)
7065 intel_runtime_pm_get(dev_priv
);
7068 void intel_aux_display_runtime_put(struct drm_i915_private
*dev_priv
)
7070 intel_runtime_pm_put(dev_priv
);
7073 void intel_runtime_pm_get(struct drm_i915_private
*dev_priv
)
7075 struct drm_device
*dev
= dev_priv
->dev
;
7076 struct device
*device
= &dev
->pdev
->dev
;
7078 if (!HAS_RUNTIME_PM(dev
))
7081 pm_runtime_get_sync(device
);
7082 WARN(dev_priv
->pm
.suspended
, "Device still suspended.\n");
7085 void intel_runtime_pm_get_noresume(struct drm_i915_private
*dev_priv
)
7087 struct drm_device
*dev
= dev_priv
->dev
;
7088 struct device
*device
= &dev
->pdev
->dev
;
7090 if (!HAS_RUNTIME_PM(dev
))
7093 WARN(dev_priv
->pm
.suspended
, "Getting nosync-ref while suspended.\n");
7094 pm_runtime_get_noresume(device
);
7097 void intel_runtime_pm_put(struct drm_i915_private
*dev_priv
)
7099 struct drm_device
*dev
= dev_priv
->dev
;
7100 struct device
*device
= &dev
->pdev
->dev
;
7102 if (!HAS_RUNTIME_PM(dev
))
7105 pm_runtime_mark_last_busy(device
);
7106 pm_runtime_put_autosuspend(device
);
7109 void intel_init_runtime_pm(struct drm_i915_private
*dev_priv
)
7111 struct drm_device
*dev
= dev_priv
->dev
;
7112 struct device
*device
= &dev
->pdev
->dev
;
7114 if (!HAS_RUNTIME_PM(dev
))
7117 pm_runtime_set_active(device
);
7120 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
7123 if (!intel_enable_rc6(dev
)) {
7124 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
7128 pm_runtime_set_autosuspend_delay(device
, 10000); /* 10s */
7129 pm_runtime_mark_last_busy(device
);
7130 pm_runtime_use_autosuspend(device
);
7132 pm_runtime_put_autosuspend(device
);
7135 void intel_fini_runtime_pm(struct drm_i915_private
*dev_priv
)
7137 struct drm_device
*dev
= dev_priv
->dev
;
7138 struct device
*device
= &dev
->pdev
->dev
;
7140 if (!HAS_RUNTIME_PM(dev
))
7143 if (!intel_enable_rc6(dev
))
7146 /* Make sure we're not suspended first. */
7147 pm_runtime_get_sync(device
);
7148 pm_runtime_disable(device
);
7151 /* Set up chip specific power management-related functions */
7152 void intel_init_pm(struct drm_device
*dev
)
7154 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7157 if (INTEL_INFO(dev
)->gen
>= 7) {
7158 dev_priv
->display
.fbc_enabled
= ironlake_fbc_enabled
;
7159 dev_priv
->display
.enable_fbc
= gen7_enable_fbc
;
7160 dev_priv
->display
.disable_fbc
= ironlake_disable_fbc
;
7161 } else if (INTEL_INFO(dev
)->gen
>= 5) {
7162 dev_priv
->display
.fbc_enabled
= ironlake_fbc_enabled
;
7163 dev_priv
->display
.enable_fbc
= ironlake_enable_fbc
;
7164 dev_priv
->display
.disable_fbc
= ironlake_disable_fbc
;
7165 } else if (IS_GM45(dev
)) {
7166 dev_priv
->display
.fbc_enabled
= g4x_fbc_enabled
;
7167 dev_priv
->display
.enable_fbc
= g4x_enable_fbc
;
7168 dev_priv
->display
.disable_fbc
= g4x_disable_fbc
;
7170 dev_priv
->display
.fbc_enabled
= i8xx_fbc_enabled
;
7171 dev_priv
->display
.enable_fbc
= i8xx_enable_fbc
;
7172 dev_priv
->display
.disable_fbc
= i8xx_disable_fbc
;
7174 /* This value was pulled out of someone's hat */
7175 I915_WRITE(FBC_CONTROL
, 500 << FBC_CTL_INTERVAL_SHIFT
);
7180 if (IS_PINEVIEW(dev
))
7181 i915_pineview_get_mem_freq(dev
);
7182 else if (IS_GEN5(dev
))
7183 i915_ironlake_get_mem_freq(dev
);
7185 /* For FIFO watermark updates */
7186 if (HAS_PCH_SPLIT(dev
)) {
7187 ilk_setup_wm_latency(dev
);
7189 if ((IS_GEN5(dev
) && dev_priv
->wm
.pri_latency
[1] &&
7190 dev_priv
->wm
.spr_latency
[1] && dev_priv
->wm
.cur_latency
[1]) ||
7191 (!IS_GEN5(dev
) && dev_priv
->wm
.pri_latency
[0] &&
7192 dev_priv
->wm
.spr_latency
[0] && dev_priv
->wm
.cur_latency
[0])) {
7193 dev_priv
->display
.update_wm
= ilk_update_wm
;
7194 dev_priv
->display
.update_sprite_wm
= ilk_update_sprite_wm
;
7196 DRM_DEBUG_KMS("Failed to read display plane latency. "
7201 dev_priv
->display
.init_clock_gating
= ironlake_init_clock_gating
;
7202 else if (IS_GEN6(dev
))
7203 dev_priv
->display
.init_clock_gating
= gen6_init_clock_gating
;
7204 else if (IS_IVYBRIDGE(dev
))
7205 dev_priv
->display
.init_clock_gating
= ivybridge_init_clock_gating
;
7206 else if (IS_HASWELL(dev
))
7207 dev_priv
->display
.init_clock_gating
= haswell_init_clock_gating
;
7208 else if (INTEL_INFO(dev
)->gen
== 8)
7209 dev_priv
->display
.init_clock_gating
= gen8_init_clock_gating
;
7210 } else if (IS_CHERRYVIEW(dev
)) {
7211 dev_priv
->display
.update_wm
= cherryview_update_wm
;
7212 dev_priv
->display
.init_clock_gating
=
7213 cherryview_init_clock_gating
;
7214 } else if (IS_VALLEYVIEW(dev
)) {
7215 dev_priv
->display
.update_wm
= valleyview_update_wm
;
7216 dev_priv
->display
.init_clock_gating
=
7217 valleyview_init_clock_gating
;
7218 } else if (IS_PINEVIEW(dev
)) {
7219 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev
),
7222 dev_priv
->mem_freq
)) {
7223 DRM_INFO("failed to find known CxSR latency "
7224 "(found ddr%s fsb freq %d, mem freq %d), "
7226 (dev_priv
->is_ddr3
== 1) ? "3" : "2",
7227 dev_priv
->fsb_freq
, dev_priv
->mem_freq
);
7228 /* Disable CxSR and never update its watermark again */
7229 intel_set_memory_cxsr(dev_priv
, false);
7230 dev_priv
->display
.update_wm
= NULL
;
7232 dev_priv
->display
.update_wm
= pineview_update_wm
;
7233 dev_priv
->display
.init_clock_gating
= gen3_init_clock_gating
;
7234 } else if (IS_G4X(dev
)) {
7235 dev_priv
->display
.update_wm
= g4x_update_wm
;
7236 dev_priv
->display
.init_clock_gating
= g4x_init_clock_gating
;
7237 } else if (IS_GEN4(dev
)) {
7238 dev_priv
->display
.update_wm
= i965_update_wm
;
7239 if (IS_CRESTLINE(dev
))
7240 dev_priv
->display
.init_clock_gating
= crestline_init_clock_gating
;
7241 else if (IS_BROADWATER(dev
))
7242 dev_priv
->display
.init_clock_gating
= broadwater_init_clock_gating
;
7243 } else if (IS_GEN3(dev
)) {
7244 dev_priv
->display
.update_wm
= i9xx_update_wm
;
7245 dev_priv
->display
.get_fifo_size
= i9xx_get_fifo_size
;
7246 dev_priv
->display
.init_clock_gating
= gen3_init_clock_gating
;
7247 } else if (IS_GEN2(dev
)) {
7248 if (INTEL_INFO(dev
)->num_pipes
== 1) {
7249 dev_priv
->display
.update_wm
= i845_update_wm
;
7250 dev_priv
->display
.get_fifo_size
= i845_get_fifo_size
;
7252 dev_priv
->display
.update_wm
= i9xx_update_wm
;
7253 dev_priv
->display
.get_fifo_size
= i830_get_fifo_size
;
7256 if (IS_I85X(dev
) || IS_I865G(dev
))
7257 dev_priv
->display
.init_clock_gating
= i85x_init_clock_gating
;
7259 dev_priv
->display
.init_clock_gating
= i830_init_clock_gating
;
7261 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
7265 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u8 mbox
, u32
*val
)
7267 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
7269 if (I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) {
7270 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7274 I915_WRITE(GEN6_PCODE_DATA
, *val
);
7275 I915_WRITE(GEN6_PCODE_MAILBOX
, GEN6_PCODE_READY
| mbox
);
7277 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) == 0,
7279 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox
);
7283 *val
= I915_READ(GEN6_PCODE_DATA
);
7284 I915_WRITE(GEN6_PCODE_DATA
, 0);
7289 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
, u8 mbox
, u32 val
)
7291 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
7293 if (I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) {
7294 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7298 I915_WRITE(GEN6_PCODE_DATA
, val
);
7299 I915_WRITE(GEN6_PCODE_MAILBOX
, GEN6_PCODE_READY
| mbox
);
7301 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) == 0,
7303 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox
);
7307 I915_WRITE(GEN6_PCODE_DATA
, 0);
7312 static int byt_gpu_freq(struct drm_i915_private
*dev_priv
, int val
)
7317 switch (dev_priv
->mem_freq
) {
7331 return DIV_ROUND_CLOSEST(dev_priv
->mem_freq
* (val
+ 6 - 0xbd), 4 * div
);
7334 static int byt_freq_opcode(struct drm_i915_private
*dev_priv
, int val
)
7339 switch (dev_priv
->mem_freq
) {
7353 return DIV_ROUND_CLOSEST(4 * mul
* val
, dev_priv
->mem_freq
) + 0xbd - 6;
7356 static int chv_gpu_freq(struct drm_i915_private
*dev_priv
, int val
)
7360 switch (dev_priv
->rps
.cz_freq
) {
7376 freq
= (DIV_ROUND_CLOSEST((dev_priv
->rps
.cz_freq
* val
), 2 * div
) / 2);
7381 static int chv_freq_opcode(struct drm_i915_private
*dev_priv
, int val
)
7385 switch (dev_priv
->rps
.cz_freq
) {
7401 opcode
= (DIV_ROUND_CLOSEST((val
* 2 * mul
), dev_priv
->rps
.cz_freq
) * 2);
7406 int vlv_gpu_freq(struct drm_i915_private
*dev_priv
, int val
)
7410 if (IS_CHERRYVIEW(dev_priv
->dev
))
7411 ret
= chv_gpu_freq(dev_priv
, val
);
7412 else if (IS_VALLEYVIEW(dev_priv
->dev
))
7413 ret
= byt_gpu_freq(dev_priv
, val
);
7418 int vlv_freq_opcode(struct drm_i915_private
*dev_priv
, int val
)
7422 if (IS_CHERRYVIEW(dev_priv
->dev
))
7423 ret
= chv_freq_opcode(dev_priv
, val
);
7424 else if (IS_VALLEYVIEW(dev_priv
->dev
))
7425 ret
= byt_freq_opcode(dev_priv
, val
);
7430 void intel_pm_setup(struct drm_device
*dev
)
7432 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7434 mutex_init(&dev_priv
->rps
.hw_lock
);
7436 INIT_DELAYED_WORK(&dev_priv
->rps
.delayed_resume_work
,
7437 intel_gen6_powersave_work
);
7439 dev_priv
->pm
.suspended
= false;
7440 dev_priv
->pm
._irqs_disabled
= false;