2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
25 * DOC: Panel Self Refresh (PSR/SRD)
27 * Since Haswell Display controller supports Panel Self-Refresh on display
28 * panels witch have a remote frame buffer (RFB) implemented according to PSR
29 * spec in eDP1.3. PSR feature allows the display to go to lower standby states
30 * when system is idle but display is on as it eliminates display refresh
31 * request to DDR memory completely as long as the frame buffer for that
32 * display is unchanged.
34 * Panel Self Refresh must be supported by both Hardware (source) and
37 * PSR saves power by caching the framebuffer in the panel RFB, which allows us
38 * to power down the link and memory controller. For DSI panels the same idea
39 * is called "manual mode".
41 * The implementation uses the hardware-based PSR support which automatically
42 * enters/exits self-refresh mode. The hardware takes care of sending the
43 * required DP aux message and could even retrain the link (that part isn't
44 * enabled yet though). The hardware also keeps track of any frontbuffer
45 * changes to know when to exit self-refresh mode again. Unfortunately that
46 * part doesn't work too well, hence why the i915 PSR support uses the
47 * software frontbuffer tracking to make sure it doesn't miss a screen
48 * update. For this integration intel_psr_invalidate() and intel_psr_flush()
49 * get called by the frontbuffer tracking code. Note that because of locking
50 * issues the self-refresh re-enable code is done from a work queue, which
51 * must be correctly synchronized/cancelled when shutting down the pipe."
56 #include "intel_drv.h"
59 static bool is_edp_psr(struct intel_dp
*intel_dp
)
61 return intel_dp
->psr_dpcd
[0] & DP_PSR_IS_SUPPORTED
;
64 static bool vlv_is_psr_active_on_pipe(struct drm_device
*dev
, int pipe
)
66 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
69 val
= I915_READ(VLV_PSRSTAT(pipe
)) &
70 VLV_EDP_PSR_CURR_STATE_MASK
;
71 return (val
== VLV_EDP_PSR_ACTIVE_NORFB_UP
) ||
72 (val
== VLV_EDP_PSR_ACTIVE_SF_UPDATE
);
75 static void intel_psr_write_vsc(struct intel_dp
*intel_dp
,
76 const struct edp_vsc_psr
*vsc_psr
)
78 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
79 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
80 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
81 struct intel_crtc
*crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
82 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
83 i915_reg_t ctl_reg
= HSW_TVIDEO_DIP_CTL(cpu_transcoder
);
84 uint32_t *data
= (uint32_t *) vsc_psr
;
87 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
88 the video DIP being updated before program video DIP data buffer
89 registers for DIP being updated. */
90 I915_WRITE(ctl_reg
, 0);
91 POSTING_READ(ctl_reg
);
93 for (i
= 0; i
< sizeof(*vsc_psr
); i
+= 4) {
94 I915_WRITE(HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder
,
98 for (; i
< VIDEO_DIP_VSC_DATA_SIZE
; i
+= 4)
99 I915_WRITE(HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder
,
102 I915_WRITE(ctl_reg
, VIDEO_DIP_ENABLE_VSC_HSW
);
103 POSTING_READ(ctl_reg
);
106 static void vlv_psr_setup_vsc(struct intel_dp
*intel_dp
)
108 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
109 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
110 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
111 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
112 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
115 /* VLV auto-generate VSC package as per EDP 1.3 spec, Table 3.10 */
116 val
= I915_READ(VLV_VSCSDP(pipe
));
117 val
&= ~VLV_EDP_PSR_SDP_FREQ_MASK
;
118 val
|= VLV_EDP_PSR_SDP_FREQ_EVFRAME
;
119 I915_WRITE(VLV_VSCSDP(pipe
), val
);
122 static void skl_psr_setup_su_vsc(struct intel_dp
*intel_dp
)
124 struct edp_vsc_psr psr_vsc
;
126 /* Prepare VSC Header for SU as per EDP 1.4 spec, Table 6.11 */
127 memset(&psr_vsc
, 0, sizeof(psr_vsc
));
128 psr_vsc
.sdp_header
.HB0
= 0;
129 psr_vsc
.sdp_header
.HB1
= 0x7;
130 psr_vsc
.sdp_header
.HB2
= 0x3;
131 psr_vsc
.sdp_header
.HB3
= 0xb;
132 intel_psr_write_vsc(intel_dp
, &psr_vsc
);
135 static void hsw_psr_setup_vsc(struct intel_dp
*intel_dp
)
137 struct edp_vsc_psr psr_vsc
;
139 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
140 memset(&psr_vsc
, 0, sizeof(psr_vsc
));
141 psr_vsc
.sdp_header
.HB0
= 0;
142 psr_vsc
.sdp_header
.HB1
= 0x7;
143 psr_vsc
.sdp_header
.HB2
= 0x2;
144 psr_vsc
.sdp_header
.HB3
= 0x8;
145 intel_psr_write_vsc(intel_dp
, &psr_vsc
);
148 static void vlv_psr_enable_sink(struct intel_dp
*intel_dp
)
150 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_PSR_EN_CFG
,
151 DP_PSR_ENABLE
| DP_PSR_MAIN_LINK_ACTIVE
);
154 static i915_reg_t
psr_aux_ctl_reg(struct drm_i915_private
*dev_priv
,
157 if (INTEL_INFO(dev_priv
)->gen
>= 9)
158 return DP_AUX_CH_CTL(port
);
160 return EDP_PSR_AUX_CTL
;
163 static i915_reg_t
psr_aux_data_reg(struct drm_i915_private
*dev_priv
,
164 enum port port
, int index
)
166 if (INTEL_INFO(dev_priv
)->gen
>= 9)
167 return DP_AUX_CH_DATA(port
, index
);
169 return EDP_PSR_AUX_DATA(index
);
172 static void hsw_psr_enable_sink(struct intel_dp
*intel_dp
)
174 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
175 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
176 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
177 uint32_t aux_clock_divider
;
178 i915_reg_t aux_ctl_reg
;
179 static const uint8_t aux_msg
[] = {
180 [0] = DP_AUX_NATIVE_WRITE
<< 4,
181 [1] = DP_SET_POWER
>> 8,
182 [2] = DP_SET_POWER
& 0xff,
184 [4] = DP_SET_POWER_D0
,
186 enum port port
= dig_port
->port
;
190 BUILD_BUG_ON(sizeof(aux_msg
) > 20);
192 aux_clock_divider
= intel_dp
->get_aux_clock_divider(intel_dp
, 0);
194 /* Enable AUX frame sync at sink */
195 if (dev_priv
->psr
.aux_frame_sync
)
196 drm_dp_dpcd_writeb(&intel_dp
->aux
,
197 DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF
,
198 DP_AUX_FRAME_SYNC_ENABLE
);
200 if (dev_priv
->psr
.link_standby
)
201 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_PSR_EN_CFG
,
202 DP_PSR_ENABLE
| DP_PSR_MAIN_LINK_ACTIVE
);
204 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_PSR_EN_CFG
,
207 aux_ctl_reg
= psr_aux_ctl_reg(dev_priv
, port
);
209 /* Setup AUX registers */
210 for (i
= 0; i
< sizeof(aux_msg
); i
+= 4)
211 I915_WRITE(psr_aux_data_reg(dev_priv
, port
, i
>> 2),
212 intel_dp_pack_aux(&aux_msg
[i
], sizeof(aux_msg
) - i
));
214 aux_ctl
= intel_dp
->get_aux_send_ctl(intel_dp
, 0, sizeof(aux_msg
),
216 I915_WRITE(aux_ctl_reg
, aux_ctl
);
219 static void vlv_psr_enable_source(struct intel_dp
*intel_dp
)
221 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
222 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
223 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
224 struct drm_crtc
*crtc
= dig_port
->base
.base
.crtc
;
225 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
227 /* Transition from PSR_state 0 to PSR_state 1, i.e. PSR Inactive */
228 I915_WRITE(VLV_PSRCTL(pipe
),
229 VLV_EDP_PSR_MODE_SW_TIMER
|
230 VLV_EDP_PSR_SRC_TRANSMITTER_STATE
|
234 static void vlv_psr_activate(struct intel_dp
*intel_dp
)
236 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
237 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
238 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
239 struct drm_crtc
*crtc
= dig_port
->base
.base
.crtc
;
240 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
242 /* Let's do the transition from PSR_state 1 to PSR_state 2
243 * that is PSR transition to active - static frame transmission.
244 * Then Hardware is responsible for the transition to PSR_state 3
245 * that is PSR active - no Remote Frame Buffer (RFB) update.
247 I915_WRITE(VLV_PSRCTL(pipe
), I915_READ(VLV_PSRCTL(pipe
)) |
248 VLV_EDP_PSR_ACTIVE_ENTRY
);
251 static void hsw_psr_enable_source(struct intel_dp
*intel_dp
)
253 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
254 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
255 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
257 uint32_t max_sleep_time
= 0x1f;
258 /* Lately it was identified that depending on panel idle frame count
259 * calculated at HW can be off by 1. So let's use what came
261 * There are also other cases where panel demands at least 4
262 * but VBT is not being set. To cover these 2 cases lets use
263 * at least 5 when VBT isn't set to be on the safest side.
265 uint32_t idle_frames
= dev_priv
->vbt
.psr
.idle_frames
+ 1;
266 uint32_t val
= EDP_PSR_ENABLE
;
268 val
|= max_sleep_time
<< EDP_PSR_MAX_SLEEP_TIME_SHIFT
;
269 val
|= idle_frames
<< EDP_PSR_IDLE_FRAME_SHIFT
;
272 val
|= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES
;
274 if (dev_priv
->psr
.link_standby
)
275 val
|= EDP_PSR_LINK_STANDBY
;
277 if (dev_priv
->vbt
.psr
.tp1_wakeup_time
> 5)
278 val
|= EDP_PSR_TP1_TIME_2500us
;
279 else if (dev_priv
->vbt
.psr
.tp1_wakeup_time
> 1)
280 val
|= EDP_PSR_TP1_TIME_500us
;
281 else if (dev_priv
->vbt
.psr
.tp1_wakeup_time
> 0)
282 val
|= EDP_PSR_TP1_TIME_100us
;
284 val
|= EDP_PSR_TP1_TIME_0us
;
286 if (dev_priv
->vbt
.psr
.tp2_tp3_wakeup_time
> 5)
287 val
|= EDP_PSR_TP2_TP3_TIME_2500us
;
288 else if (dev_priv
->vbt
.psr
.tp2_tp3_wakeup_time
> 1)
289 val
|= EDP_PSR_TP2_TP3_TIME_500us
;
290 else if (dev_priv
->vbt
.psr
.tp2_tp3_wakeup_time
> 0)
291 val
|= EDP_PSR_TP2_TP3_TIME_100us
;
293 val
|= EDP_PSR_TP2_TP3_TIME_0us
;
295 if (intel_dp_source_supports_hbr2(intel_dp
) &&
296 drm_dp_tps3_supported(intel_dp
->dpcd
))
297 val
|= EDP_PSR_TP1_TP3_SEL
;
299 val
|= EDP_PSR_TP1_TP2_SEL
;
301 I915_WRITE(EDP_PSR_CTL
, val
);
303 if (!dev_priv
->psr
.psr2_support
)
306 /* FIXME: selective update is probably totally broken because it doesn't
307 * mesh at all with our frontbuffer tracking. And the hw alone isn't
309 val
= EDP_PSR2_ENABLE
| EDP_SU_TRACK_ENABLE
;
311 if (dev_priv
->vbt
.psr
.tp2_tp3_wakeup_time
> 5)
312 val
|= EDP_PSR2_TP2_TIME_2500
;
313 else if (dev_priv
->vbt
.psr
.tp2_tp3_wakeup_time
> 1)
314 val
|= EDP_PSR2_TP2_TIME_500
;
315 else if (dev_priv
->vbt
.psr
.tp2_tp3_wakeup_time
> 0)
316 val
|= EDP_PSR2_TP2_TIME_100
;
318 val
|= EDP_PSR2_TP2_TIME_50
;
320 I915_WRITE(EDP_PSR2_CTL
, val
);
323 static bool intel_psr_match_conditions(struct intel_dp
*intel_dp
)
325 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
326 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
327 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
328 struct drm_crtc
*crtc
= dig_port
->base
.base
.crtc
;
329 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
331 lockdep_assert_held(&dev_priv
->psr
.lock
);
332 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
333 WARN_ON(!drm_modeset_is_locked(&crtc
->mutex
));
335 dev_priv
->psr
.source_ok
= false;
338 * HSW spec explicitly says PSR is tied to port A.
339 * BDW+ platforms with DDI implementation of PSR have different
340 * PSR registers per transcoder and we only implement transcoder EDP
341 * ones. Since by Display design transcoder EDP is tied to port A
342 * we can safely escape based on the port A.
344 if (HAS_DDI(dev
) && dig_port
->port
!= PORT_A
) {
345 DRM_DEBUG_KMS("PSR condition failed: Port not supported\n");
349 if (!i915
.enable_psr
) {
350 DRM_DEBUG_KMS("PSR disable by flag\n");
354 if ((IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) &&
355 !dev_priv
->psr
.link_standby
) {
356 DRM_ERROR("PSR condition failed: Link off requested but not supported on this platform\n");
360 if (IS_HASWELL(dev
) &&
361 I915_READ(HSW_STEREO_3D_CTL(intel_crtc
->config
->cpu_transcoder
)) &
363 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
367 if (IS_HASWELL(dev
) &&
368 intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
) {
369 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
373 dev_priv
->psr
.source_ok
= true;
377 static void intel_psr_activate(struct intel_dp
*intel_dp
)
379 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
380 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
381 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
383 WARN_ON(I915_READ(EDP_PSR_CTL
) & EDP_PSR_ENABLE
);
384 WARN_ON(dev_priv
->psr
.active
);
385 lockdep_assert_held(&dev_priv
->psr
.lock
);
387 /* Enable/Re-enable PSR on the host */
389 /* On HSW+ after we enable PSR on source it will activate it
390 * as soon as it match configure idle_frame count. So
391 * we just actually enable it here on activation time.
393 hsw_psr_enable_source(intel_dp
);
395 vlv_psr_activate(intel_dp
);
397 dev_priv
->psr
.active
= true;
401 * intel_psr_enable - Enable PSR
402 * @intel_dp: Intel DP
404 * This function can only be called after the pipe is fully trained and enabled.
406 void intel_psr_enable(struct intel_dp
*intel_dp
)
408 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
409 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
410 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
411 struct intel_crtc
*crtc
= to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
414 DRM_DEBUG_KMS("PSR not supported on this platform\n");
418 if (!is_edp_psr(intel_dp
)) {
419 DRM_DEBUG_KMS("PSR not supported by this panel\n");
423 mutex_lock(&dev_priv
->psr
.lock
);
424 if (dev_priv
->psr
.enabled
) {
425 DRM_DEBUG_KMS("PSR already in use\n");
429 if (!intel_psr_match_conditions(intel_dp
))
432 dev_priv
->psr
.busy_frontbuffer_bits
= 0;
435 hsw_psr_setup_vsc(intel_dp
);
437 if (dev_priv
->psr
.psr2_support
) {
438 /* PSR2 is restricted to work with panel resolutions upto 3200x2000 */
439 if (crtc
->config
->pipe_src_w
> 3200 ||
440 crtc
->config
->pipe_src_h
> 2000)
441 dev_priv
->psr
.psr2_support
= false;
443 skl_psr_setup_su_vsc(intel_dp
);
447 * Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD.
448 * Also mask LPSP to avoid dependency on other drivers that
449 * might block runtime_pm besides preventing other hw tracking
450 * issues now we can rely on frontbuffer tracking.
452 I915_WRITE(EDP_PSR_DEBUG_CTL
, EDP_PSR_DEBUG_MASK_MEMUP
|
453 EDP_PSR_DEBUG_MASK_HPD
| EDP_PSR_DEBUG_MASK_LPSP
);
455 /* Enable PSR on the panel */
456 hsw_psr_enable_sink(intel_dp
);
458 if (INTEL_INFO(dev
)->gen
>= 9)
459 intel_psr_activate(intel_dp
);
461 vlv_psr_setup_vsc(intel_dp
);
463 /* Enable PSR on the panel */
464 vlv_psr_enable_sink(intel_dp
);
466 /* On HSW+ enable_source also means go to PSR entry/active
467 * state as soon as idle_frame achieved and here would be
468 * to soon. However on VLV enable_source just enable PSR
469 * but let it on inactive state. So we might do this prior
470 * to active transition, i.e. here.
472 vlv_psr_enable_source(intel_dp
);
476 * FIXME: Activation should happen immediately since this function
477 * is just called after pipe is fully trained and enabled.
478 * However on every platform we face issues when first activation
479 * follows a modeset so quickly.
480 * - On VLV/CHV we get bank screen on first activation
481 * - On HSW/BDW we get a recoverable frozen screen until next
482 * exit-activate sequence.
484 if (INTEL_INFO(dev
)->gen
< 9)
485 schedule_delayed_work(&dev_priv
->psr
.work
,
486 msecs_to_jiffies(intel_dp
->panel_power_cycle_delay
* 5));
488 dev_priv
->psr
.enabled
= intel_dp
;
490 mutex_unlock(&dev_priv
->psr
.lock
);
493 static void vlv_psr_disable(struct intel_dp
*intel_dp
)
495 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
496 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
497 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
498 struct intel_crtc
*intel_crtc
=
499 to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
502 if (dev_priv
->psr
.active
) {
503 /* Put VLV PSR back to PSR_state 0 that is PSR Disabled. */
504 if (wait_for((I915_READ(VLV_PSRSTAT(intel_crtc
->pipe
)) &
505 VLV_EDP_PSR_IN_TRANS
) == 0, 1))
506 WARN(1, "PSR transition took longer than expected\n");
508 val
= I915_READ(VLV_PSRCTL(intel_crtc
->pipe
));
509 val
&= ~VLV_EDP_PSR_ACTIVE_ENTRY
;
510 val
&= ~VLV_EDP_PSR_ENABLE
;
511 val
&= ~VLV_EDP_PSR_MODE_MASK
;
512 I915_WRITE(VLV_PSRCTL(intel_crtc
->pipe
), val
);
514 dev_priv
->psr
.active
= false;
516 WARN_ON(vlv_is_psr_active_on_pipe(dev
, intel_crtc
->pipe
));
520 static void hsw_psr_disable(struct intel_dp
*intel_dp
)
522 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
523 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
524 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
526 if (dev_priv
->psr
.active
) {
527 I915_WRITE(EDP_PSR_CTL
,
528 I915_READ(EDP_PSR_CTL
) & ~EDP_PSR_ENABLE
);
530 /* Wait till PSR is idle */
531 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL
) &
532 EDP_PSR_STATUS_STATE_MASK
) == 0,
533 2 * USEC_PER_SEC
, 10 * USEC_PER_MSEC
))
534 DRM_ERROR("Timed out waiting for PSR Idle State\n");
536 dev_priv
->psr
.active
= false;
538 WARN_ON(I915_READ(EDP_PSR_CTL
) & EDP_PSR_ENABLE
);
543 * intel_psr_disable - Disable PSR
544 * @intel_dp: Intel DP
546 * This function needs to be called before disabling pipe.
548 void intel_psr_disable(struct intel_dp
*intel_dp
)
550 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
551 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
552 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
554 mutex_lock(&dev_priv
->psr
.lock
);
555 if (!dev_priv
->psr
.enabled
) {
556 mutex_unlock(&dev_priv
->psr
.lock
);
560 /* Disable PSR on Source */
562 hsw_psr_disable(intel_dp
);
564 vlv_psr_disable(intel_dp
);
566 /* Disable PSR on Sink */
567 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_PSR_EN_CFG
, 0);
569 dev_priv
->psr
.enabled
= NULL
;
570 mutex_unlock(&dev_priv
->psr
.lock
);
572 cancel_delayed_work_sync(&dev_priv
->psr
.work
);
575 static void intel_psr_work(struct work_struct
*work
)
577 struct drm_i915_private
*dev_priv
=
578 container_of(work
, typeof(*dev_priv
), psr
.work
.work
);
579 struct intel_dp
*intel_dp
= dev_priv
->psr
.enabled
;
580 struct drm_crtc
*crtc
= dp_to_dig_port(intel_dp
)->base
.base
.crtc
;
581 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
583 /* We have to make sure PSR is ready for re-enable
584 * otherwise it keeps disabled until next full enable/disable cycle.
585 * PSR might take some time to get fully disabled
586 * and be ready for re-enable.
588 if (HAS_DDI(dev_priv
)) {
589 if (wait_for((I915_READ(EDP_PSR_STATUS_CTL
) &
590 EDP_PSR_STATUS_STATE_MASK
) == 0, 50)) {
591 DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
595 if (wait_for((I915_READ(VLV_PSRSTAT(pipe
)) &
596 VLV_EDP_PSR_IN_TRANS
) == 0, 1)) {
597 DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
601 mutex_lock(&dev_priv
->psr
.lock
);
602 intel_dp
= dev_priv
->psr
.enabled
;
608 * The delayed work can race with an invalidate hence we need to
609 * recheck. Since psr_flush first clears this and then reschedules we
610 * won't ever miss a flush when bailing out here.
612 if (dev_priv
->psr
.busy_frontbuffer_bits
)
615 intel_psr_activate(intel_dp
);
617 mutex_unlock(&dev_priv
->psr
.lock
);
620 static void intel_psr_exit(struct drm_device
*dev
)
622 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
623 struct intel_dp
*intel_dp
= dev_priv
->psr
.enabled
;
624 struct drm_crtc
*crtc
= dp_to_dig_port(intel_dp
)->base
.base
.crtc
;
625 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
628 if (!dev_priv
->psr
.active
)
632 val
= I915_READ(EDP_PSR_CTL
);
634 WARN_ON(!(val
& EDP_PSR_ENABLE
));
636 I915_WRITE(EDP_PSR_CTL
, val
& ~EDP_PSR_ENABLE
);
638 val
= I915_READ(VLV_PSRCTL(pipe
));
640 /* Here we do the transition from PSR_state 3 to PSR_state 5
641 * directly once PSR State 4 that is active with single frame
642 * update can be skipped. PSR_state 5 that is PSR exit then
643 * Hardware is responsible to transition back to PSR_state 1
644 * that is PSR inactive. Same state after
645 * vlv_edp_psr_enable_source.
647 val
&= ~VLV_EDP_PSR_ACTIVE_ENTRY
;
648 I915_WRITE(VLV_PSRCTL(pipe
), val
);
650 /* Send AUX wake up - Spec says after transitioning to PSR
651 * active we have to send AUX wake up by writing 01h in DPCD
652 * 600h of sink device.
653 * XXX: This might slow down the transition, but without this
654 * HW doesn't complete the transition to PSR_state 1 and we
655 * never get the screen updated.
657 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
661 dev_priv
->psr
.active
= false;
665 * intel_psr_single_frame_update - Single Frame Update
667 * @frontbuffer_bits: frontbuffer plane tracking bits
669 * Some platforms support a single frame update feature that is used to
670 * send and update only one frame on Remote Frame Buffer.
671 * So far it is only implemented for Valleyview and Cherryview because
672 * hardware requires this to be done before a page flip.
674 void intel_psr_single_frame_update(struct drm_device
*dev
,
675 unsigned frontbuffer_bits
)
677 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
678 struct drm_crtc
*crtc
;
683 * Single frame update is already supported on BDW+ but it requires
684 * many W/A and it isn't really needed.
686 if (!IS_VALLEYVIEW(dev
) && !IS_CHERRYVIEW(dev
))
689 mutex_lock(&dev_priv
->psr
.lock
);
690 if (!dev_priv
->psr
.enabled
) {
691 mutex_unlock(&dev_priv
->psr
.lock
);
695 crtc
= dp_to_dig_port(dev_priv
->psr
.enabled
)->base
.base
.crtc
;
696 pipe
= to_intel_crtc(crtc
)->pipe
;
698 if (frontbuffer_bits
& INTEL_FRONTBUFFER_ALL_MASK(pipe
)) {
699 val
= I915_READ(VLV_PSRCTL(pipe
));
702 * We need to set this bit before writing registers for a flip.
703 * This bit will be self-clear when it gets to the PSR active state.
705 I915_WRITE(VLV_PSRCTL(pipe
), val
| VLV_EDP_PSR_SINGLE_FRAME_UPDATE
);
707 mutex_unlock(&dev_priv
->psr
.lock
);
711 * intel_psr_invalidate - Invalidade PSR
713 * @frontbuffer_bits: frontbuffer plane tracking bits
715 * Since the hardware frontbuffer tracking has gaps we need to integrate
716 * with the software frontbuffer tracking. This function gets called every
717 * time frontbuffer rendering starts and a buffer gets dirtied. PSR must be
718 * disabled if the frontbuffer mask contains a buffer relevant to PSR.
720 * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits."
722 void intel_psr_invalidate(struct drm_device
*dev
,
723 unsigned frontbuffer_bits
)
725 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
726 struct drm_crtc
*crtc
;
729 mutex_lock(&dev_priv
->psr
.lock
);
730 if (!dev_priv
->psr
.enabled
) {
731 mutex_unlock(&dev_priv
->psr
.lock
);
735 crtc
= dp_to_dig_port(dev_priv
->psr
.enabled
)->base
.base
.crtc
;
736 pipe
= to_intel_crtc(crtc
)->pipe
;
738 frontbuffer_bits
&= INTEL_FRONTBUFFER_ALL_MASK(pipe
);
739 dev_priv
->psr
.busy_frontbuffer_bits
|= frontbuffer_bits
;
741 if (frontbuffer_bits
)
744 mutex_unlock(&dev_priv
->psr
.lock
);
748 * intel_psr_flush - Flush PSR
750 * @frontbuffer_bits: frontbuffer plane tracking bits
751 * @origin: which operation caused the flush
753 * Since the hardware frontbuffer tracking has gaps we need to integrate
754 * with the software frontbuffer tracking. This function gets called every
755 * time frontbuffer rendering has completed and flushed out to memory. PSR
756 * can be enabled again if no other frontbuffer relevant to PSR is dirty.
758 * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits.
760 void intel_psr_flush(struct drm_device
*dev
,
761 unsigned frontbuffer_bits
, enum fb_op_origin origin
)
763 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
764 struct drm_crtc
*crtc
;
767 mutex_lock(&dev_priv
->psr
.lock
);
768 if (!dev_priv
->psr
.enabled
) {
769 mutex_unlock(&dev_priv
->psr
.lock
);
773 crtc
= dp_to_dig_port(dev_priv
->psr
.enabled
)->base
.base
.crtc
;
774 pipe
= to_intel_crtc(crtc
)->pipe
;
776 frontbuffer_bits
&= INTEL_FRONTBUFFER_ALL_MASK(pipe
);
777 dev_priv
->psr
.busy_frontbuffer_bits
&= ~frontbuffer_bits
;
779 /* By definition flush = invalidate + flush */
780 if (frontbuffer_bits
)
783 if (!dev_priv
->psr
.active
&& !dev_priv
->psr
.busy_frontbuffer_bits
)
784 if (!work_busy(&dev_priv
->psr
.work
.work
))
785 schedule_delayed_work(&dev_priv
->psr
.work
,
786 msecs_to_jiffies(100));
787 mutex_unlock(&dev_priv
->psr
.lock
);
791 * intel_psr_init - Init basic PSR work and mutex.
794 * This function is called only once at driver load to initialize basic
797 void intel_psr_init(struct drm_device
*dev
)
799 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
801 dev_priv
->psr_mmio_base
= IS_HASWELL(dev_priv
) ?
802 HSW_EDP_PSR_BASE
: BDW_EDP_PSR_BASE
;
804 /* Per platform default */
805 if (i915
.enable_psr
== -1) {
806 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
812 /* Set link_standby x link_off defaults */
813 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
814 /* HSW and BDW require workarounds that we don't implement. */
815 dev_priv
->psr
.link_standby
= false;
816 else if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
817 /* On VLV and CHV only standby mode is supported. */
818 dev_priv
->psr
.link_standby
= true;
820 /* For new platforms let's respect VBT back again */
821 dev_priv
->psr
.link_standby
= dev_priv
->vbt
.psr
.full_link
;
823 /* Override link_standby x link_off defaults */
824 if (i915
.enable_psr
== 2 && !dev_priv
->psr
.link_standby
) {
825 DRM_DEBUG_KMS("PSR: Forcing link standby\n");
826 dev_priv
->psr
.link_standby
= true;
828 if (i915
.enable_psr
== 3 && dev_priv
->psr
.link_standby
) {
829 DRM_DEBUG_KMS("PSR: Forcing main link off\n");
830 dev_priv
->psr
.link_standby
= false;
833 INIT_DELAYED_WORK(&dev_priv
->psr
.work
, intel_psr_work
);
834 mutex_init(&dev_priv
->psr
.lock
);