2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
25 * DOC: Panel Self Refresh (PSR/SRD)
27 * Since Haswell Display controller supports Panel Self-Refresh on display
28 * panels witch have a remote frame buffer (RFB) implemented according to PSR
29 * spec in eDP1.3. PSR feature allows the display to go to lower standby states
30 * when system is idle but display is on as it eliminates display refresh
31 * request to DDR memory completely as long as the frame buffer for that
32 * display is unchanged.
34 * Panel Self Refresh must be supported by both Hardware (source) and
37 * PSR saves power by caching the framebuffer in the panel RFB, which allows us
38 * to power down the link and memory controller. For DSI panels the same idea
39 * is called "manual mode".
41 * The implementation uses the hardware-based PSR support which automatically
42 * enters/exits self-refresh mode. The hardware takes care of sending the
43 * required DP aux message and could even retrain the link (that part isn't
44 * enabled yet though). The hardware also keeps track of any frontbuffer
45 * changes to know when to exit self-refresh mode again. Unfortunately that
46 * part doesn't work too well, hence why the i915 PSR support uses the
47 * software frontbuffer tracking to make sure it doesn't miss a screen
48 * update. For this integration intel_psr_invalidate() and intel_psr_flush()
49 * get called by the frontbuffer tracking code. Note that because of locking
50 * issues the self-refresh re-enable code is done from a work queue, which
51 * must be correctly synchronized/cancelled when shutting down the pipe."
56 #include "intel_drv.h"
59 static bool is_edp_psr(struct intel_dp
*intel_dp
)
61 return intel_dp
->psr_dpcd
[0] & DP_PSR_IS_SUPPORTED
;
64 static bool vlv_is_psr_active_on_pipe(struct drm_device
*dev
, int pipe
)
66 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
69 val
= I915_READ(VLV_PSRSTAT(pipe
)) &
70 VLV_EDP_PSR_CURR_STATE_MASK
;
71 return (val
== VLV_EDP_PSR_ACTIVE_NORFB_UP
) ||
72 (val
== VLV_EDP_PSR_ACTIVE_SF_UPDATE
);
75 static void intel_psr_write_vsc(struct intel_dp
*intel_dp
,
76 struct edp_vsc_psr
*vsc_psr
)
78 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
79 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
80 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
81 struct intel_crtc
*crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
82 u32 ctl_reg
= HSW_TVIDEO_DIP_CTL(crtc
->config
->cpu_transcoder
);
83 u32 data_reg
= HSW_TVIDEO_DIP_VSC_DATA(crtc
->config
->cpu_transcoder
);
84 uint32_t *data
= (uint32_t *) vsc_psr
;
87 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
88 the video DIP being updated before program video DIP data buffer
89 registers for DIP being updated. */
90 I915_WRITE(ctl_reg
, 0);
91 POSTING_READ(ctl_reg
);
93 for (i
= 0; i
< VIDEO_DIP_VSC_DATA_SIZE
; i
+= 4) {
94 if (i
< sizeof(struct edp_vsc_psr
))
95 I915_WRITE(data_reg
+ i
, *data
++);
97 I915_WRITE(data_reg
+ i
, 0);
100 I915_WRITE(ctl_reg
, VIDEO_DIP_ENABLE_VSC_HSW
);
101 POSTING_READ(ctl_reg
);
104 static void vlv_psr_setup_vsc(struct intel_dp
*intel_dp
)
106 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
107 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
108 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
109 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
110 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
113 /* VLV auto-generate VSC package as per EDP 1.3 spec, Table 3.10 */
114 val
= I915_READ(VLV_VSCSDP(pipe
));
115 val
&= ~VLV_EDP_PSR_SDP_FREQ_MASK
;
116 val
|= VLV_EDP_PSR_SDP_FREQ_EVFRAME
;
117 I915_WRITE(VLV_VSCSDP(pipe
), val
);
120 static void hsw_psr_setup_vsc(struct intel_dp
*intel_dp
)
122 struct edp_vsc_psr psr_vsc
;
124 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
125 memset(&psr_vsc
, 0, sizeof(psr_vsc
));
126 psr_vsc
.sdp_header
.HB0
= 0;
127 psr_vsc
.sdp_header
.HB1
= 0x7;
128 psr_vsc
.sdp_header
.HB2
= 0x2;
129 psr_vsc
.sdp_header
.HB3
= 0x8;
130 intel_psr_write_vsc(intel_dp
, &psr_vsc
);
133 static void vlv_psr_enable_sink(struct intel_dp
*intel_dp
)
135 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_PSR_EN_CFG
,
139 static void hsw_psr_enable_sink(struct intel_dp
*intel_dp
)
141 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
142 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
143 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
144 uint32_t aux_clock_divider
;
145 uint32_t aux_data_reg
, aux_ctl_reg
;
147 static const uint8_t aux_msg
[] = {
148 [0] = DP_AUX_NATIVE_WRITE
<< 4,
149 [1] = DP_SET_POWER
>> 8,
150 [2] = DP_SET_POWER
& 0xff,
152 [4] = DP_SET_POWER_D0
,
156 BUILD_BUG_ON(sizeof(aux_msg
) > 20);
158 aux_clock_divider
= intel_dp
->get_aux_clock_divider(intel_dp
, 0);
160 /* Enable PSR in sink */
161 if (dev_priv
->psr
.link_standby
)
162 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_PSR_EN_CFG
,
163 DP_PSR_ENABLE
| DP_PSR_MAIN_LINK_ACTIVE
);
165 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_PSR_EN_CFG
,
166 DP_PSR_ENABLE
& ~DP_PSR_MAIN_LINK_ACTIVE
);
168 aux_data_reg
= (INTEL_INFO(dev
)->gen
>= 9) ?
169 DPA_AUX_CH_DATA1
: EDP_PSR_AUX_DATA1(dev
);
170 aux_ctl_reg
= (INTEL_INFO(dev
)->gen
>= 9) ?
171 DPA_AUX_CH_CTL
: EDP_PSR_AUX_CTL(dev
);
173 /* Setup AUX registers */
174 for (i
= 0; i
< sizeof(aux_msg
); i
+= 4)
175 I915_WRITE(aux_data_reg
+ i
,
176 intel_dp_pack_aux(&aux_msg
[i
], sizeof(aux_msg
) - i
));
178 if (INTEL_INFO(dev
)->gen
>= 9) {
181 val
= I915_READ(aux_ctl_reg
);
182 val
&= ~DP_AUX_CH_CTL_TIME_OUT_MASK
;
183 val
|= DP_AUX_CH_CTL_TIME_OUT_1600us
;
184 val
&= ~DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
;
185 val
|= (sizeof(aux_msg
) << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
);
186 /* Use hardcoded data values for PSR */
187 val
&= ~DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL
;
188 I915_WRITE(aux_ctl_reg
, val
);
190 I915_WRITE(aux_ctl_reg
,
191 DP_AUX_CH_CTL_TIME_OUT_400us
|
192 (sizeof(aux_msg
) << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
193 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
194 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
));
198 static void vlv_psr_enable_source(struct intel_dp
*intel_dp
)
200 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
201 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
202 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
203 struct drm_crtc
*crtc
= dig_port
->base
.base
.crtc
;
204 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
206 /* Transition from PSR_state 0 to PSR_state 1, i.e. PSR Inactive */
207 I915_WRITE(VLV_PSRCTL(pipe
),
208 VLV_EDP_PSR_MODE_SW_TIMER
|
209 VLV_EDP_PSR_SRC_TRANSMITTER_STATE
|
213 static void vlv_psr_activate(struct intel_dp
*intel_dp
)
215 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
216 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
217 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
218 struct drm_crtc
*crtc
= dig_port
->base
.base
.crtc
;
219 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
221 /* Let's do the transition from PSR_state 1 to PSR_state 2
222 * that is PSR transition to active - static frame transmission.
223 * Then Hardware is responsible for the transition to PSR_state 3
224 * that is PSR active - no Remote Frame Buffer (RFB) update.
226 I915_WRITE(VLV_PSRCTL(pipe
), I915_READ(VLV_PSRCTL(pipe
)) |
227 VLV_EDP_PSR_ACTIVE_ENTRY
);
230 static void hsw_psr_enable_source(struct intel_dp
*intel_dp
)
232 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
233 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
234 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
235 uint32_t max_sleep_time
= 0x1f;
236 /* Lately it was identified that depending on panel idle frame count
237 * calculated at HW can be off by 1. So let's use what came
238 * from VBT + 1 and at minimum 2 to be on the safe side.
240 uint32_t idle_frames
= dev_priv
->vbt
.psr
.idle_frames
?
241 dev_priv
->vbt
.psr
.idle_frames
+ 1 : 2;
243 const uint32_t link_entry_time
= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES
;
245 if (dev_priv
->psr
.link_standby
) {
246 val
|= EDP_PSR_LINK_STANDBY
;
247 val
|= EDP_PSR_TP2_TP3_TIME_0us
;
248 val
|= EDP_PSR_TP1_TIME_0us
;
249 val
|= EDP_PSR_SKIP_AUX_EXIT
;
251 val
|= EDP_PSR_LINK_DISABLE
;
253 I915_WRITE(EDP_PSR_CTL(dev
), val
|
254 (IS_BROADWELL(dev
) ? 0 : link_entry_time
) |
255 max_sleep_time
<< EDP_PSR_MAX_SLEEP_TIME_SHIFT
|
256 idle_frames
<< EDP_PSR_IDLE_FRAME_SHIFT
|
260 static bool intel_psr_match_conditions(struct intel_dp
*intel_dp
)
262 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
263 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
264 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
265 struct drm_crtc
*crtc
= dig_port
->base
.base
.crtc
;
266 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
268 lockdep_assert_held(&dev_priv
->psr
.lock
);
269 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
270 WARN_ON(!drm_modeset_is_locked(&crtc
->mutex
));
272 dev_priv
->psr
.source_ok
= false;
274 if (IS_HASWELL(dev
) && dig_port
->port
!= PORT_A
) {
275 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
279 if (!i915
.enable_psr
) {
280 DRM_DEBUG_KMS("PSR disable by flag\n");
284 if (IS_HASWELL(dev
) &&
285 I915_READ(HSW_STEREO_3D_CTL(intel_crtc
->config
->cpu_transcoder
)) &
287 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
291 if (IS_HASWELL(dev
) &&
292 intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
) {
293 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
297 dev_priv
->psr
.source_ok
= true;
301 static void intel_psr_activate(struct intel_dp
*intel_dp
)
303 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
304 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
305 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
307 WARN_ON(I915_READ(EDP_PSR_CTL(dev
)) & EDP_PSR_ENABLE
);
308 WARN_ON(dev_priv
->psr
.active
);
309 lockdep_assert_held(&dev_priv
->psr
.lock
);
311 /* Enable/Re-enable PSR on the host */
313 /* On HSW+ after we enable PSR on source it will activate it
314 * as soon as it match configure idle_frame count. So
315 * we just actually enable it here on activation time.
317 hsw_psr_enable_source(intel_dp
);
319 vlv_psr_activate(intel_dp
);
321 dev_priv
->psr
.active
= true;
325 * intel_psr_enable - Enable PSR
326 * @intel_dp: Intel DP
328 * This function can only be called after the pipe is fully trained and enabled.
330 void intel_psr_enable(struct intel_dp
*intel_dp
)
332 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
333 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
334 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
337 DRM_DEBUG_KMS("PSR not supported on this platform\n");
341 if (!is_edp_psr(intel_dp
)) {
342 DRM_DEBUG_KMS("PSR not supported by this panel\n");
346 mutex_lock(&dev_priv
->psr
.lock
);
347 if (dev_priv
->psr
.enabled
) {
348 DRM_DEBUG_KMS("PSR already in use\n");
352 if (!intel_psr_match_conditions(intel_dp
))
355 /* First we check VBT, but we must respect sink and source
356 * known restrictions */
357 dev_priv
->psr
.link_standby
= dev_priv
->vbt
.psr
.full_link
;
358 if ((intel_dp
->psr_dpcd
[1] & DP_PSR_NO_TRAIN_ON_EXIT
) ||
359 (IS_BROADWELL(dev
) && intel_dig_port
->port
!= PORT_A
))
360 dev_priv
->psr
.link_standby
= true;
362 dev_priv
->psr
.busy_frontbuffer_bits
= 0;
365 hsw_psr_setup_vsc(intel_dp
);
367 /* Avoid continuous PSR exit by masking memup and hpd */
368 I915_WRITE(EDP_PSR_DEBUG_CTL(dev
), EDP_PSR_DEBUG_MASK_MEMUP
|
369 EDP_PSR_DEBUG_MASK_HPD
| EDP_PSR_DEBUG_MASK_LPSP
);
371 /* Enable PSR on the panel */
372 hsw_psr_enable_sink(intel_dp
);
374 if (INTEL_INFO(dev
)->gen
>= 9)
375 intel_psr_activate(intel_dp
);
377 vlv_psr_setup_vsc(intel_dp
);
379 /* Enable PSR on the panel */
380 vlv_psr_enable_sink(intel_dp
);
382 /* On HSW+ enable_source also means go to PSR entry/active
383 * state as soon as idle_frame achieved and here would be
384 * to soon. However on VLV enable_source just enable PSR
385 * but let it on inactive state. So we might do this prior
386 * to active transition, i.e. here.
388 vlv_psr_enable_source(intel_dp
);
391 dev_priv
->psr
.enabled
= intel_dp
;
393 mutex_unlock(&dev_priv
->psr
.lock
);
396 static void vlv_psr_disable(struct intel_dp
*intel_dp
)
398 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
399 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
400 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
401 struct intel_crtc
*intel_crtc
=
402 to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
405 if (dev_priv
->psr
.active
) {
406 /* Put VLV PSR back to PSR_state 0 that is PSR Disabled. */
407 if (wait_for((I915_READ(VLV_PSRSTAT(intel_crtc
->pipe
)) &
408 VLV_EDP_PSR_IN_TRANS
) == 0, 1))
409 WARN(1, "PSR transition took longer than expected\n");
411 val
= I915_READ(VLV_PSRCTL(intel_crtc
->pipe
));
412 val
&= ~VLV_EDP_PSR_ACTIVE_ENTRY
;
413 val
&= ~VLV_EDP_PSR_ENABLE
;
414 val
&= ~VLV_EDP_PSR_MODE_MASK
;
415 I915_WRITE(VLV_PSRCTL(intel_crtc
->pipe
), val
);
417 dev_priv
->psr
.active
= false;
419 WARN_ON(vlv_is_psr_active_on_pipe(dev
, intel_crtc
->pipe
));
423 static void hsw_psr_disable(struct intel_dp
*intel_dp
)
425 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
426 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
427 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
429 if (dev_priv
->psr
.active
) {
430 I915_WRITE(EDP_PSR_CTL(dev
),
431 I915_READ(EDP_PSR_CTL(dev
)) & ~EDP_PSR_ENABLE
);
433 /* Wait till PSR is idle */
434 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev
)) &
435 EDP_PSR_STATUS_STATE_MASK
) == 0, 2000, 10))
436 DRM_ERROR("Timed out waiting for PSR Idle State\n");
438 dev_priv
->psr
.active
= false;
440 WARN_ON(I915_READ(EDP_PSR_CTL(dev
)) & EDP_PSR_ENABLE
);
445 * intel_psr_disable - Disable PSR
446 * @intel_dp: Intel DP
448 * This function needs to be called before disabling pipe.
450 void intel_psr_disable(struct intel_dp
*intel_dp
)
452 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
453 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
454 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
456 mutex_lock(&dev_priv
->psr
.lock
);
457 if (!dev_priv
->psr
.enabled
) {
458 mutex_unlock(&dev_priv
->psr
.lock
);
463 hsw_psr_disable(intel_dp
);
465 vlv_psr_disable(intel_dp
);
467 dev_priv
->psr
.enabled
= NULL
;
468 mutex_unlock(&dev_priv
->psr
.lock
);
470 cancel_delayed_work_sync(&dev_priv
->psr
.work
);
473 static void intel_psr_work(struct work_struct
*work
)
475 struct drm_i915_private
*dev_priv
=
476 container_of(work
, typeof(*dev_priv
), psr
.work
.work
);
477 struct intel_dp
*intel_dp
= dev_priv
->psr
.enabled
;
478 struct drm_crtc
*crtc
= dp_to_dig_port(intel_dp
)->base
.base
.crtc
;
479 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
481 /* We have to make sure PSR is ready for re-enable
482 * otherwise it keeps disabled until next full enable/disable cycle.
483 * PSR might take some time to get fully disabled
484 * and be ready for re-enable.
486 if (HAS_DDI(dev_priv
->dev
)) {
487 if (wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev_priv
->dev
)) &
488 EDP_PSR_STATUS_STATE_MASK
) == 0, 50)) {
489 DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
493 if (wait_for((I915_READ(VLV_PSRSTAT(pipe
)) &
494 VLV_EDP_PSR_IN_TRANS
) == 0, 1)) {
495 DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
499 mutex_lock(&dev_priv
->psr
.lock
);
500 intel_dp
= dev_priv
->psr
.enabled
;
506 * The delayed work can race with an invalidate hence we need to
507 * recheck. Since psr_flush first clears this and then reschedules we
508 * won't ever miss a flush when bailing out here.
510 if (dev_priv
->psr
.busy_frontbuffer_bits
)
513 intel_psr_activate(intel_dp
);
515 mutex_unlock(&dev_priv
->psr
.lock
);
518 static void intel_psr_exit(struct drm_device
*dev
)
520 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
521 struct intel_dp
*intel_dp
= dev_priv
->psr
.enabled
;
522 struct drm_crtc
*crtc
= dp_to_dig_port(intel_dp
)->base
.base
.crtc
;
523 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
526 if (!dev_priv
->psr
.active
)
530 val
= I915_READ(EDP_PSR_CTL(dev
));
532 WARN_ON(!(val
& EDP_PSR_ENABLE
));
534 I915_WRITE(EDP_PSR_CTL(dev
), val
& ~EDP_PSR_ENABLE
);
536 dev_priv
->psr
.active
= false;
538 val
= I915_READ(VLV_PSRCTL(pipe
));
540 /* Here we do the transition from PSR_state 3 to PSR_state 5
541 * directly once PSR State 4 that is active with single frame
542 * update can be skipped. PSR_state 5 that is PSR exit then
543 * Hardware is responsible to transition back to PSR_state 1
544 * that is PSR inactive. Same state after
545 * vlv_edp_psr_enable_source.
547 val
&= ~VLV_EDP_PSR_ACTIVE_ENTRY
;
548 I915_WRITE(VLV_PSRCTL(pipe
), val
);
550 /* Send AUX wake up - Spec says after transitioning to PSR
551 * active we have to send AUX wake up by writing 01h in DPCD
552 * 600h of sink device.
553 * XXX: This might slow down the transition, but without this
554 * HW doesn't complete the transition to PSR_state 1 and we
555 * never get the screen updated.
557 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
561 dev_priv
->psr
.active
= false;
565 * intel_psr_invalidate - Invalidade PSR
567 * @frontbuffer_bits: frontbuffer plane tracking bits
569 * Since the hardware frontbuffer tracking has gaps we need to integrate
570 * with the software frontbuffer tracking. This function gets called every
571 * time frontbuffer rendering starts and a buffer gets dirtied. PSR must be
572 * disabled if the frontbuffer mask contains a buffer relevant to PSR.
574 * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits."
576 void intel_psr_invalidate(struct drm_device
*dev
,
577 unsigned frontbuffer_bits
)
579 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
580 struct drm_crtc
*crtc
;
583 mutex_lock(&dev_priv
->psr
.lock
);
584 if (!dev_priv
->psr
.enabled
) {
585 mutex_unlock(&dev_priv
->psr
.lock
);
589 crtc
= dp_to_dig_port(dev_priv
->psr
.enabled
)->base
.base
.crtc
;
590 pipe
= to_intel_crtc(crtc
)->pipe
;
594 frontbuffer_bits
&= INTEL_FRONTBUFFER_ALL_MASK(pipe
);
596 dev_priv
->psr
.busy_frontbuffer_bits
|= frontbuffer_bits
;
597 mutex_unlock(&dev_priv
->psr
.lock
);
601 * intel_psr_flush - Flush PSR
603 * @frontbuffer_bits: frontbuffer plane tracking bits
605 * Since the hardware frontbuffer tracking has gaps we need to integrate
606 * with the software frontbuffer tracking. This function gets called every
607 * time frontbuffer rendering has completed and flushed out to memory. PSR
608 * can be enabled again if no other frontbuffer relevant to PSR is dirty.
610 * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits.
612 void intel_psr_flush(struct drm_device
*dev
,
613 unsigned frontbuffer_bits
)
615 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
616 struct drm_crtc
*crtc
;
619 mutex_lock(&dev_priv
->psr
.lock
);
620 if (!dev_priv
->psr
.enabled
) {
621 mutex_unlock(&dev_priv
->psr
.lock
);
625 crtc
= dp_to_dig_port(dev_priv
->psr
.enabled
)->base
.base
.crtc
;
626 pipe
= to_intel_crtc(crtc
)->pipe
;
627 dev_priv
->psr
.busy_frontbuffer_bits
&= ~frontbuffer_bits
;
630 * On Haswell sprite plane updates don't result in a psr invalidating
631 * signal in the hardware. Which means we need to manually fake this in
632 * software for all flushes, not just when we've seen a preceding
633 * invalidation through frontbuffer rendering.
635 if (IS_HASWELL(dev
) &&
636 (frontbuffer_bits
& INTEL_FRONTBUFFER_SPRITE(pipe
)))
640 * On Valleyview and Cherryview we don't use hardware tracking so
641 * any plane updates or cursor moves don't result in a PSR
642 * invalidating. Which means we need to manually fake this in
643 * software for all flushes, not just when we've seen a preceding
644 * invalidation through frontbuffer rendering. */
648 if (!dev_priv
->psr
.active
&& !dev_priv
->psr
.busy_frontbuffer_bits
)
649 schedule_delayed_work(&dev_priv
->psr
.work
,
650 msecs_to_jiffies(100));
651 mutex_unlock(&dev_priv
->psr
.lock
);
655 * intel_psr_init - Init basic PSR work and mutex.
658 * This function is called only once at driver load to initialize basic
661 void intel_psr_init(struct drm_device
*dev
)
663 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
665 INIT_DELAYED_WORK(&dev_priv
->psr
.work
, intel_psr_work
);
666 mutex_init(&dev_priv
->psr
.lock
);