2 * Copyright © 2008-2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
32 #include <drm/i915_drm.h>
33 #include "i915_trace.h"
34 #include "intel_drv.h"
36 static inline int ring_space(struct intel_ring_buffer
*ring
)
38 int space
= (ring
->head
& HEAD_ADDR
) - (ring
->tail
+ I915_RING_FREE_SPACE
);
44 void __intel_ring_advance(struct intel_ring_buffer
*ring
)
46 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
48 ring
->tail
&= ring
->size
- 1;
49 if (dev_priv
->gpu_error
.stop_rings
& intel_ring_flag(ring
))
51 ring
->write_tail(ring
, ring
->tail
);
55 gen2_render_ring_flush(struct intel_ring_buffer
*ring
,
56 u32 invalidate_domains
,
63 if (((invalidate_domains
|flush_domains
) & I915_GEM_DOMAIN_RENDER
) == 0)
64 cmd
|= MI_NO_WRITE_FLUSH
;
66 if (invalidate_domains
& I915_GEM_DOMAIN_SAMPLER
)
69 ret
= intel_ring_begin(ring
, 2);
73 intel_ring_emit(ring
, cmd
);
74 intel_ring_emit(ring
, MI_NOOP
);
75 intel_ring_advance(ring
);
81 gen4_render_ring_flush(struct intel_ring_buffer
*ring
,
82 u32 invalidate_domains
,
85 struct drm_device
*dev
= ring
->dev
;
92 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
93 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
94 * also flushed at 2d versus 3d pipeline switches.
98 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
99 * MI_READ_FLUSH is set, and is always flushed on 965.
101 * I915_GEM_DOMAIN_COMMAND may not exist?
103 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
104 * invalidated when MI_EXE_FLUSH is set.
106 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
107 * invalidated with every MI_FLUSH.
111 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
112 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
113 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
114 * are flushed at any MI_FLUSH.
117 cmd
= MI_FLUSH
| MI_NO_WRITE_FLUSH
;
118 if ((invalidate_domains
|flush_domains
) & I915_GEM_DOMAIN_RENDER
)
119 cmd
&= ~MI_NO_WRITE_FLUSH
;
120 if (invalidate_domains
& I915_GEM_DOMAIN_INSTRUCTION
)
123 if (invalidate_domains
& I915_GEM_DOMAIN_COMMAND
&&
124 (IS_G4X(dev
) || IS_GEN5(dev
)))
125 cmd
|= MI_INVALIDATE_ISP
;
127 ret
= intel_ring_begin(ring
, 2);
131 intel_ring_emit(ring
, cmd
);
132 intel_ring_emit(ring
, MI_NOOP
);
133 intel_ring_advance(ring
);
139 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
140 * implementing two workarounds on gen6. From section 1.4.7.1
141 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
143 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
144 * produced by non-pipelined state commands), software needs to first
145 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
148 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
149 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
151 * And the workaround for these two requires this workaround first:
153 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
154 * BEFORE the pipe-control with a post-sync op and no write-cache
157 * And this last workaround is tricky because of the requirements on
158 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
161 * "1 of the following must also be set:
162 * - Render Target Cache Flush Enable ([12] of DW1)
163 * - Depth Cache Flush Enable ([0] of DW1)
164 * - Stall at Pixel Scoreboard ([1] of DW1)
165 * - Depth Stall ([13] of DW1)
166 * - Post-Sync Operation ([13] of DW1)
167 * - Notify Enable ([8] of DW1)"
169 * The cache flushes require the workaround flush that triggered this
170 * one, so we can't use it. Depth stall would trigger the same.
171 * Post-sync nonzero is what triggered this second workaround, so we
172 * can't use that one either. Notify enable is IRQs, which aren't
173 * really our business. That leaves only stall at scoreboard.
176 intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer
*ring
)
178 u32 scratch_addr
= ring
->scratch
.gtt_offset
+ 128;
182 ret
= intel_ring_begin(ring
, 6);
186 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(5));
187 intel_ring_emit(ring
, PIPE_CONTROL_CS_STALL
|
188 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
189 intel_ring_emit(ring
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
); /* address */
190 intel_ring_emit(ring
, 0); /* low dword */
191 intel_ring_emit(ring
, 0); /* high dword */
192 intel_ring_emit(ring
, MI_NOOP
);
193 intel_ring_advance(ring
);
195 ret
= intel_ring_begin(ring
, 6);
199 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(5));
200 intel_ring_emit(ring
, PIPE_CONTROL_QW_WRITE
);
201 intel_ring_emit(ring
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
); /* address */
202 intel_ring_emit(ring
, 0);
203 intel_ring_emit(ring
, 0);
204 intel_ring_emit(ring
, MI_NOOP
);
205 intel_ring_advance(ring
);
211 gen6_render_ring_flush(struct intel_ring_buffer
*ring
,
212 u32 invalidate_domains
, u32 flush_domains
)
215 u32 scratch_addr
= ring
->scratch
.gtt_offset
+ 128;
218 /* Force SNB workarounds for PIPE_CONTROL flushes */
219 ret
= intel_emit_post_sync_nonzero_flush(ring
);
223 /* Just flush everything. Experiments have shown that reducing the
224 * number of bits based on the write domains has little performance
228 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
229 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
231 * Ensure that any following seqno writes only happen
232 * when the render cache is indeed flushed.
234 flags
|= PIPE_CONTROL_CS_STALL
;
236 if (invalidate_domains
) {
237 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
238 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
239 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
240 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
241 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
242 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
244 * TLB invalidate requires a post-sync write.
246 flags
|= PIPE_CONTROL_QW_WRITE
| PIPE_CONTROL_CS_STALL
;
249 ret
= intel_ring_begin(ring
, 4);
253 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4));
254 intel_ring_emit(ring
, flags
);
255 intel_ring_emit(ring
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
);
256 intel_ring_emit(ring
, 0);
257 intel_ring_advance(ring
);
263 gen7_render_ring_cs_stall_wa(struct intel_ring_buffer
*ring
)
267 ret
= intel_ring_begin(ring
, 4);
271 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4));
272 intel_ring_emit(ring
, PIPE_CONTROL_CS_STALL
|
273 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
274 intel_ring_emit(ring
, 0);
275 intel_ring_emit(ring
, 0);
276 intel_ring_advance(ring
);
281 static int gen7_ring_fbc_flush(struct intel_ring_buffer
*ring
, u32 value
)
285 if (!ring
->fbc_dirty
)
288 ret
= intel_ring_begin(ring
, 6);
291 /* WaFbcNukeOn3DBlt:ivb/hsw */
292 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
293 intel_ring_emit(ring
, MSG_FBC_REND_STATE
);
294 intel_ring_emit(ring
, value
);
295 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM(1) | MI_SRM_LRM_GLOBAL_GTT
);
296 intel_ring_emit(ring
, MSG_FBC_REND_STATE
);
297 intel_ring_emit(ring
, ring
->scratch
.gtt_offset
+ 256);
298 intel_ring_advance(ring
);
300 ring
->fbc_dirty
= false;
305 gen7_render_ring_flush(struct intel_ring_buffer
*ring
,
306 u32 invalidate_domains
, u32 flush_domains
)
309 u32 scratch_addr
= ring
->scratch
.gtt_offset
+ 128;
313 * Ensure that any following seqno writes only happen when the render
314 * cache is indeed flushed.
316 * Workaround: 4th PIPE_CONTROL command (except the ones with only
317 * read-cache invalidate bits set) must have the CS_STALL bit set. We
318 * don't try to be clever and just set it unconditionally.
320 flags
|= PIPE_CONTROL_CS_STALL
;
322 /* Just flush everything. Experiments have shown that reducing the
323 * number of bits based on the write domains has little performance
327 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
328 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
330 if (invalidate_domains
) {
331 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
332 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
333 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
334 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
335 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
336 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
338 * TLB invalidate requires a post-sync write.
340 flags
|= PIPE_CONTROL_QW_WRITE
;
341 flags
|= PIPE_CONTROL_GLOBAL_GTT_IVB
;
343 /* Workaround: we must issue a pipe_control with CS-stall bit
344 * set before a pipe_control command that has the state cache
345 * invalidate bit set. */
346 gen7_render_ring_cs_stall_wa(ring
);
349 ret
= intel_ring_begin(ring
, 4);
353 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4));
354 intel_ring_emit(ring
, flags
);
355 intel_ring_emit(ring
, scratch_addr
);
356 intel_ring_emit(ring
, 0);
357 intel_ring_advance(ring
);
359 if (!invalidate_domains
&& flush_domains
)
360 return gen7_ring_fbc_flush(ring
, FBC_REND_NUKE
);
366 gen8_render_ring_flush(struct intel_ring_buffer
*ring
,
367 u32 invalidate_domains
, u32 flush_domains
)
370 u32 scratch_addr
= ring
->scratch
.gtt_offset
+ 128;
373 flags
|= PIPE_CONTROL_CS_STALL
;
376 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
377 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
379 if (invalidate_domains
) {
380 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
381 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
382 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
383 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
384 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
385 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
386 flags
|= PIPE_CONTROL_QW_WRITE
;
387 flags
|= PIPE_CONTROL_GLOBAL_GTT_IVB
;
390 ret
= intel_ring_begin(ring
, 6);
394 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(6));
395 intel_ring_emit(ring
, flags
);
396 intel_ring_emit(ring
, scratch_addr
);
397 intel_ring_emit(ring
, 0);
398 intel_ring_emit(ring
, 0);
399 intel_ring_emit(ring
, 0);
400 intel_ring_advance(ring
);
406 static void ring_write_tail(struct intel_ring_buffer
*ring
,
409 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
410 I915_WRITE_TAIL(ring
, value
);
413 u64
intel_ring_get_active_head(struct intel_ring_buffer
*ring
)
415 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
418 if (INTEL_INFO(ring
->dev
)->gen
>= 8)
419 acthd
= I915_READ64_2x32(RING_ACTHD(ring
->mmio_base
),
420 RING_ACTHD_UDW(ring
->mmio_base
));
421 else if (INTEL_INFO(ring
->dev
)->gen
>= 4)
422 acthd
= I915_READ(RING_ACTHD(ring
->mmio_base
));
424 acthd
= I915_READ(ACTHD
);
429 static void ring_setup_phys_status_page(struct intel_ring_buffer
*ring
)
431 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
434 addr
= dev_priv
->status_page_dmah
->busaddr
;
435 if (INTEL_INFO(ring
->dev
)->gen
>= 4)
436 addr
|= (dev_priv
->status_page_dmah
->busaddr
>> 28) & 0xf0;
437 I915_WRITE(HWS_PGA
, addr
);
440 static int init_ring_common(struct intel_ring_buffer
*ring
)
442 struct drm_device
*dev
= ring
->dev
;
443 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
444 struct drm_i915_gem_object
*obj
= ring
->obj
;
448 gen6_gt_force_wake_get(dev_priv
, FORCEWAKE_ALL
);
450 /* Stop the ring if it's running. */
451 I915_WRITE_CTL(ring
, 0);
452 I915_WRITE_HEAD(ring
, 0);
453 ring
->write_tail(ring
, 0);
454 if (wait_for_atomic((I915_READ_MODE(ring
) & MODE_IDLE
) != 0, 1000))
455 DRM_ERROR("%s :timed out trying to stop ring\n", ring
->name
);
457 if (I915_NEED_GFX_HWS(dev
))
458 intel_ring_setup_status_page(ring
);
460 ring_setup_phys_status_page(ring
);
462 head
= I915_READ_HEAD(ring
) & HEAD_ADDR
;
464 /* G45 ring initialization fails to reset head to zero */
466 DRM_DEBUG_KMS("%s head not reset to zero "
467 "ctl %08x head %08x tail %08x start %08x\n",
470 I915_READ_HEAD(ring
),
471 I915_READ_TAIL(ring
),
472 I915_READ_START(ring
));
474 I915_WRITE_HEAD(ring
, 0);
476 if (I915_READ_HEAD(ring
) & HEAD_ADDR
) {
477 DRM_ERROR("failed to set %s head to zero "
478 "ctl %08x head %08x tail %08x start %08x\n",
481 I915_READ_HEAD(ring
),
482 I915_READ_TAIL(ring
),
483 I915_READ_START(ring
));
487 /* Initialize the ring. This must happen _after_ we've cleared the ring
488 * registers with the above sequence (the readback of the HEAD registers
489 * also enforces ordering), otherwise the hw might lose the new ring
490 * register values. */
491 I915_WRITE_START(ring
, i915_gem_obj_ggtt_offset(obj
));
493 ((ring
->size
- PAGE_SIZE
) & RING_NR_PAGES
)
496 /* If the head is still not zero, the ring is dead */
497 if (wait_for((I915_READ_CTL(ring
) & RING_VALID
) != 0 &&
498 I915_READ_START(ring
) == i915_gem_obj_ggtt_offset(obj
) &&
499 (I915_READ_HEAD(ring
) & HEAD_ADDR
) == 0, 50)) {
500 DRM_ERROR("%s initialization failed "
501 "ctl %08x head %08x tail %08x start %08x\n",
504 I915_READ_HEAD(ring
),
505 I915_READ_TAIL(ring
),
506 I915_READ_START(ring
));
511 if (!drm_core_check_feature(ring
->dev
, DRIVER_MODESET
))
512 i915_kernel_lost_context(ring
->dev
);
514 ring
->head
= I915_READ_HEAD(ring
);
515 ring
->tail
= I915_READ_TAIL(ring
) & TAIL_ADDR
;
516 ring
->space
= ring_space(ring
);
517 ring
->last_retired_head
= -1;
520 memset(&ring
->hangcheck
, 0, sizeof(ring
->hangcheck
));
523 gen6_gt_force_wake_put(dev_priv
, FORCEWAKE_ALL
);
529 init_pipe_control(struct intel_ring_buffer
*ring
)
533 if (ring
->scratch
.obj
)
536 ring
->scratch
.obj
= i915_gem_alloc_object(ring
->dev
, 4096);
537 if (ring
->scratch
.obj
== NULL
) {
538 DRM_ERROR("Failed to allocate seqno page\n");
543 ret
= i915_gem_object_set_cache_level(ring
->scratch
.obj
, I915_CACHE_LLC
);
547 ret
= i915_gem_obj_ggtt_pin(ring
->scratch
.obj
, 4096, 0);
551 ring
->scratch
.gtt_offset
= i915_gem_obj_ggtt_offset(ring
->scratch
.obj
);
552 ring
->scratch
.cpu_page
= kmap(sg_page(ring
->scratch
.obj
->pages
->sgl
));
553 if (ring
->scratch
.cpu_page
== NULL
) {
558 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
559 ring
->name
, ring
->scratch
.gtt_offset
);
563 i915_gem_object_ggtt_unpin(ring
->scratch
.obj
);
565 drm_gem_object_unreference(&ring
->scratch
.obj
->base
);
570 static int init_render_ring(struct intel_ring_buffer
*ring
)
572 struct drm_device
*dev
= ring
->dev
;
573 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
574 int ret
= init_ring_common(ring
);
576 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
577 if (INTEL_INFO(dev
)->gen
>= 4 && INTEL_INFO(dev
)->gen
< 7)
578 I915_WRITE(MI_MODE
, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH
));
580 /* We need to disable the AsyncFlip performance optimisations in order
581 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
582 * programmed to '1' on all products.
584 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw
586 if (INTEL_INFO(dev
)->gen
>= 6)
587 I915_WRITE(MI_MODE
, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE
));
589 /* Required for the hardware to program scanline values for waiting */
590 if (INTEL_INFO(dev
)->gen
== 6)
592 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_ALWAYS
));
595 I915_WRITE(GFX_MODE_GEN7
,
596 _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS
) |
597 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE
));
599 if (INTEL_INFO(dev
)->gen
>= 5) {
600 ret
= init_pipe_control(ring
);
606 /* From the Sandybridge PRM, volume 1 part 3, page 24:
607 * "If this bit is set, STCunit will have LRA as replacement
608 * policy. [...] This bit must be reset. LRA replacement
609 * policy is not supported."
611 I915_WRITE(CACHE_MODE_0
,
612 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB
));
614 /* This is not explicitly set for GEN6, so read the register.
615 * see intel_ring_mi_set_context() for why we care.
616 * TODO: consider explicitly setting the bit for GEN5
618 ring
->itlb_before_ctx_switch
=
619 !!(I915_READ(GFX_MODE
) & GFX_TLB_INVALIDATE_ALWAYS
);
622 if (INTEL_INFO(dev
)->gen
>= 6)
623 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING
));
626 I915_WRITE_IMR(ring
, ~GT_PARITY_ERROR(dev
));
631 static void render_ring_cleanup(struct intel_ring_buffer
*ring
)
633 struct drm_device
*dev
= ring
->dev
;
635 if (ring
->scratch
.obj
== NULL
)
638 if (INTEL_INFO(dev
)->gen
>= 5) {
639 kunmap(sg_page(ring
->scratch
.obj
->pages
->sgl
));
640 i915_gem_object_ggtt_unpin(ring
->scratch
.obj
);
643 drm_gem_object_unreference(&ring
->scratch
.obj
->base
);
644 ring
->scratch
.obj
= NULL
;
648 update_mboxes(struct intel_ring_buffer
*ring
,
651 /* NB: In order to be able to do semaphore MBOX updates for varying number
652 * of rings, it's easiest if we round up each individual update to a
653 * multiple of 2 (since ring updates must always be a multiple of 2)
654 * even though the actual update only requires 3 dwords.
656 #define MBOX_UPDATE_DWORDS 4
657 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
658 intel_ring_emit(ring
, mmio_offset
);
659 intel_ring_emit(ring
, ring
->outstanding_lazy_seqno
);
660 intel_ring_emit(ring
, MI_NOOP
);
664 * gen6_add_request - Update the semaphore mailbox registers
666 * @ring - ring that is adding a request
667 * @seqno - return seqno stuck into the ring
669 * Update the mailbox registers in the *other* rings with the current seqno.
670 * This acts like a signal in the canonical semaphore.
673 gen6_add_request(struct intel_ring_buffer
*ring
)
675 struct drm_device
*dev
= ring
->dev
;
676 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
677 struct intel_ring_buffer
*useless
;
678 int i
, ret
, num_dwords
= 4;
680 if (i915_semaphore_is_enabled(dev
))
681 num_dwords
+= ((I915_NUM_RINGS
-1) * MBOX_UPDATE_DWORDS
);
682 #undef MBOX_UPDATE_DWORDS
684 ret
= intel_ring_begin(ring
, num_dwords
);
688 if (i915_semaphore_is_enabled(dev
)) {
689 for_each_ring(useless
, dev_priv
, i
) {
690 u32 mbox_reg
= ring
->signal_mbox
[i
];
691 if (mbox_reg
!= GEN6_NOSYNC
)
692 update_mboxes(ring
, mbox_reg
);
696 intel_ring_emit(ring
, MI_STORE_DWORD_INDEX
);
697 intel_ring_emit(ring
, I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
698 intel_ring_emit(ring
, ring
->outstanding_lazy_seqno
);
699 intel_ring_emit(ring
, MI_USER_INTERRUPT
);
700 __intel_ring_advance(ring
);
705 static inline bool i915_gem_has_seqno_wrapped(struct drm_device
*dev
,
708 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
709 return dev_priv
->last_seqno
< seqno
;
713 * intel_ring_sync - sync the waiter to the signaller on seqno
715 * @waiter - ring that is waiting
716 * @signaller - ring which has, or will signal
717 * @seqno - seqno which the waiter will block on
720 gen6_ring_sync(struct intel_ring_buffer
*waiter
,
721 struct intel_ring_buffer
*signaller
,
725 u32 dw1
= MI_SEMAPHORE_MBOX
|
726 MI_SEMAPHORE_COMPARE
|
727 MI_SEMAPHORE_REGISTER
;
729 /* Throughout all of the GEM code, seqno passed implies our current
730 * seqno is >= the last seqno executed. However for hardware the
731 * comparison is strictly greater than.
735 WARN_ON(signaller
->semaphore_register
[waiter
->id
] ==
736 MI_SEMAPHORE_SYNC_INVALID
);
738 ret
= intel_ring_begin(waiter
, 4);
742 /* If seqno wrap happened, omit the wait with no-ops */
743 if (likely(!i915_gem_has_seqno_wrapped(waiter
->dev
, seqno
))) {
744 intel_ring_emit(waiter
,
746 signaller
->semaphore_register
[waiter
->id
]);
747 intel_ring_emit(waiter
, seqno
);
748 intel_ring_emit(waiter
, 0);
749 intel_ring_emit(waiter
, MI_NOOP
);
751 intel_ring_emit(waiter
, MI_NOOP
);
752 intel_ring_emit(waiter
, MI_NOOP
);
753 intel_ring_emit(waiter
, MI_NOOP
);
754 intel_ring_emit(waiter
, MI_NOOP
);
756 intel_ring_advance(waiter
);
761 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
763 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
764 PIPE_CONTROL_DEPTH_STALL); \
765 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
766 intel_ring_emit(ring__, 0); \
767 intel_ring_emit(ring__, 0); \
771 pc_render_add_request(struct intel_ring_buffer
*ring
)
773 u32 scratch_addr
= ring
->scratch
.gtt_offset
+ 128;
776 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
777 * incoherent with writes to memory, i.e. completely fubar,
778 * so we need to use PIPE_NOTIFY instead.
780 * However, we also need to workaround the qword write
781 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
782 * memory before requesting an interrupt.
784 ret
= intel_ring_begin(ring
, 32);
788 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE
|
789 PIPE_CONTROL_WRITE_FLUSH
|
790 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
);
791 intel_ring_emit(ring
, ring
->scratch
.gtt_offset
| PIPE_CONTROL_GLOBAL_GTT
);
792 intel_ring_emit(ring
, ring
->outstanding_lazy_seqno
);
793 intel_ring_emit(ring
, 0);
794 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
795 scratch_addr
+= 128; /* write to separate cachelines */
796 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
798 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
800 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
802 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
804 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
806 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE
|
807 PIPE_CONTROL_WRITE_FLUSH
|
808 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
809 PIPE_CONTROL_NOTIFY
);
810 intel_ring_emit(ring
, ring
->scratch
.gtt_offset
| PIPE_CONTROL_GLOBAL_GTT
);
811 intel_ring_emit(ring
, ring
->outstanding_lazy_seqno
);
812 intel_ring_emit(ring
, 0);
813 __intel_ring_advance(ring
);
819 gen6_ring_get_seqno(struct intel_ring_buffer
*ring
, bool lazy_coherency
)
821 /* Workaround to force correct ordering between irq and seqno writes on
822 * ivb (and maybe also on snb) by reading from a CS register (like
823 * ACTHD) before reading the status page. */
824 if (!lazy_coherency
) {
825 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
826 POSTING_READ(RING_ACTHD(ring
->mmio_base
));
829 return intel_read_status_page(ring
, I915_GEM_HWS_INDEX
);
833 ring_get_seqno(struct intel_ring_buffer
*ring
, bool lazy_coherency
)
835 return intel_read_status_page(ring
, I915_GEM_HWS_INDEX
);
839 ring_set_seqno(struct intel_ring_buffer
*ring
, u32 seqno
)
841 intel_write_status_page(ring
, I915_GEM_HWS_INDEX
, seqno
);
845 pc_render_get_seqno(struct intel_ring_buffer
*ring
, bool lazy_coherency
)
847 return ring
->scratch
.cpu_page
[0];
851 pc_render_set_seqno(struct intel_ring_buffer
*ring
, u32 seqno
)
853 ring
->scratch
.cpu_page
[0] = seqno
;
857 gen5_ring_get_irq(struct intel_ring_buffer
*ring
)
859 struct drm_device
*dev
= ring
->dev
;
860 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
863 if (!dev
->irq_enabled
)
866 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
867 if (ring
->irq_refcount
++ == 0)
868 ilk_enable_gt_irq(dev_priv
, ring
->irq_enable_mask
);
869 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
875 gen5_ring_put_irq(struct intel_ring_buffer
*ring
)
877 struct drm_device
*dev
= ring
->dev
;
878 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
881 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
882 if (--ring
->irq_refcount
== 0)
883 ilk_disable_gt_irq(dev_priv
, ring
->irq_enable_mask
);
884 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
888 i9xx_ring_get_irq(struct intel_ring_buffer
*ring
)
890 struct drm_device
*dev
= ring
->dev
;
891 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
894 if (!dev
->irq_enabled
)
897 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
898 if (ring
->irq_refcount
++ == 0) {
899 dev_priv
->irq_mask
&= ~ring
->irq_enable_mask
;
900 I915_WRITE(IMR
, dev_priv
->irq_mask
);
903 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
909 i9xx_ring_put_irq(struct intel_ring_buffer
*ring
)
911 struct drm_device
*dev
= ring
->dev
;
912 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
915 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
916 if (--ring
->irq_refcount
== 0) {
917 dev_priv
->irq_mask
|= ring
->irq_enable_mask
;
918 I915_WRITE(IMR
, dev_priv
->irq_mask
);
921 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
925 i8xx_ring_get_irq(struct intel_ring_buffer
*ring
)
927 struct drm_device
*dev
= ring
->dev
;
928 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
931 if (!dev
->irq_enabled
)
934 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
935 if (ring
->irq_refcount
++ == 0) {
936 dev_priv
->irq_mask
&= ~ring
->irq_enable_mask
;
937 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
940 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
946 i8xx_ring_put_irq(struct intel_ring_buffer
*ring
)
948 struct drm_device
*dev
= ring
->dev
;
949 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
952 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
953 if (--ring
->irq_refcount
== 0) {
954 dev_priv
->irq_mask
|= ring
->irq_enable_mask
;
955 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
958 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
961 void intel_ring_setup_status_page(struct intel_ring_buffer
*ring
)
963 struct drm_device
*dev
= ring
->dev
;
964 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
967 /* The ring status page addresses are no longer next to the rest of
968 * the ring registers as of gen7.
973 mmio
= RENDER_HWS_PGA_GEN7
;
976 mmio
= BLT_HWS_PGA_GEN7
;
979 mmio
= BSD_HWS_PGA_GEN7
;
982 mmio
= VEBOX_HWS_PGA_GEN7
;
985 } else if (IS_GEN6(ring
->dev
)) {
986 mmio
= RING_HWS_PGA_GEN6(ring
->mmio_base
);
988 /* XXX: gen8 returns to sanity */
989 mmio
= RING_HWS_PGA(ring
->mmio_base
);
992 I915_WRITE(mmio
, (u32
)ring
->status_page
.gfx_addr
);
996 * Flush the TLB for this page
998 * FIXME: These two bits have disappeared on gen8, so a question
999 * arises: do we still need this and if so how should we go about
1000 * invalidating the TLB?
1002 if (INTEL_INFO(dev
)->gen
>= 6 && INTEL_INFO(dev
)->gen
< 8) {
1003 u32 reg
= RING_INSTPM(ring
->mmio_base
);
1005 /* ring should be idle before issuing a sync flush*/
1006 WARN_ON((I915_READ_MODE(ring
) & MODE_IDLE
) == 0);
1009 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE
|
1010 INSTPM_SYNC_FLUSH
));
1011 if (wait_for((I915_READ(reg
) & INSTPM_SYNC_FLUSH
) == 0,
1013 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
1019 bsd_ring_flush(struct intel_ring_buffer
*ring
,
1020 u32 invalidate_domains
,
1025 ret
= intel_ring_begin(ring
, 2);
1029 intel_ring_emit(ring
, MI_FLUSH
);
1030 intel_ring_emit(ring
, MI_NOOP
);
1031 intel_ring_advance(ring
);
1036 i9xx_add_request(struct intel_ring_buffer
*ring
)
1040 ret
= intel_ring_begin(ring
, 4);
1044 intel_ring_emit(ring
, MI_STORE_DWORD_INDEX
);
1045 intel_ring_emit(ring
, I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
1046 intel_ring_emit(ring
, ring
->outstanding_lazy_seqno
);
1047 intel_ring_emit(ring
, MI_USER_INTERRUPT
);
1048 __intel_ring_advance(ring
);
1054 gen6_ring_get_irq(struct intel_ring_buffer
*ring
)
1056 struct drm_device
*dev
= ring
->dev
;
1057 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1058 unsigned long flags
;
1060 if (!dev
->irq_enabled
)
1063 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1064 if (ring
->irq_refcount
++ == 0) {
1065 if (HAS_L3_DPF(dev
) && ring
->id
== RCS
)
1066 I915_WRITE_IMR(ring
,
1067 ~(ring
->irq_enable_mask
|
1068 GT_PARITY_ERROR(dev
)));
1070 I915_WRITE_IMR(ring
, ~ring
->irq_enable_mask
);
1071 ilk_enable_gt_irq(dev_priv
, ring
->irq_enable_mask
);
1073 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1079 gen6_ring_put_irq(struct intel_ring_buffer
*ring
)
1081 struct drm_device
*dev
= ring
->dev
;
1082 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1083 unsigned long flags
;
1085 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1086 if (--ring
->irq_refcount
== 0) {
1087 if (HAS_L3_DPF(dev
) && ring
->id
== RCS
)
1088 I915_WRITE_IMR(ring
, ~GT_PARITY_ERROR(dev
));
1090 I915_WRITE_IMR(ring
, ~0);
1091 ilk_disable_gt_irq(dev_priv
, ring
->irq_enable_mask
);
1093 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1097 hsw_vebox_get_irq(struct intel_ring_buffer
*ring
)
1099 struct drm_device
*dev
= ring
->dev
;
1100 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1101 unsigned long flags
;
1103 if (!dev
->irq_enabled
)
1106 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1107 if (ring
->irq_refcount
++ == 0) {
1108 I915_WRITE_IMR(ring
, ~ring
->irq_enable_mask
);
1109 snb_enable_pm_irq(dev_priv
, ring
->irq_enable_mask
);
1111 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1117 hsw_vebox_put_irq(struct intel_ring_buffer
*ring
)
1119 struct drm_device
*dev
= ring
->dev
;
1120 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1121 unsigned long flags
;
1123 if (!dev
->irq_enabled
)
1126 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1127 if (--ring
->irq_refcount
== 0) {
1128 I915_WRITE_IMR(ring
, ~0);
1129 snb_disable_pm_irq(dev_priv
, ring
->irq_enable_mask
);
1131 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1135 gen8_ring_get_irq(struct intel_ring_buffer
*ring
)
1137 struct drm_device
*dev
= ring
->dev
;
1138 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1139 unsigned long flags
;
1141 if (!dev
->irq_enabled
)
1144 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1145 if (ring
->irq_refcount
++ == 0) {
1146 if (HAS_L3_DPF(dev
) && ring
->id
== RCS
) {
1147 I915_WRITE_IMR(ring
,
1148 ~(ring
->irq_enable_mask
|
1149 GT_RENDER_L3_PARITY_ERROR_INTERRUPT
));
1151 I915_WRITE_IMR(ring
, ~ring
->irq_enable_mask
);
1153 POSTING_READ(RING_IMR(ring
->mmio_base
));
1155 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1161 gen8_ring_put_irq(struct intel_ring_buffer
*ring
)
1163 struct drm_device
*dev
= ring
->dev
;
1164 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1165 unsigned long flags
;
1167 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1168 if (--ring
->irq_refcount
== 0) {
1169 if (HAS_L3_DPF(dev
) && ring
->id
== RCS
) {
1170 I915_WRITE_IMR(ring
,
1171 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT
);
1173 I915_WRITE_IMR(ring
, ~0);
1175 POSTING_READ(RING_IMR(ring
->mmio_base
));
1177 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1181 i965_dispatch_execbuffer(struct intel_ring_buffer
*ring
,
1182 u32 offset
, u32 length
,
1187 ret
= intel_ring_begin(ring
, 2);
1191 intel_ring_emit(ring
,
1192 MI_BATCH_BUFFER_START
|
1194 (flags
& I915_DISPATCH_SECURE
? 0 : MI_BATCH_NON_SECURE_I965
));
1195 intel_ring_emit(ring
, offset
);
1196 intel_ring_advance(ring
);
1201 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1202 #define I830_BATCH_LIMIT (256*1024)
1204 i830_dispatch_execbuffer(struct intel_ring_buffer
*ring
,
1205 u32 offset
, u32 len
,
1210 if (flags
& I915_DISPATCH_PINNED
) {
1211 ret
= intel_ring_begin(ring
, 4);
1215 intel_ring_emit(ring
, MI_BATCH_BUFFER
);
1216 intel_ring_emit(ring
, offset
| (flags
& I915_DISPATCH_SECURE
? 0 : MI_BATCH_NON_SECURE
));
1217 intel_ring_emit(ring
, offset
+ len
- 8);
1218 intel_ring_emit(ring
, MI_NOOP
);
1219 intel_ring_advance(ring
);
1221 u32 cs_offset
= ring
->scratch
.gtt_offset
;
1223 if (len
> I830_BATCH_LIMIT
)
1226 ret
= intel_ring_begin(ring
, 9+3);
1229 /* Blit the batch (which has now all relocs applied) to the stable batch
1230 * scratch bo area (so that the CS never stumbles over its tlb
1231 * invalidation bug) ... */
1232 intel_ring_emit(ring
, XY_SRC_COPY_BLT_CMD
|
1233 XY_SRC_COPY_BLT_WRITE_ALPHA
|
1234 XY_SRC_COPY_BLT_WRITE_RGB
);
1235 intel_ring_emit(ring
, BLT_DEPTH_32
| BLT_ROP_GXCOPY
| 4096);
1236 intel_ring_emit(ring
, 0);
1237 intel_ring_emit(ring
, (DIV_ROUND_UP(len
, 4096) << 16) | 1024);
1238 intel_ring_emit(ring
, cs_offset
);
1239 intel_ring_emit(ring
, 0);
1240 intel_ring_emit(ring
, 4096);
1241 intel_ring_emit(ring
, offset
);
1242 intel_ring_emit(ring
, MI_FLUSH
);
1244 /* ... and execute it. */
1245 intel_ring_emit(ring
, MI_BATCH_BUFFER
);
1246 intel_ring_emit(ring
, cs_offset
| (flags
& I915_DISPATCH_SECURE
? 0 : MI_BATCH_NON_SECURE
));
1247 intel_ring_emit(ring
, cs_offset
+ len
- 8);
1248 intel_ring_advance(ring
);
1255 i915_dispatch_execbuffer(struct intel_ring_buffer
*ring
,
1256 u32 offset
, u32 len
,
1261 ret
= intel_ring_begin(ring
, 2);
1265 intel_ring_emit(ring
, MI_BATCH_BUFFER_START
| MI_BATCH_GTT
);
1266 intel_ring_emit(ring
, offset
| (flags
& I915_DISPATCH_SECURE
? 0 : MI_BATCH_NON_SECURE
));
1267 intel_ring_advance(ring
);
1272 static void cleanup_status_page(struct intel_ring_buffer
*ring
)
1274 struct drm_i915_gem_object
*obj
;
1276 obj
= ring
->status_page
.obj
;
1280 kunmap(sg_page(obj
->pages
->sgl
));
1281 i915_gem_object_ggtt_unpin(obj
);
1282 drm_gem_object_unreference(&obj
->base
);
1283 ring
->status_page
.obj
= NULL
;
1286 static int init_status_page(struct intel_ring_buffer
*ring
)
1288 struct drm_device
*dev
= ring
->dev
;
1289 struct drm_i915_gem_object
*obj
;
1292 obj
= i915_gem_alloc_object(dev
, 4096);
1294 DRM_ERROR("Failed to allocate status page\n");
1299 ret
= i915_gem_object_set_cache_level(obj
, I915_CACHE_LLC
);
1303 ret
= i915_gem_obj_ggtt_pin(obj
, 4096, 0);
1307 ring
->status_page
.gfx_addr
= i915_gem_obj_ggtt_offset(obj
);
1308 ring
->status_page
.page_addr
= kmap(sg_page(obj
->pages
->sgl
));
1309 if (ring
->status_page
.page_addr
== NULL
) {
1313 ring
->status_page
.obj
= obj
;
1314 memset(ring
->status_page
.page_addr
, 0, PAGE_SIZE
);
1316 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1317 ring
->name
, ring
->status_page
.gfx_addr
);
1322 i915_gem_object_ggtt_unpin(obj
);
1324 drm_gem_object_unreference(&obj
->base
);
1329 static int init_phys_status_page(struct intel_ring_buffer
*ring
)
1331 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1333 if (!dev_priv
->status_page_dmah
) {
1334 dev_priv
->status_page_dmah
=
1335 drm_pci_alloc(ring
->dev
, PAGE_SIZE
, PAGE_SIZE
);
1336 if (!dev_priv
->status_page_dmah
)
1340 ring
->status_page
.page_addr
= dev_priv
->status_page_dmah
->vaddr
;
1341 memset(ring
->status_page
.page_addr
, 0, PAGE_SIZE
);
1346 static int intel_init_ring_buffer(struct drm_device
*dev
,
1347 struct intel_ring_buffer
*ring
)
1349 struct drm_i915_gem_object
*obj
;
1350 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1354 INIT_LIST_HEAD(&ring
->active_list
);
1355 INIT_LIST_HEAD(&ring
->request_list
);
1356 ring
->size
= 32 * PAGE_SIZE
;
1357 memset(ring
->sync_seqno
, 0, sizeof(ring
->sync_seqno
));
1359 init_waitqueue_head(&ring
->irq_queue
);
1361 if (I915_NEED_GFX_HWS(dev
)) {
1362 ret
= init_status_page(ring
);
1366 BUG_ON(ring
->id
!= RCS
);
1367 ret
= init_phys_status_page(ring
);
1374 obj
= i915_gem_object_create_stolen(dev
, ring
->size
);
1376 obj
= i915_gem_alloc_object(dev
, ring
->size
);
1378 DRM_ERROR("Failed to allocate ringbuffer\n");
1385 ret
= i915_gem_obj_ggtt_pin(obj
, PAGE_SIZE
, PIN_MAPPABLE
);
1389 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
1393 ring
->virtual_start
=
1394 ioremap_wc(dev_priv
->gtt
.mappable_base
+ i915_gem_obj_ggtt_offset(obj
),
1396 if (ring
->virtual_start
== NULL
) {
1397 DRM_ERROR("Failed to map ringbuffer.\n");
1402 ret
= ring
->init(ring
);
1406 /* Workaround an erratum on the i830 which causes a hang if
1407 * the TAIL pointer points to within the last 2 cachelines
1410 ring
->effective_size
= ring
->size
;
1411 if (IS_I830(ring
->dev
) || IS_845G(ring
->dev
))
1412 ring
->effective_size
-= 128;
1414 i915_cmd_parser_init_ring(ring
);
1419 iounmap(ring
->virtual_start
);
1421 i915_gem_object_ggtt_unpin(obj
);
1423 drm_gem_object_unreference(&obj
->base
);
1426 cleanup_status_page(ring
);
1430 void intel_cleanup_ring_buffer(struct intel_ring_buffer
*ring
)
1432 struct drm_i915_private
*dev_priv
;
1435 if (ring
->obj
== NULL
)
1438 /* Disable the ring buffer. The ring must be idle at this point */
1439 dev_priv
= ring
->dev
->dev_private
;
1440 ret
= intel_ring_idle(ring
);
1441 if (ret
&& !i915_reset_in_progress(&dev_priv
->gpu_error
))
1442 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1445 I915_WRITE_CTL(ring
, 0);
1447 iounmap(ring
->virtual_start
);
1449 i915_gem_object_ggtt_unpin(ring
->obj
);
1450 drm_gem_object_unreference(&ring
->obj
->base
);
1452 ring
->preallocated_lazy_request
= NULL
;
1453 ring
->outstanding_lazy_seqno
= 0;
1456 ring
->cleanup(ring
);
1458 cleanup_status_page(ring
);
1461 static int intel_ring_wait_request(struct intel_ring_buffer
*ring
, int n
)
1463 struct drm_i915_gem_request
*request
;
1464 u32 seqno
= 0, tail
;
1467 if (ring
->last_retired_head
!= -1) {
1468 ring
->head
= ring
->last_retired_head
;
1469 ring
->last_retired_head
= -1;
1471 ring
->space
= ring_space(ring
);
1472 if (ring
->space
>= n
)
1476 list_for_each_entry(request
, &ring
->request_list
, list
) {
1479 if (request
->tail
== -1)
1482 space
= request
->tail
- (ring
->tail
+ I915_RING_FREE_SPACE
);
1484 space
+= ring
->size
;
1486 seqno
= request
->seqno
;
1487 tail
= request
->tail
;
1491 /* Consume this request in case we need more space than
1492 * is available and so need to prevent a race between
1493 * updating last_retired_head and direct reads of
1494 * I915_RING_HEAD. It also provides a nice sanity check.
1502 ret
= i915_wait_seqno(ring
, seqno
);
1507 ring
->space
= ring_space(ring
);
1508 if (WARN_ON(ring
->space
< n
))
1514 static int ring_wait_for_space(struct intel_ring_buffer
*ring
, int n
)
1516 struct drm_device
*dev
= ring
->dev
;
1517 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1521 ret
= intel_ring_wait_request(ring
, n
);
1525 /* force the tail write in case we have been skipping them */
1526 __intel_ring_advance(ring
);
1528 trace_i915_ring_wait_begin(ring
);
1529 /* With GEM the hangcheck timer should kick us out of the loop,
1530 * leaving it early runs the risk of corrupting GEM state (due
1531 * to running on almost untested codepaths). But on resume
1532 * timers don't work yet, so prevent a complete hang in that
1533 * case by choosing an insanely large timeout. */
1534 end
= jiffies
+ 60 * HZ
;
1537 ring
->head
= I915_READ_HEAD(ring
);
1538 ring
->space
= ring_space(ring
);
1539 if (ring
->space
>= n
) {
1540 trace_i915_ring_wait_end(ring
);
1544 if (!drm_core_check_feature(dev
, DRIVER_MODESET
) &&
1545 dev
->primary
->master
) {
1546 struct drm_i915_master_private
*master_priv
= dev
->primary
->master
->driver_priv
;
1547 if (master_priv
->sarea_priv
)
1548 master_priv
->sarea_priv
->perf_boxes
|= I915_BOX_WAIT
;
1553 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
,
1554 dev_priv
->mm
.interruptible
);
1557 } while (!time_after(jiffies
, end
));
1558 trace_i915_ring_wait_end(ring
);
1562 static int intel_wrap_ring_buffer(struct intel_ring_buffer
*ring
)
1564 uint32_t __iomem
*virt
;
1565 int rem
= ring
->size
- ring
->tail
;
1567 if (ring
->space
< rem
) {
1568 int ret
= ring_wait_for_space(ring
, rem
);
1573 virt
= ring
->virtual_start
+ ring
->tail
;
1576 iowrite32(MI_NOOP
, virt
++);
1579 ring
->space
= ring_space(ring
);
1584 int intel_ring_idle(struct intel_ring_buffer
*ring
)
1589 /* We need to add any requests required to flush the objects and ring */
1590 if (ring
->outstanding_lazy_seqno
) {
1591 ret
= i915_add_request(ring
, NULL
);
1596 /* Wait upon the last request to be completed */
1597 if (list_empty(&ring
->request_list
))
1600 seqno
= list_entry(ring
->request_list
.prev
,
1601 struct drm_i915_gem_request
,
1604 return i915_wait_seqno(ring
, seqno
);
1608 intel_ring_alloc_seqno(struct intel_ring_buffer
*ring
)
1610 if (ring
->outstanding_lazy_seqno
)
1613 if (ring
->preallocated_lazy_request
== NULL
) {
1614 struct drm_i915_gem_request
*request
;
1616 request
= kmalloc(sizeof(*request
), GFP_KERNEL
);
1617 if (request
== NULL
)
1620 ring
->preallocated_lazy_request
= request
;
1623 return i915_gem_get_seqno(ring
->dev
, &ring
->outstanding_lazy_seqno
);
1626 static int __intel_ring_prepare(struct intel_ring_buffer
*ring
,
1631 if (unlikely(ring
->tail
+ bytes
> ring
->effective_size
)) {
1632 ret
= intel_wrap_ring_buffer(ring
);
1637 if (unlikely(ring
->space
< bytes
)) {
1638 ret
= ring_wait_for_space(ring
, bytes
);
1646 int intel_ring_begin(struct intel_ring_buffer
*ring
,
1649 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
1652 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
,
1653 dev_priv
->mm
.interruptible
);
1657 ret
= __intel_ring_prepare(ring
, num_dwords
* sizeof(uint32_t));
1661 /* Preallocate the olr before touching the ring */
1662 ret
= intel_ring_alloc_seqno(ring
);
1666 ring
->space
-= num_dwords
* sizeof(uint32_t);
1670 /* Align the ring tail to a cacheline boundary */
1671 int intel_ring_cacheline_align(struct intel_ring_buffer
*ring
)
1673 int num_dwords
= (64 - (ring
->tail
& 63)) / sizeof(uint32_t);
1676 if (num_dwords
== 0)
1679 ret
= intel_ring_begin(ring
, num_dwords
);
1683 while (num_dwords
--)
1684 intel_ring_emit(ring
, MI_NOOP
);
1686 intel_ring_advance(ring
);
1691 void intel_ring_init_seqno(struct intel_ring_buffer
*ring
, u32 seqno
)
1693 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1695 BUG_ON(ring
->outstanding_lazy_seqno
);
1697 if (INTEL_INFO(ring
->dev
)->gen
>= 6) {
1698 I915_WRITE(RING_SYNC_0(ring
->mmio_base
), 0);
1699 I915_WRITE(RING_SYNC_1(ring
->mmio_base
), 0);
1700 if (HAS_VEBOX(ring
->dev
))
1701 I915_WRITE(RING_SYNC_2(ring
->mmio_base
), 0);
1704 ring
->set_seqno(ring
, seqno
);
1705 ring
->hangcheck
.seqno
= seqno
;
1708 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer
*ring
,
1711 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
1713 /* Every tail move must follow the sequence below */
1715 /* Disable notification that the ring is IDLE. The GT
1716 * will then assume that it is busy and bring it out of rc6.
1718 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL
,
1719 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE
));
1721 /* Clear the context id. Here be magic! */
1722 I915_WRITE64(GEN6_BSD_RNCID
, 0x0);
1724 /* Wait for the ring not to be idle, i.e. for it to wake up. */
1725 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL
) &
1726 GEN6_BSD_SLEEP_INDICATOR
) == 0,
1728 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
1730 /* Now that the ring is fully powered up, update the tail */
1731 I915_WRITE_TAIL(ring
, value
);
1732 POSTING_READ(RING_TAIL(ring
->mmio_base
));
1734 /* Let the ring send IDLE messages to the GT again,
1735 * and so let it sleep to conserve power when idle.
1737 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL
,
1738 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE
));
1741 static int gen6_bsd_ring_flush(struct intel_ring_buffer
*ring
,
1742 u32 invalidate
, u32 flush
)
1747 ret
= intel_ring_begin(ring
, 4);
1752 if (INTEL_INFO(ring
->dev
)->gen
>= 8)
1755 * Bspec vol 1c.5 - video engine command streamer:
1756 * "If ENABLED, all TLBs will be invalidated once the flush
1757 * operation is complete. This bit is only valid when the
1758 * Post-Sync Operation field is a value of 1h or 3h."
1760 if (invalidate
& I915_GEM_GPU_DOMAINS
)
1761 cmd
|= MI_INVALIDATE_TLB
| MI_INVALIDATE_BSD
|
1762 MI_FLUSH_DW_STORE_INDEX
| MI_FLUSH_DW_OP_STOREDW
;
1763 intel_ring_emit(ring
, cmd
);
1764 intel_ring_emit(ring
, I915_GEM_HWS_SCRATCH_ADDR
| MI_FLUSH_DW_USE_GTT
);
1765 if (INTEL_INFO(ring
->dev
)->gen
>= 8) {
1766 intel_ring_emit(ring
, 0); /* upper addr */
1767 intel_ring_emit(ring
, 0); /* value */
1769 intel_ring_emit(ring
, 0);
1770 intel_ring_emit(ring
, MI_NOOP
);
1772 intel_ring_advance(ring
);
1777 gen8_ring_dispatch_execbuffer(struct intel_ring_buffer
*ring
,
1778 u32 offset
, u32 len
,
1781 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1782 bool ppgtt
= dev_priv
->mm
.aliasing_ppgtt
!= NULL
&&
1783 !(flags
& I915_DISPATCH_SECURE
);
1786 ret
= intel_ring_begin(ring
, 4);
1790 /* FIXME(BDW): Address space and security selectors. */
1791 intel_ring_emit(ring
, MI_BATCH_BUFFER_START_GEN8
| (ppgtt
<<8));
1792 intel_ring_emit(ring
, offset
);
1793 intel_ring_emit(ring
, 0);
1794 intel_ring_emit(ring
, MI_NOOP
);
1795 intel_ring_advance(ring
);
1801 hsw_ring_dispatch_execbuffer(struct intel_ring_buffer
*ring
,
1802 u32 offset
, u32 len
,
1807 ret
= intel_ring_begin(ring
, 2);
1811 intel_ring_emit(ring
,
1812 MI_BATCH_BUFFER_START
| MI_BATCH_PPGTT_HSW
|
1813 (flags
& I915_DISPATCH_SECURE
? 0 : MI_BATCH_NON_SECURE_HSW
));
1814 /* bit0-7 is the length on GEN6+ */
1815 intel_ring_emit(ring
, offset
);
1816 intel_ring_advance(ring
);
1822 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer
*ring
,
1823 u32 offset
, u32 len
,
1828 ret
= intel_ring_begin(ring
, 2);
1832 intel_ring_emit(ring
,
1833 MI_BATCH_BUFFER_START
|
1834 (flags
& I915_DISPATCH_SECURE
? 0 : MI_BATCH_NON_SECURE_I965
));
1835 /* bit0-7 is the length on GEN6+ */
1836 intel_ring_emit(ring
, offset
);
1837 intel_ring_advance(ring
);
1842 /* Blitter support (SandyBridge+) */
1844 static int gen6_ring_flush(struct intel_ring_buffer
*ring
,
1845 u32 invalidate
, u32 flush
)
1847 struct drm_device
*dev
= ring
->dev
;
1851 ret
= intel_ring_begin(ring
, 4);
1856 if (INTEL_INFO(ring
->dev
)->gen
>= 8)
1859 * Bspec vol 1c.3 - blitter engine command streamer:
1860 * "If ENABLED, all TLBs will be invalidated once the flush
1861 * operation is complete. This bit is only valid when the
1862 * Post-Sync Operation field is a value of 1h or 3h."
1864 if (invalidate
& I915_GEM_DOMAIN_RENDER
)
1865 cmd
|= MI_INVALIDATE_TLB
| MI_FLUSH_DW_STORE_INDEX
|
1866 MI_FLUSH_DW_OP_STOREDW
;
1867 intel_ring_emit(ring
, cmd
);
1868 intel_ring_emit(ring
, I915_GEM_HWS_SCRATCH_ADDR
| MI_FLUSH_DW_USE_GTT
);
1869 if (INTEL_INFO(ring
->dev
)->gen
>= 8) {
1870 intel_ring_emit(ring
, 0); /* upper addr */
1871 intel_ring_emit(ring
, 0); /* value */
1873 intel_ring_emit(ring
, 0);
1874 intel_ring_emit(ring
, MI_NOOP
);
1876 intel_ring_advance(ring
);
1878 if (IS_GEN7(dev
) && !invalidate
&& flush
)
1879 return gen7_ring_fbc_flush(ring
, FBC_REND_CACHE_CLEAN
);
1884 int intel_init_render_ring_buffer(struct drm_device
*dev
)
1886 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1887 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
1889 ring
->name
= "render ring";
1891 ring
->mmio_base
= RENDER_RING_BASE
;
1893 if (INTEL_INFO(dev
)->gen
>= 6) {
1894 ring
->add_request
= gen6_add_request
;
1895 ring
->flush
= gen7_render_ring_flush
;
1896 if (INTEL_INFO(dev
)->gen
== 6)
1897 ring
->flush
= gen6_render_ring_flush
;
1898 if (INTEL_INFO(dev
)->gen
>= 8) {
1899 ring
->flush
= gen8_render_ring_flush
;
1900 ring
->irq_get
= gen8_ring_get_irq
;
1901 ring
->irq_put
= gen8_ring_put_irq
;
1903 ring
->irq_get
= gen6_ring_get_irq
;
1904 ring
->irq_put
= gen6_ring_put_irq
;
1906 ring
->irq_enable_mask
= GT_RENDER_USER_INTERRUPT
;
1907 ring
->get_seqno
= gen6_ring_get_seqno
;
1908 ring
->set_seqno
= ring_set_seqno
;
1909 ring
->sync_to
= gen6_ring_sync
;
1910 ring
->semaphore_register
[RCS
] = MI_SEMAPHORE_SYNC_INVALID
;
1911 ring
->semaphore_register
[VCS
] = MI_SEMAPHORE_SYNC_RV
;
1912 ring
->semaphore_register
[BCS
] = MI_SEMAPHORE_SYNC_RB
;
1913 ring
->semaphore_register
[VECS
] = MI_SEMAPHORE_SYNC_RVE
;
1914 ring
->signal_mbox
[RCS
] = GEN6_NOSYNC
;
1915 ring
->signal_mbox
[VCS
] = GEN6_VRSYNC
;
1916 ring
->signal_mbox
[BCS
] = GEN6_BRSYNC
;
1917 ring
->signal_mbox
[VECS
] = GEN6_VERSYNC
;
1918 } else if (IS_GEN5(dev
)) {
1919 ring
->add_request
= pc_render_add_request
;
1920 ring
->flush
= gen4_render_ring_flush
;
1921 ring
->get_seqno
= pc_render_get_seqno
;
1922 ring
->set_seqno
= pc_render_set_seqno
;
1923 ring
->irq_get
= gen5_ring_get_irq
;
1924 ring
->irq_put
= gen5_ring_put_irq
;
1925 ring
->irq_enable_mask
= GT_RENDER_USER_INTERRUPT
|
1926 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
;
1928 ring
->add_request
= i9xx_add_request
;
1929 if (INTEL_INFO(dev
)->gen
< 4)
1930 ring
->flush
= gen2_render_ring_flush
;
1932 ring
->flush
= gen4_render_ring_flush
;
1933 ring
->get_seqno
= ring_get_seqno
;
1934 ring
->set_seqno
= ring_set_seqno
;
1936 ring
->irq_get
= i8xx_ring_get_irq
;
1937 ring
->irq_put
= i8xx_ring_put_irq
;
1939 ring
->irq_get
= i9xx_ring_get_irq
;
1940 ring
->irq_put
= i9xx_ring_put_irq
;
1942 ring
->irq_enable_mask
= I915_USER_INTERRUPT
;
1944 ring
->write_tail
= ring_write_tail
;
1945 if (IS_HASWELL(dev
))
1946 ring
->dispatch_execbuffer
= hsw_ring_dispatch_execbuffer
;
1947 else if (IS_GEN8(dev
))
1948 ring
->dispatch_execbuffer
= gen8_ring_dispatch_execbuffer
;
1949 else if (INTEL_INFO(dev
)->gen
>= 6)
1950 ring
->dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
;
1951 else if (INTEL_INFO(dev
)->gen
>= 4)
1952 ring
->dispatch_execbuffer
= i965_dispatch_execbuffer
;
1953 else if (IS_I830(dev
) || IS_845G(dev
))
1954 ring
->dispatch_execbuffer
= i830_dispatch_execbuffer
;
1956 ring
->dispatch_execbuffer
= i915_dispatch_execbuffer
;
1957 ring
->init
= init_render_ring
;
1958 ring
->cleanup
= render_ring_cleanup
;
1960 /* Workaround batchbuffer to combat CS tlb bug. */
1961 if (HAS_BROKEN_CS_TLB(dev
)) {
1962 struct drm_i915_gem_object
*obj
;
1965 obj
= i915_gem_alloc_object(dev
, I830_BATCH_LIMIT
);
1967 DRM_ERROR("Failed to allocate batch bo\n");
1971 ret
= i915_gem_obj_ggtt_pin(obj
, 0, 0);
1973 drm_gem_object_unreference(&obj
->base
);
1974 DRM_ERROR("Failed to ping batch bo\n");
1978 ring
->scratch
.obj
= obj
;
1979 ring
->scratch
.gtt_offset
= i915_gem_obj_ggtt_offset(obj
);
1982 return intel_init_ring_buffer(dev
, ring
);
1985 int intel_render_ring_init_dri(struct drm_device
*dev
, u64 start
, u32 size
)
1987 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1988 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
1991 ring
->name
= "render ring";
1993 ring
->mmio_base
= RENDER_RING_BASE
;
1995 if (INTEL_INFO(dev
)->gen
>= 6) {
1996 /* non-kms not supported on gen6+ */
2000 /* Note: gem is not supported on gen5/ilk without kms (the corresponding
2001 * gem_init ioctl returns with -ENODEV). Hence we do not need to set up
2002 * the special gen5 functions. */
2003 ring
->add_request
= i9xx_add_request
;
2004 if (INTEL_INFO(dev
)->gen
< 4)
2005 ring
->flush
= gen2_render_ring_flush
;
2007 ring
->flush
= gen4_render_ring_flush
;
2008 ring
->get_seqno
= ring_get_seqno
;
2009 ring
->set_seqno
= ring_set_seqno
;
2011 ring
->irq_get
= i8xx_ring_get_irq
;
2012 ring
->irq_put
= i8xx_ring_put_irq
;
2014 ring
->irq_get
= i9xx_ring_get_irq
;
2015 ring
->irq_put
= i9xx_ring_put_irq
;
2017 ring
->irq_enable_mask
= I915_USER_INTERRUPT
;
2018 ring
->write_tail
= ring_write_tail
;
2019 if (INTEL_INFO(dev
)->gen
>= 4)
2020 ring
->dispatch_execbuffer
= i965_dispatch_execbuffer
;
2021 else if (IS_I830(dev
) || IS_845G(dev
))
2022 ring
->dispatch_execbuffer
= i830_dispatch_execbuffer
;
2024 ring
->dispatch_execbuffer
= i915_dispatch_execbuffer
;
2025 ring
->init
= init_render_ring
;
2026 ring
->cleanup
= render_ring_cleanup
;
2029 INIT_LIST_HEAD(&ring
->active_list
);
2030 INIT_LIST_HEAD(&ring
->request_list
);
2033 ring
->effective_size
= ring
->size
;
2034 if (IS_I830(ring
->dev
) || IS_845G(ring
->dev
))
2035 ring
->effective_size
-= 128;
2037 ring
->virtual_start
= ioremap_wc(start
, size
);
2038 if (ring
->virtual_start
== NULL
) {
2039 DRM_ERROR("can not ioremap virtual address for"
2044 if (!I915_NEED_GFX_HWS(dev
)) {
2045 ret
= init_phys_status_page(ring
);
2053 int intel_init_bsd_ring_buffer(struct drm_device
*dev
)
2055 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2056 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[VCS
];
2058 ring
->name
= "bsd ring";
2061 ring
->write_tail
= ring_write_tail
;
2062 if (INTEL_INFO(dev
)->gen
>= 6) {
2063 ring
->mmio_base
= GEN6_BSD_RING_BASE
;
2064 /* gen6 bsd needs a special wa for tail updates */
2066 ring
->write_tail
= gen6_bsd_ring_write_tail
;
2067 ring
->flush
= gen6_bsd_ring_flush
;
2068 ring
->add_request
= gen6_add_request
;
2069 ring
->get_seqno
= gen6_ring_get_seqno
;
2070 ring
->set_seqno
= ring_set_seqno
;
2071 if (INTEL_INFO(dev
)->gen
>= 8) {
2072 ring
->irq_enable_mask
=
2073 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
;
2074 ring
->irq_get
= gen8_ring_get_irq
;
2075 ring
->irq_put
= gen8_ring_put_irq
;
2076 ring
->dispatch_execbuffer
=
2077 gen8_ring_dispatch_execbuffer
;
2079 ring
->irq_enable_mask
= GT_BSD_USER_INTERRUPT
;
2080 ring
->irq_get
= gen6_ring_get_irq
;
2081 ring
->irq_put
= gen6_ring_put_irq
;
2082 ring
->dispatch_execbuffer
=
2083 gen6_ring_dispatch_execbuffer
;
2085 ring
->sync_to
= gen6_ring_sync
;
2086 ring
->semaphore_register
[RCS
] = MI_SEMAPHORE_SYNC_VR
;
2087 ring
->semaphore_register
[VCS
] = MI_SEMAPHORE_SYNC_INVALID
;
2088 ring
->semaphore_register
[BCS
] = MI_SEMAPHORE_SYNC_VB
;
2089 ring
->semaphore_register
[VECS
] = MI_SEMAPHORE_SYNC_VVE
;
2090 ring
->signal_mbox
[RCS
] = GEN6_RVSYNC
;
2091 ring
->signal_mbox
[VCS
] = GEN6_NOSYNC
;
2092 ring
->signal_mbox
[BCS
] = GEN6_BVSYNC
;
2093 ring
->signal_mbox
[VECS
] = GEN6_VEVSYNC
;
2095 ring
->mmio_base
= BSD_RING_BASE
;
2096 ring
->flush
= bsd_ring_flush
;
2097 ring
->add_request
= i9xx_add_request
;
2098 ring
->get_seqno
= ring_get_seqno
;
2099 ring
->set_seqno
= ring_set_seqno
;
2101 ring
->irq_enable_mask
= ILK_BSD_USER_INTERRUPT
;
2102 ring
->irq_get
= gen5_ring_get_irq
;
2103 ring
->irq_put
= gen5_ring_put_irq
;
2105 ring
->irq_enable_mask
= I915_BSD_USER_INTERRUPT
;
2106 ring
->irq_get
= i9xx_ring_get_irq
;
2107 ring
->irq_put
= i9xx_ring_put_irq
;
2109 ring
->dispatch_execbuffer
= i965_dispatch_execbuffer
;
2111 ring
->init
= init_ring_common
;
2113 return intel_init_ring_buffer(dev
, ring
);
2116 int intel_init_blt_ring_buffer(struct drm_device
*dev
)
2118 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2119 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[BCS
];
2121 ring
->name
= "blitter ring";
2124 ring
->mmio_base
= BLT_RING_BASE
;
2125 ring
->write_tail
= ring_write_tail
;
2126 ring
->flush
= gen6_ring_flush
;
2127 ring
->add_request
= gen6_add_request
;
2128 ring
->get_seqno
= gen6_ring_get_seqno
;
2129 ring
->set_seqno
= ring_set_seqno
;
2130 if (INTEL_INFO(dev
)->gen
>= 8) {
2131 ring
->irq_enable_mask
=
2132 GT_RENDER_USER_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
;
2133 ring
->irq_get
= gen8_ring_get_irq
;
2134 ring
->irq_put
= gen8_ring_put_irq
;
2135 ring
->dispatch_execbuffer
= gen8_ring_dispatch_execbuffer
;
2137 ring
->irq_enable_mask
= GT_BLT_USER_INTERRUPT
;
2138 ring
->irq_get
= gen6_ring_get_irq
;
2139 ring
->irq_put
= gen6_ring_put_irq
;
2140 ring
->dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
;
2142 ring
->sync_to
= gen6_ring_sync
;
2143 ring
->semaphore_register
[RCS
] = MI_SEMAPHORE_SYNC_BR
;
2144 ring
->semaphore_register
[VCS
] = MI_SEMAPHORE_SYNC_BV
;
2145 ring
->semaphore_register
[BCS
] = MI_SEMAPHORE_SYNC_INVALID
;
2146 ring
->semaphore_register
[VECS
] = MI_SEMAPHORE_SYNC_BVE
;
2147 ring
->signal_mbox
[RCS
] = GEN6_RBSYNC
;
2148 ring
->signal_mbox
[VCS
] = GEN6_VBSYNC
;
2149 ring
->signal_mbox
[BCS
] = GEN6_NOSYNC
;
2150 ring
->signal_mbox
[VECS
] = GEN6_VEBSYNC
;
2151 ring
->init
= init_ring_common
;
2153 return intel_init_ring_buffer(dev
, ring
);
2156 int intel_init_vebox_ring_buffer(struct drm_device
*dev
)
2158 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2159 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[VECS
];
2161 ring
->name
= "video enhancement ring";
2164 ring
->mmio_base
= VEBOX_RING_BASE
;
2165 ring
->write_tail
= ring_write_tail
;
2166 ring
->flush
= gen6_ring_flush
;
2167 ring
->add_request
= gen6_add_request
;
2168 ring
->get_seqno
= gen6_ring_get_seqno
;
2169 ring
->set_seqno
= ring_set_seqno
;
2171 if (INTEL_INFO(dev
)->gen
>= 8) {
2172 ring
->irq_enable_mask
=
2173 GT_RENDER_USER_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
;
2174 ring
->irq_get
= gen8_ring_get_irq
;
2175 ring
->irq_put
= gen8_ring_put_irq
;
2176 ring
->dispatch_execbuffer
= gen8_ring_dispatch_execbuffer
;
2178 ring
->irq_enable_mask
= PM_VEBOX_USER_INTERRUPT
;
2179 ring
->irq_get
= hsw_vebox_get_irq
;
2180 ring
->irq_put
= hsw_vebox_put_irq
;
2181 ring
->dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
;
2183 ring
->sync_to
= gen6_ring_sync
;
2184 ring
->semaphore_register
[RCS
] = MI_SEMAPHORE_SYNC_VER
;
2185 ring
->semaphore_register
[VCS
] = MI_SEMAPHORE_SYNC_VEV
;
2186 ring
->semaphore_register
[BCS
] = MI_SEMAPHORE_SYNC_VEB
;
2187 ring
->semaphore_register
[VECS
] = MI_SEMAPHORE_SYNC_INVALID
;
2188 ring
->signal_mbox
[RCS
] = GEN6_RVESYNC
;
2189 ring
->signal_mbox
[VCS
] = GEN6_VVESYNC
;
2190 ring
->signal_mbox
[BCS
] = GEN6_BVESYNC
;
2191 ring
->signal_mbox
[VECS
] = GEN6_NOSYNC
;
2192 ring
->init
= init_ring_common
;
2194 return intel_init_ring_buffer(dev
, ring
);
2198 intel_ring_flush_all_caches(struct intel_ring_buffer
*ring
)
2202 if (!ring
->gpu_caches_dirty
)
2205 ret
= ring
->flush(ring
, 0, I915_GEM_GPU_DOMAINS
);
2209 trace_i915_gem_ring_flush(ring
, 0, I915_GEM_GPU_DOMAINS
);
2211 ring
->gpu_caches_dirty
= false;
2216 intel_ring_invalidate_all_caches(struct intel_ring_buffer
*ring
)
2218 uint32_t flush_domains
;
2222 if (ring
->gpu_caches_dirty
)
2223 flush_domains
= I915_GEM_GPU_DOMAINS
;
2225 ret
= ring
->flush(ring
, I915_GEM_GPU_DOMAINS
, flush_domains
);
2229 trace_i915_gem_ring_flush(ring
, I915_GEM_GPU_DOMAINS
, flush_domains
);
2231 ring
->gpu_caches_dirty
= false;