projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
drm/i915: Force ringbuffers to not be at offset 0
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c
1 /*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
30 #include <linux/log2.h>
31 #include <drm/drmP.h>
32 #include "i915_drv.h"
33 #include <drm/i915_drm.h>
34 #include "i915_trace.h"
35 #include "intel_drv.h"
36
37 int __intel_ring_space(int head, int tail, int size)
38 {
39 int space = head - tail;
40 if (space <= 0)
41 space += size;
42 return space - I915_RING_FREE_SPACE;
43 }
44
45 void intel_ring_update_space(struct intel_ringbuffer *ringbuf)
46 {
47 if (ringbuf->last_retired_head != -1) {
48 ringbuf->head = ringbuf->last_retired_head;
49 ringbuf->last_retired_head = -1;
50 }
51
52 ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR,
53 ringbuf->tail, ringbuf->size);
54 }
55
56 int intel_ring_space(struct intel_ringbuffer *ringbuf)
57 {
58 intel_ring_update_space(ringbuf);
59 return ringbuf->space;
60 }
61
62 bool intel_engine_stopped(struct intel_engine_cs *engine)
63 {
64 struct drm_i915_private *dev_priv = engine->dev->dev_private;
65 return dev_priv->gpu_error.stop_rings & intel_engine_flag(engine);
66 }
67
68 static void __intel_ring_advance(struct intel_engine_cs *engine)
69 {
70 struct intel_ringbuffer *ringbuf = engine->buffer;
71 ringbuf->tail &= ringbuf->size - 1;
72 if (intel_engine_stopped(engine))
73 return;
74 engine->write_tail(engine, ringbuf->tail);
75 }
76
77 static int
78 gen2_render_ring_flush(struct drm_i915_gem_request *req,
79 u32 invalidate_domains,
80 u32 flush_domains)
81 {
82 struct intel_engine_cs *engine = req->engine;
83 u32 cmd;
84 int ret;
85
86 cmd = MI_FLUSH;
87 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
88 cmd |= MI_NO_WRITE_FLUSH;
89
90 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
91 cmd |= MI_READ_FLUSH;
92
93 ret = intel_ring_begin(req, 2);
94 if (ret)
95 return ret;
96
97 intel_ring_emit(engine, cmd);
98 intel_ring_emit(engine, MI_NOOP);
99 intel_ring_advance(engine);
100
101 return 0;
102 }
103
104 static int
105 gen4_render_ring_flush(struct drm_i915_gem_request *req,
106 u32 invalidate_domains,
107 u32 flush_domains)
108 {
109 struct intel_engine_cs *engine = req->engine;
110 struct drm_device *dev = engine->dev;
111 u32 cmd;
112 int ret;
113
114 /*
115 * read/write caches:
116 *
117 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
118 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
119 * also flushed at 2d versus 3d pipeline switches.
120 *
121 * read-only caches:
122 *
123 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
124 * MI_READ_FLUSH is set, and is always flushed on 965.
125 *
126 * I915_GEM_DOMAIN_COMMAND may not exist?
127 *
128 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
129 * invalidated when MI_EXE_FLUSH is set.
130 *
131 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
132 * invalidated with every MI_FLUSH.
133 *
134 * TLBs:
135 *
136 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
137 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
138 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
139 * are flushed at any MI_FLUSH.
140 */
141
142 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
143 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
144 cmd &= ~MI_NO_WRITE_FLUSH;
145 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
146 cmd |= MI_EXE_FLUSH;
147
148 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
149 (IS_G4X(dev) || IS_GEN5(dev)))
150 cmd |= MI_INVALIDATE_ISP;
151
152 ret = intel_ring_begin(req, 2);
153 if (ret)
154 return ret;
155
156 intel_ring_emit(engine, cmd);
157 intel_ring_emit(engine, MI_NOOP);
158 intel_ring_advance(engine);
159
160 return 0;
161 }
162
163 /**
164 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
165 * implementing two workarounds on gen6. From section 1.4.7.1
166 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
167 *
168 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
169 * produced by non-pipelined state commands), software needs to first
170 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
171 * 0.
172 *
173 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
174 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
175 *
176 * And the workaround for these two requires this workaround first:
177 *
178 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
179 * BEFORE the pipe-control with a post-sync op and no write-cache
180 * flushes.
181 *
182 * And this last workaround is tricky because of the requirements on
183 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
184 * volume 2 part 1:
185 *
186 * "1 of the following must also be set:
187 * - Render Target Cache Flush Enable ([12] of DW1)
188 * - Depth Cache Flush Enable ([0] of DW1)
189 * - Stall at Pixel Scoreboard ([1] of DW1)
190 * - Depth Stall ([13] of DW1)
191 * - Post-Sync Operation ([13] of DW1)
192 * - Notify Enable ([8] of DW1)"
193 *
194 * The cache flushes require the workaround flush that triggered this
195 * one, so we can't use it. Depth stall would trigger the same.
196 * Post-sync nonzero is what triggered this second workaround, so we
197 * can't use that one either. Notify enable is IRQs, which aren't
198 * really our business. That leaves only stall at scoreboard.
199 */
200 static int
201 intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req)
202 {
203 struct intel_engine_cs *engine = req->engine;
204 u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
205 int ret;
206
207 ret = intel_ring_begin(req, 6);
208 if (ret)
209 return ret;
210
211 intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(5));
212 intel_ring_emit(engine, PIPE_CONTROL_CS_STALL |
213 PIPE_CONTROL_STALL_AT_SCOREBOARD);
214 intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
215 intel_ring_emit(engine, 0); /* low dword */
216 intel_ring_emit(engine, 0); /* high dword */
217 intel_ring_emit(engine, MI_NOOP);
218 intel_ring_advance(engine);
219
220 ret = intel_ring_begin(req, 6);
221 if (ret)
222 return ret;
223
224 intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(5));
225 intel_ring_emit(engine, PIPE_CONTROL_QW_WRITE);
226 intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
227 intel_ring_emit(engine, 0);
228 intel_ring_emit(engine, 0);
229 intel_ring_emit(engine, MI_NOOP);
230 intel_ring_advance(engine);
231
232 return 0;
233 }
234
235 static int
236 gen6_render_ring_flush(struct drm_i915_gem_request *req,
237 u32 invalidate_domains, u32 flush_domains)
238 {
239 struct intel_engine_cs *engine = req->engine;
240 u32 flags = 0;
241 u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
242 int ret;
243
244 /* Force SNB workarounds for PIPE_CONTROL flushes */
245 ret = intel_emit_post_sync_nonzero_flush(req);
246 if (ret)
247 return ret;
248
249 /* Just flush everything. Experiments have shown that reducing the
250 * number of bits based on the write domains has little performance
251 * impact.
252 */
253 if (flush_domains) {
254 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
255 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
256 /*
257 * Ensure that any following seqno writes only happen
258 * when the render cache is indeed flushed.
259 */
260 flags |= PIPE_CONTROL_CS_STALL;
261 }
262 if (invalidate_domains) {
263 flags |= PIPE_CONTROL_TLB_INVALIDATE;
264 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
265 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
266 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
267 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
268 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
269 /*
270 * TLB invalidate requires a post-sync write.
271 */
272 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
273 }
274
275 ret = intel_ring_begin(req, 4);
276 if (ret)
277 return ret;
278
279 intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4));
280 intel_ring_emit(engine, flags);
281 intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
282 intel_ring_emit(engine, 0);
283 intel_ring_advance(engine);
284
285 return 0;
286 }
287
288 static int
289 gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req)
290 {
291 struct intel_engine_cs *engine = req->engine;
292 int ret;
293
294 ret = intel_ring_begin(req, 4);
295 if (ret)
296 return ret;
297
298 intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4));
299 intel_ring_emit(engine, PIPE_CONTROL_CS_STALL |
300 PIPE_CONTROL_STALL_AT_SCOREBOARD);
301 intel_ring_emit(engine, 0);
302 intel_ring_emit(engine, 0);
303 intel_ring_advance(engine);
304
305 return 0;
306 }
307
308 static int
309 gen7_render_ring_flush(struct drm_i915_gem_request *req,
310 u32 invalidate_domains, u32 flush_domains)
311 {
312 struct intel_engine_cs *engine = req->engine;
313 u32 flags = 0;
314 u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
315 int ret;
316
317 /*
318 * Ensure that any following seqno writes only happen when the render
319 * cache is indeed flushed.
320 *
321 * Workaround: 4th PIPE_CONTROL command (except the ones with only
322 * read-cache invalidate bits set) must have the CS_STALL bit set. We
323 * don't try to be clever and just set it unconditionally.
324 */
325 flags |= PIPE_CONTROL_CS_STALL;
326
327 /* Just flush everything. Experiments have shown that reducing the
328 * number of bits based on the write domains has little performance
329 * impact.
330 */
331 if (flush_domains) {
332 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
333 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
334 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
335 flags |= PIPE_CONTROL_FLUSH_ENABLE;
336 }
337 if (invalidate_domains) {
338 flags |= PIPE_CONTROL_TLB_INVALIDATE;
339 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
340 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
341 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
342 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
343 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
344 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
345 /*
346 * TLB invalidate requires a post-sync write.
347 */
348 flags |= PIPE_CONTROL_QW_WRITE;
349 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
350
351 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
352
353 /* Workaround: we must issue a pipe_control with CS-stall bit
354 * set before a pipe_control command that has the state cache
355 * invalidate bit set. */
356 gen7_render_ring_cs_stall_wa(req);
357 }
358
359 ret = intel_ring_begin(req, 4);
360 if (ret)
361 return ret;
362
363 intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4));
364 intel_ring_emit(engine, flags);
365 intel_ring_emit(engine, scratch_addr);
366 intel_ring_emit(engine, 0);
367 intel_ring_advance(engine);
368
369 return 0;
370 }
371
372 static int
373 gen8_emit_pipe_control(struct drm_i915_gem_request *req,
374 u32 flags, u32 scratch_addr)
375 {
376 struct intel_engine_cs *engine = req->engine;
377 int ret;
378
379 ret = intel_ring_begin(req, 6);
380 if (ret)
381 return ret;
382
383 intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(6));
384 intel_ring_emit(engine, flags);
385 intel_ring_emit(engine, scratch_addr);
386 intel_ring_emit(engine, 0);
387 intel_ring_emit(engine, 0);
388 intel_ring_emit(engine, 0);
389 intel_ring_advance(engine);
390
391 return 0;
392 }
393
394 static int
395 gen8_render_ring_flush(struct drm_i915_gem_request *req,
396 u32 invalidate_domains, u32 flush_domains)
397 {
398 u32 flags = 0;
399 u32 scratch_addr = req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
400 int ret;
401
402 flags |= PIPE_CONTROL_CS_STALL;
403
404 if (flush_domains) {
405 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
406 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
407 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
408 flags |= PIPE_CONTROL_FLUSH_ENABLE;
409 }
410 if (invalidate_domains) {
411 flags |= PIPE_CONTROL_TLB_INVALIDATE;
412 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
413 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
414 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
415 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
416 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
417 flags |= PIPE_CONTROL_QW_WRITE;
418 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
419
420 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
421 ret = gen8_emit_pipe_control(req,
422 PIPE_CONTROL_CS_STALL |
423 PIPE_CONTROL_STALL_AT_SCOREBOARD,
424 0);
425 if (ret)
426 return ret;
427 }
428
429 return gen8_emit_pipe_control(req, flags, scratch_addr);
430 }
431
432 static void ring_write_tail(struct intel_engine_cs *engine,
433 u32 value)
434 {
435 struct drm_i915_private *dev_priv = engine->dev->dev_private;
436 I915_WRITE_TAIL(engine, value);
437 }
438
439 u64 intel_ring_get_active_head(struct intel_engine_cs *engine)
440 {
441 struct drm_i915_private *dev_priv = engine->dev->dev_private;
442 u64 acthd;
443
444 if (INTEL_INFO(engine->dev)->gen >= 8)
445 acthd = I915_READ64_2x32(RING_ACTHD(engine->mmio_base),
446 RING_ACTHD_UDW(engine->mmio_base));
447 else if (INTEL_INFO(engine->dev)->gen >= 4)
448 acthd = I915_READ(RING_ACTHD(engine->mmio_base));
449 else
450 acthd = I915_READ(ACTHD);
451
452 return acthd;
453 }
454
455 static void ring_setup_phys_status_page(struct intel_engine_cs *engine)
456 {
457 struct drm_i915_private *dev_priv = engine->dev->dev_private;
458 u32 addr;
459
460 addr = dev_priv->status_page_dmah->busaddr;
461 if (INTEL_INFO(engine->dev)->gen >= 4)
462 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
463 I915_WRITE(HWS_PGA, addr);
464 }
465
466 static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
467 {
468 struct drm_device *dev = engine->dev;
469 struct drm_i915_private *dev_priv = engine->dev->dev_private;
470 i915_reg_t mmio;
471
472 /* The ring status page addresses are no longer next to the rest of
473 * the ring registers as of gen7.
474 */
475 if (IS_GEN7(dev)) {
476 switch (engine->id) {
477 case RCS:
478 mmio = RENDER_HWS_PGA_GEN7;
479 break;
480 case BCS:
481 mmio = BLT_HWS_PGA_GEN7;
482 break;
483 /*
484 * VCS2 actually doesn't exist on Gen7. Only shut up
485 * gcc switch check warning
486 */
487 case VCS2:
488 case VCS:
489 mmio = BSD_HWS_PGA_GEN7;
490 break;
491 case VECS:
492 mmio = VEBOX_HWS_PGA_GEN7;
493 break;
494 }
495 } else if (IS_GEN6(engine->dev)) {
496 mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
497 } else {
498 /* XXX: gen8 returns to sanity */
499 mmio = RING_HWS_PGA(engine->mmio_base);
500 }
501
502 I915_WRITE(mmio, (u32)engine->status_page.gfx_addr);
503 POSTING_READ(mmio);
504
505 /*
506 * Flush the TLB for this page
507 *
508 * FIXME: These two bits have disappeared on gen8, so a question
509 * arises: do we still need this and if so how should we go about
510 * invalidating the TLB?
511 */
512 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
513 i915_reg_t reg = RING_INSTPM(engine->mmio_base);
514
515 /* ring should be idle before issuing a sync flush*/
516 WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
517
518 I915_WRITE(reg,
519 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
520 INSTPM_SYNC_FLUSH));
521 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
522 1000))
523 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
524 engine->name);
525 }
526 }
527
528 static bool stop_ring(struct intel_engine_cs *engine)
529 {
530 struct drm_i915_private *dev_priv = to_i915(engine->dev);
531
532 if (!IS_GEN2(engine->dev)) {
533 I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING));
534 if (wait_for((I915_READ_MODE(engine) & MODE_IDLE) != 0, 1000)) {
535 DRM_ERROR("%s : timed out trying to stop ring\n",
536 engine->name);
537 /* Sometimes we observe that the idle flag is not
538 * set even though the ring is empty. So double
539 * check before giving up.
540 */
541 if (I915_READ_HEAD(engine) != I915_READ_TAIL(engine))
542 return false;
543 }
544 }
545
546 I915_WRITE_CTL(engine, 0);
547 I915_WRITE_HEAD(engine, 0);
548 engine->write_tail(engine, 0);
549
550 if (!IS_GEN2(engine->dev)) {
551 (void)I915_READ_CTL(engine);
552 I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING));
553 }
554
555 return (I915_READ_HEAD(engine) & HEAD_ADDR) == 0;
556 }
557
558 void intel_engine_init_hangcheck(struct intel_engine_cs *engine)
559 {
560 memset(&engine->hangcheck, 0, sizeof(engine->hangcheck));
561 }
562
563 static int init_ring_common(struct intel_engine_cs *engine)
564 {
565 struct drm_device *dev = engine->dev;
566 struct drm_i915_private *dev_priv = dev->dev_private;
567 struct intel_ringbuffer *ringbuf = engine->buffer;
568 struct drm_i915_gem_object *obj = ringbuf->obj;
569 int ret = 0;
570
571 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
572
573 if (!stop_ring(engine)) {
574 /* G45 ring initialization often fails to reset head to zero */
575 DRM_DEBUG_KMS("%s head not reset to zero "
576 "ctl %08x head %08x tail %08x start %08x\n",
577 engine->name,
578 I915_READ_CTL(engine),
579 I915_READ_HEAD(engine),
580 I915_READ_TAIL(engine),
581 I915_READ_START(engine));
582
583 if (!stop_ring(engine)) {
584 DRM_ERROR("failed to set %s head to zero "
585 "ctl %08x head %08x tail %08x start %08x\n",
586 engine->name,
587 I915_READ_CTL(engine),
588 I915_READ_HEAD(engine),
589 I915_READ_TAIL(engine),
590 I915_READ_START(engine));
591 ret = -EIO;
592 goto out;
593 }
594 }
595
596 if (I915_NEED_GFX_HWS(dev))
597 intel_ring_setup_status_page(engine);
598 else
599 ring_setup_phys_status_page(engine);
600
601 /* Enforce ordering by reading HEAD register back */
602 I915_READ_HEAD(engine);
603
604 /* Initialize the ring. This must happen _after_ we've cleared the ring
605 * registers with the above sequence (the readback of the HEAD registers
606 * also enforces ordering), otherwise the hw might lose the new ring
607 * register values. */
608 I915_WRITE_START(engine, i915_gem_obj_ggtt_offset(obj));
609
610 /* WaClearRingBufHeadRegAtInit:ctg,elk */
611 if (I915_READ_HEAD(engine))
612 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
613 engine->name, I915_READ_HEAD(engine));
614 I915_WRITE_HEAD(engine, 0);
615 (void)I915_READ_HEAD(engine);
616
617 I915_WRITE_CTL(engine,
618 ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
619 | RING_VALID);
620
621 /* If the head is still not zero, the ring is dead */
622 if (wait_for((I915_READ_CTL(engine) & RING_VALID) != 0 &&
623 I915_READ_START(engine) == i915_gem_obj_ggtt_offset(obj) &&
624 (I915_READ_HEAD(engine) & HEAD_ADDR) == 0, 50)) {
625 DRM_ERROR("%s initialization failed "
626 "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
627 engine->name,
628 I915_READ_CTL(engine),
629 I915_READ_CTL(engine) & RING_VALID,
630 I915_READ_HEAD(engine), I915_READ_TAIL(engine),
631 I915_READ_START(engine),
632 (unsigned long)i915_gem_obj_ggtt_offset(obj));
633 ret = -EIO;
634 goto out;
635 }
636
637 ringbuf->last_retired_head = -1;
638 ringbuf->head = I915_READ_HEAD(engine);
639 ringbuf->tail = I915_READ_TAIL(engine) & TAIL_ADDR;
640 intel_ring_update_space(ringbuf);
641
642 intel_engine_init_hangcheck(engine);
643
644 out:
645 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
646
647 return ret;
648 }
649
650 void
651 intel_fini_pipe_control(struct intel_engine_cs *engine)
652 {
653 struct drm_device *dev = engine->dev;
654
655 if (engine->scratch.obj == NULL)
656 return;
657
658 if (INTEL_INFO(dev)->gen >= 5) {
659 kunmap(sg_page(engine->scratch.obj->pages->sgl));
660 i915_gem_object_ggtt_unpin(engine->scratch.obj);
661 }
662
663 drm_gem_object_unreference(&engine->scratch.obj->base);
664 engine->scratch.obj = NULL;
665 }
666
667 int
668 intel_init_pipe_control(struct intel_engine_cs *engine)
669 {
670 int ret;
671
672 WARN_ON(engine->scratch.obj);
673
674 engine->scratch.obj = i915_gem_alloc_object(engine->dev, 4096);
675 if (engine->scratch.obj == NULL) {
676 DRM_ERROR("Failed to allocate seqno page\n");
677 ret = -ENOMEM;
678 goto err;
679 }
680
681 ret = i915_gem_object_set_cache_level(engine->scratch.obj,
682 I915_CACHE_LLC);
683 if (ret)
684 goto err_unref;
685
686 ret = i915_gem_obj_ggtt_pin(engine->scratch.obj, 4096, 0);
687 if (ret)
688 goto err_unref;
689
690 engine->scratch.gtt_offset = i915_gem_obj_ggtt_offset(engine->scratch.obj);
691 engine->scratch.cpu_page = kmap(sg_page(engine->scratch.obj->pages->sgl));
692 if (engine->scratch.cpu_page == NULL) {
693 ret = -ENOMEM;
694 goto err_unpin;
695 }
696
697 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
698 engine->name, engine->scratch.gtt_offset);
699 return 0;
700
701 err_unpin:
702 i915_gem_object_ggtt_unpin(engine->scratch.obj);
703 err_unref:
704 drm_gem_object_unreference(&engine->scratch.obj->base);
705 err:
706 return ret;
707 }
708
709 static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req)
710 {
711 int ret, i;
712 struct intel_engine_cs *engine = req->engine;
713 struct drm_device *dev = engine->dev;
714 struct drm_i915_private *dev_priv = dev->dev_private;
715 struct i915_workarounds *w = &dev_priv->workarounds;
716
717 if (w->count == 0)
718 return 0;
719
720 engine->gpu_caches_dirty = true;
721 ret = intel_ring_flush_all_caches(req);
722 if (ret)
723 return ret;
724
725 ret = intel_ring_begin(req, (w->count * 2 + 2));
726 if (ret)
727 return ret;
728
729 intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(w->count));
730 for (i = 0; i < w->count; i++) {
731 intel_ring_emit_reg(engine, w->reg[i].addr);
732 intel_ring_emit(engine, w->reg[i].value);
733 }
734 intel_ring_emit(engine, MI_NOOP);
735
736 intel_ring_advance(engine);
737
738 engine->gpu_caches_dirty = true;
739 ret = intel_ring_flush_all_caches(req);
740 if (ret)
741 return ret;
742
743 DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
744
745 return 0;
746 }
747
748 static int intel_rcs_ctx_init(struct drm_i915_gem_request *req)
749 {
750 int ret;
751
752 ret = intel_ring_workarounds_emit(req);
753 if (ret != 0)
754 return ret;
755
756 ret = i915_gem_render_state_init(req);
757 if (ret)
758 return ret;
759
760 return 0;
761 }
762
763 static int wa_add(struct drm_i915_private *dev_priv,
764 i915_reg_t addr,
765 const u32 mask, const u32 val)
766 {
767 const u32 idx = dev_priv->workarounds.count;
768
769 if (WARN_ON(idx >= I915_MAX_WA_REGS))
770 return -ENOSPC;
771
772 dev_priv->workarounds.reg[idx].addr = addr;
773 dev_priv->workarounds.reg[idx].value = val;
774 dev_priv->workarounds.reg[idx].mask = mask;
775
776 dev_priv->workarounds.count++;
777
778 return 0;
779 }
780
781 #define WA_REG(addr, mask, val) do { \
782 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
783 if (r) \
784 return r; \
785 } while (0)
786
787 #define WA_SET_BIT_MASKED(addr, mask) \
788 WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
789
790 #define WA_CLR_BIT_MASKED(addr, mask) \
791 WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
792
793 #define WA_SET_FIELD_MASKED(addr, mask, value) \
794 WA_REG(addr, mask, _MASKED_FIELD(mask, value))
795
796 #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
797 #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
798
799 #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
800
801 static int wa_ring_whitelist_reg(struct intel_engine_cs *engine,
802 i915_reg_t reg)
803 {
804 struct drm_i915_private *dev_priv = engine->dev->dev_private;
805 struct i915_workarounds *wa = &dev_priv->workarounds;
806 const uint32_t index = wa->hw_whitelist_count[engine->id];
807
808 if (WARN_ON(index >= RING_MAX_NONPRIV_SLOTS))
809 return -EINVAL;
810
811 WA_WRITE(RING_FORCE_TO_NONPRIV(engine->mmio_base, index),
812 i915_mmio_reg_offset(reg));
813 wa->hw_whitelist_count[engine->id]++;
814
815 return 0;
816 }
817
818 static int gen8_init_workarounds(struct intel_engine_cs *engine)
819 {
820 struct drm_device *dev = engine->dev;
821 struct drm_i915_private *dev_priv = dev->dev_private;
822
823 WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
824
825 /* WaDisableAsyncFlipPerfMode:bdw,chv */
826 WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
827
828 /* WaDisablePartialInstShootdown:bdw,chv */
829 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
830 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
831
832 /* Use Force Non-Coherent whenever executing a 3D context. This is a
833 * workaround for for a possible hang in the unlikely event a TLB
834 * invalidation occurs during a PSD flush.
835 */
836 /* WaForceEnableNonCoherent:bdw,chv */
837 /* WaHdcDisableFetchWhenMasked:bdw,chv */
838 WA_SET_BIT_MASKED(HDC_CHICKEN0,
839 HDC_DONOT_FETCH_MEM_WHEN_MASKED |
840 HDC_FORCE_NON_COHERENT);
841
842 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
843 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
844 * polygons in the same 8x4 pixel/sample area to be processed without
845 * stalling waiting for the earlier ones to write to Hierarchical Z
846 * buffer."
847 *
848 * This optimization is off by default for BDW and CHV; turn it on.
849 */
850 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
851
852 /* Wa4x4STCOptimizationDisable:bdw,chv */
853 WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
854
855 /*
856 * BSpec recommends 8x4 when MSAA is used,
857 * however in practice 16x4 seems fastest.
858 *
859 * Note that PS/WM thread counts depend on the WIZ hashing
860 * disable bit, which we don't touch here, but it's good
861 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
862 */
863 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
864 GEN6_WIZ_HASHING_MASK,
865 GEN6_WIZ_HASHING_16x4);
866
867 return 0;
868 }
869
870 static int bdw_init_workarounds(struct intel_engine_cs *engine)
871 {
872 int ret;
873 struct drm_device *dev = engine->dev;
874 struct drm_i915_private *dev_priv = dev->dev_private;
875
876 ret = gen8_init_workarounds(engine);
877 if (ret)
878 return ret;
879
880 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
881 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
882
883 /* WaDisableDopClockGating:bdw */
884 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
885 DOP_CLOCK_GATING_DISABLE);
886
887 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
888 GEN8_SAMPLER_POWER_BYPASS_DIS);
889
890 WA_SET_BIT_MASKED(HDC_CHICKEN0,
891 /* WaForceContextSaveRestoreNonCoherent:bdw */
892 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
893 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
894 (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
895
896 return 0;
897 }
898
899 static int chv_init_workarounds(struct intel_engine_cs *engine)
900 {
901 int ret;
902 struct drm_device *dev = engine->dev;
903 struct drm_i915_private *dev_priv = dev->dev_private;
904
905 ret = gen8_init_workarounds(engine);
906 if (ret)
907 return ret;
908
909 /* WaDisableThreadStallDopClockGating:chv */
910 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
911
912 /* Improve HiZ throughput on CHV. */
913 WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
914
915 return 0;
916 }
917
918 static int gen9_init_workarounds(struct intel_engine_cs *engine)
919 {
920 struct drm_device *dev = engine->dev;
921 struct drm_i915_private *dev_priv = dev->dev_private;
922 uint32_t tmp;
923 int ret;
924
925 /* WaEnableLbsSlaRetryTimerDecrement:skl */
926 I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
927 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
928
929 /* WaDisableKillLogic:bxt,skl */
930 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
931 ECOCHK_DIS_TLB);
932
933 /* WaClearFlowControlGpgpuContextSave:skl,bxt */
934 /* WaDisablePartialInstShootdown:skl,bxt */
935 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
936 FLOW_CONTROL_ENABLE |
937 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
938
939 /* Syncing dependencies between camera and graphics:skl,bxt */
940 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
941 GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
942
943 /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
944 if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
945 IS_BXT_REVID(dev, 0, BXT_REVID_A1))
946 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
947 GEN9_DG_MIRROR_FIX_ENABLE);
948
949 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
950 if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
951 IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
952 WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
953 GEN9_RHWO_OPTIMIZATION_DISABLE);
954 /*
955 * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
956 * but we do that in per ctx batchbuffer as there is an issue
957 * with this register not getting restored on ctx restore
958 */
959 }
960
961 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt */
962 if (IS_SKL_REVID(dev, SKL_REVID_C0, REVID_FOREVER) || IS_BROXTON(dev))
963 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
964 GEN9_ENABLE_YV12_BUGFIX);
965
966 /* Wa4x4STCOptimizationDisable:skl,bxt */
967 /* WaDisablePartialResolveInVc:skl,bxt */
968 WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE |
969 GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE));
970
971 /* WaCcsTlbPrefetchDisable:skl,bxt */
972 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
973 GEN9_CCS_TLB_PREFETCH_ENABLE);
974
975 /* WaDisableMaskBasedCammingInRCC:skl,bxt */
976 if (IS_SKL_REVID(dev, SKL_REVID_C0, SKL_REVID_C0) ||
977 IS_BXT_REVID(dev, 0, BXT_REVID_A1))
978 WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
979 PIXEL_MASK_CAMMING_DISABLE);
980
981 /* WaForceContextSaveRestoreNonCoherent:skl,bxt */
982 tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT;
983 if (IS_SKL_REVID(dev, SKL_REVID_F0, REVID_FOREVER) ||
984 IS_BXT_REVID(dev, BXT_REVID_B0, REVID_FOREVER))
985 tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
986 WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
987
988 /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt */
989 if (IS_SKYLAKE(dev) || IS_BXT_REVID(dev, 0, BXT_REVID_B0))
990 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
991 GEN8_SAMPLER_POWER_BYPASS_DIS);
992
993 /* WaDisableSTUnitPowerOptimization:skl,bxt */
994 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
995
996 /* WaOCLCoherentLineFlush:skl,bxt */
997 I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
998 GEN8_LQSC_FLUSH_COHERENT_LINES));
999
1000 /* WaEnablePreemptionGranularityControlByUMD:skl,bxt */
1001 ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1);
1002 if (ret)
1003 return ret;
1004
1005 /* WaAllowUMDToModifyHDCChicken1:skl,bxt */
1006 ret = wa_ring_whitelist_reg(engine, GEN8_HDC_CHICKEN1);
1007 if (ret)
1008 return ret;
1009
1010 return 0;
1011 }
1012
1013 static int skl_tune_iz_hashing(struct intel_engine_cs *engine)
1014 {
1015 struct drm_device *dev = engine->dev;
1016 struct drm_i915_private *dev_priv = dev->dev_private;
1017 u8 vals[3] = { 0, 0, 0 };
1018 unsigned int i;
1019
1020 for (i = 0; i < 3; i++) {
1021 u8 ss;
1022
1023 /*
1024 * Only consider slices where one, and only one, subslice has 7
1025 * EUs
1026 */
1027 if (!is_power_of_2(dev_priv->info.subslice_7eu[i]))
1028 continue;
1029
1030 /*
1031 * subslice_7eu[i] != 0 (because of the check above) and
1032 * ss_max == 4 (maximum number of subslices possible per slice)
1033 *
1034 * -> 0 <= ss <= 3;
1035 */
1036 ss = ffs(dev_priv->info.subslice_7eu[i]) - 1;
1037 vals[i] = 3 - ss;
1038 }
1039
1040 if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0)
1041 return 0;
1042
1043 /* Tune IZ hashing. See intel_device_info_runtime_init() */
1044 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
1045 GEN9_IZ_HASHING_MASK(2) |
1046 GEN9_IZ_HASHING_MASK(1) |
1047 GEN9_IZ_HASHING_MASK(0),
1048 GEN9_IZ_HASHING(2, vals[2]) |
1049 GEN9_IZ_HASHING(1, vals[1]) |
1050 GEN9_IZ_HASHING(0, vals[0]));
1051
1052 return 0;
1053 }
1054
1055 static int skl_init_workarounds(struct intel_engine_cs *engine)
1056 {
1057 int ret;
1058 struct drm_device *dev = engine->dev;
1059 struct drm_i915_private *dev_priv = dev->dev_private;
1060
1061 ret = gen9_init_workarounds(engine);
1062 if (ret)
1063 return ret;
1064
1065 /*
1066 * Actual WA is to disable percontext preemption granularity control
1067 * until D0 which is the default case so this is equivalent to
1068 * !WaDisablePerCtxtPreemptionGranularityControl:skl
1069 */
1070 if (IS_SKL_REVID(dev, SKL_REVID_E0, REVID_FOREVER)) {
1071 I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1,
1072 _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
1073 }
1074
1075 if (IS_SKL_REVID(dev, 0, SKL_REVID_D0)) {
1076 /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
1077 I915_WRITE(FF_SLICE_CS_CHICKEN2,
1078 _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE));
1079 }
1080
1081 /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
1082 * involving this register should also be added to WA batch as required.
1083 */
1084 if (IS_SKL_REVID(dev, 0, SKL_REVID_E0))
1085 /* WaDisableLSQCROPERFforOCL:skl */
1086 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
1087 GEN8_LQSC_RO_PERF_DIS);
1088
1089 /* WaEnableGapsTsvCreditFix:skl */
1090 if (IS_SKL_REVID(dev, SKL_REVID_C0, REVID_FOREVER)) {
1091 I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
1092 GEN9_GAPS_TSV_CREDIT_DISABLE));
1093 }
1094
1095 /* WaDisablePowerCompilerClockGating:skl */
1096 if (IS_SKL_REVID(dev, SKL_REVID_B0, SKL_REVID_B0))
1097 WA_SET_BIT_MASKED(HIZ_CHICKEN,
1098 BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
1099
1100 /* This is tied to WaForceContextSaveRestoreNonCoherent */
1101 if (IS_SKL_REVID(dev, 0, REVID_FOREVER)) {
1102 /*
1103 *Use Force Non-Coherent whenever executing a 3D context. This
1104 * is a workaround for a possible hang in the unlikely event
1105 * a TLB invalidation occurs during a PSD flush.
1106 */
1107 /* WaForceEnableNonCoherent:skl */
1108 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1109 HDC_FORCE_NON_COHERENT);
1110
1111 /* WaDisableHDCInvalidation:skl */
1112 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
1113 BDW_DISABLE_HDC_INVALIDATION);
1114 }
1115
1116 /* WaBarrierPerformanceFixDisable:skl */
1117 if (IS_SKL_REVID(dev, SKL_REVID_C0, SKL_REVID_D0))
1118 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1119 HDC_FENCE_DEST_SLM_DISABLE |
1120 HDC_BARRIER_PERFORMANCE_DISABLE);
1121
1122 /* WaDisableSbeCacheDispatchPortSharing:skl */
1123 if (IS_SKL_REVID(dev, 0, SKL_REVID_F0))
1124 WA_SET_BIT_MASKED(
1125 GEN7_HALF_SLICE_CHICKEN1,
1126 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1127
1128 /* WaDisableLSQCROPERFforOCL:skl */
1129 ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
1130 if (ret)
1131 return ret;
1132
1133 return skl_tune_iz_hashing(engine);
1134 }
1135
1136 static int bxt_init_workarounds(struct intel_engine_cs *engine)
1137 {
1138 int ret;
1139 struct drm_device *dev = engine->dev;
1140 struct drm_i915_private *dev_priv = dev->dev_private;
1141
1142 ret = gen9_init_workarounds(engine);
1143 if (ret)
1144 return ret;
1145
1146 /* WaStoreMultiplePTEenable:bxt */
1147 /* This is a requirement according to Hardware specification */
1148 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
1149 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
1150
1151 /* WaSetClckGatingDisableMedia:bxt */
1152 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
1153 I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) &
1154 ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE));
1155 }
1156
1157 /* WaDisableThreadStallDopClockGating:bxt */
1158 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
1159 STALL_DOP_GATING_DISABLE);
1160
1161 /* WaDisableSbeCacheDispatchPortSharing:bxt */
1162 if (IS_BXT_REVID(dev, 0, BXT_REVID_B0)) {
1163 WA_SET_BIT_MASKED(
1164 GEN7_HALF_SLICE_CHICKEN1,
1165 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1166 }
1167
1168 /* WaDisableObjectLevelPreemptionForTrifanOrPolygon:bxt */
1169 /* WaDisableObjectLevelPreemptionForInstancedDraw:bxt */
1170 /* WaDisableObjectLevelPreemtionForInstanceId:bxt */
1171 /* WaDisableLSQCROPERFforOCL:bxt */
1172 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
1173 ret = wa_ring_whitelist_reg(engine, GEN9_CS_DEBUG_MODE1);
1174 if (ret)
1175 return ret;
1176
1177 ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
1178 if (ret)
1179 return ret;
1180 }
1181
1182 return 0;
1183 }
1184
1185 int init_workarounds_ring(struct intel_engine_cs *engine)
1186 {
1187 struct drm_device *dev = engine->dev;
1188 struct drm_i915_private *dev_priv = dev->dev_private;
1189
1190 WARN_ON(engine->id != RCS);
1191
1192 dev_priv->workarounds.count = 0;
1193 dev_priv->workarounds.hw_whitelist_count[RCS] = 0;
1194
1195 if (IS_BROADWELL(dev))
1196 return bdw_init_workarounds(engine);
1197
1198 if (IS_CHERRYVIEW(dev))
1199 return chv_init_workarounds(engine);
1200
1201 if (IS_SKYLAKE(dev))
1202 return skl_init_workarounds(engine);
1203
1204 if (IS_BROXTON(dev))
1205 return bxt_init_workarounds(engine);
1206
1207 return 0;
1208 }
1209
1210 static int init_render_ring(struct intel_engine_cs *engine)
1211 {
1212 struct drm_device *dev = engine->dev;
1213 struct drm_i915_private *dev_priv = dev->dev_private;
1214 int ret = init_ring_common(engine);
1215 if (ret)
1216 return ret;
1217
1218 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
1219 if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
1220 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
1221
1222 /* We need to disable the AsyncFlip performance optimisations in order
1223 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1224 * programmed to '1' on all products.
1225 *
1226 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
1227 */
1228 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
1229 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1230
1231 /* Required for the hardware to program scanline values for waiting */
1232 /* WaEnableFlushTlbInvalidationMode:snb */
1233 if (INTEL_INFO(dev)->gen == 6)
1234 I915_WRITE(GFX_MODE,
1235 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
1236
1237 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1238 if (IS_GEN7(dev))
1239 I915_WRITE(GFX_MODE_GEN7,
1240 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
1241 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
1242
1243 if (IS_GEN6(dev)) {
1244 /* From the Sandybridge PRM, volume 1 part 3, page 24:
1245 * "If this bit is set, STCunit will have LRA as replacement
1246 * policy. [...] This bit must be reset. LRA replacement
1247 * policy is not supported."
1248 */
1249 I915_WRITE(CACHE_MODE_0,
1250 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
1251 }
1252
1253 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
1254 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1255
1256 if (HAS_L3_DPF(dev))
1257 I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev));
1258
1259 return init_workarounds_ring(engine);
1260 }
1261
1262 static void render_ring_cleanup(struct intel_engine_cs *engine)
1263 {
1264 struct drm_device *dev = engine->dev;
1265 struct drm_i915_private *dev_priv = dev->dev_private;
1266
1267 if (dev_priv->semaphore_obj) {
1268 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
1269 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
1270 dev_priv->semaphore_obj = NULL;
1271 }
1272
1273 intel_fini_pipe_control(engine);
1274 }
1275
1276 static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req,
1277 unsigned int num_dwords)
1278 {
1279 #define MBOX_UPDATE_DWORDS 8
1280 struct intel_engine_cs *signaller = signaller_req->engine;
1281 struct drm_device *dev = signaller->dev;
1282 struct drm_i915_private *dev_priv = dev->dev_private;
1283 struct intel_engine_cs *waiter;
1284 enum intel_engine_id id;
1285 int ret, num_rings;
1286
1287 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1288 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1289 #undef MBOX_UPDATE_DWORDS
1290
1291 ret = intel_ring_begin(signaller_req, num_dwords);
1292 if (ret)
1293 return ret;
1294
1295 for_each_engine_id(waiter, dev_priv, id) {
1296 u32 seqno;
1297 u64 gtt_offset = signaller->semaphore.signal_ggtt[id];
1298 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1299 continue;
1300
1301 seqno = i915_gem_request_get_seqno(signaller_req);
1302 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
1303 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
1304 PIPE_CONTROL_QW_WRITE |
1305 PIPE_CONTROL_FLUSH_ENABLE);
1306 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
1307 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1308 intel_ring_emit(signaller, seqno);
1309 intel_ring_emit(signaller, 0);
1310 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1311 MI_SEMAPHORE_TARGET(waiter->id));
1312 intel_ring_emit(signaller, 0);
1313 }
1314
1315 return 0;
1316 }
1317
1318 static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req,
1319 unsigned int num_dwords)
1320 {
1321 #define MBOX_UPDATE_DWORDS 6
1322 struct intel_engine_cs *signaller = signaller_req->engine;
1323 struct drm_device *dev = signaller->dev;
1324 struct drm_i915_private *dev_priv = dev->dev_private;
1325 struct intel_engine_cs *waiter;
1326 enum intel_engine_id id;
1327 int ret, num_rings;
1328
1329 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1330 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1331 #undef MBOX_UPDATE_DWORDS
1332
1333 ret = intel_ring_begin(signaller_req, num_dwords);
1334 if (ret)
1335 return ret;
1336
1337 for_each_engine_id(waiter, dev_priv, id) {
1338 u32 seqno;
1339 u64 gtt_offset = signaller->semaphore.signal_ggtt[id];
1340 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1341 continue;
1342
1343 seqno = i915_gem_request_get_seqno(signaller_req);
1344 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
1345 MI_FLUSH_DW_OP_STOREDW);
1346 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
1347 MI_FLUSH_DW_USE_GTT);
1348 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1349 intel_ring_emit(signaller, seqno);
1350 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1351 MI_SEMAPHORE_TARGET(waiter->id));
1352 intel_ring_emit(signaller, 0);
1353 }
1354
1355 return 0;
1356 }
1357
1358 static int gen6_signal(struct drm_i915_gem_request *signaller_req,
1359 unsigned int num_dwords)
1360 {
1361 struct intel_engine_cs *signaller = signaller_req->engine;
1362 struct drm_device *dev = signaller->dev;
1363 struct drm_i915_private *dev_priv = dev->dev_private;
1364 struct intel_engine_cs *useless;
1365 enum intel_engine_id id;
1366 int ret, num_rings;
1367
1368 #define MBOX_UPDATE_DWORDS 3
1369 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1370 num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
1371 #undef MBOX_UPDATE_DWORDS
1372
1373 ret = intel_ring_begin(signaller_req, num_dwords);
1374 if (ret)
1375 return ret;
1376
1377 for_each_engine_id(useless, dev_priv, id) {
1378 i915_reg_t mbox_reg = signaller->semaphore.mbox.signal[id];
1379
1380 if (i915_mmio_reg_valid(mbox_reg)) {
1381 u32 seqno = i915_gem_request_get_seqno(signaller_req);
1382
1383 intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
1384 intel_ring_emit_reg(signaller, mbox_reg);
1385 intel_ring_emit(signaller, seqno);
1386 }
1387 }
1388
1389 /* If num_dwords was rounded, make sure the tail pointer is correct */
1390 if (num_rings % 2 == 0)
1391 intel_ring_emit(signaller, MI_NOOP);
1392
1393 return 0;
1394 }
1395
1396 /**
1397 * gen6_add_request - Update the semaphore mailbox registers
1398 *
1399 * @request - request to write to the ring
1400 *
1401 * Update the mailbox registers in the *other* rings with the current seqno.
1402 * This acts like a signal in the canonical semaphore.
1403 */
1404 static int
1405 gen6_add_request(struct drm_i915_gem_request *req)
1406 {
1407 struct intel_engine_cs *engine = req->engine;
1408 int ret;
1409
1410 if (engine->semaphore.signal)
1411 ret = engine->semaphore.signal(req, 4);
1412 else
1413 ret = intel_ring_begin(req, 4);
1414
1415 if (ret)
1416 return ret;
1417
1418 intel_ring_emit(engine, MI_STORE_DWORD_INDEX);
1419 intel_ring_emit(engine,
1420 I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1421 intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1422 intel_ring_emit(engine, MI_USER_INTERRUPT);
1423 __intel_ring_advance(engine);
1424
1425 return 0;
1426 }
1427
1428 static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
1429 u32 seqno)
1430 {
1431 struct drm_i915_private *dev_priv = dev->dev_private;
1432 return dev_priv->last_seqno < seqno;
1433 }
1434
1435 /**
1436 * intel_ring_sync - sync the waiter to the signaller on seqno
1437 *
1438 * @waiter - ring that is waiting
1439 * @signaller - ring which has, or will signal
1440 * @seqno - seqno which the waiter will block on
1441 */
1442
1443 static int
1444 gen8_ring_sync(struct drm_i915_gem_request *waiter_req,
1445 struct intel_engine_cs *signaller,
1446 u32 seqno)
1447 {
1448 struct intel_engine_cs *waiter = waiter_req->engine;
1449 struct drm_i915_private *dev_priv = waiter->dev->dev_private;
1450 int ret;
1451
1452 ret = intel_ring_begin(waiter_req, 4);
1453 if (ret)
1454 return ret;
1455
1456 intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1457 MI_SEMAPHORE_GLOBAL_GTT |
1458 MI_SEMAPHORE_POLL |
1459 MI_SEMAPHORE_SAD_GTE_SDD);
1460 intel_ring_emit(waiter, seqno);
1461 intel_ring_emit(waiter,
1462 lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1463 intel_ring_emit(waiter,
1464 upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1465 intel_ring_advance(waiter);
1466 return 0;
1467 }
1468
1469 static int
1470 gen6_ring_sync(struct drm_i915_gem_request *waiter_req,
1471 struct intel_engine_cs *signaller,
1472 u32 seqno)
1473 {
1474 struct intel_engine_cs *waiter = waiter_req->engine;
1475 u32 dw1 = MI_SEMAPHORE_MBOX |
1476 MI_SEMAPHORE_COMPARE |
1477 MI_SEMAPHORE_REGISTER;
1478 u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1479 int ret;
1480
1481 /* Throughout all of the GEM code, seqno passed implies our current
1482 * seqno is >= the last seqno executed. However for hardware the
1483 * comparison is strictly greater than.
1484 */
1485 seqno -= 1;
1486
1487 WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
1488
1489 ret = intel_ring_begin(waiter_req, 4);
1490 if (ret)
1491 return ret;
1492
1493 /* If seqno wrap happened, omit the wait with no-ops */
1494 if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
1495 intel_ring_emit(waiter, dw1 | wait_mbox);
1496 intel_ring_emit(waiter, seqno);
1497 intel_ring_emit(waiter, 0);
1498 intel_ring_emit(waiter, MI_NOOP);
1499 } else {
1500 intel_ring_emit(waiter, MI_NOOP);
1501 intel_ring_emit(waiter, MI_NOOP);
1502 intel_ring_emit(waiter, MI_NOOP);
1503 intel_ring_emit(waiter, MI_NOOP);
1504 }
1505 intel_ring_advance(waiter);
1506
1507 return 0;
1508 }
1509
1510 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
1511 do { \
1512 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
1513 PIPE_CONTROL_DEPTH_STALL); \
1514 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
1515 intel_ring_emit(ring__, 0); \
1516 intel_ring_emit(ring__, 0); \
1517 } while (0)
1518
1519 static int
1520 pc_render_add_request(struct drm_i915_gem_request *req)
1521 {
1522 struct intel_engine_cs *engine = req->engine;
1523 u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1524 int ret;
1525
1526 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1527 * incoherent with writes to memory, i.e. completely fubar,
1528 * so we need to use PIPE_NOTIFY instead.
1529 *
1530 * However, we also need to workaround the qword write
1531 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1532 * memory before requesting an interrupt.
1533 */
1534 ret = intel_ring_begin(req, 32);
1535 if (ret)
1536 return ret;
1537
1538 intel_ring_emit(engine,
1539 GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1540 PIPE_CONTROL_WRITE_FLUSH |
1541 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
1542 intel_ring_emit(engine,
1543 engine->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1544 intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1545 intel_ring_emit(engine, 0);
1546 PIPE_CONTROL_FLUSH(engine, scratch_addr);
1547 scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
1548 PIPE_CONTROL_FLUSH(engine, scratch_addr);
1549 scratch_addr += 2 * CACHELINE_BYTES;
1550 PIPE_CONTROL_FLUSH(engine, scratch_addr);
1551 scratch_addr += 2 * CACHELINE_BYTES;
1552 PIPE_CONTROL_FLUSH(engine, scratch_addr);
1553 scratch_addr += 2 * CACHELINE_BYTES;
1554 PIPE_CONTROL_FLUSH(engine, scratch_addr);
1555 scratch_addr += 2 * CACHELINE_BYTES;
1556 PIPE_CONTROL_FLUSH(engine, scratch_addr);
1557
1558 intel_ring_emit(engine,
1559 GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1560 PIPE_CONTROL_WRITE_FLUSH |
1561 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
1562 PIPE_CONTROL_NOTIFY);
1563 intel_ring_emit(engine,
1564 engine->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1565 intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1566 intel_ring_emit(engine, 0);
1567 __intel_ring_advance(engine);
1568
1569 return 0;
1570 }
1571
1572 static void
1573 gen6_seqno_barrier(struct intel_engine_cs *engine)
1574 {
1575 /* Workaround to force correct ordering between irq and seqno writes on
1576 * ivb (and maybe also on snb) by reading from a CS register (like
1577 * ACTHD) before reading the status page.
1578 *
1579 * Note that this effectively stalls the read by the time it takes to
1580 * do a memory transaction, which more or less ensures that the write
1581 * from the GPU has sufficient time to invalidate the CPU cacheline.
1582 * Alternatively we could delay the interrupt from the CS ring to give
1583 * the write time to land, but that would incur a delay after every
1584 * batch i.e. much more frequent than a delay when waiting for the
1585 * interrupt (with the same net latency).
1586 */
1587 struct drm_i915_private *dev_priv = engine->dev->dev_private;
1588 POSTING_READ_FW(RING_ACTHD(engine->mmio_base));
1589 }
1590
1591 static u32
1592 ring_get_seqno(struct intel_engine_cs *engine)
1593 {
1594 return intel_read_status_page(engine, I915_GEM_HWS_INDEX);
1595 }
1596
1597 static void
1598 ring_set_seqno(struct intel_engine_cs *engine, u32 seqno)
1599 {
1600 intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno);
1601 }
1602
1603 static u32
1604 pc_render_get_seqno(struct intel_engine_cs *engine)
1605 {
1606 return engine->scratch.cpu_page[0];
1607 }
1608
1609 static void
1610 pc_render_set_seqno(struct intel_engine_cs *engine, u32 seqno)
1611 {
1612 engine->scratch.cpu_page[0] = seqno;
1613 }
1614
1615 static bool
1616 gen5_ring_get_irq(struct intel_engine_cs *engine)
1617 {
1618 struct drm_device *dev = engine->dev;
1619 struct drm_i915_private *dev_priv = dev->dev_private;
1620 unsigned long flags;
1621
1622 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1623 return false;
1624
1625 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1626 if (engine->irq_refcount++ == 0)
1627 gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask);
1628 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1629
1630 return true;
1631 }
1632
1633 static void
1634 gen5_ring_put_irq(struct intel_engine_cs *engine)
1635 {
1636 struct drm_device *dev = engine->dev;
1637 struct drm_i915_private *dev_priv = dev->dev_private;
1638 unsigned long flags;
1639
1640 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1641 if (--engine->irq_refcount == 0)
1642 gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask);
1643 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1644 }
1645
1646 static bool
1647 i9xx_ring_get_irq(struct intel_engine_cs *engine)
1648 {
1649 struct drm_device *dev = engine->dev;
1650 struct drm_i915_private *dev_priv = dev->dev_private;
1651 unsigned long flags;
1652
1653 if (!intel_irqs_enabled(dev_priv))
1654 return false;
1655
1656 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1657 if (engine->irq_refcount++ == 0) {
1658 dev_priv->irq_mask &= ~engine->irq_enable_mask;
1659 I915_WRITE(IMR, dev_priv->irq_mask);
1660 POSTING_READ(IMR);
1661 }
1662 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1663
1664 return true;
1665 }
1666
1667 static void
1668 i9xx_ring_put_irq(struct intel_engine_cs *engine)
1669 {
1670 struct drm_device *dev = engine->dev;
1671 struct drm_i915_private *dev_priv = dev->dev_private;
1672 unsigned long flags;
1673
1674 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1675 if (--engine->irq_refcount == 0) {
1676 dev_priv->irq_mask |= engine->irq_enable_mask;
1677 I915_WRITE(IMR, dev_priv->irq_mask);
1678 POSTING_READ(IMR);
1679 }
1680 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1681 }
1682
1683 static bool
1684 i8xx_ring_get_irq(struct intel_engine_cs *engine)
1685 {
1686 struct drm_device *dev = engine->dev;
1687 struct drm_i915_private *dev_priv = dev->dev_private;
1688 unsigned long flags;
1689
1690 if (!intel_irqs_enabled(dev_priv))
1691 return false;
1692
1693 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1694 if (engine->irq_refcount++ == 0) {
1695 dev_priv->irq_mask &= ~engine->irq_enable_mask;
1696 I915_WRITE16(IMR, dev_priv->irq_mask);
1697 POSTING_READ16(IMR);
1698 }
1699 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1700
1701 return true;
1702 }
1703
1704 static void
1705 i8xx_ring_put_irq(struct intel_engine_cs *engine)
1706 {
1707 struct drm_device *dev = engine->dev;
1708 struct drm_i915_private *dev_priv = dev->dev_private;
1709 unsigned long flags;
1710
1711 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1712 if (--engine->irq_refcount == 0) {
1713 dev_priv->irq_mask |= engine->irq_enable_mask;
1714 I915_WRITE16(IMR, dev_priv->irq_mask);
1715 POSTING_READ16(IMR);
1716 }
1717 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1718 }
1719
1720 static int
1721 bsd_ring_flush(struct drm_i915_gem_request *req,
1722 u32 invalidate_domains,
1723 u32 flush_domains)
1724 {
1725 struct intel_engine_cs *engine = req->engine;
1726 int ret;
1727
1728 ret = intel_ring_begin(req, 2);
1729 if (ret)
1730 return ret;
1731
1732 intel_ring_emit(engine, MI_FLUSH);
1733 intel_ring_emit(engine, MI_NOOP);
1734 intel_ring_advance(engine);
1735 return 0;
1736 }
1737
1738 static int
1739 i9xx_add_request(struct drm_i915_gem_request *req)
1740 {
1741 struct intel_engine_cs *engine = req->engine;
1742 int ret;
1743
1744 ret = intel_ring_begin(req, 4);
1745 if (ret)
1746 return ret;
1747
1748 intel_ring_emit(engine, MI_STORE_DWORD_INDEX);
1749 intel_ring_emit(engine,
1750 I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1751 intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1752 intel_ring_emit(engine, MI_USER_INTERRUPT);
1753 __intel_ring_advance(engine);
1754
1755 return 0;
1756 }
1757
1758 static bool
1759 gen6_ring_get_irq(struct intel_engine_cs *engine)
1760 {
1761 struct drm_device *dev = engine->dev;
1762 struct drm_i915_private *dev_priv = dev->dev_private;
1763 unsigned long flags;
1764
1765 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1766 return false;
1767
1768 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1769 if (engine->irq_refcount++ == 0) {
1770 if (HAS_L3_DPF(dev) && engine->id == RCS)
1771 I915_WRITE_IMR(engine,
1772 ~(engine->irq_enable_mask |
1773 GT_PARITY_ERROR(dev)));
1774 else
1775 I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
1776 gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask);
1777 }
1778 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1779
1780 return true;
1781 }
1782
1783 static void
1784 gen6_ring_put_irq(struct intel_engine_cs *engine)
1785 {
1786 struct drm_device *dev = engine->dev;
1787 struct drm_i915_private *dev_priv = dev->dev_private;
1788 unsigned long flags;
1789
1790 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1791 if (--engine->irq_refcount == 0) {
1792 if (HAS_L3_DPF(dev) && engine->id == RCS)
1793 I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev));
1794 else
1795 I915_WRITE_IMR(engine, ~0);
1796 gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask);
1797 }
1798 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1799 }
1800
1801 static bool
1802 hsw_vebox_get_irq(struct intel_engine_cs *engine)
1803 {
1804 struct drm_device *dev = engine->dev;
1805 struct drm_i915_private *dev_priv = dev->dev_private;
1806 unsigned long flags;
1807
1808 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1809 return false;
1810
1811 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1812 if (engine->irq_refcount++ == 0) {
1813 I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
1814 gen6_enable_pm_irq(dev_priv, engine->irq_enable_mask);
1815 }
1816 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1817
1818 return true;
1819 }
1820
1821 static void
1822 hsw_vebox_put_irq(struct intel_engine_cs *engine)
1823 {
1824 struct drm_device *dev = engine->dev;
1825 struct drm_i915_private *dev_priv = dev->dev_private;
1826 unsigned long flags;
1827
1828 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1829 if (--engine->irq_refcount == 0) {
1830 I915_WRITE_IMR(engine, ~0);
1831 gen6_disable_pm_irq(dev_priv, engine->irq_enable_mask);
1832 }
1833 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1834 }
1835
1836 static bool
1837 gen8_ring_get_irq(struct intel_engine_cs *engine)
1838 {
1839 struct drm_device *dev = engine->dev;
1840 struct drm_i915_private *dev_priv = dev->dev_private;
1841 unsigned long flags;
1842
1843 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1844 return false;
1845
1846 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1847 if (engine->irq_refcount++ == 0) {
1848 if (HAS_L3_DPF(dev) && engine->id == RCS) {
1849 I915_WRITE_IMR(engine,
1850 ~(engine->irq_enable_mask |
1851 GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1852 } else {
1853 I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
1854 }
1855 POSTING_READ(RING_IMR(engine->mmio_base));
1856 }
1857 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1858
1859 return true;
1860 }
1861
1862 static void
1863 gen8_ring_put_irq(struct intel_engine_cs *engine)
1864 {
1865 struct drm_device *dev = engine->dev;
1866 struct drm_i915_private *dev_priv = dev->dev_private;
1867 unsigned long flags;
1868
1869 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1870 if (--engine->irq_refcount == 0) {
1871 if (HAS_L3_DPF(dev) && engine->id == RCS) {
1872 I915_WRITE_IMR(engine,
1873 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1874 } else {
1875 I915_WRITE_IMR(engine, ~0);
1876 }
1877 POSTING_READ(RING_IMR(engine->mmio_base));
1878 }
1879 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1880 }
1881
1882 static int
1883 i965_dispatch_execbuffer(struct drm_i915_gem_request *req,
1884 u64 offset, u32 length,
1885 unsigned dispatch_flags)
1886 {
1887 struct intel_engine_cs *engine = req->engine;
1888 int ret;
1889
1890 ret = intel_ring_begin(req, 2);
1891 if (ret)
1892 return ret;
1893
1894 intel_ring_emit(engine,
1895 MI_BATCH_BUFFER_START |
1896 MI_BATCH_GTT |
1897 (dispatch_flags & I915_DISPATCH_SECURE ?
1898 0 : MI_BATCH_NON_SECURE_I965));
1899 intel_ring_emit(engine, offset);
1900 intel_ring_advance(engine);
1901
1902 return 0;
1903 }
1904
1905 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1906 #define I830_BATCH_LIMIT (256*1024)
1907 #define I830_TLB_ENTRIES (2)
1908 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
1909 static int
1910 i830_dispatch_execbuffer(struct drm_i915_gem_request *req,
1911 u64 offset, u32 len,
1912 unsigned dispatch_flags)
1913 {
1914 struct intel_engine_cs *engine = req->engine;
1915 u32 cs_offset = engine->scratch.gtt_offset;
1916 int ret;
1917
1918 ret = intel_ring_begin(req, 6);
1919 if (ret)
1920 return ret;
1921
1922 /* Evict the invalid PTE TLBs */
1923 intel_ring_emit(engine, COLOR_BLT_CMD | BLT_WRITE_RGBA);
1924 intel_ring_emit(engine, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
1925 intel_ring_emit(engine, I830_TLB_ENTRIES << 16 | 4); /* load each page */
1926 intel_ring_emit(engine, cs_offset);
1927 intel_ring_emit(engine, 0xdeadbeef);
1928 intel_ring_emit(engine, MI_NOOP);
1929 intel_ring_advance(engine);
1930
1931 if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) {
1932 if (len > I830_BATCH_LIMIT)
1933 return -ENOSPC;
1934
1935 ret = intel_ring_begin(req, 6 + 2);
1936 if (ret)
1937 return ret;
1938
1939 /* Blit the batch (which has now all relocs applied) to the
1940 * stable batch scratch bo area (so that the CS never
1941 * stumbles over its tlb invalidation bug) ...
1942 */
1943 intel_ring_emit(engine, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
1944 intel_ring_emit(engine,
1945 BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
1946 intel_ring_emit(engine, DIV_ROUND_UP(len, 4096) << 16 | 4096);
1947 intel_ring_emit(engine, cs_offset);
1948 intel_ring_emit(engine, 4096);
1949 intel_ring_emit(engine, offset);
1950
1951 intel_ring_emit(engine, MI_FLUSH);
1952 intel_ring_emit(engine, MI_NOOP);
1953 intel_ring_advance(engine);
1954
1955 /* ... and execute it. */
1956 offset = cs_offset;
1957 }
1958
1959 ret = intel_ring_begin(req, 2);
1960 if (ret)
1961 return ret;
1962
1963 intel_ring_emit(engine, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1964 intel_ring_emit(engine, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1965 0 : MI_BATCH_NON_SECURE));
1966 intel_ring_advance(engine);
1967
1968 return 0;
1969 }
1970
1971 static int
1972 i915_dispatch_execbuffer(struct drm_i915_gem_request *req,
1973 u64 offset, u32 len,
1974 unsigned dispatch_flags)
1975 {
1976 struct intel_engine_cs *engine = req->engine;
1977 int ret;
1978
1979 ret = intel_ring_begin(req, 2);
1980 if (ret)
1981 return ret;
1982
1983 intel_ring_emit(engine, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1984 intel_ring_emit(engine, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1985 0 : MI_BATCH_NON_SECURE));
1986 intel_ring_advance(engine);
1987
1988 return 0;
1989 }
1990
1991 static void cleanup_phys_status_page(struct intel_engine_cs *engine)
1992 {
1993 struct drm_i915_private *dev_priv = to_i915(engine->dev);
1994
1995 if (!dev_priv->status_page_dmah)
1996 return;
1997
1998 drm_pci_free(engine->dev, dev_priv->status_page_dmah);
1999 engine->status_page.page_addr = NULL;
2000 }
2001
2002 static void cleanup_status_page(struct intel_engine_cs *engine)
2003 {
2004 struct drm_i915_gem_object *obj;
2005
2006 obj = engine->status_page.obj;
2007 if (obj == NULL)
2008 return;
2009
2010 kunmap(sg_page(obj->pages->sgl));
2011 i915_gem_object_ggtt_unpin(obj);
2012 drm_gem_object_unreference(&obj->base);
2013 engine->status_page.obj = NULL;
2014 }
2015
2016 static int init_status_page(struct intel_engine_cs *engine)
2017 {
2018 struct drm_i915_gem_object *obj = engine->status_page.obj;
2019
2020 if (obj == NULL) {
2021 unsigned flags;
2022 int ret;
2023
2024 obj = i915_gem_alloc_object(engine->dev, 4096);
2025 if (obj == NULL) {
2026 DRM_ERROR("Failed to allocate status page\n");
2027 return -ENOMEM;
2028 }
2029
2030 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2031 if (ret)
2032 goto err_unref;
2033
2034 flags = 0;
2035 if (!HAS_LLC(engine->dev))
2036 /* On g33, we cannot place HWS above 256MiB, so
2037 * restrict its pinning to the low mappable arena.
2038 * Though this restriction is not documented for
2039 * gen4, gen5, or byt, they also behave similarly
2040 * and hang if the HWS is placed at the top of the
2041 * GTT. To generalise, it appears that all !llc
2042 * platforms have issues with us placing the HWS
2043 * above the mappable region (even though we never
2044 * actualy map it).
2045 */
2046 flags |= PIN_MAPPABLE;
2047 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
2048 if (ret) {
2049 err_unref:
2050 drm_gem_object_unreference(&obj->base);
2051 return ret;
2052 }
2053
2054 engine->status_page.obj = obj;
2055 }
2056
2057 engine->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
2058 engine->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
2059 memset(engine->status_page.page_addr, 0, PAGE_SIZE);
2060
2061 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
2062 engine->name, engine->status_page.gfx_addr);
2063
2064 return 0;
2065 }
2066
2067 static int init_phys_status_page(struct intel_engine_cs *engine)
2068 {
2069 struct drm_i915_private *dev_priv = engine->dev->dev_private;
2070
2071 if (!dev_priv->status_page_dmah) {
2072 dev_priv->status_page_dmah =
2073 drm_pci_alloc(engine->dev, PAGE_SIZE, PAGE_SIZE);
2074 if (!dev_priv->status_page_dmah)
2075 return -ENOMEM;
2076 }
2077
2078 engine->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
2079 memset(engine->status_page.page_addr, 0, PAGE_SIZE);
2080
2081 return 0;
2082 }
2083
2084 void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
2085 {
2086 if (HAS_LLC(ringbuf->obj->base.dev) && !ringbuf->obj->stolen)
2087 i915_gem_object_unpin_map(ringbuf->obj);
2088 else
2089 iounmap(ringbuf->virtual_start);
2090 ringbuf->vma = NULL;
2091 i915_gem_object_ggtt_unpin(ringbuf->obj);
2092 }
2093
2094 int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
2095 struct intel_ringbuffer *ringbuf)
2096 {
2097 struct drm_i915_private *dev_priv = to_i915(dev);
2098 struct i915_ggtt *ggtt = &dev_priv->ggtt;
2099 struct drm_i915_gem_object *obj = ringbuf->obj;
2100 /* Ring wraparound at offset 0 sometimes hangs. No idea why. */
2101 unsigned flags = PIN_OFFSET_BIAS | 4096;
2102 int ret;
2103
2104 if (HAS_LLC(dev_priv) && !obj->stolen) {
2105 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, flags);
2106 if (ret)
2107 return ret;
2108
2109 ret = i915_gem_object_set_to_cpu_domain(obj, true);
2110 if (ret)
2111 goto err_unpin;
2112
2113 ringbuf->virtual_start = i915_gem_object_pin_map(obj);
2114 if (ringbuf->virtual_start == NULL) {
2115 ret = -ENOMEM;
2116 goto err_unpin;
2117 }
2118 } else {
2119 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE,
2120 flags | PIN_MAPPABLE);
2121 if (ret)
2122 return ret;
2123
2124 ret = i915_gem_object_set_to_gtt_domain(obj, true);
2125 if (ret)
2126 goto err_unpin;
2127
2128 /* Access through the GTT requires the device to be awake. */
2129 assert_rpm_wakelock_held(dev_priv);
2130
2131 ringbuf->virtual_start = ioremap_wc(ggtt->mappable_base +
2132 i915_gem_obj_ggtt_offset(obj), ringbuf->size);
2133 if (ringbuf->virtual_start == NULL) {
2134 ret = -ENOMEM;
2135 goto err_unpin;
2136 }
2137 }
2138
2139 ringbuf->vma = i915_gem_obj_to_ggtt(obj);
2140 return 0;
2141
2142 err_unpin:
2143 i915_gem_object_ggtt_unpin(obj);
2144 return ret;
2145 }
2146
2147 static void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
2148 {
2149 drm_gem_object_unreference(&ringbuf->obj->base);
2150 ringbuf->obj = NULL;
2151 }
2152
2153 static int intel_alloc_ringbuffer_obj(struct drm_device *dev,
2154 struct intel_ringbuffer *ringbuf)
2155 {
2156 struct drm_i915_gem_object *obj;
2157
2158 obj = NULL;
2159 if (!HAS_LLC(dev))
2160 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
2161 if (obj == NULL)
2162 obj = i915_gem_alloc_object(dev, ringbuf->size);
2163 if (obj == NULL)
2164 return -ENOMEM;
2165
2166 /* mark ring buffers as read-only from GPU side by default */
2167 obj->gt_ro = 1;
2168
2169 ringbuf->obj = obj;
2170
2171 return 0;
2172 }
2173
2174 struct intel_ringbuffer *
2175 intel_engine_create_ringbuffer(struct intel_engine_cs *engine, int size)
2176 {
2177 struct intel_ringbuffer *ring;
2178 int ret;
2179
2180 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
2181 if (ring == NULL) {
2182 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n",
2183 engine->name);
2184 return ERR_PTR(-ENOMEM);
2185 }
2186
2187 ring->engine = engine;
2188 list_add(&ring->link, &engine->buffers);
2189
2190 ring->size = size;
2191 /* Workaround an erratum on the i830 which causes a hang if
2192 * the TAIL pointer points to within the last 2 cachelines
2193 * of the buffer.
2194 */
2195 ring->effective_size = size;
2196 if (IS_I830(engine->dev) || IS_845G(engine->dev))
2197 ring->effective_size -= 2 * CACHELINE_BYTES;
2198
2199 ring->last_retired_head = -1;
2200 intel_ring_update_space(ring);
2201
2202 ret = intel_alloc_ringbuffer_obj(engine->dev, ring);
2203 if (ret) {
2204 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s: %d\n",
2205 engine->name, ret);
2206 list_del(&ring->link);
2207 kfree(ring);
2208 return ERR_PTR(ret);
2209 }
2210
2211 return ring;
2212 }
2213
2214 void
2215 intel_ringbuffer_free(struct intel_ringbuffer *ring)
2216 {
2217 intel_destroy_ringbuffer_obj(ring);
2218 list_del(&ring->link);
2219 kfree(ring);
2220 }
2221
2222 static int intel_init_ring_buffer(struct drm_device *dev,
2223 struct intel_engine_cs *engine)
2224 {
2225 struct intel_ringbuffer *ringbuf;
2226 int ret;
2227
2228 WARN_ON(engine->buffer);
2229
2230 engine->dev = dev;
2231 INIT_LIST_HEAD(&engine->active_list);
2232 INIT_LIST_HEAD(&engine->request_list);
2233 INIT_LIST_HEAD(&engine->execlist_queue);
2234 INIT_LIST_HEAD(&engine->buffers);
2235 i915_gem_batch_pool_init(dev, &engine->batch_pool);
2236 memset(engine->semaphore.sync_seqno, 0,
2237 sizeof(engine->semaphore.sync_seqno));
2238
2239 init_waitqueue_head(&engine->irq_queue);
2240
2241 ringbuf = intel_engine_create_ringbuffer(engine, 32 * PAGE_SIZE);
2242 if (IS_ERR(ringbuf)) {
2243 ret = PTR_ERR(ringbuf);
2244 goto error;
2245 }
2246 engine->buffer = ringbuf;
2247
2248 if (I915_NEED_GFX_HWS(dev)) {
2249 ret = init_status_page(engine);
2250 if (ret)
2251 goto error;
2252 } else {
2253 WARN_ON(engine->id != RCS);
2254 ret = init_phys_status_page(engine);
2255 if (ret)
2256 goto error;
2257 }
2258
2259 ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
2260 if (ret) {
2261 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
2262 engine->name, ret);
2263 intel_destroy_ringbuffer_obj(ringbuf);
2264 goto error;
2265 }
2266
2267 ret = i915_cmd_parser_init_ring(engine);
2268 if (ret)
2269 goto error;
2270
2271 return 0;
2272
2273 error:
2274 intel_cleanup_engine(engine);
2275 return ret;
2276 }
2277
2278 void intel_cleanup_engine(struct intel_engine_cs *engine)
2279 {
2280 struct drm_i915_private *dev_priv;
2281
2282 if (!intel_engine_initialized(engine))
2283 return;
2284
2285 dev_priv = to_i915(engine->dev);
2286
2287 if (engine->buffer) {
2288 intel_stop_engine(engine);
2289 WARN_ON(!IS_GEN2(engine->dev) && (I915_READ_MODE(engine) & MODE_IDLE) == 0);
2290
2291 intel_unpin_ringbuffer_obj(engine->buffer);
2292 intel_ringbuffer_free(engine->buffer);
2293 engine->buffer = NULL;
2294 }
2295
2296 if (engine->cleanup)
2297 engine->cleanup(engine);
2298
2299 if (I915_NEED_GFX_HWS(engine->dev)) {
2300 cleanup_status_page(engine);
2301 } else {
2302 WARN_ON(engine->id != RCS);
2303 cleanup_phys_status_page(engine);
2304 }
2305
2306 i915_cmd_parser_fini_ring(engine);
2307 i915_gem_batch_pool_fini(&engine->batch_pool);
2308 engine->dev = NULL;
2309 }
2310
2311 static int ring_wait_for_space(struct intel_engine_cs *engine, int n)
2312 {
2313 struct intel_ringbuffer *ringbuf = engine->buffer;
2314 struct drm_i915_gem_request *request;
2315 unsigned space;
2316 int ret;
2317
2318 if (intel_ring_space(ringbuf) >= n)
2319 return 0;
2320
2321 /* The whole point of reserving space is to not wait! */
2322 WARN_ON(ringbuf->reserved_in_use);
2323
2324 list_for_each_entry(request, &engine->request_list, list) {
2325 space = __intel_ring_space(request->postfix, ringbuf->tail,
2326 ringbuf->size);
2327 if (space >= n)
2328 break;
2329 }
2330
2331 if (WARN_ON(&request->list == &engine->request_list))
2332 return -ENOSPC;
2333
2334 ret = i915_wait_request(request);
2335 if (ret)
2336 return ret;
2337
2338 ringbuf->space = space;
2339 return 0;
2340 }
2341
2342 static void __wrap_ring_buffer(struct intel_ringbuffer *ringbuf)
2343 {
2344 uint32_t __iomem *virt;
2345 int rem = ringbuf->size - ringbuf->tail;
2346
2347 virt = ringbuf->virtual_start + ringbuf->tail;
2348 rem /= 4;
2349 while (rem--)
2350 iowrite32(MI_NOOP, virt++);
2351
2352 ringbuf->tail = 0;
2353 intel_ring_update_space(ringbuf);
2354 }
2355
2356 int intel_engine_idle(struct intel_engine_cs *engine)
2357 {
2358 struct drm_i915_gem_request *req;
2359
2360 /* Wait upon the last request to be completed */
2361 if (list_empty(&engine->request_list))
2362 return 0;
2363
2364 req = list_entry(engine->request_list.prev,
2365 struct drm_i915_gem_request,
2366 list);
2367
2368 /* Make sure we do not trigger any retires */
2369 return __i915_wait_request(req,
2370 req->i915->mm.interruptible,
2371 NULL, NULL);
2372 }
2373
2374 int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request)
2375 {
2376 request->ringbuf = request->engine->buffer;
2377 return 0;
2378 }
2379
2380 int intel_ring_reserve_space(struct drm_i915_gem_request *request)
2381 {
2382 /*
2383 * The first call merely notes the reserve request and is common for
2384 * all back ends. The subsequent localised _begin() call actually
2385 * ensures that the reservation is available. Without the begin, if
2386 * the request creator immediately submitted the request without
2387 * adding any commands to it then there might not actually be
2388 * sufficient room for the submission commands.
2389 */
2390 intel_ring_reserved_space_reserve(request->ringbuf, MIN_SPACE_FOR_ADD_REQUEST);
2391
2392 return intel_ring_begin(request, 0);
2393 }
2394
2395 void intel_ring_reserved_space_reserve(struct intel_ringbuffer *ringbuf, int size)
2396 {
2397 WARN_ON(ringbuf->reserved_size);
2398 WARN_ON(ringbuf->reserved_in_use);
2399
2400 ringbuf->reserved_size = size;
2401 }
2402
2403 void intel_ring_reserved_space_cancel(struct intel_ringbuffer *ringbuf)
2404 {
2405 WARN_ON(ringbuf->reserved_in_use);
2406
2407 ringbuf->reserved_size = 0;
2408 ringbuf->reserved_in_use = false;
2409 }
2410
2411 void intel_ring_reserved_space_use(struct intel_ringbuffer *ringbuf)
2412 {
2413 WARN_ON(ringbuf->reserved_in_use);
2414
2415 ringbuf->reserved_in_use = true;
2416 ringbuf->reserved_tail = ringbuf->tail;
2417 }
2418
2419 void intel_ring_reserved_space_end(struct intel_ringbuffer *ringbuf)
2420 {
2421 WARN_ON(!ringbuf->reserved_in_use);
2422 if (ringbuf->tail > ringbuf->reserved_tail) {
2423 WARN(ringbuf->tail > ringbuf->reserved_tail + ringbuf->reserved_size,
2424 "request reserved size too small: %d vs %d!\n",
2425 ringbuf->tail - ringbuf->reserved_tail, ringbuf->reserved_size);
2426 } else {
2427 /*
2428 * The ring was wrapped while the reserved space was in use.
2429 * That means that some unknown amount of the ring tail was
2430 * no-op filled and skipped. Thus simply adding the ring size
2431 * to the tail and doing the above space check will not work.
2432 * Rather than attempt to track how much tail was skipped,
2433 * it is much simpler to say that also skipping the sanity
2434 * check every once in a while is not a big issue.
2435 */
2436 }
2437
2438 ringbuf->reserved_size = 0;
2439 ringbuf->reserved_in_use = false;
2440 }
2441
2442 static int __intel_ring_prepare(struct intel_engine_cs *engine, int bytes)
2443 {
2444 struct intel_ringbuffer *ringbuf = engine->buffer;
2445 int remain_usable = ringbuf->effective_size - ringbuf->tail;
2446 int remain_actual = ringbuf->size - ringbuf->tail;
2447 int ret, total_bytes, wait_bytes = 0;
2448 bool need_wrap = false;
2449
2450 if (ringbuf->reserved_in_use)
2451 total_bytes = bytes;
2452 else
2453 total_bytes = bytes + ringbuf->reserved_size;
2454
2455 if (unlikely(bytes > remain_usable)) {
2456 /*
2457 * Not enough space for the basic request. So need to flush
2458 * out the remainder and then wait for base + reserved.
2459 */
2460 wait_bytes = remain_actual + total_bytes;
2461 need_wrap = true;
2462 } else {
2463 if (unlikely(total_bytes > remain_usable)) {
2464 /*
2465 * The base request will fit but the reserved space
2466 * falls off the end. So don't need an immediate wrap
2467 * and only need to effectively wait for the reserved
2468 * size space from the start of ringbuffer.
2469 */
2470 wait_bytes = remain_actual + ringbuf->reserved_size;
2471 } else if (total_bytes > ringbuf->space) {
2472 /* No wrapping required, just waiting. */
2473 wait_bytes = total_bytes;
2474 }
2475 }
2476
2477 if (wait_bytes) {
2478 ret = ring_wait_for_space(engine, wait_bytes);
2479 if (unlikely(ret))
2480 return ret;
2481
2482 if (need_wrap)
2483 __wrap_ring_buffer(ringbuf);
2484 }
2485
2486 return 0;
2487 }
2488
2489 int intel_ring_begin(struct drm_i915_gem_request *req,
2490 int num_dwords)
2491 {
2492 struct intel_engine_cs *engine;
2493 struct drm_i915_private *dev_priv;
2494 int ret;
2495
2496 WARN_ON(req == NULL);
2497 engine = req->engine;
2498 dev_priv = req->i915;
2499
2500 ret = __intel_ring_prepare(engine, num_dwords * sizeof(uint32_t));
2501 if (ret)
2502 return ret;
2503
2504 engine->buffer->space -= num_dwords * sizeof(uint32_t);
2505 return 0;
2506 }
2507
2508 /* Align the ring tail to a cacheline boundary */
2509 int intel_ring_cacheline_align(struct drm_i915_gem_request *req)
2510 {
2511 struct intel_engine_cs *engine = req->engine;
2512 int num_dwords = (engine->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
2513 int ret;
2514
2515 if (num_dwords == 0)
2516 return 0;
2517
2518 num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
2519 ret = intel_ring_begin(req, num_dwords);
2520 if (ret)
2521 return ret;
2522
2523 while (num_dwords--)
2524 intel_ring_emit(engine, MI_NOOP);
2525
2526 intel_ring_advance(engine);
2527
2528 return 0;
2529 }
2530
2531 void intel_ring_init_seqno(struct intel_engine_cs *engine, u32 seqno)
2532 {
2533 struct drm_i915_private *dev_priv = to_i915(engine->dev);
2534
2535 /* Our semaphore implementation is strictly monotonic (i.e. we proceed
2536 * so long as the semaphore value in the register/page is greater
2537 * than the sync value), so whenever we reset the seqno,
2538 * so long as we reset the tracking semaphore value to 0, it will
2539 * always be before the next request's seqno. If we don't reset
2540 * the semaphore value, then when the seqno moves backwards all
2541 * future waits will complete instantly (causing rendering corruption).
2542 */
2543 if (INTEL_INFO(dev_priv)->gen == 6 || INTEL_INFO(dev_priv)->gen == 7) {
2544 I915_WRITE(RING_SYNC_0(engine->mmio_base), 0);
2545 I915_WRITE(RING_SYNC_1(engine->mmio_base), 0);
2546 if (HAS_VEBOX(dev_priv))
2547 I915_WRITE(RING_SYNC_2(engine->mmio_base), 0);
2548 }
2549 if (dev_priv->semaphore_obj) {
2550 struct drm_i915_gem_object *obj = dev_priv->semaphore_obj;
2551 struct page *page = i915_gem_object_get_dirty_page(obj, 0);
2552 void *semaphores = kmap(page);
2553 memset(semaphores + GEN8_SEMAPHORE_OFFSET(engine->id, 0),
2554 0, I915_NUM_ENGINES * gen8_semaphore_seqno_size);
2555 kunmap(page);
2556 }
2557 memset(engine->semaphore.sync_seqno, 0,
2558 sizeof(engine->semaphore.sync_seqno));
2559
2560 engine->set_seqno(engine, seqno);
2561 engine->last_submitted_seqno = seqno;
2562
2563 engine->hangcheck.seqno = seqno;
2564 }
2565
2566 static void gen6_bsd_ring_write_tail(struct intel_engine_cs *engine,
2567 u32 value)
2568 {
2569 struct drm_i915_private *dev_priv = engine->dev->dev_private;
2570
2571 /* Every tail move must follow the sequence below */
2572
2573 /* Disable notification that the ring is IDLE. The GT
2574 * will then assume that it is busy and bring it out of rc6.
2575 */
2576 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2577 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2578
2579 /* Clear the context id. Here be magic! */
2580 I915_WRITE64(GEN6_BSD_RNCID, 0x0);
2581
2582 /* Wait for the ring not to be idle, i.e. for it to wake up. */
2583 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
2584 GEN6_BSD_SLEEP_INDICATOR) == 0,
2585 50))
2586 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
2587
2588 /* Now that the ring is fully powered up, update the tail */
2589 I915_WRITE_TAIL(engine, value);
2590 POSTING_READ(RING_TAIL(engine->mmio_base));
2591
2592 /* Let the ring send IDLE messages to the GT again,
2593 * and so let it sleep to conserve power when idle.
2594 */
2595 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2596 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2597 }
2598
2599 static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req,
2600 u32 invalidate, u32 flush)
2601 {
2602 struct intel_engine_cs *engine = req->engine;
2603 uint32_t cmd;
2604 int ret;
2605
2606 ret = intel_ring_begin(req, 4);
2607 if (ret)
2608 return ret;
2609
2610 cmd = MI_FLUSH_DW;
2611 if (INTEL_INFO(engine->dev)->gen >= 8)
2612 cmd += 1;
2613
2614 /* We always require a command barrier so that subsequent
2615 * commands, such as breadcrumb interrupts, are strictly ordered
2616 * wrt the contents of the write cache being flushed to memory
2617 * (and thus being coherent from the CPU).
2618 */
2619 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2620
2621 /*
2622 * Bspec vol 1c.5 - video engine command streamer:
2623 * "If ENABLED, all TLBs will be invalidated once the flush
2624 * operation is complete. This bit is only valid when the
2625 * Post-Sync Operation field is a value of 1h or 3h."
2626 */
2627 if (invalidate & I915_GEM_GPU_DOMAINS)
2628 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
2629
2630 intel_ring_emit(engine, cmd);
2631 intel_ring_emit(engine,
2632 I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2633 if (INTEL_INFO(engine->dev)->gen >= 8) {
2634 intel_ring_emit(engine, 0); /* upper addr */
2635 intel_ring_emit(engine, 0); /* value */
2636 } else {
2637 intel_ring_emit(engine, 0);
2638 intel_ring_emit(engine, MI_NOOP);
2639 }
2640 intel_ring_advance(engine);
2641 return 0;
2642 }
2643
2644 static int
2645 gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2646 u64 offset, u32 len,
2647 unsigned dispatch_flags)
2648 {
2649 struct intel_engine_cs *engine = req->engine;
2650 bool ppgtt = USES_PPGTT(engine->dev) &&
2651 !(dispatch_flags & I915_DISPATCH_SECURE);
2652 int ret;
2653
2654 ret = intel_ring_begin(req, 4);
2655 if (ret)
2656 return ret;
2657
2658 /* FIXME(BDW): Address space and security selectors. */
2659 intel_ring_emit(engine, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8) |
2660 (dispatch_flags & I915_DISPATCH_RS ?
2661 MI_BATCH_RESOURCE_STREAMER : 0));
2662 intel_ring_emit(engine, lower_32_bits(offset));
2663 intel_ring_emit(engine, upper_32_bits(offset));
2664 intel_ring_emit(engine, MI_NOOP);
2665 intel_ring_advance(engine);
2666
2667 return 0;
2668 }
2669
2670 static int
2671 hsw_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2672 u64 offset, u32 len,
2673 unsigned dispatch_flags)
2674 {
2675 struct intel_engine_cs *engine = req->engine;
2676 int ret;
2677
2678 ret = intel_ring_begin(req, 2);
2679 if (ret)
2680 return ret;
2681
2682 intel_ring_emit(engine,
2683 MI_BATCH_BUFFER_START |
2684 (dispatch_flags & I915_DISPATCH_SECURE ?
2685 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) |
2686 (dispatch_flags & I915_DISPATCH_RS ?
2687 MI_BATCH_RESOURCE_STREAMER : 0));
2688 /* bit0-7 is the length on GEN6+ */
2689 intel_ring_emit(engine, offset);
2690 intel_ring_advance(engine);
2691
2692 return 0;
2693 }
2694
2695 static int
2696 gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2697 u64 offset, u32 len,
2698 unsigned dispatch_flags)
2699 {
2700 struct intel_engine_cs *engine = req->engine;
2701 int ret;
2702
2703 ret = intel_ring_begin(req, 2);
2704 if (ret)
2705 return ret;
2706
2707 intel_ring_emit(engine,
2708 MI_BATCH_BUFFER_START |
2709 (dispatch_flags & I915_DISPATCH_SECURE ?
2710 0 : MI_BATCH_NON_SECURE_I965));
2711 /* bit0-7 is the length on GEN6+ */
2712 intel_ring_emit(engine, offset);
2713 intel_ring_advance(engine);
2714
2715 return 0;
2716 }
2717
2718 /* Blitter support (SandyBridge+) */
2719
2720 static int gen6_ring_flush(struct drm_i915_gem_request *req,
2721 u32 invalidate, u32 flush)
2722 {
2723 struct intel_engine_cs *engine = req->engine;
2724 struct drm_device *dev = engine->dev;
2725 uint32_t cmd;
2726 int ret;
2727
2728 ret = intel_ring_begin(req, 4);
2729 if (ret)
2730 return ret;
2731
2732 cmd = MI_FLUSH_DW;
2733 if (INTEL_INFO(dev)->gen >= 8)
2734 cmd += 1;
2735
2736 /* We always require a command barrier so that subsequent
2737 * commands, such as breadcrumb interrupts, are strictly ordered
2738 * wrt the contents of the write cache being flushed to memory
2739 * (and thus being coherent from the CPU).
2740 */
2741 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2742
2743 /*
2744 * Bspec vol 1c.3 - blitter engine command streamer:
2745 * "If ENABLED, all TLBs will be invalidated once the flush
2746 * operation is complete. This bit is only valid when the
2747 * Post-Sync Operation field is a value of 1h or 3h."
2748 */
2749 if (invalidate & I915_GEM_DOMAIN_RENDER)
2750 cmd |= MI_INVALIDATE_TLB;
2751 intel_ring_emit(engine, cmd);
2752 intel_ring_emit(engine,
2753 I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2754 if (INTEL_INFO(dev)->gen >= 8) {
2755 intel_ring_emit(engine, 0); /* upper addr */
2756 intel_ring_emit(engine, 0); /* value */
2757 } else {
2758 intel_ring_emit(engine, 0);
2759 intel_ring_emit(engine, MI_NOOP);
2760 }
2761 intel_ring_advance(engine);
2762
2763 return 0;
2764 }
2765
2766 int intel_init_render_ring_buffer(struct drm_device *dev)
2767 {
2768 struct drm_i915_private *dev_priv = dev->dev_private;
2769 struct intel_engine_cs *engine = &dev_priv->engine[RCS];
2770 struct drm_i915_gem_object *obj;
2771 int ret;
2772
2773 engine->name = "render ring";
2774 engine->id = RCS;
2775 engine->exec_id = I915_EXEC_RENDER;
2776 engine->mmio_base = RENDER_RING_BASE;
2777
2778 if (INTEL_INFO(dev)->gen >= 8) {
2779 if (i915_semaphore_is_enabled(dev)) {
2780 obj = i915_gem_alloc_object(dev, 4096);
2781 if (obj == NULL) {
2782 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2783 i915.semaphores = 0;
2784 } else {
2785 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2786 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2787 if (ret != 0) {
2788 drm_gem_object_unreference(&obj->base);
2789 DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2790 i915.semaphores = 0;
2791 } else
2792 dev_priv->semaphore_obj = obj;
2793 }
2794 }
2795
2796 engine->init_context = intel_rcs_ctx_init;
2797 engine->add_request = gen6_add_request;
2798 engine->flush = gen8_render_ring_flush;
2799 engine->irq_get = gen8_ring_get_irq;
2800 engine->irq_put = gen8_ring_put_irq;
2801 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2802 engine->irq_seqno_barrier = gen6_seqno_barrier;
2803 engine->get_seqno = ring_get_seqno;
2804 engine->set_seqno = ring_set_seqno;
2805 if (i915_semaphore_is_enabled(dev)) {
2806 WARN_ON(!dev_priv->semaphore_obj);
2807 engine->semaphore.sync_to = gen8_ring_sync;
2808 engine->semaphore.signal = gen8_rcs_signal;
2809 GEN8_RING_SEMAPHORE_INIT(engine);
2810 }
2811 } else if (INTEL_INFO(dev)->gen >= 6) {
2812 engine->init_context = intel_rcs_ctx_init;
2813 engine->add_request = gen6_add_request;
2814 engine->flush = gen7_render_ring_flush;
2815 if (INTEL_INFO(dev)->gen == 6)
2816 engine->flush = gen6_render_ring_flush;
2817 engine->irq_get = gen6_ring_get_irq;
2818 engine->irq_put = gen6_ring_put_irq;
2819 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2820 engine->irq_seqno_barrier = gen6_seqno_barrier;
2821 engine->get_seqno = ring_get_seqno;
2822 engine->set_seqno = ring_set_seqno;
2823 if (i915_semaphore_is_enabled(dev)) {
2824 engine->semaphore.sync_to = gen6_ring_sync;
2825 engine->semaphore.signal = gen6_signal;
2826 /*
2827 * The current semaphore is only applied on pre-gen8
2828 * platform. And there is no VCS2 ring on the pre-gen8
2829 * platform. So the semaphore between RCS and VCS2 is
2830 * initialized as INVALID. Gen8 will initialize the
2831 * sema between VCS2 and RCS later.
2832 */
2833 engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2834 engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2835 engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2836 engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2837 engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2838 engine->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2839 engine->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2840 engine->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2841 engine->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2842 engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2843 }
2844 } else if (IS_GEN5(dev)) {
2845 engine->add_request = pc_render_add_request;
2846 engine->flush = gen4_render_ring_flush;
2847 engine->get_seqno = pc_render_get_seqno;
2848 engine->set_seqno = pc_render_set_seqno;
2849 engine->irq_get = gen5_ring_get_irq;
2850 engine->irq_put = gen5_ring_put_irq;
2851 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
2852 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
2853 } else {
2854 engine->add_request = i9xx_add_request;
2855 if (INTEL_INFO(dev)->gen < 4)
2856 engine->flush = gen2_render_ring_flush;
2857 else
2858 engine->flush = gen4_render_ring_flush;
2859 engine->get_seqno = ring_get_seqno;
2860 engine->set_seqno = ring_set_seqno;
2861 if (IS_GEN2(dev)) {
2862 engine->irq_get = i8xx_ring_get_irq;
2863 engine->irq_put = i8xx_ring_put_irq;
2864 } else {
2865 engine->irq_get = i9xx_ring_get_irq;
2866 engine->irq_put = i9xx_ring_put_irq;
2867 }
2868 engine->irq_enable_mask = I915_USER_INTERRUPT;
2869 }
2870 engine->write_tail = ring_write_tail;
2871
2872 if (IS_HASWELL(dev))
2873 engine->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
2874 else if (IS_GEN8(dev))
2875 engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2876 else if (INTEL_INFO(dev)->gen >= 6)
2877 engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2878 else if (INTEL_INFO(dev)->gen >= 4)
2879 engine->dispatch_execbuffer = i965_dispatch_execbuffer;
2880 else if (IS_I830(dev) || IS_845G(dev))
2881 engine->dispatch_execbuffer = i830_dispatch_execbuffer;
2882 else
2883 engine->dispatch_execbuffer = i915_dispatch_execbuffer;
2884 engine->init_hw = init_render_ring;
2885 engine->cleanup = render_ring_cleanup;
2886
2887 /* Workaround batchbuffer to combat CS tlb bug. */
2888 if (HAS_BROKEN_CS_TLB(dev)) {
2889 obj = i915_gem_alloc_object(dev, I830_WA_SIZE);
2890 if (obj == NULL) {
2891 DRM_ERROR("Failed to allocate batch bo\n");
2892 return -ENOMEM;
2893 }
2894
2895 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
2896 if (ret != 0) {
2897 drm_gem_object_unreference(&obj->base);
2898 DRM_ERROR("Failed to ping batch bo\n");
2899 return ret;
2900 }
2901
2902 engine->scratch.obj = obj;
2903 engine->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
2904 }
2905
2906 ret = intel_init_ring_buffer(dev, engine);
2907 if (ret)
2908 return ret;
2909
2910 if (INTEL_INFO(dev)->gen >= 5) {
2911 ret = intel_init_pipe_control(engine);
2912 if (ret)
2913 return ret;
2914 }
2915
2916 return 0;
2917 }
2918
2919 int intel_init_bsd_ring_buffer(struct drm_device *dev)
2920 {
2921 struct drm_i915_private *dev_priv = dev->dev_private;
2922 struct intel_engine_cs *engine = &dev_priv->engine[VCS];
2923
2924 engine->name = "bsd ring";
2925 engine->id = VCS;
2926 engine->exec_id = I915_EXEC_BSD;
2927
2928 engine->write_tail = ring_write_tail;
2929 if (INTEL_INFO(dev)->gen >= 6) {
2930 engine->mmio_base = GEN6_BSD_RING_BASE;
2931 /* gen6 bsd needs a special wa for tail updates */
2932 if (IS_GEN6(dev))
2933 engine->write_tail = gen6_bsd_ring_write_tail;
2934 engine->flush = gen6_bsd_ring_flush;
2935 engine->add_request = gen6_add_request;
2936 engine->irq_seqno_barrier = gen6_seqno_barrier;
2937 engine->get_seqno = ring_get_seqno;
2938 engine->set_seqno = ring_set_seqno;
2939 if (INTEL_INFO(dev)->gen >= 8) {
2940 engine->irq_enable_mask =
2941 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2942 engine->irq_get = gen8_ring_get_irq;
2943 engine->irq_put = gen8_ring_put_irq;
2944 engine->dispatch_execbuffer =
2945 gen8_ring_dispatch_execbuffer;
2946 if (i915_semaphore_is_enabled(dev)) {
2947 engine->semaphore.sync_to = gen8_ring_sync;
2948 engine->semaphore.signal = gen8_xcs_signal;
2949 GEN8_RING_SEMAPHORE_INIT(engine);
2950 }
2951 } else {
2952 engine->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2953 engine->irq_get = gen6_ring_get_irq;
2954 engine->irq_put = gen6_ring_put_irq;
2955 engine->dispatch_execbuffer =
2956 gen6_ring_dispatch_execbuffer;
2957 if (i915_semaphore_is_enabled(dev)) {
2958 engine->semaphore.sync_to = gen6_ring_sync;
2959 engine->semaphore.signal = gen6_signal;
2960 engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2961 engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2962 engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
2963 engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
2964 engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2965 engine->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
2966 engine->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2967 engine->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
2968 engine->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
2969 engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2970 }
2971 }
2972 } else {
2973 engine->mmio_base = BSD_RING_BASE;
2974 engine->flush = bsd_ring_flush;
2975 engine->add_request = i9xx_add_request;
2976 engine->get_seqno = ring_get_seqno;
2977 engine->set_seqno = ring_set_seqno;
2978 if (IS_GEN5(dev)) {
2979 engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
2980 engine->irq_get = gen5_ring_get_irq;
2981 engine->irq_put = gen5_ring_put_irq;
2982 } else {
2983 engine->irq_enable_mask = I915_BSD_USER_INTERRUPT;
2984 engine->irq_get = i9xx_ring_get_irq;
2985 engine->irq_put = i9xx_ring_put_irq;
2986 }
2987 engine->dispatch_execbuffer = i965_dispatch_execbuffer;
2988 }
2989 engine->init_hw = init_ring_common;
2990
2991 return intel_init_ring_buffer(dev, engine);
2992 }
2993
2994 /**
2995 * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
2996 */
2997 int intel_init_bsd2_ring_buffer(struct drm_device *dev)
2998 {
2999 struct drm_i915_private *dev_priv = dev->dev_private;
3000 struct intel_engine_cs *engine = &dev_priv->engine[VCS2];
3001
3002 engine->name = "bsd2 ring";
3003 engine->id = VCS2;
3004 engine->exec_id = I915_EXEC_BSD;
3005
3006 engine->write_tail = ring_write_tail;
3007 engine->mmio_base = GEN8_BSD2_RING_BASE;
3008 engine->flush = gen6_bsd_ring_flush;
3009 engine->add_request = gen6_add_request;
3010 engine->irq_seqno_barrier = gen6_seqno_barrier;
3011 engine->get_seqno = ring_get_seqno;
3012 engine->set_seqno = ring_set_seqno;
3013 engine->irq_enable_mask =
3014 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
3015 engine->irq_get = gen8_ring_get_irq;
3016 engine->irq_put = gen8_ring_put_irq;
3017 engine->dispatch_execbuffer =
3018 gen8_ring_dispatch_execbuffer;
3019 if (i915_semaphore_is_enabled(dev)) {
3020 engine->semaphore.sync_to = gen8_ring_sync;
3021 engine->semaphore.signal = gen8_xcs_signal;
3022 GEN8_RING_SEMAPHORE_INIT(engine);
3023 }
3024 engine->init_hw = init_ring_common;
3025
3026 return intel_init_ring_buffer(dev, engine);
3027 }
3028
3029 int intel_init_blt_ring_buffer(struct drm_device *dev)
3030 {
3031 struct drm_i915_private *dev_priv = dev->dev_private;
3032 struct intel_engine_cs *engine = &dev_priv->engine[BCS];
3033
3034 engine->name = "blitter ring";
3035 engine->id = BCS;
3036 engine->exec_id = I915_EXEC_BLT;
3037
3038 engine->mmio_base = BLT_RING_BASE;
3039 engine->write_tail = ring_write_tail;
3040 engine->flush = gen6_ring_flush;
3041 engine->add_request = gen6_add_request;
3042 engine->irq_seqno_barrier = gen6_seqno_barrier;
3043 engine->get_seqno = ring_get_seqno;
3044 engine->set_seqno = ring_set_seqno;
3045 if (INTEL_INFO(dev)->gen >= 8) {
3046 engine->irq_enable_mask =
3047 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
3048 engine->irq_get = gen8_ring_get_irq;
3049 engine->irq_put = gen8_ring_put_irq;
3050 engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
3051 if (i915_semaphore_is_enabled(dev)) {
3052 engine->semaphore.sync_to = gen8_ring_sync;
3053 engine->semaphore.signal = gen8_xcs_signal;
3054 GEN8_RING_SEMAPHORE_INIT(engine);
3055 }
3056 } else {
3057 engine->irq_enable_mask = GT_BLT_USER_INTERRUPT;
3058 engine->irq_get = gen6_ring_get_irq;
3059 engine->irq_put = gen6_ring_put_irq;
3060 engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
3061 if (i915_semaphore_is_enabled(dev)) {
3062 engine->semaphore.signal = gen6_signal;
3063 engine->semaphore.sync_to = gen6_ring_sync;
3064 /*
3065 * The current semaphore is only applied on pre-gen8
3066 * platform. And there is no VCS2 ring on the pre-gen8
3067 * platform. So the semaphore between BCS and VCS2 is
3068 * initialized as INVALID. Gen8 will initialize the
3069 * sema between BCS and VCS2 later.
3070 */
3071 engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
3072 engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
3073 engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
3074 engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
3075 engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
3076 engine->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
3077 engine->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
3078 engine->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
3079 engine->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
3080 engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
3081 }
3082 }
3083 engine->init_hw = init_ring_common;
3084
3085 return intel_init_ring_buffer(dev, engine);
3086 }
3087
3088 int intel_init_vebox_ring_buffer(struct drm_device *dev)
3089 {
3090 struct drm_i915_private *dev_priv = dev->dev_private;
3091 struct intel_engine_cs *engine = &dev_priv->engine[VECS];
3092
3093 engine->name = "video enhancement ring";
3094 engine->id = VECS;
3095 engine->exec_id = I915_EXEC_VEBOX;
3096
3097 engine->mmio_base = VEBOX_RING_BASE;
3098 engine->write_tail = ring_write_tail;
3099 engine->flush = gen6_ring_flush;
3100 engine->add_request = gen6_add_request;
3101 engine->irq_seqno_barrier = gen6_seqno_barrier;
3102 engine->get_seqno = ring_get_seqno;
3103 engine->set_seqno = ring_set_seqno;
3104
3105 if (INTEL_INFO(dev)->gen >= 8) {
3106 engine->irq_enable_mask =
3107 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
3108 engine->irq_get = gen8_ring_get_irq;
3109 engine->irq_put = gen8_ring_put_irq;
3110 engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
3111 if (i915_semaphore_is_enabled(dev)) {
3112 engine->semaphore.sync_to = gen8_ring_sync;
3113 engine->semaphore.signal = gen8_xcs_signal;
3114 GEN8_RING_SEMAPHORE_INIT(engine);
3115 }
3116 } else {
3117 engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
3118 engine->irq_get = hsw_vebox_get_irq;
3119 engine->irq_put = hsw_vebox_put_irq;
3120 engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
3121 if (i915_semaphore_is_enabled(dev)) {
3122 engine->semaphore.sync_to = gen6_ring_sync;
3123 engine->semaphore.signal = gen6_signal;
3124 engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
3125 engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
3126 engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
3127 engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
3128 engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
3129 engine->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
3130 engine->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
3131 engine->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
3132 engine->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
3133 engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
3134 }
3135 }
3136 engine->init_hw = init_ring_common;
3137
3138 return intel_init_ring_buffer(dev, engine);
3139 }
3140
3141 int
3142 intel_ring_flush_all_caches(struct drm_i915_gem_request *req)
3143 {
3144 struct intel_engine_cs *engine = req->engine;
3145 int ret;
3146
3147 if (!engine->gpu_caches_dirty)
3148 return 0;
3149
3150 ret = engine->flush(req, 0, I915_GEM_GPU_DOMAINS);
3151 if (ret)
3152 return ret;
3153
3154 trace_i915_gem_ring_flush(req, 0, I915_GEM_GPU_DOMAINS);
3155
3156 engine->gpu_caches_dirty = false;
3157 return 0;
3158 }
3159
3160 int
3161 intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req)
3162 {
3163 struct intel_engine_cs *engine = req->engine;
3164 uint32_t flush_domains;
3165 int ret;
3166
3167 flush_domains = 0;
3168 if (engine->gpu_caches_dirty)
3169 flush_domains = I915_GEM_GPU_DOMAINS;
3170
3171 ret = engine->flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
3172 if (ret)
3173 return ret;
3174
3175 trace_i915_gem_ring_flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
3176
3177 engine->gpu_caches_dirty = false;
3178 return 0;
3179 }
3180
3181 void
3182 intel_stop_engine(struct intel_engine_cs *engine)
3183 {
3184 int ret;
3185
3186 if (!intel_engine_initialized(engine))
3187 return;
3188
3189 ret = intel_engine_idle(engine);
3190 if (ret)
3191 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
3192 engine->name, ret);
3193
3194 stop_ring(engine);
3195 }
Linux kernel - Deliverables
This page took 0.127973 seconds and 5 git commands to generate.