2 * Copyright © 2008-2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
32 #include <drm/i915_drm.h>
33 #include "i915_trace.h"
34 #include "intel_drv.h"
37 intel_ring_initialized(struct intel_engine_cs
*ring
)
39 struct drm_device
*dev
= ring
->dev
;
44 if (i915
.enable_execlists
) {
45 struct intel_context
*dctx
= ring
->default_context
;
46 struct intel_ringbuffer
*ringbuf
= dctx
->engine
[ring
->id
].ringbuf
;
50 return ring
->buffer
&& ring
->buffer
->obj
;
53 int __intel_ring_space(int head
, int tail
, int size
)
55 int space
= head
- (tail
+ I915_RING_FREE_SPACE
);
61 int intel_ring_space(struct intel_ringbuffer
*ringbuf
)
63 return __intel_ring_space(ringbuf
->head
& HEAD_ADDR
,
64 ringbuf
->tail
, ringbuf
->size
);
67 bool intel_ring_stopped(struct intel_engine_cs
*ring
)
69 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
70 return dev_priv
->gpu_error
.stop_rings
& intel_ring_flag(ring
);
73 void __intel_ring_advance(struct intel_engine_cs
*ring
)
75 struct intel_ringbuffer
*ringbuf
= ring
->buffer
;
76 ringbuf
->tail
&= ringbuf
->size
- 1;
77 if (intel_ring_stopped(ring
))
79 ring
->write_tail(ring
, ringbuf
->tail
);
83 gen2_render_ring_flush(struct intel_engine_cs
*ring
,
84 u32 invalidate_domains
,
91 if (((invalidate_domains
|flush_domains
) & I915_GEM_DOMAIN_RENDER
) == 0)
92 cmd
|= MI_NO_WRITE_FLUSH
;
94 if (invalidate_domains
& I915_GEM_DOMAIN_SAMPLER
)
97 ret
= intel_ring_begin(ring
, 2);
101 intel_ring_emit(ring
, cmd
);
102 intel_ring_emit(ring
, MI_NOOP
);
103 intel_ring_advance(ring
);
109 gen4_render_ring_flush(struct intel_engine_cs
*ring
,
110 u32 invalidate_domains
,
113 struct drm_device
*dev
= ring
->dev
;
120 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
121 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
122 * also flushed at 2d versus 3d pipeline switches.
126 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
127 * MI_READ_FLUSH is set, and is always flushed on 965.
129 * I915_GEM_DOMAIN_COMMAND may not exist?
131 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
132 * invalidated when MI_EXE_FLUSH is set.
134 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
135 * invalidated with every MI_FLUSH.
139 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
140 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
141 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
142 * are flushed at any MI_FLUSH.
145 cmd
= MI_FLUSH
| MI_NO_WRITE_FLUSH
;
146 if ((invalidate_domains
|flush_domains
) & I915_GEM_DOMAIN_RENDER
)
147 cmd
&= ~MI_NO_WRITE_FLUSH
;
148 if (invalidate_domains
& I915_GEM_DOMAIN_INSTRUCTION
)
151 if (invalidate_domains
& I915_GEM_DOMAIN_COMMAND
&&
152 (IS_G4X(dev
) || IS_GEN5(dev
)))
153 cmd
|= MI_INVALIDATE_ISP
;
155 ret
= intel_ring_begin(ring
, 2);
159 intel_ring_emit(ring
, cmd
);
160 intel_ring_emit(ring
, MI_NOOP
);
161 intel_ring_advance(ring
);
167 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
168 * implementing two workarounds on gen6. From section 1.4.7.1
169 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
171 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
172 * produced by non-pipelined state commands), software needs to first
173 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
176 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
177 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
179 * And the workaround for these two requires this workaround first:
181 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
182 * BEFORE the pipe-control with a post-sync op and no write-cache
185 * And this last workaround is tricky because of the requirements on
186 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
189 * "1 of the following must also be set:
190 * - Render Target Cache Flush Enable ([12] of DW1)
191 * - Depth Cache Flush Enable ([0] of DW1)
192 * - Stall at Pixel Scoreboard ([1] of DW1)
193 * - Depth Stall ([13] of DW1)
194 * - Post-Sync Operation ([13] of DW1)
195 * - Notify Enable ([8] of DW1)"
197 * The cache flushes require the workaround flush that triggered this
198 * one, so we can't use it. Depth stall would trigger the same.
199 * Post-sync nonzero is what triggered this second workaround, so we
200 * can't use that one either. Notify enable is IRQs, which aren't
201 * really our business. That leaves only stall at scoreboard.
204 intel_emit_post_sync_nonzero_flush(struct intel_engine_cs
*ring
)
206 u32 scratch_addr
= ring
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
210 ret
= intel_ring_begin(ring
, 6);
214 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(5));
215 intel_ring_emit(ring
, PIPE_CONTROL_CS_STALL
|
216 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
217 intel_ring_emit(ring
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
); /* address */
218 intel_ring_emit(ring
, 0); /* low dword */
219 intel_ring_emit(ring
, 0); /* high dword */
220 intel_ring_emit(ring
, MI_NOOP
);
221 intel_ring_advance(ring
);
223 ret
= intel_ring_begin(ring
, 6);
227 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(5));
228 intel_ring_emit(ring
, PIPE_CONTROL_QW_WRITE
);
229 intel_ring_emit(ring
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
); /* address */
230 intel_ring_emit(ring
, 0);
231 intel_ring_emit(ring
, 0);
232 intel_ring_emit(ring
, MI_NOOP
);
233 intel_ring_advance(ring
);
239 gen6_render_ring_flush(struct intel_engine_cs
*ring
,
240 u32 invalidate_domains
, u32 flush_domains
)
243 u32 scratch_addr
= ring
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
246 /* Force SNB workarounds for PIPE_CONTROL flushes */
247 ret
= intel_emit_post_sync_nonzero_flush(ring
);
251 /* Just flush everything. Experiments have shown that reducing the
252 * number of bits based on the write domains has little performance
256 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
257 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
259 * Ensure that any following seqno writes only happen
260 * when the render cache is indeed flushed.
262 flags
|= PIPE_CONTROL_CS_STALL
;
264 if (invalidate_domains
) {
265 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
266 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
267 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
268 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
269 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
270 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
272 * TLB invalidate requires a post-sync write.
274 flags
|= PIPE_CONTROL_QW_WRITE
| PIPE_CONTROL_CS_STALL
;
277 ret
= intel_ring_begin(ring
, 4);
281 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4));
282 intel_ring_emit(ring
, flags
);
283 intel_ring_emit(ring
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
);
284 intel_ring_emit(ring
, 0);
285 intel_ring_advance(ring
);
291 gen7_render_ring_cs_stall_wa(struct intel_engine_cs
*ring
)
295 ret
= intel_ring_begin(ring
, 4);
299 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4));
300 intel_ring_emit(ring
, PIPE_CONTROL_CS_STALL
|
301 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
302 intel_ring_emit(ring
, 0);
303 intel_ring_emit(ring
, 0);
304 intel_ring_advance(ring
);
309 static int gen7_ring_fbc_flush(struct intel_engine_cs
*ring
, u32 value
)
313 if (!ring
->fbc_dirty
)
316 ret
= intel_ring_begin(ring
, 6);
319 /* WaFbcNukeOn3DBlt:ivb/hsw */
320 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
321 intel_ring_emit(ring
, MSG_FBC_REND_STATE
);
322 intel_ring_emit(ring
, value
);
323 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM(1) | MI_SRM_LRM_GLOBAL_GTT
);
324 intel_ring_emit(ring
, MSG_FBC_REND_STATE
);
325 intel_ring_emit(ring
, ring
->scratch
.gtt_offset
+ 256);
326 intel_ring_advance(ring
);
328 ring
->fbc_dirty
= false;
333 gen7_render_ring_flush(struct intel_engine_cs
*ring
,
334 u32 invalidate_domains
, u32 flush_domains
)
337 u32 scratch_addr
= ring
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
341 * Ensure that any following seqno writes only happen when the render
342 * cache is indeed flushed.
344 * Workaround: 4th PIPE_CONTROL command (except the ones with only
345 * read-cache invalidate bits set) must have the CS_STALL bit set. We
346 * don't try to be clever and just set it unconditionally.
348 flags
|= PIPE_CONTROL_CS_STALL
;
350 /* Just flush everything. Experiments have shown that reducing the
351 * number of bits based on the write domains has little performance
355 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
356 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
358 if (invalidate_domains
) {
359 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
360 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
361 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
362 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
363 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
364 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
366 * TLB invalidate requires a post-sync write.
368 flags
|= PIPE_CONTROL_QW_WRITE
;
369 flags
|= PIPE_CONTROL_GLOBAL_GTT_IVB
;
371 /* Workaround: we must issue a pipe_control with CS-stall bit
372 * set before a pipe_control command that has the state cache
373 * invalidate bit set. */
374 gen7_render_ring_cs_stall_wa(ring
);
377 ret
= intel_ring_begin(ring
, 4);
381 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4));
382 intel_ring_emit(ring
, flags
);
383 intel_ring_emit(ring
, scratch_addr
);
384 intel_ring_emit(ring
, 0);
385 intel_ring_advance(ring
);
387 if (!invalidate_domains
&& flush_domains
)
388 return gen7_ring_fbc_flush(ring
, FBC_REND_NUKE
);
394 gen8_emit_pipe_control(struct intel_engine_cs
*ring
,
395 u32 flags
, u32 scratch_addr
)
399 ret
= intel_ring_begin(ring
, 6);
403 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(6));
404 intel_ring_emit(ring
, flags
);
405 intel_ring_emit(ring
, scratch_addr
);
406 intel_ring_emit(ring
, 0);
407 intel_ring_emit(ring
, 0);
408 intel_ring_emit(ring
, 0);
409 intel_ring_advance(ring
);
415 gen8_render_ring_flush(struct intel_engine_cs
*ring
,
416 u32 invalidate_domains
, u32 flush_domains
)
419 u32 scratch_addr
= ring
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
422 flags
|= PIPE_CONTROL_CS_STALL
;
425 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
426 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
428 if (invalidate_domains
) {
429 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
430 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
431 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
432 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
433 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
434 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
435 flags
|= PIPE_CONTROL_QW_WRITE
;
436 flags
|= PIPE_CONTROL_GLOBAL_GTT_IVB
;
438 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
439 ret
= gen8_emit_pipe_control(ring
,
440 PIPE_CONTROL_CS_STALL
|
441 PIPE_CONTROL_STALL_AT_SCOREBOARD
,
447 ret
= gen8_emit_pipe_control(ring
, flags
, scratch_addr
);
451 if (!invalidate_domains
&& flush_domains
)
452 return gen7_ring_fbc_flush(ring
, FBC_REND_NUKE
);
457 static void ring_write_tail(struct intel_engine_cs
*ring
,
460 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
461 I915_WRITE_TAIL(ring
, value
);
464 u64
intel_ring_get_active_head(struct intel_engine_cs
*ring
)
466 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
469 if (INTEL_INFO(ring
->dev
)->gen
>= 8)
470 acthd
= I915_READ64_2x32(RING_ACTHD(ring
->mmio_base
),
471 RING_ACTHD_UDW(ring
->mmio_base
));
472 else if (INTEL_INFO(ring
->dev
)->gen
>= 4)
473 acthd
= I915_READ(RING_ACTHD(ring
->mmio_base
));
475 acthd
= I915_READ(ACTHD
);
480 static void ring_setup_phys_status_page(struct intel_engine_cs
*ring
)
482 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
485 addr
= dev_priv
->status_page_dmah
->busaddr
;
486 if (INTEL_INFO(ring
->dev
)->gen
>= 4)
487 addr
|= (dev_priv
->status_page_dmah
->busaddr
>> 28) & 0xf0;
488 I915_WRITE(HWS_PGA
, addr
);
491 static bool stop_ring(struct intel_engine_cs
*ring
)
493 struct drm_i915_private
*dev_priv
= to_i915(ring
->dev
);
495 if (!IS_GEN2(ring
->dev
)) {
496 I915_WRITE_MODE(ring
, _MASKED_BIT_ENABLE(STOP_RING
));
497 if (wait_for((I915_READ_MODE(ring
) & MODE_IDLE
) != 0, 1000)) {
498 DRM_ERROR("%s : timed out trying to stop ring\n", ring
->name
);
499 /* Sometimes we observe that the idle flag is not
500 * set even though the ring is empty. So double
501 * check before giving up.
503 if (I915_READ_HEAD(ring
) != I915_READ_TAIL(ring
))
508 I915_WRITE_CTL(ring
, 0);
509 I915_WRITE_HEAD(ring
, 0);
510 ring
->write_tail(ring
, 0);
512 if (!IS_GEN2(ring
->dev
)) {
513 (void)I915_READ_CTL(ring
);
514 I915_WRITE_MODE(ring
, _MASKED_BIT_DISABLE(STOP_RING
));
517 return (I915_READ_HEAD(ring
) & HEAD_ADDR
) == 0;
520 static int init_ring_common(struct intel_engine_cs
*ring
)
522 struct drm_device
*dev
= ring
->dev
;
523 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
524 struct intel_ringbuffer
*ringbuf
= ring
->buffer
;
525 struct drm_i915_gem_object
*obj
= ringbuf
->obj
;
528 gen6_gt_force_wake_get(dev_priv
, FORCEWAKE_ALL
);
530 if (!stop_ring(ring
)) {
531 /* G45 ring initialization often fails to reset head to zero */
532 DRM_DEBUG_KMS("%s head not reset to zero "
533 "ctl %08x head %08x tail %08x start %08x\n",
536 I915_READ_HEAD(ring
),
537 I915_READ_TAIL(ring
),
538 I915_READ_START(ring
));
540 if (!stop_ring(ring
)) {
541 DRM_ERROR("failed to set %s head to zero "
542 "ctl %08x head %08x tail %08x start %08x\n",
545 I915_READ_HEAD(ring
),
546 I915_READ_TAIL(ring
),
547 I915_READ_START(ring
));
553 if (I915_NEED_GFX_HWS(dev
))
554 intel_ring_setup_status_page(ring
);
556 ring_setup_phys_status_page(ring
);
558 /* Enforce ordering by reading HEAD register back */
559 I915_READ_HEAD(ring
);
561 /* Initialize the ring. This must happen _after_ we've cleared the ring
562 * registers with the above sequence (the readback of the HEAD registers
563 * also enforces ordering), otherwise the hw might lose the new ring
564 * register values. */
565 I915_WRITE_START(ring
, i915_gem_obj_ggtt_offset(obj
));
567 ((ringbuf
->size
- PAGE_SIZE
) & RING_NR_PAGES
)
570 /* If the head is still not zero, the ring is dead */
571 if (wait_for((I915_READ_CTL(ring
) & RING_VALID
) != 0 &&
572 I915_READ_START(ring
) == i915_gem_obj_ggtt_offset(obj
) &&
573 (I915_READ_HEAD(ring
) & HEAD_ADDR
) == 0, 50)) {
574 DRM_ERROR("%s initialization failed "
575 "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
577 I915_READ_CTL(ring
), I915_READ_CTL(ring
) & RING_VALID
,
578 I915_READ_HEAD(ring
), I915_READ_TAIL(ring
),
579 I915_READ_START(ring
), (unsigned long)i915_gem_obj_ggtt_offset(obj
));
584 if (!drm_core_check_feature(ring
->dev
, DRIVER_MODESET
))
585 i915_kernel_lost_context(ring
->dev
);
587 ringbuf
->head
= I915_READ_HEAD(ring
);
588 ringbuf
->tail
= I915_READ_TAIL(ring
) & TAIL_ADDR
;
589 ringbuf
->space
= intel_ring_space(ringbuf
);
590 ringbuf
->last_retired_head
= -1;
593 memset(&ring
->hangcheck
, 0, sizeof(ring
->hangcheck
));
596 gen6_gt_force_wake_put(dev_priv
, FORCEWAKE_ALL
);
602 intel_fini_pipe_control(struct intel_engine_cs
*ring
)
604 struct drm_device
*dev
= ring
->dev
;
606 if (ring
->scratch
.obj
== NULL
)
609 if (INTEL_INFO(dev
)->gen
>= 5) {
610 kunmap(sg_page(ring
->scratch
.obj
->pages
->sgl
));
611 i915_gem_object_ggtt_unpin(ring
->scratch
.obj
);
614 drm_gem_object_unreference(&ring
->scratch
.obj
->base
);
615 ring
->scratch
.obj
= NULL
;
619 intel_init_pipe_control(struct intel_engine_cs
*ring
)
623 if (ring
->scratch
.obj
)
626 ring
->scratch
.obj
= i915_gem_alloc_object(ring
->dev
, 4096);
627 if (ring
->scratch
.obj
== NULL
) {
628 DRM_ERROR("Failed to allocate seqno page\n");
633 ret
= i915_gem_object_set_cache_level(ring
->scratch
.obj
, I915_CACHE_LLC
);
637 ret
= i915_gem_obj_ggtt_pin(ring
->scratch
.obj
, 4096, 0);
641 ring
->scratch
.gtt_offset
= i915_gem_obj_ggtt_offset(ring
->scratch
.obj
);
642 ring
->scratch
.cpu_page
= kmap(sg_page(ring
->scratch
.obj
->pages
->sgl
));
643 if (ring
->scratch
.cpu_page
== NULL
) {
648 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
649 ring
->name
, ring
->scratch
.gtt_offset
);
653 i915_gem_object_ggtt_unpin(ring
->scratch
.obj
);
655 drm_gem_object_unreference(&ring
->scratch
.obj
->base
);
660 static inline void intel_ring_emit_wa(struct intel_engine_cs
*ring
,
663 struct drm_device
*dev
= ring
->dev
;
664 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
666 if (dev_priv
->num_wa_regs
> I915_MAX_WA_REGS
)
669 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
670 intel_ring_emit(ring
, addr
);
671 intel_ring_emit(ring
, value
);
673 dev_priv
->intel_wa_regs
[dev_priv
->num_wa_regs
].addr
= addr
;
674 dev_priv
->intel_wa_regs
[dev_priv
->num_wa_regs
].mask
= (value
) & 0xFFFF;
675 /* value is updated with the status of remaining bits of this
676 * register when it is read from debugfs file
678 dev_priv
->intel_wa_regs
[dev_priv
->num_wa_regs
].value
= value
;
679 dev_priv
->num_wa_regs
++;
684 static int bdw_init_workarounds(struct intel_engine_cs
*ring
)
687 struct drm_device
*dev
= ring
->dev
;
688 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
691 * workarounds applied in this fn are part of register state context,
692 * they need to be re-initialized followed by gpu reset, suspend/resume,
695 dev_priv
->num_wa_regs
= 0;
696 memset(dev_priv
->intel_wa_regs
, 0, sizeof(dev_priv
->intel_wa_regs
));
699 * update the number of dwords required based on the
700 * actual number of workarounds applied
702 ret
= intel_ring_begin(ring
, 24);
706 /* WaDisablePartialInstShootdown:bdw */
707 /* WaDisableThreadStallDopClockGating:bdw */
708 /* FIXME: Unclear whether we really need this on production bdw. */
709 intel_ring_emit_wa(ring
, GEN8_ROW_CHICKEN
,
710 _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE
711 | STALL_DOP_GATING_DISABLE
));
713 /* WaDisableDopClockGating:bdw May not be needed for production */
714 intel_ring_emit_wa(ring
, GEN7_ROW_CHICKEN2
,
715 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
718 * This GEN8_CENTROID_PIXEL_OPT_DIS W/A is only needed for
719 * pre-production hardware
721 intel_ring_emit_wa(ring
, HALF_SLICE_CHICKEN3
,
722 _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS
723 | GEN8_SAMPLER_POWER_BYPASS_DIS
));
725 intel_ring_emit_wa(ring
, GEN7_HALF_SLICE_CHICKEN1
,
726 _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE
));
728 intel_ring_emit_wa(ring
, COMMON_SLICE_CHICKEN2
,
729 _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE
));
731 /* Use Force Non-Coherent whenever executing a 3D context. This is a
732 * workaround for for a possible hang in the unlikely event a TLB
733 * invalidation occurs during a PSD flush.
735 intel_ring_emit_wa(ring
, HDC_CHICKEN0
,
736 _MASKED_BIT_ENABLE(HDC_FORCE_NON_COHERENT
));
738 /* Wa4x4STCOptimizationDisable:bdw */
739 intel_ring_emit_wa(ring
, CACHE_MODE_1
,
740 _MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE
));
743 * BSpec recommends 8x4 when MSAA is used,
744 * however in practice 16x4 seems fastest.
746 * Note that PS/WM thread counts depend on the WIZ hashing
747 * disable bit, which we don't touch here, but it's good
748 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
750 intel_ring_emit_wa(ring
, GEN7_GT_MODE
,
751 GEN6_WIZ_HASHING_MASK
| GEN6_WIZ_HASHING_16x4
);
753 intel_ring_advance(ring
);
755 DRM_DEBUG_DRIVER("Number of Workarounds applied: %d\n",
756 dev_priv
->num_wa_regs
);
761 static int chv_init_workarounds(struct intel_engine_cs
*ring
)
764 struct drm_device
*dev
= ring
->dev
;
765 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
768 * workarounds applied in this fn are part of register state context,
769 * they need to be re-initialized followed by gpu reset, suspend/resume,
772 dev_priv
->num_wa_regs
= 0;
773 memset(dev_priv
->intel_wa_regs
, 0, sizeof(dev_priv
->intel_wa_regs
));
775 ret
= intel_ring_begin(ring
, 12);
779 /* WaDisablePartialInstShootdown:chv */
780 intel_ring_emit_wa(ring
, GEN8_ROW_CHICKEN
,
781 _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE
));
783 /* WaDisableThreadStallDopClockGating:chv */
784 intel_ring_emit_wa(ring
, GEN8_ROW_CHICKEN
,
785 _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE
));
787 /* WaDisableDopClockGating:chv (pre-production hw) */
788 intel_ring_emit_wa(ring
, GEN7_ROW_CHICKEN2
,
789 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
791 /* WaDisableSamplerPowerBypass:chv (pre-production hw) */
792 intel_ring_emit_wa(ring
, HALF_SLICE_CHICKEN3
,
793 _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS
));
795 intel_ring_advance(ring
);
800 static int init_render_ring(struct intel_engine_cs
*ring
)
802 struct drm_device
*dev
= ring
->dev
;
803 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
804 int ret
= init_ring_common(ring
);
808 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
809 if (INTEL_INFO(dev
)->gen
>= 4 && INTEL_INFO(dev
)->gen
< 7)
810 I915_WRITE(MI_MODE
, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH
));
812 /* We need to disable the AsyncFlip performance optimisations in order
813 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
814 * programmed to '1' on all products.
816 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
818 if (INTEL_INFO(dev
)->gen
>= 6)
819 I915_WRITE(MI_MODE
, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE
));
821 /* Required for the hardware to program scanline values for waiting */
822 /* WaEnableFlushTlbInvalidationMode:snb */
823 if (INTEL_INFO(dev
)->gen
== 6)
825 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT
));
827 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
829 I915_WRITE(GFX_MODE_GEN7
,
830 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT
) |
831 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE
));
833 if (INTEL_INFO(dev
)->gen
>= 5) {
834 ret
= intel_init_pipe_control(ring
);
840 /* From the Sandybridge PRM, volume 1 part 3, page 24:
841 * "If this bit is set, STCunit will have LRA as replacement
842 * policy. [...] This bit must be reset. LRA replacement
843 * policy is not supported."
845 I915_WRITE(CACHE_MODE_0
,
846 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB
));
849 if (INTEL_INFO(dev
)->gen
>= 6)
850 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING
));
853 I915_WRITE_IMR(ring
, ~GT_PARITY_ERROR(dev
));
858 static void render_ring_cleanup(struct intel_engine_cs
*ring
)
860 struct drm_device
*dev
= ring
->dev
;
861 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
863 if (dev_priv
->semaphore_obj
) {
864 i915_gem_object_ggtt_unpin(dev_priv
->semaphore_obj
);
865 drm_gem_object_unreference(&dev_priv
->semaphore_obj
->base
);
866 dev_priv
->semaphore_obj
= NULL
;
869 intel_fini_pipe_control(ring
);
872 static int gen8_rcs_signal(struct intel_engine_cs
*signaller
,
873 unsigned int num_dwords
)
875 #define MBOX_UPDATE_DWORDS 8
876 struct drm_device
*dev
= signaller
->dev
;
877 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
878 struct intel_engine_cs
*waiter
;
879 int i
, ret
, num_rings
;
881 num_rings
= hweight32(INTEL_INFO(dev
)->ring_mask
);
882 num_dwords
+= (num_rings
-1) * MBOX_UPDATE_DWORDS
;
883 #undef MBOX_UPDATE_DWORDS
885 ret
= intel_ring_begin(signaller
, num_dwords
);
889 for_each_ring(waiter
, dev_priv
, i
) {
890 u64 gtt_offset
= signaller
->semaphore
.signal_ggtt
[i
];
891 if (gtt_offset
== MI_SEMAPHORE_SYNC_INVALID
)
894 intel_ring_emit(signaller
, GFX_OP_PIPE_CONTROL(6));
895 intel_ring_emit(signaller
, PIPE_CONTROL_GLOBAL_GTT_IVB
|
896 PIPE_CONTROL_QW_WRITE
|
897 PIPE_CONTROL_FLUSH_ENABLE
);
898 intel_ring_emit(signaller
, lower_32_bits(gtt_offset
));
899 intel_ring_emit(signaller
, upper_32_bits(gtt_offset
));
900 intel_ring_emit(signaller
, signaller
->outstanding_lazy_seqno
);
901 intel_ring_emit(signaller
, 0);
902 intel_ring_emit(signaller
, MI_SEMAPHORE_SIGNAL
|
903 MI_SEMAPHORE_TARGET(waiter
->id
));
904 intel_ring_emit(signaller
, 0);
910 static int gen8_xcs_signal(struct intel_engine_cs
*signaller
,
911 unsigned int num_dwords
)
913 #define MBOX_UPDATE_DWORDS 6
914 struct drm_device
*dev
= signaller
->dev
;
915 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
916 struct intel_engine_cs
*waiter
;
917 int i
, ret
, num_rings
;
919 num_rings
= hweight32(INTEL_INFO(dev
)->ring_mask
);
920 num_dwords
+= (num_rings
-1) * MBOX_UPDATE_DWORDS
;
921 #undef MBOX_UPDATE_DWORDS
923 ret
= intel_ring_begin(signaller
, num_dwords
);
927 for_each_ring(waiter
, dev_priv
, i
) {
928 u64 gtt_offset
= signaller
->semaphore
.signal_ggtt
[i
];
929 if (gtt_offset
== MI_SEMAPHORE_SYNC_INVALID
)
932 intel_ring_emit(signaller
, (MI_FLUSH_DW
+ 1) |
933 MI_FLUSH_DW_OP_STOREDW
);
934 intel_ring_emit(signaller
, lower_32_bits(gtt_offset
) |
935 MI_FLUSH_DW_USE_GTT
);
936 intel_ring_emit(signaller
, upper_32_bits(gtt_offset
));
937 intel_ring_emit(signaller
, signaller
->outstanding_lazy_seqno
);
938 intel_ring_emit(signaller
, MI_SEMAPHORE_SIGNAL
|
939 MI_SEMAPHORE_TARGET(waiter
->id
));
940 intel_ring_emit(signaller
, 0);
946 static int gen6_signal(struct intel_engine_cs
*signaller
,
947 unsigned int num_dwords
)
949 struct drm_device
*dev
= signaller
->dev
;
950 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
951 struct intel_engine_cs
*useless
;
952 int i
, ret
, num_rings
;
954 #define MBOX_UPDATE_DWORDS 3
955 num_rings
= hweight32(INTEL_INFO(dev
)->ring_mask
);
956 num_dwords
+= round_up((num_rings
-1) * MBOX_UPDATE_DWORDS
, 2);
957 #undef MBOX_UPDATE_DWORDS
959 ret
= intel_ring_begin(signaller
, num_dwords
);
963 for_each_ring(useless
, dev_priv
, i
) {
964 u32 mbox_reg
= signaller
->semaphore
.mbox
.signal
[i
];
965 if (mbox_reg
!= GEN6_NOSYNC
) {
966 intel_ring_emit(signaller
, MI_LOAD_REGISTER_IMM(1));
967 intel_ring_emit(signaller
, mbox_reg
);
968 intel_ring_emit(signaller
, signaller
->outstanding_lazy_seqno
);
972 /* If num_dwords was rounded, make sure the tail pointer is correct */
973 if (num_rings
% 2 == 0)
974 intel_ring_emit(signaller
, MI_NOOP
);
980 * gen6_add_request - Update the semaphore mailbox registers
982 * @ring - ring that is adding a request
983 * @seqno - return seqno stuck into the ring
985 * Update the mailbox registers in the *other* rings with the current seqno.
986 * This acts like a signal in the canonical semaphore.
989 gen6_add_request(struct intel_engine_cs
*ring
)
993 if (ring
->semaphore
.signal
)
994 ret
= ring
->semaphore
.signal(ring
, 4);
996 ret
= intel_ring_begin(ring
, 4);
1001 intel_ring_emit(ring
, MI_STORE_DWORD_INDEX
);
1002 intel_ring_emit(ring
, I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
1003 intel_ring_emit(ring
, ring
->outstanding_lazy_seqno
);
1004 intel_ring_emit(ring
, MI_USER_INTERRUPT
);
1005 __intel_ring_advance(ring
);
1010 static inline bool i915_gem_has_seqno_wrapped(struct drm_device
*dev
,
1013 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1014 return dev_priv
->last_seqno
< seqno
;
1018 * intel_ring_sync - sync the waiter to the signaller on seqno
1020 * @waiter - ring that is waiting
1021 * @signaller - ring which has, or will signal
1022 * @seqno - seqno which the waiter will block on
1026 gen8_ring_sync(struct intel_engine_cs
*waiter
,
1027 struct intel_engine_cs
*signaller
,
1030 struct drm_i915_private
*dev_priv
= waiter
->dev
->dev_private
;
1033 ret
= intel_ring_begin(waiter
, 4);
1037 intel_ring_emit(waiter
, MI_SEMAPHORE_WAIT
|
1038 MI_SEMAPHORE_GLOBAL_GTT
|
1040 MI_SEMAPHORE_SAD_GTE_SDD
);
1041 intel_ring_emit(waiter
, seqno
);
1042 intel_ring_emit(waiter
,
1043 lower_32_bits(GEN8_WAIT_OFFSET(waiter
, signaller
->id
)));
1044 intel_ring_emit(waiter
,
1045 upper_32_bits(GEN8_WAIT_OFFSET(waiter
, signaller
->id
)));
1046 intel_ring_advance(waiter
);
1051 gen6_ring_sync(struct intel_engine_cs
*waiter
,
1052 struct intel_engine_cs
*signaller
,
1055 u32 dw1
= MI_SEMAPHORE_MBOX
|
1056 MI_SEMAPHORE_COMPARE
|
1057 MI_SEMAPHORE_REGISTER
;
1058 u32 wait_mbox
= signaller
->semaphore
.mbox
.wait
[waiter
->id
];
1061 /* Throughout all of the GEM code, seqno passed implies our current
1062 * seqno is >= the last seqno executed. However for hardware the
1063 * comparison is strictly greater than.
1067 WARN_ON(wait_mbox
== MI_SEMAPHORE_SYNC_INVALID
);
1069 ret
= intel_ring_begin(waiter
, 4);
1073 /* If seqno wrap happened, omit the wait with no-ops */
1074 if (likely(!i915_gem_has_seqno_wrapped(waiter
->dev
, seqno
))) {
1075 intel_ring_emit(waiter
, dw1
| wait_mbox
);
1076 intel_ring_emit(waiter
, seqno
);
1077 intel_ring_emit(waiter
, 0);
1078 intel_ring_emit(waiter
, MI_NOOP
);
1080 intel_ring_emit(waiter
, MI_NOOP
);
1081 intel_ring_emit(waiter
, MI_NOOP
);
1082 intel_ring_emit(waiter
, MI_NOOP
);
1083 intel_ring_emit(waiter
, MI_NOOP
);
1085 intel_ring_advance(waiter
);
1090 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
1092 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
1093 PIPE_CONTROL_DEPTH_STALL); \
1094 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
1095 intel_ring_emit(ring__, 0); \
1096 intel_ring_emit(ring__, 0); \
1100 pc_render_add_request(struct intel_engine_cs
*ring
)
1102 u32 scratch_addr
= ring
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
1105 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1106 * incoherent with writes to memory, i.e. completely fubar,
1107 * so we need to use PIPE_NOTIFY instead.
1109 * However, we also need to workaround the qword write
1110 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1111 * memory before requesting an interrupt.
1113 ret
= intel_ring_begin(ring
, 32);
1117 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE
|
1118 PIPE_CONTROL_WRITE_FLUSH
|
1119 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
);
1120 intel_ring_emit(ring
, ring
->scratch
.gtt_offset
| PIPE_CONTROL_GLOBAL_GTT
);
1121 intel_ring_emit(ring
, ring
->outstanding_lazy_seqno
);
1122 intel_ring_emit(ring
, 0);
1123 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
1124 scratch_addr
+= 2 * CACHELINE_BYTES
; /* write to separate cachelines */
1125 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
1126 scratch_addr
+= 2 * CACHELINE_BYTES
;
1127 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
1128 scratch_addr
+= 2 * CACHELINE_BYTES
;
1129 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
1130 scratch_addr
+= 2 * CACHELINE_BYTES
;
1131 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
1132 scratch_addr
+= 2 * CACHELINE_BYTES
;
1133 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
1135 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE
|
1136 PIPE_CONTROL_WRITE_FLUSH
|
1137 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
1138 PIPE_CONTROL_NOTIFY
);
1139 intel_ring_emit(ring
, ring
->scratch
.gtt_offset
| PIPE_CONTROL_GLOBAL_GTT
);
1140 intel_ring_emit(ring
, ring
->outstanding_lazy_seqno
);
1141 intel_ring_emit(ring
, 0);
1142 __intel_ring_advance(ring
);
1148 gen6_ring_get_seqno(struct intel_engine_cs
*ring
, bool lazy_coherency
)
1150 /* Workaround to force correct ordering between irq and seqno writes on
1151 * ivb (and maybe also on snb) by reading from a CS register (like
1152 * ACTHD) before reading the status page. */
1153 if (!lazy_coherency
) {
1154 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1155 POSTING_READ(RING_ACTHD(ring
->mmio_base
));
1158 return intel_read_status_page(ring
, I915_GEM_HWS_INDEX
);
1162 ring_get_seqno(struct intel_engine_cs
*ring
, bool lazy_coherency
)
1164 return intel_read_status_page(ring
, I915_GEM_HWS_INDEX
);
1168 ring_set_seqno(struct intel_engine_cs
*ring
, u32 seqno
)
1170 intel_write_status_page(ring
, I915_GEM_HWS_INDEX
, seqno
);
1174 pc_render_get_seqno(struct intel_engine_cs
*ring
, bool lazy_coherency
)
1176 return ring
->scratch
.cpu_page
[0];
1180 pc_render_set_seqno(struct intel_engine_cs
*ring
, u32 seqno
)
1182 ring
->scratch
.cpu_page
[0] = seqno
;
1186 gen5_ring_get_irq(struct intel_engine_cs
*ring
)
1188 struct drm_device
*dev
= ring
->dev
;
1189 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1190 unsigned long flags
;
1192 if (!dev
->irq_enabled
)
1195 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1196 if (ring
->irq_refcount
++ == 0)
1197 gen5_enable_gt_irq(dev_priv
, ring
->irq_enable_mask
);
1198 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1204 gen5_ring_put_irq(struct intel_engine_cs
*ring
)
1206 struct drm_device
*dev
= ring
->dev
;
1207 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1208 unsigned long flags
;
1210 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1211 if (--ring
->irq_refcount
== 0)
1212 gen5_disable_gt_irq(dev_priv
, ring
->irq_enable_mask
);
1213 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1217 i9xx_ring_get_irq(struct intel_engine_cs
*ring
)
1219 struct drm_device
*dev
= ring
->dev
;
1220 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1221 unsigned long flags
;
1223 if (!dev
->irq_enabled
)
1226 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1227 if (ring
->irq_refcount
++ == 0) {
1228 dev_priv
->irq_mask
&= ~ring
->irq_enable_mask
;
1229 I915_WRITE(IMR
, dev_priv
->irq_mask
);
1232 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1238 i9xx_ring_put_irq(struct intel_engine_cs
*ring
)
1240 struct drm_device
*dev
= ring
->dev
;
1241 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1242 unsigned long flags
;
1244 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1245 if (--ring
->irq_refcount
== 0) {
1246 dev_priv
->irq_mask
|= ring
->irq_enable_mask
;
1247 I915_WRITE(IMR
, dev_priv
->irq_mask
);
1250 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1254 i8xx_ring_get_irq(struct intel_engine_cs
*ring
)
1256 struct drm_device
*dev
= ring
->dev
;
1257 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1258 unsigned long flags
;
1260 if (!dev
->irq_enabled
)
1263 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1264 if (ring
->irq_refcount
++ == 0) {
1265 dev_priv
->irq_mask
&= ~ring
->irq_enable_mask
;
1266 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
1267 POSTING_READ16(IMR
);
1269 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1275 i8xx_ring_put_irq(struct intel_engine_cs
*ring
)
1277 struct drm_device
*dev
= ring
->dev
;
1278 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1279 unsigned long flags
;
1281 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1282 if (--ring
->irq_refcount
== 0) {
1283 dev_priv
->irq_mask
|= ring
->irq_enable_mask
;
1284 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
1285 POSTING_READ16(IMR
);
1287 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1290 void intel_ring_setup_status_page(struct intel_engine_cs
*ring
)
1292 struct drm_device
*dev
= ring
->dev
;
1293 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1296 /* The ring status page addresses are no longer next to the rest of
1297 * the ring registers as of gen7.
1302 mmio
= RENDER_HWS_PGA_GEN7
;
1305 mmio
= BLT_HWS_PGA_GEN7
;
1308 * VCS2 actually doesn't exist on Gen7. Only shut up
1309 * gcc switch check warning
1313 mmio
= BSD_HWS_PGA_GEN7
;
1316 mmio
= VEBOX_HWS_PGA_GEN7
;
1319 } else if (IS_GEN6(ring
->dev
)) {
1320 mmio
= RING_HWS_PGA_GEN6(ring
->mmio_base
);
1322 /* XXX: gen8 returns to sanity */
1323 mmio
= RING_HWS_PGA(ring
->mmio_base
);
1326 I915_WRITE(mmio
, (u32
)ring
->status_page
.gfx_addr
);
1330 * Flush the TLB for this page
1332 * FIXME: These two bits have disappeared on gen8, so a question
1333 * arises: do we still need this and if so how should we go about
1334 * invalidating the TLB?
1336 if (INTEL_INFO(dev
)->gen
>= 6 && INTEL_INFO(dev
)->gen
< 8) {
1337 u32 reg
= RING_INSTPM(ring
->mmio_base
);
1339 /* ring should be idle before issuing a sync flush*/
1340 WARN_ON((I915_READ_MODE(ring
) & MODE_IDLE
) == 0);
1343 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE
|
1344 INSTPM_SYNC_FLUSH
));
1345 if (wait_for((I915_READ(reg
) & INSTPM_SYNC_FLUSH
) == 0,
1347 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
1353 bsd_ring_flush(struct intel_engine_cs
*ring
,
1354 u32 invalidate_domains
,
1359 ret
= intel_ring_begin(ring
, 2);
1363 intel_ring_emit(ring
, MI_FLUSH
);
1364 intel_ring_emit(ring
, MI_NOOP
);
1365 intel_ring_advance(ring
);
1370 i9xx_add_request(struct intel_engine_cs
*ring
)
1374 ret
= intel_ring_begin(ring
, 4);
1378 intel_ring_emit(ring
, MI_STORE_DWORD_INDEX
);
1379 intel_ring_emit(ring
, I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
1380 intel_ring_emit(ring
, ring
->outstanding_lazy_seqno
);
1381 intel_ring_emit(ring
, MI_USER_INTERRUPT
);
1382 __intel_ring_advance(ring
);
1388 gen6_ring_get_irq(struct intel_engine_cs
*ring
)
1390 struct drm_device
*dev
= ring
->dev
;
1391 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1392 unsigned long flags
;
1394 if (!dev
->irq_enabled
)
1397 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1398 if (ring
->irq_refcount
++ == 0) {
1399 if (HAS_L3_DPF(dev
) && ring
->id
== RCS
)
1400 I915_WRITE_IMR(ring
,
1401 ~(ring
->irq_enable_mask
|
1402 GT_PARITY_ERROR(dev
)));
1404 I915_WRITE_IMR(ring
, ~ring
->irq_enable_mask
);
1405 gen5_enable_gt_irq(dev_priv
, ring
->irq_enable_mask
);
1407 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1413 gen6_ring_put_irq(struct intel_engine_cs
*ring
)
1415 struct drm_device
*dev
= ring
->dev
;
1416 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1417 unsigned long flags
;
1419 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1420 if (--ring
->irq_refcount
== 0) {
1421 if (HAS_L3_DPF(dev
) && ring
->id
== RCS
)
1422 I915_WRITE_IMR(ring
, ~GT_PARITY_ERROR(dev
));
1424 I915_WRITE_IMR(ring
, ~0);
1425 gen5_disable_gt_irq(dev_priv
, ring
->irq_enable_mask
);
1427 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1431 hsw_vebox_get_irq(struct intel_engine_cs
*ring
)
1433 struct drm_device
*dev
= ring
->dev
;
1434 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1435 unsigned long flags
;
1437 if (!dev
->irq_enabled
)
1440 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1441 if (ring
->irq_refcount
++ == 0) {
1442 I915_WRITE_IMR(ring
, ~ring
->irq_enable_mask
);
1443 gen6_enable_pm_irq(dev_priv
, ring
->irq_enable_mask
);
1445 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1451 hsw_vebox_put_irq(struct intel_engine_cs
*ring
)
1453 struct drm_device
*dev
= ring
->dev
;
1454 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1455 unsigned long flags
;
1457 if (!dev
->irq_enabled
)
1460 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1461 if (--ring
->irq_refcount
== 0) {
1462 I915_WRITE_IMR(ring
, ~0);
1463 gen6_disable_pm_irq(dev_priv
, ring
->irq_enable_mask
);
1465 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1469 gen8_ring_get_irq(struct intel_engine_cs
*ring
)
1471 struct drm_device
*dev
= ring
->dev
;
1472 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1473 unsigned long flags
;
1475 if (!dev
->irq_enabled
)
1478 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1479 if (ring
->irq_refcount
++ == 0) {
1480 if (HAS_L3_DPF(dev
) && ring
->id
== RCS
) {
1481 I915_WRITE_IMR(ring
,
1482 ~(ring
->irq_enable_mask
|
1483 GT_RENDER_L3_PARITY_ERROR_INTERRUPT
));
1485 I915_WRITE_IMR(ring
, ~ring
->irq_enable_mask
);
1487 POSTING_READ(RING_IMR(ring
->mmio_base
));
1489 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1495 gen8_ring_put_irq(struct intel_engine_cs
*ring
)
1497 struct drm_device
*dev
= ring
->dev
;
1498 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1499 unsigned long flags
;
1501 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1502 if (--ring
->irq_refcount
== 0) {
1503 if (HAS_L3_DPF(dev
) && ring
->id
== RCS
) {
1504 I915_WRITE_IMR(ring
,
1505 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT
);
1507 I915_WRITE_IMR(ring
, ~0);
1509 POSTING_READ(RING_IMR(ring
->mmio_base
));
1511 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1515 i965_dispatch_execbuffer(struct intel_engine_cs
*ring
,
1516 u64 offset
, u32 length
,
1521 ret
= intel_ring_begin(ring
, 2);
1525 intel_ring_emit(ring
,
1526 MI_BATCH_BUFFER_START
|
1528 (flags
& I915_DISPATCH_SECURE
? 0 : MI_BATCH_NON_SECURE_I965
));
1529 intel_ring_emit(ring
, offset
);
1530 intel_ring_advance(ring
);
1535 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1536 #define I830_BATCH_LIMIT (256*1024)
1538 i830_dispatch_execbuffer(struct intel_engine_cs
*ring
,
1539 u64 offset
, u32 len
,
1544 if (flags
& I915_DISPATCH_PINNED
) {
1545 ret
= intel_ring_begin(ring
, 4);
1549 intel_ring_emit(ring
, MI_BATCH_BUFFER
);
1550 intel_ring_emit(ring
, offset
| (flags
& I915_DISPATCH_SECURE
? 0 : MI_BATCH_NON_SECURE
));
1551 intel_ring_emit(ring
, offset
+ len
- 8);
1552 intel_ring_emit(ring
, MI_NOOP
);
1553 intel_ring_advance(ring
);
1555 u32 cs_offset
= ring
->scratch
.gtt_offset
;
1557 if (len
> I830_BATCH_LIMIT
)
1560 ret
= intel_ring_begin(ring
, 9+3);
1563 /* Blit the batch (which has now all relocs applied) to the stable batch
1564 * scratch bo area (so that the CS never stumbles over its tlb
1565 * invalidation bug) ... */
1566 intel_ring_emit(ring
, XY_SRC_COPY_BLT_CMD
|
1567 XY_SRC_COPY_BLT_WRITE_ALPHA
|
1568 XY_SRC_COPY_BLT_WRITE_RGB
);
1569 intel_ring_emit(ring
, BLT_DEPTH_32
| BLT_ROP_GXCOPY
| 4096);
1570 intel_ring_emit(ring
, 0);
1571 intel_ring_emit(ring
, (DIV_ROUND_UP(len
, 4096) << 16) | 1024);
1572 intel_ring_emit(ring
, cs_offset
);
1573 intel_ring_emit(ring
, 0);
1574 intel_ring_emit(ring
, 4096);
1575 intel_ring_emit(ring
, offset
);
1576 intel_ring_emit(ring
, MI_FLUSH
);
1578 /* ... and execute it. */
1579 intel_ring_emit(ring
, MI_BATCH_BUFFER
);
1580 intel_ring_emit(ring
, cs_offset
| (flags
& I915_DISPATCH_SECURE
? 0 : MI_BATCH_NON_SECURE
));
1581 intel_ring_emit(ring
, cs_offset
+ len
- 8);
1582 intel_ring_advance(ring
);
1589 i915_dispatch_execbuffer(struct intel_engine_cs
*ring
,
1590 u64 offset
, u32 len
,
1595 ret
= intel_ring_begin(ring
, 2);
1599 intel_ring_emit(ring
, MI_BATCH_BUFFER_START
| MI_BATCH_GTT
);
1600 intel_ring_emit(ring
, offset
| (flags
& I915_DISPATCH_SECURE
? 0 : MI_BATCH_NON_SECURE
));
1601 intel_ring_advance(ring
);
1606 static void cleanup_status_page(struct intel_engine_cs
*ring
)
1608 struct drm_i915_gem_object
*obj
;
1610 obj
= ring
->status_page
.obj
;
1614 kunmap(sg_page(obj
->pages
->sgl
));
1615 i915_gem_object_ggtt_unpin(obj
);
1616 drm_gem_object_unreference(&obj
->base
);
1617 ring
->status_page
.obj
= NULL
;
1620 static int init_status_page(struct intel_engine_cs
*ring
)
1622 struct drm_i915_gem_object
*obj
;
1624 if ((obj
= ring
->status_page
.obj
) == NULL
) {
1628 obj
= i915_gem_alloc_object(ring
->dev
, 4096);
1630 DRM_ERROR("Failed to allocate status page\n");
1634 ret
= i915_gem_object_set_cache_level(obj
, I915_CACHE_LLC
);
1639 if (!HAS_LLC(ring
->dev
))
1640 /* On g33, we cannot place HWS above 256MiB, so
1641 * restrict its pinning to the low mappable arena.
1642 * Though this restriction is not documented for
1643 * gen4, gen5, or byt, they also behave similarly
1644 * and hang if the HWS is placed at the top of the
1645 * GTT. To generalise, it appears that all !llc
1646 * platforms have issues with us placing the HWS
1647 * above the mappable region (even though we never
1650 flags
|= PIN_MAPPABLE
;
1651 ret
= i915_gem_obj_ggtt_pin(obj
, 4096, flags
);
1654 drm_gem_object_unreference(&obj
->base
);
1658 ring
->status_page
.obj
= obj
;
1661 ring
->status_page
.gfx_addr
= i915_gem_obj_ggtt_offset(obj
);
1662 ring
->status_page
.page_addr
= kmap(sg_page(obj
->pages
->sgl
));
1663 memset(ring
->status_page
.page_addr
, 0, PAGE_SIZE
);
1665 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1666 ring
->name
, ring
->status_page
.gfx_addr
);
1671 static int init_phys_status_page(struct intel_engine_cs
*ring
)
1673 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1675 if (!dev_priv
->status_page_dmah
) {
1676 dev_priv
->status_page_dmah
=
1677 drm_pci_alloc(ring
->dev
, PAGE_SIZE
, PAGE_SIZE
);
1678 if (!dev_priv
->status_page_dmah
)
1682 ring
->status_page
.page_addr
= dev_priv
->status_page_dmah
->vaddr
;
1683 memset(ring
->status_page
.page_addr
, 0, PAGE_SIZE
);
1688 void intel_destroy_ringbuffer_obj(struct intel_ringbuffer
*ringbuf
)
1693 iounmap(ringbuf
->virtual_start
);
1694 i915_gem_object_ggtt_unpin(ringbuf
->obj
);
1695 drm_gem_object_unreference(&ringbuf
->obj
->base
);
1696 ringbuf
->obj
= NULL
;
1699 int intel_alloc_ringbuffer_obj(struct drm_device
*dev
,
1700 struct intel_ringbuffer
*ringbuf
)
1702 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1703 struct drm_i915_gem_object
*obj
;
1711 obj
= i915_gem_object_create_stolen(dev
, ringbuf
->size
);
1713 obj
= i915_gem_alloc_object(dev
, ringbuf
->size
);
1717 /* mark ring buffers as read-only from GPU side by default */
1720 ret
= i915_gem_obj_ggtt_pin(obj
, PAGE_SIZE
, PIN_MAPPABLE
);
1724 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
1728 ringbuf
->virtual_start
=
1729 ioremap_wc(dev_priv
->gtt
.mappable_base
+ i915_gem_obj_ggtt_offset(obj
),
1731 if (ringbuf
->virtual_start
== NULL
) {
1740 i915_gem_object_ggtt_unpin(obj
);
1742 drm_gem_object_unreference(&obj
->base
);
1746 static int intel_init_ring_buffer(struct drm_device
*dev
,
1747 struct intel_engine_cs
*ring
)
1749 struct intel_ringbuffer
*ringbuf
= ring
->buffer
;
1752 if (ringbuf
== NULL
) {
1753 ringbuf
= kzalloc(sizeof(*ringbuf
), GFP_KERNEL
);
1756 ring
->buffer
= ringbuf
;
1760 INIT_LIST_HEAD(&ring
->active_list
);
1761 INIT_LIST_HEAD(&ring
->request_list
);
1762 INIT_LIST_HEAD(&ring
->execlist_queue
);
1763 ringbuf
->size
= 32 * PAGE_SIZE
;
1764 ringbuf
->ring
= ring
;
1765 memset(ring
->semaphore
.sync_seqno
, 0, sizeof(ring
->semaphore
.sync_seqno
));
1767 init_waitqueue_head(&ring
->irq_queue
);
1769 if (I915_NEED_GFX_HWS(dev
)) {
1770 ret
= init_status_page(ring
);
1774 BUG_ON(ring
->id
!= RCS
);
1775 ret
= init_phys_status_page(ring
);
1780 ret
= intel_alloc_ringbuffer_obj(dev
, ringbuf
);
1782 DRM_ERROR("Failed to allocate ringbuffer %s: %d\n", ring
->name
, ret
);
1786 /* Workaround an erratum on the i830 which causes a hang if
1787 * the TAIL pointer points to within the last 2 cachelines
1790 ringbuf
->effective_size
= ringbuf
->size
;
1791 if (IS_I830(dev
) || IS_845G(dev
))
1792 ringbuf
->effective_size
-= 2 * CACHELINE_BYTES
;
1794 ret
= i915_cmd_parser_init_ring(ring
);
1798 ret
= ring
->init(ring
);
1806 ring
->buffer
= NULL
;
1810 void intel_cleanup_ring_buffer(struct intel_engine_cs
*ring
)
1812 struct drm_i915_private
*dev_priv
= to_i915(ring
->dev
);
1813 struct intel_ringbuffer
*ringbuf
= ring
->buffer
;
1815 if (!intel_ring_initialized(ring
))
1818 intel_stop_ring_buffer(ring
);
1819 WARN_ON(!IS_GEN2(ring
->dev
) && (I915_READ_MODE(ring
) & MODE_IDLE
) == 0);
1821 intel_destroy_ringbuffer_obj(ringbuf
);
1822 ring
->preallocated_lazy_request
= NULL
;
1823 ring
->outstanding_lazy_seqno
= 0;
1826 ring
->cleanup(ring
);
1828 cleanup_status_page(ring
);
1830 i915_cmd_parser_fini_ring(ring
);
1833 ring
->buffer
= NULL
;
1836 static int intel_ring_wait_request(struct intel_engine_cs
*ring
, int n
)
1838 struct intel_ringbuffer
*ringbuf
= ring
->buffer
;
1839 struct drm_i915_gem_request
*request
;
1843 if (ringbuf
->last_retired_head
!= -1) {
1844 ringbuf
->head
= ringbuf
->last_retired_head
;
1845 ringbuf
->last_retired_head
= -1;
1847 ringbuf
->space
= intel_ring_space(ringbuf
);
1848 if (ringbuf
->space
>= n
)
1852 list_for_each_entry(request
, &ring
->request_list
, list
) {
1853 if (__intel_ring_space(request
->tail
, ringbuf
->tail
,
1854 ringbuf
->size
) >= n
) {
1855 seqno
= request
->seqno
;
1863 ret
= i915_wait_seqno(ring
, seqno
);
1867 i915_gem_retire_requests_ring(ring
);
1868 ringbuf
->head
= ringbuf
->last_retired_head
;
1869 ringbuf
->last_retired_head
= -1;
1871 ringbuf
->space
= intel_ring_space(ringbuf
);
1875 static int ring_wait_for_space(struct intel_engine_cs
*ring
, int n
)
1877 struct drm_device
*dev
= ring
->dev
;
1878 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1879 struct intel_ringbuffer
*ringbuf
= ring
->buffer
;
1883 ret
= intel_ring_wait_request(ring
, n
);
1887 /* force the tail write in case we have been skipping them */
1888 __intel_ring_advance(ring
);
1890 /* With GEM the hangcheck timer should kick us out of the loop,
1891 * leaving it early runs the risk of corrupting GEM state (due
1892 * to running on almost untested codepaths). But on resume
1893 * timers don't work yet, so prevent a complete hang in that
1894 * case by choosing an insanely large timeout. */
1895 end
= jiffies
+ 60 * HZ
;
1897 trace_i915_ring_wait_begin(ring
);
1899 ringbuf
->head
= I915_READ_HEAD(ring
);
1900 ringbuf
->space
= intel_ring_space(ringbuf
);
1901 if (ringbuf
->space
>= n
) {
1906 if (!drm_core_check_feature(dev
, DRIVER_MODESET
) &&
1907 dev
->primary
->master
) {
1908 struct drm_i915_master_private
*master_priv
= dev
->primary
->master
->driver_priv
;
1909 if (master_priv
->sarea_priv
)
1910 master_priv
->sarea_priv
->perf_boxes
|= I915_BOX_WAIT
;
1915 if (dev_priv
->mm
.interruptible
&& signal_pending(current
)) {
1920 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
,
1921 dev_priv
->mm
.interruptible
);
1925 if (time_after(jiffies
, end
)) {
1930 trace_i915_ring_wait_end(ring
);
1934 static int intel_wrap_ring_buffer(struct intel_engine_cs
*ring
)
1936 uint32_t __iomem
*virt
;
1937 struct intel_ringbuffer
*ringbuf
= ring
->buffer
;
1938 int rem
= ringbuf
->size
- ringbuf
->tail
;
1940 if (ringbuf
->space
< rem
) {
1941 int ret
= ring_wait_for_space(ring
, rem
);
1946 virt
= ringbuf
->virtual_start
+ ringbuf
->tail
;
1949 iowrite32(MI_NOOP
, virt
++);
1952 ringbuf
->space
= intel_ring_space(ringbuf
);
1957 int intel_ring_idle(struct intel_engine_cs
*ring
)
1962 /* We need to add any requests required to flush the objects and ring */
1963 if (ring
->outstanding_lazy_seqno
) {
1964 ret
= i915_add_request(ring
, NULL
);
1969 /* Wait upon the last request to be completed */
1970 if (list_empty(&ring
->request_list
))
1973 seqno
= list_entry(ring
->request_list
.prev
,
1974 struct drm_i915_gem_request
,
1977 return i915_wait_seqno(ring
, seqno
);
1981 intel_ring_alloc_seqno(struct intel_engine_cs
*ring
)
1983 if (ring
->outstanding_lazy_seqno
)
1986 if (ring
->preallocated_lazy_request
== NULL
) {
1987 struct drm_i915_gem_request
*request
;
1989 request
= kmalloc(sizeof(*request
), GFP_KERNEL
);
1990 if (request
== NULL
)
1993 ring
->preallocated_lazy_request
= request
;
1996 return i915_gem_get_seqno(ring
->dev
, &ring
->outstanding_lazy_seqno
);
1999 static int __intel_ring_prepare(struct intel_engine_cs
*ring
,
2002 struct intel_ringbuffer
*ringbuf
= ring
->buffer
;
2005 if (unlikely(ringbuf
->tail
+ bytes
> ringbuf
->effective_size
)) {
2006 ret
= intel_wrap_ring_buffer(ring
);
2011 if (unlikely(ringbuf
->space
< bytes
)) {
2012 ret
= ring_wait_for_space(ring
, bytes
);
2020 int intel_ring_begin(struct intel_engine_cs
*ring
,
2023 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2026 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
,
2027 dev_priv
->mm
.interruptible
);
2031 ret
= __intel_ring_prepare(ring
, num_dwords
* sizeof(uint32_t));
2035 /* Preallocate the olr before touching the ring */
2036 ret
= intel_ring_alloc_seqno(ring
);
2040 ring
->buffer
->space
-= num_dwords
* sizeof(uint32_t);
2044 /* Align the ring tail to a cacheline boundary */
2045 int intel_ring_cacheline_align(struct intel_engine_cs
*ring
)
2047 int num_dwords
= (ring
->buffer
->tail
& (CACHELINE_BYTES
- 1)) / sizeof(uint32_t);
2050 if (num_dwords
== 0)
2053 num_dwords
= CACHELINE_BYTES
/ sizeof(uint32_t) - num_dwords
;
2054 ret
= intel_ring_begin(ring
, num_dwords
);
2058 while (num_dwords
--)
2059 intel_ring_emit(ring
, MI_NOOP
);
2061 intel_ring_advance(ring
);
2066 void intel_ring_init_seqno(struct intel_engine_cs
*ring
, u32 seqno
)
2068 struct drm_device
*dev
= ring
->dev
;
2069 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2071 BUG_ON(ring
->outstanding_lazy_seqno
);
2073 if (INTEL_INFO(dev
)->gen
== 6 || INTEL_INFO(dev
)->gen
== 7) {
2074 I915_WRITE(RING_SYNC_0(ring
->mmio_base
), 0);
2075 I915_WRITE(RING_SYNC_1(ring
->mmio_base
), 0);
2077 I915_WRITE(RING_SYNC_2(ring
->mmio_base
), 0);
2080 ring
->set_seqno(ring
, seqno
);
2081 ring
->hangcheck
.seqno
= seqno
;
2084 static void gen6_bsd_ring_write_tail(struct intel_engine_cs
*ring
,
2087 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2089 /* Every tail move must follow the sequence below */
2091 /* Disable notification that the ring is IDLE. The GT
2092 * will then assume that it is busy and bring it out of rc6.
2094 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL
,
2095 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE
));
2097 /* Clear the context id. Here be magic! */
2098 I915_WRITE64(GEN6_BSD_RNCID
, 0x0);
2100 /* Wait for the ring not to be idle, i.e. for it to wake up. */
2101 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL
) &
2102 GEN6_BSD_SLEEP_INDICATOR
) == 0,
2104 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
2106 /* Now that the ring is fully powered up, update the tail */
2107 I915_WRITE_TAIL(ring
, value
);
2108 POSTING_READ(RING_TAIL(ring
->mmio_base
));
2110 /* Let the ring send IDLE messages to the GT again,
2111 * and so let it sleep to conserve power when idle.
2113 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL
,
2114 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE
));
2117 static int gen6_bsd_ring_flush(struct intel_engine_cs
*ring
,
2118 u32 invalidate
, u32 flush
)
2123 ret
= intel_ring_begin(ring
, 4);
2128 if (INTEL_INFO(ring
->dev
)->gen
>= 8)
2131 * Bspec vol 1c.5 - video engine command streamer:
2132 * "If ENABLED, all TLBs will be invalidated once the flush
2133 * operation is complete. This bit is only valid when the
2134 * Post-Sync Operation field is a value of 1h or 3h."
2136 if (invalidate
& I915_GEM_GPU_DOMAINS
)
2137 cmd
|= MI_INVALIDATE_TLB
| MI_INVALIDATE_BSD
|
2138 MI_FLUSH_DW_STORE_INDEX
| MI_FLUSH_DW_OP_STOREDW
;
2139 intel_ring_emit(ring
, cmd
);
2140 intel_ring_emit(ring
, I915_GEM_HWS_SCRATCH_ADDR
| MI_FLUSH_DW_USE_GTT
);
2141 if (INTEL_INFO(ring
->dev
)->gen
>= 8) {
2142 intel_ring_emit(ring
, 0); /* upper addr */
2143 intel_ring_emit(ring
, 0); /* value */
2145 intel_ring_emit(ring
, 0);
2146 intel_ring_emit(ring
, MI_NOOP
);
2148 intel_ring_advance(ring
);
2153 gen8_ring_dispatch_execbuffer(struct intel_engine_cs
*ring
,
2154 u64 offset
, u32 len
,
2157 bool ppgtt
= USES_PPGTT(ring
->dev
) && !(flags
& I915_DISPATCH_SECURE
);
2160 ret
= intel_ring_begin(ring
, 4);
2164 /* FIXME(BDW): Address space and security selectors. */
2165 intel_ring_emit(ring
, MI_BATCH_BUFFER_START_GEN8
| (ppgtt
<<8));
2166 intel_ring_emit(ring
, lower_32_bits(offset
));
2167 intel_ring_emit(ring
, upper_32_bits(offset
));
2168 intel_ring_emit(ring
, MI_NOOP
);
2169 intel_ring_advance(ring
);
2175 hsw_ring_dispatch_execbuffer(struct intel_engine_cs
*ring
,
2176 u64 offset
, u32 len
,
2181 ret
= intel_ring_begin(ring
, 2);
2185 intel_ring_emit(ring
,
2186 MI_BATCH_BUFFER_START
| MI_BATCH_PPGTT_HSW
|
2187 (flags
& I915_DISPATCH_SECURE
? 0 : MI_BATCH_NON_SECURE_HSW
));
2188 /* bit0-7 is the length on GEN6+ */
2189 intel_ring_emit(ring
, offset
);
2190 intel_ring_advance(ring
);
2196 gen6_ring_dispatch_execbuffer(struct intel_engine_cs
*ring
,
2197 u64 offset
, u32 len
,
2202 ret
= intel_ring_begin(ring
, 2);
2206 intel_ring_emit(ring
,
2207 MI_BATCH_BUFFER_START
|
2208 (flags
& I915_DISPATCH_SECURE
? 0 : MI_BATCH_NON_SECURE_I965
));
2209 /* bit0-7 is the length on GEN6+ */
2210 intel_ring_emit(ring
, offset
);
2211 intel_ring_advance(ring
);
2216 /* Blitter support (SandyBridge+) */
2218 static int gen6_ring_flush(struct intel_engine_cs
*ring
,
2219 u32 invalidate
, u32 flush
)
2221 struct drm_device
*dev
= ring
->dev
;
2225 ret
= intel_ring_begin(ring
, 4);
2230 if (INTEL_INFO(ring
->dev
)->gen
>= 8)
2233 * Bspec vol 1c.3 - blitter engine command streamer:
2234 * "If ENABLED, all TLBs will be invalidated once the flush
2235 * operation is complete. This bit is only valid when the
2236 * Post-Sync Operation field is a value of 1h or 3h."
2238 if (invalidate
& I915_GEM_DOMAIN_RENDER
)
2239 cmd
|= MI_INVALIDATE_TLB
| MI_FLUSH_DW_STORE_INDEX
|
2240 MI_FLUSH_DW_OP_STOREDW
;
2241 intel_ring_emit(ring
, cmd
);
2242 intel_ring_emit(ring
, I915_GEM_HWS_SCRATCH_ADDR
| MI_FLUSH_DW_USE_GTT
);
2243 if (INTEL_INFO(ring
->dev
)->gen
>= 8) {
2244 intel_ring_emit(ring
, 0); /* upper addr */
2245 intel_ring_emit(ring
, 0); /* value */
2247 intel_ring_emit(ring
, 0);
2248 intel_ring_emit(ring
, MI_NOOP
);
2250 intel_ring_advance(ring
);
2252 if (IS_GEN7(dev
) && !invalidate
&& flush
)
2253 return gen7_ring_fbc_flush(ring
, FBC_REND_CACHE_CLEAN
);
2258 int intel_init_render_ring_buffer(struct drm_device
*dev
)
2260 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2261 struct intel_engine_cs
*ring
= &dev_priv
->ring
[RCS
];
2262 struct drm_i915_gem_object
*obj
;
2265 ring
->name
= "render ring";
2267 ring
->mmio_base
= RENDER_RING_BASE
;
2269 if (INTEL_INFO(dev
)->gen
>= 8) {
2270 if (i915_semaphore_is_enabled(dev
)) {
2271 obj
= i915_gem_alloc_object(dev
, 4096);
2273 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2274 i915
.semaphores
= 0;
2276 i915_gem_object_set_cache_level(obj
, I915_CACHE_LLC
);
2277 ret
= i915_gem_obj_ggtt_pin(obj
, 0, PIN_NONBLOCK
);
2279 drm_gem_object_unreference(&obj
->base
);
2280 DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2281 i915
.semaphores
= 0;
2283 dev_priv
->semaphore_obj
= obj
;
2286 if (IS_CHERRYVIEW(dev
))
2287 ring
->init_context
= chv_init_workarounds
;
2289 ring
->init_context
= bdw_init_workarounds
;
2290 ring
->add_request
= gen6_add_request
;
2291 ring
->flush
= gen8_render_ring_flush
;
2292 ring
->irq_get
= gen8_ring_get_irq
;
2293 ring
->irq_put
= gen8_ring_put_irq
;
2294 ring
->irq_enable_mask
= GT_RENDER_USER_INTERRUPT
;
2295 ring
->get_seqno
= gen6_ring_get_seqno
;
2296 ring
->set_seqno
= ring_set_seqno
;
2297 if (i915_semaphore_is_enabled(dev
)) {
2298 WARN_ON(!dev_priv
->semaphore_obj
);
2299 ring
->semaphore
.sync_to
= gen8_ring_sync
;
2300 ring
->semaphore
.signal
= gen8_rcs_signal
;
2301 GEN8_RING_SEMAPHORE_INIT
;
2303 } else if (INTEL_INFO(dev
)->gen
>= 6) {
2304 ring
->add_request
= gen6_add_request
;
2305 ring
->flush
= gen7_render_ring_flush
;
2306 if (INTEL_INFO(dev
)->gen
== 6)
2307 ring
->flush
= gen6_render_ring_flush
;
2308 ring
->irq_get
= gen6_ring_get_irq
;
2309 ring
->irq_put
= gen6_ring_put_irq
;
2310 ring
->irq_enable_mask
= GT_RENDER_USER_INTERRUPT
;
2311 ring
->get_seqno
= gen6_ring_get_seqno
;
2312 ring
->set_seqno
= ring_set_seqno
;
2313 if (i915_semaphore_is_enabled(dev
)) {
2314 ring
->semaphore
.sync_to
= gen6_ring_sync
;
2315 ring
->semaphore
.signal
= gen6_signal
;
2317 * The current semaphore is only applied on pre-gen8
2318 * platform. And there is no VCS2 ring on the pre-gen8
2319 * platform. So the semaphore between RCS and VCS2 is
2320 * initialized as INVALID. Gen8 will initialize the
2321 * sema between VCS2 and RCS later.
2323 ring
->semaphore
.mbox
.wait
[RCS
] = MI_SEMAPHORE_SYNC_INVALID
;
2324 ring
->semaphore
.mbox
.wait
[VCS
] = MI_SEMAPHORE_SYNC_RV
;
2325 ring
->semaphore
.mbox
.wait
[BCS
] = MI_SEMAPHORE_SYNC_RB
;
2326 ring
->semaphore
.mbox
.wait
[VECS
] = MI_SEMAPHORE_SYNC_RVE
;
2327 ring
->semaphore
.mbox
.wait
[VCS2
] = MI_SEMAPHORE_SYNC_INVALID
;
2328 ring
->semaphore
.mbox
.signal
[RCS
] = GEN6_NOSYNC
;
2329 ring
->semaphore
.mbox
.signal
[VCS
] = GEN6_VRSYNC
;
2330 ring
->semaphore
.mbox
.signal
[BCS
] = GEN6_BRSYNC
;
2331 ring
->semaphore
.mbox
.signal
[VECS
] = GEN6_VERSYNC
;
2332 ring
->semaphore
.mbox
.signal
[VCS2
] = GEN6_NOSYNC
;
2334 } else if (IS_GEN5(dev
)) {
2335 ring
->add_request
= pc_render_add_request
;
2336 ring
->flush
= gen4_render_ring_flush
;
2337 ring
->get_seqno
= pc_render_get_seqno
;
2338 ring
->set_seqno
= pc_render_set_seqno
;
2339 ring
->irq_get
= gen5_ring_get_irq
;
2340 ring
->irq_put
= gen5_ring_put_irq
;
2341 ring
->irq_enable_mask
= GT_RENDER_USER_INTERRUPT
|
2342 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
;
2344 ring
->add_request
= i9xx_add_request
;
2345 if (INTEL_INFO(dev
)->gen
< 4)
2346 ring
->flush
= gen2_render_ring_flush
;
2348 ring
->flush
= gen4_render_ring_flush
;
2349 ring
->get_seqno
= ring_get_seqno
;
2350 ring
->set_seqno
= ring_set_seqno
;
2352 ring
->irq_get
= i8xx_ring_get_irq
;
2353 ring
->irq_put
= i8xx_ring_put_irq
;
2355 ring
->irq_get
= i9xx_ring_get_irq
;
2356 ring
->irq_put
= i9xx_ring_put_irq
;
2358 ring
->irq_enable_mask
= I915_USER_INTERRUPT
;
2360 ring
->write_tail
= ring_write_tail
;
2362 if (IS_HASWELL(dev
))
2363 ring
->dispatch_execbuffer
= hsw_ring_dispatch_execbuffer
;
2364 else if (IS_GEN8(dev
))
2365 ring
->dispatch_execbuffer
= gen8_ring_dispatch_execbuffer
;
2366 else if (INTEL_INFO(dev
)->gen
>= 6)
2367 ring
->dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
;
2368 else if (INTEL_INFO(dev
)->gen
>= 4)
2369 ring
->dispatch_execbuffer
= i965_dispatch_execbuffer
;
2370 else if (IS_I830(dev
) || IS_845G(dev
))
2371 ring
->dispatch_execbuffer
= i830_dispatch_execbuffer
;
2373 ring
->dispatch_execbuffer
= i915_dispatch_execbuffer
;
2374 ring
->init
= init_render_ring
;
2375 ring
->cleanup
= render_ring_cleanup
;
2377 /* Workaround batchbuffer to combat CS tlb bug. */
2378 if (HAS_BROKEN_CS_TLB(dev
)) {
2379 obj
= i915_gem_alloc_object(dev
, I830_BATCH_LIMIT
);
2381 DRM_ERROR("Failed to allocate batch bo\n");
2385 ret
= i915_gem_obj_ggtt_pin(obj
, 0, 0);
2387 drm_gem_object_unreference(&obj
->base
);
2388 DRM_ERROR("Failed to ping batch bo\n");
2392 ring
->scratch
.obj
= obj
;
2393 ring
->scratch
.gtt_offset
= i915_gem_obj_ggtt_offset(obj
);
2396 return intel_init_ring_buffer(dev
, ring
);
2399 int intel_render_ring_init_dri(struct drm_device
*dev
, u64 start
, u32 size
)
2401 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2402 struct intel_engine_cs
*ring
= &dev_priv
->ring
[RCS
];
2403 struct intel_ringbuffer
*ringbuf
= ring
->buffer
;
2406 if (ringbuf
== NULL
) {
2407 ringbuf
= kzalloc(sizeof(*ringbuf
), GFP_KERNEL
);
2410 ring
->buffer
= ringbuf
;
2413 ring
->name
= "render ring";
2415 ring
->mmio_base
= RENDER_RING_BASE
;
2417 if (INTEL_INFO(dev
)->gen
>= 6) {
2418 /* non-kms not supported on gen6+ */
2423 /* Note: gem is not supported on gen5/ilk without kms (the corresponding
2424 * gem_init ioctl returns with -ENODEV). Hence we do not need to set up
2425 * the special gen5 functions. */
2426 ring
->add_request
= i9xx_add_request
;
2427 if (INTEL_INFO(dev
)->gen
< 4)
2428 ring
->flush
= gen2_render_ring_flush
;
2430 ring
->flush
= gen4_render_ring_flush
;
2431 ring
->get_seqno
= ring_get_seqno
;
2432 ring
->set_seqno
= ring_set_seqno
;
2434 ring
->irq_get
= i8xx_ring_get_irq
;
2435 ring
->irq_put
= i8xx_ring_put_irq
;
2437 ring
->irq_get
= i9xx_ring_get_irq
;
2438 ring
->irq_put
= i9xx_ring_put_irq
;
2440 ring
->irq_enable_mask
= I915_USER_INTERRUPT
;
2441 ring
->write_tail
= ring_write_tail
;
2442 if (INTEL_INFO(dev
)->gen
>= 4)
2443 ring
->dispatch_execbuffer
= i965_dispatch_execbuffer
;
2444 else if (IS_I830(dev
) || IS_845G(dev
))
2445 ring
->dispatch_execbuffer
= i830_dispatch_execbuffer
;
2447 ring
->dispatch_execbuffer
= i915_dispatch_execbuffer
;
2448 ring
->init
= init_render_ring
;
2449 ring
->cleanup
= render_ring_cleanup
;
2452 INIT_LIST_HEAD(&ring
->active_list
);
2453 INIT_LIST_HEAD(&ring
->request_list
);
2455 ringbuf
->size
= size
;
2456 ringbuf
->effective_size
= ringbuf
->size
;
2457 if (IS_I830(ring
->dev
) || IS_845G(ring
->dev
))
2458 ringbuf
->effective_size
-= 2 * CACHELINE_BYTES
;
2460 ringbuf
->virtual_start
= ioremap_wc(start
, size
);
2461 if (ringbuf
->virtual_start
== NULL
) {
2462 DRM_ERROR("can not ioremap virtual address for"
2468 if (!I915_NEED_GFX_HWS(dev
)) {
2469 ret
= init_phys_status_page(ring
);
2477 iounmap(ringbuf
->virtual_start
);
2480 ring
->buffer
= NULL
;
2484 int intel_init_bsd_ring_buffer(struct drm_device
*dev
)
2486 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2487 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VCS
];
2489 ring
->name
= "bsd ring";
2492 ring
->write_tail
= ring_write_tail
;
2493 if (INTEL_INFO(dev
)->gen
>= 6) {
2494 ring
->mmio_base
= GEN6_BSD_RING_BASE
;
2495 /* gen6 bsd needs a special wa for tail updates */
2497 ring
->write_tail
= gen6_bsd_ring_write_tail
;
2498 ring
->flush
= gen6_bsd_ring_flush
;
2499 ring
->add_request
= gen6_add_request
;
2500 ring
->get_seqno
= gen6_ring_get_seqno
;
2501 ring
->set_seqno
= ring_set_seqno
;
2502 if (INTEL_INFO(dev
)->gen
>= 8) {
2503 ring
->irq_enable_mask
=
2504 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
;
2505 ring
->irq_get
= gen8_ring_get_irq
;
2506 ring
->irq_put
= gen8_ring_put_irq
;
2507 ring
->dispatch_execbuffer
=
2508 gen8_ring_dispatch_execbuffer
;
2509 if (i915_semaphore_is_enabled(dev
)) {
2510 ring
->semaphore
.sync_to
= gen8_ring_sync
;
2511 ring
->semaphore
.signal
= gen8_xcs_signal
;
2512 GEN8_RING_SEMAPHORE_INIT
;
2515 ring
->irq_enable_mask
= GT_BSD_USER_INTERRUPT
;
2516 ring
->irq_get
= gen6_ring_get_irq
;
2517 ring
->irq_put
= gen6_ring_put_irq
;
2518 ring
->dispatch_execbuffer
=
2519 gen6_ring_dispatch_execbuffer
;
2520 if (i915_semaphore_is_enabled(dev
)) {
2521 ring
->semaphore
.sync_to
= gen6_ring_sync
;
2522 ring
->semaphore
.signal
= gen6_signal
;
2523 ring
->semaphore
.mbox
.wait
[RCS
] = MI_SEMAPHORE_SYNC_VR
;
2524 ring
->semaphore
.mbox
.wait
[VCS
] = MI_SEMAPHORE_SYNC_INVALID
;
2525 ring
->semaphore
.mbox
.wait
[BCS
] = MI_SEMAPHORE_SYNC_VB
;
2526 ring
->semaphore
.mbox
.wait
[VECS
] = MI_SEMAPHORE_SYNC_VVE
;
2527 ring
->semaphore
.mbox
.wait
[VCS2
] = MI_SEMAPHORE_SYNC_INVALID
;
2528 ring
->semaphore
.mbox
.signal
[RCS
] = GEN6_RVSYNC
;
2529 ring
->semaphore
.mbox
.signal
[VCS
] = GEN6_NOSYNC
;
2530 ring
->semaphore
.mbox
.signal
[BCS
] = GEN6_BVSYNC
;
2531 ring
->semaphore
.mbox
.signal
[VECS
] = GEN6_VEVSYNC
;
2532 ring
->semaphore
.mbox
.signal
[VCS2
] = GEN6_NOSYNC
;
2536 ring
->mmio_base
= BSD_RING_BASE
;
2537 ring
->flush
= bsd_ring_flush
;
2538 ring
->add_request
= i9xx_add_request
;
2539 ring
->get_seqno
= ring_get_seqno
;
2540 ring
->set_seqno
= ring_set_seqno
;
2542 ring
->irq_enable_mask
= ILK_BSD_USER_INTERRUPT
;
2543 ring
->irq_get
= gen5_ring_get_irq
;
2544 ring
->irq_put
= gen5_ring_put_irq
;
2546 ring
->irq_enable_mask
= I915_BSD_USER_INTERRUPT
;
2547 ring
->irq_get
= i9xx_ring_get_irq
;
2548 ring
->irq_put
= i9xx_ring_put_irq
;
2550 ring
->dispatch_execbuffer
= i965_dispatch_execbuffer
;
2552 ring
->init
= init_ring_common
;
2554 return intel_init_ring_buffer(dev
, ring
);
2558 * Initialize the second BSD ring for Broadwell GT3.
2559 * It is noted that this only exists on Broadwell GT3.
2561 int intel_init_bsd2_ring_buffer(struct drm_device
*dev
)
2563 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2564 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VCS2
];
2566 if ((INTEL_INFO(dev
)->gen
!= 8)) {
2567 DRM_ERROR("No dual-BSD ring on non-BDW machine\n");
2571 ring
->name
= "bsd2 ring";
2574 ring
->write_tail
= ring_write_tail
;
2575 ring
->mmio_base
= GEN8_BSD2_RING_BASE
;
2576 ring
->flush
= gen6_bsd_ring_flush
;
2577 ring
->add_request
= gen6_add_request
;
2578 ring
->get_seqno
= gen6_ring_get_seqno
;
2579 ring
->set_seqno
= ring_set_seqno
;
2580 ring
->irq_enable_mask
=
2581 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS2_IRQ_SHIFT
;
2582 ring
->irq_get
= gen8_ring_get_irq
;
2583 ring
->irq_put
= gen8_ring_put_irq
;
2584 ring
->dispatch_execbuffer
=
2585 gen8_ring_dispatch_execbuffer
;
2586 if (i915_semaphore_is_enabled(dev
)) {
2587 ring
->semaphore
.sync_to
= gen8_ring_sync
;
2588 ring
->semaphore
.signal
= gen8_xcs_signal
;
2589 GEN8_RING_SEMAPHORE_INIT
;
2591 ring
->init
= init_ring_common
;
2593 return intel_init_ring_buffer(dev
, ring
);
2596 int intel_init_blt_ring_buffer(struct drm_device
*dev
)
2598 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2599 struct intel_engine_cs
*ring
= &dev_priv
->ring
[BCS
];
2601 ring
->name
= "blitter ring";
2604 ring
->mmio_base
= BLT_RING_BASE
;
2605 ring
->write_tail
= ring_write_tail
;
2606 ring
->flush
= gen6_ring_flush
;
2607 ring
->add_request
= gen6_add_request
;
2608 ring
->get_seqno
= gen6_ring_get_seqno
;
2609 ring
->set_seqno
= ring_set_seqno
;
2610 if (INTEL_INFO(dev
)->gen
>= 8) {
2611 ring
->irq_enable_mask
=
2612 GT_RENDER_USER_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
;
2613 ring
->irq_get
= gen8_ring_get_irq
;
2614 ring
->irq_put
= gen8_ring_put_irq
;
2615 ring
->dispatch_execbuffer
= gen8_ring_dispatch_execbuffer
;
2616 if (i915_semaphore_is_enabled(dev
)) {
2617 ring
->semaphore
.sync_to
= gen8_ring_sync
;
2618 ring
->semaphore
.signal
= gen8_xcs_signal
;
2619 GEN8_RING_SEMAPHORE_INIT
;
2622 ring
->irq_enable_mask
= GT_BLT_USER_INTERRUPT
;
2623 ring
->irq_get
= gen6_ring_get_irq
;
2624 ring
->irq_put
= gen6_ring_put_irq
;
2625 ring
->dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
;
2626 if (i915_semaphore_is_enabled(dev
)) {
2627 ring
->semaphore
.signal
= gen6_signal
;
2628 ring
->semaphore
.sync_to
= gen6_ring_sync
;
2630 * The current semaphore is only applied on pre-gen8
2631 * platform. And there is no VCS2 ring on the pre-gen8
2632 * platform. So the semaphore between BCS and VCS2 is
2633 * initialized as INVALID. Gen8 will initialize the
2634 * sema between BCS and VCS2 later.
2636 ring
->semaphore
.mbox
.wait
[RCS
] = MI_SEMAPHORE_SYNC_BR
;
2637 ring
->semaphore
.mbox
.wait
[VCS
] = MI_SEMAPHORE_SYNC_BV
;
2638 ring
->semaphore
.mbox
.wait
[BCS
] = MI_SEMAPHORE_SYNC_INVALID
;
2639 ring
->semaphore
.mbox
.wait
[VECS
] = MI_SEMAPHORE_SYNC_BVE
;
2640 ring
->semaphore
.mbox
.wait
[VCS2
] = MI_SEMAPHORE_SYNC_INVALID
;
2641 ring
->semaphore
.mbox
.signal
[RCS
] = GEN6_RBSYNC
;
2642 ring
->semaphore
.mbox
.signal
[VCS
] = GEN6_VBSYNC
;
2643 ring
->semaphore
.mbox
.signal
[BCS
] = GEN6_NOSYNC
;
2644 ring
->semaphore
.mbox
.signal
[VECS
] = GEN6_VEBSYNC
;
2645 ring
->semaphore
.mbox
.signal
[VCS2
] = GEN6_NOSYNC
;
2648 ring
->init
= init_ring_common
;
2650 return intel_init_ring_buffer(dev
, ring
);
2653 int intel_init_vebox_ring_buffer(struct drm_device
*dev
)
2655 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2656 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VECS
];
2658 ring
->name
= "video enhancement ring";
2661 ring
->mmio_base
= VEBOX_RING_BASE
;
2662 ring
->write_tail
= ring_write_tail
;
2663 ring
->flush
= gen6_ring_flush
;
2664 ring
->add_request
= gen6_add_request
;
2665 ring
->get_seqno
= gen6_ring_get_seqno
;
2666 ring
->set_seqno
= ring_set_seqno
;
2668 if (INTEL_INFO(dev
)->gen
>= 8) {
2669 ring
->irq_enable_mask
=
2670 GT_RENDER_USER_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
;
2671 ring
->irq_get
= gen8_ring_get_irq
;
2672 ring
->irq_put
= gen8_ring_put_irq
;
2673 ring
->dispatch_execbuffer
= gen8_ring_dispatch_execbuffer
;
2674 if (i915_semaphore_is_enabled(dev
)) {
2675 ring
->semaphore
.sync_to
= gen8_ring_sync
;
2676 ring
->semaphore
.signal
= gen8_xcs_signal
;
2677 GEN8_RING_SEMAPHORE_INIT
;
2680 ring
->irq_enable_mask
= PM_VEBOX_USER_INTERRUPT
;
2681 ring
->irq_get
= hsw_vebox_get_irq
;
2682 ring
->irq_put
= hsw_vebox_put_irq
;
2683 ring
->dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
;
2684 if (i915_semaphore_is_enabled(dev
)) {
2685 ring
->semaphore
.sync_to
= gen6_ring_sync
;
2686 ring
->semaphore
.signal
= gen6_signal
;
2687 ring
->semaphore
.mbox
.wait
[RCS
] = MI_SEMAPHORE_SYNC_VER
;
2688 ring
->semaphore
.mbox
.wait
[VCS
] = MI_SEMAPHORE_SYNC_VEV
;
2689 ring
->semaphore
.mbox
.wait
[BCS
] = MI_SEMAPHORE_SYNC_VEB
;
2690 ring
->semaphore
.mbox
.wait
[VECS
] = MI_SEMAPHORE_SYNC_INVALID
;
2691 ring
->semaphore
.mbox
.wait
[VCS2
] = MI_SEMAPHORE_SYNC_INVALID
;
2692 ring
->semaphore
.mbox
.signal
[RCS
] = GEN6_RVESYNC
;
2693 ring
->semaphore
.mbox
.signal
[VCS
] = GEN6_VVESYNC
;
2694 ring
->semaphore
.mbox
.signal
[BCS
] = GEN6_BVESYNC
;
2695 ring
->semaphore
.mbox
.signal
[VECS
] = GEN6_NOSYNC
;
2696 ring
->semaphore
.mbox
.signal
[VCS2
] = GEN6_NOSYNC
;
2699 ring
->init
= init_ring_common
;
2701 return intel_init_ring_buffer(dev
, ring
);
2705 intel_ring_flush_all_caches(struct intel_engine_cs
*ring
)
2709 if (!ring
->gpu_caches_dirty
)
2712 ret
= ring
->flush(ring
, 0, I915_GEM_GPU_DOMAINS
);
2716 trace_i915_gem_ring_flush(ring
, 0, I915_GEM_GPU_DOMAINS
);
2718 ring
->gpu_caches_dirty
= false;
2723 intel_ring_invalidate_all_caches(struct intel_engine_cs
*ring
)
2725 uint32_t flush_domains
;
2729 if (ring
->gpu_caches_dirty
)
2730 flush_domains
= I915_GEM_GPU_DOMAINS
;
2732 ret
= ring
->flush(ring
, I915_GEM_GPU_DOMAINS
, flush_domains
);
2736 trace_i915_gem_ring_flush(ring
, I915_GEM_GPU_DOMAINS
, flush_domains
);
2738 ring
->gpu_caches_dirty
= false;
2743 intel_stop_ring_buffer(struct intel_engine_cs
*ring
)
2747 if (!intel_ring_initialized(ring
))
2750 ret
= intel_ring_idle(ring
);
2751 if (ret
&& !i915_reset_in_progress(&to_i915(ring
->dev
)->gpu_error
))
2752 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",