2 * Copyright © 2008-2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
34 #include "i915_trace.h"
35 #include "intel_drv.h"
38 * 965+ support PIPE_CONTROL commands, which provide finer grained control
39 * over cache flushing.
42 struct drm_i915_gem_object
*obj
;
43 volatile u32
*cpu_page
;
47 static inline int ring_space(struct intel_ring_buffer
*ring
)
49 int space
= (ring
->head
& HEAD_ADDR
) - (ring
->tail
+ 8);
56 gen2_render_ring_flush(struct intel_ring_buffer
*ring
,
57 u32 invalidate_domains
,
64 if (((invalidate_domains
|flush_domains
) & I915_GEM_DOMAIN_RENDER
) == 0)
65 cmd
|= MI_NO_WRITE_FLUSH
;
67 if (invalidate_domains
& I915_GEM_DOMAIN_SAMPLER
)
70 ret
= intel_ring_begin(ring
, 2);
74 intel_ring_emit(ring
, cmd
);
75 intel_ring_emit(ring
, MI_NOOP
);
76 intel_ring_advance(ring
);
82 gen4_render_ring_flush(struct intel_ring_buffer
*ring
,
83 u32 invalidate_domains
,
86 struct drm_device
*dev
= ring
->dev
;
93 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
94 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
95 * also flushed at 2d versus 3d pipeline switches.
99 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
100 * MI_READ_FLUSH is set, and is always flushed on 965.
102 * I915_GEM_DOMAIN_COMMAND may not exist?
104 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
105 * invalidated when MI_EXE_FLUSH is set.
107 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
108 * invalidated with every MI_FLUSH.
112 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
113 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
114 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
115 * are flushed at any MI_FLUSH.
118 cmd
= MI_FLUSH
| MI_NO_WRITE_FLUSH
;
119 if ((invalidate_domains
|flush_domains
) & I915_GEM_DOMAIN_RENDER
)
120 cmd
&= ~MI_NO_WRITE_FLUSH
;
121 if (invalidate_domains
& I915_GEM_DOMAIN_INSTRUCTION
)
124 if (invalidate_domains
& I915_GEM_DOMAIN_COMMAND
&&
125 (IS_G4X(dev
) || IS_GEN5(dev
)))
126 cmd
|= MI_INVALIDATE_ISP
;
128 ret
= intel_ring_begin(ring
, 2);
132 intel_ring_emit(ring
, cmd
);
133 intel_ring_emit(ring
, MI_NOOP
);
134 intel_ring_advance(ring
);
140 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
141 * implementing two workarounds on gen6. From section 1.4.7.1
142 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
144 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
145 * produced by non-pipelined state commands), software needs to first
146 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
149 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
150 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
152 * And the workaround for these two requires this workaround first:
154 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
155 * BEFORE the pipe-control with a post-sync op and no write-cache
158 * And this last workaround is tricky because of the requirements on
159 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
162 * "1 of the following must also be set:
163 * - Render Target Cache Flush Enable ([12] of DW1)
164 * - Depth Cache Flush Enable ([0] of DW1)
165 * - Stall at Pixel Scoreboard ([1] of DW1)
166 * - Depth Stall ([13] of DW1)
167 * - Post-Sync Operation ([13] of DW1)
168 * - Notify Enable ([8] of DW1)"
170 * The cache flushes require the workaround flush that triggered this
171 * one, so we can't use it. Depth stall would trigger the same.
172 * Post-sync nonzero is what triggered this second workaround, so we
173 * can't use that one either. Notify enable is IRQs, which aren't
174 * really our business. That leaves only stall at scoreboard.
177 intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer
*ring
)
179 struct pipe_control
*pc
= ring
->private;
180 u32 scratch_addr
= pc
->gtt_offset
+ 128;
184 ret
= intel_ring_begin(ring
, 6);
188 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(5));
189 intel_ring_emit(ring
, PIPE_CONTROL_CS_STALL
|
190 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
191 intel_ring_emit(ring
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
); /* address */
192 intel_ring_emit(ring
, 0); /* low dword */
193 intel_ring_emit(ring
, 0); /* high dword */
194 intel_ring_emit(ring
, MI_NOOP
);
195 intel_ring_advance(ring
);
197 ret
= intel_ring_begin(ring
, 6);
201 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(5));
202 intel_ring_emit(ring
, PIPE_CONTROL_QW_WRITE
);
203 intel_ring_emit(ring
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
); /* address */
204 intel_ring_emit(ring
, 0);
205 intel_ring_emit(ring
, 0);
206 intel_ring_emit(ring
, MI_NOOP
);
207 intel_ring_advance(ring
);
213 gen6_render_ring_flush(struct intel_ring_buffer
*ring
,
214 u32 invalidate_domains
, u32 flush_domains
)
217 struct pipe_control
*pc
= ring
->private;
218 u32 scratch_addr
= pc
->gtt_offset
+ 128;
221 /* Force SNB workarounds for PIPE_CONTROL flushes */
222 intel_emit_post_sync_nonzero_flush(ring
);
224 /* Just flush everything. Experiments have shown that reducing the
225 * number of bits based on the write domains has little performance
228 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
229 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
230 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
231 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
232 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
233 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
234 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
236 ret
= intel_ring_begin(ring
, 6);
240 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(5));
241 intel_ring_emit(ring
, flags
);
242 intel_ring_emit(ring
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
);
243 intel_ring_emit(ring
, 0); /* lower dword */
244 intel_ring_emit(ring
, 0); /* uppwer dword */
245 intel_ring_emit(ring
, MI_NOOP
);
246 intel_ring_advance(ring
);
251 static void ring_write_tail(struct intel_ring_buffer
*ring
,
254 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
255 I915_WRITE_TAIL(ring
, value
);
258 u32
intel_ring_get_active_head(struct intel_ring_buffer
*ring
)
260 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
261 u32 acthd_reg
= INTEL_INFO(ring
->dev
)->gen
>= 4 ?
262 RING_ACTHD(ring
->mmio_base
) : ACTHD
;
264 return I915_READ(acthd_reg
);
267 static int init_ring_common(struct intel_ring_buffer
*ring
)
269 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
270 struct drm_i915_gem_object
*obj
= ring
->obj
;
273 /* Stop the ring if it's running. */
274 I915_WRITE_CTL(ring
, 0);
275 I915_WRITE_HEAD(ring
, 0);
276 ring
->write_tail(ring
, 0);
278 /* Initialize the ring. */
279 I915_WRITE_START(ring
, obj
->gtt_offset
);
280 head
= I915_READ_HEAD(ring
) & HEAD_ADDR
;
282 /* G45 ring initialization fails to reset head to zero */
284 DRM_DEBUG_KMS("%s head not reset to zero "
285 "ctl %08x head %08x tail %08x start %08x\n",
288 I915_READ_HEAD(ring
),
289 I915_READ_TAIL(ring
),
290 I915_READ_START(ring
));
292 I915_WRITE_HEAD(ring
, 0);
294 if (I915_READ_HEAD(ring
) & HEAD_ADDR
) {
295 DRM_ERROR("failed to set %s head to zero "
296 "ctl %08x head %08x tail %08x start %08x\n",
299 I915_READ_HEAD(ring
),
300 I915_READ_TAIL(ring
),
301 I915_READ_START(ring
));
306 ((ring
->size
- PAGE_SIZE
) & RING_NR_PAGES
)
309 /* If the head is still not zero, the ring is dead */
310 if (wait_for((I915_READ_CTL(ring
) & RING_VALID
) != 0 &&
311 I915_READ_START(ring
) == obj
->gtt_offset
&&
312 (I915_READ_HEAD(ring
) & HEAD_ADDR
) == 0, 50)) {
313 DRM_ERROR("%s initialization failed "
314 "ctl %08x head %08x tail %08x start %08x\n",
317 I915_READ_HEAD(ring
),
318 I915_READ_TAIL(ring
),
319 I915_READ_START(ring
));
323 if (!drm_core_check_feature(ring
->dev
, DRIVER_MODESET
))
324 i915_kernel_lost_context(ring
->dev
);
326 ring
->head
= I915_READ_HEAD(ring
);
327 ring
->tail
= I915_READ_TAIL(ring
) & TAIL_ADDR
;
328 ring
->space
= ring_space(ring
);
335 init_pipe_control(struct intel_ring_buffer
*ring
)
337 struct pipe_control
*pc
;
338 struct drm_i915_gem_object
*obj
;
344 pc
= kmalloc(sizeof(*pc
), GFP_KERNEL
);
348 obj
= i915_gem_alloc_object(ring
->dev
, 4096);
350 DRM_ERROR("Failed to allocate seqno page\n");
355 i915_gem_object_set_cache_level(obj
, I915_CACHE_LLC
);
357 ret
= i915_gem_object_pin(obj
, 4096, true);
361 pc
->gtt_offset
= obj
->gtt_offset
;
362 pc
->cpu_page
= kmap(obj
->pages
[0]);
363 if (pc
->cpu_page
== NULL
)
371 i915_gem_object_unpin(obj
);
373 drm_gem_object_unreference(&obj
->base
);
380 cleanup_pipe_control(struct intel_ring_buffer
*ring
)
382 struct pipe_control
*pc
= ring
->private;
383 struct drm_i915_gem_object
*obj
;
389 kunmap(obj
->pages
[0]);
390 i915_gem_object_unpin(obj
);
391 drm_gem_object_unreference(&obj
->base
);
394 ring
->private = NULL
;
397 static int init_render_ring(struct intel_ring_buffer
*ring
)
399 struct drm_device
*dev
= ring
->dev
;
400 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
401 int ret
= init_ring_common(ring
);
403 if (INTEL_INFO(dev
)->gen
> 3) {
404 int mode
= VS_TIMER_DISPATCH
<< 16 | VS_TIMER_DISPATCH
;
405 I915_WRITE(MI_MODE
, mode
);
407 I915_WRITE(GFX_MODE_GEN7
,
408 GFX_MODE_DISABLE(GFX_TLB_INVALIDATE_ALWAYS
) |
409 GFX_MODE_ENABLE(GFX_REPLAY_MODE
));
412 if (INTEL_INFO(dev
)->gen
>= 5) {
413 ret
= init_pipe_control(ring
);
418 if (INTEL_INFO(dev
)->gen
>= 6) {
420 INSTPM_FORCE_ORDERING
<< 16 | INSTPM_FORCE_ORDERING
);
426 static void render_ring_cleanup(struct intel_ring_buffer
*ring
)
431 cleanup_pipe_control(ring
);
435 update_mboxes(struct intel_ring_buffer
*ring
,
439 intel_ring_emit(ring
, MI_SEMAPHORE_MBOX
|
440 MI_SEMAPHORE_GLOBAL_GTT
|
441 MI_SEMAPHORE_REGISTER
|
442 MI_SEMAPHORE_UPDATE
);
443 intel_ring_emit(ring
, seqno
);
444 intel_ring_emit(ring
, mmio_offset
);
448 * gen6_add_request - Update the semaphore mailbox registers
450 * @ring - ring that is adding a request
451 * @seqno - return seqno stuck into the ring
453 * Update the mailbox registers in the *other* rings with the current seqno.
454 * This acts like a signal in the canonical semaphore.
457 gen6_add_request(struct intel_ring_buffer
*ring
,
464 ret
= intel_ring_begin(ring
, 10);
468 mbox1_reg
= ring
->signal_mbox
[0];
469 mbox2_reg
= ring
->signal_mbox
[1];
471 *seqno
= i915_gem_next_request_seqno(ring
);
473 update_mboxes(ring
, *seqno
, mbox1_reg
);
474 update_mboxes(ring
, *seqno
, mbox2_reg
);
475 intel_ring_emit(ring
, MI_STORE_DWORD_INDEX
);
476 intel_ring_emit(ring
, I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
477 intel_ring_emit(ring
, *seqno
);
478 intel_ring_emit(ring
, MI_USER_INTERRUPT
);
479 intel_ring_advance(ring
);
485 * intel_ring_sync - sync the waiter to the signaller on seqno
487 * @waiter - ring that is waiting
488 * @signaller - ring which has, or will signal
489 * @seqno - seqno which the waiter will block on
492 gen6_ring_sync(struct intel_ring_buffer
*waiter
,
493 struct intel_ring_buffer
*signaller
,
497 u32 dw1
= MI_SEMAPHORE_MBOX
|
498 MI_SEMAPHORE_COMPARE
|
499 MI_SEMAPHORE_REGISTER
;
501 /* Throughout all of the GEM code, seqno passed implies our current
502 * seqno is >= the last seqno executed. However for hardware the
503 * comparison is strictly greater than.
507 WARN_ON(signaller
->semaphore_register
[waiter
->id
] ==
508 MI_SEMAPHORE_SYNC_INVALID
);
510 ret
= intel_ring_begin(waiter
, 4);
514 intel_ring_emit(waiter
,
515 dw1
| signaller
->semaphore_register
[waiter
->id
]);
516 intel_ring_emit(waiter
, seqno
);
517 intel_ring_emit(waiter
, 0);
518 intel_ring_emit(waiter
, MI_NOOP
);
519 intel_ring_advance(waiter
);
524 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
526 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
527 PIPE_CONTROL_DEPTH_STALL); \
528 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
529 intel_ring_emit(ring__, 0); \
530 intel_ring_emit(ring__, 0); \
534 pc_render_add_request(struct intel_ring_buffer
*ring
,
537 u32 seqno
= i915_gem_next_request_seqno(ring
);
538 struct pipe_control
*pc
= ring
->private;
539 u32 scratch_addr
= pc
->gtt_offset
+ 128;
542 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
543 * incoherent with writes to memory, i.e. completely fubar,
544 * so we need to use PIPE_NOTIFY instead.
546 * However, we also need to workaround the qword write
547 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
548 * memory before requesting an interrupt.
550 ret
= intel_ring_begin(ring
, 32);
554 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE
|
555 PIPE_CONTROL_WRITE_FLUSH
|
556 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
);
557 intel_ring_emit(ring
, pc
->gtt_offset
| PIPE_CONTROL_GLOBAL_GTT
);
558 intel_ring_emit(ring
, seqno
);
559 intel_ring_emit(ring
, 0);
560 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
561 scratch_addr
+= 128; /* write to separate cachelines */
562 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
564 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
566 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
568 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
570 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
572 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE
|
573 PIPE_CONTROL_WRITE_FLUSH
|
574 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
575 PIPE_CONTROL_NOTIFY
);
576 intel_ring_emit(ring
, pc
->gtt_offset
| PIPE_CONTROL_GLOBAL_GTT
);
577 intel_ring_emit(ring
, seqno
);
578 intel_ring_emit(ring
, 0);
579 intel_ring_advance(ring
);
586 gen6_ring_get_seqno(struct intel_ring_buffer
*ring
)
588 struct drm_device
*dev
= ring
->dev
;
590 /* Workaround to force correct ordering between irq and seqno writes on
591 * ivb (and maybe also on snb) by reading from a CS register (like
592 * ACTHD) before reading the status page. */
593 if (IS_GEN6(dev
) || IS_GEN7(dev
))
594 intel_ring_get_active_head(ring
);
595 return intel_read_status_page(ring
, I915_GEM_HWS_INDEX
);
599 ring_get_seqno(struct intel_ring_buffer
*ring
)
601 return intel_read_status_page(ring
, I915_GEM_HWS_INDEX
);
605 pc_render_get_seqno(struct intel_ring_buffer
*ring
)
607 struct pipe_control
*pc
= ring
->private;
608 return pc
->cpu_page
[0];
612 gen5_ring_get_irq(struct intel_ring_buffer
*ring
)
614 struct drm_device
*dev
= ring
->dev
;
615 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
617 if (!dev
->irq_enabled
)
620 spin_lock(&ring
->irq_lock
);
621 if (ring
->irq_refcount
++ == 0) {
622 dev_priv
->gt_irq_mask
&= ~ring
->irq_enable_mask
;
623 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
626 spin_unlock(&ring
->irq_lock
);
632 gen5_ring_put_irq(struct intel_ring_buffer
*ring
)
634 struct drm_device
*dev
= ring
->dev
;
635 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
637 spin_lock(&ring
->irq_lock
);
638 if (--ring
->irq_refcount
== 0) {
639 dev_priv
->gt_irq_mask
|= ring
->irq_enable_mask
;
640 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
643 spin_unlock(&ring
->irq_lock
);
647 i9xx_ring_get_irq(struct intel_ring_buffer
*ring
)
649 struct drm_device
*dev
= ring
->dev
;
650 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
652 if (!dev
->irq_enabled
)
655 spin_lock(&ring
->irq_lock
);
656 if (ring
->irq_refcount
++ == 0) {
657 dev_priv
->irq_mask
&= ~ring
->irq_enable_mask
;
658 I915_WRITE(IMR
, dev_priv
->irq_mask
);
661 spin_unlock(&ring
->irq_lock
);
667 i9xx_ring_put_irq(struct intel_ring_buffer
*ring
)
669 struct drm_device
*dev
= ring
->dev
;
670 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
672 spin_lock(&ring
->irq_lock
);
673 if (--ring
->irq_refcount
== 0) {
674 dev_priv
->irq_mask
|= ring
->irq_enable_mask
;
675 I915_WRITE(IMR
, dev_priv
->irq_mask
);
678 spin_unlock(&ring
->irq_lock
);
681 void intel_ring_setup_status_page(struct intel_ring_buffer
*ring
)
683 struct drm_device
*dev
= ring
->dev
;
684 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
687 /* The ring status page addresses are no longer next to the rest of
688 * the ring registers as of gen7.
693 mmio
= RENDER_HWS_PGA_GEN7
;
696 mmio
= BLT_HWS_PGA_GEN7
;
699 mmio
= BSD_HWS_PGA_GEN7
;
702 } else if (IS_GEN6(ring
->dev
)) {
703 mmio
= RING_HWS_PGA_GEN6(ring
->mmio_base
);
705 mmio
= RING_HWS_PGA(ring
->mmio_base
);
708 I915_WRITE(mmio
, (u32
)ring
->status_page
.gfx_addr
);
713 bsd_ring_flush(struct intel_ring_buffer
*ring
,
714 u32 invalidate_domains
,
719 ret
= intel_ring_begin(ring
, 2);
723 intel_ring_emit(ring
, MI_FLUSH
);
724 intel_ring_emit(ring
, MI_NOOP
);
725 intel_ring_advance(ring
);
730 i9xx_add_request(struct intel_ring_buffer
*ring
,
736 ret
= intel_ring_begin(ring
, 4);
740 seqno
= i915_gem_next_request_seqno(ring
);
742 intel_ring_emit(ring
, MI_STORE_DWORD_INDEX
);
743 intel_ring_emit(ring
, I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
744 intel_ring_emit(ring
, seqno
);
745 intel_ring_emit(ring
, MI_USER_INTERRUPT
);
746 intel_ring_advance(ring
);
753 gen6_ring_get_irq(struct intel_ring_buffer
*ring
)
755 struct drm_device
*dev
= ring
->dev
;
756 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
758 if (!dev
->irq_enabled
)
761 /* It looks like we need to prevent the gt from suspending while waiting
762 * for an notifiy irq, otherwise irqs seem to get lost on at least the
763 * blt/bsd rings on ivb. */
764 gen6_gt_force_wake_get(dev_priv
);
766 spin_lock(&ring
->irq_lock
);
767 if (ring
->irq_refcount
++ == 0) {
768 I915_WRITE_IMR(ring
, ~ring
->irq_enable_mask
);
769 dev_priv
->gt_irq_mask
&= ~ring
->irq_enable_mask
;
770 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
773 spin_unlock(&ring
->irq_lock
);
779 gen6_ring_put_irq(struct intel_ring_buffer
*ring
)
781 struct drm_device
*dev
= ring
->dev
;
782 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
784 spin_lock(&ring
->irq_lock
);
785 if (--ring
->irq_refcount
== 0) {
786 I915_WRITE_IMR(ring
, ~0);
787 dev_priv
->gt_irq_mask
|= ring
->irq_enable_mask
;
788 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
791 spin_unlock(&ring
->irq_lock
);
793 gen6_gt_force_wake_put(dev_priv
);
797 i965_dispatch_execbuffer(struct intel_ring_buffer
*ring
, u32 offset
, u32 length
)
801 ret
= intel_ring_begin(ring
, 2);
805 intel_ring_emit(ring
,
806 MI_BATCH_BUFFER_START
|
808 MI_BATCH_NON_SECURE_I965
);
809 intel_ring_emit(ring
, offset
);
810 intel_ring_advance(ring
);
816 i830_dispatch_execbuffer(struct intel_ring_buffer
*ring
,
821 ret
= intel_ring_begin(ring
, 4);
825 intel_ring_emit(ring
, MI_BATCH_BUFFER
);
826 intel_ring_emit(ring
, offset
| MI_BATCH_NON_SECURE
);
827 intel_ring_emit(ring
, offset
+ len
- 8);
828 intel_ring_emit(ring
, 0);
829 intel_ring_advance(ring
);
835 i915_dispatch_execbuffer(struct intel_ring_buffer
*ring
,
840 ret
= intel_ring_begin(ring
, 2);
844 intel_ring_emit(ring
, MI_BATCH_BUFFER_START
| MI_BATCH_GTT
);
845 intel_ring_emit(ring
, offset
| MI_BATCH_NON_SECURE
);
846 intel_ring_advance(ring
);
851 static void cleanup_status_page(struct intel_ring_buffer
*ring
)
853 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
854 struct drm_i915_gem_object
*obj
;
856 obj
= ring
->status_page
.obj
;
860 kunmap(obj
->pages
[0]);
861 i915_gem_object_unpin(obj
);
862 drm_gem_object_unreference(&obj
->base
);
863 ring
->status_page
.obj
= NULL
;
865 memset(&dev_priv
->hws_map
, 0, sizeof(dev_priv
->hws_map
));
868 static int init_status_page(struct intel_ring_buffer
*ring
)
870 struct drm_device
*dev
= ring
->dev
;
871 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
872 struct drm_i915_gem_object
*obj
;
875 obj
= i915_gem_alloc_object(dev
, 4096);
877 DRM_ERROR("Failed to allocate status page\n");
882 i915_gem_object_set_cache_level(obj
, I915_CACHE_LLC
);
884 ret
= i915_gem_object_pin(obj
, 4096, true);
889 ring
->status_page
.gfx_addr
= obj
->gtt_offset
;
890 ring
->status_page
.page_addr
= kmap(obj
->pages
[0]);
891 if (ring
->status_page
.page_addr
== NULL
) {
892 memset(&dev_priv
->hws_map
, 0, sizeof(dev_priv
->hws_map
));
895 ring
->status_page
.obj
= obj
;
896 memset(ring
->status_page
.page_addr
, 0, PAGE_SIZE
);
898 intel_ring_setup_status_page(ring
);
899 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
900 ring
->name
, ring
->status_page
.gfx_addr
);
905 i915_gem_object_unpin(obj
);
907 drm_gem_object_unreference(&obj
->base
);
912 static int intel_init_ring_buffer(struct drm_device
*dev
,
913 struct intel_ring_buffer
*ring
)
915 struct drm_i915_gem_object
*obj
;
919 INIT_LIST_HEAD(&ring
->active_list
);
920 INIT_LIST_HEAD(&ring
->request_list
);
921 INIT_LIST_HEAD(&ring
->gpu_write_list
);
922 ring
->size
= 32 * PAGE_SIZE
;
924 init_waitqueue_head(&ring
->irq_queue
);
925 spin_lock_init(&ring
->irq_lock
);
927 if (I915_NEED_GFX_HWS(dev
)) {
928 ret
= init_status_page(ring
);
933 obj
= i915_gem_alloc_object(dev
, ring
->size
);
935 DRM_ERROR("Failed to allocate ringbuffer\n");
942 ret
= i915_gem_object_pin(obj
, PAGE_SIZE
, true);
946 ring
->map
.size
= ring
->size
;
947 ring
->map
.offset
= dev
->agp
->base
+ obj
->gtt_offset
;
952 drm_core_ioremap_wc(&ring
->map
, dev
);
953 if (ring
->map
.handle
== NULL
) {
954 DRM_ERROR("Failed to map ringbuffer.\n");
959 ring
->virtual_start
= ring
->map
.handle
;
960 ret
= ring
->init(ring
);
964 /* Workaround an erratum on the i830 which causes a hang if
965 * the TAIL pointer points to within the last 2 cachelines
968 ring
->effective_size
= ring
->size
;
969 if (IS_I830(ring
->dev
) || IS_845G(ring
->dev
))
970 ring
->effective_size
-= 128;
975 drm_core_ioremapfree(&ring
->map
, dev
);
977 i915_gem_object_unpin(obj
);
979 drm_gem_object_unreference(&obj
->base
);
982 cleanup_status_page(ring
);
986 void intel_cleanup_ring_buffer(struct intel_ring_buffer
*ring
)
988 struct drm_i915_private
*dev_priv
;
991 if (ring
->obj
== NULL
)
994 /* Disable the ring buffer. The ring must be idle at this point */
995 dev_priv
= ring
->dev
->dev_private
;
996 ret
= intel_wait_ring_idle(ring
);
998 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1001 I915_WRITE_CTL(ring
, 0);
1003 drm_core_ioremapfree(&ring
->map
, ring
->dev
);
1005 i915_gem_object_unpin(ring
->obj
);
1006 drm_gem_object_unreference(&ring
->obj
->base
);
1010 ring
->cleanup(ring
);
1012 cleanup_status_page(ring
);
1015 static int intel_wrap_ring_buffer(struct intel_ring_buffer
*ring
)
1018 int rem
= ring
->size
- ring
->tail
;
1020 if (ring
->space
< rem
) {
1021 int ret
= intel_wait_ring_buffer(ring
, rem
);
1026 virt
= (unsigned int *)(ring
->virtual_start
+ ring
->tail
);
1034 ring
->space
= ring_space(ring
);
1039 static int intel_ring_wait_seqno(struct intel_ring_buffer
*ring
, u32 seqno
)
1041 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1042 bool was_interruptible
;
1045 /* XXX As we have not yet audited all the paths to check that
1046 * they are ready for ERESTARTSYS from intel_ring_begin, do not
1047 * allow us to be interruptible by a signal.
1049 was_interruptible
= dev_priv
->mm
.interruptible
;
1050 dev_priv
->mm
.interruptible
= false;
1052 ret
= i915_wait_request(ring
, seqno
, true);
1054 dev_priv
->mm
.interruptible
= was_interruptible
;
1059 static int intel_ring_wait_request(struct intel_ring_buffer
*ring
, int n
)
1061 struct drm_i915_gem_request
*request
;
1065 i915_gem_retire_requests_ring(ring
);
1067 if (ring
->last_retired_head
!= -1) {
1068 ring
->head
= ring
->last_retired_head
;
1069 ring
->last_retired_head
= -1;
1070 ring
->space
= ring_space(ring
);
1071 if (ring
->space
>= n
)
1075 list_for_each_entry(request
, &ring
->request_list
, list
) {
1078 if (request
->tail
== -1)
1081 space
= request
->tail
- (ring
->tail
+ 8);
1083 space
+= ring
->size
;
1085 seqno
= request
->seqno
;
1089 /* Consume this request in case we need more space than
1090 * is available and so need to prevent a race between
1091 * updating last_retired_head and direct reads of
1092 * I915_RING_HEAD. It also provides a nice sanity check.
1100 ret
= intel_ring_wait_seqno(ring
, seqno
);
1104 if (WARN_ON(ring
->last_retired_head
== -1))
1107 ring
->head
= ring
->last_retired_head
;
1108 ring
->last_retired_head
= -1;
1109 ring
->space
= ring_space(ring
);
1110 if (WARN_ON(ring
->space
< n
))
1116 int intel_wait_ring_buffer(struct intel_ring_buffer
*ring
, int n
)
1118 struct drm_device
*dev
= ring
->dev
;
1119 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1123 ret
= intel_ring_wait_request(ring
, n
);
1127 trace_i915_ring_wait_begin(ring
);
1128 if (drm_core_check_feature(dev
, DRIVER_GEM
))
1129 /* With GEM the hangcheck timer should kick us out of the loop,
1130 * leaving it early runs the risk of corrupting GEM state (due
1131 * to running on almost untested codepaths). But on resume
1132 * timers don't work yet, so prevent a complete hang in that
1133 * case by choosing an insanely large timeout. */
1134 end
= jiffies
+ 60 * HZ
;
1136 end
= jiffies
+ 3 * HZ
;
1139 ring
->head
= I915_READ_HEAD(ring
);
1140 ring
->space
= ring_space(ring
);
1141 if (ring
->space
>= n
) {
1142 trace_i915_ring_wait_end(ring
);
1146 if (dev
->primary
->master
) {
1147 struct drm_i915_master_private
*master_priv
= dev
->primary
->master
->driver_priv
;
1148 if (master_priv
->sarea_priv
)
1149 master_priv
->sarea_priv
->perf_boxes
|= I915_BOX_WAIT
;
1153 if (atomic_read(&dev_priv
->mm
.wedged
))
1155 } while (!time_after(jiffies
, end
));
1156 trace_i915_ring_wait_end(ring
);
1160 int intel_ring_begin(struct intel_ring_buffer
*ring
,
1163 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1164 int n
= 4*num_dwords
;
1167 if (unlikely(atomic_read(&dev_priv
->mm
.wedged
)))
1170 if (unlikely(ring
->tail
+ n
> ring
->effective_size
)) {
1171 ret
= intel_wrap_ring_buffer(ring
);
1176 if (unlikely(ring
->space
< n
)) {
1177 ret
= intel_wait_ring_buffer(ring
, n
);
1186 void intel_ring_advance(struct intel_ring_buffer
*ring
)
1188 ring
->tail
&= ring
->size
- 1;
1189 ring
->write_tail(ring
, ring
->tail
);
1193 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer
*ring
,
1196 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
1198 /* Every tail move must follow the sequence below */
1199 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL
,
1200 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK
|
1201 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE
);
1202 I915_WRITE(GEN6_BSD_RNCID
, 0x0);
1204 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL
) &
1205 GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR
) == 0,
1207 DRM_ERROR("timed out waiting for IDLE Indicator\n");
1209 I915_WRITE_TAIL(ring
, value
);
1210 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL
,
1211 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK
|
1212 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE
);
1215 static int gen6_ring_flush(struct intel_ring_buffer
*ring
,
1216 u32 invalidate
, u32 flush
)
1221 ret
= intel_ring_begin(ring
, 4);
1226 if (invalidate
& I915_GEM_GPU_DOMAINS
)
1227 cmd
|= MI_INVALIDATE_TLB
| MI_INVALIDATE_BSD
;
1228 intel_ring_emit(ring
, cmd
);
1229 intel_ring_emit(ring
, 0);
1230 intel_ring_emit(ring
, 0);
1231 intel_ring_emit(ring
, MI_NOOP
);
1232 intel_ring_advance(ring
);
1237 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer
*ring
,
1238 u32 offset
, u32 len
)
1242 ret
= intel_ring_begin(ring
, 2);
1246 intel_ring_emit(ring
, MI_BATCH_BUFFER_START
| MI_BATCH_NON_SECURE_I965
);
1247 /* bit0-7 is the length on GEN6+ */
1248 intel_ring_emit(ring
, offset
);
1249 intel_ring_advance(ring
);
1254 /* Blitter support (SandyBridge+) */
1256 static int blt_ring_flush(struct intel_ring_buffer
*ring
,
1257 u32 invalidate
, u32 flush
)
1262 ret
= intel_ring_begin(ring
, 4);
1267 if (invalidate
& I915_GEM_DOMAIN_RENDER
)
1268 cmd
|= MI_INVALIDATE_TLB
;
1269 intel_ring_emit(ring
, cmd
);
1270 intel_ring_emit(ring
, 0);
1271 intel_ring_emit(ring
, 0);
1272 intel_ring_emit(ring
, MI_NOOP
);
1273 intel_ring_advance(ring
);
1277 int intel_init_render_ring_buffer(struct drm_device
*dev
)
1279 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1280 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
1282 ring
->name
= "render ring";
1284 ring
->mmio_base
= RENDER_RING_BASE
;
1286 if (INTEL_INFO(dev
)->gen
>= 6) {
1287 ring
->add_request
= gen6_add_request
;
1288 ring
->flush
= gen6_render_ring_flush
;
1289 ring
->irq_get
= gen6_ring_get_irq
;
1290 ring
->irq_put
= gen6_ring_put_irq
;
1291 ring
->irq_enable_mask
= GT_USER_INTERRUPT
;
1292 ring
->get_seqno
= gen6_ring_get_seqno
;
1293 ring
->sync_to
= gen6_ring_sync
;
1294 ring
->semaphore_register
[0] = MI_SEMAPHORE_SYNC_INVALID
;
1295 ring
->semaphore_register
[1] = MI_SEMAPHORE_SYNC_RV
;
1296 ring
->semaphore_register
[2] = MI_SEMAPHORE_SYNC_RB
;
1297 ring
->signal_mbox
[0] = GEN6_VRSYNC
;
1298 ring
->signal_mbox
[1] = GEN6_BRSYNC
;
1299 } else if (IS_GEN5(dev
)) {
1300 ring
->add_request
= pc_render_add_request
;
1301 ring
->flush
= gen4_render_ring_flush
;
1302 ring
->get_seqno
= pc_render_get_seqno
;
1303 ring
->irq_get
= gen5_ring_get_irq
;
1304 ring
->irq_put
= gen5_ring_put_irq
;
1305 ring
->irq_enable_mask
= GT_USER_INTERRUPT
| GT_PIPE_NOTIFY
;
1307 ring
->add_request
= i9xx_add_request
;
1308 if (INTEL_INFO(dev
)->gen
< 4)
1309 ring
->flush
= gen2_render_ring_flush
;
1311 ring
->flush
= gen4_render_ring_flush
;
1312 ring
->get_seqno
= ring_get_seqno
;
1313 ring
->irq_get
= i9xx_ring_get_irq
;
1314 ring
->irq_put
= i9xx_ring_put_irq
;
1315 ring
->irq_enable_mask
= I915_USER_INTERRUPT
;
1317 ring
->write_tail
= ring_write_tail
;
1318 if (INTEL_INFO(dev
)->gen
>= 6)
1319 ring
->dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
;
1320 else if (INTEL_INFO(dev
)->gen
>= 4)
1321 ring
->dispatch_execbuffer
= i965_dispatch_execbuffer
;
1322 else if (IS_I830(dev
) || IS_845G(dev
))
1323 ring
->dispatch_execbuffer
= i830_dispatch_execbuffer
;
1325 ring
->dispatch_execbuffer
= i915_dispatch_execbuffer
;
1326 ring
->init
= init_render_ring
;
1327 ring
->cleanup
= render_ring_cleanup
;
1330 if (!I915_NEED_GFX_HWS(dev
)) {
1331 ring
->status_page
.page_addr
= dev_priv
->status_page_dmah
->vaddr
;
1332 memset(ring
->status_page
.page_addr
, 0, PAGE_SIZE
);
1335 return intel_init_ring_buffer(dev
, ring
);
1338 int intel_render_ring_init_dri(struct drm_device
*dev
, u64 start
, u32 size
)
1340 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1341 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
1343 ring
->name
= "render ring";
1345 ring
->mmio_base
= RENDER_RING_BASE
;
1347 if (INTEL_INFO(dev
)->gen
>= 6) {
1348 /* non-kms not supported on gen6+ */
1352 /* Note: gem is not supported on gen5/ilk without kms (the corresponding
1353 * gem_init ioctl returns with -ENODEV). Hence we do not need to set up
1354 * the special gen5 functions. */
1355 ring
->add_request
= i9xx_add_request
;
1356 if (INTEL_INFO(dev
)->gen
< 4)
1357 ring
->flush
= gen2_render_ring_flush
;
1359 ring
->flush
= gen4_render_ring_flush
;
1360 ring
->get_seqno
= ring_get_seqno
;
1361 ring
->irq_get
= i9xx_ring_get_irq
;
1362 ring
->irq_put
= i9xx_ring_put_irq
;
1363 ring
->irq_enable_mask
= I915_USER_INTERRUPT
;
1364 ring
->write_tail
= ring_write_tail
;
1365 if (INTEL_INFO(dev
)->gen
>= 4)
1366 ring
->dispatch_execbuffer
= i965_dispatch_execbuffer
;
1367 else if (IS_I830(dev
) || IS_845G(dev
))
1368 ring
->dispatch_execbuffer
= i830_dispatch_execbuffer
;
1370 ring
->dispatch_execbuffer
= i915_dispatch_execbuffer
;
1371 ring
->init
= init_render_ring
;
1372 ring
->cleanup
= render_ring_cleanup
;
1374 if (!I915_NEED_GFX_HWS(dev
))
1375 ring
->status_page
.page_addr
= dev_priv
->status_page_dmah
->vaddr
;
1378 INIT_LIST_HEAD(&ring
->active_list
);
1379 INIT_LIST_HEAD(&ring
->request_list
);
1380 INIT_LIST_HEAD(&ring
->gpu_write_list
);
1383 ring
->effective_size
= ring
->size
;
1384 if (IS_I830(ring
->dev
))
1385 ring
->effective_size
-= 128;
1387 ring
->map
.offset
= start
;
1388 ring
->map
.size
= size
;
1390 ring
->map
.flags
= 0;
1393 drm_core_ioremap_wc(&ring
->map
, dev
);
1394 if (ring
->map
.handle
== NULL
) {
1395 DRM_ERROR("can not ioremap virtual address for"
1400 ring
->virtual_start
= (void __force __iomem
*)ring
->map
.handle
;
1404 int intel_init_bsd_ring_buffer(struct drm_device
*dev
)
1406 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1407 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[VCS
];
1409 ring
->name
= "bsd ring";
1412 ring
->write_tail
= ring_write_tail
;
1413 if (IS_GEN6(dev
) || IS_GEN7(dev
)) {
1414 ring
->mmio_base
= GEN6_BSD_RING_BASE
;
1415 /* gen6 bsd needs a special wa for tail updates */
1417 ring
->write_tail
= gen6_bsd_ring_write_tail
;
1418 ring
->flush
= gen6_ring_flush
;
1419 ring
->add_request
= gen6_add_request
;
1420 ring
->get_seqno
= gen6_ring_get_seqno
;
1421 ring
->irq_enable_mask
= GEN6_BSD_USER_INTERRUPT
;
1422 ring
->irq_get
= gen6_ring_get_irq
;
1423 ring
->irq_put
= gen6_ring_put_irq
;
1424 ring
->dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
;
1425 ring
->sync_to
= gen6_ring_sync
;
1426 ring
->semaphore_register
[0] = MI_SEMAPHORE_SYNC_VR
;
1427 ring
->semaphore_register
[1] = MI_SEMAPHORE_SYNC_INVALID
;
1428 ring
->semaphore_register
[2] = MI_SEMAPHORE_SYNC_VB
;
1429 ring
->signal_mbox
[0] = GEN6_RVSYNC
;
1430 ring
->signal_mbox
[1] = GEN6_BVSYNC
;
1432 ring
->mmio_base
= BSD_RING_BASE
;
1433 ring
->flush
= bsd_ring_flush
;
1434 ring
->add_request
= i9xx_add_request
;
1435 ring
->get_seqno
= ring_get_seqno
;
1437 ring
->irq_enable_mask
= GT_BSD_USER_INTERRUPT
;
1438 ring
->irq_get
= gen5_ring_get_irq
;
1439 ring
->irq_put
= gen5_ring_put_irq
;
1441 ring
->irq_enable_mask
= I915_BSD_USER_INTERRUPT
;
1442 ring
->irq_get
= i9xx_ring_get_irq
;
1443 ring
->irq_put
= i9xx_ring_put_irq
;
1445 ring
->dispatch_execbuffer
= i965_dispatch_execbuffer
;
1447 ring
->init
= init_ring_common
;
1450 return intel_init_ring_buffer(dev
, ring
);
1453 int intel_init_blt_ring_buffer(struct drm_device
*dev
)
1455 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1456 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[BCS
];
1458 ring
->name
= "blitter ring";
1461 ring
->mmio_base
= BLT_RING_BASE
;
1462 ring
->write_tail
= ring_write_tail
;
1463 ring
->flush
= blt_ring_flush
;
1464 ring
->add_request
= gen6_add_request
;
1465 ring
->get_seqno
= gen6_ring_get_seqno
;
1466 ring
->irq_enable_mask
= GEN6_BLITTER_USER_INTERRUPT
;
1467 ring
->irq_get
= gen6_ring_get_irq
;
1468 ring
->irq_put
= gen6_ring_put_irq
;
1469 ring
->dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
;
1470 ring
->sync_to
= gen6_ring_sync
;
1471 ring
->semaphore_register
[0] = MI_SEMAPHORE_SYNC_BR
;
1472 ring
->semaphore_register
[1] = MI_SEMAPHORE_SYNC_BV
;
1473 ring
->semaphore_register
[2] = MI_SEMAPHORE_SYNC_INVALID
;
1474 ring
->signal_mbox
[0] = GEN6_RBSYNC
;
1475 ring
->signal_mbox
[1] = GEN6_VBSYNC
;
1476 ring
->init
= init_ring_common
;
1478 return intel_init_ring_buffer(dev
, ring
);