2 * Copyright © 2008-2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
32 #include <drm/i915_drm.h>
33 #include "i915_trace.h"
34 #include "intel_drv.h"
37 intel_ring_initialized(struct intel_engine_cs
*ring
)
39 struct drm_device
*dev
= ring
->dev
;
44 if (i915
.enable_execlists
) {
45 struct intel_context
*dctx
= ring
->default_context
;
46 struct intel_ringbuffer
*ringbuf
= dctx
->engine
[ring
->id
].ringbuf
;
50 return ring
->buffer
&& ring
->buffer
->obj
;
53 int __intel_ring_space(int head
, int tail
, int size
)
55 int space
= head
- tail
;
58 return space
- I915_RING_FREE_SPACE
;
61 void intel_ring_update_space(struct intel_ringbuffer
*ringbuf
)
63 if (ringbuf
->last_retired_head
!= -1) {
64 ringbuf
->head
= ringbuf
->last_retired_head
;
65 ringbuf
->last_retired_head
= -1;
68 ringbuf
->space
= __intel_ring_space(ringbuf
->head
& HEAD_ADDR
,
69 ringbuf
->tail
, ringbuf
->size
);
72 int intel_ring_space(struct intel_ringbuffer
*ringbuf
)
74 intel_ring_update_space(ringbuf
);
75 return ringbuf
->space
;
78 bool intel_ring_stopped(struct intel_engine_cs
*ring
)
80 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
81 return dev_priv
->gpu_error
.stop_rings
& intel_ring_flag(ring
);
84 void __intel_ring_advance(struct intel_engine_cs
*ring
)
86 struct intel_ringbuffer
*ringbuf
= ring
->buffer
;
87 ringbuf
->tail
&= ringbuf
->size
- 1;
88 if (intel_ring_stopped(ring
))
90 ring
->write_tail(ring
, ringbuf
->tail
);
94 gen2_render_ring_flush(struct intel_engine_cs
*ring
,
95 u32 invalidate_domains
,
102 if (((invalidate_domains
|flush_domains
) & I915_GEM_DOMAIN_RENDER
) == 0)
103 cmd
|= MI_NO_WRITE_FLUSH
;
105 if (invalidate_domains
& I915_GEM_DOMAIN_SAMPLER
)
106 cmd
|= MI_READ_FLUSH
;
108 ret
= intel_ring_begin(ring
, 2);
112 intel_ring_emit(ring
, cmd
);
113 intel_ring_emit(ring
, MI_NOOP
);
114 intel_ring_advance(ring
);
120 gen4_render_ring_flush(struct intel_engine_cs
*ring
,
121 u32 invalidate_domains
,
124 struct drm_device
*dev
= ring
->dev
;
131 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
132 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
133 * also flushed at 2d versus 3d pipeline switches.
137 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
138 * MI_READ_FLUSH is set, and is always flushed on 965.
140 * I915_GEM_DOMAIN_COMMAND may not exist?
142 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
143 * invalidated when MI_EXE_FLUSH is set.
145 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
146 * invalidated with every MI_FLUSH.
150 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
151 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
152 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
153 * are flushed at any MI_FLUSH.
156 cmd
= MI_FLUSH
| MI_NO_WRITE_FLUSH
;
157 if ((invalidate_domains
|flush_domains
) & I915_GEM_DOMAIN_RENDER
)
158 cmd
&= ~MI_NO_WRITE_FLUSH
;
159 if (invalidate_domains
& I915_GEM_DOMAIN_INSTRUCTION
)
162 if (invalidate_domains
& I915_GEM_DOMAIN_COMMAND
&&
163 (IS_G4X(dev
) || IS_GEN5(dev
)))
164 cmd
|= MI_INVALIDATE_ISP
;
166 ret
= intel_ring_begin(ring
, 2);
170 intel_ring_emit(ring
, cmd
);
171 intel_ring_emit(ring
, MI_NOOP
);
172 intel_ring_advance(ring
);
178 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
179 * implementing two workarounds on gen6. From section 1.4.7.1
180 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
182 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
183 * produced by non-pipelined state commands), software needs to first
184 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
187 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
188 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
190 * And the workaround for these two requires this workaround first:
192 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
193 * BEFORE the pipe-control with a post-sync op and no write-cache
196 * And this last workaround is tricky because of the requirements on
197 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
200 * "1 of the following must also be set:
201 * - Render Target Cache Flush Enable ([12] of DW1)
202 * - Depth Cache Flush Enable ([0] of DW1)
203 * - Stall at Pixel Scoreboard ([1] of DW1)
204 * - Depth Stall ([13] of DW1)
205 * - Post-Sync Operation ([13] of DW1)
206 * - Notify Enable ([8] of DW1)"
208 * The cache flushes require the workaround flush that triggered this
209 * one, so we can't use it. Depth stall would trigger the same.
210 * Post-sync nonzero is what triggered this second workaround, so we
211 * can't use that one either. Notify enable is IRQs, which aren't
212 * really our business. That leaves only stall at scoreboard.
215 intel_emit_post_sync_nonzero_flush(struct intel_engine_cs
*ring
)
217 u32 scratch_addr
= ring
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
221 ret
= intel_ring_begin(ring
, 6);
225 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(5));
226 intel_ring_emit(ring
, PIPE_CONTROL_CS_STALL
|
227 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
228 intel_ring_emit(ring
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
); /* address */
229 intel_ring_emit(ring
, 0); /* low dword */
230 intel_ring_emit(ring
, 0); /* high dword */
231 intel_ring_emit(ring
, MI_NOOP
);
232 intel_ring_advance(ring
);
234 ret
= intel_ring_begin(ring
, 6);
238 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(5));
239 intel_ring_emit(ring
, PIPE_CONTROL_QW_WRITE
);
240 intel_ring_emit(ring
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
); /* address */
241 intel_ring_emit(ring
, 0);
242 intel_ring_emit(ring
, 0);
243 intel_ring_emit(ring
, MI_NOOP
);
244 intel_ring_advance(ring
);
250 gen6_render_ring_flush(struct intel_engine_cs
*ring
,
251 u32 invalidate_domains
, u32 flush_domains
)
254 u32 scratch_addr
= ring
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
257 /* Force SNB workarounds for PIPE_CONTROL flushes */
258 ret
= intel_emit_post_sync_nonzero_flush(ring
);
262 /* Just flush everything. Experiments have shown that reducing the
263 * number of bits based on the write domains has little performance
267 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
268 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
270 * Ensure that any following seqno writes only happen
271 * when the render cache is indeed flushed.
273 flags
|= PIPE_CONTROL_CS_STALL
;
275 if (invalidate_domains
) {
276 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
277 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
278 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
279 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
280 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
281 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
283 * TLB invalidate requires a post-sync write.
285 flags
|= PIPE_CONTROL_QW_WRITE
| PIPE_CONTROL_CS_STALL
;
288 ret
= intel_ring_begin(ring
, 4);
292 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4));
293 intel_ring_emit(ring
, flags
);
294 intel_ring_emit(ring
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
);
295 intel_ring_emit(ring
, 0);
296 intel_ring_advance(ring
);
302 gen7_render_ring_cs_stall_wa(struct intel_engine_cs
*ring
)
306 ret
= intel_ring_begin(ring
, 4);
310 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4));
311 intel_ring_emit(ring
, PIPE_CONTROL_CS_STALL
|
312 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
313 intel_ring_emit(ring
, 0);
314 intel_ring_emit(ring
, 0);
315 intel_ring_advance(ring
);
320 static int gen7_ring_fbc_flush(struct intel_engine_cs
*ring
, u32 value
)
324 if (!ring
->fbc_dirty
)
327 ret
= intel_ring_begin(ring
, 6);
330 /* WaFbcNukeOn3DBlt:ivb/hsw */
331 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
332 intel_ring_emit(ring
, MSG_FBC_REND_STATE
);
333 intel_ring_emit(ring
, value
);
334 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM(1) | MI_SRM_LRM_GLOBAL_GTT
);
335 intel_ring_emit(ring
, MSG_FBC_REND_STATE
);
336 intel_ring_emit(ring
, ring
->scratch
.gtt_offset
+ 256);
337 intel_ring_advance(ring
);
339 ring
->fbc_dirty
= false;
344 gen7_render_ring_flush(struct intel_engine_cs
*ring
,
345 u32 invalidate_domains
, u32 flush_domains
)
348 u32 scratch_addr
= ring
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
352 * Ensure that any following seqno writes only happen when the render
353 * cache is indeed flushed.
355 * Workaround: 4th PIPE_CONTROL command (except the ones with only
356 * read-cache invalidate bits set) must have the CS_STALL bit set. We
357 * don't try to be clever and just set it unconditionally.
359 flags
|= PIPE_CONTROL_CS_STALL
;
361 /* Just flush everything. Experiments have shown that reducing the
362 * number of bits based on the write domains has little performance
366 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
367 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
369 if (invalidate_domains
) {
370 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
371 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
372 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
373 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
374 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
375 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
376 flags
|= PIPE_CONTROL_MEDIA_STATE_CLEAR
;
378 * TLB invalidate requires a post-sync write.
380 flags
|= PIPE_CONTROL_QW_WRITE
;
381 flags
|= PIPE_CONTROL_GLOBAL_GTT_IVB
;
383 flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
385 /* Workaround: we must issue a pipe_control with CS-stall bit
386 * set before a pipe_control command that has the state cache
387 * invalidate bit set. */
388 gen7_render_ring_cs_stall_wa(ring
);
391 ret
= intel_ring_begin(ring
, 4);
395 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4));
396 intel_ring_emit(ring
, flags
);
397 intel_ring_emit(ring
, scratch_addr
);
398 intel_ring_emit(ring
, 0);
399 intel_ring_advance(ring
);
401 if (!invalidate_domains
&& flush_domains
)
402 return gen7_ring_fbc_flush(ring
, FBC_REND_NUKE
);
408 gen8_emit_pipe_control(struct intel_engine_cs
*ring
,
409 u32 flags
, u32 scratch_addr
)
413 ret
= intel_ring_begin(ring
, 6);
417 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(6));
418 intel_ring_emit(ring
, flags
);
419 intel_ring_emit(ring
, scratch_addr
);
420 intel_ring_emit(ring
, 0);
421 intel_ring_emit(ring
, 0);
422 intel_ring_emit(ring
, 0);
423 intel_ring_advance(ring
);
429 gen8_render_ring_flush(struct intel_engine_cs
*ring
,
430 u32 invalidate_domains
, u32 flush_domains
)
433 u32 scratch_addr
= ring
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
436 flags
|= PIPE_CONTROL_CS_STALL
;
439 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
440 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
442 if (invalidate_domains
) {
443 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
444 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
445 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
446 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
447 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
448 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
449 flags
|= PIPE_CONTROL_QW_WRITE
;
450 flags
|= PIPE_CONTROL_GLOBAL_GTT_IVB
;
452 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
453 ret
= gen8_emit_pipe_control(ring
,
454 PIPE_CONTROL_CS_STALL
|
455 PIPE_CONTROL_STALL_AT_SCOREBOARD
,
461 ret
= gen8_emit_pipe_control(ring
, flags
, scratch_addr
);
465 if (!invalidate_domains
&& flush_domains
)
466 return gen7_ring_fbc_flush(ring
, FBC_REND_NUKE
);
471 static void ring_write_tail(struct intel_engine_cs
*ring
,
474 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
475 I915_WRITE_TAIL(ring
, value
);
478 u64
intel_ring_get_active_head(struct intel_engine_cs
*ring
)
480 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
483 if (INTEL_INFO(ring
->dev
)->gen
>= 8)
484 acthd
= I915_READ64_2x32(RING_ACTHD(ring
->mmio_base
),
485 RING_ACTHD_UDW(ring
->mmio_base
));
486 else if (INTEL_INFO(ring
->dev
)->gen
>= 4)
487 acthd
= I915_READ(RING_ACTHD(ring
->mmio_base
));
489 acthd
= I915_READ(ACTHD
);
494 static void ring_setup_phys_status_page(struct intel_engine_cs
*ring
)
496 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
499 addr
= dev_priv
->status_page_dmah
->busaddr
;
500 if (INTEL_INFO(ring
->dev
)->gen
>= 4)
501 addr
|= (dev_priv
->status_page_dmah
->busaddr
>> 28) & 0xf0;
502 I915_WRITE(HWS_PGA
, addr
);
505 static bool stop_ring(struct intel_engine_cs
*ring
)
507 struct drm_i915_private
*dev_priv
= to_i915(ring
->dev
);
509 if (!IS_GEN2(ring
->dev
)) {
510 I915_WRITE_MODE(ring
, _MASKED_BIT_ENABLE(STOP_RING
));
511 if (wait_for((I915_READ_MODE(ring
) & MODE_IDLE
) != 0, 1000)) {
512 DRM_ERROR("%s : timed out trying to stop ring\n", ring
->name
);
513 /* Sometimes we observe that the idle flag is not
514 * set even though the ring is empty. So double
515 * check before giving up.
517 if (I915_READ_HEAD(ring
) != I915_READ_TAIL(ring
))
522 I915_WRITE_CTL(ring
, 0);
523 I915_WRITE_HEAD(ring
, 0);
524 ring
->write_tail(ring
, 0);
526 if (!IS_GEN2(ring
->dev
)) {
527 (void)I915_READ_CTL(ring
);
528 I915_WRITE_MODE(ring
, _MASKED_BIT_DISABLE(STOP_RING
));
531 return (I915_READ_HEAD(ring
) & HEAD_ADDR
) == 0;
534 static int init_ring_common(struct intel_engine_cs
*ring
)
536 struct drm_device
*dev
= ring
->dev
;
537 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
538 struct intel_ringbuffer
*ringbuf
= ring
->buffer
;
539 struct drm_i915_gem_object
*obj
= ringbuf
->obj
;
542 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
544 if (!stop_ring(ring
)) {
545 /* G45 ring initialization often fails to reset head to zero */
546 DRM_DEBUG_KMS("%s head not reset to zero "
547 "ctl %08x head %08x tail %08x start %08x\n",
550 I915_READ_HEAD(ring
),
551 I915_READ_TAIL(ring
),
552 I915_READ_START(ring
));
554 if (!stop_ring(ring
)) {
555 DRM_ERROR("failed to set %s head to zero "
556 "ctl %08x head %08x tail %08x start %08x\n",
559 I915_READ_HEAD(ring
),
560 I915_READ_TAIL(ring
),
561 I915_READ_START(ring
));
567 if (I915_NEED_GFX_HWS(dev
))
568 intel_ring_setup_status_page(ring
);
570 ring_setup_phys_status_page(ring
);
572 /* Enforce ordering by reading HEAD register back */
573 I915_READ_HEAD(ring
);
575 /* Initialize the ring. This must happen _after_ we've cleared the ring
576 * registers with the above sequence (the readback of the HEAD registers
577 * also enforces ordering), otherwise the hw might lose the new ring
578 * register values. */
579 I915_WRITE_START(ring
, i915_gem_obj_ggtt_offset(obj
));
581 /* WaClearRingBufHeadRegAtInit:ctg,elk */
582 if (I915_READ_HEAD(ring
))
583 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
584 ring
->name
, I915_READ_HEAD(ring
));
585 I915_WRITE_HEAD(ring
, 0);
586 (void)I915_READ_HEAD(ring
);
589 ((ringbuf
->size
- PAGE_SIZE
) & RING_NR_PAGES
)
592 /* If the head is still not zero, the ring is dead */
593 if (wait_for((I915_READ_CTL(ring
) & RING_VALID
) != 0 &&
594 I915_READ_START(ring
) == i915_gem_obj_ggtt_offset(obj
) &&
595 (I915_READ_HEAD(ring
) & HEAD_ADDR
) == 0, 50)) {
596 DRM_ERROR("%s initialization failed "
597 "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
599 I915_READ_CTL(ring
), I915_READ_CTL(ring
) & RING_VALID
,
600 I915_READ_HEAD(ring
), I915_READ_TAIL(ring
),
601 I915_READ_START(ring
), (unsigned long)i915_gem_obj_ggtt_offset(obj
));
606 ringbuf
->last_retired_head
= -1;
607 ringbuf
->head
= I915_READ_HEAD(ring
);
608 ringbuf
->tail
= I915_READ_TAIL(ring
) & TAIL_ADDR
;
609 intel_ring_update_space(ringbuf
);
611 memset(&ring
->hangcheck
, 0, sizeof(ring
->hangcheck
));
614 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
620 intel_fini_pipe_control(struct intel_engine_cs
*ring
)
622 struct drm_device
*dev
= ring
->dev
;
624 if (ring
->scratch
.obj
== NULL
)
627 if (INTEL_INFO(dev
)->gen
>= 5) {
628 kunmap(sg_page(ring
->scratch
.obj
->pages
->sgl
));
629 i915_gem_object_ggtt_unpin(ring
->scratch
.obj
);
632 drm_gem_object_unreference(&ring
->scratch
.obj
->base
);
633 ring
->scratch
.obj
= NULL
;
637 intel_init_pipe_control(struct intel_engine_cs
*ring
)
641 WARN_ON(ring
->scratch
.obj
);
643 ring
->scratch
.obj
= i915_gem_alloc_object(ring
->dev
, 4096);
644 if (ring
->scratch
.obj
== NULL
) {
645 DRM_ERROR("Failed to allocate seqno page\n");
650 ret
= i915_gem_object_set_cache_level(ring
->scratch
.obj
, I915_CACHE_LLC
);
654 ret
= i915_gem_obj_ggtt_pin(ring
->scratch
.obj
, 4096, 0);
658 ring
->scratch
.gtt_offset
= i915_gem_obj_ggtt_offset(ring
->scratch
.obj
);
659 ring
->scratch
.cpu_page
= kmap(sg_page(ring
->scratch
.obj
->pages
->sgl
));
660 if (ring
->scratch
.cpu_page
== NULL
) {
665 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
666 ring
->name
, ring
->scratch
.gtt_offset
);
670 i915_gem_object_ggtt_unpin(ring
->scratch
.obj
);
672 drm_gem_object_unreference(&ring
->scratch
.obj
->base
);
677 static int intel_ring_workarounds_emit(struct intel_engine_cs
*ring
,
678 struct intel_context
*ctx
)
681 struct drm_device
*dev
= ring
->dev
;
682 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
683 struct i915_workarounds
*w
= &dev_priv
->workarounds
;
685 if (WARN_ON_ONCE(w
->count
== 0))
688 ring
->gpu_caches_dirty
= true;
689 ret
= intel_ring_flush_all_caches(ring
);
693 ret
= intel_ring_begin(ring
, (w
->count
* 2 + 2));
697 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(w
->count
));
698 for (i
= 0; i
< w
->count
; i
++) {
699 intel_ring_emit(ring
, w
->reg
[i
].addr
);
700 intel_ring_emit(ring
, w
->reg
[i
].value
);
702 intel_ring_emit(ring
, MI_NOOP
);
704 intel_ring_advance(ring
);
706 ring
->gpu_caches_dirty
= true;
707 ret
= intel_ring_flush_all_caches(ring
);
711 DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w
->count
);
716 static int intel_rcs_ctx_init(struct intel_engine_cs
*ring
,
717 struct intel_context
*ctx
)
721 ret
= intel_ring_workarounds_emit(ring
, ctx
);
725 ret
= i915_gem_render_state_init(ring
);
727 DRM_ERROR("init render state: %d\n", ret
);
732 static int wa_add(struct drm_i915_private
*dev_priv
,
733 const u32 addr
, const u32 mask
, const u32 val
)
735 const u32 idx
= dev_priv
->workarounds
.count
;
737 if (WARN_ON(idx
>= I915_MAX_WA_REGS
))
740 dev_priv
->workarounds
.reg
[idx
].addr
= addr
;
741 dev_priv
->workarounds
.reg
[idx
].value
= val
;
742 dev_priv
->workarounds
.reg
[idx
].mask
= mask
;
744 dev_priv
->workarounds
.count
++;
749 #define WA_REG(addr, mask, val) { \
750 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
755 #define WA_SET_BIT_MASKED(addr, mask) \
756 WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
758 #define WA_CLR_BIT_MASKED(addr, mask) \
759 WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
761 #define WA_SET_FIELD_MASKED(addr, mask, value) \
762 WA_REG(addr, mask, _MASKED_FIELD(mask, value))
764 #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
765 #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
767 #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
769 static int bdw_init_workarounds(struct intel_engine_cs
*ring
)
771 struct drm_device
*dev
= ring
->dev
;
772 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
774 /* WaDisablePartialInstShootdown:bdw */
775 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
776 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN
,
777 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE
|
778 STALL_DOP_GATING_DISABLE
);
780 /* WaDisableDopClockGating:bdw */
781 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2
,
782 DOP_CLOCK_GATING_DISABLE
);
784 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3
,
785 GEN8_SAMPLER_POWER_BYPASS_DIS
);
787 /* Use Force Non-Coherent whenever executing a 3D context. This is a
788 * workaround for for a possible hang in the unlikely event a TLB
789 * invalidation occurs during a PSD flush.
791 /* WaForceEnableNonCoherent:bdw */
792 /* WaHdcDisableFetchWhenMasked:bdw */
793 /* WaDisableFenceDestinationToSLM:bdw (GT3 pre-production) */
794 WA_SET_BIT_MASKED(HDC_CHICKEN0
,
795 HDC_FORCE_NON_COHERENT
|
796 HDC_DONOT_FETCH_MEM_WHEN_MASKED
|
797 (IS_BDW_GT3(dev
) ? HDC_FENCE_DEST_SLM_DISABLE
: 0));
799 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
800 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
801 * polygons in the same 8x4 pixel/sample area to be processed without
802 * stalling waiting for the earlier ones to write to Hierarchical Z
805 * This optimization is off by default for Broadwell; turn it on.
807 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7
, HIZ_RAW_STALL_OPT_DISABLE
);
809 /* Wa4x4STCOptimizationDisable:bdw */
810 WA_SET_BIT_MASKED(CACHE_MODE_1
,
811 GEN8_4x4_STC_OPTIMIZATION_DISABLE
);
814 * BSpec recommends 8x4 when MSAA is used,
815 * however in practice 16x4 seems fastest.
817 * Note that PS/WM thread counts depend on the WIZ hashing
818 * disable bit, which we don't touch here, but it's good
819 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
821 WA_SET_FIELD_MASKED(GEN7_GT_MODE
,
822 GEN6_WIZ_HASHING_MASK
,
823 GEN6_WIZ_HASHING_16x4
);
828 static int chv_init_workarounds(struct intel_engine_cs
*ring
)
830 struct drm_device
*dev
= ring
->dev
;
831 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
833 /* WaDisablePartialInstShootdown:chv */
834 /* WaDisableThreadStallDopClockGating:chv */
835 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN
,
836 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE
|
837 STALL_DOP_GATING_DISABLE
);
839 /* Use Force Non-Coherent whenever executing a 3D context. This is a
840 * workaround for a possible hang in the unlikely event a TLB
841 * invalidation occurs during a PSD flush.
843 /* WaForceEnableNonCoherent:chv */
844 /* WaHdcDisableFetchWhenMasked:chv */
845 WA_SET_BIT_MASKED(HDC_CHICKEN0
,
846 HDC_FORCE_NON_COHERENT
|
847 HDC_DONOT_FETCH_MEM_WHEN_MASKED
);
849 /* According to the CACHE_MODE_0 default value documentation, some
850 * CHV platforms disable this optimization by default. Turn it on.
852 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7
, HIZ_RAW_STALL_OPT_DISABLE
);
854 /* Wa4x4STCOptimizationDisable:chv */
855 WA_SET_BIT_MASKED(CACHE_MODE_1
,
856 GEN8_4x4_STC_OPTIMIZATION_DISABLE
);
858 /* Improve HiZ throughput on CHV. */
859 WA_SET_BIT_MASKED(HIZ_CHICKEN
, CHV_HZ_8X8_MODE_IN_1X
);
864 int init_workarounds_ring(struct intel_engine_cs
*ring
)
866 struct drm_device
*dev
= ring
->dev
;
867 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
869 WARN_ON(ring
->id
!= RCS
);
871 dev_priv
->workarounds
.count
= 0;
873 if (IS_BROADWELL(dev
))
874 return bdw_init_workarounds(ring
);
876 if (IS_CHERRYVIEW(dev
))
877 return chv_init_workarounds(ring
);
882 static int init_render_ring(struct intel_engine_cs
*ring
)
884 struct drm_device
*dev
= ring
->dev
;
885 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
886 int ret
= init_ring_common(ring
);
890 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
891 if (INTEL_INFO(dev
)->gen
>= 4 && INTEL_INFO(dev
)->gen
< 7)
892 I915_WRITE(MI_MODE
, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH
));
894 /* We need to disable the AsyncFlip performance optimisations in order
895 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
896 * programmed to '1' on all products.
898 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
900 if (INTEL_INFO(dev
)->gen
>= 6 && INTEL_INFO(dev
)->gen
< 9)
901 I915_WRITE(MI_MODE
, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE
));
903 /* Required for the hardware to program scanline values for waiting */
904 /* WaEnableFlushTlbInvalidationMode:snb */
905 if (INTEL_INFO(dev
)->gen
== 6)
907 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT
));
909 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
911 I915_WRITE(GFX_MODE_GEN7
,
912 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT
) |
913 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE
));
916 /* From the Sandybridge PRM, volume 1 part 3, page 24:
917 * "If this bit is set, STCunit will have LRA as replacement
918 * policy. [...] This bit must be reset. LRA replacement
919 * policy is not supported."
921 I915_WRITE(CACHE_MODE_0
,
922 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB
));
925 if (INTEL_INFO(dev
)->gen
>= 6)
926 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING
));
929 I915_WRITE_IMR(ring
, ~GT_PARITY_ERROR(dev
));
931 return init_workarounds_ring(ring
);
934 static void render_ring_cleanup(struct intel_engine_cs
*ring
)
936 struct drm_device
*dev
= ring
->dev
;
937 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
939 if (dev_priv
->semaphore_obj
) {
940 i915_gem_object_ggtt_unpin(dev_priv
->semaphore_obj
);
941 drm_gem_object_unreference(&dev_priv
->semaphore_obj
->base
);
942 dev_priv
->semaphore_obj
= NULL
;
945 intel_fini_pipe_control(ring
);
948 static int gen8_rcs_signal(struct intel_engine_cs
*signaller
,
949 unsigned int num_dwords
)
951 #define MBOX_UPDATE_DWORDS 8
952 struct drm_device
*dev
= signaller
->dev
;
953 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
954 struct intel_engine_cs
*waiter
;
955 int i
, ret
, num_rings
;
957 num_rings
= hweight32(INTEL_INFO(dev
)->ring_mask
);
958 num_dwords
+= (num_rings
-1) * MBOX_UPDATE_DWORDS
;
959 #undef MBOX_UPDATE_DWORDS
961 ret
= intel_ring_begin(signaller
, num_dwords
);
965 for_each_ring(waiter
, dev_priv
, i
) {
967 u64 gtt_offset
= signaller
->semaphore
.signal_ggtt
[i
];
968 if (gtt_offset
== MI_SEMAPHORE_SYNC_INVALID
)
971 seqno
= i915_gem_request_get_seqno(
972 signaller
->outstanding_lazy_request
);
973 intel_ring_emit(signaller
, GFX_OP_PIPE_CONTROL(6));
974 intel_ring_emit(signaller
, PIPE_CONTROL_GLOBAL_GTT_IVB
|
975 PIPE_CONTROL_QW_WRITE
|
976 PIPE_CONTROL_FLUSH_ENABLE
);
977 intel_ring_emit(signaller
, lower_32_bits(gtt_offset
));
978 intel_ring_emit(signaller
, upper_32_bits(gtt_offset
));
979 intel_ring_emit(signaller
, seqno
);
980 intel_ring_emit(signaller
, 0);
981 intel_ring_emit(signaller
, MI_SEMAPHORE_SIGNAL
|
982 MI_SEMAPHORE_TARGET(waiter
->id
));
983 intel_ring_emit(signaller
, 0);
989 static int gen8_xcs_signal(struct intel_engine_cs
*signaller
,
990 unsigned int num_dwords
)
992 #define MBOX_UPDATE_DWORDS 6
993 struct drm_device
*dev
= signaller
->dev
;
994 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
995 struct intel_engine_cs
*waiter
;
996 int i
, ret
, num_rings
;
998 num_rings
= hweight32(INTEL_INFO(dev
)->ring_mask
);
999 num_dwords
+= (num_rings
-1) * MBOX_UPDATE_DWORDS
;
1000 #undef MBOX_UPDATE_DWORDS
1002 ret
= intel_ring_begin(signaller
, num_dwords
);
1006 for_each_ring(waiter
, dev_priv
, i
) {
1008 u64 gtt_offset
= signaller
->semaphore
.signal_ggtt
[i
];
1009 if (gtt_offset
== MI_SEMAPHORE_SYNC_INVALID
)
1012 seqno
= i915_gem_request_get_seqno(
1013 signaller
->outstanding_lazy_request
);
1014 intel_ring_emit(signaller
, (MI_FLUSH_DW
+ 1) |
1015 MI_FLUSH_DW_OP_STOREDW
);
1016 intel_ring_emit(signaller
, lower_32_bits(gtt_offset
) |
1017 MI_FLUSH_DW_USE_GTT
);
1018 intel_ring_emit(signaller
, upper_32_bits(gtt_offset
));
1019 intel_ring_emit(signaller
, seqno
);
1020 intel_ring_emit(signaller
, MI_SEMAPHORE_SIGNAL
|
1021 MI_SEMAPHORE_TARGET(waiter
->id
));
1022 intel_ring_emit(signaller
, 0);
1028 static int gen6_signal(struct intel_engine_cs
*signaller
,
1029 unsigned int num_dwords
)
1031 struct drm_device
*dev
= signaller
->dev
;
1032 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1033 struct intel_engine_cs
*useless
;
1034 int i
, ret
, num_rings
;
1036 #define MBOX_UPDATE_DWORDS 3
1037 num_rings
= hweight32(INTEL_INFO(dev
)->ring_mask
);
1038 num_dwords
+= round_up((num_rings
-1) * MBOX_UPDATE_DWORDS
, 2);
1039 #undef MBOX_UPDATE_DWORDS
1041 ret
= intel_ring_begin(signaller
, num_dwords
);
1045 for_each_ring(useless
, dev_priv
, i
) {
1046 u32 mbox_reg
= signaller
->semaphore
.mbox
.signal
[i
];
1047 if (mbox_reg
!= GEN6_NOSYNC
) {
1048 u32 seqno
= i915_gem_request_get_seqno(
1049 signaller
->outstanding_lazy_request
);
1050 intel_ring_emit(signaller
, MI_LOAD_REGISTER_IMM(1));
1051 intel_ring_emit(signaller
, mbox_reg
);
1052 intel_ring_emit(signaller
, seqno
);
1056 /* If num_dwords was rounded, make sure the tail pointer is correct */
1057 if (num_rings
% 2 == 0)
1058 intel_ring_emit(signaller
, MI_NOOP
);
1064 * gen6_add_request - Update the semaphore mailbox registers
1066 * @ring - ring that is adding a request
1067 * @seqno - return seqno stuck into the ring
1069 * Update the mailbox registers in the *other* rings with the current seqno.
1070 * This acts like a signal in the canonical semaphore.
1073 gen6_add_request(struct intel_engine_cs
*ring
)
1077 if (ring
->semaphore
.signal
)
1078 ret
= ring
->semaphore
.signal(ring
, 4);
1080 ret
= intel_ring_begin(ring
, 4);
1085 intel_ring_emit(ring
, MI_STORE_DWORD_INDEX
);
1086 intel_ring_emit(ring
, I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
1087 intel_ring_emit(ring
,
1088 i915_gem_request_get_seqno(ring
->outstanding_lazy_request
));
1089 intel_ring_emit(ring
, MI_USER_INTERRUPT
);
1090 __intel_ring_advance(ring
);
1095 static inline bool i915_gem_has_seqno_wrapped(struct drm_device
*dev
,
1098 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1099 return dev_priv
->last_seqno
< seqno
;
1103 * intel_ring_sync - sync the waiter to the signaller on seqno
1105 * @waiter - ring that is waiting
1106 * @signaller - ring which has, or will signal
1107 * @seqno - seqno which the waiter will block on
1111 gen8_ring_sync(struct intel_engine_cs
*waiter
,
1112 struct intel_engine_cs
*signaller
,
1115 struct drm_i915_private
*dev_priv
= waiter
->dev
->dev_private
;
1118 ret
= intel_ring_begin(waiter
, 4);
1122 intel_ring_emit(waiter
, MI_SEMAPHORE_WAIT
|
1123 MI_SEMAPHORE_GLOBAL_GTT
|
1125 MI_SEMAPHORE_SAD_GTE_SDD
);
1126 intel_ring_emit(waiter
, seqno
);
1127 intel_ring_emit(waiter
,
1128 lower_32_bits(GEN8_WAIT_OFFSET(waiter
, signaller
->id
)));
1129 intel_ring_emit(waiter
,
1130 upper_32_bits(GEN8_WAIT_OFFSET(waiter
, signaller
->id
)));
1131 intel_ring_advance(waiter
);
1136 gen6_ring_sync(struct intel_engine_cs
*waiter
,
1137 struct intel_engine_cs
*signaller
,
1140 u32 dw1
= MI_SEMAPHORE_MBOX
|
1141 MI_SEMAPHORE_COMPARE
|
1142 MI_SEMAPHORE_REGISTER
;
1143 u32 wait_mbox
= signaller
->semaphore
.mbox
.wait
[waiter
->id
];
1146 /* Throughout all of the GEM code, seqno passed implies our current
1147 * seqno is >= the last seqno executed. However for hardware the
1148 * comparison is strictly greater than.
1152 WARN_ON(wait_mbox
== MI_SEMAPHORE_SYNC_INVALID
);
1154 ret
= intel_ring_begin(waiter
, 4);
1158 /* If seqno wrap happened, omit the wait with no-ops */
1159 if (likely(!i915_gem_has_seqno_wrapped(waiter
->dev
, seqno
))) {
1160 intel_ring_emit(waiter
, dw1
| wait_mbox
);
1161 intel_ring_emit(waiter
, seqno
);
1162 intel_ring_emit(waiter
, 0);
1163 intel_ring_emit(waiter
, MI_NOOP
);
1165 intel_ring_emit(waiter
, MI_NOOP
);
1166 intel_ring_emit(waiter
, MI_NOOP
);
1167 intel_ring_emit(waiter
, MI_NOOP
);
1168 intel_ring_emit(waiter
, MI_NOOP
);
1170 intel_ring_advance(waiter
);
1175 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
1177 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
1178 PIPE_CONTROL_DEPTH_STALL); \
1179 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
1180 intel_ring_emit(ring__, 0); \
1181 intel_ring_emit(ring__, 0); \
1185 pc_render_add_request(struct intel_engine_cs
*ring
)
1187 u32 scratch_addr
= ring
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
1190 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1191 * incoherent with writes to memory, i.e. completely fubar,
1192 * so we need to use PIPE_NOTIFY instead.
1194 * However, we also need to workaround the qword write
1195 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1196 * memory before requesting an interrupt.
1198 ret
= intel_ring_begin(ring
, 32);
1202 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE
|
1203 PIPE_CONTROL_WRITE_FLUSH
|
1204 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
);
1205 intel_ring_emit(ring
, ring
->scratch
.gtt_offset
| PIPE_CONTROL_GLOBAL_GTT
);
1206 intel_ring_emit(ring
,
1207 i915_gem_request_get_seqno(ring
->outstanding_lazy_request
));
1208 intel_ring_emit(ring
, 0);
1209 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
1210 scratch_addr
+= 2 * CACHELINE_BYTES
; /* write to separate cachelines */
1211 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
1212 scratch_addr
+= 2 * CACHELINE_BYTES
;
1213 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
1214 scratch_addr
+= 2 * CACHELINE_BYTES
;
1215 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
1216 scratch_addr
+= 2 * CACHELINE_BYTES
;
1217 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
1218 scratch_addr
+= 2 * CACHELINE_BYTES
;
1219 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
1221 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE
|
1222 PIPE_CONTROL_WRITE_FLUSH
|
1223 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
1224 PIPE_CONTROL_NOTIFY
);
1225 intel_ring_emit(ring
, ring
->scratch
.gtt_offset
| PIPE_CONTROL_GLOBAL_GTT
);
1226 intel_ring_emit(ring
,
1227 i915_gem_request_get_seqno(ring
->outstanding_lazy_request
));
1228 intel_ring_emit(ring
, 0);
1229 __intel_ring_advance(ring
);
1235 gen6_ring_get_seqno(struct intel_engine_cs
*ring
, bool lazy_coherency
)
1237 /* Workaround to force correct ordering between irq and seqno writes on
1238 * ivb (and maybe also on snb) by reading from a CS register (like
1239 * ACTHD) before reading the status page. */
1240 if (!lazy_coherency
) {
1241 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1242 POSTING_READ(RING_ACTHD(ring
->mmio_base
));
1245 return intel_read_status_page(ring
, I915_GEM_HWS_INDEX
);
1249 ring_get_seqno(struct intel_engine_cs
*ring
, bool lazy_coherency
)
1251 return intel_read_status_page(ring
, I915_GEM_HWS_INDEX
);
1255 ring_set_seqno(struct intel_engine_cs
*ring
, u32 seqno
)
1257 intel_write_status_page(ring
, I915_GEM_HWS_INDEX
, seqno
);
1261 pc_render_get_seqno(struct intel_engine_cs
*ring
, bool lazy_coherency
)
1263 return ring
->scratch
.cpu_page
[0];
1267 pc_render_set_seqno(struct intel_engine_cs
*ring
, u32 seqno
)
1269 ring
->scratch
.cpu_page
[0] = seqno
;
1273 gen5_ring_get_irq(struct intel_engine_cs
*ring
)
1275 struct drm_device
*dev
= ring
->dev
;
1276 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1277 unsigned long flags
;
1279 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
1282 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1283 if (ring
->irq_refcount
++ == 0)
1284 gen5_enable_gt_irq(dev_priv
, ring
->irq_enable_mask
);
1285 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1291 gen5_ring_put_irq(struct intel_engine_cs
*ring
)
1293 struct drm_device
*dev
= ring
->dev
;
1294 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1295 unsigned long flags
;
1297 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1298 if (--ring
->irq_refcount
== 0)
1299 gen5_disable_gt_irq(dev_priv
, ring
->irq_enable_mask
);
1300 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1304 i9xx_ring_get_irq(struct intel_engine_cs
*ring
)
1306 struct drm_device
*dev
= ring
->dev
;
1307 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1308 unsigned long flags
;
1310 if (!intel_irqs_enabled(dev_priv
))
1313 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1314 if (ring
->irq_refcount
++ == 0) {
1315 dev_priv
->irq_mask
&= ~ring
->irq_enable_mask
;
1316 I915_WRITE(IMR
, dev_priv
->irq_mask
);
1319 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1325 i9xx_ring_put_irq(struct intel_engine_cs
*ring
)
1327 struct drm_device
*dev
= ring
->dev
;
1328 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1329 unsigned long flags
;
1331 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1332 if (--ring
->irq_refcount
== 0) {
1333 dev_priv
->irq_mask
|= ring
->irq_enable_mask
;
1334 I915_WRITE(IMR
, dev_priv
->irq_mask
);
1337 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1341 i8xx_ring_get_irq(struct intel_engine_cs
*ring
)
1343 struct drm_device
*dev
= ring
->dev
;
1344 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1345 unsigned long flags
;
1347 if (!intel_irqs_enabled(dev_priv
))
1350 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1351 if (ring
->irq_refcount
++ == 0) {
1352 dev_priv
->irq_mask
&= ~ring
->irq_enable_mask
;
1353 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
1354 POSTING_READ16(IMR
);
1356 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1362 i8xx_ring_put_irq(struct intel_engine_cs
*ring
)
1364 struct drm_device
*dev
= ring
->dev
;
1365 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1366 unsigned long flags
;
1368 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1369 if (--ring
->irq_refcount
== 0) {
1370 dev_priv
->irq_mask
|= ring
->irq_enable_mask
;
1371 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
1372 POSTING_READ16(IMR
);
1374 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1377 void intel_ring_setup_status_page(struct intel_engine_cs
*ring
)
1379 struct drm_device
*dev
= ring
->dev
;
1380 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1383 /* The ring status page addresses are no longer next to the rest of
1384 * the ring registers as of gen7.
1389 mmio
= RENDER_HWS_PGA_GEN7
;
1392 mmio
= BLT_HWS_PGA_GEN7
;
1395 * VCS2 actually doesn't exist on Gen7. Only shut up
1396 * gcc switch check warning
1400 mmio
= BSD_HWS_PGA_GEN7
;
1403 mmio
= VEBOX_HWS_PGA_GEN7
;
1406 } else if (IS_GEN6(ring
->dev
)) {
1407 mmio
= RING_HWS_PGA_GEN6(ring
->mmio_base
);
1409 /* XXX: gen8 returns to sanity */
1410 mmio
= RING_HWS_PGA(ring
->mmio_base
);
1413 I915_WRITE(mmio
, (u32
)ring
->status_page
.gfx_addr
);
1417 * Flush the TLB for this page
1419 * FIXME: These two bits have disappeared on gen8, so a question
1420 * arises: do we still need this and if so how should we go about
1421 * invalidating the TLB?
1423 if (INTEL_INFO(dev
)->gen
>= 6 && INTEL_INFO(dev
)->gen
< 8) {
1424 u32 reg
= RING_INSTPM(ring
->mmio_base
);
1426 /* ring should be idle before issuing a sync flush*/
1427 WARN_ON((I915_READ_MODE(ring
) & MODE_IDLE
) == 0);
1430 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE
|
1431 INSTPM_SYNC_FLUSH
));
1432 if (wait_for((I915_READ(reg
) & INSTPM_SYNC_FLUSH
) == 0,
1434 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
1440 bsd_ring_flush(struct intel_engine_cs
*ring
,
1441 u32 invalidate_domains
,
1446 ret
= intel_ring_begin(ring
, 2);
1450 intel_ring_emit(ring
, MI_FLUSH
);
1451 intel_ring_emit(ring
, MI_NOOP
);
1452 intel_ring_advance(ring
);
1457 i9xx_add_request(struct intel_engine_cs
*ring
)
1461 ret
= intel_ring_begin(ring
, 4);
1465 intel_ring_emit(ring
, MI_STORE_DWORD_INDEX
);
1466 intel_ring_emit(ring
, I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
1467 intel_ring_emit(ring
,
1468 i915_gem_request_get_seqno(ring
->outstanding_lazy_request
));
1469 intel_ring_emit(ring
, MI_USER_INTERRUPT
);
1470 __intel_ring_advance(ring
);
1476 gen6_ring_get_irq(struct intel_engine_cs
*ring
)
1478 struct drm_device
*dev
= ring
->dev
;
1479 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1480 unsigned long flags
;
1482 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
1485 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1486 if (ring
->irq_refcount
++ == 0) {
1487 if (HAS_L3_DPF(dev
) && ring
->id
== RCS
)
1488 I915_WRITE_IMR(ring
,
1489 ~(ring
->irq_enable_mask
|
1490 GT_PARITY_ERROR(dev
)));
1492 I915_WRITE_IMR(ring
, ~ring
->irq_enable_mask
);
1493 gen5_enable_gt_irq(dev_priv
, ring
->irq_enable_mask
);
1495 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1501 gen6_ring_put_irq(struct intel_engine_cs
*ring
)
1503 struct drm_device
*dev
= ring
->dev
;
1504 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1505 unsigned long flags
;
1507 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1508 if (--ring
->irq_refcount
== 0) {
1509 if (HAS_L3_DPF(dev
) && ring
->id
== RCS
)
1510 I915_WRITE_IMR(ring
, ~GT_PARITY_ERROR(dev
));
1512 I915_WRITE_IMR(ring
, ~0);
1513 gen5_disable_gt_irq(dev_priv
, ring
->irq_enable_mask
);
1515 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1519 hsw_vebox_get_irq(struct intel_engine_cs
*ring
)
1521 struct drm_device
*dev
= ring
->dev
;
1522 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1523 unsigned long flags
;
1525 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
1528 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1529 if (ring
->irq_refcount
++ == 0) {
1530 I915_WRITE_IMR(ring
, ~ring
->irq_enable_mask
);
1531 gen6_enable_pm_irq(dev_priv
, ring
->irq_enable_mask
);
1533 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1539 hsw_vebox_put_irq(struct intel_engine_cs
*ring
)
1541 struct drm_device
*dev
= ring
->dev
;
1542 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1543 unsigned long flags
;
1545 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1546 if (--ring
->irq_refcount
== 0) {
1547 I915_WRITE_IMR(ring
, ~0);
1548 gen6_disable_pm_irq(dev_priv
, ring
->irq_enable_mask
);
1550 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1554 gen8_ring_get_irq(struct intel_engine_cs
*ring
)
1556 struct drm_device
*dev
= ring
->dev
;
1557 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1558 unsigned long flags
;
1560 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
1563 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1564 if (ring
->irq_refcount
++ == 0) {
1565 if (HAS_L3_DPF(dev
) && ring
->id
== RCS
) {
1566 I915_WRITE_IMR(ring
,
1567 ~(ring
->irq_enable_mask
|
1568 GT_RENDER_L3_PARITY_ERROR_INTERRUPT
));
1570 I915_WRITE_IMR(ring
, ~ring
->irq_enable_mask
);
1572 POSTING_READ(RING_IMR(ring
->mmio_base
));
1574 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1580 gen8_ring_put_irq(struct intel_engine_cs
*ring
)
1582 struct drm_device
*dev
= ring
->dev
;
1583 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1584 unsigned long flags
;
1586 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1587 if (--ring
->irq_refcount
== 0) {
1588 if (HAS_L3_DPF(dev
) && ring
->id
== RCS
) {
1589 I915_WRITE_IMR(ring
,
1590 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT
);
1592 I915_WRITE_IMR(ring
, ~0);
1594 POSTING_READ(RING_IMR(ring
->mmio_base
));
1596 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1600 i965_dispatch_execbuffer(struct intel_engine_cs
*ring
,
1601 u64 offset
, u32 length
,
1606 ret
= intel_ring_begin(ring
, 2);
1610 intel_ring_emit(ring
,
1611 MI_BATCH_BUFFER_START
|
1613 (flags
& I915_DISPATCH_SECURE
? 0 : MI_BATCH_NON_SECURE_I965
));
1614 intel_ring_emit(ring
, offset
);
1615 intel_ring_advance(ring
);
1620 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1621 #define I830_BATCH_LIMIT (256*1024)
1622 #define I830_TLB_ENTRIES (2)
1623 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
1625 i830_dispatch_execbuffer(struct intel_engine_cs
*ring
,
1626 u64 offset
, u32 len
,
1629 u32 cs_offset
= ring
->scratch
.gtt_offset
;
1632 ret
= intel_ring_begin(ring
, 6);
1636 /* Evict the invalid PTE TLBs */
1637 intel_ring_emit(ring
, COLOR_BLT_CMD
| BLT_WRITE_RGBA
);
1638 intel_ring_emit(ring
, BLT_DEPTH_32
| BLT_ROP_COLOR_COPY
| 4096);
1639 intel_ring_emit(ring
, I830_TLB_ENTRIES
<< 16 | 4); /* load each page */
1640 intel_ring_emit(ring
, cs_offset
);
1641 intel_ring_emit(ring
, 0xdeadbeef);
1642 intel_ring_emit(ring
, MI_NOOP
);
1643 intel_ring_advance(ring
);
1645 if ((flags
& I915_DISPATCH_PINNED
) == 0) {
1646 if (len
> I830_BATCH_LIMIT
)
1649 ret
= intel_ring_begin(ring
, 6 + 2);
1653 /* Blit the batch (which has now all relocs applied) to the
1654 * stable batch scratch bo area (so that the CS never
1655 * stumbles over its tlb invalidation bug) ...
1657 intel_ring_emit(ring
, SRC_COPY_BLT_CMD
| BLT_WRITE_RGBA
);
1658 intel_ring_emit(ring
, BLT_DEPTH_32
| BLT_ROP_SRC_COPY
| 4096);
1659 intel_ring_emit(ring
, DIV_ROUND_UP(len
, 4096) << 16 | 4096);
1660 intel_ring_emit(ring
, cs_offset
);
1661 intel_ring_emit(ring
, 4096);
1662 intel_ring_emit(ring
, offset
);
1664 intel_ring_emit(ring
, MI_FLUSH
);
1665 intel_ring_emit(ring
, MI_NOOP
);
1666 intel_ring_advance(ring
);
1668 /* ... and execute it. */
1672 ret
= intel_ring_begin(ring
, 4);
1676 intel_ring_emit(ring
, MI_BATCH_BUFFER
);
1677 intel_ring_emit(ring
, offset
| (flags
& I915_DISPATCH_SECURE
? 0 : MI_BATCH_NON_SECURE
));
1678 intel_ring_emit(ring
, offset
+ len
- 8);
1679 intel_ring_emit(ring
, MI_NOOP
);
1680 intel_ring_advance(ring
);
1686 i915_dispatch_execbuffer(struct intel_engine_cs
*ring
,
1687 u64 offset
, u32 len
,
1692 ret
= intel_ring_begin(ring
, 2);
1696 intel_ring_emit(ring
, MI_BATCH_BUFFER_START
| MI_BATCH_GTT
);
1697 intel_ring_emit(ring
, offset
| (flags
& I915_DISPATCH_SECURE
? 0 : MI_BATCH_NON_SECURE
));
1698 intel_ring_advance(ring
);
1703 static void cleanup_status_page(struct intel_engine_cs
*ring
)
1705 struct drm_i915_gem_object
*obj
;
1707 obj
= ring
->status_page
.obj
;
1711 kunmap(sg_page(obj
->pages
->sgl
));
1712 i915_gem_object_ggtt_unpin(obj
);
1713 drm_gem_object_unreference(&obj
->base
);
1714 ring
->status_page
.obj
= NULL
;
1717 static int init_status_page(struct intel_engine_cs
*ring
)
1719 struct drm_i915_gem_object
*obj
;
1721 if ((obj
= ring
->status_page
.obj
) == NULL
) {
1725 obj
= i915_gem_alloc_object(ring
->dev
, 4096);
1727 DRM_ERROR("Failed to allocate status page\n");
1731 ret
= i915_gem_object_set_cache_level(obj
, I915_CACHE_LLC
);
1736 if (!HAS_LLC(ring
->dev
))
1737 /* On g33, we cannot place HWS above 256MiB, so
1738 * restrict its pinning to the low mappable arena.
1739 * Though this restriction is not documented for
1740 * gen4, gen5, or byt, they also behave similarly
1741 * and hang if the HWS is placed at the top of the
1742 * GTT. To generalise, it appears that all !llc
1743 * platforms have issues with us placing the HWS
1744 * above the mappable region (even though we never
1747 flags
|= PIN_MAPPABLE
;
1748 ret
= i915_gem_obj_ggtt_pin(obj
, 4096, flags
);
1751 drm_gem_object_unreference(&obj
->base
);
1755 ring
->status_page
.obj
= obj
;
1758 ring
->status_page
.gfx_addr
= i915_gem_obj_ggtt_offset(obj
);
1759 ring
->status_page
.page_addr
= kmap(sg_page(obj
->pages
->sgl
));
1760 memset(ring
->status_page
.page_addr
, 0, PAGE_SIZE
);
1762 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1763 ring
->name
, ring
->status_page
.gfx_addr
);
1768 static int init_phys_status_page(struct intel_engine_cs
*ring
)
1770 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1772 if (!dev_priv
->status_page_dmah
) {
1773 dev_priv
->status_page_dmah
=
1774 drm_pci_alloc(ring
->dev
, PAGE_SIZE
, PAGE_SIZE
);
1775 if (!dev_priv
->status_page_dmah
)
1779 ring
->status_page
.page_addr
= dev_priv
->status_page_dmah
->vaddr
;
1780 memset(ring
->status_page
.page_addr
, 0, PAGE_SIZE
);
1785 void intel_unpin_ringbuffer_obj(struct intel_ringbuffer
*ringbuf
)
1787 iounmap(ringbuf
->virtual_start
);
1788 ringbuf
->virtual_start
= NULL
;
1789 i915_gem_object_ggtt_unpin(ringbuf
->obj
);
1792 int intel_pin_and_map_ringbuffer_obj(struct drm_device
*dev
,
1793 struct intel_ringbuffer
*ringbuf
)
1795 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1796 struct drm_i915_gem_object
*obj
= ringbuf
->obj
;
1799 ret
= i915_gem_obj_ggtt_pin(obj
, PAGE_SIZE
, PIN_MAPPABLE
);
1803 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
1805 i915_gem_object_ggtt_unpin(obj
);
1809 ringbuf
->virtual_start
= ioremap_wc(dev_priv
->gtt
.mappable_base
+
1810 i915_gem_obj_ggtt_offset(obj
), ringbuf
->size
);
1811 if (ringbuf
->virtual_start
== NULL
) {
1812 i915_gem_object_ggtt_unpin(obj
);
1819 void intel_destroy_ringbuffer_obj(struct intel_ringbuffer
*ringbuf
)
1821 drm_gem_object_unreference(&ringbuf
->obj
->base
);
1822 ringbuf
->obj
= NULL
;
1825 int intel_alloc_ringbuffer_obj(struct drm_device
*dev
,
1826 struct intel_ringbuffer
*ringbuf
)
1828 struct drm_i915_gem_object
*obj
;
1832 obj
= i915_gem_object_create_stolen(dev
, ringbuf
->size
);
1834 obj
= i915_gem_alloc_object(dev
, ringbuf
->size
);
1838 /* mark ring buffers as read-only from GPU side by default */
1846 static int intel_init_ring_buffer(struct drm_device
*dev
,
1847 struct intel_engine_cs
*ring
)
1849 struct intel_ringbuffer
*ringbuf
;
1852 WARN_ON(ring
->buffer
);
1854 ringbuf
= kzalloc(sizeof(*ringbuf
), GFP_KERNEL
);
1857 ring
->buffer
= ringbuf
;
1860 INIT_LIST_HEAD(&ring
->active_list
);
1861 INIT_LIST_HEAD(&ring
->request_list
);
1862 INIT_LIST_HEAD(&ring
->execlist_queue
);
1863 ringbuf
->size
= 32 * PAGE_SIZE
;
1864 ringbuf
->ring
= ring
;
1865 memset(ring
->semaphore
.sync_seqno
, 0, sizeof(ring
->semaphore
.sync_seqno
));
1867 init_waitqueue_head(&ring
->irq_queue
);
1869 if (I915_NEED_GFX_HWS(dev
)) {
1870 ret
= init_status_page(ring
);
1874 BUG_ON(ring
->id
!= RCS
);
1875 ret
= init_phys_status_page(ring
);
1880 WARN_ON(ringbuf
->obj
);
1882 ret
= intel_alloc_ringbuffer_obj(dev
, ringbuf
);
1884 DRM_ERROR("Failed to allocate ringbuffer %s: %d\n",
1889 ret
= intel_pin_and_map_ringbuffer_obj(dev
, ringbuf
);
1891 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
1893 intel_destroy_ringbuffer_obj(ringbuf
);
1897 /* Workaround an erratum on the i830 which causes a hang if
1898 * the TAIL pointer points to within the last 2 cachelines
1901 ringbuf
->effective_size
= ringbuf
->size
;
1902 if (IS_I830(dev
) || IS_845G(dev
))
1903 ringbuf
->effective_size
-= 2 * CACHELINE_BYTES
;
1905 ret
= i915_cmd_parser_init_ring(ring
);
1913 ring
->buffer
= NULL
;
1917 void intel_cleanup_ring_buffer(struct intel_engine_cs
*ring
)
1919 struct drm_i915_private
*dev_priv
;
1920 struct intel_ringbuffer
*ringbuf
;
1922 if (!intel_ring_initialized(ring
))
1925 dev_priv
= to_i915(ring
->dev
);
1926 ringbuf
= ring
->buffer
;
1928 intel_stop_ring_buffer(ring
);
1929 WARN_ON(!IS_GEN2(ring
->dev
) && (I915_READ_MODE(ring
) & MODE_IDLE
) == 0);
1931 intel_unpin_ringbuffer_obj(ringbuf
);
1932 intel_destroy_ringbuffer_obj(ringbuf
);
1933 i915_gem_request_assign(&ring
->outstanding_lazy_request
, NULL
);
1936 ring
->cleanup(ring
);
1938 cleanup_status_page(ring
);
1940 i915_cmd_parser_fini_ring(ring
);
1943 ring
->buffer
= NULL
;
1946 static int intel_ring_wait_request(struct intel_engine_cs
*ring
, int n
)
1948 struct intel_ringbuffer
*ringbuf
= ring
->buffer
;
1949 struct drm_i915_gem_request
*request
;
1952 if (intel_ring_space(ringbuf
) >= n
)
1955 list_for_each_entry(request
, &ring
->request_list
, list
) {
1956 if (__intel_ring_space(request
->postfix
, ringbuf
->tail
,
1957 ringbuf
->size
) >= n
) {
1962 if (&request
->list
== &ring
->request_list
)
1965 ret
= i915_wait_request(request
);
1969 i915_gem_retire_requests_ring(ring
);
1974 static int ring_wait_for_space(struct intel_engine_cs
*ring
, int n
)
1976 struct drm_device
*dev
= ring
->dev
;
1977 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1978 struct intel_ringbuffer
*ringbuf
= ring
->buffer
;
1982 ret
= intel_ring_wait_request(ring
, n
);
1986 /* force the tail write in case we have been skipping them */
1987 __intel_ring_advance(ring
);
1989 /* With GEM the hangcheck timer should kick us out of the loop,
1990 * leaving it early runs the risk of corrupting GEM state (due
1991 * to running on almost untested codepaths). But on resume
1992 * timers don't work yet, so prevent a complete hang in that
1993 * case by choosing an insanely large timeout. */
1994 end
= jiffies
+ 60 * HZ
;
1997 trace_i915_ring_wait_begin(ring
);
1999 if (intel_ring_space(ringbuf
) >= n
)
2001 ringbuf
->head
= I915_READ_HEAD(ring
);
2002 if (intel_ring_space(ringbuf
) >= n
)
2007 if (dev_priv
->mm
.interruptible
&& signal_pending(current
)) {
2012 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
,
2013 dev_priv
->mm
.interruptible
);
2017 if (time_after(jiffies
, end
)) {
2022 trace_i915_ring_wait_end(ring
);
2026 static int intel_wrap_ring_buffer(struct intel_engine_cs
*ring
)
2028 uint32_t __iomem
*virt
;
2029 struct intel_ringbuffer
*ringbuf
= ring
->buffer
;
2030 int rem
= ringbuf
->size
- ringbuf
->tail
;
2032 if (ringbuf
->space
< rem
) {
2033 int ret
= ring_wait_for_space(ring
, rem
);
2038 virt
= ringbuf
->virtual_start
+ ringbuf
->tail
;
2041 iowrite32(MI_NOOP
, virt
++);
2044 intel_ring_update_space(ringbuf
);
2049 int intel_ring_idle(struct intel_engine_cs
*ring
)
2051 struct drm_i915_gem_request
*req
;
2054 /* We need to add any requests required to flush the objects and ring */
2055 if (ring
->outstanding_lazy_request
) {
2056 ret
= i915_add_request(ring
);
2061 /* Wait upon the last request to be completed */
2062 if (list_empty(&ring
->request_list
))
2065 req
= list_entry(ring
->request_list
.prev
,
2066 struct drm_i915_gem_request
,
2069 return i915_wait_request(req
);
2073 intel_ring_alloc_request(struct intel_engine_cs
*ring
)
2076 struct drm_i915_gem_request
*request
;
2077 struct drm_i915_private
*dev_private
= ring
->dev
->dev_private
;
2079 if (ring
->outstanding_lazy_request
)
2082 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
2083 if (request
== NULL
)
2086 kref_init(&request
->ref
);
2087 request
->ring
= ring
;
2088 request
->uniq
= dev_private
->request_uniq
++;
2090 ret
= i915_gem_get_seqno(ring
->dev
, &request
->seqno
);
2096 ring
->outstanding_lazy_request
= request
;
2100 static int __intel_ring_prepare(struct intel_engine_cs
*ring
,
2103 struct intel_ringbuffer
*ringbuf
= ring
->buffer
;
2106 if (unlikely(ringbuf
->tail
+ bytes
> ringbuf
->effective_size
)) {
2107 ret
= intel_wrap_ring_buffer(ring
);
2112 if (unlikely(ringbuf
->space
< bytes
)) {
2113 ret
= ring_wait_for_space(ring
, bytes
);
2121 int intel_ring_begin(struct intel_engine_cs
*ring
,
2124 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2127 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
,
2128 dev_priv
->mm
.interruptible
);
2132 ret
= __intel_ring_prepare(ring
, num_dwords
* sizeof(uint32_t));
2136 /* Preallocate the olr before touching the ring */
2137 ret
= intel_ring_alloc_request(ring
);
2141 ring
->buffer
->space
-= num_dwords
* sizeof(uint32_t);
2145 /* Align the ring tail to a cacheline boundary */
2146 int intel_ring_cacheline_align(struct intel_engine_cs
*ring
)
2148 int num_dwords
= (ring
->buffer
->tail
& (CACHELINE_BYTES
- 1)) / sizeof(uint32_t);
2151 if (num_dwords
== 0)
2154 num_dwords
= CACHELINE_BYTES
/ sizeof(uint32_t) - num_dwords
;
2155 ret
= intel_ring_begin(ring
, num_dwords
);
2159 while (num_dwords
--)
2160 intel_ring_emit(ring
, MI_NOOP
);
2162 intel_ring_advance(ring
);
2167 void intel_ring_init_seqno(struct intel_engine_cs
*ring
, u32 seqno
)
2169 struct drm_device
*dev
= ring
->dev
;
2170 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2172 BUG_ON(ring
->outstanding_lazy_request
);
2174 if (INTEL_INFO(dev
)->gen
== 6 || INTEL_INFO(dev
)->gen
== 7) {
2175 I915_WRITE(RING_SYNC_0(ring
->mmio_base
), 0);
2176 I915_WRITE(RING_SYNC_1(ring
->mmio_base
), 0);
2178 I915_WRITE(RING_SYNC_2(ring
->mmio_base
), 0);
2181 ring
->set_seqno(ring
, seqno
);
2182 ring
->hangcheck
.seqno
= seqno
;
2185 static void gen6_bsd_ring_write_tail(struct intel_engine_cs
*ring
,
2188 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2190 /* Every tail move must follow the sequence below */
2192 /* Disable notification that the ring is IDLE. The GT
2193 * will then assume that it is busy and bring it out of rc6.
2195 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL
,
2196 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE
));
2198 /* Clear the context id. Here be magic! */
2199 I915_WRITE64(GEN6_BSD_RNCID
, 0x0);
2201 /* Wait for the ring not to be idle, i.e. for it to wake up. */
2202 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL
) &
2203 GEN6_BSD_SLEEP_INDICATOR
) == 0,
2205 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
2207 /* Now that the ring is fully powered up, update the tail */
2208 I915_WRITE_TAIL(ring
, value
);
2209 POSTING_READ(RING_TAIL(ring
->mmio_base
));
2211 /* Let the ring send IDLE messages to the GT again,
2212 * and so let it sleep to conserve power when idle.
2214 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL
,
2215 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE
));
2218 static int gen6_bsd_ring_flush(struct intel_engine_cs
*ring
,
2219 u32 invalidate
, u32 flush
)
2224 ret
= intel_ring_begin(ring
, 4);
2229 if (INTEL_INFO(ring
->dev
)->gen
>= 8)
2232 * Bspec vol 1c.5 - video engine command streamer:
2233 * "If ENABLED, all TLBs will be invalidated once the flush
2234 * operation is complete. This bit is only valid when the
2235 * Post-Sync Operation field is a value of 1h or 3h."
2237 if (invalidate
& I915_GEM_GPU_DOMAINS
)
2238 cmd
|= MI_INVALIDATE_TLB
| MI_INVALIDATE_BSD
|
2239 MI_FLUSH_DW_STORE_INDEX
| MI_FLUSH_DW_OP_STOREDW
;
2240 intel_ring_emit(ring
, cmd
);
2241 intel_ring_emit(ring
, I915_GEM_HWS_SCRATCH_ADDR
| MI_FLUSH_DW_USE_GTT
);
2242 if (INTEL_INFO(ring
->dev
)->gen
>= 8) {
2243 intel_ring_emit(ring
, 0); /* upper addr */
2244 intel_ring_emit(ring
, 0); /* value */
2246 intel_ring_emit(ring
, 0);
2247 intel_ring_emit(ring
, MI_NOOP
);
2249 intel_ring_advance(ring
);
2254 gen8_ring_dispatch_execbuffer(struct intel_engine_cs
*ring
,
2255 u64 offset
, u32 len
,
2258 bool ppgtt
= USES_PPGTT(ring
->dev
) && !(flags
& I915_DISPATCH_SECURE
);
2261 ret
= intel_ring_begin(ring
, 4);
2265 /* FIXME(BDW): Address space and security selectors. */
2266 intel_ring_emit(ring
, MI_BATCH_BUFFER_START_GEN8
| (ppgtt
<<8));
2267 intel_ring_emit(ring
, lower_32_bits(offset
));
2268 intel_ring_emit(ring
, upper_32_bits(offset
));
2269 intel_ring_emit(ring
, MI_NOOP
);
2270 intel_ring_advance(ring
);
2276 hsw_ring_dispatch_execbuffer(struct intel_engine_cs
*ring
,
2277 u64 offset
, u32 len
,
2282 ret
= intel_ring_begin(ring
, 2);
2286 intel_ring_emit(ring
,
2287 MI_BATCH_BUFFER_START
|
2288 (flags
& I915_DISPATCH_SECURE
?
2289 0 : MI_BATCH_PPGTT_HSW
| MI_BATCH_NON_SECURE_HSW
));
2290 /* bit0-7 is the length on GEN6+ */
2291 intel_ring_emit(ring
, offset
);
2292 intel_ring_advance(ring
);
2298 gen6_ring_dispatch_execbuffer(struct intel_engine_cs
*ring
,
2299 u64 offset
, u32 len
,
2304 ret
= intel_ring_begin(ring
, 2);
2308 intel_ring_emit(ring
,
2309 MI_BATCH_BUFFER_START
|
2310 (flags
& I915_DISPATCH_SECURE
? 0 : MI_BATCH_NON_SECURE_I965
));
2311 /* bit0-7 is the length on GEN6+ */
2312 intel_ring_emit(ring
, offset
);
2313 intel_ring_advance(ring
);
2318 /* Blitter support (SandyBridge+) */
2320 static int gen6_ring_flush(struct intel_engine_cs
*ring
,
2321 u32 invalidate
, u32 flush
)
2323 struct drm_device
*dev
= ring
->dev
;
2324 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2328 ret
= intel_ring_begin(ring
, 4);
2333 if (INTEL_INFO(ring
->dev
)->gen
>= 8)
2336 * Bspec vol 1c.3 - blitter engine command streamer:
2337 * "If ENABLED, all TLBs will be invalidated once the flush
2338 * operation is complete. This bit is only valid when the
2339 * Post-Sync Operation field is a value of 1h or 3h."
2341 if (invalidate
& I915_GEM_DOMAIN_RENDER
)
2342 cmd
|= MI_INVALIDATE_TLB
| MI_FLUSH_DW_STORE_INDEX
|
2343 MI_FLUSH_DW_OP_STOREDW
;
2344 intel_ring_emit(ring
, cmd
);
2345 intel_ring_emit(ring
, I915_GEM_HWS_SCRATCH_ADDR
| MI_FLUSH_DW_USE_GTT
);
2346 if (INTEL_INFO(ring
->dev
)->gen
>= 8) {
2347 intel_ring_emit(ring
, 0); /* upper addr */
2348 intel_ring_emit(ring
, 0); /* value */
2350 intel_ring_emit(ring
, 0);
2351 intel_ring_emit(ring
, MI_NOOP
);
2353 intel_ring_advance(ring
);
2355 if (!invalidate
&& flush
) {
2357 return gen7_ring_fbc_flush(ring
, FBC_REND_CACHE_CLEAN
);
2358 else if (IS_BROADWELL(dev
))
2359 dev_priv
->fbc
.need_sw_cache_clean
= true;
2365 int intel_init_render_ring_buffer(struct drm_device
*dev
)
2367 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2368 struct intel_engine_cs
*ring
= &dev_priv
->ring
[RCS
];
2369 struct drm_i915_gem_object
*obj
;
2372 ring
->name
= "render ring";
2374 ring
->mmio_base
= RENDER_RING_BASE
;
2376 if (INTEL_INFO(dev
)->gen
>= 8) {
2377 if (i915_semaphore_is_enabled(dev
)) {
2378 obj
= i915_gem_alloc_object(dev
, 4096);
2380 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2381 i915
.semaphores
= 0;
2383 i915_gem_object_set_cache_level(obj
, I915_CACHE_LLC
);
2384 ret
= i915_gem_obj_ggtt_pin(obj
, 0, PIN_NONBLOCK
);
2386 drm_gem_object_unreference(&obj
->base
);
2387 DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2388 i915
.semaphores
= 0;
2390 dev_priv
->semaphore_obj
= obj
;
2394 ring
->init_context
= intel_rcs_ctx_init
;
2395 ring
->add_request
= gen6_add_request
;
2396 ring
->flush
= gen8_render_ring_flush
;
2397 ring
->irq_get
= gen8_ring_get_irq
;
2398 ring
->irq_put
= gen8_ring_put_irq
;
2399 ring
->irq_enable_mask
= GT_RENDER_USER_INTERRUPT
;
2400 ring
->get_seqno
= gen6_ring_get_seqno
;
2401 ring
->set_seqno
= ring_set_seqno
;
2402 if (i915_semaphore_is_enabled(dev
)) {
2403 WARN_ON(!dev_priv
->semaphore_obj
);
2404 ring
->semaphore
.sync_to
= gen8_ring_sync
;
2405 ring
->semaphore
.signal
= gen8_rcs_signal
;
2406 GEN8_RING_SEMAPHORE_INIT
;
2408 } else if (INTEL_INFO(dev
)->gen
>= 6) {
2409 ring
->add_request
= gen6_add_request
;
2410 ring
->flush
= gen7_render_ring_flush
;
2411 if (INTEL_INFO(dev
)->gen
== 6)
2412 ring
->flush
= gen6_render_ring_flush
;
2413 ring
->irq_get
= gen6_ring_get_irq
;
2414 ring
->irq_put
= gen6_ring_put_irq
;
2415 ring
->irq_enable_mask
= GT_RENDER_USER_INTERRUPT
;
2416 ring
->get_seqno
= gen6_ring_get_seqno
;
2417 ring
->set_seqno
= ring_set_seqno
;
2418 if (i915_semaphore_is_enabled(dev
)) {
2419 ring
->semaphore
.sync_to
= gen6_ring_sync
;
2420 ring
->semaphore
.signal
= gen6_signal
;
2422 * The current semaphore is only applied on pre-gen8
2423 * platform. And there is no VCS2 ring on the pre-gen8
2424 * platform. So the semaphore between RCS and VCS2 is
2425 * initialized as INVALID. Gen8 will initialize the
2426 * sema between VCS2 and RCS later.
2428 ring
->semaphore
.mbox
.wait
[RCS
] = MI_SEMAPHORE_SYNC_INVALID
;
2429 ring
->semaphore
.mbox
.wait
[VCS
] = MI_SEMAPHORE_SYNC_RV
;
2430 ring
->semaphore
.mbox
.wait
[BCS
] = MI_SEMAPHORE_SYNC_RB
;
2431 ring
->semaphore
.mbox
.wait
[VECS
] = MI_SEMAPHORE_SYNC_RVE
;
2432 ring
->semaphore
.mbox
.wait
[VCS2
] = MI_SEMAPHORE_SYNC_INVALID
;
2433 ring
->semaphore
.mbox
.signal
[RCS
] = GEN6_NOSYNC
;
2434 ring
->semaphore
.mbox
.signal
[VCS
] = GEN6_VRSYNC
;
2435 ring
->semaphore
.mbox
.signal
[BCS
] = GEN6_BRSYNC
;
2436 ring
->semaphore
.mbox
.signal
[VECS
] = GEN6_VERSYNC
;
2437 ring
->semaphore
.mbox
.signal
[VCS2
] = GEN6_NOSYNC
;
2439 } else if (IS_GEN5(dev
)) {
2440 ring
->add_request
= pc_render_add_request
;
2441 ring
->flush
= gen4_render_ring_flush
;
2442 ring
->get_seqno
= pc_render_get_seqno
;
2443 ring
->set_seqno
= pc_render_set_seqno
;
2444 ring
->irq_get
= gen5_ring_get_irq
;
2445 ring
->irq_put
= gen5_ring_put_irq
;
2446 ring
->irq_enable_mask
= GT_RENDER_USER_INTERRUPT
|
2447 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
;
2449 ring
->add_request
= i9xx_add_request
;
2450 if (INTEL_INFO(dev
)->gen
< 4)
2451 ring
->flush
= gen2_render_ring_flush
;
2453 ring
->flush
= gen4_render_ring_flush
;
2454 ring
->get_seqno
= ring_get_seqno
;
2455 ring
->set_seqno
= ring_set_seqno
;
2457 ring
->irq_get
= i8xx_ring_get_irq
;
2458 ring
->irq_put
= i8xx_ring_put_irq
;
2460 ring
->irq_get
= i9xx_ring_get_irq
;
2461 ring
->irq_put
= i9xx_ring_put_irq
;
2463 ring
->irq_enable_mask
= I915_USER_INTERRUPT
;
2465 ring
->write_tail
= ring_write_tail
;
2467 if (IS_HASWELL(dev
))
2468 ring
->dispatch_execbuffer
= hsw_ring_dispatch_execbuffer
;
2469 else if (IS_GEN8(dev
))
2470 ring
->dispatch_execbuffer
= gen8_ring_dispatch_execbuffer
;
2471 else if (INTEL_INFO(dev
)->gen
>= 6)
2472 ring
->dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
;
2473 else if (INTEL_INFO(dev
)->gen
>= 4)
2474 ring
->dispatch_execbuffer
= i965_dispatch_execbuffer
;
2475 else if (IS_I830(dev
) || IS_845G(dev
))
2476 ring
->dispatch_execbuffer
= i830_dispatch_execbuffer
;
2478 ring
->dispatch_execbuffer
= i915_dispatch_execbuffer
;
2479 ring
->init_hw
= init_render_ring
;
2480 ring
->cleanup
= render_ring_cleanup
;
2482 /* Workaround batchbuffer to combat CS tlb bug. */
2483 if (HAS_BROKEN_CS_TLB(dev
)) {
2484 obj
= i915_gem_alloc_object(dev
, I830_WA_SIZE
);
2486 DRM_ERROR("Failed to allocate batch bo\n");
2490 ret
= i915_gem_obj_ggtt_pin(obj
, 0, 0);
2492 drm_gem_object_unreference(&obj
->base
);
2493 DRM_ERROR("Failed to ping batch bo\n");
2497 ring
->scratch
.obj
= obj
;
2498 ring
->scratch
.gtt_offset
= i915_gem_obj_ggtt_offset(obj
);
2501 ret
= intel_init_ring_buffer(dev
, ring
);
2505 if (INTEL_INFO(dev
)->gen
>= 5) {
2506 ret
= intel_init_pipe_control(ring
);
2514 int intel_init_bsd_ring_buffer(struct drm_device
*dev
)
2516 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2517 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VCS
];
2519 ring
->name
= "bsd ring";
2522 ring
->write_tail
= ring_write_tail
;
2523 if (INTEL_INFO(dev
)->gen
>= 6) {
2524 ring
->mmio_base
= GEN6_BSD_RING_BASE
;
2525 /* gen6 bsd needs a special wa for tail updates */
2527 ring
->write_tail
= gen6_bsd_ring_write_tail
;
2528 ring
->flush
= gen6_bsd_ring_flush
;
2529 ring
->add_request
= gen6_add_request
;
2530 ring
->get_seqno
= gen6_ring_get_seqno
;
2531 ring
->set_seqno
= ring_set_seqno
;
2532 if (INTEL_INFO(dev
)->gen
>= 8) {
2533 ring
->irq_enable_mask
=
2534 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
;
2535 ring
->irq_get
= gen8_ring_get_irq
;
2536 ring
->irq_put
= gen8_ring_put_irq
;
2537 ring
->dispatch_execbuffer
=
2538 gen8_ring_dispatch_execbuffer
;
2539 if (i915_semaphore_is_enabled(dev
)) {
2540 ring
->semaphore
.sync_to
= gen8_ring_sync
;
2541 ring
->semaphore
.signal
= gen8_xcs_signal
;
2542 GEN8_RING_SEMAPHORE_INIT
;
2545 ring
->irq_enable_mask
= GT_BSD_USER_INTERRUPT
;
2546 ring
->irq_get
= gen6_ring_get_irq
;
2547 ring
->irq_put
= gen6_ring_put_irq
;
2548 ring
->dispatch_execbuffer
=
2549 gen6_ring_dispatch_execbuffer
;
2550 if (i915_semaphore_is_enabled(dev
)) {
2551 ring
->semaphore
.sync_to
= gen6_ring_sync
;
2552 ring
->semaphore
.signal
= gen6_signal
;
2553 ring
->semaphore
.mbox
.wait
[RCS
] = MI_SEMAPHORE_SYNC_VR
;
2554 ring
->semaphore
.mbox
.wait
[VCS
] = MI_SEMAPHORE_SYNC_INVALID
;
2555 ring
->semaphore
.mbox
.wait
[BCS
] = MI_SEMAPHORE_SYNC_VB
;
2556 ring
->semaphore
.mbox
.wait
[VECS
] = MI_SEMAPHORE_SYNC_VVE
;
2557 ring
->semaphore
.mbox
.wait
[VCS2
] = MI_SEMAPHORE_SYNC_INVALID
;
2558 ring
->semaphore
.mbox
.signal
[RCS
] = GEN6_RVSYNC
;
2559 ring
->semaphore
.mbox
.signal
[VCS
] = GEN6_NOSYNC
;
2560 ring
->semaphore
.mbox
.signal
[BCS
] = GEN6_BVSYNC
;
2561 ring
->semaphore
.mbox
.signal
[VECS
] = GEN6_VEVSYNC
;
2562 ring
->semaphore
.mbox
.signal
[VCS2
] = GEN6_NOSYNC
;
2566 ring
->mmio_base
= BSD_RING_BASE
;
2567 ring
->flush
= bsd_ring_flush
;
2568 ring
->add_request
= i9xx_add_request
;
2569 ring
->get_seqno
= ring_get_seqno
;
2570 ring
->set_seqno
= ring_set_seqno
;
2572 ring
->irq_enable_mask
= ILK_BSD_USER_INTERRUPT
;
2573 ring
->irq_get
= gen5_ring_get_irq
;
2574 ring
->irq_put
= gen5_ring_put_irq
;
2576 ring
->irq_enable_mask
= I915_BSD_USER_INTERRUPT
;
2577 ring
->irq_get
= i9xx_ring_get_irq
;
2578 ring
->irq_put
= i9xx_ring_put_irq
;
2580 ring
->dispatch_execbuffer
= i965_dispatch_execbuffer
;
2582 ring
->init_hw
= init_ring_common
;
2584 return intel_init_ring_buffer(dev
, ring
);
2588 * Initialize the second BSD ring for Broadwell GT3.
2589 * It is noted that this only exists on Broadwell GT3.
2591 int intel_init_bsd2_ring_buffer(struct drm_device
*dev
)
2593 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2594 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VCS2
];
2596 if ((INTEL_INFO(dev
)->gen
!= 8)) {
2597 DRM_ERROR("No dual-BSD ring on non-BDW machine\n");
2601 ring
->name
= "bsd2 ring";
2604 ring
->write_tail
= ring_write_tail
;
2605 ring
->mmio_base
= GEN8_BSD2_RING_BASE
;
2606 ring
->flush
= gen6_bsd_ring_flush
;
2607 ring
->add_request
= gen6_add_request
;
2608 ring
->get_seqno
= gen6_ring_get_seqno
;
2609 ring
->set_seqno
= ring_set_seqno
;
2610 ring
->irq_enable_mask
=
2611 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS2_IRQ_SHIFT
;
2612 ring
->irq_get
= gen8_ring_get_irq
;
2613 ring
->irq_put
= gen8_ring_put_irq
;
2614 ring
->dispatch_execbuffer
=
2615 gen8_ring_dispatch_execbuffer
;
2616 if (i915_semaphore_is_enabled(dev
)) {
2617 ring
->semaphore
.sync_to
= gen8_ring_sync
;
2618 ring
->semaphore
.signal
= gen8_xcs_signal
;
2619 GEN8_RING_SEMAPHORE_INIT
;
2621 ring
->init_hw
= init_ring_common
;
2623 return intel_init_ring_buffer(dev
, ring
);
2626 int intel_init_blt_ring_buffer(struct drm_device
*dev
)
2628 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2629 struct intel_engine_cs
*ring
= &dev_priv
->ring
[BCS
];
2631 ring
->name
= "blitter ring";
2634 ring
->mmio_base
= BLT_RING_BASE
;
2635 ring
->write_tail
= ring_write_tail
;
2636 ring
->flush
= gen6_ring_flush
;
2637 ring
->add_request
= gen6_add_request
;
2638 ring
->get_seqno
= gen6_ring_get_seqno
;
2639 ring
->set_seqno
= ring_set_seqno
;
2640 if (INTEL_INFO(dev
)->gen
>= 8) {
2641 ring
->irq_enable_mask
=
2642 GT_RENDER_USER_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
;
2643 ring
->irq_get
= gen8_ring_get_irq
;
2644 ring
->irq_put
= gen8_ring_put_irq
;
2645 ring
->dispatch_execbuffer
= gen8_ring_dispatch_execbuffer
;
2646 if (i915_semaphore_is_enabled(dev
)) {
2647 ring
->semaphore
.sync_to
= gen8_ring_sync
;
2648 ring
->semaphore
.signal
= gen8_xcs_signal
;
2649 GEN8_RING_SEMAPHORE_INIT
;
2652 ring
->irq_enable_mask
= GT_BLT_USER_INTERRUPT
;
2653 ring
->irq_get
= gen6_ring_get_irq
;
2654 ring
->irq_put
= gen6_ring_put_irq
;
2655 ring
->dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
;
2656 if (i915_semaphore_is_enabled(dev
)) {
2657 ring
->semaphore
.signal
= gen6_signal
;
2658 ring
->semaphore
.sync_to
= gen6_ring_sync
;
2660 * The current semaphore is only applied on pre-gen8
2661 * platform. And there is no VCS2 ring on the pre-gen8
2662 * platform. So the semaphore between BCS and VCS2 is
2663 * initialized as INVALID. Gen8 will initialize the
2664 * sema between BCS and VCS2 later.
2666 ring
->semaphore
.mbox
.wait
[RCS
] = MI_SEMAPHORE_SYNC_BR
;
2667 ring
->semaphore
.mbox
.wait
[VCS
] = MI_SEMAPHORE_SYNC_BV
;
2668 ring
->semaphore
.mbox
.wait
[BCS
] = MI_SEMAPHORE_SYNC_INVALID
;
2669 ring
->semaphore
.mbox
.wait
[VECS
] = MI_SEMAPHORE_SYNC_BVE
;
2670 ring
->semaphore
.mbox
.wait
[VCS2
] = MI_SEMAPHORE_SYNC_INVALID
;
2671 ring
->semaphore
.mbox
.signal
[RCS
] = GEN6_RBSYNC
;
2672 ring
->semaphore
.mbox
.signal
[VCS
] = GEN6_VBSYNC
;
2673 ring
->semaphore
.mbox
.signal
[BCS
] = GEN6_NOSYNC
;
2674 ring
->semaphore
.mbox
.signal
[VECS
] = GEN6_VEBSYNC
;
2675 ring
->semaphore
.mbox
.signal
[VCS2
] = GEN6_NOSYNC
;
2678 ring
->init_hw
= init_ring_common
;
2680 return intel_init_ring_buffer(dev
, ring
);
2683 int intel_init_vebox_ring_buffer(struct drm_device
*dev
)
2685 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2686 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VECS
];
2688 ring
->name
= "video enhancement ring";
2691 ring
->mmio_base
= VEBOX_RING_BASE
;
2692 ring
->write_tail
= ring_write_tail
;
2693 ring
->flush
= gen6_ring_flush
;
2694 ring
->add_request
= gen6_add_request
;
2695 ring
->get_seqno
= gen6_ring_get_seqno
;
2696 ring
->set_seqno
= ring_set_seqno
;
2698 if (INTEL_INFO(dev
)->gen
>= 8) {
2699 ring
->irq_enable_mask
=
2700 GT_RENDER_USER_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
;
2701 ring
->irq_get
= gen8_ring_get_irq
;
2702 ring
->irq_put
= gen8_ring_put_irq
;
2703 ring
->dispatch_execbuffer
= gen8_ring_dispatch_execbuffer
;
2704 if (i915_semaphore_is_enabled(dev
)) {
2705 ring
->semaphore
.sync_to
= gen8_ring_sync
;
2706 ring
->semaphore
.signal
= gen8_xcs_signal
;
2707 GEN8_RING_SEMAPHORE_INIT
;
2710 ring
->irq_enable_mask
= PM_VEBOX_USER_INTERRUPT
;
2711 ring
->irq_get
= hsw_vebox_get_irq
;
2712 ring
->irq_put
= hsw_vebox_put_irq
;
2713 ring
->dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
;
2714 if (i915_semaphore_is_enabled(dev
)) {
2715 ring
->semaphore
.sync_to
= gen6_ring_sync
;
2716 ring
->semaphore
.signal
= gen6_signal
;
2717 ring
->semaphore
.mbox
.wait
[RCS
] = MI_SEMAPHORE_SYNC_VER
;
2718 ring
->semaphore
.mbox
.wait
[VCS
] = MI_SEMAPHORE_SYNC_VEV
;
2719 ring
->semaphore
.mbox
.wait
[BCS
] = MI_SEMAPHORE_SYNC_VEB
;
2720 ring
->semaphore
.mbox
.wait
[VECS
] = MI_SEMAPHORE_SYNC_INVALID
;
2721 ring
->semaphore
.mbox
.wait
[VCS2
] = MI_SEMAPHORE_SYNC_INVALID
;
2722 ring
->semaphore
.mbox
.signal
[RCS
] = GEN6_RVESYNC
;
2723 ring
->semaphore
.mbox
.signal
[VCS
] = GEN6_VVESYNC
;
2724 ring
->semaphore
.mbox
.signal
[BCS
] = GEN6_BVESYNC
;
2725 ring
->semaphore
.mbox
.signal
[VECS
] = GEN6_NOSYNC
;
2726 ring
->semaphore
.mbox
.signal
[VCS2
] = GEN6_NOSYNC
;
2729 ring
->init_hw
= init_ring_common
;
2731 return intel_init_ring_buffer(dev
, ring
);
2735 intel_ring_flush_all_caches(struct intel_engine_cs
*ring
)
2739 if (!ring
->gpu_caches_dirty
)
2742 ret
= ring
->flush(ring
, 0, I915_GEM_GPU_DOMAINS
);
2746 trace_i915_gem_ring_flush(ring
, 0, I915_GEM_GPU_DOMAINS
);
2748 ring
->gpu_caches_dirty
= false;
2753 intel_ring_invalidate_all_caches(struct intel_engine_cs
*ring
)
2755 uint32_t flush_domains
;
2759 if (ring
->gpu_caches_dirty
)
2760 flush_domains
= I915_GEM_GPU_DOMAINS
;
2762 ret
= ring
->flush(ring
, I915_GEM_GPU_DOMAINS
, flush_domains
);
2766 trace_i915_gem_ring_flush(ring
, I915_GEM_GPU_DOMAINS
, flush_domains
);
2768 ring
->gpu_caches_dirty
= false;
2773 intel_stop_ring_buffer(struct intel_engine_cs
*ring
)
2777 if (!intel_ring_initialized(ring
))
2780 ret
= intel_ring_idle(ring
);
2781 if (ret
&& !i915_reset_in_progress(&to_i915(ring
->dev
)->gpu_error
))
2782 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",