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drm/i915/gen8: Add gen8_init_workarounds for common WA
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c
1 /*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
30 #include <drm/drmP.h>
31 #include "i915_drv.h"
32 #include <drm/i915_drm.h>
33 #include "i915_trace.h"
34 #include "intel_drv.h"
35
36 bool
37 intel_ring_initialized(struct intel_engine_cs *ring)
38 {
39 struct drm_device *dev = ring->dev;
40
41 if (!dev)
42 return false;
43
44 if (i915.enable_execlists) {
45 struct intel_context *dctx = ring->default_context;
46 struct intel_ringbuffer *ringbuf = dctx->engine[ring->id].ringbuf;
47
48 return ringbuf->obj;
49 } else
50 return ring->buffer && ring->buffer->obj;
51 }
52
53 int __intel_ring_space(int head, int tail, int size)
54 {
55 int space = head - tail;
56 if (space <= 0)
57 space += size;
58 return space - I915_RING_FREE_SPACE;
59 }
60
61 void intel_ring_update_space(struct intel_ringbuffer *ringbuf)
62 {
63 if (ringbuf->last_retired_head != -1) {
64 ringbuf->head = ringbuf->last_retired_head;
65 ringbuf->last_retired_head = -1;
66 }
67
68 ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR,
69 ringbuf->tail, ringbuf->size);
70 }
71
72 int intel_ring_space(struct intel_ringbuffer *ringbuf)
73 {
74 intel_ring_update_space(ringbuf);
75 return ringbuf->space;
76 }
77
78 bool intel_ring_stopped(struct intel_engine_cs *ring)
79 {
80 struct drm_i915_private *dev_priv = ring->dev->dev_private;
81 return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring);
82 }
83
84 static void __intel_ring_advance(struct intel_engine_cs *ring)
85 {
86 struct intel_ringbuffer *ringbuf = ring->buffer;
87 ringbuf->tail &= ringbuf->size - 1;
88 if (intel_ring_stopped(ring))
89 return;
90 ring->write_tail(ring, ringbuf->tail);
91 }
92
93 static int
94 gen2_render_ring_flush(struct drm_i915_gem_request *req,
95 u32 invalidate_domains,
96 u32 flush_domains)
97 {
98 struct intel_engine_cs *ring = req->ring;
99 u32 cmd;
100 int ret;
101
102 cmd = MI_FLUSH;
103 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
104 cmd |= MI_NO_WRITE_FLUSH;
105
106 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
107 cmd |= MI_READ_FLUSH;
108
109 ret = intel_ring_begin(req, 2);
110 if (ret)
111 return ret;
112
113 intel_ring_emit(ring, cmd);
114 intel_ring_emit(ring, MI_NOOP);
115 intel_ring_advance(ring);
116
117 return 0;
118 }
119
120 static int
121 gen4_render_ring_flush(struct drm_i915_gem_request *req,
122 u32 invalidate_domains,
123 u32 flush_domains)
124 {
125 struct intel_engine_cs *ring = req->ring;
126 struct drm_device *dev = ring->dev;
127 u32 cmd;
128 int ret;
129
130 /*
131 * read/write caches:
132 *
133 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
134 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
135 * also flushed at 2d versus 3d pipeline switches.
136 *
137 * read-only caches:
138 *
139 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
140 * MI_READ_FLUSH is set, and is always flushed on 965.
141 *
142 * I915_GEM_DOMAIN_COMMAND may not exist?
143 *
144 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
145 * invalidated when MI_EXE_FLUSH is set.
146 *
147 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
148 * invalidated with every MI_FLUSH.
149 *
150 * TLBs:
151 *
152 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
153 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
154 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
155 * are flushed at any MI_FLUSH.
156 */
157
158 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
159 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
160 cmd &= ~MI_NO_WRITE_FLUSH;
161 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
162 cmd |= MI_EXE_FLUSH;
163
164 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
165 (IS_G4X(dev) || IS_GEN5(dev)))
166 cmd |= MI_INVALIDATE_ISP;
167
168 ret = intel_ring_begin(req, 2);
169 if (ret)
170 return ret;
171
172 intel_ring_emit(ring, cmd);
173 intel_ring_emit(ring, MI_NOOP);
174 intel_ring_advance(ring);
175
176 return 0;
177 }
178
179 /**
180 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
181 * implementing two workarounds on gen6. From section 1.4.7.1
182 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
183 *
184 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
185 * produced by non-pipelined state commands), software needs to first
186 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
187 * 0.
188 *
189 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
190 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
191 *
192 * And the workaround for these two requires this workaround first:
193 *
194 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
195 * BEFORE the pipe-control with a post-sync op and no write-cache
196 * flushes.
197 *
198 * And this last workaround is tricky because of the requirements on
199 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
200 * volume 2 part 1:
201 *
202 * "1 of the following must also be set:
203 * - Render Target Cache Flush Enable ([12] of DW1)
204 * - Depth Cache Flush Enable ([0] of DW1)
205 * - Stall at Pixel Scoreboard ([1] of DW1)
206 * - Depth Stall ([13] of DW1)
207 * - Post-Sync Operation ([13] of DW1)
208 * - Notify Enable ([8] of DW1)"
209 *
210 * The cache flushes require the workaround flush that triggered this
211 * one, so we can't use it. Depth stall would trigger the same.
212 * Post-sync nonzero is what triggered this second workaround, so we
213 * can't use that one either. Notify enable is IRQs, which aren't
214 * really our business. That leaves only stall at scoreboard.
215 */
216 static int
217 intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req)
218 {
219 struct intel_engine_cs *ring = req->ring;
220 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
221 int ret;
222
223 ret = intel_ring_begin(req, 6);
224 if (ret)
225 return ret;
226
227 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
228 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
229 PIPE_CONTROL_STALL_AT_SCOREBOARD);
230 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
231 intel_ring_emit(ring, 0); /* low dword */
232 intel_ring_emit(ring, 0); /* high dword */
233 intel_ring_emit(ring, MI_NOOP);
234 intel_ring_advance(ring);
235
236 ret = intel_ring_begin(req, 6);
237 if (ret)
238 return ret;
239
240 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
241 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
242 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
243 intel_ring_emit(ring, 0);
244 intel_ring_emit(ring, 0);
245 intel_ring_emit(ring, MI_NOOP);
246 intel_ring_advance(ring);
247
248 return 0;
249 }
250
251 static int
252 gen6_render_ring_flush(struct drm_i915_gem_request *req,
253 u32 invalidate_domains, u32 flush_domains)
254 {
255 struct intel_engine_cs *ring = req->ring;
256 u32 flags = 0;
257 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
258 int ret;
259
260 /* Force SNB workarounds for PIPE_CONTROL flushes */
261 ret = intel_emit_post_sync_nonzero_flush(req);
262 if (ret)
263 return ret;
264
265 /* Just flush everything. Experiments have shown that reducing the
266 * number of bits based on the write domains has little performance
267 * impact.
268 */
269 if (flush_domains) {
270 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
271 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
272 /*
273 * Ensure that any following seqno writes only happen
274 * when the render cache is indeed flushed.
275 */
276 flags |= PIPE_CONTROL_CS_STALL;
277 }
278 if (invalidate_domains) {
279 flags |= PIPE_CONTROL_TLB_INVALIDATE;
280 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
281 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
282 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
283 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
284 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
285 /*
286 * TLB invalidate requires a post-sync write.
287 */
288 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
289 }
290
291 ret = intel_ring_begin(req, 4);
292 if (ret)
293 return ret;
294
295 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
296 intel_ring_emit(ring, flags);
297 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
298 intel_ring_emit(ring, 0);
299 intel_ring_advance(ring);
300
301 return 0;
302 }
303
304 static int
305 gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req)
306 {
307 struct intel_engine_cs *ring = req->ring;
308 int ret;
309
310 ret = intel_ring_begin(req, 4);
311 if (ret)
312 return ret;
313
314 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
315 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
316 PIPE_CONTROL_STALL_AT_SCOREBOARD);
317 intel_ring_emit(ring, 0);
318 intel_ring_emit(ring, 0);
319 intel_ring_advance(ring);
320
321 return 0;
322 }
323
324 static int
325 gen7_render_ring_flush(struct drm_i915_gem_request *req,
326 u32 invalidate_domains, u32 flush_domains)
327 {
328 struct intel_engine_cs *ring = req->ring;
329 u32 flags = 0;
330 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
331 int ret;
332
333 /*
334 * Ensure that any following seqno writes only happen when the render
335 * cache is indeed flushed.
336 *
337 * Workaround: 4th PIPE_CONTROL command (except the ones with only
338 * read-cache invalidate bits set) must have the CS_STALL bit set. We
339 * don't try to be clever and just set it unconditionally.
340 */
341 flags |= PIPE_CONTROL_CS_STALL;
342
343 /* Just flush everything. Experiments have shown that reducing the
344 * number of bits based on the write domains has little performance
345 * impact.
346 */
347 if (flush_domains) {
348 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
349 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
350 }
351 if (invalidate_domains) {
352 flags |= PIPE_CONTROL_TLB_INVALIDATE;
353 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
354 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
355 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
356 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
357 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
358 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
359 /*
360 * TLB invalidate requires a post-sync write.
361 */
362 flags |= PIPE_CONTROL_QW_WRITE;
363 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
364
365 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
366
367 /* Workaround: we must issue a pipe_control with CS-stall bit
368 * set before a pipe_control command that has the state cache
369 * invalidate bit set. */
370 gen7_render_ring_cs_stall_wa(req);
371 }
372
373 ret = intel_ring_begin(req, 4);
374 if (ret)
375 return ret;
376
377 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
378 intel_ring_emit(ring, flags);
379 intel_ring_emit(ring, scratch_addr);
380 intel_ring_emit(ring, 0);
381 intel_ring_advance(ring);
382
383 return 0;
384 }
385
386 static int
387 gen8_emit_pipe_control(struct drm_i915_gem_request *req,
388 u32 flags, u32 scratch_addr)
389 {
390 struct intel_engine_cs *ring = req->ring;
391 int ret;
392
393 ret = intel_ring_begin(req, 6);
394 if (ret)
395 return ret;
396
397 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
398 intel_ring_emit(ring, flags);
399 intel_ring_emit(ring, scratch_addr);
400 intel_ring_emit(ring, 0);
401 intel_ring_emit(ring, 0);
402 intel_ring_emit(ring, 0);
403 intel_ring_advance(ring);
404
405 return 0;
406 }
407
408 static int
409 gen8_render_ring_flush(struct drm_i915_gem_request *req,
410 u32 invalidate_domains, u32 flush_domains)
411 {
412 u32 flags = 0;
413 u32 scratch_addr = req->ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
414 int ret;
415
416 flags |= PIPE_CONTROL_CS_STALL;
417
418 if (flush_domains) {
419 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
420 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
421 }
422 if (invalidate_domains) {
423 flags |= PIPE_CONTROL_TLB_INVALIDATE;
424 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
425 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
426 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
427 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
428 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
429 flags |= PIPE_CONTROL_QW_WRITE;
430 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
431
432 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
433 ret = gen8_emit_pipe_control(req,
434 PIPE_CONTROL_CS_STALL |
435 PIPE_CONTROL_STALL_AT_SCOREBOARD,
436 0);
437 if (ret)
438 return ret;
439 }
440
441 return gen8_emit_pipe_control(req, flags, scratch_addr);
442 }
443
444 static void ring_write_tail(struct intel_engine_cs *ring,
445 u32 value)
446 {
447 struct drm_i915_private *dev_priv = ring->dev->dev_private;
448 I915_WRITE_TAIL(ring, value);
449 }
450
451 u64 intel_ring_get_active_head(struct intel_engine_cs *ring)
452 {
453 struct drm_i915_private *dev_priv = ring->dev->dev_private;
454 u64 acthd;
455
456 if (INTEL_INFO(ring->dev)->gen >= 8)
457 acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base),
458 RING_ACTHD_UDW(ring->mmio_base));
459 else if (INTEL_INFO(ring->dev)->gen >= 4)
460 acthd = I915_READ(RING_ACTHD(ring->mmio_base));
461 else
462 acthd = I915_READ(ACTHD);
463
464 return acthd;
465 }
466
467 static void ring_setup_phys_status_page(struct intel_engine_cs *ring)
468 {
469 struct drm_i915_private *dev_priv = ring->dev->dev_private;
470 u32 addr;
471
472 addr = dev_priv->status_page_dmah->busaddr;
473 if (INTEL_INFO(ring->dev)->gen >= 4)
474 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
475 I915_WRITE(HWS_PGA, addr);
476 }
477
478 static void intel_ring_setup_status_page(struct intel_engine_cs *ring)
479 {
480 struct drm_device *dev = ring->dev;
481 struct drm_i915_private *dev_priv = ring->dev->dev_private;
482 u32 mmio = 0;
483
484 /* The ring status page addresses are no longer next to the rest of
485 * the ring registers as of gen7.
486 */
487 if (IS_GEN7(dev)) {
488 switch (ring->id) {
489 case RCS:
490 mmio = RENDER_HWS_PGA_GEN7;
491 break;
492 case BCS:
493 mmio = BLT_HWS_PGA_GEN7;
494 break;
495 /*
496 * VCS2 actually doesn't exist on Gen7. Only shut up
497 * gcc switch check warning
498 */
499 case VCS2:
500 case VCS:
501 mmio = BSD_HWS_PGA_GEN7;
502 break;
503 case VECS:
504 mmio = VEBOX_HWS_PGA_GEN7;
505 break;
506 }
507 } else if (IS_GEN6(ring->dev)) {
508 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
509 } else {
510 /* XXX: gen8 returns to sanity */
511 mmio = RING_HWS_PGA(ring->mmio_base);
512 }
513
514 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
515 POSTING_READ(mmio);
516
517 /*
518 * Flush the TLB for this page
519 *
520 * FIXME: These two bits have disappeared on gen8, so a question
521 * arises: do we still need this and if so how should we go about
522 * invalidating the TLB?
523 */
524 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
525 u32 reg = RING_INSTPM(ring->mmio_base);
526
527 /* ring should be idle before issuing a sync flush*/
528 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
529
530 I915_WRITE(reg,
531 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
532 INSTPM_SYNC_FLUSH));
533 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
534 1000))
535 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
536 ring->name);
537 }
538 }
539
540 static bool stop_ring(struct intel_engine_cs *ring)
541 {
542 struct drm_i915_private *dev_priv = to_i915(ring->dev);
543
544 if (!IS_GEN2(ring->dev)) {
545 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
546 if (wait_for((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
547 DRM_ERROR("%s : timed out trying to stop ring\n", ring->name);
548 /* Sometimes we observe that the idle flag is not
549 * set even though the ring is empty. So double
550 * check before giving up.
551 */
552 if (I915_READ_HEAD(ring) != I915_READ_TAIL(ring))
553 return false;
554 }
555 }
556
557 I915_WRITE_CTL(ring, 0);
558 I915_WRITE_HEAD(ring, 0);
559 ring->write_tail(ring, 0);
560
561 if (!IS_GEN2(ring->dev)) {
562 (void)I915_READ_CTL(ring);
563 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
564 }
565
566 return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0;
567 }
568
569 static int init_ring_common(struct intel_engine_cs *ring)
570 {
571 struct drm_device *dev = ring->dev;
572 struct drm_i915_private *dev_priv = dev->dev_private;
573 struct intel_ringbuffer *ringbuf = ring->buffer;
574 struct drm_i915_gem_object *obj = ringbuf->obj;
575 int ret = 0;
576
577 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
578
579 if (!stop_ring(ring)) {
580 /* G45 ring initialization often fails to reset head to zero */
581 DRM_DEBUG_KMS("%s head not reset to zero "
582 "ctl %08x head %08x tail %08x start %08x\n",
583 ring->name,
584 I915_READ_CTL(ring),
585 I915_READ_HEAD(ring),
586 I915_READ_TAIL(ring),
587 I915_READ_START(ring));
588
589 if (!stop_ring(ring)) {
590 DRM_ERROR("failed to set %s head to zero "
591 "ctl %08x head %08x tail %08x start %08x\n",
592 ring->name,
593 I915_READ_CTL(ring),
594 I915_READ_HEAD(ring),
595 I915_READ_TAIL(ring),
596 I915_READ_START(ring));
597 ret = -EIO;
598 goto out;
599 }
600 }
601
602 if (I915_NEED_GFX_HWS(dev))
603 intel_ring_setup_status_page(ring);
604 else
605 ring_setup_phys_status_page(ring);
606
607 /* Enforce ordering by reading HEAD register back */
608 I915_READ_HEAD(ring);
609
610 /* Initialize the ring. This must happen _after_ we've cleared the ring
611 * registers with the above sequence (the readback of the HEAD registers
612 * also enforces ordering), otherwise the hw might lose the new ring
613 * register values. */
614 I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
615
616 /* WaClearRingBufHeadRegAtInit:ctg,elk */
617 if (I915_READ_HEAD(ring))
618 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
619 ring->name, I915_READ_HEAD(ring));
620 I915_WRITE_HEAD(ring, 0);
621 (void)I915_READ_HEAD(ring);
622
623 I915_WRITE_CTL(ring,
624 ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
625 | RING_VALID);
626
627 /* If the head is still not zero, the ring is dead */
628 if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
629 I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) &&
630 (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
631 DRM_ERROR("%s initialization failed "
632 "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
633 ring->name,
634 I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID,
635 I915_READ_HEAD(ring), I915_READ_TAIL(ring),
636 I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj));
637 ret = -EIO;
638 goto out;
639 }
640
641 ringbuf->last_retired_head = -1;
642 ringbuf->head = I915_READ_HEAD(ring);
643 ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
644 intel_ring_update_space(ringbuf);
645
646 memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
647
648 out:
649 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
650
651 return ret;
652 }
653
654 void
655 intel_fini_pipe_control(struct intel_engine_cs *ring)
656 {
657 struct drm_device *dev = ring->dev;
658
659 if (ring->scratch.obj == NULL)
660 return;
661
662 if (INTEL_INFO(dev)->gen >= 5) {
663 kunmap(sg_page(ring->scratch.obj->pages->sgl));
664 i915_gem_object_ggtt_unpin(ring->scratch.obj);
665 }
666
667 drm_gem_object_unreference(&ring->scratch.obj->base);
668 ring->scratch.obj = NULL;
669 }
670
671 int
672 intel_init_pipe_control(struct intel_engine_cs *ring)
673 {
674 int ret;
675
676 WARN_ON(ring->scratch.obj);
677
678 ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096);
679 if (ring->scratch.obj == NULL) {
680 DRM_ERROR("Failed to allocate seqno page\n");
681 ret = -ENOMEM;
682 goto err;
683 }
684
685 ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
686 if (ret)
687 goto err_unref;
688
689 ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0);
690 if (ret)
691 goto err_unref;
692
693 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj);
694 ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl));
695 if (ring->scratch.cpu_page == NULL) {
696 ret = -ENOMEM;
697 goto err_unpin;
698 }
699
700 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
701 ring->name, ring->scratch.gtt_offset);
702 return 0;
703
704 err_unpin:
705 i915_gem_object_ggtt_unpin(ring->scratch.obj);
706 err_unref:
707 drm_gem_object_unreference(&ring->scratch.obj->base);
708 err:
709 return ret;
710 }
711
712 static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req)
713 {
714 int ret, i;
715 struct intel_engine_cs *ring = req->ring;
716 struct drm_device *dev = ring->dev;
717 struct drm_i915_private *dev_priv = dev->dev_private;
718 struct i915_workarounds *w = &dev_priv->workarounds;
719
720 if (WARN_ON_ONCE(w->count == 0))
721 return 0;
722
723 ring->gpu_caches_dirty = true;
724 ret = intel_ring_flush_all_caches(req);
725 if (ret)
726 return ret;
727
728 ret = intel_ring_begin(req, (w->count * 2 + 2));
729 if (ret)
730 return ret;
731
732 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count));
733 for (i = 0; i < w->count; i++) {
734 intel_ring_emit(ring, w->reg[i].addr);
735 intel_ring_emit(ring, w->reg[i].value);
736 }
737 intel_ring_emit(ring, MI_NOOP);
738
739 intel_ring_advance(ring);
740
741 ring->gpu_caches_dirty = true;
742 ret = intel_ring_flush_all_caches(req);
743 if (ret)
744 return ret;
745
746 DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
747
748 return 0;
749 }
750
751 static int intel_rcs_ctx_init(struct drm_i915_gem_request *req)
752 {
753 int ret;
754
755 ret = intel_ring_workarounds_emit(req);
756 if (ret != 0)
757 return ret;
758
759 ret = i915_gem_render_state_init(req);
760 if (ret)
761 DRM_ERROR("init render state: %d\n", ret);
762
763 return ret;
764 }
765
766 static int wa_add(struct drm_i915_private *dev_priv,
767 const u32 addr, const u32 mask, const u32 val)
768 {
769 const u32 idx = dev_priv->workarounds.count;
770
771 if (WARN_ON(idx >= I915_MAX_WA_REGS))
772 return -ENOSPC;
773
774 dev_priv->workarounds.reg[idx].addr = addr;
775 dev_priv->workarounds.reg[idx].value = val;
776 dev_priv->workarounds.reg[idx].mask = mask;
777
778 dev_priv->workarounds.count++;
779
780 return 0;
781 }
782
783 #define WA_REG(addr, mask, val) do { \
784 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
785 if (r) \
786 return r; \
787 } while (0)
788
789 #define WA_SET_BIT_MASKED(addr, mask) \
790 WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
791
792 #define WA_CLR_BIT_MASKED(addr, mask) \
793 WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
794
795 #define WA_SET_FIELD_MASKED(addr, mask, value) \
796 WA_REG(addr, mask, _MASKED_FIELD(mask, value))
797
798 #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
799 #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
800
801 #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
802
803 static int gen8_init_workarounds(struct intel_engine_cs *ring)
804 {
805
806 return 0;
807 }
808
809 static int bdw_init_workarounds(struct intel_engine_cs *ring)
810 {
811 int ret;
812 struct drm_device *dev = ring->dev;
813 struct drm_i915_private *dev_priv = dev->dev_private;
814
815 ret = gen8_init_workarounds(ring);
816 if (ret)
817 return ret;
818
819 WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
820
821 /* WaDisableAsyncFlipPerfMode:bdw */
822 WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
823
824 /* WaDisablePartialInstShootdown:bdw */
825 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
826 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
827 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
828 STALL_DOP_GATING_DISABLE);
829
830 /* WaDisableDopClockGating:bdw */
831 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
832 DOP_CLOCK_GATING_DISABLE);
833
834 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
835 GEN8_SAMPLER_POWER_BYPASS_DIS);
836
837 /* Use Force Non-Coherent whenever executing a 3D context. This is a
838 * workaround for for a possible hang in the unlikely event a TLB
839 * invalidation occurs during a PSD flush.
840 */
841 WA_SET_BIT_MASKED(HDC_CHICKEN0,
842 /* WaForceEnableNonCoherent:bdw */
843 HDC_FORCE_NON_COHERENT |
844 /* WaForceContextSaveRestoreNonCoherent:bdw */
845 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
846 /* WaHdcDisableFetchWhenMasked:bdw */
847 HDC_DONOT_FETCH_MEM_WHEN_MASKED |
848 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
849 (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
850
851 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
852 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
853 * polygons in the same 8x4 pixel/sample area to be processed without
854 * stalling waiting for the earlier ones to write to Hierarchical Z
855 * buffer."
856 *
857 * This optimization is off by default for Broadwell; turn it on.
858 */
859 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
860
861 /* Wa4x4STCOptimizationDisable:bdw */
862 WA_SET_BIT_MASKED(CACHE_MODE_1,
863 GEN8_4x4_STC_OPTIMIZATION_DISABLE);
864
865 /*
866 * BSpec recommends 8x4 when MSAA is used,
867 * however in practice 16x4 seems fastest.
868 *
869 * Note that PS/WM thread counts depend on the WIZ hashing
870 * disable bit, which we don't touch here, but it's good
871 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
872 */
873 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
874 GEN6_WIZ_HASHING_MASK,
875 GEN6_WIZ_HASHING_16x4);
876
877 return 0;
878 }
879
880 static int chv_init_workarounds(struct intel_engine_cs *ring)
881 {
882 int ret;
883 struct drm_device *dev = ring->dev;
884 struct drm_i915_private *dev_priv = dev->dev_private;
885
886 ret = gen8_init_workarounds(ring);
887 if (ret)
888 return ret;
889
890 WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
891
892 /* WaDisableAsyncFlipPerfMode:chv */
893 WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
894
895 /* WaDisablePartialInstShootdown:chv */
896 /* WaDisableThreadStallDopClockGating:chv */
897 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
898 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
899 STALL_DOP_GATING_DISABLE);
900
901 /* Use Force Non-Coherent whenever executing a 3D context. This is a
902 * workaround for a possible hang in the unlikely event a TLB
903 * invalidation occurs during a PSD flush.
904 */
905 /* WaForceEnableNonCoherent:chv */
906 /* WaHdcDisableFetchWhenMasked:chv */
907 WA_SET_BIT_MASKED(HDC_CHICKEN0,
908 HDC_FORCE_NON_COHERENT |
909 HDC_DONOT_FETCH_MEM_WHEN_MASKED);
910
911 /* According to the CACHE_MODE_0 default value documentation, some
912 * CHV platforms disable this optimization by default. Turn it on.
913 */
914 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
915
916 /* Wa4x4STCOptimizationDisable:chv */
917 WA_SET_BIT_MASKED(CACHE_MODE_1,
918 GEN8_4x4_STC_OPTIMIZATION_DISABLE);
919
920 /* Improve HiZ throughput on CHV. */
921 WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
922
923 /*
924 * BSpec recommends 8x4 when MSAA is used,
925 * however in practice 16x4 seems fastest.
926 *
927 * Note that PS/WM thread counts depend on the WIZ hashing
928 * disable bit, which we don't touch here, but it's good
929 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
930 */
931 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
932 GEN6_WIZ_HASHING_MASK,
933 GEN6_WIZ_HASHING_16x4);
934
935 return 0;
936 }
937
938 static int gen9_init_workarounds(struct intel_engine_cs *ring)
939 {
940 struct drm_device *dev = ring->dev;
941 struct drm_i915_private *dev_priv = dev->dev_private;
942 uint32_t tmp;
943
944 /* WaDisablePartialInstShootdown:skl,bxt */
945 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
946 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
947
948 /* Syncing dependencies between camera and graphics:skl,bxt */
949 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
950 GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
951
952 if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) == SKL_REVID_A0 ||
953 INTEL_REVID(dev) == SKL_REVID_B0)) ||
954 (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) {
955 /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
956 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
957 GEN9_DG_MIRROR_FIX_ENABLE);
958 }
959
960 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) ||
961 (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) {
962 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
963 WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
964 GEN9_RHWO_OPTIMIZATION_DISABLE);
965 /*
966 * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
967 * but we do that in per ctx batchbuffer as there is an issue
968 * with this register not getting restored on ctx restore
969 */
970 }
971
972 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) >= SKL_REVID_C0) ||
973 IS_BROXTON(dev)) {
974 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt */
975 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
976 GEN9_ENABLE_YV12_BUGFIX);
977 }
978
979 /* Wa4x4STCOptimizationDisable:skl,bxt */
980 /* WaDisablePartialResolveInVc:skl,bxt */
981 WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE |
982 GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE));
983
984 /* WaCcsTlbPrefetchDisable:skl,bxt */
985 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
986 GEN9_CCS_TLB_PREFETCH_ENABLE);
987
988 /* WaDisableMaskBasedCammingInRCC:skl,bxt */
989 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) == SKL_REVID_C0) ||
990 (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0))
991 WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
992 PIXEL_MASK_CAMMING_DISABLE);
993
994 /* WaForceContextSaveRestoreNonCoherent:skl,bxt */
995 tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT;
996 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) == SKL_REVID_F0) ||
997 (IS_BROXTON(dev) && INTEL_REVID(dev) >= BXT_REVID_B0))
998 tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
999 WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
1000
1001 /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt */
1002 if (IS_SKYLAKE(dev) ||
1003 (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_B0)) {
1004 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
1005 GEN8_SAMPLER_POWER_BYPASS_DIS);
1006 }
1007
1008 /* WaDisableSTUnitPowerOptimization:skl,bxt */
1009 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
1010
1011 return 0;
1012 }
1013
1014 static int skl_tune_iz_hashing(struct intel_engine_cs *ring)
1015 {
1016 struct drm_device *dev = ring->dev;
1017 struct drm_i915_private *dev_priv = dev->dev_private;
1018 u8 vals[3] = { 0, 0, 0 };
1019 unsigned int i;
1020
1021 for (i = 0; i < 3; i++) {
1022 u8 ss;
1023
1024 /*
1025 * Only consider slices where one, and only one, subslice has 7
1026 * EUs
1027 */
1028 if (hweight8(dev_priv->info.subslice_7eu[i]) != 1)
1029 continue;
1030
1031 /*
1032 * subslice_7eu[i] != 0 (because of the check above) and
1033 * ss_max == 4 (maximum number of subslices possible per slice)
1034 *
1035 * -> 0 <= ss <= 3;
1036 */
1037 ss = ffs(dev_priv->info.subslice_7eu[i]) - 1;
1038 vals[i] = 3 - ss;
1039 }
1040
1041 if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0)
1042 return 0;
1043
1044 /* Tune IZ hashing. See intel_device_info_runtime_init() */
1045 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
1046 GEN9_IZ_HASHING_MASK(2) |
1047 GEN9_IZ_HASHING_MASK(1) |
1048 GEN9_IZ_HASHING_MASK(0),
1049 GEN9_IZ_HASHING(2, vals[2]) |
1050 GEN9_IZ_HASHING(1, vals[1]) |
1051 GEN9_IZ_HASHING(0, vals[0]));
1052
1053 return 0;
1054 }
1055
1056
1057 static int skl_init_workarounds(struct intel_engine_cs *ring)
1058 {
1059 int ret;
1060 struct drm_device *dev = ring->dev;
1061 struct drm_i915_private *dev_priv = dev->dev_private;
1062
1063 ret = gen9_init_workarounds(ring);
1064 if (ret)
1065 return ret;
1066
1067 /* WaDisablePowerCompilerClockGating:skl */
1068 if (INTEL_REVID(dev) == SKL_REVID_B0)
1069 WA_SET_BIT_MASKED(HIZ_CHICKEN,
1070 BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
1071
1072 if (INTEL_REVID(dev) <= SKL_REVID_D0) {
1073 /*
1074 *Use Force Non-Coherent whenever executing a 3D context. This
1075 * is a workaround for a possible hang in the unlikely event
1076 * a TLB invalidation occurs during a PSD flush.
1077 */
1078 /* WaForceEnableNonCoherent:skl */
1079 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1080 HDC_FORCE_NON_COHERENT);
1081 }
1082
1083 if (INTEL_REVID(dev) == SKL_REVID_C0 ||
1084 INTEL_REVID(dev) == SKL_REVID_D0)
1085 /* WaBarrierPerformanceFixDisable:skl */
1086 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1087 HDC_FENCE_DEST_SLM_DISABLE |
1088 HDC_BARRIER_PERFORMANCE_DISABLE);
1089
1090 /* WaDisableSbeCacheDispatchPortSharing:skl */
1091 if (INTEL_REVID(dev) <= SKL_REVID_F0) {
1092 WA_SET_BIT_MASKED(
1093 GEN7_HALF_SLICE_CHICKEN1,
1094 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1095 }
1096
1097 return skl_tune_iz_hashing(ring);
1098 }
1099
1100 static int bxt_init_workarounds(struct intel_engine_cs *ring)
1101 {
1102 int ret;
1103 struct drm_device *dev = ring->dev;
1104 struct drm_i915_private *dev_priv = dev->dev_private;
1105
1106 ret = gen9_init_workarounds(ring);
1107 if (ret)
1108 return ret;
1109
1110 /* WaDisableThreadStallDopClockGating:bxt */
1111 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
1112 STALL_DOP_GATING_DISABLE);
1113
1114 /* WaDisableSbeCacheDispatchPortSharing:bxt */
1115 if (INTEL_REVID(dev) <= BXT_REVID_B0) {
1116 WA_SET_BIT_MASKED(
1117 GEN7_HALF_SLICE_CHICKEN1,
1118 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1119 }
1120
1121 return 0;
1122 }
1123
1124 int init_workarounds_ring(struct intel_engine_cs *ring)
1125 {
1126 struct drm_device *dev = ring->dev;
1127 struct drm_i915_private *dev_priv = dev->dev_private;
1128
1129 WARN_ON(ring->id != RCS);
1130
1131 dev_priv->workarounds.count = 0;
1132
1133 if (IS_BROADWELL(dev))
1134 return bdw_init_workarounds(ring);
1135
1136 if (IS_CHERRYVIEW(dev))
1137 return chv_init_workarounds(ring);
1138
1139 if (IS_SKYLAKE(dev))
1140 return skl_init_workarounds(ring);
1141
1142 if (IS_BROXTON(dev))
1143 return bxt_init_workarounds(ring);
1144
1145 return 0;
1146 }
1147
1148 static int init_render_ring(struct intel_engine_cs *ring)
1149 {
1150 struct drm_device *dev = ring->dev;
1151 struct drm_i915_private *dev_priv = dev->dev_private;
1152 int ret = init_ring_common(ring);
1153 if (ret)
1154 return ret;
1155
1156 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
1157 if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
1158 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
1159
1160 /* We need to disable the AsyncFlip performance optimisations in order
1161 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1162 * programmed to '1' on all products.
1163 *
1164 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
1165 */
1166 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
1167 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1168
1169 /* Required for the hardware to program scanline values for waiting */
1170 /* WaEnableFlushTlbInvalidationMode:snb */
1171 if (INTEL_INFO(dev)->gen == 6)
1172 I915_WRITE(GFX_MODE,
1173 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
1174
1175 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1176 if (IS_GEN7(dev))
1177 I915_WRITE(GFX_MODE_GEN7,
1178 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
1179 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
1180
1181 if (IS_GEN6(dev)) {
1182 /* From the Sandybridge PRM, volume 1 part 3, page 24:
1183 * "If this bit is set, STCunit will have LRA as replacement
1184 * policy. [...] This bit must be reset. LRA replacement
1185 * policy is not supported."
1186 */
1187 I915_WRITE(CACHE_MODE_0,
1188 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
1189 }
1190
1191 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
1192 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1193
1194 if (HAS_L3_DPF(dev))
1195 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1196
1197 return init_workarounds_ring(ring);
1198 }
1199
1200 static void render_ring_cleanup(struct intel_engine_cs *ring)
1201 {
1202 struct drm_device *dev = ring->dev;
1203 struct drm_i915_private *dev_priv = dev->dev_private;
1204
1205 if (dev_priv->semaphore_obj) {
1206 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
1207 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
1208 dev_priv->semaphore_obj = NULL;
1209 }
1210
1211 intel_fini_pipe_control(ring);
1212 }
1213
1214 static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req,
1215 unsigned int num_dwords)
1216 {
1217 #define MBOX_UPDATE_DWORDS 8
1218 struct intel_engine_cs *signaller = signaller_req->ring;
1219 struct drm_device *dev = signaller->dev;
1220 struct drm_i915_private *dev_priv = dev->dev_private;
1221 struct intel_engine_cs *waiter;
1222 int i, ret, num_rings;
1223
1224 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1225 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1226 #undef MBOX_UPDATE_DWORDS
1227
1228 ret = intel_ring_begin(signaller_req, num_dwords);
1229 if (ret)
1230 return ret;
1231
1232 for_each_ring(waiter, dev_priv, i) {
1233 u32 seqno;
1234 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1235 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1236 continue;
1237
1238 seqno = i915_gem_request_get_seqno(signaller_req);
1239 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
1240 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
1241 PIPE_CONTROL_QW_WRITE |
1242 PIPE_CONTROL_FLUSH_ENABLE);
1243 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
1244 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1245 intel_ring_emit(signaller, seqno);
1246 intel_ring_emit(signaller, 0);
1247 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1248 MI_SEMAPHORE_TARGET(waiter->id));
1249 intel_ring_emit(signaller, 0);
1250 }
1251
1252 return 0;
1253 }
1254
1255 static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req,
1256 unsigned int num_dwords)
1257 {
1258 #define MBOX_UPDATE_DWORDS 6
1259 struct intel_engine_cs *signaller = signaller_req->ring;
1260 struct drm_device *dev = signaller->dev;
1261 struct drm_i915_private *dev_priv = dev->dev_private;
1262 struct intel_engine_cs *waiter;
1263 int i, ret, num_rings;
1264
1265 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1266 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1267 #undef MBOX_UPDATE_DWORDS
1268
1269 ret = intel_ring_begin(signaller_req, num_dwords);
1270 if (ret)
1271 return ret;
1272
1273 for_each_ring(waiter, dev_priv, i) {
1274 u32 seqno;
1275 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1276 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1277 continue;
1278
1279 seqno = i915_gem_request_get_seqno(signaller_req);
1280 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
1281 MI_FLUSH_DW_OP_STOREDW);
1282 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
1283 MI_FLUSH_DW_USE_GTT);
1284 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1285 intel_ring_emit(signaller, seqno);
1286 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1287 MI_SEMAPHORE_TARGET(waiter->id));
1288 intel_ring_emit(signaller, 0);
1289 }
1290
1291 return 0;
1292 }
1293
1294 static int gen6_signal(struct drm_i915_gem_request *signaller_req,
1295 unsigned int num_dwords)
1296 {
1297 struct intel_engine_cs *signaller = signaller_req->ring;
1298 struct drm_device *dev = signaller->dev;
1299 struct drm_i915_private *dev_priv = dev->dev_private;
1300 struct intel_engine_cs *useless;
1301 int i, ret, num_rings;
1302
1303 #define MBOX_UPDATE_DWORDS 3
1304 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1305 num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
1306 #undef MBOX_UPDATE_DWORDS
1307
1308 ret = intel_ring_begin(signaller_req, num_dwords);
1309 if (ret)
1310 return ret;
1311
1312 for_each_ring(useless, dev_priv, i) {
1313 u32 mbox_reg = signaller->semaphore.mbox.signal[i];
1314 if (mbox_reg != GEN6_NOSYNC) {
1315 u32 seqno = i915_gem_request_get_seqno(signaller_req);
1316 intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
1317 intel_ring_emit(signaller, mbox_reg);
1318 intel_ring_emit(signaller, seqno);
1319 }
1320 }
1321
1322 /* If num_dwords was rounded, make sure the tail pointer is correct */
1323 if (num_rings % 2 == 0)
1324 intel_ring_emit(signaller, MI_NOOP);
1325
1326 return 0;
1327 }
1328
1329 /**
1330 * gen6_add_request - Update the semaphore mailbox registers
1331 *
1332 * @request - request to write to the ring
1333 *
1334 * Update the mailbox registers in the *other* rings with the current seqno.
1335 * This acts like a signal in the canonical semaphore.
1336 */
1337 static int
1338 gen6_add_request(struct drm_i915_gem_request *req)
1339 {
1340 struct intel_engine_cs *ring = req->ring;
1341 int ret;
1342
1343 if (ring->semaphore.signal)
1344 ret = ring->semaphore.signal(req, 4);
1345 else
1346 ret = intel_ring_begin(req, 4);
1347
1348 if (ret)
1349 return ret;
1350
1351 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1352 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1353 intel_ring_emit(ring, i915_gem_request_get_seqno(req));
1354 intel_ring_emit(ring, MI_USER_INTERRUPT);
1355 __intel_ring_advance(ring);
1356
1357 return 0;
1358 }
1359
1360 static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
1361 u32 seqno)
1362 {
1363 struct drm_i915_private *dev_priv = dev->dev_private;
1364 return dev_priv->last_seqno < seqno;
1365 }
1366
1367 /**
1368 * intel_ring_sync - sync the waiter to the signaller on seqno
1369 *
1370 * @waiter - ring that is waiting
1371 * @signaller - ring which has, or will signal
1372 * @seqno - seqno which the waiter will block on
1373 */
1374
1375 static int
1376 gen8_ring_sync(struct drm_i915_gem_request *waiter_req,
1377 struct intel_engine_cs *signaller,
1378 u32 seqno)
1379 {
1380 struct intel_engine_cs *waiter = waiter_req->ring;
1381 struct drm_i915_private *dev_priv = waiter->dev->dev_private;
1382 int ret;
1383
1384 ret = intel_ring_begin(waiter_req, 4);
1385 if (ret)
1386 return ret;
1387
1388 intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1389 MI_SEMAPHORE_GLOBAL_GTT |
1390 MI_SEMAPHORE_POLL |
1391 MI_SEMAPHORE_SAD_GTE_SDD);
1392 intel_ring_emit(waiter, seqno);
1393 intel_ring_emit(waiter,
1394 lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1395 intel_ring_emit(waiter,
1396 upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1397 intel_ring_advance(waiter);
1398 return 0;
1399 }
1400
1401 static int
1402 gen6_ring_sync(struct drm_i915_gem_request *waiter_req,
1403 struct intel_engine_cs *signaller,
1404 u32 seqno)
1405 {
1406 struct intel_engine_cs *waiter = waiter_req->ring;
1407 u32 dw1 = MI_SEMAPHORE_MBOX |
1408 MI_SEMAPHORE_COMPARE |
1409 MI_SEMAPHORE_REGISTER;
1410 u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1411 int ret;
1412
1413 /* Throughout all of the GEM code, seqno passed implies our current
1414 * seqno is >= the last seqno executed. However for hardware the
1415 * comparison is strictly greater than.
1416 */
1417 seqno -= 1;
1418
1419 WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
1420
1421 ret = intel_ring_begin(waiter_req, 4);
1422 if (ret)
1423 return ret;
1424
1425 /* If seqno wrap happened, omit the wait with no-ops */
1426 if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
1427 intel_ring_emit(waiter, dw1 | wait_mbox);
1428 intel_ring_emit(waiter, seqno);
1429 intel_ring_emit(waiter, 0);
1430 intel_ring_emit(waiter, MI_NOOP);
1431 } else {
1432 intel_ring_emit(waiter, MI_NOOP);
1433 intel_ring_emit(waiter, MI_NOOP);
1434 intel_ring_emit(waiter, MI_NOOP);
1435 intel_ring_emit(waiter, MI_NOOP);
1436 }
1437 intel_ring_advance(waiter);
1438
1439 return 0;
1440 }
1441
1442 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
1443 do { \
1444 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
1445 PIPE_CONTROL_DEPTH_STALL); \
1446 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
1447 intel_ring_emit(ring__, 0); \
1448 intel_ring_emit(ring__, 0); \
1449 } while (0)
1450
1451 static int
1452 pc_render_add_request(struct drm_i915_gem_request *req)
1453 {
1454 struct intel_engine_cs *ring = req->ring;
1455 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1456 int ret;
1457
1458 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1459 * incoherent with writes to memory, i.e. completely fubar,
1460 * so we need to use PIPE_NOTIFY instead.
1461 *
1462 * However, we also need to workaround the qword write
1463 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1464 * memory before requesting an interrupt.
1465 */
1466 ret = intel_ring_begin(req, 32);
1467 if (ret)
1468 return ret;
1469
1470 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1471 PIPE_CONTROL_WRITE_FLUSH |
1472 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
1473 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1474 intel_ring_emit(ring, i915_gem_request_get_seqno(req));
1475 intel_ring_emit(ring, 0);
1476 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1477 scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
1478 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1479 scratch_addr += 2 * CACHELINE_BYTES;
1480 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1481 scratch_addr += 2 * CACHELINE_BYTES;
1482 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1483 scratch_addr += 2 * CACHELINE_BYTES;
1484 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1485 scratch_addr += 2 * CACHELINE_BYTES;
1486 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1487
1488 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1489 PIPE_CONTROL_WRITE_FLUSH |
1490 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
1491 PIPE_CONTROL_NOTIFY);
1492 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1493 intel_ring_emit(ring, i915_gem_request_get_seqno(req));
1494 intel_ring_emit(ring, 0);
1495 __intel_ring_advance(ring);
1496
1497 return 0;
1498 }
1499
1500 static u32
1501 gen6_ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1502 {
1503 /* Workaround to force correct ordering between irq and seqno writes on
1504 * ivb (and maybe also on snb) by reading from a CS register (like
1505 * ACTHD) before reading the status page. */
1506 if (!lazy_coherency) {
1507 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1508 POSTING_READ(RING_ACTHD(ring->mmio_base));
1509 }
1510
1511 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1512 }
1513
1514 static u32
1515 ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1516 {
1517 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1518 }
1519
1520 static void
1521 ring_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1522 {
1523 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1524 }
1525
1526 static u32
1527 pc_render_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1528 {
1529 return ring->scratch.cpu_page[0];
1530 }
1531
1532 static void
1533 pc_render_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1534 {
1535 ring->scratch.cpu_page[0] = seqno;
1536 }
1537
1538 static bool
1539 gen5_ring_get_irq(struct intel_engine_cs *ring)
1540 {
1541 struct drm_device *dev = ring->dev;
1542 struct drm_i915_private *dev_priv = dev->dev_private;
1543 unsigned long flags;
1544
1545 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1546 return false;
1547
1548 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1549 if (ring->irq_refcount++ == 0)
1550 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1551 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1552
1553 return true;
1554 }
1555
1556 static void
1557 gen5_ring_put_irq(struct intel_engine_cs *ring)
1558 {
1559 struct drm_device *dev = ring->dev;
1560 struct drm_i915_private *dev_priv = dev->dev_private;
1561 unsigned long flags;
1562
1563 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1564 if (--ring->irq_refcount == 0)
1565 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1566 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1567 }
1568
1569 static bool
1570 i9xx_ring_get_irq(struct intel_engine_cs *ring)
1571 {
1572 struct drm_device *dev = ring->dev;
1573 struct drm_i915_private *dev_priv = dev->dev_private;
1574 unsigned long flags;
1575
1576 if (!intel_irqs_enabled(dev_priv))
1577 return false;
1578
1579 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1580 if (ring->irq_refcount++ == 0) {
1581 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1582 I915_WRITE(IMR, dev_priv->irq_mask);
1583 POSTING_READ(IMR);
1584 }
1585 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1586
1587 return true;
1588 }
1589
1590 static void
1591 i9xx_ring_put_irq(struct intel_engine_cs *ring)
1592 {
1593 struct drm_device *dev = ring->dev;
1594 struct drm_i915_private *dev_priv = dev->dev_private;
1595 unsigned long flags;
1596
1597 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1598 if (--ring->irq_refcount == 0) {
1599 dev_priv->irq_mask |= ring->irq_enable_mask;
1600 I915_WRITE(IMR, dev_priv->irq_mask);
1601 POSTING_READ(IMR);
1602 }
1603 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1604 }
1605
1606 static bool
1607 i8xx_ring_get_irq(struct intel_engine_cs *ring)
1608 {
1609 struct drm_device *dev = ring->dev;
1610 struct drm_i915_private *dev_priv = dev->dev_private;
1611 unsigned long flags;
1612
1613 if (!intel_irqs_enabled(dev_priv))
1614 return false;
1615
1616 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1617 if (ring->irq_refcount++ == 0) {
1618 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1619 I915_WRITE16(IMR, dev_priv->irq_mask);
1620 POSTING_READ16(IMR);
1621 }
1622 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1623
1624 return true;
1625 }
1626
1627 static void
1628 i8xx_ring_put_irq(struct intel_engine_cs *ring)
1629 {
1630 struct drm_device *dev = ring->dev;
1631 struct drm_i915_private *dev_priv = dev->dev_private;
1632 unsigned long flags;
1633
1634 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1635 if (--ring->irq_refcount == 0) {
1636 dev_priv->irq_mask |= ring->irq_enable_mask;
1637 I915_WRITE16(IMR, dev_priv->irq_mask);
1638 POSTING_READ16(IMR);
1639 }
1640 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1641 }
1642
1643 static int
1644 bsd_ring_flush(struct drm_i915_gem_request *req,
1645 u32 invalidate_domains,
1646 u32 flush_domains)
1647 {
1648 struct intel_engine_cs *ring = req->ring;
1649 int ret;
1650
1651 ret = intel_ring_begin(req, 2);
1652 if (ret)
1653 return ret;
1654
1655 intel_ring_emit(ring, MI_FLUSH);
1656 intel_ring_emit(ring, MI_NOOP);
1657 intel_ring_advance(ring);
1658 return 0;
1659 }
1660
1661 static int
1662 i9xx_add_request(struct drm_i915_gem_request *req)
1663 {
1664 struct intel_engine_cs *ring = req->ring;
1665 int ret;
1666
1667 ret = intel_ring_begin(req, 4);
1668 if (ret)
1669 return ret;
1670
1671 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1672 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1673 intel_ring_emit(ring, i915_gem_request_get_seqno(req));
1674 intel_ring_emit(ring, MI_USER_INTERRUPT);
1675 __intel_ring_advance(ring);
1676
1677 return 0;
1678 }
1679
1680 static bool
1681 gen6_ring_get_irq(struct intel_engine_cs *ring)
1682 {
1683 struct drm_device *dev = ring->dev;
1684 struct drm_i915_private *dev_priv = dev->dev_private;
1685 unsigned long flags;
1686
1687 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1688 return false;
1689
1690 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1691 if (ring->irq_refcount++ == 0) {
1692 if (HAS_L3_DPF(dev) && ring->id == RCS)
1693 I915_WRITE_IMR(ring,
1694 ~(ring->irq_enable_mask |
1695 GT_PARITY_ERROR(dev)));
1696 else
1697 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1698 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1699 }
1700 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1701
1702 return true;
1703 }
1704
1705 static void
1706 gen6_ring_put_irq(struct intel_engine_cs *ring)
1707 {
1708 struct drm_device *dev = ring->dev;
1709 struct drm_i915_private *dev_priv = dev->dev_private;
1710 unsigned long flags;
1711
1712 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1713 if (--ring->irq_refcount == 0) {
1714 if (HAS_L3_DPF(dev) && ring->id == RCS)
1715 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1716 else
1717 I915_WRITE_IMR(ring, ~0);
1718 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1719 }
1720 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1721 }
1722
1723 static bool
1724 hsw_vebox_get_irq(struct intel_engine_cs *ring)
1725 {
1726 struct drm_device *dev = ring->dev;
1727 struct drm_i915_private *dev_priv = dev->dev_private;
1728 unsigned long flags;
1729
1730 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1731 return false;
1732
1733 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1734 if (ring->irq_refcount++ == 0) {
1735 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1736 gen6_enable_pm_irq(dev_priv, ring->irq_enable_mask);
1737 }
1738 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1739
1740 return true;
1741 }
1742
1743 static void
1744 hsw_vebox_put_irq(struct intel_engine_cs *ring)
1745 {
1746 struct drm_device *dev = ring->dev;
1747 struct drm_i915_private *dev_priv = dev->dev_private;
1748 unsigned long flags;
1749
1750 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1751 if (--ring->irq_refcount == 0) {
1752 I915_WRITE_IMR(ring, ~0);
1753 gen6_disable_pm_irq(dev_priv, ring->irq_enable_mask);
1754 }
1755 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1756 }
1757
1758 static bool
1759 gen8_ring_get_irq(struct intel_engine_cs *ring)
1760 {
1761 struct drm_device *dev = ring->dev;
1762 struct drm_i915_private *dev_priv = dev->dev_private;
1763 unsigned long flags;
1764
1765 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1766 return false;
1767
1768 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1769 if (ring->irq_refcount++ == 0) {
1770 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1771 I915_WRITE_IMR(ring,
1772 ~(ring->irq_enable_mask |
1773 GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1774 } else {
1775 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1776 }
1777 POSTING_READ(RING_IMR(ring->mmio_base));
1778 }
1779 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1780
1781 return true;
1782 }
1783
1784 static void
1785 gen8_ring_put_irq(struct intel_engine_cs *ring)
1786 {
1787 struct drm_device *dev = ring->dev;
1788 struct drm_i915_private *dev_priv = dev->dev_private;
1789 unsigned long flags;
1790
1791 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1792 if (--ring->irq_refcount == 0) {
1793 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1794 I915_WRITE_IMR(ring,
1795 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1796 } else {
1797 I915_WRITE_IMR(ring, ~0);
1798 }
1799 POSTING_READ(RING_IMR(ring->mmio_base));
1800 }
1801 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1802 }
1803
1804 static int
1805 i965_dispatch_execbuffer(struct drm_i915_gem_request *req,
1806 u64 offset, u32 length,
1807 unsigned dispatch_flags)
1808 {
1809 struct intel_engine_cs *ring = req->ring;
1810 int ret;
1811
1812 ret = intel_ring_begin(req, 2);
1813 if (ret)
1814 return ret;
1815
1816 intel_ring_emit(ring,
1817 MI_BATCH_BUFFER_START |
1818 MI_BATCH_GTT |
1819 (dispatch_flags & I915_DISPATCH_SECURE ?
1820 0 : MI_BATCH_NON_SECURE_I965));
1821 intel_ring_emit(ring, offset);
1822 intel_ring_advance(ring);
1823
1824 return 0;
1825 }
1826
1827 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1828 #define I830_BATCH_LIMIT (256*1024)
1829 #define I830_TLB_ENTRIES (2)
1830 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
1831 static int
1832 i830_dispatch_execbuffer(struct drm_i915_gem_request *req,
1833 u64 offset, u32 len,
1834 unsigned dispatch_flags)
1835 {
1836 struct intel_engine_cs *ring = req->ring;
1837 u32 cs_offset = ring->scratch.gtt_offset;
1838 int ret;
1839
1840 ret = intel_ring_begin(req, 6);
1841 if (ret)
1842 return ret;
1843
1844 /* Evict the invalid PTE TLBs */
1845 intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA);
1846 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
1847 intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */
1848 intel_ring_emit(ring, cs_offset);
1849 intel_ring_emit(ring, 0xdeadbeef);
1850 intel_ring_emit(ring, MI_NOOP);
1851 intel_ring_advance(ring);
1852
1853 if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) {
1854 if (len > I830_BATCH_LIMIT)
1855 return -ENOSPC;
1856
1857 ret = intel_ring_begin(req, 6 + 2);
1858 if (ret)
1859 return ret;
1860
1861 /* Blit the batch (which has now all relocs applied) to the
1862 * stable batch scratch bo area (so that the CS never
1863 * stumbles over its tlb invalidation bug) ...
1864 */
1865 intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
1866 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
1867 intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 4096);
1868 intel_ring_emit(ring, cs_offset);
1869 intel_ring_emit(ring, 4096);
1870 intel_ring_emit(ring, offset);
1871
1872 intel_ring_emit(ring, MI_FLUSH);
1873 intel_ring_emit(ring, MI_NOOP);
1874 intel_ring_advance(ring);
1875
1876 /* ... and execute it. */
1877 offset = cs_offset;
1878 }
1879
1880 ret = intel_ring_begin(req, 4);
1881 if (ret)
1882 return ret;
1883
1884 intel_ring_emit(ring, MI_BATCH_BUFFER);
1885 intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1886 0 : MI_BATCH_NON_SECURE));
1887 intel_ring_emit(ring, offset + len - 8);
1888 intel_ring_emit(ring, MI_NOOP);
1889 intel_ring_advance(ring);
1890
1891 return 0;
1892 }
1893
1894 static int
1895 i915_dispatch_execbuffer(struct drm_i915_gem_request *req,
1896 u64 offset, u32 len,
1897 unsigned dispatch_flags)
1898 {
1899 struct intel_engine_cs *ring = req->ring;
1900 int ret;
1901
1902 ret = intel_ring_begin(req, 2);
1903 if (ret)
1904 return ret;
1905
1906 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1907 intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1908 0 : MI_BATCH_NON_SECURE));
1909 intel_ring_advance(ring);
1910
1911 return 0;
1912 }
1913
1914 static void cleanup_status_page(struct intel_engine_cs *ring)
1915 {
1916 struct drm_i915_gem_object *obj;
1917
1918 obj = ring->status_page.obj;
1919 if (obj == NULL)
1920 return;
1921
1922 kunmap(sg_page(obj->pages->sgl));
1923 i915_gem_object_ggtt_unpin(obj);
1924 drm_gem_object_unreference(&obj->base);
1925 ring->status_page.obj = NULL;
1926 }
1927
1928 static int init_status_page(struct intel_engine_cs *ring)
1929 {
1930 struct drm_i915_gem_object *obj;
1931
1932 if ((obj = ring->status_page.obj) == NULL) {
1933 unsigned flags;
1934 int ret;
1935
1936 obj = i915_gem_alloc_object(ring->dev, 4096);
1937 if (obj == NULL) {
1938 DRM_ERROR("Failed to allocate status page\n");
1939 return -ENOMEM;
1940 }
1941
1942 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1943 if (ret)
1944 goto err_unref;
1945
1946 flags = 0;
1947 if (!HAS_LLC(ring->dev))
1948 /* On g33, we cannot place HWS above 256MiB, so
1949 * restrict its pinning to the low mappable arena.
1950 * Though this restriction is not documented for
1951 * gen4, gen5, or byt, they also behave similarly
1952 * and hang if the HWS is placed at the top of the
1953 * GTT. To generalise, it appears that all !llc
1954 * platforms have issues with us placing the HWS
1955 * above the mappable region (even though we never
1956 * actualy map it).
1957 */
1958 flags |= PIN_MAPPABLE;
1959 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
1960 if (ret) {
1961 err_unref:
1962 drm_gem_object_unreference(&obj->base);
1963 return ret;
1964 }
1965
1966 ring->status_page.obj = obj;
1967 }
1968
1969 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
1970 ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
1971 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1972
1973 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1974 ring->name, ring->status_page.gfx_addr);
1975
1976 return 0;
1977 }
1978
1979 static int init_phys_status_page(struct intel_engine_cs *ring)
1980 {
1981 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1982
1983 if (!dev_priv->status_page_dmah) {
1984 dev_priv->status_page_dmah =
1985 drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1986 if (!dev_priv->status_page_dmah)
1987 return -ENOMEM;
1988 }
1989
1990 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1991 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1992
1993 return 0;
1994 }
1995
1996 void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
1997 {
1998 iounmap(ringbuf->virtual_start);
1999 ringbuf->virtual_start = NULL;
2000 i915_gem_object_ggtt_unpin(ringbuf->obj);
2001 }
2002
2003 int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
2004 struct intel_ringbuffer *ringbuf)
2005 {
2006 struct drm_i915_private *dev_priv = to_i915(dev);
2007 struct drm_i915_gem_object *obj = ringbuf->obj;
2008 int ret;
2009
2010 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
2011 if (ret)
2012 return ret;
2013
2014 ret = i915_gem_object_set_to_gtt_domain(obj, true);
2015 if (ret) {
2016 i915_gem_object_ggtt_unpin(obj);
2017 return ret;
2018 }
2019
2020 ringbuf->virtual_start = ioremap_wc(dev_priv->gtt.mappable_base +
2021 i915_gem_obj_ggtt_offset(obj), ringbuf->size);
2022 if (ringbuf->virtual_start == NULL) {
2023 i915_gem_object_ggtt_unpin(obj);
2024 return -EINVAL;
2025 }
2026
2027 return 0;
2028 }
2029
2030 static void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
2031 {
2032 drm_gem_object_unreference(&ringbuf->obj->base);
2033 ringbuf->obj = NULL;
2034 }
2035
2036 static int intel_alloc_ringbuffer_obj(struct drm_device *dev,
2037 struct intel_ringbuffer *ringbuf)
2038 {
2039 struct drm_i915_gem_object *obj;
2040
2041 obj = NULL;
2042 if (!HAS_LLC(dev))
2043 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
2044 if (obj == NULL)
2045 obj = i915_gem_alloc_object(dev, ringbuf->size);
2046 if (obj == NULL)
2047 return -ENOMEM;
2048
2049 /* mark ring buffers as read-only from GPU side by default */
2050 obj->gt_ro = 1;
2051
2052 ringbuf->obj = obj;
2053
2054 return 0;
2055 }
2056
2057 struct intel_ringbuffer *
2058 intel_engine_create_ringbuffer(struct intel_engine_cs *engine, int size)
2059 {
2060 struct intel_ringbuffer *ring;
2061 int ret;
2062
2063 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
2064 if (ring == NULL)
2065 return ERR_PTR(-ENOMEM);
2066
2067 ring->ring = engine;
2068
2069 ring->size = size;
2070 /* Workaround an erratum on the i830 which causes a hang if
2071 * the TAIL pointer points to within the last 2 cachelines
2072 * of the buffer.
2073 */
2074 ring->effective_size = size;
2075 if (IS_I830(engine->dev) || IS_845G(engine->dev))
2076 ring->effective_size -= 2 * CACHELINE_BYTES;
2077
2078 ring->last_retired_head = -1;
2079 intel_ring_update_space(ring);
2080
2081 ret = intel_alloc_ringbuffer_obj(engine->dev, ring);
2082 if (ret) {
2083 DRM_ERROR("Failed to allocate ringbuffer %s: %d\n",
2084 engine->name, ret);
2085 kfree(ring);
2086 return ERR_PTR(ret);
2087 }
2088
2089 return ring;
2090 }
2091
2092 void
2093 intel_ringbuffer_free(struct intel_ringbuffer *ring)
2094 {
2095 intel_destroy_ringbuffer_obj(ring);
2096 kfree(ring);
2097 }
2098
2099 static int intel_init_ring_buffer(struct drm_device *dev,
2100 struct intel_engine_cs *ring)
2101 {
2102 struct intel_ringbuffer *ringbuf;
2103 int ret;
2104
2105 WARN_ON(ring->buffer);
2106
2107 ring->dev = dev;
2108 INIT_LIST_HEAD(&ring->active_list);
2109 INIT_LIST_HEAD(&ring->request_list);
2110 INIT_LIST_HEAD(&ring->execlist_queue);
2111 i915_gem_batch_pool_init(dev, &ring->batch_pool);
2112 memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno));
2113
2114 init_waitqueue_head(&ring->irq_queue);
2115
2116 ringbuf = intel_engine_create_ringbuffer(ring, 32 * PAGE_SIZE);
2117 if (IS_ERR(ringbuf))
2118 return PTR_ERR(ringbuf);
2119 ring->buffer = ringbuf;
2120
2121 if (I915_NEED_GFX_HWS(dev)) {
2122 ret = init_status_page(ring);
2123 if (ret)
2124 goto error;
2125 } else {
2126 BUG_ON(ring->id != RCS);
2127 ret = init_phys_status_page(ring);
2128 if (ret)
2129 goto error;
2130 }
2131
2132 ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
2133 if (ret) {
2134 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
2135 ring->name, ret);
2136 intel_destroy_ringbuffer_obj(ringbuf);
2137 goto error;
2138 }
2139
2140 ret = i915_cmd_parser_init_ring(ring);
2141 if (ret)
2142 goto error;
2143
2144 return 0;
2145
2146 error:
2147 intel_ringbuffer_free(ringbuf);
2148 ring->buffer = NULL;
2149 return ret;
2150 }
2151
2152 void intel_cleanup_ring_buffer(struct intel_engine_cs *ring)
2153 {
2154 struct drm_i915_private *dev_priv;
2155
2156 if (!intel_ring_initialized(ring))
2157 return;
2158
2159 dev_priv = to_i915(ring->dev);
2160
2161 intel_stop_ring_buffer(ring);
2162 WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0);
2163
2164 intel_unpin_ringbuffer_obj(ring->buffer);
2165 intel_ringbuffer_free(ring->buffer);
2166 ring->buffer = NULL;
2167
2168 if (ring->cleanup)
2169 ring->cleanup(ring);
2170
2171 cleanup_status_page(ring);
2172
2173 i915_cmd_parser_fini_ring(ring);
2174 i915_gem_batch_pool_fini(&ring->batch_pool);
2175 }
2176
2177 static int ring_wait_for_space(struct intel_engine_cs *ring, int n)
2178 {
2179 struct intel_ringbuffer *ringbuf = ring->buffer;
2180 struct drm_i915_gem_request *request;
2181 unsigned space;
2182 int ret;
2183
2184 if (intel_ring_space(ringbuf) >= n)
2185 return 0;
2186
2187 /* The whole point of reserving space is to not wait! */
2188 WARN_ON(ringbuf->reserved_in_use);
2189
2190 list_for_each_entry(request, &ring->request_list, list) {
2191 space = __intel_ring_space(request->postfix, ringbuf->tail,
2192 ringbuf->size);
2193 if (space >= n)
2194 break;
2195 }
2196
2197 if (WARN_ON(&request->list == &ring->request_list))
2198 return -ENOSPC;
2199
2200 ret = i915_wait_request(request);
2201 if (ret)
2202 return ret;
2203
2204 ringbuf->space = space;
2205 return 0;
2206 }
2207
2208 static void __wrap_ring_buffer(struct intel_ringbuffer *ringbuf)
2209 {
2210 uint32_t __iomem *virt;
2211 int rem = ringbuf->size - ringbuf->tail;
2212
2213 virt = ringbuf->virtual_start + ringbuf->tail;
2214 rem /= 4;
2215 while (rem--)
2216 iowrite32(MI_NOOP, virt++);
2217
2218 ringbuf->tail = 0;
2219 intel_ring_update_space(ringbuf);
2220 }
2221
2222 int intel_ring_idle(struct intel_engine_cs *ring)
2223 {
2224 struct drm_i915_gem_request *req;
2225
2226 /* Wait upon the last request to be completed */
2227 if (list_empty(&ring->request_list))
2228 return 0;
2229
2230 req = list_entry(ring->request_list.prev,
2231 struct drm_i915_gem_request,
2232 list);
2233
2234 /* Make sure we do not trigger any retires */
2235 return __i915_wait_request(req,
2236 atomic_read(&to_i915(ring->dev)->gpu_error.reset_counter),
2237 to_i915(ring->dev)->mm.interruptible,
2238 NULL, NULL);
2239 }
2240
2241 int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request)
2242 {
2243 request->ringbuf = request->ring->buffer;
2244 return 0;
2245 }
2246
2247 int intel_ring_reserve_space(struct drm_i915_gem_request *request)
2248 {
2249 /*
2250 * The first call merely notes the reserve request and is common for
2251 * all back ends. The subsequent localised _begin() call actually
2252 * ensures that the reservation is available. Without the begin, if
2253 * the request creator immediately submitted the request without
2254 * adding any commands to it then there might not actually be
2255 * sufficient room for the submission commands.
2256 */
2257 intel_ring_reserved_space_reserve(request->ringbuf, MIN_SPACE_FOR_ADD_REQUEST);
2258
2259 return intel_ring_begin(request, 0);
2260 }
2261
2262 void intel_ring_reserved_space_reserve(struct intel_ringbuffer *ringbuf, int size)
2263 {
2264 WARN_ON(ringbuf->reserved_size);
2265 WARN_ON(ringbuf->reserved_in_use);
2266
2267 ringbuf->reserved_size = size;
2268 }
2269
2270 void intel_ring_reserved_space_cancel(struct intel_ringbuffer *ringbuf)
2271 {
2272 WARN_ON(ringbuf->reserved_in_use);
2273
2274 ringbuf->reserved_size = 0;
2275 ringbuf->reserved_in_use = false;
2276 }
2277
2278 void intel_ring_reserved_space_use(struct intel_ringbuffer *ringbuf)
2279 {
2280 WARN_ON(ringbuf->reserved_in_use);
2281
2282 ringbuf->reserved_in_use = true;
2283 ringbuf->reserved_tail = ringbuf->tail;
2284 }
2285
2286 void intel_ring_reserved_space_end(struct intel_ringbuffer *ringbuf)
2287 {
2288 WARN_ON(!ringbuf->reserved_in_use);
2289 if (ringbuf->tail > ringbuf->reserved_tail) {
2290 WARN(ringbuf->tail > ringbuf->reserved_tail + ringbuf->reserved_size,
2291 "request reserved size too small: %d vs %d!\n",
2292 ringbuf->tail - ringbuf->reserved_tail, ringbuf->reserved_size);
2293 } else {
2294 /*
2295 * The ring was wrapped while the reserved space was in use.
2296 * That means that some unknown amount of the ring tail was
2297 * no-op filled and skipped. Thus simply adding the ring size
2298 * to the tail and doing the above space check will not work.
2299 * Rather than attempt to track how much tail was skipped,
2300 * it is much simpler to say that also skipping the sanity
2301 * check every once in a while is not a big issue.
2302 */
2303 }
2304
2305 ringbuf->reserved_size = 0;
2306 ringbuf->reserved_in_use = false;
2307 }
2308
2309 static int __intel_ring_prepare(struct intel_engine_cs *ring, int bytes)
2310 {
2311 struct intel_ringbuffer *ringbuf = ring->buffer;
2312 int remain_usable = ringbuf->effective_size - ringbuf->tail;
2313 int remain_actual = ringbuf->size - ringbuf->tail;
2314 int ret, total_bytes, wait_bytes = 0;
2315 bool need_wrap = false;
2316
2317 if (ringbuf->reserved_in_use)
2318 total_bytes = bytes;
2319 else
2320 total_bytes = bytes + ringbuf->reserved_size;
2321
2322 if (unlikely(bytes > remain_usable)) {
2323 /*
2324 * Not enough space for the basic request. So need to flush
2325 * out the remainder and then wait for base + reserved.
2326 */
2327 wait_bytes = remain_actual + total_bytes;
2328 need_wrap = true;
2329 } else {
2330 if (unlikely(total_bytes > remain_usable)) {
2331 /*
2332 * The base request will fit but the reserved space
2333 * falls off the end. So only need to to wait for the
2334 * reserved size after flushing out the remainder.
2335 */
2336 wait_bytes = remain_actual + ringbuf->reserved_size;
2337 need_wrap = true;
2338 } else if (total_bytes > ringbuf->space) {
2339 /* No wrapping required, just waiting. */
2340 wait_bytes = total_bytes;
2341 }
2342 }
2343
2344 if (wait_bytes) {
2345 ret = ring_wait_for_space(ring, wait_bytes);
2346 if (unlikely(ret))
2347 return ret;
2348
2349 if (need_wrap)
2350 __wrap_ring_buffer(ringbuf);
2351 }
2352
2353 return 0;
2354 }
2355
2356 int intel_ring_begin(struct drm_i915_gem_request *req,
2357 int num_dwords)
2358 {
2359 struct intel_engine_cs *ring;
2360 struct drm_i915_private *dev_priv;
2361 int ret;
2362
2363 WARN_ON(req == NULL);
2364 ring = req->ring;
2365 dev_priv = ring->dev->dev_private;
2366
2367 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
2368 dev_priv->mm.interruptible);
2369 if (ret)
2370 return ret;
2371
2372 ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t));
2373 if (ret)
2374 return ret;
2375
2376 ring->buffer->space -= num_dwords * sizeof(uint32_t);
2377 return 0;
2378 }
2379
2380 /* Align the ring tail to a cacheline boundary */
2381 int intel_ring_cacheline_align(struct drm_i915_gem_request *req)
2382 {
2383 struct intel_engine_cs *ring = req->ring;
2384 int num_dwords = (ring->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
2385 int ret;
2386
2387 if (num_dwords == 0)
2388 return 0;
2389
2390 num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
2391 ret = intel_ring_begin(req, num_dwords);
2392 if (ret)
2393 return ret;
2394
2395 while (num_dwords--)
2396 intel_ring_emit(ring, MI_NOOP);
2397
2398 intel_ring_advance(ring);
2399
2400 return 0;
2401 }
2402
2403 void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno)
2404 {
2405 struct drm_device *dev = ring->dev;
2406 struct drm_i915_private *dev_priv = dev->dev_private;
2407
2408 if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) {
2409 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
2410 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
2411 if (HAS_VEBOX(dev))
2412 I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
2413 }
2414
2415 ring->set_seqno(ring, seqno);
2416 ring->hangcheck.seqno = seqno;
2417 }
2418
2419 static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring,
2420 u32 value)
2421 {
2422 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2423
2424 /* Every tail move must follow the sequence below */
2425
2426 /* Disable notification that the ring is IDLE. The GT
2427 * will then assume that it is busy and bring it out of rc6.
2428 */
2429 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2430 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2431
2432 /* Clear the context id. Here be magic! */
2433 I915_WRITE64(GEN6_BSD_RNCID, 0x0);
2434
2435 /* Wait for the ring not to be idle, i.e. for it to wake up. */
2436 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
2437 GEN6_BSD_SLEEP_INDICATOR) == 0,
2438 50))
2439 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
2440
2441 /* Now that the ring is fully powered up, update the tail */
2442 I915_WRITE_TAIL(ring, value);
2443 POSTING_READ(RING_TAIL(ring->mmio_base));
2444
2445 /* Let the ring send IDLE messages to the GT again,
2446 * and so let it sleep to conserve power when idle.
2447 */
2448 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2449 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2450 }
2451
2452 static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req,
2453 u32 invalidate, u32 flush)
2454 {
2455 struct intel_engine_cs *ring = req->ring;
2456 uint32_t cmd;
2457 int ret;
2458
2459 ret = intel_ring_begin(req, 4);
2460 if (ret)
2461 return ret;
2462
2463 cmd = MI_FLUSH_DW;
2464 if (INTEL_INFO(ring->dev)->gen >= 8)
2465 cmd += 1;
2466
2467 /* We always require a command barrier so that subsequent
2468 * commands, such as breadcrumb interrupts, are strictly ordered
2469 * wrt the contents of the write cache being flushed to memory
2470 * (and thus being coherent from the CPU).
2471 */
2472 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2473
2474 /*
2475 * Bspec vol 1c.5 - video engine command streamer:
2476 * "If ENABLED, all TLBs will be invalidated once the flush
2477 * operation is complete. This bit is only valid when the
2478 * Post-Sync Operation field is a value of 1h or 3h."
2479 */
2480 if (invalidate & I915_GEM_GPU_DOMAINS)
2481 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
2482
2483 intel_ring_emit(ring, cmd);
2484 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2485 if (INTEL_INFO(ring->dev)->gen >= 8) {
2486 intel_ring_emit(ring, 0); /* upper addr */
2487 intel_ring_emit(ring, 0); /* value */
2488 } else {
2489 intel_ring_emit(ring, 0);
2490 intel_ring_emit(ring, MI_NOOP);
2491 }
2492 intel_ring_advance(ring);
2493 return 0;
2494 }
2495
2496 static int
2497 gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2498 u64 offset, u32 len,
2499 unsigned dispatch_flags)
2500 {
2501 struct intel_engine_cs *ring = req->ring;
2502 bool ppgtt = USES_PPGTT(ring->dev) &&
2503 !(dispatch_flags & I915_DISPATCH_SECURE);
2504 int ret;
2505
2506 ret = intel_ring_begin(req, 4);
2507 if (ret)
2508 return ret;
2509
2510 /* FIXME(BDW): Address space and security selectors. */
2511 intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8) |
2512 (dispatch_flags & I915_DISPATCH_RS ?
2513 MI_BATCH_RESOURCE_STREAMER : 0));
2514 intel_ring_emit(ring, lower_32_bits(offset));
2515 intel_ring_emit(ring, upper_32_bits(offset));
2516 intel_ring_emit(ring, MI_NOOP);
2517 intel_ring_advance(ring);
2518
2519 return 0;
2520 }
2521
2522 static int
2523 hsw_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2524 u64 offset, u32 len,
2525 unsigned dispatch_flags)
2526 {
2527 struct intel_engine_cs *ring = req->ring;
2528 int ret;
2529
2530 ret = intel_ring_begin(req, 2);
2531 if (ret)
2532 return ret;
2533
2534 intel_ring_emit(ring,
2535 MI_BATCH_BUFFER_START |
2536 (dispatch_flags & I915_DISPATCH_SECURE ?
2537 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) |
2538 (dispatch_flags & I915_DISPATCH_RS ?
2539 MI_BATCH_RESOURCE_STREAMER : 0));
2540 /* bit0-7 is the length on GEN6+ */
2541 intel_ring_emit(ring, offset);
2542 intel_ring_advance(ring);
2543
2544 return 0;
2545 }
2546
2547 static int
2548 gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2549 u64 offset, u32 len,
2550 unsigned dispatch_flags)
2551 {
2552 struct intel_engine_cs *ring = req->ring;
2553 int ret;
2554
2555 ret = intel_ring_begin(req, 2);
2556 if (ret)
2557 return ret;
2558
2559 intel_ring_emit(ring,
2560 MI_BATCH_BUFFER_START |
2561 (dispatch_flags & I915_DISPATCH_SECURE ?
2562 0 : MI_BATCH_NON_SECURE_I965));
2563 /* bit0-7 is the length on GEN6+ */
2564 intel_ring_emit(ring, offset);
2565 intel_ring_advance(ring);
2566
2567 return 0;
2568 }
2569
2570 /* Blitter support (SandyBridge+) */
2571
2572 static int gen6_ring_flush(struct drm_i915_gem_request *req,
2573 u32 invalidate, u32 flush)
2574 {
2575 struct intel_engine_cs *ring = req->ring;
2576 struct drm_device *dev = ring->dev;
2577 uint32_t cmd;
2578 int ret;
2579
2580 ret = intel_ring_begin(req, 4);
2581 if (ret)
2582 return ret;
2583
2584 cmd = MI_FLUSH_DW;
2585 if (INTEL_INFO(dev)->gen >= 8)
2586 cmd += 1;
2587
2588 /* We always require a command barrier so that subsequent
2589 * commands, such as breadcrumb interrupts, are strictly ordered
2590 * wrt the contents of the write cache being flushed to memory
2591 * (and thus being coherent from the CPU).
2592 */
2593 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2594
2595 /*
2596 * Bspec vol 1c.3 - blitter engine command streamer:
2597 * "If ENABLED, all TLBs will be invalidated once the flush
2598 * operation is complete. This bit is only valid when the
2599 * Post-Sync Operation field is a value of 1h or 3h."
2600 */
2601 if (invalidate & I915_GEM_DOMAIN_RENDER)
2602 cmd |= MI_INVALIDATE_TLB;
2603 intel_ring_emit(ring, cmd);
2604 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2605 if (INTEL_INFO(dev)->gen >= 8) {
2606 intel_ring_emit(ring, 0); /* upper addr */
2607 intel_ring_emit(ring, 0); /* value */
2608 } else {
2609 intel_ring_emit(ring, 0);
2610 intel_ring_emit(ring, MI_NOOP);
2611 }
2612 intel_ring_advance(ring);
2613
2614 return 0;
2615 }
2616
2617 int intel_init_render_ring_buffer(struct drm_device *dev)
2618 {
2619 struct drm_i915_private *dev_priv = dev->dev_private;
2620 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
2621 struct drm_i915_gem_object *obj;
2622 int ret;
2623
2624 ring->name = "render ring";
2625 ring->id = RCS;
2626 ring->mmio_base = RENDER_RING_BASE;
2627
2628 if (INTEL_INFO(dev)->gen >= 8) {
2629 if (i915_semaphore_is_enabled(dev)) {
2630 obj = i915_gem_alloc_object(dev, 4096);
2631 if (obj == NULL) {
2632 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2633 i915.semaphores = 0;
2634 } else {
2635 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2636 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2637 if (ret != 0) {
2638 drm_gem_object_unreference(&obj->base);
2639 DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2640 i915.semaphores = 0;
2641 } else
2642 dev_priv->semaphore_obj = obj;
2643 }
2644 }
2645
2646 ring->init_context = intel_rcs_ctx_init;
2647 ring->add_request = gen6_add_request;
2648 ring->flush = gen8_render_ring_flush;
2649 ring->irq_get = gen8_ring_get_irq;
2650 ring->irq_put = gen8_ring_put_irq;
2651 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2652 ring->get_seqno = gen6_ring_get_seqno;
2653 ring->set_seqno = ring_set_seqno;
2654 if (i915_semaphore_is_enabled(dev)) {
2655 WARN_ON(!dev_priv->semaphore_obj);
2656 ring->semaphore.sync_to = gen8_ring_sync;
2657 ring->semaphore.signal = gen8_rcs_signal;
2658 GEN8_RING_SEMAPHORE_INIT;
2659 }
2660 } else if (INTEL_INFO(dev)->gen >= 6) {
2661 ring->add_request = gen6_add_request;
2662 ring->flush = gen7_render_ring_flush;
2663 if (INTEL_INFO(dev)->gen == 6)
2664 ring->flush = gen6_render_ring_flush;
2665 ring->irq_get = gen6_ring_get_irq;
2666 ring->irq_put = gen6_ring_put_irq;
2667 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2668 ring->get_seqno = gen6_ring_get_seqno;
2669 ring->set_seqno = ring_set_seqno;
2670 if (i915_semaphore_is_enabled(dev)) {
2671 ring->semaphore.sync_to = gen6_ring_sync;
2672 ring->semaphore.signal = gen6_signal;
2673 /*
2674 * The current semaphore is only applied on pre-gen8
2675 * platform. And there is no VCS2 ring on the pre-gen8
2676 * platform. So the semaphore between RCS and VCS2 is
2677 * initialized as INVALID. Gen8 will initialize the
2678 * sema between VCS2 and RCS later.
2679 */
2680 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2681 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2682 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2683 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2684 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2685 ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2686 ring->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2687 ring->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2688 ring->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2689 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2690 }
2691 } else if (IS_GEN5(dev)) {
2692 ring->add_request = pc_render_add_request;
2693 ring->flush = gen4_render_ring_flush;
2694 ring->get_seqno = pc_render_get_seqno;
2695 ring->set_seqno = pc_render_set_seqno;
2696 ring->irq_get = gen5_ring_get_irq;
2697 ring->irq_put = gen5_ring_put_irq;
2698 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
2699 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
2700 } else {
2701 ring->add_request = i9xx_add_request;
2702 if (INTEL_INFO(dev)->gen < 4)
2703 ring->flush = gen2_render_ring_flush;
2704 else
2705 ring->flush = gen4_render_ring_flush;
2706 ring->get_seqno = ring_get_seqno;
2707 ring->set_seqno = ring_set_seqno;
2708 if (IS_GEN2(dev)) {
2709 ring->irq_get = i8xx_ring_get_irq;
2710 ring->irq_put = i8xx_ring_put_irq;
2711 } else {
2712 ring->irq_get = i9xx_ring_get_irq;
2713 ring->irq_put = i9xx_ring_put_irq;
2714 }
2715 ring->irq_enable_mask = I915_USER_INTERRUPT;
2716 }
2717 ring->write_tail = ring_write_tail;
2718
2719 if (IS_HASWELL(dev))
2720 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
2721 else if (IS_GEN8(dev))
2722 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2723 else if (INTEL_INFO(dev)->gen >= 6)
2724 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2725 else if (INTEL_INFO(dev)->gen >= 4)
2726 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2727 else if (IS_I830(dev) || IS_845G(dev))
2728 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2729 else
2730 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
2731 ring->init_hw = init_render_ring;
2732 ring->cleanup = render_ring_cleanup;
2733
2734 /* Workaround batchbuffer to combat CS tlb bug. */
2735 if (HAS_BROKEN_CS_TLB(dev)) {
2736 obj = i915_gem_alloc_object(dev, I830_WA_SIZE);
2737 if (obj == NULL) {
2738 DRM_ERROR("Failed to allocate batch bo\n");
2739 return -ENOMEM;
2740 }
2741
2742 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
2743 if (ret != 0) {
2744 drm_gem_object_unreference(&obj->base);
2745 DRM_ERROR("Failed to ping batch bo\n");
2746 return ret;
2747 }
2748
2749 ring->scratch.obj = obj;
2750 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
2751 }
2752
2753 ret = intel_init_ring_buffer(dev, ring);
2754 if (ret)
2755 return ret;
2756
2757 if (INTEL_INFO(dev)->gen >= 5) {
2758 ret = intel_init_pipe_control(ring);
2759 if (ret)
2760 return ret;
2761 }
2762
2763 return 0;
2764 }
2765
2766 int intel_init_bsd_ring_buffer(struct drm_device *dev)
2767 {
2768 struct drm_i915_private *dev_priv = dev->dev_private;
2769 struct intel_engine_cs *ring = &dev_priv->ring[VCS];
2770
2771 ring->name = "bsd ring";
2772 ring->id = VCS;
2773
2774 ring->write_tail = ring_write_tail;
2775 if (INTEL_INFO(dev)->gen >= 6) {
2776 ring->mmio_base = GEN6_BSD_RING_BASE;
2777 /* gen6 bsd needs a special wa for tail updates */
2778 if (IS_GEN6(dev))
2779 ring->write_tail = gen6_bsd_ring_write_tail;
2780 ring->flush = gen6_bsd_ring_flush;
2781 ring->add_request = gen6_add_request;
2782 ring->get_seqno = gen6_ring_get_seqno;
2783 ring->set_seqno = ring_set_seqno;
2784 if (INTEL_INFO(dev)->gen >= 8) {
2785 ring->irq_enable_mask =
2786 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2787 ring->irq_get = gen8_ring_get_irq;
2788 ring->irq_put = gen8_ring_put_irq;
2789 ring->dispatch_execbuffer =
2790 gen8_ring_dispatch_execbuffer;
2791 if (i915_semaphore_is_enabled(dev)) {
2792 ring->semaphore.sync_to = gen8_ring_sync;
2793 ring->semaphore.signal = gen8_xcs_signal;
2794 GEN8_RING_SEMAPHORE_INIT;
2795 }
2796 } else {
2797 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2798 ring->irq_get = gen6_ring_get_irq;
2799 ring->irq_put = gen6_ring_put_irq;
2800 ring->dispatch_execbuffer =
2801 gen6_ring_dispatch_execbuffer;
2802 if (i915_semaphore_is_enabled(dev)) {
2803 ring->semaphore.sync_to = gen6_ring_sync;
2804 ring->semaphore.signal = gen6_signal;
2805 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2806 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2807 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
2808 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
2809 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2810 ring->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
2811 ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2812 ring->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
2813 ring->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
2814 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2815 }
2816 }
2817 } else {
2818 ring->mmio_base = BSD_RING_BASE;
2819 ring->flush = bsd_ring_flush;
2820 ring->add_request = i9xx_add_request;
2821 ring->get_seqno = ring_get_seqno;
2822 ring->set_seqno = ring_set_seqno;
2823 if (IS_GEN5(dev)) {
2824 ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
2825 ring->irq_get = gen5_ring_get_irq;
2826 ring->irq_put = gen5_ring_put_irq;
2827 } else {
2828 ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
2829 ring->irq_get = i9xx_ring_get_irq;
2830 ring->irq_put = i9xx_ring_put_irq;
2831 }
2832 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2833 }
2834 ring->init_hw = init_ring_common;
2835
2836 return intel_init_ring_buffer(dev, ring);
2837 }
2838
2839 /**
2840 * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
2841 */
2842 int intel_init_bsd2_ring_buffer(struct drm_device *dev)
2843 {
2844 struct drm_i915_private *dev_priv = dev->dev_private;
2845 struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
2846
2847 ring->name = "bsd2 ring";
2848 ring->id = VCS2;
2849
2850 ring->write_tail = ring_write_tail;
2851 ring->mmio_base = GEN8_BSD2_RING_BASE;
2852 ring->flush = gen6_bsd_ring_flush;
2853 ring->add_request = gen6_add_request;
2854 ring->get_seqno = gen6_ring_get_seqno;
2855 ring->set_seqno = ring_set_seqno;
2856 ring->irq_enable_mask =
2857 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2858 ring->irq_get = gen8_ring_get_irq;
2859 ring->irq_put = gen8_ring_put_irq;
2860 ring->dispatch_execbuffer =
2861 gen8_ring_dispatch_execbuffer;
2862 if (i915_semaphore_is_enabled(dev)) {
2863 ring->semaphore.sync_to = gen8_ring_sync;
2864 ring->semaphore.signal = gen8_xcs_signal;
2865 GEN8_RING_SEMAPHORE_INIT;
2866 }
2867 ring->init_hw = init_ring_common;
2868
2869 return intel_init_ring_buffer(dev, ring);
2870 }
2871
2872 int intel_init_blt_ring_buffer(struct drm_device *dev)
2873 {
2874 struct drm_i915_private *dev_priv = dev->dev_private;
2875 struct intel_engine_cs *ring = &dev_priv->ring[BCS];
2876
2877 ring->name = "blitter ring";
2878 ring->id = BCS;
2879
2880 ring->mmio_base = BLT_RING_BASE;
2881 ring->write_tail = ring_write_tail;
2882 ring->flush = gen6_ring_flush;
2883 ring->add_request = gen6_add_request;
2884 ring->get_seqno = gen6_ring_get_seqno;
2885 ring->set_seqno = ring_set_seqno;
2886 if (INTEL_INFO(dev)->gen >= 8) {
2887 ring->irq_enable_mask =
2888 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2889 ring->irq_get = gen8_ring_get_irq;
2890 ring->irq_put = gen8_ring_put_irq;
2891 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2892 if (i915_semaphore_is_enabled(dev)) {
2893 ring->semaphore.sync_to = gen8_ring_sync;
2894 ring->semaphore.signal = gen8_xcs_signal;
2895 GEN8_RING_SEMAPHORE_INIT;
2896 }
2897 } else {
2898 ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2899 ring->irq_get = gen6_ring_get_irq;
2900 ring->irq_put = gen6_ring_put_irq;
2901 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2902 if (i915_semaphore_is_enabled(dev)) {
2903 ring->semaphore.signal = gen6_signal;
2904 ring->semaphore.sync_to = gen6_ring_sync;
2905 /*
2906 * The current semaphore is only applied on pre-gen8
2907 * platform. And there is no VCS2 ring on the pre-gen8
2908 * platform. So the semaphore between BCS and VCS2 is
2909 * initialized as INVALID. Gen8 will initialize the
2910 * sema between BCS and VCS2 later.
2911 */
2912 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
2913 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
2914 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
2915 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
2916 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2917 ring->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
2918 ring->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
2919 ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
2920 ring->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
2921 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2922 }
2923 }
2924 ring->init_hw = init_ring_common;
2925
2926 return intel_init_ring_buffer(dev, ring);
2927 }
2928
2929 int intel_init_vebox_ring_buffer(struct drm_device *dev)
2930 {
2931 struct drm_i915_private *dev_priv = dev->dev_private;
2932 struct intel_engine_cs *ring = &dev_priv->ring[VECS];
2933
2934 ring->name = "video enhancement ring";
2935 ring->id = VECS;
2936
2937 ring->mmio_base = VEBOX_RING_BASE;
2938 ring->write_tail = ring_write_tail;
2939 ring->flush = gen6_ring_flush;
2940 ring->add_request = gen6_add_request;
2941 ring->get_seqno = gen6_ring_get_seqno;
2942 ring->set_seqno = ring_set_seqno;
2943
2944 if (INTEL_INFO(dev)->gen >= 8) {
2945 ring->irq_enable_mask =
2946 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
2947 ring->irq_get = gen8_ring_get_irq;
2948 ring->irq_put = gen8_ring_put_irq;
2949 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2950 if (i915_semaphore_is_enabled(dev)) {
2951 ring->semaphore.sync_to = gen8_ring_sync;
2952 ring->semaphore.signal = gen8_xcs_signal;
2953 GEN8_RING_SEMAPHORE_INIT;
2954 }
2955 } else {
2956 ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2957 ring->irq_get = hsw_vebox_get_irq;
2958 ring->irq_put = hsw_vebox_put_irq;
2959 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2960 if (i915_semaphore_is_enabled(dev)) {
2961 ring->semaphore.sync_to = gen6_ring_sync;
2962 ring->semaphore.signal = gen6_signal;
2963 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
2964 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
2965 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
2966 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
2967 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2968 ring->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
2969 ring->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
2970 ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
2971 ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
2972 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2973 }
2974 }
2975 ring->init_hw = init_ring_common;
2976
2977 return intel_init_ring_buffer(dev, ring);
2978 }
2979
2980 int
2981 intel_ring_flush_all_caches(struct drm_i915_gem_request *req)
2982 {
2983 struct intel_engine_cs *ring = req->ring;
2984 int ret;
2985
2986 if (!ring->gpu_caches_dirty)
2987 return 0;
2988
2989 ret = ring->flush(req, 0, I915_GEM_GPU_DOMAINS);
2990 if (ret)
2991 return ret;
2992
2993 trace_i915_gem_ring_flush(req, 0, I915_GEM_GPU_DOMAINS);
2994
2995 ring->gpu_caches_dirty = false;
2996 return 0;
2997 }
2998
2999 int
3000 intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req)
3001 {
3002 struct intel_engine_cs *ring = req->ring;
3003 uint32_t flush_domains;
3004 int ret;
3005
3006 flush_domains = 0;
3007 if (ring->gpu_caches_dirty)
3008 flush_domains = I915_GEM_GPU_DOMAINS;
3009
3010 ret = ring->flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
3011 if (ret)
3012 return ret;
3013
3014 trace_i915_gem_ring_flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
3015
3016 ring->gpu_caches_dirty = false;
3017 return 0;
3018 }
3019
3020 void
3021 intel_stop_ring_buffer(struct intel_engine_cs *ring)
3022 {
3023 int ret;
3024
3025 if (!intel_ring_initialized(ring))
3026 return;
3027
3028 ret = intel_ring_idle(ring);
3029 if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
3030 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
3031 ring->name, ret);
3032
3033 stop_ring(ring);
3034 }
Linux kernel - Deliverables
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