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drm/i915: wrap GTIMR changes
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c
1 /*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
30 #include <drm/drmP.h>
31 #include "i915_drv.h"
32 #include <drm/i915_drm.h>
33 #include "i915_trace.h"
34 #include "intel_drv.h"
35
36 /*
37 * 965+ support PIPE_CONTROL commands, which provide finer grained control
38 * over cache flushing.
39 */
40 struct pipe_control {
41 struct drm_i915_gem_object *obj;
42 volatile u32 *cpu_page;
43 u32 gtt_offset;
44 };
45
46 static inline int ring_space(struct intel_ring_buffer *ring)
47 {
48 int space = (ring->head & HEAD_ADDR) - (ring->tail + I915_RING_FREE_SPACE);
49 if (space < 0)
50 space += ring->size;
51 return space;
52 }
53
54 static int
55 gen2_render_ring_flush(struct intel_ring_buffer *ring,
56 u32 invalidate_domains,
57 u32 flush_domains)
58 {
59 u32 cmd;
60 int ret;
61
62 cmd = MI_FLUSH;
63 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
64 cmd |= MI_NO_WRITE_FLUSH;
65
66 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
67 cmd |= MI_READ_FLUSH;
68
69 ret = intel_ring_begin(ring, 2);
70 if (ret)
71 return ret;
72
73 intel_ring_emit(ring, cmd);
74 intel_ring_emit(ring, MI_NOOP);
75 intel_ring_advance(ring);
76
77 return 0;
78 }
79
80 static int
81 gen4_render_ring_flush(struct intel_ring_buffer *ring,
82 u32 invalidate_domains,
83 u32 flush_domains)
84 {
85 struct drm_device *dev = ring->dev;
86 u32 cmd;
87 int ret;
88
89 /*
90 * read/write caches:
91 *
92 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
93 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
94 * also flushed at 2d versus 3d pipeline switches.
95 *
96 * read-only caches:
97 *
98 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
99 * MI_READ_FLUSH is set, and is always flushed on 965.
100 *
101 * I915_GEM_DOMAIN_COMMAND may not exist?
102 *
103 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
104 * invalidated when MI_EXE_FLUSH is set.
105 *
106 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
107 * invalidated with every MI_FLUSH.
108 *
109 * TLBs:
110 *
111 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
112 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
113 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
114 * are flushed at any MI_FLUSH.
115 */
116
117 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
118 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
119 cmd &= ~MI_NO_WRITE_FLUSH;
120 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
121 cmd |= MI_EXE_FLUSH;
122
123 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
124 (IS_G4X(dev) || IS_GEN5(dev)))
125 cmd |= MI_INVALIDATE_ISP;
126
127 ret = intel_ring_begin(ring, 2);
128 if (ret)
129 return ret;
130
131 intel_ring_emit(ring, cmd);
132 intel_ring_emit(ring, MI_NOOP);
133 intel_ring_advance(ring);
134
135 return 0;
136 }
137
138 /**
139 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
140 * implementing two workarounds on gen6. From section 1.4.7.1
141 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
142 *
143 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
144 * produced by non-pipelined state commands), software needs to first
145 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
146 * 0.
147 *
148 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
149 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
150 *
151 * And the workaround for these two requires this workaround first:
152 *
153 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
154 * BEFORE the pipe-control with a post-sync op and no write-cache
155 * flushes.
156 *
157 * And this last workaround is tricky because of the requirements on
158 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
159 * volume 2 part 1:
160 *
161 * "1 of the following must also be set:
162 * - Render Target Cache Flush Enable ([12] of DW1)
163 * - Depth Cache Flush Enable ([0] of DW1)
164 * - Stall at Pixel Scoreboard ([1] of DW1)
165 * - Depth Stall ([13] of DW1)
166 * - Post-Sync Operation ([13] of DW1)
167 * - Notify Enable ([8] of DW1)"
168 *
169 * The cache flushes require the workaround flush that triggered this
170 * one, so we can't use it. Depth stall would trigger the same.
171 * Post-sync nonzero is what triggered this second workaround, so we
172 * can't use that one either. Notify enable is IRQs, which aren't
173 * really our business. That leaves only stall at scoreboard.
174 */
175 static int
176 intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring)
177 {
178 struct pipe_control *pc = ring->private;
179 u32 scratch_addr = pc->gtt_offset + 128;
180 int ret;
181
182
183 ret = intel_ring_begin(ring, 6);
184 if (ret)
185 return ret;
186
187 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
188 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
189 PIPE_CONTROL_STALL_AT_SCOREBOARD);
190 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
191 intel_ring_emit(ring, 0); /* low dword */
192 intel_ring_emit(ring, 0); /* high dword */
193 intel_ring_emit(ring, MI_NOOP);
194 intel_ring_advance(ring);
195
196 ret = intel_ring_begin(ring, 6);
197 if (ret)
198 return ret;
199
200 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
201 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
202 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
203 intel_ring_emit(ring, 0);
204 intel_ring_emit(ring, 0);
205 intel_ring_emit(ring, MI_NOOP);
206 intel_ring_advance(ring);
207
208 return 0;
209 }
210
211 static int
212 gen6_render_ring_flush(struct intel_ring_buffer *ring,
213 u32 invalidate_domains, u32 flush_domains)
214 {
215 u32 flags = 0;
216 struct pipe_control *pc = ring->private;
217 u32 scratch_addr = pc->gtt_offset + 128;
218 int ret;
219
220 /* Force SNB workarounds for PIPE_CONTROL flushes */
221 ret = intel_emit_post_sync_nonzero_flush(ring);
222 if (ret)
223 return ret;
224
225 /* Just flush everything. Experiments have shown that reducing the
226 * number of bits based on the write domains has little performance
227 * impact.
228 */
229 if (flush_domains) {
230 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
231 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
232 /*
233 * Ensure that any following seqno writes only happen
234 * when the render cache is indeed flushed.
235 */
236 flags |= PIPE_CONTROL_CS_STALL;
237 }
238 if (invalidate_domains) {
239 flags |= PIPE_CONTROL_TLB_INVALIDATE;
240 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
241 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
242 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
243 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
244 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
245 /*
246 * TLB invalidate requires a post-sync write.
247 */
248 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
249 }
250
251 ret = intel_ring_begin(ring, 4);
252 if (ret)
253 return ret;
254
255 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
256 intel_ring_emit(ring, flags);
257 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
258 intel_ring_emit(ring, 0);
259 intel_ring_advance(ring);
260
261 return 0;
262 }
263
264 static int
265 gen7_render_ring_cs_stall_wa(struct intel_ring_buffer *ring)
266 {
267 int ret;
268
269 ret = intel_ring_begin(ring, 4);
270 if (ret)
271 return ret;
272
273 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
274 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
275 PIPE_CONTROL_STALL_AT_SCOREBOARD);
276 intel_ring_emit(ring, 0);
277 intel_ring_emit(ring, 0);
278 intel_ring_advance(ring);
279
280 return 0;
281 }
282
283 static int gen7_ring_fbc_flush(struct intel_ring_buffer *ring, u32 value)
284 {
285 int ret;
286
287 if (!ring->fbc_dirty)
288 return 0;
289
290 ret = intel_ring_begin(ring, 4);
291 if (ret)
292 return ret;
293 intel_ring_emit(ring, MI_NOOP);
294 /* WaFbcNukeOn3DBlt:ivb/hsw */
295 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
296 intel_ring_emit(ring, MSG_FBC_REND_STATE);
297 intel_ring_emit(ring, value);
298 intel_ring_advance(ring);
299
300 ring->fbc_dirty = false;
301 return 0;
302 }
303
304 static int
305 gen7_render_ring_flush(struct intel_ring_buffer *ring,
306 u32 invalidate_domains, u32 flush_domains)
307 {
308 u32 flags = 0;
309 struct pipe_control *pc = ring->private;
310 u32 scratch_addr = pc->gtt_offset + 128;
311 int ret;
312
313 /*
314 * Ensure that any following seqno writes only happen when the render
315 * cache is indeed flushed.
316 *
317 * Workaround: 4th PIPE_CONTROL command (except the ones with only
318 * read-cache invalidate bits set) must have the CS_STALL bit set. We
319 * don't try to be clever and just set it unconditionally.
320 */
321 flags |= PIPE_CONTROL_CS_STALL;
322
323 /* Just flush everything. Experiments have shown that reducing the
324 * number of bits based on the write domains has little performance
325 * impact.
326 */
327 if (flush_domains) {
328 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
329 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
330 }
331 if (invalidate_domains) {
332 flags |= PIPE_CONTROL_TLB_INVALIDATE;
333 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
334 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
335 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
336 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
337 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
338 /*
339 * TLB invalidate requires a post-sync write.
340 */
341 flags |= PIPE_CONTROL_QW_WRITE;
342 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
343
344 /* Workaround: we must issue a pipe_control with CS-stall bit
345 * set before a pipe_control command that has the state cache
346 * invalidate bit set. */
347 gen7_render_ring_cs_stall_wa(ring);
348 }
349
350 ret = intel_ring_begin(ring, 4);
351 if (ret)
352 return ret;
353
354 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
355 intel_ring_emit(ring, flags);
356 intel_ring_emit(ring, scratch_addr);
357 intel_ring_emit(ring, 0);
358 intel_ring_advance(ring);
359
360 if (flush_domains)
361 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
362
363 return 0;
364 }
365
366 static void ring_write_tail(struct intel_ring_buffer *ring,
367 u32 value)
368 {
369 drm_i915_private_t *dev_priv = ring->dev->dev_private;
370 I915_WRITE_TAIL(ring, value);
371 }
372
373 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
374 {
375 drm_i915_private_t *dev_priv = ring->dev->dev_private;
376 u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
377 RING_ACTHD(ring->mmio_base) : ACTHD;
378
379 return I915_READ(acthd_reg);
380 }
381
382 static void ring_setup_phys_status_page(struct intel_ring_buffer *ring)
383 {
384 struct drm_i915_private *dev_priv = ring->dev->dev_private;
385 u32 addr;
386
387 addr = dev_priv->status_page_dmah->busaddr;
388 if (INTEL_INFO(ring->dev)->gen >= 4)
389 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
390 I915_WRITE(HWS_PGA, addr);
391 }
392
393 static int init_ring_common(struct intel_ring_buffer *ring)
394 {
395 struct drm_device *dev = ring->dev;
396 drm_i915_private_t *dev_priv = dev->dev_private;
397 struct drm_i915_gem_object *obj = ring->obj;
398 int ret = 0;
399 u32 head;
400
401 if (HAS_FORCE_WAKE(dev))
402 gen6_gt_force_wake_get(dev_priv);
403
404 if (I915_NEED_GFX_HWS(dev))
405 intel_ring_setup_status_page(ring);
406 else
407 ring_setup_phys_status_page(ring);
408
409 /* Stop the ring if it's running. */
410 I915_WRITE_CTL(ring, 0);
411 I915_WRITE_HEAD(ring, 0);
412 ring->write_tail(ring, 0);
413
414 head = I915_READ_HEAD(ring) & HEAD_ADDR;
415
416 /* G45 ring initialization fails to reset head to zero */
417 if (head != 0) {
418 DRM_DEBUG_KMS("%s head not reset to zero "
419 "ctl %08x head %08x tail %08x start %08x\n",
420 ring->name,
421 I915_READ_CTL(ring),
422 I915_READ_HEAD(ring),
423 I915_READ_TAIL(ring),
424 I915_READ_START(ring));
425
426 I915_WRITE_HEAD(ring, 0);
427
428 if (I915_READ_HEAD(ring) & HEAD_ADDR) {
429 DRM_ERROR("failed to set %s head to zero "
430 "ctl %08x head %08x tail %08x start %08x\n",
431 ring->name,
432 I915_READ_CTL(ring),
433 I915_READ_HEAD(ring),
434 I915_READ_TAIL(ring),
435 I915_READ_START(ring));
436 }
437 }
438
439 /* Initialize the ring. This must happen _after_ we've cleared the ring
440 * registers with the above sequence (the readback of the HEAD registers
441 * also enforces ordering), otherwise the hw might lose the new ring
442 * register values. */
443 I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
444 I915_WRITE_CTL(ring,
445 ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
446 | RING_VALID);
447
448 /* If the head is still not zero, the ring is dead */
449 if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
450 I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) &&
451 (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
452 DRM_ERROR("%s initialization failed "
453 "ctl %08x head %08x tail %08x start %08x\n",
454 ring->name,
455 I915_READ_CTL(ring),
456 I915_READ_HEAD(ring),
457 I915_READ_TAIL(ring),
458 I915_READ_START(ring));
459 ret = -EIO;
460 goto out;
461 }
462
463 if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
464 i915_kernel_lost_context(ring->dev);
465 else {
466 ring->head = I915_READ_HEAD(ring);
467 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
468 ring->space = ring_space(ring);
469 ring->last_retired_head = -1;
470 }
471
472 memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
473
474 out:
475 if (HAS_FORCE_WAKE(dev))
476 gen6_gt_force_wake_put(dev_priv);
477
478 return ret;
479 }
480
481 static int
482 init_pipe_control(struct intel_ring_buffer *ring)
483 {
484 struct pipe_control *pc;
485 struct drm_i915_gem_object *obj;
486 int ret;
487
488 if (ring->private)
489 return 0;
490
491 pc = kmalloc(sizeof(*pc), GFP_KERNEL);
492 if (!pc)
493 return -ENOMEM;
494
495 obj = i915_gem_alloc_object(ring->dev, 4096);
496 if (obj == NULL) {
497 DRM_ERROR("Failed to allocate seqno page\n");
498 ret = -ENOMEM;
499 goto err;
500 }
501
502 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
503
504 ret = i915_gem_obj_ggtt_pin(obj, 4096, true, false);
505 if (ret)
506 goto err_unref;
507
508 pc->gtt_offset = i915_gem_obj_ggtt_offset(obj);
509 pc->cpu_page = kmap(sg_page(obj->pages->sgl));
510 if (pc->cpu_page == NULL) {
511 ret = -ENOMEM;
512 goto err_unpin;
513 }
514
515 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
516 ring->name, pc->gtt_offset);
517
518 pc->obj = obj;
519 ring->private = pc;
520 return 0;
521
522 err_unpin:
523 i915_gem_object_unpin(obj);
524 err_unref:
525 drm_gem_object_unreference(&obj->base);
526 err:
527 kfree(pc);
528 return ret;
529 }
530
531 static void
532 cleanup_pipe_control(struct intel_ring_buffer *ring)
533 {
534 struct pipe_control *pc = ring->private;
535 struct drm_i915_gem_object *obj;
536
537 obj = pc->obj;
538
539 kunmap(sg_page(obj->pages->sgl));
540 i915_gem_object_unpin(obj);
541 drm_gem_object_unreference(&obj->base);
542
543 kfree(pc);
544 }
545
546 static int init_render_ring(struct intel_ring_buffer *ring)
547 {
548 struct drm_device *dev = ring->dev;
549 struct drm_i915_private *dev_priv = dev->dev_private;
550 int ret = init_ring_common(ring);
551
552 if (INTEL_INFO(dev)->gen > 3)
553 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
554
555 /* We need to disable the AsyncFlip performance optimisations in order
556 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
557 * programmed to '1' on all products.
558 *
559 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
560 */
561 if (INTEL_INFO(dev)->gen >= 6)
562 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
563
564 /* Required for the hardware to program scanline values for waiting */
565 if (INTEL_INFO(dev)->gen == 6)
566 I915_WRITE(GFX_MODE,
567 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_ALWAYS));
568
569 if (IS_GEN7(dev))
570 I915_WRITE(GFX_MODE_GEN7,
571 _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
572 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
573
574 if (INTEL_INFO(dev)->gen >= 5) {
575 ret = init_pipe_control(ring);
576 if (ret)
577 return ret;
578 }
579
580 if (IS_GEN6(dev)) {
581 /* From the Sandybridge PRM, volume 1 part 3, page 24:
582 * "If this bit is set, STCunit will have LRA as replacement
583 * policy. [...] This bit must be reset. LRA replacement
584 * policy is not supported."
585 */
586 I915_WRITE(CACHE_MODE_0,
587 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
588
589 /* This is not explicitly set for GEN6, so read the register.
590 * see intel_ring_mi_set_context() for why we care.
591 * TODO: consider explicitly setting the bit for GEN5
592 */
593 ring->itlb_before_ctx_switch =
594 !!(I915_READ(GFX_MODE) & GFX_TLB_INVALIDATE_ALWAYS);
595 }
596
597 if (INTEL_INFO(dev)->gen >= 6)
598 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
599
600 if (HAS_L3_GPU_CACHE(dev))
601 I915_WRITE_IMR(ring, ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
602
603 return ret;
604 }
605
606 static void render_ring_cleanup(struct intel_ring_buffer *ring)
607 {
608 struct drm_device *dev = ring->dev;
609
610 if (!ring->private)
611 return;
612
613 if (HAS_BROKEN_CS_TLB(dev))
614 drm_gem_object_unreference(to_gem_object(ring->private));
615
616 if (INTEL_INFO(dev)->gen >= 5)
617 cleanup_pipe_control(ring);
618
619 ring->private = NULL;
620 }
621
622 static void
623 update_mboxes(struct intel_ring_buffer *ring,
624 u32 mmio_offset)
625 {
626 /* NB: In order to be able to do semaphore MBOX updates for varying number
627 * of rings, it's easiest if we round up each individual update to a
628 * multiple of 2 (since ring updates must always be a multiple of 2)
629 * even though the actual update only requires 3 dwords.
630 */
631 #define MBOX_UPDATE_DWORDS 4
632 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
633 intel_ring_emit(ring, mmio_offset);
634 intel_ring_emit(ring, ring->outstanding_lazy_request);
635 intel_ring_emit(ring, MI_NOOP);
636 }
637
638 /**
639 * gen6_add_request - Update the semaphore mailbox registers
640 *
641 * @ring - ring that is adding a request
642 * @seqno - return seqno stuck into the ring
643 *
644 * Update the mailbox registers in the *other* rings with the current seqno.
645 * This acts like a signal in the canonical semaphore.
646 */
647 static int
648 gen6_add_request(struct intel_ring_buffer *ring)
649 {
650 struct drm_device *dev = ring->dev;
651 struct drm_i915_private *dev_priv = dev->dev_private;
652 struct intel_ring_buffer *useless;
653 int i, ret;
654
655 ret = intel_ring_begin(ring, ((I915_NUM_RINGS-1) *
656 MBOX_UPDATE_DWORDS) +
657 4);
658 if (ret)
659 return ret;
660 #undef MBOX_UPDATE_DWORDS
661
662 for_each_ring(useless, dev_priv, i) {
663 u32 mbox_reg = ring->signal_mbox[i];
664 if (mbox_reg != GEN6_NOSYNC)
665 update_mboxes(ring, mbox_reg);
666 }
667
668 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
669 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
670 intel_ring_emit(ring, ring->outstanding_lazy_request);
671 intel_ring_emit(ring, MI_USER_INTERRUPT);
672 intel_ring_advance(ring);
673
674 return 0;
675 }
676
677 static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
678 u32 seqno)
679 {
680 struct drm_i915_private *dev_priv = dev->dev_private;
681 return dev_priv->last_seqno < seqno;
682 }
683
684 /**
685 * intel_ring_sync - sync the waiter to the signaller on seqno
686 *
687 * @waiter - ring that is waiting
688 * @signaller - ring which has, or will signal
689 * @seqno - seqno which the waiter will block on
690 */
691 static int
692 gen6_ring_sync(struct intel_ring_buffer *waiter,
693 struct intel_ring_buffer *signaller,
694 u32 seqno)
695 {
696 int ret;
697 u32 dw1 = MI_SEMAPHORE_MBOX |
698 MI_SEMAPHORE_COMPARE |
699 MI_SEMAPHORE_REGISTER;
700
701 /* Throughout all of the GEM code, seqno passed implies our current
702 * seqno is >= the last seqno executed. However for hardware the
703 * comparison is strictly greater than.
704 */
705 seqno -= 1;
706
707 WARN_ON(signaller->semaphore_register[waiter->id] ==
708 MI_SEMAPHORE_SYNC_INVALID);
709
710 ret = intel_ring_begin(waiter, 4);
711 if (ret)
712 return ret;
713
714 /* If seqno wrap happened, omit the wait with no-ops */
715 if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
716 intel_ring_emit(waiter,
717 dw1 |
718 signaller->semaphore_register[waiter->id]);
719 intel_ring_emit(waiter, seqno);
720 intel_ring_emit(waiter, 0);
721 intel_ring_emit(waiter, MI_NOOP);
722 } else {
723 intel_ring_emit(waiter, MI_NOOP);
724 intel_ring_emit(waiter, MI_NOOP);
725 intel_ring_emit(waiter, MI_NOOP);
726 intel_ring_emit(waiter, MI_NOOP);
727 }
728 intel_ring_advance(waiter);
729
730 return 0;
731 }
732
733 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
734 do { \
735 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
736 PIPE_CONTROL_DEPTH_STALL); \
737 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
738 intel_ring_emit(ring__, 0); \
739 intel_ring_emit(ring__, 0); \
740 } while (0)
741
742 static int
743 pc_render_add_request(struct intel_ring_buffer *ring)
744 {
745 struct pipe_control *pc = ring->private;
746 u32 scratch_addr = pc->gtt_offset + 128;
747 int ret;
748
749 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
750 * incoherent with writes to memory, i.e. completely fubar,
751 * so we need to use PIPE_NOTIFY instead.
752 *
753 * However, we also need to workaround the qword write
754 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
755 * memory before requesting an interrupt.
756 */
757 ret = intel_ring_begin(ring, 32);
758 if (ret)
759 return ret;
760
761 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
762 PIPE_CONTROL_WRITE_FLUSH |
763 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
764 intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
765 intel_ring_emit(ring, ring->outstanding_lazy_request);
766 intel_ring_emit(ring, 0);
767 PIPE_CONTROL_FLUSH(ring, scratch_addr);
768 scratch_addr += 128; /* write to separate cachelines */
769 PIPE_CONTROL_FLUSH(ring, scratch_addr);
770 scratch_addr += 128;
771 PIPE_CONTROL_FLUSH(ring, scratch_addr);
772 scratch_addr += 128;
773 PIPE_CONTROL_FLUSH(ring, scratch_addr);
774 scratch_addr += 128;
775 PIPE_CONTROL_FLUSH(ring, scratch_addr);
776 scratch_addr += 128;
777 PIPE_CONTROL_FLUSH(ring, scratch_addr);
778
779 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
780 PIPE_CONTROL_WRITE_FLUSH |
781 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
782 PIPE_CONTROL_NOTIFY);
783 intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
784 intel_ring_emit(ring, ring->outstanding_lazy_request);
785 intel_ring_emit(ring, 0);
786 intel_ring_advance(ring);
787
788 return 0;
789 }
790
791 static u32
792 gen6_ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
793 {
794 /* Workaround to force correct ordering between irq and seqno writes on
795 * ivb (and maybe also on snb) by reading from a CS register (like
796 * ACTHD) before reading the status page. */
797 if (!lazy_coherency)
798 intel_ring_get_active_head(ring);
799 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
800 }
801
802 static u32
803 ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
804 {
805 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
806 }
807
808 static void
809 ring_set_seqno(struct intel_ring_buffer *ring, u32 seqno)
810 {
811 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
812 }
813
814 static u32
815 pc_render_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
816 {
817 struct pipe_control *pc = ring->private;
818 return pc->cpu_page[0];
819 }
820
821 static void
822 pc_render_set_seqno(struct intel_ring_buffer *ring, u32 seqno)
823 {
824 struct pipe_control *pc = ring->private;
825 pc->cpu_page[0] = seqno;
826 }
827
828 static bool
829 gen5_ring_get_irq(struct intel_ring_buffer *ring)
830 {
831 struct drm_device *dev = ring->dev;
832 drm_i915_private_t *dev_priv = dev->dev_private;
833 unsigned long flags;
834
835 if (!dev->irq_enabled)
836 return false;
837
838 spin_lock_irqsave(&dev_priv->irq_lock, flags);
839 if (ring->irq_refcount++ == 0)
840 ilk_enable_gt_irq(dev_priv, ring->irq_enable_mask);
841 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
842
843 return true;
844 }
845
846 static void
847 gen5_ring_put_irq(struct intel_ring_buffer *ring)
848 {
849 struct drm_device *dev = ring->dev;
850 drm_i915_private_t *dev_priv = dev->dev_private;
851 unsigned long flags;
852
853 spin_lock_irqsave(&dev_priv->irq_lock, flags);
854 if (--ring->irq_refcount == 0)
855 ilk_disable_gt_irq(dev_priv, ring->irq_enable_mask);
856 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
857 }
858
859 static bool
860 i9xx_ring_get_irq(struct intel_ring_buffer *ring)
861 {
862 struct drm_device *dev = ring->dev;
863 drm_i915_private_t *dev_priv = dev->dev_private;
864 unsigned long flags;
865
866 if (!dev->irq_enabled)
867 return false;
868
869 spin_lock_irqsave(&dev_priv->irq_lock, flags);
870 if (ring->irq_refcount++ == 0) {
871 dev_priv->irq_mask &= ~ring->irq_enable_mask;
872 I915_WRITE(IMR, dev_priv->irq_mask);
873 POSTING_READ(IMR);
874 }
875 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
876
877 return true;
878 }
879
880 static void
881 i9xx_ring_put_irq(struct intel_ring_buffer *ring)
882 {
883 struct drm_device *dev = ring->dev;
884 drm_i915_private_t *dev_priv = dev->dev_private;
885 unsigned long flags;
886
887 spin_lock_irqsave(&dev_priv->irq_lock, flags);
888 if (--ring->irq_refcount == 0) {
889 dev_priv->irq_mask |= ring->irq_enable_mask;
890 I915_WRITE(IMR, dev_priv->irq_mask);
891 POSTING_READ(IMR);
892 }
893 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
894 }
895
896 static bool
897 i8xx_ring_get_irq(struct intel_ring_buffer *ring)
898 {
899 struct drm_device *dev = ring->dev;
900 drm_i915_private_t *dev_priv = dev->dev_private;
901 unsigned long flags;
902
903 if (!dev->irq_enabled)
904 return false;
905
906 spin_lock_irqsave(&dev_priv->irq_lock, flags);
907 if (ring->irq_refcount++ == 0) {
908 dev_priv->irq_mask &= ~ring->irq_enable_mask;
909 I915_WRITE16(IMR, dev_priv->irq_mask);
910 POSTING_READ16(IMR);
911 }
912 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
913
914 return true;
915 }
916
917 static void
918 i8xx_ring_put_irq(struct intel_ring_buffer *ring)
919 {
920 struct drm_device *dev = ring->dev;
921 drm_i915_private_t *dev_priv = dev->dev_private;
922 unsigned long flags;
923
924 spin_lock_irqsave(&dev_priv->irq_lock, flags);
925 if (--ring->irq_refcount == 0) {
926 dev_priv->irq_mask |= ring->irq_enable_mask;
927 I915_WRITE16(IMR, dev_priv->irq_mask);
928 POSTING_READ16(IMR);
929 }
930 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
931 }
932
933 void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
934 {
935 struct drm_device *dev = ring->dev;
936 drm_i915_private_t *dev_priv = ring->dev->dev_private;
937 u32 mmio = 0;
938
939 /* The ring status page addresses are no longer next to the rest of
940 * the ring registers as of gen7.
941 */
942 if (IS_GEN7(dev)) {
943 switch (ring->id) {
944 case RCS:
945 mmio = RENDER_HWS_PGA_GEN7;
946 break;
947 case BCS:
948 mmio = BLT_HWS_PGA_GEN7;
949 break;
950 case VCS:
951 mmio = BSD_HWS_PGA_GEN7;
952 break;
953 case VECS:
954 mmio = VEBOX_HWS_PGA_GEN7;
955 break;
956 }
957 } else if (IS_GEN6(ring->dev)) {
958 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
959 } else {
960 mmio = RING_HWS_PGA(ring->mmio_base);
961 }
962
963 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
964 POSTING_READ(mmio);
965 }
966
967 static int
968 bsd_ring_flush(struct intel_ring_buffer *ring,
969 u32 invalidate_domains,
970 u32 flush_domains)
971 {
972 int ret;
973
974 ret = intel_ring_begin(ring, 2);
975 if (ret)
976 return ret;
977
978 intel_ring_emit(ring, MI_FLUSH);
979 intel_ring_emit(ring, MI_NOOP);
980 intel_ring_advance(ring);
981 return 0;
982 }
983
984 static int
985 i9xx_add_request(struct intel_ring_buffer *ring)
986 {
987 int ret;
988
989 ret = intel_ring_begin(ring, 4);
990 if (ret)
991 return ret;
992
993 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
994 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
995 intel_ring_emit(ring, ring->outstanding_lazy_request);
996 intel_ring_emit(ring, MI_USER_INTERRUPT);
997 intel_ring_advance(ring);
998
999 return 0;
1000 }
1001
1002 static bool
1003 gen6_ring_get_irq(struct intel_ring_buffer *ring)
1004 {
1005 struct drm_device *dev = ring->dev;
1006 drm_i915_private_t *dev_priv = dev->dev_private;
1007 unsigned long flags;
1008
1009 if (!dev->irq_enabled)
1010 return false;
1011
1012 /* It looks like we need to prevent the gt from suspending while waiting
1013 * for an notifiy irq, otherwise irqs seem to get lost on at least the
1014 * blt/bsd rings on ivb. */
1015 gen6_gt_force_wake_get(dev_priv);
1016
1017 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1018 if (ring->irq_refcount++ == 0) {
1019 if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
1020 I915_WRITE_IMR(ring,
1021 ~(ring->irq_enable_mask |
1022 GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1023 else
1024 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1025 ilk_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1026 }
1027 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1028
1029 return true;
1030 }
1031
1032 static void
1033 gen6_ring_put_irq(struct intel_ring_buffer *ring)
1034 {
1035 struct drm_device *dev = ring->dev;
1036 drm_i915_private_t *dev_priv = dev->dev_private;
1037 unsigned long flags;
1038
1039 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1040 if (--ring->irq_refcount == 0) {
1041 if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
1042 I915_WRITE_IMR(ring,
1043 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1044 else
1045 I915_WRITE_IMR(ring, ~0);
1046 ilk_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1047 }
1048 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1049
1050 gen6_gt_force_wake_put(dev_priv);
1051 }
1052
1053 static bool
1054 hsw_vebox_get_irq(struct intel_ring_buffer *ring)
1055 {
1056 struct drm_device *dev = ring->dev;
1057 struct drm_i915_private *dev_priv = dev->dev_private;
1058 unsigned long flags;
1059
1060 if (!dev->irq_enabled)
1061 return false;
1062
1063 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1064 if (ring->irq_refcount++ == 0) {
1065 u32 pm_imr = I915_READ(GEN6_PMIMR);
1066 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1067 I915_WRITE(GEN6_PMIMR, pm_imr & ~ring->irq_enable_mask);
1068 POSTING_READ(GEN6_PMIMR);
1069 }
1070 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1071
1072 return true;
1073 }
1074
1075 static void
1076 hsw_vebox_put_irq(struct intel_ring_buffer *ring)
1077 {
1078 struct drm_device *dev = ring->dev;
1079 struct drm_i915_private *dev_priv = dev->dev_private;
1080 unsigned long flags;
1081
1082 if (!dev->irq_enabled)
1083 return;
1084
1085 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1086 if (--ring->irq_refcount == 0) {
1087 u32 pm_imr = I915_READ(GEN6_PMIMR);
1088 I915_WRITE_IMR(ring, ~0);
1089 I915_WRITE(GEN6_PMIMR, pm_imr | ring->irq_enable_mask);
1090 POSTING_READ(GEN6_PMIMR);
1091 }
1092 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1093 }
1094
1095 static int
1096 i965_dispatch_execbuffer(struct intel_ring_buffer *ring,
1097 u32 offset, u32 length,
1098 unsigned flags)
1099 {
1100 int ret;
1101
1102 ret = intel_ring_begin(ring, 2);
1103 if (ret)
1104 return ret;
1105
1106 intel_ring_emit(ring,
1107 MI_BATCH_BUFFER_START |
1108 MI_BATCH_GTT |
1109 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
1110 intel_ring_emit(ring, offset);
1111 intel_ring_advance(ring);
1112
1113 return 0;
1114 }
1115
1116 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1117 #define I830_BATCH_LIMIT (256*1024)
1118 static int
1119 i830_dispatch_execbuffer(struct intel_ring_buffer *ring,
1120 u32 offset, u32 len,
1121 unsigned flags)
1122 {
1123 int ret;
1124
1125 if (flags & I915_DISPATCH_PINNED) {
1126 ret = intel_ring_begin(ring, 4);
1127 if (ret)
1128 return ret;
1129
1130 intel_ring_emit(ring, MI_BATCH_BUFFER);
1131 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1132 intel_ring_emit(ring, offset + len - 8);
1133 intel_ring_emit(ring, MI_NOOP);
1134 intel_ring_advance(ring);
1135 } else {
1136 struct drm_i915_gem_object *obj = ring->private;
1137 u32 cs_offset = i915_gem_obj_ggtt_offset(obj);
1138
1139 if (len > I830_BATCH_LIMIT)
1140 return -ENOSPC;
1141
1142 ret = intel_ring_begin(ring, 9+3);
1143 if (ret)
1144 return ret;
1145 /* Blit the batch (which has now all relocs applied) to the stable batch
1146 * scratch bo area (so that the CS never stumbles over its tlb
1147 * invalidation bug) ... */
1148 intel_ring_emit(ring, XY_SRC_COPY_BLT_CMD |
1149 XY_SRC_COPY_BLT_WRITE_ALPHA |
1150 XY_SRC_COPY_BLT_WRITE_RGB);
1151 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_GXCOPY | 4096);
1152 intel_ring_emit(ring, 0);
1153 intel_ring_emit(ring, (DIV_ROUND_UP(len, 4096) << 16) | 1024);
1154 intel_ring_emit(ring, cs_offset);
1155 intel_ring_emit(ring, 0);
1156 intel_ring_emit(ring, 4096);
1157 intel_ring_emit(ring, offset);
1158 intel_ring_emit(ring, MI_FLUSH);
1159
1160 /* ... and execute it. */
1161 intel_ring_emit(ring, MI_BATCH_BUFFER);
1162 intel_ring_emit(ring, cs_offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1163 intel_ring_emit(ring, cs_offset + len - 8);
1164 intel_ring_advance(ring);
1165 }
1166
1167 return 0;
1168 }
1169
1170 static int
1171 i915_dispatch_execbuffer(struct intel_ring_buffer *ring,
1172 u32 offset, u32 len,
1173 unsigned flags)
1174 {
1175 int ret;
1176
1177 ret = intel_ring_begin(ring, 2);
1178 if (ret)
1179 return ret;
1180
1181 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1182 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1183 intel_ring_advance(ring);
1184
1185 return 0;
1186 }
1187
1188 static void cleanup_status_page(struct intel_ring_buffer *ring)
1189 {
1190 struct drm_i915_gem_object *obj;
1191
1192 obj = ring->status_page.obj;
1193 if (obj == NULL)
1194 return;
1195
1196 kunmap(sg_page(obj->pages->sgl));
1197 i915_gem_object_unpin(obj);
1198 drm_gem_object_unreference(&obj->base);
1199 ring->status_page.obj = NULL;
1200 }
1201
1202 static int init_status_page(struct intel_ring_buffer *ring)
1203 {
1204 struct drm_device *dev = ring->dev;
1205 struct drm_i915_gem_object *obj;
1206 int ret;
1207
1208 obj = i915_gem_alloc_object(dev, 4096);
1209 if (obj == NULL) {
1210 DRM_ERROR("Failed to allocate status page\n");
1211 ret = -ENOMEM;
1212 goto err;
1213 }
1214
1215 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1216
1217 ret = i915_gem_obj_ggtt_pin(obj, 4096, true, false);
1218 if (ret != 0) {
1219 goto err_unref;
1220 }
1221
1222 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
1223 ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
1224 if (ring->status_page.page_addr == NULL) {
1225 ret = -ENOMEM;
1226 goto err_unpin;
1227 }
1228 ring->status_page.obj = obj;
1229 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1230
1231 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1232 ring->name, ring->status_page.gfx_addr);
1233
1234 return 0;
1235
1236 err_unpin:
1237 i915_gem_object_unpin(obj);
1238 err_unref:
1239 drm_gem_object_unreference(&obj->base);
1240 err:
1241 return ret;
1242 }
1243
1244 static int init_phys_status_page(struct intel_ring_buffer *ring)
1245 {
1246 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1247
1248 if (!dev_priv->status_page_dmah) {
1249 dev_priv->status_page_dmah =
1250 drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1251 if (!dev_priv->status_page_dmah)
1252 return -ENOMEM;
1253 }
1254
1255 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1256 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1257
1258 return 0;
1259 }
1260
1261 static int intel_init_ring_buffer(struct drm_device *dev,
1262 struct intel_ring_buffer *ring)
1263 {
1264 struct drm_i915_gem_object *obj;
1265 struct drm_i915_private *dev_priv = dev->dev_private;
1266 int ret;
1267
1268 ring->dev = dev;
1269 INIT_LIST_HEAD(&ring->active_list);
1270 INIT_LIST_HEAD(&ring->request_list);
1271 ring->size = 32 * PAGE_SIZE;
1272 memset(ring->sync_seqno, 0, sizeof(ring->sync_seqno));
1273
1274 init_waitqueue_head(&ring->irq_queue);
1275
1276 if (I915_NEED_GFX_HWS(dev)) {
1277 ret = init_status_page(ring);
1278 if (ret)
1279 return ret;
1280 } else {
1281 BUG_ON(ring->id != RCS);
1282 ret = init_phys_status_page(ring);
1283 if (ret)
1284 return ret;
1285 }
1286
1287 obj = NULL;
1288 if (!HAS_LLC(dev))
1289 obj = i915_gem_object_create_stolen(dev, ring->size);
1290 if (obj == NULL)
1291 obj = i915_gem_alloc_object(dev, ring->size);
1292 if (obj == NULL) {
1293 DRM_ERROR("Failed to allocate ringbuffer\n");
1294 ret = -ENOMEM;
1295 goto err_hws;
1296 }
1297
1298 ring->obj = obj;
1299
1300 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, true, false);
1301 if (ret)
1302 goto err_unref;
1303
1304 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1305 if (ret)
1306 goto err_unpin;
1307
1308 ring->virtual_start =
1309 ioremap_wc(dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj),
1310 ring->size);
1311 if (ring->virtual_start == NULL) {
1312 DRM_ERROR("Failed to map ringbuffer.\n");
1313 ret = -EINVAL;
1314 goto err_unpin;
1315 }
1316
1317 ret = ring->init(ring);
1318 if (ret)
1319 goto err_unmap;
1320
1321 /* Workaround an erratum on the i830 which causes a hang if
1322 * the TAIL pointer points to within the last 2 cachelines
1323 * of the buffer.
1324 */
1325 ring->effective_size = ring->size;
1326 if (IS_I830(ring->dev) || IS_845G(ring->dev))
1327 ring->effective_size -= 128;
1328
1329 return 0;
1330
1331 err_unmap:
1332 iounmap(ring->virtual_start);
1333 err_unpin:
1334 i915_gem_object_unpin(obj);
1335 err_unref:
1336 drm_gem_object_unreference(&obj->base);
1337 ring->obj = NULL;
1338 err_hws:
1339 cleanup_status_page(ring);
1340 return ret;
1341 }
1342
1343 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
1344 {
1345 struct drm_i915_private *dev_priv;
1346 int ret;
1347
1348 if (ring->obj == NULL)
1349 return;
1350
1351 /* Disable the ring buffer. The ring must be idle at this point */
1352 dev_priv = ring->dev->dev_private;
1353 ret = intel_ring_idle(ring);
1354 if (ret)
1355 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1356 ring->name, ret);
1357
1358 I915_WRITE_CTL(ring, 0);
1359
1360 iounmap(ring->virtual_start);
1361
1362 i915_gem_object_unpin(ring->obj);
1363 drm_gem_object_unreference(&ring->obj->base);
1364 ring->obj = NULL;
1365
1366 if (ring->cleanup)
1367 ring->cleanup(ring);
1368
1369 cleanup_status_page(ring);
1370 }
1371
1372 static int intel_ring_wait_seqno(struct intel_ring_buffer *ring, u32 seqno)
1373 {
1374 int ret;
1375
1376 ret = i915_wait_seqno(ring, seqno);
1377 if (!ret)
1378 i915_gem_retire_requests_ring(ring);
1379
1380 return ret;
1381 }
1382
1383 static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n)
1384 {
1385 struct drm_i915_gem_request *request;
1386 u32 seqno = 0;
1387 int ret;
1388
1389 i915_gem_retire_requests_ring(ring);
1390
1391 if (ring->last_retired_head != -1) {
1392 ring->head = ring->last_retired_head;
1393 ring->last_retired_head = -1;
1394 ring->space = ring_space(ring);
1395 if (ring->space >= n)
1396 return 0;
1397 }
1398
1399 list_for_each_entry(request, &ring->request_list, list) {
1400 int space;
1401
1402 if (request->tail == -1)
1403 continue;
1404
1405 space = request->tail - (ring->tail + I915_RING_FREE_SPACE);
1406 if (space < 0)
1407 space += ring->size;
1408 if (space >= n) {
1409 seqno = request->seqno;
1410 break;
1411 }
1412
1413 /* Consume this request in case we need more space than
1414 * is available and so need to prevent a race between
1415 * updating last_retired_head and direct reads of
1416 * I915_RING_HEAD. It also provides a nice sanity check.
1417 */
1418 request->tail = -1;
1419 }
1420
1421 if (seqno == 0)
1422 return -ENOSPC;
1423
1424 ret = intel_ring_wait_seqno(ring, seqno);
1425 if (ret)
1426 return ret;
1427
1428 if (WARN_ON(ring->last_retired_head == -1))
1429 return -ENOSPC;
1430
1431 ring->head = ring->last_retired_head;
1432 ring->last_retired_head = -1;
1433 ring->space = ring_space(ring);
1434 if (WARN_ON(ring->space < n))
1435 return -ENOSPC;
1436
1437 return 0;
1438 }
1439
1440 static int ring_wait_for_space(struct intel_ring_buffer *ring, int n)
1441 {
1442 struct drm_device *dev = ring->dev;
1443 struct drm_i915_private *dev_priv = dev->dev_private;
1444 unsigned long end;
1445 int ret;
1446
1447 ret = intel_ring_wait_request(ring, n);
1448 if (ret != -ENOSPC)
1449 return ret;
1450
1451 trace_i915_ring_wait_begin(ring);
1452 /* With GEM the hangcheck timer should kick us out of the loop,
1453 * leaving it early runs the risk of corrupting GEM state (due
1454 * to running on almost untested codepaths). But on resume
1455 * timers don't work yet, so prevent a complete hang in that
1456 * case by choosing an insanely large timeout. */
1457 end = jiffies + 60 * HZ;
1458
1459 do {
1460 ring->head = I915_READ_HEAD(ring);
1461 ring->space = ring_space(ring);
1462 if (ring->space >= n) {
1463 trace_i915_ring_wait_end(ring);
1464 return 0;
1465 }
1466
1467 if (dev->primary->master) {
1468 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1469 if (master_priv->sarea_priv)
1470 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1471 }
1472
1473 msleep(1);
1474
1475 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1476 dev_priv->mm.interruptible);
1477 if (ret)
1478 return ret;
1479 } while (!time_after(jiffies, end));
1480 trace_i915_ring_wait_end(ring);
1481 return -EBUSY;
1482 }
1483
1484 static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
1485 {
1486 uint32_t __iomem *virt;
1487 int rem = ring->size - ring->tail;
1488
1489 if (ring->space < rem) {
1490 int ret = ring_wait_for_space(ring, rem);
1491 if (ret)
1492 return ret;
1493 }
1494
1495 virt = ring->virtual_start + ring->tail;
1496 rem /= 4;
1497 while (rem--)
1498 iowrite32(MI_NOOP, virt++);
1499
1500 ring->tail = 0;
1501 ring->space = ring_space(ring);
1502
1503 return 0;
1504 }
1505
1506 int intel_ring_idle(struct intel_ring_buffer *ring)
1507 {
1508 u32 seqno;
1509 int ret;
1510
1511 /* We need to add any requests required to flush the objects and ring */
1512 if (ring->outstanding_lazy_request) {
1513 ret = i915_add_request(ring, NULL);
1514 if (ret)
1515 return ret;
1516 }
1517
1518 /* Wait upon the last request to be completed */
1519 if (list_empty(&ring->request_list))
1520 return 0;
1521
1522 seqno = list_entry(ring->request_list.prev,
1523 struct drm_i915_gem_request,
1524 list)->seqno;
1525
1526 return i915_wait_seqno(ring, seqno);
1527 }
1528
1529 static int
1530 intel_ring_alloc_seqno(struct intel_ring_buffer *ring)
1531 {
1532 if (ring->outstanding_lazy_request)
1533 return 0;
1534
1535 return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_request);
1536 }
1537
1538 static int __intel_ring_begin(struct intel_ring_buffer *ring,
1539 int bytes)
1540 {
1541 int ret;
1542
1543 if (unlikely(ring->tail + bytes > ring->effective_size)) {
1544 ret = intel_wrap_ring_buffer(ring);
1545 if (unlikely(ret))
1546 return ret;
1547 }
1548
1549 if (unlikely(ring->space < bytes)) {
1550 ret = ring_wait_for_space(ring, bytes);
1551 if (unlikely(ret))
1552 return ret;
1553 }
1554
1555 ring->space -= bytes;
1556 return 0;
1557 }
1558
1559 int intel_ring_begin(struct intel_ring_buffer *ring,
1560 int num_dwords)
1561 {
1562 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1563 int ret;
1564
1565 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1566 dev_priv->mm.interruptible);
1567 if (ret)
1568 return ret;
1569
1570 /* Preallocate the olr before touching the ring */
1571 ret = intel_ring_alloc_seqno(ring);
1572 if (ret)
1573 return ret;
1574
1575 return __intel_ring_begin(ring, num_dwords * sizeof(uint32_t));
1576 }
1577
1578 void intel_ring_init_seqno(struct intel_ring_buffer *ring, u32 seqno)
1579 {
1580 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1581
1582 BUG_ON(ring->outstanding_lazy_request);
1583
1584 if (INTEL_INFO(ring->dev)->gen >= 6) {
1585 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
1586 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
1587 if (HAS_VEBOX(ring->dev))
1588 I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
1589 }
1590
1591 ring->set_seqno(ring, seqno);
1592 ring->hangcheck.seqno = seqno;
1593 }
1594
1595 void intel_ring_advance(struct intel_ring_buffer *ring)
1596 {
1597 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1598
1599 ring->tail &= ring->size - 1;
1600 if (dev_priv->gpu_error.stop_rings & intel_ring_flag(ring))
1601 return;
1602 ring->write_tail(ring, ring->tail);
1603 }
1604
1605
1606 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
1607 u32 value)
1608 {
1609 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1610
1611 /* Every tail move must follow the sequence below */
1612
1613 /* Disable notification that the ring is IDLE. The GT
1614 * will then assume that it is busy and bring it out of rc6.
1615 */
1616 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1617 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1618
1619 /* Clear the context id. Here be magic! */
1620 I915_WRITE64(GEN6_BSD_RNCID, 0x0);
1621
1622 /* Wait for the ring not to be idle, i.e. for it to wake up. */
1623 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
1624 GEN6_BSD_SLEEP_INDICATOR) == 0,
1625 50))
1626 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
1627
1628 /* Now that the ring is fully powered up, update the tail */
1629 I915_WRITE_TAIL(ring, value);
1630 POSTING_READ(RING_TAIL(ring->mmio_base));
1631
1632 /* Let the ring send IDLE messages to the GT again,
1633 * and so let it sleep to conserve power when idle.
1634 */
1635 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1636 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1637 }
1638
1639 static int gen6_bsd_ring_flush(struct intel_ring_buffer *ring,
1640 u32 invalidate, u32 flush)
1641 {
1642 uint32_t cmd;
1643 int ret;
1644
1645 ret = intel_ring_begin(ring, 4);
1646 if (ret)
1647 return ret;
1648
1649 cmd = MI_FLUSH_DW;
1650 /*
1651 * Bspec vol 1c.5 - video engine command streamer:
1652 * "If ENABLED, all TLBs will be invalidated once the flush
1653 * operation is complete. This bit is only valid when the
1654 * Post-Sync Operation field is a value of 1h or 3h."
1655 */
1656 if (invalidate & I915_GEM_GPU_DOMAINS)
1657 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD |
1658 MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1659 intel_ring_emit(ring, cmd);
1660 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
1661 intel_ring_emit(ring, 0);
1662 intel_ring_emit(ring, MI_NOOP);
1663 intel_ring_advance(ring);
1664 return 0;
1665 }
1666
1667 static int
1668 hsw_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1669 u32 offset, u32 len,
1670 unsigned flags)
1671 {
1672 int ret;
1673
1674 ret = intel_ring_begin(ring, 2);
1675 if (ret)
1676 return ret;
1677
1678 intel_ring_emit(ring,
1679 MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW |
1680 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_HSW));
1681 /* bit0-7 is the length on GEN6+ */
1682 intel_ring_emit(ring, offset);
1683 intel_ring_advance(ring);
1684
1685 return 0;
1686 }
1687
1688 static int
1689 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1690 u32 offset, u32 len,
1691 unsigned flags)
1692 {
1693 int ret;
1694
1695 ret = intel_ring_begin(ring, 2);
1696 if (ret)
1697 return ret;
1698
1699 intel_ring_emit(ring,
1700 MI_BATCH_BUFFER_START |
1701 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
1702 /* bit0-7 is the length on GEN6+ */
1703 intel_ring_emit(ring, offset);
1704 intel_ring_advance(ring);
1705
1706 return 0;
1707 }
1708
1709 /* Blitter support (SandyBridge+) */
1710
1711 static int gen6_ring_flush(struct intel_ring_buffer *ring,
1712 u32 invalidate, u32 flush)
1713 {
1714 struct drm_device *dev = ring->dev;
1715 uint32_t cmd;
1716 int ret;
1717
1718 ret = intel_ring_begin(ring, 4);
1719 if (ret)
1720 return ret;
1721
1722 cmd = MI_FLUSH_DW;
1723 /*
1724 * Bspec vol 1c.3 - blitter engine command streamer:
1725 * "If ENABLED, all TLBs will be invalidated once the flush
1726 * operation is complete. This bit is only valid when the
1727 * Post-Sync Operation field is a value of 1h or 3h."
1728 */
1729 if (invalidate & I915_GEM_DOMAIN_RENDER)
1730 cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX |
1731 MI_FLUSH_DW_OP_STOREDW;
1732 intel_ring_emit(ring, cmd);
1733 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
1734 intel_ring_emit(ring, 0);
1735 intel_ring_emit(ring, MI_NOOP);
1736 intel_ring_advance(ring);
1737
1738 if (IS_GEN7(dev) && flush)
1739 return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN);
1740
1741 return 0;
1742 }
1743
1744 int intel_init_render_ring_buffer(struct drm_device *dev)
1745 {
1746 drm_i915_private_t *dev_priv = dev->dev_private;
1747 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1748
1749 ring->name = "render ring";
1750 ring->id = RCS;
1751 ring->mmio_base = RENDER_RING_BASE;
1752
1753 if (INTEL_INFO(dev)->gen >= 6) {
1754 ring->add_request = gen6_add_request;
1755 ring->flush = gen7_render_ring_flush;
1756 if (INTEL_INFO(dev)->gen == 6)
1757 ring->flush = gen6_render_ring_flush;
1758 ring->irq_get = gen6_ring_get_irq;
1759 ring->irq_put = gen6_ring_put_irq;
1760 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
1761 ring->get_seqno = gen6_ring_get_seqno;
1762 ring->set_seqno = ring_set_seqno;
1763 ring->sync_to = gen6_ring_sync;
1764 ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_INVALID;
1765 ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_RV;
1766 ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_RB;
1767 ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_RVE;
1768 ring->signal_mbox[RCS] = GEN6_NOSYNC;
1769 ring->signal_mbox[VCS] = GEN6_VRSYNC;
1770 ring->signal_mbox[BCS] = GEN6_BRSYNC;
1771 ring->signal_mbox[VECS] = GEN6_VERSYNC;
1772 } else if (IS_GEN5(dev)) {
1773 ring->add_request = pc_render_add_request;
1774 ring->flush = gen4_render_ring_flush;
1775 ring->get_seqno = pc_render_get_seqno;
1776 ring->set_seqno = pc_render_set_seqno;
1777 ring->irq_get = gen5_ring_get_irq;
1778 ring->irq_put = gen5_ring_put_irq;
1779 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
1780 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
1781 } else {
1782 ring->add_request = i9xx_add_request;
1783 if (INTEL_INFO(dev)->gen < 4)
1784 ring->flush = gen2_render_ring_flush;
1785 else
1786 ring->flush = gen4_render_ring_flush;
1787 ring->get_seqno = ring_get_seqno;
1788 ring->set_seqno = ring_set_seqno;
1789 if (IS_GEN2(dev)) {
1790 ring->irq_get = i8xx_ring_get_irq;
1791 ring->irq_put = i8xx_ring_put_irq;
1792 } else {
1793 ring->irq_get = i9xx_ring_get_irq;
1794 ring->irq_put = i9xx_ring_put_irq;
1795 }
1796 ring->irq_enable_mask = I915_USER_INTERRUPT;
1797 }
1798 ring->write_tail = ring_write_tail;
1799 if (IS_HASWELL(dev))
1800 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
1801 else if (INTEL_INFO(dev)->gen >= 6)
1802 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1803 else if (INTEL_INFO(dev)->gen >= 4)
1804 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1805 else if (IS_I830(dev) || IS_845G(dev))
1806 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1807 else
1808 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1809 ring->init = init_render_ring;
1810 ring->cleanup = render_ring_cleanup;
1811
1812 /* Workaround batchbuffer to combat CS tlb bug. */
1813 if (HAS_BROKEN_CS_TLB(dev)) {
1814 struct drm_i915_gem_object *obj;
1815 int ret;
1816
1817 obj = i915_gem_alloc_object(dev, I830_BATCH_LIMIT);
1818 if (obj == NULL) {
1819 DRM_ERROR("Failed to allocate batch bo\n");
1820 return -ENOMEM;
1821 }
1822
1823 ret = i915_gem_obj_ggtt_pin(obj, 0, true, false);
1824 if (ret != 0) {
1825 drm_gem_object_unreference(&obj->base);
1826 DRM_ERROR("Failed to ping batch bo\n");
1827 return ret;
1828 }
1829
1830 ring->private = obj;
1831 }
1832
1833 return intel_init_ring_buffer(dev, ring);
1834 }
1835
1836 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
1837 {
1838 drm_i915_private_t *dev_priv = dev->dev_private;
1839 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1840 int ret;
1841
1842 ring->name = "render ring";
1843 ring->id = RCS;
1844 ring->mmio_base = RENDER_RING_BASE;
1845
1846 if (INTEL_INFO(dev)->gen >= 6) {
1847 /* non-kms not supported on gen6+ */
1848 return -ENODEV;
1849 }
1850
1851 /* Note: gem is not supported on gen5/ilk without kms (the corresponding
1852 * gem_init ioctl returns with -ENODEV). Hence we do not need to set up
1853 * the special gen5 functions. */
1854 ring->add_request = i9xx_add_request;
1855 if (INTEL_INFO(dev)->gen < 4)
1856 ring->flush = gen2_render_ring_flush;
1857 else
1858 ring->flush = gen4_render_ring_flush;
1859 ring->get_seqno = ring_get_seqno;
1860 ring->set_seqno = ring_set_seqno;
1861 if (IS_GEN2(dev)) {
1862 ring->irq_get = i8xx_ring_get_irq;
1863 ring->irq_put = i8xx_ring_put_irq;
1864 } else {
1865 ring->irq_get = i9xx_ring_get_irq;
1866 ring->irq_put = i9xx_ring_put_irq;
1867 }
1868 ring->irq_enable_mask = I915_USER_INTERRUPT;
1869 ring->write_tail = ring_write_tail;
1870 if (INTEL_INFO(dev)->gen >= 4)
1871 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1872 else if (IS_I830(dev) || IS_845G(dev))
1873 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1874 else
1875 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1876 ring->init = init_render_ring;
1877 ring->cleanup = render_ring_cleanup;
1878
1879 ring->dev = dev;
1880 INIT_LIST_HEAD(&ring->active_list);
1881 INIT_LIST_HEAD(&ring->request_list);
1882
1883 ring->size = size;
1884 ring->effective_size = ring->size;
1885 if (IS_I830(ring->dev) || IS_845G(ring->dev))
1886 ring->effective_size -= 128;
1887
1888 ring->virtual_start = ioremap_wc(start, size);
1889 if (ring->virtual_start == NULL) {
1890 DRM_ERROR("can not ioremap virtual address for"
1891 " ring buffer\n");
1892 return -ENOMEM;
1893 }
1894
1895 if (!I915_NEED_GFX_HWS(dev)) {
1896 ret = init_phys_status_page(ring);
1897 if (ret)
1898 return ret;
1899 }
1900
1901 return 0;
1902 }
1903
1904 int intel_init_bsd_ring_buffer(struct drm_device *dev)
1905 {
1906 drm_i915_private_t *dev_priv = dev->dev_private;
1907 struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
1908
1909 ring->name = "bsd ring";
1910 ring->id = VCS;
1911
1912 ring->write_tail = ring_write_tail;
1913 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1914 ring->mmio_base = GEN6_BSD_RING_BASE;
1915 /* gen6 bsd needs a special wa for tail updates */
1916 if (IS_GEN6(dev))
1917 ring->write_tail = gen6_bsd_ring_write_tail;
1918 ring->flush = gen6_bsd_ring_flush;
1919 ring->add_request = gen6_add_request;
1920 ring->get_seqno = gen6_ring_get_seqno;
1921 ring->set_seqno = ring_set_seqno;
1922 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
1923 ring->irq_get = gen6_ring_get_irq;
1924 ring->irq_put = gen6_ring_put_irq;
1925 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1926 ring->sync_to = gen6_ring_sync;
1927 ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VR;
1928 ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_INVALID;
1929 ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VB;
1930 ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_VVE;
1931 ring->signal_mbox[RCS] = GEN6_RVSYNC;
1932 ring->signal_mbox[VCS] = GEN6_NOSYNC;
1933 ring->signal_mbox[BCS] = GEN6_BVSYNC;
1934 ring->signal_mbox[VECS] = GEN6_VEVSYNC;
1935 } else {
1936 ring->mmio_base = BSD_RING_BASE;
1937 ring->flush = bsd_ring_flush;
1938 ring->add_request = i9xx_add_request;
1939 ring->get_seqno = ring_get_seqno;
1940 ring->set_seqno = ring_set_seqno;
1941 if (IS_GEN5(dev)) {
1942 ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
1943 ring->irq_get = gen5_ring_get_irq;
1944 ring->irq_put = gen5_ring_put_irq;
1945 } else {
1946 ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
1947 ring->irq_get = i9xx_ring_get_irq;
1948 ring->irq_put = i9xx_ring_put_irq;
1949 }
1950 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1951 }
1952 ring->init = init_ring_common;
1953
1954 return intel_init_ring_buffer(dev, ring);
1955 }
1956
1957 int intel_init_blt_ring_buffer(struct drm_device *dev)
1958 {
1959 drm_i915_private_t *dev_priv = dev->dev_private;
1960 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
1961
1962 ring->name = "blitter ring";
1963 ring->id = BCS;
1964
1965 ring->mmio_base = BLT_RING_BASE;
1966 ring->write_tail = ring_write_tail;
1967 ring->flush = gen6_ring_flush;
1968 ring->add_request = gen6_add_request;
1969 ring->get_seqno = gen6_ring_get_seqno;
1970 ring->set_seqno = ring_set_seqno;
1971 ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
1972 ring->irq_get = gen6_ring_get_irq;
1973 ring->irq_put = gen6_ring_put_irq;
1974 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1975 ring->sync_to = gen6_ring_sync;
1976 ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_BR;
1977 ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_BV;
1978 ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_INVALID;
1979 ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_BVE;
1980 ring->signal_mbox[RCS] = GEN6_RBSYNC;
1981 ring->signal_mbox[VCS] = GEN6_VBSYNC;
1982 ring->signal_mbox[BCS] = GEN6_NOSYNC;
1983 ring->signal_mbox[VECS] = GEN6_VEBSYNC;
1984 ring->init = init_ring_common;
1985
1986 return intel_init_ring_buffer(dev, ring);
1987 }
1988
1989 int intel_init_vebox_ring_buffer(struct drm_device *dev)
1990 {
1991 drm_i915_private_t *dev_priv = dev->dev_private;
1992 struct intel_ring_buffer *ring = &dev_priv->ring[VECS];
1993
1994 ring->name = "video enhancement ring";
1995 ring->id = VECS;
1996
1997 ring->mmio_base = VEBOX_RING_BASE;
1998 ring->write_tail = ring_write_tail;
1999 ring->flush = gen6_ring_flush;
2000 ring->add_request = gen6_add_request;
2001 ring->get_seqno = gen6_ring_get_seqno;
2002 ring->set_seqno = ring_set_seqno;
2003 ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2004 ring->irq_get = hsw_vebox_get_irq;
2005 ring->irq_put = hsw_vebox_put_irq;
2006 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2007 ring->sync_to = gen6_ring_sync;
2008 ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VER;
2009 ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_VEV;
2010 ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VEB;
2011 ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_INVALID;
2012 ring->signal_mbox[RCS] = GEN6_RVESYNC;
2013 ring->signal_mbox[VCS] = GEN6_VVESYNC;
2014 ring->signal_mbox[BCS] = GEN6_BVESYNC;
2015 ring->signal_mbox[VECS] = GEN6_NOSYNC;
2016 ring->init = init_ring_common;
2017
2018 return intel_init_ring_buffer(dev, ring);
2019 }
2020
2021 int
2022 intel_ring_flush_all_caches(struct intel_ring_buffer *ring)
2023 {
2024 int ret;
2025
2026 if (!ring->gpu_caches_dirty)
2027 return 0;
2028
2029 ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
2030 if (ret)
2031 return ret;
2032
2033 trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
2034
2035 ring->gpu_caches_dirty = false;
2036 return 0;
2037 }
2038
2039 int
2040 intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring)
2041 {
2042 uint32_t flush_domains;
2043 int ret;
2044
2045 flush_domains = 0;
2046 if (ring->gpu_caches_dirty)
2047 flush_domains = I915_GEM_GPU_DOMAINS;
2048
2049 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2050 if (ret)
2051 return ret;
2052
2053 trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2054
2055 ring->gpu_caches_dirty = false;
2056 return 0;
2057 }
Linux kernel - Deliverables
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